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igb: Fix sparse warnings on function pointers
[linux-2.6-block.git] / drivers / net / ethernet / intel / igb / igb_ethtool.c
CommitLineData
9d5c8243
AK		 1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4b9ea462 4 Copyright(c) 2007-2013 Intel Corporation.
9d5c8243
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for igb */
29
30#include <linux/vmalloc.h>
31#include <linux/netdevice.h>
32#include <linux/pci.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/if_ether.h>
36#include <linux/ethtool.h>
d43c36dc 37#include <linux/sched.h>
5a0e3ad6 38#include <linux/slab.h>
749ab2cd 39#include <linux/pm_runtime.h>
1a1c225b 40#include <linux/highmem.h>
9d5c8243
AK		 41
42#include "igb.h"
43
44struct igb_stats {
45 char stat_string[ETH_GSTRING_LEN];
46 int sizeof_stat;
47 int stat_offset;
48};
49
128e45eb
AD		 50#define IGB_STAT(_name, _stat) { \
51 .stat_string = _name, \
52 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
53 .stat_offset = offsetof(struct igb_adapter, _stat) \
54}
9d5c8243 55static const struct igb_stats igb_gstrings_stats[] = {
128e45eb
AD		 56 IGB_STAT("rx_packets", stats.gprc),
57 IGB_STAT("tx_packets", stats.gptc),
58 IGB_STAT("rx_bytes", stats.gorc),
59 IGB_STAT("tx_bytes", stats.gotc),
60 IGB_STAT("rx_broadcast", stats.bprc),
61 IGB_STAT("tx_broadcast", stats.bptc),
62 IGB_STAT("rx_multicast", stats.mprc),
63 IGB_STAT("tx_multicast", stats.mptc),
64 IGB_STAT("multicast", stats.mprc),
65 IGB_STAT("collisions", stats.colc),
66 IGB_STAT("rx_crc_errors", stats.crcerrs),
67 IGB_STAT("rx_no_buffer_count", stats.rnbc),
68 IGB_STAT("rx_missed_errors", stats.mpc),
69 IGB_STAT("tx_aborted_errors", stats.ecol),
70 IGB_STAT("tx_carrier_errors", stats.tncrs),
71 IGB_STAT("tx_window_errors", stats.latecol),
72 IGB_STAT("tx_abort_late_coll", stats.latecol),
73 IGB_STAT("tx_deferred_ok", stats.dc),
74 IGB_STAT("tx_single_coll_ok", stats.scc),
75 IGB_STAT("tx_multi_coll_ok", stats.mcc),
76 IGB_STAT("tx_timeout_count", tx_timeout_count),
77 IGB_STAT("rx_long_length_errors", stats.roc),
78 IGB_STAT("rx_short_length_errors", stats.ruc),
79 IGB_STAT("rx_align_errors", stats.algnerrc),
80 IGB_STAT("tx_tcp_seg_good", stats.tsctc),
81 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
82 IGB_STAT("rx_flow_control_xon", stats.xonrxc),
83 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
84 IGB_STAT("tx_flow_control_xon", stats.xontxc),
85 IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
86 IGB_STAT("rx_long_byte_count", stats.gorc),
87 IGB_STAT("tx_dma_out_of_sync", stats.doosync),
88 IGB_STAT("tx_smbus", stats.mgptc),
89 IGB_STAT("rx_smbus", stats.mgprc),
90 IGB_STAT("dropped_smbus", stats.mgpdc),
0a915b95
CW		 91 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
92 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
93 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
94 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
428f1f71 95 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts),
fc580751 96 IGB_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
128e45eb
AD		 97};
98
99#define IGB_NETDEV_STAT(_net_stat) { \
100 .stat_string = __stringify(_net_stat), \
12dcd86b
ED		 101 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
102 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
128e45eb
AD		 103}
104static const struct igb_stats igb_gstrings_net_stats[] = {
105 IGB_NETDEV_STAT(rx_errors),
106 IGB_NETDEV_STAT(tx_errors),
107 IGB_NETDEV_STAT(tx_dropped),
108 IGB_NETDEV_STAT(rx_length_errors),
109 IGB_NETDEV_STAT(rx_over_errors),
110 IGB_NETDEV_STAT(rx_frame_errors),
111 IGB_NETDEV_STAT(rx_fifo_errors),
112 IGB_NETDEV_STAT(tx_fifo_errors),
113 IGB_NETDEV_STAT(tx_heartbeat_errors)
9d5c8243
AK		 114};
115
128e45eb
AD		 116#define IGB_GLOBAL_STATS_LEN \
117 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
118#define IGB_NETDEV_STATS_LEN \
119 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
120#define IGB_RX_QUEUE_STATS_LEN \
121 (sizeof(struct igb_rx_queue_stats) / sizeof(u64))
12dcd86b
ED		 122
123#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
124
9d5c8243 125#define IGB_QUEUE_STATS_LEN \
317f66bd 126 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
128e45eb 127 IGB_RX_QUEUE_STATS_LEN) + \
317f66bd 128 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
128e45eb
AD		 129 IGB_TX_QUEUE_STATS_LEN))
130#define IGB_STATS_LEN \
131 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
132
9d5c8243
AK		 133static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
134 "Register test (offline)", "Eeprom test (offline)",
135 "Interrupt test (offline)", "Loopback test (offline)",
136 "Link test (on/offline)"
137};
317f66bd 138#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
9d5c8243
AK		 139
140static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
141{
142 struct igb_adapter *adapter = netdev_priv(netdev);
143 struct e1000_hw *hw = &adapter->hw;
317f66bd 144 u32 status;
9d5c8243
AK		 145
146 if (hw->phy.media_type == e1000_media_type_copper) {
147
148 ecmd->supported = (SUPPORTED_10baseT_Half |
149 SUPPORTED_10baseT_Full |
150 SUPPORTED_100baseT_Half |
151 SUPPORTED_100baseT_Full |
152 SUPPORTED_1000baseT_Full|
153 SUPPORTED_Autoneg |
42f3c43b
AA		 154 SUPPORTED_TP |
155 SUPPORTED_Pause);
156 ecmd->advertising = ADVERTISED_TP;
9d5c8243
AK		 157
158 if (hw->mac.autoneg == 1) {
159 ecmd->advertising |= ADVERTISED_Autoneg;
160 /* the e1000 autoneg seems to match ethtool nicely */
161 ecmd->advertising |= hw->phy.autoneg_advertised;
162 }
163
42f3c43b
AA		 164 if (hw->mac.autoneg != 1)
165 ecmd->advertising &= ~(ADVERTISED_Pause |
166 ADVERTISED_Asym_Pause);
167
168 if (hw->fc.requested_mode == e1000_fc_full)
169 ecmd->advertising |= ADVERTISED_Pause;
170 else if (hw->fc.requested_mode == e1000_fc_rx_pause)
171 ecmd->advertising |= (ADVERTISED_Pause |
172 ADVERTISED_Asym_Pause);
173 else if (hw->fc.requested_mode == e1000_fc_tx_pause)
174 ecmd->advertising |= ADVERTISED_Asym_Pause;
175 else
176 ecmd->advertising &= ~(ADVERTISED_Pause |
177 ADVERTISED_Asym_Pause);
178
9d5c8243
AK		 179 ecmd->port = PORT_TP;
180 ecmd->phy_address = hw->phy.addr;
f502ef7d 181 ecmd->transceiver = XCVR_INTERNAL;
9d5c8243
AK		 182 } else {
183 ecmd->supported = (SUPPORTED_1000baseT_Full |
f502ef7d
AA		 184 SUPPORTED_100baseT_Full |
185 SUPPORTED_Autoneg |
9d5c8243 186 SUPPORTED_FIBRE |
f502ef7d 187 SUPPORTED_Pause);
9d5c8243 188
f502ef7d
AA		 189 ecmd->advertising = ADVERTISED_FIBRE;
190
191 if (adapter->link_speed == SPEED_100)
192 ecmd->advertising = ADVERTISED_100baseT_Full;
193 else if (adapter->link_speed == SPEED_1000)
194 ecmd->advertising = ADVERTISED_1000baseT_Full;
195
196 if (hw->mac.autoneg == 1)
197 ecmd->advertising |= ADVERTISED_Autoneg;
9d5c8243
AK		 198
199 ecmd->port = PORT_FIBRE;
f502ef7d 200 ecmd->transceiver = XCVR_EXTERNAL;
9d5c8243
AK		 201 }
202
317f66bd 203 status = rd32(E1000_STATUS);
9d5c8243 204
317f66bd 205 if (status & E1000_STATUS_LU) {
9d5c8243 206
f502ef7d 207 if (status & E1000_STATUS_SPEED_1000)
70739497 208 ethtool_cmd_speed_set(ecmd, SPEED_1000);
317f66bd 209 else if (status & E1000_STATUS_SPEED_100)
70739497 210 ethtool_cmd_speed_set(ecmd, SPEED_100);
317f66bd 211 else
70739497 212 ethtool_cmd_speed_set(ecmd, SPEED_10);
9d5c8243 213
317f66bd
AD		 214 if ((status & E1000_STATUS_FD) ||
215 hw->phy.media_type != e1000_media_type_copper)
9d5c8243
AK		 216 ecmd->duplex = DUPLEX_FULL;
217 else
218 ecmd->duplex = DUPLEX_HALF;
219 } else {
70739497 220 ethtool_cmd_speed_set(ecmd, -1);
9d5c8243
AK		 221 ecmd->duplex = -1;
222 }
223
f502ef7d
AA		 224 if ((hw->phy.media_type == e1000_media_type_fiber) ||
225 hw->mac.autoneg)
226 ecmd->autoneg = AUTONEG_ENABLE;
227 else
228 ecmd->autoneg = AUTONEG_DISABLE;
8376dad0
JB		 229
230 /* MDI-X => 2; MDI =>1; Invalid =>0 */
231 if (hw->phy.media_type == e1000_media_type_copper)
232 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
233 ETH_TP_MDI;
234 else
235 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
236
237 if (hw->phy.mdix == AUTO_ALL_MODES)
238 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
239 else
240 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
241
9d5c8243
AK		 242 return 0;
243}
244
245static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
246{
247 struct igb_adapter *adapter = netdev_priv(netdev);
248 struct e1000_hw *hw = &adapter->hw;
249
250 /* When SoL/IDER sessions are active, autoneg/speed/duplex
251 * cannot be changed */
252 if (igb_check_reset_block(hw)) {
d836200a
JJ		 253 dev_err(&adapter->pdev->dev,
254 "Cannot change link characteristics when SoL/IDER is active.\n");
9d5c8243
AK		 255 return -EINVAL;
256 }
257
8376dad0
JB		 258 /*
259 * MDI setting is only allowed when autoneg enabled because
260 * some hardware doesn't allow MDI setting when speed or
261 * duplex is forced.
262 */
263 if (ecmd->eth_tp_mdix_ctrl) {
264 if (hw->phy.media_type != e1000_media_type_copper)
265 return -EOPNOTSUPP;
266
267 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
268 (ecmd->autoneg != AUTONEG_ENABLE)) {
269 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
270 return -EINVAL;
271 }
272 }
273
9d5c8243
AK		 274 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
275 msleep(1);
276
277 if (ecmd->autoneg == AUTONEG_ENABLE) {
278 hw->mac.autoneg = 1;
f502ef7d
AA		 279 if (hw->phy.media_type == e1000_media_type_fiber) {
280 hw->phy.autoneg_advertised = ecmd->advertising |
281 ADVERTISED_FIBRE |
282 ADVERTISED_Autoneg;
283 if (adapter->link_speed == SPEED_1000)
284 hw->phy.autoneg_advertised =
285 ADVERTISED_1000baseT_Full;
286 else if (adapter->link_speed == SPEED_100)
287 hw->phy.autoneg_advertised =
288 ADVERTISED_100baseT_Full;
289 } else {
290 hw->phy.autoneg_advertised = ecmd->advertising |
291 ADVERTISED_TP |
292 ADVERTISED_Autoneg;
293 }
9d5c8243 294 ecmd->advertising = hw->phy.autoneg_advertised;
0cce119a
AD		 295 if (adapter->fc_autoneg)
296 hw->fc.requested_mode = e1000_fc_default;
dcc3ae9a 297 } else {
25db0338 298 u32 speed = ethtool_cmd_speed(ecmd);
8376dad0 299 /* calling this overrides forced MDI setting */
14ad2513 300 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
9d5c8243
AK		 301 clear_bit(__IGB_RESETTING, &adapter->state);
302 return -EINVAL;
303 }
dcc3ae9a 304 }
9d5c8243 305
8376dad0
JB		 306 /* MDI-X => 2; MDI => 1; Auto => 3 */
307 if (ecmd->eth_tp_mdix_ctrl) {
308 /*
309 * fix up the value for auto (3 => 0) as zero is mapped
310 * internally to auto
311 */
312 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
313 hw->phy.mdix = AUTO_ALL_MODES;
314 else
315 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
316 }
317
9d5c8243 318 /* reset the link */
9d5c8243
AK		 319 if (netif_running(adapter->netdev)) {
320 igb_down(adapter);
321 igb_up(adapter);
322 } else
323 igb_reset(adapter);
324
325 clear_bit(__IGB_RESETTING, &adapter->state);
326 return 0;
327}
328
3145535a
NN		 329static u32 igb_get_link(struct net_device *netdev)
330{
331 struct igb_adapter *adapter = netdev_priv(netdev);
332 struct e1000_mac_info *mac = &adapter->hw.mac;
333
334 /*
335 * If the link is not reported up to netdev, interrupts are disabled,
336 * and so the physical link state may have changed since we last
337 * looked. Set get_link_status to make sure that the true link
338 * state is interrogated, rather than pulling a cached and possibly
339 * stale link state from the driver.
340 */
341 if (!netif_carrier_ok(netdev))
342 mac->get_link_status = 1;
343
344 return igb_has_link(adapter);
345}
346
9d5c8243
AK		 347static void igb_get_pauseparam(struct net_device *netdev,
348 struct ethtool_pauseparam *pause)
349{
350 struct igb_adapter *adapter = netdev_priv(netdev);
351 struct e1000_hw *hw = &adapter->hw;
352
353 pause->autoneg =
354 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
355
0cce119a 356 if (hw->fc.current_mode == e1000_fc_rx_pause)
9d5c8243 357 pause->rx_pause = 1;
0cce119a 358 else if (hw->fc.current_mode == e1000_fc_tx_pause)
9d5c8243 359 pause->tx_pause = 1;
0cce119a 360 else if (hw->fc.current_mode == e1000_fc_full) {
9d5c8243
AK		 361 pause->rx_pause = 1;
362 pause->tx_pause = 1;
363 }
364}
365
366static int igb_set_pauseparam(struct net_device *netdev,
367 struct ethtool_pauseparam *pause)
368{
369 struct igb_adapter *adapter = netdev_priv(netdev);
370 struct e1000_hw *hw = &adapter->hw;
371 int retval = 0;
372
373 adapter->fc_autoneg = pause->autoneg;
374
375 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
376 msleep(1);
377
9d5c8243 378 if (adapter->fc_autoneg == AUTONEG_ENABLE) {
0cce119a 379 hw->fc.requested_mode = e1000_fc_default;
9d5c8243
AK		 380 if (netif_running(adapter->netdev)) {
381 igb_down(adapter);
382 igb_up(adapter);
317f66bd 383 } else {
9d5c8243 384 igb_reset(adapter);
317f66bd 385 }
0cce119a
AD		 386 } else {
387 if (pause->rx_pause && pause->tx_pause)
388 hw->fc.requested_mode = e1000_fc_full;
389 else if (pause->rx_pause && !pause->tx_pause)
390 hw->fc.requested_mode = e1000_fc_rx_pause;
391 else if (!pause->rx_pause && pause->tx_pause)
392 hw->fc.requested_mode = e1000_fc_tx_pause;
393 else if (!pause->rx_pause && !pause->tx_pause)
394 hw->fc.requested_mode = e1000_fc_none;
395
396 hw->fc.current_mode = hw->fc.requested_mode;
397
dcc3ae9a
AD		 398 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
399 igb_force_mac_fc(hw) : igb_setup_link(hw));
0cce119a 400 }
9d5c8243
AK		 401
402 clear_bit(__IGB_RESETTING, &adapter->state);
403 return retval;
404}
405
9d5c8243
AK		 406static u32 igb_get_msglevel(struct net_device *netdev)
407{
408 struct igb_adapter *adapter = netdev_priv(netdev);
409 return adapter->msg_enable;
410}
411
412static void igb_set_msglevel(struct net_device *netdev, u32 data)
413{
414 struct igb_adapter *adapter = netdev_priv(netdev);
415 adapter->msg_enable = data;
416}
417
418static int igb_get_regs_len(struct net_device *netdev)
419{
7e3b4ffb 420#define IGB_REGS_LEN 739
9d5c8243
AK		 421 return IGB_REGS_LEN * sizeof(u32);
422}
423
424static void igb_get_regs(struct net_device *netdev,
425 struct ethtool_regs *regs, void *p)
426{
427 struct igb_adapter *adapter = netdev_priv(netdev);
428 struct e1000_hw *hw = &adapter->hw;
429 u32 *regs_buff = p;
430 u8 i;
431
432 memset(p, 0, IGB_REGS_LEN * sizeof(u32));
433
434 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
435
436 /* General Registers */
437 regs_buff[0] = rd32(E1000_CTRL);
438 regs_buff[1] = rd32(E1000_STATUS);
439 regs_buff[2] = rd32(E1000_CTRL_EXT);
440 regs_buff[3] = rd32(E1000_MDIC);
441 regs_buff[4] = rd32(E1000_SCTL);
442 regs_buff[5] = rd32(E1000_CONNSW);
443 regs_buff[6] = rd32(E1000_VET);
444 regs_buff[7] = rd32(E1000_LEDCTL);
445 regs_buff[8] = rd32(E1000_PBA);
446 regs_buff[9] = rd32(E1000_PBS);
447 regs_buff[10] = rd32(E1000_FRTIMER);
448 regs_buff[11] = rd32(E1000_TCPTIMER);
449
450 /* NVM Register */
451 regs_buff[12] = rd32(E1000_EECD);
452
453 /* Interrupt */
fe59de38
AD		 454 /* Reading EICS for EICR because they read the
455 * same but EICS does not clear on read */
456 regs_buff[13] = rd32(E1000_EICS);
9d5c8243
AK		 457 regs_buff[14] = rd32(E1000_EICS);
458 regs_buff[15] = rd32(E1000_EIMS);
459 regs_buff[16] = rd32(E1000_EIMC);
460 regs_buff[17] = rd32(E1000_EIAC);
461 regs_buff[18] = rd32(E1000_EIAM);
fe59de38
AD		 462 /* Reading ICS for ICR because they read the
463 * same but ICS does not clear on read */
464 regs_buff[19] = rd32(E1000_ICS);
9d5c8243
AK		 465 regs_buff[20] = rd32(E1000_ICS);
466 regs_buff[21] = rd32(E1000_IMS);
467 regs_buff[22] = rd32(E1000_IMC);
468 regs_buff[23] = rd32(E1000_IAC);
469 regs_buff[24] = rd32(E1000_IAM);
470 regs_buff[25] = rd32(E1000_IMIRVP);
471
472 /* Flow Control */
473 regs_buff[26] = rd32(E1000_FCAL);
474 regs_buff[27] = rd32(E1000_FCAH);
475 regs_buff[28] = rd32(E1000_FCTTV);
476 regs_buff[29] = rd32(E1000_FCRTL);
477 regs_buff[30] = rd32(E1000_FCRTH);
478 regs_buff[31] = rd32(E1000_FCRTV);
479
480 /* Receive */
481 regs_buff[32] = rd32(E1000_RCTL);
482 regs_buff[33] = rd32(E1000_RXCSUM);
483 regs_buff[34] = rd32(E1000_RLPML);
484 regs_buff[35] = rd32(E1000_RFCTL);
485 regs_buff[36] = rd32(E1000_MRQC);
e1739522 486 regs_buff[37] = rd32(E1000_VT_CTL);
9d5c8243
AK		 487
488 /* Transmit */
489 regs_buff[38] = rd32(E1000_TCTL);
490 regs_buff[39] = rd32(E1000_TCTL_EXT);
491 regs_buff[40] = rd32(E1000_TIPG);
492 regs_buff[41] = rd32(E1000_DTXCTL);
493
494 /* Wake Up */
495 regs_buff[42] = rd32(E1000_WUC);
496 regs_buff[43] = rd32(E1000_WUFC);
497 regs_buff[44] = rd32(E1000_WUS);
498 regs_buff[45] = rd32(E1000_IPAV);
499 regs_buff[46] = rd32(E1000_WUPL);
500
501 /* MAC */
502 regs_buff[47] = rd32(E1000_PCS_CFG0);
503 regs_buff[48] = rd32(E1000_PCS_LCTL);
504 regs_buff[49] = rd32(E1000_PCS_LSTAT);
505 regs_buff[50] = rd32(E1000_PCS_ANADV);
506 regs_buff[51] = rd32(E1000_PCS_LPAB);
507 regs_buff[52] = rd32(E1000_PCS_NPTX);
508 regs_buff[53] = rd32(E1000_PCS_LPABNP);
509
510 /* Statistics */
511 regs_buff[54] = adapter->stats.crcerrs;
512 regs_buff[55] = adapter->stats.algnerrc;
513 regs_buff[56] = adapter->stats.symerrs;
514 regs_buff[57] = adapter->stats.rxerrc;
515 regs_buff[58] = adapter->stats.mpc;
516 regs_buff[59] = adapter->stats.scc;
517 regs_buff[60] = adapter->stats.ecol;
518 regs_buff[61] = adapter->stats.mcc;
519 regs_buff[62] = adapter->stats.latecol;
520 regs_buff[63] = adapter->stats.colc;
521 regs_buff[64] = adapter->stats.dc;
522 regs_buff[65] = adapter->stats.tncrs;
523 regs_buff[66] = adapter->stats.sec;
524 regs_buff[67] = adapter->stats.htdpmc;
525 regs_buff[68] = adapter->stats.rlec;
526 regs_buff[69] = adapter->stats.xonrxc;
527 regs_buff[70] = adapter->stats.xontxc;
528 regs_buff[71] = adapter->stats.xoffrxc;
529 regs_buff[72] = adapter->stats.xofftxc;
530 regs_buff[73] = adapter->stats.fcruc;
531 regs_buff[74] = adapter->stats.prc64;
532 regs_buff[75] = adapter->stats.prc127;
533 regs_buff[76] = adapter->stats.prc255;
534 regs_buff[77] = adapter->stats.prc511;
535 regs_buff[78] = adapter->stats.prc1023;
536 regs_buff[79] = adapter->stats.prc1522;
537 regs_buff[80] = adapter->stats.gprc;
538 regs_buff[81] = adapter->stats.bprc;
539 regs_buff[82] = adapter->stats.mprc;
540 regs_buff[83] = adapter->stats.gptc;
541 regs_buff[84] = adapter->stats.gorc;
542 regs_buff[86] = adapter->stats.gotc;
543 regs_buff[88] = adapter->stats.rnbc;
544 regs_buff[89] = adapter->stats.ruc;
545 regs_buff[90] = adapter->stats.rfc;
546 regs_buff[91] = adapter->stats.roc;
547 regs_buff[92] = adapter->stats.rjc;
548 regs_buff[93] = adapter->stats.mgprc;
549 regs_buff[94] = adapter->stats.mgpdc;
550 regs_buff[95] = adapter->stats.mgptc;
551 regs_buff[96] = adapter->stats.tor;
552 regs_buff[98] = adapter->stats.tot;
553 regs_buff[100] = adapter->stats.tpr;
554 regs_buff[101] = adapter->stats.tpt;
555 regs_buff[102] = adapter->stats.ptc64;
556 regs_buff[103] = adapter->stats.ptc127;
557 regs_buff[104] = adapter->stats.ptc255;
558 regs_buff[105] = adapter->stats.ptc511;
559 regs_buff[106] = adapter->stats.ptc1023;
560 regs_buff[107] = adapter->stats.ptc1522;
561 regs_buff[108] = adapter->stats.mptc;
562 regs_buff[109] = adapter->stats.bptc;
563 regs_buff[110] = adapter->stats.tsctc;
564 regs_buff[111] = adapter->stats.iac;
565 regs_buff[112] = adapter->stats.rpthc;
566 regs_buff[113] = adapter->stats.hgptc;
567 regs_buff[114] = adapter->stats.hgorc;
568 regs_buff[116] = adapter->stats.hgotc;
569 regs_buff[118] = adapter->stats.lenerrs;
570 regs_buff[119] = adapter->stats.scvpc;
571 regs_buff[120] = adapter->stats.hrmpc;
572
9d5c8243
AK		 573 for (i = 0; i < 4; i++)
574 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
575 for (i = 0; i < 4; i++)
83ab50a5 576 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
9d5c8243
AK		 577 for (i = 0; i < 4; i++)
578 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
579 for (i = 0; i < 4; i++)
580 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
581 for (i = 0; i < 4; i++)
582 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
583 for (i = 0; i < 4; i++)
584 regs_buff[141 + i] = rd32(E1000_RDH(i));
585 for (i = 0; i < 4; i++)
586 regs_buff[145 + i] = rd32(E1000_RDT(i));
587 for (i = 0; i < 4; i++)
588 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
589
590 for (i = 0; i < 10; i++)
591 regs_buff[153 + i] = rd32(E1000_EITR(i));
592 for (i = 0; i < 8; i++)
593 regs_buff[163 + i] = rd32(E1000_IMIR(i));
594 for (i = 0; i < 8; i++)
595 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
596 for (i = 0; i < 16; i++)
597 regs_buff[179 + i] = rd32(E1000_RAL(i));
598 for (i = 0; i < 16; i++)
599 regs_buff[195 + i] = rd32(E1000_RAH(i));
600
601 for (i = 0; i < 4; i++)
602 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
603 for (i = 0; i < 4; i++)
604 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
605 for (i = 0; i < 4; i++)
606 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
607 for (i = 0; i < 4; i++)
608 regs_buff[223 + i] = rd32(E1000_TDH(i));
609 for (i = 0; i < 4; i++)
610 regs_buff[227 + i] = rd32(E1000_TDT(i));
611 for (i = 0; i < 4; i++)
612 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
613 for (i = 0; i < 4; i++)
614 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
615 for (i = 0; i < 4; i++)
616 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
617 for (i = 0; i < 4; i++)
618 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
619
620 for (i = 0; i < 4; i++)
621 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
622 for (i = 0; i < 4; i++)
623 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
624 for (i = 0; i < 32; i++)
625 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
626 for (i = 0; i < 128; i++)
627 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
628 for (i = 0; i < 128; i++)
629 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
630 for (i = 0; i < 4; i++)
631 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
632
633 regs_buff[547] = rd32(E1000_TDFH);
634 regs_buff[548] = rd32(E1000_TDFT);
635 regs_buff[549] = rd32(E1000_TDFHS);
636 regs_buff[550] = rd32(E1000_TDFPC);
f96a8a0b
CW		 637
638 if (hw->mac.type > e1000_82580) {
639 regs_buff[551] = adapter->stats.o2bgptc;
640 regs_buff[552] = adapter->stats.b2ospc;
641 regs_buff[553] = adapter->stats.o2bspc;
642 regs_buff[554] = adapter->stats.b2ogprc;
643 }
7e3b4ffb
KS		 644
645 if (hw->mac.type != e1000_82576)
646 return;
647 for (i = 0; i < 12; i++)
648 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
649 for (i = 0; i < 4; i++)
650 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
651 for (i = 0; i < 12; i++)
652 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
653 for (i = 0; i < 12; i++)
654 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
655 for (i = 0; i < 12; i++)
656 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
657 for (i = 0; i < 12; i++)
658 regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
659 for (i = 0; i < 12; i++)
660 regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
661 for (i = 0; i < 12; i++)
662 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
663
664 for (i = 0; i < 12; i++)
665 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
666 for (i = 0; i < 12; i++)
667 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
668 for (i = 0; i < 12; i++)
669 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
670 for (i = 0; i < 12; i++)
671 regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
672 for (i = 0; i < 12; i++)
673 regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
674 for (i = 0; i < 12; i++)
675 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
676 for (i = 0; i < 12; i++)
677 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
678 for (i = 0; i < 12; i++)
679 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
9d5c8243
AK		 680}
681
682static int igb_get_eeprom_len(struct net_device *netdev)
683{
684 struct igb_adapter *adapter = netdev_priv(netdev);
685 return adapter->hw.nvm.word_size * 2;
686}
687
688static int igb_get_eeprom(struct net_device *netdev,
689 struct ethtool_eeprom *eeprom, u8 *bytes)
690{
691 struct igb_adapter *adapter = netdev_priv(netdev);
692 struct e1000_hw *hw = &adapter->hw;
693 u16 *eeprom_buff;
694 int first_word, last_word;
695 int ret_val = 0;
696 u16 i;
697
698 if (eeprom->len == 0)
699 return -EINVAL;
700
701 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
702
703 first_word = eeprom->offset >> 1;
704 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
705
706 eeprom_buff = kmalloc(sizeof(u16) *
707 (last_word - first_word + 1), GFP_KERNEL);
708 if (!eeprom_buff)
709 return -ENOMEM;
710
711 if (hw->nvm.type == e1000_nvm_eeprom_spi)
312c75ae 712 ret_val = hw->nvm.ops.read(hw, first_word,
9d5c8243
AK		 713 last_word - first_word + 1,
714 eeprom_buff);
715 else {
716 for (i = 0; i < last_word - first_word + 1; i++) {
312c75ae 717 ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
9d5c8243
AK		 718 &eeprom_buff[i]);
719 if (ret_val)
720 break;
721 }
722 }
723
724 /* Device's eeprom is always little-endian, word addressable */
725 for (i = 0; i < last_word - first_word + 1; i++)
726 le16_to_cpus(&eeprom_buff[i]);
727
728 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
729 eeprom->len);
730 kfree(eeprom_buff);
731
732 return ret_val;
733}
734
735static int igb_set_eeprom(struct net_device *netdev,
736 struct ethtool_eeprom *eeprom, u8 *bytes)
737{
738 struct igb_adapter *adapter = netdev_priv(netdev);
739 struct e1000_hw *hw = &adapter->hw;
740 u16 *eeprom_buff;
741 void *ptr;
742 int max_len, first_word, last_word, ret_val = 0;
743 u16 i;
744
745 if (eeprom->len == 0)
746 return -EOPNOTSUPP;
747
f96a8a0b
CW		 748 if (hw->mac.type == e1000_i211)
749 return -EOPNOTSUPP;
750
9d5c8243
AK		 751 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
752 return -EFAULT;
753
754 max_len = hw->nvm.word_size * 2;
755
756 first_word = eeprom->offset >> 1;
757 last_word = (eeprom->offset + eeprom->len - 1) >> 1;
758 eeprom_buff = kmalloc(max_len, GFP_KERNEL);
759 if (!eeprom_buff)
760 return -ENOMEM;
761
762 ptr = (void *)eeprom_buff;
763
764 if (eeprom->offset & 1) {
765 /* need read/modify/write of first changed EEPROM word */
766 /* only the second byte of the word is being modified */
312c75ae 767 ret_val = hw->nvm.ops.read(hw, first_word, 1,
9d5c8243
AK		 768 &eeprom_buff[0]);
769 ptr++;
770 }
771 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
772 /* need read/modify/write of last changed EEPROM word */
773 /* only the first byte of the word is being modified */
312c75ae 774 ret_val = hw->nvm.ops.read(hw, last_word, 1,
9d5c8243
AK		 775 &eeprom_buff[last_word - first_word]);
776 }
777
778 /* Device's eeprom is always little-endian, word addressable */
779 for (i = 0; i < last_word - first_word + 1; i++)
780 le16_to_cpus(&eeprom_buff[i]);
781
782 memcpy(ptr, bytes, eeprom->len);
783
784 for (i = 0; i < last_word - first_word + 1; i++)
785 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
786
312c75ae 787 ret_val = hw->nvm.ops.write(hw, first_word,
9d5c8243
AK		 788 last_word - first_word + 1, eeprom_buff);
789
790 /* Update the checksum over the first part of the EEPROM if needed
791 * and flush shadow RAM for 82573 controllers */
792 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
4322e561 793 hw->nvm.ops.update(hw);
9d5c8243 794
d67974f0 795 igb_set_fw_version(adapter);
9d5c8243
AK		 796 kfree(eeprom_buff);
797 return ret_val;
798}
799
800static void igb_get_drvinfo(struct net_device *netdev,
801 struct ethtool_drvinfo *drvinfo)
802{
803 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 804
612a94d6
RJ		 805 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver));
806 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
9d5c8243 807
d67974f0
CW		 808 /*
809 * EEPROM image version # is reported as firmware version # for
810 * 82575 controllers
811 */
812 strlcpy(drvinfo->fw_version, adapter->fw_version,
813 sizeof(drvinfo->fw_version));
612a94d6
RJ		 814 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
815 sizeof(drvinfo->bus_info));
9d5c8243
AK		 816 drvinfo->n_stats = IGB_STATS_LEN;
817 drvinfo->testinfo_len = IGB_TEST_LEN;
818 drvinfo->regdump_len = igb_get_regs_len(netdev);
819 drvinfo->eedump_len = igb_get_eeprom_len(netdev);
820}
821
822static void igb_get_ringparam(struct net_device *netdev,
823 struct ethtool_ringparam *ring)
824{
825 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243
AK		 826
827 ring->rx_max_pending = IGB_MAX_RXD;
828 ring->tx_max_pending = IGB_MAX_TXD;
68fd9910
AD		 829 ring->rx_pending = adapter->rx_ring_count;
830 ring->tx_pending = adapter->tx_ring_count;
9d5c8243
AK		 831}
832
833static int igb_set_ringparam(struct net_device *netdev,
834 struct ethtool_ringparam *ring)
835{
836 struct igb_adapter *adapter = netdev_priv(netdev);
68fd9910 837 struct igb_ring *temp_ring;
6d9f4fc4 838 int i, err = 0;
0e15439a 839 u16 new_rx_count, new_tx_count;
9d5c8243
AK		 840
841 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
842 return -EINVAL;
843
0e15439a
AD		 844 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
845 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
9d5c8243
AK		 846 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
847
0e15439a
AD		 848 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
849 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
9d5c8243
AK		 850 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
851
68fd9910
AD		 852 if ((new_tx_count == adapter->tx_ring_count) &&
853 (new_rx_count == adapter->rx_ring_count)) {
9d5c8243
AK		 854 /* nothing to do */
855 return 0;
856 }
857
6d9f4fc4
AD		 858 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
859 msleep(1);
860
861 if (!netif_running(adapter->netdev)) {
862 for (i = 0; i < adapter->num_tx_queues; i++)
3025a446 863 adapter->tx_ring[i]->count = new_tx_count;
6d9f4fc4 864 for (i = 0; i < adapter->num_rx_queues; i++)
3025a446 865 adapter->rx_ring[i]->count = new_rx_count;
6d9f4fc4
AD		 866 adapter->tx_ring_count = new_tx_count;
867 adapter->rx_ring_count = new_rx_count;
868 goto clear_reset;
869 }
870
68fd9910
AD		 871 if (adapter->num_tx_queues > adapter->num_rx_queues)
872 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
873 else
874 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
68fd9910 875
6d9f4fc4
AD		 876 if (!temp_ring) {
877 err = -ENOMEM;
878 goto clear_reset;
879 }
9d5c8243 880
6d9f4fc4 881 igb_down(adapter);
9d5c8243
AK		 882
883 /*
884 * We can't just free everything and then setup again,
885 * because the ISRs in MSI-X mode get passed pointers
886 * to the tx and rx ring structs.
887 */
68fd9910 888 if (new_tx_count != adapter->tx_ring_count) {
9d5c8243 889 for (i = 0; i < adapter->num_tx_queues; i++) {
3025a446
AD		 890 memcpy(&temp_ring[i], adapter->tx_ring[i],
891 sizeof(struct igb_ring));
892
68fd9910 893 temp_ring[i].count = new_tx_count;
80785298 894 err = igb_setup_tx_resources(&temp_ring[i]);
9d5c8243 895 if (err) {
68fd9910
AD		 896 while (i) {
897 i--;
898 igb_free_tx_resources(&temp_ring[i]);
899 }
9d5c8243
AK		 900 goto err_setup;
901 }
9d5c8243 902 }
68fd9910 903
3025a446
AD		 904 for (i = 0; i < adapter->num_tx_queues; i++) {
905 igb_free_tx_resources(adapter->tx_ring[i]);
68fd9910 906
3025a446
AD		 907 memcpy(adapter->tx_ring[i], &temp_ring[i],
908 sizeof(struct igb_ring));
909 }
68fd9910
AD		 910
911 adapter->tx_ring_count = new_tx_count;
9d5c8243
AK		 912 }
913
3025a446 914 if (new_rx_count != adapter->rx_ring_count) {
68fd9910 915 for (i = 0; i < adapter->num_rx_queues; i++) {
3025a446
AD		 916 memcpy(&temp_ring[i], adapter->rx_ring[i],
917 sizeof(struct igb_ring));
918
68fd9910 919 temp_ring[i].count = new_rx_count;
80785298 920 err = igb_setup_rx_resources(&temp_ring[i]);
9d5c8243 921 if (err) {
68fd9910
AD		 922 while (i) {
923 i--;
924 igb_free_rx_resources(&temp_ring[i]);
925 }
9d5c8243
AK		 926 goto err_setup;
927 }
928
9d5c8243 929 }
68fd9910 930
3025a446
AD		 931 for (i = 0; i < adapter->num_rx_queues; i++) {
932 igb_free_rx_resources(adapter->rx_ring[i]);
68fd9910 933
3025a446
AD		 934 memcpy(adapter->rx_ring[i], &temp_ring[i],
935 sizeof(struct igb_ring));
936 }
68fd9910
AD		 937
938 adapter->rx_ring_count = new_rx_count;
9d5c8243 939 }
9d5c8243 940err_setup:
6d9f4fc4 941 igb_up(adapter);
68fd9910 942 vfree(temp_ring);
6d9f4fc4
AD		 943clear_reset:
944 clear_bit(__IGB_RESETTING, &adapter->state);
9d5c8243
AK		 945 return err;
946}
947
948/* ethtool register test data */
949struct igb_reg_test {
950 u16 reg;
2d064c06
AD		 951 u16 reg_offset;
952 u16 array_len;
953 u16 test_type;
9d5c8243
AK		 954 u32 mask;
955 u32 write;
956};
957
958/* In the hardware, registers are laid out either singly, in arrays
959 * spaced 0x100 bytes apart, or in contiguous tables. We assume
960 * most tests take place on arrays or single registers (handled
961 * as a single-element array) and special-case the tables.
962 * Table tests are always pattern tests.
963 *
964 * We also make provision for some required setup steps by specifying
965 * registers to be written without any read-back testing.
966 */
967
968#define PATTERN_TEST 1
969#define SET_READ_TEST 2
970#define WRITE_NO_TEST 3
971#define TABLE32_TEST 4
972#define TABLE64_TEST_LO 5
973#define TABLE64_TEST_HI 6
974
f96a8a0b
CW		 975/* i210 reg test */
976static struct igb_reg_test reg_test_i210[] = {
977 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
978 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
979 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
980 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
981 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
982 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
983 /* RDH is read-only for i210, only test RDT. */
984 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
985 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
986 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
987 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
988 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
989 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
990 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
991 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
992 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
993 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
994 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
995 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
996 { E1000_RA, 0, 16, TABLE64_TEST_LO,
997 0xFFFFFFFF, 0xFFFFFFFF },
998 { E1000_RA, 0, 16, TABLE64_TEST_HI,
999 0x900FFFFF, 0xFFFFFFFF },
1000 { E1000_MTA, 0, 128, TABLE32_TEST,
1001 0xFFFFFFFF, 0xFFFFFFFF },
1002 { 0, 0, 0, 0, 0 }
1003};
1004
d2ba2ed8
AD		 1005/* i350 reg test */
1006static struct igb_reg_test reg_test_i350[] = {
1007 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1008 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1009 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1010 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
1011 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1012 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1013 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1014 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1015 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1016 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1017 /* RDH is read-only for i350, only test RDT. */
1018 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1019 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1020 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1021 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1022 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1023 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1024 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1025 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1026 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1027 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1b6e6618 1028 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
d2ba2ed8
AD		 1029 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1030 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1031 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1032 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1033 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1034 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1035 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1036 0xFFFFFFFF, 0xFFFFFFFF },
1037 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1038 0xC3FFFFFF, 0xFFFFFFFF },
1039 { E1000_RA2, 0, 16, TABLE64_TEST_LO,
1040 0xFFFFFFFF, 0xFFFFFFFF },
1041 { E1000_RA2, 0, 16, TABLE64_TEST_HI,
1042 0xC3FFFFFF, 0xFFFFFFFF },
1043 { E1000_MTA, 0, 128, TABLE32_TEST,
1044 0xFFFFFFFF, 0xFFFFFFFF },
1045 { 0, 0, 0, 0 }
1046};
1047
55cac248
AD		 1048/* 82580 reg test */
1049static struct igb_reg_test reg_test_82580[] = {
1050 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1051 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1052 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1053 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1054 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1055 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1056 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1057 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1058 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1059 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1060 /* RDH is read-only for 82580, only test RDT. */
1061 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1062 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1063 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1064 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1065 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1066 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1067 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1068 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1069 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1070 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1071 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1072 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1073 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1074 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1075 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1076 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1077 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1078 { E1000_RA, 0, 16, TABLE64_TEST_LO,
1079 0xFFFFFFFF, 0xFFFFFFFF },
1080 { E1000_RA, 0, 16, TABLE64_TEST_HI,
1081 0x83FFFFFF, 0xFFFFFFFF },
1082 { E1000_RA2, 0, 8, TABLE64_TEST_LO,
1083 0xFFFFFFFF, 0xFFFFFFFF },
1084 { E1000_RA2, 0, 8, TABLE64_TEST_HI,
1085 0x83FFFFFF, 0xFFFFFFFF },
1086 { E1000_MTA, 0, 128, TABLE32_TEST,
1087 0xFFFFFFFF, 0xFFFFFFFF },
1088 { 0, 0, 0, 0 }
1089};
1090
2d064c06
AD		 1091/* 82576 reg test */
1092static struct igb_reg_test reg_test_82576[] = {
1093 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1094 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1095 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1096 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1097 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1098 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1099 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 1100 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1101 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1102 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1103 /* Enable all RX queues before testing. */
1104 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1105 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
2d064c06
AD		 1106 /* RDH is read-only for 82576, only test RDT. */
1107 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2753f4ce 1108 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
2d064c06 1109 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
2753f4ce 1110 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 },
2d064c06
AD		 1111 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1112 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1113 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1114 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1115 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1116 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2753f4ce
AD		 1117 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1118 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1119 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
2d064c06
AD		 1120 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1121 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1122 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1123 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1124 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1125 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1126 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1127 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1128 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1129 { 0, 0, 0, 0 }
1130};
1131
1132/* 82575 register test */
9d5c8243 1133static struct igb_reg_test reg_test_82575[] = {
2d064c06
AD		 1134 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1135 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1136 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1137 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1138 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1139 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1140 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
9d5c8243 1141 /* Enable all four RX queues before testing. */
2d064c06 1142 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
9d5c8243 1143 /* RDH is read-only for 82575, only test RDT. */
2d064c06
AD		 1144 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1145 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1146 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1147 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1148 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1149 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1150 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1151 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1152 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1153 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1154 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1155 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1156 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1157 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1158 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1159 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
9d5c8243
AK		 1160 { 0, 0, 0, 0 }
1161};
1162
1163static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1164 int reg, u32 mask, u32 write)
1165{
2753f4ce 1166 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1167 u32 pat, val;
317f66bd 1168 static const u32 _test[] =
9d5c8243
AK		 1169 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1170 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
2753f4ce 1171 wr32(reg, (_test[pat] & write));
93ed8359 1172 val = rd32(reg) & mask;
9d5c8243 1173 if (val != (_test[pat] & write & mask)) {
d836200a
JJ		 1174 dev_err(&adapter->pdev->dev,
1175 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n",
9d5c8243
AK		 1176 reg, val, (_test[pat] & write & mask));
1177 *data = reg;
1178 return 1;
1179 }
1180 }
317f66bd 1181
9d5c8243
AK		 1182 return 0;
1183}
1184
1185static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1186 int reg, u32 mask, u32 write)
1187{
2753f4ce 1188 struct e1000_hw *hw = &adapter->hw;
9d5c8243 1189 u32 val;
2753f4ce
AD		 1190 wr32(reg, write & mask);
1191 val = rd32(reg);
9d5c8243 1192 if ((write & mask) != (val & mask)) {
d836200a
JJ		 1193 dev_err(&adapter->pdev->dev,
1194 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", reg,
9d5c8243
AK		 1195 (val & mask), (write & mask));
1196 *data = reg;
1197 return 1;
1198 }
317f66bd 1199
9d5c8243
AK		 1200 return 0;
1201}
1202
1203#define REG_PATTERN_TEST(reg, mask, write) \
1204 do { \
1205 if (reg_pattern_test(adapter, data, reg, mask, write)) \
1206 return 1; \
1207 } while (0)
1208
1209#define REG_SET_AND_CHECK(reg, mask, write) \
1210 do { \
1211 if (reg_set_and_check(adapter, data, reg, mask, write)) \
1212 return 1; \
1213 } while (0)
1214
1215static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1216{
1217 struct e1000_hw *hw = &adapter->hw;
1218 struct igb_reg_test *test;
1219 u32 value, before, after;
1220 u32 i, toggle;
1221
2d064c06 1222 switch (adapter->hw.mac.type) {
d2ba2ed8
AD		 1223 case e1000_i350:
1224 test = reg_test_i350;
1225 toggle = 0x7FEFF3FF;
1226 break;
f96a8a0b
CW		 1227 case e1000_i210:
1228 case e1000_i211:
1229 test = reg_test_i210;
1230 toggle = 0x7FEFF3FF;
1231 break;
55cac248
AD		 1232 case e1000_82580:
1233 test = reg_test_82580;
1234 toggle = 0x7FEFF3FF;
1235 break;
2d064c06
AD		 1236 case e1000_82576:
1237 test = reg_test_82576;
317f66bd 1238 toggle = 0x7FFFF3FF;
2d064c06
AD		 1239 break;
1240 default:
1241 test = reg_test_82575;
317f66bd 1242 toggle = 0x7FFFF3FF;
2d064c06
AD		 1243 break;
1244 }
9d5c8243
AK		 1245
1246 /* Because the status register is such a special case,
1247 * we handle it separately from the rest of the register
1248 * tests. Some bits are read-only, some toggle, and some
1249 * are writable on newer MACs.
1250 */
1251 before = rd32(E1000_STATUS);
1252 value = (rd32(E1000_STATUS) & toggle);
1253 wr32(E1000_STATUS, toggle);
1254 after = rd32(E1000_STATUS) & toggle;
1255 if (value != after) {
d836200a
JJ		 1256 dev_err(&adapter->pdev->dev,
1257 "failed STATUS register test got: 0x%08X expected: 0x%08X\n",
1258 after, value);
9d5c8243
AK		 1259 *data = 1;
1260 return 1;
1261 }
1262 /* restore previous status */
1263 wr32(E1000_STATUS, before);
1264
1265 /* Perform the remainder of the register test, looping through
1266 * the test table until we either fail or reach the null entry.
1267 */
1268 while (test->reg) {
1269 for (i = 0; i < test->array_len; i++) {
1270 switch (test->test_type) {
1271 case PATTERN_TEST:
2753f4ce
AD		 1272 REG_PATTERN_TEST(test->reg +
1273 (i * test->reg_offset),
9d5c8243
AK		 1274 test->mask,
1275 test->write);
1276 break;
1277 case SET_READ_TEST:
2753f4ce
AD		 1278 REG_SET_AND_CHECK(test->reg +
1279 (i * test->reg_offset),
9d5c8243
AK		 1280 test->mask,
1281 test->write);
1282 break;
1283 case WRITE_NO_TEST:
1284 writel(test->write,
1285 (adapter->hw.hw_addr + test->reg)
2d064c06 1286 + (i * test->reg_offset));
9d5c8243
AK		 1287 break;
1288 case TABLE32_TEST:
1289 REG_PATTERN_TEST(test->reg + (i * 4),
1290 test->mask,
1291 test->write);
1292 break;
1293 case TABLE64_TEST_LO:
1294 REG_PATTERN_TEST(test->reg + (i * 8),
1295 test->mask,
1296 test->write);
1297 break;
1298 case TABLE64_TEST_HI:
1299 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1300 test->mask,
1301 test->write);
1302 break;
1303 }
1304 }
1305 test++;
1306 }
1307
1308 *data = 0;
1309 return 0;
1310}
1311
1312static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1313{
9d5c8243 1314 *data = 0;
9d5c8243 1315
f96a8a0b
CW		 1316 /* Validate eeprom on all parts but i211 */
1317 if (adapter->hw.mac.type != e1000_i211) {
1318 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1319 *data = 2;
1320 }
9d5c8243
AK		 1321
1322 return *data;
1323}
1324
1325static irqreturn_t igb_test_intr(int irq, void *data)
1326{
317f66bd 1327 struct igb_adapter *adapter = (struct igb_adapter *) data;
9d5c8243
AK		 1328 struct e1000_hw *hw = &adapter->hw;
1329
1330 adapter->test_icr |= rd32(E1000_ICR);
1331
1332 return IRQ_HANDLED;
1333}
1334
1335static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1336{
1337 struct e1000_hw *hw = &adapter->hw;
1338 struct net_device *netdev = adapter->netdev;
2753f4ce 1339 u32 mask, ics_mask, i = 0, shared_int = true;
9d5c8243
AK		 1340 u32 irq = adapter->pdev->irq;
1341
1342 *data = 0;
1343
1344 /* Hook up test interrupt handler just for this test */
4eefa8f0
AD		 1345 if (adapter->msix_entries) {
1346 if (request_irq(adapter->msix_entries[0].vector,
a0607fd3 1347 igb_test_intr, 0, netdev->name, adapter)) {
4eefa8f0
AD		 1348 *data = 1;
1349 return -1;
1350 }
4eefa8f0 1351 } else if (adapter->flags & IGB_FLAG_HAS_MSI) {
9d5c8243 1352 shared_int = false;
4eefa8f0 1353 if (request_irq(irq,
a0607fd3 1354 igb_test_intr, 0, netdev->name, adapter)) {
9d5c8243
AK		 1355 *data = 1;
1356 return -1;
1357 }
a0607fd3 1358 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
4eefa8f0 1359 netdev->name, adapter)) {
9d5c8243 1360 shared_int = false;
a0607fd3 1361 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
4eefa8f0 1362 netdev->name, adapter)) {
9d5c8243
AK		 1363 *data = 1;
1364 return -1;
1365 }
1366 dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1367 (shared_int ? "shared" : "unshared"));
317f66bd 1368
9d5c8243 1369 /* Disable all the interrupts */
4eefa8f0 1370 wr32(E1000_IMC, ~0);
945a5151 1371 wrfl();
9d5c8243
AK		 1372 msleep(10);
1373
2753f4ce 1374 /* Define all writable bits for ICS */
4eefa8f0 1375 switch (hw->mac.type) {
2753f4ce
AD		 1376 case e1000_82575:
1377 ics_mask = 0x37F47EDD;
1378 break;
1379 case e1000_82576:
1380 ics_mask = 0x77D4FBFD;
1381 break;
55cac248
AD		 1382 case e1000_82580:
1383 ics_mask = 0x77DCFED5;
1384 break;
d2ba2ed8 1385 case e1000_i350:
f96a8a0b
CW		 1386 case e1000_i210:
1387 case e1000_i211:
d2ba2ed8
AD		 1388 ics_mask = 0x77DCFED5;
1389 break;
2753f4ce
AD		 1390 default:
1391 ics_mask = 0x7FFFFFFF;
1392 break;
1393 }
1394
9d5c8243 1395 /* Test each interrupt */
2753f4ce 1396 for (; i < 31; i++) {
9d5c8243
AK		 1397 /* Interrupt to test */
1398 mask = 1 << i;
1399
2753f4ce
AD		 1400 if (!(mask & ics_mask))
1401 continue;
1402
9d5c8243
AK		 1403 if (!shared_int) {
1404 /* Disable the interrupt to be reported in
1405 * the cause register and then force the same
1406 * interrupt and see if one gets posted. If
1407 * an interrupt was posted to the bus, the
1408 * test failed.
1409 */
1410 adapter->test_icr = 0;
2753f4ce
AD		 1411
1412 /* Flush any pending interrupts */
1413 wr32(E1000_ICR, ~0);
1414
1415 wr32(E1000_IMC, mask);
1416 wr32(E1000_ICS, mask);
945a5151 1417 wrfl();
9d5c8243
AK		 1418 msleep(10);
1419
1420 if (adapter->test_icr & mask) {
1421 *data = 3;
1422 break;
1423 }
1424 }
1425
1426 /* Enable the interrupt to be reported in
1427 * the cause register and then force the same
1428 * interrupt and see if one gets posted. If
1429 * an interrupt was not posted to the bus, the
1430 * test failed.
1431 */
1432 adapter->test_icr = 0;
2753f4ce
AD		 1433
1434 /* Flush any pending interrupts */
1435 wr32(E1000_ICR, ~0);
1436
9d5c8243
AK		 1437 wr32(E1000_IMS, mask);
1438 wr32(E1000_ICS, mask);
945a5151 1439 wrfl();
9d5c8243
AK		 1440 msleep(10);
1441
1442 if (!(adapter->test_icr & mask)) {
1443 *data = 4;
1444 break;
1445 }
1446
1447 if (!shared_int) {
1448 /* Disable the other interrupts to be reported in
1449 * the cause register and then force the other
1450 * interrupts and see if any get posted. If
1451 * an interrupt was posted to the bus, the
1452 * test failed.
1453 */
1454 adapter->test_icr = 0;
2753f4ce
AD		 1455
1456 /* Flush any pending interrupts */
1457 wr32(E1000_ICR, ~0);
1458
1459 wr32(E1000_IMC, ~mask);
1460 wr32(E1000_ICS, ~mask);
945a5151 1461 wrfl();
9d5c8243
AK		 1462 msleep(10);
1463
2753f4ce 1464 if (adapter->test_icr & mask) {
9d5c8243
AK		 1465 *data = 5;
1466 break;
1467 }
1468 }
1469 }
1470
1471 /* Disable all the interrupts */
2753f4ce 1472 wr32(E1000_IMC, ~0);
945a5151 1473 wrfl();
9d5c8243
AK		 1474 msleep(10);
1475
1476 /* Unhook test interrupt handler */
4eefa8f0
AD		 1477 if (adapter->msix_entries)
1478 free_irq(adapter->msix_entries[0].vector, adapter);
1479 else
1480 free_irq(irq, adapter);
9d5c8243
AK		 1481
1482 return *data;
1483}
1484
1485static void igb_free_desc_rings(struct igb_adapter *adapter)
1486{
d7ee5b3a
AD		 1487 igb_free_tx_resources(&adapter->test_tx_ring);
1488 igb_free_rx_resources(&adapter->test_rx_ring);
9d5c8243
AK		 1489}
1490
1491static int igb_setup_desc_rings(struct igb_adapter *adapter)
1492{
9d5c8243
AK		 1493 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1494 struct igb_ring *rx_ring = &adapter->test_rx_ring;
d7ee5b3a 1495 struct e1000_hw *hw = &adapter->hw;
ad93d17e 1496 int ret_val;
9d5c8243
AK		 1497
1498 /* Setup Tx descriptor ring and Tx buffers */
d7ee5b3a 1499 tx_ring->count = IGB_DEFAULT_TXD;
59d71989 1500 tx_ring->dev = &adapter->pdev->dev;
d7ee5b3a
AD		 1501 tx_ring->netdev = adapter->netdev;
1502 tx_ring->reg_idx = adapter->vfs_allocated_count;
9d5c8243 1503
d7ee5b3a 1504 if (igb_setup_tx_resources(tx_ring)) {
9d5c8243
AK		 1505 ret_val = 1;
1506 goto err_nomem;
1507 }
1508
d7ee5b3a
AD		 1509 igb_setup_tctl(adapter);
1510 igb_configure_tx_ring(adapter, tx_ring);
9d5c8243 1511
9d5c8243 1512 /* Setup Rx descriptor ring and Rx buffers */
d7ee5b3a 1513 rx_ring->count = IGB_DEFAULT_RXD;
59d71989 1514 rx_ring->dev = &adapter->pdev->dev;
d7ee5b3a 1515 rx_ring->netdev = adapter->netdev;
d7ee5b3a
AD		 1516 rx_ring->reg_idx = adapter->vfs_allocated_count;
1517
1518 if (igb_setup_rx_resources(rx_ring)) {
1519 ret_val = 3;
9d5c8243
AK		 1520 goto err_nomem;
1521 }
9d5c8243 1522
d7ee5b3a
AD		 1523 /* set the default queue to queue 0 of PF */
1524 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
9d5c8243 1525
d7ee5b3a
AD		 1526 /* enable receive ring */
1527 igb_setup_rctl(adapter);
1528 igb_configure_rx_ring(adapter, rx_ring);
9d5c8243 1529
cd392f5c 1530 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
9d5c8243
AK		 1531
1532 return 0;
1533
1534err_nomem:
1535 igb_free_desc_rings(adapter);
1536 return ret_val;
1537}
1538
1539static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1540{
1541 struct e1000_hw *hw = &adapter->hw;
1542
1543 /* Write out to PHY registers 29 and 30 to disable the Receiver. */
f5f4cf08
AD		 1544 igb_write_phy_reg(hw, 29, 0x001F);
1545 igb_write_phy_reg(hw, 30, 0x8FFC);
1546 igb_write_phy_reg(hw, 29, 0x001A);
1547 igb_write_phy_reg(hw, 30, 0x8FF0);
9d5c8243
AK		 1548}
1549
1550static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1551{
1552 struct e1000_hw *hw = &adapter->hw;
1553 u32 ctrl_reg = 0;
9d5c8243
AK		 1554
1555 hw->mac.autoneg = false;
1556
8aa23f0d
CW		 1557 if (hw->phy.type == e1000_phy_m88) {
1558 if (hw->phy.id != I210_I_PHY_ID) {
1559 /* Auto-MDI/MDIX Off */
1560 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1561 /* reset to update Auto-MDI/MDIX */
1562 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1563 /* autoneg off */
1564 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1565 } else {
1566 /* force 1000, set loopback */
1567 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0);
1568 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1569 }
9d5c8243
AK		 1570 }
1571
119b0e03
SA		 1572 /* add small delay to avoid loopback test failure */
1573 msleep(50);
1574
9d5c8243 1575 /* force 1000, set loopback */
f5f4cf08 1576 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
9d5c8243
AK		 1577
1578 /* Now set up the MAC to the same speed/duplex as the PHY. */
1579 ctrl_reg = rd32(E1000_CTRL);
1580 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1581 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1582 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1583 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
cdfa9f64
AD		 1584 E1000_CTRL_FD | /* Force Duplex to FULL */
1585 E1000_CTRL_SLU); /* Set link up enable bit */
9d5c8243 1586
8aa23f0d 1587 if (hw->phy.type == e1000_phy_m88)
9d5c8243 1588 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
9d5c8243
AK		 1589
1590 wr32(E1000_CTRL, ctrl_reg);
1591
1592 /* Disable the receiver on the PHY so when a cable is plugged in, the
1593 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1594 */
8aa23f0d 1595 if (hw->phy.type == e1000_phy_m88)
9d5c8243
AK		 1596 igb_phy_disable_receiver(adapter);
1597
8aa23f0d 1598 mdelay(500);
9d5c8243
AK		 1599 return 0;
1600}
1601
1602static int igb_set_phy_loopback(struct igb_adapter *adapter)
1603{
1604 return igb_integrated_phy_loopback(adapter);
1605}
1606
1607static int igb_setup_loopback_test(struct igb_adapter *adapter)
1608{
1609 struct e1000_hw *hw = &adapter->hw;
2d064c06 1610 u32 reg;
9d5c8243 1611
317f66bd
AD		 1612 reg = rd32(E1000_CTRL_EXT);
1613
1614 /* use CTRL_EXT to identify link type as SGMII can appear as copper */
1615 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
a14bc2bb
RH		 1616 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1617 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1618 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1619 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1620
1621 /* Enable DH89xxCC MPHY for near end loopback */
1622 reg = rd32(E1000_MPHY_ADDR_CTL);
1623 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1624 E1000_MPHY_PCS_CLK_REG_OFFSET;
1625 wr32(E1000_MPHY_ADDR_CTL, reg);
1626
1627 reg = rd32(E1000_MPHY_DATA);
1628 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1629 wr32(E1000_MPHY_DATA, reg);
1630 }
1631
2d064c06
AD		 1632 reg = rd32(E1000_RCTL);
1633 reg |= E1000_RCTL_LBM_TCVR;
1634 wr32(E1000_RCTL, reg);
1635
1636 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1637
1638 reg = rd32(E1000_CTRL);
1639 reg &= ~(E1000_CTRL_RFCE |
1640 E1000_CTRL_TFCE |
1641 E1000_CTRL_LRST);
1642 reg |= E1000_CTRL_SLU |
2753f4ce 1643 E1000_CTRL_FD;
2d064c06
AD		 1644 wr32(E1000_CTRL, reg);
1645
1646 /* Unset switch control to serdes energy detect */
1647 reg = rd32(E1000_CONNSW);
1648 reg &= ~E1000_CONNSW_ENRGSRC;
1649 wr32(E1000_CONNSW, reg);
1650
3860a0bf
CW		 1651 /* Unset sigdetect for SERDES loopback on
1652 * 82580 and i350 devices.
1653 */
1654 switch (hw->mac.type) {
1655 case e1000_82580:
1656 case e1000_i350:
1657 reg = rd32(E1000_PCS_CFG0);
1658 reg |= E1000_PCS_CFG_IGN_SD;
1659 wr32(E1000_PCS_CFG0, reg);
1660 break;
1661 default:
1662 break;
1663 }
1664
2d064c06
AD		 1665 /* Set PCS register for forced speed */
1666 reg = rd32(E1000_PCS_LCTL);
1667 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/
1668 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1669 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1670 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1671 E1000_PCS_LCTL_FSD | /* Force Speed */
1672 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1673 wr32(E1000_PCS_LCTL, reg);
1674
9d5c8243 1675 return 0;
9d5c8243
AK		 1676 }
1677
317f66bd 1678 return igb_set_phy_loopback(adapter);
9d5c8243
AK		 1679}
1680
1681static void igb_loopback_cleanup(struct igb_adapter *adapter)
1682{
1683 struct e1000_hw *hw = &adapter->hw;
1684 u32 rctl;
1685 u16 phy_reg;
1686
a14bc2bb
RH		 1687 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1688 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1689 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1690 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1691 u32 reg;
1692
1693 /* Disable near end loopback on DH89xxCC */
1694 reg = rd32(E1000_MPHY_ADDR_CTL);
1695 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1696 E1000_MPHY_PCS_CLK_REG_OFFSET;
1697 wr32(E1000_MPHY_ADDR_CTL, reg);
1698
1699 reg = rd32(E1000_MPHY_DATA);
1700 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1701 wr32(E1000_MPHY_DATA, reg);
1702 }
1703
9d5c8243
AK		 1704 rctl = rd32(E1000_RCTL);
1705 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1706 wr32(E1000_RCTL, rctl);
1707
1708 hw->mac.autoneg = true;
f5f4cf08 1709 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
9d5c8243
AK		 1710 if (phy_reg & MII_CR_LOOPBACK) {
1711 phy_reg &= ~MII_CR_LOOPBACK;
f5f4cf08 1712 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
9d5c8243
AK		 1713 igb_phy_sw_reset(hw);
1714 }
1715}
1716
1717static void igb_create_lbtest_frame(struct sk_buff *skb,
1718 unsigned int frame_size)
1719{
1720 memset(skb->data, 0xFF, frame_size);
317f66bd
AD		 1721 frame_size /= 2;
1722 memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1723 memset(&skb->data[frame_size + 10], 0xBE, 1);
1724 memset(&skb->data[frame_size + 12], 0xAF, 1);
9d5c8243
AK		 1725}
1726
1a1c225b
AD		 1727static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer,
1728 unsigned int frame_size)
9d5c8243 1729{
1a1c225b
AD		 1730 unsigned char *data;
1731 bool match = true;
1732
1733 frame_size >>= 1;
1734
cbc8e55f 1735 data = kmap(rx_buffer->page);
1a1c225b
AD		 1736
1737 if (data[3] != 0xFF ||
1738 data[frame_size + 10] != 0xBE ||
1739 data[frame_size + 12] != 0xAF)
1740 match = false;
1741
1742 kunmap(rx_buffer->page);
1743
1744 return match;
9d5c8243
AK		 1745}
1746
ad93d17e
AD		 1747static int igb_clean_test_rings(struct igb_ring *rx_ring,
1748 struct igb_ring *tx_ring,
1749 unsigned int size)
1750{
1751 union e1000_adv_rx_desc *rx_desc;
06034649
AD		 1752 struct igb_rx_buffer *rx_buffer_info;
1753 struct igb_tx_buffer *tx_buffer_info;
6ad4edfc 1754 u16 rx_ntc, tx_ntc, count = 0;
ad93d17e
AD		 1755
1756 /* initialize next to clean and descriptor values */
1757 rx_ntc = rx_ring->next_to_clean;
1758 tx_ntc = tx_ring->next_to_clean;
60136906 1759 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e 1760
3ceb90fd 1761 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
ad93d17e 1762 /* check rx buffer */
06034649 1763 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
ad93d17e 1764
cbc8e55f
AD		 1765 /* sync Rx buffer for CPU read */
1766 dma_sync_single_for_cpu(rx_ring->dev,
1767 rx_buffer_info->dma,
de78d1f9 1768 IGB_RX_BUFSZ,
cbc8e55f 1769 DMA_FROM_DEVICE);
ad93d17e
AD		 1770
1771 /* verify contents of skb */
1a1c225b 1772 if (igb_check_lbtest_frame(rx_buffer_info, size))
ad93d17e
AD		 1773 count++;
1774
cbc8e55f
AD		 1775 /* sync Rx buffer for device write */
1776 dma_sync_single_for_device(rx_ring->dev,
1777 rx_buffer_info->dma,
de78d1f9 1778 IGB_RX_BUFSZ,
cbc8e55f
AD		 1779 DMA_FROM_DEVICE);
1780
ad93d17e 1781 /* unmap buffer on tx side */
06034649
AD		 1782 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1783 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
ad93d17e
AD		 1784
1785 /* increment rx/tx next to clean counters */
1786 rx_ntc++;
1787 if (rx_ntc == rx_ring->count)
1788 rx_ntc = 0;
1789 tx_ntc++;
1790 if (tx_ntc == tx_ring->count)
1791 tx_ntc = 0;
1792
1793 /* fetch next descriptor */
60136906 1794 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
ad93d17e
AD		 1795 }
1796
cbc8e55f 1797 netdev_tx_reset_queue(txring_txq(tx_ring));
51a76c30 1798
ad93d17e 1799 /* re-map buffers to ring, store next to clean values */
cd392f5c 1800 igb_alloc_rx_buffers(rx_ring, count);
ad93d17e
AD		 1801 rx_ring->next_to_clean = rx_ntc;
1802 tx_ring->next_to_clean = tx_ntc;
1803
1804 return count;
1805}
1806
9d5c8243
AK		 1807static int igb_run_loopback_test(struct igb_adapter *adapter)
1808{
9d5c8243
AK		 1809 struct igb_ring *tx_ring = &adapter->test_tx_ring;
1810 struct igb_ring *rx_ring = &adapter->test_rx_ring;
6ad4edfc
AD		 1811 u16 i, j, lc, good_cnt;
1812 int ret_val = 0;
44390ca6 1813 unsigned int size = IGB_RX_HDR_LEN;
ad93d17e
AD		 1814 netdev_tx_t tx_ret_val;
1815 struct sk_buff *skb;
1816
1817 /* allocate test skb */
1818 skb = alloc_skb(size, GFP_KERNEL);
1819 if (!skb)
1820 return 11;
9d5c8243 1821
ad93d17e
AD		 1822 /* place data into test skb */
1823 igb_create_lbtest_frame(skb, size);
1824 skb_put(skb, size);
9d5c8243 1825
317f66bd
AD		 1826 /*
1827 * Calculate the loop count based on the largest descriptor ring
9d5c8243
AK		 1828 * The idea is to wrap the largest ring a number of times using 64
1829 * send/receive pairs during each loop
1830 */
1831
1832 if (rx_ring->count <= tx_ring->count)
1833 lc = ((tx_ring->count / 64) * 2) + 1;
1834 else
1835 lc = ((rx_ring->count / 64) * 2) + 1;
1836
9d5c8243 1837 for (j = 0; j <= lc; j++) { /* loop count loop */
ad93d17e 1838 /* reset count of good packets */
9d5c8243 1839 good_cnt = 0;
ad93d17e
AD		 1840
1841 /* place 64 packets on the transmit queue*/
1842 for (i = 0; i < 64; i++) {
1843 skb_get(skb);
cd392f5c 1844 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
ad93d17e 1845 if (tx_ret_val == NETDEV_TX_OK)
9d5c8243 1846 good_cnt++;
ad93d17e
AD		 1847 }
1848
9d5c8243 1849 if (good_cnt != 64) {
ad93d17e 1850 ret_val = 12;
9d5c8243
AK		 1851 break;
1852 }
ad93d17e
AD		 1853
1854 /* allow 200 milliseconds for packets to go from tx to rx */
1855 msleep(200);
1856
1857 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1858 if (good_cnt != 64) {
1859 ret_val = 13;
9d5c8243
AK		 1860 break;
1861 }
1862 } /* end loop count loop */
ad93d17e
AD		 1863
1864 /* free the original skb */
1865 kfree_skb(skb);
1866
9d5c8243
AK		 1867 return ret_val;
1868}
1869
1870static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1871{
1872 /* PHY loopback cannot be performed if SoL/IDER
1873 * sessions are active */
1874 if (igb_check_reset_block(&adapter->hw)) {
1875 dev_err(&adapter->pdev->dev,
d836200a 1876 "Cannot do PHY loopback test when SoL/IDER is active.\n");
f96a8a0b
CW		 1877 *data = 0;
1878 goto out;
1879 }
9d5c8243
AK		 1880 *data = igb_setup_desc_rings(adapter);
1881 if (*data)
1882 goto out;
1883 *data = igb_setup_loopback_test(adapter);
1884 if (*data)
1885 goto err_loopback;
1886 *data = igb_run_loopback_test(adapter);
1887 igb_loopback_cleanup(adapter);
1888
1889err_loopback:
1890 igb_free_desc_rings(adapter);
1891out:
1892 return *data;
1893}
1894
1895static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1896{
1897 struct e1000_hw *hw = &adapter->hw;
1898 *data = 0;
1899 if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1900 int i = 0;
1901 hw->mac.serdes_has_link = false;
1902
1903 /* On some blade server designs, link establishment
1904 * could take as long as 2-3 minutes */
1905 do {
1906 hw->mac.ops.check_for_link(&adapter->hw);
1907 if (hw->mac.serdes_has_link)
1908 return *data;
1909 msleep(20);
1910 } while (i++ < 3750);
1911
1912 *data = 1;
1913 } else {
1914 hw->mac.ops.check_for_link(&adapter->hw);
1915 if (hw->mac.autoneg)
4507dc9f 1916 msleep(5000);
9d5c8243 1917
317f66bd 1918 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
9d5c8243
AK		 1919 *data = 1;
1920 }
1921 return *data;
1922}
1923
1924static void igb_diag_test(struct net_device *netdev,
1925 struct ethtool_test *eth_test, u64 *data)
1926{
1927 struct igb_adapter *adapter = netdev_priv(netdev);
1928 u16 autoneg_advertised;
1929 u8 forced_speed_duplex, autoneg;
1930 bool if_running = netif_running(netdev);
1931
1932 set_bit(__IGB_TESTING, &adapter->state);
1933 if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1934 /* Offline tests */
1935
1936 /* save speed, duplex, autoneg settings */
1937 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1938 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1939 autoneg = adapter->hw.mac.autoneg;
1940
1941 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1942
88a268c1
NN		 1943 /* power up link for link test */
1944 igb_power_up_link(adapter);
1945
9d5c8243
AK		 1946 /* Link test performed before hardware reset so autoneg doesn't
1947 * interfere with test result */
1948 if (igb_link_test(adapter, &data[4]))
1949 eth_test->flags |= ETH_TEST_FL_FAILED;
1950
1951 if (if_running)
1952 /* indicate we're in test mode */
1953 dev_close(netdev);
1954 else
1955 igb_reset(adapter);
1956
1957 if (igb_reg_test(adapter, &data[0]))
1958 eth_test->flags |= ETH_TEST_FL_FAILED;
1959
1960 igb_reset(adapter);
1961 if (igb_eeprom_test(adapter, &data[1]))
1962 eth_test->flags |= ETH_TEST_FL_FAILED;
1963
1964 igb_reset(adapter);
1965 if (igb_intr_test(adapter, &data[2]))
1966 eth_test->flags |= ETH_TEST_FL_FAILED;
1967
1968 igb_reset(adapter);
88a268c1
NN		 1969 /* power up link for loopback test */
1970 igb_power_up_link(adapter);
9d5c8243
AK		 1971 if (igb_loopback_test(adapter, &data[3]))
1972 eth_test->flags |= ETH_TEST_FL_FAILED;
1973
1974 /* restore speed, duplex, autoneg settings */
1975 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1976 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1977 adapter->hw.mac.autoneg = autoneg;
1978
1979 /* force this routine to wait until autoneg complete/timeout */
1980 adapter->hw.phy.autoneg_wait_to_complete = true;
1981 igb_reset(adapter);
1982 adapter->hw.phy.autoneg_wait_to_complete = false;
1983
1984 clear_bit(__IGB_TESTING, &adapter->state);
1985 if (if_running)
1986 dev_open(netdev);
1987 } else {
1988 dev_info(&adapter->pdev->dev, "online testing starting\n");
88a268c1
NN		 1989
1990 /* PHY is powered down when interface is down */
8d420a1b
AD		 1991 if (if_running && igb_link_test(adapter, &data[4]))
1992 eth_test->flags |= ETH_TEST_FL_FAILED;
1993 else
88a268c1 1994 data[4] = 0;
9d5c8243
AK		 1995
1996 /* Online tests aren't run; pass by default */
1997 data[0] = 0;
1998 data[1] = 0;
1999 data[2] = 0;
2000 data[3] = 0;
2001
2002 clear_bit(__IGB_TESTING, &adapter->state);
2003 }
2004 msleep_interruptible(4 * 1000);
2005}
2006
9d5c8243
AK		 2007static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2008{
2009 struct igb_adapter *adapter = netdev_priv(netdev);
2010
2011 wol->supported = WAKE_UCAST | WAKE_MCAST |
22939f06
NN		 2012 WAKE_BCAST | WAKE_MAGIC |
2013 WAKE_PHY;
9d5c8243
AK		 2014 wol->wolopts = 0;
2015
63d4a8f9 2016 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
9d5c8243
AK		 2017 return;
2018
2019 /* apply any specific unsupported masks here */
2020 switch (adapter->hw.device_id) {
2021 default:
2022 break;
2023 }
2024
2025 if (adapter->wol & E1000_WUFC_EX)
2026 wol->wolopts |= WAKE_UCAST;
2027 if (adapter->wol & E1000_WUFC_MC)
2028 wol->wolopts |= WAKE_MCAST;
2029 if (adapter->wol & E1000_WUFC_BC)
2030 wol->wolopts |= WAKE_BCAST;
2031 if (adapter->wol & E1000_WUFC_MAG)
2032 wol->wolopts |= WAKE_MAGIC;
22939f06
NN		 2033 if (adapter->wol & E1000_WUFC_LNKC)
2034 wol->wolopts |= WAKE_PHY;
9d5c8243
AK		 2035}
2036
2037static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2038{
2039 struct igb_adapter *adapter = netdev_priv(netdev);
9d5c8243 2040
22939f06 2041 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
9d5c8243
AK		 2042 return -EOPNOTSUPP;
2043
63d4a8f9 2044 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED))
9d5c8243
AK		 2045 return wol->wolopts ? -EOPNOTSUPP : 0;
2046
9d5c8243
AK		 2047 /* these settings will always override what we currently have */
2048 adapter->wol = 0;
2049
2050 if (wol->wolopts & WAKE_UCAST)
2051 adapter->wol |= E1000_WUFC_EX;
2052 if (wol->wolopts & WAKE_MCAST)
2053 adapter->wol |= E1000_WUFC_MC;
2054 if (wol->wolopts & WAKE_BCAST)
2055 adapter->wol |= E1000_WUFC_BC;
2056 if (wol->wolopts & WAKE_MAGIC)
2057 adapter->wol |= E1000_WUFC_MAG;
22939f06
NN		 2058 if (wol->wolopts & WAKE_PHY)
2059 adapter->wol |= E1000_WUFC_LNKC;
e1b86d84
RW		 2060 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2061
9d5c8243
AK		 2062 return 0;
2063}
2064
9d5c8243
AK		 2065/* bit defines for adapter->led_status */
2066#define IGB_LED_ON 0
2067
936db355
JK		 2068static int igb_set_phys_id(struct net_device *netdev,
2069 enum ethtool_phys_id_state state)
9d5c8243
AK		 2070{
2071 struct igb_adapter *adapter = netdev_priv(netdev);
2072 struct e1000_hw *hw = &adapter->hw;
2073
936db355
JK		 2074 switch (state) {
2075 case ETHTOOL_ID_ACTIVE:
2076 igb_blink_led(hw);
2077 return 2;
2078 case ETHTOOL_ID_ON:
2079 igb_blink_led(hw);
2080 break;
2081 case ETHTOOL_ID_OFF:
2082 igb_led_off(hw);
2083 break;
2084 case ETHTOOL_ID_INACTIVE:
2085 igb_led_off(hw);
2086 clear_bit(IGB_LED_ON, &adapter->led_status);
2087 igb_cleanup_led(hw);
2088 break;
2089 }
9d5c8243
AK		 2090
2091 return 0;
2092}
2093
2094static int igb_set_coalesce(struct net_device *netdev,
2095 struct ethtool_coalesce *ec)
2096{
2097 struct igb_adapter *adapter = netdev_priv(netdev);
6eb5a7f1 2098 int i;
9d5c8243
AK		 2099
2100 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2101 ((ec->rx_coalesce_usecs > 3) &&
2102 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2103 (ec->rx_coalesce_usecs == 2))
2104 return -EINVAL;
2105
4fc82adf
AD		 2106 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2107 ((ec->tx_coalesce_usecs > 3) &&
2108 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2109 (ec->tx_coalesce_usecs == 2))
2110 return -EINVAL;
2111
2112 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2113 return -EINVAL;
2114
831ec0b4
CW		 2115 /* If ITR is disabled, disable DMAC */
2116 if (ec->rx_coalesce_usecs == 0) {
2117 if (adapter->flags & IGB_FLAG_DMAC)
2118 adapter->flags &= ~IGB_FLAG_DMAC;
2119 }
2120
9d5c8243 2121 /* convert to rate of irq's per second */
4fc82adf
AD		 2122 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2123 adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2124 else
2125 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2126
2127 /* convert to rate of irq's per second */
2128 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2129 adapter->tx_itr_setting = adapter->rx_itr_setting;
2130 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2131 adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2132 else
2133 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
9d5c8243 2134
047e0030
AD		 2135 for (i = 0; i < adapter->num_q_vectors; i++) {
2136 struct igb_q_vector *q_vector = adapter->q_vector[i];
0ba82994
AD		 2137 q_vector->tx.work_limit = adapter->tx_work_limit;
2138 if (q_vector->rx.ring)
4fc82adf
AD		 2139 q_vector->itr_val = adapter->rx_itr_setting;
2140 else
2141 q_vector->itr_val = adapter->tx_itr_setting;
2142 if (q_vector->itr_val && q_vector->itr_val <= 3)
2143 q_vector->itr_val = IGB_START_ITR;
047e0030
AD		 2144 q_vector->set_itr = 1;
2145 }
9d5c8243
AK		 2146
2147 return 0;
2148}
2149
2150static int igb_get_coalesce(struct net_device *netdev,
2151 struct ethtool_coalesce *ec)
2152{
2153 struct igb_adapter *adapter = netdev_priv(netdev);
2154
4fc82adf
AD		 2155 if (adapter->rx_itr_setting <= 3)
2156 ec->rx_coalesce_usecs = adapter->rx_itr_setting;
9d5c8243 2157 else
4fc82adf
AD		 2158 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2159
2160 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2161 if (adapter->tx_itr_setting <= 3)
2162 ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2163 else
2164 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2165 }
9d5c8243
AK		 2166
2167 return 0;
2168}
2169
9d5c8243
AK		 2170static int igb_nway_reset(struct net_device *netdev)
2171{
2172 struct igb_adapter *adapter = netdev_priv(netdev);
2173 if (netif_running(netdev))
2174 igb_reinit_locked(adapter);
2175 return 0;
2176}
2177
2178static int igb_get_sset_count(struct net_device *netdev, int sset)
2179{
2180 switch (sset) {
2181 case ETH_SS_STATS:
2182 return IGB_STATS_LEN;
2183 case ETH_SS_TEST:
2184 return IGB_TEST_LEN;
2185 default:
2186 return -ENOTSUPP;
2187 }
2188}
2189
2190static void igb_get_ethtool_stats(struct net_device *netdev,
2191 struct ethtool_stats *stats, u64 *data)
2192{
2193 struct igb_adapter *adapter = netdev_priv(netdev);
12dcd86b
ED		 2194 struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2195 unsigned int start;
2196 struct igb_ring *ring;
2197 int i, j;
128e45eb 2198 char *p;
9d5c8243 2199
12dcd86b
ED		 2200 spin_lock(&adapter->stats64_lock);
2201 igb_update_stats(adapter, net_stats);
317f66bd 2202
9d5c8243 2203 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
128e45eb 2204 p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
9d5c8243
AK		 2205 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2206 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2207 }
128e45eb
AD		 2208 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2209 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2210 data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2211 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2212 }
e21ed353 2213 for (j = 0; j < adapter->num_tx_queues; j++) {
12dcd86b
ED		 2214 u64 restart2;
2215
2216 ring = adapter->tx_ring[j];
2217 do {
2218 start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
2219 data[i] = ring->tx_stats.packets;
2220 data[i+1] = ring->tx_stats.bytes;
2221 data[i+2] = ring->tx_stats.restart_queue;
2222 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
2223 do {
2224 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2);
2225 restart2 = ring->tx_stats.restart_queue2;
2226 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start));
2227 data[i+2] += restart2;
2228
2229 i += IGB_TX_QUEUE_STATS_LEN;
e21ed353 2230 }
9d5c8243 2231 for (j = 0; j < adapter->num_rx_queues; j++) {
12dcd86b
ED		 2232 ring = adapter->rx_ring[j];
2233 do {
2234 start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
2235 data[i] = ring->rx_stats.packets;
2236 data[i+1] = ring->rx_stats.bytes;
2237 data[i+2] = ring->rx_stats.drops;
2238 data[i+3] = ring->rx_stats.csum_err;
2239 data[i+4] = ring->rx_stats.alloc_failed;
2240 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
2241 i += IGB_RX_QUEUE_STATS_LEN;
9d5c8243 2242 }
12dcd86b 2243 spin_unlock(&adapter->stats64_lock);
9d5c8243
AK		 2244}
2245
2246static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2247{
2248 struct igb_adapter *adapter = netdev_priv(netdev);
2249 u8 *p = data;
2250 int i;
2251
2252 switch (stringset) {
2253 case ETH_SS_TEST:
2254 memcpy(data, *igb_gstrings_test,
2255 IGB_TEST_LEN*ETH_GSTRING_LEN);
2256 break;
2257 case ETH_SS_STATS:
2258 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2259 memcpy(p, igb_gstrings_stats[i].stat_string,
2260 ETH_GSTRING_LEN);
2261 p += ETH_GSTRING_LEN;
2262 }
128e45eb
AD		 2263 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2264 memcpy(p, igb_gstrings_net_stats[i].stat_string,
2265 ETH_GSTRING_LEN);
2266 p += ETH_GSTRING_LEN;
2267 }
9d5c8243
AK		 2268 for (i = 0; i < adapter->num_tx_queues; i++) {
2269 sprintf(p, "tx_queue_%u_packets", i);
2270 p += ETH_GSTRING_LEN;
2271 sprintf(p, "tx_queue_%u_bytes", i);
2272 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2273 sprintf(p, "tx_queue_%u_restart", i);
2274 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2275 }
2276 for (i = 0; i < adapter->num_rx_queues; i++) {
2277 sprintf(p, "rx_queue_%u_packets", i);
2278 p += ETH_GSTRING_LEN;
2279 sprintf(p, "rx_queue_%u_bytes", i);
2280 p += ETH_GSTRING_LEN;
8c0ab70a
JDB		 2281 sprintf(p, "rx_queue_%u_drops", i);
2282 p += ETH_GSTRING_LEN;
04a5fcaa
AD		 2283 sprintf(p, "rx_queue_%u_csum_err", i);
2284 p += ETH_GSTRING_LEN;
2285 sprintf(p, "rx_queue_%u_alloc_failed", i);
2286 p += ETH_GSTRING_LEN;
9d5c8243
AK		 2287 }
2288/* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2289 break;
2290 }
2291}
2292
a79f4f88 2293static int igb_get_ts_info(struct net_device *dev,
a9188028 2294 struct ethtool_ts_info *info)
cb41145e
CW		 2295{
2296 struct igb_adapter *adapter = netdev_priv(dev);
2297
a9188028 2298 switch (adapter->hw.mac.type) {
b66e2397
MV		 2299 case e1000_82575:
2300 info->so_timestamping =
2301 SOF_TIMESTAMPING_TX_SOFTWARE |
2302 SOF_TIMESTAMPING_RX_SOFTWARE |
2303 SOF_TIMESTAMPING_SOFTWARE;
2304 return 0;
a9188028
MV		 2305 case e1000_82576:
2306 case e1000_82580:
2307 case e1000_i350:
2308 case e1000_i210:
2309 case e1000_i211:
2310 info->so_timestamping =
b66e2397
MV		 2311 SOF_TIMESTAMPING_TX_SOFTWARE |
2312 SOF_TIMESTAMPING_RX_SOFTWARE |
2313 SOF_TIMESTAMPING_SOFTWARE |
a9188028
MV		 2314 SOF_TIMESTAMPING_TX_HARDWARE |
2315 SOF_TIMESTAMPING_RX_HARDWARE |
2316 SOF_TIMESTAMPING_RAW_HARDWARE;
cb41145e 2317
a9188028
MV		 2318 if (adapter->ptp_clock)
2319 info->phc_index = ptp_clock_index(adapter->ptp_clock);
2320 else
2321 info->phc_index = -1;
cb41145e 2322
a9188028
MV		 2323 info->tx_types =
2324 (1 << HWTSTAMP_TX_OFF) |
2325 (1 << HWTSTAMP_TX_ON);
cb41145e 2326
a9188028 2327 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE;
cb41145e 2328
a9188028
MV		 2329 /* 82576 does not support timestamping all packets. */
2330 if (adapter->hw.mac.type >= e1000_82580)
2331 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL;
2332 else
2333 info->rx_filters |=
2334 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2335 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2336 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
2337 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
2338 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
2339 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
2340 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2341
2342 return 0;
a9188028
MV		 2343 default:
2344 return -EOPNOTSUPP;
2345 }
2346}
cb41145e 2347
039454a8
AA		 2348static int igb_get_rss_hash_opts(struct igb_adapter *adapter,
2349 struct ethtool_rxnfc *cmd)
2350{
2351 cmd->data = 0;
2352
2353 /* Report default options for RSS on igb */
2354 switch (cmd->flow_type) {
2355 case TCP_V4_FLOW:
2356 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2357 case UDP_V4_FLOW:
2358 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2359 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2360 case SCTP_V4_FLOW:
2361 case AH_ESP_V4_FLOW:
2362 case AH_V4_FLOW:
2363 case ESP_V4_FLOW:
2364 case IPV4_FLOW:
2365 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2366 break;
2367 case TCP_V6_FLOW:
2368 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2369 case UDP_V6_FLOW:
2370 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2371 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3;
2372 case SCTP_V6_FLOW:
2373 case AH_ESP_V6_FLOW:
2374 case AH_V6_FLOW:
2375 case ESP_V6_FLOW:
2376 case IPV6_FLOW:
2377 cmd->data |= RXH_IP_SRC | RXH_IP_DST;
2378 break;
2379 default:
2380 return -EINVAL;
2381 }
2382
2383 return 0;
2384}
2385
2386static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2387 u32 *rule_locs)
2388{
2389 struct igb_adapter *adapter = netdev_priv(dev);
2390 int ret = -EOPNOTSUPP;
2391
2392 switch (cmd->cmd) {
2393 case ETHTOOL_GRXRINGS:
2394 cmd->data = adapter->num_rx_queues;
2395 ret = 0;
2396 break;
2397 case ETHTOOL_GRXFH:
2398 ret = igb_get_rss_hash_opts(adapter, cmd);
2399 break;
2400 default:
2401 break;
2402 }
2403
2404 return ret;
2405}
2406
2407#define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \
2408 IGB_FLAG_RSS_FIELD_IPV6_UDP)
2409static int igb_set_rss_hash_opt(struct igb_adapter *adapter,
2410 struct ethtool_rxnfc *nfc)
2411{
2412 u32 flags = adapter->flags;
2413
2414 /* RSS does not support anything other than hashing
2415 * to queues on src and dst IPs and ports
2416 */
2417 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2418 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2419 return -EINVAL;
2420
2421 switch (nfc->flow_type) {
2422 case TCP_V4_FLOW:
2423 case TCP_V6_FLOW:
2424 if (!(nfc->data & RXH_IP_SRC) ||
2425 !(nfc->data & RXH_IP_DST) ||
2426 !(nfc->data & RXH_L4_B_0_1) ||
2427 !(nfc->data & RXH_L4_B_2_3))
2428 return -EINVAL;
2429 break;
2430 case UDP_V4_FLOW:
2431 if (!(nfc->data & RXH_IP_SRC) ||
2432 !(nfc->data & RXH_IP_DST))
2433 return -EINVAL;
2434 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2435 case 0:
2436 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP;
2437 break;
2438 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2439 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP;
2440 break;
2441 default:
2442 return -EINVAL;
2443 }
2444 break;
2445 case UDP_V6_FLOW:
2446 if (!(nfc->data & RXH_IP_SRC) ||
2447 !(nfc->data & RXH_IP_DST))
2448 return -EINVAL;
2449 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
2450 case 0:
2451 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP;
2452 break;
2453 case (RXH_L4_B_0_1 | RXH_L4_B_2_3):
2454 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP;
2455 break;
2456 default:
2457 return -EINVAL;
2458 }
2459 break;
2460 case AH_ESP_V4_FLOW:
2461 case AH_V4_FLOW:
2462 case ESP_V4_FLOW:
2463 case SCTP_V4_FLOW:
2464 case AH_ESP_V6_FLOW:
2465 case AH_V6_FLOW:
2466 case ESP_V6_FLOW:
2467 case SCTP_V6_FLOW:
2468 if (!(nfc->data & RXH_IP_SRC) ||
2469 !(nfc->data & RXH_IP_DST) ||
2470 (nfc->data & RXH_L4_B_0_1) ||
2471 (nfc->data & RXH_L4_B_2_3))
2472 return -EINVAL;
2473 break;
2474 default:
2475 return -EINVAL;
2476 }
2477
2478 /* if we changed something we need to update flags */
2479 if (flags != adapter->flags) {
2480 struct e1000_hw *hw = &adapter->hw;
2481 u32 mrqc = rd32(E1000_MRQC);
2482
2483 if ((flags & UDP_RSS_FLAGS) &&
2484 !(adapter->flags & UDP_RSS_FLAGS))
2485 dev_err(&adapter->pdev->dev,
2486 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n");
2487
2488 adapter->flags = flags;
2489
2490 /* Perform hash on these packet types */
2491 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
2492 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2493 E1000_MRQC_RSS_FIELD_IPV6 |
2494 E1000_MRQC_RSS_FIELD_IPV6_TCP;
2495
2496 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP |
2497 E1000_MRQC_RSS_FIELD_IPV6_UDP);
2498
2499 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP)
2500 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP;
2501
2502 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP)
2503 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP;
2504
2505 wr32(E1000_MRQC, mrqc);
2506 }
2507
2508 return 0;
2509}
2510
2511static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2512{
2513 struct igb_adapter *adapter = netdev_priv(dev);
2514 int ret = -EOPNOTSUPP;
2515
2516 switch (cmd->cmd) {
2517 case ETHTOOL_SRXFH:
2518 ret = igb_set_rss_hash_opt(adapter, cmd);
2519 break;
2520 default:
2521 break;
2522 }
2523
2524 return ret;
2525}
2526
24a372cd
AA		 2527static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata)
2528{
2529 struct igb_adapter *adapter = netdev_priv(netdev);
2530 struct e1000_hw *hw = &adapter->hw;
2531 u32 ipcnfg, eeer;
2532
2533 if ((hw->mac.type < e1000_i350) ||
2534 (hw->phy.media_type != e1000_media_type_copper))
2535 return -EOPNOTSUPP;
2536
2537 edata->supported = (SUPPORTED_1000baseT_Full |
2538 SUPPORTED_100baseT_Full);
2539
2540 ipcnfg = rd32(E1000_IPCNFG);
2541 eeer = rd32(E1000_EEER);
2542
2543 /* EEE status on negotiated link */
2544 if (ipcnfg & E1000_IPCNFG_EEE_1G_AN)
2545 edata->advertised = ADVERTISED_1000baseT_Full;
2546
2547 if (ipcnfg & E1000_IPCNFG_EEE_100M_AN)
2548 edata->advertised |= ADVERTISED_100baseT_Full;
2549
2550 if (eeer & E1000_EEER_EEE_NEG)
2551 edata->eee_active = true;
2552
2553 edata->eee_enabled = !hw->dev_spec._82575.eee_disable;
2554
2555 if (eeer & E1000_EEER_TX_LPI_EN)
2556 edata->tx_lpi_enabled = true;
2557
2558 /* Report correct negotiated EEE status for devices that
2559 * wrongly report EEE at half-duplex
2560 */
2561 if (adapter->link_duplex == HALF_DUPLEX) {
2562 edata->eee_enabled = false;
2563 edata->eee_active = false;
2564 edata->tx_lpi_enabled = false;
2565 edata->advertised &= ~edata->advertised;
2566 }
2567
2568 return 0;
2569}
2570
2571static int igb_set_eee(struct net_device *netdev,
2572 struct ethtool_eee *edata)
2573{
2574 struct igb_adapter *adapter = netdev_priv(netdev);
2575 struct e1000_hw *hw = &adapter->hw;
2576 struct ethtool_eee eee_curr;
2577 s32 ret_val;
2578
2579 if ((hw->mac.type < e1000_i350) ||
2580 (hw->phy.media_type != e1000_media_type_copper))
2581 return -EOPNOTSUPP;
2582
2583 ret_val = igb_get_eee(netdev, &eee_curr);
2584 if (ret_val)
2585 return ret_val;
2586
2587 if (eee_curr.eee_enabled) {
2588 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) {
2589 dev_err(&adapter->pdev->dev,
2590 "Setting EEE tx-lpi is not supported\n");
2591 return -EINVAL;
2592 }
2593
2594 /* Tx LPI timer is not implemented currently */
2595 if (edata->tx_lpi_timer) {
2596 dev_err(&adapter->pdev->dev,
2597 "Setting EEE Tx LPI timer is not supported\n");
2598 return -EINVAL;
2599 }
2600
2601 if (eee_curr.advertised != edata->advertised) {
2602 dev_err(&adapter->pdev->dev,
2603 "Setting EEE Advertisement is not supported\n");
2604 return -EINVAL;
2605 }
2606
2607 } else if (!edata->eee_enabled) {
2608 dev_err(&adapter->pdev->dev,
2609 "Setting EEE options are not supported with EEE disabled\n");
2610 return -EINVAL;
2611 }
2612
2613 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
2614 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
2615 igb_set_eee_i350(hw);
2616
2617 /* reset link */
2618 if (!netif_running(netdev))
2619 igb_reset(adapter);
2620 }
2621
2622 return 0;
2623}
2624
f69aa390
AA		 2625static int igb_get_module_info(struct net_device *netdev,
2626 struct ethtool_modinfo *modinfo)
2627{
2628 struct igb_adapter *adapter = netdev_priv(netdev);
2629 struct e1000_hw *hw = &adapter->hw;
2630 u32 status = E1000_SUCCESS;
2631 u16 sff8472_rev, addr_mode;
2632 bool page_swap = false;
2633
2634 if ((hw->phy.media_type == e1000_media_type_copper) ||
2635 (hw->phy.media_type == e1000_media_type_unknown))
2636 return -EOPNOTSUPP;
2637
2638 /* Check whether we support SFF-8472 or not */
2639 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_COMP, &sff8472_rev);
2640 if (status != E1000_SUCCESS)
2641 return -EIO;
2642
2643 /* addressing mode is not supported */
2644 status = igb_read_phy_reg_i2c(hw, IGB_SFF_8472_SWAP, &addr_mode);
2645 if (status != E1000_SUCCESS)
2646 return -EIO;
2647
2648 /* addressing mode is not supported */
2649 if ((addr_mode & 0xFF) & IGB_SFF_ADDRESSING_MODE) {
2650 hw_dbg("Address change required to access page 0xA2, but not supported. Please report the module type to the driver maintainers.\n");
2651 page_swap = true;
2652 }
2653
2654 if ((sff8472_rev & 0xFF) == IGB_SFF_8472_UNSUP || page_swap) {
2655 /* We have an SFP, but it does not support SFF-8472 */
2656 modinfo->type = ETH_MODULE_SFF_8079;
2657 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
2658 } else {
2659 /* We have an SFP which supports a revision of SFF-8472 */
2660 modinfo->type = ETH_MODULE_SFF_8472;
2661 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
2662 }
2663
2664 return 0;
2665}
2666
2667static int igb_get_module_eeprom(struct net_device *netdev,
2668 struct ethtool_eeprom *ee, u8 *data)
2669{
2670 struct igb_adapter *adapter = netdev_priv(netdev);
2671 struct e1000_hw *hw = &adapter->hw;
2672 u32 status = E1000_SUCCESS;
2673 u16 *dataword;
2674 u16 first_word, last_word;
2675 int i = 0;
2676
2677 if (ee->len == 0)
2678 return -EINVAL;
2679
2680 first_word = ee->offset >> 1;
2681 last_word = (ee->offset + ee->len - 1) >> 1;
2682
2683 dataword = kmalloc(sizeof(u16) * (last_word - first_word + 1),
2684 GFP_KERNEL);
2685 if (!dataword)
2686 return -ENOMEM;
2687
2688 /* Read EEPROM block, SFF-8079/SFF-8472, word at a time */
2689 for (i = 0; i < last_word - first_word + 1; i++) {
2690 status = igb_read_phy_reg_i2c(hw, first_word + i, &dataword[i]);
2691 if (status != E1000_SUCCESS)
2692 /* Error occurred while reading module */
2693 return -EIO;
2694
2695 be16_to_cpus(&dataword[i]);
2696 }
2697
2698 memcpy(data, (u8 *)dataword + (ee->offset & 1), ee->len);
2699 kfree(dataword);
2700
2701 return 0;
2702}
2703
a79f4f88
MV		 2704static int igb_ethtool_begin(struct net_device *netdev)
2705{
2706 struct igb_adapter *adapter = netdev_priv(netdev);
2707 pm_runtime_get_sync(&adapter->pdev->dev);
2708 return 0;
2709}
2710
2711static void igb_ethtool_complete(struct net_device *netdev)
2712{
2713 struct igb_adapter *adapter = netdev_priv(netdev);
2714 pm_runtime_put(&adapter->pdev->dev);
2715}
2716
0fc0b732 2717static const struct ethtool_ops igb_ethtool_ops = {
9d5c8243
AK		 2718 .get_settings = igb_get_settings,
2719 .set_settings = igb_set_settings,
2720 .get_drvinfo = igb_get_drvinfo,
2721 .get_regs_len = igb_get_regs_len,
2722 .get_regs = igb_get_regs,
2723 .get_wol = igb_get_wol,
2724 .set_wol = igb_set_wol,
2725 .get_msglevel = igb_get_msglevel,
2726 .set_msglevel = igb_set_msglevel,
2727 .nway_reset = igb_nway_reset,
3145535a 2728 .get_link = igb_get_link,
9d5c8243
AK		 2729 .get_eeprom_len = igb_get_eeprom_len,
2730 .get_eeprom = igb_get_eeprom,
2731 .set_eeprom = igb_set_eeprom,
2732 .get_ringparam = igb_get_ringparam,
2733 .set_ringparam = igb_set_ringparam,
2734 .get_pauseparam = igb_get_pauseparam,
2735 .set_pauseparam = igb_set_pauseparam,
9d5c8243
AK		 2736 .self_test = igb_diag_test,
2737 .get_strings = igb_get_strings,
936db355 2738 .set_phys_id = igb_set_phys_id,
9d5c8243
AK		 2739 .get_sset_count = igb_get_sset_count,
2740 .get_ethtool_stats = igb_get_ethtool_stats,
2741 .get_coalesce = igb_get_coalesce,
2742 .set_coalesce = igb_set_coalesce,
a79f4f88 2743 .get_ts_info = igb_get_ts_info,
039454a8
AA		 2744 .get_rxnfc = igb_get_rxnfc,
2745 .set_rxnfc = igb_set_rxnfc,
24a372cd
AA		 2746 .get_eee = igb_get_eee,
2747 .set_eee = igb_set_eee,
f69aa390
AA		 2748 .get_module_info = igb_get_module_info,
2749 .get_module_eeprom = igb_get_module_eeprom,
a79f4f88
MV		 2750 .begin = igb_ethtool_begin,
2751 .complete = igb_ethtool_complete,
9d5c8243
AK		 2752};
2753
2754void igb_set_ethtool_ops(struct net_device *netdev)
2755{
2756 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2757}
Linux 6.x block layer and io_uring tree(s)