[linux-2.6-block.git] / drivers / net / ethernet / intel / igb / e1000_82575.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright(c) 2007 - 2018 Intel Corporation. */

#ifndef _E1000_82575_H_
#define _E1000_82575_H_

void igb_shutdown_serdes_link_82575(struct e1000_hw *hw);
void igb_power_up_serdes_link_82575(struct e1000_hw *hw);
void igb_power_down_phy_copper_82575(struct e1000_hw *hw);
void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
		      u8 *data);
s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
		       u8 data);

#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
				     (ID_LED_DEF1_DEF2 <<  8) | \
				     (ID_LED_DEF1_DEF2 <<  4) | \
				     (ID_LED_OFF1_ON2))

#define E1000_RAR_ENTRIES_82575        16
#define E1000_RAR_ENTRIES_82576        24
#define E1000_RAR_ENTRIES_82580        24
#define E1000_RAR_ENTRIES_I350         32

#define E1000_SW_SYNCH_MB              0x00000100
#define E1000_STAT_DEV_RST_SET         0x00100000
#define E1000_CTRL_DEV_RST             0x20000000

/* SRRCTL bit definitions */
#define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
#define E1000_SRRCTL_DROP_EN                            0x80000000
#define E1000_SRRCTL_TIMESTAMP                          0x40000000


#define E1000_MRQC_ENABLE_RSS_MQ            0x00000002
#define E1000_MRQC_ENABLE_VMDQ              0x00000003
#define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000
#define E1000_MRQC_ENABLE_VMDQ_RSS_MQ       0x00000005
#define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000
#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000

#define E1000_EICR_TX_QUEUE ( \
	E1000_EICR_TX_QUEUE0 |    \
	E1000_EICR_TX_QUEUE1 |    \
	E1000_EICR_TX_QUEUE2 |    \
	E1000_EICR_TX_QUEUE3)

#define E1000_EICR_RX_QUEUE ( \
	E1000_EICR_RX_QUEUE0 |    \
	E1000_EICR_RX_QUEUE1 |    \
	E1000_EICR_RX_QUEUE2 |    \
	E1000_EICR_RX_QUEUE3)

/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
#define E1000_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
#define E1000_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of ctrl bits */

/* Receive Descriptor - Advanced */
union e1000_adv_rx_desc {
	struct {
		__le64 pkt_addr;             /* Packet buffer address */
		__le64 hdr_addr;             /* Header buffer address */
	} read;
	struct {
		struct {
			struct {
				__le16 pkt_info;   /* RSS type, Packet type */
				__le16 hdr_info;   /* Split Head, buf len */
			} lo_dword;
			union {
				__le32 rss;          /* RSS Hash */
				struct {
					__le16 ip_id;    /* IP id */
					__le16 csum;     /* Packet Checksum */
				} csum_ip;
			} hi_dword;
		} lower;
		struct {
			__le32 status_error;     /* ext status/error */
			__le16 length;           /* Packet length */
			__le16 vlan;             /* VLAN tag */
		} upper;
	} wb;  /* writeback */
};

#define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
#define E1000_RXDADV_HDRBUFLEN_SHIFT     5
#define E1000_RXDADV_STAT_TS             0x10000 /* Pkt was time stamped */
#define E1000_RXDADV_STAT_TSIP           0x08000 /* timestamp in packet */

/* Transmit Descriptor - Advanced */
union e1000_adv_tx_desc {
	struct {
		__le64 buffer_addr;    /* Address of descriptor's data buf */
		__le32 cmd_type_len;
		__le32 olinfo_status;
	} read;
	struct {
		__le64 rsvd;       /* Reserved */
		__le32 nxtseq_seed;
		__le32 status;
	} wb;
};

/* Adv Transmit Descriptor Config Masks */
#define E1000_ADVTXD_MAC_TSTAMP   0x00080000 /* IEEE1588 Timestamp packet */
#define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
#define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
#define E1000_ADVTXD_DCMD_EOP     0x01000000 /* End of Packet */
#define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
#define E1000_ADVTXD_DCMD_RS      0x08000000 /* Report Status */
#define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
#define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
#define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
#define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */

/* Context descriptors */
struct e1000_adv_tx_context_desc {
	__le32 vlan_macip_lens;
	__le32 seqnum_seed;
	__le32 type_tucmd_mlhl;
	__le32 mss_l4len_idx;
};

#define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000  /* L4 Packet TYPE of UDP */
#define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
/* IPSec Encrypt Enable for ESP */
#define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
#define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
/* Adv ctxt IPSec SA IDX mask */
/* Adv ctxt IPSec ESP len mask */

/* Additional Transmit Descriptor Control definitions */
#define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
/* Tx Queue Arbitration Priority 0=low, 1=high */

/* Additional Receive Descriptor Control definitions */
#define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */

/* Direct Cache Access (DCA) definitions */
#define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
#define E1000_DCA_CTRL_DCA_MODE_CB2     0x02 /* DCA Mode CB2 */

#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
#define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
#define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
#define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
#define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */

#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
#define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
#define E1000_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
#define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
#define E1000_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */

/* Additional DCA related definitions, note change in position of CPUID */
#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */

/* ETQF register bit definitions */
#define E1000_ETQF_FILTER_ENABLE   BIT(26)
#define E1000_ETQF_1588            BIT(30)
#define E1000_ETQF_IMM_INT         BIT(29)
#define E1000_ETQF_QUEUE_ENABLE    BIT(31)
#define E1000_ETQF_QUEUE_SHIFT     16
#define E1000_ETQF_QUEUE_MASK      0x00070000
#define E1000_ETQF_ETYPE_MASK      0x0000FFFF

/* FTQF register bit definitions */
#define E1000_FTQF_VF_BP               0x00008000
#define E1000_FTQF_1588_TIME_STAMP     0x08000000
#define E1000_FTQF_MASK                0xF0000000
#define E1000_FTQF_MASK_PROTO_BP       0x10000000
#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000

#define E1000_NVM_APME_82575          0x0400
#define MAX_NUM_VFS                   8

#define E1000_DTXSWC_MAC_SPOOF_MASK   0x000000FF /* Per VF MAC spoof control */
#define E1000_DTXSWC_VLAN_SPOOF_MASK  0x0000FF00 /* Per VF VLAN spoof control */
#define E1000_DTXSWC_LLE_MASK         0x00FF0000 /* Per VF Local LB enables */
#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
#define E1000_DTXSWC_VMDQ_LOOPBACK_EN BIT(31)  /* global VF LB enable */

/* Easy defines for setting default pool, would normally be left a zero */
#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
#define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)

/* Other useful VMD_CTL register defines */
#define E1000_VT_CTL_IGNORE_MAC         BIT(28)
#define E1000_VT_CTL_DISABLE_DEF_POOL   BIT(29)
#define E1000_VT_CTL_VM_REPL_EN         BIT(30)

/* Per VM Offload register setup */
#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
#define E1000_VMOLR_LPE        0x00010000 /* Accept Long packet */
#define E1000_VMOLR_RSSE       0x00020000 /* Enable RSS */
#define E1000_VMOLR_AUPE       0x01000000 /* Accept untagged packets */
#define E1000_VMOLR_ROMPE      0x02000000 /* Accept overflow multicast */
#define E1000_VMOLR_ROPE       0x04000000 /* Accept overflow unicast */
#define E1000_VMOLR_BAM        0x08000000 /* Accept Broadcast packets */
#define E1000_VMOLR_MPME       0x10000000 /* Multicast promiscuous mode */
#define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
#define E1000_VMOLR_STRCRC     0x80000000 /* CRC stripping enable */

#define E1000_DVMOLR_HIDEVLAN  0x20000000 /* Hide vlan enable */
#define E1000_DVMOLR_STRVLAN   0x40000000 /* Vlan stripping enable */
#define E1000_DVMOLR_STRCRC    0x80000000 /* CRC stripping enable */

#define E1000_VLVF_ARRAY_SIZE     32
#define E1000_VLVF_VLANID_MASK    0x00000FFF
#define E1000_VLVF_POOLSEL_SHIFT  12
#define E1000_VLVF_POOLSEL_MASK   (0xFF << E1000_VLVF_POOLSEL_SHIFT)
#define E1000_VLVF_LVLAN          0x00100000
#define E1000_VLVF_VLANID_ENABLE  0x80000000

#define E1000_VMVIR_VLANA_DEFAULT      0x40000000 /* Always use default VLAN */
#define E1000_VMVIR_VLANA_NEVER        0x80000000 /* Never insert VLAN tag */

#define E1000_IOVCTL 0x05BBC
#define E1000_IOVCTL_REUSE_VFQ 0x00000001

#define E1000_RPLOLR_STRVLAN   0x40000000
#define E1000_RPLOLR_STRCRC    0x80000000

#define E1000_DTXCTL_8023LL     0x0004
#define E1000_DTXCTL_VLAN_ADDED 0x0008
#define E1000_DTXCTL_OOS_ENABLE 0x0010
#define E1000_DTXCTL_MDP_EN     0x0020
#define E1000_DTXCTL_SPOOF_INT  0x0040

#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT	BIT(14)

#define ALL_QUEUES   0xFFFF

/* RX packet buffer size defines */
#define E1000_RXPBS_SIZE_MASK_82576  0x0000007F
void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
u16 igb_rxpbs_adjust_82580(u32 data);
s32 igb_read_emi_reg(struct e1000_hw *, u16 addr, u16 *data);
s32 igb_set_eee_i350(struct e1000_hw *, bool adv1G, bool adv100M);
s32 igb_set_eee_i354(struct e1000_hw *, bool adv1G, bool adv100M);
s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status);

#define E1000_I2C_THERMAL_SENSOR_ADDR	0xF8
#define E1000_EMC_INTERNAL_DATA		0x00
#define E1000_EMC_INTERNAL_THERM_LIMIT	0x20
#define E1000_EMC_DIODE1_DATA		0x01
#define E1000_EMC_DIODE1_THERM_LIMIT	0x19
#define E1000_EMC_DIODE2_DATA		0x23
#define E1000_EMC_DIODE2_THERM_LIMIT	0x1A
#define E1000_EMC_DIODE3_DATA		0x2A
#define E1000_EMC_DIODE3_THERM_LIMIT	0x30
#endif
Commit	Line	Data
ae06c70b	1	/* SPDX-License-Identifier: GPL-2.0 */
51dce24b	2	/* Copyright(c) 2007 - 2018 Intel Corporation. */
9d5c8243 AK	3
	4	#ifndef _E1000_82575_H_
	5	#define _E1000_82575_H_
	6
5ccc921a JP	7	void igb_shutdown_serdes_link_82575(struct e1000_hw *hw);
	8	void igb_power_up_serdes_link_82575(struct e1000_hw *hw);
	9	void igb_power_down_phy_copper_82575(struct e1000_hw *hw);
	10	void igb_rx_fifo_flush_82575(struct e1000_hw *hw);
	11	s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
	12	u8 *data);
	13	s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, u8 dev_addr,
	14	u8 data);
662d7205	15
099e1cb7	16	#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) \| \
9005df38 CW	17	(ID_LED_DEF1_DEF2 << 8) \| \
	18	(ID_LED_DEF1_DEF2 << 4) \| \
	19	(ID_LED_OFF1_ON2))
099e1cb7	20
d2ba2ed8 AD	21	#define E1000_RAR_ENTRIES_82575 16
	22	#define E1000_RAR_ENTRIES_82576 24
	23	#define E1000_RAR_ENTRIES_82580 24
	24	#define E1000_RAR_ENTRIES_I350 32
bb2ac47b AD	25
	26	#define E1000_SW_SYNCH_MB 0x00000100
	27	#define E1000_STAT_DEV_RST_SET 0x00100000
	28	#define E1000_CTRL_DEV_RST 0x20000000
9d5c8243 AK	29
	30	/* SRRCTL bit definitions */
	31	#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
	32	#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
	33	#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
	34	#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
e1739522	35	#define E1000_SRRCTL_DROP_EN 0x80000000
757b77e2	36	#define E1000_SRRCTL_TIMESTAMP 0x40000000
9d5c8243	37
f96a8a0b	38
c883de9f	39	#define E1000_MRQC_ENABLE_RSS_MQ 0x00000002
e1739522	40	#define E1000_MRQC_ENABLE_VMDQ 0x00000003
9d5c8243	41	#define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
c883de9f	42	#define E1000_MRQC_ENABLE_VMDQ_RSS_MQ 0x00000005
9d5c8243 AK	43	#define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
	44	#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000
	45
	46	#define E1000_EICR_TX_QUEUE ( \
9005df38 CW	47	E1000_EICR_TX_QUEUE0 \| \
	48	E1000_EICR_TX_QUEUE1 \| \
	49	E1000_EICR_TX_QUEUE2 \| \
	50	E1000_EICR_TX_QUEUE3)
9d5c8243 AK	51
9d5c8243 AK	52	#define E1000_EICR_RX_QUEUE ( \
9005df38 CW	53	E1000_EICR_RX_QUEUE0 \| \
	54	E1000_EICR_RX_QUEUE1 \| \
	55	E1000_EICR_RX_QUEUE2 \| \
	56	E1000_EICR_RX_QUEUE3)
9d5c8243	57
652fff32	58	/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
c5b9bd5e AD	59	#define E1000_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
c5b9bd5e AD	60	#define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */
9d5c8243 AK	61
	62	/* Receive Descriptor - Advanced */
	63	union e1000_adv_rx_desc {
	64	struct {
6d8126f9 AV	65	__le64 pkt_addr; /* Packet buffer address */
6d8126f9 AV	66	__le64 hdr_addr; /* Header buffer address */
9d5c8243 AK	67	} read;
	68	struct {
	69	struct {
	70	struct {
6d8126f9	71	__le16 pkt_info; /* RSS type, Packet type */
e52c0f96	72	__le16 hdr_info; /* Split Head, buf len */
9d5c8243 AK	73	} lo_dword;
9d5c8243 AK	74	union {
6d8126f9	75	__le32 rss; /* RSS Hash */
9d5c8243	76	struct {
6d8126f9 AV	77	__le16 ip_id; /* IP id */
6d8126f9 AV	78	__le16 csum; /* Packet Checksum */
9d5c8243 AK	79	} csum_ip;
	80	} hi_dword;
	81	} lower;
	82	struct {
6d8126f9 AV	83	__le32 status_error; /* ext status/error */
	84	__le16 length; /* Packet length */
	85	__le16 vlan; /* VLAN tag */
9d5c8243 AK	86	} upper;
	87	} wb; /* writeback */
	88	};
	89
	90	#define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
	91	#define E1000_RXDADV_HDRBUFLEN_SHIFT 5
c5b9bd5e	92	#define E1000_RXDADV_STAT_TS 0x10000 /* Pkt was time stamped */
757b77e2	93	#define E1000_RXDADV_STAT_TSIP 0x08000 /* timestamp in packet */
9d5c8243	94
9d5c8243 AK	95	/* Transmit Descriptor - Advanced */
	96	union e1000_adv_tx_desc {
	97	struct {
6d8126f9 AV	98	__le64 buffer_addr; /* Address of descriptor's data buf */
	99	__le32 cmd_type_len;
	100	__le32 olinfo_status;
9d5c8243 AK	101	} read;
9d5c8243 AK	102	struct {
6d8126f9 AV	103	__le64 rsvd; /* Reserved */
	104	__le32 nxtseq_seed;
	105	__le32 status;
9d5c8243 AK	106	} wb;
	107	};
	108
	109	/* Adv Transmit Descriptor Config Masks */
33af6bcc	110	#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp packet */
9d5c8243 AK	111	#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
9d5c8243 AK	112	#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
e032afc8	113	#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
9d5c8243	114	#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
e032afc8	115	#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
9d5c8243 AK	116	#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
	117	#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
	118	#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
	119	#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
	120
	121	/* Context descriptors */
	122	struct e1000_adv_tx_context_desc {
6d8126f9 AV	123	__le32 vlan_macip_lens;
	124	__le32 seqnum_seed;
	125	__le32 type_tucmd_mlhl;
	126	__le32 mss_l4len_idx;
9d5c8243 AK	127	};
	128
	129	#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
4085d06d	130	#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
9d5c8243 AK	131	#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
9d5c8243 AK	132	#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
b9473560	133	#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
9d5c8243 AK	134	/* IPSec Encrypt Enable for ESP */
	135	#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
	136	#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
	137	/* Adv ctxt IPSec SA IDX mask */
	138	/* Adv ctxt IPSec ESP len mask */
	139
	140	/* Additional Transmit Descriptor Control definitions */
	141	#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
	142	/* Tx Queue Arbitration Priority 0=low, 1=high */
	143
	144	/* Additional Receive Descriptor Control definitions */
	145	#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
	146
	147	/* Direct Cache Access (DCA) definitions */
cbd347ad AD	148	#define E1000_DCA_CTRL_DCA_MODE_DISABLE 0x01 /* DCA Disable */
cbd347ad AD	149	#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
9d5c8243	150
fe4506b6	151	#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
a51d8c21 JK	152	#define E1000_DCA_RXCTRL_DESC_DCA_EN BIT(5) /* DCA Rx Desc enable */
	153	#define E1000_DCA_RXCTRL_HEAD_DCA_EN BIT(6) /* DCA Rx Desc header enable */
	154	#define E1000_DCA_RXCTRL_DATA_DCA_EN BIT(7) /* DCA Rx Desc payload enable */
	155	#define E1000_DCA_RXCTRL_DESC_RRO_EN BIT(9) /* DCA Rx rd Desc Relax Order */
9d5c8243	156
fe4506b6	157	#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
a51d8c21 JK	158	#define E1000_DCA_TXCTRL_DESC_DCA_EN BIT(5) /* DCA Tx Desc enable */
	159	#define E1000_DCA_TXCTRL_DESC_RRO_EN BIT(9) /* Tx rd Desc Relax Order */
	160	#define E1000_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
	161	#define E1000_DCA_TXCTRL_DATA_RRO_EN BIT(13) /* Tx rd data Relax Order */
9d5c8243	162
2d064c06 AD	163	/* Additional DCA related definitions, note change in position of CPUID */
	164	#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
	165	#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
	166	#define E1000_DCA_TXCTRL_CPUID_SHIFT 24 /* Tx CPUID now in the last byte */
	167	#define E1000_DCA_RXCTRL_CPUID_SHIFT 24 /* Rx CPUID now in the last byte */
fe4506b6	168
c5b9bd5e	169	/* ETQF register bit definitions */
a51d8c21 JK	170	#define E1000_ETQF_FILTER_ENABLE BIT(26)
a51d8c21 JK	171	#define E1000_ETQF_1588 BIT(30)
64c75d41 GH	172	#define E1000_ETQF_IMM_INT BIT(29)
	173	#define E1000_ETQF_QUEUE_ENABLE BIT(31)
	174	#define E1000_ETQF_QUEUE_SHIFT 16
	175	#define E1000_ETQF_QUEUE_MASK 0x00070000
	176	#define E1000_ETQF_ETYPE_MASK 0x0000FFFF
c5b9bd5e AD	177
	178	/* FTQF register bit definitions */
	179	#define E1000_FTQF_VF_BP 0x00008000
	180	#define E1000_FTQF_1588_TIME_STAMP 0x08000000
	181	#define E1000_FTQF_MASK 0xF0000000
	182	#define E1000_FTQF_MASK_PROTO_BP 0x10000000
	183	#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
	184
70d92f86	185	#define E1000_NVM_APME_82575 0x0400
4ae196df AD	186	#define MAX_NUM_VFS 8
4ae196df AD	187
13800469 GR	188	#define E1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF /* Per VF MAC spoof control */
	189	#define E1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 /* Per VF VLAN spoof control */
	190	#define E1000_DTXSWC_LLE_MASK 0x00FF0000 /* Per VF Local LB enables */
	191	#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
a51d8c21	192	#define E1000_DTXSWC_VMDQ_LOOPBACK_EN BIT(31) /* global VF LB enable */
4ae196df	193
e1739522 AD	194	/* Easy defines for setting default pool, would normally be left a zero */
	195	#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
	196	#define E1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
	197
	198	/* Other useful VMD_CTL register defines */
a51d8c21 JK	199	#define E1000_VT_CTL_IGNORE_MAC BIT(28)
	200	#define E1000_VT_CTL_DISABLE_DEF_POOL BIT(29)
	201	#define E1000_VT_CTL_VM_REPL_EN BIT(30)
e1739522 AD	202
	203	/* Per VM Offload register setup */
	204	#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
	205	#define E1000_VMOLR_LPE 0x00010000 /* Accept Long packet */
	206	#define E1000_VMOLR_RSSE 0x00020000 /* Enable RSS */
	207	#define E1000_VMOLR_AUPE 0x01000000 /* Accept untagged packets */
	208	#define E1000_VMOLR_ROMPE 0x02000000 /* Accept overflow multicast */
	209	#define E1000_VMOLR_ROPE 0x04000000 /* Accept overflow unicast */
	210	#define E1000_VMOLR_BAM 0x08000000 /* Accept Broadcast packets */
	211	#define E1000_VMOLR_MPME 0x10000000 /* Multicast promiscuous mode */
	212	#define E1000_VMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
4ae196df AD	213	#define E1000_VMOLR_STRCRC 0x80000000 /* CRC stripping enable */
4ae196df AD	214
dc1edc67 SA	215	#define E1000_DVMOLR_HIDEVLAN 0x20000000 /* Hide vlan enable */
	216	#define E1000_DVMOLR_STRVLAN 0x40000000 /* Vlan stripping enable */
	217	#define E1000_DVMOLR_STRCRC 0x80000000 /* CRC stripping enable */
	218
4ae196df AD	219	#define E1000_VLVF_ARRAY_SIZE 32
	220	#define E1000_VLVF_VLANID_MASK 0x00000FFF
	221	#define E1000_VLVF_POOLSEL_SHIFT 12
	222	#define E1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT)
	223	#define E1000_VLVF_LVLAN 0x00100000
	224	#define E1000_VLVF_VLANID_ENABLE 0x80000000
	225
8151d294 WM	226	#define E1000_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
	227	#define E1000_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */
	228
4ae196df AD	229	#define E1000_IOVCTL 0x05BBC
4ae196df AD	230	#define E1000_IOVCTL_REUSE_VFQ 0x00000001
e1739522	231
10d8e907 AD	232	#define E1000_RPLOLR_STRVLAN 0x40000000
	233	#define E1000_RPLOLR_STRCRC 0x80000000
	234
	235	#define E1000_DTXCTL_8023LL 0x0004
	236	#define E1000_DTXCTL_VLAN_ADDED 0x0008
	237	#define E1000_DTXCTL_OOS_ENABLE 0x0010
	238	#define E1000_DTXCTL_MDP_EN 0x0020
	239	#define E1000_DTXCTL_SPOOF_INT 0x0040
	240
a51d8c21	241	#define E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT BIT(14)
2c670b5b	242
e1739522 AD	243	#define ALL_QUEUES 0xFFFF
e1739522 AD	244
d249be54 AD	245	/* RX packet buffer size defines */
d249be54 AD	246	#define E1000_RXPBS_SIZE_MASK_82576 0x0000007F
13800469	247	void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *, bool, int);
4ae196df AD	248	void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
4ae196df AD	249	void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
bb2ac47b	250	u16 igb_rxpbs_adjust_82580(u32 data);
87371b9d	251	s32 igb_read_emi_reg(struct e1000_hw , u16 addr, u16 data);
c4c112f1 TF	252	s32 igb_set_eee_i350(struct e1000_hw *, bool adv1G, bool adv100M);
c4c112f1 TF	253	s32 igb_set_eee_i354(struct e1000_hw *, bool adv1G, bool adv100M);
f4c01e96	254	s32 igb_get_eee_status_i354(struct e1000_hw hw, bool status);
e1739522	255
441fc6fd	256	#define E1000_I2C_THERMAL_SENSOR_ADDR 0xF8
aca5dae8 CW	257	#define E1000_EMC_INTERNAL_DATA 0x00
	258	#define E1000_EMC_INTERNAL_THERM_LIMIT 0x20
	259	#define E1000_EMC_DIODE1_DATA 0x01
	260	#define E1000_EMC_DIODE1_THERM_LIMIT 0x19
	261	#define E1000_EMC_DIODE2_DATA 0x23
	262	#define E1000_EMC_DIODE2_THERM_LIMIT 0x1A
	263	#define E1000_EMC_DIODE3_DATA 0x2A
	264	#define E1000_EMC_DIODE3_THERM_LIMIT 0x30
9d5c8243	265	#endif