Commit | Line | Data |
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837f08fd AV |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (c) 2018, Intel Corporation. */ | |
3 | ||
4 | #ifndef _ICE_TYPE_H_ | |
5 | #define _ICE_TYPE_H_ | |
6 | ||
6a025730 TN |
7 | #define ICE_BYTES_PER_WORD 2 |
8 | #define ICE_BYTES_PER_DWORD 4 | |
9 | ||
7ec59eea AV |
10 | #include "ice_status.h" |
11 | #include "ice_hw_autogen.h" | |
12 | #include "ice_osdep.h" | |
13 | #include "ice_controlq.h" | |
cdedef59 | 14 | #include "ice_lan_tx_rx.h" |
c7648810 | 15 | #include "ice_flex_type.h" |
31ad4e4e | 16 | #include "ice_protocol_type.h" |
7ec59eea | 17 | |
35b4f437 | 18 | static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc) |
5513b920 | 19 | { |
35b4f437 | 20 | return test_bit(tc, &bitmap); |
5513b920 AV |
21 | } |
22 | ||
1ddef455 UK |
23 | static inline u64 round_up_64bit(u64 a, u32 b) |
24 | { | |
25 | return div64_long(((a) + (b) / 2), (b)); | |
26 | } | |
27 | ||
28 | static inline u32 ice_round_to_num(u32 N, u32 R) | |
29 | { | |
30 | return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) : | |
31 | ((((N) + (R) - 1) / (R)) * (R))); | |
32 | } | |
33 | ||
334cb062 AV |
34 | /* Driver always calls main vsi_handle first */ |
35 | #define ICE_MAIN_VSI_HANDLE 0 | |
36 | ||
7ec59eea | 37 | /* debug masks - set these bits in hw->debug_mask to control output */ |
f31e4b6f | 38 | #define ICE_DBG_INIT BIT_ULL(1) |
4f70daa0 | 39 | #define ICE_DBG_FW_LOG BIT_ULL(3) |
0b28b702 | 40 | #define ICE_DBG_LINK BIT_ULL(4) |
d8df260a | 41 | #define ICE_DBG_PHY BIT_ULL(5) |
cdedef59 | 42 | #define ICE_DBG_QCTX BIT_ULL(6) |
f31e4b6f | 43 | #define ICE_DBG_NVM BIT_ULL(7) |
dc49c772 | 44 | #define ICE_DBG_LAN BIT_ULL(8) |
31ad4e4e | 45 | #define ICE_DBG_FLOW BIT_ULL(9) |
9c20346b AV |
46 | #define ICE_DBG_SW BIT_ULL(13) |
47 | #define ICE_DBG_SCHED BIT_ULL(14) | |
c7648810 | 48 | #define ICE_DBG_PKG BIT_ULL(16) |
f31e4b6f | 49 | #define ICE_DBG_RES BIT_ULL(17) |
7ec59eea | 50 | #define ICE_DBG_AQ_MSG BIT_ULL(24) |
faa01721 JK |
51 | #define ICE_DBG_AQ_DESC BIT_ULL(25) |
52 | #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26) | |
7ec59eea | 53 | #define ICE_DBG_AQ_CMD BIT_ULL(27) |
fcea6f3d | 54 | #define ICE_DBG_USER BIT_ULL(31) |
7ec59eea | 55 | |
f31e4b6f AV |
56 | enum ice_aq_res_ids { |
57 | ICE_NVM_RES_ID = 1, | |
58 | ICE_SPD_RES_ID, | |
ff2b1321 DN |
59 | ICE_CHANGE_LOCK_RES_ID, |
60 | ICE_GLOBAL_CFG_LOCK_RES_ID | |
f31e4b6f AV |
61 | }; |
62 | ||
ff2b1321 DN |
63 | /* FW update timeout definitions are in milliseconds */ |
64 | #define ICE_NVM_TIMEOUT 180000 | |
65 | #define ICE_CHANGE_LOCK_TIMEOUT 1000 | |
66 | #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 3000 | |
67 | ||
f31e4b6f AV |
68 | enum ice_aq_res_access_type { |
69 | ICE_RES_READ = 1, | |
70 | ICE_RES_WRITE | |
71 | }; | |
72 | ||
e3710a01 PSJ |
73 | struct ice_driver_ver { |
74 | u8 major_ver; | |
75 | u8 minor_ver; | |
76 | u8 build_ver; | |
77 | u8 subbuild_ver; | |
78 | u8 driver_string[32]; | |
79 | }; | |
80 | ||
dc49c772 AV |
81 | enum ice_fc_mode { |
82 | ICE_FC_NONE = 0, | |
83 | ICE_FC_RX_PAUSE, | |
84 | ICE_FC_TX_PAUSE, | |
85 | ICE_FC_FULL, | |
86 | ICE_FC_PFC, | |
87 | ICE_FC_DFLT | |
88 | }; | |
89 | ||
f776b3ac PG |
90 | enum ice_fec_mode { |
91 | ICE_FEC_NONE = 0, | |
92 | ICE_FEC_RS, | |
93 | ICE_FEC_BASER, | |
94 | ICE_FEC_AUTO | |
95 | }; | |
96 | ||
fcea6f3d AV |
97 | enum ice_set_fc_aq_failures { |
98 | ICE_SET_FC_AQ_FAIL_NONE = 0, | |
99 | ICE_SET_FC_AQ_FAIL_GET, | |
100 | ICE_SET_FC_AQ_FAIL_SET, | |
101 | ICE_SET_FC_AQ_FAIL_UPDATE | |
102 | }; | |
103 | ||
f31e4b6f AV |
104 | /* Various MAC types */ |
105 | enum ice_mac_type { | |
106 | ICE_MAC_UNKNOWN = 0, | |
107 | ICE_MAC_GENERIC, | |
108 | }; | |
109 | ||
dc49c772 AV |
110 | /* Media Types */ |
111 | enum ice_media_type { | |
112 | ICE_MEDIA_UNKNOWN = 0, | |
113 | ICE_MEDIA_FIBER, | |
114 | ICE_MEDIA_BASET, | |
115 | ICE_MEDIA_BACKPLANE, | |
116 | ICE_MEDIA_DA, | |
117 | }; | |
118 | ||
3a858ba3 AV |
119 | enum ice_vsi_type { |
120 | ICE_VSI_PF = 0, | |
75d2b253 | 121 | ICE_VSI_VF, |
0e674aeb | 122 | ICE_VSI_LB = 6, |
3a858ba3 AV |
123 | }; |
124 | ||
dc49c772 AV |
125 | struct ice_link_status { |
126 | /* Refer to ice_aq_phy_type for bits definition */ | |
127 | u64 phy_type_low; | |
aef74145 | 128 | u64 phy_type_high; |
f776b3ac | 129 | u8 topo_media_conflict; |
dc49c772 AV |
130 | u16 max_frame_size; |
131 | u16 link_speed; | |
ffe49823 | 132 | u16 req_speeds; |
43f8b224 | 133 | u8 lse_ena; /* Link Status Event notification */ |
dc49c772 AV |
134 | u8 link_info; |
135 | u8 an_info; | |
136 | u8 ext_info; | |
f776b3ac | 137 | u8 fec_info; |
dc49c772 | 138 | u8 pacing; |
dc49c772 AV |
139 | /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of |
140 | * ice_aqc_get_phy_caps structure | |
141 | */ | |
142 | u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; | |
143 | }; | |
144 | ||
ddf30f7f | 145 | /* Different reset sources for which a disable queue AQ call has to be made in |
f9867df6 | 146 | * order to clean the Tx scheduler as a part of the reset |
ddf30f7f AV |
147 | */ |
148 | enum ice_disq_rst_src { | |
149 | ICE_NO_RESET = 0, | |
150 | ICE_VM_RESET, | |
151 | ICE_VF_RESET, | |
152 | }; | |
153 | ||
dc49c772 AV |
154 | /* PHY info such as phy_type, etc... */ |
155 | struct ice_phy_info { | |
156 | struct ice_link_status link_info; | |
157 | struct ice_link_status link_info_old; | |
158 | u64 phy_type_low; | |
aef74145 | 159 | u64 phy_type_high; |
dc49c772 | 160 | enum ice_media_type media_type; |
43f8b224 | 161 | u8 get_link_info; |
dc49c772 AV |
162 | }; |
163 | ||
9c20346b AV |
164 | /* Common HW capabilities for SW use */ |
165 | struct ice_hw_common_caps { | |
995c90f2 | 166 | u32 valid_functions; |
a257f188 UK |
167 | /* DCB capabilities */ |
168 | u32 active_tc_bitmap; | |
169 | u32 maxtc; | |
995c90f2 | 170 | |
f9867df6 AV |
171 | /* Tx/Rx queues */ |
172 | u16 num_rxq; /* Number/Total Rx queues */ | |
173 | u16 rxq_first_id; /* First queue ID for Rx queues */ | |
174 | u16 num_txq; /* Number/Total Tx queues */ | |
175 | u16 txq_first_id; /* First queue ID for Tx queues */ | |
9c20346b AV |
176 | |
177 | /* MSI-X vectors */ | |
178 | u16 num_msix_vectors; | |
179 | u16 msix_vector_first_id; | |
180 | ||
181 | /* Max MTU for function or device */ | |
182 | u16 max_mtu; | |
183 | ||
75d2b253 AV |
184 | /* Virtualization support */ |
185 | u8 sr_iov_1_1; /* SR-IOV enabled */ | |
ddf30f7f | 186 | |
9c20346b AV |
187 | /* RSS related capabilities */ |
188 | u16 rss_table_size; /* 512 for PFs and 64 for VFs */ | |
189 | u8 rss_table_entry_width; /* RSS Entry width in bits */ | |
37b6f646 AV |
190 | |
191 | u8 dcb; | |
9c20346b AV |
192 | }; |
193 | ||
194 | /* Function specific capabilities */ | |
195 | struct ice_hw_func_caps { | |
196 | struct ice_hw_common_caps common_cap; | |
75d2b253 AV |
197 | u32 num_allocd_vfs; /* Number of allocated VFs */ |
198 | u32 vf_base_id; /* Logical ID of the first VF */ | |
995c90f2 | 199 | u32 guar_num_vsi; |
9c20346b AV |
200 | }; |
201 | ||
202 | /* Device wide capabilities */ | |
203 | struct ice_hw_dev_caps { | |
204 | struct ice_hw_common_caps common_cap; | |
75d2b253 | 205 | u32 num_vfs_exposed; /* Total number of VFs exposed */ |
9c20346b | 206 | u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */ |
eae1bbb2 | 207 | u32 num_funcs; |
9c20346b AV |
208 | }; |
209 | ||
dc49c772 AV |
210 | /* MAC info */ |
211 | struct ice_mac_info { | |
212 | u8 lan_addr[ETH_ALEN]; | |
213 | u8 perm_addr[ETH_ALEN]; | |
214 | }; | |
215 | ||
ca4929b6 BC |
216 | /* Reset types used to determine which kind of reset was requested. These |
217 | * defines match what the RESET_TYPE field of the GLGEN_RSTAT register. | |
218 | * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register | |
219 | * because its reset source is different than the other types listed. | |
220 | */ | |
f31e4b6f | 221 | enum ice_reset_req { |
ca4929b6 | 222 | ICE_RESET_POR = 0, |
0f9d5027 | 223 | ICE_RESET_INVAL = 0, |
ca4929b6 BC |
224 | ICE_RESET_CORER = 1, |
225 | ICE_RESET_GLOBR = 2, | |
226 | ICE_RESET_EMPR = 3, | |
227 | ICE_RESET_PFR = 4, | |
f31e4b6f AV |
228 | }; |
229 | ||
837f08fd AV |
230 | /* Bus parameters */ |
231 | struct ice_bus_info { | |
232 | u16 device; | |
233 | u8 func; | |
234 | }; | |
235 | ||
dc49c772 AV |
236 | /* Flow control (FC) parameters */ |
237 | struct ice_fc_info { | |
238 | enum ice_fc_mode current_mode; /* FC mode in effect */ | |
239 | enum ice_fc_mode req_mode; /* FC mode requested by caller */ | |
240 | }; | |
241 | ||
f31e4b6f AV |
242 | /* NVM Information */ |
243 | struct ice_nvm_info { | |
244 | u32 eetrack; /* NVM data version */ | |
245 | u32 oem_ver; /* OEM version info */ | |
246 | u16 sr_words; /* Shadow RAM size in words */ | |
247 | u16 ver; /* NVM package version */ | |
43f8b224 | 248 | u8 blank_nvm_mode; /* is NVM empty (no FW present) */ |
f31e4b6f AV |
249 | }; |
250 | ||
870f805e LC |
251 | #define ICE_NVM_VER_LEN 32 |
252 | ||
9c20346b AV |
253 | /* Max number of port to queue branches w.r.t topology */ |
254 | #define ICE_MAX_TRAFFIC_CLASS 8 | |
dc49c772 | 255 | #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS |
9c20346b | 256 | |
2bdc97be BA |
257 | #define ice_for_each_traffic_class(_i) \ |
258 | for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++) | |
259 | ||
7b9ffc76 AV |
260 | #define ICE_INVAL_TEID 0xFFFFFFFF |
261 | ||
9c20346b AV |
262 | struct ice_sched_node { |
263 | struct ice_sched_node *parent; | |
264 | struct ice_sched_node *sibling; /* next sibling in the same layer */ | |
265 | struct ice_sched_node **children; | |
266 | struct ice_aqc_txsched_elem_data info; | |
f9867df6 | 267 | u32 agg_id; /* aggregator group ID */ |
4fb33f31 | 268 | u16 vsi_handle; |
43f8b224 | 269 | u8 in_use; /* suspended or in use */ |
9c20346b AV |
270 | u8 tx_sched_layer; /* Logical Layer (1-9) */ |
271 | u8 num_children; | |
272 | u8 tc_num; | |
273 | u8 owner; | |
274 | #define ICE_SCHED_NODE_OWNER_LAN 0 | |
275 | }; | |
276 | ||
dc49c772 AV |
277 | /* Access Macros for Tx Sched Elements data */ |
278 | #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid) | |
279 | ||
9c20346b AV |
280 | /* The aggregator type determines if identifier is for a VSI group, |
281 | * aggregator group, aggregator of queues, or queue group. | |
282 | */ | |
283 | enum ice_agg_type { | |
284 | ICE_AGG_TYPE_UNKNOWN = 0, | |
285 | ICE_AGG_TYPE_VSI, | |
286 | ICE_AGG_TYPE_AGG, /* aggregator */ | |
287 | ICE_AGG_TYPE_Q, | |
288 | ICE_AGG_TYPE_QG | |
289 | }; | |
290 | ||
1ddef455 UK |
291 | /* Rate limit types */ |
292 | enum ice_rl_type { | |
293 | ICE_UNKNOWN_BW = 0, | |
294 | ICE_MIN_BW, /* for CIR profile */ | |
295 | ICE_MAX_BW, /* for EIR profile */ | |
296 | ICE_SHARED_BW /* for shared profile */ | |
297 | }; | |
298 | ||
299 | #define ICE_SCHED_MIN_BW 500 /* in Kbps */ | |
300 | #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */ | |
301 | #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */ | |
5513b920 | 302 | #define ICE_SCHED_DFLT_RL_PROF_ID 0 |
1ddef455 | 303 | #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF |
b36c598c | 304 | #define ICE_SCHED_DFLT_BW_WT 1 |
1ddef455 UK |
305 | #define ICE_SCHED_INVAL_PROF_ID 0xFFFF |
306 | #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ | |
5513b920 | 307 | |
1ddef455 UK |
308 | /* Data structure for saving BW information */ |
309 | enum ice_bw_type { | |
310 | ICE_BW_TYPE_PRIO, | |
311 | ICE_BW_TYPE_CIR, | |
312 | ICE_BW_TYPE_CIR_WT, | |
313 | ICE_BW_TYPE_EIR, | |
314 | ICE_BW_TYPE_EIR_WT, | |
315 | ICE_BW_TYPE_SHARED, | |
316 | ICE_BW_TYPE_CNT /* This must be last */ | |
317 | }; | |
318 | ||
319 | struct ice_bw { | |
320 | u32 bw; | |
321 | u16 bw_alloc; | |
322 | }; | |
323 | ||
324 | struct ice_bw_type_info { | |
325 | DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT); | |
326 | u8 generic; | |
327 | struct ice_bw cir_bw; | |
328 | struct ice_bw eir_bw; | |
329 | u32 shared_bw; | |
330 | }; | |
331 | ||
332 | /* VSI queue context structure for given TC */ | |
333 | struct ice_q_ctx { | |
334 | u16 q_handle; | |
335 | u32 q_teid; | |
336 | /* bw_t_info saves queue BW information */ | |
337 | struct ice_bw_type_info bw_t_info; | |
338 | }; | |
339 | ||
340 | /* VSI type list entry to locate corresponding VSI/aggregator nodes */ | |
9c20346b AV |
341 | struct ice_sched_vsi_info { |
342 | struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS]; | |
343 | struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS]; | |
344 | struct list_head list_entry; | |
345 | u16 max_lanq[ICE_MAX_TRAFFIC_CLASS]; | |
9c20346b AV |
346 | }; |
347 | ||
348 | /* driver defines the policy */ | |
349 | struct ice_sched_tx_policy { | |
350 | u16 max_num_vsis; | |
351 | u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS]; | |
43f8b224 | 352 | u8 rdma_ena; |
9c20346b AV |
353 | }; |
354 | ||
0ebd3ff1 AV |
355 | /* CEE or IEEE 802.1Qaz ETS Configuration data */ |
356 | struct ice_dcb_ets_cfg { | |
357 | u8 willing; | |
358 | u8 cbs; | |
359 | u8 maxtcs; | |
360 | u8 prio_table[ICE_MAX_TRAFFIC_CLASS]; | |
361 | u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS]; | |
362 | u8 tsatable[ICE_MAX_TRAFFIC_CLASS]; | |
363 | }; | |
364 | ||
365 | /* CEE or IEEE 802.1Qaz PFC Configuration data */ | |
366 | struct ice_dcb_pfc_cfg { | |
367 | u8 willing; | |
368 | u8 mbc; | |
369 | u8 pfccap; | |
370 | u8 pfcena; | |
371 | }; | |
372 | ||
373 | /* CEE or IEEE 802.1Qaz Application Priority data */ | |
374 | struct ice_dcb_app_priority_table { | |
375 | u16 prot_id; | |
376 | u8 priority; | |
377 | u8 selector; | |
378 | }; | |
379 | ||
380 | #define ICE_MAX_USER_PRIORITY 8 | |
381 | #define ICE_DCBX_MAX_APPS 32 | |
382 | #define ICE_LLDPDU_SIZE 1500 | |
383 | #define ICE_TLV_STATUS_OPER 0x1 | |
384 | #define ICE_TLV_STATUS_SYNC 0x2 | |
385 | #define ICE_TLV_STATUS_ERR 0x4 | |
386 | #define ICE_APP_PROT_ID_FCOE 0x8906 | |
387 | #define ICE_APP_PROT_ID_ISCSI 0x0cbc | |
388 | #define ICE_APP_PROT_ID_FIP 0x8914 | |
389 | #define ICE_APP_SEL_ETHTYPE 0x1 | |
390 | #define ICE_APP_SEL_TCPIP 0x2 | |
391 | #define ICE_CEE_APP_SEL_ETHTYPE 0x0 | |
392 | #define ICE_CEE_APP_SEL_TCPIP 0x1 | |
393 | ||
394 | struct ice_dcbx_cfg { | |
395 | u32 numapps; | |
396 | u32 tlv_status; /* CEE mode TLV status */ | |
397 | struct ice_dcb_ets_cfg etscfg; | |
398 | struct ice_dcb_ets_cfg etsrec; | |
399 | struct ice_dcb_pfc_cfg pfc; | |
400 | struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS]; | |
401 | u8 dcbx_mode; | |
402 | #define ICE_DCBX_MODE_CEE 0x1 | |
403 | #define ICE_DCBX_MODE_IEEE 0x2 | |
404 | u8 app_mode; | |
405 | #define ICE_DCBX_APPS_NON_WILLING 0x1 | |
406 | }; | |
407 | ||
9c20346b AV |
408 | struct ice_port_info { |
409 | struct ice_sched_node *root; /* Root Node per Port */ | |
f9867df6 | 410 | struct ice_hw *hw; /* back pointer to HW instance */ |
dc49c772 | 411 | u32 last_node_teid; /* scheduler last node info */ |
9c20346b AV |
412 | u16 sw_id; /* Initial switch ID belongs to port */ |
413 | u16 pf_vf_num; | |
414 | u8 port_state; | |
415 | #define ICE_SCHED_PORT_STATE_INIT 0x0 | |
416 | #define ICE_SCHED_PORT_STATE_READY 0x1 | |
0437f1a9 JB |
417 | u8 lport; |
418 | #define ICE_LPORT_MASK 0xff | |
e94d4478 | 419 | u16 dflt_tx_vsi_rule_id; |
9c20346b | 420 | u16 dflt_tx_vsi_num; |
e94d4478 | 421 | u16 dflt_rx_vsi_rule_id; |
9c20346b | 422 | u16 dflt_rx_vsi_num; |
dc49c772 AV |
423 | struct ice_fc_info fc; |
424 | struct ice_mac_info mac; | |
425 | struct ice_phy_info phy; | |
9c20346b | 426 | struct mutex sched_lock; /* protect access to TXSched tree */ |
29358248 VR |
427 | struct ice_sched_node * |
428 | sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM]; | |
1ddef455 UK |
429 | /* List contain profile ID(s) and other params per layer */ |
430 | struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM]; | |
0ebd3ff1 AV |
431 | struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */ |
432 | /* DCBX info */ | |
433 | struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */ | |
434 | struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */ | |
37b6f646 | 435 | /* LLDP/DCBX Status */ |
0437f1a9 JB |
436 | u8 dcbx_status:3; /* see ICE_DCBX_STATUS_DIS */ |
437 | u8 is_sw_lldp:1; | |
438 | u8 is_vf:1; | |
9c20346b AV |
439 | }; |
440 | ||
9daf8208 | 441 | struct ice_switch_info { |
9daf8208 | 442 | struct list_head vsi_list_map_head; |
80d144c9 | 443 | struct ice_sw_recipe *recp_list; |
9daf8208 AV |
444 | }; |
445 | ||
8b97ceb1 HT |
446 | /* FW logging configuration */ |
447 | struct ice_fw_log_evnt { | |
448 | u8 cfg : 4; /* New event enables to configure */ | |
449 | u8 cur : 4; /* Current/active event enables */ | |
450 | }; | |
451 | ||
452 | struct ice_fw_log_cfg { | |
453 | u8 cq_en : 1; /* FW logging is enabled via the control queue */ | |
454 | u8 uart_en : 1; /* FW logging is enabled via UART for all PFs */ | |
455 | u8 actv_evnts; /* Cumulation of currently enabled log events */ | |
456 | ||
457 | #define ICE_FW_LOG_EVNT_INFO (ICE_AQC_FW_LOG_INFO_EN >> ICE_AQC_FW_LOG_EN_S) | |
458 | #define ICE_FW_LOG_EVNT_INIT (ICE_AQC_FW_LOG_INIT_EN >> ICE_AQC_FW_LOG_EN_S) | |
459 | #define ICE_FW_LOG_EVNT_FLOW (ICE_AQC_FW_LOG_FLOW_EN >> ICE_AQC_FW_LOG_EN_S) | |
460 | #define ICE_FW_LOG_EVNT_ERR (ICE_AQC_FW_LOG_ERR_EN >> ICE_AQC_FW_LOG_EN_S) | |
461 | struct ice_fw_log_evnt evnts[ICE_AQC_FW_LOG_ID_MAX]; | |
462 | }; | |
463 | ||
837f08fd AV |
464 | /* Port hardware description */ |
465 | struct ice_hw { | |
466 | u8 __iomem *hw_addr; | |
467 | void *back; | |
9c20346b AV |
468 | struct ice_aqc_layer_props *layer_info; |
469 | struct ice_port_info *port_info; | |
7ec59eea | 470 | u64 debug_mask; /* bitmap for debug mask */ |
f31e4b6f | 471 | enum ice_mac_type mac_type; |
837f08fd AV |
472 | |
473 | /* pci info */ | |
474 | u16 device_id; | |
475 | u16 vendor_id; | |
476 | u16 subsystem_device_id; | |
477 | u16 subsystem_vendor_id; | |
478 | u8 revision_id; | |
479 | ||
f31e4b6f AV |
480 | u8 pf_id; /* device profile info */ |
481 | ||
1ddef455 UK |
482 | u16 max_burst_size; /* driver sets this value */ |
483 | ||
f9867df6 | 484 | /* Tx Scheduler values */ |
9c20346b AV |
485 | u16 num_tx_sched_layers; |
486 | u16 num_tx_sched_phys_layers; | |
487 | u8 flattened_layers; | |
488 | u8 max_cgds; | |
489 | u8 sw_entry_point_layer; | |
b36c598c | 490 | u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM]; |
9be1d6f8 | 491 | struct list_head agg_list; /* lists all aggregator */ |
9c20346b | 492 | |
0f9d5027 | 493 | struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI]; |
43f8b224 | 494 | u8 evb_veb; /* true for VEB, false for VEPA */ |
f9867df6 | 495 | u8 reset_ongoing; /* true if HW is in reset, false otherwise */ |
837f08fd | 496 | struct ice_bus_info bus; |
f31e4b6f | 497 | struct ice_nvm_info nvm; |
9c20346b AV |
498 | struct ice_hw_dev_caps dev_caps; /* device capabilities */ |
499 | struct ice_hw_func_caps func_caps; /* function capabilities */ | |
f31e4b6f | 500 | |
9daf8208 AV |
501 | struct ice_switch_info *switch_info; /* switch filter lists */ |
502 | ||
7ec59eea AV |
503 | /* Control Queue info */ |
504 | struct ice_ctl_q_info adminq; | |
75d2b253 | 505 | struct ice_ctl_q_info mailboxq; |
7ec59eea AV |
506 | |
507 | u8 api_branch; /* API branch version */ | |
508 | u8 api_maj_ver; /* API major version */ | |
509 | u8 api_min_ver; /* API minor version */ | |
510 | u8 api_patch; /* API patch version */ | |
511 | u8 fw_branch; /* firmware branch version */ | |
512 | u8 fw_maj_ver; /* firmware major version */ | |
513 | u8 fw_min_ver; /* firmware minor version */ | |
514 | u8 fw_patch; /* firmware patch version */ | |
515 | u32 fw_build; /* firmware build number */ | |
940b61af | 516 | |
8b97ceb1 | 517 | struct ice_fw_log_cfg fw_log; |
9e4ab4c2 BC |
518 | |
519 | /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL | |
4ee656bb | 520 | * register. Used for determining the ITR/INTRL granularity during |
9e4ab4c2 BC |
521 | * initialization. |
522 | */ | |
523 | #define ICE_MAX_AGG_BW_200G 0x0 | |
524 | #define ICE_MAX_AGG_BW_100G 0X1 | |
525 | #define ICE_MAX_AGG_BW_50G 0x2 | |
526 | #define ICE_MAX_AGG_BW_25G 0x3 | |
527 | /* ITR granularity for different speeds */ | |
528 | #define ICE_ITR_GRAN_ABOVE_25 2 | |
529 | #define ICE_ITR_GRAN_MAX_25 4 | |
940b61af | 530 | /* ITR granularity in 1 us */ |
9e4ab4c2 BC |
531 | u8 itr_gran; |
532 | /* INTRL granularity for different speeds */ | |
533 | #define ICE_INTRL_GRAN_ABOVE_25 4 | |
534 | #define ICE_INTRL_GRAN_MAX_25 8 | |
535 | /* INTRL granularity in 1 us */ | |
536 | u8 intrl_gran; | |
537 | ||
43f8b224 | 538 | u8 ucast_shared; /* true if VSIs can share unicast addr */ |
9daf8208 | 539 | |
c7648810 TN |
540 | /* Active package version (currently active) */ |
541 | struct ice_pkg_ver active_pkg_ver; | |
542 | u8 active_pkg_name[ICE_PKG_NAME_SIZE]; | |
543 | u8 active_pkg_in_nvm; | |
544 | ||
545 | enum ice_aq_err pkg_dwnld_status; | |
546 | ||
547 | /* Driver's package ver - (from the Metadata seg) */ | |
548 | struct ice_pkg_ver pkg_ver; | |
549 | u8 pkg_name[ICE_PKG_NAME_SIZE]; | |
550 | ||
551 | /* Driver's Ice package version (from the Ice seg) */ | |
552 | struct ice_pkg_ver ice_pkg_ver; | |
553 | u8 ice_pkg_name[ICE_PKG_NAME_SIZE]; | |
554 | ||
555 | /* Pointer to the ice segment */ | |
556 | struct ice_seg *seg; | |
557 | ||
558 | /* Pointer to allocated copy of pkg memory */ | |
559 | u8 *pkg_copy; | |
560 | u32 pkg_size; | |
561 | ||
562 | /* HW block tables */ | |
563 | struct ice_blk_info blk[ICE_BLK_COUNT]; | |
c90ed40c TN |
564 | struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */ |
565 | struct list_head fl_profs[ICE_BLK_COUNT]; | |
566 | struct mutex rss_locks; /* protect RSS configuration */ | |
567 | struct list_head rss_list_head; | |
837f08fd AV |
568 | }; |
569 | ||
fcea6f3d AV |
570 | /* Statistics collected by each port, VSI, VEB, and S-channel */ |
571 | struct ice_eth_stats { | |
572 | u64 rx_bytes; /* gorc */ | |
573 | u64 rx_unicast; /* uprc */ | |
574 | u64 rx_multicast; /* mprc */ | |
575 | u64 rx_broadcast; /* bprc */ | |
576 | u64 rx_discards; /* rdpc */ | |
577 | u64 rx_unknown_protocol; /* rupp */ | |
578 | u64 tx_bytes; /* gotc */ | |
579 | u64 tx_unicast; /* uptc */ | |
580 | u64 tx_multicast; /* mptc */ | |
581 | u64 tx_broadcast; /* bptc */ | |
582 | u64 tx_discards; /* tdpc */ | |
583 | u64 tx_errors; /* tepc */ | |
584 | }; | |
585 | ||
586 | /* Statistics collected by the MAC */ | |
587 | struct ice_hw_port_stats { | |
588 | /* eth stats collected by the port */ | |
589 | struct ice_eth_stats eth; | |
590 | /* additional port specific stats */ | |
591 | u64 tx_dropped_link_down; /* tdold */ | |
592 | u64 crc_errors; /* crcerrs */ | |
593 | u64 illegal_bytes; /* illerrc */ | |
594 | u64 error_bytes; /* errbc */ | |
595 | u64 mac_local_faults; /* mlfc */ | |
596 | u64 mac_remote_faults; /* mrfc */ | |
597 | u64 rx_len_errors; /* rlec */ | |
598 | u64 link_xon_rx; /* lxonrxc */ | |
599 | u64 link_xoff_rx; /* lxoffrxc */ | |
600 | u64 link_xon_tx; /* lxontxc */ | |
601 | u64 link_xoff_tx; /* lxofftxc */ | |
4b0fdceb AV |
602 | u64 priority_xon_rx[8]; /* pxonrxc[8] */ |
603 | u64 priority_xoff_rx[8]; /* pxoffrxc[8] */ | |
604 | u64 priority_xon_tx[8]; /* pxontxc[8] */ | |
605 | u64 priority_xoff_tx[8]; /* pxofftxc[8] */ | |
606 | u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */ | |
fcea6f3d AV |
607 | u64 rx_size_64; /* prc64 */ |
608 | u64 rx_size_127; /* prc127 */ | |
609 | u64 rx_size_255; /* prc255 */ | |
610 | u64 rx_size_511; /* prc511 */ | |
611 | u64 rx_size_1023; /* prc1023 */ | |
612 | u64 rx_size_1522; /* prc1522 */ | |
613 | u64 rx_size_big; /* prc9522 */ | |
614 | u64 rx_undersize; /* ruc */ | |
615 | u64 rx_fragments; /* rfc */ | |
616 | u64 rx_oversize; /* roc */ | |
617 | u64 rx_jabber; /* rjc */ | |
618 | u64 tx_size_64; /* ptc64 */ | |
619 | u64 tx_size_127; /* ptc127 */ | |
620 | u64 tx_size_255; /* ptc255 */ | |
621 | u64 tx_size_511; /* ptc511 */ | |
622 | u64 tx_size_1023; /* ptc1023 */ | |
623 | u64 tx_size_1522; /* ptc1522 */ | |
624 | u64 tx_size_big; /* ptc9522 */ | |
625 | }; | |
626 | ||
f31e4b6f | 627 | /* Checksum and Shadow RAM pointers */ |
031f2147 MFIP |
628 | #define ICE_SR_BOOT_CFG_PTR 0x132 |
629 | #define ICE_NVM_OEM_VER_OFF 0x02 | |
f31e4b6f AV |
630 | #define ICE_SR_NVM_DEV_STARTER_VER 0x18 |
631 | #define ICE_SR_NVM_EETRACK_LO 0x2D | |
632 | #define ICE_SR_NVM_EETRACK_HI 0x2E | |
fcea6f3d AV |
633 | #define ICE_NVM_VER_LO_SHIFT 0 |
634 | #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT) | |
635 | #define ICE_NVM_VER_HI_SHIFT 12 | |
636 | #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT) | |
637 | #define ICE_OEM_VER_PATCH_SHIFT 0 | |
638 | #define ICE_OEM_VER_PATCH_MASK (0xff << ICE_OEM_VER_PATCH_SHIFT) | |
639 | #define ICE_OEM_VER_BUILD_SHIFT 8 | |
640 | #define ICE_OEM_VER_BUILD_MASK (0xffff << ICE_OEM_VER_BUILD_SHIFT) | |
641 | #define ICE_OEM_VER_SHIFT 24 | |
642 | #define ICE_OEM_VER_MASK (0xff << ICE_OEM_VER_SHIFT) | |
031f2147 | 643 | #define ICE_SR_PFA_PTR 0x40 |
f31e4b6f AV |
644 | #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800 |
645 | #define ICE_SR_WORDS_IN_1KB 512 | |
646 | ||
8ede0178 AV |
647 | /* Hash redirection LUT for VSI - maximum array size */ |
648 | #define ICE_VSIQF_HLUT_ARRAY_SIZE ((VSIQF_HLUT_MAX_INDEX + 1) * 4) | |
649 | ||
837f08fd | 650 | #endif /* _ICE_TYPE_H_ */ |