[linux-block.git] / drivers / net / ethernet / intel / ice / ice_txrx.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2018, Intel Corporation. */

#ifndef _ICE_TXRX_H_
#define _ICE_TXRX_H_

#include "ice_type.h"

#define ICE_DFLT_IRQ_WORK	256
#define ICE_RXBUF_3072		3072
#define ICE_RXBUF_2048		2048
#define ICE_RXBUF_1536		1536
#define ICE_MAX_CHAINED_RX_BUFS	5
#define ICE_MAX_BUF_TXD		8
#define ICE_MIN_TX_LEN		17

/* The size limit for a transmit buffer in a descriptor is (16K - 1).
 * In order to align with the read requests we will align the value to
 * the nearest 4K which represents our maximum read request size.
 */
#define ICE_MAX_READ_REQ_SIZE	4096
#define ICE_MAX_DATA_PER_TXD	(16 * 1024 - 1)
#define ICE_MAX_DATA_PER_TXD_ALIGNED \
	(~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD)

#define ICE_RX_BUF_WRITE	16	/* Must be power of 2 */
#define ICE_MAX_TXQ_PER_TXQG	128

/* Attempt to maximize the headroom available for incoming frames. We use a 2K
 * buffer for MTUs <= 1500 and need 1536/1534 to store the data for the frame.
 * This leaves us with 512 bytes of room.  From that we need to deduct the
 * space needed for the shared info and the padding needed to IP align the
 * frame.
 *
 * Note: For cache line sizes 256 or larger this value is going to end
 *	 up negative.  In these cases we should fall back to the legacy
 *	 receive path.
 */
#if (PAGE_SIZE < 8192)
#define ICE_2K_TOO_SMALL_WITH_PADDING \
	((unsigned int)(NET_SKB_PAD + ICE_RXBUF_1536) > \
			SKB_WITH_OVERHEAD(ICE_RXBUF_2048))

/**
 * ice_compute_pad - compute the padding
 * @rx_buf_len: buffer length
 *
 * Figure out the size of half page based on given buffer length and
 * then subtract the skb_shared_info followed by subtraction of the
 * actual buffer length; this in turn results in the actual space that
 * is left for padding usage
 */
static inline int ice_compute_pad(int rx_buf_len)
{
	int half_page_size;

	half_page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
	return SKB_WITH_OVERHEAD(half_page_size) - rx_buf_len;
}

/**
 * ice_skb_pad - determine the padding that we can supply
 *
 * Figure out the right Rx buffer size and based on that calculate the
 * padding
 */
static inline int ice_skb_pad(void)
{
	int rx_buf_len;

	/* If a 2K buffer cannot handle a standard Ethernet frame then
	 * optimize padding for a 3K buffer instead of a 1.5K buffer.
	 *
	 * For a 3K buffer we need to add enough padding to allow for
	 * tailroom due to NET_IP_ALIGN possibly shifting us out of
	 * cache-line alignment.
	 */
	if (ICE_2K_TOO_SMALL_WITH_PADDING)
		rx_buf_len = ICE_RXBUF_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN);
	else
		rx_buf_len = ICE_RXBUF_1536;

	/* if needed make room for NET_IP_ALIGN */
	rx_buf_len -= NET_IP_ALIGN;

	return ice_compute_pad(rx_buf_len);
}

#define ICE_SKB_PAD ice_skb_pad()
#else
#define ICE_2K_TOO_SMALL_WITH_PADDING false
#define ICE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
#endif

/* We are assuming that the cache line is always 64 Bytes here for ice.
 * In order to make sure that is a correct assumption there is a check in probe
 * to print a warning if the read from GLPCI_CNF2 tells us that the cache line
 * size is 128 bytes. We do it this way because we do not want to read the
 * GLPCI_CNF2 register or a variable containing the value on every pass through
 * the Tx path.
 */
#define ICE_CACHE_LINE_BYTES		64
#define ICE_DESCS_PER_CACHE_LINE	(ICE_CACHE_LINE_BYTES / \
					 sizeof(struct ice_tx_desc))
#define ICE_DESCS_FOR_CTX_DESC		1
#define ICE_DESCS_FOR_SKB_DATA_PTR	1
/* Tx descriptors needed, worst case */
#define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \
		     ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR)
#define ICE_DESC_UNUSED(R)	\
	(u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
	      (R)->next_to_clean - (R)->next_to_use - 1)

#define ICE_TX_FLAGS_TSO	BIT(0)
#define ICE_TX_FLAGS_HW_VLAN	BIT(1)
#define ICE_TX_FLAGS_SW_VLAN	BIT(2)
/* ICE_TX_FLAGS_DUMMY_PKT is used to mark dummy packets that should be
 * freed instead of returned like skb packets.
 */
#define ICE_TX_FLAGS_DUMMY_PKT	BIT(3)
#define ICE_TX_FLAGS_TSYN	BIT(4)
#define ICE_TX_FLAGS_IPV4	BIT(5)
#define ICE_TX_FLAGS_IPV6	BIT(6)
#define ICE_TX_FLAGS_TUNNEL	BIT(7)
#define ICE_TX_FLAGS_VLAN_M	0xffff0000
#define ICE_TX_FLAGS_VLAN_PR_M	0xe0000000
#define ICE_TX_FLAGS_VLAN_PR_S	29
#define ICE_TX_FLAGS_VLAN_S	16

#define ICE_XDP_PASS		0
#define ICE_XDP_CONSUMED	BIT(0)
#define ICE_XDP_TX		BIT(1)
#define ICE_XDP_REDIR		BIT(2)

#define ICE_RX_DMA_ATTR \
	(DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)

#define ICE_ETH_PKT_HDR_PAD	(ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))

#define ICE_TXD_LAST_DESC_CMD (ICE_TX_DESC_CMD_EOP | ICE_TX_DESC_CMD_RS)

struct ice_tx_buf {
	struct ice_tx_desc *next_to_watch;
	union {
		struct sk_buff *skb;
		void *raw_buf; /* used for XDP */
	};
	unsigned int bytecount;
	unsigned short gso_segs;
	u32 tx_flags;
	DEFINE_DMA_UNMAP_LEN(len);
	DEFINE_DMA_UNMAP_ADDR(dma);
};

struct ice_tx_offload_params {
	u64 cd_qw1;
	struct ice_ring *tx_ring;
	u32 td_cmd;
	u32 td_offset;
	u32 td_l2tag1;
	u32 cd_tunnel_params;
	u16 cd_l2tag2;
	u8 header_len;
};

struct ice_rx_buf {
	dma_addr_t dma;
	struct page *page;
	unsigned int page_offset;
	u16 pagecnt_bias;
};

struct ice_q_stats {
	u64 pkts;
	u64 bytes;
};

struct ice_txq_stats {
	u64 restart_q;
	u64 tx_busy;
	u64 tx_linearize;
	int prev_pkt; /* negative if no pending Tx descriptors */
};

struct ice_rxq_stats {
	u64 non_eop_descs;
	u64 alloc_page_failed;
	u64 alloc_buf_failed;
};

enum ice_ring_state_t {
	ICE_TX_XPS_INIT_DONE,
	ICE_TX_NBITS,
};

/* this enum matches hardware bits and is meant to be used by DYN_CTLN
 * registers and QINT registers or more generally anywhere in the manual
 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
 * register but instead is a special value meaning "don't update" ITR0/1/2.
 */
enum ice_dyn_idx_t {
	ICE_IDX_ITR0 = 0,
	ICE_IDX_ITR1 = 1,
	ICE_IDX_ITR2 = 2,
	ICE_ITR_NONE = 3	/* ITR_NONE must not be used as an index */
};

/* Header split modes defined by DTYPE field of Rx RLAN context */
enum ice_rx_dtype {
	ICE_RX_DTYPE_NO_SPLIT		= 0,
	ICE_RX_DTYPE_HEADER_SPLIT	= 1,
	ICE_RX_DTYPE_SPLIT_ALWAYS	= 2,
};

/* indices into GLINT_ITR registers */
#define ICE_RX_ITR	ICE_IDX_ITR0
#define ICE_TX_ITR	ICE_IDX_ITR1
#define ICE_ITR_8K	124
#define ICE_ITR_20K	50
#define ICE_ITR_MAX	8160 /* 0x1FE0 */
#define ICE_DFLT_TX_ITR	ICE_ITR_20K
#define ICE_DFLT_RX_ITR	ICE_ITR_20K
enum ice_dynamic_itr {
	ITR_STATIC = 0,
	ITR_DYNAMIC = 1
};

#define ITR_IS_DYNAMIC(rc) ((rc)->itr_mode == ITR_DYNAMIC)
#define ICE_ITR_GRAN_S		1	/* ITR granularity is always 2us */
#define ICE_ITR_GRAN_US		BIT(ICE_ITR_GRAN_S)
#define ICE_ITR_MASK		0x1FFE	/* ITR register value alignment mask */
#define ITR_REG_ALIGN(setting)	((setting) & ICE_ITR_MASK)

#define ICE_DFLT_INTRL	0
#define ICE_MAX_INTRL	236

#define ICE_IN_WB_ON_ITR_MODE	255
/* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows
 * setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also,
 * set the write-back latency to the usecs passed in.
 */
#define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx)	\
	((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \
	  GLINT_DYN_CTL_INTERVAL_M) | \
	 (((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \
	  GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \
	 GLINT_DYN_CTL_WB_ON_ITR_M)

/* Legacy or Advanced Mode Queue */
#define ICE_TX_ADVANCED	0
#define ICE_TX_LEGACY	1

/* descriptor ring, associated with a VSI */
struct ice_ring {
	/* CL1 - 1st cacheline starts here */
	struct ice_ring *next;		/* pointer to next ring in q_vector */
	void *desc;			/* Descriptor ring memory */
	struct device *dev;		/* Used for DMA mapping */
	struct net_device *netdev;	/* netdev ring maps to */
	struct ice_vsi *vsi;		/* Backreference to associated VSI */
	struct ice_q_vector *q_vector;	/* Backreference to associated vector */
	u8 __iomem *tail;
	union {
		struct ice_tx_buf *tx_buf;
		struct ice_rx_buf *rx_buf;
		struct xdp_buff **xdp_buf;
	};
	/* CL2 - 2nd cacheline starts here */
	u16 q_index;			/* Queue number of ring */
	u16 q_handle;			/* Queue handle per TC */

	u16 count;			/* Number of descriptors */
	u16 reg_idx;			/* HW register index of the ring */

	/* used in interrupt processing */
	u16 next_to_use;
	u16 next_to_clean;
	u16 next_to_alloc;

	/* stats structs */
	struct ice_q_stats	stats;
	struct u64_stats_sync syncp;
	union {
		struct ice_txq_stats tx_stats;
		struct ice_rxq_stats rx_stats;
	};

	struct rcu_head rcu;		/* to avoid race on free */
	DECLARE_BITMAP(xps_state, ICE_TX_NBITS);	/* XPS Config State */
	struct bpf_prog *xdp_prog;
	struct xsk_buff_pool *xsk_pool;
	u16 rx_offset;
	/* CL3 - 3rd cacheline starts here */
	struct xdp_rxq_info xdp_rxq;
	struct sk_buff *skb;
	/* CLX - the below items are only accessed infrequently and should be
	 * in their own cache line if possible
	 */
#define ICE_TX_FLAGS_RING_XDP		BIT(0)
#define ICE_RX_FLAGS_RING_BUILD_SKB	BIT(1)
	u8 flags;
	dma_addr_t dma;			/* physical address of ring */
	unsigned int size;		/* length of descriptor ring in bytes */
	u32 txq_teid;			/* Added Tx queue TEID */
	u16 rx_buf_len;
	u8 dcb_tc;			/* Traffic class of ring */
	struct ice_ptp_tx *tx_tstamps;
	u64 cached_phctime;
	u8 ptp_rx:1;
	u8 ptp_tx:1;
} ____cacheline_internodealigned_in_smp;

static inline bool ice_ring_uses_build_skb(struct ice_ring *ring)
{
	return !!(ring->flags & ICE_RX_FLAGS_RING_BUILD_SKB);
}

static inline void ice_set_ring_build_skb_ena(struct ice_ring *ring)
{
	ring->flags |= ICE_RX_FLAGS_RING_BUILD_SKB;
}

static inline void ice_clear_ring_build_skb_ena(struct ice_ring *ring)
{
	ring->flags &= ~ICE_RX_FLAGS_RING_BUILD_SKB;
}

static inline bool ice_ring_is_xdp(struct ice_ring *ring)
{
	return !!(ring->flags & ICE_TX_FLAGS_RING_XDP);
}

struct ice_ring_container {
	/* head of linked-list of rings */
	struct ice_ring *ring;
	struct dim dim;		/* data for net_dim algorithm */
	u16 itr_idx;		/* index in the interrupt vector */
	/* this matches the maximum number of ITR bits, but in usec
	 * values, so it is shifted left one bit (bit zero is ignored)
	 */
	u16 itr_setting:13;
	u16 itr_reserved:2;
	u16 itr_mode:1;
};

struct ice_coalesce_stored {
	u16 itr_tx;
	u16 itr_rx;
	u8 intrl;
	u8 tx_valid;
	u8 rx_valid;
};

/* iterator for handling rings in ring container */
#define ice_for_each_ring(pos, head) \
	for (pos = (head).ring; pos; pos = pos->next)

static inline unsigned int ice_rx_pg_order(struct ice_ring *ring)
{
#if (PAGE_SIZE < 8192)
	if (ring->rx_buf_len > (PAGE_SIZE / 2))
		return 1;
#endif
	return 0;
}

#define ice_rx_pg_size(_ring) (PAGE_SIZE << ice_rx_pg_order(_ring))

union ice_32b_rx_flex_desc;

bool ice_alloc_rx_bufs(struct ice_ring *rxr, u16 cleaned_count);
netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev);
u16
ice_select_queue(struct net_device *dev, struct sk_buff *skb,
		 struct net_device *sb_dev);
void ice_clean_tx_ring(struct ice_ring *tx_ring);
void ice_clean_rx_ring(struct ice_ring *rx_ring);
int ice_setup_tx_ring(struct ice_ring *tx_ring);
int ice_setup_rx_ring(struct ice_ring *rx_ring);
void ice_free_tx_ring(struct ice_ring *tx_ring);
void ice_free_rx_ring(struct ice_ring *rx_ring);
int ice_napi_poll(struct napi_struct *napi, int budget);
int
ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc,
		   u8 *raw_packet);
int ice_clean_rx_irq(struct ice_ring *rx_ring, int budget);
void ice_clean_ctrl_tx_irq(struct ice_ring *tx_ring);
#endif /* _ICE_TXRX_H_ */
Commit	Line	Data
940b61af AV	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright (c) 2018, Intel Corporation. */
	3
	4	#ifndef _ICE_TXRX_H_
	5	#define _ICE_TXRX_H_
	6
2d4238f5 KK	7	#include "ice_type.h"
2d4238f5 KK	8
940b61af	9	#define ICE_DFLT_IRQ_WORK 256
7237f5b0	10	#define ICE_RXBUF_3072 3072
cdedef59	11	#define ICE_RXBUF_2048 2048
7237f5b0	12	#define ICE_RXBUF_1536 1536
cdedef59	13	#define ICE_MAX_CHAINED_RX_BUFS 5
2b245cb2 AV	14	#define ICE_MAX_BUF_TXD 8
	15	#define ICE_MIN_TX_LEN 17
	16
	17	/* The size limit for a transmit buffer in a descriptor is (16K - 1).
	18	* In order to align with the read requests we will align the value to
	19	* the nearest 4K which represents our maximum read request size.
	20	*/
	21	#define ICE_MAX_READ_REQ_SIZE 4096
	22	#define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1)
	23	#define ICE_MAX_DATA_PER_TXD_ALIGNED \
	24	(~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD)
	25
	26	#define ICE_RX_BUF_WRITE 16 /* Must be power of 2 */
cdedef59 AV	27	#define ICE_MAX_TXQ_PER_TXQG 128
cdedef59 AV	28
59bb0808 MF	29	/* Attempt to maximize the headroom available for incoming frames. We use a 2K
	30	* buffer for MTUs <= 1500 and need 1536/1534 to store the data for the frame.
	31	* This leaves us with 512 bytes of room. From that we need to deduct the
	32	* space needed for the shared info and the padding needed to IP align the
	33	* frame.
	34	*
	35	* Note: For cache line sizes 256 or larger this value is going to end
4ee656bb TN	36	* up negative. In these cases we should fall back to the legacy
4ee656bb TN	37	* receive path.
59bb0808 MF	38	*/
	39	#if (PAGE_SIZE < 8192)
	40	#define ICE_2K_TOO_SMALL_WITH_PADDING \
22bef5e7 JB	41	((unsigned int)(NET_SKB_PAD + ICE_RXBUF_1536) > \
22bef5e7 JB	42	SKB_WITH_OVERHEAD(ICE_RXBUF_2048))
59bb0808 MF	43
	44	/**
	45	* ice_compute_pad - compute the padding
b50f7bca	46	* @rx_buf_len: buffer length
59bb0808 MF	47	*
	48	* Figure out the size of half page based on given buffer length and
	49	* then subtract the skb_shared_info followed by subtraction of the
	50	* actual buffer length; this in turn results in the actual space that
	51	* is left for padding usage
	52	*/
	53	static inline int ice_compute_pad(int rx_buf_len)
	54	{
	55	int half_page_size;
	56
	57	half_page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
	58	return SKB_WITH_OVERHEAD(half_page_size) - rx_buf_len;
	59	}
	60
	61	/**
	62	* ice_skb_pad - determine the padding that we can supply
	63	*
	64	* Figure out the right Rx buffer size and based on that calculate the
	65	* padding
	66	*/
	67	static inline int ice_skb_pad(void)
	68	{
	69	int rx_buf_len;
	70
	71	/* If a 2K buffer cannot handle a standard Ethernet frame then
	72	* optimize padding for a 3K buffer instead of a 1.5K buffer.
	73	*
	74	* For a 3K buffer we need to add enough padding to allow for
	75	* tailroom due to NET_IP_ALIGN possibly shifting us out of
	76	* cache-line alignment.
	77	*/
	78	if (ICE_2K_TOO_SMALL_WITH_PADDING)
	79	rx_buf_len = ICE_RXBUF_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN);
	80	else
	81	rx_buf_len = ICE_RXBUF_1536;
	82
	83	/* if needed make room for NET_IP_ALIGN */
	84	rx_buf_len -= NET_IP_ALIGN;
	85
	86	return ice_compute_pad(rx_buf_len);
	87	}
	88
	89	#define ICE_SKB_PAD ice_skb_pad()
	90	#else
	91	#define ICE_2K_TOO_SMALL_WITH_PADDING false
	92	#define ICE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
	93	#endif
	94
c585ea42 BC	95	/* We are assuming that the cache line is always 64 Bytes here for ice.
	96	* In order to make sure that is a correct assumption there is a check in probe
	97	* to print a warning if the read from GLPCI_CNF2 tells us that the cache line
	98	* size is 128 bytes. We do it this way because we do not want to read the
	99	* GLPCI_CNF2 register or a variable containing the value on every pass through
	100	* the Tx path.
	101	*/
	102	#define ICE_CACHE_LINE_BYTES 64
	103	#define ICE_DESCS_PER_CACHE_LINE (ICE_CACHE_LINE_BYTES / \
	104	sizeof(struct ice_tx_desc))
	105	#define ICE_DESCS_FOR_CTX_DESC 1
	106	#define ICE_DESCS_FOR_SKB_DATA_PTR 1
	107	/* Tx descriptors needed, worst case */
	108	#define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \
	109	ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR)
cdedef59	110	#define ICE_DESC_UNUSED(R) \
22bef5e7 JB	111	(u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
22bef5e7 JB	112	(R)->next_to_clean - (R)->next_to_use - 1)
cdedef59	113
d76a60ba AV	114	#define ICE_TX_FLAGS_TSO BIT(0)
	115	#define ICE_TX_FLAGS_HW_VLAN BIT(1)
	116	#define ICE_TX_FLAGS_SW_VLAN BIT(2)
148beb61 HT	117	/* ICE_TX_FLAGS_DUMMY_PKT is used to mark dummy packets that should be
	118	* freed instead of returned like skb packets.
	119	*/
	120	#define ICE_TX_FLAGS_DUMMY_PKT BIT(3)
ea9b847c	121	#define ICE_TX_FLAGS_TSYN BIT(4)
a4e82a81 TN	122	#define ICE_TX_FLAGS_IPV4 BIT(5)
	123	#define ICE_TX_FLAGS_IPV6 BIT(6)
	124	#define ICE_TX_FLAGS_TUNNEL BIT(7)
d76a60ba	125	#define ICE_TX_FLAGS_VLAN_M 0xffff0000
5f6aa50e AV	126	#define ICE_TX_FLAGS_VLAN_PR_M 0xe0000000
5f6aa50e AV	127	#define ICE_TX_FLAGS_VLAN_PR_S 29
d76a60ba AV	128	#define ICE_TX_FLAGS_VLAN_S 16
d76a60ba AV	129
efc2214b MF	130	#define ICE_XDP_PASS 0
	131	#define ICE_XDP_CONSUMED BIT(0)
	132	#define ICE_XDP_TX BIT(1)
	133	#define ICE_XDP_REDIR BIT(2)
	134
a65f71fe MF	135	#define ICE_RX_DMA_ATTR \
	136	(DMA_ATTR_SKIP_CPU_SYNC \| DMA_ATTR_WEAK_ORDERING)
	137
efc2214b MF	138	#define ICE_ETH_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
	139
	140	#define ICE_TXD_LAST_DESC_CMD (ICE_TX_DESC_CMD_EOP \| ICE_TX_DESC_CMD_RS)
	141
cdedef59 AV	142	struct ice_tx_buf {
cdedef59 AV	143	struct ice_tx_desc *next_to_watch;
efc2214b MF	144	union {
	145	struct sk_buff *skb;
	146	void raw_buf; / used for XDP */
	147	};
cdedef59 AV	148	unsigned int bytecount;
	149	unsigned short gso_segs;
	150	u32 tx_flags;
cdedef59	151	DEFINE_DMA_UNMAP_LEN(len);
65124bbf	152	DEFINE_DMA_UNMAP_ADDR(dma);
cdedef59 AV	153	};
cdedef59 AV	154
d76a60ba	155	struct ice_tx_offload_params {
65124bbf JB	156	u64 cd_qw1;
65124bbf JB	157	struct ice_ring *tx_ring;
d76a60ba AV	158	u32 td_cmd;
	159	u32 td_offset;
	160	u32 td_l2tag1;
d76a60ba	161	u32 cd_tunnel_params;
65124bbf JB	162	u16 cd_l2tag2;
65124bbf JB	163	u8 header_len;
d76a60ba AV	164	};
d76a60ba AV	165
cdedef59	166	struct ice_rx_buf {
57f7f8b6 MK	167	dma_addr_t dma;
	168	struct page *page;
	169	unsigned int page_offset;
	170	u16 pagecnt_bias;
cdedef59	171	};
940b61af	172
2b245cb2 AV	173	struct ice_q_stats {
	174	u64 pkts;
	175	u64 bytes;
	176	};
	177
	178	struct ice_txq_stats {
	179	u64 restart_q;
	180	u64 tx_busy;
	181	u64 tx_linearize;
b3969fd7	182	int prev_pkt; /* negative if no pending Tx descriptors */
2b245cb2 AV	183	};
	184
	185	struct ice_rxq_stats {
	186	u64 non_eop_descs;
	187	u64 alloc_page_failed;
	188	u64 alloc_buf_failed;
2b245cb2 AV	189	};
2b245cb2 AV	190
634da4c1 BB	191	enum ice_ring_state_t {
	192	ICE_TX_XPS_INIT_DONE,
	193	ICE_TX_NBITS,
	194	};
	195
940b61af AV	196	/* this enum matches hardware bits and is meant to be used by DYN_CTLN
	197	* registers and QINT registers or more generally anywhere in the manual
	198	* mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
	199	* register but instead is a special value meaning "don't update" ITR0/1/2.
	200	*/
	201	enum ice_dyn_idx_t {
	202	ICE_IDX_ITR0 = 0,
	203	ICE_IDX_ITR1 = 1,
	204	ICE_IDX_ITR2 = 2,
	205	ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
	206	};
	207
cdedef59 AV	208	/* Header split modes defined by DTYPE field of Rx RLAN context */
	209	enum ice_rx_dtype {
	210	ICE_RX_DTYPE_NO_SPLIT = 0,
	211	ICE_RX_DTYPE_HEADER_SPLIT = 1,
	212	ICE_RX_DTYPE_SPLIT_ALWAYS = 2,
	213	};
	214
940b61af AV	215	/* indices into GLINT_ITR registers */
940b61af AV	216	#define ICE_RX_ITR ICE_IDX_ITR0
cdedef59	217	#define ICE_TX_ITR ICE_IDX_ITR1
63f545ed	218	#define ICE_ITR_8K 124
d2b464a7	219	#define ICE_ITR_20K 50
d59684a0 JB	220	#define ICE_ITR_MAX 8160 /* 0x1FE0 */
	221	#define ICE_DFLT_TX_ITR ICE_ITR_20K
	222	#define ICE_DFLT_RX_ITR ICE_ITR_20K
	223	enum ice_dynamic_itr {
	224	ITR_STATIC = 0,
	225	ITR_DYNAMIC = 1
	226	};
	227
	228	#define ITR_IS_DYNAMIC(rc) ((rc)->itr_mode == ITR_DYNAMIC)
92414f32	229	#define ICE_ITR_GRAN_S 1 /* ITR granularity is always 2us */
70457520	230	#define ICE_ITR_GRAN_US BIT(ICE_ITR_GRAN_S)
63f545ed	231	#define ICE_ITR_MASK 0x1FFE /* ITR register value alignment mask */
840f8ad0	232	#define ITR_REG_ALIGN(setting) ((setting) & ICE_ITR_MASK)
940b61af	233
9e4ab4c2	234	#define ICE_DFLT_INTRL 0
b9c8bb06	235	#define ICE_MAX_INTRL 236
940b61af	236
2ab28bb0 BC	237	#define ICE_IN_WB_ON_ITR_MODE 255
	238	/* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows
	239	* setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also,
	240	* set the write-back latency to the usecs passed in.
	241	*/
	242	#define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx) \
	243	((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \
	244	GLINT_DYN_CTL_INTERVAL_M) \| \
	245	(((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \
	246	GLINT_DYN_CTL_ITR_INDX_M) \| GLINT_DYN_CTL_INTENA_MSK_M \| \
	247	GLINT_DYN_CTL_WB_ON_ITR_M)
	248
cdedef59 AV	249	/* Legacy or Advanced Mode Queue */
	250	#define ICE_TX_ADVANCED 0
	251	#define ICE_TX_LEGACY 1
	252
3a858ba3 AV	253	/* descriptor ring, associated with a VSI */
3a858ba3 AV	254	struct ice_ring {
65124bbf	255	/* CL1 - 1st cacheline starts here */
3a858ba3	256	struct ice_ring next; / pointer to next ring in q_vector */
cdedef59	257	void desc; / Descriptor ring memory */
3a858ba3 AV	258	struct device dev; / Used for DMA mapping */
	259	struct net_device netdev; / netdev ring maps to */
	260	struct ice_vsi vsi; / Backreference to associated VSI */
	261	struct ice_q_vector q_vector; / Backreference to associated vector */
cdedef59 AV	262	u8 __iomem *tail;
	263	union {
	264	struct ice_tx_buf *tx_buf;
	265	struct ice_rx_buf *rx_buf;
57f7f8b6	266	struct xdp_buff **xdp_buf;
cdedef59	267	};
65124bbf	268	/* CL2 - 2nd cacheline starts here */
3a858ba3	269	u16 q_index; /* Queue number of ring */
65124bbf JB	270	u16 q_handle; /* Queue handle per TC */
65124bbf JB	271
3a858ba3 AV	272	u16 count; /* Number of descriptors */
3a858ba3 AV	273	u16 reg_idx; /* HW register index of the ring */
cdedef59 AV	274
	275	/* used in interrupt processing */
	276	u16 next_to_use;
	277	u16 next_to_clean;
65124bbf	278	u16 next_to_alloc;
2b245cb2 AV	279
	280	/* stats structs */
	281	struct ice_q_stats stats;
	282	struct u64_stats_sync syncp;
	283	union {
	284	struct ice_txq_stats tx_stats;
	285	struct ice_rxq_stats rx_stats;
	286	};
	287
3a858ba3	288	struct rcu_head rcu; /* to avoid race on free */
634da4c1	289	DECLARE_BITMAP(xps_state, ICE_TX_NBITS); /* XPS Config State */
efc2214b	290	struct bpf_prog *xdp_prog;
1742b3d5	291	struct xsk_buff_pool *xsk_pool;
f1b1f409	292	u16 rx_offset;
efc2214b MF	293	/* CL3 - 3rd cacheline starts here */
efc2214b MF	294	struct xdp_rxq_info xdp_rxq;
29b82f2a	295	struct sk_buff *skb;
65124bbf JB	296	/* CLX - the below items are only accessed infrequently and should be
	297	* in their own cache line if possible
	298	*/
efc2214b	299	#define ICE_TX_FLAGS_RING_XDP BIT(0)
59bb0808	300	#define ICE_RX_FLAGS_RING_BUILD_SKB BIT(1)
efc2214b	301	u8 flags;
65124bbf JB	302	dma_addr_t dma; /* physical address of ring */
	303	unsigned int size; /* length of descriptor ring in bytes */
	304	u32 txq_teid; /* Added Tx queue TEID */
	305	u16 rx_buf_len;
65124bbf	306	u8 dcb_tc; /* Traffic class of ring */
ea9b847c	307	struct ice_ptp_tx *tx_tstamps;
77a78115 JK	308	u64 cached_phctime;
77a78115 JK	309	u8 ptp_rx:1;
ea9b847c	310	u8 ptp_tx:1;
3a858ba3 AV	311	} ____cacheline_internodealigned_in_smp;
3a858ba3 AV	312
59bb0808 MF	313	static inline bool ice_ring_uses_build_skb(struct ice_ring *ring)
	314	{
	315	return !!(ring->flags & ICE_RX_FLAGS_RING_BUILD_SKB);
	316	}
	317
	318	static inline void ice_set_ring_build_skb_ena(struct ice_ring *ring)
	319	{
	320	ring->flags \|= ICE_RX_FLAGS_RING_BUILD_SKB;
	321	}
	322
	323	static inline void ice_clear_ring_build_skb_ena(struct ice_ring *ring)
	324	{
	325	ring->flags &= ~ICE_RX_FLAGS_RING_BUILD_SKB;
	326	}
	327
efc2214b MF	328	static inline bool ice_ring_is_xdp(struct ice_ring *ring)
	329	{
	330	return !!(ring->flags & ICE_TX_FLAGS_RING_XDP);
	331	}
	332
3a858ba3	333	struct ice_ring_container {
63f545ed	334	/* head of linked-list of rings */
3a858ba3	335	struct ice_ring *ring;
cdf1f1f1	336	struct dim dim; /* data for net_dim algorithm */
8244dd2d	337	u16 itr_idx; /* index in the interrupt vector */
d59684a0 JB	338	/* this matches the maximum number of ITR bits, but in usec
d59684a0 JB	339	* values, so it is shifted left one bit (bit zero is ignored)
63f545ed	340	*/
d59684a0 JB	341	u16 itr_setting:13;
	342	u16 itr_reserved:2;
	343	u16 itr_mode:1;
3a858ba3 AV	344	};
3a858ba3 AV	345
61dc79ce MS	346	struct ice_coalesce_stored {
	347	u16 itr_tx;
	348	u16 itr_rx;
	349	u8 intrl;
2ec56385 PSJ	350	u8 tx_valid;
2ec56385 PSJ	351	u8 rx_valid;
61dc79ce MS	352	};
61dc79ce MS	353
3a858ba3 AV	354	/* iterator for handling rings in ring container */
	355	#define ice_for_each_ring(pos, head) \
	356	for (pos = (head).ring; pos; pos = pos->next)
	357
7237f5b0 MF	358	static inline unsigned int ice_rx_pg_order(struct ice_ring *ring)
	359	{
	360	#if (PAGE_SIZE < 8192)
	361	if (ring->rx_buf_len > (PAGE_SIZE / 2))
	362	return 1;
	363	#endif
	364	return 0;
	365	}
	366
	367	#define ice_rx_pg_size(_ring) (PAGE_SIZE << ice_rx_pg_order(_ring))
	368
2d4238f5 KK	369	union ice_32b_rx_flex_desc;
2d4238f5 KK	370
cdedef59	371	bool ice_alloc_rx_bufs(struct ice_ring *rxr, u16 cleaned_count);
2b245cb2	372	netdev_tx_t ice_start_xmit(struct sk_buff skb, struct net_device netdev);
2a87bd73 DE	373	u16
	374	ice_select_queue(struct net_device dev, struct sk_buff skb,
	375	struct net_device *sb_dev);
cdedef59 AV	376	void ice_clean_tx_ring(struct ice_ring *tx_ring);
	377	void ice_clean_rx_ring(struct ice_ring *rx_ring);
	378	int ice_setup_tx_ring(struct ice_ring *tx_ring);
	379	int ice_setup_rx_ring(struct ice_ring *rx_ring);
	380	void ice_free_tx_ring(struct ice_ring *tx_ring);
	381	void ice_free_rx_ring(struct ice_ring *rx_ring);
2b245cb2	382	int ice_napi_poll(struct napi_struct *napi, int budget);
cac2a27c HT	383	int
	384	ice_prgm_fdir_fltr(struct ice_vsi vsi, struct ice_fltr_desc fdir_desc,
	385	u8 *raw_packet);
148beb61 HT	386	int ice_clean_rx_irq(struct ice_ring *rx_ring, int budget);
148beb61 HT	387	void ice_clean_ctrl_tx_irq(struct ice_ring *tx_ring);
940b61af	388	#endif /* _ICE_TXRX_H_ */