Commit | Line | Data |
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940b61af AV |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* Copyright (c) 2018, Intel Corporation. */ | |
3 | ||
4 | #ifndef _ICE_TXRX_H_ | |
5 | #define _ICE_TXRX_H_ | |
6 | ||
2d4238f5 KK |
7 | #include "ice_type.h" |
8 | ||
940b61af | 9 | #define ICE_DFLT_IRQ_WORK 256 |
7237f5b0 | 10 | #define ICE_RXBUF_3072 3072 |
cdedef59 | 11 | #define ICE_RXBUF_2048 2048 |
c61bcebd | 12 | #define ICE_RXBUF_1664 1664 |
7237f5b0 | 13 | #define ICE_RXBUF_1536 1536 |
cdedef59 | 14 | #define ICE_MAX_CHAINED_RX_BUFS 5 |
2b245cb2 AV |
15 | #define ICE_MAX_BUF_TXD 8 |
16 | #define ICE_MIN_TX_LEN 17 | |
c61bcebd | 17 | #define ICE_MAX_FRAME_LEGACY_RX 8320 |
2b245cb2 AV |
18 | |
19 | /* The size limit for a transmit buffer in a descriptor is (16K - 1). | |
20 | * In order to align with the read requests we will align the value to | |
21 | * the nearest 4K which represents our maximum read request size. | |
22 | */ | |
23 | #define ICE_MAX_READ_REQ_SIZE 4096 | |
24 | #define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1) | |
25 | #define ICE_MAX_DATA_PER_TXD_ALIGNED \ | |
26 | (~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD) | |
27 | ||
cdedef59 AV |
28 | #define ICE_MAX_TXQ_PER_TXQG 128 |
29 | ||
59bb0808 MF |
30 | /* Attempt to maximize the headroom available for incoming frames. We use a 2K |
31 | * buffer for MTUs <= 1500 and need 1536/1534 to store the data for the frame. | |
32 | * This leaves us with 512 bytes of room. From that we need to deduct the | |
33 | * space needed for the shared info and the padding needed to IP align the | |
34 | * frame. | |
35 | * | |
36 | * Note: For cache line sizes 256 or larger this value is going to end | |
4ee656bb TN |
37 | * up negative. In these cases we should fall back to the legacy |
38 | * receive path. | |
59bb0808 MF |
39 | */ |
40 | #if (PAGE_SIZE < 8192) | |
41 | #define ICE_2K_TOO_SMALL_WITH_PADDING \ | |
22bef5e7 JB |
42 | ((unsigned int)(NET_SKB_PAD + ICE_RXBUF_1536) > \ |
43 | SKB_WITH_OVERHEAD(ICE_RXBUF_2048)) | |
59bb0808 MF |
44 | |
45 | /** | |
46 | * ice_compute_pad - compute the padding | |
b50f7bca | 47 | * @rx_buf_len: buffer length |
59bb0808 MF |
48 | * |
49 | * Figure out the size of half page based on given buffer length and | |
50 | * then subtract the skb_shared_info followed by subtraction of the | |
51 | * actual buffer length; this in turn results in the actual space that | |
52 | * is left for padding usage | |
53 | */ | |
54 | static inline int ice_compute_pad(int rx_buf_len) | |
55 | { | |
56 | int half_page_size; | |
57 | ||
58 | half_page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); | |
59 | return SKB_WITH_OVERHEAD(half_page_size) - rx_buf_len; | |
60 | } | |
61 | ||
62 | /** | |
63 | * ice_skb_pad - determine the padding that we can supply | |
64 | * | |
65 | * Figure out the right Rx buffer size and based on that calculate the | |
66 | * padding | |
67 | */ | |
68 | static inline int ice_skb_pad(void) | |
69 | { | |
70 | int rx_buf_len; | |
71 | ||
72 | /* If a 2K buffer cannot handle a standard Ethernet frame then | |
73 | * optimize padding for a 3K buffer instead of a 1.5K buffer. | |
74 | * | |
75 | * For a 3K buffer we need to add enough padding to allow for | |
76 | * tailroom due to NET_IP_ALIGN possibly shifting us out of | |
77 | * cache-line alignment. | |
78 | */ | |
79 | if (ICE_2K_TOO_SMALL_WITH_PADDING) | |
80 | rx_buf_len = ICE_RXBUF_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN); | |
81 | else | |
82 | rx_buf_len = ICE_RXBUF_1536; | |
83 | ||
84 | /* if needed make room for NET_IP_ALIGN */ | |
85 | rx_buf_len -= NET_IP_ALIGN; | |
86 | ||
87 | return ice_compute_pad(rx_buf_len); | |
88 | } | |
89 | ||
90 | #define ICE_SKB_PAD ice_skb_pad() | |
91 | #else | |
92 | #define ICE_2K_TOO_SMALL_WITH_PADDING false | |
93 | #define ICE_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) | |
94 | #endif | |
95 | ||
c585ea42 BC |
96 | /* We are assuming that the cache line is always 64 Bytes here for ice. |
97 | * In order to make sure that is a correct assumption there is a check in probe | |
98 | * to print a warning if the read from GLPCI_CNF2 tells us that the cache line | |
99 | * size is 128 bytes. We do it this way because we do not want to read the | |
100 | * GLPCI_CNF2 register or a variable containing the value on every pass through | |
101 | * the Tx path. | |
102 | */ | |
103 | #define ICE_CACHE_LINE_BYTES 64 | |
104 | #define ICE_DESCS_PER_CACHE_LINE (ICE_CACHE_LINE_BYTES / \ | |
105 | sizeof(struct ice_tx_desc)) | |
106 | #define ICE_DESCS_FOR_CTX_DESC 1 | |
107 | #define ICE_DESCS_FOR_SKB_DATA_PTR 1 | |
108 | /* Tx descriptors needed, worst case */ | |
109 | #define DESC_NEEDED (MAX_SKB_FRAGS + ICE_DESCS_FOR_CTX_DESC + \ | |
110 | ICE_DESCS_PER_CACHE_LINE + ICE_DESCS_FOR_SKB_DATA_PTR) | |
cdedef59 | 111 | #define ICE_DESC_UNUSED(R) \ |
22bef5e7 JB |
112 | (u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ |
113 | (R)->next_to_clean - (R)->next_to_use - 1) | |
cdedef59 | 114 | |
2fba7dc5 MF |
115 | #define ICE_RX_DESC_UNUSED(R) \ |
116 | ((((R)->first_desc > (R)->next_to_use) ? 0 : (R)->count) + \ | |
117 | (R)->first_desc - (R)->next_to_use - 1) | |
118 | ||
3876ff52 MF |
119 | #define ICE_RING_QUARTER(R) ((R)->count >> 2) |
120 | ||
d76a60ba AV |
121 | #define ICE_TX_FLAGS_TSO BIT(0) |
122 | #define ICE_TX_FLAGS_HW_VLAN BIT(1) | |
123 | #define ICE_TX_FLAGS_SW_VLAN BIT(2) | |
aa1d3faf | 124 | /* Free, was ICE_TX_FLAGS_DUMMY_PKT */ |
ea9b847c | 125 | #define ICE_TX_FLAGS_TSYN BIT(4) |
a4e82a81 TN |
126 | #define ICE_TX_FLAGS_IPV4 BIT(5) |
127 | #define ICE_TX_FLAGS_IPV6 BIT(6) | |
128 | #define ICE_TX_FLAGS_TUNNEL BIT(7) | |
0d54d8f7 | 129 | #define ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN BIT(8) |
d76a60ba | 130 | |
efc2214b MF |
131 | #define ICE_XDP_PASS 0 |
132 | #define ICE_XDP_CONSUMED BIT(0) | |
133 | #define ICE_XDP_TX BIT(1) | |
134 | #define ICE_XDP_REDIR BIT(2) | |
50ae0664 | 135 | #define ICE_XDP_EXIT BIT(3) |
2fba7dc5 | 136 | #define ICE_SKB_CONSUMED ICE_XDP_CONSUMED |
efc2214b | 137 | |
a65f71fe MF |
138 | #define ICE_RX_DMA_ATTR \ |
139 | (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) | |
140 | ||
efc2214b MF |
141 | #define ICE_ETH_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)) |
142 | ||
143 | #define ICE_TXD_LAST_DESC_CMD (ICE_TX_DESC_CMD_EOP | ICE_TX_DESC_CMD_RS) | |
144 | ||
aa1d3faf AL |
145 | /** |
146 | * enum ice_tx_buf_type - type of &ice_tx_buf to act on Tx completion | |
147 | * @ICE_TX_BUF_EMPTY: unused OR XSk frame, no action required | |
148 | * @ICE_TX_BUF_DUMMY: dummy Flow Director packet, unmap and kfree() | |
149 | * @ICE_TX_BUF_FRAG: mapped skb OR &xdp_buff frag, only unmap DMA | |
150 | * @ICE_TX_BUF_SKB: &sk_buff, unmap and consume_skb(), update stats | |
151 | * @ICE_TX_BUF_XDP_TX: &xdp_buff, unmap and page_frag_free(), stats | |
055d0920 | 152 | * @ICE_TX_BUF_XDP_XMIT: &xdp_frame, unmap and xdp_return_frame(), stats |
aa1d3faf AL |
153 | * @ICE_TX_BUF_XSK_TX: &xdp_buff on XSk queue, xsk_buff_free(), stats |
154 | */ | |
155 | enum ice_tx_buf_type { | |
156 | ICE_TX_BUF_EMPTY = 0U, | |
157 | ICE_TX_BUF_DUMMY, | |
158 | ICE_TX_BUF_FRAG, | |
159 | ICE_TX_BUF_SKB, | |
160 | ICE_TX_BUF_XDP_TX, | |
055d0920 | 161 | ICE_TX_BUF_XDP_XMIT, |
aa1d3faf AL |
162 | ICE_TX_BUF_XSK_TX, |
163 | }; | |
164 | ||
cdedef59 | 165 | struct ice_tx_buf { |
3246a107 MF |
166 | union { |
167 | struct ice_tx_desc *next_to_watch; | |
168 | u32 rs_idx; | |
169 | }; | |
efc2214b | 170 | union { |
aa1d3faf AL |
171 | void *raw_buf; /* used for XDP_TX and FDir rules */ |
172 | struct sk_buff *skb; /* used for .ndo_start_xmit() */ | |
055d0920 | 173 | struct xdp_frame *xdpf; /* used for .ndo_xdp_xmit() */ |
aa1d3faf | 174 | struct xdp_buff *xdp; /* used for XDP_TX ZC */ |
efc2214b | 175 | }; |
cdedef59 | 176 | unsigned int bytecount; |
3246a107 MF |
177 | union { |
178 | unsigned int gso_segs; | |
aa1d3faf | 179 | unsigned int nr_frags; /* used for mbuf XDP */ |
3246a107 | 180 | }; |
9113302b JS |
181 | u32 tx_flags:12; |
182 | u32 type:4; /* &ice_tx_buf_type */ | |
183 | u32 vid:16; | |
cdedef59 | 184 | DEFINE_DMA_UNMAP_LEN(len); |
65124bbf | 185 | DEFINE_DMA_UNMAP_ADDR(dma); |
cdedef59 AV |
186 | }; |
187 | ||
d76a60ba | 188 | struct ice_tx_offload_params { |
65124bbf | 189 | u64 cd_qw1; |
e72bba21 | 190 | struct ice_tx_ring *tx_ring; |
d76a60ba AV |
191 | u32 td_cmd; |
192 | u32 td_offset; | |
193 | u32 td_l2tag1; | |
d76a60ba | 194 | u32 cd_tunnel_params; |
65124bbf JB |
195 | u16 cd_l2tag2; |
196 | u8 header_len; | |
d76a60ba AV |
197 | }; |
198 | ||
cdedef59 | 199 | struct ice_rx_buf { |
57f7f8b6 MK |
200 | dma_addr_t dma; |
201 | struct page *page; | |
202 | unsigned int page_offset; | |
ac075339 | 203 | unsigned int pgcnt; |
1dc1a7e7 | 204 | unsigned int act; |
ac075339 | 205 | unsigned int pagecnt_bias; |
cdedef59 | 206 | }; |
940b61af | 207 | |
2b245cb2 AV |
208 | struct ice_q_stats { |
209 | u64 pkts; | |
210 | u64 bytes; | |
211 | }; | |
212 | ||
213 | struct ice_txq_stats { | |
214 | u64 restart_q; | |
215 | u64 tx_busy; | |
216 | u64 tx_linearize; | |
b3969fd7 | 217 | int prev_pkt; /* negative if no pending Tx descriptors */ |
2b245cb2 AV |
218 | }; |
219 | ||
220 | struct ice_rxq_stats { | |
221 | u64 non_eop_descs; | |
222 | u64 alloc_page_failed; | |
223 | u64 alloc_buf_failed; | |
2b245cb2 AV |
224 | }; |
225 | ||
288ecf49 BM |
226 | struct ice_ring_stats { |
227 | struct rcu_head rcu; /* to avoid race on free */ | |
228 | struct ice_q_stats stats; | |
229 | struct u64_stats_sync syncp; | |
230 | union { | |
231 | struct ice_txq_stats tx_stats; | |
232 | struct ice_rxq_stats rx_stats; | |
233 | }; | |
234 | }; | |
235 | ||
634da4c1 BB |
236 | enum ice_ring_state_t { |
237 | ICE_TX_XPS_INIT_DONE, | |
238 | ICE_TX_NBITS, | |
239 | }; | |
240 | ||
940b61af AV |
241 | /* this enum matches hardware bits and is meant to be used by DYN_CTLN |
242 | * registers and QINT registers or more generally anywhere in the manual | |
243 | * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any | |
244 | * register but instead is a special value meaning "don't update" ITR0/1/2. | |
245 | */ | |
246 | enum ice_dyn_idx_t { | |
247 | ICE_IDX_ITR0 = 0, | |
248 | ICE_IDX_ITR1 = 1, | |
249 | ICE_IDX_ITR2 = 2, | |
250 | ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ | |
251 | }; | |
252 | ||
cdedef59 AV |
253 | /* Header split modes defined by DTYPE field of Rx RLAN context */ |
254 | enum ice_rx_dtype { | |
255 | ICE_RX_DTYPE_NO_SPLIT = 0, | |
256 | ICE_RX_DTYPE_HEADER_SPLIT = 1, | |
257 | ICE_RX_DTYPE_SPLIT_ALWAYS = 2, | |
258 | }; | |
259 | ||
9031d5f4 LZ |
260 | struct ice_pkt_ctx { |
261 | u64 cached_phctime; | |
714ed949 | 262 | __be16 vlan_proto; |
9031d5f4 LZ |
263 | }; |
264 | ||
d951c14a LZ |
265 | struct ice_xdp_buff { |
266 | struct xdp_buff xdp_buff; | |
267 | const union ice_32b_rx_flex_desc *eop_desc; | |
9031d5f4 | 268 | const struct ice_pkt_ctx *pkt_ctx; |
d951c14a LZ |
269 | }; |
270 | ||
271 | /* Required for compatibility with xdp_buffs from xsk_pool */ | |
272 | static_assert(offsetof(struct ice_xdp_buff, xdp_buff) == 0); | |
273 | ||
940b61af AV |
274 | /* indices into GLINT_ITR registers */ |
275 | #define ICE_RX_ITR ICE_IDX_ITR0 | |
cdedef59 | 276 | #define ICE_TX_ITR ICE_IDX_ITR1 |
63f545ed | 277 | #define ICE_ITR_8K 124 |
d2b464a7 | 278 | #define ICE_ITR_20K 50 |
d59684a0 JB |
279 | #define ICE_ITR_MAX 8160 /* 0x1FE0 */ |
280 | #define ICE_DFLT_TX_ITR ICE_ITR_20K | |
281 | #define ICE_DFLT_RX_ITR ICE_ITR_20K | |
282 | enum ice_dynamic_itr { | |
283 | ITR_STATIC = 0, | |
284 | ITR_DYNAMIC = 1 | |
285 | }; | |
286 | ||
287 | #define ITR_IS_DYNAMIC(rc) ((rc)->itr_mode == ITR_DYNAMIC) | |
92414f32 | 288 | #define ICE_ITR_GRAN_S 1 /* ITR granularity is always 2us */ |
70457520 | 289 | #define ICE_ITR_GRAN_US BIT(ICE_ITR_GRAN_S) |
63f545ed | 290 | #define ICE_ITR_MASK 0x1FFE /* ITR register value alignment mask */ |
840f8ad0 | 291 | #define ITR_REG_ALIGN(setting) ((setting) & ICE_ITR_MASK) |
940b61af | 292 | |
9e4ab4c2 | 293 | #define ICE_DFLT_INTRL 0 |
b9c8bb06 | 294 | #define ICE_MAX_INTRL 236 |
940b61af | 295 | |
2ab28bb0 BC |
296 | #define ICE_IN_WB_ON_ITR_MODE 255 |
297 | /* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows | |
298 | * setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also, | |
299 | * set the write-back latency to the usecs passed in. | |
300 | */ | |
301 | #define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx) \ | |
302 | ((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \ | |
303 | GLINT_DYN_CTL_INTERVAL_M) | \ | |
304 | (((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \ | |
305 | GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \ | |
306 | GLINT_DYN_CTL_WB_ON_ITR_M) | |
307 | ||
cdedef59 AV |
308 | /* Legacy or Advanced Mode Queue */ |
309 | #define ICE_TX_ADVANCED 0 | |
310 | #define ICE_TX_LEGACY 1 | |
311 | ||
3a858ba3 | 312 | /* descriptor ring, associated with a VSI */ |
e72bba21 | 313 | struct ice_rx_ring { |
65124bbf | 314 | /* CL1 - 1st cacheline starts here */ |
cdedef59 | 315 | void *desc; /* Descriptor ring memory */ |
3a858ba3 AV |
316 | struct device *dev; /* Used for DMA mapping */ |
317 | struct net_device *netdev; /* netdev ring maps to */ | |
318 | struct ice_vsi *vsi; /* Backreference to associated VSI */ | |
319 | struct ice_q_vector *q_vector; /* Backreference to associated vector */ | |
cdedef59 | 320 | u8 __iomem *tail; |
2fba7dc5 MF |
321 | u16 q_index; /* Queue number of ring */ |
322 | ||
323 | u16 count; /* Number of descriptors */ | |
324 | u16 reg_idx; /* HW register index of the ring */ | |
325 | u16 next_to_alloc; | |
d951c14a | 326 | |
cdedef59 | 327 | union { |
cdedef59 | 328 | struct ice_rx_buf *rx_buf; |
57f7f8b6 | 329 | struct xdp_buff **xdp_buf; |
cdedef59 | 330 | }; |
d951c14a LZ |
331 | /* CL2 - 2nd cacheline starts here */ |
332 | union { | |
333 | struct ice_xdp_buff xdp_ext; | |
334 | struct xdp_buff xdp; | |
335 | }; | |
e72bba21 | 336 | /* CL3 - 3rd cacheline starts here */ |
9031d5f4 LZ |
337 | union { |
338 | struct ice_pkt_ctx pkt_ctx; | |
714ed949 LZ |
339 | struct { |
340 | u64 cached_phctime; | |
341 | __be16 vlan_proto; | |
342 | }; | |
9031d5f4 | 343 | }; |
2fba7dc5 MF |
344 | struct bpf_prog *xdp_prog; |
345 | u16 rx_offset; | |
cdedef59 AV |
346 | |
347 | /* used in interrupt processing */ | |
348 | u16 next_to_use; | |
349 | u16 next_to_clean; | |
2fba7dc5 | 350 | u16 first_desc; |
2b245cb2 AV |
351 | |
352 | /* stats structs */ | |
288ecf49 | 353 | struct ice_ring_stats *ring_stats; |
2b245cb2 | 354 | |
3a858ba3 | 355 | struct rcu_head rcu; /* to avoid race on free */ |
2fba7dc5 | 356 | /* CL4 - 4th cacheline starts here */ |
0754d65b | 357 | struct ice_channel *ch; |
eb087cd8 | 358 | struct ice_tx_ring *xdp_ring; |
d951c14a | 359 | struct ice_rx_ring *next; /* pointer to next ring in q_vector */ |
1742b3d5 | 360 | struct xsk_buff_pool *xsk_pool; |
ad2047cf | 361 | u32 nr_frags; |
e72bba21 | 362 | dma_addr_t dma; /* physical address of ring */ |
2fba7dc5 | 363 | u16 rx_buf_len; |
e72bba21 MF |
364 | u8 dcb_tc; /* Traffic class of ring */ |
365 | u8 ptp_rx; | |
dddd406d JB |
366 | #define ICE_RX_FLAGS_RING_BUILD_SKB BIT(1) |
367 | #define ICE_RX_FLAGS_CRC_STRIP_DIS BIT(2) | |
efc2214b | 368 | u8 flags; |
2fba7dc5 MF |
369 | /* CL5 - 5th cacheline starts here */ |
370 | struct xdp_rxq_info xdp_rxq; | |
e72bba21 MF |
371 | } ____cacheline_internodealigned_in_smp; |
372 | ||
373 | struct ice_tx_ring { | |
374 | /* CL1 - 1st cacheline starts here */ | |
375 | struct ice_tx_ring *next; /* pointer to next ring in q_vector */ | |
376 | void *desc; /* Descriptor ring memory */ | |
377 | struct device *dev; /* Used for DMA mapping */ | |
378 | u8 __iomem *tail; | |
379 | struct ice_tx_buf *tx_buf; | |
380 | struct ice_q_vector *q_vector; /* Backreference to associated vector */ | |
381 | struct net_device *netdev; /* netdev ring maps to */ | |
382 | struct ice_vsi *vsi; /* Backreference to associated VSI */ | |
383 | /* CL2 - 2nd cacheline starts here */ | |
65124bbf | 384 | dma_addr_t dma; /* physical address of ring */ |
9610bd98 | 385 | struct xsk_buff_pool *xsk_pool; |
e72bba21 MF |
386 | u16 next_to_use; |
387 | u16 next_to_clean; | |
9610bd98 MF |
388 | u16 q_handle; /* Queue handle per TC */ |
389 | u16 reg_idx; /* HW register index of the ring */ | |
e72bba21 MF |
390 | u16 count; /* Number of descriptors */ |
391 | u16 q_index; /* Queue number of ring */ | |
3246a107 | 392 | u16 xdp_tx_active; |
e72bba21 | 393 | /* stats structs */ |
288ecf49 | 394 | struct ice_ring_stats *ring_stats; |
e72bba21 MF |
395 | /* CL3 - 3rd cacheline starts here */ |
396 | struct rcu_head rcu; /* to avoid race on free */ | |
397 | DECLARE_BITMAP(xps_state, ICE_TX_NBITS); /* XPS Config State */ | |
0754d65b | 398 | struct ice_channel *ch; |
e72bba21 | 399 | struct ice_ptp_tx *tx_tstamps; |
22bf877e | 400 | spinlock_t tx_lock; |
65124bbf | 401 | u32 txq_teid; /* Added Tx queue TEID */ |
126cdfe1 | 402 | /* CL4 - 4th cacheline starts here */ |
e72bba21 | 403 | #define ICE_TX_FLAGS_RING_XDP BIT(0) |
0d54d8f7 BC |
404 | #define ICE_TX_FLAGS_RING_VLAN_L2TAG1 BIT(1) |
405 | #define ICE_TX_FLAGS_RING_VLAN_L2TAG2 BIT(2) | |
e72bba21 | 406 | u8 flags; |
65124bbf | 407 | u8 dcb_tc; /* Traffic class of ring */ |
3a858ba3 AV |
408 | } ____cacheline_internodealigned_in_smp; |
409 | ||
e72bba21 | 410 | static inline bool ice_ring_uses_build_skb(struct ice_rx_ring *ring) |
59bb0808 MF |
411 | { |
412 | return !!(ring->flags & ICE_RX_FLAGS_RING_BUILD_SKB); | |
413 | } | |
414 | ||
e72bba21 | 415 | static inline void ice_set_ring_build_skb_ena(struct ice_rx_ring *ring) |
59bb0808 MF |
416 | { |
417 | ring->flags |= ICE_RX_FLAGS_RING_BUILD_SKB; | |
418 | } | |
419 | ||
e72bba21 | 420 | static inline void ice_clear_ring_build_skb_ena(struct ice_rx_ring *ring) |
59bb0808 MF |
421 | { |
422 | ring->flags &= ~ICE_RX_FLAGS_RING_BUILD_SKB; | |
423 | } | |
424 | ||
0754d65b KP |
425 | static inline bool ice_ring_ch_enabled(struct ice_tx_ring *ring) |
426 | { | |
427 | return !!ring->ch; | |
428 | } | |
429 | ||
e72bba21 | 430 | static inline bool ice_ring_is_xdp(struct ice_tx_ring *ring) |
efc2214b MF |
431 | { |
432 | return !!(ring->flags & ICE_TX_FLAGS_RING_XDP); | |
433 | } | |
434 | ||
dc23715c MF |
435 | enum ice_container_type { |
436 | ICE_RX_CONTAINER, | |
437 | ICE_TX_CONTAINER, | |
438 | }; | |
439 | ||
3a858ba3 | 440 | struct ice_ring_container { |
63f545ed | 441 | /* head of linked-list of rings */ |
e72bba21 MF |
442 | union { |
443 | struct ice_rx_ring *rx_ring; | |
444 | struct ice_tx_ring *tx_ring; | |
445 | }; | |
cdf1f1f1 | 446 | struct dim dim; /* data for net_dim algorithm */ |
8244dd2d | 447 | u16 itr_idx; /* index in the interrupt vector */ |
d59684a0 JB |
448 | /* this matches the maximum number of ITR bits, but in usec |
449 | * values, so it is shifted left one bit (bit zero is ignored) | |
63f545ed | 450 | */ |
bf13502e MW |
451 | union { |
452 | struct { | |
453 | u16 itr_setting:13; | |
454 | u16 itr_reserved:2; | |
455 | u16 itr_mode:1; | |
456 | }; | |
457 | u16 itr_settings; | |
458 | }; | |
dc23715c | 459 | enum ice_container_type type; |
3a858ba3 AV |
460 | }; |
461 | ||
61dc79ce MS |
462 | struct ice_coalesce_stored { |
463 | u16 itr_tx; | |
464 | u16 itr_rx; | |
465 | u8 intrl; | |
2ec56385 PSJ |
466 | u8 tx_valid; |
467 | u8 rx_valid; | |
61dc79ce MS |
468 | }; |
469 | ||
3a858ba3 | 470 | /* iterator for handling rings in ring container */ |
e72bba21 MF |
471 | #define ice_for_each_rx_ring(pos, head) \ |
472 | for (pos = (head).rx_ring; pos; pos = pos->next) | |
473 | ||
474 | #define ice_for_each_tx_ring(pos, head) \ | |
475 | for (pos = (head).tx_ring; pos; pos = pos->next) | |
3a858ba3 | 476 | |
e72bba21 | 477 | static inline unsigned int ice_rx_pg_order(struct ice_rx_ring *ring) |
7237f5b0 MF |
478 | { |
479 | #if (PAGE_SIZE < 8192) | |
480 | if (ring->rx_buf_len > (PAGE_SIZE / 2)) | |
481 | return 1; | |
482 | #endif | |
483 | return 0; | |
484 | } | |
485 | ||
486 | #define ice_rx_pg_size(_ring) (PAGE_SIZE << ice_rx_pg_order(_ring)) | |
487 | ||
2d4238f5 KK |
488 | union ice_32b_rx_flex_desc; |
489 | ||
2fba7dc5 | 490 | bool ice_alloc_rx_bufs(struct ice_rx_ring *rxr, unsigned int cleaned_count); |
2b245cb2 | 491 | netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev); |
2a87bd73 DE |
492 | u16 |
493 | ice_select_queue(struct net_device *dev, struct sk_buff *skb, | |
494 | struct net_device *sb_dev); | |
e72bba21 MF |
495 | void ice_clean_tx_ring(struct ice_tx_ring *tx_ring); |
496 | void ice_clean_rx_ring(struct ice_rx_ring *rx_ring); | |
497 | int ice_setup_tx_ring(struct ice_tx_ring *tx_ring); | |
498 | int ice_setup_rx_ring(struct ice_rx_ring *rx_ring); | |
499 | void ice_free_tx_ring(struct ice_tx_ring *tx_ring); | |
500 | void ice_free_rx_ring(struct ice_rx_ring *rx_ring); | |
2b245cb2 | 501 | int ice_napi_poll(struct napi_struct *napi, int budget); |
cac2a27c HT |
502 | int |
503 | ice_prgm_fdir_fltr(struct ice_vsi *vsi, struct ice_fltr_desc *fdir_desc, | |
504 | u8 *raw_packet); | |
e72bba21 MF |
505 | int ice_clean_rx_irq(struct ice_rx_ring *rx_ring, int budget); |
506 | void ice_clean_ctrl_tx_irq(struct ice_tx_ring *tx_ring); | |
940b61af | 507 | #endif /* _ICE_TXRX_H_ */ |