projects / linux-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 7ec59eea AV |
1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* Copyright (c) 2018, Intel Corporation. */ | |
| 3 | ||
| 4 | #ifndef _ICE_ADMINQ_CMD_H_ | |
| 5 | #define _ICE_ADMINQ_CMD_H_ | |
| 6 | ||
| 7 | /* This header file defines the Admin Queue commands, error codes and | |
| 8 | * descriptor format. It is shared between Firmware and Software. | |
| 9 | */ | |
| 10 | ||
| 9daf8208 | 11 | #define ICE_MAX_VSI 768 |
| 9c20346b | 12 | #define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9 |
| 3a858ba3 | 13 | #define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728 |
| 9c20346b | 14 | |
| 7ec59eea AV |
15 | struct ice_aqc_generic { |
| 16 | __le32 param0; | |
| 17 | __le32 param1; | |
| 18 | __le32 addr_high; | |
| 19 | __le32 addr_low; | |
| 20 | }; | |
| 21 | ||
| 22 | /* Get version (direct 0x0001) */ | |
| 23 | struct ice_aqc_get_ver { | |
| 24 | __le32 rom_ver; | |
| 25 | __le32 fw_build; | |
| 26 | u8 fw_branch; | |
| 27 | u8 fw_major; | |
| 28 | u8 fw_minor; | |
| 29 | u8 fw_patch; | |
| 30 | u8 api_branch; | |
| 31 | u8 api_major; | |
| 32 | u8 api_minor; | |
| 33 | u8 api_patch; | |
| 34 | }; | |
| 35 | ||
| 36 | /* Queue Shutdown (direct 0x0003) */ | |
| 37 | struct ice_aqc_q_shutdown { | |
| 38 | #define ICE_AQC_DRIVER_UNLOADING BIT(0) | |
| 39 | __le32 driver_unloading; | |
| 40 | u8 reserved[12]; | |
| 41 | }; | |
| 42 | ||
| f31e4b6f AV |
43 | /* Request resource ownership (direct 0x0008) |
| 44 | * Release resource ownership (direct 0x0009) | |
| 45 | */ | |
| 46 | struct ice_aqc_req_res { | |
| 47 | __le16 res_id; | |
| 48 | #define ICE_AQC_RES_ID_NVM 1 | |
| 49 | #define ICE_AQC_RES_ID_SDP 2 | |
| 50 | #define ICE_AQC_RES_ID_CHNG_LOCK 3 | |
| 51 | #define ICE_AQC_RES_ID_GLBL_LOCK 4 | |
| 52 | __le16 access_type; | |
| 53 | #define ICE_AQC_RES_ACCESS_READ 1 | |
| 54 | #define ICE_AQC_RES_ACCESS_WRITE 2 | |
| 55 | ||
| 56 | /* Upon successful completion, FW writes this value and driver is | |
| 57 | * expected to release resource before timeout. This value is provided | |
| 58 | * in milliseconds. | |
| 59 | */ | |
| 60 | __le32 timeout; | |
| 61 | #define ICE_AQ_RES_NVM_READ_DFLT_TIMEOUT_MS 3000 | |
| 62 | #define ICE_AQ_RES_NVM_WRITE_DFLT_TIMEOUT_MS 180000 | |
| 63 | #define ICE_AQ_RES_CHNG_LOCK_DFLT_TIMEOUT_MS 1000 | |
| 64 | #define ICE_AQ_RES_GLBL_LOCK_DFLT_TIMEOUT_MS 3000 | |
| 65 | /* For SDP: pin id of the SDP */ | |
| 66 | __le32 res_number; | |
| 67 | /* Status is only used for ICE_AQC_RES_ID_GLBL_LOCK */ | |
| 68 | __le16 status; | |
| 69 | #define ICE_AQ_RES_GLBL_SUCCESS 0 | |
| 70 | #define ICE_AQ_RES_GLBL_IN_PROG 1 | |
| 71 | #define ICE_AQ_RES_GLBL_DONE 2 | |
| 72 | u8 reserved[2]; | |
| 73 | }; | |
| 74 | ||
| 9c20346b AV |
75 | /* Get function capabilities (indirect 0x000A) |
| 76 | * Get device capabilities (indirect 0x000B) | |
| 77 | */ | |
| 78 | struct ice_aqc_list_caps { | |
| 79 | u8 cmd_flags; | |
| 80 | u8 pf_index; | |
| 81 | u8 reserved[2]; | |
| 82 | __le32 count; | |
| 83 | __le32 addr_high; | |
| 84 | __le32 addr_low; | |
| 85 | }; | |
| 86 | ||
| 87 | /* Device/Function buffer entry, repeated per reported capability */ | |
| 88 | struct ice_aqc_list_caps_elem { | |
| 89 | __le16 cap; | |
| 90 | #define ICE_AQC_CAPS_VSI 0x0017 | |
| 91 | #define ICE_AQC_CAPS_RSS 0x0040 | |
| 92 | #define ICE_AQC_CAPS_RXQS 0x0041 | |
| 93 | #define ICE_AQC_CAPS_TXQS 0x0042 | |
| 94 | #define ICE_AQC_CAPS_MSIX 0x0043 | |
| 95 | #define ICE_AQC_CAPS_MAX_MTU 0x0047 | |
| 96 | ||
| 97 | u8 major_ver; | |
| 98 | u8 minor_ver; | |
| 99 | /* Number of resources described by this capability */ | |
| 100 | __le32 number; | |
| 101 | /* Only meaningful for some types of resources */ | |
| 102 | __le32 logical_id; | |
| 103 | /* Only meaningful for some types of resources */ | |
| 104 | __le32 phys_id; | |
| 105 | __le64 rsvd1; | |
| 106 | __le64 rsvd2; | |
| 107 | }; | |
| 108 | ||
| dc49c772 AV |
109 | /* Manage MAC address, read command - indirect (0x0107) |
| 110 | * This struct is also used for the response | |
| 111 | */ | |
| 112 | struct ice_aqc_manage_mac_read { | |
| 113 | __le16 flags; /* Zeroed by device driver */ | |
| 114 | #define ICE_AQC_MAN_MAC_LAN_ADDR_VALID BIT(4) | |
| 115 | #define ICE_AQC_MAN_MAC_SAN_ADDR_VALID BIT(5) | |
| 116 | #define ICE_AQC_MAN_MAC_PORT_ADDR_VALID BIT(6) | |
| 117 | #define ICE_AQC_MAN_MAC_WOL_ADDR_VALID BIT(7) | |
| 118 | #define ICE_AQC_MAN_MAC_READ_S 4 | |
| 119 | #define ICE_AQC_MAN_MAC_READ_M (0xF << ICE_AQC_MAN_MAC_READ_S) | |
| 120 | u8 lport_num; | |
| 121 | u8 lport_num_valid; | |
| 122 | #define ICE_AQC_MAN_MAC_PORT_NUM_IS_VALID BIT(0) | |
| 123 | u8 num_addr; /* Used in response */ | |
| 124 | u8 reserved[3]; | |
| 125 | __le32 addr_high; | |
| 126 | __le32 addr_low; | |
| 127 | }; | |
| 128 | ||
| 129 | /* Response buffer format for manage MAC read command */ | |
| 130 | struct ice_aqc_manage_mac_read_resp { | |
| 131 | u8 lport_num; | |
| 132 | u8 addr_type; | |
| 133 | #define ICE_AQC_MAN_MAC_ADDR_TYPE_LAN 0 | |
| 134 | #define ICE_AQC_MAN_MAC_ADDR_TYPE_WOL 1 | |
| 135 | u8 mac_addr[ETH_ALEN]; | |
| 136 | }; | |
| 137 | ||
| f31e4b6f AV |
138 | /* Clear PXE Command and response (direct 0x0110) */ |
| 139 | struct ice_aqc_clear_pxe { | |
| 140 | u8 rx_cnt; | |
| 141 | #define ICE_AQC_CLEAR_PXE_RX_CNT 0x2 | |
| 142 | u8 reserved[15]; | |
| 143 | }; | |
| 144 | ||
| 9c20346b AV |
145 | /* Get switch configuration (0x0200) */ |
| 146 | struct ice_aqc_get_sw_cfg { | |
| 147 | /* Reserved for command and copy of request flags for response */ | |
| 148 | __le16 flags; | |
| 149 | /* First desc in case of command and next_elem in case of response | |
| 150 | * In case of response, if it is not zero, means all the configuration | |
| 151 | * was not returned and new command shall be sent with this value in | |
| 152 | * the 'first desc' field | |
| 153 | */ | |
| 154 | __le16 element; | |
| 155 | /* Reserved for command, only used for response */ | |
| 156 | __le16 num_elems; | |
| 157 | __le16 rsvd; | |
| 158 | __le32 addr_high; | |
| 159 | __le32 addr_low; | |
| 160 | }; | |
| 161 | ||
| 162 | /* Each entry in the response buffer is of the following type: */ | |
| 163 | struct ice_aqc_get_sw_cfg_resp_elem { | |
| 164 | /* VSI/Port Number */ | |
| 165 | __le16 vsi_port_num; | |
| 166 | #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S 0 | |
| 167 | #define ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_M \ | |
| 168 | (0x3FF << ICE_AQC_GET_SW_CONF_RESP_VSI_PORT_NUM_S) | |
| 169 | #define ICE_AQC_GET_SW_CONF_RESP_TYPE_S 14 | |
| 170 | #define ICE_AQC_GET_SW_CONF_RESP_TYPE_M (0x3 << ICE_AQC_GET_SW_CONF_RESP_TYPE_S) | |
| 171 | #define ICE_AQC_GET_SW_CONF_RESP_PHYS_PORT 0 | |
| 172 | #define ICE_AQC_GET_SW_CONF_RESP_VIRT_PORT 1 | |
| 173 | #define ICE_AQC_GET_SW_CONF_RESP_VSI 2 | |
| 174 | ||
| 175 | /* SWID VSI/Port belongs to */ | |
| 176 | __le16 swid; | |
| 177 | ||
| 178 | /* Bit 14..0 : PF/VF number VSI belongs to | |
| 179 | * Bit 15 : VF indication bit | |
| 180 | */ | |
| 181 | __le16 pf_vf_num; | |
| 182 | #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S 0 | |
| 183 | #define ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_M \ | |
| 184 | (0x7FFF << ICE_AQC_GET_SW_CONF_RESP_FUNC_NUM_S) | |
| 185 | #define ICE_AQC_GET_SW_CONF_RESP_IS_VF BIT(15) | |
| 186 | }; | |
| 187 | ||
| 188 | /* The response buffer is as follows. Note that the length of the | |
| 189 | * elements array varies with the length of the command response. | |
| 190 | */ | |
| 191 | struct ice_aqc_get_sw_cfg_resp { | |
| 192 | struct ice_aqc_get_sw_cfg_resp_elem elements[1]; | |
| 193 | }; | |
| 194 | ||
| 9daf8208 AV |
195 | /* These resource type defines are used for all switch resource |
| 196 | * commands where a resource type is required, such as: | |
| 197 | * Get Resource Allocation command (indirect 0x0204) | |
| 198 | * Allocate Resources command (indirect 0x0208) | |
| 199 | * Free Resources command (indirect 0x0209) | |
| 200 | * Get Allocated Resource Descriptors Command (indirect 0x020A) | |
| 201 | */ | |
| 202 | #define ICE_AQC_RES_TYPE_VSI_LIST_REP 0x03 | |
| 203 | #define ICE_AQC_RES_TYPE_VSI_LIST_PRUNE 0x04 | |
| 204 | ||
| 205 | /* Allocate Resources command (indirect 0x0208) | |
| 206 | * Free Resources command (indirect 0x0209) | |
| 207 | */ | |
| 208 | struct ice_aqc_alloc_free_res_cmd { | |
| 209 | __le16 num_entries; /* Number of Resource entries */ | |
| 210 | u8 reserved[6]; | |
| 211 | __le32 addr_high; | |
| 212 | __le32 addr_low; | |
| 213 | }; | |
| 214 | ||
| 215 | /* Resource descriptor */ | |
| 216 | struct ice_aqc_res_elem { | |
| 217 | union { | |
| 218 | __le16 sw_resp; | |
| 219 | __le16 flu_resp; | |
| 220 | } e; | |
| 221 | }; | |
| 222 | ||
| 223 | /* Buffer for Allocate/Free Resources commands */ | |
| 224 | struct ice_aqc_alloc_free_res_elem { | |
| 225 | __le16 res_type; /* Types defined above cmd 0x0204 */ | |
| 226 | #define ICE_AQC_RES_TYPE_SHARED_S 7 | |
| 227 | #define ICE_AQC_RES_TYPE_SHARED_M (0x1 << ICE_AQC_RES_TYPE_SHARED_S) | |
| 228 | #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S 8 | |
| 229 | #define ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_M \ | |
| 230 | (0xF << ICE_AQC_RES_TYPE_VSI_PRUNE_LIST_S) | |
| 231 | __le16 num_elems; | |
| 232 | struct ice_aqc_res_elem elem[1]; | |
| 233 | }; | |
| 234 | ||
| 3a858ba3 AV |
235 | /* Add VSI (indirect 0x0210) |
| 236 | * Update VSI (indirect 0x0211) | |
| 237 | * Get VSI (indirect 0x0212) | |
| 238 | * Free VSI (indirect 0x0213) | |
| 239 | */ | |
| 240 | struct ice_aqc_add_get_update_free_vsi { | |
| 241 | __le16 vsi_num; | |
| 242 | #define ICE_AQ_VSI_NUM_S 0 | |
| 243 | #define ICE_AQ_VSI_NUM_M (0x03FF << ICE_AQ_VSI_NUM_S) | |
| 244 | #define ICE_AQ_VSI_IS_VALID BIT(15) | |
| 245 | __le16 cmd_flags; | |
| 246 | #define ICE_AQ_VSI_KEEP_ALLOC 0x1 | |
| 247 | u8 vf_id; | |
| 248 | u8 reserved; | |
| 249 | __le16 vsi_flags; | |
| 250 | #define ICE_AQ_VSI_TYPE_S 0 | |
| 251 | #define ICE_AQ_VSI_TYPE_M (0x3 << ICE_AQ_VSI_TYPE_S) | |
| 252 | #define ICE_AQ_VSI_TYPE_VF 0x0 | |
| 253 | #define ICE_AQ_VSI_TYPE_VMDQ2 0x1 | |
| 254 | #define ICE_AQ_VSI_TYPE_PF 0x2 | |
| 255 | #define ICE_AQ_VSI_TYPE_EMP_MNG 0x3 | |
| 256 | __le32 addr_high; | |
| 257 | __le32 addr_low; | |
| 258 | }; | |
| 259 | ||
| 260 | /* Response descriptor for: | |
| 261 | * Add VSI (indirect 0x0210) | |
| 262 | * Update VSI (indirect 0x0211) | |
| 263 | * Free VSI (indirect 0x0213) | |
| 264 | */ | |
| 265 | struct ice_aqc_add_update_free_vsi_resp { | |
| 266 | __le16 vsi_num; | |
| 267 | __le16 ext_status; | |
| 268 | __le16 vsi_used; | |
| 269 | __le16 vsi_free; | |
| 270 | __le32 addr_high; | |
| 271 | __le32 addr_low; | |
| 272 | }; | |
| 273 | ||
| 274 | struct ice_aqc_vsi_props { | |
| 275 | __le16 valid_sections; | |
| 276 | #define ICE_AQ_VSI_PROP_SW_VALID BIT(0) | |
| 277 | #define ICE_AQ_VSI_PROP_SECURITY_VALID BIT(1) | |
| 278 | #define ICE_AQ_VSI_PROP_VLAN_VALID BIT(2) | |
| 279 | #define ICE_AQ_VSI_PROP_OUTER_TAG_VALID BIT(3) | |
| 280 | #define ICE_AQ_VSI_PROP_INGRESS_UP_VALID BIT(4) | |
| 281 | #define ICE_AQ_VSI_PROP_EGRESS_UP_VALID BIT(5) | |
| 282 | #define ICE_AQ_VSI_PROP_RXQ_MAP_VALID BIT(6) | |
| 283 | #define ICE_AQ_VSI_PROP_Q_OPT_VALID BIT(7) | |
| 284 | #define ICE_AQ_VSI_PROP_OUTER_UP_VALID BIT(8) | |
| 285 | #define ICE_AQ_VSI_PROP_FLOW_DIR_VALID BIT(11) | |
| 286 | #define ICE_AQ_VSI_PROP_PASID_VALID BIT(12) | |
| 287 | /* switch section */ | |
| 288 | u8 sw_id; | |
| 289 | u8 sw_flags; | |
| 290 | #define ICE_AQ_VSI_SW_FLAG_ALLOW_LB BIT(5) | |
| 291 | #define ICE_AQ_VSI_SW_FLAG_LOCAL_LB BIT(6) | |
| 292 | #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7) | |
| 293 | u8 sw_flags2; | |
| 294 | #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0 | |
| 295 | #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \ | |
| 296 | (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S) | |
| 297 | #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0) | |
| 298 | #define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4) | |
| 299 | u8 veb_stat_id; | |
| 300 | #define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0 | |
| 301 | #define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S) | |
| 302 | #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5) | |
| 303 | /* security section */ | |
| 304 | u8 sec_flags; | |
| 305 | #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0) | |
| 306 | #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2) | |
| 307 | #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4 | |
| 308 | #define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S) | |
| 309 | #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0) | |
| 310 | u8 sec_reserved; | |
| 311 | /* VLAN section */ | |
| 312 | __le16 pvid; /* VLANS include priority bits */ | |
| 313 | u8 pvlan_reserved[2]; | |
| 314 | u8 port_vlan_flags; | |
| 315 | #define ICE_AQ_VSI_PVLAN_MODE_S 0 | |
| 316 | #define ICE_AQ_VSI_PVLAN_MODE_M (0x3 << ICE_AQ_VSI_PVLAN_MODE_S) | |
| 317 | #define ICE_AQ_VSI_PVLAN_MODE_UNTAGGED 0x1 | |
| 318 | #define ICE_AQ_VSI_PVLAN_MODE_TAGGED 0x2 | |
| 319 | #define ICE_AQ_VSI_PVLAN_MODE_ALL 0x3 | |
| 320 | #define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2) | |
| 321 | #define ICE_AQ_VSI_PVLAN_EMOD_S 3 | |
| 322 | #define ICE_AQ_VSI_PVLAN_EMOD_M (0x3 << ICE_AQ_VSI_PVLAN_EMOD_S) | |
| 323 | #define ICE_AQ_VSI_PVLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_PVLAN_EMOD_S) | |
| 324 | #define ICE_AQ_VSI_PVLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_PVLAN_EMOD_S) | |
| 325 | #define ICE_AQ_VSI_PVLAN_EMOD_STR (0x2 << ICE_AQ_VSI_PVLAN_EMOD_S) | |
| 326 | #define ICE_AQ_VSI_PVLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_PVLAN_EMOD_S) | |
| 327 | u8 pvlan_reserved2[3]; | |
| 328 | /* ingress egress up sections */ | |
| 329 | __le32 ingress_table; /* bitmap, 3 bits per up */ | |
| 330 | #define ICE_AQ_VSI_UP_TABLE_UP0_S 0 | |
| 331 | #define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S) | |
| 332 | #define ICE_AQ_VSI_UP_TABLE_UP1_S 3 | |
| 333 | #define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S) | |
| 334 | #define ICE_AQ_VSI_UP_TABLE_UP2_S 6 | |
| 335 | #define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S) | |
| 336 | #define ICE_AQ_VSI_UP_TABLE_UP3_S 9 | |
| 337 | #define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S) | |
| 338 | #define ICE_AQ_VSI_UP_TABLE_UP4_S 12 | |
| 339 | #define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S) | |
| 340 | #define ICE_AQ_VSI_UP_TABLE_UP5_S 15 | |
| 341 | #define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S) | |
| 342 | #define ICE_AQ_VSI_UP_TABLE_UP6_S 18 | |
| 343 | #define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S) | |
| 344 | #define ICE_AQ_VSI_UP_TABLE_UP7_S 21 | |
| 345 | #define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S) | |
| 346 | __le32 egress_table; /* same defines as for ingress table */ | |
| 347 | /* outer tags section */ | |
| 348 | __le16 outer_tag; | |
| 349 | u8 outer_tag_flags; | |
| 350 | #define ICE_AQ_VSI_OUTER_TAG_MODE_S 0 | |
| 351 | #define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S) | |
| 352 | #define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0 | |
| 353 | #define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1 | |
| 354 | #define ICE_AQ_VSI_OUTER_TAG_COPY 0x2 | |
| 355 | #define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2 | |
| 356 | #define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S) | |
| 357 | #define ICE_AQ_VSI_OUTER_TAG_NONE 0x0 | |
| 358 | #define ICE_AQ_VSI_OUTER_TAG_STAG 0x1 | |
| 359 | #define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2 | |
| 360 | #define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3 | |
| 361 | #define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4) | |
| 362 | #define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6) | |
| 363 | u8 outer_tag_reserved; | |
| 364 | /* queue mapping section */ | |
| 365 | __le16 mapping_flags; | |
| 366 | #define ICE_AQ_VSI_Q_MAP_CONTIG 0x0 | |
| 367 | #define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0) | |
| 368 | __le16 q_mapping[16]; | |
| 369 | #define ICE_AQ_VSI_Q_S 0 | |
| 370 | #define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S) | |
| 371 | __le16 tc_mapping[8]; | |
| 372 | #define ICE_AQ_VSI_TC_Q_OFFSET_S 0 | |
| 373 | #define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S) | |
| 374 | #define ICE_AQ_VSI_TC_Q_NUM_S 11 | |
| 375 | #define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S) | |
| 376 | /* queueing option section */ | |
| 377 | u8 q_opt_rss; | |
| 378 | #define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0 | |
| 379 | #define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) | |
| 380 | #define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0 | |
| 381 | #define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2 | |
| 382 | #define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3 | |
| 383 | #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2 | |
| 384 | #define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S) | |
| 385 | #define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6 | |
| 386 | #define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | |
| 387 | #define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | |
| 388 | #define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | |
| 389 | #define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | |
| 390 | #define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) | |
| 391 | u8 q_opt_tc; | |
| 392 | #define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0 | |
| 393 | #define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S) | |
| 394 | #define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7) | |
| 395 | u8 q_opt_flags; | |
| 396 | #define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0) | |
| 397 | u8 q_opt_reserved[3]; | |
| 398 | /* outer up section */ | |
| 399 | __le32 outer_up_table; /* same structure and defines as ingress tbl */ | |
| 400 | /* section 10 */ | |
| 401 | __le16 sect_10_reserved; | |
| 402 | /* flow director section */ | |
| 403 | __le16 fd_options; | |
| 404 | #define ICE_AQ_VSI_FD_ENABLE BIT(0) | |
| 405 | #define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1) | |
| 406 | #define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3) | |
| 407 | __le16 max_fd_fltr_dedicated; | |
| 408 | __le16 max_fd_fltr_shared; | |
| 409 | __le16 fd_def_q; | |
| 410 | #define ICE_AQ_VSI_FD_DEF_Q_S 0 | |
| 411 | #define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S) | |
| 412 | #define ICE_AQ_VSI_FD_DEF_GRP_S 12 | |
| 413 | #define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S) | |
| 414 | __le16 fd_report_opt; | |
| 415 | #define ICE_AQ_VSI_FD_REPORT_Q_S 0 | |
| 416 | #define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S) | |
| 417 | #define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12 | |
| 418 | #define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S) | |
| 419 | #define ICE_AQ_VSI_FD_DEF_DROP BIT(15) | |
| 420 | /* PASID section */ | |
| 421 | __le32 pasid_id; | |
| 422 | #define ICE_AQ_VSI_PASID_ID_S 0 | |
| 423 | #define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S) | |
| 424 | #define ICE_AQ_VSI_PASID_ID_VALID BIT(31) | |
| 425 | u8 reserved[24]; | |
| 426 | }; | |
| 427 | ||
| 9daf8208 AV |
428 | /* Add/Update/Remove/Get switch rules (indirect 0x02A0, 0x02A1, 0x02A2, 0x02A3) |
| 429 | */ | |
| 430 | struct ice_aqc_sw_rules { | |
| 431 | /* ops: add switch rules, referring the number of rules. | |
| 432 | * ops: update switch rules, referring the number of filters | |
| 433 | * ops: remove switch rules, referring the entry index. | |
| 434 | * ops: get switch rules, referring to the number of filters. | |
| 435 | */ | |
| 436 | __le16 num_rules_fltr_entry_index; | |
| 437 | u8 reserved[6]; | |
| 438 | __le32 addr_high; | |
| 439 | __le32 addr_low; | |
| 440 | }; | |
| 441 | ||
| 442 | /* Add/Update/Get/Remove lookup Rx/Tx command/response entry | |
| 443 | * This structures describes the lookup rules and associated actions. "index" | |
| 444 | * is returned as part of a response to a successful Add command, and can be | |
| 445 | * used to identify the rule for Update/Get/Remove commands. | |
| 446 | */ | |
| 447 | struct ice_sw_rule_lkup_rx_tx { | |
| 448 | __le16 recipe_id; | |
| 449 | #define ICE_SW_RECIPE_LOGICAL_PORT_FWD 10 | |
| 450 | /* Source port for LOOKUP_RX and source VSI in case of LOOKUP_TX */ | |
| 451 | __le16 src; | |
| 452 | __le32 act; | |
| 453 | ||
| 454 | /* Bit 0:1 - Action type */ | |
| 455 | #define ICE_SINGLE_ACT_TYPE_S 0x00 | |
| 456 | #define ICE_SINGLE_ACT_TYPE_M (0x3 << ICE_SINGLE_ACT_TYPE_S) | |
| 457 | ||
| 458 | /* Bit 2 - Loop back enable | |
| 459 | * Bit 3 - LAN enable | |
| 460 | */ | |
| 461 | #define ICE_SINGLE_ACT_LB_ENABLE BIT(2) | |
| 462 | #define ICE_SINGLE_ACT_LAN_ENABLE BIT(3) | |
| 463 | ||
| 464 | /* Action type = 0 - Forward to VSI or VSI list */ | |
| 465 | #define ICE_SINGLE_ACT_VSI_FORWARDING 0x0 | |
| 466 | ||
| 467 | #define ICE_SINGLE_ACT_VSI_ID_S 4 | |
| 468 | #define ICE_SINGLE_ACT_VSI_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_ID_S) | |
| 469 | #define ICE_SINGLE_ACT_VSI_LIST_ID_S 4 | |
| 470 | #define ICE_SINGLE_ACT_VSI_LIST_ID_M (0x3FF << ICE_SINGLE_ACT_VSI_LIST_ID_S) | |
| 471 | /* This bit needs to be set if action is forward to VSI list */ | |
| 472 | #define ICE_SINGLE_ACT_VSI_LIST BIT(14) | |
| 473 | #define ICE_SINGLE_ACT_VALID_BIT BIT(17) | |
| 474 | #define ICE_SINGLE_ACT_DROP BIT(18) | |
| 475 | ||
| 476 | /* Action type = 1 - Forward to Queue of Queue group */ | |
| 477 | #define ICE_SINGLE_ACT_TO_Q 0x1 | |
| 478 | #define ICE_SINGLE_ACT_Q_INDEX_S 4 | |
| 479 | #define ICE_SINGLE_ACT_Q_INDEX_M (0x7FF << ICE_SINGLE_ACT_Q_INDEX_S) | |
| 480 | #define ICE_SINGLE_ACT_Q_REGION_S 15 | |
| 481 | #define ICE_SINGLE_ACT_Q_REGION_M (0x7 << ICE_SINGLE_ACT_Q_REGION_S) | |
| 482 | #define ICE_SINGLE_ACT_Q_PRIORITY BIT(18) | |
| 483 | ||
| 484 | /* Action type = 2 - Prune */ | |
| 485 | #define ICE_SINGLE_ACT_PRUNE 0x2 | |
| 486 | #define ICE_SINGLE_ACT_EGRESS BIT(15) | |
| 487 | #define ICE_SINGLE_ACT_INGRESS BIT(16) | |
| 488 | #define ICE_SINGLE_ACT_PRUNET BIT(17) | |
| 489 | /* Bit 18 should be set to 0 for this action */ | |
| 490 | ||
| 491 | /* Action type = 2 - Pointer */ | |
| 492 | #define ICE_SINGLE_ACT_PTR 0x2 | |
| 493 | #define ICE_SINGLE_ACT_PTR_VAL_S 4 | |
| 494 | #define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S) | |
| 495 | /* Bit 18 should be set to 1 */ | |
| 496 | #define ICE_SINGLE_ACT_PTR_BIT BIT(18) | |
| 497 | ||
| 498 | /* Action type = 3 - Other actions. Last two bits | |
| 499 | * are other action identifier | |
| 500 | */ | |
| 501 | #define ICE_SINGLE_ACT_OTHER_ACTS 0x3 | |
| 502 | #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_S 17 | |
| 503 | #define ICE_SINGLE_OTHER_ACT_IDENTIFIER_M \ | |
| 504 | (0x3 << \ ICE_SINGLE_OTHER_ACT_IDENTIFIER_S) | |
| 505 | ||
| 506 | /* Bit 17:18 - Defines other actions */ | |
| 507 | /* Other action = 0 - Mirror VSI */ | |
| 508 | #define ICE_SINGLE_OTHER_ACT_MIRROR 0 | |
| 509 | #define ICE_SINGLE_ACT_MIRROR_VSI_ID_S 4 | |
| 510 | #define ICE_SINGLE_ACT_MIRROR_VSI_ID_M \ | |
| 511 | (0x3FF << ICE_SINGLE_ACT_MIRROR_VSI_ID_S) | |
| 512 | ||
| 513 | /* Other action = 3 - Set Stat count */ | |
| 514 | #define ICE_SINGLE_OTHER_ACT_STAT_COUNT 3 | |
| 515 | #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_S 4 | |
| 516 | #define ICE_SINGLE_ACT_STAT_COUNT_INDEX_M \ | |
| 517 | (0x7F << ICE_SINGLE_ACT_STAT_COUNT_INDEX_S) | |
| 518 | ||
| 519 | __le16 index; /* The index of the rule in the lookup table */ | |
| 520 | /* Length and values of the header to be matched per recipe or | |
| 521 | * lookup-type | |
| 522 | */ | |
| 523 | __le16 hdr_len; | |
| 524 | u8 hdr[1]; | |
| 525 | } __packed; | |
| 526 | ||
| 527 | /* Add/Update/Remove large action command/response entry | |
| 528 | * "index" is returned as part of a response to a successful Add command, and | |
| 529 | * can be used to identify the action for Update/Get/Remove commands. | |
| 530 | */ | |
| 531 | struct ice_sw_rule_lg_act { | |
| 532 | __le16 index; /* Index in large action table */ | |
| 533 | __le16 size; | |
| 534 | __le32 act[1]; /* array of size for actions */ | |
| 535 | /* Max number of large actions */ | |
| 536 | #define ICE_MAX_LG_ACT 4 | |
| 537 | /* Bit 0:1 - Action type */ | |
| 538 | #define ICE_LG_ACT_TYPE_S 0 | |
| 539 | #define ICE_LG_ACT_TYPE_M (0x7 << ICE_LG_ACT_TYPE_S) | |
| 540 | ||
| 541 | /* Action type = 0 - Forward to VSI or VSI list */ | |
| 542 | #define ICE_LG_ACT_VSI_FORWARDING 0 | |
| 543 | #define ICE_LG_ACT_VSI_ID_S 3 | |
| 544 | #define ICE_LG_ACT_VSI_ID_M (0x3FF << ICE_LG_ACT_VSI_ID_S) | |
| 545 | #define ICE_LG_ACT_VSI_LIST_ID_S 3 | |
| 546 | #define ICE_LG_ACT_VSI_LIST_ID_M (0x3FF << ICE_LG_ACT_VSI_LIST_ID_S) | |
| 547 | /* This bit needs to be set if action is forward to VSI list */ | |
| 548 | #define ICE_LG_ACT_VSI_LIST BIT(13) | |
| 549 | ||
| 550 | #define ICE_LG_ACT_VALID_BIT BIT(16) | |
| 551 | ||
| 552 | /* Action type = 1 - Forward to Queue of Queue group */ | |
| 553 | #define ICE_LG_ACT_TO_Q 0x1 | |
| 554 | #define ICE_LG_ACT_Q_INDEX_S 3 | |
| 555 | #define ICE_LG_ACT_Q_INDEX_M (0x7FF << ICE_LG_ACT_Q_INDEX_S) | |
| 556 | #define ICE_LG_ACT_Q_REGION_S 14 | |
| 557 | #define ICE_LG_ACT_Q_REGION_M (0x7 << ICE_LG_ACT_Q_REGION_S) | |
| 558 | #define ICE_LG_ACT_Q_PRIORITY_SET BIT(17) | |
| 559 | ||
| 560 | /* Action type = 2 - Prune */ | |
| 561 | #define ICE_LG_ACT_PRUNE 0x2 | |
| 562 | #define ICE_LG_ACT_EGRESS BIT(14) | |
| 563 | #define ICE_LG_ACT_INGRESS BIT(15) | |
| 564 | #define ICE_LG_ACT_PRUNET BIT(16) | |
| 565 | ||
| 566 | /* Action type = 3 - Mirror VSI */ | |
| 567 | #define ICE_LG_OTHER_ACT_MIRROR 0x3 | |
| 568 | #define ICE_LG_ACT_MIRROR_VSI_ID_S 3 | |
| 569 | #define ICE_LG_ACT_MIRROR_VSI_ID_M (0x3FF << ICE_LG_ACT_MIRROR_VSI_ID_S) | |
| 570 | ||
| 571 | /* Action type = 5 - Large Action */ | |
| 572 | #define ICE_LG_ACT_GENERIC 0x5 | |
| 573 | #define ICE_LG_ACT_GENERIC_VALUE_S 3 | |
| 574 | #define ICE_LG_ACT_GENERIC_VALUE_M (0xFFFF << ICE_LG_ACT_GENERIC_VALUE_S) | |
| 575 | #define ICE_LG_ACT_GENERIC_OFFSET_S 19 | |
| 576 | #define ICE_LG_ACT_GENERIC_OFFSET_M (0x7 << ICE_LG_ACT_GENERIC_OFFSET_S) | |
| 577 | #define ICE_LG_ACT_GENERIC_PRIORITY_S 22 | |
| 578 | #define ICE_LG_ACT_GENERIC_PRIORITY_M (0x7 << ICE_LG_ACT_GENERIC_PRIORITY_S) | |
| 579 | ||
| 580 | /* Action = 7 - Set Stat count */ | |
| 581 | #define ICE_LG_ACT_STAT_COUNT 0x7 | |
| 582 | #define ICE_LG_ACT_STAT_COUNT_S 3 | |
| 583 | #define ICE_LG_ACT_STAT_COUNT_M (0x7F << ICE_LG_ACT_STAT_COUNT_S) | |
| 584 | }; | |
| 585 | ||
| 586 | /* Add/Update/Remove VSI list command/response entry | |
| 587 | * "index" is returned as part of a response to a successful Add command, and | |
| 588 | * can be used to identify the VSI list for Update/Get/Remove commands. | |
| 589 | */ | |
| 590 | struct ice_sw_rule_vsi_list { | |
| 591 | __le16 index; /* Index of VSI/Prune list */ | |
| 592 | __le16 number_vsi; | |
| 593 | __le16 vsi[1]; /* Array of number_vsi VSI numbers */ | |
| 594 | }; | |
| 595 | ||
| 596 | /* Query VSI list command/response entry */ | |
| 597 | struct ice_sw_rule_vsi_list_query { | |
| 598 | __le16 index; | |
| 599 | DECLARE_BITMAP(vsi_list, ICE_MAX_VSI); | |
| 600 | } __packed; | |
| 601 | ||
| 602 | /* Add switch rule response: | |
| 603 | * Content of return buffer is same as the input buffer. The status field and | |
| 604 | * LUT index are updated as part of the response | |
| 605 | */ | |
| 606 | struct ice_aqc_sw_rules_elem { | |
| 607 | __le16 type; /* Switch rule type, one of T_... */ | |
| 608 | #define ICE_AQC_SW_RULES_T_LKUP_RX 0x0 | |
| 609 | #define ICE_AQC_SW_RULES_T_LKUP_TX 0x1 | |
| 610 | #define ICE_AQC_SW_RULES_T_LG_ACT 0x2 | |
| 611 | #define ICE_AQC_SW_RULES_T_VSI_LIST_SET 0x3 | |
| 612 | #define ICE_AQC_SW_RULES_T_VSI_LIST_CLEAR 0x4 | |
| 613 | #define ICE_AQC_SW_RULES_T_PRUNE_LIST_SET 0x5 | |
| 614 | #define ICE_AQC_SW_RULES_T_PRUNE_LIST_CLEAR 0x6 | |
| 615 | __le16 status; | |
| 616 | union { | |
| 617 | struct ice_sw_rule_lkup_rx_tx lkup_tx_rx; | |
| 618 | struct ice_sw_rule_lg_act lg_act; | |
| 619 | struct ice_sw_rule_vsi_list vsi_list; | |
| 620 | struct ice_sw_rule_vsi_list_query vsi_list_query; | |
| 621 | } __packed pdata; | |
| 622 | }; | |
| 623 | ||
| dc49c772 AV |
624 | /* Get Default Topology (indirect 0x0400) */ |
| 625 | struct ice_aqc_get_topo { | |
| 626 | u8 port_num; | |
| 627 | u8 num_branches; | |
| 628 | __le16 reserved1; | |
| 629 | __le32 reserved2; | |
| 630 | __le32 addr_high; | |
| 631 | __le32 addr_low; | |
| 632 | }; | |
| 633 | ||
| 9c20346b AV |
634 | /* Add TSE (indirect 0x0401) |
| 635 | * Delete TSE (indirect 0x040F) | |
| 636 | * Move TSE (indirect 0x0408) | |
| 637 | */ | |
| 638 | struct ice_aqc_add_move_delete_elem { | |
| 639 | __le16 num_grps_req; | |
| 640 | __le16 num_grps_updated; | |
| 641 | __le32 reserved; | |
| 642 | __le32 addr_high; | |
| 643 | __le32 addr_low; | |
| 644 | }; | |
| 645 | ||
| 646 | struct ice_aqc_elem_info_bw { | |
| 647 | __le16 bw_profile_idx; | |
| 648 | __le16 bw_alloc; | |
| 649 | }; | |
| 650 | ||
| 651 | struct ice_aqc_txsched_elem { | |
| 652 | u8 elem_type; /* Special field, reserved for some aq calls */ | |
| 653 | #define ICE_AQC_ELEM_TYPE_UNDEFINED 0x0 | |
| 654 | #define ICE_AQC_ELEM_TYPE_ROOT_PORT 0x1 | |
| 655 | #define ICE_AQC_ELEM_TYPE_TC 0x2 | |
| 656 | #define ICE_AQC_ELEM_TYPE_SE_GENERIC 0x3 | |
| 657 | #define ICE_AQC_ELEM_TYPE_ENTRY_POINT 0x4 | |
| 658 | #define ICE_AQC_ELEM_TYPE_LEAF 0x5 | |
| 659 | #define ICE_AQC_ELEM_TYPE_SE_PADDED 0x6 | |
| 660 | u8 valid_sections; | |
| 661 | #define ICE_AQC_ELEM_VALID_GENERIC BIT(0) | |
| 662 | #define ICE_AQC_ELEM_VALID_CIR BIT(1) | |
| 663 | #define ICE_AQC_ELEM_VALID_EIR BIT(2) | |
| 664 | #define ICE_AQC_ELEM_VALID_SHARED BIT(3) | |
| 665 | u8 generic; | |
| 666 | #define ICE_AQC_ELEM_GENERIC_MODE_M 0x1 | |
| 667 | #define ICE_AQC_ELEM_GENERIC_PRIO_S 0x1 | |
| 668 | #define ICE_AQC_ELEM_GENERIC_PRIO_M (0x7 << ICE_AQC_ELEM_GENERIC_PRIO_S) | |
| 669 | #define ICE_AQC_ELEM_GENERIC_SP_S 0x4 | |
| 670 | #define ICE_AQC_ELEM_GENERIC_SP_M (0x1 << ICE_AQC_ELEM_GENERIC_SP_S) | |
| 671 | #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S 0x5 | |
| 672 | #define ICE_AQC_ELEM_GENERIC_ADJUST_VAL_M \ | |
| 673 | (0x3 << ICE_AQC_ELEM_GENERIC_ADJUST_VAL_S) | |
| 674 | u8 flags; /* Special field, reserved for some aq calls */ | |
| 675 | #define ICE_AQC_ELEM_FLAG_SUSPEND_M 0x1 | |
| 676 | struct ice_aqc_elem_info_bw cir_bw; | |
| 677 | struct ice_aqc_elem_info_bw eir_bw; | |
| 678 | __le16 srl_id; | |
| 679 | __le16 reserved2; | |
| 680 | }; | |
| 681 | ||
| 682 | struct ice_aqc_txsched_elem_data { | |
| 683 | __le32 parent_teid; | |
| 684 | __le32 node_teid; | |
| 685 | struct ice_aqc_txsched_elem data; | |
| 686 | }; | |
| 687 | ||
| 688 | struct ice_aqc_txsched_topo_grp_info_hdr { | |
| 689 | __le32 parent_teid; | |
| 690 | __le16 num_elems; | |
| 691 | __le16 reserved2; | |
| 692 | }; | |
| 693 | ||
| dc49c772 AV |
694 | struct ice_aqc_get_topo_elem { |
| 695 | struct ice_aqc_txsched_topo_grp_info_hdr hdr; | |
| 696 | struct ice_aqc_txsched_elem_data | |
| 697 | generic[ICE_AQC_TOPO_MAX_LEVEL_NUM]; | |
| 698 | }; | |
| 699 | ||
| 9c20346b AV |
700 | struct ice_aqc_delete_elem { |
| 701 | struct ice_aqc_txsched_topo_grp_info_hdr hdr; | |
| 702 | __le32 teid[1]; | |
| 703 | }; | |
| 704 | ||
| 705 | /* Query Scheduler Resource Allocation (indirect 0x0412) | |
| 706 | * This indirect command retrieves the scheduler resources allocated by | |
| 707 | * EMP Firmware to the given PF. | |
| 708 | */ | |
| 709 | struct ice_aqc_query_txsched_res { | |
| 710 | u8 reserved[8]; | |
| 711 | __le32 addr_high; | |
| 712 | __le32 addr_low; | |
| 713 | }; | |
| 714 | ||
| 715 | struct ice_aqc_generic_sched_props { | |
| 716 | __le16 phys_levels; | |
| 717 | __le16 logical_levels; | |
| 718 | u8 flattening_bitmap; | |
| 719 | u8 max_device_cgds; | |
| 720 | u8 max_pf_cgds; | |
| 721 | u8 rsvd0; | |
| 722 | __le16 rdma_qsets; | |
| 723 | u8 rsvd1[22]; | |
| 724 | }; | |
| 725 | ||
| 726 | struct ice_aqc_layer_props { | |
| 727 | u8 logical_layer; | |
| 728 | u8 chunk_size; | |
| 729 | __le16 max_device_nodes; | |
| 730 | __le16 max_pf_nodes; | |
| 731 | u8 rsvd0[2]; | |
| 732 | __le16 max_shared_rate_lmtr; | |
| 733 | __le16 max_children; | |
| 734 | __le16 max_cir_rl_profiles; | |
| 735 | __le16 max_eir_rl_profiles; | |
| 736 | __le16 max_srl_profiles; | |
| 737 | u8 rsvd1[14]; | |
| 738 | }; | |
| 739 | ||
| 740 | struct ice_aqc_query_txsched_res_resp { | |
| 741 | struct ice_aqc_generic_sched_props sched_props; | |
| 742 | struct ice_aqc_layer_props layer_props[ICE_AQC_TOPO_MAX_LEVEL_NUM]; | |
| 743 | }; | |
| 744 | ||
| dc49c772 AV |
745 | /* Get PHY capabilities (indirect 0x0600) */ |
| 746 | struct ice_aqc_get_phy_caps { | |
| 747 | u8 lport_num; | |
| 748 | u8 reserved; | |
| 749 | __le16 param0; | |
| 750 | /* 18.0 - Report qualified modules */ | |
| 751 | #define ICE_AQC_GET_PHY_RQM BIT(0) | |
| 752 | /* 18.1 - 18.2 : Report mode | |
| 753 | * 00b - Report NVM capabilities | |
| 754 | * 01b - Report topology capabilities | |
| 755 | * 10b - Report SW configured | |
| 756 | */ | |
| 757 | #define ICE_AQC_REPORT_MODE_S 1 | |
| 758 | #define ICE_AQC_REPORT_MODE_M (3 << ICE_AQC_REPORT_MODE_S) | |
| 759 | #define ICE_AQC_REPORT_NVM_CAP 0 | |
| 760 | #define ICE_AQC_REPORT_TOPO_CAP BIT(1) | |
| 761 | #define ICE_AQC_REPORT_SW_CFG BIT(2) | |
| 762 | __le32 reserved1; | |
| 763 | __le32 addr_high; | |
| 764 | __le32 addr_low; | |
| 765 | }; | |
| 766 | ||
| 767 | /* This is #define of PHY type (Extended): | |
| 768 | * The first set of defines is for phy_type_low. | |
| 769 | */ | |
| 770 | #define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0) | |
| 771 | #define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1) | |
| 772 | #define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2) | |
| 773 | #define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3) | |
| 774 | #define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4) | |
| 775 | #define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5) | |
| 776 | #define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6) | |
| 777 | #define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7) | |
| 778 | #define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8) | |
| 779 | #define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9) | |
| 780 | #define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10) | |
| 781 | #define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11) | |
| 782 | #define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12) | |
| 783 | #define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13) | |
| 784 | #define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14) | |
| 785 | #define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15) | |
| 786 | #define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16) | |
| 787 | #define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17) | |
| 788 | #define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18) | |
| 789 | #define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19) | |
| 790 | #define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20) | |
| 791 | #define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21) | |
| 792 | #define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22) | |
| 793 | #define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23) | |
| 794 | #define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24) | |
| 795 | #define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25) | |
| 796 | #define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26) | |
| 797 | #define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27) | |
| 798 | #define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28) | |
| 799 | #define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29) | |
| 800 | #define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30) | |
| 801 | #define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31) | |
| 802 | #define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32) | |
| 803 | #define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33) | |
| 804 | #define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34) | |
| 805 | #define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35) | |
| 806 | #define ICE_PHY_TYPE_LOW_MAX_INDEX 63 | |
| 807 | ||
| 808 | struct ice_aqc_get_phy_caps_data { | |
| 809 | __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ | |
| 810 | __le64 reserved; | |
| 811 | u8 caps; | |
| 812 | #define ICE_AQC_PHY_EN_TX_LINK_PAUSE BIT(0) | |
| 813 | #define ICE_AQC_PHY_EN_RX_LINK_PAUSE BIT(1) | |
| 814 | #define ICE_AQC_PHY_LOW_POWER_MODE BIT(2) | |
| 815 | #define ICE_AQC_PHY_EN_LINK BIT(3) | |
| 816 | #define ICE_AQC_PHY_AN_MODE BIT(4) | |
| 817 | #define ICE_AQC_GET_PHY_EN_MOD_QUAL BIT(5) | |
| 818 | u8 low_power_ctrl; | |
| 819 | #define ICE_AQC_PHY_EN_D3COLD_LOW_POWER_AUTONEG BIT(0) | |
| 820 | __le16 eee_cap; | |
| 821 | #define ICE_AQC_PHY_EEE_EN_100BASE_TX BIT(0) | |
| 822 | #define ICE_AQC_PHY_EEE_EN_1000BASE_T BIT(1) | |
| 823 | #define ICE_AQC_PHY_EEE_EN_10GBASE_T BIT(2) | |
| 824 | #define ICE_AQC_PHY_EEE_EN_1000BASE_KX BIT(3) | |
| 825 | #define ICE_AQC_PHY_EEE_EN_10GBASE_KR BIT(4) | |
| 826 | #define ICE_AQC_PHY_EEE_EN_25GBASE_KR BIT(5) | |
| 827 | #define ICE_AQC_PHY_EEE_EN_40GBASE_KR4 BIT(6) | |
| 828 | __le16 eeer_value; | |
| 829 | u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */ | |
| 830 | u8 link_fec_options; | |
| 831 | #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN BIT(0) | |
| 832 | #define ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ BIT(1) | |
| 833 | #define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2) | |
| 834 | #define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3) | |
| 835 | #define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4) | |
| 836 | #define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6) | |
| 837 | #define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7) | |
| 838 | u8 extended_compliance_code; | |
| 839 | #define ICE_MODULE_TYPE_TOTAL_BYTE 3 | |
| 840 | u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE]; | |
| 841 | #define ICE_AQC_MOD_TYPE_BYTE0_SFP_PLUS 0xA0 | |
| 842 | #define ICE_AQC_MOD_TYPE_BYTE0_QSFP_PLUS 0x80 | |
| 843 | #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE BIT(0) | |
| 844 | #define ICE_AQC_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE BIT(1) | |
| 845 | #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_SR BIT(4) | |
| 846 | #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LR BIT(5) | |
| 847 | #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_LRM BIT(6) | |
| 848 | #define ICE_AQC_MOD_TYPE_BYTE1_10G_BASE_ER BIT(7) | |
| 849 | #define ICE_AQC_MOD_TYPE_BYTE2_SFP_PLUS 0xA0 | |
| 850 | #define ICE_AQC_MOD_TYPE_BYTE2_QSFP_PLUS 0x86 | |
| 851 | u8 qualified_module_count; | |
| 852 | #define ICE_AQC_QUAL_MOD_COUNT_MAX 16 | |
| 853 | struct { | |
| 854 | u8 v_oui[3]; | |
| 855 | u8 rsvd1; | |
| 856 | u8 v_part[16]; | |
| 857 | __le32 v_rev; | |
| 858 | __le64 rsvd8; | |
| 859 | } qual_modules[ICE_AQC_QUAL_MOD_COUNT_MAX]; | |
| 860 | }; | |
| 861 | ||
| 862 | /* Get link status (indirect 0x0607), also used for Link Status Event */ | |
| 863 | struct ice_aqc_get_link_status { | |
| 864 | u8 lport_num; | |
| 865 | u8 reserved; | |
| 866 | __le16 cmd_flags; | |
| 867 | #define ICE_AQ_LSE_M 0x3 | |
| 868 | #define ICE_AQ_LSE_NOP 0x0 | |
| 869 | #define ICE_AQ_LSE_DIS 0x2 | |
| 870 | #define ICE_AQ_LSE_ENA 0x3 | |
| 871 | /* only response uses this flag */ | |
| 872 | #define ICE_AQ_LSE_IS_ENABLED 0x1 | |
| 873 | __le32 reserved2; | |
| 874 | __le32 addr_high; | |
| 875 | __le32 addr_low; | |
| 876 | }; | |
| 877 | ||
| 878 | /* Get link status response data structure, also used for Link Status Event */ | |
| 879 | struct ice_aqc_get_link_status_data { | |
| 880 | u8 topo_media_conflict; | |
| 881 | #define ICE_AQ_LINK_TOPO_CONFLICT BIT(0) | |
| 882 | #define ICE_AQ_LINK_MEDIA_CONFLICT BIT(1) | |
| 883 | #define ICE_AQ_LINK_TOPO_CORRUPT BIT(2) | |
| 884 | u8 reserved1; | |
| 885 | u8 link_info; | |
| 886 | #define ICE_AQ_LINK_UP BIT(0) /* Link Status */ | |
| 887 | #define ICE_AQ_LINK_FAULT BIT(1) | |
| 888 | #define ICE_AQ_LINK_FAULT_TX BIT(2) | |
| 889 | #define ICE_AQ_LINK_FAULT_RX BIT(3) | |
| 890 | #define ICE_AQ_LINK_FAULT_REMOTE BIT(4) | |
| 891 | #define ICE_AQ_LINK_UP_PORT BIT(5) /* External Port Link Status */ | |
| 892 | #define ICE_AQ_MEDIA_AVAILABLE BIT(6) | |
| 893 | #define ICE_AQ_SIGNAL_DETECT BIT(7) | |
| 894 | u8 an_info; | |
| 895 | #define ICE_AQ_AN_COMPLETED BIT(0) | |
| 896 | #define ICE_AQ_LP_AN_ABILITY BIT(1) | |
| 897 | #define ICE_AQ_PD_FAULT BIT(2) /* Parallel Detection Fault */ | |
| 898 | #define ICE_AQ_FEC_EN BIT(3) | |
| 899 | #define ICE_AQ_PHY_LOW_POWER BIT(4) /* Low Power State */ | |
| 900 | #define ICE_AQ_LINK_PAUSE_TX BIT(5) | |
| 901 | #define ICE_AQ_LINK_PAUSE_RX BIT(6) | |
| 902 | #define ICE_AQ_QUALIFIED_MODULE BIT(7) | |
| 903 | u8 ext_info; | |
| 904 | #define ICE_AQ_LINK_PHY_TEMP_ALARM BIT(0) | |
| 905 | #define ICE_AQ_LINK_EXCESSIVE_ERRORS BIT(1) /* Excessive Link Errors */ | |
| 906 | /* Port TX Suspended */ | |
| 907 | #define ICE_AQ_LINK_TX_S 2 | |
| 908 | #define ICE_AQ_LINK_TX_M (0x03 << ICE_AQ_LINK_TX_S) | |
| 909 | #define ICE_AQ_LINK_TX_ACTIVE 0 | |
| 910 | #define ICE_AQ_LINK_TX_DRAINED 1 | |
| 911 | #define ICE_AQ_LINK_TX_FLUSHED 3 | |
| 912 | u8 reserved2; | |
| 913 | __le16 max_frame_size; | |
| 914 | u8 cfg; | |
| 915 | #define ICE_AQ_LINK_25G_KR_FEC_EN BIT(0) | |
| 916 | #define ICE_AQ_LINK_25G_RS_528_FEC_EN BIT(1) | |
| 917 | #define ICE_AQ_LINK_25G_RS_544_FEC_EN BIT(2) | |
| 918 | /* Pacing Config */ | |
| 919 | #define ICE_AQ_CFG_PACING_S 3 | |
| 920 | #define ICE_AQ_CFG_PACING_M (0xF << ICE_AQ_CFG_PACING_S) | |
| 921 | #define ICE_AQ_CFG_PACING_TYPE_M BIT(7) | |
| 922 | #define ICE_AQ_CFG_PACING_TYPE_AVG 0 | |
| 923 | #define ICE_AQ_CFG_PACING_TYPE_FIXED ICE_AQ_CFG_PACING_TYPE_M | |
| 924 | /* External Device Power Ability */ | |
| 925 | u8 power_desc; | |
| 926 | #define ICE_AQ_PWR_CLASS_M 0x3 | |
| 927 | #define ICE_AQ_LINK_PWR_BASET_LOW_HIGH 0 | |
| 928 | #define ICE_AQ_LINK_PWR_BASET_HIGH 1 | |
| 929 | #define ICE_AQ_LINK_PWR_QSFP_CLASS_1 0 | |
| 930 | #define ICE_AQ_LINK_PWR_QSFP_CLASS_2 1 | |
| 931 | #define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2 | |
| 932 | #define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3 | |
| 933 | __le16 link_speed; | |
| 934 | #define ICE_AQ_LINK_SPEED_10MB BIT(0) | |
| 935 | #define ICE_AQ_LINK_SPEED_100MB BIT(1) | |
| 936 | #define ICE_AQ_LINK_SPEED_1000MB BIT(2) | |
| 937 | #define ICE_AQ_LINK_SPEED_2500MB BIT(3) | |
| 938 | #define ICE_AQ_LINK_SPEED_5GB BIT(4) | |
| 939 | #define ICE_AQ_LINK_SPEED_10GB BIT(5) | |
| 940 | #define ICE_AQ_LINK_SPEED_20GB BIT(6) | |
| 941 | #define ICE_AQ_LINK_SPEED_25GB BIT(7) | |
| 942 | #define ICE_AQ_LINK_SPEED_40GB BIT(8) | |
| 943 | #define ICE_AQ_LINK_SPEED_UNKNOWN BIT(15) | |
| 944 | __le32 reserved3; /* Aligns next field to 8-byte boundary */ | |
| 945 | __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */ | |
| 946 | __le64 reserved4; | |
| 947 | }; | |
| 948 | ||
| f31e4b6f AV |
949 | /* NVM Read command (indirect 0x0701) |
| 950 | * NVM Erase commands (direct 0x0702) | |
| 951 | * NVM Update commands (indirect 0x0703) | |
| 952 | */ | |
| 953 | struct ice_aqc_nvm { | |
| 954 | u8 cmd_flags; | |
| 955 | #define ICE_AQC_NVM_LAST_CMD BIT(0) | |
| 956 | #define ICE_AQC_NVM_PCIR_REQ BIT(0) /* Used by NVM Update reply */ | |
| 957 | #define ICE_AQC_NVM_PRESERVATION_S 1 | |
| 958 | #define ICE_AQC_NVM_PRESERVATION_M (3 << CSR_AQ_NVM_PRESERVATION_S) | |
| 959 | #define ICE_AQC_NVM_NO_PRESERVATION (0 << CSR_AQ_NVM_PRESERVATION_S) | |
| 960 | #define ICE_AQC_NVM_PRESERVE_ALL BIT(1) | |
| 961 | #define ICE_AQC_NVM_PRESERVE_SELECTED (3 << CSR_AQ_NVM_PRESERVATION_S) | |
| 962 | #define ICE_AQC_NVM_FLASH_ONLY BIT(7) | |
| 963 | u8 module_typeid; | |
| 964 | __le16 length; | |
| 965 | #define ICE_AQC_NVM_ERASE_LEN 0xFFFF | |
| 966 | __le32 offset; | |
| 967 | __le32 addr_high; | |
| 968 | __le32 addr_low; | |
| 969 | }; | |
| 970 | ||
| cdedef59 AV |
971 | /* Add TX LAN Queues (indirect 0x0C30) */ |
| 972 | struct ice_aqc_add_txqs { | |
| 973 | u8 num_qgrps; | |
| 974 | u8 reserved[3]; | |
| 975 | __le32 reserved1; | |
| 976 | __le32 addr_high; | |
| 977 | __le32 addr_low; | |
| 978 | }; | |
| 979 | ||
| 980 | /* This is the descriptor of each queue entry for the Add TX LAN Queues | |
| 981 | * command (0x0C30). Only used within struct ice_aqc_add_tx_qgrp. | |
| 982 | */ | |
| 983 | struct ice_aqc_add_txqs_perq { | |
| 984 | __le16 txq_id; | |
| 985 | u8 rsvd[2]; | |
| 986 | __le32 q_teid; | |
| 987 | u8 txq_ctx[22]; | |
| 988 | u8 rsvd2[2]; | |
| 989 | struct ice_aqc_txsched_elem info; | |
| 990 | }; | |
| 991 | ||
| 992 | /* The format of the command buffer for Add TX LAN Queues (0x0C30) | |
| 993 | * is an array of the following structs. Please note that the length of | |
| 994 | * each struct ice_aqc_add_tx_qgrp is variable due | |
| 995 | * to the variable number of queues in each group! | |
| 996 | */ | |
| 997 | struct ice_aqc_add_tx_qgrp { | |
| 998 | __le32 parent_teid; | |
| 999 | u8 num_txqs; | |
| 1000 | u8 rsvd[3]; | |
| 1001 | struct ice_aqc_add_txqs_perq txqs[1]; | |
| 1002 | }; | |
| 1003 | ||
| 1004 | /* Disable TX LAN Queues (indirect 0x0C31) */ | |
| 1005 | struct ice_aqc_dis_txqs { | |
| 1006 | u8 cmd_type; | |
| 1007 | #define ICE_AQC_Q_DIS_CMD_S 0 | |
| 1008 | #define ICE_AQC_Q_DIS_CMD_M (0x3 << ICE_AQC_Q_DIS_CMD_S) | |
| 1009 | #define ICE_AQC_Q_DIS_CMD_NO_FUNC_RESET (0 << ICE_AQC_Q_DIS_CMD_S) | |
| 1010 | #define ICE_AQC_Q_DIS_CMD_VM_RESET BIT(ICE_AQC_Q_DIS_CMD_S) | |
| 1011 | #define ICE_AQC_Q_DIS_CMD_VF_RESET (2 << ICE_AQC_Q_DIS_CMD_S) | |
| 1012 | #define ICE_AQC_Q_DIS_CMD_PF_RESET (3 << ICE_AQC_Q_DIS_CMD_S) | |
| 1013 | #define ICE_AQC_Q_DIS_CMD_SUBSEQ_CALL BIT(2) | |
| 1014 | #define ICE_AQC_Q_DIS_CMD_FLUSH_PIPE BIT(3) | |
| 1015 | u8 num_entries; | |
| 1016 | __le16 vmvf_and_timeout; | |
| 1017 | #define ICE_AQC_Q_DIS_VMVF_NUM_S 0 | |
| 1018 | #define ICE_AQC_Q_DIS_VMVF_NUM_M (0x3FF << ICE_AQC_Q_DIS_VMVF_NUM_S) | |
| 1019 | #define ICE_AQC_Q_DIS_TIMEOUT_S 10 | |
| 1020 | #define ICE_AQC_Q_DIS_TIMEOUT_M (0x3F << ICE_AQC_Q_DIS_TIMEOUT_S) | |
| 1021 | __le32 blocked_cgds; | |
| 1022 | __le32 addr_high; | |
| 1023 | __le32 addr_low; | |
| 1024 | }; | |
| 1025 | ||
| 1026 | /* The buffer for Disable TX LAN Queues (indirect 0x0C31) | |
| 1027 | * contains the following structures, arrayed one after the | |
| 1028 | * other. | |
| 1029 | * Note: Since the q_id is 16 bits wide, if the | |
| 1030 | * number of queues is even, then 2 bytes of alignment MUST be | |
| 1031 | * added before the start of the next group, to allow correct | |
| 1032 | * alignment of the parent_teid field. | |
| 1033 | */ | |
| 1034 | struct ice_aqc_dis_txq_item { | |
| 1035 | __le32 parent_teid; | |
| 1036 | u8 num_qs; | |
| 1037 | u8 rsvd; | |
| 1038 | /* The length of the q_id array varies according to num_qs */ | |
| 1039 | __le16 q_id[1]; | |
| 1040 | /* This only applies from F8 onward */ | |
| 1041 | #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S 15 | |
| 1042 | #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_LAN_Q \ | |
| 1043 | (0 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) | |
| 1044 | #define ICE_AQC_Q_DIS_BUF_ELEM_TYPE_RDMA_QSET \ | |
| 1045 | (1 << ICE_AQC_Q_DIS_BUF_ELEM_TYPE_S) | |
| 1046 | }; | |
| 1047 | ||
| 1048 | struct ice_aqc_dis_txq { | |
| 1049 | struct ice_aqc_dis_txq_item qgrps[1]; | |
| 1050 | }; | |
| 1051 | ||
| 7ec59eea AV |
1052 | /** |
| 1053 | * struct ice_aq_desc - Admin Queue (AQ) descriptor | |
| 1054 | * @flags: ICE_AQ_FLAG_* flags | |
| 1055 | * @opcode: AQ command opcode | |
| 1056 | * @datalen: length in bytes of indirect/external data buffer | |
| 1057 | * @retval: return value from firmware | |
| 1058 | * @cookie_h: opaque data high-half | |
| 1059 | * @cookie_l: opaque data low-half | |
| 1060 | * @params: command-specific parameters | |
| 1061 | * | |
| 1062 | * Descriptor format for commands the driver posts on the Admin Transmit Queue | |
| 1063 | * (ATQ). The firmware writes back onto the command descriptor and returns | |
| 1064 | * the result of the command. Asynchronous events that are not an immediate | |
| 1065 | * result of the command are written to the Admin Receive Queue (ARQ) using | |
| 1066 | * the same descriptor format. Descriptors are in little-endian notation with | |
| 1067 | * 32-bit words. | |
| 1068 | */ | |
| 1069 | struct ice_aq_desc { | |
| 1070 | __le16 flags; | |
| 1071 | __le16 opcode; | |
| 1072 | __le16 datalen; | |
| 1073 | __le16 retval; | |
| 1074 | __le32 cookie_high; | |
| 1075 | __le32 cookie_low; | |
| 1076 | union { | |
| 1077 | u8 raw[16]; | |
| 1078 | struct ice_aqc_generic generic; | |
| 1079 | struct ice_aqc_get_ver get_ver; | |
| 1080 | struct ice_aqc_q_shutdown q_shutdown; | |
| f31e4b6f | 1081 | struct ice_aqc_req_res res_owner; |
| dc49c772 | 1082 | struct ice_aqc_manage_mac_read mac_read; |
| f31e4b6f | 1083 | struct ice_aqc_clear_pxe clear_pxe; |
| 9c20346b | 1084 | struct ice_aqc_list_caps get_cap; |
| dc49c772 | 1085 | struct ice_aqc_get_phy_caps get_phy; |
| 9c20346b | 1086 | struct ice_aqc_get_sw_cfg get_sw_conf; |
| 9daf8208 | 1087 | struct ice_aqc_sw_rules sw_rules; |
| dc49c772 | 1088 | struct ice_aqc_get_topo get_topo; |
| 9c20346b AV |
1089 | struct ice_aqc_query_txsched_res query_sched_res; |
| 1090 | struct ice_aqc_add_move_delete_elem add_move_delete_elem; | |
| f31e4b6f | 1091 | struct ice_aqc_nvm nvm; |
| cdedef59 AV |
1092 | struct ice_aqc_add_txqs add_txqs; |
| 1093 | struct ice_aqc_dis_txqs dis_txqs; | |
| 3a858ba3 | 1094 | struct ice_aqc_add_get_update_free_vsi vsi_cmd; |
| 9daf8208 | 1095 | struct ice_aqc_alloc_free_res_cmd sw_res_ctrl; |
| dc49c772 | 1096 | struct ice_aqc_get_link_status get_link_status; |
| 7ec59eea AV |
1097 | } params; |
| 1098 | }; | |
| 1099 | ||
| 1100 | /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */ | |
| 1101 | #define ICE_AQ_LG_BUF 512 | |
| 1102 | ||
| 940b61af | 1103 | #define ICE_AQ_FLAG_ERR_S 2 |
| 7ec59eea | 1104 | #define ICE_AQ_FLAG_LB_S 9 |
| 9c20346b | 1105 | #define ICE_AQ_FLAG_RD_S 10 |
| 7ec59eea AV |
1106 | #define ICE_AQ_FLAG_BUF_S 12 |
| 1107 | #define ICE_AQ_FLAG_SI_S 13 | |
| 1108 | ||
| 940b61af | 1109 | #define ICE_AQ_FLAG_ERR BIT(ICE_AQ_FLAG_ERR_S) /* 0x4 */ |
| 7ec59eea | 1110 | #define ICE_AQ_FLAG_LB BIT(ICE_AQ_FLAG_LB_S) /* 0x200 */ |
| 9c20346b | 1111 | #define ICE_AQ_FLAG_RD BIT(ICE_AQ_FLAG_RD_S) /* 0x400 */ |
| 7ec59eea AV |
1112 | #define ICE_AQ_FLAG_BUF BIT(ICE_AQ_FLAG_BUF_S) /* 0x1000 */ |
| 1113 | #define ICE_AQ_FLAG_SI BIT(ICE_AQ_FLAG_SI_S) /* 0x2000 */ | |
| 1114 | ||
| 1115 | /* error codes */ | |
| 1116 | enum ice_aq_err { | |
| 1117 | ICE_AQ_RC_OK = 0, /* success */ | |
| 9c20346b | 1118 | ICE_AQ_RC_ENOMEM = 9, /* Out of memory */ |
| f31e4b6f AV |
1119 | ICE_AQ_RC_EBUSY = 12, /* Device or resource busy */ |
| 1120 | ICE_AQ_RC_EEXIST = 13, /* object already exists */ | |
| 7ec59eea AV |
1121 | }; |
| 1122 | ||
| 1123 | /* Admin Queue command opcodes */ | |
| 1124 | enum ice_adminq_opc { | |
| 1125 | /* AQ commands */ | |
| 1126 | ice_aqc_opc_get_ver = 0x0001, | |
| 1127 | ice_aqc_opc_q_shutdown = 0x0003, | |
| f31e4b6f AV |
1128 | |
| 1129 | /* resource ownership */ | |
| 1130 | ice_aqc_opc_req_res = 0x0008, | |
| 1131 | ice_aqc_opc_release_res = 0x0009, | |
| 1132 | ||
| 9c20346b AV |
1133 | /* device/function capabilities */ |
| 1134 | ice_aqc_opc_list_func_caps = 0x000A, | |
| 1135 | ice_aqc_opc_list_dev_caps = 0x000B, | |
| 1136 | ||
| dc49c772 AV |
1137 | /* manage MAC address */ |
| 1138 | ice_aqc_opc_manage_mac_read = 0x0107, | |
| 1139 | ||
| f31e4b6f AV |
1140 | /* PXE */ |
| 1141 | ice_aqc_opc_clear_pxe_mode = 0x0110, | |
| 1142 | ||
| 9c20346b AV |
1143 | /* internal switch commands */ |
| 1144 | ice_aqc_opc_get_sw_cfg = 0x0200, | |
| 1145 | ||
| 9daf8208 AV |
1146 | /* Alloc/Free/Get Resources */ |
| 1147 | ice_aqc_opc_alloc_res = 0x0208, | |
| 1148 | ice_aqc_opc_free_res = 0x0209, | |
| 1149 | ||
| 3a858ba3 AV |
1150 | /* VSI commands */ |
| 1151 | ice_aqc_opc_add_vsi = 0x0210, | |
| 1152 | ice_aqc_opc_update_vsi = 0x0211, | |
| 1153 | ice_aqc_opc_free_vsi = 0x0213, | |
| 9daf8208 AV |
1154 | |
| 1155 | /* switch rules population commands */ | |
| 1156 | ice_aqc_opc_add_sw_rules = 0x02A0, | |
| 1157 | ice_aqc_opc_update_sw_rules = 0x02A1, | |
| 1158 | ice_aqc_opc_remove_sw_rules = 0x02A2, | |
| 1159 | ||
| f31e4b6f AV |
1160 | ice_aqc_opc_clear_pf_cfg = 0x02A4, |
| 1161 | ||
| 9c20346b | 1162 | /* transmit scheduler commands */ |
| dc49c772 | 1163 | ice_aqc_opc_get_dflt_topo = 0x0400, |
| 9c20346b AV |
1164 | ice_aqc_opc_delete_sched_elems = 0x040F, |
| 1165 | ice_aqc_opc_query_sched_res = 0x0412, | |
| 1166 | ||
| dc49c772 AV |
1167 | /* PHY commands */ |
| 1168 | ice_aqc_opc_get_phy_caps = 0x0600, | |
| 1169 | ice_aqc_opc_get_link_status = 0x0607, | |
| 1170 | ||
| f31e4b6f AV |
1171 | /* NVM commands */ |
| 1172 | ice_aqc_opc_nvm_read = 0x0701, | |
| 1173 | ||
| cdedef59 AV |
1174 | /* TX queue handling commands/events */ |
| 1175 | ice_aqc_opc_add_txqs = 0x0C30, | |
| 1176 | ice_aqc_opc_dis_txqs = 0x0C31, | |
| 7ec59eea AV |
1177 | }; |
| 1178 | ||
| 1179 | #endif /* _ICE_ADMINQ_CMD_H_ */ |