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Merge tag 'fscache-fixes-20140917' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40evf / i40e_txrx.c
CommitLineData
7f12ad74
GR		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
af1a2a9c 4 * Copyright(c) 2013 - 2014 Intel Corporation.
7f12ad74
GR		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
b831607d
JB		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
7f12ad74
GR		 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
7ed3f5f0
PG		 27#include <linux/prefetch.h>
28
7f12ad74 29#include "i40evf.h"
206812b5 30#include "i40e_prototype.h"
7f12ad74
GR		 31
32static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
33 u32 td_tag)
34{
35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
40}
41
42#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
43
44/**
45 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
46 * @ring: the ring that owns the buffer
47 * @tx_buffer: the buffer to free
48 **/
49static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
50 struct i40e_tx_buffer *tx_buffer)
51{
52 if (tx_buffer->skb) {
49d7d933
ASJ		 53 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
54 kfree(tx_buffer->raw_buf);
55 else
56 dev_kfree_skb_any(tx_buffer->skb);
57
7f12ad74
GR		 58 if (dma_unmap_len(tx_buffer, len))
59 dma_unmap_single(ring->dev,
60 dma_unmap_addr(tx_buffer, dma),
61 dma_unmap_len(tx_buffer, len),
62 DMA_TO_DEVICE);
63 } else if (dma_unmap_len(tx_buffer, len)) {
64 dma_unmap_page(ring->dev,
65 dma_unmap_addr(tx_buffer, dma),
66 dma_unmap_len(tx_buffer, len),
67 DMA_TO_DEVICE);
68 }
69 tx_buffer->next_to_watch = NULL;
70 tx_buffer->skb = NULL;
71 dma_unmap_len_set(tx_buffer, len, 0);
72 /* tx_buffer must be completely set up in the transmit path */
73}
74
75/**
76 * i40evf_clean_tx_ring - Free any empty Tx buffers
77 * @tx_ring: ring to be cleaned
78 **/
79void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
80{
81 unsigned long bi_size;
82 u16 i;
83
84 /* ring already cleared, nothing to do */
85 if (!tx_ring->tx_bi)
86 return;
87
88 /* Free all the Tx ring sk_buffs */
89 for (i = 0; i < tx_ring->count; i++)
90 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
91
92 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
93 memset(tx_ring->tx_bi, 0, bi_size);
94
95 /* Zero out the descriptor ring */
96 memset(tx_ring->desc, 0, tx_ring->size);
97
98 tx_ring->next_to_use = 0;
99 tx_ring->next_to_clean = 0;
100
101 if (!tx_ring->netdev)
102 return;
103
104 /* cleanup Tx queue statistics */
105 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
106 tx_ring->queue_index));
107}
108
109/**
110 * i40evf_free_tx_resources - Free Tx resources per queue
111 * @tx_ring: Tx descriptor ring for a specific queue
112 *
113 * Free all transmit software resources
114 **/
115void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
116{
117 i40evf_clean_tx_ring(tx_ring);
118 kfree(tx_ring->tx_bi);
119 tx_ring->tx_bi = NULL;
120
121 if (tx_ring->desc) {
122 dma_free_coherent(tx_ring->dev, tx_ring->size,
123 tx_ring->desc, tx_ring->dma);
124 tx_ring->desc = NULL;
125 }
126}
127
128/**
129 * i40e_get_tx_pending - how many tx descriptors not processed
130 * @tx_ring: the ring of descriptors
131 *
132 * Since there is no access to the ring head register
133 * in XL710, we need to use our local copies
134 **/
135static u32 i40e_get_tx_pending(struct i40e_ring *ring)
136{
137 u32 ntu = ((ring->next_to_clean <= ring->next_to_use)
138 ? ring->next_to_use
139 : ring->next_to_use + ring->count);
140 return ntu - ring->next_to_clean;
141}
142
143/**
144 * i40e_check_tx_hang - Is there a hang in the Tx queue
145 * @tx_ring: the ring of descriptors
146 **/
147static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
148{
149 u32 tx_pending = i40e_get_tx_pending(tx_ring);
150 bool ret = false;
151
152 clear_check_for_tx_hang(tx_ring);
153
154 /* Check for a hung queue, but be thorough. This verifies
155 * that a transmit has been completed since the previous
156 * check AND there is at least one packet pending. The
157 * ARMED bit is set to indicate a potential hang. The
158 * bit is cleared if a pause frame is received to remove
159 * false hang detection due to PFC or 802.3x frames. By
160 * requiring this to fail twice we avoid races with
161 * PFC clearing the ARMED bit and conditions where we
162 * run the check_tx_hang logic with a transmit completion
163 * pending but without time to complete it yet.
164 */
165 if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) &&
166 tx_pending) {
167 /* make sure it is true for two checks in a row */
168 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
169 &tx_ring->state);
170 } else {
171 /* update completed stats and disarm the hang check */
172 tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets;
173 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
174 }
175
176 return ret;
177}
178
1943d8ba
JB		 179/**
180 * i40e_get_head - Retrieve head from head writeback
181 * @tx_ring: tx ring to fetch head of
182 *
183 * Returns value of Tx ring head based on value stored
184 * in head write-back location
185 **/
186static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
187{
188 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
189
190 return le32_to_cpu(*(volatile __le32 *)head);
191}
192
7f12ad74
GR		 193/**
194 * i40e_clean_tx_irq - Reclaim resources after transmit completes
195 * @tx_ring: tx ring to clean
196 * @budget: how many cleans we're allowed
197 *
198 * Returns true if there's any budget left (e.g. the clean is finished)
199 **/
200static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
201{
202 u16 i = tx_ring->next_to_clean;
203 struct i40e_tx_buffer *tx_buf;
1943d8ba 204 struct i40e_tx_desc *tx_head;
7f12ad74
GR		 205 struct i40e_tx_desc *tx_desc;
206 unsigned int total_packets = 0;
207 unsigned int total_bytes = 0;
208
209 tx_buf = &tx_ring->tx_bi[i];
210 tx_desc = I40E_TX_DESC(tx_ring, i);
211 i -= tx_ring->count;
212
1943d8ba
JB		 213 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
214
7f12ad74
GR		 215 do {
216 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
217
218 /* if next_to_watch is not set then there is no work pending */
219 if (!eop_desc)
220 break;
221
222 /* prevent any other reads prior to eop_desc */
223 read_barrier_depends();
224
1943d8ba
JB		 225 /* we have caught up to head, no work left to do */
226 if (tx_head == tx_desc)
7f12ad74
GR		 227 break;
228
229 /* clear next_to_watch to prevent false hangs */
230 tx_buf->next_to_watch = NULL;
231
232 /* update the statistics for this packet */
233 total_bytes += tx_buf->bytecount;
234 total_packets += tx_buf->gso_segs;
235
236 /* free the skb */
237 dev_kfree_skb_any(tx_buf->skb);
238
239 /* unmap skb header data */
240 dma_unmap_single(tx_ring->dev,
241 dma_unmap_addr(tx_buf, dma),
242 dma_unmap_len(tx_buf, len),
243 DMA_TO_DEVICE);
244
245 /* clear tx_buffer data */
246 tx_buf->skb = NULL;
247 dma_unmap_len_set(tx_buf, len, 0);
248
249 /* unmap remaining buffers */
250 while (tx_desc != eop_desc) {
251
252 tx_buf++;
253 tx_desc++;
254 i++;
255 if (unlikely(!i)) {
256 i -= tx_ring->count;
257 tx_buf = tx_ring->tx_bi;
258 tx_desc = I40E_TX_DESC(tx_ring, 0);
259 }
260
261 /* unmap any remaining paged data */
262 if (dma_unmap_len(tx_buf, len)) {
263 dma_unmap_page(tx_ring->dev,
264 dma_unmap_addr(tx_buf, dma),
265 dma_unmap_len(tx_buf, len),
266 DMA_TO_DEVICE);
267 dma_unmap_len_set(tx_buf, len, 0);
268 }
269 }
270
271 /* move us one more past the eop_desc for start of next pkt */
272 tx_buf++;
273 tx_desc++;
274 i++;
275 if (unlikely(!i)) {
276 i -= tx_ring->count;
277 tx_buf = tx_ring->tx_bi;
278 tx_desc = I40E_TX_DESC(tx_ring, 0);
279 }
280
281 /* update budget accounting */
282 budget--;
283 } while (likely(budget));
284
285 i += tx_ring->count;
286 tx_ring->next_to_clean = i;
287 u64_stats_update_begin(&tx_ring->syncp);
288 tx_ring->stats.bytes += total_bytes;
289 tx_ring->stats.packets += total_packets;
290 u64_stats_update_end(&tx_ring->syncp);
291 tx_ring->q_vector->tx.total_bytes += total_bytes;
292 tx_ring->q_vector->tx.total_packets += total_packets;
293
294 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
295 /* schedule immediate reset if we believe we hung */
296 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
297 " VSI <%d>\n"
298 " Tx Queue <%d>\n"
299 " next_to_use <%x>\n"
300 " next_to_clean <%x>\n",
301 tx_ring->vsi->seid,
302 tx_ring->queue_index,
303 tx_ring->next_to_use, i);
304 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
305 " time_stamp <%lx>\n"
306 " jiffies <%lx>\n",
307 tx_ring->tx_bi[i].time_stamp, jiffies);
308
309 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
310
311 dev_info(tx_ring->dev,
312 "tx hang detected on queue %d, resetting adapter\n",
313 tx_ring->queue_index);
314
315 tx_ring->netdev->netdev_ops->ndo_tx_timeout(tx_ring->netdev);
316
317 /* the adapter is about to reset, no point in enabling stuff */
318 return true;
319 }
320
321 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
322 tx_ring->queue_index),
323 total_packets, total_bytes);
324
325#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
326 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
327 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
328 /* Make sure that anybody stopping the queue after this
329 * sees the new next_to_clean.
330 */
331 smp_mb();
332 if (__netif_subqueue_stopped(tx_ring->netdev,
333 tx_ring->queue_index) &&
334 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
335 netif_wake_subqueue(tx_ring->netdev,
336 tx_ring->queue_index);
337 ++tx_ring->tx_stats.restart_queue;
338 }
339 }
340
341 return budget > 0;
342}
343
344/**
345 * i40e_set_new_dynamic_itr - Find new ITR level
346 * @rc: structure containing ring performance data
347 *
348 * Stores a new ITR value based on packets and byte counts during
349 * the last interrupt. The advantage of per interrupt computation
350 * is faster updates and more accurate ITR for the current traffic
351 * pattern. Constants in this function were computed based on
352 * theoretical maximum wire speed and thresholds were set based on
353 * testing data as well as attempting to minimize response time
354 * while increasing bulk throughput.
355 **/
356static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
357{
358 enum i40e_latency_range new_latency_range = rc->latency_range;
359 u32 new_itr = rc->itr;
360 int bytes_per_int;
361
362 if (rc->total_packets == 0 || !rc->itr)
363 return;
364
365 /* simple throttlerate management
366 * 0-10MB/s lowest (100000 ints/s)
367 * 10-20MB/s low (20000 ints/s)
368 * 20-1249MB/s bulk (8000 ints/s)
369 */
370 bytes_per_int = rc->total_bytes / rc->itr;
371 switch (rc->itr) {
372 case I40E_LOWEST_LATENCY:
373 if (bytes_per_int > 10)
374 new_latency_range = I40E_LOW_LATENCY;
375 break;
376 case I40E_LOW_LATENCY:
377 if (bytes_per_int > 20)
378 new_latency_range = I40E_BULK_LATENCY;
379 else if (bytes_per_int <= 10)
380 new_latency_range = I40E_LOWEST_LATENCY;
381 break;
382 case I40E_BULK_LATENCY:
383 if (bytes_per_int <= 20)
384 rc->latency_range = I40E_LOW_LATENCY;
385 break;
386 }
387
388 switch (new_latency_range) {
389 case I40E_LOWEST_LATENCY:
390 new_itr = I40E_ITR_100K;
391 break;
392 case I40E_LOW_LATENCY:
393 new_itr = I40E_ITR_20K;
394 break;
395 case I40E_BULK_LATENCY:
396 new_itr = I40E_ITR_8K;
397 break;
398 default:
399 break;
400 }
401
402 if (new_itr != rc->itr) {
403 /* do an exponential smoothing */
404 new_itr = (10 * new_itr * rc->itr) /
405 ((9 * new_itr) + rc->itr);
406 rc->itr = new_itr & I40E_MAX_ITR;
407 }
408
409 rc->total_bytes = 0;
410 rc->total_packets = 0;
411}
412
413/**
414 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
415 * @q_vector: the vector to adjust
416 **/
417static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
418{
419 u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
420 struct i40e_hw *hw = &q_vector->vsi->back->hw;
421 u32 reg_addr;
422 u16 old_itr;
423
424 reg_addr = I40E_VFINT_ITRN1(I40E_RX_ITR, vector - 1);
425 old_itr = q_vector->rx.itr;
426 i40e_set_new_dynamic_itr(&q_vector->rx);
427 if (old_itr != q_vector->rx.itr)
428 wr32(hw, reg_addr, q_vector->rx.itr);
429
430 reg_addr = I40E_VFINT_ITRN1(I40E_TX_ITR, vector - 1);
431 old_itr = q_vector->tx.itr;
432 i40e_set_new_dynamic_itr(&q_vector->tx);
433 if (old_itr != q_vector->tx.itr)
434 wr32(hw, reg_addr, q_vector->tx.itr);
435}
436
437/**
438 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
439 * @tx_ring: the tx ring to set up
440 *
441 * Return 0 on success, negative on error
442 **/
443int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
444{
445 struct device *dev = tx_ring->dev;
446 int bi_size;
447
448 if (!dev)
449 return -ENOMEM;
450
451 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
452 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
453 if (!tx_ring->tx_bi)
454 goto err;
455
456 /* round up to nearest 4K */
457 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1943d8ba
JB		 458 /* add u32 for head writeback, align after this takes care of
459 * guaranteeing this is at least one cache line in size
460 */
461 tx_ring->size += sizeof(u32);
7f12ad74
GR		 462 tx_ring->size = ALIGN(tx_ring->size, 4096);
463 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
464 &tx_ring->dma, GFP_KERNEL);
465 if (!tx_ring->desc) {
466 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
467 tx_ring->size);
468 goto err;
469 }
470
471 tx_ring->next_to_use = 0;
472 tx_ring->next_to_clean = 0;
473 return 0;
474
475err:
476 kfree(tx_ring->tx_bi);
477 tx_ring->tx_bi = NULL;
478 return -ENOMEM;
479}
480
481/**
482 * i40evf_clean_rx_ring - Free Rx buffers
483 * @rx_ring: ring to be cleaned
484 **/
485void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
486{
487 struct device *dev = rx_ring->dev;
488 struct i40e_rx_buffer *rx_bi;
489 unsigned long bi_size;
490 u16 i;
491
492 /* ring already cleared, nothing to do */
493 if (!rx_ring->rx_bi)
494 return;
495
496 /* Free all the Rx ring sk_buffs */
497 for (i = 0; i < rx_ring->count; i++) {
498 rx_bi = &rx_ring->rx_bi[i];
499 if (rx_bi->dma) {
500 dma_unmap_single(dev,
501 rx_bi->dma,
502 rx_ring->rx_buf_len,
503 DMA_FROM_DEVICE);
504 rx_bi->dma = 0;
505 }
506 if (rx_bi->skb) {
507 dev_kfree_skb(rx_bi->skb);
508 rx_bi->skb = NULL;
509 }
510 if (rx_bi->page) {
511 if (rx_bi->page_dma) {
512 dma_unmap_page(dev,
513 rx_bi->page_dma,
514 PAGE_SIZE / 2,
515 DMA_FROM_DEVICE);
516 rx_bi->page_dma = 0;
517 }
518 __free_page(rx_bi->page);
519 rx_bi->page = NULL;
520 rx_bi->page_offset = 0;
521 }
522 }
523
524 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
525 memset(rx_ring->rx_bi, 0, bi_size);
526
527 /* Zero out the descriptor ring */
528 memset(rx_ring->desc, 0, rx_ring->size);
529
530 rx_ring->next_to_clean = 0;
531 rx_ring->next_to_use = 0;
532}
533
534/**
535 * i40evf_free_rx_resources - Free Rx resources
536 * @rx_ring: ring to clean the resources from
537 *
538 * Free all receive software resources
539 **/
540void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
541{
542 i40evf_clean_rx_ring(rx_ring);
543 kfree(rx_ring->rx_bi);
544 rx_ring->rx_bi = NULL;
545
546 if (rx_ring->desc) {
547 dma_free_coherent(rx_ring->dev, rx_ring->size,
548 rx_ring->desc, rx_ring->dma);
549 rx_ring->desc = NULL;
550 }
551}
552
553/**
554 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
555 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
556 *
557 * Returns 0 on success, negative on failure
558 **/
559int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
560{
561 struct device *dev = rx_ring->dev;
562 int bi_size;
563
564 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
565 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
566 if (!rx_ring->rx_bi)
567 goto err;
568
569 /* Round up to nearest 4K */
570 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
571 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
572 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
573 rx_ring->size = ALIGN(rx_ring->size, 4096);
574 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
575 &rx_ring->dma, GFP_KERNEL);
576
577 if (!rx_ring->desc) {
578 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
579 rx_ring->size);
580 goto err;
581 }
582
583 rx_ring->next_to_clean = 0;
584 rx_ring->next_to_use = 0;
585
586 return 0;
587err:
588 kfree(rx_ring->rx_bi);
589 rx_ring->rx_bi = NULL;
590 return -ENOMEM;
591}
592
593/**
594 * i40e_release_rx_desc - Store the new tail and head values
595 * @rx_ring: ring to bump
596 * @val: new head index
597 **/
598static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
599{
600 rx_ring->next_to_use = val;
601 /* Force memory writes to complete before letting h/w
602 * know there are new descriptors to fetch. (Only
603 * applicable for weak-ordered memory model archs,
604 * such as IA-64).
605 */
606 wmb();
607 writel(val, rx_ring->tail);
608}
609
610/**
611 * i40evf_alloc_rx_buffers - Replace used receive buffers; packet split
612 * @rx_ring: ring to place buffers on
613 * @cleaned_count: number of buffers to replace
614 **/
615void i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
616{
617 u16 i = rx_ring->next_to_use;
618 union i40e_rx_desc *rx_desc;
619 struct i40e_rx_buffer *bi;
620 struct sk_buff *skb;
621
622 /* do nothing if no valid netdev defined */
623 if (!rx_ring->netdev || !cleaned_count)
624 return;
625
626 while (cleaned_count--) {
627 rx_desc = I40E_RX_DESC(rx_ring, i);
628 bi = &rx_ring->rx_bi[i];
629 skb = bi->skb;
630
631 if (!skb) {
632 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
633 rx_ring->rx_buf_len);
634 if (!skb) {
635 rx_ring->rx_stats.alloc_buff_failed++;
636 goto no_buffers;
637 }
638 /* initialize queue mapping */
639 skb_record_rx_queue(skb, rx_ring->queue_index);
640 bi->skb = skb;
641 }
642
643 if (!bi->dma) {
644 bi->dma = dma_map_single(rx_ring->dev,
645 skb->data,
646 rx_ring->rx_buf_len,
647 DMA_FROM_DEVICE);
648 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
649 rx_ring->rx_stats.alloc_buff_failed++;
650 bi->dma = 0;
651 goto no_buffers;
652 }
653 }
654
655 if (ring_is_ps_enabled(rx_ring)) {
656 if (!bi->page) {
657 bi->page = alloc_page(GFP_ATOMIC);
658 if (!bi->page) {
659 rx_ring->rx_stats.alloc_page_failed++;
660 goto no_buffers;
661 }
662 }
663
664 if (!bi->page_dma) {
665 /* use a half page if we're re-using */
666 bi->page_offset ^= PAGE_SIZE / 2;
667 bi->page_dma = dma_map_page(rx_ring->dev,
668 bi->page,
669 bi->page_offset,
670 PAGE_SIZE / 2,
671 DMA_FROM_DEVICE);
672 if (dma_mapping_error(rx_ring->dev,
673 bi->page_dma)) {
674 rx_ring->rx_stats.alloc_page_failed++;
675 bi->page_dma = 0;
676 goto no_buffers;
677 }
678 }
679
680 /* Refresh the desc even if buffer_addrs didn't change
681 * because each write-back erases this info.
682 */
683 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
684 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
685 } else {
686 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
687 rx_desc->read.hdr_addr = 0;
688 }
689 i++;
690 if (i == rx_ring->count)
691 i = 0;
692 }
693
694no_buffers:
695 if (rx_ring->next_to_use != i)
696 i40e_release_rx_desc(rx_ring, i);
697}
698
699/**
700 * i40e_receive_skb - Send a completed packet up the stack
701 * @rx_ring: rx ring in play
702 * @skb: packet to send up
703 * @vlan_tag: vlan tag for packet
704 **/
705static void i40e_receive_skb(struct i40e_ring *rx_ring,
706 struct sk_buff *skb, u16 vlan_tag)
707{
708 struct i40e_q_vector *q_vector = rx_ring->q_vector;
709 struct i40e_vsi *vsi = rx_ring->vsi;
710 u64 flags = vsi->back->flags;
711
712 if (vlan_tag & VLAN_VID_MASK)
713 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
714
715 if (flags & I40E_FLAG_IN_NETPOLL)
716 netif_rx(skb);
717 else
718 napi_gro_receive(&q_vector->napi, skb);
719}
720
721/**
722 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
723 * @vsi: the VSI we care about
724 * @skb: skb currently being received and modified
725 * @rx_status: status value of last descriptor in packet
726 * @rx_error: error value of last descriptor in packet
727 * @rx_ptype: ptype value of last descriptor in packet
728 **/
729static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
730 struct sk_buff *skb,
731 u32 rx_status,
732 u32 rx_error,
733 u16 rx_ptype)
734{
8a3c91cc
JB		 735 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
736 bool ipv4 = false, ipv6 = false;
7f12ad74
GR		 737 bool ipv4_tunnel, ipv6_tunnel;
738 __wsum rx_udp_csum;
7f12ad74 739 struct iphdr *iph;
8a3c91cc 740 __sum16 csum;
7f12ad74
GR		 741
742 ipv4_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
743 (rx_ptype < I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
744 ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
745 (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
746
747 skb->encapsulation = ipv4_tunnel || ipv6_tunnel;
748 skb->ip_summed = CHECKSUM_NONE;
749
750 /* Rx csum enabled and ip headers found? */
8a3c91cc
JB		 751 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
752 return;
753
754 /* did the hardware decode the packet and checksum? */
755 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
756 return;
757
758 /* both known and outer_ip must be set for the below code to work */
759 if (!(decoded.known && decoded.outer_ip))
7f12ad74
GR		 760 return;
761
8a3c91cc
JB		 762 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
763 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
764 ipv4 = true;
765 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
766 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
767 ipv6 = true;
768
769 if (ipv4 &&
770 (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
771 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))))
772 goto checksum_fail;
773
ddf1d0d7 774 /* likely incorrect csum if alternate IP extension headers found */
8a3c91cc 775 if (ipv6 &&
8a3c91cc
JB		 776 rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
777 /* don't increment checksum err here, non-fatal err */
7f12ad74
GR		 778 return;
779
8a3c91cc
JB		 780 /* there was some L4 error, count error and punt packet to the stack */
781 if (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))
782 goto checksum_fail;
783
784 /* handle packets that were not able to be checksummed due
785 * to arrival speed, in this case the stack can compute
786 * the csum.
787 */
788 if (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT))
7f12ad74 789 return;
7f12ad74 790
8a3c91cc
JB		 791 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
792 * it in the driver, hardware does not do it for us.
793 * Since L3L4P bit was set we assume a valid IHL value (>=5)
794 * so the total length of IPv4 header is IHL*4 bytes
795 * The UDP_0 bit *may* bet set if the *inner* header is UDP
796 */
7f12ad74 797 if (ipv4_tunnel &&
8a3c91cc 798 (decoded.inner_prot != I40E_RX_PTYPE_INNER_PROT_UDP) &&
7f12ad74 799 !(rx_status & (1 << I40E_RX_DESC_STATUS_UDP_0_SHIFT))) {
7f12ad74
GR		 800 skb->transport_header = skb->mac_header +
801 sizeof(struct ethhdr) +
802 (ip_hdr(skb)->ihl * 4);
803
804 /* Add 4 bytes for VLAN tagged packets */
805 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
806 skb->protocol == htons(ETH_P_8021AD))
807 ? VLAN_HLEN : 0;
808
809 rx_udp_csum = udp_csum(skb);
810 iph = ip_hdr(skb);
811 csum = csum_tcpudp_magic(
812 iph->saddr, iph->daddr,
813 (skb->len - skb_transport_offset(skb)),
814 IPPROTO_UDP, rx_udp_csum);
815
8a3c91cc
JB		 816 if (udp_hdr(skb)->check != csum)
817 goto checksum_fail;
7f12ad74
GR		 818 }
819
820 skb->ip_summed = CHECKSUM_UNNECESSARY;
8a3c91cc
JB		 821
822 return;
823
824checksum_fail:
825 vsi->back->hw_csum_rx_error++;
7f12ad74
GR		 826}
827
828/**
829 * i40e_rx_hash - returns the hash value from the Rx descriptor
830 * @ring: descriptor ring
831 * @rx_desc: specific descriptor
832 **/
833static inline u32 i40e_rx_hash(struct i40e_ring *ring,
834 union i40e_rx_desc *rx_desc)
835{
836 const __le64 rss_mask =
837 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
838 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
839
840 if ((ring->netdev->features & NETIF_F_RXHASH) &&
841 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
842 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
843 else
844 return 0;
845}
846
206812b5
JB		 847/**
848 * i40e_ptype_to_hash - get a hash type
849 * @ptype: the ptype value from the descriptor
850 *
851 * Returns a hash type to be used by skb_set_hash
852 **/
853static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
854{
855 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
856
857 if (!decoded.known)
858 return PKT_HASH_TYPE_NONE;
859
860 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
861 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
862 return PKT_HASH_TYPE_L4;
863 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
864 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
865 return PKT_HASH_TYPE_L3;
866 else
867 return PKT_HASH_TYPE_L2;
868}
869
7f12ad74
GR		 870/**
871 * i40e_clean_rx_irq - Reclaim resources after receive completes
872 * @rx_ring: rx ring to clean
873 * @budget: how many cleans we're allowed
874 *
875 * Returns true if there's any budget left (e.g. the clean is finished)
876 **/
877static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
878{
879 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
880 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
881 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
882 const int current_node = numa_node_id();
883 struct i40e_vsi *vsi = rx_ring->vsi;
884 u16 i = rx_ring->next_to_clean;
885 union i40e_rx_desc *rx_desc;
886 u32 rx_error, rx_status;
206812b5 887 u8 rx_ptype;
7f12ad74 888 u64 qword;
7f12ad74
GR		 889
890 rx_desc = I40E_RX_DESC(rx_ring, i);
891 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
af1a2a9c
JB		 892 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
893 I40E_RXD_QW1_STATUS_SHIFT;
7f12ad74
GR		 894
895 while (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
896 union i40e_rx_desc *next_rxd;
897 struct i40e_rx_buffer *rx_bi;
898 struct sk_buff *skb;
899 u16 vlan_tag;
900 rx_bi = &rx_ring->rx_bi[i];
901 skb = rx_bi->skb;
902 prefetch(skb->data);
903
904 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
905 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
906 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
907 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
908 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
909 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
910
911 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
912 I40E_RXD_QW1_ERROR_SHIFT;
913 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
914 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
915
916 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
917 I40E_RXD_QW1_PTYPE_SHIFT;
918 rx_bi->skb = NULL;
919
920 /* This memory barrier is needed to keep us from reading
921 * any other fields out of the rx_desc until we know the
922 * STATUS_DD bit is set
923 */
924 rmb();
925
926 /* Get the header and possibly the whole packet
927 * If this is an skb from previous receive dma will be 0
928 */
929 if (rx_bi->dma) {
930 u16 len;
931
932 if (rx_hbo)
933 len = I40E_RX_HDR_SIZE;
934 else if (rx_sph)
935 len = rx_header_len;
936 else if (rx_packet_len)
937 len = rx_packet_len; /* 1buf/no split found */
938 else
939 len = rx_header_len; /* split always mode */
940
941 skb_put(skb, len);
942 dma_unmap_single(rx_ring->dev,
943 rx_bi->dma,
944 rx_ring->rx_buf_len,
945 DMA_FROM_DEVICE);
946 rx_bi->dma = 0;
947 }
948
949 /* Get the rest of the data if this was a header split */
950 if (ring_is_ps_enabled(rx_ring) && rx_packet_len) {
951
952 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
953 rx_bi->page,
954 rx_bi->page_offset,
955 rx_packet_len);
956
957 skb->len += rx_packet_len;
958 skb->data_len += rx_packet_len;
959 skb->truesize += rx_packet_len;
960
961 if ((page_count(rx_bi->page) == 1) &&
962 (page_to_nid(rx_bi->page) == current_node))
963 get_page(rx_bi->page);
964 else
965 rx_bi->page = NULL;
966
967 dma_unmap_page(rx_ring->dev,
968 rx_bi->page_dma,
969 PAGE_SIZE / 2,
970 DMA_FROM_DEVICE);
971 rx_bi->page_dma = 0;
972 }
973 I40E_RX_NEXT_DESC_PREFETCH(rx_ring, i, next_rxd);
974
975 if (unlikely(
976 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
977 struct i40e_rx_buffer *next_buffer;
978
979 next_buffer = &rx_ring->rx_bi[i];
980
981 if (ring_is_ps_enabled(rx_ring)) {
982 rx_bi->skb = next_buffer->skb;
983 rx_bi->dma = next_buffer->dma;
984 next_buffer->skb = skb;
985 next_buffer->dma = 0;
986 }
987 rx_ring->rx_stats.non_eop_descs++;
988 goto next_desc;
989 }
990
991 /* ERR_MASK will only have valid bits if EOP set */
992 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
993 dev_kfree_skb_any(skb);
8a3c91cc
JB		 994 /* TODO: shouldn't we increment a counter indicating the
995 * drop?
996 */
7f12ad74
GR		 997 goto next_desc;
998 }
999
206812b5
JB		 1000 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1001 i40e_ptype_to_hash(rx_ptype));
7f12ad74
GR		 1002 /* probably a little skewed due to removing CRC */
1003 total_rx_bytes += skb->len;
1004 total_rx_packets++;
1005
1006 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1007
1008 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1009
1010 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1011 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1012 : 0;
1013 i40e_receive_skb(rx_ring, skb, vlan_tag);
1014
1015 rx_ring->netdev->last_rx = jiffies;
1016 budget--;
1017next_desc:
1018 rx_desc->wb.qword1.status_error_len = 0;
1019 if (!budget)
1020 break;
1021
1022 cleaned_count++;
1023 /* return some buffers to hardware, one at a time is too slow */
1024 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1025 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
1026 cleaned_count = 0;
1027 }
1028
1029 /* use prefetched values */
1030 rx_desc = next_rxd;
1031 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1032 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1033 I40E_RXD_QW1_STATUS_SHIFT;
1034 }
1035
1036 rx_ring->next_to_clean = i;
1037 u64_stats_update_begin(&rx_ring->syncp);
1038 rx_ring->stats.packets += total_rx_packets;
1039 rx_ring->stats.bytes += total_rx_bytes;
1040 u64_stats_update_end(&rx_ring->syncp);
1041 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1042 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1043
1044 if (cleaned_count)
1045 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
1046
1047 return budget > 0;
1048}
1049
1050/**
1051 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1052 * @napi: napi struct with our devices info in it
1053 * @budget: amount of work driver is allowed to do this pass, in packets
1054 *
1055 * This function will clean all queues associated with a q_vector.
1056 *
1057 * Returns the amount of work done
1058 **/
1059int i40evf_napi_poll(struct napi_struct *napi, int budget)
1060{
1061 struct i40e_q_vector *q_vector =
1062 container_of(napi, struct i40e_q_vector, napi);
1063 struct i40e_vsi *vsi = q_vector->vsi;
1064 struct i40e_ring *ring;
1065 bool clean_complete = true;
1066 int budget_per_ring;
1067
1068 if (test_bit(__I40E_DOWN, &vsi->state)) {
1069 napi_complete(napi);
1070 return 0;
1071 }
1072
1073 /* Since the actual Tx work is minimal, we can give the Tx a larger
1074 * budget and be more aggressive about cleaning up the Tx descriptors.
1075 */
1076 i40e_for_each_ring(ring, q_vector->tx)
1077 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
1078
1079 /* We attempt to distribute budget to each Rx queue fairly, but don't
1080 * allow the budget to go below 1 because that would exit polling early.
1081 */
1082 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1083
1084 i40e_for_each_ring(ring, q_vector->rx)
1085 clean_complete &= i40e_clean_rx_irq(ring, budget_per_ring);
1086
1087 /* If work not completed, return budget and polling will return */
1088 if (!clean_complete)
1089 return budget;
1090
1091 /* Work is done so exit the polling mode and re-enable the interrupt */
1092 napi_complete(napi);
1093 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1094 ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1095 i40e_update_dynamic_itr(q_vector);
1096
1097 if (!test_bit(__I40E_DOWN, &vsi->state))
1098 i40evf_irq_enable_queues(vsi->back, 1 << q_vector->v_idx);
1099
1100 return 0;
1101}
1102
1103/**
1104 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1105 * @skb: send buffer
1106 * @tx_ring: ring to send buffer on
1107 * @flags: the tx flags to be set
1108 *
1109 * Checks the skb and set up correspondingly several generic transmit flags
1110 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1111 *
1112 * Returns error code indicate the frame should be dropped upon error and the
1113 * otherwise returns 0 to indicate the flags has been set properly.
1114 **/
1115static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
1116 struct i40e_ring *tx_ring,
1117 u32 *flags)
1118{
1119 __be16 protocol = skb->protocol;
1120 u32 tx_flags = 0;
1121
1122 /* if we have a HW VLAN tag being added, default to the HW one */
1123 if (vlan_tx_tag_present(skb)) {
1124 tx_flags |= vlan_tx_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1125 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1126 /* else if it is a SW VLAN, check the next protocol and store the tag */
1127 } else if (protocol == htons(ETH_P_8021Q)) {
1128 struct vlan_hdr *vhdr, _vhdr;
1129 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1130 if (!vhdr)
1131 return -EINVAL;
1132
1133 protocol = vhdr->h_vlan_encapsulated_proto;
1134 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1135 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1136 }
1137
1138 *flags = tx_flags;
1139 return 0;
1140}
1141
1142/**
1143 * i40e_tso - set up the tso context descriptor
1144 * @tx_ring: ptr to the ring to send
1145 * @skb: ptr to the skb we're sending
1146 * @tx_flags: the collected send information
1147 * @protocol: the send protocol
1148 * @hdr_len: ptr to the size of the packet header
1149 * @cd_tunneling: ptr to context descriptor bits
1150 *
1151 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1152 **/
1153static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
1154 u32 tx_flags, __be16 protocol, u8 *hdr_len,
1155 u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
1156{
1157 u32 cd_cmd, cd_tso_len, cd_mss;
fe6d4aa4 1158 struct ipv6hdr *ipv6h;
7f12ad74
GR		 1159 struct tcphdr *tcph;
1160 struct iphdr *iph;
1161 u32 l4len;
1162 int err;
7f12ad74
GR		 1163
1164 if (!skb_is_gso(skb))
1165 return 0;
1166
fe6d4aa4
FR		 1167 err = skb_cow_head(skb, 0);
1168 if (err < 0)
1169 return err;
7f12ad74
GR		 1170
1171 if (protocol == htons(ETH_P_IP)) {
1172 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
1173 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1174 iph->tot_len = 0;
1175 iph->check = 0;
1176 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
1177 0, IPPROTO_TCP, 0);
1178 } else if (skb_is_gso_v6(skb)) {
1179
1180 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb)
1181 : ipv6_hdr(skb);
1182 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1183 ipv6h->payload_len = 0;
1184 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
1185 0, IPPROTO_TCP, 0);
1186 }
1187
1188 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1189 *hdr_len = (skb->encapsulation
1190 ? (skb_inner_transport_header(skb) - skb->data)
1191 : skb_transport_offset(skb)) + l4len;
1192
1193 /* find the field values */
1194 cd_cmd = I40E_TX_CTX_DESC_TSO;
1195 cd_tso_len = skb->len - *hdr_len;
1196 cd_mss = skb_shinfo(skb)->gso_size;
1197 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1198 ((u64)cd_tso_len <<
1199 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1200 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1201 return 1;
1202}
1203
1204/**
1205 * i40e_tx_enable_csum - Enable Tx checksum offloads
1206 * @skb: send buffer
1207 * @tx_flags: Tx flags currently set
1208 * @td_cmd: Tx descriptor command bits to set
1209 * @td_offset: Tx descriptor header offsets to set
1210 * @cd_tunneling: ptr to context desc bits
1211 **/
1212static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
1213 u32 *td_cmd, u32 *td_offset,
1214 struct i40e_ring *tx_ring,
1215 u32 *cd_tunneling)
1216{
1217 struct ipv6hdr *this_ipv6_hdr;
1218 unsigned int this_tcp_hdrlen;
1219 struct iphdr *this_ip_hdr;
1220 u32 network_hdr_len;
1221 u8 l4_hdr = 0;
1222
1223 if (skb->encapsulation) {
1224 network_hdr_len = skb_inner_network_header_len(skb);
1225 this_ip_hdr = inner_ip_hdr(skb);
1226 this_ipv6_hdr = inner_ipv6_hdr(skb);
1227 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
1228
1229 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1230
1231 if (tx_flags & I40E_TX_FLAGS_TSO) {
1232 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
1233 ip_hdr(skb)->check = 0;
1234 } else {
1235 *cd_tunneling |=
1236 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1237 }
1238 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1239 if (tx_flags & I40E_TX_FLAGS_TSO) {
1240 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
1241 ip_hdr(skb)->check = 0;
1242 } else {
1243 *cd_tunneling |=
1244 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1245 }
1246 }
1247
1248 /* Now set the ctx descriptor fields */
1249 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
1250 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
1251 I40E_TXD_CTX_UDP_TUNNELING |
1252 ((skb_inner_network_offset(skb) -
1253 skb_transport_offset(skb)) >> 1) <<
1254 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1255
1256 } else {
1257 network_hdr_len = skb_network_header_len(skb);
1258 this_ip_hdr = ip_hdr(skb);
1259 this_ipv6_hdr = ipv6_hdr(skb);
1260 this_tcp_hdrlen = tcp_hdrlen(skb);
1261 }
1262
1263 /* Enable IP checksum offloads */
1264 if (tx_flags & I40E_TX_FLAGS_IPV4) {
1265 l4_hdr = this_ip_hdr->protocol;
1266 /* the stack computes the IP header already, the only time we
1267 * need the hardware to recompute it is in the case of TSO.
1268 */
1269 if (tx_flags & I40E_TX_FLAGS_TSO) {
1270 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
1271 this_ip_hdr->check = 0;
1272 } else {
1273 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
1274 }
1275 /* Now set the td_offset for IP header length */
1276 *td_offset = (network_hdr_len >> 2) <<
1277 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1278 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
1279 l4_hdr = this_ipv6_hdr->nexthdr;
1280 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1281 /* Now set the td_offset for IP header length */
1282 *td_offset = (network_hdr_len >> 2) <<
1283 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1284 }
1285 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
1286 *td_offset |= (skb_network_offset(skb) >> 1) <<
1287 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1288
1289 /* Enable L4 checksum offloads */
1290 switch (l4_hdr) {
1291 case IPPROTO_TCP:
1292 /* enable checksum offloads */
1293 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1294 *td_offset |= (this_tcp_hdrlen >> 2) <<
1295 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1296 break;
1297 case IPPROTO_SCTP:
1298 /* enable SCTP checksum offload */
1299 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1300 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
1301 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1302 break;
1303 case IPPROTO_UDP:
1304 /* enable UDP checksum offload */
1305 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1306 *td_offset |= (sizeof(struct udphdr) >> 2) <<
1307 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1308 break;
1309 default:
1310 break;
1311 }
1312}
1313
1314/**
1315 * i40e_create_tx_ctx Build the Tx context descriptor
1316 * @tx_ring: ring to create the descriptor on
1317 * @cd_type_cmd_tso_mss: Quad Word 1
1318 * @cd_tunneling: Quad Word 0 - bits 0-31
1319 * @cd_l2tag2: Quad Word 0 - bits 32-63
1320 **/
1321static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1322 const u64 cd_type_cmd_tso_mss,
1323 const u32 cd_tunneling, const u32 cd_l2tag2)
1324{
1325 struct i40e_tx_context_desc *context_desc;
1326 int i = tx_ring->next_to_use;
1327
ff40dd5d
JB		 1328 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1329 !cd_tunneling && !cd_l2tag2)
7f12ad74
GR		 1330 return;
1331
1332 /* grab the next descriptor */
1333 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1334
1335 i++;
1336 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1337
1338 /* cpu_to_le32 and assign to struct fields */
1339 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1340 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3efbbb20 1341 context_desc->rsvd = cpu_to_le16(0);
7f12ad74
GR		 1342 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1343}
1344
1345/**
1346 * i40e_tx_map - Build the Tx descriptor
1347 * @tx_ring: ring to send buffer on
1348 * @skb: send buffer
1349 * @first: first buffer info buffer to use
1350 * @tx_flags: collected send information
1351 * @hdr_len: size of the packet header
1352 * @td_cmd: the command field in the descriptor
1353 * @td_offset: offset for checksum or crc
1354 **/
1355static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1356 struct i40e_tx_buffer *first, u32 tx_flags,
1357 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1358{
1359 unsigned int data_len = skb->data_len;
1360 unsigned int size = skb_headlen(skb);
1361 struct skb_frag_struct *frag;
1362 struct i40e_tx_buffer *tx_bi;
1363 struct i40e_tx_desc *tx_desc;
1364 u16 i = tx_ring->next_to_use;
1365 u32 td_tag = 0;
1366 dma_addr_t dma;
1367 u16 gso_segs;
1368
1369 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1370 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1371 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1372 I40E_TX_FLAGS_VLAN_SHIFT;
1373 }
1374
1375 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1376 gso_segs = skb_shinfo(skb)->gso_segs;
1377 else
1378 gso_segs = 1;
1379
1380 /* multiply data chunks by size of headers */
1381 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1382 first->gso_segs = gso_segs;
1383 first->skb = skb;
1384 first->tx_flags = tx_flags;
1385
1386 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1387
1388 tx_desc = I40E_TX_DESC(tx_ring, i);
1389 tx_bi = first;
1390
1391 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1392 if (dma_mapping_error(tx_ring->dev, dma))
1393 goto dma_error;
1394
1395 /* record length, and DMA address */
1396 dma_unmap_len_set(tx_bi, len, size);
1397 dma_unmap_addr_set(tx_bi, dma, dma);
1398
1399 tx_desc->buffer_addr = cpu_to_le64(dma);
1400
1401 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1402 tx_desc->cmd_type_offset_bsz =
1403 build_ctob(td_cmd, td_offset,
1404 I40E_MAX_DATA_PER_TXD, td_tag);
1405
1406 tx_desc++;
1407 i++;
1408 if (i == tx_ring->count) {
1409 tx_desc = I40E_TX_DESC(tx_ring, 0);
1410 i = 0;
1411 }
1412
1413 dma += I40E_MAX_DATA_PER_TXD;
1414 size -= I40E_MAX_DATA_PER_TXD;
1415
1416 tx_desc->buffer_addr = cpu_to_le64(dma);
1417 }
1418
1419 if (likely(!data_len))
1420 break;
1421
1422 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
1423 size, td_tag);
1424
1425 tx_desc++;
1426 i++;
1427 if (i == tx_ring->count) {
1428 tx_desc = I40E_TX_DESC(tx_ring, 0);
1429 i = 0;
1430 }
1431
1432 size = skb_frag_size(frag);
1433 data_len -= size;
1434
1435 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1436 DMA_TO_DEVICE);
1437
1438 tx_bi = &tx_ring->tx_bi[i];
1439 }
1440
1943d8ba
JB		 1441 /* Place RS bit on last descriptor of any packet that spans across the
1442 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
1443 */
1444#define WB_STRIDE 0x3
1445 if (((i & WB_STRIDE) != WB_STRIDE) &&
1446 (first <= &tx_ring->tx_bi[i]) &&
1447 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
1448 tx_desc->cmd_type_offset_bsz =
1449 build_ctob(td_cmd, td_offset, size, td_tag) |
1450 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
1451 I40E_TXD_QW1_CMD_SHIFT);
1452 } else {
1453 tx_desc->cmd_type_offset_bsz =
1454 build_ctob(td_cmd, td_offset, size, td_tag) |
1455 cpu_to_le64((u64)I40E_TXD_CMD <<
1456 I40E_TXD_QW1_CMD_SHIFT);
1457 }
7f12ad74
GR		 1458
1459 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
1460 tx_ring->queue_index),
1461 first->bytecount);
1462
1463 /* set the timestamp */
1464 first->time_stamp = jiffies;
1465
1466 /* Force memory writes to complete before letting h/w
1467 * know there are new descriptors to fetch. (Only
1468 * applicable for weak-ordered memory model archs,
1469 * such as IA-64).
1470 */
1471 wmb();
1472
1473 /* set next_to_watch value indicating a packet is present */
1474 first->next_to_watch = tx_desc;
1475
1476 i++;
1477 if (i == tx_ring->count)
1478 i = 0;
1479
1480 tx_ring->next_to_use = i;
1481
1482 /* notify HW of packet */
1483 writel(i, tx_ring->tail);
1484
1485 return;
1486
1487dma_error:
1488 dev_info(tx_ring->dev, "TX DMA map failed\n");
1489
1490 /* clear dma mappings for failed tx_bi map */
1491 for (;;) {
1492 tx_bi = &tx_ring->tx_bi[i];
1493 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
1494 if (tx_bi == first)
1495 break;
1496 if (i == 0)
1497 i = tx_ring->count;
1498 i--;
1499 }
1500
1501 tx_ring->next_to_use = i;
1502}
1503
1504/**
1505 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
1506 * @tx_ring: the ring to be checked
1507 * @size: the size buffer we want to assure is available
1508 *
1509 * Returns -EBUSY if a stop is needed, else 0
1510 **/
1511static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1512{
1513 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1514 /* Memory barrier before checking head and tail */
1515 smp_mb();
1516
1517 /* Check again in a case another CPU has just made room available. */
1518 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1519 return -EBUSY;
1520
1521 /* A reprieve! - use start_queue because it doesn't call schedule */
1522 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1523 ++tx_ring->tx_stats.restart_queue;
1524 return 0;
1525}
1526
1527/**
1528 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
1529 * @tx_ring: the ring to be checked
1530 * @size: the size buffer we want to assure is available
1531 *
1532 * Returns 0 if stop is not needed
1533 **/
1534static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1535{
1536 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
1537 return 0;
1538 return __i40e_maybe_stop_tx(tx_ring, size);
1539}
1540
1541/**
1542 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
1543 * @skb: send buffer
1544 * @tx_ring: ring to send buffer on
1545 *
1546 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
1547 * there is not enough descriptors available in this ring since we need at least
1548 * one descriptor.
1549 **/
1550static int i40e_xmit_descriptor_count(struct sk_buff *skb,
1551 struct i40e_ring *tx_ring)
1552{
7f12ad74 1553 unsigned int f;
7f12ad74
GR		 1554 int count = 0;
1555
1556 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
1557 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
be560521 1558 * + 4 desc gap to avoid the cache line where head is,
7f12ad74
GR		 1559 * + 1 desc for context descriptor,
1560 * otherwise try next time
1561 */
7f12ad74
GR		 1562 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1563 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
980093eb 1564
7f12ad74 1565 count += TXD_USE_COUNT(skb_headlen(skb));
be560521 1566 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
7f12ad74
GR		 1567 tx_ring->tx_stats.tx_busy++;
1568 return 0;
1569 }
1570 return count;
1571}
1572
1573/**
1574 * i40e_xmit_frame_ring - Sends buffer on Tx ring
1575 * @skb: send buffer
1576 * @tx_ring: ring to send buffer on
1577 *
1578 * Returns NETDEV_TX_OK if sent, else an error code
1579 **/
1580static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
1581 struct i40e_ring *tx_ring)
1582{
1583 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
1584 u32 cd_tunneling = 0, cd_l2tag2 = 0;
1585 struct i40e_tx_buffer *first;
1586 u32 td_offset = 0;
1587 u32 tx_flags = 0;
1588 __be16 protocol;
1589 u32 td_cmd = 0;
1590 u8 hdr_len = 0;
1591 int tso;
1592 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
1593 return NETDEV_TX_BUSY;
1594
1595 /* prepare the xmit flags */
1596 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
1597 goto out_drop;
1598
1599 /* obtain protocol of skb */
a12c4158 1600 protocol = vlan_get_protocol(skb);
7f12ad74
GR		 1601
1602 /* record the location of the first descriptor for this packet */
1603 first = &tx_ring->tx_bi[tx_ring->next_to_use];
1604
1605 /* setup IPv4/IPv6 offloads */
1606 if (protocol == htons(ETH_P_IP))
1607 tx_flags |= I40E_TX_FLAGS_IPV4;
1608 else if (protocol == htons(ETH_P_IPV6))
1609 tx_flags |= I40E_TX_FLAGS_IPV6;
1610
1611 tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
1612 &cd_type_cmd_tso_mss, &cd_tunneling);
1613
1614 if (tso < 0)
1615 goto out_drop;
1616 else if (tso)
1617 tx_flags |= I40E_TX_FLAGS_TSO;
1618
1619 skb_tx_timestamp(skb);
1620
1621 /* always enable CRC insertion offload */
1622 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1623
1624 /* Always offload the checksum, since it's in the data descriptor */
1625 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1626 tx_flags |= I40E_TX_FLAGS_CSUM;
1627
1628 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
1629 tx_ring, &cd_tunneling);
1630 }
1631
1632 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
1633 cd_tunneling, cd_l2tag2);
1634
1635 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
1636 td_cmd, td_offset);
1637
1638 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
1639
1640 return NETDEV_TX_OK;
1641
1642out_drop:
1643 dev_kfree_skb_any(skb);
1644 return NETDEV_TX_OK;
1645}
1646
1647/**
1648 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
1649 * @skb: send buffer
1650 * @netdev: network interface device structure
1651 *
1652 * Returns NETDEV_TX_OK if sent, else an error code
1653 **/
1654netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1655{
1656 struct i40evf_adapter *adapter = netdev_priv(netdev);
1657 struct i40e_ring *tx_ring = adapter->tx_rings[skb->queue_mapping];
1658
1659 /* hardware can't handle really short frames, hardware padding works
1660 * beyond this point
1661 */
1662 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
1663 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
1664 return NETDEV_TX_OK;
1665 skb->len = I40E_MIN_TX_LEN;
1666 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
1667 }
1668
1669 return i40e_xmit_frame_ring(skb, tx_ring);
1670}
Linux 6.x block layer and io_uring tree(s)