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7f12ad74 GR |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver | |
ecc6a239 | 4 | * Copyright(c) 2013 - 2016 Intel Corporation. |
7f12ad74 GR |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
b831607d JB |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
7f12ad74 GR |
18 | * The full GNU General Public License is included in this distribution in |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
7ed3f5f0 | 27 | #include <linux/prefetch.h> |
a132af24 | 28 | #include <net/busy_poll.h> |
7ed3f5f0 | 29 | |
7f12ad74 | 30 | #include "i40evf.h" |
206812b5 | 31 | #include "i40e_prototype.h" |
7f12ad74 GR |
32 | |
33 | static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size, | |
34 | u32 td_tag) | |
35 | { | |
36 | return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA | | |
37 | ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) | | |
38 | ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) | | |
39 | ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) | | |
40 | ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT)); | |
41 | } | |
42 | ||
43 | #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS) | |
44 | ||
45 | /** | |
46 | * i40e_unmap_and_free_tx_resource - Release a Tx buffer | |
47 | * @ring: the ring that owns the buffer | |
48 | * @tx_buffer: the buffer to free | |
49 | **/ | |
50 | static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring, | |
51 | struct i40e_tx_buffer *tx_buffer) | |
52 | { | |
53 | if (tx_buffer->skb) { | |
64bfd68e AD |
54 | if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB) |
55 | kfree(tx_buffer->raw_buf); | |
56 | else | |
57 | dev_kfree_skb_any(tx_buffer->skb); | |
7f12ad74 GR |
58 | if (dma_unmap_len(tx_buffer, len)) |
59 | dma_unmap_single(ring->dev, | |
60 | dma_unmap_addr(tx_buffer, dma), | |
61 | dma_unmap_len(tx_buffer, len), | |
62 | DMA_TO_DEVICE); | |
63 | } else if (dma_unmap_len(tx_buffer, len)) { | |
64 | dma_unmap_page(ring->dev, | |
65 | dma_unmap_addr(tx_buffer, dma), | |
66 | dma_unmap_len(tx_buffer, len), | |
67 | DMA_TO_DEVICE); | |
68 | } | |
a42e7a36 | 69 | |
7f12ad74 GR |
70 | tx_buffer->next_to_watch = NULL; |
71 | tx_buffer->skb = NULL; | |
72 | dma_unmap_len_set(tx_buffer, len, 0); | |
73 | /* tx_buffer must be completely set up in the transmit path */ | |
74 | } | |
75 | ||
76 | /** | |
77 | * i40evf_clean_tx_ring - Free any empty Tx buffers | |
78 | * @tx_ring: ring to be cleaned | |
79 | **/ | |
80 | void i40evf_clean_tx_ring(struct i40e_ring *tx_ring) | |
81 | { | |
82 | unsigned long bi_size; | |
83 | u16 i; | |
84 | ||
85 | /* ring already cleared, nothing to do */ | |
86 | if (!tx_ring->tx_bi) | |
87 | return; | |
88 | ||
89 | /* Free all the Tx ring sk_buffs */ | |
90 | for (i = 0; i < tx_ring->count; i++) | |
91 | i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]); | |
92 | ||
93 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; | |
94 | memset(tx_ring->tx_bi, 0, bi_size); | |
95 | ||
96 | /* Zero out the descriptor ring */ | |
97 | memset(tx_ring->desc, 0, tx_ring->size); | |
98 | ||
99 | tx_ring->next_to_use = 0; | |
100 | tx_ring->next_to_clean = 0; | |
101 | ||
102 | if (!tx_ring->netdev) | |
103 | return; | |
104 | ||
105 | /* cleanup Tx queue statistics */ | |
e486bdfd | 106 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
7f12ad74 GR |
107 | } |
108 | ||
109 | /** | |
110 | * i40evf_free_tx_resources - Free Tx resources per queue | |
111 | * @tx_ring: Tx descriptor ring for a specific queue | |
112 | * | |
113 | * Free all transmit software resources | |
114 | **/ | |
115 | void i40evf_free_tx_resources(struct i40e_ring *tx_ring) | |
116 | { | |
117 | i40evf_clean_tx_ring(tx_ring); | |
118 | kfree(tx_ring->tx_bi); | |
119 | tx_ring->tx_bi = NULL; | |
120 | ||
121 | if (tx_ring->desc) { | |
122 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
123 | tx_ring->desc, tx_ring->dma); | |
124 | tx_ring->desc = NULL; | |
125 | } | |
126 | } | |
127 | ||
a68de58d | 128 | /** |
9c6c1259 KP |
129 | * i40evf_get_tx_pending - how many Tx descriptors not processed |
130 | * @tx_ring: the ring of descriptors | |
dd353109 | 131 | * @in_sw: is tx_pending being checked in SW or HW |
a68de58d | 132 | * |
9c6c1259 KP |
133 | * Since there is no access to the ring head register |
134 | * in XL710, we need to use our local copies | |
a68de58d | 135 | **/ |
dd353109 | 136 | u32 i40evf_get_tx_pending(struct i40e_ring *ring, bool in_sw) |
a68de58d | 137 | { |
9c6c1259 | 138 | u32 head, tail; |
a68de58d | 139 | |
b1cb07db | 140 | head = ring->next_to_clean; |
9c6c1259 KP |
141 | tail = readl(ring->tail); |
142 | ||
143 | if (head != tail) | |
144 | return (head < tail) ? | |
145 | tail - head : (tail + ring->count - head); | |
146 | ||
147 | return 0; | |
a68de58d JB |
148 | } |
149 | ||
1dc8b538 | 150 | #define WB_STRIDE 4 |
c29af37f | 151 | |
7f12ad74 GR |
152 | /** |
153 | * i40e_clean_tx_irq - Reclaim resources after transmit completes | |
a619afe8 AD |
154 | * @vsi: the VSI we care about |
155 | * @tx_ring: Tx ring to clean | |
156 | * @napi_budget: Used to determine if we are in netpoll | |
7f12ad74 GR |
157 | * |
158 | * Returns true if there's any budget left (e.g. the clean is finished) | |
159 | **/ | |
a619afe8 AD |
160 | static bool i40e_clean_tx_irq(struct i40e_vsi *vsi, |
161 | struct i40e_ring *tx_ring, int napi_budget) | |
7f12ad74 GR |
162 | { |
163 | u16 i = tx_ring->next_to_clean; | |
164 | struct i40e_tx_buffer *tx_buf; | |
165 | struct i40e_tx_desc *tx_desc; | |
a619afe8 AD |
166 | unsigned int total_bytes = 0, total_packets = 0; |
167 | unsigned int budget = vsi->work_limit; | |
7f12ad74 GR |
168 | |
169 | tx_buf = &tx_ring->tx_bi[i]; | |
170 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
171 | i -= tx_ring->count; | |
172 | ||
173 | do { | |
174 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
175 | ||
176 | /* if next_to_watch is not set then there is no work pending */ | |
177 | if (!eop_desc) | |
178 | break; | |
179 | ||
180 | /* prevent any other reads prior to eop_desc */ | |
181 | read_barrier_depends(); | |
182 | ||
b1cb07db PB |
183 | /* if the descriptor isn't done, no work yet to do */ |
184 | if (!(eop_desc->cmd_type_offset_bsz & | |
185 | cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE))) | |
7f12ad74 GR |
186 | break; |
187 | ||
188 | /* clear next_to_watch to prevent false hangs */ | |
189 | tx_buf->next_to_watch = NULL; | |
190 | ||
191 | /* update the statistics for this packet */ | |
192 | total_bytes += tx_buf->bytecount; | |
193 | total_packets += tx_buf->gso_segs; | |
194 | ||
195 | /* free the skb */ | |
a619afe8 | 196 | napi_consume_skb(tx_buf->skb, napi_budget); |
7f12ad74 GR |
197 | |
198 | /* unmap skb header data */ | |
199 | dma_unmap_single(tx_ring->dev, | |
200 | dma_unmap_addr(tx_buf, dma), | |
201 | dma_unmap_len(tx_buf, len), | |
202 | DMA_TO_DEVICE); | |
203 | ||
204 | /* clear tx_buffer data */ | |
205 | tx_buf->skb = NULL; | |
206 | dma_unmap_len_set(tx_buf, len, 0); | |
207 | ||
208 | /* unmap remaining buffers */ | |
209 | while (tx_desc != eop_desc) { | |
210 | ||
211 | tx_buf++; | |
212 | tx_desc++; | |
213 | i++; | |
214 | if (unlikely(!i)) { | |
215 | i -= tx_ring->count; | |
216 | tx_buf = tx_ring->tx_bi; | |
217 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
218 | } | |
219 | ||
220 | /* unmap any remaining paged data */ | |
221 | if (dma_unmap_len(tx_buf, len)) { | |
222 | dma_unmap_page(tx_ring->dev, | |
223 | dma_unmap_addr(tx_buf, dma), | |
224 | dma_unmap_len(tx_buf, len), | |
225 | DMA_TO_DEVICE); | |
226 | dma_unmap_len_set(tx_buf, len, 0); | |
227 | } | |
228 | } | |
229 | ||
230 | /* move us one more past the eop_desc for start of next pkt */ | |
231 | tx_buf++; | |
232 | tx_desc++; | |
233 | i++; | |
234 | if (unlikely(!i)) { | |
235 | i -= tx_ring->count; | |
236 | tx_buf = tx_ring->tx_bi; | |
237 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
238 | } | |
239 | ||
016890b9 JB |
240 | prefetch(tx_desc); |
241 | ||
7f12ad74 GR |
242 | /* update budget accounting */ |
243 | budget--; | |
244 | } while (likely(budget)); | |
245 | ||
246 | i += tx_ring->count; | |
247 | tx_ring->next_to_clean = i; | |
248 | u64_stats_update_begin(&tx_ring->syncp); | |
249 | tx_ring->stats.bytes += total_bytes; | |
250 | tx_ring->stats.packets += total_packets; | |
251 | u64_stats_update_end(&tx_ring->syncp); | |
252 | tx_ring->q_vector->tx.total_bytes += total_bytes; | |
253 | tx_ring->q_vector->tx.total_packets += total_packets; | |
254 | ||
f6d83d13 | 255 | if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) { |
f6d83d13 ASJ |
256 | /* check to see if there are < 4 descriptors |
257 | * waiting to be written back, then kick the hardware to force | |
258 | * them to be written back in case we stay in NAPI. | |
259 | * In this mode on X722 we do not enable Interrupt. | |
260 | */ | |
88dc9e6f | 261 | unsigned int j = i40evf_get_tx_pending(tx_ring, false); |
f6d83d13 ASJ |
262 | |
263 | if (budget && | |
1dc8b538 | 264 | ((j / WB_STRIDE) == 0) && (j > 0) && |
a619afe8 | 265 | !test_bit(__I40E_DOWN, &vsi->state) && |
f6d83d13 ASJ |
266 | (I40E_DESC_UNUSED(tx_ring) != tx_ring->count)) |
267 | tx_ring->arm_wb = true; | |
268 | } | |
269 | ||
e486bdfd AD |
270 | /* notify netdev of completed buffers */ |
271 | netdev_tx_completed_queue(txring_txq(tx_ring), | |
7f12ad74 GR |
272 | total_packets, total_bytes); |
273 | ||
274 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) | |
275 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && | |
276 | (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) { | |
277 | /* Make sure that anybody stopping the queue after this | |
278 | * sees the new next_to_clean. | |
279 | */ | |
280 | smp_mb(); | |
281 | if (__netif_subqueue_stopped(tx_ring->netdev, | |
282 | tx_ring->queue_index) && | |
a619afe8 | 283 | !test_bit(__I40E_DOWN, &vsi->state)) { |
7f12ad74 GR |
284 | netif_wake_subqueue(tx_ring->netdev, |
285 | tx_ring->queue_index); | |
286 | ++tx_ring->tx_stats.restart_queue; | |
287 | } | |
288 | } | |
289 | ||
b03a8c1f | 290 | return !!budget; |
7f12ad74 GR |
291 | } |
292 | ||
c29af37f | 293 | /** |
ecc6a239 | 294 | * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled |
c29af37f | 295 | * @vsi: the VSI we care about |
ecc6a239 | 296 | * @q_vector: the vector on which to enable writeback |
c29af37f ASJ |
297 | * |
298 | **/ | |
ecc6a239 ASJ |
299 | static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi, |
300 | struct i40e_q_vector *q_vector) | |
c29af37f | 301 | { |
8e0764b4 | 302 | u16 flags = q_vector->tx.ring[0].flags; |
ecc6a239 | 303 | u32 val; |
8e0764b4 | 304 | |
ecc6a239 ASJ |
305 | if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR)) |
306 | return; | |
307 | ||
308 | if (q_vector->arm_wb_state) | |
309 | return; | |
310 | ||
311 | val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK | | |
312 | I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */ | |
313 | ||
314 | wr32(&vsi->back->hw, | |
315 | I40E_VFINT_DYN_CTLN1(q_vector->v_idx + | |
316 | vsi->base_vector - 1), val); | |
317 | q_vector->arm_wb_state = true; | |
318 | } | |
319 | ||
320 | /** | |
321 | * i40evf_force_wb - Issue SW Interrupt so HW does a wb | |
322 | * @vsi: the VSI we care about | |
323 | * @q_vector: the vector on which to force writeback | |
324 | * | |
325 | **/ | |
326 | void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector) | |
327 | { | |
328 | u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK | | |
329 | I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */ | |
330 | I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK | | |
331 | I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK | |
332 | /* allow 00 to be written to the index */; | |
333 | ||
334 | wr32(&vsi->back->hw, | |
335 | I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1), | |
336 | val); | |
c29af37f ASJ |
337 | } |
338 | ||
7f12ad74 GR |
339 | /** |
340 | * i40e_set_new_dynamic_itr - Find new ITR level | |
341 | * @rc: structure containing ring performance data | |
342 | * | |
8f5e39ce JB |
343 | * Returns true if ITR changed, false if not |
344 | * | |
7f12ad74 GR |
345 | * Stores a new ITR value based on packets and byte counts during |
346 | * the last interrupt. The advantage of per interrupt computation | |
347 | * is faster updates and more accurate ITR for the current traffic | |
348 | * pattern. Constants in this function were computed based on | |
349 | * theoretical maximum wire speed and thresholds were set based on | |
350 | * testing data as well as attempting to minimize response time | |
351 | * while increasing bulk throughput. | |
352 | **/ | |
8f5e39ce | 353 | static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc) |
7f12ad74 GR |
354 | { |
355 | enum i40e_latency_range new_latency_range = rc->latency_range; | |
c56625d5 | 356 | struct i40e_q_vector *qv = rc->ring->q_vector; |
7f12ad74 GR |
357 | u32 new_itr = rc->itr; |
358 | int bytes_per_int; | |
51cc6d9f | 359 | int usecs; |
7f12ad74 GR |
360 | |
361 | if (rc->total_packets == 0 || !rc->itr) | |
8f5e39ce | 362 | return false; |
7f12ad74 GR |
363 | |
364 | /* simple throttlerate management | |
c56625d5 | 365 | * 0-10MB/s lowest (50000 ints/s) |
7f12ad74 | 366 | * 10-20MB/s low (20000 ints/s) |
c56625d5 JB |
367 | * 20-1249MB/s bulk (18000 ints/s) |
368 | * > 40000 Rx packets per second (8000 ints/s) | |
51cc6d9f JB |
369 | * |
370 | * The math works out because the divisor is in 10^(-6) which | |
371 | * turns the bytes/us input value into MB/s values, but | |
372 | * make sure to use usecs, as the register values written | |
ee2319cf JB |
373 | * are in 2 usec increments in the ITR registers, and make sure |
374 | * to use the smoothed values that the countdown timer gives us. | |
7f12ad74 | 375 | */ |
ee2319cf | 376 | usecs = (rc->itr << 1) * ITR_COUNTDOWN_START; |
51cc6d9f | 377 | bytes_per_int = rc->total_bytes / usecs; |
ee2319cf | 378 | |
de32e3ef | 379 | switch (new_latency_range) { |
7f12ad74 GR |
380 | case I40E_LOWEST_LATENCY: |
381 | if (bytes_per_int > 10) | |
382 | new_latency_range = I40E_LOW_LATENCY; | |
383 | break; | |
384 | case I40E_LOW_LATENCY: | |
385 | if (bytes_per_int > 20) | |
386 | new_latency_range = I40E_BULK_LATENCY; | |
387 | else if (bytes_per_int <= 10) | |
388 | new_latency_range = I40E_LOWEST_LATENCY; | |
389 | break; | |
390 | case I40E_BULK_LATENCY: | |
c56625d5 | 391 | case I40E_ULTRA_LATENCY: |
de32e3ef CW |
392 | default: |
393 | if (bytes_per_int <= 20) | |
394 | new_latency_range = I40E_LOW_LATENCY; | |
7f12ad74 GR |
395 | break; |
396 | } | |
c56625d5 JB |
397 | |
398 | /* this is to adjust RX more aggressively when streaming small | |
399 | * packets. The value of 40000 was picked as it is just beyond | |
400 | * what the hardware can receive per second if in low latency | |
401 | * mode. | |
402 | */ | |
403 | #define RX_ULTRA_PACKET_RATE 40000 | |
404 | ||
405 | if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) && | |
406 | (&qv->rx == rc)) | |
407 | new_latency_range = I40E_ULTRA_LATENCY; | |
408 | ||
de32e3ef | 409 | rc->latency_range = new_latency_range; |
7f12ad74 GR |
410 | |
411 | switch (new_latency_range) { | |
412 | case I40E_LOWEST_LATENCY: | |
c56625d5 | 413 | new_itr = I40E_ITR_50K; |
7f12ad74 GR |
414 | break; |
415 | case I40E_LOW_LATENCY: | |
416 | new_itr = I40E_ITR_20K; | |
417 | break; | |
418 | case I40E_BULK_LATENCY: | |
c56625d5 JB |
419 | new_itr = I40E_ITR_18K; |
420 | break; | |
421 | case I40E_ULTRA_LATENCY: | |
7f12ad74 GR |
422 | new_itr = I40E_ITR_8K; |
423 | break; | |
424 | default: | |
425 | break; | |
426 | } | |
427 | ||
7f12ad74 GR |
428 | rc->total_bytes = 0; |
429 | rc->total_packets = 0; | |
8f5e39ce JB |
430 | |
431 | if (new_itr != rc->itr) { | |
432 | rc->itr = new_itr; | |
433 | return true; | |
434 | } | |
435 | ||
436 | return false; | |
7f12ad74 GR |
437 | } |
438 | ||
4eeb1fff | 439 | /** |
7f12ad74 GR |
440 | * i40evf_setup_tx_descriptors - Allocate the Tx descriptors |
441 | * @tx_ring: the tx ring to set up | |
442 | * | |
443 | * Return 0 on success, negative on error | |
444 | **/ | |
445 | int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring) | |
446 | { | |
447 | struct device *dev = tx_ring->dev; | |
448 | int bi_size; | |
449 | ||
450 | if (!dev) | |
451 | return -ENOMEM; | |
452 | ||
67c818a1 MW |
453 | /* warn if we are about to overwrite the pointer */ |
454 | WARN_ON(tx_ring->tx_bi); | |
7f12ad74 GR |
455 | bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count; |
456 | tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL); | |
457 | if (!tx_ring->tx_bi) | |
458 | goto err; | |
459 | ||
460 | /* round up to nearest 4K */ | |
461 | tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc); | |
462 | tx_ring->size = ALIGN(tx_ring->size, 4096); | |
463 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
464 | &tx_ring->dma, GFP_KERNEL); | |
465 | if (!tx_ring->desc) { | |
466 | dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n", | |
467 | tx_ring->size); | |
468 | goto err; | |
469 | } | |
470 | ||
471 | tx_ring->next_to_use = 0; | |
472 | tx_ring->next_to_clean = 0; | |
473 | return 0; | |
474 | ||
475 | err: | |
476 | kfree(tx_ring->tx_bi); | |
477 | tx_ring->tx_bi = NULL; | |
478 | return -ENOMEM; | |
479 | } | |
480 | ||
481 | /** | |
482 | * i40evf_clean_rx_ring - Free Rx buffers | |
483 | * @rx_ring: ring to be cleaned | |
484 | **/ | |
485 | void i40evf_clean_rx_ring(struct i40e_ring *rx_ring) | |
486 | { | |
7f12ad74 GR |
487 | unsigned long bi_size; |
488 | u16 i; | |
489 | ||
490 | /* ring already cleared, nothing to do */ | |
491 | if (!rx_ring->rx_bi) | |
492 | return; | |
493 | ||
e72e5659 SP |
494 | if (rx_ring->skb) { |
495 | dev_kfree_skb(rx_ring->skb); | |
496 | rx_ring->skb = NULL; | |
497 | } | |
498 | ||
7f12ad74 GR |
499 | /* Free all the Rx ring sk_buffs */ |
500 | for (i = 0; i < rx_ring->count; i++) { | |
ab9ad98e JB |
501 | struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i]; |
502 | ||
ab9ad98e JB |
503 | if (!rx_bi->page) |
504 | continue; | |
505 | ||
59605bc0 AD |
506 | /* Invalidate cache lines that may have been written to by |
507 | * device so that we avoid corrupting memory. | |
508 | */ | |
509 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
510 | rx_bi->dma, | |
511 | rx_bi->page_offset, | |
512 | I40E_RXBUFFER_2048, | |
513 | DMA_FROM_DEVICE); | |
514 | ||
515 | /* free resources associated with mapping */ | |
516 | dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma, | |
517 | PAGE_SIZE, | |
518 | DMA_FROM_DEVICE, | |
519 | I40E_RX_DMA_ATTR); | |
1793668c | 520 | __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias); |
ab9ad98e JB |
521 | |
522 | rx_bi->page = NULL; | |
523 | rx_bi->page_offset = 0; | |
7f12ad74 GR |
524 | } |
525 | ||
526 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; | |
527 | memset(rx_ring->rx_bi, 0, bi_size); | |
528 | ||
529 | /* Zero out the descriptor ring */ | |
530 | memset(rx_ring->desc, 0, rx_ring->size); | |
531 | ||
ab9ad98e | 532 | rx_ring->next_to_alloc = 0; |
7f12ad74 GR |
533 | rx_ring->next_to_clean = 0; |
534 | rx_ring->next_to_use = 0; | |
535 | } | |
536 | ||
537 | /** | |
538 | * i40evf_free_rx_resources - Free Rx resources | |
539 | * @rx_ring: ring to clean the resources from | |
540 | * | |
541 | * Free all receive software resources | |
542 | **/ | |
543 | void i40evf_free_rx_resources(struct i40e_ring *rx_ring) | |
544 | { | |
545 | i40evf_clean_rx_ring(rx_ring); | |
546 | kfree(rx_ring->rx_bi); | |
547 | rx_ring->rx_bi = NULL; | |
548 | ||
549 | if (rx_ring->desc) { | |
550 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
551 | rx_ring->desc, rx_ring->dma); | |
552 | rx_ring->desc = NULL; | |
553 | } | |
554 | } | |
555 | ||
556 | /** | |
557 | * i40evf_setup_rx_descriptors - Allocate Rx descriptors | |
558 | * @rx_ring: Rx descriptor ring (for a specific queue) to setup | |
559 | * | |
560 | * Returns 0 on success, negative on failure | |
561 | **/ | |
562 | int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring) | |
563 | { | |
564 | struct device *dev = rx_ring->dev; | |
565 | int bi_size; | |
566 | ||
67c818a1 MW |
567 | /* warn if we are about to overwrite the pointer */ |
568 | WARN_ON(rx_ring->rx_bi); | |
7f12ad74 GR |
569 | bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count; |
570 | rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL); | |
571 | if (!rx_ring->rx_bi) | |
572 | goto err; | |
573 | ||
f217d6ca | 574 | u64_stats_init(&rx_ring->syncp); |
638702bd | 575 | |
7f12ad74 | 576 | /* Round up to nearest 4K */ |
ab9ad98e | 577 | rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc); |
7f12ad74 GR |
578 | rx_ring->size = ALIGN(rx_ring->size, 4096); |
579 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
580 | &rx_ring->dma, GFP_KERNEL); | |
581 | ||
582 | if (!rx_ring->desc) { | |
583 | dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n", | |
584 | rx_ring->size); | |
585 | goto err; | |
586 | } | |
587 | ||
ab9ad98e | 588 | rx_ring->next_to_alloc = 0; |
7f12ad74 GR |
589 | rx_ring->next_to_clean = 0; |
590 | rx_ring->next_to_use = 0; | |
591 | ||
592 | return 0; | |
593 | err: | |
594 | kfree(rx_ring->rx_bi); | |
595 | rx_ring->rx_bi = NULL; | |
596 | return -ENOMEM; | |
597 | } | |
598 | ||
599 | /** | |
600 | * i40e_release_rx_desc - Store the new tail and head values | |
601 | * @rx_ring: ring to bump | |
602 | * @val: new head index | |
603 | **/ | |
604 | static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val) | |
605 | { | |
606 | rx_ring->next_to_use = val; | |
ab9ad98e JB |
607 | |
608 | /* update next to alloc since we have filled the ring */ | |
609 | rx_ring->next_to_alloc = val; | |
610 | ||
7f12ad74 GR |
611 | /* Force memory writes to complete before letting h/w |
612 | * know there are new descriptors to fetch. (Only | |
613 | * applicable for weak-ordered memory model archs, | |
614 | * such as IA-64). | |
615 | */ | |
616 | wmb(); | |
617 | writel(val, rx_ring->tail); | |
618 | } | |
619 | ||
620 | /** | |
ab9ad98e JB |
621 | * i40e_alloc_mapped_page - recycle or make a new page |
622 | * @rx_ring: ring to use | |
623 | * @bi: rx_buffer struct to modify | |
c2e245ab | 624 | * |
ab9ad98e JB |
625 | * Returns true if the page was successfully allocated or |
626 | * reused. | |
a132af24 | 627 | **/ |
ab9ad98e JB |
628 | static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring, |
629 | struct i40e_rx_buffer *bi) | |
a132af24 | 630 | { |
ab9ad98e JB |
631 | struct page *page = bi->page; |
632 | dma_addr_t dma; | |
a132af24 | 633 | |
ab9ad98e JB |
634 | /* since we are recycling buffers we should seldom need to alloc */ |
635 | if (likely(page)) { | |
636 | rx_ring->rx_stats.page_reuse_count++; | |
637 | return true; | |
638 | } | |
a132af24 | 639 | |
ab9ad98e JB |
640 | /* alloc new page for storage */ |
641 | page = dev_alloc_page(); | |
642 | if (unlikely(!page)) { | |
643 | rx_ring->rx_stats.alloc_page_failed++; | |
644 | return false; | |
645 | } | |
a132af24 | 646 | |
ab9ad98e | 647 | /* map page for use */ |
59605bc0 AD |
648 | dma = dma_map_page_attrs(rx_ring->dev, page, 0, |
649 | PAGE_SIZE, | |
650 | DMA_FROM_DEVICE, | |
651 | I40E_RX_DMA_ATTR); | |
f16704e5 | 652 | |
ab9ad98e JB |
653 | /* if mapping failed free memory back to system since |
654 | * there isn't much point in holding memory we can't use | |
f16704e5 | 655 | */ |
ab9ad98e JB |
656 | if (dma_mapping_error(rx_ring->dev, dma)) { |
657 | __free_pages(page, 0); | |
658 | rx_ring->rx_stats.alloc_page_failed++; | |
659 | return false; | |
a132af24 MW |
660 | } |
661 | ||
ab9ad98e JB |
662 | bi->dma = dma; |
663 | bi->page = page; | |
664 | bi->page_offset = 0; | |
a0cfc313 AD |
665 | |
666 | /* initialize pagecnt_bias to 1 representing we fully own page */ | |
1793668c | 667 | bi->pagecnt_bias = 1; |
c2e245ab | 668 | |
ab9ad98e JB |
669 | return true; |
670 | } | |
c2e245ab | 671 | |
ab9ad98e JB |
672 | /** |
673 | * i40e_receive_skb - Send a completed packet up the stack | |
674 | * @rx_ring: rx ring in play | |
675 | * @skb: packet to send up | |
676 | * @vlan_tag: vlan tag for packet | |
677 | **/ | |
678 | static void i40e_receive_skb(struct i40e_ring *rx_ring, | |
679 | struct sk_buff *skb, u16 vlan_tag) | |
680 | { | |
681 | struct i40e_q_vector *q_vector = rx_ring->q_vector; | |
c2e245ab | 682 | |
ab9ad98e JB |
683 | if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && |
684 | (vlan_tag & VLAN_VID_MASK)) | |
685 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag); | |
686 | ||
687 | napi_gro_receive(&q_vector->napi, skb); | |
a132af24 MW |
688 | } |
689 | ||
690 | /** | |
ab9ad98e | 691 | * i40evf_alloc_rx_buffers - Replace used receive buffers |
7f12ad74 GR |
692 | * @rx_ring: ring to place buffers on |
693 | * @cleaned_count: number of buffers to replace | |
c2e245ab | 694 | * |
ab9ad98e | 695 | * Returns false if all allocations were successful, true if any fail |
7f12ad74 | 696 | **/ |
ab9ad98e | 697 | bool i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count) |
7f12ad74 | 698 | { |
ab9ad98e | 699 | u16 ntu = rx_ring->next_to_use; |
7f12ad74 GR |
700 | union i40e_rx_desc *rx_desc; |
701 | struct i40e_rx_buffer *bi; | |
7f12ad74 GR |
702 | |
703 | /* do nothing if no valid netdev defined */ | |
704 | if (!rx_ring->netdev || !cleaned_count) | |
c2e245ab | 705 | return false; |
7f12ad74 | 706 | |
ab9ad98e JB |
707 | rx_desc = I40E_RX_DESC(rx_ring, ntu); |
708 | bi = &rx_ring->rx_bi[ntu]; | |
7f12ad74 | 709 | |
ab9ad98e JB |
710 | do { |
711 | if (!i40e_alloc_mapped_page(rx_ring, bi)) | |
712 | goto no_buffers; | |
7f12ad74 | 713 | |
59605bc0 AD |
714 | /* sync the buffer for use by the device */ |
715 | dma_sync_single_range_for_device(rx_ring->dev, bi->dma, | |
716 | bi->page_offset, | |
717 | I40E_RXBUFFER_2048, | |
718 | DMA_FROM_DEVICE); | |
719 | ||
ab9ad98e JB |
720 | /* Refresh the desc even if buffer_addrs didn't change |
721 | * because each write-back erases this info. | |
722 | */ | |
723 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
7f12ad74 | 724 | |
ab9ad98e JB |
725 | rx_desc++; |
726 | bi++; | |
727 | ntu++; | |
728 | if (unlikely(ntu == rx_ring->count)) { | |
729 | rx_desc = I40E_RX_DESC(rx_ring, 0); | |
730 | bi = rx_ring->rx_bi; | |
731 | ntu = 0; | |
732 | } | |
733 | ||
734 | /* clear the status bits for the next_to_use descriptor */ | |
735 | rx_desc->wb.qword1.status_error_len = 0; | |
736 | ||
737 | cleaned_count--; | |
738 | } while (cleaned_count); | |
739 | ||
740 | if (rx_ring->next_to_use != ntu) | |
741 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
742 | |
743 | return false; | |
744 | ||
7f12ad74 | 745 | no_buffers: |
ab9ad98e JB |
746 | if (rx_ring->next_to_use != ntu) |
747 | i40e_release_rx_desc(rx_ring, ntu); | |
c2e245ab JB |
748 | |
749 | /* make sure to come back via polling to try again after | |
750 | * allocation failure | |
751 | */ | |
752 | return true; | |
7f12ad74 GR |
753 | } |
754 | ||
7f12ad74 GR |
755 | /** |
756 | * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum | |
757 | * @vsi: the VSI we care about | |
758 | * @skb: skb currently being received and modified | |
ab9ad98e | 759 | * @rx_desc: the receive descriptor |
7f12ad74 GR |
760 | **/ |
761 | static inline void i40e_rx_checksum(struct i40e_vsi *vsi, | |
762 | struct sk_buff *skb, | |
ab9ad98e | 763 | union i40e_rx_desc *rx_desc) |
7f12ad74 | 764 | { |
ab9ad98e | 765 | struct i40e_rx_ptype_decoded decoded; |
ab9ad98e | 766 | u32 rx_error, rx_status; |
858296c8 | 767 | bool ipv4, ipv6; |
ab9ad98e JB |
768 | u8 ptype; |
769 | u64 qword; | |
770 | ||
771 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); | |
772 | ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT; | |
773 | rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >> | |
774 | I40E_RXD_QW1_ERROR_SHIFT; | |
775 | rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >> | |
776 | I40E_RXD_QW1_STATUS_SHIFT; | |
777 | decoded = decode_rx_desc_ptype(ptype); | |
7f12ad74 | 778 | |
7f12ad74 GR |
779 | skb->ip_summed = CHECKSUM_NONE; |
780 | ||
ab9ad98e JB |
781 | skb_checksum_none_assert(skb); |
782 | ||
7f12ad74 | 783 | /* Rx csum enabled and ip headers found? */ |
8a3c91cc JB |
784 | if (!(vsi->netdev->features & NETIF_F_RXCSUM)) |
785 | return; | |
786 | ||
787 | /* did the hardware decode the packet and checksum? */ | |
41a1d04b | 788 | if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT))) |
8a3c91cc JB |
789 | return; |
790 | ||
791 | /* both known and outer_ip must be set for the below code to work */ | |
792 | if (!(decoded.known && decoded.outer_ip)) | |
7f12ad74 GR |
793 | return; |
794 | ||
fad57330 AD |
795 | ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && |
796 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4); | |
797 | ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) && | |
798 | (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6); | |
8a3c91cc JB |
799 | |
800 | if (ipv4 && | |
41a1d04b JB |
801 | (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) | |
802 | BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT)))) | |
8a3c91cc JB |
803 | goto checksum_fail; |
804 | ||
ddf1d0d7 | 805 | /* likely incorrect csum if alternate IP extension headers found */ |
8a3c91cc | 806 | if (ipv6 && |
41a1d04b | 807 | rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) |
8a3c91cc | 808 | /* don't increment checksum err here, non-fatal err */ |
7f12ad74 GR |
809 | return; |
810 | ||
8a3c91cc | 811 | /* there was some L4 error, count error and punt packet to the stack */ |
41a1d04b | 812 | if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT)) |
8a3c91cc JB |
813 | goto checksum_fail; |
814 | ||
815 | /* handle packets that were not able to be checksummed due | |
816 | * to arrival speed, in this case the stack can compute | |
817 | * the csum. | |
818 | */ | |
41a1d04b | 819 | if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT)) |
7f12ad74 | 820 | return; |
7f12ad74 | 821 | |
858296c8 AD |
822 | /* If there is an outer header present that might contain a checksum |
823 | * we need to bump the checksum level by 1 to reflect the fact that | |
824 | * we are indicating we validated the inner checksum. | |
8a3c91cc | 825 | */ |
858296c8 AD |
826 | if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT) |
827 | skb->csum_level = 1; | |
828 | ||
829 | /* Only report checksum unnecessary for TCP, UDP, or SCTP */ | |
830 | switch (decoded.inner_prot) { | |
831 | case I40E_RX_PTYPE_INNER_PROT_TCP: | |
832 | case I40E_RX_PTYPE_INNER_PROT_UDP: | |
833 | case I40E_RX_PTYPE_INNER_PROT_SCTP: | |
834 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
835 | /* fall though */ | |
836 | default: | |
837 | break; | |
838 | } | |
8a3c91cc JB |
839 | |
840 | return; | |
841 | ||
842 | checksum_fail: | |
843 | vsi->back->hw_csum_rx_error++; | |
7f12ad74 GR |
844 | } |
845 | ||
846 | /** | |
857942fd | 847 | * i40e_ptype_to_htype - get a hash type |
206812b5 JB |
848 | * @ptype: the ptype value from the descriptor |
849 | * | |
850 | * Returns a hash type to be used by skb_set_hash | |
851 | **/ | |
ab9ad98e | 852 | static inline int i40e_ptype_to_htype(u8 ptype) |
206812b5 JB |
853 | { |
854 | struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype); | |
855 | ||
856 | if (!decoded.known) | |
857 | return PKT_HASH_TYPE_NONE; | |
858 | ||
859 | if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
860 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4) | |
861 | return PKT_HASH_TYPE_L4; | |
862 | else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP && | |
863 | decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3) | |
864 | return PKT_HASH_TYPE_L3; | |
865 | else | |
866 | return PKT_HASH_TYPE_L2; | |
867 | } | |
868 | ||
857942fd ASJ |
869 | /** |
870 | * i40e_rx_hash - set the hash value in the skb | |
871 | * @ring: descriptor ring | |
872 | * @rx_desc: specific descriptor | |
873 | **/ | |
874 | static inline void i40e_rx_hash(struct i40e_ring *ring, | |
875 | union i40e_rx_desc *rx_desc, | |
876 | struct sk_buff *skb, | |
877 | u8 rx_ptype) | |
878 | { | |
879 | u32 hash; | |
ab9ad98e | 880 | const __le64 rss_mask = |
857942fd ASJ |
881 | cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH << |
882 | I40E_RX_DESC_STATUS_FLTSTAT_SHIFT); | |
883 | ||
884 | if (ring->netdev->features & NETIF_F_RXHASH) | |
885 | return; | |
886 | ||
887 | if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) { | |
888 | hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss); | |
889 | skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype)); | |
890 | } | |
891 | } | |
892 | ||
7f12ad74 | 893 | /** |
ab9ad98e JB |
894 | * i40evf_process_skb_fields - Populate skb header fields from Rx descriptor |
895 | * @rx_ring: rx descriptor ring packet is being transacted on | |
896 | * @rx_desc: pointer to the EOP Rx descriptor | |
897 | * @skb: pointer to current skb being populated | |
898 | * @rx_ptype: the packet type decoded by hardware | |
7f12ad74 | 899 | * |
ab9ad98e JB |
900 | * This function checks the ring, descriptor, and packet information in |
901 | * order to populate the hash, checksum, VLAN, protocol, and | |
902 | * other fields within the skb. | |
7f12ad74 | 903 | **/ |
ab9ad98e JB |
904 | static inline |
905 | void i40evf_process_skb_fields(struct i40e_ring *rx_ring, | |
906 | union i40e_rx_desc *rx_desc, struct sk_buff *skb, | |
907 | u8 rx_ptype) | |
7f12ad74 | 908 | { |
ab9ad98e | 909 | i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype); |
7f12ad74 | 910 | |
ab9ad98e | 911 | i40e_rx_checksum(rx_ring->vsi, skb, rx_desc); |
a132af24 | 912 | |
ab9ad98e | 913 | skb_record_rx_queue(skb, rx_ring->queue_index); |
a5b268e4 AD |
914 | |
915 | /* modifies the skb - consumes the enet header */ | |
916 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); | |
ab9ad98e | 917 | } |
a132af24 | 918 | |
ab9ad98e JB |
919 | /** |
920 | * i40e_cleanup_headers - Correct empty headers | |
921 | * @rx_ring: rx descriptor ring packet is being transacted on | |
922 | * @skb: pointer to current skb being fixed | |
923 | * | |
924 | * Also address the case where we are pulling data in on pages only | |
925 | * and as such no data is present in the skb header. | |
926 | * | |
927 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
928 | * it is large enough to qualify as a valid Ethernet frame. | |
929 | * | |
930 | * Returns true if an error was encountered and skb was freed. | |
931 | **/ | |
932 | static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb) | |
933 | { | |
ab9ad98e JB |
934 | /* if eth_skb_pad returns an error the skb was freed */ |
935 | if (eth_skb_pad(skb)) | |
936 | return true; | |
7f12ad74 | 937 | |
ab9ad98e JB |
938 | return false; |
939 | } | |
857942fd | 940 | |
ab9ad98e JB |
941 | /** |
942 | * i40e_reuse_rx_page - page flip buffer and store it back on the ring | |
943 | * @rx_ring: rx descriptor ring to store buffers on | |
944 | * @old_buff: donor buffer to have page reused | |
945 | * | |
946 | * Synchronizes page for reuse by the adapter | |
947 | **/ | |
948 | static void i40e_reuse_rx_page(struct i40e_ring *rx_ring, | |
949 | struct i40e_rx_buffer *old_buff) | |
950 | { | |
951 | struct i40e_rx_buffer *new_buff; | |
952 | u16 nta = rx_ring->next_to_alloc; | |
7f12ad74 | 953 | |
ab9ad98e | 954 | new_buff = &rx_ring->rx_bi[nta]; |
7f12ad74 | 955 | |
ab9ad98e JB |
956 | /* update, and store next to alloc */ |
957 | nta++; | |
958 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
7f12ad74 | 959 | |
ab9ad98e | 960 | /* transfer page from old buffer to new buffer */ |
1793668c AD |
961 | new_buff->dma = old_buff->dma; |
962 | new_buff->page = old_buff->page; | |
963 | new_buff->page_offset = old_buff->page_offset; | |
964 | new_buff->pagecnt_bias = old_buff->pagecnt_bias; | |
ab9ad98e JB |
965 | } |
966 | ||
967 | /** | |
9b37c937 | 968 | * i40e_page_is_reusable - check if any reuse is possible |
ab9ad98e | 969 | * @page: page struct to check |
9b37c937 SP |
970 | * |
971 | * A page is not reusable if it was allocated under low memory | |
972 | * conditions, or it's not in the same NUMA node as this CPU. | |
ab9ad98e | 973 | */ |
9b37c937 | 974 | static inline bool i40e_page_is_reusable(struct page *page) |
ab9ad98e | 975 | { |
9b37c937 SP |
976 | return (page_to_nid(page) == numa_mem_id()) && |
977 | !page_is_pfmemalloc(page); | |
978 | } | |
979 | ||
980 | /** | |
981 | * i40e_can_reuse_rx_page - Determine if this page can be reused by | |
982 | * the adapter for another receive | |
983 | * | |
984 | * @rx_buffer: buffer containing the page | |
9b37c937 SP |
985 | * |
986 | * If page is reusable, rx_buffer->page_offset is adjusted to point to | |
987 | * an unused region in the page. | |
988 | * | |
989 | * For small pages, @truesize will be a constant value, half the size | |
990 | * of the memory at page. We'll attempt to alternate between high and | |
991 | * low halves of the page, with one half ready for use by the hardware | |
992 | * and the other half being consumed by the stack. We use the page | |
993 | * ref count to determine whether the stack has finished consuming the | |
994 | * portion of this page that was passed up with a previous packet. If | |
995 | * the page ref count is >1, we'll assume the "other" half page is | |
996 | * still busy, and this page cannot be reused. | |
997 | * | |
998 | * For larger pages, @truesize will be the actual space used by the | |
999 | * received packet (adjusted upward to an even multiple of the cache | |
1000 | * line size). This will advance through the page by the amount | |
1001 | * actually consumed by the received packets while there is still | |
1002 | * space for a buffer. Each region of larger pages will be used at | |
1003 | * most once, after which the page will not be reused. | |
1004 | * | |
1005 | * In either case, if the page is reusable its refcount is increased. | |
1006 | **/ | |
a0cfc313 | 1007 | static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer) |
9b37c937 SP |
1008 | { |
1009 | #if (PAGE_SIZE >= 8192) | |
1010 | unsigned int last_offset = PAGE_SIZE - I40E_RXBUFFER_2048; | |
1011 | #endif | |
a0cfc313 AD |
1012 | unsigned int pagecnt_bias = rx_buffer->pagecnt_bias; |
1013 | struct page *page = rx_buffer->page; | |
9b37c937 SP |
1014 | |
1015 | /* Is any reuse possible? */ | |
1016 | if (unlikely(!i40e_page_is_reusable(page))) | |
1017 | return false; | |
1018 | ||
1019 | #if (PAGE_SIZE < 8192) | |
1020 | /* if we are only owner of page we can reuse it */ | |
a0cfc313 | 1021 | if (unlikely((page_count(page) - pagecnt_bias) > 1)) |
9b37c937 | 1022 | return false; |
9b37c937 | 1023 | #else |
9b37c937 SP |
1024 | if (rx_buffer->page_offset > last_offset) |
1025 | return false; | |
1026 | #endif | |
1027 | ||
1793668c AD |
1028 | /* If we have drained the page fragment pool we need to update |
1029 | * the pagecnt_bias and page count so that we fully restock the | |
1030 | * number of references the driver holds. | |
1031 | */ | |
a0cfc313 | 1032 | if (unlikely(!pagecnt_bias)) { |
1793668c AD |
1033 | page_ref_add(page, USHRT_MAX); |
1034 | rx_buffer->pagecnt_bias = USHRT_MAX; | |
1035 | } | |
9b37c937 SP |
1036 | |
1037 | return true; | |
ab9ad98e JB |
1038 | } |
1039 | ||
1040 | /** | |
1041 | * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1042 | * @rx_ring: rx descriptor ring to transact packets on | |
1043 | * @rx_buffer: buffer containing page to add | |
ab9ad98e | 1044 | * @skb: sk_buff to place the data into |
a0cfc313 | 1045 | * @size: packet length from rx_desc |
ab9ad98e JB |
1046 | * |
1047 | * This function will add the data contained in rx_buffer->page to the skb. | |
fa2343e9 | 1048 | * It will just attach the page as a frag to the skb. |
ab9ad98e | 1049 | * |
fa2343e9 | 1050 | * The function will then update the page offset. |
ab9ad98e | 1051 | **/ |
a0cfc313 | 1052 | static void i40e_add_rx_frag(struct i40e_ring *rx_ring, |
ab9ad98e | 1053 | struct i40e_rx_buffer *rx_buffer, |
a0cfc313 AD |
1054 | struct sk_buff *skb, |
1055 | unsigned int size) | |
ab9ad98e | 1056 | { |
ab9ad98e JB |
1057 | #if (PAGE_SIZE < 8192) |
1058 | unsigned int truesize = I40E_RXBUFFER_2048; | |
1059 | #else | |
fa2343e9 | 1060 | unsigned int truesize = SKB_DATA_ALIGN(size); |
a132af24 | 1061 | #endif |
ab9ad98e | 1062 | |
fa2343e9 AD |
1063 | skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page, |
1064 | rx_buffer->page_offset, size, truesize); | |
ab9ad98e | 1065 | |
a0cfc313 AD |
1066 | /* page is being used so we must update the page offset */ |
1067 | #if (PAGE_SIZE < 8192) | |
1068 | rx_buffer->page_offset ^= truesize; | |
1069 | #else | |
1070 | rx_buffer->page_offset += truesize; | |
1071 | #endif | |
ab9ad98e JB |
1072 | } |
1073 | ||
9a064128 AD |
1074 | /** |
1075 | * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use | |
1076 | * @rx_ring: rx descriptor ring to transact packets on | |
1077 | * @size: size of buffer to add to skb | |
1078 | * | |
1079 | * This function will pull an Rx buffer from the ring and synchronize it | |
1080 | * for use by the CPU. | |
1081 | */ | |
1082 | static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring, | |
1083 | const unsigned int size) | |
1084 | { | |
1085 | struct i40e_rx_buffer *rx_buffer; | |
1086 | ||
1087 | rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean]; | |
1088 | prefetchw(rx_buffer->page); | |
1089 | ||
1090 | /* we are reusing so sync this buffer for CPU use */ | |
1091 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1092 | rx_buffer->dma, | |
1093 | rx_buffer->page_offset, | |
1094 | size, | |
1095 | DMA_FROM_DEVICE); | |
1096 | ||
a0cfc313 AD |
1097 | /* We have pulled a buffer for use, so decrement pagecnt_bias */ |
1098 | rx_buffer->pagecnt_bias--; | |
1099 | ||
9a064128 AD |
1100 | return rx_buffer; |
1101 | } | |
1102 | ||
ab9ad98e | 1103 | /** |
fa2343e9 | 1104 | * i40e_construct_skb - Allocate skb and populate it |
ab9ad98e | 1105 | * @rx_ring: rx descriptor ring to transact packets on |
9a064128 | 1106 | * @rx_buffer: rx buffer to pull data from |
d57c0e08 | 1107 | * @size: size of buffer to add to skb |
ab9ad98e | 1108 | * |
fa2343e9 AD |
1109 | * This function allocates an skb. It then populates it with the page |
1110 | * data from the current receive descriptor, taking care to set up the | |
1111 | * skb correctly. | |
ab9ad98e | 1112 | */ |
fa2343e9 AD |
1113 | static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring, |
1114 | struct i40e_rx_buffer *rx_buffer, | |
1115 | unsigned int size) | |
ab9ad98e | 1116 | { |
fa2343e9 AD |
1117 | void *va = page_address(rx_buffer->page) + rx_buffer->page_offset; |
1118 | #if (PAGE_SIZE < 8192) | |
1119 | unsigned int truesize = I40E_RXBUFFER_2048; | |
1120 | #else | |
1121 | unsigned int truesize = SKB_DATA_ALIGN(size); | |
1122 | #endif | |
1123 | unsigned int headlen; | |
1124 | struct sk_buff *skb; | |
ab9ad98e | 1125 | |
fa2343e9 AD |
1126 | /* prefetch first cache line of first page */ |
1127 | prefetch(va); | |
ab9ad98e | 1128 | #if L1_CACHE_BYTES < 128 |
fa2343e9 | 1129 | prefetch(va + L1_CACHE_BYTES); |
ab9ad98e JB |
1130 | #endif |
1131 | ||
fa2343e9 AD |
1132 | /* allocate a skb to store the frags */ |
1133 | skb = __napi_alloc_skb(&rx_ring->q_vector->napi, | |
1134 | I40E_RX_HDR_SIZE, | |
1135 | GFP_ATOMIC | __GFP_NOWARN); | |
1136 | if (unlikely(!skb)) | |
1137 | return NULL; | |
1138 | ||
1139 | /* Determine available headroom for copy */ | |
1140 | headlen = size; | |
1141 | if (headlen > I40E_RX_HDR_SIZE) | |
1142 | headlen = eth_get_headlen(va, I40E_RX_HDR_SIZE); | |
ab9ad98e | 1143 | |
fa2343e9 AD |
1144 | /* align pull length to size of long to optimize memcpy performance */ |
1145 | memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long))); | |
1146 | ||
1147 | /* update all of the pointers */ | |
1148 | size -= headlen; | |
1149 | if (size) { | |
1150 | skb_add_rx_frag(skb, 0, rx_buffer->page, | |
1151 | rx_buffer->page_offset + headlen, | |
1152 | size, truesize); | |
1153 | ||
1154 | /* buffer is used by skb, update page_offset */ | |
1155 | #if (PAGE_SIZE < 8192) | |
1156 | rx_buffer->page_offset ^= truesize; | |
1157 | #else | |
1158 | rx_buffer->page_offset += truesize; | |
1159 | #endif | |
1160 | } else { | |
1161 | /* buffer is unused, reset bias back to rx_buffer */ | |
1162 | rx_buffer->pagecnt_bias++; | |
1163 | } | |
a0cfc313 AD |
1164 | |
1165 | return skb; | |
1166 | } | |
1167 | ||
1168 | /** | |
1169 | * i40e_put_rx_buffer - Clean up used buffer and either recycle or free | |
1170 | * @rx_ring: rx descriptor ring to transact packets on | |
1171 | * @rx_buffer: rx buffer to pull data from | |
1172 | * | |
1173 | * This function will clean up the contents of the rx_buffer. It will | |
1174 | * either recycle the bufer or unmap it and free the associated resources. | |
1175 | */ | |
1176 | static void i40e_put_rx_buffer(struct i40e_ring *rx_ring, | |
1177 | struct i40e_rx_buffer *rx_buffer) | |
1178 | { | |
1179 | if (i40e_can_reuse_rx_page(rx_buffer)) { | |
ab9ad98e JB |
1180 | /* hand second half of page back to the ring */ |
1181 | i40e_reuse_rx_page(rx_ring, rx_buffer); | |
1182 | rx_ring->rx_stats.page_reuse_count++; | |
1183 | } else { | |
1184 | /* we are not reusing the buffer so unmap it */ | |
59605bc0 AD |
1185 | dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma, PAGE_SIZE, |
1186 | DMA_FROM_DEVICE, I40E_RX_DMA_ATTR); | |
1793668c AD |
1187 | __page_frag_cache_drain(rx_buffer->page, |
1188 | rx_buffer->pagecnt_bias); | |
ab9ad98e JB |
1189 | } |
1190 | ||
1191 | /* clear contents of buffer_info */ | |
1192 | rx_buffer->page = NULL; | |
ab9ad98e JB |
1193 | } |
1194 | ||
1195 | /** | |
1196 | * i40e_is_non_eop - process handling of non-EOP buffers | |
1197 | * @rx_ring: Rx ring being processed | |
1198 | * @rx_desc: Rx descriptor for current buffer | |
1199 | * @skb: Current socket buffer containing buffer in progress | |
1200 | * | |
1201 | * This function updates next to clean. If the buffer is an EOP buffer | |
1202 | * this function exits returning false, otherwise it will place the | |
1203 | * sk_buff in the next buffer to be chained and return true indicating | |
1204 | * that this is in fact a non-EOP buffer. | |
1205 | **/ | |
1206 | static bool i40e_is_non_eop(struct i40e_ring *rx_ring, | |
1207 | union i40e_rx_desc *rx_desc, | |
1208 | struct sk_buff *skb) | |
1209 | { | |
1210 | u32 ntc = rx_ring->next_to_clean + 1; | |
1211 | ||
1212 | /* fetch, update, and store next to clean */ | |
1213 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1214 | rx_ring->next_to_clean = ntc; | |
1215 | ||
1216 | prefetch(I40E_RX_DESC(rx_ring, ntc)); | |
1217 | ||
1218 | /* if we are the last buffer then there is nothing else to do */ | |
1219 | #define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT) | |
1220 | if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF))) | |
1221 | return false; | |
1222 | ||
ab9ad98e JB |
1223 | rx_ring->rx_stats.non_eop_descs++; |
1224 | ||
1225 | return true; | |
a132af24 MW |
1226 | } |
1227 | ||
1228 | /** | |
ab9ad98e JB |
1229 | * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf |
1230 | * @rx_ring: rx descriptor ring to transact packets on | |
1231 | * @budget: Total limit on number of packets to process | |
1232 | * | |
1233 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1234 | * processing. The advantage to this is that on systems that have | |
1235 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1236 | * it by maintaining the mapping of the page to the system. | |
a132af24 | 1237 | * |
ab9ad98e | 1238 | * Returns amount of work completed |
a132af24 | 1239 | **/ |
ab9ad98e | 1240 | static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget) |
a132af24 MW |
1241 | { |
1242 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; | |
e72e5659 | 1243 | struct sk_buff *skb = rx_ring->skb; |
a132af24 | 1244 | u16 cleaned_count = I40E_DESC_UNUSED(rx_ring); |
c2e245ab | 1245 | bool failure = false; |
a132af24 | 1246 | |
ab9ad98e | 1247 | while (likely(total_rx_packets < budget)) { |
9a064128 | 1248 | struct i40e_rx_buffer *rx_buffer; |
ab9ad98e | 1249 | union i40e_rx_desc *rx_desc; |
d57c0e08 | 1250 | unsigned int size; |
a132af24 | 1251 | u16 vlan_tag; |
ab9ad98e JB |
1252 | u8 rx_ptype; |
1253 | u64 qword; | |
1254 | ||
7f12ad74 GR |
1255 | /* return some buffers to hardware, one at a time is too slow */ |
1256 | if (cleaned_count >= I40E_RX_BUFFER_WRITE) { | |
c2e245ab | 1257 | failure = failure || |
ab9ad98e | 1258 | i40evf_alloc_rx_buffers(rx_ring, cleaned_count); |
7f12ad74 GR |
1259 | cleaned_count = 0; |
1260 | } | |
1261 | ||
ab9ad98e JB |
1262 | rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean); |
1263 | ||
ab9ad98e JB |
1264 | /* status_error_len will always be zero for unused descriptors |
1265 | * because it's cleared in cleanup, and overlaps with hdr_addr | |
1266 | * which is always zero because packet split isn't used, if the | |
d57c0e08 | 1267 | * hardware wrote DD then the length will be non-zero |
ab9ad98e | 1268 | */ |
d57c0e08 AD |
1269 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
1270 | size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >> | |
1271 | I40E_RXD_QW1_LENGTH_PBUF_SHIFT; | |
1272 | if (!size) | |
ab9ad98e JB |
1273 | break; |
1274 | ||
a132af24 | 1275 | /* This memory barrier is needed to keep us from reading |
d57c0e08 AD |
1276 | * any other fields out of the rx_desc until we have |
1277 | * verified the descriptor has been written back. | |
a132af24 | 1278 | */ |
67317166 | 1279 | dma_rmb(); |
a132af24 | 1280 | |
9a064128 AD |
1281 | rx_buffer = i40e_get_rx_buffer(rx_ring, size); |
1282 | ||
fa2343e9 AD |
1283 | /* retrieve a buffer from the ring */ |
1284 | if (skb) | |
1285 | i40e_add_rx_frag(rx_ring, rx_buffer, skb, size); | |
1286 | else | |
1287 | skb = i40e_construct_skb(rx_ring, rx_buffer, size); | |
1288 | ||
1289 | /* exit if we failed to retrieve a buffer */ | |
1290 | if (!skb) { | |
1291 | rx_ring->rx_stats.alloc_buff_failed++; | |
1292 | rx_buffer->pagecnt_bias++; | |
ab9ad98e | 1293 | break; |
fa2343e9 | 1294 | } |
a132af24 | 1295 | |
a0cfc313 | 1296 | i40e_put_rx_buffer(rx_ring, rx_buffer); |
a132af24 MW |
1297 | cleaned_count++; |
1298 | ||
ab9ad98e | 1299 | if (i40e_is_non_eop(rx_ring, rx_desc, skb)) |
a132af24 | 1300 | continue; |
a132af24 | 1301 | |
ab9ad98e JB |
1302 | /* ERR_MASK will only have valid bits if EOP set, and |
1303 | * what we are doing here is actually checking | |
1304 | * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in | |
1305 | * the error field | |
1306 | */ | |
1307 | if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) { | |
a132af24 | 1308 | dev_kfree_skb_any(skb); |
741b8b83 | 1309 | skb = NULL; |
a132af24 MW |
1310 | continue; |
1311 | } | |
1312 | ||
e72e5659 SP |
1313 | if (i40e_cleanup_headers(rx_ring, skb)) { |
1314 | skb = NULL; | |
ab9ad98e | 1315 | continue; |
e72e5659 | 1316 | } |
ab9ad98e | 1317 | |
a132af24 MW |
1318 | /* probably a little skewed due to removing CRC */ |
1319 | total_rx_bytes += skb->len; | |
a132af24 | 1320 | |
99dad8b3 AD |
1321 | qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len); |
1322 | rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> | |
1323 | I40E_RXD_QW1_PTYPE_SHIFT; | |
1324 | ||
ab9ad98e JB |
1325 | /* populate checksum, VLAN, and protocol */ |
1326 | i40evf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype); | |
a132af24 | 1327 | |
a132af24 | 1328 | |
ab9ad98e JB |
1329 | vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ? |
1330 | le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0; | |
1331 | ||
a132af24 | 1332 | i40e_receive_skb(rx_ring, skb, vlan_tag); |
e72e5659 | 1333 | skb = NULL; |
a132af24 | 1334 | |
ab9ad98e JB |
1335 | /* update budget accounting */ |
1336 | total_rx_packets++; | |
1337 | } | |
7f12ad74 | 1338 | |
e72e5659 SP |
1339 | rx_ring->skb = skb; |
1340 | ||
7f12ad74 GR |
1341 | u64_stats_update_begin(&rx_ring->syncp); |
1342 | rx_ring->stats.packets += total_rx_packets; | |
1343 | rx_ring->stats.bytes += total_rx_bytes; | |
1344 | u64_stats_update_end(&rx_ring->syncp); | |
1345 | rx_ring->q_vector->rx.total_packets += total_rx_packets; | |
1346 | rx_ring->q_vector->rx.total_bytes += total_rx_bytes; | |
1347 | ||
ab9ad98e | 1348 | /* guarantee a trip back through this routine if there was a failure */ |
c2e245ab | 1349 | return failure ? budget : total_rx_packets; |
7f12ad74 GR |
1350 | } |
1351 | ||
8f5e39ce JB |
1352 | static u32 i40e_buildreg_itr(const int type, const u16 itr) |
1353 | { | |
1354 | u32 val; | |
1355 | ||
1356 | val = I40E_VFINT_DYN_CTLN1_INTENA_MASK | | |
40d72a50 JB |
1357 | /* Don't clear PBA because that can cause lost interrupts that |
1358 | * came in while we were cleaning/polling | |
1359 | */ | |
8f5e39ce JB |
1360 | (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) | |
1361 | (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT); | |
1362 | ||
1363 | return val; | |
1364 | } | |
1365 | ||
1366 | /* a small macro to shorten up some long lines */ | |
1367 | #define INTREG I40E_VFINT_DYN_CTLN1 | |
3c234c47 | 1368 | static inline int get_rx_itr(struct i40e_vsi *vsi, int idx) |
65e87c03 JK |
1369 | { |
1370 | struct i40evf_adapter *adapter = vsi->back; | |
1371 | ||
3c234c47 | 1372 | return adapter->rx_rings[idx].rx_itr_setting; |
65e87c03 JK |
1373 | } |
1374 | ||
3c234c47 | 1375 | static inline int get_tx_itr(struct i40e_vsi *vsi, int idx) |
65e87c03 JK |
1376 | { |
1377 | struct i40evf_adapter *adapter = vsi->back; | |
1378 | ||
3c234c47 | 1379 | return adapter->tx_rings[idx].tx_itr_setting; |
65e87c03 | 1380 | } |
8f5e39ce | 1381 | |
de32e3ef CW |
1382 | /** |
1383 | * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt | |
1384 | * @vsi: the VSI we care about | |
1385 | * @q_vector: q_vector for which itr is being updated and interrupt enabled | |
1386 | * | |
1387 | **/ | |
1388 | static inline void i40e_update_enable_itr(struct i40e_vsi *vsi, | |
1389 | struct i40e_q_vector *q_vector) | |
1390 | { | |
1391 | struct i40e_hw *hw = &vsi->back->hw; | |
8f5e39ce JB |
1392 | bool rx = false, tx = false; |
1393 | u32 rxval, txval; | |
de32e3ef | 1394 | int vector; |
65e87c03 JK |
1395 | int idx = q_vector->v_idx; |
1396 | int rx_itr_setting, tx_itr_setting; | |
de32e3ef CW |
1397 | |
1398 | vector = (q_vector->v_idx + vsi->base_vector); | |
ee2319cf JB |
1399 | |
1400 | /* avoid dynamic calculation if in countdown mode OR if | |
1401 | * all dynamic is disabled | |
1402 | */ | |
8f5e39ce JB |
1403 | rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0); |
1404 | ||
3c234c47 CW |
1405 | rx_itr_setting = get_rx_itr(vsi, idx); |
1406 | tx_itr_setting = get_tx_itr(vsi, idx); | |
65e87c03 | 1407 | |
ee2319cf | 1408 | if (q_vector->itr_countdown > 0 || |
65e87c03 JK |
1409 | (!ITR_IS_DYNAMIC(rx_itr_setting) && |
1410 | !ITR_IS_DYNAMIC(tx_itr_setting))) { | |
ee2319cf JB |
1411 | goto enable_int; |
1412 | } | |
1413 | ||
65e87c03 | 1414 | if (ITR_IS_DYNAMIC(rx_itr_setting)) { |
8f5e39ce JB |
1415 | rx = i40e_set_new_dynamic_itr(&q_vector->rx); |
1416 | rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr); | |
de32e3ef | 1417 | } |
4eeb1fff | 1418 | |
65e87c03 | 1419 | if (ITR_IS_DYNAMIC(tx_itr_setting)) { |
8f5e39ce JB |
1420 | tx = i40e_set_new_dynamic_itr(&q_vector->tx); |
1421 | txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr); | |
1422 | } | |
4eeb1fff | 1423 | |
8f5e39ce JB |
1424 | if (rx || tx) { |
1425 | /* get the higher of the two ITR adjustments and | |
1426 | * use the same value for both ITR registers | |
1427 | * when in adaptive mode (Rx and/or Tx) | |
1428 | */ | |
1429 | u16 itr = max(q_vector->tx.itr, q_vector->rx.itr); | |
1430 | ||
1431 | q_vector->tx.itr = q_vector->rx.itr = itr; | |
1432 | txval = i40e_buildreg_itr(I40E_TX_ITR, itr); | |
1433 | tx = true; | |
1434 | rxval = i40e_buildreg_itr(I40E_RX_ITR, itr); | |
1435 | rx = true; | |
de32e3ef | 1436 | } |
8f5e39ce JB |
1437 | |
1438 | /* only need to enable the interrupt once, but need | |
1439 | * to possibly update both ITR values | |
1440 | */ | |
1441 | if (rx) { | |
1442 | /* set the INTENA_MSK_MASK so that this first write | |
1443 | * won't actually enable the interrupt, instead just | |
1444 | * updating the ITR (it's bit 31 PF and VF) | |
1445 | */ | |
1446 | rxval |= BIT(31); | |
1447 | /* don't check _DOWN because interrupt isn't being enabled */ | |
1448 | wr32(hw, INTREG(vector - 1), rxval); | |
1449 | } | |
1450 | ||
ee2319cf | 1451 | enable_int: |
8f5e39ce JB |
1452 | if (!test_bit(__I40E_DOWN, &vsi->state)) |
1453 | wr32(hw, INTREG(vector - 1), txval); | |
ee2319cf JB |
1454 | |
1455 | if (q_vector->itr_countdown) | |
1456 | q_vector->itr_countdown--; | |
1457 | else | |
1458 | q_vector->itr_countdown = ITR_COUNTDOWN_START; | |
de32e3ef CW |
1459 | } |
1460 | ||
7f12ad74 GR |
1461 | /** |
1462 | * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine | |
1463 | * @napi: napi struct with our devices info in it | |
1464 | * @budget: amount of work driver is allowed to do this pass, in packets | |
1465 | * | |
1466 | * This function will clean all queues associated with a q_vector. | |
1467 | * | |
1468 | * Returns the amount of work done | |
1469 | **/ | |
1470 | int i40evf_napi_poll(struct napi_struct *napi, int budget) | |
1471 | { | |
1472 | struct i40e_q_vector *q_vector = | |
1473 | container_of(napi, struct i40e_q_vector, napi); | |
1474 | struct i40e_vsi *vsi = q_vector->vsi; | |
1475 | struct i40e_ring *ring; | |
1476 | bool clean_complete = true; | |
c29af37f | 1477 | bool arm_wb = false; |
7f12ad74 | 1478 | int budget_per_ring; |
32b3e08f | 1479 | int work_done = 0; |
7f12ad74 GR |
1480 | |
1481 | if (test_bit(__I40E_DOWN, &vsi->state)) { | |
1482 | napi_complete(napi); | |
1483 | return 0; | |
1484 | } | |
1485 | ||
1486 | /* Since the actual Tx work is minimal, we can give the Tx a larger | |
1487 | * budget and be more aggressive about cleaning up the Tx descriptors. | |
1488 | */ | |
c29af37f | 1489 | i40e_for_each_ring(ring, q_vector->tx) { |
a619afe8 | 1490 | if (!i40e_clean_tx_irq(vsi, ring, budget)) { |
f2edaaaa AD |
1491 | clean_complete = false; |
1492 | continue; | |
1493 | } | |
1494 | arm_wb |= ring->arm_wb; | |
0deda868 | 1495 | ring->arm_wb = false; |
c29af37f | 1496 | } |
7f12ad74 | 1497 | |
c67caceb AD |
1498 | /* Handle case where we are called by netpoll with a budget of 0 */ |
1499 | if (budget <= 0) | |
1500 | goto tx_only; | |
1501 | ||
7f12ad74 GR |
1502 | /* We attempt to distribute budget to each Rx queue fairly, but don't |
1503 | * allow the budget to go below 1 because that would exit polling early. | |
1504 | */ | |
1505 | budget_per_ring = max(budget/q_vector->num_ringpairs, 1); | |
1506 | ||
a132af24 | 1507 | i40e_for_each_ring(ring, q_vector->rx) { |
ab9ad98e | 1508 | int cleaned = i40e_clean_rx_irq(ring, budget_per_ring); |
32b3e08f JB |
1509 | |
1510 | work_done += cleaned; | |
f2edaaaa AD |
1511 | /* if we clean as many as budgeted, we must not be done */ |
1512 | if (cleaned >= budget_per_ring) | |
1513 | clean_complete = false; | |
a132af24 | 1514 | } |
7f12ad74 GR |
1515 | |
1516 | /* If work not completed, return budget and polling will return */ | |
c29af37f | 1517 | if (!clean_complete) { |
96db776a AB |
1518 | const cpumask_t *aff_mask = &q_vector->affinity_mask; |
1519 | int cpu_id = smp_processor_id(); | |
1520 | ||
1521 | /* It is possible that the interrupt affinity has changed but, | |
1522 | * if the cpu is pegged at 100%, polling will never exit while | |
1523 | * traffic continues and the interrupt will be stuck on this | |
1524 | * cpu. We check to make sure affinity is correct before we | |
1525 | * continue to poll, otherwise we must stop polling so the | |
1526 | * interrupt can move to the correct cpu. | |
1527 | */ | |
1528 | if (likely(cpumask_test_cpu(cpu_id, aff_mask))) { | |
c67caceb | 1529 | tx_only: |
96db776a AB |
1530 | if (arm_wb) { |
1531 | q_vector->tx.ring[0].tx_stats.tx_force_wb++; | |
1532 | i40e_enable_wb_on_itr(vsi, q_vector); | |
1533 | } | |
1534 | return budget; | |
164c9f54 | 1535 | } |
c29af37f | 1536 | } |
7f12ad74 | 1537 | |
8e0764b4 ASJ |
1538 | if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR) |
1539 | q_vector->arm_wb_state = false; | |
1540 | ||
7f12ad74 | 1541 | /* Work is done so exit the polling mode and re-enable the interrupt */ |
32b3e08f | 1542 | napi_complete_done(napi, work_done); |
96db776a AB |
1543 | |
1544 | /* If we're prematurely stopping polling to fix the interrupt | |
1545 | * affinity we want to make sure polling starts back up so we | |
1546 | * issue a call to i40evf_force_wb which triggers a SW interrupt. | |
1547 | */ | |
1548 | if (!clean_complete) | |
1549 | i40evf_force_wb(vsi, q_vector); | |
1550 | else | |
1551 | i40e_update_enable_itr(vsi, q_vector); | |
1552 | ||
6beb84a7 | 1553 | return min(work_done, budget - 1); |
7f12ad74 GR |
1554 | } |
1555 | ||
1556 | /** | |
3e587cf3 | 1557 | * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW |
7f12ad74 GR |
1558 | * @skb: send buffer |
1559 | * @tx_ring: ring to send buffer on | |
1560 | * @flags: the tx flags to be set | |
1561 | * | |
1562 | * Checks the skb and set up correspondingly several generic transmit flags | |
1563 | * related to VLAN tagging for the HW, such as VLAN, DCB, etc. | |
1564 | * | |
1565 | * Returns error code indicate the frame should be dropped upon error and the | |
1566 | * otherwise returns 0 to indicate the flags has been set properly. | |
1567 | **/ | |
3e587cf3 JB |
1568 | static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb, |
1569 | struct i40e_ring *tx_ring, | |
1570 | u32 *flags) | |
7f12ad74 GR |
1571 | { |
1572 | __be16 protocol = skb->protocol; | |
1573 | u32 tx_flags = 0; | |
1574 | ||
31eaaccf GR |
1575 | if (protocol == htons(ETH_P_8021Q) && |
1576 | !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) { | |
1577 | /* When HW VLAN acceleration is turned off by the user the | |
1578 | * stack sets the protocol to 8021q so that the driver | |
1579 | * can take any steps required to support the SW only | |
1580 | * VLAN handling. In our case the driver doesn't need | |
1581 | * to take any further steps so just set the protocol | |
1582 | * to the encapsulated ethertype. | |
1583 | */ | |
1584 | skb->protocol = vlan_get_protocol(skb); | |
1585 | goto out; | |
1586 | } | |
1587 | ||
7f12ad74 | 1588 | /* if we have a HW VLAN tag being added, default to the HW one */ |
df8a39de JP |
1589 | if (skb_vlan_tag_present(skb)) { |
1590 | tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT; | |
7f12ad74 GR |
1591 | tx_flags |= I40E_TX_FLAGS_HW_VLAN; |
1592 | /* else if it is a SW VLAN, check the next protocol and store the tag */ | |
1593 | } else if (protocol == htons(ETH_P_8021Q)) { | |
1594 | struct vlan_hdr *vhdr, _vhdr; | |
6995b36c | 1595 | |
7f12ad74 GR |
1596 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); |
1597 | if (!vhdr) | |
1598 | return -EINVAL; | |
1599 | ||
1600 | protocol = vhdr->h_vlan_encapsulated_proto; | |
1601 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT; | |
1602 | tx_flags |= I40E_TX_FLAGS_SW_VLAN; | |
1603 | } | |
1604 | ||
31eaaccf | 1605 | out: |
7f12ad74 GR |
1606 | *flags = tx_flags; |
1607 | return 0; | |
1608 | } | |
1609 | ||
1610 | /** | |
1611 | * i40e_tso - set up the tso context descriptor | |
52ea3e80 | 1612 | * @first: pointer to first Tx buffer for xmit |
7f12ad74 | 1613 | * @hdr_len: ptr to the size of the packet header |
9c883bd3 | 1614 | * @cd_type_cmd_tso_mss: Quad Word 1 |
7f12ad74 GR |
1615 | * |
1616 | * Returns 0 if no TSO can happen, 1 if tso is going, or error | |
1617 | **/ | |
52ea3e80 AD |
1618 | static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len, |
1619 | u64 *cd_type_cmd_tso_mss) | |
7f12ad74 | 1620 | { |
52ea3e80 | 1621 | struct sk_buff *skb = first->skb; |
03f9d6a5 | 1622 | u64 cd_cmd, cd_tso_len, cd_mss; |
c777019a AD |
1623 | union { |
1624 | struct iphdr *v4; | |
1625 | struct ipv6hdr *v6; | |
1626 | unsigned char *hdr; | |
1627 | } ip; | |
c49a7bc3 AD |
1628 | union { |
1629 | struct tcphdr *tcp; | |
5453205c | 1630 | struct udphdr *udp; |
c49a7bc3 AD |
1631 | unsigned char *hdr; |
1632 | } l4; | |
1633 | u32 paylen, l4_offset; | |
52ea3e80 | 1634 | u16 gso_segs, gso_size; |
7f12ad74 | 1635 | int err; |
7f12ad74 | 1636 | |
e9f6563d SN |
1637 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
1638 | return 0; | |
1639 | ||
7f12ad74 GR |
1640 | if (!skb_is_gso(skb)) |
1641 | return 0; | |
1642 | ||
fe6d4aa4 FR |
1643 | err = skb_cow_head(skb, 0); |
1644 | if (err < 0) | |
1645 | return err; | |
7f12ad74 | 1646 | |
c777019a AD |
1647 | ip.hdr = skb_network_header(skb); |
1648 | l4.hdr = skb_transport_header(skb); | |
85e76d03 | 1649 | |
c777019a AD |
1650 | /* initialize outer IP header fields */ |
1651 | if (ip.v4->version == 4) { | |
1652 | ip.v4->tot_len = 0; | |
1653 | ip.v4->check = 0; | |
c49a7bc3 | 1654 | } else { |
c777019a AD |
1655 | ip.v6->payload_len = 0; |
1656 | } | |
1657 | ||
577389a5 | 1658 | if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE | |
1c7b4a23 | 1659 | SKB_GSO_GRE_CSUM | |
7e13318d | 1660 | SKB_GSO_IPXIP4 | |
bf2d1df3 | 1661 | SKB_GSO_IPXIP6 | |
577389a5 | 1662 | SKB_GSO_UDP_TUNNEL | |
5453205c | 1663 | SKB_GSO_UDP_TUNNEL_CSUM)) { |
1c7b4a23 AD |
1664 | if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
1665 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) { | |
1666 | l4.udp->len = 0; | |
1667 | ||
5453205c AD |
1668 | /* determine offset of outer transport header */ |
1669 | l4_offset = l4.hdr - skb->data; | |
1670 | ||
1671 | /* remove payload length from outer checksum */ | |
24d41e5e | 1672 | paylen = skb->len - l4_offset; |
b9c015d4 JK |
1673 | csum_replace_by_diff(&l4.udp->check, |
1674 | (__force __wsum)htonl(paylen)); | |
5453205c AD |
1675 | } |
1676 | ||
c777019a AD |
1677 | /* reset pointers to inner headers */ |
1678 | ip.hdr = skb_inner_network_header(skb); | |
1679 | l4.hdr = skb_inner_transport_header(skb); | |
1680 | ||
1681 | /* initialize inner IP header fields */ | |
1682 | if (ip.v4->version == 4) { | |
1683 | ip.v4->tot_len = 0; | |
1684 | ip.v4->check = 0; | |
1685 | } else { | |
1686 | ip.v6->payload_len = 0; | |
1687 | } | |
7f12ad74 GR |
1688 | } |
1689 | ||
c49a7bc3 AD |
1690 | /* determine offset of inner transport header */ |
1691 | l4_offset = l4.hdr - skb->data; | |
1692 | ||
1693 | /* remove payload length from inner checksum */ | |
24d41e5e | 1694 | paylen = skb->len - l4_offset; |
b9c015d4 | 1695 | csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen)); |
c49a7bc3 AD |
1696 | |
1697 | /* compute length of segmentation header */ | |
1698 | *hdr_len = (l4.tcp->doff * 4) + l4_offset; | |
7f12ad74 | 1699 | |
52ea3e80 AD |
1700 | /* pull values out of skb_shinfo */ |
1701 | gso_size = skb_shinfo(skb)->gso_size; | |
1702 | gso_segs = skb_shinfo(skb)->gso_segs; | |
1703 | ||
1704 | /* update GSO size and bytecount with header size */ | |
1705 | first->gso_segs = gso_segs; | |
1706 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
1707 | ||
7f12ad74 GR |
1708 | /* find the field values */ |
1709 | cd_cmd = I40E_TX_CTX_DESC_TSO; | |
1710 | cd_tso_len = skb->len - *hdr_len; | |
52ea3e80 | 1711 | cd_mss = gso_size; |
03f9d6a5 AD |
1712 | *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) | |
1713 | (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) | | |
1714 | (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT); | |
7f12ad74 GR |
1715 | return 1; |
1716 | } | |
1717 | ||
1718 | /** | |
1719 | * i40e_tx_enable_csum - Enable Tx checksum offloads | |
1720 | * @skb: send buffer | |
89232c3b | 1721 | * @tx_flags: pointer to Tx flags currently set |
7f12ad74 GR |
1722 | * @td_cmd: Tx descriptor command bits to set |
1723 | * @td_offset: Tx descriptor header offsets to set | |
529f1f65 | 1724 | * @tx_ring: Tx descriptor ring |
7f12ad74 GR |
1725 | * @cd_tunneling: ptr to context desc bits |
1726 | **/ | |
529f1f65 AD |
1727 | static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags, |
1728 | u32 *td_cmd, u32 *td_offset, | |
1729 | struct i40e_ring *tx_ring, | |
1730 | u32 *cd_tunneling) | |
7f12ad74 | 1731 | { |
b96b78f2 AD |
1732 | union { |
1733 | struct iphdr *v4; | |
1734 | struct ipv6hdr *v6; | |
1735 | unsigned char *hdr; | |
1736 | } ip; | |
1737 | union { | |
1738 | struct tcphdr *tcp; | |
1739 | struct udphdr *udp; | |
1740 | unsigned char *hdr; | |
1741 | } l4; | |
a3fd9d88 | 1742 | unsigned char *exthdr; |
d1bd743b | 1743 | u32 offset, cmd = 0; |
a3fd9d88 | 1744 | __be16 frag_off; |
b96b78f2 AD |
1745 | u8 l4_proto = 0; |
1746 | ||
529f1f65 AD |
1747 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
1748 | return 0; | |
1749 | ||
b96b78f2 AD |
1750 | ip.hdr = skb_network_header(skb); |
1751 | l4.hdr = skb_transport_header(skb); | |
7f12ad74 | 1752 | |
475b4205 AD |
1753 | /* compute outer L2 header size */ |
1754 | offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT; | |
1755 | ||
7f12ad74 | 1756 | if (skb->encapsulation) { |
d1bd743b | 1757 | u32 tunnel = 0; |
a0064728 AD |
1758 | /* define outer network header type */ |
1759 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { | |
475b4205 AD |
1760 | tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
1761 | I40E_TX_CTX_EXT_IP_IPV4 : | |
1762 | I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM; | |
1763 | ||
a0064728 AD |
1764 | l4_proto = ip.v4->protocol; |
1765 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { | |
475b4205 | 1766 | tunnel |= I40E_TX_CTX_EXT_IP_IPV6; |
a3fd9d88 AD |
1767 | |
1768 | exthdr = ip.hdr + sizeof(*ip.v6); | |
a0064728 | 1769 | l4_proto = ip.v6->nexthdr; |
a3fd9d88 AD |
1770 | if (l4.hdr != exthdr) |
1771 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
1772 | &l4_proto, &frag_off); | |
a0064728 AD |
1773 | } |
1774 | ||
1775 | /* define outer transport */ | |
1776 | switch (l4_proto) { | |
45991204 | 1777 | case IPPROTO_UDP: |
475b4205 | 1778 | tunnel |= I40E_TXD_CTX_UDP_TUNNELING; |
89232c3b | 1779 | *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; |
45991204 | 1780 | break; |
a0064728 | 1781 | case IPPROTO_GRE: |
475b4205 | 1782 | tunnel |= I40E_TXD_CTX_GRE_TUNNELING; |
a0064728 AD |
1783 | *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; |
1784 | break; | |
577389a5 AD |
1785 | case IPPROTO_IPIP: |
1786 | case IPPROTO_IPV6: | |
1787 | *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL; | |
1788 | l4.hdr = skb_inner_network_header(skb); | |
1789 | break; | |
45991204 | 1790 | default: |
529f1f65 AD |
1791 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
1792 | return -1; | |
1793 | ||
1794 | skb_checksum_help(skb); | |
1795 | return 0; | |
45991204 | 1796 | } |
b96b78f2 | 1797 | |
577389a5 AD |
1798 | /* compute outer L3 header size */ |
1799 | tunnel |= ((l4.hdr - ip.hdr) / 4) << | |
1800 | I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT; | |
1801 | ||
1802 | /* switch IP header pointer from outer to inner header */ | |
1803 | ip.hdr = skb_inner_network_header(skb); | |
1804 | ||
475b4205 AD |
1805 | /* compute tunnel header size */ |
1806 | tunnel |= ((ip.hdr - l4.hdr) / 2) << | |
1807 | I40E_TXD_CTX_QW0_NATLEN_SHIFT; | |
1808 | ||
5453205c AD |
1809 | /* indicate if we need to offload outer UDP header */ |
1810 | if ((*tx_flags & I40E_TX_FLAGS_TSO) && | |
1c7b4a23 | 1811 | !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) && |
5453205c AD |
1812 | (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) |
1813 | tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK; | |
1814 | ||
475b4205 AD |
1815 | /* record tunnel offload values */ |
1816 | *cd_tunneling |= tunnel; | |
1817 | ||
b96b78f2 | 1818 | /* switch L4 header pointer from outer to inner */ |
b96b78f2 | 1819 | l4.hdr = skb_inner_transport_header(skb); |
a0064728 | 1820 | l4_proto = 0; |
7f12ad74 | 1821 | |
a0064728 AD |
1822 | /* reset type as we transition from outer to inner headers */ |
1823 | *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6); | |
1824 | if (ip.v4->version == 4) | |
1825 | *tx_flags |= I40E_TX_FLAGS_IPV4; | |
1826 | if (ip.v6->version == 6) | |
89232c3b | 1827 | *tx_flags |= I40E_TX_FLAGS_IPV6; |
7f12ad74 GR |
1828 | } |
1829 | ||
1830 | /* Enable IP checksum offloads */ | |
89232c3b | 1831 | if (*tx_flags & I40E_TX_FLAGS_IPV4) { |
b96b78f2 | 1832 | l4_proto = ip.v4->protocol; |
7f12ad74 GR |
1833 | /* the stack computes the IP header already, the only time we |
1834 | * need the hardware to recompute it is in the case of TSO. | |
1835 | */ | |
475b4205 AD |
1836 | cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ? |
1837 | I40E_TX_DESC_CMD_IIPT_IPV4_CSUM : | |
1838 | I40E_TX_DESC_CMD_IIPT_IPV4; | |
89232c3b | 1839 | } else if (*tx_flags & I40E_TX_FLAGS_IPV6) { |
475b4205 | 1840 | cmd |= I40E_TX_DESC_CMD_IIPT_IPV6; |
a3fd9d88 AD |
1841 | |
1842 | exthdr = ip.hdr + sizeof(*ip.v6); | |
1843 | l4_proto = ip.v6->nexthdr; | |
1844 | if (l4.hdr != exthdr) | |
1845 | ipv6_skip_exthdr(skb, exthdr - skb->data, | |
1846 | &l4_proto, &frag_off); | |
7f12ad74 | 1847 | } |
b96b78f2 | 1848 | |
475b4205 AD |
1849 | /* compute inner L3 header size */ |
1850 | offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT; | |
7f12ad74 GR |
1851 | |
1852 | /* Enable L4 checksum offloads */ | |
b96b78f2 | 1853 | switch (l4_proto) { |
7f12ad74 GR |
1854 | case IPPROTO_TCP: |
1855 | /* enable checksum offloads */ | |
475b4205 AD |
1856 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP; |
1857 | offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
7f12ad74 GR |
1858 | break; |
1859 | case IPPROTO_SCTP: | |
1860 | /* enable SCTP checksum offload */ | |
475b4205 AD |
1861 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP; |
1862 | offset |= (sizeof(struct sctphdr) >> 2) << | |
1863 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
7f12ad74 GR |
1864 | break; |
1865 | case IPPROTO_UDP: | |
1866 | /* enable UDP checksum offload */ | |
475b4205 AD |
1867 | cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP; |
1868 | offset |= (sizeof(struct udphdr) >> 2) << | |
1869 | I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT; | |
7f12ad74 GR |
1870 | break; |
1871 | default: | |
529f1f65 AD |
1872 | if (*tx_flags & I40E_TX_FLAGS_TSO) |
1873 | return -1; | |
1874 | skb_checksum_help(skb); | |
1875 | return 0; | |
7f12ad74 | 1876 | } |
475b4205 AD |
1877 | |
1878 | *td_cmd |= cmd; | |
1879 | *td_offset |= offset; | |
529f1f65 AD |
1880 | |
1881 | return 1; | |
7f12ad74 GR |
1882 | } |
1883 | ||
1884 | /** | |
1885 | * i40e_create_tx_ctx Build the Tx context descriptor | |
1886 | * @tx_ring: ring to create the descriptor on | |
1887 | * @cd_type_cmd_tso_mss: Quad Word 1 | |
1888 | * @cd_tunneling: Quad Word 0 - bits 0-31 | |
1889 | * @cd_l2tag2: Quad Word 0 - bits 32-63 | |
1890 | **/ | |
1891 | static void i40e_create_tx_ctx(struct i40e_ring *tx_ring, | |
1892 | const u64 cd_type_cmd_tso_mss, | |
1893 | const u32 cd_tunneling, const u32 cd_l2tag2) | |
1894 | { | |
1895 | struct i40e_tx_context_desc *context_desc; | |
1896 | int i = tx_ring->next_to_use; | |
1897 | ||
ff40dd5d JB |
1898 | if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) && |
1899 | !cd_tunneling && !cd_l2tag2) | |
7f12ad74 GR |
1900 | return; |
1901 | ||
1902 | /* grab the next descriptor */ | |
1903 | context_desc = I40E_TX_CTXTDESC(tx_ring, i); | |
1904 | ||
1905 | i++; | |
1906 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
1907 | ||
1908 | /* cpu_to_le32 and assign to struct fields */ | |
1909 | context_desc->tunneling_params = cpu_to_le32(cd_tunneling); | |
1910 | context_desc->l2tag2 = cpu_to_le16(cd_l2tag2); | |
3efbbb20 | 1911 | context_desc->rsvd = cpu_to_le16(0); |
7f12ad74 GR |
1912 | context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss); |
1913 | } | |
1914 | ||
4eeb1fff | 1915 | /** |
3f3f7cb8 | 1916 | * __i40evf_chk_linearize - Check if there are more than 8 buffers per packet |
71da6197 | 1917 | * @skb: send buffer |
71da6197 | 1918 | * |
3f3f7cb8 AD |
1919 | * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire |
1920 | * and so we need to figure out the cases where we need to linearize the skb. | |
1921 | * | |
1922 | * For TSO we need to count the TSO header and segment payload separately. | |
1923 | * As such we need to check cases where we have 7 fragments or more as we | |
1924 | * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for | |
1925 | * the segment payload in the first descriptor, and another 7 for the | |
1926 | * fragments. | |
71da6197 | 1927 | **/ |
2d37490b | 1928 | bool __i40evf_chk_linearize(struct sk_buff *skb) |
71da6197 | 1929 | { |
2d37490b | 1930 | const struct skb_frag_struct *frag, *stale; |
3f3f7cb8 | 1931 | int nr_frags, sum; |
71da6197 | 1932 | |
3f3f7cb8 | 1933 | /* no need to check if number of frags is less than 7 */ |
2d37490b | 1934 | nr_frags = skb_shinfo(skb)->nr_frags; |
3f3f7cb8 | 1935 | if (nr_frags < (I40E_MAX_BUFFER_TXD - 1)) |
2d37490b | 1936 | return false; |
71da6197 | 1937 | |
2d37490b | 1938 | /* We need to walk through the list and validate that each group |
841493a3 | 1939 | * of 6 fragments totals at least gso_size. |
2d37490b | 1940 | */ |
3f3f7cb8 | 1941 | nr_frags -= I40E_MAX_BUFFER_TXD - 2; |
2d37490b AD |
1942 | frag = &skb_shinfo(skb)->frags[0]; |
1943 | ||
1944 | /* Initialize size to the negative value of gso_size minus 1. We | |
1945 | * use this as the worst case scenerio in which the frag ahead | |
1946 | * of us only provides one byte which is why we are limited to 6 | |
1947 | * descriptors for a single transmit as the header and previous | |
1948 | * fragment are already consuming 2 descriptors. | |
1949 | */ | |
3f3f7cb8 | 1950 | sum = 1 - skb_shinfo(skb)->gso_size; |
2d37490b | 1951 | |
3f3f7cb8 AD |
1952 | /* Add size of frags 0 through 4 to create our initial sum */ |
1953 | sum += skb_frag_size(frag++); | |
1954 | sum += skb_frag_size(frag++); | |
1955 | sum += skb_frag_size(frag++); | |
1956 | sum += skb_frag_size(frag++); | |
1957 | sum += skb_frag_size(frag++); | |
2d37490b AD |
1958 | |
1959 | /* Walk through fragments adding latest fragment, testing it, and | |
1960 | * then removing stale fragments from the sum. | |
1961 | */ | |
1962 | stale = &skb_shinfo(skb)->frags[0]; | |
1963 | for (;;) { | |
3f3f7cb8 | 1964 | sum += skb_frag_size(frag++); |
2d37490b AD |
1965 | |
1966 | /* if sum is negative we failed to make sufficient progress */ | |
1967 | if (sum < 0) | |
1968 | return true; | |
1969 | ||
841493a3 | 1970 | if (!nr_frags--) |
2d37490b AD |
1971 | break; |
1972 | ||
3f3f7cb8 | 1973 | sum -= skb_frag_size(stale++); |
71da6197 AS |
1974 | } |
1975 | ||
2d37490b | 1976 | return false; |
71da6197 AS |
1977 | } |
1978 | ||
8f6a2b05 JB |
1979 | /** |
1980 | * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions | |
1981 | * @tx_ring: the ring to be checked | |
1982 | * @size: the size buffer we want to assure is available | |
1983 | * | |
1984 | * Returns -EBUSY if a stop is needed, else 0 | |
1985 | **/ | |
4ec441df | 1986 | int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size) |
8f6a2b05 JB |
1987 | { |
1988 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
1989 | /* Memory barrier before checking head and tail */ | |
1990 | smp_mb(); | |
1991 | ||
1992 | /* Check again in a case another CPU has just made room available. */ | |
1993 | if (likely(I40E_DESC_UNUSED(tx_ring) < size)) | |
1994 | return -EBUSY; | |
1995 | ||
1996 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
1997 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
1998 | ++tx_ring->tx_stats.restart_queue; | |
1999 | return 0; | |
2000 | } | |
2001 | ||
7f12ad74 | 2002 | /** |
3e587cf3 | 2003 | * i40evf_tx_map - Build the Tx descriptor |
7f12ad74 GR |
2004 | * @tx_ring: ring to send buffer on |
2005 | * @skb: send buffer | |
2006 | * @first: first buffer info buffer to use | |
2007 | * @tx_flags: collected send information | |
2008 | * @hdr_len: size of the packet header | |
2009 | * @td_cmd: the command field in the descriptor | |
2010 | * @td_offset: offset for checksum or crc | |
2011 | **/ | |
3e587cf3 JB |
2012 | static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb, |
2013 | struct i40e_tx_buffer *first, u32 tx_flags, | |
2014 | const u8 hdr_len, u32 td_cmd, u32 td_offset) | |
7f12ad74 GR |
2015 | { |
2016 | unsigned int data_len = skb->data_len; | |
2017 | unsigned int size = skb_headlen(skb); | |
2018 | struct skb_frag_struct *frag; | |
2019 | struct i40e_tx_buffer *tx_bi; | |
2020 | struct i40e_tx_desc *tx_desc; | |
2021 | u16 i = tx_ring->next_to_use; | |
2022 | u32 td_tag = 0; | |
2023 | dma_addr_t dma; | |
7f12ad74 GR |
2024 | |
2025 | if (tx_flags & I40E_TX_FLAGS_HW_VLAN) { | |
2026 | td_cmd |= I40E_TX_DESC_CMD_IL2TAG1; | |
2027 | td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >> | |
2028 | I40E_TX_FLAGS_VLAN_SHIFT; | |
2029 | } | |
2030 | ||
7f12ad74 GR |
2031 | first->tx_flags = tx_flags; |
2032 | ||
2033 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); | |
2034 | ||
2035 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
2036 | tx_bi = first; | |
2037 | ||
2038 | for (frag = &skb_shinfo(skb)->frags[0];; frag++) { | |
5c4654da AD |
2039 | unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
2040 | ||
7f12ad74 GR |
2041 | if (dma_mapping_error(tx_ring->dev, dma)) |
2042 | goto dma_error; | |
2043 | ||
2044 | /* record length, and DMA address */ | |
2045 | dma_unmap_len_set(tx_bi, len, size); | |
2046 | dma_unmap_addr_set(tx_bi, dma, dma); | |
2047 | ||
5c4654da AD |
2048 | /* align size to end of page */ |
2049 | max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1); | |
7f12ad74 GR |
2050 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2051 | ||
2052 | while (unlikely(size > I40E_MAX_DATA_PER_TXD)) { | |
2053 | tx_desc->cmd_type_offset_bsz = | |
2054 | build_ctob(td_cmd, td_offset, | |
5c4654da | 2055 | max_data, td_tag); |
7f12ad74 GR |
2056 | |
2057 | tx_desc++; | |
2058 | i++; | |
6a7fded7 | 2059 | |
7f12ad74 GR |
2060 | if (i == tx_ring->count) { |
2061 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2062 | i = 0; | |
2063 | } | |
2064 | ||
5c4654da AD |
2065 | dma += max_data; |
2066 | size -= max_data; | |
7f12ad74 | 2067 | |
5c4654da | 2068 | max_data = I40E_MAX_DATA_PER_TXD_ALIGNED; |
7f12ad74 GR |
2069 | tx_desc->buffer_addr = cpu_to_le64(dma); |
2070 | } | |
2071 | ||
2072 | if (likely(!data_len)) | |
2073 | break; | |
2074 | ||
2075 | tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset, | |
2076 | size, td_tag); | |
2077 | ||
2078 | tx_desc++; | |
2079 | i++; | |
6a7fded7 | 2080 | |
7f12ad74 GR |
2081 | if (i == tx_ring->count) { |
2082 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
2083 | i = 0; | |
2084 | } | |
2085 | ||
2086 | size = skb_frag_size(frag); | |
2087 | data_len -= size; | |
2088 | ||
2089 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, | |
2090 | DMA_TO_DEVICE); | |
2091 | ||
2092 | tx_bi = &tx_ring->tx_bi[i]; | |
2093 | } | |
2094 | ||
1dc8b538 | 2095 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
7f12ad74 GR |
2096 | |
2097 | i++; | |
2098 | if (i == tx_ring->count) | |
2099 | i = 0; | |
2100 | ||
2101 | tx_ring->next_to_use = i; | |
2102 | ||
4ec441df | 2103 | i40e_maybe_stop_tx(tx_ring, DESC_NEEDED); |
6a7fded7 | 2104 | |
b1cb07db PB |
2105 | /* write last descriptor with RS and EOP bits */ |
2106 | td_cmd |= I40E_TXD_CMD; | |
6a7fded7 | 2107 | tx_desc->cmd_type_offset_bsz = |
1dc8b538 AD |
2108 | build_ctob(td_cmd, td_offset, size, td_tag); |
2109 | ||
2110 | /* Force memory writes to complete before letting h/w know there | |
2111 | * are new descriptors to fetch. | |
2112 | * | |
2113 | * We also use this memory barrier to make certain all of the | |
2114 | * status bits have been updated before next_to_watch is written. | |
2115 | */ | |
2116 | wmb(); | |
2117 | ||
2118 | /* set next_to_watch value indicating a packet is present */ | |
2119 | first->next_to_watch = tx_desc; | |
6a7fded7 | 2120 | |
7f12ad74 | 2121 | /* notify HW of packet */ |
b1cb07db | 2122 | if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) { |
6a7fded7 | 2123 | writel(i, tx_ring->tail); |
1dc8b538 AD |
2124 | |
2125 | /* we need this if more than one processor can write to our tail | |
2126 | * at a time, it synchronizes IO on IA64/Altix systems | |
2127 | */ | |
2128 | mmiowb(); | |
6a7fded7 | 2129 | } |
1dc8b538 | 2130 | |
7f12ad74 GR |
2131 | return; |
2132 | ||
2133 | dma_error: | |
2134 | dev_info(tx_ring->dev, "TX DMA map failed\n"); | |
2135 | ||
2136 | /* clear dma mappings for failed tx_bi map */ | |
2137 | for (;;) { | |
2138 | tx_bi = &tx_ring->tx_bi[i]; | |
2139 | i40e_unmap_and_free_tx_resource(tx_ring, tx_bi); | |
2140 | if (tx_bi == first) | |
2141 | break; | |
2142 | if (i == 0) | |
2143 | i = tx_ring->count; | |
2144 | i--; | |
2145 | } | |
2146 | ||
2147 | tx_ring->next_to_use = i; | |
2148 | } | |
2149 | ||
7f12ad74 GR |
2150 | /** |
2151 | * i40e_xmit_frame_ring - Sends buffer on Tx ring | |
2152 | * @skb: send buffer | |
2153 | * @tx_ring: ring to send buffer on | |
2154 | * | |
2155 | * Returns NETDEV_TX_OK if sent, else an error code | |
2156 | **/ | |
2157 | static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb, | |
2158 | struct i40e_ring *tx_ring) | |
2159 | { | |
2160 | u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT; | |
2161 | u32 cd_tunneling = 0, cd_l2tag2 = 0; | |
2162 | struct i40e_tx_buffer *first; | |
2163 | u32 td_offset = 0; | |
2164 | u32 tx_flags = 0; | |
2165 | __be16 protocol; | |
2166 | u32 td_cmd = 0; | |
2167 | u8 hdr_len = 0; | |
4ec441df | 2168 | int tso, count; |
6995b36c | 2169 | |
b74118f0 JB |
2170 | /* prefetch the data, we'll need it later */ |
2171 | prefetch(skb->data); | |
2172 | ||
4ec441df | 2173 | count = i40e_xmit_descriptor_count(skb); |
2d37490b | 2174 | if (i40e_chk_linearize(skb, count)) { |
52ea3e80 AD |
2175 | if (__skb_linearize(skb)) { |
2176 | dev_kfree_skb_any(skb); | |
2177 | return NETDEV_TX_OK; | |
2178 | } | |
5c4654da | 2179 | count = i40e_txd_use_count(skb->len); |
2d37490b AD |
2180 | tx_ring->tx_stats.tx_linearize++; |
2181 | } | |
4ec441df AD |
2182 | |
2183 | /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD, | |
2184 | * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD, | |
2185 | * + 4 desc gap to avoid the cache line where head is, | |
2186 | * + 1 desc for context descriptor, | |
2187 | * otherwise try next time | |
2188 | */ | |
2189 | if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) { | |
2190 | tx_ring->tx_stats.tx_busy++; | |
7f12ad74 | 2191 | return NETDEV_TX_BUSY; |
4ec441df | 2192 | } |
7f12ad74 | 2193 | |
52ea3e80 AD |
2194 | /* record the location of the first descriptor for this packet */ |
2195 | first = &tx_ring->tx_bi[tx_ring->next_to_use]; | |
2196 | first->skb = skb; | |
2197 | first->bytecount = skb->len; | |
2198 | first->gso_segs = 1; | |
2199 | ||
7f12ad74 | 2200 | /* prepare the xmit flags */ |
3e587cf3 | 2201 | if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags)) |
7f12ad74 GR |
2202 | goto out_drop; |
2203 | ||
2204 | /* obtain protocol of skb */ | |
a12c4158 | 2205 | protocol = vlan_get_protocol(skb); |
7f12ad74 | 2206 | |
7f12ad74 GR |
2207 | /* setup IPv4/IPv6 offloads */ |
2208 | if (protocol == htons(ETH_P_IP)) | |
2209 | tx_flags |= I40E_TX_FLAGS_IPV4; | |
2210 | else if (protocol == htons(ETH_P_IPV6)) | |
2211 | tx_flags |= I40E_TX_FLAGS_IPV6; | |
2212 | ||
52ea3e80 | 2213 | tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss); |
7f12ad74 GR |
2214 | |
2215 | if (tso < 0) | |
2216 | goto out_drop; | |
2217 | else if (tso) | |
2218 | tx_flags |= I40E_TX_FLAGS_TSO; | |
2219 | ||
7f12ad74 | 2220 | /* Always offload the checksum, since it's in the data descriptor */ |
529f1f65 AD |
2221 | tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset, |
2222 | tx_ring, &cd_tunneling); | |
2223 | if (tso < 0) | |
2224 | goto out_drop; | |
7f12ad74 | 2225 | |
3bc67973 AD |
2226 | skb_tx_timestamp(skb); |
2227 | ||
2228 | /* always enable CRC insertion offload */ | |
2229 | td_cmd |= I40E_TX_DESC_CMD_ICRC; | |
2230 | ||
7f12ad74 GR |
2231 | i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss, |
2232 | cd_tunneling, cd_l2tag2); | |
2233 | ||
3e587cf3 JB |
2234 | i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len, |
2235 | td_cmd, td_offset); | |
7f12ad74 | 2236 | |
7f12ad74 GR |
2237 | return NETDEV_TX_OK; |
2238 | ||
2239 | out_drop: | |
52ea3e80 AD |
2240 | dev_kfree_skb_any(first->skb); |
2241 | first->skb = NULL; | |
7f12ad74 GR |
2242 | return NETDEV_TX_OK; |
2243 | } | |
2244 | ||
2245 | /** | |
2246 | * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer | |
2247 | * @skb: send buffer | |
2248 | * @netdev: network interface device structure | |
2249 | * | |
2250 | * Returns NETDEV_TX_OK if sent, else an error code | |
2251 | **/ | |
2252 | netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev) | |
2253 | { | |
2254 | struct i40evf_adapter *adapter = netdev_priv(netdev); | |
0dd438d8 | 2255 | struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping]; |
7f12ad74 GR |
2256 | |
2257 | /* hardware can't handle really short frames, hardware padding works | |
2258 | * beyond this point | |
2259 | */ | |
2260 | if (unlikely(skb->len < I40E_MIN_TX_LEN)) { | |
2261 | if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len)) | |
2262 | return NETDEV_TX_OK; | |
2263 | skb->len = I40E_MIN_TX_LEN; | |
2264 | skb_set_tail_pointer(skb, I40E_MIN_TX_LEN); | |
2265 | } | |
2266 | ||
2267 | return i40e_xmit_frame_ring(skb, tx_ring); | |
2268 | } |