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ae06c70b | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
51dce24b | 2 | /* Copyright(c) 2013 - 2018 Intel Corporation. */ |
7daa6bf3 | 3 | |
36fac581 VD |
4 | #ifndef _I40E_TXRX_H_ |
5 | #define _I40E_TXRX_H_ | |
6 | ||
87128824 | 7 | #include <net/xdp.h> |
56df3459 | 8 | #include "i40e_type.h" |
87128824 | 9 | |
aee8087f | 10 | /* Interrupt Throttling and Rate Limiting Goodies */ |
7daa6bf3 | 11 | #define I40E_DEFAULT_IRQ_WORK 256 |
92418fb1 AD |
12 | |
13 | /* The datasheet for the X710 and XL710 indicate that the maximum value for | |
14 | * the ITR is 8160usec which is then called out as 0xFF0 with a 2usec | |
15 | * resolution. 8160 is 0x1FE0 when written out in hex. So instead of storing | |
16 | * the register value which is divided by 2 lets use the actual values and | |
17 | * avoid an excessive amount of translation. | |
18 | */ | |
19 | #define I40E_ITR_DYNAMIC 0x8000 /* use top bit as a flag */ | |
20 | #define I40E_ITR_MASK 0x1FFE /* mask for ITR register value */ | |
21 | #define I40E_MIN_ITR 2 /* reg uses 2 usec resolution */ | |
92418fb1 | 22 | #define I40E_ITR_20K 50 |
92418fb1 AD |
23 | #define I40E_ITR_8K 122 |
24 | #define I40E_MAX_ITR 8160 /* maximum value as per datasheet */ | |
25 | #define ITR_TO_REG(setting) ((setting) & ~I40E_ITR_DYNAMIC) | |
26 | #define ITR_REG_ALIGN(setting) __ALIGN_MASK(setting, ~I40E_ITR_MASK) | |
27 | #define ITR_IS_DYNAMIC(setting) (!!((setting) & I40E_ITR_DYNAMIC)) | |
28 | ||
29 | #define I40E_ITR_RX_DEF (I40E_ITR_20K | I40E_ITR_DYNAMIC) | |
30 | #define I40E_ITR_TX_DEF (I40E_ITR_20K | I40E_ITR_DYNAMIC) | |
31 | ||
ac26fc13 JB |
32 | /* 0x40 is the enable bit for interrupt rate limiting, and must be set if |
33 | * the value of the rate limit is non-zero | |
34 | */ | |
35 | #define INTRL_ENA BIT(6) | |
92418fb1 | 36 | #define I40E_MAX_INTRL 0x3B /* reg uses 4 usec resolution */ |
ac26fc13 | 37 | #define INTRL_REG_TO_USEC(intrl) ((intrl & ~INTRL_ENA) << 2) |
92418fb1 | 38 | |
1c0e6a36 AB |
39 | /** |
40 | * i40e_intrl_usec_to_reg - convert interrupt rate limit to register | |
41 | * @intrl: interrupt rate limit to convert | |
42 | * | |
43 | * This function converts a decimal interrupt rate limit to the appropriate | |
44 | * register format expected by the firmware when setting interrupt rate limit. | |
45 | */ | |
46 | static inline u16 i40e_intrl_usec_to_reg(int intrl) | |
47 | { | |
48 | if (intrl >> 2) | |
49 | return ((intrl >> 2) | INTRL_ENA); | |
50 | else | |
51 | return 0; | |
52 | } | |
7daa6bf3 JB |
53 | |
54 | #define I40E_QUEUE_END_OF_LIST 0x7FF | |
55 | ||
0319577f JB |
56 | /* this enum matches hardware bits and is meant to be used by DYN_CTLN |
57 | * registers and QINT registers or more generally anywhere in the manual | |
58 | * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any | |
59 | * register but instead is a special value meaning "don't update" ITR0/1/2. | |
60 | */ | |
addca917 | 61 | enum i40e_dyn_idx { |
0319577f JB |
62 | I40E_IDX_ITR0 = 0, |
63 | I40E_IDX_ITR1 = 1, | |
64 | I40E_IDX_ITR2 = 2, | |
65 | I40E_ITR_NONE = 3 /* ITR_NONE must not be used as an index */ | |
66 | }; | |
67 | ||
68 | /* these are indexes into ITRN registers */ | |
69 | #define I40E_RX_ITR I40E_IDX_ITR0 | |
70 | #define I40E_TX_ITR I40E_IDX_ITR1 | |
ea558de7 | 71 | #define I40E_SW_ITR I40E_IDX_ITR2 |
0319577f | 72 | |
12dc4fe3 MW |
73 | /* Supported RSS offloads */ |
74 | #define I40E_DEFAULT_RSS_HENA ( \ | |
41a1d04b JB |
75 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \ |
76 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \ | |
77 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \ | |
78 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \ | |
79 | BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \ | |
80 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \ | |
81 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \ | |
82 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \ | |
83 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \ | |
84 | BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \ | |
85 | BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD)) | |
12dc4fe3 | 86 | |
e25d00b8 | 87 | #define I40E_DEFAULT_RSS_HENA_EXPANDED (I40E_DEFAULT_RSS_HENA | \ |
9c70d7ce JB |
88 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \ |
89 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \ | |
90 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \ | |
91 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \ | |
92 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \ | |
93 | BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP)) | |
e25d00b8 ASJ |
94 | |
95 | #define i40e_pf_get_default_rss_hena(pf) \ | |
0e8b9fdd | 96 | (test_bit(I40E_HW_CAP_MULTI_TCP_UDP_RSS_PCTYPE, (pf)->hw.caps) ? \ |
70756d0a | 97 | I40E_DEFAULT_RSS_HENA_EXPANDED : I40E_DEFAULT_RSS_HENA) |
e25d00b8 | 98 | |
1a557afc JB |
99 | /* Supported Rx Buffer Sizes (a multiple of 128) */ |
100 | #define I40E_RXBUFFER_256 256 | |
dab86afd | 101 | #define I40E_RXBUFFER_1536 1536 /* 128B aligned standard Ethernet frame */ |
7daa6bf3 | 102 | #define I40E_RXBUFFER_2048 2048 |
98efd694 | 103 | #define I40E_RXBUFFER_3072 3072 /* Used for large frames w/ padding */ |
7daa6bf3 JB |
104 | #define I40E_MAX_RXBUFFER 9728 /* largest size for single descriptor */ |
105 | ||
106 | /* NOTE: netdev_alloc_skb reserves up to 64 bytes, NET_IP_ALIGN means we | |
107 | * reserve 2 more, and skb_shared_info adds an additional 384 bytes more, | |
108 | * this adds up to 512 bytes of extra data meaning the smallest allocation | |
109 | * we could have is 1K. | |
1a557afc JB |
110 | * i.e. RXBUFFER_256 --> 960 byte skb (size-1024 slab) |
111 | * i.e. RXBUFFER_512 --> 1216 byte skb (size-2048 slab) | |
7daa6bf3 | 112 | */ |
1a557afc | 113 | #define I40E_RX_HDR_SIZE I40E_RXBUFFER_256 |
1e3a5fd5 | 114 | #define I40E_PACKET_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2)) |
f0064bfd | 115 | #define i40e_rx_desc i40e_16byte_rx_desc |
1a557afc | 116 | |
59605bc0 AD |
117 | #define I40E_RX_DMA_ATTR \ |
118 | (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING) | |
119 | ||
ca9ec088 AD |
120 | /* Attempt to maximize the headroom available for incoming frames. We |
121 | * use a 2K buffer for receives and need 1536/1534 to store the data for | |
122 | * the frame. This leaves us with 512 bytes of room. From that we need | |
123 | * to deduct the space needed for the shared info and the padding needed | |
124 | * to IP align the frame. | |
125 | * | |
126 | * Note: For cache line sizes 256 or larger this value is going to end | |
127 | * up negative. In these cases we should fall back to the legacy | |
128 | * receive path. | |
129 | */ | |
130 | #if (PAGE_SIZE < 8192) | |
131 | #define I40E_2K_TOO_SMALL_WITH_PADDING \ | |
132 | ((NET_SKB_PAD + I40E_RXBUFFER_1536) > SKB_WITH_OVERHEAD(I40E_RXBUFFER_2048)) | |
133 | ||
134 | static inline int i40e_compute_pad(int rx_buf_len) | |
135 | { | |
136 | int page_size, pad_size; | |
137 | ||
138 | page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2); | |
139 | pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len; | |
140 | ||
141 | return pad_size; | |
142 | } | |
143 | ||
144 | static inline int i40e_skb_pad(void) | |
145 | { | |
146 | int rx_buf_len; | |
147 | ||
148 | /* If a 2K buffer cannot handle a standard Ethernet frame then | |
149 | * optimize padding for a 3K buffer instead of a 1.5K buffer. | |
150 | * | |
151 | * For a 3K buffer we need to add enough padding to allow for | |
152 | * tailroom due to NET_IP_ALIGN possibly shifting us out of | |
153 | * cache-line alignment. | |
154 | */ | |
155 | if (I40E_2K_TOO_SMALL_WITH_PADDING) | |
156 | rx_buf_len = I40E_RXBUFFER_3072 + SKB_DATA_ALIGN(NET_IP_ALIGN); | |
157 | else | |
158 | rx_buf_len = I40E_RXBUFFER_1536; | |
159 | ||
160 | /* if needed make room for NET_IP_ALIGN */ | |
161 | rx_buf_len -= NET_IP_ALIGN; | |
162 | ||
163 | return i40e_compute_pad(rx_buf_len); | |
164 | } | |
165 | ||
166 | #define I40E_SKB_PAD i40e_skb_pad() | |
167 | #else | |
168 | #define I40E_2K_TOO_SMALL_WITH_PADDING false | |
169 | #define I40E_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN) | |
170 | #endif | |
171 | ||
1a557afc JB |
172 | /** |
173 | * i40e_test_staterr - tests bits in Rx descriptor status and error fields | |
174 | * @rx_desc: pointer to receive descriptor (in le64 format) | |
175 | * @stat_err_bits: value to mask | |
176 | * | |
177 | * This function does some fast chicanery in order to return the | |
178 | * value of the mask which is really only used for boolean tests. | |
179 | * The status_error_len doesn't need to be shifted because it begins | |
180 | * at offset zero. | |
181 | */ | |
182 | static inline bool i40e_test_staterr(union i40e_rx_desc *rx_desc, | |
183 | const u64 stat_err_bits) | |
184 | { | |
185 | return !!(rx_desc->wb.qword1.status_error_len & | |
186 | cpu_to_le64(stat_err_bits)); | |
187 | } | |
7daa6bf3 JB |
188 | |
189 | /* How many Rx Buffers do we bundle into one write to the hardware ? */ | |
95bc2fb4 | 190 | #define I40E_RX_BUFFER_WRITE 32 /* Must be power of 2 */ |
a132af24 | 191 | |
7daa6bf3 JB |
192 | #define I40E_RX_NEXT_DESC(r, i, n) \ |
193 | do { \ | |
194 | (i)++; \ | |
195 | if ((i) == (r)->count) \ | |
196 | i = 0; \ | |
197 | (n) = I40E_RX_DESC((r), (i)); \ | |
198 | } while (0) | |
199 | ||
7daa6bf3 | 200 | |
71da6197 | 201 | #define I40E_MAX_BUFFER_TXD 8 |
7daa6bf3 | 202 | #define I40E_MIN_TX_LEN 17 |
5c4654da AD |
203 | |
204 | /* The size limit for a transmit buffer in a descriptor is (16K - 1). | |
205 | * In order to align with the read requests we will align the value to | |
206 | * the nearest 4K which represents our maximum read request size. | |
207 | */ | |
208 | #define I40E_MAX_READ_REQ_SIZE 4096 | |
209 | #define I40E_MAX_DATA_PER_TXD (16 * 1024 - 1) | |
210 | #define I40E_MAX_DATA_PER_TXD_ALIGNED \ | |
211 | (I40E_MAX_DATA_PER_TXD & ~(I40E_MAX_READ_REQ_SIZE - 1)) | |
212 | ||
4293d5f5 MW |
213 | /** |
214 | * i40e_txd_use_count - estimate the number of descriptors needed for Tx | |
215 | * @size: transmit request size in bytes | |
216 | * | |
217 | * Due to hardware alignment restrictions (4K alignment), we need to | |
218 | * assume that we can have no more than 12K of data per descriptor, even | |
219 | * though each descriptor can take up to 16K - 1 bytes of aligned memory. | |
220 | * Thus, we need to divide by 12K. But division is slow! Instead, | |
221 | * we decompose the operation into shifts and one relatively cheap | |
222 | * multiply operation. | |
223 | * | |
224 | * To divide by 12K, we first divide by 4K, then divide by 3: | |
225 | * To divide by 4K, shift right by 12 bits | |
226 | * To divide by 3, multiply by 85, then divide by 256 | |
227 | * (Divide by 256 is done by shifting right by 8 bits) | |
228 | * Finally, we add one to round up. Because 256 isn't an exact multiple of | |
229 | * 3, we'll underestimate near each multiple of 12K. This is actually more | |
230 | * accurate as we have 4K - 1 of wiggle room that we can fit into the last | |
231 | * segment. For our purposes this is accurate out to 1M which is orders of | |
232 | * magnitude greater than our largest possible GSO size. | |
233 | * | |
234 | * This would then be implemented as: | |
235 | * return (((size >> 12) * 85) >> 8) + 1; | |
236 | * | |
237 | * Since multiplication and division are commutative, we can reorder | |
238 | * operations into: | |
239 | * return ((size * 85) >> 20) + 1; | |
5c4654da AD |
240 | */ |
241 | static inline unsigned int i40e_txd_use_count(unsigned int size) | |
242 | { | |
4293d5f5 | 243 | return ((size * 85) >> 20) + 1; |
5c4654da | 244 | } |
7daa6bf3 JB |
245 | |
246 | /* Tx Descriptors needed, worst case */ | |
0a797db3 | 247 | #define DESC_NEEDED (MAX_SKB_FRAGS + 6) |
7daa6bf3 | 248 | |
41a1d04b JB |
249 | #define I40E_TX_FLAGS_HW_VLAN BIT(1) |
250 | #define I40E_TX_FLAGS_SW_VLAN BIT(2) | |
251 | #define I40E_TX_FLAGS_TSO BIT(3) | |
252 | #define I40E_TX_FLAGS_IPV4 BIT(4) | |
253 | #define I40E_TX_FLAGS_IPV6 BIT(5) | |
41a1d04b JB |
254 | #define I40E_TX_FLAGS_TSYN BIT(8) |
255 | #define I40E_TX_FLAGS_FD_SB BIT(9) | |
6a899024 | 256 | #define I40E_TX_FLAGS_UDP_TUNNEL BIT(10) |
7daa6bf3 JB |
257 | #define I40E_TX_FLAGS_VLAN_MASK 0xffff0000 |
258 | #define I40E_TX_FLAGS_VLAN_PRIO_MASK 0xe0000000 | |
259 | #define I40E_TX_FLAGS_VLAN_PRIO_SHIFT 29 | |
260 | #define I40E_TX_FLAGS_VLAN_SHIFT 16 | |
261 | ||
262 | struct i40e_tx_buffer { | |
7daa6bf3 | 263 | struct i40e_tx_desc *next_to_watch; |
49d7d933 | 264 | union { |
b411ef11 | 265 | struct xdp_frame *xdpf; |
49d7d933 ASJ |
266 | struct sk_buff *skb; |
267 | void *raw_buf; | |
268 | }; | |
7daa6bf3 | 269 | unsigned int bytecount; |
35a1e2ad | 270 | unsigned short gso_segs; |
6995b36c | 271 | |
35a1e2ad AD |
272 | DEFINE_DMA_UNMAP_ADDR(dma); |
273 | DEFINE_DMA_UNMAP_LEN(len); | |
274 | u32 tx_flags; | |
7daa6bf3 JB |
275 | }; |
276 | ||
277 | struct i40e_rx_buffer { | |
7daa6bf3 | 278 | dma_addr_t dma; |
be1222b5 BT |
279 | struct page *page; |
280 | __u32 page_offset; | |
281 | __u16 pagecnt_bias; | |
e2843f03 | 282 | __u32 page_count; |
be1222b5 BT |
283 | }; |
284 | ||
a114d0a6 | 285 | struct i40e_queue_stats { |
7daa6bf3 JB |
286 | u64 packets; |
287 | u64 bytes; | |
a114d0a6 AD |
288 | }; |
289 | ||
290 | struct i40e_tx_queue_stats { | |
7daa6bf3 JB |
291 | u64 restart_queue; |
292 | u64 tx_busy; | |
7daa6bf3 | 293 | u64 tx_done_old; |
2fc3d715 | 294 | u64 tx_linearize; |
164c9f54 | 295 | u64 tx_force_wb; |
f728fa01 | 296 | u64 tx_stopped; |
07d44190 | 297 | int prev_pkt_ctr; |
7daa6bf3 JB |
298 | }; |
299 | ||
300 | struct i40e_rx_queue_stats { | |
7daa6bf3 | 301 | u64 non_eop_descs; |
420136cc MW |
302 | u64 alloc_page_failed; |
303 | u64 alloc_buff_failed; | |
f16704e5 | 304 | u64 page_reuse_count; |
453f8305 | 305 | u64 page_alloc_count; |
cb963b98 | 306 | u64 page_waive_count; |
b76bc129 | 307 | u64 page_busy_count; |
7daa6bf3 JB |
308 | }; |
309 | ||
addca917 | 310 | enum i40e_ring_state { |
7daa6bf3 JB |
311 | __I40E_TX_FDIR_INIT_DONE, |
312 | __I40E_TX_XPS_INIT_DONE, | |
bd6cd4e6 | 313 | __I40E_RING_STATE_NBITS /* must be last */ |
7daa6bf3 JB |
314 | }; |
315 | ||
bec60fc4 JB |
316 | /* some useful defines for virtchannel interface, which |
317 | * is the only remaining user of header split | |
318 | */ | |
bec60fc4 | 319 | #define I40E_RX_DTYPE_HEADER_SPLIT 1 |
bec60fc4 JB |
320 | #define I40E_RX_SPLIT_L2 0x1 |
321 | #define I40E_RX_SPLIT_IP 0x2 | |
322 | #define I40E_RX_SPLIT_TCP_UDP 0x4 | |
323 | #define I40E_RX_SPLIT_SCTP 0x8 | |
7daa6bf3 JB |
324 | |
325 | /* struct that defines a descriptor ring, associated with a VSI */ | |
326 | struct i40e_ring { | |
cd0b6fa6 | 327 | struct i40e_ring *next; /* pointer to next ring in q_vector */ |
7daa6bf3 JB |
328 | void *desc; /* Descriptor ring memory */ |
329 | struct device *dev; /* Used for DMA mapping */ | |
330 | struct net_device *netdev; /* netdev ring maps to */ | |
0c8493d9 | 331 | struct bpf_prog *xdp_prog; |
7daa6bf3 JB |
332 | union { |
333 | struct i40e_tx_buffer *tx_bi; | |
334 | struct i40e_rx_buffer *rx_bi; | |
3b4f0b66 | 335 | struct xdp_buff **rx_bi_zc; |
7daa6bf3 | 336 | }; |
bd6cd4e6 | 337 | DECLARE_BITMAP(state, __I40E_RING_STATE_NBITS); |
7daa6bf3 JB |
338 | u16 queue_index; /* Queue number of ring */ |
339 | u8 dcb_tc; /* Traffic class of ring */ | |
340 | u8 __iomem *tail; | |
341 | ||
01aa49e3 TS |
342 | /* Storing xdp_buff on ring helps in saving the state of partially built |
343 | * packet when i40e_clean_rx_ring_irq() must return before it sees EOP | |
344 | * and to resume packet building for this ring in the next call to | |
345 | * i40e_clean_rx_ring_irq(). | |
346 | */ | |
347 | struct xdp_buff xdp; | |
348 | ||
e9031f2d TS |
349 | /* Next descriptor to be processed; next_to_clean is updated only on |
350 | * processing EOP descriptor | |
351 | */ | |
352 | u16 next_to_process; | |
a75e8005 KL |
353 | /* high bit set means dynamic, use accessor routines to read/write. |
354 | * hardware only supports 2us resolution for the ITR registers. | |
355 | * these values always store the USER setting, and must be converted | |
356 | * before programming to a register. | |
357 | */ | |
40588ca6 | 358 | u16 itr_setting; |
a75e8005 | 359 | |
7daa6bf3 JB |
360 | u16 count; /* Number of descriptors */ |
361 | u16 reg_idx; /* HW register index of the ring */ | |
7daa6bf3 | 362 | u16 rx_buf_len; |
7daa6bf3 JB |
363 | |
364 | /* used in interrupt processing */ | |
365 | u16 next_to_use; | |
366 | u16 next_to_clean; | |
5574ff7b | 367 | u16 xdp_tx_active; |
7daa6bf3 JB |
368 | |
369 | u8 atr_sample_rate; | |
370 | u8 atr_count; | |
371 | ||
372 | bool ring_active; /* is ring online or not */ | |
d91649f5 | 373 | bool arm_wb; /* do something to arm write back */ |
58044743 | 374 | u8 packet_stride; |
7daa6bf3 | 375 | |
8e0764b4 | 376 | u16 flags; |
ca9ec088 AD |
377 | #define I40E_TXR_FLAGS_WB_ON_ITR BIT(0) |
378 | #define I40E_RXR_FLAGS_BUILD_SKB_ENABLED BIT(1) | |
74608d17 | 379 | #define I40E_TXR_FLAGS_XDP BIT(2) |
527274c7 | 380 | |
7daa6bf3 | 381 | /* stats structs */ |
a114d0a6 | 382 | struct i40e_queue_stats stats; |
980e9b11 | 383 | struct u64_stats_sync syncp; |
7daa6bf3 JB |
384 | union { |
385 | struct i40e_tx_queue_stats tx_stats; | |
386 | struct i40e_rx_queue_stats rx_stats; | |
387 | }; | |
388 | ||
389 | unsigned int size; /* length of descriptor ring in bytes */ | |
390 | dma_addr_t dma; /* physical address of ring */ | |
391 | ||
392 | struct i40e_vsi *vsi; /* Backreference to associated VSI */ | |
393 | struct i40e_q_vector *q_vector; /* Backreference to associated vector */ | |
9f65e15b AD |
394 | |
395 | struct rcu_head rcu; /* to avoid race on free */ | |
1a557afc | 396 | u16 next_to_alloc; |
8f88b303 AN |
397 | |
398 | struct i40e_channel *ch; | |
f7bb0d71 | 399 | u16 rx_offset; |
87128824 | 400 | struct xdp_rxq_info xdp_rxq; |
1742b3d5 | 401 | struct xsk_buff_pool *xsk_pool; |
7daa6bf3 JB |
402 | } ____cacheline_internodealigned_in_smp; |
403 | ||
ca9ec088 AD |
404 | static inline bool ring_uses_build_skb(struct i40e_ring *ring) |
405 | { | |
406 | return !!(ring->flags & I40E_RXR_FLAGS_BUILD_SKB_ENABLED); | |
407 | } | |
408 | ||
409 | static inline void set_ring_build_skb_enabled(struct i40e_ring *ring) | |
410 | { | |
411 | ring->flags |= I40E_RXR_FLAGS_BUILD_SKB_ENABLED; | |
412 | } | |
413 | ||
414 | static inline void clear_ring_build_skb_enabled(struct i40e_ring *ring) | |
415 | { | |
416 | ring->flags &= ~I40E_RXR_FLAGS_BUILD_SKB_ENABLED; | |
417 | } | |
418 | ||
74608d17 BT |
419 | static inline bool ring_is_xdp(struct i40e_ring *ring) |
420 | { | |
421 | return !!(ring->flags & I40E_TXR_FLAGS_XDP); | |
422 | } | |
423 | ||
424 | static inline void set_ring_xdp(struct i40e_ring *ring) | |
425 | { | |
426 | ring->flags |= I40E_TXR_FLAGS_XDP; | |
427 | } | |
428 | ||
a0073a4b AD |
429 | #define I40E_ITR_ADAPTIVE_MIN_INC 0x0002 |
430 | #define I40E_ITR_ADAPTIVE_MIN_USECS 0x0002 | |
431 | #define I40E_ITR_ADAPTIVE_MAX_USECS 0x007e | |
432 | #define I40E_ITR_ADAPTIVE_LATENCY 0x8000 | |
433 | #define I40E_ITR_ADAPTIVE_BULK 0x0000 | |
7daa6bf3 JB |
434 | |
435 | struct i40e_ring_container { | |
a0073a4b AD |
436 | struct i40e_ring *ring; /* pointer to linked list of ring(s) */ |
437 | unsigned long next_update; /* jiffies value of next update */ | |
7daa6bf3 JB |
438 | unsigned int total_bytes; /* total bytes processed this int */ |
439 | unsigned int total_packets; /* total packets processed this int */ | |
440 | u16 count; | |
556fdfd6 AD |
441 | u16 target_itr; /* target ITR setting for ring(s) */ |
442 | u16 current_itr; /* current ITR setting for ring(s) */ | |
7daa6bf3 JB |
443 | }; |
444 | ||
cd0b6fa6 AD |
445 | /* iterator for handling rings in ring container */ |
446 | #define i40e_for_each_ring(pos, head) \ | |
447 | for (pos = (head).ring; pos != NULL; pos = pos->next) | |
448 | ||
98efd694 AD |
449 | static inline unsigned int i40e_rx_pg_order(struct i40e_ring *ring) |
450 | { | |
451 | #if (PAGE_SIZE < 8192) | |
452 | if (ring->rx_buf_len > (PAGE_SIZE / 2)) | |
453 | return 1; | |
454 | #endif | |
455 | return 0; | |
456 | } | |
457 | ||
458 | #define i40e_rx_pg_size(_ring) (PAGE_SIZE << i40e_rx_pg_order(_ring)) | |
459 | ||
1a557afc | 460 | bool i40e_alloc_rx_buffers(struct i40e_ring *rxr, u16 cleaned_count); |
7daa6bf3 | 461 | netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev); |
89ec1f08 JJ |
462 | u16 i40e_lan_select_queue(struct net_device *netdev, struct sk_buff *skb, |
463 | struct net_device *sb_dev); | |
7daa6bf3 JB |
464 | void i40e_clean_tx_ring(struct i40e_ring *tx_ring); |
465 | void i40e_clean_rx_ring(struct i40e_ring *rx_ring); | |
466 | int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring); | |
467 | int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring); | |
468 | void i40e_free_tx_resources(struct i40e_ring *tx_ring); | |
469 | void i40e_free_rx_resources(struct i40e_ring *rx_ring); | |
470 | int i40e_napi_poll(struct napi_struct *napi, int budget); | |
b03a8c1f | 471 | void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector); |
04d41051 | 472 | u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw); |
07d44190 | 473 | void i40e_detect_recover_hung(struct i40e_vsi *vsi); |
4ec441df | 474 | int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size); |
2d37490b | 475 | bool __i40e_chk_linearize(struct sk_buff *skb); |
42b33468 JDB |
476 | int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames, |
477 | u32 flags); | |
1c9ba9c1 TS |
478 | bool i40e_is_non_eop(struct i40e_ring *rx_ring, |
479 | union i40e_rx_desc *rx_desc); | |
1e6d6f8c KP |
480 | |
481 | /** | |
482 | * i40e_get_head - Retrieve head from head writeback | |
483 | * @tx_ring: tx ring to fetch head of | |
484 | * | |
485 | * Returns value of Tx ring head based on value stored | |
486 | * in head write-back location | |
487 | **/ | |
488 | static inline u32 i40e_get_head(struct i40e_ring *tx_ring) | |
489 | { | |
490 | void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count; | |
491 | ||
492 | return le32_to_cpu(*(volatile __le32 *)head); | |
493 | } | |
4ec441df AD |
494 | |
495 | /** | |
496 | * i40e_xmit_descriptor_count - calculate number of Tx descriptors needed | |
497 | * @skb: send buffer | |
4ec441df AD |
498 | * |
499 | * Returns number of data descriptors needed for this skb. Returns 0 to indicate | |
500 | * there is not enough descriptors available in this ring since we need at least | |
501 | * one descriptor. | |
502 | **/ | |
503 | static inline int i40e_xmit_descriptor_count(struct sk_buff *skb) | |
504 | { | |
d7840976 | 505 | const skb_frag_t *frag = &skb_shinfo(skb)->frags[0]; |
4ec441df AD |
506 | unsigned int nr_frags = skb_shinfo(skb)->nr_frags; |
507 | int count = 0, size = skb_headlen(skb); | |
508 | ||
509 | for (;;) { | |
5c4654da | 510 | count += i40e_txd_use_count(size); |
4ec441df AD |
511 | |
512 | if (!nr_frags--) | |
513 | break; | |
514 | ||
515 | size = skb_frag_size(frag++); | |
516 | } | |
517 | ||
518 | return count; | |
519 | } | |
520 | ||
521 | /** | |
522 | * i40e_maybe_stop_tx - 1st level check for Tx stop conditions | |
523 | * @tx_ring: the ring to be checked | |
524 | * @size: the size buffer we want to assure is available | |
525 | * | |
526 | * Returns 0 if stop is not needed | |
527 | **/ | |
528 | static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size) | |
529 | { | |
530 | if (likely(I40E_DESC_UNUSED(tx_ring) >= size)) | |
531 | return 0; | |
532 | return __i40e_maybe_stop_tx(tx_ring, size); | |
533 | } | |
2d37490b AD |
534 | |
535 | /** | |
536 | * i40e_chk_linearize - Check if there are more than 8 fragments per packet | |
537 | * @skb: send buffer | |
538 | * @count: number of buffers used | |
539 | * | |
540 | * Note: Our HW can't scatter-gather more than 8 fragments to build | |
541 | * a packet on the wire and so we need to figure out the cases where we | |
542 | * need to linearize the skb. | |
543 | **/ | |
544 | static inline bool i40e_chk_linearize(struct sk_buff *skb, int count) | |
545 | { | |
3f3f7cb8 AD |
546 | /* Both TSO and single send will work if count is less than 8 */ |
547 | if (likely(count < I40E_MAX_BUFFER_TXD)) | |
2d37490b AD |
548 | return false; |
549 | ||
3f3f7cb8 AD |
550 | if (skb_is_gso(skb)) |
551 | return __i40e_chk_linearize(skb); | |
552 | ||
553 | /* we can support up to 8 data buffers for a single send */ | |
554 | return count != I40E_MAX_BUFFER_TXD; | |
2d37490b | 555 | } |
1f15d667 | 556 | |
e486bdfd AD |
557 | /** |
558 | * txring_txq - Find the netdev Tx ring based on the i40e Tx ring | |
559 | * @ring: Tx ring to find the netdev equivalent of | |
560 | **/ | |
561 | static inline struct netdev_queue *txring_txq(const struct i40e_ring *ring) | |
562 | { | |
563 | return netdev_get_tx_queue(ring->netdev, ring->queue_index); | |
564 | } | |
36fac581 | 565 | #endif /* _I40E_TXRX_H_ */ |