projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i40e: Detection and recovery of TX queue hung logic moved to service_task from tx_timeout
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_txrx.c
CommitLineData
fd0a05ce
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
fd0a05ce
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
fd0a05ce
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
1c112a64 27#include <linux/prefetch.h>
a132af24 28#include <net/busy_poll.h>
fd0a05ce 29#include "i40e.h"
206812b5 30#include "i40e_prototype.h"
fd0a05ce
JB		 31
32static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
33 u32 td_tag)
34{
35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
40}
41
eaefbd06 42#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
49d7d933 43#define I40E_FD_CLEAN_DELAY 10
fd0a05ce
JB		 44/**
45 * i40e_program_fdir_filter - Program a Flow Director filter
17a73f6b
JG		 46 * @fdir_data: Packet data that will be filter parameters
47 * @raw_packet: the pre-allocated packet buffer for FDir
b40c82e6 48 * @pf: The PF pointer
fd0a05ce
JB		 49 * @add: True for add/update, False for remove
50 **/
17a73f6b 51int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
fd0a05ce
JB		 52 struct i40e_pf *pf, bool add)
53{
54 struct i40e_filter_program_desc *fdir_desc;
49d7d933 55 struct i40e_tx_buffer *tx_buf, *first;
fd0a05ce
JB		 56 struct i40e_tx_desc *tx_desc;
57 struct i40e_ring *tx_ring;
eaefbd06 58 unsigned int fpt, dcc;
fd0a05ce
JB		 59 struct i40e_vsi *vsi;
60 struct device *dev;
61 dma_addr_t dma;
62 u32 td_cmd = 0;
49d7d933 63 u16 delay = 0;
fd0a05ce
JB		 64 u16 i;
65
66 /* find existing FDIR VSI */
67 vsi = NULL;
505682cd 68 for (i = 0; i < pf->num_alloc_vsi; i++)
fd0a05ce
JB		 69 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
70 vsi = pf->vsi[i];
71 if (!vsi)
72 return -ENOENT;
73
9f65e15b 74 tx_ring = vsi->tx_rings[0];
fd0a05ce
JB		 75 dev = tx_ring->dev;
76
49d7d933
ASJ		 77 /* we need two descriptors to add/del a filter and we can wait */
78 do {
79 if (I40E_DESC_UNUSED(tx_ring) > 1)
80 break;
81 msleep_interruptible(1);
82 delay++;
83 } while (delay < I40E_FD_CLEAN_DELAY);
84
85 if (!(I40E_DESC_UNUSED(tx_ring) > 1))
86 return -EAGAIN;
87
17a73f6b
JG		 88 dma = dma_map_single(dev, raw_packet,
89 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
fd0a05ce
JB		 90 if (dma_mapping_error(dev, dma))
91 goto dma_fail;
92
93 /* grab the next descriptor */
fc4ac67b
AD		 94 i = tx_ring->next_to_use;
95 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
49d7d933
ASJ		 96 first = &tx_ring->tx_bi[i];
97 memset(first, 0, sizeof(struct i40e_tx_buffer));
fc4ac67b 98
49d7d933 99 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
fd0a05ce 100
eaefbd06
JB		 101 fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
102 I40E_TXD_FLTR_QW0_QINDEX_MASK;
fd0a05ce 103
eaefbd06
JB		 104 fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
105 I40E_TXD_FLTR_QW0_FLEXOFF_MASK;
fd0a05ce 106
eaefbd06
JB		 107 fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
108 I40E_TXD_FLTR_QW0_PCTYPE_MASK;
fd0a05ce
JB		 109
110 /* Use LAN VSI Id if not programmed by user */
111 if (fdir_data->dest_vsi == 0)
eaefbd06
JB		 112 fpt |= (pf->vsi[pf->lan_vsi]->id) <<
113 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
fd0a05ce 114 else
eaefbd06
JB		 115 fpt |= ((u32)fdir_data->dest_vsi <<
116 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
117 I40E_TXD_FLTR_QW0_DEST_VSI_MASK;
118
eaefbd06 119 dcc = I40E_TX_DESC_DTYPE_FILTER_PROG;
fd0a05ce
JB		 120
121 if (add)
eaefbd06
JB		 122 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
123 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
fd0a05ce 124 else
eaefbd06
JB		 125 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
126 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
fd0a05ce 127
eaefbd06
JB		 128 dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) &
129 I40E_TXD_FLTR_QW1_DEST_MASK;
fd0a05ce 130
eaefbd06
JB		 131 dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
132 I40E_TXD_FLTR_QW1_FD_STATUS_MASK;
fd0a05ce
JB		 133
134 if (fdir_data->cnt_index != 0) {
eaefbd06
JB		 135 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
136 dcc |= ((u32)fdir_data->cnt_index <<
137 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
433c47de 138 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
fd0a05ce
JB		 139 }
140
99753ea6
JB		 141 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt);
142 fdir_desc->rsvd = cpu_to_le32(0);
eaefbd06 143 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc);
fd0a05ce
JB		 144 fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id);
145
146 /* Now program a dummy descriptor */
fc4ac67b
AD		 147 i = tx_ring->next_to_use;
148 tx_desc = I40E_TX_DESC(tx_ring, i);
298deef1 149 tx_buf = &tx_ring->tx_bi[i];
fc4ac67b 150
49d7d933
ASJ		 151 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
152
153 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
fd0a05ce 154
298deef1 155 /* record length, and DMA address */
17a73f6b 156 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
298deef1
ASJ		 157 dma_unmap_addr_set(tx_buf, dma, dma);
158
fd0a05ce 159 tx_desc->buffer_addr = cpu_to_le64(dma);
eaefbd06 160 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
fd0a05ce 161
49d7d933
ASJ		 162 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
163 tx_buf->raw_buf = (void *)raw_packet;
164
fd0a05ce 165 tx_desc->cmd_type_offset_bsz =
17a73f6b 166 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
fd0a05ce 167
fd0a05ce 168 /* Force memory writes to complete before letting h/w
49d7d933 169 * know there are new descriptors to fetch.
fd0a05ce
JB		 170 */
171 wmb();
172
fc4ac67b 173 /* Mark the data descriptor to be watched */
49d7d933 174 first->next_to_watch = tx_desc;
fc4ac67b 175
fd0a05ce
JB		 176 writel(tx_ring->next_to_use, tx_ring->tail);
177 return 0;
178
179dma_fail:
180 return -1;
181}
182
17a73f6b
JG		 183#define IP_HEADER_OFFSET 14
184#define I40E_UDPIP_DUMMY_PACKET_LEN 42
185/**
186 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
187 * @vsi: pointer to the targeted VSI
188 * @fd_data: the flow director data required for the FDir descriptor
17a73f6b
JG		 189 * @add: true adds a filter, false removes it
190 *
191 * Returns 0 if the filters were successfully added or removed
192 **/
193static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
194 struct i40e_fdir_filter *fd_data,
49d7d933 195 bool add)
17a73f6b
JG		 196{
197 struct i40e_pf *pf = vsi->back;
198 struct udphdr *udp;
199 struct iphdr *ip;
200 bool err = false;
49d7d933 201 u8 *raw_packet;
17a73f6b 202 int ret;
17a73f6b
JG		 203 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
204 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
206
49d7d933
ASJ		 207 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
208 if (!raw_packet)
209 return -ENOMEM;
17a73f6b
JG		 210 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
211
212 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
213 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
214 + sizeof(struct iphdr));
215
216 ip->daddr = fd_data->dst_ip[0];
217 udp->dest = fd_data->dst_port;
218 ip->saddr = fd_data->src_ip[0];
219 udp->source = fd_data->src_port;
220
b2d36c03
KS		 221 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
222 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
223 if (ret) {
224 dev_info(&pf->pdev->dev,
e99bdd39
CW		 225 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
226 fd_data->pctype, fd_data->fd_id, ret);
b2d36c03 227 err = true;
4205d379 228 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
f7233c54
ASJ		 229 if (add)
230 dev_info(&pf->pdev->dev,
231 "Filter OK for PCTYPE %d loc = %d\n",
232 fd_data->pctype, fd_data->fd_id);
233 else
234 dev_info(&pf->pdev->dev,
235 "Filter deleted for PCTYPE %d loc = %d\n",
236 fd_data->pctype, fd_data->fd_id);
17a73f6b 237 }
17a73f6b
JG		 238 return err ? -EOPNOTSUPP : 0;
239}
240
241#define I40E_TCPIP_DUMMY_PACKET_LEN 54
242/**
243 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
244 * @vsi: pointer to the targeted VSI
245 * @fd_data: the flow director data required for the FDir descriptor
17a73f6b
JG		 246 * @add: true adds a filter, false removes it
247 *
248 * Returns 0 if the filters were successfully added or removed
249 **/
250static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
251 struct i40e_fdir_filter *fd_data,
49d7d933 252 bool add)
17a73f6b
JG		 253{
254 struct i40e_pf *pf = vsi->back;
255 struct tcphdr *tcp;
256 struct iphdr *ip;
257 bool err = false;
49d7d933 258 u8 *raw_packet;
17a73f6b
JG		 259 int ret;
260 /* Dummy packet */
261 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
262 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
264 0x0, 0x72, 0, 0, 0, 0};
265
49d7d933
ASJ		 266 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
267 if (!raw_packet)
268 return -ENOMEM;
17a73f6b
JG		 269 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
270
271 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
272 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
273 + sizeof(struct iphdr));
274
275 ip->daddr = fd_data->dst_ip[0];
276 tcp->dest = fd_data->dst_port;
277 ip->saddr = fd_data->src_ip[0];
278 tcp->source = fd_data->src_port;
279
280 if (add) {
1e1be8f6 281 pf->fd_tcp_rule++;
17a73f6b 282 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) {
2e4875e3
ASJ		 283 if (I40E_DEBUG_FD & pf->hw.debug_mask)
284 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
17a73f6b
JG		 285 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
286 }
1e1be8f6
ASJ		 287 } else {
288 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ?
289 (pf->fd_tcp_rule - 1) : 0;
290 if (pf->fd_tcp_rule == 0) {
291 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 292 if (I40E_DEBUG_FD & pf->hw.debug_mask)
293 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n");
1e1be8f6 294 }
17a73f6b
JG		 295 }
296
b2d36c03 297 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
17a73f6b
JG		 298 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
299
300 if (ret) {
301 dev_info(&pf->pdev->dev,
e99bdd39
CW		 302 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
303 fd_data->pctype, fd_data->fd_id, ret);
17a73f6b 304 err = true;
4205d379 305 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
f7233c54
ASJ		 306 if (add)
307 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
308 fd_data->pctype, fd_data->fd_id);
309 else
310 dev_info(&pf->pdev->dev,
311 "Filter deleted for PCTYPE %d loc = %d\n",
312 fd_data->pctype, fd_data->fd_id);
17a73f6b
JG		 313 }
314
17a73f6b
JG		 315 return err ? -EOPNOTSUPP : 0;
316}
317
318/**
319 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
320 * a specific flow spec
321 * @vsi: pointer to the targeted VSI
322 * @fd_data: the flow director data required for the FDir descriptor
17a73f6b
JG		 323 * @add: true adds a filter, false removes it
324 *
21d3efdc 325 * Always returns -EOPNOTSUPP
17a73f6b
JG		 326 **/
327static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
328 struct i40e_fdir_filter *fd_data,
49d7d933 329 bool add)
17a73f6b
JG		 330{
331 return -EOPNOTSUPP;
332}
333
334#define I40E_IP_DUMMY_PACKET_LEN 34
335/**
336 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
337 * a specific flow spec
338 * @vsi: pointer to the targeted VSI
339 * @fd_data: the flow director data required for the FDir descriptor
17a73f6b
JG		 340 * @add: true adds a filter, false removes it
341 *
342 * Returns 0 if the filters were successfully added or removed
343 **/
344static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
345 struct i40e_fdir_filter *fd_data,
49d7d933 346 bool add)
17a73f6b
JG		 347{
348 struct i40e_pf *pf = vsi->back;
349 struct iphdr *ip;
350 bool err = false;
49d7d933 351 u8 *raw_packet;
17a73f6b
JG		 352 int ret;
353 int i;
354 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
355 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
356 0, 0, 0, 0};
357
17a73f6b
JG		 358 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
359 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
49d7d933
ASJ		 360 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
361 if (!raw_packet)
362 return -ENOMEM;
363 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
364 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
365
366 ip->saddr = fd_data->src_ip[0];
367 ip->daddr = fd_data->dst_ip[0];
368 ip->protocol = 0;
369
17a73f6b
JG		 370 fd_data->pctype = i;
371 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
372
373 if (ret) {
374 dev_info(&pf->pdev->dev,
e99bdd39
CW		 375 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
376 fd_data->pctype, fd_data->fd_id, ret);
17a73f6b 377 err = true;
4205d379 378 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
f7233c54
ASJ		 379 if (add)
380 dev_info(&pf->pdev->dev,
381 "Filter OK for PCTYPE %d loc = %d\n",
382 fd_data->pctype, fd_data->fd_id);
383 else
384 dev_info(&pf->pdev->dev,
385 "Filter deleted for PCTYPE %d loc = %d\n",
386 fd_data->pctype, fd_data->fd_id);
17a73f6b
JG		 387 }
388 }
389
390 return err ? -EOPNOTSUPP : 0;
391}
392
393/**
394 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
395 * @vsi: pointer to the targeted VSI
396 * @cmd: command to get or set RX flow classification rules
397 * @add: true adds a filter, false removes it
398 *
399 **/
400int i40e_add_del_fdir(struct i40e_vsi *vsi,
401 struct i40e_fdir_filter *input, bool add)
402{
403 struct i40e_pf *pf = vsi->back;
17a73f6b
JG		 404 int ret;
405
17a73f6b
JG		 406 switch (input->flow_type & ~FLOW_EXT) {
407 case TCP_V4_FLOW:
49d7d933 408 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
17a73f6b
JG		 409 break;
410 case UDP_V4_FLOW:
49d7d933 411 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
17a73f6b
JG		 412 break;
413 case SCTP_V4_FLOW:
49d7d933 414 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
17a73f6b
JG		 415 break;
416 case IPV4_FLOW:
49d7d933 417 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
17a73f6b
JG		 418 break;
419 case IP_USER_FLOW:
420 switch (input->ip4_proto) {
421 case IPPROTO_TCP:
49d7d933 422 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
17a73f6b
JG		 423 break;
424 case IPPROTO_UDP:
49d7d933 425 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
17a73f6b
JG		 426 break;
427 case IPPROTO_SCTP:
49d7d933 428 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
17a73f6b
JG		 429 break;
430 default:
49d7d933 431 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
17a73f6b
JG		 432 break;
433 }
434 break;
435 default:
c5ffe7e1 436 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n",
17a73f6b
JG		 437 input->flow_type);
438 ret = -EINVAL;
439 }
440
49d7d933 441 /* The buffer allocated here is freed by the i40e_clean_tx_ring() */
17a73f6b
JG		 442 return ret;
443}
444
fd0a05ce
JB		 445/**
446 * i40e_fd_handle_status - check the Programming Status for FD
447 * @rx_ring: the Rx ring for this descriptor
55a5e60b 448 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
fd0a05ce
JB		 449 * @prog_id: the id originally used for programming
450 *
451 * This is used to verify if the FD programming or invalidation
452 * requested by SW to the HW is successful or not and take actions accordingly.
453 **/
55a5e60b
ASJ		 454static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
455 union i40e_rx_desc *rx_desc, u8 prog_id)
fd0a05ce 456{
55a5e60b
ASJ		 457 struct i40e_pf *pf = rx_ring->vsi->back;
458 struct pci_dev *pdev = pf->pdev;
459 u32 fcnt_prog, fcnt_avail;
fd0a05ce 460 u32 error;
55a5e60b 461 u64 qw;
fd0a05ce 462
55a5e60b 463 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
fd0a05ce
JB		 464 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
465 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
466
41a1d04b 467 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
3487b6c3 468 pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id);
f7233c54
ASJ		 469 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
470 (I40E_DEBUG_FD & pf->hw.debug_mask))
471 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
3487b6c3 472 pf->fd_inv);
55a5e60b 473
04294e38
ASJ		 474 /* Check if the programming error is for ATR.
475 * If so, auto disable ATR and set a state for
476 * flush in progress. Next time we come here if flush is in
477 * progress do nothing, once flush is complete the state will
478 * be cleared.
479 */
480 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
481 return;
482
1e1be8f6
ASJ		 483 pf->fd_add_err++;
484 /* store the current atr filter count */
485 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
486
04294e38
ASJ		 487 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) &&
488 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
489 pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED;
490 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
491 }
492
55a5e60b 493 /* filter programming failed most likely due to table full */
04294e38 494 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 495 fcnt_avail = pf->fdir_pf_filter_count;
55a5e60b
ASJ		 496 /* If ATR is running fcnt_prog can quickly change,
497 * if we are very close to full, it makes sense to disable
498 * FD ATR/SB and then re-enable it when there is room.
499 */
500 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
1e1be8f6 501 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
b814ba65 502 !(pf->auto_disable_flags &
b814ba65 503 I40E_FLAG_FD_SB_ENABLED)) {
2e4875e3
ASJ		 504 if (I40E_DEBUG_FD & pf->hw.debug_mask)
505 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
55a5e60b
ASJ		 506 pf->auto_disable_flags |=
507 I40E_FLAG_FD_SB_ENABLED;
55a5e60b
ASJ		 508 }
509 } else {
e99bdd39 510 dev_info(&pdev->dev,
f7233c54 511 "FD filter programming failed due to incorrect filter parameters\n");
55a5e60b 512 }
41a1d04b 513 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
13c2884f 514 if (I40E_DEBUG_FD & pf->hw.debug_mask)
e99bdd39 515 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
13c2884f 516 rx_desc->wb.qword0.hi_dword.fd_id);
55a5e60b 517 }
fd0a05ce
JB		 518}
519
520/**
a5e9c572 521 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
fd0a05ce
JB		 522 * @ring: the ring that owns the buffer
523 * @tx_buffer: the buffer to free
524 **/
a5e9c572
AD		 525static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
526 struct i40e_tx_buffer *tx_buffer)
fd0a05ce 527{
a5e9c572 528 if (tx_buffer->skb) {
49d7d933
ASJ		 529 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
530 kfree(tx_buffer->raw_buf);
531 else
532 dev_kfree_skb_any(tx_buffer->skb);
533
a5e9c572 534 if (dma_unmap_len(tx_buffer, len))
fd0a05ce 535 dma_unmap_single(ring->dev,
35a1e2ad
AD		 536 dma_unmap_addr(tx_buffer, dma),
537 dma_unmap_len(tx_buffer, len),
fd0a05ce 538 DMA_TO_DEVICE);
a5e9c572
AD		 539 } else if (dma_unmap_len(tx_buffer, len)) {
540 dma_unmap_page(ring->dev,
541 dma_unmap_addr(tx_buffer, dma),
542 dma_unmap_len(tx_buffer, len),
543 DMA_TO_DEVICE);
fd0a05ce 544 }
a5e9c572
AD		 545 tx_buffer->next_to_watch = NULL;
546 tx_buffer->skb = NULL;
35a1e2ad 547 dma_unmap_len_set(tx_buffer, len, 0);
a5e9c572 548 /* tx_buffer must be completely set up in the transmit path */
fd0a05ce
JB		 549}
550
551/**
552 * i40e_clean_tx_ring - Free any empty Tx buffers
553 * @tx_ring: ring to be cleaned
554 **/
555void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
556{
fd0a05ce
JB		 557 unsigned long bi_size;
558 u16 i;
559
560 /* ring already cleared, nothing to do */
561 if (!tx_ring->tx_bi)
562 return;
563
564 /* Free all the Tx ring sk_buffs */
a5e9c572
AD		 565 for (i = 0; i < tx_ring->count; i++)
566 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
fd0a05ce
JB		 567
568 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
569 memset(tx_ring->tx_bi, 0, bi_size);
570
571 /* Zero out the descriptor ring */
572 memset(tx_ring->desc, 0, tx_ring->size);
573
574 tx_ring->next_to_use = 0;
575 tx_ring->next_to_clean = 0;
7070ce0a
AD		 576
577 if (!tx_ring->netdev)
578 return;
579
580 /* cleanup Tx queue statistics */
581 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
582 tx_ring->queue_index));
fd0a05ce
JB		 583}
584
585/**
586 * i40e_free_tx_resources - Free Tx resources per queue
587 * @tx_ring: Tx descriptor ring for a specific queue
588 *
589 * Free all transmit software resources
590 **/
591void i40e_free_tx_resources(struct i40e_ring *tx_ring)
592{
593 i40e_clean_tx_ring(tx_ring);
594 kfree(tx_ring->tx_bi);
595 tx_ring->tx_bi = NULL;
596
597 if (tx_ring->desc) {
598 dma_free_coherent(tx_ring->dev, tx_ring->size,
599 tx_ring->desc, tx_ring->dma);
600 tx_ring->desc = NULL;
601 }
602}
603
604/**
605 * i40e_get_tx_pending - how many tx descriptors not processed
606 * @tx_ring: the ring of descriptors
607 *
608 * Since there is no access to the ring head register
609 * in XL710, we need to use our local copies
610 **/
b03a8c1f 611u32 i40e_get_tx_pending(struct i40e_ring *ring)
fd0a05ce 612{
a68de58d
JB		 613 u32 head, tail;
614
615 head = i40e_get_head(ring);
616 tail = readl(ring->tail);
617
618 if (head != tail)
619 return (head < tail) ?
620 tail - head : (tail + ring->count - head);
621
622 return 0;
fd0a05ce
JB		 623}
624
d91649f5
JB		 625#define WB_STRIDE 0x3
626
fd0a05ce
JB		 627/**
628 * i40e_clean_tx_irq - Reclaim resources after transmit completes
629 * @tx_ring: tx ring to clean
630 * @budget: how many cleans we're allowed
631 *
632 * Returns true if there's any budget left (e.g. the clean is finished)
633 **/
634static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
635{
636 u16 i = tx_ring->next_to_clean;
637 struct i40e_tx_buffer *tx_buf;
1943d8ba 638 struct i40e_tx_desc *tx_head;
fd0a05ce
JB		 639 struct i40e_tx_desc *tx_desc;
640 unsigned int total_packets = 0;
641 unsigned int total_bytes = 0;
642
643 tx_buf = &tx_ring->tx_bi[i];
644 tx_desc = I40E_TX_DESC(tx_ring, i);
a5e9c572 645 i -= tx_ring->count;
fd0a05ce 646
1943d8ba
JB		 647 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
648
a5e9c572
AD		 649 do {
650 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
fd0a05ce
JB		 651
652 /* if next_to_watch is not set then there is no work pending */
653 if (!eop_desc)
654 break;
655
a5e9c572
AD		 656 /* prevent any other reads prior to eop_desc */
657 read_barrier_depends();
658
1943d8ba
JB		 659 /* we have caught up to head, no work left to do */
660 if (tx_head == tx_desc)
fd0a05ce
JB		 661 break;
662
c304fdac 663 /* clear next_to_watch to prevent false hangs */
fd0a05ce 664 tx_buf->next_to_watch = NULL;
fd0a05ce 665
a5e9c572
AD		 666 /* update the statistics for this packet */
667 total_bytes += tx_buf->bytecount;
668 total_packets += tx_buf->gso_segs;
fd0a05ce 669
a5e9c572 670 /* free the skb */
a81fb049 671 dev_consume_skb_any(tx_buf->skb);
fd0a05ce 672
a5e9c572
AD		 673 /* unmap skb header data */
674 dma_unmap_single(tx_ring->dev,
675 dma_unmap_addr(tx_buf, dma),
676 dma_unmap_len(tx_buf, len),
677 DMA_TO_DEVICE);
fd0a05ce 678
a5e9c572
AD		 679 /* clear tx_buffer data */
680 tx_buf->skb = NULL;
681 dma_unmap_len_set(tx_buf, len, 0);
fd0a05ce 682
a5e9c572
AD		 683 /* unmap remaining buffers */
684 while (tx_desc != eop_desc) {
fd0a05ce
JB		 685
686 tx_buf++;
687 tx_desc++;
688 i++;
a5e9c572
AD		 689 if (unlikely(!i)) {
690 i -= tx_ring->count;
fd0a05ce
JB		 691 tx_buf = tx_ring->tx_bi;
692 tx_desc = I40E_TX_DESC(tx_ring, 0);
693 }
fd0a05ce 694
a5e9c572
AD		 695 /* unmap any remaining paged data */
696 if (dma_unmap_len(tx_buf, len)) {
697 dma_unmap_page(tx_ring->dev,
698 dma_unmap_addr(tx_buf, dma),
699 dma_unmap_len(tx_buf, len),
700 DMA_TO_DEVICE);
701 dma_unmap_len_set(tx_buf, len, 0);
702 }
703 }
704
705 /* move us one more past the eop_desc for start of next pkt */
706 tx_buf++;
707 tx_desc++;
708 i++;
709 if (unlikely(!i)) {
710 i -= tx_ring->count;
711 tx_buf = tx_ring->tx_bi;
712 tx_desc = I40E_TX_DESC(tx_ring, 0);
713 }
714
016890b9
JB		 715 prefetch(tx_desc);
716
a5e9c572
AD		 717 /* update budget accounting */
718 budget--;
719 } while (likely(budget));
720
721 i += tx_ring->count;
fd0a05ce 722 tx_ring->next_to_clean = i;
980e9b11 723 u64_stats_update_begin(&tx_ring->syncp);
a114d0a6
AD		 724 tx_ring->stats.bytes += total_bytes;
725 tx_ring->stats.packets += total_packets;
980e9b11 726 u64_stats_update_end(&tx_ring->syncp);
fd0a05ce
JB		 727 tx_ring->q_vector->tx.total_bytes += total_bytes;
728 tx_ring->q_vector->tx.total_packets += total_packets;
a5e9c572 729
58044743
AS		 730 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
731 unsigned int j = 0;
732
733 /* check to see if there are < 4 descriptors
734 * waiting to be written back, then kick the hardware to force
735 * them to be written back in case we stay in NAPI.
736 * In this mode on X722 we do not enable Interrupt.
737 */
738 j = i40e_get_tx_pending(tx_ring);
739
740 if (budget &&
741 ((j / (WB_STRIDE + 1)) == 0) && (j != 0) &&
742 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
743 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
744 tx_ring->arm_wb = true;
745 }
d91649f5 746
7070ce0a
AD		 747 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
748 tx_ring->queue_index),
749 total_packets, total_bytes);
750
fd0a05ce
JB		 751#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
752 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
753 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
754 /* Make sure that anybody stopping the queue after this
755 * sees the new next_to_clean.
756 */
757 smp_mb();
758 if (__netif_subqueue_stopped(tx_ring->netdev,
759 tx_ring->queue_index) &&
760 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
761 netif_wake_subqueue(tx_ring->netdev,
762 tx_ring->queue_index);
763 ++tx_ring->tx_stats.restart_queue;
764 }
765 }
766
d91649f5
JB		 767 return !!budget;
768}
769
770/**
771 * i40e_force_wb - Arm hardware to do a wb on noncache aligned descriptors
772 * @vsi: the VSI we care about
773 * @q_vector: the vector on which to force writeback
774 *
775 **/
b03a8c1f 776void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
d91649f5 777{
8e0764b4
ASJ		 778 u16 flags = q_vector->tx.ring[0].flags;
779
780 if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
781 u32 val;
782
783 if (q_vector->arm_wb_state)
784 return;
785
786 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK;
787
788 wr32(&vsi->back->hw,
789 I40E_PFINT_DYN_CTLN(q_vector->v_idx +
790 vsi->base_vector - 1),
791 val);
792 q_vector->arm_wb_state = true;
793 } else if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
794 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
795 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
796 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
797 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
798 /* allow 00 to be written to the index */
799
800 wr32(&vsi->back->hw,
801 I40E_PFINT_DYN_CTLN(q_vector->v_idx +
802 vsi->base_vector - 1), val);
803 } else {
804 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
805 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
806 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
807 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
808 /* allow 00 to be written to the index */
809
810 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
811 }
fd0a05ce
JB		 812}
813
814/**
815 * i40e_set_new_dynamic_itr - Find new ITR level
816 * @rc: structure containing ring performance data
817 *
8f5e39ce
JB		 818 * Returns true if ITR changed, false if not
819 *
fd0a05ce
JB		 820 * Stores a new ITR value based on packets and byte counts during
821 * the last interrupt. The advantage of per interrupt computation
822 * is faster updates and more accurate ITR for the current traffic
823 * pattern. Constants in this function were computed based on
824 * theoretical maximum wire speed and thresholds were set based on
825 * testing data as well as attempting to minimize response time
826 * while increasing bulk throughput.
827 **/
8f5e39ce 828static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
fd0a05ce
JB		 829{
830 enum i40e_latency_range new_latency_range = rc->latency_range;
c56625d5 831 struct i40e_q_vector *qv = rc->ring->q_vector;
fd0a05ce
JB		 832 u32 new_itr = rc->itr;
833 int bytes_per_int;
51cc6d9f 834 int usecs;
fd0a05ce
JB		 835
836 if (rc->total_packets == 0 || !rc->itr)
8f5e39ce 837 return false;
fd0a05ce
JB		 838
839 /* simple throttlerate management
c56625d5 840 * 0-10MB/s lowest (50000 ints/s)
fd0a05ce 841 * 10-20MB/s low (20000 ints/s)
c56625d5
JB		 842 * 20-1249MB/s bulk (18000 ints/s)
843 * > 40000 Rx packets per second (8000 ints/s)
51cc6d9f
JB		 844 *
845 * The math works out because the divisor is in 10^(-6) which
846 * turns the bytes/us input value into MB/s values, but
847 * make sure to use usecs, as the register values written
ee2319cf
JB		 848 * are in 2 usec increments in the ITR registers, and make sure
849 * to use the smoothed values that the countdown timer gives us.
fd0a05ce 850 */
ee2319cf 851 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
51cc6d9f 852 bytes_per_int = rc->total_bytes / usecs;
ee2319cf 853
de32e3ef 854 switch (new_latency_range) {
fd0a05ce
JB		 855 case I40E_LOWEST_LATENCY:
856 if (bytes_per_int > 10)
857 new_latency_range = I40E_LOW_LATENCY;
858 break;
859 case I40E_LOW_LATENCY:
860 if (bytes_per_int > 20)
861 new_latency_range = I40E_BULK_LATENCY;
862 else if (bytes_per_int <= 10)
863 new_latency_range = I40E_LOWEST_LATENCY;
864 break;
865 case I40E_BULK_LATENCY:
c56625d5 866 case I40E_ULTRA_LATENCY:
de32e3ef
CW		 867 default:
868 if (bytes_per_int <= 20)
869 new_latency_range = I40E_LOW_LATENCY;
fd0a05ce
JB		 870 break;
871 }
c56625d5
JB		 872
873 /* this is to adjust RX more aggressively when streaming small
874 * packets. The value of 40000 was picked as it is just beyond
875 * what the hardware can receive per second if in low latency
876 * mode.
877 */
878#define RX_ULTRA_PACKET_RATE 40000
879
880 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
881 (&qv->rx == rc))
882 new_latency_range = I40E_ULTRA_LATENCY;
883
de32e3ef 884 rc->latency_range = new_latency_range;
fd0a05ce
JB		 885
886 switch (new_latency_range) {
887 case I40E_LOWEST_LATENCY:
c56625d5 888 new_itr = I40E_ITR_50K;
fd0a05ce
JB		 889 break;
890 case I40E_LOW_LATENCY:
891 new_itr = I40E_ITR_20K;
892 break;
893 case I40E_BULK_LATENCY:
c56625d5
JB		 894 new_itr = I40E_ITR_18K;
895 break;
896 case I40E_ULTRA_LATENCY:
fd0a05ce
JB		 897 new_itr = I40E_ITR_8K;
898 break;
899 default:
900 break;
901 }
902
fd0a05ce
JB		 903 rc->total_bytes = 0;
904 rc->total_packets = 0;
8f5e39ce
JB		 905
906 if (new_itr != rc->itr) {
907 rc->itr = new_itr;
908 return true;
909 }
910
911 return false;
fd0a05ce
JB		 912}
913
fd0a05ce
JB		 914/**
915 * i40e_clean_programming_status - clean the programming status descriptor
916 * @rx_ring: the rx ring that has this descriptor
917 * @rx_desc: the rx descriptor written back by HW
918 *
919 * Flow director should handle FD_FILTER_STATUS to check its filter programming
920 * status being successful or not and take actions accordingly. FCoE should
921 * handle its context/filter programming/invalidation status and take actions.
922 *
923 **/
924static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
925 union i40e_rx_desc *rx_desc)
926{
927 u64 qw;
928 u8 id;
929
930 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
931 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
932 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
933
934 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
55a5e60b 935 i40e_fd_handle_status(rx_ring, rx_desc, id);
38e00438
VD		 936#ifdef I40E_FCOE
937 else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) ||
938 (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS))
939 i40e_fcoe_handle_status(rx_ring, rx_desc, id);
940#endif
fd0a05ce
JB		 941}
942
943/**
944 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
945 * @tx_ring: the tx ring to set up
946 *
947 * Return 0 on success, negative on error
948 **/
949int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
950{
951 struct device *dev = tx_ring->dev;
952 int bi_size;
953
954 if (!dev)
955 return -ENOMEM;
956
e908f815
JB		 957 /* warn if we are about to overwrite the pointer */
958 WARN_ON(tx_ring->tx_bi);
fd0a05ce
JB		 959 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
960 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
961 if (!tx_ring->tx_bi)
962 goto err;
963
964 /* round up to nearest 4K */
965 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1943d8ba
JB		 966 /* add u32 for head writeback, align after this takes care of
967 * guaranteeing this is at least one cache line in size
968 */
969 tx_ring->size += sizeof(u32);
fd0a05ce
JB		 970 tx_ring->size = ALIGN(tx_ring->size, 4096);
971 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
972 &tx_ring->dma, GFP_KERNEL);
973 if (!tx_ring->desc) {
974 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
975 tx_ring->size);
976 goto err;
977 }
978
979 tx_ring->next_to_use = 0;
980 tx_ring->next_to_clean = 0;
981 return 0;
982
983err:
984 kfree(tx_ring->tx_bi);
985 tx_ring->tx_bi = NULL;
986 return -ENOMEM;
987}
988
989/**
990 * i40e_clean_rx_ring - Free Rx buffers
991 * @rx_ring: ring to be cleaned
992 **/
993void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
994{
995 struct device *dev = rx_ring->dev;
996 struct i40e_rx_buffer *rx_bi;
997 unsigned long bi_size;
998 u16 i;
999
1000 /* ring already cleared, nothing to do */
1001 if (!rx_ring->rx_bi)
1002 return;
1003
a132af24
MW		 1004 if (ring_is_ps_enabled(rx_ring)) {
1005 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
1006
1007 rx_bi = &rx_ring->rx_bi[0];
1008 if (rx_bi->hdr_buf) {
1009 dma_free_coherent(dev,
1010 bufsz,
1011 rx_bi->hdr_buf,
1012 rx_bi->dma);
1013 for (i = 0; i < rx_ring->count; i++) {
1014 rx_bi = &rx_ring->rx_bi[i];
1015 rx_bi->dma = 0;
37a2973a 1016 rx_bi->hdr_buf = NULL;
a132af24
MW		 1017 }
1018 }
1019 }
fd0a05ce
JB		 1020 /* Free all the Rx ring sk_buffs */
1021 for (i = 0; i < rx_ring->count; i++) {
1022 rx_bi = &rx_ring->rx_bi[i];
1023 if (rx_bi->dma) {
1024 dma_unmap_single(dev,
1025 rx_bi->dma,
1026 rx_ring->rx_buf_len,
1027 DMA_FROM_DEVICE);
1028 rx_bi->dma = 0;
1029 }
1030 if (rx_bi->skb) {
1031 dev_kfree_skb(rx_bi->skb);
1032 rx_bi->skb = NULL;
1033 }
1034 if (rx_bi->page) {
1035 if (rx_bi->page_dma) {
1036 dma_unmap_page(dev,
1037 rx_bi->page_dma,
1038 PAGE_SIZE / 2,
1039 DMA_FROM_DEVICE);
1040 rx_bi->page_dma = 0;
1041 }
1042 __free_page(rx_bi->page);
1043 rx_bi->page = NULL;
1044 rx_bi->page_offset = 0;
1045 }
1046 }
1047
1048 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1049 memset(rx_ring->rx_bi, 0, bi_size);
1050
1051 /* Zero out the descriptor ring */
1052 memset(rx_ring->desc, 0, rx_ring->size);
1053
1054 rx_ring->next_to_clean = 0;
1055 rx_ring->next_to_use = 0;
1056}
1057
1058/**
1059 * i40e_free_rx_resources - Free Rx resources
1060 * @rx_ring: ring to clean the resources from
1061 *
1062 * Free all receive software resources
1063 **/
1064void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1065{
1066 i40e_clean_rx_ring(rx_ring);
1067 kfree(rx_ring->rx_bi);
1068 rx_ring->rx_bi = NULL;
1069
1070 if (rx_ring->desc) {
1071 dma_free_coherent(rx_ring->dev, rx_ring->size,
1072 rx_ring->desc, rx_ring->dma);
1073 rx_ring->desc = NULL;
1074 }
1075}
1076
a132af24
MW		 1077/**
1078 * i40e_alloc_rx_headers - allocate rx header buffers
1079 * @rx_ring: ring to alloc buffers
1080 *
1081 * Allocate rx header buffers for the entire ring. As these are static,
1082 * this is only called when setting up a new ring.
1083 **/
1084void i40e_alloc_rx_headers(struct i40e_ring *rx_ring)
1085{
1086 struct device *dev = rx_ring->dev;
1087 struct i40e_rx_buffer *rx_bi;
1088 dma_addr_t dma;
1089 void *buffer;
1090 int buf_size;
1091 int i;
1092
1093 if (rx_ring->rx_bi[0].hdr_buf)
1094 return;
1095 /* Make sure the buffers don't cross cache line boundaries. */
1096 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
1097 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
1098 &dma, GFP_KERNEL);
1099 if (!buffer)
1100 return;
1101 for (i = 0; i < rx_ring->count; i++) {
1102 rx_bi = &rx_ring->rx_bi[i];
1103 rx_bi->dma = dma + (i * buf_size);
1104 rx_bi->hdr_buf = buffer + (i * buf_size);
1105 }
1106}
1107
fd0a05ce
JB		 1108/**
1109 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1110 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1111 *
1112 * Returns 0 on success, negative on failure
1113 **/
1114int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1115{
1116 struct device *dev = rx_ring->dev;
1117 int bi_size;
1118
e908f815
JB		 1119 /* warn if we are about to overwrite the pointer */
1120 WARN_ON(rx_ring->rx_bi);
fd0a05ce
JB		 1121 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1122 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1123 if (!rx_ring->rx_bi)
1124 goto err;
1125
f217d6ca 1126 u64_stats_init(&rx_ring->syncp);
638702bd 1127
fd0a05ce
JB		 1128 /* Round up to nearest 4K */
1129 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
1130 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
1131 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1132 rx_ring->size = ALIGN(rx_ring->size, 4096);
1133 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1134 &rx_ring->dma, GFP_KERNEL);
1135
1136 if (!rx_ring->desc) {
1137 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1138 rx_ring->size);
1139 goto err;
1140 }
1141
1142 rx_ring->next_to_clean = 0;
1143 rx_ring->next_to_use = 0;
1144
1145 return 0;
1146err:
1147 kfree(rx_ring->rx_bi);
1148 rx_ring->rx_bi = NULL;
1149 return -ENOMEM;
1150}
1151
1152/**
1153 * i40e_release_rx_desc - Store the new tail and head values
1154 * @rx_ring: ring to bump
1155 * @val: new head index
1156 **/
1157static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1158{
1159 rx_ring->next_to_use = val;
1160 /* Force memory writes to complete before letting h/w
1161 * know there are new descriptors to fetch. (Only
1162 * applicable for weak-ordered memory model archs,
1163 * such as IA-64).
1164 */
1165 wmb();
1166 writel(val, rx_ring->tail);
1167}
1168
1169/**
a132af24 1170 * i40e_alloc_rx_buffers_ps - Replace used receive buffers; packet split
fd0a05ce
JB		 1171 * @rx_ring: ring to place buffers on
1172 * @cleaned_count: number of buffers to replace
1173 **/
a132af24
MW		 1174void i40e_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
1175{
1176 u16 i = rx_ring->next_to_use;
1177 union i40e_rx_desc *rx_desc;
1178 struct i40e_rx_buffer *bi;
1179
1180 /* do nothing if no valid netdev defined */
1181 if (!rx_ring->netdev || !cleaned_count)
1182 return;
1183
1184 while (cleaned_count--) {
1185 rx_desc = I40E_RX_DESC(rx_ring, i);
1186 bi = &rx_ring->rx_bi[i];
1187
1188 if (bi->skb) /* desc is in use */
1189 goto no_buffers;
1190 if (!bi->page) {
1191 bi->page = alloc_page(GFP_ATOMIC);
1192 if (!bi->page) {
1193 rx_ring->rx_stats.alloc_page_failed++;
1194 goto no_buffers;
1195 }
1196 }
1197
1198 if (!bi->page_dma) {
1199 /* use a half page if we're re-using */
1200 bi->page_offset ^= PAGE_SIZE / 2;
1201 bi->page_dma = dma_map_page(rx_ring->dev,
1202 bi->page,
1203 bi->page_offset,
1204 PAGE_SIZE / 2,
1205 DMA_FROM_DEVICE);
1206 if (dma_mapping_error(rx_ring->dev,
1207 bi->page_dma)) {
1208 rx_ring->rx_stats.alloc_page_failed++;
1209 bi->page_dma = 0;
1210 goto no_buffers;
1211 }
1212 }
1213
1214 dma_sync_single_range_for_device(rx_ring->dev,
1215 bi->dma,
1216 0,
1217 rx_ring->rx_hdr_len,
1218 DMA_FROM_DEVICE);
1219 /* Refresh the desc even if buffer_addrs didn't change
1220 * because each write-back erases this info.
1221 */
1222 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1223 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1224 i++;
1225 if (i == rx_ring->count)
1226 i = 0;
1227 }
1228
1229no_buffers:
1230 if (rx_ring->next_to_use != i)
1231 i40e_release_rx_desc(rx_ring, i);
1232}
1233
1234/**
1235 * i40e_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
1236 * @rx_ring: ring to place buffers on
1237 * @cleaned_count: number of buffers to replace
1238 **/
1239void i40e_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
fd0a05ce
JB		 1240{
1241 u16 i = rx_ring->next_to_use;
1242 union i40e_rx_desc *rx_desc;
1243 struct i40e_rx_buffer *bi;
1244 struct sk_buff *skb;
1245
1246 /* do nothing if no valid netdev defined */
1247 if (!rx_ring->netdev || !cleaned_count)
1248 return;
1249
1250 while (cleaned_count--) {
1251 rx_desc = I40E_RX_DESC(rx_ring, i);
1252 bi = &rx_ring->rx_bi[i];
1253 skb = bi->skb;
1254
1255 if (!skb) {
1256 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1257 rx_ring->rx_buf_len);
1258 if (!skb) {
420136cc 1259 rx_ring->rx_stats.alloc_buff_failed++;
fd0a05ce
JB		 1260 goto no_buffers;
1261 }
1262 /* initialize queue mapping */
1263 skb_record_rx_queue(skb, rx_ring->queue_index);
1264 bi->skb = skb;
1265 }
1266
1267 if (!bi->dma) {
1268 bi->dma = dma_map_single(rx_ring->dev,
1269 skb->data,
1270 rx_ring->rx_buf_len,
1271 DMA_FROM_DEVICE);
1272 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
420136cc 1273 rx_ring->rx_stats.alloc_buff_failed++;
fd0a05ce
JB		 1274 bi->dma = 0;
1275 goto no_buffers;
1276 }
1277 }
1278
a132af24
MW		 1279 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1280 rx_desc->read.hdr_addr = 0;
fd0a05ce
JB		 1281 i++;
1282 if (i == rx_ring->count)
1283 i = 0;
1284 }
1285
1286no_buffers:
1287 if (rx_ring->next_to_use != i)
1288 i40e_release_rx_desc(rx_ring, i);
1289}
1290
1291/**
1292 * i40e_receive_skb - Send a completed packet up the stack
1293 * @rx_ring: rx ring in play
1294 * @skb: packet to send up
1295 * @vlan_tag: vlan tag for packet
1296 **/
1297static void i40e_receive_skb(struct i40e_ring *rx_ring,
1298 struct sk_buff *skb, u16 vlan_tag)
1299{
1300 struct i40e_q_vector *q_vector = rx_ring->q_vector;
fd0a05ce
JB		 1301
1302 if (vlan_tag & VLAN_VID_MASK)
1303 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
1304
8b650359 1305 napi_gro_receive(&q_vector->napi, skb);
fd0a05ce
JB		 1306}
1307
1308/**
1309 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1310 * @vsi: the VSI we care about
1311 * @skb: skb currently being received and modified
1312 * @rx_status: status value of last descriptor in packet
1313 * @rx_error: error value of last descriptor in packet
8144f0f7 1314 * @rx_ptype: ptype value of last descriptor in packet
fd0a05ce
JB		 1315 **/
1316static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1317 struct sk_buff *skb,
1318 u32 rx_status,
8144f0f7
JG		 1319 u32 rx_error,
1320 u16 rx_ptype)
fd0a05ce 1321{
8a3c91cc
JB		 1322 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
1323 bool ipv4 = false, ipv6 = false;
8144f0f7
JG		 1324 bool ipv4_tunnel, ipv6_tunnel;
1325 __wsum rx_udp_csum;
8144f0f7 1326 struct iphdr *iph;
8a3c91cc 1327 __sum16 csum;
8144f0f7 1328
f8faaa40
ASJ		 1329 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
1330 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
1331 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
1332 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
8144f0f7 1333
fd0a05ce
JB		 1334 skb->ip_summed = CHECKSUM_NONE;
1335
1336 /* Rx csum enabled and ip headers found? */
8a3c91cc
JB		 1337 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1338 return;
1339
1340 /* did the hardware decode the packet and checksum? */
41a1d04b 1341 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
8a3c91cc
JB		 1342 return;
1343
1344 /* both known and outer_ip must be set for the below code to work */
1345 if (!(decoded.known && decoded.outer_ip))
fd0a05ce
JB		 1346 return;
1347
8a3c91cc
JB		 1348 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1349 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
1350 ipv4 = true;
1351 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1352 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
1353 ipv6 = true;
1354
1355 if (ipv4 &&
41a1d04b
JB		 1356 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1357 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
8a3c91cc
JB		 1358 goto checksum_fail;
1359
ddf1d0d7 1360 /* likely incorrect csum if alternate IP extension headers found */
8a3c91cc 1361 if (ipv6 &&
41a1d04b 1362 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
8a3c91cc 1363 /* don't increment checksum err here, non-fatal err */
8ee75a8e
SN		 1364 return;
1365
8a3c91cc 1366 /* there was some L4 error, count error and punt packet to the stack */
41a1d04b 1367 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
8a3c91cc
JB		 1368 goto checksum_fail;
1369
1370 /* handle packets that were not able to be checksummed due
1371 * to arrival speed, in this case the stack can compute
1372 * the csum.
1373 */
41a1d04b 1374 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
fd0a05ce 1375 return;
fd0a05ce 1376
8a3c91cc
JB		 1377 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
1378 * it in the driver, hardware does not do it for us.
1379 * Since L3L4P bit was set we assume a valid IHL value (>=5)
1380 * so the total length of IPv4 header is IHL*4 bytes
1381 * The UDP_0 bit *may* bet set if the *inner* header is UDP
1382 */
527274c7
ASJ		 1383 if (!(vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE) &&
1384 (ipv4_tunnel)) {
8144f0f7
JG		 1385 skb->transport_header = skb->mac_header +
1386 sizeof(struct ethhdr) +
1387 (ip_hdr(skb)->ihl * 4);
1388
1389 /* Add 4 bytes for VLAN tagged packets */
1390 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
1391 skb->protocol == htons(ETH_P_8021AD))
1392 ? VLAN_HLEN : 0;
1393
f6385979
AS		 1394 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
1395 (udp_hdr(skb)->check != 0)) {
1396 rx_udp_csum = udp_csum(skb);
1397 iph = ip_hdr(skb);
1398 csum = csum_tcpudp_magic(
1399 iph->saddr, iph->daddr,
1400 (skb->len - skb_transport_offset(skb)),
1401 IPPROTO_UDP, rx_udp_csum);
8144f0f7 1402
f6385979
AS		 1403 if (udp_hdr(skb)->check != csum)
1404 goto checksum_fail;
1405
1406 } /* else its GRE and so no outer UDP header */
8144f0f7
JG		 1407 }
1408
fd0a05ce 1409 skb->ip_summed = CHECKSUM_UNNECESSARY;
fa4ba69b 1410 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
8a3c91cc
JB		 1411
1412 return;
1413
1414checksum_fail:
1415 vsi->back->hw_csum_rx_error++;
fd0a05ce
JB		 1416}
1417
1418/**
1419 * i40e_rx_hash - returns the hash value from the Rx descriptor
1420 * @ring: descriptor ring
1421 * @rx_desc: specific descriptor
1422 **/
1423static inline u32 i40e_rx_hash(struct i40e_ring *ring,
1424 union i40e_rx_desc *rx_desc)
1425{
8a494920
JB		 1426 const __le64 rss_mask =
1427 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1428 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1429
1430 if ((ring->netdev->features & NETIF_F_RXHASH) &&
1431 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
1432 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1433 else
1434 return 0;
fd0a05ce
JB		 1435}
1436
206812b5
JB		 1437/**
1438 * i40e_ptype_to_hash - get a hash type
1439 * @ptype: the ptype value from the descriptor
1440 *
1441 * Returns a hash type to be used by skb_set_hash
1442 **/
1443static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
1444{
1445 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1446
1447 if (!decoded.known)
1448 return PKT_HASH_TYPE_NONE;
1449
1450 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1451 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1452 return PKT_HASH_TYPE_L4;
1453 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1454 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1455 return PKT_HASH_TYPE_L3;
1456 else
1457 return PKT_HASH_TYPE_L2;
1458}
1459
fd0a05ce 1460/**
a132af24 1461 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
fd0a05ce
JB		 1462 * @rx_ring: rx ring to clean
1463 * @budget: how many cleans we're allowed
1464 *
1465 * Returns true if there's any budget left (e.g. the clean is finished)
1466 **/
a132af24 1467static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
fd0a05ce
JB		 1468{
1469 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1470 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1471 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
8dc5562e 1472 const int current_node = numa_mem_id();
fd0a05ce
JB		 1473 struct i40e_vsi *vsi = rx_ring->vsi;
1474 u16 i = rx_ring->next_to_clean;
1475 union i40e_rx_desc *rx_desc;
1476 u32 rx_error, rx_status;
206812b5 1477 u8 rx_ptype;
fd0a05ce
JB		 1478 u64 qword;
1479
390f86df
EB		 1480 if (budget <= 0)
1481 return 0;
1482
a132af24 1483 do {
fd0a05ce
JB		 1484 struct i40e_rx_buffer *rx_bi;
1485 struct sk_buff *skb;
1486 u16 vlan_tag;
a132af24
MW		 1487 /* return some buffers to hardware, one at a time is too slow */
1488 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1489 i40e_alloc_rx_buffers_ps(rx_ring, cleaned_count);
1490 cleaned_count = 0;
1491 }
1492
1493 i = rx_ring->next_to_clean;
1494 rx_desc = I40E_RX_DESC(rx_ring, i);
1495 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1496 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1497 I40E_RXD_QW1_STATUS_SHIFT;
1498
41a1d04b 1499 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
a132af24
MW		 1500 break;
1501
1502 /* This memory barrier is needed to keep us from reading
1503 * any other fields out of the rx_desc until we know the
1504 * DD bit is set.
1505 */
67317166 1506 dma_rmb();
fd0a05ce
JB		 1507 if (i40e_rx_is_programming_status(qword)) {
1508 i40e_clean_programming_status(rx_ring, rx_desc);
a132af24
MW		 1509 I40E_RX_INCREMENT(rx_ring, i);
1510 continue;
fd0a05ce
JB		 1511 }
1512 rx_bi = &rx_ring->rx_bi[i];
1513 skb = rx_bi->skb;
a132af24
MW		 1514 if (likely(!skb)) {
1515 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1516 rx_ring->rx_hdr_len);
8b6ed9c2 1517 if (!skb) {
a132af24 1518 rx_ring->rx_stats.alloc_buff_failed++;
8b6ed9c2
JB		 1519 break;
1520 }
1521
a132af24
MW		 1522 /* initialize queue mapping */
1523 skb_record_rx_queue(skb, rx_ring->queue_index);
1524 /* we are reusing so sync this buffer for CPU use */
1525 dma_sync_single_range_for_cpu(rx_ring->dev,
1526 rx_bi->dma,
1527 0,
1528 rx_ring->rx_hdr_len,
1529 DMA_FROM_DEVICE);
1530 }
829af3ac
MW		 1531 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1532 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1533 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1534 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1535 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1536 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1537
1538 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1539 I40E_RXD_QW1_ERROR_SHIFT;
41a1d04b
JB		 1540 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1541 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
fd0a05ce 1542
8144f0f7
JG		 1543 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1544 I40E_RXD_QW1_PTYPE_SHIFT;
a132af24 1545 prefetch(rx_bi->page);
fd0a05ce 1546 rx_bi->skb = NULL;
a132af24
MW		 1547 cleaned_count++;
1548 if (rx_hbo || rx_sph) {
1549 int len;
6995b36c 1550
fd0a05ce
JB		 1551 if (rx_hbo)
1552 len = I40E_RX_HDR_SIZE;
fd0a05ce 1553 else
a132af24
MW		 1554 len = rx_header_len;
1555 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1556 } else if (skb->len == 0) {
1557 int len;
1558
1559 len = (rx_packet_len > skb_headlen(skb) ?
1560 skb_headlen(skb) : rx_packet_len);
1561 memcpy(__skb_put(skb, len),
1562 rx_bi->page + rx_bi->page_offset,
1563 len);
1564 rx_bi->page_offset += len;
1565 rx_packet_len -= len;
fd0a05ce
JB		 1566 }
1567
1568 /* Get the rest of the data if this was a header split */
a132af24 1569 if (rx_packet_len) {
fd0a05ce
JB		 1570 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1571 rx_bi->page,
1572 rx_bi->page_offset,
1573 rx_packet_len);
1574
1575 skb->len += rx_packet_len;
1576 skb->data_len += rx_packet_len;
1577 skb->truesize += rx_packet_len;
1578
1579 if ((page_count(rx_bi->page) == 1) &&
1580 (page_to_nid(rx_bi->page) == current_node))
1581 get_page(rx_bi->page);
1582 else
1583 rx_bi->page = NULL;
1584
1585 dma_unmap_page(rx_ring->dev,
1586 rx_bi->page_dma,
1587 PAGE_SIZE / 2,
1588 DMA_FROM_DEVICE);
1589 rx_bi->page_dma = 0;
1590 }
a132af24 1591 I40E_RX_INCREMENT(rx_ring, i);
fd0a05ce
JB		 1592
1593 if (unlikely(
41a1d04b 1594 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
fd0a05ce
JB		 1595 struct i40e_rx_buffer *next_buffer;
1596
1597 next_buffer = &rx_ring->rx_bi[i];
a132af24 1598 next_buffer->skb = skb;
fd0a05ce 1599 rx_ring->rx_stats.non_eop_descs++;
a132af24 1600 continue;
fd0a05ce
JB		 1601 }
1602
1603 /* ERR_MASK will only have valid bits if EOP set */
41a1d04b 1604 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
fd0a05ce 1605 dev_kfree_skb_any(skb);
a132af24 1606 continue;
fd0a05ce
JB		 1607 }
1608
206812b5
JB		 1609 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1610 i40e_ptype_to_hash(rx_ptype));
beb0dff1
JK		 1611 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1612 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1613 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1614 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1615 rx_ring->last_rx_timestamp = jiffies;
1616 }
1617
fd0a05ce
JB		 1618 /* probably a little skewed due to removing CRC */
1619 total_rx_bytes += skb->len;
1620 total_rx_packets++;
1621
1622 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8144f0f7
JG		 1623
1624 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1625
41a1d04b 1626 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
fd0a05ce
JB		 1627 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1628 : 0;
38e00438
VD		 1629#ifdef I40E_FCOE
1630 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1631 dev_kfree_skb_any(skb);
a132af24 1632 continue;
38e00438
VD		 1633 }
1634#endif
fd0a05ce
JB		 1635 i40e_receive_skb(rx_ring, skb, vlan_tag);
1636
fd0a05ce 1637 rx_desc->wb.qword1.status_error_len = 0;
fd0a05ce 1638
a132af24
MW		 1639 } while (likely(total_rx_packets < budget));
1640
1641 u64_stats_update_begin(&rx_ring->syncp);
1642 rx_ring->stats.packets += total_rx_packets;
1643 rx_ring->stats.bytes += total_rx_bytes;
1644 u64_stats_update_end(&rx_ring->syncp);
1645 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1646 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1647
1648 return total_rx_packets;
1649}
1650
1651/**
1652 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1653 * @rx_ring: rx ring to clean
1654 * @budget: how many cleans we're allowed
1655 *
1656 * Returns number of packets cleaned
1657 **/
1658static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1659{
1660 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1661 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1662 struct i40e_vsi *vsi = rx_ring->vsi;
1663 union i40e_rx_desc *rx_desc;
1664 u32 rx_error, rx_status;
1665 u16 rx_packet_len;
1666 u8 rx_ptype;
1667 u64 qword;
1668 u16 i;
1669
1670 do {
1671 struct i40e_rx_buffer *rx_bi;
1672 struct sk_buff *skb;
1673 u16 vlan_tag;
fd0a05ce
JB		 1674 /* return some buffers to hardware, one at a time is too slow */
1675 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
a132af24 1676 i40e_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
fd0a05ce
JB		 1677 cleaned_count = 0;
1678 }
1679
a132af24
MW		 1680 i = rx_ring->next_to_clean;
1681 rx_desc = I40E_RX_DESC(rx_ring, i);
fd0a05ce 1682 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
829af3ac 1683 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
a132af24
MW		 1684 I40E_RXD_QW1_STATUS_SHIFT;
1685
41a1d04b 1686 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
a132af24
MW		 1687 break;
1688
1689 /* This memory barrier is needed to keep us from reading
1690 * any other fields out of the rx_desc until we know the
1691 * DD bit is set.
1692 */
67317166 1693 dma_rmb();
a132af24
MW		 1694
1695 if (i40e_rx_is_programming_status(qword)) {
1696 i40e_clean_programming_status(rx_ring, rx_desc);
1697 I40E_RX_INCREMENT(rx_ring, i);
1698 continue;
1699 }
1700 rx_bi = &rx_ring->rx_bi[i];
1701 skb = rx_bi->skb;
1702 prefetch(skb->data);
1703
1704 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1705 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1706
1707 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1708 I40E_RXD_QW1_ERROR_SHIFT;
41a1d04b 1709 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
a132af24
MW		 1710
1711 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1712 I40E_RXD_QW1_PTYPE_SHIFT;
1713 rx_bi->skb = NULL;
1714 cleaned_count++;
1715
1716 /* Get the header and possibly the whole packet
1717 * If this is an skb from previous receive dma will be 0
1718 */
1719 skb_put(skb, rx_packet_len);
1720 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1721 DMA_FROM_DEVICE);
1722 rx_bi->dma = 0;
1723
1724 I40E_RX_INCREMENT(rx_ring, i);
1725
1726 if (unlikely(
41a1d04b 1727 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
a132af24
MW		 1728 rx_ring->rx_stats.non_eop_descs++;
1729 continue;
1730 }
1731
1732 /* ERR_MASK will only have valid bits if EOP set */
41a1d04b 1733 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
a132af24 1734 dev_kfree_skb_any(skb);
a132af24
MW		 1735 continue;
1736 }
1737
1738 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1739 i40e_ptype_to_hash(rx_ptype));
1740 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1741 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1742 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1743 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1744 rx_ring->last_rx_timestamp = jiffies;
1745 }
1746
1747 /* probably a little skewed due to removing CRC */
1748 total_rx_bytes += skb->len;
1749 total_rx_packets++;
1750
1751 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1752
1753 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1754
41a1d04b 1755 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
a132af24
MW		 1756 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1757 : 0;
1758#ifdef I40E_FCOE
1759 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1760 dev_kfree_skb_any(skb);
1761 continue;
1762 }
1763#endif
1764 i40e_receive_skb(rx_ring, skb, vlan_tag);
1765
a132af24
MW		 1766 rx_desc->wb.qword1.status_error_len = 0;
1767 } while (likely(total_rx_packets < budget));
fd0a05ce 1768
980e9b11 1769 u64_stats_update_begin(&rx_ring->syncp);
a114d0a6
AD		 1770 rx_ring->stats.packets += total_rx_packets;
1771 rx_ring->stats.bytes += total_rx_bytes;
980e9b11 1772 u64_stats_update_end(&rx_ring->syncp);
fd0a05ce
JB		 1773 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1774 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1775
a132af24 1776 return total_rx_packets;
fd0a05ce
JB		 1777}
1778
8f5e39ce
JB		 1779static u32 i40e_buildreg_itr(const int type, const u16 itr)
1780{
1781 u32 val;
1782
1783 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1784 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1785 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1786 (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
1787
1788 return val;
1789}
1790
1791/* a small macro to shorten up some long lines */
1792#define INTREG I40E_PFINT_DYN_CTLN
1793
de32e3ef
CW		 1794/**
1795 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1796 * @vsi: the VSI we care about
1797 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1798 *
1799 **/
1800static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1801 struct i40e_q_vector *q_vector)
1802{
1803 struct i40e_hw *hw = &vsi->back->hw;
8f5e39ce
JB		 1804 bool rx = false, tx = false;
1805 u32 rxval, txval;
de32e3ef 1806 int vector;
de32e3ef
CW		 1807
1808 vector = (q_vector->v_idx + vsi->base_vector);
8f5e39ce 1809
ee2319cf
JB		 1810 /* avoid dynamic calculation if in countdown mode OR if
1811 * all dynamic is disabled
1812 */
8f5e39ce
JB		 1813 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1814
ee2319cf
JB		 1815 if (q_vector->itr_countdown > 0 ||
1816 (!ITR_IS_DYNAMIC(vsi->rx_itr_setting) &&
1817 !ITR_IS_DYNAMIC(vsi->tx_itr_setting))) {
1818 goto enable_int;
1819 }
1820
de32e3ef 1821 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
8f5e39ce
JB		 1822 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1823 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
de32e3ef 1824 }
8f5e39ce 1825
de32e3ef 1826 if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
8f5e39ce
JB		 1827 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1828 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
de32e3ef 1829 }
8f5e39ce
JB		 1830
1831 if (rx || tx) {
1832 /* get the higher of the two ITR adjustments and
1833 * use the same value for both ITR registers
1834 * when in adaptive mode (Rx and/or Tx)
1835 */
1836 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1837
1838 q_vector->tx.itr = q_vector->rx.itr = itr;
1839 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1840 tx = true;
1841 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1842 rx = true;
1843 }
1844
1845 /* only need to enable the interrupt once, but need
1846 * to possibly update both ITR values
1847 */
1848 if (rx) {
1849 /* set the INTENA_MSK_MASK so that this first write
1850 * won't actually enable the interrupt, instead just
1851 * updating the ITR (it's bit 31 PF and VF)
1852 */
1853 rxval |= BIT(31);
1854 /* don't check _DOWN because interrupt isn't being enabled */
1855 wr32(hw, INTREG(vector - 1), rxval);
1856 }
1857
ee2319cf 1858enable_int:
8f5e39ce
JB		 1859 if (!test_bit(__I40E_DOWN, &vsi->state))
1860 wr32(hw, INTREG(vector - 1), txval);
ee2319cf
JB		 1861
1862 if (q_vector->itr_countdown)
1863 q_vector->itr_countdown--;
1864 else
1865 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1866
de32e3ef
CW		 1867}
1868
fd0a05ce
JB		 1869/**
1870 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
1871 * @napi: napi struct with our devices info in it
1872 * @budget: amount of work driver is allowed to do this pass, in packets
1873 *
1874 * This function will clean all queues associated with a q_vector.
1875 *
1876 * Returns the amount of work done
1877 **/
1878int i40e_napi_poll(struct napi_struct *napi, int budget)
1879{
1880 struct i40e_q_vector *q_vector =
1881 container_of(napi, struct i40e_q_vector, napi);
1882 struct i40e_vsi *vsi = q_vector->vsi;
cd0b6fa6 1883 struct i40e_ring *ring;
fd0a05ce 1884 bool clean_complete = true;
d91649f5 1885 bool arm_wb = false;
fd0a05ce 1886 int budget_per_ring;
32b3e08f 1887 int work_done = 0;
fd0a05ce
JB		 1888
1889 if (test_bit(__I40E_DOWN, &vsi->state)) {
1890 napi_complete(napi);
1891 return 0;
1892 }
1893
9c6c1259
KP		 1894 /* Clear hung_detected bit */
1895 clear_bit(I40E_Q_VECTOR_HUNG_DETECT, &q_vector->hung_detected);
cd0b6fa6
AD		 1896 /* Since the actual Tx work is minimal, we can give the Tx a larger
1897 * budget and be more aggressive about cleaning up the Tx descriptors.
1898 */
d91649f5 1899 i40e_for_each_ring(ring, q_vector->tx) {
cd0b6fa6 1900 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
d91649f5 1901 arm_wb |= ring->arm_wb;
0deda868 1902 ring->arm_wb = false;
d91649f5 1903 }
cd0b6fa6 1904
c67caceb
AD		 1905 /* Handle case where we are called by netpoll with a budget of 0 */
1906 if (budget <= 0)
1907 goto tx_only;
1908
fd0a05ce
JB		 1909 /* We attempt to distribute budget to each Rx queue fairly, but don't
1910 * allow the budget to go below 1 because that would exit polling early.
fd0a05ce
JB		 1911 */
1912 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
cd0b6fa6 1913
a132af24 1914 i40e_for_each_ring(ring, q_vector->rx) {
32b3e08f
JB		 1915 int cleaned;
1916
a132af24
MW		 1917 if (ring_is_ps_enabled(ring))
1918 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1919 else
1920 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
32b3e08f
JB		 1921
1922 work_done += cleaned;
a132af24
MW		 1923 /* if we didn't clean as many as budgeted, we must be done */
1924 clean_complete &= (budget_per_ring != cleaned);
1925 }
fd0a05ce
JB		 1926
1927 /* If work not completed, return budget and polling will return */
d91649f5 1928 if (!clean_complete) {
c67caceb 1929tx_only:
164c9f54
ASJ		 1930 if (arm_wb) {
1931 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
d91649f5 1932 i40e_force_wb(vsi, q_vector);
164c9f54 1933 }
fd0a05ce 1934 return budget;
d91649f5 1935 }
fd0a05ce 1936
8e0764b4
ASJ		 1937 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1938 q_vector->arm_wb_state = false;
1939
fd0a05ce 1940 /* Work is done so exit the polling mode and re-enable the interrupt */
32b3e08f 1941 napi_complete_done(napi, work_done);
de32e3ef
CW		 1942 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1943 i40e_update_enable_itr(vsi, q_vector);
1944 } else { /* Legacy mode */
1945 struct i40e_hw *hw = &vsi->back->hw;
1946 /* We re-enable the queue 0 cause, but
1947 * don't worry about dynamic_enable
1948 * because we left it on for the other
1949 * possible interrupts during napi
1950 */
1951 u32 qval = rd32(hw, I40E_QINT_RQCTL(0)) |
1952 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1953
1954 wr32(hw, I40E_QINT_RQCTL(0), qval);
1955 qval = rd32(hw, I40E_QINT_TQCTL(0)) |
1956 I40E_QINT_TQCTL_CAUSE_ENA_MASK;
1957 wr32(hw, I40E_QINT_TQCTL(0), qval);
1958 i40e_irq_dynamic_enable_icr0(vsi->back);
fd0a05ce 1959 }
fd0a05ce
JB		 1960 return 0;
1961}
1962
1963/**
1964 * i40e_atr - Add a Flow Director ATR filter
1965 * @tx_ring: ring to add programming descriptor to
1966 * @skb: send buffer
89232c3b 1967 * @tx_flags: send tx flags
fd0a05ce
JB		 1968 * @protocol: wire protocol
1969 **/
1970static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
89232c3b 1971 u32 tx_flags, __be16 protocol)
fd0a05ce
JB		 1972{
1973 struct i40e_filter_program_desc *fdir_desc;
1974 struct i40e_pf *pf = tx_ring->vsi->back;
1975 union {
1976 unsigned char *network;
1977 struct iphdr *ipv4;
1978 struct ipv6hdr *ipv6;
1979 } hdr;
1980 struct tcphdr *th;
1981 unsigned int hlen;
1982 u32 flex_ptype, dtype_cmd;
fc4ac67b 1983 u16 i;
fd0a05ce
JB		 1984
1985 /* make sure ATR is enabled */
60ea5f83 1986 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
fd0a05ce
JB		 1987 return;
1988
04294e38
ASJ		 1989 if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1990 return;
1991
fd0a05ce
JB		 1992 /* if sampling is disabled do nothing */
1993 if (!tx_ring->atr_sample_rate)
1994 return;
1995
89232c3b
ASJ		 1996 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
1997 return;
fd0a05ce 1998
89232c3b
ASJ		 1999 if (!(tx_flags & I40E_TX_FLAGS_VXLAN_TUNNEL)) {
2000 /* snag network header to get L4 type and address */
2001 hdr.network = skb_network_header(skb);
fd0a05ce 2002
89232c3b
ASJ		 2003 /* Currently only IPv4/IPv6 with TCP is supported
2004 * access ihl as u8 to avoid unaligned access on ia64
2005 */
2006 if (tx_flags & I40E_TX_FLAGS_IPV4)
2007 hlen = (hdr.network[0] & 0x0F) << 2;
2008 else if (protocol == htons(ETH_P_IPV6))
2009 hlen = sizeof(struct ipv6hdr);
2010 else
fd0a05ce 2011 return;
fd0a05ce 2012 } else {
89232c3b
ASJ		 2013 hdr.network = skb_inner_network_header(skb);
2014 hlen = skb_inner_network_header_len(skb);
fd0a05ce
JB		 2015 }
2016
89232c3b
ASJ		 2017 /* Currently only IPv4/IPv6 with TCP is supported
2018 * Note: tx_flags gets modified to reflect inner protocols in
2019 * tx_enable_csum function if encap is enabled.
2020 */
2021 if ((tx_flags & I40E_TX_FLAGS_IPV4) &&
2022 (hdr.ipv4->protocol != IPPROTO_TCP))
2023 return;
2024 else if ((tx_flags & I40E_TX_FLAGS_IPV6) &&
2025 (hdr.ipv6->nexthdr != IPPROTO_TCP))
2026 return;
2027
fd0a05ce
JB		 2028 th = (struct tcphdr *)(hdr.network + hlen);
2029
55a5e60b
ASJ		 2030 /* Due to lack of space, no more new filters can be programmed */
2031 if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
2032 return;
52eb95ef
ASJ		 2033 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) {
2034 /* HW ATR eviction will take care of removing filters on FIN
2035 * and RST packets.
2036 */
2037 if (th->fin || th->rst)
2038 return;
2039 }
55a5e60b
ASJ		 2040
2041 tx_ring->atr_count++;
2042
ce806783
ASJ		 2043 /* sample on all syn/fin/rst packets or once every atr sample rate */
2044 if (!th->fin &&
2045 !th->syn &&
2046 !th->rst &&
2047 (tx_ring->atr_count < tx_ring->atr_sample_rate))
fd0a05ce
JB		 2048 return;
2049
2050 tx_ring->atr_count = 0;
2051
2052 /* grab the next descriptor */
fc4ac67b
AD		 2053 i = tx_ring->next_to_use;
2054 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2055
2056 i++;
2057 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
fd0a05ce
JB		 2058
2059 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2060 I40E_TXD_FLTR_QW0_QINDEX_MASK;
2061 flex_ptype |= (protocol == htons(ETH_P_IP)) ?
2062 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2063 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2064 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2065 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2066
2067 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2068
2069 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2070
ce806783 2071 dtype_cmd |= (th->fin || th->rst) ?
fd0a05ce
JB		 2072 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2073 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2074 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2075 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2076
2077 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2078 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2079
2080 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2081 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2082
433c47de 2083 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
60ccd45c
ASJ		 2084 if (!(tx_flags & I40E_TX_FLAGS_VXLAN_TUNNEL))
2085 dtype_cmd |=
2086 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2087 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2088 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2089 else
2090 dtype_cmd |=
2091 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2092 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2093 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
433c47de 2094
52eb95ef
ASJ		 2095 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)
2096 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2097
fd0a05ce 2098 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
99753ea6 2099 fdir_desc->rsvd = cpu_to_le32(0);
fd0a05ce 2100 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
99753ea6 2101 fdir_desc->fd_id = cpu_to_le32(0);
fd0a05ce
JB		 2102}
2103
fd0a05ce
JB		 2104/**
2105 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2106 * @skb: send buffer
2107 * @tx_ring: ring to send buffer on
2108 * @flags: the tx flags to be set
2109 *
2110 * Checks the skb and set up correspondingly several generic transmit flags
2111 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2112 *
2113 * Returns error code indicate the frame should be dropped upon error and the
2114 * otherwise returns 0 to indicate the flags has been set properly.
2115 **/
38e00438 2116#ifdef I40E_FCOE
3e587cf3 2117inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
fd0a05ce
JB		 2118 struct i40e_ring *tx_ring,
2119 u32 *flags)
3e587cf3
JB		 2120#else
2121static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2122 struct i40e_ring *tx_ring,
2123 u32 *flags)
38e00438 2124#endif
fd0a05ce
JB		 2125{
2126 __be16 protocol = skb->protocol;
2127 u32 tx_flags = 0;
2128
31eaaccf
GR		 2129 if (protocol == htons(ETH_P_8021Q) &&
2130 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2131 /* When HW VLAN acceleration is turned off by the user the
2132 * stack sets the protocol to 8021q so that the driver
2133 * can take any steps required to support the SW only
2134 * VLAN handling. In our case the driver doesn't need
2135 * to take any further steps so just set the protocol
2136 * to the encapsulated ethertype.
2137 */
2138 skb->protocol = vlan_get_protocol(skb);
2139 goto out;
2140 }
2141
fd0a05ce 2142 /* if we have a HW VLAN tag being added, default to the HW one */
df8a39de
JP		 2143 if (skb_vlan_tag_present(skb)) {
2144 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
fd0a05ce
JB		 2145 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2146 /* else if it is a SW VLAN, check the next protocol and store the tag */
0e2fe46c 2147 } else if (protocol == htons(ETH_P_8021Q)) {
fd0a05ce 2148 struct vlan_hdr *vhdr, _vhdr;
6995b36c 2149
fd0a05ce
JB		 2150 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2151 if (!vhdr)
2152 return -EINVAL;
2153
2154 protocol = vhdr->h_vlan_encapsulated_proto;
2155 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2156 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2157 }
2158
d40d00b1
NP		 2159 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2160 goto out;
2161
fd0a05ce 2162 /* Insert 802.1p priority into VLAN header */
38e00438
VD		 2163 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2164 (skb->priority != TC_PRIO_CONTROL)) {
fd0a05ce
JB		 2165 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2166 tx_flags |= (skb->priority & 0x7) <<
2167 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2168 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2169 struct vlan_ethhdr *vhdr;
dd225bc6
FR		 2170 int rc;
2171
2172 rc = skb_cow_head(skb, 0);
2173 if (rc < 0)
2174 return rc;
fd0a05ce
JB		 2175 vhdr = (struct vlan_ethhdr *)skb->data;
2176 vhdr->h_vlan_TCI = htons(tx_flags >>
2177 I40E_TX_FLAGS_VLAN_SHIFT);
2178 } else {
2179 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2180 }
2181 }
d40d00b1
NP		 2182
2183out:
fd0a05ce
JB		 2184 *flags = tx_flags;
2185 return 0;
2186}
2187
fd0a05ce
JB		 2188/**
2189 * i40e_tso - set up the tso context descriptor
2190 * @tx_ring: ptr to the ring to send
2191 * @skb: ptr to the skb we're sending
fd0a05ce 2192 * @hdr_len: ptr to the size of the packet header
9c883bd3 2193 * @cd_type_cmd_tso_mss: Quad Word 1
fd0a05ce
JB		 2194 *
2195 * Returns 0 if no TSO can happen, 1 if tso is going, or error
2196 **/
2197static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
9c883bd3 2198 u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
fd0a05ce
JB		 2199{
2200 u32 cd_cmd, cd_tso_len, cd_mss;
dd225bc6 2201 struct ipv6hdr *ipv6h;
fd0a05ce
JB		 2202 struct tcphdr *tcph;
2203 struct iphdr *iph;
2204 u32 l4len;
2205 int err;
fd0a05ce
JB		 2206
2207 if (!skb_is_gso(skb))
2208 return 0;
2209
dd225bc6
FR		 2210 err = skb_cow_head(skb, 0);
2211 if (err < 0)
2212 return err;
fd0a05ce 2213
df23075f
AS		 2214 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
2215 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
2216
2217 if (iph->version == 4) {
fd0a05ce
JB		 2218 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2219 iph->tot_len = 0;
2220 iph->check = 0;
2221 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
2222 0, IPPROTO_TCP, 0);
df23075f 2223 } else if (ipv6h->version == 6) {
fd0a05ce
JB		 2224 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2225 ipv6h->payload_len = 0;
2226 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
2227 0, IPPROTO_TCP, 0);
2228 }
2229
2230 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
2231 *hdr_len = (skb->encapsulation
2232 ? (skb_inner_transport_header(skb) - skb->data)
2233 : skb_transport_offset(skb)) + l4len;
2234
2235 /* find the field values */
2236 cd_cmd = I40E_TX_CTX_DESC_TSO;
2237 cd_tso_len = skb->len - *hdr_len;
2238 cd_mss = skb_shinfo(skb)->gso_size;
829af3ac
MW		 2239 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2240 ((u64)cd_tso_len <<
2241 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2242 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
fd0a05ce
JB		 2243 return 1;
2244}
2245
beb0dff1
JK		 2246/**
2247 * i40e_tsyn - set up the tsyn context descriptor
2248 * @tx_ring: ptr to the ring to send
2249 * @skb: ptr to the skb we're sending
2250 * @tx_flags: the collected send information
9c883bd3 2251 * @cd_type_cmd_tso_mss: Quad Word 1
beb0dff1
JK		 2252 *
2253 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
2254 **/
2255static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
2256 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
2257{
2258 struct i40e_pf *pf;
2259
2260 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
2261 return 0;
2262
2263 /* Tx timestamps cannot be sampled when doing TSO */
2264 if (tx_flags & I40E_TX_FLAGS_TSO)
2265 return 0;
2266
2267 /* only timestamp the outbound packet if the user has requested it and
2268 * we are not already transmitting a packet to be timestamped
2269 */
2270 pf = i40e_netdev_to_pf(tx_ring->netdev);
22b4777d
JK		 2271 if (!(pf->flags & I40E_FLAG_PTP))
2272 return 0;
2273
9ce34f02
JK		 2274 if (pf->ptp_tx &&
2275 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) {
beb0dff1
JK		 2276 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2277 pf->ptp_tx_skb = skb_get(skb);
2278 } else {
2279 return 0;
2280 }
2281
2282 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
2283 I40E_TXD_CTX_QW1_CMD_SHIFT;
2284
beb0dff1
JK		 2285 return 1;
2286}
2287
fd0a05ce
JB		 2288/**
2289 * i40e_tx_enable_csum - Enable Tx checksum offloads
2290 * @skb: send buffer
89232c3b 2291 * @tx_flags: pointer to Tx flags currently set
fd0a05ce
JB		 2292 * @td_cmd: Tx descriptor command bits to set
2293 * @td_offset: Tx descriptor header offsets to set
554f4544 2294 * @tx_ring: Tx descriptor ring
fd0a05ce
JB		 2295 * @cd_tunneling: ptr to context desc bits
2296 **/
89232c3b 2297static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
fd0a05ce
JB		 2298 u32 *td_cmd, u32 *td_offset,
2299 struct i40e_ring *tx_ring,
2300 u32 *cd_tunneling)
2301{
2302 struct ipv6hdr *this_ipv6_hdr;
2303 unsigned int this_tcp_hdrlen;
2304 struct iphdr *this_ip_hdr;
2305 u32 network_hdr_len;
2306 u8 l4_hdr = 0;
527274c7
ASJ		 2307 struct udphdr *oudph;
2308 struct iphdr *oiph;
45991204 2309 u32 l4_tunnel = 0;
fd0a05ce
JB		 2310
2311 if (skb->encapsulation) {
45991204
ASJ		 2312 switch (ip_hdr(skb)->protocol) {
2313 case IPPROTO_UDP:
527274c7
ASJ		 2314 oudph = udp_hdr(skb);
2315 oiph = ip_hdr(skb);
45991204 2316 l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
89232c3b 2317 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
45991204 2318 break;
c1d1791d
SN		 2319 case IPPROTO_GRE:
2320 l4_tunnel = I40E_TXD_CTX_GRE_TUNNELING;
2321 break;
45991204
ASJ		 2322 default:
2323 return;
2324 }
fd0a05ce
JB		 2325 network_hdr_len = skb_inner_network_header_len(skb);
2326 this_ip_hdr = inner_ip_hdr(skb);
2327 this_ipv6_hdr = inner_ipv6_hdr(skb);
2328 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
2329
89232c3b
ASJ		 2330 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2331 if (*tx_flags & I40E_TX_FLAGS_TSO) {
fd0a05ce
JB		 2332 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
2333 ip_hdr(skb)->check = 0;
2334 } else {
2335 *cd_tunneling |=
2336 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
2337 }
89232c3b 2338 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
df23075f 2339 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
89232c3b 2340 if (*tx_flags & I40E_TX_FLAGS_TSO)
fd0a05ce 2341 ip_hdr(skb)->check = 0;
fd0a05ce
JB		 2342 }
2343
2344 /* Now set the ctx descriptor fields */
2345 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
45991204
ASJ		 2346 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
2347 l4_tunnel |
fd0a05ce
JB		 2348 ((skb_inner_network_offset(skb) -
2349 skb_transport_offset(skb)) >> 1) <<
2350 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
df23075f 2351 if (this_ip_hdr->version == 6) {
89232c3b
ASJ		 2352 *tx_flags &= ~I40E_TX_FLAGS_IPV4;
2353 *tx_flags |= I40E_TX_FLAGS_IPV6;
df23075f 2354 }
527274c7
ASJ		 2355 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
2356 (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING) &&
2357 (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
2358 oudph->check = ~csum_tcpudp_magic(oiph->saddr,
2359 oiph->daddr,
2360 (skb->len - skb_transport_offset(skb)),
2361 IPPROTO_UDP, 0);
2362 *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
2363 }
fd0a05ce
JB		 2364 } else {
2365 network_hdr_len = skb_network_header_len(skb);
2366 this_ip_hdr = ip_hdr(skb);
2367 this_ipv6_hdr = ipv6_hdr(skb);
2368 this_tcp_hdrlen = tcp_hdrlen(skb);
2369 }
2370
2371 /* Enable IP checksum offloads */
89232c3b 2372 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
fd0a05ce
JB		 2373 l4_hdr = this_ip_hdr->protocol;
2374 /* the stack computes the IP header already, the only time we
2375 * need the hardware to recompute it is in the case of TSO.
2376 */
89232c3b 2377 if (*tx_flags & I40E_TX_FLAGS_TSO) {
fd0a05ce
JB		 2378 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
2379 this_ip_hdr->check = 0;
2380 } else {
2381 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
2382 }
2383 /* Now set the td_offset for IP header length */
2384 *td_offset = (network_hdr_len >> 2) <<
2385 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
89232c3b 2386 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
fd0a05ce
JB		 2387 l4_hdr = this_ipv6_hdr->nexthdr;
2388 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
2389 /* Now set the td_offset for IP header length */
2390 *td_offset = (network_hdr_len >> 2) <<
2391 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2392 }
2393 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
2394 *td_offset |= (skb_network_offset(skb) >> 1) <<
2395 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
2396
2397 /* Enable L4 checksum offloads */
2398 switch (l4_hdr) {
2399 case IPPROTO_TCP:
2400 /* enable checksum offloads */
2401 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
2402 *td_offset |= (this_tcp_hdrlen >> 2) <<
2403 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2404 break;
2405 case IPPROTO_SCTP:
2406 /* enable SCTP checksum offload */
2407 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
2408 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
2409 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2410 break;
2411 case IPPROTO_UDP:
2412 /* enable UDP checksum offload */
2413 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
2414 *td_offset |= (sizeof(struct udphdr) >> 2) <<
2415 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2416 break;
2417 default:
2418 break;
2419 }
2420}
2421
2422/**
2423 * i40e_create_tx_ctx Build the Tx context descriptor
2424 * @tx_ring: ring to create the descriptor on
2425 * @cd_type_cmd_tso_mss: Quad Word 1
2426 * @cd_tunneling: Quad Word 0 - bits 0-31
2427 * @cd_l2tag2: Quad Word 0 - bits 32-63
2428 **/
2429static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
2430 const u64 cd_type_cmd_tso_mss,
2431 const u32 cd_tunneling, const u32 cd_l2tag2)
2432{
2433 struct i40e_tx_context_desc *context_desc;
fc4ac67b 2434 int i = tx_ring->next_to_use;
fd0a05ce 2435
ff40dd5d
JB		 2436 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
2437 !cd_tunneling && !cd_l2tag2)
fd0a05ce
JB		 2438 return;
2439
2440 /* grab the next descriptor */
fc4ac67b
AD		 2441 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
2442
2443 i++;
2444 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
fd0a05ce
JB		 2445
2446 /* cpu_to_le32 and assign to struct fields */
2447 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2448 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3efbbb20 2449 context_desc->rsvd = cpu_to_le16(0);
fd0a05ce
JB		 2450 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2451}
2452
4567dc10
ED		 2453/**
2454 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
2455 * @tx_ring: the ring to be checked
2456 * @size: the size buffer we want to assure is available
2457 *
2458 * Returns -EBUSY if a stop is needed, else 0
2459 **/
2460static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2461{
2462 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2463 /* Memory barrier before checking head and tail */
2464 smp_mb();
2465
2466 /* Check again in a case another CPU has just made room available. */
2467 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
2468 return -EBUSY;
2469
2470 /* A reprieve! - use start_queue because it doesn't call schedule */
2471 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2472 ++tx_ring->tx_stats.restart_queue;
2473 return 0;
2474}
2475
2476/**
2477 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
2478 * @tx_ring: the ring to be checked
2479 * @size: the size buffer we want to assure is available
2480 *
2481 * Returns 0 if stop is not needed
2482 **/
2483#ifdef I40E_FCOE
3e587cf3 2484inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
4567dc10 2485#else
3e587cf3 2486static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
4567dc10
ED		 2487#endif
2488{
2489 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
2490 return 0;
2491 return __i40e_maybe_stop_tx(tx_ring, size);
2492}
2493
71da6197
AS		 2494/**
2495 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
2496 * @skb: send buffer
2497 * @tx_flags: collected send information
71da6197
AS		 2498 *
2499 * Note: Our HW can't scatter-gather more than 8 fragments to build
2500 * a packet on the wire and so we need to figure out the cases where we
2501 * need to linearize the skb.
2502 **/
30520831 2503static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
71da6197
AS		 2504{
2505 struct skb_frag_struct *frag;
2506 bool linearize = false;
2507 unsigned int size = 0;
2508 u16 num_frags;
2509 u16 gso_segs;
2510
2511 num_frags = skb_shinfo(skb)->nr_frags;
2512 gso_segs = skb_shinfo(skb)->gso_segs;
2513
2514 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
30520831 2515 u16 j = 0;
71da6197
AS		 2516
2517 if (num_frags < (I40E_MAX_BUFFER_TXD))
2518 goto linearize_chk_done;
2519 /* try the simple math, if we have too many frags per segment */
2520 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
2521 I40E_MAX_BUFFER_TXD) {
2522 linearize = true;
2523 goto linearize_chk_done;
2524 }
2525 frag = &skb_shinfo(skb)->frags[0];
71da6197
AS		 2526 /* we might still have more fragments per segment */
2527 do {
2528 size += skb_frag_size(frag);
2529 frag++; j++;
30520831
ASJ		 2530 if ((size >= skb_shinfo(skb)->gso_size) &&
2531 (j < I40E_MAX_BUFFER_TXD)) {
2532 size = (size % skb_shinfo(skb)->gso_size);
2533 j = (size) ? 1 : 0;
2534 }
71da6197 2535 if (j == I40E_MAX_BUFFER_TXD) {
30520831
ASJ		 2536 linearize = true;
2537 break;
71da6197
AS		 2538 }
2539 num_frags--;
2540 } while (num_frags);
2541 } else {
2542 if (num_frags >= I40E_MAX_BUFFER_TXD)
2543 linearize = true;
2544 }
2545
2546linearize_chk_done:
2547 return linearize;
2548}
2549
fd0a05ce
JB		 2550/**
2551 * i40e_tx_map - Build the Tx descriptor
2552 * @tx_ring: ring to send buffer on
2553 * @skb: send buffer
2554 * @first: first buffer info buffer to use
2555 * @tx_flags: collected send information
2556 * @hdr_len: size of the packet header
2557 * @td_cmd: the command field in the descriptor
2558 * @td_offset: offset for checksum or crc
2559 **/
38e00438 2560#ifdef I40E_FCOE
3e587cf3 2561inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
fd0a05ce
JB		 2562 struct i40e_tx_buffer *first, u32 tx_flags,
2563 const u8 hdr_len, u32 td_cmd, u32 td_offset)
3e587cf3
JB		 2564#else
2565static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2566 struct i40e_tx_buffer *first, u32 tx_flags,
2567 const u8 hdr_len, u32 td_cmd, u32 td_offset)
38e00438 2568#endif
fd0a05ce 2569{
fd0a05ce
JB		 2570 unsigned int data_len = skb->data_len;
2571 unsigned int size = skb_headlen(skb);
a5e9c572 2572 struct skb_frag_struct *frag;
fd0a05ce
JB		 2573 struct i40e_tx_buffer *tx_bi;
2574 struct i40e_tx_desc *tx_desc;
a5e9c572 2575 u16 i = tx_ring->next_to_use;
fd0a05ce
JB		 2576 u32 td_tag = 0;
2577 dma_addr_t dma;
2578 u16 gso_segs;
58044743
AS		 2579 u16 desc_count = 0;
2580 bool tail_bump = true;
2581 bool do_rs = false;
fd0a05ce 2582
fd0a05ce
JB		 2583 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
2584 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
2585 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
2586 I40E_TX_FLAGS_VLAN_SHIFT;
2587 }
2588
a5e9c572
AD		 2589 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
2590 gso_segs = skb_shinfo(skb)->gso_segs;
2591 else
2592 gso_segs = 1;
2593
2594 /* multiply data chunks by size of headers */
2595 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
2596 first->gso_segs = gso_segs;
2597 first->skb = skb;
2598 first->tx_flags = tx_flags;
2599
2600 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2601
fd0a05ce 2602 tx_desc = I40E_TX_DESC(tx_ring, i);
a5e9c572
AD		 2603 tx_bi = first;
2604
2605 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2606 if (dma_mapping_error(tx_ring->dev, dma))
2607 goto dma_error;
2608
2609 /* record length, and DMA address */
2610 dma_unmap_len_set(tx_bi, len, size);
2611 dma_unmap_addr_set(tx_bi, dma, dma);
2612
2613 tx_desc->buffer_addr = cpu_to_le64(dma);
2614
2615 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
fd0a05ce
JB		 2616 tx_desc->cmd_type_offset_bsz =
2617 build_ctob(td_cmd, td_offset,
2618 I40E_MAX_DATA_PER_TXD, td_tag);
2619
fd0a05ce
JB		 2620 tx_desc++;
2621 i++;
58044743
AS		 2622 desc_count++;
2623
fd0a05ce
JB		 2624 if (i == tx_ring->count) {
2625 tx_desc = I40E_TX_DESC(tx_ring, 0);
2626 i = 0;
2627 }
fd0a05ce 2628
a5e9c572
AD		 2629 dma += I40E_MAX_DATA_PER_TXD;
2630 size -= I40E_MAX_DATA_PER_TXD;
fd0a05ce 2631
a5e9c572
AD		 2632 tx_desc->buffer_addr = cpu_to_le64(dma);
2633 }
fd0a05ce
JB		 2634
2635 if (likely(!data_len))
2636 break;
2637
a5e9c572
AD		 2638 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2639 size, td_tag);
fd0a05ce
JB		 2640
2641 tx_desc++;
2642 i++;
58044743
AS		 2643 desc_count++;
2644
fd0a05ce
JB		 2645 if (i == tx_ring->count) {
2646 tx_desc = I40E_TX_DESC(tx_ring, 0);
2647 i = 0;
2648 }
2649
a5e9c572
AD		 2650 size = skb_frag_size(frag);
2651 data_len -= size;
fd0a05ce 2652
a5e9c572
AD		 2653 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2654 DMA_TO_DEVICE);
fd0a05ce 2655
a5e9c572
AD		 2656 tx_bi = &tx_ring->tx_bi[i];
2657 }
fd0a05ce 2658
a5e9c572
AD		 2659 /* set next_to_watch value indicating a packet is present */
2660 first->next_to_watch = tx_desc;
2661
2662 i++;
2663 if (i == tx_ring->count)
2664 i = 0;
2665
2666 tx_ring->next_to_use = i;
2667
58044743
AS		 2668 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
2669 tx_ring->queue_index),
2670 first->bytecount);
4567dc10 2671 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
58044743
AS		 2672
2673 /* Algorithm to optimize tail and RS bit setting:
2674 * if xmit_more is supported
2675 * if xmit_more is true
2676 * do not update tail and do not mark RS bit.
2677 * if xmit_more is false and last xmit_more was false
2678 * if every packet spanned less than 4 desc
2679 * then set RS bit on 4th packet and update tail
2680 * on every packet
2681 * else
2682 * update tail and set RS bit on every packet.
2683 * if xmit_more is false and last_xmit_more was true
2684 * update tail and set RS bit.
2685 *
2686 * Optimization: wmb to be issued only in case of tail update.
2687 * Also optimize the Descriptor WB path for RS bit with the same
2688 * algorithm.
2689 *
2690 * Note: If there are less than 4 packets
2691 * pending and interrupts were disabled the service task will
2692 * trigger a force WB.
2693 */
2694 if (skb->xmit_more &&
2695 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2696 tx_ring->queue_index))) {
2697 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2698 tail_bump = false;
2699 } else if (!skb->xmit_more &&
2700 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2701 tx_ring->queue_index)) &&
2702 (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
2703 (tx_ring->packet_stride < WB_STRIDE) &&
2704 (desc_count < WB_STRIDE)) {
2705 tx_ring->packet_stride++;
2706 } else {
2707 tx_ring->packet_stride = 0;
2708 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2709 do_rs = true;
2710 }
2711 if (do_rs)
2712 tx_ring->packet_stride = 0;
2713
2714 tx_desc->cmd_type_offset_bsz =
2715 build_ctob(td_cmd, td_offset, size, td_tag) |
2716 cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
2717 I40E_TX_DESC_CMD_EOP) <<
2718 I40E_TXD_QW1_CMD_SHIFT);
2719
a5e9c572 2720 /* notify HW of packet */
58044743 2721 if (!tail_bump)
489ce7a4 2722 prefetchw(tx_desc + 1);
a5e9c572 2723
58044743
AS		 2724 if (tail_bump) {
2725 /* Force memory writes to complete before letting h/w
2726 * know there are new descriptors to fetch. (Only
2727 * applicable for weak-ordered memory model archs,
2728 * such as IA-64).
2729 */
2730 wmb();
2731 writel(i, tx_ring->tail);
2732 }
2733
fd0a05ce
JB		 2734 return;
2735
2736dma_error:
a5e9c572 2737 dev_info(tx_ring->dev, "TX DMA map failed\n");
fd0a05ce
JB		 2738
2739 /* clear dma mappings for failed tx_bi map */
2740 for (;;) {
2741 tx_bi = &tx_ring->tx_bi[i];
a5e9c572 2742 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
fd0a05ce
JB		 2743 if (tx_bi == first)
2744 break;
2745 if (i == 0)
2746 i = tx_ring->count;
2747 i--;
2748 }
2749
fd0a05ce
JB		 2750 tx_ring->next_to_use = i;
2751}
2752
fd0a05ce
JB		 2753/**
2754 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
2755 * @skb: send buffer
2756 * @tx_ring: ring to send buffer on
2757 *
2758 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
2759 * there is not enough descriptors available in this ring since we need at least
2760 * one descriptor.
2761 **/
38e00438 2762#ifdef I40E_FCOE
3e587cf3 2763inline int i40e_xmit_descriptor_count(struct sk_buff *skb,
fd0a05ce 2764 struct i40e_ring *tx_ring)
3e587cf3
JB		 2765#else
2766static inline int i40e_xmit_descriptor_count(struct sk_buff *skb,
2767 struct i40e_ring *tx_ring)
38e00438 2768#endif
fd0a05ce 2769{
fd0a05ce 2770 unsigned int f;
fd0a05ce
JB		 2771 int count = 0;
2772
2773 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2774 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
be560521 2775 * + 4 desc gap to avoid the cache line where head is,
fd0a05ce
JB		 2776 * + 1 desc for context descriptor,
2777 * otherwise try next time
2778 */
fd0a05ce
JB		 2779 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
2780 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
980093eb 2781
fd0a05ce 2782 count += TXD_USE_COUNT(skb_headlen(skb));
be560521 2783 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
fd0a05ce
JB		 2784 tx_ring->tx_stats.tx_busy++;
2785 return 0;
2786 }
2787 return count;
2788}
2789
2790/**
2791 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2792 * @skb: send buffer
2793 * @tx_ring: ring to send buffer on
2794 *
2795 * Returns NETDEV_TX_OK if sent, else an error code
2796 **/
2797static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2798 struct i40e_ring *tx_ring)
2799{
2800 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2801 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2802 struct i40e_tx_buffer *first;
2803 u32 td_offset = 0;
2804 u32 tx_flags = 0;
2805 __be16 protocol;
2806 u32 td_cmd = 0;
2807 u8 hdr_len = 0;
beb0dff1 2808 int tsyn;
fd0a05ce 2809 int tso;
6995b36c 2810
b74118f0
JB		 2811 /* prefetch the data, we'll need it later */
2812 prefetch(skb->data);
2813
fd0a05ce
JB		 2814 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
2815 return NETDEV_TX_BUSY;
2816
2817 /* prepare the xmit flags */
2818 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2819 goto out_drop;
2820
2821 /* obtain protocol of skb */
3d34dd03 2822 protocol = vlan_get_protocol(skb);
fd0a05ce
JB		 2823
2824 /* record the location of the first descriptor for this packet */
2825 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2826
2827 /* setup IPv4/IPv6 offloads */
0e2fe46c 2828 if (protocol == htons(ETH_P_IP))
fd0a05ce 2829 tx_flags |= I40E_TX_FLAGS_IPV4;
0e2fe46c 2830 else if (protocol == htons(ETH_P_IPV6))
fd0a05ce
JB		 2831 tx_flags |= I40E_TX_FLAGS_IPV6;
2832
9c883bd3 2833 tso = i40e_tso(tx_ring, skb, &hdr_len, &cd_type_cmd_tso_mss);
fd0a05ce
JB		 2834
2835 if (tso < 0)
2836 goto out_drop;
2837 else if (tso)
2838 tx_flags |= I40E_TX_FLAGS_TSO;
2839
beb0dff1
JK		 2840 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
2841
2842 if (tsyn)
2843 tx_flags |= I40E_TX_FLAGS_TSYN;
2844
2fc3d715 2845 if (i40e_chk_linearize(skb, tx_flags)) {
71da6197
AS		 2846 if (skb_linearize(skb))
2847 goto out_drop;
2fc3d715
ASJ		 2848 tx_ring->tx_stats.tx_linearize++;
2849 }
259afec7
JK		 2850 skb_tx_timestamp(skb);
2851
b1941306
AD		 2852 /* always enable CRC insertion offload */
2853 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2854
fd0a05ce 2855 /* Always offload the checksum, since it's in the data descriptor */
b1941306 2856 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fd0a05ce
JB		 2857 tx_flags |= I40E_TX_FLAGS_CSUM;
2858
89232c3b 2859 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
fd0a05ce 2860 tx_ring, &cd_tunneling);
b1941306 2861 }
fd0a05ce
JB		 2862
2863 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2864 cd_tunneling, cd_l2tag2);
2865
2866 /* Add Flow Director ATR if it's enabled.
2867 *
2868 * NOTE: this must always be directly before the data descriptor.
2869 */
2870 i40e_atr(tx_ring, skb, tx_flags, protocol);
2871
2872 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2873 td_cmd, td_offset);
2874
fd0a05ce
JB		 2875 return NETDEV_TX_OK;
2876
2877out_drop:
2878 dev_kfree_skb_any(skb);
2879 return NETDEV_TX_OK;
2880}
2881
2882/**
2883 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2884 * @skb: send buffer
2885 * @netdev: network interface device structure
2886 *
2887 * Returns NETDEV_TX_OK if sent, else an error code
2888 **/
2889netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2890{
2891 struct i40e_netdev_priv *np = netdev_priv(netdev);
2892 struct i40e_vsi *vsi = np->vsi;
9f65e15b 2893 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
fd0a05ce
JB		 2894
2895 /* hardware can't handle really short frames, hardware padding works
2896 * beyond this point
2897 */
a94d9e22
AD		 2898 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
2899 return NETDEV_TX_OK;
fd0a05ce
JB		 2900
2901 return i40e_xmit_frame_ring(skb, tx_ring);
2902}
Linux 6.x block layer and io_uring tree(s)