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i40e/i40evf: refactor IRQ enable function
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_txrx.c
CommitLineData
fd0a05ce
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
fd0a05ce
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
fd0a05ce
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
1c112a64 27#include <linux/prefetch.h>
a132af24 28#include <net/busy_poll.h>
fd0a05ce 29#include "i40e.h"
206812b5 30#include "i40e_prototype.h"
fd0a05ce
JB		 31
32static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
33 u32 td_tag)
34{
35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
40}
41
eaefbd06 42#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
49d7d933 43#define I40E_FD_CLEAN_DELAY 10
fd0a05ce
JB		 44/**
45 * i40e_program_fdir_filter - Program a Flow Director filter
17a73f6b
JG		 46 * @fdir_data: Packet data that will be filter parameters
47 * @raw_packet: the pre-allocated packet buffer for FDir
b40c82e6 48 * @pf: The PF pointer
fd0a05ce
JB		 49 * @add: True for add/update, False for remove
50 **/
17a73f6b 51int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
fd0a05ce
JB		 52 struct i40e_pf *pf, bool add)
53{
54 struct i40e_filter_program_desc *fdir_desc;
49d7d933 55 struct i40e_tx_buffer *tx_buf, *first;
fd0a05ce
JB		 56 struct i40e_tx_desc *tx_desc;
57 struct i40e_ring *tx_ring;
eaefbd06 58 unsigned int fpt, dcc;
fd0a05ce
JB		 59 struct i40e_vsi *vsi;
60 struct device *dev;
61 dma_addr_t dma;
62 u32 td_cmd = 0;
49d7d933 63 u16 delay = 0;
fd0a05ce
JB		 64 u16 i;
65
66 /* find existing FDIR VSI */
67 vsi = NULL;
505682cd 68 for (i = 0; i < pf->num_alloc_vsi; i++)
fd0a05ce
JB		 69 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
70 vsi = pf->vsi[i];
71 if (!vsi)
72 return -ENOENT;
73
9f65e15b 74 tx_ring = vsi->tx_rings[0];
fd0a05ce
JB		 75 dev = tx_ring->dev;
76
49d7d933
ASJ		 77 /* we need two descriptors to add/del a filter and we can wait */
78 do {
79 if (I40E_DESC_UNUSED(tx_ring) > 1)
80 break;
81 msleep_interruptible(1);
82 delay++;
83 } while (delay < I40E_FD_CLEAN_DELAY);
84
85 if (!(I40E_DESC_UNUSED(tx_ring) > 1))
86 return -EAGAIN;
87
17a73f6b
JG		 88 dma = dma_map_single(dev, raw_packet,
89 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
fd0a05ce
JB		 90 if (dma_mapping_error(dev, dma))
91 goto dma_fail;
92
93 /* grab the next descriptor */
fc4ac67b
AD		 94 i = tx_ring->next_to_use;
95 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
49d7d933
ASJ		 96 first = &tx_ring->tx_bi[i];
97 memset(first, 0, sizeof(struct i40e_tx_buffer));
fc4ac67b 98
49d7d933 99 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
fd0a05ce 100
eaefbd06
JB		 101 fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
102 I40E_TXD_FLTR_QW0_QINDEX_MASK;
fd0a05ce 103
eaefbd06
JB		 104 fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
105 I40E_TXD_FLTR_QW0_FLEXOFF_MASK;
fd0a05ce 106
eaefbd06
JB		 107 fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
108 I40E_TXD_FLTR_QW0_PCTYPE_MASK;
fd0a05ce
JB		 109
110 /* Use LAN VSI Id if not programmed by user */
111 if (fdir_data->dest_vsi == 0)
eaefbd06
JB		 112 fpt |= (pf->vsi[pf->lan_vsi]->id) <<
113 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
fd0a05ce 114 else
eaefbd06
JB		 115 fpt |= ((u32)fdir_data->dest_vsi <<
116 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
117 I40E_TXD_FLTR_QW0_DEST_VSI_MASK;
118
eaefbd06 119 dcc = I40E_TX_DESC_DTYPE_FILTER_PROG;
fd0a05ce
JB		 120
121 if (add)
eaefbd06
JB		 122 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
123 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
fd0a05ce 124 else
eaefbd06
JB		 125 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
126 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
fd0a05ce 127
eaefbd06
JB		 128 dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) &
129 I40E_TXD_FLTR_QW1_DEST_MASK;
fd0a05ce 130
eaefbd06
JB		 131 dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
132 I40E_TXD_FLTR_QW1_FD_STATUS_MASK;
fd0a05ce
JB		 133
134 if (fdir_data->cnt_index != 0) {
eaefbd06
JB		 135 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
136 dcc |= ((u32)fdir_data->cnt_index <<
137 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
433c47de 138 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
fd0a05ce
JB		 139 }
140
99753ea6
JB		 141 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt);
142 fdir_desc->rsvd = cpu_to_le32(0);
eaefbd06 143 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc);
fd0a05ce
JB		 144 fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id);
145
146 /* Now program a dummy descriptor */
fc4ac67b
AD		 147 i = tx_ring->next_to_use;
148 tx_desc = I40E_TX_DESC(tx_ring, i);
298deef1 149 tx_buf = &tx_ring->tx_bi[i];
fc4ac67b 150
49d7d933
ASJ		 151 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
152
153 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
fd0a05ce 154
298deef1 155 /* record length, and DMA address */
17a73f6b 156 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
298deef1
ASJ		 157 dma_unmap_addr_set(tx_buf, dma, dma);
158
fd0a05ce 159 tx_desc->buffer_addr = cpu_to_le64(dma);
eaefbd06 160 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
fd0a05ce 161
49d7d933
ASJ		 162 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
163 tx_buf->raw_buf = (void *)raw_packet;
164
fd0a05ce 165 tx_desc->cmd_type_offset_bsz =
17a73f6b 166 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
fd0a05ce 167
fd0a05ce 168 /* Force memory writes to complete before letting h/w
49d7d933 169 * know there are new descriptors to fetch.
fd0a05ce
JB		 170 */
171 wmb();
172
fc4ac67b 173 /* Mark the data descriptor to be watched */
49d7d933 174 first->next_to_watch = tx_desc;
fc4ac67b 175
fd0a05ce
JB		 176 writel(tx_ring->next_to_use, tx_ring->tail);
177 return 0;
178
179dma_fail:
180 return -1;
181}
182
17a73f6b
JG		 183#define IP_HEADER_OFFSET 14
184#define I40E_UDPIP_DUMMY_PACKET_LEN 42
185/**
186 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
187 * @vsi: pointer to the targeted VSI
188 * @fd_data: the flow director data required for the FDir descriptor
17a73f6b
JG		 189 * @add: true adds a filter, false removes it
190 *
191 * Returns 0 if the filters were successfully added or removed
192 **/
193static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
194 struct i40e_fdir_filter *fd_data,
49d7d933 195 bool add)
17a73f6b
JG		 196{
197 struct i40e_pf *pf = vsi->back;
198 struct udphdr *udp;
199 struct iphdr *ip;
200 bool err = false;
49d7d933 201 u8 *raw_packet;
17a73f6b 202 int ret;
17a73f6b
JG		 203 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
204 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
206
49d7d933
ASJ		 207 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
208 if (!raw_packet)
209 return -ENOMEM;
17a73f6b
JG		 210 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
211
212 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
213 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
214 + sizeof(struct iphdr));
215
216 ip->daddr = fd_data->dst_ip[0];
217 udp->dest = fd_data->dst_port;
218 ip->saddr = fd_data->src_ip[0];
219 udp->source = fd_data->src_port;
220
b2d36c03
KS		 221 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
222 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
223 if (ret) {
224 dev_info(&pf->pdev->dev,
e99bdd39
CW		 225 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
226 fd_data->pctype, fd_data->fd_id, ret);
b2d36c03 227 err = true;
4205d379 228 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
f7233c54
ASJ		 229 if (add)
230 dev_info(&pf->pdev->dev,
231 "Filter OK for PCTYPE %d loc = %d\n",
232 fd_data->pctype, fd_data->fd_id);
233 else
234 dev_info(&pf->pdev->dev,
235 "Filter deleted for PCTYPE %d loc = %d\n",
236 fd_data->pctype, fd_data->fd_id);
17a73f6b 237 }
17a73f6b
JG		 238 return err ? -EOPNOTSUPP : 0;
239}
240
241#define I40E_TCPIP_DUMMY_PACKET_LEN 54
242/**
243 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
244 * @vsi: pointer to the targeted VSI
245 * @fd_data: the flow director data required for the FDir descriptor
17a73f6b
JG		 246 * @add: true adds a filter, false removes it
247 *
248 * Returns 0 if the filters were successfully added or removed
249 **/
250static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
251 struct i40e_fdir_filter *fd_data,
49d7d933 252 bool add)
17a73f6b
JG		 253{
254 struct i40e_pf *pf = vsi->back;
255 struct tcphdr *tcp;
256 struct iphdr *ip;
257 bool err = false;
49d7d933 258 u8 *raw_packet;
17a73f6b
JG		 259 int ret;
260 /* Dummy packet */
261 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
262 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
264 0x0, 0x72, 0, 0, 0, 0};
265
49d7d933
ASJ		 266 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
267 if (!raw_packet)
268 return -ENOMEM;
17a73f6b
JG		 269 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
270
271 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
272 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
273 + sizeof(struct iphdr));
274
275 ip->daddr = fd_data->dst_ip[0];
276 tcp->dest = fd_data->dst_port;
277 ip->saddr = fd_data->src_ip[0];
278 tcp->source = fd_data->src_port;
279
280 if (add) {
1e1be8f6 281 pf->fd_tcp_rule++;
17a73f6b 282 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) {
2e4875e3
ASJ		 283 if (I40E_DEBUG_FD & pf->hw.debug_mask)
284 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
17a73f6b
JG		 285 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
286 }
1e1be8f6
ASJ		 287 } else {
288 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ?
289 (pf->fd_tcp_rule - 1) : 0;
290 if (pf->fd_tcp_rule == 0) {
291 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 292 if (I40E_DEBUG_FD & pf->hw.debug_mask)
293 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n");
1e1be8f6 294 }
17a73f6b
JG		 295 }
296
b2d36c03 297 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
17a73f6b
JG		 298 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
299
300 if (ret) {
301 dev_info(&pf->pdev->dev,
e99bdd39
CW		 302 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
303 fd_data->pctype, fd_data->fd_id, ret);
17a73f6b 304 err = true;
4205d379 305 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
f7233c54
ASJ		 306 if (add)
307 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
308 fd_data->pctype, fd_data->fd_id);
309 else
310 dev_info(&pf->pdev->dev,
311 "Filter deleted for PCTYPE %d loc = %d\n",
312 fd_data->pctype, fd_data->fd_id);
17a73f6b
JG		 313 }
314
17a73f6b
JG		 315 return err ? -EOPNOTSUPP : 0;
316}
317
318/**
319 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
320 * a specific flow spec
321 * @vsi: pointer to the targeted VSI
322 * @fd_data: the flow director data required for the FDir descriptor
17a73f6b
JG		 323 * @add: true adds a filter, false removes it
324 *
21d3efdc 325 * Always returns -EOPNOTSUPP
17a73f6b
JG		 326 **/
327static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
328 struct i40e_fdir_filter *fd_data,
49d7d933 329 bool add)
17a73f6b
JG		 330{
331 return -EOPNOTSUPP;
332}
333
334#define I40E_IP_DUMMY_PACKET_LEN 34
335/**
336 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
337 * a specific flow spec
338 * @vsi: pointer to the targeted VSI
339 * @fd_data: the flow director data required for the FDir descriptor
17a73f6b
JG		 340 * @add: true adds a filter, false removes it
341 *
342 * Returns 0 if the filters were successfully added or removed
343 **/
344static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
345 struct i40e_fdir_filter *fd_data,
49d7d933 346 bool add)
17a73f6b
JG		 347{
348 struct i40e_pf *pf = vsi->back;
349 struct iphdr *ip;
350 bool err = false;
49d7d933 351 u8 *raw_packet;
17a73f6b
JG		 352 int ret;
353 int i;
354 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
355 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
356 0, 0, 0, 0};
357
17a73f6b
JG		 358 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
359 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
49d7d933
ASJ		 360 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
361 if (!raw_packet)
362 return -ENOMEM;
363 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
364 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
365
366 ip->saddr = fd_data->src_ip[0];
367 ip->daddr = fd_data->dst_ip[0];
368 ip->protocol = 0;
369
17a73f6b
JG		 370 fd_data->pctype = i;
371 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
372
373 if (ret) {
374 dev_info(&pf->pdev->dev,
e99bdd39
CW		 375 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
376 fd_data->pctype, fd_data->fd_id, ret);
17a73f6b 377 err = true;
4205d379 378 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
f7233c54
ASJ		 379 if (add)
380 dev_info(&pf->pdev->dev,
381 "Filter OK for PCTYPE %d loc = %d\n",
382 fd_data->pctype, fd_data->fd_id);
383 else
384 dev_info(&pf->pdev->dev,
385 "Filter deleted for PCTYPE %d loc = %d\n",
386 fd_data->pctype, fd_data->fd_id);
17a73f6b
JG		 387 }
388 }
389
390 return err ? -EOPNOTSUPP : 0;
391}
392
393/**
394 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
395 * @vsi: pointer to the targeted VSI
396 * @cmd: command to get or set RX flow classification rules
397 * @add: true adds a filter, false removes it
398 *
399 **/
400int i40e_add_del_fdir(struct i40e_vsi *vsi,
401 struct i40e_fdir_filter *input, bool add)
402{
403 struct i40e_pf *pf = vsi->back;
17a73f6b
JG		 404 int ret;
405
17a73f6b
JG		 406 switch (input->flow_type & ~FLOW_EXT) {
407 case TCP_V4_FLOW:
49d7d933 408 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
17a73f6b
JG		 409 break;
410 case UDP_V4_FLOW:
49d7d933 411 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
17a73f6b
JG		 412 break;
413 case SCTP_V4_FLOW:
49d7d933 414 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
17a73f6b
JG		 415 break;
416 case IPV4_FLOW:
49d7d933 417 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
17a73f6b
JG		 418 break;
419 case IP_USER_FLOW:
420 switch (input->ip4_proto) {
421 case IPPROTO_TCP:
49d7d933 422 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
17a73f6b
JG		 423 break;
424 case IPPROTO_UDP:
49d7d933 425 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
17a73f6b
JG		 426 break;
427 case IPPROTO_SCTP:
49d7d933 428 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
17a73f6b
JG		 429 break;
430 default:
49d7d933 431 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
17a73f6b
JG		 432 break;
433 }
434 break;
435 default:
c5ffe7e1 436 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n",
17a73f6b
JG		 437 input->flow_type);
438 ret = -EINVAL;
439 }
440
49d7d933 441 /* The buffer allocated here is freed by the i40e_clean_tx_ring() */
17a73f6b
JG		 442 return ret;
443}
444
fd0a05ce
JB		 445/**
446 * i40e_fd_handle_status - check the Programming Status for FD
447 * @rx_ring: the Rx ring for this descriptor
55a5e60b 448 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
fd0a05ce
JB		 449 * @prog_id: the id originally used for programming
450 *
451 * This is used to verify if the FD programming or invalidation
452 * requested by SW to the HW is successful or not and take actions accordingly.
453 **/
55a5e60b
ASJ		 454static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
455 union i40e_rx_desc *rx_desc, u8 prog_id)
fd0a05ce 456{
55a5e60b
ASJ		 457 struct i40e_pf *pf = rx_ring->vsi->back;
458 struct pci_dev *pdev = pf->pdev;
459 u32 fcnt_prog, fcnt_avail;
fd0a05ce 460 u32 error;
55a5e60b 461 u64 qw;
fd0a05ce 462
55a5e60b 463 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
fd0a05ce
JB		 464 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
465 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
466
41a1d04b 467 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
3487b6c3 468 pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id);
f7233c54
ASJ		 469 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
470 (I40E_DEBUG_FD & pf->hw.debug_mask))
471 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
3487b6c3 472 pf->fd_inv);
55a5e60b 473
04294e38
ASJ		 474 /* Check if the programming error is for ATR.
475 * If so, auto disable ATR and set a state for
476 * flush in progress. Next time we come here if flush is in
477 * progress do nothing, once flush is complete the state will
478 * be cleared.
479 */
480 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
481 return;
482
1e1be8f6
ASJ		 483 pf->fd_add_err++;
484 /* store the current atr filter count */
485 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
486
04294e38
ASJ		 487 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) &&
488 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
489 pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED;
490 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
491 }
492
55a5e60b 493 /* filter programming failed most likely due to table full */
04294e38 494 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 495 fcnt_avail = pf->fdir_pf_filter_count;
55a5e60b
ASJ		 496 /* If ATR is running fcnt_prog can quickly change,
497 * if we are very close to full, it makes sense to disable
498 * FD ATR/SB and then re-enable it when there is room.
499 */
500 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
1e1be8f6 501 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
b814ba65 502 !(pf->auto_disable_flags &
b814ba65 503 I40E_FLAG_FD_SB_ENABLED)) {
2e4875e3
ASJ		 504 if (I40E_DEBUG_FD & pf->hw.debug_mask)
505 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
55a5e60b
ASJ		 506 pf->auto_disable_flags |=
507 I40E_FLAG_FD_SB_ENABLED;
55a5e60b
ASJ		 508 }
509 } else {
e99bdd39 510 dev_info(&pdev->dev,
f7233c54 511 "FD filter programming failed due to incorrect filter parameters\n");
55a5e60b 512 }
41a1d04b 513 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
13c2884f 514 if (I40E_DEBUG_FD & pf->hw.debug_mask)
e99bdd39 515 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
13c2884f 516 rx_desc->wb.qword0.hi_dword.fd_id);
55a5e60b 517 }
fd0a05ce
JB		 518}
519
520/**
a5e9c572 521 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
fd0a05ce
JB		 522 * @ring: the ring that owns the buffer
523 * @tx_buffer: the buffer to free
524 **/
a5e9c572
AD		 525static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
526 struct i40e_tx_buffer *tx_buffer)
fd0a05ce 527{
a5e9c572 528 if (tx_buffer->skb) {
49d7d933
ASJ		 529 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
530 kfree(tx_buffer->raw_buf);
531 else
532 dev_kfree_skb_any(tx_buffer->skb);
533
a5e9c572 534 if (dma_unmap_len(tx_buffer, len))
fd0a05ce 535 dma_unmap_single(ring->dev,
35a1e2ad
AD		 536 dma_unmap_addr(tx_buffer, dma),
537 dma_unmap_len(tx_buffer, len),
fd0a05ce 538 DMA_TO_DEVICE);
a5e9c572
AD		 539 } else if (dma_unmap_len(tx_buffer, len)) {
540 dma_unmap_page(ring->dev,
541 dma_unmap_addr(tx_buffer, dma),
542 dma_unmap_len(tx_buffer, len),
543 DMA_TO_DEVICE);
fd0a05ce 544 }
a5e9c572
AD		 545 tx_buffer->next_to_watch = NULL;
546 tx_buffer->skb = NULL;
35a1e2ad 547 dma_unmap_len_set(tx_buffer, len, 0);
a5e9c572 548 /* tx_buffer must be completely set up in the transmit path */
fd0a05ce
JB		 549}
550
551/**
552 * i40e_clean_tx_ring - Free any empty Tx buffers
553 * @tx_ring: ring to be cleaned
554 **/
555void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
556{
fd0a05ce
JB		 557 unsigned long bi_size;
558 u16 i;
559
560 /* ring already cleared, nothing to do */
561 if (!tx_ring->tx_bi)
562 return;
563
564 /* Free all the Tx ring sk_buffs */
a5e9c572
AD		 565 for (i = 0; i < tx_ring->count; i++)
566 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
fd0a05ce
JB		 567
568 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
569 memset(tx_ring->tx_bi, 0, bi_size);
570
571 /* Zero out the descriptor ring */
572 memset(tx_ring->desc, 0, tx_ring->size);
573
574 tx_ring->next_to_use = 0;
575 tx_ring->next_to_clean = 0;
7070ce0a
AD		 576
577 if (!tx_ring->netdev)
578 return;
579
580 /* cleanup Tx queue statistics */
581 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
582 tx_ring->queue_index));
fd0a05ce
JB		 583}
584
585/**
586 * i40e_free_tx_resources - Free Tx resources per queue
587 * @tx_ring: Tx descriptor ring for a specific queue
588 *
589 * Free all transmit software resources
590 **/
591void i40e_free_tx_resources(struct i40e_ring *tx_ring)
592{
593 i40e_clean_tx_ring(tx_ring);
594 kfree(tx_ring->tx_bi);
595 tx_ring->tx_bi = NULL;
596
597 if (tx_ring->desc) {
598 dma_free_coherent(tx_ring->dev, tx_ring->size,
599 tx_ring->desc, tx_ring->dma);
600 tx_ring->desc = NULL;
601 }
602}
603
604/**
605 * i40e_get_tx_pending - how many tx descriptors not processed
606 * @tx_ring: the ring of descriptors
607 *
608 * Since there is no access to the ring head register
609 * in XL710, we need to use our local copies
610 **/
b03a8c1f 611u32 i40e_get_tx_pending(struct i40e_ring *ring)
fd0a05ce 612{
a68de58d
JB		 613 u32 head, tail;
614
615 head = i40e_get_head(ring);
616 tail = readl(ring->tail);
617
618 if (head != tail)
619 return (head < tail) ?
620 tail - head : (tail + ring->count - head);
621
622 return 0;
fd0a05ce
JB		 623}
624
d91649f5
JB		 625#define WB_STRIDE 0x3
626
fd0a05ce
JB		 627/**
628 * i40e_clean_tx_irq - Reclaim resources after transmit completes
629 * @tx_ring: tx ring to clean
630 * @budget: how many cleans we're allowed
631 *
632 * Returns true if there's any budget left (e.g. the clean is finished)
633 **/
634static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
635{
636 u16 i = tx_ring->next_to_clean;
637 struct i40e_tx_buffer *tx_buf;
1943d8ba 638 struct i40e_tx_desc *tx_head;
fd0a05ce
JB		 639 struct i40e_tx_desc *tx_desc;
640 unsigned int total_packets = 0;
641 unsigned int total_bytes = 0;
642
643 tx_buf = &tx_ring->tx_bi[i];
644 tx_desc = I40E_TX_DESC(tx_ring, i);
a5e9c572 645 i -= tx_ring->count;
fd0a05ce 646
1943d8ba
JB		 647 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
648
a5e9c572
AD		 649 do {
650 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
fd0a05ce
JB		 651
652 /* if next_to_watch is not set then there is no work pending */
653 if (!eop_desc)
654 break;
655
a5e9c572
AD		 656 /* prevent any other reads prior to eop_desc */
657 read_barrier_depends();
658
1943d8ba
JB		 659 /* we have caught up to head, no work left to do */
660 if (tx_head == tx_desc)
fd0a05ce
JB		 661 break;
662
c304fdac 663 /* clear next_to_watch to prevent false hangs */
fd0a05ce 664 tx_buf->next_to_watch = NULL;
fd0a05ce 665
a5e9c572
AD		 666 /* update the statistics for this packet */
667 total_bytes += tx_buf->bytecount;
668 total_packets += tx_buf->gso_segs;
fd0a05ce 669
a5e9c572 670 /* free the skb */
a81fb049 671 dev_consume_skb_any(tx_buf->skb);
fd0a05ce 672
a5e9c572
AD		 673 /* unmap skb header data */
674 dma_unmap_single(tx_ring->dev,
675 dma_unmap_addr(tx_buf, dma),
676 dma_unmap_len(tx_buf, len),
677 DMA_TO_DEVICE);
fd0a05ce 678
a5e9c572
AD		 679 /* clear tx_buffer data */
680 tx_buf->skb = NULL;
681 dma_unmap_len_set(tx_buf, len, 0);
fd0a05ce 682
a5e9c572
AD		 683 /* unmap remaining buffers */
684 while (tx_desc != eop_desc) {
fd0a05ce
JB		 685
686 tx_buf++;
687 tx_desc++;
688 i++;
a5e9c572
AD		 689 if (unlikely(!i)) {
690 i -= tx_ring->count;
fd0a05ce
JB		 691 tx_buf = tx_ring->tx_bi;
692 tx_desc = I40E_TX_DESC(tx_ring, 0);
693 }
fd0a05ce 694
a5e9c572
AD		 695 /* unmap any remaining paged data */
696 if (dma_unmap_len(tx_buf, len)) {
697 dma_unmap_page(tx_ring->dev,
698 dma_unmap_addr(tx_buf, dma),
699 dma_unmap_len(tx_buf, len),
700 DMA_TO_DEVICE);
701 dma_unmap_len_set(tx_buf, len, 0);
702 }
703 }
704
705 /* move us one more past the eop_desc for start of next pkt */
706 tx_buf++;
707 tx_desc++;
708 i++;
709 if (unlikely(!i)) {
710 i -= tx_ring->count;
711 tx_buf = tx_ring->tx_bi;
712 tx_desc = I40E_TX_DESC(tx_ring, 0);
713 }
714
016890b9
JB		 715 prefetch(tx_desc);
716
a5e9c572
AD		 717 /* update budget accounting */
718 budget--;
719 } while (likely(budget));
720
721 i += tx_ring->count;
fd0a05ce 722 tx_ring->next_to_clean = i;
980e9b11 723 u64_stats_update_begin(&tx_ring->syncp);
a114d0a6
AD		 724 tx_ring->stats.bytes += total_bytes;
725 tx_ring->stats.packets += total_packets;
980e9b11 726 u64_stats_update_end(&tx_ring->syncp);
fd0a05ce
JB		 727 tx_ring->q_vector->tx.total_bytes += total_bytes;
728 tx_ring->q_vector->tx.total_packets += total_packets;
a5e9c572 729
58044743
AS		 730 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
731 unsigned int j = 0;
732
733 /* check to see if there are < 4 descriptors
734 * waiting to be written back, then kick the hardware to force
735 * them to be written back in case we stay in NAPI.
736 * In this mode on X722 we do not enable Interrupt.
737 */
738 j = i40e_get_tx_pending(tx_ring);
739
740 if (budget &&
741 ((j / (WB_STRIDE + 1)) == 0) && (j != 0) &&
742 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
743 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
744 tx_ring->arm_wb = true;
745 }
d91649f5 746
7070ce0a
AD		 747 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
748 tx_ring->queue_index),
749 total_packets, total_bytes);
750
fd0a05ce
JB		 751#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
752 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
753 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
754 /* Make sure that anybody stopping the queue after this
755 * sees the new next_to_clean.
756 */
757 smp_mb();
758 if (__netif_subqueue_stopped(tx_ring->netdev,
759 tx_ring->queue_index) &&
760 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
761 netif_wake_subqueue(tx_ring->netdev,
762 tx_ring->queue_index);
763 ++tx_ring->tx_stats.restart_queue;
764 }
765 }
766
d91649f5
JB		 767 return !!budget;
768}
769
770/**
771 * i40e_force_wb - Arm hardware to do a wb on noncache aligned descriptors
772 * @vsi: the VSI we care about
773 * @q_vector: the vector on which to force writeback
774 *
775 **/
b03a8c1f 776void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
d91649f5 777{
8e0764b4
ASJ		 778 u16 flags = q_vector->tx.ring[0].flags;
779
780 if (flags & I40E_TXR_FLAGS_WB_ON_ITR) {
781 u32 val;
782
783 if (q_vector->arm_wb_state)
784 return;
785
786 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK;
787
788 wr32(&vsi->back->hw,
789 I40E_PFINT_DYN_CTLN(q_vector->v_idx +
790 vsi->base_vector - 1),
791 val);
792 q_vector->arm_wb_state = true;
793 } else if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
794 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
795 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
796 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
797 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
798 /* allow 00 to be written to the index */
799
800 wr32(&vsi->back->hw,
801 I40E_PFINT_DYN_CTLN(q_vector->v_idx +
802 vsi->base_vector - 1), val);
803 } else {
804 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
805 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
806 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
807 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
808 /* allow 00 to be written to the index */
809
810 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
811 }
fd0a05ce
JB		 812}
813
814/**
815 * i40e_set_new_dynamic_itr - Find new ITR level
816 * @rc: structure containing ring performance data
817 *
8f5e39ce
JB		 818 * Returns true if ITR changed, false if not
819 *
fd0a05ce
JB		 820 * Stores a new ITR value based on packets and byte counts during
821 * the last interrupt. The advantage of per interrupt computation
822 * is faster updates and more accurate ITR for the current traffic
823 * pattern. Constants in this function were computed based on
824 * theoretical maximum wire speed and thresholds were set based on
825 * testing data as well as attempting to minimize response time
826 * while increasing bulk throughput.
827 **/
8f5e39ce 828static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
fd0a05ce
JB		 829{
830 enum i40e_latency_range new_latency_range = rc->latency_range;
831 u32 new_itr = rc->itr;
832 int bytes_per_int;
833
834 if (rc->total_packets == 0 || !rc->itr)
8f5e39ce 835 return false;
fd0a05ce
JB		 836
837 /* simple throttlerate management
838 * 0-10MB/s lowest (100000 ints/s)
839 * 10-20MB/s low (20000 ints/s)
840 * 20-1249MB/s bulk (8000 ints/s)
841 */
842 bytes_per_int = rc->total_bytes / rc->itr;
de32e3ef 843 switch (new_latency_range) {
fd0a05ce
JB		 844 case I40E_LOWEST_LATENCY:
845 if (bytes_per_int > 10)
846 new_latency_range = I40E_LOW_LATENCY;
847 break;
848 case I40E_LOW_LATENCY:
849 if (bytes_per_int > 20)
850 new_latency_range = I40E_BULK_LATENCY;
851 else if (bytes_per_int <= 10)
852 new_latency_range = I40E_LOWEST_LATENCY;
853 break;
854 case I40E_BULK_LATENCY:
855 if (bytes_per_int <= 20)
de32e3ef
CW		 856 new_latency_range = I40E_LOW_LATENCY;
857 break;
858 default:
859 if (bytes_per_int <= 20)
860 new_latency_range = I40E_LOW_LATENCY;
fd0a05ce
JB		 861 break;
862 }
de32e3ef 863 rc->latency_range = new_latency_range;
fd0a05ce
JB		 864
865 switch (new_latency_range) {
866 case I40E_LOWEST_LATENCY:
867 new_itr = I40E_ITR_100K;
868 break;
869 case I40E_LOW_LATENCY:
870 new_itr = I40E_ITR_20K;
871 break;
872 case I40E_BULK_LATENCY:
873 new_itr = I40E_ITR_8K;
874 break;
875 default:
876 break;
877 }
878
fd0a05ce
JB		 879 rc->total_bytes = 0;
880 rc->total_packets = 0;
8f5e39ce
JB		 881
882 if (new_itr != rc->itr) {
883 rc->itr = new_itr;
884 return true;
885 }
886
887 return false;
fd0a05ce
JB		 888}
889
fd0a05ce
JB		 890/**
891 * i40e_clean_programming_status - clean the programming status descriptor
892 * @rx_ring: the rx ring that has this descriptor
893 * @rx_desc: the rx descriptor written back by HW
894 *
895 * Flow director should handle FD_FILTER_STATUS to check its filter programming
896 * status being successful or not and take actions accordingly. FCoE should
897 * handle its context/filter programming/invalidation status and take actions.
898 *
899 **/
900static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
901 union i40e_rx_desc *rx_desc)
902{
903 u64 qw;
904 u8 id;
905
906 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
907 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
908 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
909
910 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
55a5e60b 911 i40e_fd_handle_status(rx_ring, rx_desc, id);
38e00438
VD		 912#ifdef I40E_FCOE
913 else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) ||
914 (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS))
915 i40e_fcoe_handle_status(rx_ring, rx_desc, id);
916#endif
fd0a05ce
JB		 917}
918
919/**
920 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
921 * @tx_ring: the tx ring to set up
922 *
923 * Return 0 on success, negative on error
924 **/
925int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
926{
927 struct device *dev = tx_ring->dev;
928 int bi_size;
929
930 if (!dev)
931 return -ENOMEM;
932
e908f815
JB		 933 /* warn if we are about to overwrite the pointer */
934 WARN_ON(tx_ring->tx_bi);
fd0a05ce
JB		 935 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
936 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
937 if (!tx_ring->tx_bi)
938 goto err;
939
940 /* round up to nearest 4K */
941 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1943d8ba
JB		 942 /* add u32 for head writeback, align after this takes care of
943 * guaranteeing this is at least one cache line in size
944 */
945 tx_ring->size += sizeof(u32);
fd0a05ce
JB		 946 tx_ring->size = ALIGN(tx_ring->size, 4096);
947 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
948 &tx_ring->dma, GFP_KERNEL);
949 if (!tx_ring->desc) {
950 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
951 tx_ring->size);
952 goto err;
953 }
954
955 tx_ring->next_to_use = 0;
956 tx_ring->next_to_clean = 0;
957 return 0;
958
959err:
960 kfree(tx_ring->tx_bi);
961 tx_ring->tx_bi = NULL;
962 return -ENOMEM;
963}
964
965/**
966 * i40e_clean_rx_ring - Free Rx buffers
967 * @rx_ring: ring to be cleaned
968 **/
969void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
970{
971 struct device *dev = rx_ring->dev;
972 struct i40e_rx_buffer *rx_bi;
973 unsigned long bi_size;
974 u16 i;
975
976 /* ring already cleared, nothing to do */
977 if (!rx_ring->rx_bi)
978 return;
979
a132af24
MW		 980 if (ring_is_ps_enabled(rx_ring)) {
981 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
982
983 rx_bi = &rx_ring->rx_bi[0];
984 if (rx_bi->hdr_buf) {
985 dma_free_coherent(dev,
986 bufsz,
987 rx_bi->hdr_buf,
988 rx_bi->dma);
989 for (i = 0; i < rx_ring->count; i++) {
990 rx_bi = &rx_ring->rx_bi[i];
991 rx_bi->dma = 0;
37a2973a 992 rx_bi->hdr_buf = NULL;
a132af24
MW		 993 }
994 }
995 }
fd0a05ce
JB		 996 /* Free all the Rx ring sk_buffs */
997 for (i = 0; i < rx_ring->count; i++) {
998 rx_bi = &rx_ring->rx_bi[i];
999 if (rx_bi->dma) {
1000 dma_unmap_single(dev,
1001 rx_bi->dma,
1002 rx_ring->rx_buf_len,
1003 DMA_FROM_DEVICE);
1004 rx_bi->dma = 0;
1005 }
1006 if (rx_bi->skb) {
1007 dev_kfree_skb(rx_bi->skb);
1008 rx_bi->skb = NULL;
1009 }
1010 if (rx_bi->page) {
1011 if (rx_bi->page_dma) {
1012 dma_unmap_page(dev,
1013 rx_bi->page_dma,
1014 PAGE_SIZE / 2,
1015 DMA_FROM_DEVICE);
1016 rx_bi->page_dma = 0;
1017 }
1018 __free_page(rx_bi->page);
1019 rx_bi->page = NULL;
1020 rx_bi->page_offset = 0;
1021 }
1022 }
1023
1024 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1025 memset(rx_ring->rx_bi, 0, bi_size);
1026
1027 /* Zero out the descriptor ring */
1028 memset(rx_ring->desc, 0, rx_ring->size);
1029
1030 rx_ring->next_to_clean = 0;
1031 rx_ring->next_to_use = 0;
1032}
1033
1034/**
1035 * i40e_free_rx_resources - Free Rx resources
1036 * @rx_ring: ring to clean the resources from
1037 *
1038 * Free all receive software resources
1039 **/
1040void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1041{
1042 i40e_clean_rx_ring(rx_ring);
1043 kfree(rx_ring->rx_bi);
1044 rx_ring->rx_bi = NULL;
1045
1046 if (rx_ring->desc) {
1047 dma_free_coherent(rx_ring->dev, rx_ring->size,
1048 rx_ring->desc, rx_ring->dma);
1049 rx_ring->desc = NULL;
1050 }
1051}
1052
a132af24
MW		 1053/**
1054 * i40e_alloc_rx_headers - allocate rx header buffers
1055 * @rx_ring: ring to alloc buffers
1056 *
1057 * Allocate rx header buffers for the entire ring. As these are static,
1058 * this is only called when setting up a new ring.
1059 **/
1060void i40e_alloc_rx_headers(struct i40e_ring *rx_ring)
1061{
1062 struct device *dev = rx_ring->dev;
1063 struct i40e_rx_buffer *rx_bi;
1064 dma_addr_t dma;
1065 void *buffer;
1066 int buf_size;
1067 int i;
1068
1069 if (rx_ring->rx_bi[0].hdr_buf)
1070 return;
1071 /* Make sure the buffers don't cross cache line boundaries. */
1072 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
1073 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
1074 &dma, GFP_KERNEL);
1075 if (!buffer)
1076 return;
1077 for (i = 0; i < rx_ring->count; i++) {
1078 rx_bi = &rx_ring->rx_bi[i];
1079 rx_bi->dma = dma + (i * buf_size);
1080 rx_bi->hdr_buf = buffer + (i * buf_size);
1081 }
1082}
1083
fd0a05ce
JB		 1084/**
1085 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1086 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1087 *
1088 * Returns 0 on success, negative on failure
1089 **/
1090int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1091{
1092 struct device *dev = rx_ring->dev;
1093 int bi_size;
1094
e908f815
JB		 1095 /* warn if we are about to overwrite the pointer */
1096 WARN_ON(rx_ring->rx_bi);
fd0a05ce
JB		 1097 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1098 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1099 if (!rx_ring->rx_bi)
1100 goto err;
1101
f217d6ca 1102 u64_stats_init(&rx_ring->syncp);
638702bd 1103
fd0a05ce
JB		 1104 /* Round up to nearest 4K */
1105 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
1106 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
1107 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1108 rx_ring->size = ALIGN(rx_ring->size, 4096);
1109 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1110 &rx_ring->dma, GFP_KERNEL);
1111
1112 if (!rx_ring->desc) {
1113 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1114 rx_ring->size);
1115 goto err;
1116 }
1117
1118 rx_ring->next_to_clean = 0;
1119 rx_ring->next_to_use = 0;
1120
1121 return 0;
1122err:
1123 kfree(rx_ring->rx_bi);
1124 rx_ring->rx_bi = NULL;
1125 return -ENOMEM;
1126}
1127
1128/**
1129 * i40e_release_rx_desc - Store the new tail and head values
1130 * @rx_ring: ring to bump
1131 * @val: new head index
1132 **/
1133static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1134{
1135 rx_ring->next_to_use = val;
1136 /* Force memory writes to complete before letting h/w
1137 * know there are new descriptors to fetch. (Only
1138 * applicable for weak-ordered memory model archs,
1139 * such as IA-64).
1140 */
1141 wmb();
1142 writel(val, rx_ring->tail);
1143}
1144
1145/**
a132af24 1146 * i40e_alloc_rx_buffers_ps - Replace used receive buffers; packet split
fd0a05ce
JB		 1147 * @rx_ring: ring to place buffers on
1148 * @cleaned_count: number of buffers to replace
1149 **/
a132af24
MW		 1150void i40e_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
1151{
1152 u16 i = rx_ring->next_to_use;
1153 union i40e_rx_desc *rx_desc;
1154 struct i40e_rx_buffer *bi;
1155
1156 /* do nothing if no valid netdev defined */
1157 if (!rx_ring->netdev || !cleaned_count)
1158 return;
1159
1160 while (cleaned_count--) {
1161 rx_desc = I40E_RX_DESC(rx_ring, i);
1162 bi = &rx_ring->rx_bi[i];
1163
1164 if (bi->skb) /* desc is in use */
1165 goto no_buffers;
1166 if (!bi->page) {
1167 bi->page = alloc_page(GFP_ATOMIC);
1168 if (!bi->page) {
1169 rx_ring->rx_stats.alloc_page_failed++;
1170 goto no_buffers;
1171 }
1172 }
1173
1174 if (!bi->page_dma) {
1175 /* use a half page if we're re-using */
1176 bi->page_offset ^= PAGE_SIZE / 2;
1177 bi->page_dma = dma_map_page(rx_ring->dev,
1178 bi->page,
1179 bi->page_offset,
1180 PAGE_SIZE / 2,
1181 DMA_FROM_DEVICE);
1182 if (dma_mapping_error(rx_ring->dev,
1183 bi->page_dma)) {
1184 rx_ring->rx_stats.alloc_page_failed++;
1185 bi->page_dma = 0;
1186 goto no_buffers;
1187 }
1188 }
1189
1190 dma_sync_single_range_for_device(rx_ring->dev,
1191 bi->dma,
1192 0,
1193 rx_ring->rx_hdr_len,
1194 DMA_FROM_DEVICE);
1195 /* Refresh the desc even if buffer_addrs didn't change
1196 * because each write-back erases this info.
1197 */
1198 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1199 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1200 i++;
1201 if (i == rx_ring->count)
1202 i = 0;
1203 }
1204
1205no_buffers:
1206 if (rx_ring->next_to_use != i)
1207 i40e_release_rx_desc(rx_ring, i);
1208}
1209
1210/**
1211 * i40e_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
1212 * @rx_ring: ring to place buffers on
1213 * @cleaned_count: number of buffers to replace
1214 **/
1215void i40e_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
fd0a05ce
JB		 1216{
1217 u16 i = rx_ring->next_to_use;
1218 union i40e_rx_desc *rx_desc;
1219 struct i40e_rx_buffer *bi;
1220 struct sk_buff *skb;
1221
1222 /* do nothing if no valid netdev defined */
1223 if (!rx_ring->netdev || !cleaned_count)
1224 return;
1225
1226 while (cleaned_count--) {
1227 rx_desc = I40E_RX_DESC(rx_ring, i);
1228 bi = &rx_ring->rx_bi[i];
1229 skb = bi->skb;
1230
1231 if (!skb) {
1232 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1233 rx_ring->rx_buf_len);
1234 if (!skb) {
420136cc 1235 rx_ring->rx_stats.alloc_buff_failed++;
fd0a05ce
JB		 1236 goto no_buffers;
1237 }
1238 /* initialize queue mapping */
1239 skb_record_rx_queue(skb, rx_ring->queue_index);
1240 bi->skb = skb;
1241 }
1242
1243 if (!bi->dma) {
1244 bi->dma = dma_map_single(rx_ring->dev,
1245 skb->data,
1246 rx_ring->rx_buf_len,
1247 DMA_FROM_DEVICE);
1248 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
420136cc 1249 rx_ring->rx_stats.alloc_buff_failed++;
fd0a05ce
JB		 1250 bi->dma = 0;
1251 goto no_buffers;
1252 }
1253 }
1254
a132af24
MW		 1255 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1256 rx_desc->read.hdr_addr = 0;
fd0a05ce
JB		 1257 i++;
1258 if (i == rx_ring->count)
1259 i = 0;
1260 }
1261
1262no_buffers:
1263 if (rx_ring->next_to_use != i)
1264 i40e_release_rx_desc(rx_ring, i);
1265}
1266
1267/**
1268 * i40e_receive_skb - Send a completed packet up the stack
1269 * @rx_ring: rx ring in play
1270 * @skb: packet to send up
1271 * @vlan_tag: vlan tag for packet
1272 **/
1273static void i40e_receive_skb(struct i40e_ring *rx_ring,
1274 struct sk_buff *skb, u16 vlan_tag)
1275{
1276 struct i40e_q_vector *q_vector = rx_ring->q_vector;
fd0a05ce
JB		 1277
1278 if (vlan_tag & VLAN_VID_MASK)
1279 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
1280
8b650359 1281 napi_gro_receive(&q_vector->napi, skb);
fd0a05ce
JB		 1282}
1283
1284/**
1285 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1286 * @vsi: the VSI we care about
1287 * @skb: skb currently being received and modified
1288 * @rx_status: status value of last descriptor in packet
1289 * @rx_error: error value of last descriptor in packet
8144f0f7 1290 * @rx_ptype: ptype value of last descriptor in packet
fd0a05ce
JB		 1291 **/
1292static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1293 struct sk_buff *skb,
1294 u32 rx_status,
8144f0f7
JG		 1295 u32 rx_error,
1296 u16 rx_ptype)
fd0a05ce 1297{
8a3c91cc
JB		 1298 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
1299 bool ipv4 = false, ipv6 = false;
8144f0f7
JG		 1300 bool ipv4_tunnel, ipv6_tunnel;
1301 __wsum rx_udp_csum;
8144f0f7 1302 struct iphdr *iph;
8a3c91cc 1303 __sum16 csum;
8144f0f7 1304
f8faaa40
ASJ		 1305 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
1306 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
1307 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
1308 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
8144f0f7 1309
fd0a05ce
JB		 1310 skb->ip_summed = CHECKSUM_NONE;
1311
1312 /* Rx csum enabled and ip headers found? */
8a3c91cc
JB		 1313 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1314 return;
1315
1316 /* did the hardware decode the packet and checksum? */
41a1d04b 1317 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
8a3c91cc
JB		 1318 return;
1319
1320 /* both known and outer_ip must be set for the below code to work */
1321 if (!(decoded.known && decoded.outer_ip))
fd0a05ce
JB		 1322 return;
1323
8a3c91cc
JB		 1324 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1325 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
1326 ipv4 = true;
1327 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1328 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
1329 ipv6 = true;
1330
1331 if (ipv4 &&
41a1d04b
JB		 1332 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1333 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
8a3c91cc
JB		 1334 goto checksum_fail;
1335
ddf1d0d7 1336 /* likely incorrect csum if alternate IP extension headers found */
8a3c91cc 1337 if (ipv6 &&
41a1d04b 1338 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
8a3c91cc 1339 /* don't increment checksum err here, non-fatal err */
8ee75a8e
SN		 1340 return;
1341
8a3c91cc 1342 /* there was some L4 error, count error and punt packet to the stack */
41a1d04b 1343 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
8a3c91cc
JB		 1344 goto checksum_fail;
1345
1346 /* handle packets that were not able to be checksummed due
1347 * to arrival speed, in this case the stack can compute
1348 * the csum.
1349 */
41a1d04b 1350 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
fd0a05ce 1351 return;
fd0a05ce 1352
8a3c91cc
JB		 1353 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
1354 * it in the driver, hardware does not do it for us.
1355 * Since L3L4P bit was set we assume a valid IHL value (>=5)
1356 * so the total length of IPv4 header is IHL*4 bytes
1357 * The UDP_0 bit *may* bet set if the *inner* header is UDP
1358 */
527274c7
ASJ		 1359 if (!(vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE) &&
1360 (ipv4_tunnel)) {
8144f0f7
JG		 1361 skb->transport_header = skb->mac_header +
1362 sizeof(struct ethhdr) +
1363 (ip_hdr(skb)->ihl * 4);
1364
1365 /* Add 4 bytes for VLAN tagged packets */
1366 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
1367 skb->protocol == htons(ETH_P_8021AD))
1368 ? VLAN_HLEN : 0;
1369
f6385979
AS		 1370 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
1371 (udp_hdr(skb)->check != 0)) {
1372 rx_udp_csum = udp_csum(skb);
1373 iph = ip_hdr(skb);
1374 csum = csum_tcpudp_magic(
1375 iph->saddr, iph->daddr,
1376 (skb->len - skb_transport_offset(skb)),
1377 IPPROTO_UDP, rx_udp_csum);
8144f0f7 1378
f6385979
AS		 1379 if (udp_hdr(skb)->check != csum)
1380 goto checksum_fail;
1381
1382 } /* else its GRE and so no outer UDP header */
8144f0f7
JG		 1383 }
1384
fd0a05ce 1385 skb->ip_summed = CHECKSUM_UNNECESSARY;
fa4ba69b 1386 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
8a3c91cc
JB		 1387
1388 return;
1389
1390checksum_fail:
1391 vsi->back->hw_csum_rx_error++;
fd0a05ce
JB		 1392}
1393
1394/**
1395 * i40e_rx_hash - returns the hash value from the Rx descriptor
1396 * @ring: descriptor ring
1397 * @rx_desc: specific descriptor
1398 **/
1399static inline u32 i40e_rx_hash(struct i40e_ring *ring,
1400 union i40e_rx_desc *rx_desc)
1401{
8a494920
JB		 1402 const __le64 rss_mask =
1403 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1404 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1405
1406 if ((ring->netdev->features & NETIF_F_RXHASH) &&
1407 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
1408 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1409 else
1410 return 0;
fd0a05ce
JB		 1411}
1412
206812b5
JB		 1413/**
1414 * i40e_ptype_to_hash - get a hash type
1415 * @ptype: the ptype value from the descriptor
1416 *
1417 * Returns a hash type to be used by skb_set_hash
1418 **/
1419static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
1420{
1421 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1422
1423 if (!decoded.known)
1424 return PKT_HASH_TYPE_NONE;
1425
1426 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1427 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1428 return PKT_HASH_TYPE_L4;
1429 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1430 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1431 return PKT_HASH_TYPE_L3;
1432 else
1433 return PKT_HASH_TYPE_L2;
1434}
1435
fd0a05ce 1436/**
a132af24 1437 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
fd0a05ce
JB		 1438 * @rx_ring: rx ring to clean
1439 * @budget: how many cleans we're allowed
1440 *
1441 * Returns true if there's any budget left (e.g. the clean is finished)
1442 **/
a132af24 1443static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
fd0a05ce
JB		 1444{
1445 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1446 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1447 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
8dc5562e 1448 const int current_node = numa_mem_id();
fd0a05ce
JB		 1449 struct i40e_vsi *vsi = rx_ring->vsi;
1450 u16 i = rx_ring->next_to_clean;
1451 union i40e_rx_desc *rx_desc;
1452 u32 rx_error, rx_status;
206812b5 1453 u8 rx_ptype;
fd0a05ce
JB		 1454 u64 qword;
1455
390f86df
EB		 1456 if (budget <= 0)
1457 return 0;
1458
a132af24 1459 do {
fd0a05ce
JB		 1460 struct i40e_rx_buffer *rx_bi;
1461 struct sk_buff *skb;
1462 u16 vlan_tag;
a132af24
MW		 1463 /* return some buffers to hardware, one at a time is too slow */
1464 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1465 i40e_alloc_rx_buffers_ps(rx_ring, cleaned_count);
1466 cleaned_count = 0;
1467 }
1468
1469 i = rx_ring->next_to_clean;
1470 rx_desc = I40E_RX_DESC(rx_ring, i);
1471 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1472 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1473 I40E_RXD_QW1_STATUS_SHIFT;
1474
41a1d04b 1475 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
a132af24
MW		 1476 break;
1477
1478 /* This memory barrier is needed to keep us from reading
1479 * any other fields out of the rx_desc until we know the
1480 * DD bit is set.
1481 */
67317166 1482 dma_rmb();
fd0a05ce
JB		 1483 if (i40e_rx_is_programming_status(qword)) {
1484 i40e_clean_programming_status(rx_ring, rx_desc);
a132af24
MW		 1485 I40E_RX_INCREMENT(rx_ring, i);
1486 continue;
fd0a05ce
JB		 1487 }
1488 rx_bi = &rx_ring->rx_bi[i];
1489 skb = rx_bi->skb;
a132af24
MW		 1490 if (likely(!skb)) {
1491 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1492 rx_ring->rx_hdr_len);
8b6ed9c2 1493 if (!skb) {
a132af24 1494 rx_ring->rx_stats.alloc_buff_failed++;
8b6ed9c2
JB		 1495 break;
1496 }
1497
a132af24
MW		 1498 /* initialize queue mapping */
1499 skb_record_rx_queue(skb, rx_ring->queue_index);
1500 /* we are reusing so sync this buffer for CPU use */
1501 dma_sync_single_range_for_cpu(rx_ring->dev,
1502 rx_bi->dma,
1503 0,
1504 rx_ring->rx_hdr_len,
1505 DMA_FROM_DEVICE);
1506 }
829af3ac
MW		 1507 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1508 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1509 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1510 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1511 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1512 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1513
1514 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1515 I40E_RXD_QW1_ERROR_SHIFT;
41a1d04b
JB		 1516 rx_hbo = rx_error & BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
1517 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
fd0a05ce 1518
8144f0f7
JG		 1519 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1520 I40E_RXD_QW1_PTYPE_SHIFT;
a132af24 1521 prefetch(rx_bi->page);
fd0a05ce 1522 rx_bi->skb = NULL;
a132af24
MW		 1523 cleaned_count++;
1524 if (rx_hbo || rx_sph) {
1525 int len;
6995b36c 1526
fd0a05ce
JB		 1527 if (rx_hbo)
1528 len = I40E_RX_HDR_SIZE;
fd0a05ce 1529 else
a132af24
MW		 1530 len = rx_header_len;
1531 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1532 } else if (skb->len == 0) {
1533 int len;
1534
1535 len = (rx_packet_len > skb_headlen(skb) ?
1536 skb_headlen(skb) : rx_packet_len);
1537 memcpy(__skb_put(skb, len),
1538 rx_bi->page + rx_bi->page_offset,
1539 len);
1540 rx_bi->page_offset += len;
1541 rx_packet_len -= len;
fd0a05ce
JB		 1542 }
1543
1544 /* Get the rest of the data if this was a header split */
a132af24 1545 if (rx_packet_len) {
fd0a05ce
JB		 1546 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1547 rx_bi->page,
1548 rx_bi->page_offset,
1549 rx_packet_len);
1550
1551 skb->len += rx_packet_len;
1552 skb->data_len += rx_packet_len;
1553 skb->truesize += rx_packet_len;
1554
1555 if ((page_count(rx_bi->page) == 1) &&
1556 (page_to_nid(rx_bi->page) == current_node))
1557 get_page(rx_bi->page);
1558 else
1559 rx_bi->page = NULL;
1560
1561 dma_unmap_page(rx_ring->dev,
1562 rx_bi->page_dma,
1563 PAGE_SIZE / 2,
1564 DMA_FROM_DEVICE);
1565 rx_bi->page_dma = 0;
1566 }
a132af24 1567 I40E_RX_INCREMENT(rx_ring, i);
fd0a05ce
JB		 1568
1569 if (unlikely(
41a1d04b 1570 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
fd0a05ce
JB		 1571 struct i40e_rx_buffer *next_buffer;
1572
1573 next_buffer = &rx_ring->rx_bi[i];
a132af24 1574 next_buffer->skb = skb;
fd0a05ce 1575 rx_ring->rx_stats.non_eop_descs++;
a132af24 1576 continue;
fd0a05ce
JB		 1577 }
1578
1579 /* ERR_MASK will only have valid bits if EOP set */
41a1d04b 1580 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
fd0a05ce 1581 dev_kfree_skb_any(skb);
a132af24 1582 continue;
fd0a05ce
JB		 1583 }
1584
206812b5
JB		 1585 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1586 i40e_ptype_to_hash(rx_ptype));
beb0dff1
JK		 1587 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1588 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1589 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1590 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1591 rx_ring->last_rx_timestamp = jiffies;
1592 }
1593
fd0a05ce
JB		 1594 /* probably a little skewed due to removing CRC */
1595 total_rx_bytes += skb->len;
1596 total_rx_packets++;
1597
1598 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8144f0f7
JG		 1599
1600 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1601
41a1d04b 1602 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
fd0a05ce
JB		 1603 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1604 : 0;
38e00438
VD		 1605#ifdef I40E_FCOE
1606 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1607 dev_kfree_skb_any(skb);
a132af24 1608 continue;
38e00438
VD		 1609 }
1610#endif
a132af24 1611 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
fd0a05ce
JB		 1612 i40e_receive_skb(rx_ring, skb, vlan_tag);
1613
fd0a05ce 1614 rx_desc->wb.qword1.status_error_len = 0;
fd0a05ce 1615
a132af24
MW		 1616 } while (likely(total_rx_packets < budget));
1617
1618 u64_stats_update_begin(&rx_ring->syncp);
1619 rx_ring->stats.packets += total_rx_packets;
1620 rx_ring->stats.bytes += total_rx_bytes;
1621 u64_stats_update_end(&rx_ring->syncp);
1622 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1623 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1624
1625 return total_rx_packets;
1626}
1627
1628/**
1629 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1630 * @rx_ring: rx ring to clean
1631 * @budget: how many cleans we're allowed
1632 *
1633 * Returns number of packets cleaned
1634 **/
1635static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1636{
1637 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1638 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1639 struct i40e_vsi *vsi = rx_ring->vsi;
1640 union i40e_rx_desc *rx_desc;
1641 u32 rx_error, rx_status;
1642 u16 rx_packet_len;
1643 u8 rx_ptype;
1644 u64 qword;
1645 u16 i;
1646
1647 do {
1648 struct i40e_rx_buffer *rx_bi;
1649 struct sk_buff *skb;
1650 u16 vlan_tag;
fd0a05ce
JB		 1651 /* return some buffers to hardware, one at a time is too slow */
1652 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
a132af24 1653 i40e_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
fd0a05ce
JB		 1654 cleaned_count = 0;
1655 }
1656
a132af24
MW		 1657 i = rx_ring->next_to_clean;
1658 rx_desc = I40E_RX_DESC(rx_ring, i);
fd0a05ce 1659 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
829af3ac 1660 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
a132af24
MW		 1661 I40E_RXD_QW1_STATUS_SHIFT;
1662
41a1d04b 1663 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
a132af24
MW		 1664 break;
1665
1666 /* This memory barrier is needed to keep us from reading
1667 * any other fields out of the rx_desc until we know the
1668 * DD bit is set.
1669 */
67317166 1670 dma_rmb();
a132af24
MW		 1671
1672 if (i40e_rx_is_programming_status(qword)) {
1673 i40e_clean_programming_status(rx_ring, rx_desc);
1674 I40E_RX_INCREMENT(rx_ring, i);
1675 continue;
1676 }
1677 rx_bi = &rx_ring->rx_bi[i];
1678 skb = rx_bi->skb;
1679 prefetch(skb->data);
1680
1681 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1682 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1683
1684 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1685 I40E_RXD_QW1_ERROR_SHIFT;
41a1d04b 1686 rx_error &= ~BIT(I40E_RX_DESC_ERROR_HBO_SHIFT);
a132af24
MW		 1687
1688 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1689 I40E_RXD_QW1_PTYPE_SHIFT;
1690 rx_bi->skb = NULL;
1691 cleaned_count++;
1692
1693 /* Get the header and possibly the whole packet
1694 * If this is an skb from previous receive dma will be 0
1695 */
1696 skb_put(skb, rx_packet_len);
1697 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1698 DMA_FROM_DEVICE);
1699 rx_bi->dma = 0;
1700
1701 I40E_RX_INCREMENT(rx_ring, i);
1702
1703 if (unlikely(
41a1d04b 1704 !(rx_status & BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
a132af24
MW		 1705 rx_ring->rx_stats.non_eop_descs++;
1706 continue;
1707 }
1708
1709 /* ERR_MASK will only have valid bits if EOP set */
41a1d04b 1710 if (unlikely(rx_error & BIT(I40E_RX_DESC_ERROR_RXE_SHIFT))) {
a132af24 1711 dev_kfree_skb_any(skb);
a132af24
MW		 1712 continue;
1713 }
1714
1715 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1716 i40e_ptype_to_hash(rx_ptype));
1717 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1718 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1719 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1720 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1721 rx_ring->last_rx_timestamp = jiffies;
1722 }
1723
1724 /* probably a little skewed due to removing CRC */
1725 total_rx_bytes += skb->len;
1726 total_rx_packets++;
1727
1728 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1729
1730 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1731
41a1d04b 1732 vlan_tag = rx_status & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
a132af24
MW		 1733 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1734 : 0;
1735#ifdef I40E_FCOE
1736 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1737 dev_kfree_skb_any(skb);
1738 continue;
1739 }
1740#endif
1741 i40e_receive_skb(rx_ring, skb, vlan_tag);
1742
a132af24
MW		 1743 rx_desc->wb.qword1.status_error_len = 0;
1744 } while (likely(total_rx_packets < budget));
fd0a05ce 1745
980e9b11 1746 u64_stats_update_begin(&rx_ring->syncp);
a114d0a6
AD		 1747 rx_ring->stats.packets += total_rx_packets;
1748 rx_ring->stats.bytes += total_rx_bytes;
980e9b11 1749 u64_stats_update_end(&rx_ring->syncp);
fd0a05ce
JB		 1750 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1751 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1752
a132af24 1753 return total_rx_packets;
fd0a05ce
JB		 1754}
1755
8f5e39ce
JB		 1756static u32 i40e_buildreg_itr(const int type, const u16 itr)
1757{
1758 u32 val;
1759
1760 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1761 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1762 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1763 (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
1764
1765 return val;
1766}
1767
1768/* a small macro to shorten up some long lines */
1769#define INTREG I40E_PFINT_DYN_CTLN
1770
de32e3ef
CW		 1771/**
1772 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1773 * @vsi: the VSI we care about
1774 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1775 *
1776 **/
1777static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1778 struct i40e_q_vector *q_vector)
1779{
1780 struct i40e_hw *hw = &vsi->back->hw;
8f5e39ce
JB		 1781 bool rx = false, tx = false;
1782 u32 rxval, txval;
de32e3ef 1783 int vector;
de32e3ef
CW		 1784
1785 vector = (q_vector->v_idx + vsi->base_vector);
8f5e39ce
JB		 1786
1787 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1788
de32e3ef 1789 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting)) {
8f5e39ce
JB		 1790 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1791 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
de32e3ef 1792 }
8f5e39ce 1793
de32e3ef 1794 if (ITR_IS_DYNAMIC(vsi->tx_itr_setting)) {
8f5e39ce
JB		 1795 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1796 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
de32e3ef 1797 }
8f5e39ce
JB		 1798
1799 if (rx || tx) {
1800 /* get the higher of the two ITR adjustments and
1801 * use the same value for both ITR registers
1802 * when in adaptive mode (Rx and/or Tx)
1803 */
1804 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1805
1806 q_vector->tx.itr = q_vector->rx.itr = itr;
1807 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1808 tx = true;
1809 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1810 rx = true;
1811 }
1812
1813 /* only need to enable the interrupt once, but need
1814 * to possibly update both ITR values
1815 */
1816 if (rx) {
1817 /* set the INTENA_MSK_MASK so that this first write
1818 * won't actually enable the interrupt, instead just
1819 * updating the ITR (it's bit 31 PF and VF)
1820 */
1821 rxval |= BIT(31);
1822 /* don't check _DOWN because interrupt isn't being enabled */
1823 wr32(hw, INTREG(vector - 1), rxval);
1824 }
1825
1826 if (!test_bit(__I40E_DOWN, &vsi->state))
1827 wr32(hw, INTREG(vector - 1), txval);
de32e3ef
CW		 1828}
1829
fd0a05ce
JB		 1830/**
1831 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
1832 * @napi: napi struct with our devices info in it
1833 * @budget: amount of work driver is allowed to do this pass, in packets
1834 *
1835 * This function will clean all queues associated with a q_vector.
1836 *
1837 * Returns the amount of work done
1838 **/
1839int i40e_napi_poll(struct napi_struct *napi, int budget)
1840{
1841 struct i40e_q_vector *q_vector =
1842 container_of(napi, struct i40e_q_vector, napi);
1843 struct i40e_vsi *vsi = q_vector->vsi;
cd0b6fa6 1844 struct i40e_ring *ring;
fd0a05ce 1845 bool clean_complete = true;
d91649f5 1846 bool arm_wb = false;
fd0a05ce 1847 int budget_per_ring;
32b3e08f 1848 int work_done = 0;
fd0a05ce
JB		 1849
1850 if (test_bit(__I40E_DOWN, &vsi->state)) {
1851 napi_complete(napi);
1852 return 0;
1853 }
1854
cd0b6fa6
AD		 1855 /* Since the actual Tx work is minimal, we can give the Tx a larger
1856 * budget and be more aggressive about cleaning up the Tx descriptors.
1857 */
d91649f5 1858 i40e_for_each_ring(ring, q_vector->tx) {
cd0b6fa6 1859 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
d91649f5 1860 arm_wb |= ring->arm_wb;
0deda868 1861 ring->arm_wb = false;
d91649f5 1862 }
cd0b6fa6 1863
c67caceb
AD		 1864 /* Handle case where we are called by netpoll with a budget of 0 */
1865 if (budget <= 0)
1866 goto tx_only;
1867
fd0a05ce
JB		 1868 /* We attempt to distribute budget to each Rx queue fairly, but don't
1869 * allow the budget to go below 1 because that would exit polling early.
fd0a05ce
JB		 1870 */
1871 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
cd0b6fa6 1872
a132af24 1873 i40e_for_each_ring(ring, q_vector->rx) {
32b3e08f
JB		 1874 int cleaned;
1875
a132af24
MW		 1876 if (ring_is_ps_enabled(ring))
1877 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1878 else
1879 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
32b3e08f
JB		 1880
1881 work_done += cleaned;
a132af24
MW		 1882 /* if we didn't clean as many as budgeted, we must be done */
1883 clean_complete &= (budget_per_ring != cleaned);
1884 }
fd0a05ce
JB		 1885
1886 /* If work not completed, return budget and polling will return */
d91649f5 1887 if (!clean_complete) {
c67caceb 1888tx_only:
d91649f5
JB		 1889 if (arm_wb)
1890 i40e_force_wb(vsi, q_vector);
fd0a05ce 1891 return budget;
d91649f5 1892 }
fd0a05ce 1893
8e0764b4
ASJ		 1894 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1895 q_vector->arm_wb_state = false;
1896
fd0a05ce 1897 /* Work is done so exit the polling mode and re-enable the interrupt */
32b3e08f 1898 napi_complete_done(napi, work_done);
de32e3ef
CW		 1899 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1900 i40e_update_enable_itr(vsi, q_vector);
1901 } else { /* Legacy mode */
1902 struct i40e_hw *hw = &vsi->back->hw;
1903 /* We re-enable the queue 0 cause, but
1904 * don't worry about dynamic_enable
1905 * because we left it on for the other
1906 * possible interrupts during napi
1907 */
1908 u32 qval = rd32(hw, I40E_QINT_RQCTL(0)) |
1909 I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1910
1911 wr32(hw, I40E_QINT_RQCTL(0), qval);
1912 qval = rd32(hw, I40E_QINT_TQCTL(0)) |
1913 I40E_QINT_TQCTL_CAUSE_ENA_MASK;
1914 wr32(hw, I40E_QINT_TQCTL(0), qval);
1915 i40e_irq_dynamic_enable_icr0(vsi->back);
fd0a05ce 1916 }
fd0a05ce
JB		 1917 return 0;
1918}
1919
1920/**
1921 * i40e_atr - Add a Flow Director ATR filter
1922 * @tx_ring: ring to add programming descriptor to
1923 * @skb: send buffer
89232c3b 1924 * @tx_flags: send tx flags
fd0a05ce
JB		 1925 * @protocol: wire protocol
1926 **/
1927static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
89232c3b 1928 u32 tx_flags, __be16 protocol)
fd0a05ce
JB		 1929{
1930 struct i40e_filter_program_desc *fdir_desc;
1931 struct i40e_pf *pf = tx_ring->vsi->back;
1932 union {
1933 unsigned char *network;
1934 struct iphdr *ipv4;
1935 struct ipv6hdr *ipv6;
1936 } hdr;
1937 struct tcphdr *th;
1938 unsigned int hlen;
1939 u32 flex_ptype, dtype_cmd;
fc4ac67b 1940 u16 i;
fd0a05ce
JB		 1941
1942 /* make sure ATR is enabled */
60ea5f83 1943 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
fd0a05ce
JB		 1944 return;
1945
04294e38
ASJ		 1946 if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1947 return;
1948
fd0a05ce
JB		 1949 /* if sampling is disabled do nothing */
1950 if (!tx_ring->atr_sample_rate)
1951 return;
1952
89232c3b
ASJ		 1953 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
1954 return;
fd0a05ce 1955
89232c3b
ASJ		 1956 if (!(tx_flags & I40E_TX_FLAGS_VXLAN_TUNNEL)) {
1957 /* snag network header to get L4 type and address */
1958 hdr.network = skb_network_header(skb);
fd0a05ce 1959
89232c3b
ASJ		 1960 /* Currently only IPv4/IPv6 with TCP is supported
1961 * access ihl as u8 to avoid unaligned access on ia64
1962 */
1963 if (tx_flags & I40E_TX_FLAGS_IPV4)
1964 hlen = (hdr.network[0] & 0x0F) << 2;
1965 else if (protocol == htons(ETH_P_IPV6))
1966 hlen = sizeof(struct ipv6hdr);
1967 else
fd0a05ce 1968 return;
fd0a05ce 1969 } else {
89232c3b
ASJ		 1970 hdr.network = skb_inner_network_header(skb);
1971 hlen = skb_inner_network_header_len(skb);
fd0a05ce
JB		 1972 }
1973
89232c3b
ASJ		 1974 /* Currently only IPv4/IPv6 with TCP is supported
1975 * Note: tx_flags gets modified to reflect inner protocols in
1976 * tx_enable_csum function if encap is enabled.
1977 */
1978 if ((tx_flags & I40E_TX_FLAGS_IPV4) &&
1979 (hdr.ipv4->protocol != IPPROTO_TCP))
1980 return;
1981 else if ((tx_flags & I40E_TX_FLAGS_IPV6) &&
1982 (hdr.ipv6->nexthdr != IPPROTO_TCP))
1983 return;
1984
fd0a05ce
JB		 1985 th = (struct tcphdr *)(hdr.network + hlen);
1986
55a5e60b
ASJ		 1987 /* Due to lack of space, no more new filters can be programmed */
1988 if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1989 return;
52eb95ef
ASJ		 1990 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) {
1991 /* HW ATR eviction will take care of removing filters on FIN
1992 * and RST packets.
1993 */
1994 if (th->fin || th->rst)
1995 return;
1996 }
55a5e60b
ASJ		 1997
1998 tx_ring->atr_count++;
1999
ce806783
ASJ		 2000 /* sample on all syn/fin/rst packets or once every atr sample rate */
2001 if (!th->fin &&
2002 !th->syn &&
2003 !th->rst &&
2004 (tx_ring->atr_count < tx_ring->atr_sample_rate))
fd0a05ce
JB		 2005 return;
2006
2007 tx_ring->atr_count = 0;
2008
2009 /* grab the next descriptor */
fc4ac67b
AD		 2010 i = tx_ring->next_to_use;
2011 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2012
2013 i++;
2014 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
fd0a05ce
JB		 2015
2016 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2017 I40E_TXD_FLTR_QW0_QINDEX_MASK;
2018 flex_ptype |= (protocol == htons(ETH_P_IP)) ?
2019 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2020 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2021 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2022 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2023
2024 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2025
2026 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2027
ce806783 2028 dtype_cmd |= (th->fin || th->rst) ?
fd0a05ce
JB		 2029 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2030 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2031 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2032 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2033
2034 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2035 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2036
2037 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2038 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2039
433c47de 2040 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
60ccd45c
ASJ		 2041 if (!(tx_flags & I40E_TX_FLAGS_VXLAN_TUNNEL))
2042 dtype_cmd |=
2043 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2044 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2045 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2046 else
2047 dtype_cmd |=
2048 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2049 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2050 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
433c47de 2051
52eb95ef
ASJ		 2052 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)
2053 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2054
fd0a05ce 2055 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
99753ea6 2056 fdir_desc->rsvd = cpu_to_le32(0);
fd0a05ce 2057 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
99753ea6 2058 fdir_desc->fd_id = cpu_to_le32(0);
fd0a05ce
JB		 2059}
2060
fd0a05ce
JB		 2061/**
2062 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2063 * @skb: send buffer
2064 * @tx_ring: ring to send buffer on
2065 * @flags: the tx flags to be set
2066 *
2067 * Checks the skb and set up correspondingly several generic transmit flags
2068 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2069 *
2070 * Returns error code indicate the frame should be dropped upon error and the
2071 * otherwise returns 0 to indicate the flags has been set properly.
2072 **/
38e00438 2073#ifdef I40E_FCOE
3e587cf3 2074inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
fd0a05ce
JB		 2075 struct i40e_ring *tx_ring,
2076 u32 *flags)
3e587cf3
JB		 2077#else
2078static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2079 struct i40e_ring *tx_ring,
2080 u32 *flags)
38e00438 2081#endif
fd0a05ce
JB		 2082{
2083 __be16 protocol = skb->protocol;
2084 u32 tx_flags = 0;
2085
31eaaccf
GR		 2086 if (protocol == htons(ETH_P_8021Q) &&
2087 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2088 /* When HW VLAN acceleration is turned off by the user the
2089 * stack sets the protocol to 8021q so that the driver
2090 * can take any steps required to support the SW only
2091 * VLAN handling. In our case the driver doesn't need
2092 * to take any further steps so just set the protocol
2093 * to the encapsulated ethertype.
2094 */
2095 skb->protocol = vlan_get_protocol(skb);
2096 goto out;
2097 }
2098
fd0a05ce 2099 /* if we have a HW VLAN tag being added, default to the HW one */
df8a39de
JP		 2100 if (skb_vlan_tag_present(skb)) {
2101 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
fd0a05ce
JB		 2102 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2103 /* else if it is a SW VLAN, check the next protocol and store the tag */
0e2fe46c 2104 } else if (protocol == htons(ETH_P_8021Q)) {
fd0a05ce 2105 struct vlan_hdr *vhdr, _vhdr;
6995b36c 2106
fd0a05ce
JB		 2107 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2108 if (!vhdr)
2109 return -EINVAL;
2110
2111 protocol = vhdr->h_vlan_encapsulated_proto;
2112 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2113 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2114 }
2115
d40d00b1
NP		 2116 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2117 goto out;
2118
fd0a05ce 2119 /* Insert 802.1p priority into VLAN header */
38e00438
VD		 2120 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2121 (skb->priority != TC_PRIO_CONTROL)) {
fd0a05ce
JB		 2122 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2123 tx_flags |= (skb->priority & 0x7) <<
2124 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2125 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2126 struct vlan_ethhdr *vhdr;
dd225bc6
FR		 2127 int rc;
2128
2129 rc = skb_cow_head(skb, 0);
2130 if (rc < 0)
2131 return rc;
fd0a05ce
JB		 2132 vhdr = (struct vlan_ethhdr *)skb->data;
2133 vhdr->h_vlan_TCI = htons(tx_flags >>
2134 I40E_TX_FLAGS_VLAN_SHIFT);
2135 } else {
2136 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2137 }
2138 }
d40d00b1
NP		 2139
2140out:
fd0a05ce
JB		 2141 *flags = tx_flags;
2142 return 0;
2143}
2144
fd0a05ce
JB		 2145/**
2146 * i40e_tso - set up the tso context descriptor
2147 * @tx_ring: ptr to the ring to send
2148 * @skb: ptr to the skb we're sending
fd0a05ce
JB		 2149 * @hdr_len: ptr to the size of the packet header
2150 * @cd_tunneling: ptr to context descriptor bits
2151 *
2152 * Returns 0 if no TSO can happen, 1 if tso is going, or error
2153 **/
2154static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
89232c3b
ASJ		 2155 u8 *hdr_len, u64 *cd_type_cmd_tso_mss,
2156 u32 *cd_tunneling)
fd0a05ce
JB		 2157{
2158 u32 cd_cmd, cd_tso_len, cd_mss;
dd225bc6 2159 struct ipv6hdr *ipv6h;
fd0a05ce
JB		 2160 struct tcphdr *tcph;
2161 struct iphdr *iph;
2162 u32 l4len;
2163 int err;
fd0a05ce
JB		 2164
2165 if (!skb_is_gso(skb))
2166 return 0;
2167
dd225bc6
FR		 2168 err = skb_cow_head(skb, 0);
2169 if (err < 0)
2170 return err;
fd0a05ce 2171
df23075f
AS		 2172 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
2173 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
2174
2175 if (iph->version == 4) {
fd0a05ce
JB		 2176 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2177 iph->tot_len = 0;
2178 iph->check = 0;
2179 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
2180 0, IPPROTO_TCP, 0);
df23075f 2181 } else if (ipv6h->version == 6) {
fd0a05ce
JB		 2182 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2183 ipv6h->payload_len = 0;
2184 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
2185 0, IPPROTO_TCP, 0);
2186 }
2187
2188 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
2189 *hdr_len = (skb->encapsulation
2190 ? (skb_inner_transport_header(skb) - skb->data)
2191 : skb_transport_offset(skb)) + l4len;
2192
2193 /* find the field values */
2194 cd_cmd = I40E_TX_CTX_DESC_TSO;
2195 cd_tso_len = skb->len - *hdr_len;
2196 cd_mss = skb_shinfo(skb)->gso_size;
829af3ac
MW		 2197 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2198 ((u64)cd_tso_len <<
2199 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2200 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
fd0a05ce
JB		 2201 return 1;
2202}
2203
beb0dff1
JK		 2204/**
2205 * i40e_tsyn - set up the tsyn context descriptor
2206 * @tx_ring: ptr to the ring to send
2207 * @skb: ptr to the skb we're sending
2208 * @tx_flags: the collected send information
2209 *
2210 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
2211 **/
2212static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
2213 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
2214{
2215 struct i40e_pf *pf;
2216
2217 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
2218 return 0;
2219
2220 /* Tx timestamps cannot be sampled when doing TSO */
2221 if (tx_flags & I40E_TX_FLAGS_TSO)
2222 return 0;
2223
2224 /* only timestamp the outbound packet if the user has requested it and
2225 * we are not already transmitting a packet to be timestamped
2226 */
2227 pf = i40e_netdev_to_pf(tx_ring->netdev);
22b4777d
JK		 2228 if (!(pf->flags & I40E_FLAG_PTP))
2229 return 0;
2230
9ce34f02
JK		 2231 if (pf->ptp_tx &&
2232 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) {
beb0dff1
JK		 2233 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2234 pf->ptp_tx_skb = skb_get(skb);
2235 } else {
2236 return 0;
2237 }
2238
2239 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
2240 I40E_TXD_CTX_QW1_CMD_SHIFT;
2241
beb0dff1
JK		 2242 return 1;
2243}
2244
fd0a05ce
JB		 2245/**
2246 * i40e_tx_enable_csum - Enable Tx checksum offloads
2247 * @skb: send buffer
89232c3b 2248 * @tx_flags: pointer to Tx flags currently set
fd0a05ce
JB		 2249 * @td_cmd: Tx descriptor command bits to set
2250 * @td_offset: Tx descriptor header offsets to set
2251 * @cd_tunneling: ptr to context desc bits
2252 **/
89232c3b 2253static void i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
fd0a05ce
JB		 2254 u32 *td_cmd, u32 *td_offset,
2255 struct i40e_ring *tx_ring,
2256 u32 *cd_tunneling)
2257{
2258 struct ipv6hdr *this_ipv6_hdr;
2259 unsigned int this_tcp_hdrlen;
2260 struct iphdr *this_ip_hdr;
2261 u32 network_hdr_len;
2262 u8 l4_hdr = 0;
527274c7
ASJ		 2263 struct udphdr *oudph;
2264 struct iphdr *oiph;
45991204 2265 u32 l4_tunnel = 0;
fd0a05ce
JB		 2266
2267 if (skb->encapsulation) {
45991204
ASJ		 2268 switch (ip_hdr(skb)->protocol) {
2269 case IPPROTO_UDP:
527274c7
ASJ		 2270 oudph = udp_hdr(skb);
2271 oiph = ip_hdr(skb);
45991204 2272 l4_tunnel = I40E_TXD_CTX_UDP_TUNNELING;
89232c3b 2273 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
45991204 2274 break;
c1d1791d
SN		 2275 case IPPROTO_GRE:
2276 l4_tunnel = I40E_TXD_CTX_GRE_TUNNELING;
2277 break;
45991204
ASJ		 2278 default:
2279 return;
2280 }
fd0a05ce
JB		 2281 network_hdr_len = skb_inner_network_header_len(skb);
2282 this_ip_hdr = inner_ip_hdr(skb);
2283 this_ipv6_hdr = inner_ipv6_hdr(skb);
2284 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
2285
89232c3b
ASJ		 2286 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2287 if (*tx_flags & I40E_TX_FLAGS_TSO) {
fd0a05ce
JB		 2288 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
2289 ip_hdr(skb)->check = 0;
2290 } else {
2291 *cd_tunneling |=
2292 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
2293 }
89232c3b 2294 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
df23075f 2295 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
89232c3b 2296 if (*tx_flags & I40E_TX_FLAGS_TSO)
fd0a05ce 2297 ip_hdr(skb)->check = 0;
fd0a05ce
JB		 2298 }
2299
2300 /* Now set the ctx descriptor fields */
2301 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
45991204
ASJ		 2302 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
2303 l4_tunnel |
fd0a05ce
JB		 2304 ((skb_inner_network_offset(skb) -
2305 skb_transport_offset(skb)) >> 1) <<
2306 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
df23075f 2307 if (this_ip_hdr->version == 6) {
89232c3b
ASJ		 2308 *tx_flags &= ~I40E_TX_FLAGS_IPV4;
2309 *tx_flags |= I40E_TX_FLAGS_IPV6;
df23075f 2310 }
527274c7
ASJ		 2311 if ((tx_ring->flags & I40E_TXR_FLAGS_OUTER_UDP_CSUM) &&
2312 (l4_tunnel == I40E_TXD_CTX_UDP_TUNNELING) &&
2313 (*cd_tunneling & I40E_TXD_CTX_QW0_EXT_IP_MASK)) {
2314 oudph->check = ~csum_tcpudp_magic(oiph->saddr,
2315 oiph->daddr,
2316 (skb->len - skb_transport_offset(skb)),
2317 IPPROTO_UDP, 0);
2318 *cd_tunneling |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
2319 }
fd0a05ce
JB		 2320 } else {
2321 network_hdr_len = skb_network_header_len(skb);
2322 this_ip_hdr = ip_hdr(skb);
2323 this_ipv6_hdr = ipv6_hdr(skb);
2324 this_tcp_hdrlen = tcp_hdrlen(skb);
2325 }
2326
2327 /* Enable IP checksum offloads */
89232c3b 2328 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
fd0a05ce
JB		 2329 l4_hdr = this_ip_hdr->protocol;
2330 /* the stack computes the IP header already, the only time we
2331 * need the hardware to recompute it is in the case of TSO.
2332 */
89232c3b 2333 if (*tx_flags & I40E_TX_FLAGS_TSO) {
fd0a05ce
JB		 2334 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
2335 this_ip_hdr->check = 0;
2336 } else {
2337 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
2338 }
2339 /* Now set the td_offset for IP header length */
2340 *td_offset = (network_hdr_len >> 2) <<
2341 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
89232c3b 2342 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
fd0a05ce
JB		 2343 l4_hdr = this_ipv6_hdr->nexthdr;
2344 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
2345 /* Now set the td_offset for IP header length */
2346 *td_offset = (network_hdr_len >> 2) <<
2347 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2348 }
2349 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
2350 *td_offset |= (skb_network_offset(skb) >> 1) <<
2351 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
2352
2353 /* Enable L4 checksum offloads */
2354 switch (l4_hdr) {
2355 case IPPROTO_TCP:
2356 /* enable checksum offloads */
2357 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
2358 *td_offset |= (this_tcp_hdrlen >> 2) <<
2359 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2360 break;
2361 case IPPROTO_SCTP:
2362 /* enable SCTP checksum offload */
2363 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
2364 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
2365 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2366 break;
2367 case IPPROTO_UDP:
2368 /* enable UDP checksum offload */
2369 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
2370 *td_offset |= (sizeof(struct udphdr) >> 2) <<
2371 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2372 break;
2373 default:
2374 break;
2375 }
2376}
2377
2378/**
2379 * i40e_create_tx_ctx Build the Tx context descriptor
2380 * @tx_ring: ring to create the descriptor on
2381 * @cd_type_cmd_tso_mss: Quad Word 1
2382 * @cd_tunneling: Quad Word 0 - bits 0-31
2383 * @cd_l2tag2: Quad Word 0 - bits 32-63
2384 **/
2385static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
2386 const u64 cd_type_cmd_tso_mss,
2387 const u32 cd_tunneling, const u32 cd_l2tag2)
2388{
2389 struct i40e_tx_context_desc *context_desc;
fc4ac67b 2390 int i = tx_ring->next_to_use;
fd0a05ce 2391
ff40dd5d
JB		 2392 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
2393 !cd_tunneling && !cd_l2tag2)
fd0a05ce
JB		 2394 return;
2395
2396 /* grab the next descriptor */
fc4ac67b
AD		 2397 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
2398
2399 i++;
2400 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
fd0a05ce
JB		 2401
2402 /* cpu_to_le32 and assign to struct fields */
2403 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2404 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3efbbb20 2405 context_desc->rsvd = cpu_to_le16(0);
fd0a05ce
JB		 2406 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2407}
2408
4567dc10
ED		 2409/**
2410 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
2411 * @tx_ring: the ring to be checked
2412 * @size: the size buffer we want to assure is available
2413 *
2414 * Returns -EBUSY if a stop is needed, else 0
2415 **/
2416static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2417{
2418 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2419 /* Memory barrier before checking head and tail */
2420 smp_mb();
2421
2422 /* Check again in a case another CPU has just made room available. */
2423 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
2424 return -EBUSY;
2425
2426 /* A reprieve! - use start_queue because it doesn't call schedule */
2427 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2428 ++tx_ring->tx_stats.restart_queue;
2429 return 0;
2430}
2431
2432/**
2433 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
2434 * @tx_ring: the ring to be checked
2435 * @size: the size buffer we want to assure is available
2436 *
2437 * Returns 0 if stop is not needed
2438 **/
2439#ifdef I40E_FCOE
3e587cf3 2440inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
4567dc10 2441#else
3e587cf3 2442static inline int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
4567dc10
ED		 2443#endif
2444{
2445 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
2446 return 0;
2447 return __i40e_maybe_stop_tx(tx_ring, size);
2448}
2449
71da6197
AS		 2450/**
2451 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
2452 * @skb: send buffer
2453 * @tx_flags: collected send information
71da6197
AS		 2454 *
2455 * Note: Our HW can't scatter-gather more than 8 fragments to build
2456 * a packet on the wire and so we need to figure out the cases where we
2457 * need to linearize the skb.
2458 **/
30520831 2459static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags)
71da6197
AS		 2460{
2461 struct skb_frag_struct *frag;
2462 bool linearize = false;
2463 unsigned int size = 0;
2464 u16 num_frags;
2465 u16 gso_segs;
2466
2467 num_frags = skb_shinfo(skb)->nr_frags;
2468 gso_segs = skb_shinfo(skb)->gso_segs;
2469
2470 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
30520831 2471 u16 j = 0;
71da6197
AS		 2472
2473 if (num_frags < (I40E_MAX_BUFFER_TXD))
2474 goto linearize_chk_done;
2475 /* try the simple math, if we have too many frags per segment */
2476 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
2477 I40E_MAX_BUFFER_TXD) {
2478 linearize = true;
2479 goto linearize_chk_done;
2480 }
2481 frag = &skb_shinfo(skb)->frags[0];
71da6197
AS		 2482 /* we might still have more fragments per segment */
2483 do {
2484 size += skb_frag_size(frag);
2485 frag++; j++;
30520831
ASJ		 2486 if ((size >= skb_shinfo(skb)->gso_size) &&
2487 (j < I40E_MAX_BUFFER_TXD)) {
2488 size = (size % skb_shinfo(skb)->gso_size);
2489 j = (size) ? 1 : 0;
2490 }
71da6197 2491 if (j == I40E_MAX_BUFFER_TXD) {
30520831
ASJ		 2492 linearize = true;
2493 break;
71da6197
AS		 2494 }
2495 num_frags--;
2496 } while (num_frags);
2497 } else {
2498 if (num_frags >= I40E_MAX_BUFFER_TXD)
2499 linearize = true;
2500 }
2501
2502linearize_chk_done:
2503 return linearize;
2504}
2505
fd0a05ce
JB		 2506/**
2507 * i40e_tx_map - Build the Tx descriptor
2508 * @tx_ring: ring to send buffer on
2509 * @skb: send buffer
2510 * @first: first buffer info buffer to use
2511 * @tx_flags: collected send information
2512 * @hdr_len: size of the packet header
2513 * @td_cmd: the command field in the descriptor
2514 * @td_offset: offset for checksum or crc
2515 **/
38e00438 2516#ifdef I40E_FCOE
3e587cf3 2517inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
fd0a05ce
JB		 2518 struct i40e_tx_buffer *first, u32 tx_flags,
2519 const u8 hdr_len, u32 td_cmd, u32 td_offset)
3e587cf3
JB		 2520#else
2521static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2522 struct i40e_tx_buffer *first, u32 tx_flags,
2523 const u8 hdr_len, u32 td_cmd, u32 td_offset)
38e00438 2524#endif
fd0a05ce 2525{
fd0a05ce
JB		 2526 unsigned int data_len = skb->data_len;
2527 unsigned int size = skb_headlen(skb);
a5e9c572 2528 struct skb_frag_struct *frag;
fd0a05ce
JB		 2529 struct i40e_tx_buffer *tx_bi;
2530 struct i40e_tx_desc *tx_desc;
a5e9c572 2531 u16 i = tx_ring->next_to_use;
fd0a05ce
JB		 2532 u32 td_tag = 0;
2533 dma_addr_t dma;
2534 u16 gso_segs;
58044743
AS		 2535 u16 desc_count = 0;
2536 bool tail_bump = true;
2537 bool do_rs = false;
fd0a05ce 2538
fd0a05ce
JB		 2539 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
2540 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
2541 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
2542 I40E_TX_FLAGS_VLAN_SHIFT;
2543 }
2544
a5e9c572
AD		 2545 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
2546 gso_segs = skb_shinfo(skb)->gso_segs;
2547 else
2548 gso_segs = 1;
2549
2550 /* multiply data chunks by size of headers */
2551 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
2552 first->gso_segs = gso_segs;
2553 first->skb = skb;
2554 first->tx_flags = tx_flags;
2555
2556 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2557
fd0a05ce 2558 tx_desc = I40E_TX_DESC(tx_ring, i);
a5e9c572
AD		 2559 tx_bi = first;
2560
2561 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2562 if (dma_mapping_error(tx_ring->dev, dma))
2563 goto dma_error;
2564
2565 /* record length, and DMA address */
2566 dma_unmap_len_set(tx_bi, len, size);
2567 dma_unmap_addr_set(tx_bi, dma, dma);
2568
2569 tx_desc->buffer_addr = cpu_to_le64(dma);
2570
2571 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
fd0a05ce
JB		 2572 tx_desc->cmd_type_offset_bsz =
2573 build_ctob(td_cmd, td_offset,
2574 I40E_MAX_DATA_PER_TXD, td_tag);
2575
fd0a05ce
JB		 2576 tx_desc++;
2577 i++;
58044743
AS		 2578 desc_count++;
2579
fd0a05ce
JB		 2580 if (i == tx_ring->count) {
2581 tx_desc = I40E_TX_DESC(tx_ring, 0);
2582 i = 0;
2583 }
fd0a05ce 2584
a5e9c572
AD		 2585 dma += I40E_MAX_DATA_PER_TXD;
2586 size -= I40E_MAX_DATA_PER_TXD;
fd0a05ce 2587
a5e9c572
AD		 2588 tx_desc->buffer_addr = cpu_to_le64(dma);
2589 }
fd0a05ce
JB		 2590
2591 if (likely(!data_len))
2592 break;
2593
a5e9c572
AD		 2594 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2595 size, td_tag);
fd0a05ce
JB		 2596
2597 tx_desc++;
2598 i++;
58044743
AS		 2599 desc_count++;
2600
fd0a05ce
JB		 2601 if (i == tx_ring->count) {
2602 tx_desc = I40E_TX_DESC(tx_ring, 0);
2603 i = 0;
2604 }
2605
a5e9c572
AD		 2606 size = skb_frag_size(frag);
2607 data_len -= size;
fd0a05ce 2608
a5e9c572
AD		 2609 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2610 DMA_TO_DEVICE);
fd0a05ce 2611
a5e9c572
AD		 2612 tx_bi = &tx_ring->tx_bi[i];
2613 }
fd0a05ce 2614
a5e9c572
AD		 2615 /* set next_to_watch value indicating a packet is present */
2616 first->next_to_watch = tx_desc;
2617
2618 i++;
2619 if (i == tx_ring->count)
2620 i = 0;
2621
2622 tx_ring->next_to_use = i;
2623
58044743
AS		 2624 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
2625 tx_ring->queue_index),
2626 first->bytecount);
4567dc10 2627 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
58044743
AS		 2628
2629 /* Algorithm to optimize tail and RS bit setting:
2630 * if xmit_more is supported
2631 * if xmit_more is true
2632 * do not update tail and do not mark RS bit.
2633 * if xmit_more is false and last xmit_more was false
2634 * if every packet spanned less than 4 desc
2635 * then set RS bit on 4th packet and update tail
2636 * on every packet
2637 * else
2638 * update tail and set RS bit on every packet.
2639 * if xmit_more is false and last_xmit_more was true
2640 * update tail and set RS bit.
2641 *
2642 * Optimization: wmb to be issued only in case of tail update.
2643 * Also optimize the Descriptor WB path for RS bit with the same
2644 * algorithm.
2645 *
2646 * Note: If there are less than 4 packets
2647 * pending and interrupts were disabled the service task will
2648 * trigger a force WB.
2649 */
2650 if (skb->xmit_more &&
2651 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2652 tx_ring->queue_index))) {
2653 tx_ring->flags |= I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2654 tail_bump = false;
2655 } else if (!skb->xmit_more &&
2656 !netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2657 tx_ring->queue_index)) &&
2658 (!(tx_ring->flags & I40E_TXR_FLAGS_LAST_XMIT_MORE_SET)) &&
2659 (tx_ring->packet_stride < WB_STRIDE) &&
2660 (desc_count < WB_STRIDE)) {
2661 tx_ring->packet_stride++;
2662 } else {
2663 tx_ring->packet_stride = 0;
2664 tx_ring->flags &= ~I40E_TXR_FLAGS_LAST_XMIT_MORE_SET;
2665 do_rs = true;
2666 }
2667 if (do_rs)
2668 tx_ring->packet_stride = 0;
2669
2670 tx_desc->cmd_type_offset_bsz =
2671 build_ctob(td_cmd, td_offset, size, td_tag) |
2672 cpu_to_le64((u64)(do_rs ? I40E_TXD_CMD :
2673 I40E_TX_DESC_CMD_EOP) <<
2674 I40E_TXD_QW1_CMD_SHIFT);
2675
a5e9c572 2676 /* notify HW of packet */
58044743 2677 if (!tail_bump)
489ce7a4 2678 prefetchw(tx_desc + 1);
a5e9c572 2679
58044743
AS		 2680 if (tail_bump) {
2681 /* Force memory writes to complete before letting h/w
2682 * know there are new descriptors to fetch. (Only
2683 * applicable for weak-ordered memory model archs,
2684 * such as IA-64).
2685 */
2686 wmb();
2687 writel(i, tx_ring->tail);
2688 }
2689
fd0a05ce
JB		 2690 return;
2691
2692dma_error:
a5e9c572 2693 dev_info(tx_ring->dev, "TX DMA map failed\n");
fd0a05ce
JB		 2694
2695 /* clear dma mappings for failed tx_bi map */
2696 for (;;) {
2697 tx_bi = &tx_ring->tx_bi[i];
a5e9c572 2698 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
fd0a05ce
JB		 2699 if (tx_bi == first)
2700 break;
2701 if (i == 0)
2702 i = tx_ring->count;
2703 i--;
2704 }
2705
fd0a05ce
JB		 2706 tx_ring->next_to_use = i;
2707}
2708
fd0a05ce
JB		 2709/**
2710 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
2711 * @skb: send buffer
2712 * @tx_ring: ring to send buffer on
2713 *
2714 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
2715 * there is not enough descriptors available in this ring since we need at least
2716 * one descriptor.
2717 **/
38e00438 2718#ifdef I40E_FCOE
3e587cf3 2719inline int i40e_xmit_descriptor_count(struct sk_buff *skb,
fd0a05ce 2720 struct i40e_ring *tx_ring)
3e587cf3
JB		 2721#else
2722static inline int i40e_xmit_descriptor_count(struct sk_buff *skb,
2723 struct i40e_ring *tx_ring)
38e00438 2724#endif
fd0a05ce 2725{
fd0a05ce 2726 unsigned int f;
fd0a05ce
JB		 2727 int count = 0;
2728
2729 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2730 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
be560521 2731 * + 4 desc gap to avoid the cache line where head is,
fd0a05ce
JB		 2732 * + 1 desc for context descriptor,
2733 * otherwise try next time
2734 */
fd0a05ce
JB		 2735 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
2736 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
980093eb 2737
fd0a05ce 2738 count += TXD_USE_COUNT(skb_headlen(skb));
be560521 2739 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
fd0a05ce
JB		 2740 tx_ring->tx_stats.tx_busy++;
2741 return 0;
2742 }
2743 return count;
2744}
2745
2746/**
2747 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2748 * @skb: send buffer
2749 * @tx_ring: ring to send buffer on
2750 *
2751 * Returns NETDEV_TX_OK if sent, else an error code
2752 **/
2753static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2754 struct i40e_ring *tx_ring)
2755{
2756 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2757 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2758 struct i40e_tx_buffer *first;
2759 u32 td_offset = 0;
2760 u32 tx_flags = 0;
2761 __be16 protocol;
2762 u32 td_cmd = 0;
2763 u8 hdr_len = 0;
beb0dff1 2764 int tsyn;
fd0a05ce 2765 int tso;
6995b36c 2766
fd0a05ce
JB		 2767 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
2768 return NETDEV_TX_BUSY;
2769
2770 /* prepare the xmit flags */
2771 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2772 goto out_drop;
2773
2774 /* obtain protocol of skb */
3d34dd03 2775 protocol = vlan_get_protocol(skb);
fd0a05ce
JB		 2776
2777 /* record the location of the first descriptor for this packet */
2778 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2779
2780 /* setup IPv4/IPv6 offloads */
0e2fe46c 2781 if (protocol == htons(ETH_P_IP))
fd0a05ce 2782 tx_flags |= I40E_TX_FLAGS_IPV4;
0e2fe46c 2783 else if (protocol == htons(ETH_P_IPV6))
fd0a05ce
JB		 2784 tx_flags |= I40E_TX_FLAGS_IPV6;
2785
89232c3b 2786 tso = i40e_tso(tx_ring, skb, &hdr_len,
fd0a05ce
JB		 2787 &cd_type_cmd_tso_mss, &cd_tunneling);
2788
2789 if (tso < 0)
2790 goto out_drop;
2791 else if (tso)
2792 tx_flags |= I40E_TX_FLAGS_TSO;
2793
beb0dff1
JK		 2794 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
2795
2796 if (tsyn)
2797 tx_flags |= I40E_TX_FLAGS_TSYN;
2798
2fc3d715 2799 if (i40e_chk_linearize(skb, tx_flags)) {
71da6197
AS		 2800 if (skb_linearize(skb))
2801 goto out_drop;
2fc3d715
ASJ		 2802 tx_ring->tx_stats.tx_linearize++;
2803 }
259afec7
JK		 2804 skb_tx_timestamp(skb);
2805
b1941306
AD		 2806 /* always enable CRC insertion offload */
2807 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2808
fd0a05ce 2809 /* Always offload the checksum, since it's in the data descriptor */
b1941306 2810 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fd0a05ce
JB		 2811 tx_flags |= I40E_TX_FLAGS_CSUM;
2812
89232c3b 2813 i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
fd0a05ce 2814 tx_ring, &cd_tunneling);
b1941306 2815 }
fd0a05ce
JB		 2816
2817 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2818 cd_tunneling, cd_l2tag2);
2819
2820 /* Add Flow Director ATR if it's enabled.
2821 *
2822 * NOTE: this must always be directly before the data descriptor.
2823 */
2824 i40e_atr(tx_ring, skb, tx_flags, protocol);
2825
2826 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2827 td_cmd, td_offset);
2828
fd0a05ce
JB		 2829 return NETDEV_TX_OK;
2830
2831out_drop:
2832 dev_kfree_skb_any(skb);
2833 return NETDEV_TX_OK;
2834}
2835
2836/**
2837 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2838 * @skb: send buffer
2839 * @netdev: network interface device structure
2840 *
2841 * Returns NETDEV_TX_OK if sent, else an error code
2842 **/
2843netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2844{
2845 struct i40e_netdev_priv *np = netdev_priv(netdev);
2846 struct i40e_vsi *vsi = np->vsi;
9f65e15b 2847 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
fd0a05ce
JB		 2848
2849 /* hardware can't handle really short frames, hardware padding works
2850 * beyond this point
2851 */
a94d9e22
AD		 2852 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
2853 return NETDEV_TX_OK;
fd0a05ce
JB		 2854
2855 return i40e_xmit_frame_ring(skb, tx_ring);
2856}
Linux 6.x block layer and io_uring tree(s)