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rocker: sparse: fix dynamic allocation on stack warning
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_txrx.c
CommitLineData
fd0a05ce
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
fd0a05ce
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
fd0a05ce
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
1c112a64 27#include <linux/prefetch.h>
a132af24 28#include <net/busy_poll.h>
fd0a05ce 29#include "i40e.h"
206812b5 30#include "i40e_prototype.h"
fd0a05ce
JB		 31
32static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
33 u32 td_tag)
34{
35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
40}
41
eaefbd06 42#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
49d7d933 43#define I40E_FD_CLEAN_DELAY 10
fd0a05ce
JB		 44/**
45 * i40e_program_fdir_filter - Program a Flow Director filter
17a73f6b
JG		 46 * @fdir_data: Packet data that will be filter parameters
47 * @raw_packet: the pre-allocated packet buffer for FDir
fd0a05ce
JB		 48 * @pf: The pf pointer
49 * @add: True for add/update, False for remove
50 **/
17a73f6b 51int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
fd0a05ce
JB		 52 struct i40e_pf *pf, bool add)
53{
54 struct i40e_filter_program_desc *fdir_desc;
49d7d933 55 struct i40e_tx_buffer *tx_buf, *first;
fd0a05ce
JB		 56 struct i40e_tx_desc *tx_desc;
57 struct i40e_ring *tx_ring;
eaefbd06 58 unsigned int fpt, dcc;
fd0a05ce
JB		 59 struct i40e_vsi *vsi;
60 struct device *dev;
61 dma_addr_t dma;
62 u32 td_cmd = 0;
49d7d933 63 u16 delay = 0;
fd0a05ce
JB		 64 u16 i;
65
66 /* find existing FDIR VSI */
67 vsi = NULL;
505682cd 68 for (i = 0; i < pf->num_alloc_vsi; i++)
fd0a05ce
JB		 69 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR)
70 vsi = pf->vsi[i];
71 if (!vsi)
72 return -ENOENT;
73
9f65e15b 74 tx_ring = vsi->tx_rings[0];
fd0a05ce
JB		 75 dev = tx_ring->dev;
76
49d7d933
ASJ		 77 /* we need two descriptors to add/del a filter and we can wait */
78 do {
79 if (I40E_DESC_UNUSED(tx_ring) > 1)
80 break;
81 msleep_interruptible(1);
82 delay++;
83 } while (delay < I40E_FD_CLEAN_DELAY);
84
85 if (!(I40E_DESC_UNUSED(tx_ring) > 1))
86 return -EAGAIN;
87
17a73f6b
JG		 88 dma = dma_map_single(dev, raw_packet,
89 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
fd0a05ce
JB		 90 if (dma_mapping_error(dev, dma))
91 goto dma_fail;
92
93 /* grab the next descriptor */
fc4ac67b
AD		 94 i = tx_ring->next_to_use;
95 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
49d7d933
ASJ		 96 first = &tx_ring->tx_bi[i];
97 memset(first, 0, sizeof(struct i40e_tx_buffer));
fc4ac67b 98
49d7d933 99 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
fd0a05ce 100
eaefbd06
JB		 101 fpt = (fdir_data->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
102 I40E_TXD_FLTR_QW0_QINDEX_MASK;
fd0a05ce 103
eaefbd06
JB		 104 fpt |= (fdir_data->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
105 I40E_TXD_FLTR_QW0_FLEXOFF_MASK;
fd0a05ce 106
eaefbd06
JB		 107 fpt |= (fdir_data->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
108 I40E_TXD_FLTR_QW0_PCTYPE_MASK;
fd0a05ce
JB		 109
110 /* Use LAN VSI Id if not programmed by user */
111 if (fdir_data->dest_vsi == 0)
eaefbd06
JB		 112 fpt |= (pf->vsi[pf->lan_vsi]->id) <<
113 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
fd0a05ce 114 else
eaefbd06
JB		 115 fpt |= ((u32)fdir_data->dest_vsi <<
116 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
117 I40E_TXD_FLTR_QW0_DEST_VSI_MASK;
118
eaefbd06 119 dcc = I40E_TX_DESC_DTYPE_FILTER_PROG;
fd0a05ce
JB		 120
121 if (add)
eaefbd06
JB		 122 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
123 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
fd0a05ce 124 else
eaefbd06
JB		 125 dcc |= I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
126 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
fd0a05ce 127
eaefbd06
JB		 128 dcc |= (fdir_data->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT) &
129 I40E_TXD_FLTR_QW1_DEST_MASK;
fd0a05ce 130
eaefbd06
JB		 131 dcc |= (fdir_data->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
132 I40E_TXD_FLTR_QW1_FD_STATUS_MASK;
fd0a05ce
JB		 133
134 if (fdir_data->cnt_index != 0) {
eaefbd06
JB		 135 dcc |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
136 dcc |= ((u32)fdir_data->cnt_index <<
137 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
433c47de 138 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
fd0a05ce
JB		 139 }
140
99753ea6
JB		 141 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(fpt);
142 fdir_desc->rsvd = cpu_to_le32(0);
eaefbd06 143 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dcc);
fd0a05ce
JB		 144 fdir_desc->fd_id = cpu_to_le32(fdir_data->fd_id);
145
146 /* Now program a dummy descriptor */
fc4ac67b
AD		 147 i = tx_ring->next_to_use;
148 tx_desc = I40E_TX_DESC(tx_ring, i);
298deef1 149 tx_buf = &tx_ring->tx_bi[i];
fc4ac67b 150
49d7d933
ASJ		 151 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
152
153 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
fd0a05ce 154
298deef1 155 /* record length, and DMA address */
17a73f6b 156 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
298deef1
ASJ		 157 dma_unmap_addr_set(tx_buf, dma, dma);
158
fd0a05ce 159 tx_desc->buffer_addr = cpu_to_le64(dma);
eaefbd06 160 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
fd0a05ce 161
49d7d933
ASJ		 162 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
163 tx_buf->raw_buf = (void *)raw_packet;
164
fd0a05ce 165 tx_desc->cmd_type_offset_bsz =
17a73f6b 166 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
fd0a05ce 167
298deef1
ASJ		 168 /* set the timestamp */
169 tx_buf->time_stamp = jiffies;
170
fd0a05ce 171 /* Force memory writes to complete before letting h/w
49d7d933 172 * know there are new descriptors to fetch.
fd0a05ce
JB		 173 */
174 wmb();
175
fc4ac67b 176 /* Mark the data descriptor to be watched */
49d7d933 177 first->next_to_watch = tx_desc;
fc4ac67b 178
fd0a05ce
JB		 179 writel(tx_ring->next_to_use, tx_ring->tail);
180 return 0;
181
182dma_fail:
183 return -1;
184}
185
17a73f6b
JG		 186#define IP_HEADER_OFFSET 14
187#define I40E_UDPIP_DUMMY_PACKET_LEN 42
188/**
189 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
190 * @vsi: pointer to the targeted VSI
191 * @fd_data: the flow director data required for the FDir descriptor
17a73f6b
JG		 192 * @add: true adds a filter, false removes it
193 *
194 * Returns 0 if the filters were successfully added or removed
195 **/
196static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
197 struct i40e_fdir_filter *fd_data,
49d7d933 198 bool add)
17a73f6b
JG		 199{
200 struct i40e_pf *pf = vsi->back;
201 struct udphdr *udp;
202 struct iphdr *ip;
203 bool err = false;
49d7d933 204 u8 *raw_packet;
17a73f6b 205 int ret;
17a73f6b
JG		 206 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
207 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
208 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
209
49d7d933
ASJ		 210 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
211 if (!raw_packet)
212 return -ENOMEM;
17a73f6b
JG		 213 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
214
215 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
216 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
217 + sizeof(struct iphdr));
218
219 ip->daddr = fd_data->dst_ip[0];
220 udp->dest = fd_data->dst_port;
221 ip->saddr = fd_data->src_ip[0];
222 udp->source = fd_data->src_port;
223
b2d36c03
KS		 224 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
225 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
226 if (ret) {
227 dev_info(&pf->pdev->dev,
e99bdd39
CW		 228 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
229 fd_data->pctype, fd_data->fd_id, ret);
b2d36c03
KS		 230 err = true;
231 } else {
f7233c54
ASJ		 232 if (add)
233 dev_info(&pf->pdev->dev,
234 "Filter OK for PCTYPE %d loc = %d\n",
235 fd_data->pctype, fd_data->fd_id);
236 else
237 dev_info(&pf->pdev->dev,
238 "Filter deleted for PCTYPE %d loc = %d\n",
239 fd_data->pctype, fd_data->fd_id);
17a73f6b 240 }
17a73f6b
JG		 241 return err ? -EOPNOTSUPP : 0;
242}
243
244#define I40E_TCPIP_DUMMY_PACKET_LEN 54
245/**
246 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
247 * @vsi: pointer to the targeted VSI
248 * @fd_data: the flow director data required for the FDir descriptor
17a73f6b
JG		 249 * @add: true adds a filter, false removes it
250 *
251 * Returns 0 if the filters were successfully added or removed
252 **/
253static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
254 struct i40e_fdir_filter *fd_data,
49d7d933 255 bool add)
17a73f6b
JG		 256{
257 struct i40e_pf *pf = vsi->back;
258 struct tcphdr *tcp;
259 struct iphdr *ip;
260 bool err = false;
49d7d933 261 u8 *raw_packet;
17a73f6b
JG		 262 int ret;
263 /* Dummy packet */
264 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
265 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
266 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
267 0x0, 0x72, 0, 0, 0, 0};
268
49d7d933
ASJ		 269 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
270 if (!raw_packet)
271 return -ENOMEM;
17a73f6b
JG		 272 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
273
274 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
275 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
276 + sizeof(struct iphdr));
277
278 ip->daddr = fd_data->dst_ip[0];
279 tcp->dest = fd_data->dst_port;
280 ip->saddr = fd_data->src_ip[0];
281 tcp->source = fd_data->src_port;
282
283 if (add) {
1e1be8f6 284 pf->fd_tcp_rule++;
17a73f6b
JG		 285 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) {
286 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
287 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
288 }
1e1be8f6
ASJ		 289 } else {
290 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ?
291 (pf->fd_tcp_rule - 1) : 0;
292 if (pf->fd_tcp_rule == 0) {
293 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
294 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n");
295 }
17a73f6b
JG		 296 }
297
b2d36c03 298 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
17a73f6b
JG		 299 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
300
301 if (ret) {
302 dev_info(&pf->pdev->dev,
e99bdd39
CW		 303 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
304 fd_data->pctype, fd_data->fd_id, ret);
17a73f6b
JG		 305 err = true;
306 } else {
f7233c54
ASJ		 307 if (add)
308 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
309 fd_data->pctype, fd_data->fd_id);
310 else
311 dev_info(&pf->pdev->dev,
312 "Filter deleted for PCTYPE %d loc = %d\n",
313 fd_data->pctype, fd_data->fd_id);
17a73f6b
JG		 314 }
315
17a73f6b
JG		 316 return err ? -EOPNOTSUPP : 0;
317}
318
319/**
320 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
321 * a specific flow spec
322 * @vsi: pointer to the targeted VSI
323 * @fd_data: the flow director data required for the FDir descriptor
17a73f6b
JG		 324 * @add: true adds a filter, false removes it
325 *
21d3efdc 326 * Always returns -EOPNOTSUPP
17a73f6b
JG		 327 **/
328static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
329 struct i40e_fdir_filter *fd_data,
49d7d933 330 bool add)
17a73f6b
JG		 331{
332 return -EOPNOTSUPP;
333}
334
335#define I40E_IP_DUMMY_PACKET_LEN 34
336/**
337 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
338 * a specific flow spec
339 * @vsi: pointer to the targeted VSI
340 * @fd_data: the flow director data required for the FDir descriptor
17a73f6b
JG		 341 * @add: true adds a filter, false removes it
342 *
343 * Returns 0 if the filters were successfully added or removed
344 **/
345static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
346 struct i40e_fdir_filter *fd_data,
49d7d933 347 bool add)
17a73f6b
JG		 348{
349 struct i40e_pf *pf = vsi->back;
350 struct iphdr *ip;
351 bool err = false;
49d7d933 352 u8 *raw_packet;
17a73f6b
JG		 353 int ret;
354 int i;
355 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
356 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
357 0, 0, 0, 0};
358
17a73f6b
JG		 359 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
360 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
49d7d933
ASJ		 361 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
362 if (!raw_packet)
363 return -ENOMEM;
364 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
365 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
366
367 ip->saddr = fd_data->src_ip[0];
368 ip->daddr = fd_data->dst_ip[0];
369 ip->protocol = 0;
370
17a73f6b
JG		 371 fd_data->pctype = i;
372 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
373
374 if (ret) {
375 dev_info(&pf->pdev->dev,
e99bdd39
CW		 376 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
377 fd_data->pctype, fd_data->fd_id, ret);
17a73f6b
JG		 378 err = true;
379 } else {
f7233c54
ASJ		 380 if (add)
381 dev_info(&pf->pdev->dev,
382 "Filter OK for PCTYPE %d loc = %d\n",
383 fd_data->pctype, fd_data->fd_id);
384 else
385 dev_info(&pf->pdev->dev,
386 "Filter deleted for PCTYPE %d loc = %d\n",
387 fd_data->pctype, fd_data->fd_id);
17a73f6b
JG		 388 }
389 }
390
391 return err ? -EOPNOTSUPP : 0;
392}
393
394/**
395 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
396 * @vsi: pointer to the targeted VSI
397 * @cmd: command to get or set RX flow classification rules
398 * @add: true adds a filter, false removes it
399 *
400 **/
401int i40e_add_del_fdir(struct i40e_vsi *vsi,
402 struct i40e_fdir_filter *input, bool add)
403{
404 struct i40e_pf *pf = vsi->back;
17a73f6b
JG		 405 int ret;
406
17a73f6b
JG		 407 switch (input->flow_type & ~FLOW_EXT) {
408 case TCP_V4_FLOW:
49d7d933 409 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
17a73f6b
JG		 410 break;
411 case UDP_V4_FLOW:
49d7d933 412 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
17a73f6b
JG		 413 break;
414 case SCTP_V4_FLOW:
49d7d933 415 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
17a73f6b
JG		 416 break;
417 case IPV4_FLOW:
49d7d933 418 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
17a73f6b
JG		 419 break;
420 case IP_USER_FLOW:
421 switch (input->ip4_proto) {
422 case IPPROTO_TCP:
49d7d933 423 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
17a73f6b
JG		 424 break;
425 case IPPROTO_UDP:
49d7d933 426 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
17a73f6b
JG		 427 break;
428 case IPPROTO_SCTP:
49d7d933 429 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
17a73f6b
JG		 430 break;
431 default:
49d7d933 432 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
17a73f6b
JG		 433 break;
434 }
435 break;
436 default:
c5ffe7e1 437 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n",
17a73f6b
JG		 438 input->flow_type);
439 ret = -EINVAL;
440 }
441
49d7d933 442 /* The buffer allocated here is freed by the i40e_clean_tx_ring() */
17a73f6b
JG		 443 return ret;
444}
445
fd0a05ce
JB		 446/**
447 * i40e_fd_handle_status - check the Programming Status for FD
448 * @rx_ring: the Rx ring for this descriptor
55a5e60b 449 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
fd0a05ce
JB		 450 * @prog_id: the id originally used for programming
451 *
452 * This is used to verify if the FD programming or invalidation
453 * requested by SW to the HW is successful or not and take actions accordingly.
454 **/
55a5e60b
ASJ		 455static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
456 union i40e_rx_desc *rx_desc, u8 prog_id)
fd0a05ce 457{
55a5e60b
ASJ		 458 struct i40e_pf *pf = rx_ring->vsi->back;
459 struct pci_dev *pdev = pf->pdev;
460 u32 fcnt_prog, fcnt_avail;
fd0a05ce 461 u32 error;
55a5e60b 462 u64 qw;
fd0a05ce 463
55a5e60b 464 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
fd0a05ce
JB		 465 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
466 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
467
55a5e60b 468 if (error == (0x1 << I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
f7233c54
ASJ		 469 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
470 (I40E_DEBUG_FD & pf->hw.debug_mask))
471 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
472 rx_desc->wb.qword0.hi_dword.fd_id);
55a5e60b 473
1e1be8f6
ASJ		 474 pf->fd_add_err++;
475 /* store the current atr filter count */
476 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
477
55a5e60b 478 /* filter programming failed most likely due to table full */
12957388
ASJ		 479 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
480 fcnt_avail = pf->fdir_pf_filter_count;
55a5e60b
ASJ		 481 /* If ATR is running fcnt_prog can quickly change,
482 * if we are very close to full, it makes sense to disable
483 * FD ATR/SB and then re-enable it when there is room.
484 */
485 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
1e1be8f6 486 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
b814ba65 487 !(pf->auto_disable_flags &
b814ba65 488 I40E_FLAG_FD_SB_ENABLED)) {
55a5e60b
ASJ		 489 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
490 pf->auto_disable_flags |=
491 I40E_FLAG_FD_SB_ENABLED;
55a5e60b
ASJ		 492 }
493 } else {
e99bdd39 494 dev_info(&pdev->dev,
f7233c54 495 "FD filter programming failed due to incorrect filter parameters\n");
55a5e60b
ASJ		 496 }
497 } else if (error ==
498 (0x1 << I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
13c2884f 499 if (I40E_DEBUG_FD & pf->hw.debug_mask)
e99bdd39 500 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
13c2884f 501 rx_desc->wb.qword0.hi_dword.fd_id);
55a5e60b 502 }
fd0a05ce
JB		 503}
504
505/**
a5e9c572 506 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
fd0a05ce
JB		 507 * @ring: the ring that owns the buffer
508 * @tx_buffer: the buffer to free
509 **/
a5e9c572
AD		 510static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
511 struct i40e_tx_buffer *tx_buffer)
fd0a05ce 512{
a5e9c572 513 if (tx_buffer->skb) {
49d7d933
ASJ		 514 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
515 kfree(tx_buffer->raw_buf);
516 else
517 dev_kfree_skb_any(tx_buffer->skb);
518
a5e9c572 519 if (dma_unmap_len(tx_buffer, len))
fd0a05ce 520 dma_unmap_single(ring->dev,
35a1e2ad
AD		 521 dma_unmap_addr(tx_buffer, dma),
522 dma_unmap_len(tx_buffer, len),
fd0a05ce 523 DMA_TO_DEVICE);
a5e9c572
AD		 524 } else if (dma_unmap_len(tx_buffer, len)) {
525 dma_unmap_page(ring->dev,
526 dma_unmap_addr(tx_buffer, dma),
527 dma_unmap_len(tx_buffer, len),
528 DMA_TO_DEVICE);
fd0a05ce 529 }
a5e9c572
AD		 530 tx_buffer->next_to_watch = NULL;
531 tx_buffer->skb = NULL;
35a1e2ad 532 dma_unmap_len_set(tx_buffer, len, 0);
a5e9c572 533 /* tx_buffer must be completely set up in the transmit path */
fd0a05ce
JB		 534}
535
536/**
537 * i40e_clean_tx_ring - Free any empty Tx buffers
538 * @tx_ring: ring to be cleaned
539 **/
540void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
541{
fd0a05ce
JB		 542 unsigned long bi_size;
543 u16 i;
544
545 /* ring already cleared, nothing to do */
546 if (!tx_ring->tx_bi)
547 return;
548
549 /* Free all the Tx ring sk_buffs */
a5e9c572
AD		 550 for (i = 0; i < tx_ring->count; i++)
551 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
fd0a05ce
JB		 552
553 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
554 memset(tx_ring->tx_bi, 0, bi_size);
555
556 /* Zero out the descriptor ring */
557 memset(tx_ring->desc, 0, tx_ring->size);
558
559 tx_ring->next_to_use = 0;
560 tx_ring->next_to_clean = 0;
7070ce0a
AD		 561
562 if (!tx_ring->netdev)
563 return;
564
565 /* cleanup Tx queue statistics */
566 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
567 tx_ring->queue_index));
fd0a05ce
JB		 568}
569
570/**
571 * i40e_free_tx_resources - Free Tx resources per queue
572 * @tx_ring: Tx descriptor ring for a specific queue
573 *
574 * Free all transmit software resources
575 **/
576void i40e_free_tx_resources(struct i40e_ring *tx_ring)
577{
578 i40e_clean_tx_ring(tx_ring);
579 kfree(tx_ring->tx_bi);
580 tx_ring->tx_bi = NULL;
581
582 if (tx_ring->desc) {
583 dma_free_coherent(tx_ring->dev, tx_ring->size,
584 tx_ring->desc, tx_ring->dma);
585 tx_ring->desc = NULL;
586 }
587}
588
a68de58d
JB		 589/**
590 * i40e_get_head - Retrieve head from head writeback
591 * @tx_ring: tx ring to fetch head of
592 *
593 * Returns value of Tx ring head based on value stored
594 * in head write-back location
595 **/
596static inline u32 i40e_get_head(struct i40e_ring *tx_ring)
597{
598 void *head = (struct i40e_tx_desc *)tx_ring->desc + tx_ring->count;
599
600 return le32_to_cpu(*(volatile __le32 *)head);
601}
602
fd0a05ce
JB		 603/**
604 * i40e_get_tx_pending - how many tx descriptors not processed
605 * @tx_ring: the ring of descriptors
606 *
607 * Since there is no access to the ring head register
608 * in XL710, we need to use our local copies
609 **/
610static u32 i40e_get_tx_pending(struct i40e_ring *ring)
611{
a68de58d
JB		 612 u32 head, tail;
613
614 head = i40e_get_head(ring);
615 tail = readl(ring->tail);
616
617 if (head != tail)
618 return (head < tail) ?
619 tail - head : (tail + ring->count - head);
620
621 return 0;
fd0a05ce
JB		 622}
623
624/**
625 * i40e_check_tx_hang - Is there a hang in the Tx queue
626 * @tx_ring: the ring of descriptors
627 **/
628static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
629{
a68de58d
JB		 630 u32 tx_done = tx_ring->stats.packets;
631 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
fd0a05ce 632 u32 tx_pending = i40e_get_tx_pending(tx_ring);
810b3ae4 633 struct i40e_pf *pf = tx_ring->vsi->back;
fd0a05ce
JB		 634 bool ret = false;
635
636 clear_check_for_tx_hang(tx_ring);
637
638 /* Check for a hung queue, but be thorough. This verifies
639 * that a transmit has been completed since the previous
640 * check AND there is at least one packet pending. The
641 * ARMED bit is set to indicate a potential hang. The
642 * bit is cleared if a pause frame is received to remove
643 * false hang detection due to PFC or 802.3x frames. By
644 * requiring this to fail twice we avoid races with
645 * PFC clearing the ARMED bit and conditions where we
646 * run the check_tx_hang logic with a transmit completion
647 * pending but without time to complete it yet.
648 */
a68de58d 649 if ((tx_done_old == tx_done) && tx_pending) {
fd0a05ce
JB		 650 /* make sure it is true for two checks in a row */
651 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
652 &tx_ring->state);
a68de58d
JB		 653 } else if (tx_done_old == tx_done &&
654 (tx_pending < I40E_MIN_DESC_PENDING) && (tx_pending > 0)) {
810b3ae4
ASJ		 655 if (I40E_DEBUG_FLOW & pf->hw.debug_mask)
656 dev_info(tx_ring->dev, "HW needs some more descs to do a cacheline flush. tx_pending %d, queue %d",
657 tx_pending, tx_ring->queue_index);
658 pf->tx_sluggish_count++;
fd0a05ce
JB		 659 } else {
660 /* update completed stats and disarm the hang check */
a68de58d 661 tx_ring->tx_stats.tx_done_old = tx_done;
fd0a05ce
JB		 662 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
663 }
664
665 return ret;
666}
667
d91649f5
JB		 668#define WB_STRIDE 0x3
669
fd0a05ce
JB		 670/**
671 * i40e_clean_tx_irq - Reclaim resources after transmit completes
672 * @tx_ring: tx ring to clean
673 * @budget: how many cleans we're allowed
674 *
675 * Returns true if there's any budget left (e.g. the clean is finished)
676 **/
677static bool i40e_clean_tx_irq(struct i40e_ring *tx_ring, int budget)
678{
679 u16 i = tx_ring->next_to_clean;
680 struct i40e_tx_buffer *tx_buf;
1943d8ba 681 struct i40e_tx_desc *tx_head;
fd0a05ce
JB		 682 struct i40e_tx_desc *tx_desc;
683 unsigned int total_packets = 0;
684 unsigned int total_bytes = 0;
685
686 tx_buf = &tx_ring->tx_bi[i];
687 tx_desc = I40E_TX_DESC(tx_ring, i);
a5e9c572 688 i -= tx_ring->count;
fd0a05ce 689
1943d8ba
JB		 690 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
691
a5e9c572
AD		 692 do {
693 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
fd0a05ce
JB		 694
695 /* if next_to_watch is not set then there is no work pending */
696 if (!eop_desc)
697 break;
698
a5e9c572
AD		 699 /* prevent any other reads prior to eop_desc */
700 read_barrier_depends();
701
1943d8ba
JB		 702 /* we have caught up to head, no work left to do */
703 if (tx_head == tx_desc)
fd0a05ce
JB		 704 break;
705
c304fdac 706 /* clear next_to_watch to prevent false hangs */
fd0a05ce 707 tx_buf->next_to_watch = NULL;
fd0a05ce 708
a5e9c572
AD		 709 /* update the statistics for this packet */
710 total_bytes += tx_buf->bytecount;
711 total_packets += tx_buf->gso_segs;
fd0a05ce 712
a5e9c572 713 /* free the skb */
a81fb049 714 dev_consume_skb_any(tx_buf->skb);
fd0a05ce 715
a5e9c572
AD		 716 /* unmap skb header data */
717 dma_unmap_single(tx_ring->dev,
718 dma_unmap_addr(tx_buf, dma),
719 dma_unmap_len(tx_buf, len),
720 DMA_TO_DEVICE);
fd0a05ce 721
a5e9c572
AD		 722 /* clear tx_buffer data */
723 tx_buf->skb = NULL;
724 dma_unmap_len_set(tx_buf, len, 0);
fd0a05ce 725
a5e9c572
AD		 726 /* unmap remaining buffers */
727 while (tx_desc != eop_desc) {
fd0a05ce
JB		 728
729 tx_buf++;
730 tx_desc++;
731 i++;
a5e9c572
AD		 732 if (unlikely(!i)) {
733 i -= tx_ring->count;
fd0a05ce
JB		 734 tx_buf = tx_ring->tx_bi;
735 tx_desc = I40E_TX_DESC(tx_ring, 0);
736 }
fd0a05ce 737
a5e9c572
AD		 738 /* unmap any remaining paged data */
739 if (dma_unmap_len(tx_buf, len)) {
740 dma_unmap_page(tx_ring->dev,
741 dma_unmap_addr(tx_buf, dma),
742 dma_unmap_len(tx_buf, len),
743 DMA_TO_DEVICE);
744 dma_unmap_len_set(tx_buf, len, 0);
745 }
746 }
747
748 /* move us one more past the eop_desc for start of next pkt */
749 tx_buf++;
750 tx_desc++;
751 i++;
752 if (unlikely(!i)) {
753 i -= tx_ring->count;
754 tx_buf = tx_ring->tx_bi;
755 tx_desc = I40E_TX_DESC(tx_ring, 0);
756 }
757
758 /* update budget accounting */
759 budget--;
760 } while (likely(budget));
761
762 i += tx_ring->count;
fd0a05ce 763 tx_ring->next_to_clean = i;
980e9b11 764 u64_stats_update_begin(&tx_ring->syncp);
a114d0a6
AD		 765 tx_ring->stats.bytes += total_bytes;
766 tx_ring->stats.packets += total_packets;
980e9b11 767 u64_stats_update_end(&tx_ring->syncp);
fd0a05ce
JB		 768 tx_ring->q_vector->tx.total_bytes += total_bytes;
769 tx_ring->q_vector->tx.total_packets += total_packets;
a5e9c572 770
d91649f5
JB		 771 /* check to see if there are any non-cache aligned descriptors
772 * waiting to be written back, and kick the hardware to force
773 * them to be written back in case of napi polling
774 */
775 if (budget &&
776 !((i & WB_STRIDE) == WB_STRIDE) &&
777 !test_bit(__I40E_DOWN, &tx_ring->vsi->state) &&
778 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
779 tx_ring->arm_wb = true;
780 else
781 tx_ring->arm_wb = false;
782
fd0a05ce
JB		 783 if (check_for_tx_hang(tx_ring) && i40e_check_tx_hang(tx_ring)) {
784 /* schedule immediate reset if we believe we hung */
785 dev_info(tx_ring->dev, "Detected Tx Unit Hang\n"
786 " VSI <%d>\n"
787 " Tx Queue <%d>\n"
788 " next_to_use <%x>\n"
789 " next_to_clean <%x>\n",
790 tx_ring->vsi->seid,
791 tx_ring->queue_index,
792 tx_ring->next_to_use, i);
793 dev_info(tx_ring->dev, "tx_bi[next_to_clean]\n"
794 " time_stamp <%lx>\n"
795 " jiffies <%lx>\n",
796 tx_ring->tx_bi[i].time_stamp, jiffies);
797
798 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
799
800 dev_info(tx_ring->dev,
d91649f5 801 "tx hang detected on queue %d, reset requested\n",
fd0a05ce
JB		 802 tx_ring->queue_index);
803
d91649f5
JB		 804 /* do not fire the reset immediately, wait for the stack to
805 * decide we are truly stuck, also prevents every queue from
806 * simultaneously requesting a reset
807 */
fd0a05ce 808
d91649f5
JB		 809 /* the adapter is about to reset, no point in enabling polling */
810 budget = 1;
fd0a05ce
JB		 811 }
812
7070ce0a
AD		 813 netdev_tx_completed_queue(netdev_get_tx_queue(tx_ring->netdev,
814 tx_ring->queue_index),
815 total_packets, total_bytes);
816
fd0a05ce
JB		 817#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
818 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
819 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
820 /* Make sure that anybody stopping the queue after this
821 * sees the new next_to_clean.
822 */
823 smp_mb();
824 if (__netif_subqueue_stopped(tx_ring->netdev,
825 tx_ring->queue_index) &&
826 !test_bit(__I40E_DOWN, &tx_ring->vsi->state)) {
827 netif_wake_subqueue(tx_ring->netdev,
828 tx_ring->queue_index);
829 ++tx_ring->tx_stats.restart_queue;
830 }
831 }
832
d91649f5
JB		 833 return !!budget;
834}
835
836/**
837 * i40e_force_wb - Arm hardware to do a wb on noncache aligned descriptors
838 * @vsi: the VSI we care about
839 * @q_vector: the vector on which to force writeback
840 *
841 **/
842static void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
843{
844 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
845 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
c29af37f
ASJ		 846 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
847 /* allow 00 to be written to the index */
d91649f5
JB		 848
849 wr32(&vsi->back->hw,
850 I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1),
851 val);
fd0a05ce
JB		 852}
853
854/**
855 * i40e_set_new_dynamic_itr - Find new ITR level
856 * @rc: structure containing ring performance data
857 *
858 * Stores a new ITR value based on packets and byte counts during
859 * the last interrupt. The advantage of per interrupt computation
860 * is faster updates and more accurate ITR for the current traffic
861 * pattern. Constants in this function were computed based on
862 * theoretical maximum wire speed and thresholds were set based on
863 * testing data as well as attempting to minimize response time
864 * while increasing bulk throughput.
865 **/
866static void i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
867{
868 enum i40e_latency_range new_latency_range = rc->latency_range;
869 u32 new_itr = rc->itr;
870 int bytes_per_int;
871
872 if (rc->total_packets == 0 || !rc->itr)
873 return;
874
875 /* simple throttlerate management
876 * 0-10MB/s lowest (100000 ints/s)
877 * 10-20MB/s low (20000 ints/s)
878 * 20-1249MB/s bulk (8000 ints/s)
879 */
880 bytes_per_int = rc->total_bytes / rc->itr;
881 switch (rc->itr) {
882 case I40E_LOWEST_LATENCY:
883 if (bytes_per_int > 10)
884 new_latency_range = I40E_LOW_LATENCY;
885 break;
886 case I40E_LOW_LATENCY:
887 if (bytes_per_int > 20)
888 new_latency_range = I40E_BULK_LATENCY;
889 else if (bytes_per_int <= 10)
890 new_latency_range = I40E_LOWEST_LATENCY;
891 break;
892 case I40E_BULK_LATENCY:
893 if (bytes_per_int <= 20)
894 rc->latency_range = I40E_LOW_LATENCY;
895 break;
896 }
897
898 switch (new_latency_range) {
899 case I40E_LOWEST_LATENCY:
900 new_itr = I40E_ITR_100K;
901 break;
902 case I40E_LOW_LATENCY:
903 new_itr = I40E_ITR_20K;
904 break;
905 case I40E_BULK_LATENCY:
906 new_itr = I40E_ITR_8K;
907 break;
908 default:
909 break;
910 }
911
912 if (new_itr != rc->itr) {
913 /* do an exponential smoothing */
914 new_itr = (10 * new_itr * rc->itr) /
915 ((9 * new_itr) + rc->itr);
916 rc->itr = new_itr & I40E_MAX_ITR;
917 }
918
919 rc->total_bytes = 0;
920 rc->total_packets = 0;
921}
922
923/**
924 * i40e_update_dynamic_itr - Adjust ITR based on bytes per int
925 * @q_vector: the vector to adjust
926 **/
927static void i40e_update_dynamic_itr(struct i40e_q_vector *q_vector)
928{
929 u16 vector = q_vector->vsi->base_vector + q_vector->v_idx;
930 struct i40e_hw *hw = &q_vector->vsi->back->hw;
931 u32 reg_addr;
932 u16 old_itr;
933
934 reg_addr = I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1);
935 old_itr = q_vector->rx.itr;
936 i40e_set_new_dynamic_itr(&q_vector->rx);
937 if (old_itr != q_vector->rx.itr)
938 wr32(hw, reg_addr, q_vector->rx.itr);
939
940 reg_addr = I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1);
941 old_itr = q_vector->tx.itr;
942 i40e_set_new_dynamic_itr(&q_vector->tx);
943 if (old_itr != q_vector->tx.itr)
944 wr32(hw, reg_addr, q_vector->tx.itr);
fd0a05ce
JB		 945}
946
947/**
948 * i40e_clean_programming_status - clean the programming status descriptor
949 * @rx_ring: the rx ring that has this descriptor
950 * @rx_desc: the rx descriptor written back by HW
951 *
952 * Flow director should handle FD_FILTER_STATUS to check its filter programming
953 * status being successful or not and take actions accordingly. FCoE should
954 * handle its context/filter programming/invalidation status and take actions.
955 *
956 **/
957static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
958 union i40e_rx_desc *rx_desc)
959{
960 u64 qw;
961 u8 id;
962
963 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
964 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
965 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
966
967 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
55a5e60b 968 i40e_fd_handle_status(rx_ring, rx_desc, id);
38e00438
VD		 969#ifdef I40E_FCOE
970 else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) ||
971 (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS))
972 i40e_fcoe_handle_status(rx_ring, rx_desc, id);
973#endif
fd0a05ce
JB		 974}
975
976/**
977 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
978 * @tx_ring: the tx ring to set up
979 *
980 * Return 0 on success, negative on error
981 **/
982int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
983{
984 struct device *dev = tx_ring->dev;
985 int bi_size;
986
987 if (!dev)
988 return -ENOMEM;
989
990 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
991 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
992 if (!tx_ring->tx_bi)
993 goto err;
994
995 /* round up to nearest 4K */
996 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1943d8ba
JB		 997 /* add u32 for head writeback, align after this takes care of
998 * guaranteeing this is at least one cache line in size
999 */
1000 tx_ring->size += sizeof(u32);
fd0a05ce
JB		 1001 tx_ring->size = ALIGN(tx_ring->size, 4096);
1002 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1003 &tx_ring->dma, GFP_KERNEL);
1004 if (!tx_ring->desc) {
1005 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1006 tx_ring->size);
1007 goto err;
1008 }
1009
1010 tx_ring->next_to_use = 0;
1011 tx_ring->next_to_clean = 0;
1012 return 0;
1013
1014err:
1015 kfree(tx_ring->tx_bi);
1016 tx_ring->tx_bi = NULL;
1017 return -ENOMEM;
1018}
1019
1020/**
1021 * i40e_clean_rx_ring - Free Rx buffers
1022 * @rx_ring: ring to be cleaned
1023 **/
1024void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1025{
1026 struct device *dev = rx_ring->dev;
1027 struct i40e_rx_buffer *rx_bi;
1028 unsigned long bi_size;
1029 u16 i;
1030
1031 /* ring already cleared, nothing to do */
1032 if (!rx_ring->rx_bi)
1033 return;
1034
a132af24
MW		 1035 if (ring_is_ps_enabled(rx_ring)) {
1036 int bufsz = ALIGN(rx_ring->rx_hdr_len, 256) * rx_ring->count;
1037
1038 rx_bi = &rx_ring->rx_bi[0];
1039 if (rx_bi->hdr_buf) {
1040 dma_free_coherent(dev,
1041 bufsz,
1042 rx_bi->hdr_buf,
1043 rx_bi->dma);
1044 for (i = 0; i < rx_ring->count; i++) {
1045 rx_bi = &rx_ring->rx_bi[i];
1046 rx_bi->dma = 0;
1047 rx_bi->hdr_buf = 0;
1048 }
1049 }
1050 }
fd0a05ce
JB		 1051 /* Free all the Rx ring sk_buffs */
1052 for (i = 0; i < rx_ring->count; i++) {
1053 rx_bi = &rx_ring->rx_bi[i];
1054 if (rx_bi->dma) {
1055 dma_unmap_single(dev,
1056 rx_bi->dma,
1057 rx_ring->rx_buf_len,
1058 DMA_FROM_DEVICE);
1059 rx_bi->dma = 0;
1060 }
1061 if (rx_bi->skb) {
1062 dev_kfree_skb(rx_bi->skb);
1063 rx_bi->skb = NULL;
1064 }
1065 if (rx_bi->page) {
1066 if (rx_bi->page_dma) {
1067 dma_unmap_page(dev,
1068 rx_bi->page_dma,
1069 PAGE_SIZE / 2,
1070 DMA_FROM_DEVICE);
1071 rx_bi->page_dma = 0;
1072 }
1073 __free_page(rx_bi->page);
1074 rx_bi->page = NULL;
1075 rx_bi->page_offset = 0;
1076 }
1077 }
1078
1079 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1080 memset(rx_ring->rx_bi, 0, bi_size);
1081
1082 /* Zero out the descriptor ring */
1083 memset(rx_ring->desc, 0, rx_ring->size);
1084
1085 rx_ring->next_to_clean = 0;
1086 rx_ring->next_to_use = 0;
1087}
1088
1089/**
1090 * i40e_free_rx_resources - Free Rx resources
1091 * @rx_ring: ring to clean the resources from
1092 *
1093 * Free all receive software resources
1094 **/
1095void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1096{
1097 i40e_clean_rx_ring(rx_ring);
1098 kfree(rx_ring->rx_bi);
1099 rx_ring->rx_bi = NULL;
1100
1101 if (rx_ring->desc) {
1102 dma_free_coherent(rx_ring->dev, rx_ring->size,
1103 rx_ring->desc, rx_ring->dma);
1104 rx_ring->desc = NULL;
1105 }
1106}
1107
a132af24
MW		 1108/**
1109 * i40e_alloc_rx_headers - allocate rx header buffers
1110 * @rx_ring: ring to alloc buffers
1111 *
1112 * Allocate rx header buffers for the entire ring. As these are static,
1113 * this is only called when setting up a new ring.
1114 **/
1115void i40e_alloc_rx_headers(struct i40e_ring *rx_ring)
1116{
1117 struct device *dev = rx_ring->dev;
1118 struct i40e_rx_buffer *rx_bi;
1119 dma_addr_t dma;
1120 void *buffer;
1121 int buf_size;
1122 int i;
1123
1124 if (rx_ring->rx_bi[0].hdr_buf)
1125 return;
1126 /* Make sure the buffers don't cross cache line boundaries. */
1127 buf_size = ALIGN(rx_ring->rx_hdr_len, 256);
1128 buffer = dma_alloc_coherent(dev, buf_size * rx_ring->count,
1129 &dma, GFP_KERNEL);
1130 if (!buffer)
1131 return;
1132 for (i = 0; i < rx_ring->count; i++) {
1133 rx_bi = &rx_ring->rx_bi[i];
1134 rx_bi->dma = dma + (i * buf_size);
1135 rx_bi->hdr_buf = buffer + (i * buf_size);
1136 }
1137}
1138
fd0a05ce
JB		 1139/**
1140 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1141 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1142 *
1143 * Returns 0 on success, negative on failure
1144 **/
1145int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1146{
1147 struct device *dev = rx_ring->dev;
1148 int bi_size;
1149
1150 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1151 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1152 if (!rx_ring->rx_bi)
1153 goto err;
1154
f217d6ca 1155 u64_stats_init(&rx_ring->syncp);
638702bd 1156
fd0a05ce
JB		 1157 /* Round up to nearest 4K */
1158 rx_ring->size = ring_is_16byte_desc_enabled(rx_ring)
1159 ? rx_ring->count * sizeof(union i40e_16byte_rx_desc)
1160 : rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1161 rx_ring->size = ALIGN(rx_ring->size, 4096);
1162 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1163 &rx_ring->dma, GFP_KERNEL);
1164
1165 if (!rx_ring->desc) {
1166 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1167 rx_ring->size);
1168 goto err;
1169 }
1170
1171 rx_ring->next_to_clean = 0;
1172 rx_ring->next_to_use = 0;
1173
1174 return 0;
1175err:
1176 kfree(rx_ring->rx_bi);
1177 rx_ring->rx_bi = NULL;
1178 return -ENOMEM;
1179}
1180
1181/**
1182 * i40e_release_rx_desc - Store the new tail and head values
1183 * @rx_ring: ring to bump
1184 * @val: new head index
1185 **/
1186static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1187{
1188 rx_ring->next_to_use = val;
1189 /* Force memory writes to complete before letting h/w
1190 * know there are new descriptors to fetch. (Only
1191 * applicable for weak-ordered memory model archs,
1192 * such as IA-64).
1193 */
1194 wmb();
1195 writel(val, rx_ring->tail);
1196}
1197
1198/**
a132af24 1199 * i40e_alloc_rx_buffers_ps - Replace used receive buffers; packet split
fd0a05ce
JB		 1200 * @rx_ring: ring to place buffers on
1201 * @cleaned_count: number of buffers to replace
1202 **/
a132af24
MW		 1203void i40e_alloc_rx_buffers_ps(struct i40e_ring *rx_ring, u16 cleaned_count)
1204{
1205 u16 i = rx_ring->next_to_use;
1206 union i40e_rx_desc *rx_desc;
1207 struct i40e_rx_buffer *bi;
1208
1209 /* do nothing if no valid netdev defined */
1210 if (!rx_ring->netdev || !cleaned_count)
1211 return;
1212
1213 while (cleaned_count--) {
1214 rx_desc = I40E_RX_DESC(rx_ring, i);
1215 bi = &rx_ring->rx_bi[i];
1216
1217 if (bi->skb) /* desc is in use */
1218 goto no_buffers;
1219 if (!bi->page) {
1220 bi->page = alloc_page(GFP_ATOMIC);
1221 if (!bi->page) {
1222 rx_ring->rx_stats.alloc_page_failed++;
1223 goto no_buffers;
1224 }
1225 }
1226
1227 if (!bi->page_dma) {
1228 /* use a half page if we're re-using */
1229 bi->page_offset ^= PAGE_SIZE / 2;
1230 bi->page_dma = dma_map_page(rx_ring->dev,
1231 bi->page,
1232 bi->page_offset,
1233 PAGE_SIZE / 2,
1234 DMA_FROM_DEVICE);
1235 if (dma_mapping_error(rx_ring->dev,
1236 bi->page_dma)) {
1237 rx_ring->rx_stats.alloc_page_failed++;
1238 bi->page_dma = 0;
1239 goto no_buffers;
1240 }
1241 }
1242
1243 dma_sync_single_range_for_device(rx_ring->dev,
1244 bi->dma,
1245 0,
1246 rx_ring->rx_hdr_len,
1247 DMA_FROM_DEVICE);
1248 /* Refresh the desc even if buffer_addrs didn't change
1249 * because each write-back erases this info.
1250 */
1251 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1252 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1253 i++;
1254 if (i == rx_ring->count)
1255 i = 0;
1256 }
1257
1258no_buffers:
1259 if (rx_ring->next_to_use != i)
1260 i40e_release_rx_desc(rx_ring, i);
1261}
1262
1263/**
1264 * i40e_alloc_rx_buffers_1buf - Replace used receive buffers; single buffer
1265 * @rx_ring: ring to place buffers on
1266 * @cleaned_count: number of buffers to replace
1267 **/
1268void i40e_alloc_rx_buffers_1buf(struct i40e_ring *rx_ring, u16 cleaned_count)
fd0a05ce
JB		 1269{
1270 u16 i = rx_ring->next_to_use;
1271 union i40e_rx_desc *rx_desc;
1272 struct i40e_rx_buffer *bi;
1273 struct sk_buff *skb;
1274
1275 /* do nothing if no valid netdev defined */
1276 if (!rx_ring->netdev || !cleaned_count)
1277 return;
1278
1279 while (cleaned_count--) {
1280 rx_desc = I40E_RX_DESC(rx_ring, i);
1281 bi = &rx_ring->rx_bi[i];
1282 skb = bi->skb;
1283
1284 if (!skb) {
1285 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1286 rx_ring->rx_buf_len);
1287 if (!skb) {
420136cc 1288 rx_ring->rx_stats.alloc_buff_failed++;
fd0a05ce
JB		 1289 goto no_buffers;
1290 }
1291 /* initialize queue mapping */
1292 skb_record_rx_queue(skb, rx_ring->queue_index);
1293 bi->skb = skb;
1294 }
1295
1296 if (!bi->dma) {
1297 bi->dma = dma_map_single(rx_ring->dev,
1298 skb->data,
1299 rx_ring->rx_buf_len,
1300 DMA_FROM_DEVICE);
1301 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
420136cc 1302 rx_ring->rx_stats.alloc_buff_failed++;
fd0a05ce
JB		 1303 bi->dma = 0;
1304 goto no_buffers;
1305 }
1306 }
1307
a132af24
MW		 1308 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1309 rx_desc->read.hdr_addr = 0;
fd0a05ce
JB		 1310 i++;
1311 if (i == rx_ring->count)
1312 i = 0;
1313 }
1314
1315no_buffers:
1316 if (rx_ring->next_to_use != i)
1317 i40e_release_rx_desc(rx_ring, i);
1318}
1319
1320/**
1321 * i40e_receive_skb - Send a completed packet up the stack
1322 * @rx_ring: rx ring in play
1323 * @skb: packet to send up
1324 * @vlan_tag: vlan tag for packet
1325 **/
1326static void i40e_receive_skb(struct i40e_ring *rx_ring,
1327 struct sk_buff *skb, u16 vlan_tag)
1328{
1329 struct i40e_q_vector *q_vector = rx_ring->q_vector;
1330 struct i40e_vsi *vsi = rx_ring->vsi;
1331 u64 flags = vsi->back->flags;
1332
1333 if (vlan_tag & VLAN_VID_MASK)
1334 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
1335
1336 if (flags & I40E_FLAG_IN_NETPOLL)
1337 netif_rx(skb);
1338 else
1339 napi_gro_receive(&q_vector->napi, skb);
1340}
1341
1342/**
1343 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1344 * @vsi: the VSI we care about
1345 * @skb: skb currently being received and modified
1346 * @rx_status: status value of last descriptor in packet
1347 * @rx_error: error value of last descriptor in packet
8144f0f7 1348 * @rx_ptype: ptype value of last descriptor in packet
fd0a05ce
JB		 1349 **/
1350static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1351 struct sk_buff *skb,
1352 u32 rx_status,
8144f0f7
JG		 1353 u32 rx_error,
1354 u16 rx_ptype)
fd0a05ce 1355{
8a3c91cc
JB		 1356 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(rx_ptype);
1357 bool ipv4 = false, ipv6 = false;
8144f0f7
JG		 1358 bool ipv4_tunnel, ipv6_tunnel;
1359 __wsum rx_udp_csum;
8144f0f7 1360 struct iphdr *iph;
8a3c91cc 1361 __sum16 csum;
8144f0f7 1362
f8faaa40
ASJ		 1363 ipv4_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT4_MAC_PAY3) &&
1364 (rx_ptype <= I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4);
1365 ipv6_tunnel = (rx_ptype >= I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
1366 (rx_ptype <= I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
8144f0f7 1367
fd0a05ce
JB		 1368 skb->ip_summed = CHECKSUM_NONE;
1369
1370 /* Rx csum enabled and ip headers found? */
8a3c91cc
JB		 1371 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1372 return;
1373
1374 /* did the hardware decode the packet and checksum? */
1375 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1376 return;
1377
1378 /* both known and outer_ip must be set for the below code to work */
1379 if (!(decoded.known && decoded.outer_ip))
fd0a05ce
JB		 1380 return;
1381
8a3c91cc
JB		 1382 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1383 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4)
1384 ipv4 = true;
1385 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1386 decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
1387 ipv6 = true;
1388
1389 if (ipv4 &&
1390 (rx_error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
1391 (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1392 goto checksum_fail;
1393
ddf1d0d7 1394 /* likely incorrect csum if alternate IP extension headers found */
8a3c91cc 1395 if (ipv6 &&
8a3c91cc
JB		 1396 rx_status & (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1397 /* don't increment checksum err here, non-fatal err */
8ee75a8e
SN		 1398 return;
1399
8a3c91cc
JB		 1400 /* there was some L4 error, count error and punt packet to the stack */
1401 if (rx_error & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))
1402 goto checksum_fail;
1403
1404 /* handle packets that were not able to be checksummed due
1405 * to arrival speed, in this case the stack can compute
1406 * the csum.
1407 */
1408 if (rx_error & (1 << I40E_RX_DESC_ERROR_PPRS_SHIFT))
fd0a05ce 1409 return;
fd0a05ce 1410
8a3c91cc
JB		 1411 /* If VXLAN traffic has an outer UDPv4 checksum we need to check
1412 * it in the driver, hardware does not do it for us.
1413 * Since L3L4P bit was set we assume a valid IHL value (>=5)
1414 * so the total length of IPv4 header is IHL*4 bytes
1415 * The UDP_0 bit *may* bet set if the *inner* header is UDP
1416 */
f6385979 1417 if (ipv4_tunnel) {
8144f0f7
JG		 1418 skb->transport_header = skb->mac_header +
1419 sizeof(struct ethhdr) +
1420 (ip_hdr(skb)->ihl * 4);
1421
1422 /* Add 4 bytes for VLAN tagged packets */
1423 skb->transport_header += (skb->protocol == htons(ETH_P_8021Q) ||
1424 skb->protocol == htons(ETH_P_8021AD))
1425 ? VLAN_HLEN : 0;
1426
f6385979
AS		 1427 if ((ip_hdr(skb)->protocol == IPPROTO_UDP) &&
1428 (udp_hdr(skb)->check != 0)) {
1429 rx_udp_csum = udp_csum(skb);
1430 iph = ip_hdr(skb);
1431 csum = csum_tcpudp_magic(
1432 iph->saddr, iph->daddr,
1433 (skb->len - skb_transport_offset(skb)),
1434 IPPROTO_UDP, rx_udp_csum);
8144f0f7 1435
f6385979
AS		 1436 if (udp_hdr(skb)->check != csum)
1437 goto checksum_fail;
1438
1439 } /* else its GRE and so no outer UDP header */
8144f0f7
JG		 1440 }
1441
fd0a05ce 1442 skb->ip_summed = CHECKSUM_UNNECESSARY;
fa4ba69b 1443 skb->csum_level = ipv4_tunnel || ipv6_tunnel;
8a3c91cc
JB		 1444
1445 return;
1446
1447checksum_fail:
1448 vsi->back->hw_csum_rx_error++;
fd0a05ce
JB		 1449}
1450
1451/**
1452 * i40e_rx_hash - returns the hash value from the Rx descriptor
1453 * @ring: descriptor ring
1454 * @rx_desc: specific descriptor
1455 **/
1456static inline u32 i40e_rx_hash(struct i40e_ring *ring,
1457 union i40e_rx_desc *rx_desc)
1458{
8a494920
JB		 1459 const __le64 rss_mask =
1460 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1461 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1462
1463 if ((ring->netdev->features & NETIF_F_RXHASH) &&
1464 (rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask)
1465 return le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1466 else
1467 return 0;
fd0a05ce
JB		 1468}
1469
206812b5
JB		 1470/**
1471 * i40e_ptype_to_hash - get a hash type
1472 * @ptype: the ptype value from the descriptor
1473 *
1474 * Returns a hash type to be used by skb_set_hash
1475 **/
1476static inline enum pkt_hash_types i40e_ptype_to_hash(u8 ptype)
1477{
1478 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1479
1480 if (!decoded.known)
1481 return PKT_HASH_TYPE_NONE;
1482
1483 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1484 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1485 return PKT_HASH_TYPE_L4;
1486 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1487 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1488 return PKT_HASH_TYPE_L3;
1489 else
1490 return PKT_HASH_TYPE_L2;
1491}
1492
fd0a05ce 1493/**
a132af24 1494 * i40e_clean_rx_irq_ps - Reclaim resources after receive; packet split
fd0a05ce
JB		 1495 * @rx_ring: rx ring to clean
1496 * @budget: how many cleans we're allowed
1497 *
1498 * Returns true if there's any budget left (e.g. the clean is finished)
1499 **/
a132af24 1500static int i40e_clean_rx_irq_ps(struct i40e_ring *rx_ring, int budget)
fd0a05ce
JB		 1501{
1502 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1503 u16 rx_packet_len, rx_header_len, rx_sph, rx_hbo;
1504 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1505 const int current_node = numa_node_id();
1506 struct i40e_vsi *vsi = rx_ring->vsi;
1507 u16 i = rx_ring->next_to_clean;
1508 union i40e_rx_desc *rx_desc;
1509 u32 rx_error, rx_status;
206812b5 1510 u8 rx_ptype;
fd0a05ce
JB		 1511 u64 qword;
1512
390f86df
EB		 1513 if (budget <= 0)
1514 return 0;
1515
a132af24 1516 do {
fd0a05ce
JB		 1517 struct i40e_rx_buffer *rx_bi;
1518 struct sk_buff *skb;
1519 u16 vlan_tag;
a132af24
MW		 1520 /* return some buffers to hardware, one at a time is too slow */
1521 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1522 i40e_alloc_rx_buffers_ps(rx_ring, cleaned_count);
1523 cleaned_count = 0;
1524 }
1525
1526 i = rx_ring->next_to_clean;
1527 rx_desc = I40E_RX_DESC(rx_ring, i);
1528 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1529 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1530 I40E_RXD_QW1_STATUS_SHIFT;
1531
1532 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1533 break;
1534
1535 /* This memory barrier is needed to keep us from reading
1536 * any other fields out of the rx_desc until we know the
1537 * DD bit is set.
1538 */
1539 rmb();
fd0a05ce
JB		 1540 if (i40e_rx_is_programming_status(qword)) {
1541 i40e_clean_programming_status(rx_ring, rx_desc);
a132af24
MW		 1542 I40E_RX_INCREMENT(rx_ring, i);
1543 continue;
fd0a05ce
JB		 1544 }
1545 rx_bi = &rx_ring->rx_bi[i];
1546 skb = rx_bi->skb;
a132af24
MW		 1547 if (likely(!skb)) {
1548 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1549 rx_ring->rx_hdr_len);
1550 if (!skb)
1551 rx_ring->rx_stats.alloc_buff_failed++;
1552 /* initialize queue mapping */
1553 skb_record_rx_queue(skb, rx_ring->queue_index);
1554 /* we are reusing so sync this buffer for CPU use */
1555 dma_sync_single_range_for_cpu(rx_ring->dev,
1556 rx_bi->dma,
1557 0,
1558 rx_ring->rx_hdr_len,
1559 DMA_FROM_DEVICE);
1560 }
829af3ac
MW		 1561 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1562 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1563 rx_header_len = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK) >>
1564 I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
1565 rx_sph = (qword & I40E_RXD_QW1_LENGTH_SPH_MASK) >>
1566 I40E_RXD_QW1_LENGTH_SPH_SHIFT;
1567
1568 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1569 I40E_RXD_QW1_ERROR_SHIFT;
fd0a05ce
JB		 1570 rx_hbo = rx_error & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1571 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1572
8144f0f7
JG		 1573 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1574 I40E_RXD_QW1_PTYPE_SHIFT;
a132af24 1575 prefetch(rx_bi->page);
fd0a05ce 1576 rx_bi->skb = NULL;
a132af24
MW		 1577 cleaned_count++;
1578 if (rx_hbo || rx_sph) {
1579 int len;
fd0a05ce
JB		 1580 if (rx_hbo)
1581 len = I40E_RX_HDR_SIZE;
fd0a05ce 1582 else
a132af24
MW		 1583 len = rx_header_len;
1584 memcpy(__skb_put(skb, len), rx_bi->hdr_buf, len);
1585 } else if (skb->len == 0) {
1586 int len;
1587
1588 len = (rx_packet_len > skb_headlen(skb) ?
1589 skb_headlen(skb) : rx_packet_len);
1590 memcpy(__skb_put(skb, len),
1591 rx_bi->page + rx_bi->page_offset,
1592 len);
1593 rx_bi->page_offset += len;
1594 rx_packet_len -= len;
fd0a05ce
JB		 1595 }
1596
1597 /* Get the rest of the data if this was a header split */
a132af24 1598 if (rx_packet_len) {
fd0a05ce
JB		 1599 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1600 rx_bi->page,
1601 rx_bi->page_offset,
1602 rx_packet_len);
1603
1604 skb->len += rx_packet_len;
1605 skb->data_len += rx_packet_len;
1606 skb->truesize += rx_packet_len;
1607
1608 if ((page_count(rx_bi->page) == 1) &&
1609 (page_to_nid(rx_bi->page) == current_node))
1610 get_page(rx_bi->page);
1611 else
1612 rx_bi->page = NULL;
1613
1614 dma_unmap_page(rx_ring->dev,
1615 rx_bi->page_dma,
1616 PAGE_SIZE / 2,
1617 DMA_FROM_DEVICE);
1618 rx_bi->page_dma = 0;
1619 }
a132af24 1620 I40E_RX_INCREMENT(rx_ring, i);
fd0a05ce
JB		 1621
1622 if (unlikely(
1623 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1624 struct i40e_rx_buffer *next_buffer;
1625
1626 next_buffer = &rx_ring->rx_bi[i];
a132af24 1627 next_buffer->skb = skb;
fd0a05ce 1628 rx_ring->rx_stats.non_eop_descs++;
a132af24 1629 continue;
fd0a05ce
JB		 1630 }
1631
1632 /* ERR_MASK will only have valid bits if EOP set */
1633 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1634 dev_kfree_skb_any(skb);
8a3c91cc
JB		 1635 /* TODO: shouldn't we increment a counter indicating the
1636 * drop?
1637 */
a132af24 1638 continue;
fd0a05ce
JB		 1639 }
1640
206812b5
JB		 1641 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1642 i40e_ptype_to_hash(rx_ptype));
beb0dff1
JK		 1643 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1644 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1645 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1646 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1647 rx_ring->last_rx_timestamp = jiffies;
1648 }
1649
fd0a05ce
JB		 1650 /* probably a little skewed due to removing CRC */
1651 total_rx_bytes += skb->len;
1652 total_rx_packets++;
1653
1654 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
8144f0f7
JG		 1655
1656 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1657
fd0a05ce
JB		 1658 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1659 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1660 : 0;
38e00438
VD		 1661#ifdef I40E_FCOE
1662 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1663 dev_kfree_skb_any(skb);
a132af24 1664 continue;
38e00438
VD		 1665 }
1666#endif
a132af24 1667 skb_mark_napi_id(skb, &rx_ring->q_vector->napi);
fd0a05ce
JB		 1668 i40e_receive_skb(rx_ring, skb, vlan_tag);
1669
1670 rx_ring->netdev->last_rx = jiffies;
fd0a05ce 1671 rx_desc->wb.qword1.status_error_len = 0;
fd0a05ce 1672
a132af24
MW		 1673 } while (likely(total_rx_packets < budget));
1674
1675 u64_stats_update_begin(&rx_ring->syncp);
1676 rx_ring->stats.packets += total_rx_packets;
1677 rx_ring->stats.bytes += total_rx_bytes;
1678 u64_stats_update_end(&rx_ring->syncp);
1679 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1680 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1681
1682 return total_rx_packets;
1683}
1684
1685/**
1686 * i40e_clean_rx_irq_1buf - Reclaim resources after receive; single buffer
1687 * @rx_ring: rx ring to clean
1688 * @budget: how many cleans we're allowed
1689 *
1690 * Returns number of packets cleaned
1691 **/
1692static int i40e_clean_rx_irq_1buf(struct i40e_ring *rx_ring, int budget)
1693{
1694 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1695 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1696 struct i40e_vsi *vsi = rx_ring->vsi;
1697 union i40e_rx_desc *rx_desc;
1698 u32 rx_error, rx_status;
1699 u16 rx_packet_len;
1700 u8 rx_ptype;
1701 u64 qword;
1702 u16 i;
1703
1704 do {
1705 struct i40e_rx_buffer *rx_bi;
1706 struct sk_buff *skb;
1707 u16 vlan_tag;
fd0a05ce
JB		 1708 /* return some buffers to hardware, one at a time is too slow */
1709 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
a132af24 1710 i40e_alloc_rx_buffers_1buf(rx_ring, cleaned_count);
fd0a05ce
JB		 1711 cleaned_count = 0;
1712 }
1713
a132af24
MW		 1714 i = rx_ring->next_to_clean;
1715 rx_desc = I40E_RX_DESC(rx_ring, i);
fd0a05ce 1716 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
829af3ac 1717 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
a132af24
MW		 1718 I40E_RXD_QW1_STATUS_SHIFT;
1719
1720 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1721 break;
1722
1723 /* This memory barrier is needed to keep us from reading
1724 * any other fields out of the rx_desc until we know the
1725 * DD bit is set.
1726 */
1727 rmb();
1728
1729 if (i40e_rx_is_programming_status(qword)) {
1730 i40e_clean_programming_status(rx_ring, rx_desc);
1731 I40E_RX_INCREMENT(rx_ring, i);
1732 continue;
1733 }
1734 rx_bi = &rx_ring->rx_bi[i];
1735 skb = rx_bi->skb;
1736 prefetch(skb->data);
1737
1738 rx_packet_len = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1739 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1740
1741 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1742 I40E_RXD_QW1_ERROR_SHIFT;
1743 rx_error &= ~(1 << I40E_RX_DESC_ERROR_HBO_SHIFT);
1744
1745 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1746 I40E_RXD_QW1_PTYPE_SHIFT;
1747 rx_bi->skb = NULL;
1748 cleaned_count++;
1749
1750 /* Get the header and possibly the whole packet
1751 * If this is an skb from previous receive dma will be 0
1752 */
1753 skb_put(skb, rx_packet_len);
1754 dma_unmap_single(rx_ring->dev, rx_bi->dma, rx_ring->rx_buf_len,
1755 DMA_FROM_DEVICE);
1756 rx_bi->dma = 0;
1757
1758 I40E_RX_INCREMENT(rx_ring, i);
1759
1760 if (unlikely(
1761 !(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT)))) {
1762 rx_ring->rx_stats.non_eop_descs++;
1763 continue;
1764 }
1765
1766 /* ERR_MASK will only have valid bits if EOP set */
1767 if (unlikely(rx_error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
1768 dev_kfree_skb_any(skb);
1769 /* TODO: shouldn't we increment a counter indicating the
1770 * drop?
1771 */
1772 continue;
1773 }
1774
1775 skb_set_hash(skb, i40e_rx_hash(rx_ring, rx_desc),
1776 i40e_ptype_to_hash(rx_ptype));
1777 if (unlikely(rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK)) {
1778 i40e_ptp_rx_hwtstamp(vsi->back, skb, (rx_status &
1779 I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1780 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT);
1781 rx_ring->last_rx_timestamp = jiffies;
1782 }
1783
1784 /* probably a little skewed due to removing CRC */
1785 total_rx_bytes += skb->len;
1786 total_rx_packets++;
1787
1788 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1789
1790 i40e_rx_checksum(vsi, skb, rx_status, rx_error, rx_ptype);
1791
1792 vlan_tag = rx_status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)
1793 ? le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1)
1794 : 0;
1795#ifdef I40E_FCOE
1796 if (!i40e_fcoe_handle_offload(rx_ring, rx_desc, skb)) {
1797 dev_kfree_skb_any(skb);
1798 continue;
1799 }
1800#endif
1801 i40e_receive_skb(rx_ring, skb, vlan_tag);
1802
1803 rx_ring->netdev->last_rx = jiffies;
1804 rx_desc->wb.qword1.status_error_len = 0;
1805 } while (likely(total_rx_packets < budget));
fd0a05ce 1806
980e9b11 1807 u64_stats_update_begin(&rx_ring->syncp);
a114d0a6
AD		 1808 rx_ring->stats.packets += total_rx_packets;
1809 rx_ring->stats.bytes += total_rx_bytes;
980e9b11 1810 u64_stats_update_end(&rx_ring->syncp);
fd0a05ce
JB		 1811 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1812 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1813
a132af24 1814 return total_rx_packets;
fd0a05ce
JB		 1815}
1816
1817/**
1818 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
1819 * @napi: napi struct with our devices info in it
1820 * @budget: amount of work driver is allowed to do this pass, in packets
1821 *
1822 * This function will clean all queues associated with a q_vector.
1823 *
1824 * Returns the amount of work done
1825 **/
1826int i40e_napi_poll(struct napi_struct *napi, int budget)
1827{
1828 struct i40e_q_vector *q_vector =
1829 container_of(napi, struct i40e_q_vector, napi);
1830 struct i40e_vsi *vsi = q_vector->vsi;
cd0b6fa6 1831 struct i40e_ring *ring;
fd0a05ce 1832 bool clean_complete = true;
d91649f5 1833 bool arm_wb = false;
fd0a05ce 1834 int budget_per_ring;
a132af24 1835 int cleaned;
fd0a05ce
JB		 1836
1837 if (test_bit(__I40E_DOWN, &vsi->state)) {
1838 napi_complete(napi);
1839 return 0;
1840 }
1841
cd0b6fa6
AD		 1842 /* Since the actual Tx work is minimal, we can give the Tx a larger
1843 * budget and be more aggressive about cleaning up the Tx descriptors.
1844 */
d91649f5 1845 i40e_for_each_ring(ring, q_vector->tx) {
cd0b6fa6 1846 clean_complete &= i40e_clean_tx_irq(ring, vsi->work_limit);
d91649f5
JB		 1847 arm_wb |= ring->arm_wb;
1848 }
cd0b6fa6 1849
fd0a05ce
JB		 1850 /* We attempt to distribute budget to each Rx queue fairly, but don't
1851 * allow the budget to go below 1 because that would exit polling early.
fd0a05ce
JB		 1852 */
1853 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
cd0b6fa6 1854
a132af24
MW		 1855 i40e_for_each_ring(ring, q_vector->rx) {
1856 if (ring_is_ps_enabled(ring))
1857 cleaned = i40e_clean_rx_irq_ps(ring, budget_per_ring);
1858 else
1859 cleaned = i40e_clean_rx_irq_1buf(ring, budget_per_ring);
1860 /* if we didn't clean as many as budgeted, we must be done */
1861 clean_complete &= (budget_per_ring != cleaned);
1862 }
fd0a05ce
JB		 1863
1864 /* If work not completed, return budget and polling will return */
d91649f5
JB		 1865 if (!clean_complete) {
1866 if (arm_wb)
1867 i40e_force_wb(vsi, q_vector);
fd0a05ce 1868 return budget;
d91649f5 1869 }
fd0a05ce
JB		 1870
1871 /* Work is done so exit the polling mode and re-enable the interrupt */
1872 napi_complete(napi);
1873 if (ITR_IS_DYNAMIC(vsi->rx_itr_setting) ||
1874 ITR_IS_DYNAMIC(vsi->tx_itr_setting))
1875 i40e_update_dynamic_itr(q_vector);
1876
1877 if (!test_bit(__I40E_DOWN, &vsi->state)) {
1878 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
1879 i40e_irq_dynamic_enable(vsi,
1880 q_vector->v_idx + vsi->base_vector);
1881 } else {
1882 struct i40e_hw *hw = &vsi->back->hw;
1883 /* We re-enable the queue 0 cause, but
1884 * don't worry about dynamic_enable
1885 * because we left it on for the other
1886 * possible interrupts during napi
1887 */
1888 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
1889 qval |= I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1890 wr32(hw, I40E_QINT_RQCTL(0), qval);
1891
1892 qval = rd32(hw, I40E_QINT_TQCTL(0));
1893 qval |= I40E_QINT_TQCTL_CAUSE_ENA_MASK;
1894 wr32(hw, I40E_QINT_TQCTL(0), qval);
116a57d4
SN		 1895
1896 i40e_irq_dynamic_enable_icr0(vsi->back);
fd0a05ce
JB		 1897 }
1898 }
1899
1900 return 0;
1901}
1902
1903/**
1904 * i40e_atr - Add a Flow Director ATR filter
1905 * @tx_ring: ring to add programming descriptor to
1906 * @skb: send buffer
1907 * @flags: send flags
1908 * @protocol: wire protocol
1909 **/
1910static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
1911 u32 flags, __be16 protocol)
1912{
1913 struct i40e_filter_program_desc *fdir_desc;
1914 struct i40e_pf *pf = tx_ring->vsi->back;
1915 union {
1916 unsigned char *network;
1917 struct iphdr *ipv4;
1918 struct ipv6hdr *ipv6;
1919 } hdr;
1920 struct tcphdr *th;
1921 unsigned int hlen;
1922 u32 flex_ptype, dtype_cmd;
fc4ac67b 1923 u16 i;
fd0a05ce
JB		 1924
1925 /* make sure ATR is enabled */
60ea5f83 1926 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
fd0a05ce
JB		 1927 return;
1928
1929 /* if sampling is disabled do nothing */
1930 if (!tx_ring->atr_sample_rate)
1931 return;
1932
fd0a05ce
JB		 1933 /* snag network header to get L4 type and address */
1934 hdr.network = skb_network_header(skb);
1935
1936 /* Currently only IPv4/IPv6 with TCP is supported */
1937 if (protocol == htons(ETH_P_IP)) {
1938 if (hdr.ipv4->protocol != IPPROTO_TCP)
1939 return;
1940
1941 /* access ihl as a u8 to avoid unaligned access on ia64 */
1942 hlen = (hdr.network[0] & 0x0F) << 2;
1943 } else if (protocol == htons(ETH_P_IPV6)) {
1944 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1945 return;
1946
1947 hlen = sizeof(struct ipv6hdr);
1948 } else {
1949 return;
1950 }
1951
1952 th = (struct tcphdr *)(hdr.network + hlen);
1953
55a5e60b
ASJ		 1954 /* Due to lack of space, no more new filters can be programmed */
1955 if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1956 return;
1957
1958 tx_ring->atr_count++;
1959
ce806783
ASJ		 1960 /* sample on all syn/fin/rst packets or once every atr sample rate */
1961 if (!th->fin &&
1962 !th->syn &&
1963 !th->rst &&
1964 (tx_ring->atr_count < tx_ring->atr_sample_rate))
fd0a05ce
JB		 1965 return;
1966
1967 tx_ring->atr_count = 0;
1968
1969 /* grab the next descriptor */
fc4ac67b
AD		 1970 i = tx_ring->next_to_use;
1971 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
1972
1973 i++;
1974 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
fd0a05ce
JB		 1975
1976 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1977 I40E_TXD_FLTR_QW0_QINDEX_MASK;
1978 flex_ptype |= (protocol == htons(ETH_P_IP)) ?
1979 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
1980 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
1981 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
1982 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
1983
1984 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
1985
1986 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
1987
ce806783 1988 dtype_cmd |= (th->fin || th->rst) ?
fd0a05ce
JB		 1989 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1990 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
1991 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1992 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1993
1994 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
1995 I40E_TXD_FLTR_QW1_DEST_SHIFT;
1996
1997 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
1998 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
1999
433c47de
ASJ		 2000 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2001 dtype_cmd |=
2002 ((u32)pf->fd_atr_cnt_idx << I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2003 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2004
fd0a05ce 2005 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
99753ea6 2006 fdir_desc->rsvd = cpu_to_le32(0);
fd0a05ce 2007 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
99753ea6 2008 fdir_desc->fd_id = cpu_to_le32(0);
fd0a05ce
JB		 2009}
2010
fd0a05ce
JB		 2011/**
2012 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2013 * @skb: send buffer
2014 * @tx_ring: ring to send buffer on
2015 * @flags: the tx flags to be set
2016 *
2017 * Checks the skb and set up correspondingly several generic transmit flags
2018 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2019 *
2020 * Returns error code indicate the frame should be dropped upon error and the
2021 * otherwise returns 0 to indicate the flags has been set properly.
2022 **/
38e00438
VD		 2023#ifdef I40E_FCOE
2024int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2025 struct i40e_ring *tx_ring,
2026 u32 *flags)
2027#else
fd0a05ce
JB		 2028static int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2029 struct i40e_ring *tx_ring,
2030 u32 *flags)
38e00438 2031#endif
fd0a05ce
JB		 2032{
2033 __be16 protocol = skb->protocol;
2034 u32 tx_flags = 0;
2035
2036 /* if we have a HW VLAN tag being added, default to the HW one */
df8a39de
JP		 2037 if (skb_vlan_tag_present(skb)) {
2038 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
fd0a05ce
JB		 2039 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2040 /* else if it is a SW VLAN, check the next protocol and store the tag */
0e2fe46c 2041 } else if (protocol == htons(ETH_P_8021Q)) {
fd0a05ce
JB		 2042 struct vlan_hdr *vhdr, _vhdr;
2043 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2044 if (!vhdr)
2045 return -EINVAL;
2046
2047 protocol = vhdr->h_vlan_encapsulated_proto;
2048 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2049 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2050 }
2051
d40d00b1
NP		 2052 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2053 goto out;
2054
fd0a05ce 2055 /* Insert 802.1p priority into VLAN header */
38e00438
VD		 2056 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2057 (skb->priority != TC_PRIO_CONTROL)) {
fd0a05ce
JB		 2058 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2059 tx_flags |= (skb->priority & 0x7) <<
2060 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2061 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2062 struct vlan_ethhdr *vhdr;
dd225bc6
FR		 2063 int rc;
2064
2065 rc = skb_cow_head(skb, 0);
2066 if (rc < 0)
2067 return rc;
fd0a05ce
JB		 2068 vhdr = (struct vlan_ethhdr *)skb->data;
2069 vhdr->h_vlan_TCI = htons(tx_flags >>
2070 I40E_TX_FLAGS_VLAN_SHIFT);
2071 } else {
2072 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2073 }
2074 }
d40d00b1
NP		 2075
2076out:
fd0a05ce
JB		 2077 *flags = tx_flags;
2078 return 0;
2079}
2080
fd0a05ce
JB		 2081/**
2082 * i40e_tso - set up the tso context descriptor
2083 * @tx_ring: ptr to the ring to send
2084 * @skb: ptr to the skb we're sending
2085 * @tx_flags: the collected send information
2086 * @protocol: the send protocol
2087 * @hdr_len: ptr to the size of the packet header
2088 * @cd_tunneling: ptr to context descriptor bits
2089 *
2090 * Returns 0 if no TSO can happen, 1 if tso is going, or error
2091 **/
2092static int i40e_tso(struct i40e_ring *tx_ring, struct sk_buff *skb,
2093 u32 tx_flags, __be16 protocol, u8 *hdr_len,
2094 u64 *cd_type_cmd_tso_mss, u32 *cd_tunneling)
2095{
2096 u32 cd_cmd, cd_tso_len, cd_mss;
dd225bc6 2097 struct ipv6hdr *ipv6h;
fd0a05ce
JB		 2098 struct tcphdr *tcph;
2099 struct iphdr *iph;
2100 u32 l4len;
2101 int err;
fd0a05ce
JB		 2102
2103 if (!skb_is_gso(skb))
2104 return 0;
2105
dd225bc6
FR		 2106 err = skb_cow_head(skb, 0);
2107 if (err < 0)
2108 return err;
fd0a05ce 2109
df23075f
AS		 2110 iph = skb->encapsulation ? inner_ip_hdr(skb) : ip_hdr(skb);
2111 ipv6h = skb->encapsulation ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
2112
2113 if (iph->version == 4) {
fd0a05ce
JB		 2114 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2115 iph->tot_len = 0;
2116 iph->check = 0;
2117 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
2118 0, IPPROTO_TCP, 0);
df23075f 2119 } else if (ipv6h->version == 6) {
fd0a05ce
JB		 2120 tcph = skb->encapsulation ? inner_tcp_hdr(skb) : tcp_hdr(skb);
2121 ipv6h->payload_len = 0;
2122 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr, &ipv6h->daddr,
2123 0, IPPROTO_TCP, 0);
2124 }
2125
2126 l4len = skb->encapsulation ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
2127 *hdr_len = (skb->encapsulation
2128 ? (skb_inner_transport_header(skb) - skb->data)
2129 : skb_transport_offset(skb)) + l4len;
2130
2131 /* find the field values */
2132 cd_cmd = I40E_TX_CTX_DESC_TSO;
2133 cd_tso_len = skb->len - *hdr_len;
2134 cd_mss = skb_shinfo(skb)->gso_size;
829af3ac
MW		 2135 *cd_type_cmd_tso_mss |= ((u64)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2136 ((u64)cd_tso_len <<
2137 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2138 ((u64)cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
fd0a05ce
JB		 2139 return 1;
2140}
2141
beb0dff1
JK		 2142/**
2143 * i40e_tsyn - set up the tsyn context descriptor
2144 * @tx_ring: ptr to the ring to send
2145 * @skb: ptr to the skb we're sending
2146 * @tx_flags: the collected send information
2147 *
2148 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
2149 **/
2150static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
2151 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
2152{
2153 struct i40e_pf *pf;
2154
2155 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
2156 return 0;
2157
2158 /* Tx timestamps cannot be sampled when doing TSO */
2159 if (tx_flags & I40E_TX_FLAGS_TSO)
2160 return 0;
2161
2162 /* only timestamp the outbound packet if the user has requested it and
2163 * we are not already transmitting a packet to be timestamped
2164 */
2165 pf = i40e_netdev_to_pf(tx_ring->netdev);
22b4777d
JK		 2166 if (!(pf->flags & I40E_FLAG_PTP))
2167 return 0;
2168
9ce34f02
JK		 2169 if (pf->ptp_tx &&
2170 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) {
beb0dff1
JK		 2171 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2172 pf->ptp_tx_skb = skb_get(skb);
2173 } else {
2174 return 0;
2175 }
2176
2177 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
2178 I40E_TXD_CTX_QW1_CMD_SHIFT;
2179
beb0dff1
JK		 2180 return 1;
2181}
2182
fd0a05ce
JB		 2183/**
2184 * i40e_tx_enable_csum - Enable Tx checksum offloads
2185 * @skb: send buffer
2186 * @tx_flags: Tx flags currently set
2187 * @td_cmd: Tx descriptor command bits to set
2188 * @td_offset: Tx descriptor header offsets to set
2189 * @cd_tunneling: ptr to context desc bits
2190 **/
2191static void i40e_tx_enable_csum(struct sk_buff *skb, u32 tx_flags,
2192 u32 *td_cmd, u32 *td_offset,
2193 struct i40e_ring *tx_ring,
2194 u32 *cd_tunneling)
2195{
2196 struct ipv6hdr *this_ipv6_hdr;
2197 unsigned int this_tcp_hdrlen;
2198 struct iphdr *this_ip_hdr;
2199 u32 network_hdr_len;
2200 u8 l4_hdr = 0;
2201
2202 if (skb->encapsulation) {
2203 network_hdr_len = skb_inner_network_header_len(skb);
2204 this_ip_hdr = inner_ip_hdr(skb);
2205 this_ipv6_hdr = inner_ipv6_hdr(skb);
2206 this_tcp_hdrlen = inner_tcp_hdrlen(skb);
2207
2208 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2209
2210 if (tx_flags & I40E_TX_FLAGS_TSO) {
2211 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
2212 ip_hdr(skb)->check = 0;
2213 } else {
2214 *cd_tunneling |=
2215 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
2216 }
2217 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
df23075f
AS		 2218 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
2219 if (tx_flags & I40E_TX_FLAGS_TSO)
fd0a05ce 2220 ip_hdr(skb)->check = 0;
fd0a05ce
JB		 2221 }
2222
2223 /* Now set the ctx descriptor fields */
2224 *cd_tunneling |= (skb_network_header_len(skb) >> 2) <<
2225 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
2226 I40E_TXD_CTX_UDP_TUNNELING |
2227 ((skb_inner_network_offset(skb) -
2228 skb_transport_offset(skb)) >> 1) <<
2229 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
df23075f
AS		 2230 if (this_ip_hdr->version == 6) {
2231 tx_flags &= ~I40E_TX_FLAGS_IPV4;
2232 tx_flags |= I40E_TX_FLAGS_IPV6;
2233 }
fd0a05ce
JB		 2234 } else {
2235 network_hdr_len = skb_network_header_len(skb);
2236 this_ip_hdr = ip_hdr(skb);
2237 this_ipv6_hdr = ipv6_hdr(skb);
2238 this_tcp_hdrlen = tcp_hdrlen(skb);
2239 }
2240
2241 /* Enable IP checksum offloads */
2242 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2243 l4_hdr = this_ip_hdr->protocol;
2244 /* the stack computes the IP header already, the only time we
2245 * need the hardware to recompute it is in the case of TSO.
2246 */
2247 if (tx_flags & I40E_TX_FLAGS_TSO) {
2248 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
2249 this_ip_hdr->check = 0;
2250 } else {
2251 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
2252 }
2253 /* Now set the td_offset for IP header length */
2254 *td_offset = (network_hdr_len >> 2) <<
2255 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2256 } else if (tx_flags & I40E_TX_FLAGS_IPV6) {
2257 l4_hdr = this_ipv6_hdr->nexthdr;
2258 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
2259 /* Now set the td_offset for IP header length */
2260 *td_offset = (network_hdr_len >> 2) <<
2261 I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2262 }
2263 /* words in MACLEN + dwords in IPLEN + dwords in L4Len */
2264 *td_offset |= (skb_network_offset(skb) >> 1) <<
2265 I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
2266
2267 /* Enable L4 checksum offloads */
2268 switch (l4_hdr) {
2269 case IPPROTO_TCP:
2270 /* enable checksum offloads */
2271 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
2272 *td_offset |= (this_tcp_hdrlen >> 2) <<
2273 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2274 break;
2275 case IPPROTO_SCTP:
2276 /* enable SCTP checksum offload */
2277 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
2278 *td_offset |= (sizeof(struct sctphdr) >> 2) <<
2279 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2280 break;
2281 case IPPROTO_UDP:
2282 /* enable UDP checksum offload */
2283 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
2284 *td_offset |= (sizeof(struct udphdr) >> 2) <<
2285 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2286 break;
2287 default:
2288 break;
2289 }
2290}
2291
2292/**
2293 * i40e_create_tx_ctx Build the Tx context descriptor
2294 * @tx_ring: ring to create the descriptor on
2295 * @cd_type_cmd_tso_mss: Quad Word 1
2296 * @cd_tunneling: Quad Word 0 - bits 0-31
2297 * @cd_l2tag2: Quad Word 0 - bits 32-63
2298 **/
2299static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
2300 const u64 cd_type_cmd_tso_mss,
2301 const u32 cd_tunneling, const u32 cd_l2tag2)
2302{
2303 struct i40e_tx_context_desc *context_desc;
fc4ac67b 2304 int i = tx_ring->next_to_use;
fd0a05ce 2305
ff40dd5d
JB		 2306 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
2307 !cd_tunneling && !cd_l2tag2)
fd0a05ce
JB		 2308 return;
2309
2310 /* grab the next descriptor */
fc4ac67b
AD		 2311 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
2312
2313 i++;
2314 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
fd0a05ce
JB		 2315
2316 /* cpu_to_le32 and assign to struct fields */
2317 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2318 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3efbbb20 2319 context_desc->rsvd = cpu_to_le16(0);
fd0a05ce
JB		 2320 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2321}
2322
4567dc10
ED		 2323/**
2324 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
2325 * @tx_ring: the ring to be checked
2326 * @size: the size buffer we want to assure is available
2327 *
2328 * Returns -EBUSY if a stop is needed, else 0
2329 **/
2330static inline int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2331{
2332 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2333 /* Memory barrier before checking head and tail */
2334 smp_mb();
2335
2336 /* Check again in a case another CPU has just made room available. */
2337 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
2338 return -EBUSY;
2339
2340 /* A reprieve! - use start_queue because it doesn't call schedule */
2341 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2342 ++tx_ring->tx_stats.restart_queue;
2343 return 0;
2344}
2345
2346/**
2347 * i40e_maybe_stop_tx - 1st level check for tx stop conditions
2348 * @tx_ring: the ring to be checked
2349 * @size: the size buffer we want to assure is available
2350 *
2351 * Returns 0 if stop is not needed
2352 **/
2353#ifdef I40E_FCOE
2354int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2355#else
2356static int i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2357#endif
2358{
2359 if (likely(I40E_DESC_UNUSED(tx_ring) >= size))
2360 return 0;
2361 return __i40e_maybe_stop_tx(tx_ring, size);
2362}
2363
71da6197
AS		 2364/**
2365 * i40e_chk_linearize - Check if there are more than 8 fragments per packet
2366 * @skb: send buffer
2367 * @tx_flags: collected send information
2368 * @hdr_len: size of the packet header
2369 *
2370 * Note: Our HW can't scatter-gather more than 8 fragments to build
2371 * a packet on the wire and so we need to figure out the cases where we
2372 * need to linearize the skb.
2373 **/
2374static bool i40e_chk_linearize(struct sk_buff *skb, u32 tx_flags,
2375 const u8 hdr_len)
2376{
2377 struct skb_frag_struct *frag;
2378 bool linearize = false;
2379 unsigned int size = 0;
2380 u16 num_frags;
2381 u16 gso_segs;
2382
2383 num_frags = skb_shinfo(skb)->nr_frags;
2384 gso_segs = skb_shinfo(skb)->gso_segs;
2385
2386 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO)) {
2387 u16 j = 1;
2388
2389 if (num_frags < (I40E_MAX_BUFFER_TXD))
2390 goto linearize_chk_done;
2391 /* try the simple math, if we have too many frags per segment */
2392 if (DIV_ROUND_UP((num_frags + gso_segs), gso_segs) >
2393 I40E_MAX_BUFFER_TXD) {
2394 linearize = true;
2395 goto linearize_chk_done;
2396 }
2397 frag = &skb_shinfo(skb)->frags[0];
2398 size = hdr_len;
2399 /* we might still have more fragments per segment */
2400 do {
2401 size += skb_frag_size(frag);
2402 frag++; j++;
2403 if (j == I40E_MAX_BUFFER_TXD) {
2404 if (size < skb_shinfo(skb)->gso_size) {
2405 linearize = true;
2406 break;
2407 }
2408 j = 1;
2409 size -= skb_shinfo(skb)->gso_size;
2410 if (size)
2411 j++;
2412 size += hdr_len;
2413 }
2414 num_frags--;
2415 } while (num_frags);
2416 } else {
2417 if (num_frags >= I40E_MAX_BUFFER_TXD)
2418 linearize = true;
2419 }
2420
2421linearize_chk_done:
2422 return linearize;
2423}
2424
fd0a05ce
JB		 2425/**
2426 * i40e_tx_map - Build the Tx descriptor
2427 * @tx_ring: ring to send buffer on
2428 * @skb: send buffer
2429 * @first: first buffer info buffer to use
2430 * @tx_flags: collected send information
2431 * @hdr_len: size of the packet header
2432 * @td_cmd: the command field in the descriptor
2433 * @td_offset: offset for checksum or crc
2434 **/
38e00438
VD		 2435#ifdef I40E_FCOE
2436void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2437 struct i40e_tx_buffer *first, u32 tx_flags,
2438 const u8 hdr_len, u32 td_cmd, u32 td_offset)
2439#else
fd0a05ce
JB		 2440static void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2441 struct i40e_tx_buffer *first, u32 tx_flags,
2442 const u8 hdr_len, u32 td_cmd, u32 td_offset)
38e00438 2443#endif
fd0a05ce 2444{
fd0a05ce
JB		 2445 unsigned int data_len = skb->data_len;
2446 unsigned int size = skb_headlen(skb);
a5e9c572 2447 struct skb_frag_struct *frag;
fd0a05ce
JB		 2448 struct i40e_tx_buffer *tx_bi;
2449 struct i40e_tx_desc *tx_desc;
a5e9c572 2450 u16 i = tx_ring->next_to_use;
fd0a05ce
JB		 2451 u32 td_tag = 0;
2452 dma_addr_t dma;
2453 u16 gso_segs;
2454
fd0a05ce
JB		 2455 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
2456 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
2457 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
2458 I40E_TX_FLAGS_VLAN_SHIFT;
2459 }
2460
a5e9c572
AD		 2461 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
2462 gso_segs = skb_shinfo(skb)->gso_segs;
2463 else
2464 gso_segs = 1;
2465
2466 /* multiply data chunks by size of headers */
2467 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
2468 first->gso_segs = gso_segs;
2469 first->skb = skb;
2470 first->tx_flags = tx_flags;
2471
2472 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2473
fd0a05ce 2474 tx_desc = I40E_TX_DESC(tx_ring, i);
a5e9c572
AD		 2475 tx_bi = first;
2476
2477 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2478 if (dma_mapping_error(tx_ring->dev, dma))
2479 goto dma_error;
2480
2481 /* record length, and DMA address */
2482 dma_unmap_len_set(tx_bi, len, size);
2483 dma_unmap_addr_set(tx_bi, dma, dma);
2484
2485 tx_desc->buffer_addr = cpu_to_le64(dma);
2486
2487 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
fd0a05ce
JB		 2488 tx_desc->cmd_type_offset_bsz =
2489 build_ctob(td_cmd, td_offset,
2490 I40E_MAX_DATA_PER_TXD, td_tag);
2491
fd0a05ce
JB		 2492 tx_desc++;
2493 i++;
2494 if (i == tx_ring->count) {
2495 tx_desc = I40E_TX_DESC(tx_ring, 0);
2496 i = 0;
2497 }
fd0a05ce 2498
a5e9c572
AD		 2499 dma += I40E_MAX_DATA_PER_TXD;
2500 size -= I40E_MAX_DATA_PER_TXD;
fd0a05ce 2501
a5e9c572
AD		 2502 tx_desc->buffer_addr = cpu_to_le64(dma);
2503 }
fd0a05ce
JB		 2504
2505 if (likely(!data_len))
2506 break;
2507
a5e9c572
AD		 2508 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2509 size, td_tag);
fd0a05ce
JB		 2510
2511 tx_desc++;
2512 i++;
2513 if (i == tx_ring->count) {
2514 tx_desc = I40E_TX_DESC(tx_ring, 0);
2515 i = 0;
2516 }
2517
a5e9c572
AD		 2518 size = skb_frag_size(frag);
2519 data_len -= size;
fd0a05ce 2520
a5e9c572
AD		 2521 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2522 DMA_TO_DEVICE);
fd0a05ce 2523
a5e9c572
AD		 2524 tx_bi = &tx_ring->tx_bi[i];
2525 }
fd0a05ce 2526
1943d8ba
JB		 2527 /* Place RS bit on last descriptor of any packet that spans across the
2528 * 4th descriptor (WB_STRIDE aka 0x3) in a 64B cacheline.
2529 */
1943d8ba
JB		 2530 if (((i & WB_STRIDE) != WB_STRIDE) &&
2531 (first <= &tx_ring->tx_bi[i]) &&
2532 (first >= &tx_ring->tx_bi[i & ~WB_STRIDE])) {
2533 tx_desc->cmd_type_offset_bsz =
2534 build_ctob(td_cmd, td_offset, size, td_tag) |
2535 cpu_to_le64((u64)I40E_TX_DESC_CMD_EOP <<
2536 I40E_TXD_QW1_CMD_SHIFT);
2537 } else {
2538 tx_desc->cmd_type_offset_bsz =
2539 build_ctob(td_cmd, td_offset, size, td_tag) |
2540 cpu_to_le64((u64)I40E_TXD_CMD <<
2541 I40E_TXD_QW1_CMD_SHIFT);
2542 }
fd0a05ce 2543
7070ce0a
AD		 2544 netdev_tx_sent_queue(netdev_get_tx_queue(tx_ring->netdev,
2545 tx_ring->queue_index),
2546 first->bytecount);
2547
a5e9c572 2548 /* set the timestamp */
fd0a05ce 2549 first->time_stamp = jiffies;
fd0a05ce
JB		 2550
2551 /* Force memory writes to complete before letting h/w
2552 * know there are new descriptors to fetch. (Only
2553 * applicable for weak-ordered memory model archs,
2554 * such as IA-64).
2555 */
2556 wmb();
2557
a5e9c572
AD		 2558 /* set next_to_watch value indicating a packet is present */
2559 first->next_to_watch = tx_desc;
2560
2561 i++;
2562 if (i == tx_ring->count)
2563 i = 0;
2564
2565 tx_ring->next_to_use = i;
2566
4567dc10 2567 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
a5e9c572 2568 /* notify HW of packet */
4567dc10
ED		 2569 if (!skb->xmit_more ||
2570 netif_xmit_stopped(netdev_get_tx_queue(tx_ring->netdev,
2571 tx_ring->queue_index)))
2572 writel(i, tx_ring->tail);
a5e9c572 2573
fd0a05ce
JB		 2574 return;
2575
2576dma_error:
a5e9c572 2577 dev_info(tx_ring->dev, "TX DMA map failed\n");
fd0a05ce
JB		 2578
2579 /* clear dma mappings for failed tx_bi map */
2580 for (;;) {
2581 tx_bi = &tx_ring->tx_bi[i];
a5e9c572 2582 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
fd0a05ce
JB		 2583 if (tx_bi == first)
2584 break;
2585 if (i == 0)
2586 i = tx_ring->count;
2587 i--;
2588 }
2589
fd0a05ce
JB		 2590 tx_ring->next_to_use = i;
2591}
2592
fd0a05ce
JB		 2593/**
2594 * i40e_xmit_descriptor_count - calculate number of tx descriptors needed
2595 * @skb: send buffer
2596 * @tx_ring: ring to send buffer on
2597 *
2598 * Returns number of data descriptors needed for this skb. Returns 0 to indicate
2599 * there is not enough descriptors available in this ring since we need at least
2600 * one descriptor.
2601 **/
38e00438
VD		 2602#ifdef I40E_FCOE
2603int i40e_xmit_descriptor_count(struct sk_buff *skb,
2604 struct i40e_ring *tx_ring)
2605#else
fd0a05ce
JB		 2606static int i40e_xmit_descriptor_count(struct sk_buff *skb,
2607 struct i40e_ring *tx_ring)
38e00438 2608#endif
fd0a05ce 2609{
fd0a05ce 2610 unsigned int f;
fd0a05ce
JB		 2611 int count = 0;
2612
2613 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2614 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
be560521 2615 * + 4 desc gap to avoid the cache line where head is,
fd0a05ce
JB		 2616 * + 1 desc for context descriptor,
2617 * otherwise try next time
2618 */
fd0a05ce
JB		 2619 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
2620 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
980093eb 2621
fd0a05ce 2622 count += TXD_USE_COUNT(skb_headlen(skb));
be560521 2623 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
fd0a05ce
JB		 2624 tx_ring->tx_stats.tx_busy++;
2625 return 0;
2626 }
2627 return count;
2628}
2629
2630/**
2631 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2632 * @skb: send buffer
2633 * @tx_ring: ring to send buffer on
2634 *
2635 * Returns NETDEV_TX_OK if sent, else an error code
2636 **/
2637static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2638 struct i40e_ring *tx_ring)
2639{
2640 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2641 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2642 struct i40e_tx_buffer *first;
2643 u32 td_offset = 0;
2644 u32 tx_flags = 0;
2645 __be16 protocol;
2646 u32 td_cmd = 0;
2647 u8 hdr_len = 0;
beb0dff1 2648 int tsyn;
fd0a05ce
JB		 2649 int tso;
2650 if (0 == i40e_xmit_descriptor_count(skb, tx_ring))
2651 return NETDEV_TX_BUSY;
2652
2653 /* prepare the xmit flags */
2654 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2655 goto out_drop;
2656
2657 /* obtain protocol of skb */
3d34dd03 2658 protocol = vlan_get_protocol(skb);
fd0a05ce
JB		 2659
2660 /* record the location of the first descriptor for this packet */
2661 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2662
2663 /* setup IPv4/IPv6 offloads */
0e2fe46c 2664 if (protocol == htons(ETH_P_IP))
fd0a05ce 2665 tx_flags |= I40E_TX_FLAGS_IPV4;
0e2fe46c 2666 else if (protocol == htons(ETH_P_IPV6))
fd0a05ce
JB		 2667 tx_flags |= I40E_TX_FLAGS_IPV6;
2668
2669 tso = i40e_tso(tx_ring, skb, tx_flags, protocol, &hdr_len,
2670 &cd_type_cmd_tso_mss, &cd_tunneling);
2671
2672 if (tso < 0)
2673 goto out_drop;
2674 else if (tso)
2675 tx_flags |= I40E_TX_FLAGS_TSO;
2676
beb0dff1
JK		 2677 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
2678
2679 if (tsyn)
2680 tx_flags |= I40E_TX_FLAGS_TSYN;
2681
71da6197
AS		 2682 if (i40e_chk_linearize(skb, tx_flags, hdr_len))
2683 if (skb_linearize(skb))
2684 goto out_drop;
2685
259afec7
JK		 2686 skb_tx_timestamp(skb);
2687
b1941306
AD		 2688 /* always enable CRC insertion offload */
2689 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2690
fd0a05ce 2691 /* Always offload the checksum, since it's in the data descriptor */
b1941306 2692 if (skb->ip_summed == CHECKSUM_PARTIAL) {
fd0a05ce
JB		 2693 tx_flags |= I40E_TX_FLAGS_CSUM;
2694
fd0a05ce
JB		 2695 i40e_tx_enable_csum(skb, tx_flags, &td_cmd, &td_offset,
2696 tx_ring, &cd_tunneling);
b1941306 2697 }
fd0a05ce
JB		 2698
2699 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2700 cd_tunneling, cd_l2tag2);
2701
2702 /* Add Flow Director ATR if it's enabled.
2703 *
2704 * NOTE: this must always be directly before the data descriptor.
2705 */
2706 i40e_atr(tx_ring, skb, tx_flags, protocol);
2707
2708 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2709 td_cmd, td_offset);
2710
fd0a05ce
JB		 2711 return NETDEV_TX_OK;
2712
2713out_drop:
2714 dev_kfree_skb_any(skb);
2715 return NETDEV_TX_OK;
2716}
2717
2718/**
2719 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2720 * @skb: send buffer
2721 * @netdev: network interface device structure
2722 *
2723 * Returns NETDEV_TX_OK if sent, else an error code
2724 **/
2725netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2726{
2727 struct i40e_netdev_priv *np = netdev_priv(netdev);
2728 struct i40e_vsi *vsi = np->vsi;
9f65e15b 2729 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
fd0a05ce
JB		 2730
2731 /* hardware can't handle really short frames, hardware padding works
2732 * beyond this point
2733 */
a94d9e22
AD		 2734 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
2735 return NETDEV_TX_OK;
fd0a05ce
JB		 2736
2737 return i40e_xmit_frame_ring(skb, tx_ring);
2738}
Linux 6.x block layer and io_uring tree(s)