Commit | Line | Data |
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ae06c70b | 1 | // SPDX-License-Identifier: GPL-2.0 |
4b208eaa | 2 | /* Copyright(c) 2013 - 2021 Intel Corporation. */ |
41c445ff | 3 | |
b499ffb0 SV |
4 | #include <linux/etherdevice.h> |
5 | #include <linux/of_net.h> | |
6 | #include <linux/pci.h> | |
0c8493d9 | 7 | #include <linux/bpf.h> |
34a2a3b8 | 8 | #include <generated/utsrelease.h> |
065aa694 | 9 | #include <linux/crash_dump.h> |
b499ffb0 | 10 | |
41c445ff JB |
11 | /* Local includes */ |
12 | #include "i40e.h" | |
4eb3f768 | 13 | #include "i40e_diag.h" |
0a714186 | 14 | #include "i40e_xsk.h" |
06a5f7f1 | 15 | #include <net/udp_tunnel.h> |
a71506a4 | 16 | #include <net/xdp_sock_drv.h> |
ed0980c4 SP |
17 | /* All i40e tracepoints are defined by the include below, which |
18 | * must be included exactly once across the whole kernel with | |
19 | * CREATE_TRACE_POINTS defined | |
20 | */ | |
21 | #define CREATE_TRACE_POINTS | |
22 | #include "i40e_trace.h" | |
41c445ff JB |
23 | |
24 | const char i40e_driver_name[] = "i40e"; | |
25 | static const char i40e_driver_string[] = | |
26 | "Intel(R) Ethernet Connection XL710 Network Driver"; | |
27 | ||
559ac25c | 28 | static const char i40e_copyright[] = "Copyright (c) 2013 - 2019 Intel Corporation."; |
41c445ff JB |
29 | |
30 | /* a bit of forward declarations */ | |
31 | static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi); | |
373149fc | 32 | static void i40e_handle_reset_warning(struct i40e_pf *pf, bool lock_acquired); |
41c445ff JB |
33 | static int i40e_add_vsi(struct i40e_vsi *vsi); |
34 | static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi); | |
956e759d | 35 | static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit, bool lock_acquired); |
41c445ff JB |
36 | static int i40e_setup_misc_vector(struct i40e_pf *pf); |
37 | static void i40e_determine_queue_usage(struct i40e_pf *pf); | |
38 | static int i40e_setup_pf_filter_control(struct i40e_pf *pf); | |
4b208eaa | 39 | static void i40e_prep_for_reset(struct i40e_pf *pf); |
3ac874fa SD |
40 | static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit, |
41 | bool lock_acquired); | |
373149fc MS |
42 | static int i40e_reset(struct i40e_pf *pf); |
43 | static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired); | |
4ff0ee1a AM |
44 | static int i40e_setup_misc_vector_for_recovery_mode(struct i40e_pf *pf); |
45 | static int i40e_restore_interrupt_scheme(struct i40e_pf *pf); | |
46 | static bool i40e_check_recovery_mode(struct i40e_pf *pf); | |
47 | static int i40e_init_recovery_mode(struct i40e_pf *pf, struct i40e_hw *hw); | |
cbf61325 | 48 | static void i40e_fdir_sb_setup(struct i40e_pf *pf); |
4e3b35b0 | 49 | static int i40e_veb_get_bw_info(struct i40e_veb *veb); |
2f4b411a AN |
50 | static int i40e_get_capabilities(struct i40e_pf *pf, |
51 | enum i40e_admin_queue_opc list_type); | |
d5ec9e2c | 52 | static bool i40e_is_total_port_shutdown_enabled(struct i40e_pf *pf); |
41c445ff JB |
53 | |
54 | /* i40e_pci_tbl - PCI Device ID Table | |
55 | * | |
56 | * Last entry must be all 0s | |
57 | * | |
58 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
59 | * Class, Class Mask, private data (not used) } | |
60 | */ | |
9baa3c34 | 61 | static const struct pci_device_id i40e_pci_tbl[] = { |
ab60085e | 62 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0}, |
ab60085e | 63 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0}, |
ab60085e SN |
64 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0}, |
65 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0}, | |
ab60085e SN |
66 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0}, |
67 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0}, | |
68 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0}, | |
5960d33f | 69 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0}, |
bc5166b9 | 70 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0}, |
f78787f3 | 71 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_BC), 0}, |
2e45d3f4 AL |
72 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_SFP), 0}, |
73 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_B), 0}, | |
35dae51d ASJ |
74 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0}, |
75 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0}, | |
87e6c1d7 ASJ |
76 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0}, |
77 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0}, | |
78 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0}, | |
d6bf58c2 | 79 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0}, |
48a3b512 SN |
80 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0}, |
81 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0}, | |
e576e769 AL |
82 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_X710_N3000), 0}, |
83 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_XXV710_N3000), 0}, | |
3123237a CW |
84 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_B), 0}, |
85 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_SFP28), 0}, | |
41c445ff JB |
86 | /* required last entry */ |
87 | {0, } | |
88 | }; | |
89 | MODULE_DEVICE_TABLE(pci, i40e_pci_tbl); | |
90 | ||
91 | #define I40E_MAX_VF_COUNT 128 | |
92 | static int debug = -1; | |
5d4ca23e AD |
93 | module_param(debug, uint, 0); |
94 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all), Debug mask (0x8XXXXXXX)"); | |
41c445ff JB |
95 | |
96 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
97 | MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver"); | |
98674ebe | 98 | MODULE_LICENSE("GPL v2"); |
41c445ff | 99 | |
2803b16c JB |
100 | static struct workqueue_struct *i40e_wq; |
101 | ||
3116f59c DZ |
102 | static void netdev_hw_addr_refcnt(struct i40e_mac_filter *f, |
103 | struct net_device *netdev, int delta) | |
104 | { | |
105 | struct netdev_hw_addr *ha; | |
106 | ||
107 | if (!f || !netdev) | |
108 | return; | |
109 | ||
110 | netdev_for_each_mc_addr(ha, netdev) { | |
111 | if (ether_addr_equal(ha->addr, f->macaddr)) { | |
112 | ha->refcount += delta; | |
113 | if (ha->refcount <= 0) | |
114 | ha->refcount = 1; | |
115 | break; | |
116 | } | |
117 | } | |
118 | } | |
119 | ||
41c445ff JB |
120 | /** |
121 | * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code | |
122 | * @hw: pointer to the HW structure | |
123 | * @mem: ptr to mem struct to fill out | |
124 | * @size: size of memory requested | |
125 | * @alignment: what to align the allocation to | |
126 | **/ | |
127 | int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem, | |
128 | u64 size, u32 alignment) | |
129 | { | |
130 | struct i40e_pf *pf = (struct i40e_pf *)hw->back; | |
131 | ||
132 | mem->size = ALIGN(size, alignment); | |
750afb08 LC |
133 | mem->va = dma_alloc_coherent(&pf->pdev->dev, mem->size, &mem->pa, |
134 | GFP_KERNEL); | |
93bc73b8 JB |
135 | if (!mem->va) |
136 | return -ENOMEM; | |
41c445ff | 137 | |
93bc73b8 | 138 | return 0; |
41c445ff JB |
139 | } |
140 | ||
141 | /** | |
142 | * i40e_free_dma_mem_d - OS specific memory free for shared code | |
143 | * @hw: pointer to the HW structure | |
144 | * @mem: ptr to mem struct to free | |
145 | **/ | |
146 | int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem) | |
147 | { | |
148 | struct i40e_pf *pf = (struct i40e_pf *)hw->back; | |
149 | ||
150 | dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa); | |
151 | mem->va = NULL; | |
152 | mem->pa = 0; | |
153 | mem->size = 0; | |
154 | ||
155 | return 0; | |
156 | } | |
157 | ||
158 | /** | |
159 | * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code | |
160 | * @hw: pointer to the HW structure | |
161 | * @mem: ptr to mem struct to fill out | |
162 | * @size: size of memory requested | |
163 | **/ | |
164 | int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem, | |
165 | u32 size) | |
166 | { | |
167 | mem->size = size; | |
168 | mem->va = kzalloc(size, GFP_KERNEL); | |
169 | ||
93bc73b8 JB |
170 | if (!mem->va) |
171 | return -ENOMEM; | |
41c445ff | 172 | |
93bc73b8 | 173 | return 0; |
41c445ff JB |
174 | } |
175 | ||
176 | /** | |
177 | * i40e_free_virt_mem_d - OS specific memory free for shared code | |
178 | * @hw: pointer to the HW structure | |
179 | * @mem: ptr to mem struct to free | |
180 | **/ | |
181 | int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem) | |
182 | { | |
183 | /* it's ok to kfree a NULL pointer */ | |
184 | kfree(mem->va); | |
185 | mem->va = NULL; | |
186 | mem->size = 0; | |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
191 | /** | |
192 | * i40e_get_lump - find a lump of free generic resource | |
193 | * @pf: board private structure | |
194 | * @pile: the pile of resource to search | |
195 | * @needed: the number of items needed | |
196 | * @id: an owner id to stick on the items assigned | |
197 | * | |
198 | * Returns the base item index of the lump, or negative for error | |
199 | * | |
200 | * The search_hint trick and lack of advanced fit-finding only work | |
201 | * because we're highly likely to have all the same size lump requests. | |
202 | * Linear search time and any fragmentation should be minimal. | |
203 | **/ | |
204 | static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile, | |
205 | u16 needed, u16 id) | |
206 | { | |
207 | int ret = -ENOMEM; | |
ddf434ac | 208 | int i, j; |
41c445ff JB |
209 | |
210 | if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) { | |
211 | dev_info(&pf->pdev->dev, | |
7be78aa4 MW |
212 | "param err: pile=%s needed=%d id=0x%04x\n", |
213 | pile ? "<valid>" : "<null>", needed, id); | |
41c445ff JB |
214 | return -EINVAL; |
215 | } | |
216 | ||
217 | /* start the linear search with an imperfect hint */ | |
218 | i = pile->search_hint; | |
ddf434ac | 219 | while (i < pile->num_entries) { |
41c445ff JB |
220 | /* skip already allocated entries */ |
221 | if (pile->list[i] & I40E_PILE_VALID_BIT) { | |
222 | i++; | |
223 | continue; | |
224 | } | |
225 | ||
226 | /* do we have enough in this lump? */ | |
227 | for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) { | |
228 | if (pile->list[i+j] & I40E_PILE_VALID_BIT) | |
229 | break; | |
230 | } | |
231 | ||
232 | if (j == needed) { | |
233 | /* there was enough, so assign it to the requestor */ | |
234 | for (j = 0; j < needed; j++) | |
235 | pile->list[i+j] = id | I40E_PILE_VALID_BIT; | |
236 | ret = i; | |
237 | pile->search_hint = i + j; | |
ddf434ac | 238 | break; |
41c445ff | 239 | } |
6995b36c JB |
240 | |
241 | /* not enough, so skip over it and continue looking */ | |
242 | i += j; | |
41c445ff JB |
243 | } |
244 | ||
245 | return ret; | |
246 | } | |
247 | ||
248 | /** | |
249 | * i40e_put_lump - return a lump of generic resource | |
250 | * @pile: the pile of resource to search | |
251 | * @index: the base item index | |
252 | * @id: the owner id of the items assigned | |
253 | * | |
254 | * Returns the count of items in the lump | |
255 | **/ | |
256 | static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id) | |
257 | { | |
258 | int valid_id = (id | I40E_PILE_VALID_BIT); | |
259 | int count = 0; | |
260 | int i; | |
261 | ||
262 | if (!pile || index >= pile->num_entries) | |
263 | return -EINVAL; | |
264 | ||
265 | for (i = index; | |
266 | i < pile->num_entries && pile->list[i] == valid_id; | |
267 | i++) { | |
268 | pile->list[i] = 0; | |
269 | count++; | |
270 | } | |
271 | ||
272 | if (count && index < pile->search_hint) | |
273 | pile->search_hint = index; | |
274 | ||
275 | return count; | |
276 | } | |
277 | ||
fdf0e0bf ASJ |
278 | /** |
279 | * i40e_find_vsi_from_id - searches for the vsi with the given id | |
f5254429 JK |
280 | * @pf: the pf structure to search for the vsi |
281 | * @id: id of the vsi it is searching for | |
fdf0e0bf ASJ |
282 | **/ |
283 | struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id) | |
284 | { | |
285 | int i; | |
286 | ||
287 | for (i = 0; i < pf->num_alloc_vsi; i++) | |
288 | if (pf->vsi[i] && (pf->vsi[i]->id == id)) | |
289 | return pf->vsi[i]; | |
290 | ||
291 | return NULL; | |
292 | } | |
293 | ||
41c445ff JB |
294 | /** |
295 | * i40e_service_event_schedule - Schedule the service task to wake up | |
296 | * @pf: board private structure | |
297 | * | |
298 | * If not already scheduled, this puts the task into the work queue | |
299 | **/ | |
e3219ce6 | 300 | void i40e_service_event_schedule(struct i40e_pf *pf) |
41c445ff | 301 | { |
4ff0ee1a AM |
302 | if ((!test_bit(__I40E_DOWN, pf->state) && |
303 | !test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) || | |
304 | test_bit(__I40E_RECOVERY_MODE, pf->state)) | |
2803b16c | 305 | queue_work(i40e_wq, &pf->service_task); |
41c445ff JB |
306 | } |
307 | ||
308 | /** | |
309 | * i40e_tx_timeout - Respond to a Tx Hang | |
310 | * @netdev: network interface device structure | |
b50f7bca | 311 | * @txqueue: queue number timing out |
41c445ff JB |
312 | * |
313 | * If any port has noticed a Tx timeout, it is likely that the whole | |
314 | * device is munged, not just the one netdev port, so go for the full | |
315 | * reset. | |
316 | **/ | |
0290bd29 | 317 | static void i40e_tx_timeout(struct net_device *netdev, unsigned int txqueue) |
41c445ff JB |
318 | { |
319 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
320 | struct i40e_vsi *vsi = np->vsi; | |
321 | struct i40e_pf *pf = vsi->back; | |
b03a8c1f | 322 | struct i40e_ring *tx_ring = NULL; |
65279bee | 323 | unsigned int i; |
b03a8c1f | 324 | u32 head, val; |
41c445ff JB |
325 | |
326 | pf->tx_timeout_count++; | |
327 | ||
65279bee JF |
328 | /* with txqueue index, find the tx_ring struct */ |
329 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
330 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) { | |
331 | if (txqueue == | |
332 | vsi->tx_rings[i]->queue_index) { | |
333 | tx_ring = vsi->tx_rings[i]; | |
334 | break; | |
b03a8c1f KP |
335 | } |
336 | } | |
337 | } | |
338 | ||
41c445ff | 339 | if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20))) |
b03a8c1f KP |
340 | pf->tx_timeout_recovery_level = 1; /* reset after some time */ |
341 | else if (time_before(jiffies, | |
342 | (pf->tx_timeout_last_recovery + netdev->watchdog_timeo))) | |
343 | return; /* don't do any new action before the next timeout */ | |
344 | ||
d5585b7b AB |
345 | /* don't kick off another recovery if one is already pending */ |
346 | if (test_and_set_bit(__I40E_TIMEOUT_RECOVERY_PENDING, pf->state)) | |
347 | return; | |
348 | ||
b03a8c1f KP |
349 | if (tx_ring) { |
350 | head = i40e_get_head(tx_ring); | |
351 | /* Read interrupt register */ | |
352 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
353 | val = rd32(&pf->hw, | |
354 | I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx + | |
355 | tx_ring->vsi->base_vector - 1)); | |
356 | else | |
357 | val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); | |
358 | ||
359 | netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n", | |
65279bee | 360 | vsi->seid, txqueue, tx_ring->next_to_clean, |
b03a8c1f KP |
361 | head, tx_ring->next_to_use, |
362 | readl(tx_ring->tail), val); | |
363 | } | |
364 | ||
41c445ff | 365 | pf->tx_timeout_last_recovery = jiffies; |
65279bee JF |
366 | netdev_info(netdev, "tx_timeout recovery level %d, txqueue %d\n", |
367 | pf->tx_timeout_recovery_level, txqueue); | |
41c445ff JB |
368 | |
369 | switch (pf->tx_timeout_recovery_level) { | |
41c445ff | 370 | case 1: |
0da36b97 | 371 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
41c445ff JB |
372 | break; |
373 | case 2: | |
0da36b97 | 374 | set_bit(__I40E_CORE_RESET_REQUESTED, pf->state); |
41c445ff JB |
375 | break; |
376 | case 3: | |
0da36b97 | 377 | set_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state); |
41c445ff JB |
378 | break; |
379 | default: | |
380 | netdev_err(netdev, "tx_timeout recovery unsuccessful\n"); | |
41c445ff JB |
381 | break; |
382 | } | |
b03a8c1f | 383 | |
41c445ff JB |
384 | i40e_service_event_schedule(pf); |
385 | pf->tx_timeout_recovery_level++; | |
386 | } | |
387 | ||
41c445ff JB |
388 | /** |
389 | * i40e_get_vsi_stats_struct - Get System Network Statistics | |
390 | * @vsi: the VSI we care about | |
391 | * | |
392 | * Returns the address of the device statistics structure. | |
393 | * The statistics are actually updated from the service task. | |
394 | **/ | |
395 | struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi) | |
396 | { | |
397 | return &vsi->net_stats; | |
398 | } | |
399 | ||
74608d17 BT |
400 | /** |
401 | * i40e_get_netdev_stats_struct_tx - populate stats from a Tx ring | |
402 | * @ring: Tx ring to get statistics from | |
403 | * @stats: statistics entry to be updated | |
404 | **/ | |
405 | static void i40e_get_netdev_stats_struct_tx(struct i40e_ring *ring, | |
406 | struct rtnl_link_stats64 *stats) | |
407 | { | |
408 | u64 bytes, packets; | |
409 | unsigned int start; | |
410 | ||
411 | do { | |
412 | start = u64_stats_fetch_begin_irq(&ring->syncp); | |
413 | packets = ring->stats.packets; | |
414 | bytes = ring->stats.bytes; | |
415 | } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); | |
416 | ||
417 | stats->tx_packets += packets; | |
418 | stats->tx_bytes += bytes; | |
419 | } | |
420 | ||
41c445ff JB |
421 | /** |
422 | * i40e_get_netdev_stats_struct - Get statistics for netdev interface | |
423 | * @netdev: network interface device structure | |
f5254429 | 424 | * @stats: data structure to store statistics |
41c445ff JB |
425 | * |
426 | * Returns the address of the device statistics structure. | |
427 | * The statistics are actually updated from the service task. | |
428 | **/ | |
9eed69a9 | 429 | static void i40e_get_netdev_stats_struct(struct net_device *netdev, |
bc1f4470 | 430 | struct rtnl_link_stats64 *stats) |
41c445ff JB |
431 | { |
432 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
433 | struct i40e_vsi *vsi = np->vsi; | |
980e9b11 | 434 | struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi); |
cdec2141 | 435 | struct i40e_ring *ring; |
980e9b11 AD |
436 | int i; |
437 | ||
0da36b97 | 438 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) |
bc1f4470 | 439 | return; |
bc7d338f | 440 | |
3c325ced | 441 | if (!vsi->tx_rings) |
bc1f4470 | 442 | return; |
3c325ced | 443 | |
980e9b11 AD |
444 | rcu_read_lock(); |
445 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
980e9b11 AD |
446 | u64 bytes, packets; |
447 | unsigned int start; | |
448 | ||
cdec2141 BT |
449 | ring = READ_ONCE(vsi->tx_rings[i]); |
450 | if (!ring) | |
980e9b11 | 451 | continue; |
cdec2141 | 452 | i40e_get_netdev_stats_struct_tx(ring, stats); |
980e9b11 | 453 | |
cdec2141 | 454 | if (i40e_enabled_xdp_vsi(vsi)) { |
d59e2679 CL |
455 | ring = READ_ONCE(vsi->xdp_rings[i]); |
456 | if (!ring) | |
457 | continue; | |
cdec2141 BT |
458 | i40e_get_netdev_stats_struct_tx(ring, stats); |
459 | } | |
980e9b11 | 460 | |
d59e2679 CL |
461 | ring = READ_ONCE(vsi->rx_rings[i]); |
462 | if (!ring) | |
463 | continue; | |
980e9b11 | 464 | do { |
cdec2141 BT |
465 | start = u64_stats_fetch_begin_irq(&ring->syncp); |
466 | packets = ring->stats.packets; | |
467 | bytes = ring->stats.bytes; | |
468 | } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); | |
41c445ff | 469 | |
980e9b11 AD |
470 | stats->rx_packets += packets; |
471 | stats->rx_bytes += bytes; | |
74608d17 | 472 | |
980e9b11 AD |
473 | } |
474 | rcu_read_unlock(); | |
475 | ||
a5282f44 | 476 | /* following stats updated by i40e_watchdog_subtask() */ |
980e9b11 AD |
477 | stats->multicast = vsi_stats->multicast; |
478 | stats->tx_errors = vsi_stats->tx_errors; | |
479 | stats->tx_dropped = vsi_stats->tx_dropped; | |
480 | stats->rx_errors = vsi_stats->rx_errors; | |
d8201e20 | 481 | stats->rx_dropped = vsi_stats->rx_dropped; |
980e9b11 AD |
482 | stats->rx_crc_errors = vsi_stats->rx_crc_errors; |
483 | stats->rx_length_errors = vsi_stats->rx_length_errors; | |
41c445ff JB |
484 | } |
485 | ||
486 | /** | |
487 | * i40e_vsi_reset_stats - Resets all stats of the given vsi | |
488 | * @vsi: the VSI to have its stats reset | |
489 | **/ | |
490 | void i40e_vsi_reset_stats(struct i40e_vsi *vsi) | |
491 | { | |
492 | struct rtnl_link_stats64 *ns; | |
493 | int i; | |
494 | ||
495 | if (!vsi) | |
496 | return; | |
497 | ||
498 | ns = i40e_get_vsi_stats_struct(vsi); | |
499 | memset(ns, 0, sizeof(*ns)); | |
500 | memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets)); | |
501 | memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats)); | |
502 | memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets)); | |
8e9dca53 | 503 | if (vsi->rx_rings && vsi->rx_rings[0]) { |
41c445ff | 504 | for (i = 0; i < vsi->num_queue_pairs; i++) { |
6995b36c | 505 | memset(&vsi->rx_rings[i]->stats, 0, |
9f65e15b | 506 | sizeof(vsi->rx_rings[i]->stats)); |
6995b36c | 507 | memset(&vsi->rx_rings[i]->rx_stats, 0, |
9f65e15b | 508 | sizeof(vsi->rx_rings[i]->rx_stats)); |
6995b36c | 509 | memset(&vsi->tx_rings[i]->stats, 0, |
9f65e15b AD |
510 | sizeof(vsi->tx_rings[i]->stats)); |
511 | memset(&vsi->tx_rings[i]->tx_stats, 0, | |
512 | sizeof(vsi->tx_rings[i]->tx_stats)); | |
41c445ff | 513 | } |
8e9dca53 | 514 | } |
41c445ff JB |
515 | vsi->stat_offsets_loaded = false; |
516 | } | |
517 | ||
518 | /** | |
b40c82e6 | 519 | * i40e_pf_reset_stats - Reset all of the stats for the given PF |
41c445ff JB |
520 | * @pf: the PF to be reset |
521 | **/ | |
522 | void i40e_pf_reset_stats(struct i40e_pf *pf) | |
523 | { | |
e91fdf76 SN |
524 | int i; |
525 | ||
41c445ff JB |
526 | memset(&pf->stats, 0, sizeof(pf->stats)); |
527 | memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets)); | |
528 | pf->stat_offsets_loaded = false; | |
e91fdf76 SN |
529 | |
530 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
531 | if (pf->veb[i]) { | |
532 | memset(&pf->veb[i]->stats, 0, | |
533 | sizeof(pf->veb[i]->stats)); | |
534 | memset(&pf->veb[i]->stats_offsets, 0, | |
535 | sizeof(pf->veb[i]->stats_offsets)); | |
1e0303fd JK |
536 | memset(&pf->veb[i]->tc_stats, 0, |
537 | sizeof(pf->veb[i]->tc_stats)); | |
538 | memset(&pf->veb[i]->tc_stats_offsets, 0, | |
539 | sizeof(pf->veb[i]->tc_stats_offsets)); | |
e91fdf76 SN |
540 | pf->veb[i]->stat_offsets_loaded = false; |
541 | } | |
542 | } | |
42bce04e | 543 | pf->hw_csum_rx_error = 0; |
41c445ff JB |
544 | } |
545 | ||
546 | /** | |
547 | * i40e_stat_update48 - read and update a 48 bit stat from the chip | |
548 | * @hw: ptr to the hardware info | |
549 | * @hireg: the high 32 bit reg to read | |
550 | * @loreg: the low 32 bit reg to read | |
551 | * @offset_loaded: has the initial offset been loaded yet | |
552 | * @offset: ptr to current offset value | |
553 | * @stat: ptr to the stat | |
554 | * | |
555 | * Since the device stats are not reset at PFReset, they likely will not | |
556 | * be zeroed when the driver starts. We'll save the first values read | |
557 | * and use them as offsets to be subtracted from the raw values in order | |
558 | * to report stats that count from zero. In the process, we also manage | |
559 | * the potential roll-over. | |
560 | **/ | |
561 | static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg, | |
562 | bool offset_loaded, u64 *offset, u64 *stat) | |
563 | { | |
564 | u64 new_data; | |
565 | ||
ab60085e | 566 | if (hw->device_id == I40E_DEV_ID_QEMU) { |
41c445ff JB |
567 | new_data = rd32(hw, loreg); |
568 | new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; | |
569 | } else { | |
570 | new_data = rd64(hw, loreg); | |
571 | } | |
572 | if (!offset_loaded) | |
573 | *offset = new_data; | |
574 | if (likely(new_data >= *offset)) | |
575 | *stat = new_data - *offset; | |
576 | else | |
41a1d04b | 577 | *stat = (new_data + BIT_ULL(48)) - *offset; |
41c445ff JB |
578 | *stat &= 0xFFFFFFFFFFFFULL; |
579 | } | |
580 | ||
581 | /** | |
582 | * i40e_stat_update32 - read and update a 32 bit stat from the chip | |
583 | * @hw: ptr to the hardware info | |
584 | * @reg: the hw reg to read | |
585 | * @offset_loaded: has the initial offset been loaded yet | |
586 | * @offset: ptr to current offset value | |
587 | * @stat: ptr to the stat | |
588 | **/ | |
589 | static void i40e_stat_update32(struct i40e_hw *hw, u32 reg, | |
590 | bool offset_loaded, u64 *offset, u64 *stat) | |
591 | { | |
592 | u32 new_data; | |
593 | ||
594 | new_data = rd32(hw, reg); | |
595 | if (!offset_loaded) | |
596 | *offset = new_data; | |
597 | if (likely(new_data >= *offset)) | |
598 | *stat = (u32)(new_data - *offset); | |
599 | else | |
41a1d04b | 600 | *stat = (u32)((new_data + BIT_ULL(32)) - *offset); |
41c445ff JB |
601 | } |
602 | ||
0dc8692e MS |
603 | /** |
604 | * i40e_stat_update_and_clear32 - read and clear hw reg, update a 32 bit stat | |
605 | * @hw: ptr to the hardware info | |
606 | * @reg: the hw reg to read and clear | |
607 | * @stat: ptr to the stat | |
608 | **/ | |
609 | static void i40e_stat_update_and_clear32(struct i40e_hw *hw, u32 reg, u64 *stat) | |
610 | { | |
611 | u32 new_data = rd32(hw, reg); | |
612 | ||
613 | wr32(hw, reg, 1); /* must write a nonzero value to clear register */ | |
614 | *stat += new_data; | |
615 | } | |
616 | ||
41c445ff JB |
617 | /** |
618 | * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters. | |
619 | * @vsi: the VSI to be updated | |
620 | **/ | |
621 | void i40e_update_eth_stats(struct i40e_vsi *vsi) | |
622 | { | |
623 | int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx); | |
624 | struct i40e_pf *pf = vsi->back; | |
625 | struct i40e_hw *hw = &pf->hw; | |
626 | struct i40e_eth_stats *oes; | |
627 | struct i40e_eth_stats *es; /* device's eth stats */ | |
628 | ||
629 | es = &vsi->eth_stats; | |
630 | oes = &vsi->eth_stats_offsets; | |
631 | ||
632 | /* Gather up the stats that the hw collects */ | |
633 | i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), | |
634 | vsi->stat_offsets_loaded, | |
635 | &oes->tx_errors, &es->tx_errors); | |
636 | i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), | |
637 | vsi->stat_offsets_loaded, | |
638 | &oes->rx_discards, &es->rx_discards); | |
41a9e55c SN |
639 | i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx), |
640 | vsi->stat_offsets_loaded, | |
641 | &oes->rx_unknown_protocol, &es->rx_unknown_protocol); | |
41c445ff JB |
642 | |
643 | i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx), | |
644 | I40E_GLV_GORCL(stat_idx), | |
645 | vsi->stat_offsets_loaded, | |
646 | &oes->rx_bytes, &es->rx_bytes); | |
647 | i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx), | |
648 | I40E_GLV_UPRCL(stat_idx), | |
649 | vsi->stat_offsets_loaded, | |
650 | &oes->rx_unicast, &es->rx_unicast); | |
651 | i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx), | |
652 | I40E_GLV_MPRCL(stat_idx), | |
653 | vsi->stat_offsets_loaded, | |
654 | &oes->rx_multicast, &es->rx_multicast); | |
655 | i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx), | |
656 | I40E_GLV_BPRCL(stat_idx), | |
657 | vsi->stat_offsets_loaded, | |
658 | &oes->rx_broadcast, &es->rx_broadcast); | |
659 | ||
660 | i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx), | |
661 | I40E_GLV_GOTCL(stat_idx), | |
662 | vsi->stat_offsets_loaded, | |
663 | &oes->tx_bytes, &es->tx_bytes); | |
664 | i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx), | |
665 | I40E_GLV_UPTCL(stat_idx), | |
666 | vsi->stat_offsets_loaded, | |
667 | &oes->tx_unicast, &es->tx_unicast); | |
668 | i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx), | |
669 | I40E_GLV_MPTCL(stat_idx), | |
670 | vsi->stat_offsets_loaded, | |
671 | &oes->tx_multicast, &es->tx_multicast); | |
672 | i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx), | |
673 | I40E_GLV_BPTCL(stat_idx), | |
674 | vsi->stat_offsets_loaded, | |
675 | &oes->tx_broadcast, &es->tx_broadcast); | |
676 | vsi->stat_offsets_loaded = true; | |
677 | } | |
678 | ||
679 | /** | |
680 | * i40e_update_veb_stats - Update Switch component statistics | |
681 | * @veb: the VEB being updated | |
682 | **/ | |
f21fa060 | 683 | void i40e_update_veb_stats(struct i40e_veb *veb) |
41c445ff JB |
684 | { |
685 | struct i40e_pf *pf = veb->pf; | |
686 | struct i40e_hw *hw = &pf->hw; | |
687 | struct i40e_eth_stats *oes; | |
688 | struct i40e_eth_stats *es; /* device's eth stats */ | |
fe860afb NP |
689 | struct i40e_veb_tc_stats *veb_oes; |
690 | struct i40e_veb_tc_stats *veb_es; | |
691 | int i, idx = 0; | |
41c445ff JB |
692 | |
693 | idx = veb->stats_idx; | |
694 | es = &veb->stats; | |
695 | oes = &veb->stats_offsets; | |
fe860afb NP |
696 | veb_es = &veb->tc_stats; |
697 | veb_oes = &veb->tc_stats_offsets; | |
41c445ff JB |
698 | |
699 | /* Gather up the stats that the hw collects */ | |
700 | i40e_stat_update32(hw, I40E_GLSW_TDPC(idx), | |
701 | veb->stat_offsets_loaded, | |
702 | &oes->tx_discards, &es->tx_discards); | |
7134f9ce JB |
703 | if (hw->revision_id > 0) |
704 | i40e_stat_update32(hw, I40E_GLSW_RUPP(idx), | |
705 | veb->stat_offsets_loaded, | |
706 | &oes->rx_unknown_protocol, | |
707 | &es->rx_unknown_protocol); | |
41c445ff JB |
708 | i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx), |
709 | veb->stat_offsets_loaded, | |
710 | &oes->rx_bytes, &es->rx_bytes); | |
711 | i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx), | |
712 | veb->stat_offsets_loaded, | |
713 | &oes->rx_unicast, &es->rx_unicast); | |
714 | i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx), | |
715 | veb->stat_offsets_loaded, | |
716 | &oes->rx_multicast, &es->rx_multicast); | |
717 | i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx), | |
718 | veb->stat_offsets_loaded, | |
719 | &oes->rx_broadcast, &es->rx_broadcast); | |
720 | ||
721 | i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx), | |
722 | veb->stat_offsets_loaded, | |
723 | &oes->tx_bytes, &es->tx_bytes); | |
724 | i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx), | |
725 | veb->stat_offsets_loaded, | |
726 | &oes->tx_unicast, &es->tx_unicast); | |
727 | i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx), | |
728 | veb->stat_offsets_loaded, | |
729 | &oes->tx_multicast, &es->tx_multicast); | |
730 | i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx), | |
731 | veb->stat_offsets_loaded, | |
732 | &oes->tx_broadcast, &es->tx_broadcast); | |
fe860afb NP |
733 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
734 | i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx), | |
735 | I40E_GLVEBTC_RPCL(i, idx), | |
736 | veb->stat_offsets_loaded, | |
737 | &veb_oes->tc_rx_packets[i], | |
738 | &veb_es->tc_rx_packets[i]); | |
739 | i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx), | |
740 | I40E_GLVEBTC_RBCL(i, idx), | |
741 | veb->stat_offsets_loaded, | |
742 | &veb_oes->tc_rx_bytes[i], | |
743 | &veb_es->tc_rx_bytes[i]); | |
744 | i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx), | |
745 | I40E_GLVEBTC_TPCL(i, idx), | |
746 | veb->stat_offsets_loaded, | |
747 | &veb_oes->tc_tx_packets[i], | |
748 | &veb_es->tc_tx_packets[i]); | |
749 | i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx), | |
750 | I40E_GLVEBTC_TBCL(i, idx), | |
751 | veb->stat_offsets_loaded, | |
752 | &veb_oes->tc_tx_bytes[i], | |
753 | &veb_es->tc_tx_bytes[i]); | |
754 | } | |
41c445ff JB |
755 | veb->stat_offsets_loaded = true; |
756 | } | |
757 | ||
41c445ff | 758 | /** |
7812fddc | 759 | * i40e_update_vsi_stats - Update the vsi statistics counters. |
41c445ff JB |
760 | * @vsi: the VSI to be updated |
761 | * | |
762 | * There are a few instances where we store the same stat in a | |
763 | * couple of different structs. This is partly because we have | |
764 | * the netdev stats that need to be filled out, which is slightly | |
765 | * different from the "eth_stats" defined by the chip and used in | |
7812fddc | 766 | * VF communications. We sort it out here. |
41c445ff | 767 | **/ |
7812fddc | 768 | static void i40e_update_vsi_stats(struct i40e_vsi *vsi) |
41c445ff JB |
769 | { |
770 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
771 | struct rtnl_link_stats64 *ons; |
772 | struct rtnl_link_stats64 *ns; /* netdev stats */ | |
773 | struct i40e_eth_stats *oes; | |
774 | struct i40e_eth_stats *es; /* device's eth stats */ | |
775 | u32 tx_restart, tx_busy; | |
bf00b376 | 776 | struct i40e_ring *p; |
41c445ff | 777 | u32 rx_page, rx_buf; |
bf00b376 AA |
778 | u64 bytes, packets; |
779 | unsigned int start; | |
2fc3d715 | 780 | u64 tx_linearize; |
164c9f54 | 781 | u64 tx_force_wb; |
41c445ff JB |
782 | u64 rx_p, rx_b; |
783 | u64 tx_p, tx_b; | |
41c445ff JB |
784 | u16 q; |
785 | ||
0da36b97 JK |
786 | if (test_bit(__I40E_VSI_DOWN, vsi->state) || |
787 | test_bit(__I40E_CONFIG_BUSY, pf->state)) | |
41c445ff JB |
788 | return; |
789 | ||
790 | ns = i40e_get_vsi_stats_struct(vsi); | |
791 | ons = &vsi->net_stats_offsets; | |
792 | es = &vsi->eth_stats; | |
793 | oes = &vsi->eth_stats_offsets; | |
794 | ||
795 | /* Gather up the netdev and vsi stats that the driver collects | |
796 | * on the fly during packet processing | |
797 | */ | |
798 | rx_b = rx_p = 0; | |
799 | tx_b = tx_p = 0; | |
164c9f54 | 800 | tx_restart = tx_busy = tx_linearize = tx_force_wb = 0; |
41c445ff JB |
801 | rx_page = 0; |
802 | rx_buf = 0; | |
980e9b11 | 803 | rcu_read_lock(); |
41c445ff | 804 | for (q = 0; q < vsi->num_queue_pairs; q++) { |
980e9b11 | 805 | /* locate Tx ring */ |
6aa7de05 | 806 | p = READ_ONCE(vsi->tx_rings[q]); |
d59e2679 CL |
807 | if (!p) |
808 | continue; | |
980e9b11 AD |
809 | |
810 | do { | |
57a7744e | 811 | start = u64_stats_fetch_begin_irq(&p->syncp); |
980e9b11 AD |
812 | packets = p->stats.packets; |
813 | bytes = p->stats.bytes; | |
57a7744e | 814 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); |
980e9b11 AD |
815 | tx_b += bytes; |
816 | tx_p += packets; | |
817 | tx_restart += p->tx_stats.restart_queue; | |
818 | tx_busy += p->tx_stats.tx_busy; | |
2fc3d715 | 819 | tx_linearize += p->tx_stats.tx_linearize; |
164c9f54 | 820 | tx_force_wb += p->tx_stats.tx_force_wb; |
41c445ff | 821 | |
d59e2679 CL |
822 | /* locate Rx ring */ |
823 | p = READ_ONCE(vsi->rx_rings[q]); | |
824 | if (!p) | |
825 | continue; | |
826 | ||
980e9b11 | 827 | do { |
57a7744e | 828 | start = u64_stats_fetch_begin_irq(&p->syncp); |
980e9b11 AD |
829 | packets = p->stats.packets; |
830 | bytes = p->stats.bytes; | |
57a7744e | 831 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); |
980e9b11 AD |
832 | rx_b += bytes; |
833 | rx_p += packets; | |
420136cc MW |
834 | rx_buf += p->rx_stats.alloc_buff_failed; |
835 | rx_page += p->rx_stats.alloc_page_failed; | |
e2968260 CL |
836 | |
837 | if (i40e_enabled_xdp_vsi(vsi)) { | |
838 | /* locate XDP ring */ | |
839 | p = READ_ONCE(vsi->xdp_rings[q]); | |
840 | if (!p) | |
841 | continue; | |
842 | ||
843 | do { | |
844 | start = u64_stats_fetch_begin_irq(&p->syncp); | |
845 | packets = p->stats.packets; | |
846 | bytes = p->stats.bytes; | |
847 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); | |
848 | tx_b += bytes; | |
849 | tx_p += packets; | |
850 | tx_restart += p->tx_stats.restart_queue; | |
851 | tx_busy += p->tx_stats.tx_busy; | |
852 | tx_linearize += p->tx_stats.tx_linearize; | |
853 | tx_force_wb += p->tx_stats.tx_force_wb; | |
854 | } | |
41c445ff | 855 | } |
980e9b11 | 856 | rcu_read_unlock(); |
41c445ff JB |
857 | vsi->tx_restart = tx_restart; |
858 | vsi->tx_busy = tx_busy; | |
2fc3d715 | 859 | vsi->tx_linearize = tx_linearize; |
164c9f54 | 860 | vsi->tx_force_wb = tx_force_wb; |
41c445ff JB |
861 | vsi->rx_page_failed = rx_page; |
862 | vsi->rx_buf_failed = rx_buf; | |
863 | ||
864 | ns->rx_packets = rx_p; | |
865 | ns->rx_bytes = rx_b; | |
866 | ns->tx_packets = tx_p; | |
867 | ns->tx_bytes = tx_b; | |
868 | ||
41c445ff | 869 | /* update netdev stats from eth stats */ |
7812fddc | 870 | i40e_update_eth_stats(vsi); |
41c445ff JB |
871 | ons->tx_errors = oes->tx_errors; |
872 | ns->tx_errors = es->tx_errors; | |
873 | ons->multicast = oes->rx_multicast; | |
874 | ns->multicast = es->rx_multicast; | |
41a9e55c SN |
875 | ons->rx_dropped = oes->rx_discards; |
876 | ns->rx_dropped = es->rx_discards; | |
41c445ff JB |
877 | ons->tx_dropped = oes->tx_discards; |
878 | ns->tx_dropped = es->tx_discards; | |
879 | ||
7812fddc | 880 | /* pull in a couple PF stats if this is the main vsi */ |
41c445ff | 881 | if (vsi == pf->vsi[pf->lan_vsi]) { |
7812fddc SN |
882 | ns->rx_crc_errors = pf->stats.crc_errors; |
883 | ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes; | |
884 | ns->rx_length_errors = pf->stats.rx_length_errors; | |
885 | } | |
886 | } | |
41c445ff | 887 | |
7812fddc | 888 | /** |
b40c82e6 | 889 | * i40e_update_pf_stats - Update the PF statistics counters. |
7812fddc SN |
890 | * @pf: the PF to be updated |
891 | **/ | |
892 | static void i40e_update_pf_stats(struct i40e_pf *pf) | |
893 | { | |
894 | struct i40e_hw_port_stats *osd = &pf->stats_offsets; | |
895 | struct i40e_hw_port_stats *nsd = &pf->stats; | |
896 | struct i40e_hw *hw = &pf->hw; | |
897 | u32 val; | |
898 | int i; | |
41c445ff | 899 | |
7812fddc SN |
900 | i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port), |
901 | I40E_GLPRT_GORCL(hw->port), | |
902 | pf->stat_offsets_loaded, | |
903 | &osd->eth.rx_bytes, &nsd->eth.rx_bytes); | |
904 | i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port), | |
905 | I40E_GLPRT_GOTCL(hw->port), | |
906 | pf->stat_offsets_loaded, | |
907 | &osd->eth.tx_bytes, &nsd->eth.tx_bytes); | |
908 | i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port), | |
909 | pf->stat_offsets_loaded, | |
910 | &osd->eth.rx_discards, | |
911 | &nsd->eth.rx_discards); | |
532d283d SN |
912 | i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port), |
913 | I40E_GLPRT_UPRCL(hw->port), | |
914 | pf->stat_offsets_loaded, | |
915 | &osd->eth.rx_unicast, | |
916 | &nsd->eth.rx_unicast); | |
7812fddc SN |
917 | i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port), |
918 | I40E_GLPRT_MPRCL(hw->port), | |
919 | pf->stat_offsets_loaded, | |
920 | &osd->eth.rx_multicast, | |
921 | &nsd->eth.rx_multicast); | |
532d283d SN |
922 | i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port), |
923 | I40E_GLPRT_BPRCL(hw->port), | |
924 | pf->stat_offsets_loaded, | |
925 | &osd->eth.rx_broadcast, | |
926 | &nsd->eth.rx_broadcast); | |
927 | i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port), | |
928 | I40E_GLPRT_UPTCL(hw->port), | |
929 | pf->stat_offsets_loaded, | |
930 | &osd->eth.tx_unicast, | |
931 | &nsd->eth.tx_unicast); | |
932 | i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port), | |
933 | I40E_GLPRT_MPTCL(hw->port), | |
934 | pf->stat_offsets_loaded, | |
935 | &osd->eth.tx_multicast, | |
936 | &nsd->eth.tx_multicast); | |
937 | i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port), | |
938 | I40E_GLPRT_BPTCL(hw->port), | |
939 | pf->stat_offsets_loaded, | |
940 | &osd->eth.tx_broadcast, | |
941 | &nsd->eth.tx_broadcast); | |
41c445ff | 942 | |
7812fddc SN |
943 | i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port), |
944 | pf->stat_offsets_loaded, | |
945 | &osd->tx_dropped_link_down, | |
946 | &nsd->tx_dropped_link_down); | |
41c445ff | 947 | |
7812fddc SN |
948 | i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port), |
949 | pf->stat_offsets_loaded, | |
950 | &osd->crc_errors, &nsd->crc_errors); | |
41c445ff | 951 | |
7812fddc SN |
952 | i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port), |
953 | pf->stat_offsets_loaded, | |
954 | &osd->illegal_bytes, &nsd->illegal_bytes); | |
41c445ff | 955 | |
7812fddc SN |
956 | i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port), |
957 | pf->stat_offsets_loaded, | |
958 | &osd->mac_local_faults, | |
959 | &nsd->mac_local_faults); | |
960 | i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port), | |
961 | pf->stat_offsets_loaded, | |
962 | &osd->mac_remote_faults, | |
963 | &nsd->mac_remote_faults); | |
41c445ff | 964 | |
7812fddc SN |
965 | i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port), |
966 | pf->stat_offsets_loaded, | |
967 | &osd->rx_length_errors, | |
968 | &nsd->rx_length_errors); | |
41c445ff | 969 | |
7812fddc SN |
970 | i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port), |
971 | pf->stat_offsets_loaded, | |
972 | &osd->link_xon_rx, &nsd->link_xon_rx); | |
973 | i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port), | |
974 | pf->stat_offsets_loaded, | |
975 | &osd->link_xon_tx, &nsd->link_xon_tx); | |
95db239f NP |
976 | i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port), |
977 | pf->stat_offsets_loaded, | |
978 | &osd->link_xoff_rx, &nsd->link_xoff_rx); | |
7812fddc SN |
979 | i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port), |
980 | pf->stat_offsets_loaded, | |
981 | &osd->link_xoff_tx, &nsd->link_xoff_tx); | |
41c445ff | 982 | |
7812fddc | 983 | for (i = 0; i < 8; i++) { |
95db239f NP |
984 | i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i), |
985 | pf->stat_offsets_loaded, | |
986 | &osd->priority_xoff_rx[i], | |
987 | &nsd->priority_xoff_rx[i]); | |
7812fddc | 988 | i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i), |
41c445ff | 989 | pf->stat_offsets_loaded, |
7812fddc SN |
990 | &osd->priority_xon_rx[i], |
991 | &nsd->priority_xon_rx[i]); | |
992 | i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i), | |
41c445ff | 993 | pf->stat_offsets_loaded, |
7812fddc SN |
994 | &osd->priority_xon_tx[i], |
995 | &nsd->priority_xon_tx[i]); | |
996 | i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i), | |
41c445ff | 997 | pf->stat_offsets_loaded, |
7812fddc SN |
998 | &osd->priority_xoff_tx[i], |
999 | &nsd->priority_xoff_tx[i]); | |
1000 | i40e_stat_update32(hw, | |
1001 | I40E_GLPRT_RXON2OFFCNT(hw->port, i), | |
bee5af7e | 1002 | pf->stat_offsets_loaded, |
7812fddc SN |
1003 | &osd->priority_xon_2_xoff[i], |
1004 | &nsd->priority_xon_2_xoff[i]); | |
41c445ff JB |
1005 | } |
1006 | ||
7812fddc SN |
1007 | i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port), |
1008 | I40E_GLPRT_PRC64L(hw->port), | |
1009 | pf->stat_offsets_loaded, | |
1010 | &osd->rx_size_64, &nsd->rx_size_64); | |
1011 | i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port), | |
1012 | I40E_GLPRT_PRC127L(hw->port), | |
1013 | pf->stat_offsets_loaded, | |
1014 | &osd->rx_size_127, &nsd->rx_size_127); | |
1015 | i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port), | |
1016 | I40E_GLPRT_PRC255L(hw->port), | |
1017 | pf->stat_offsets_loaded, | |
1018 | &osd->rx_size_255, &nsd->rx_size_255); | |
1019 | i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port), | |
1020 | I40E_GLPRT_PRC511L(hw->port), | |
1021 | pf->stat_offsets_loaded, | |
1022 | &osd->rx_size_511, &nsd->rx_size_511); | |
1023 | i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port), | |
1024 | I40E_GLPRT_PRC1023L(hw->port), | |
1025 | pf->stat_offsets_loaded, | |
1026 | &osd->rx_size_1023, &nsd->rx_size_1023); | |
1027 | i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port), | |
1028 | I40E_GLPRT_PRC1522L(hw->port), | |
1029 | pf->stat_offsets_loaded, | |
1030 | &osd->rx_size_1522, &nsd->rx_size_1522); | |
1031 | i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port), | |
1032 | I40E_GLPRT_PRC9522L(hw->port), | |
1033 | pf->stat_offsets_loaded, | |
1034 | &osd->rx_size_big, &nsd->rx_size_big); | |
1035 | ||
1036 | i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port), | |
1037 | I40E_GLPRT_PTC64L(hw->port), | |
1038 | pf->stat_offsets_loaded, | |
1039 | &osd->tx_size_64, &nsd->tx_size_64); | |
1040 | i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port), | |
1041 | I40E_GLPRT_PTC127L(hw->port), | |
1042 | pf->stat_offsets_loaded, | |
1043 | &osd->tx_size_127, &nsd->tx_size_127); | |
1044 | i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port), | |
1045 | I40E_GLPRT_PTC255L(hw->port), | |
1046 | pf->stat_offsets_loaded, | |
1047 | &osd->tx_size_255, &nsd->tx_size_255); | |
1048 | i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port), | |
1049 | I40E_GLPRT_PTC511L(hw->port), | |
1050 | pf->stat_offsets_loaded, | |
1051 | &osd->tx_size_511, &nsd->tx_size_511); | |
1052 | i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port), | |
1053 | I40E_GLPRT_PTC1023L(hw->port), | |
1054 | pf->stat_offsets_loaded, | |
1055 | &osd->tx_size_1023, &nsd->tx_size_1023); | |
1056 | i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port), | |
1057 | I40E_GLPRT_PTC1522L(hw->port), | |
1058 | pf->stat_offsets_loaded, | |
1059 | &osd->tx_size_1522, &nsd->tx_size_1522); | |
1060 | i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port), | |
1061 | I40E_GLPRT_PTC9522L(hw->port), | |
1062 | pf->stat_offsets_loaded, | |
1063 | &osd->tx_size_big, &nsd->tx_size_big); | |
1064 | ||
1065 | i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port), | |
1066 | pf->stat_offsets_loaded, | |
1067 | &osd->rx_undersize, &nsd->rx_undersize); | |
1068 | i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port), | |
1069 | pf->stat_offsets_loaded, | |
1070 | &osd->rx_fragments, &nsd->rx_fragments); | |
1071 | i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port), | |
1072 | pf->stat_offsets_loaded, | |
1073 | &osd->rx_oversize, &nsd->rx_oversize); | |
1074 | i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port), | |
1075 | pf->stat_offsets_loaded, | |
1076 | &osd->rx_jabber, &nsd->rx_jabber); | |
1077 | ||
433c47de | 1078 | /* FDIR stats */ |
0dc8692e MS |
1079 | i40e_stat_update_and_clear32(hw, |
1080 | I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(hw->pf_id)), | |
1081 | &nsd->fd_atr_match); | |
1082 | i40e_stat_update_and_clear32(hw, | |
1083 | I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(hw->pf_id)), | |
1084 | &nsd->fd_sb_match); | |
1085 | i40e_stat_update_and_clear32(hw, | |
1086 | I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(hw->pf_id)), | |
1087 | &nsd->fd_atr_tunnel_match); | |
433c47de | 1088 | |
7812fddc SN |
1089 | val = rd32(hw, I40E_PRTPM_EEE_STAT); |
1090 | nsd->tx_lpi_status = | |
1091 | (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >> | |
1092 | I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT; | |
1093 | nsd->rx_lpi_status = | |
1094 | (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >> | |
1095 | I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT; | |
1096 | i40e_stat_update32(hw, I40E_PRTPM_TLPIC, | |
1097 | pf->stat_offsets_loaded, | |
1098 | &osd->tx_lpi_count, &nsd->tx_lpi_count); | |
1099 | i40e_stat_update32(hw, I40E_PRTPM_RLPIC, | |
1100 | pf->stat_offsets_loaded, | |
1101 | &osd->rx_lpi_count, &nsd->rx_lpi_count); | |
1102 | ||
d0389e51 | 1103 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED && |
134201ae | 1104 | !test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) |
d0389e51 ASJ |
1105 | nsd->fd_sb_status = true; |
1106 | else | |
1107 | nsd->fd_sb_status = false; | |
1108 | ||
1109 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED && | |
134201ae | 1110 | !test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) |
d0389e51 ASJ |
1111 | nsd->fd_atr_status = true; |
1112 | else | |
1113 | nsd->fd_atr_status = false; | |
1114 | ||
41c445ff JB |
1115 | pf->stat_offsets_loaded = true; |
1116 | } | |
1117 | ||
7812fddc SN |
1118 | /** |
1119 | * i40e_update_stats - Update the various statistics counters. | |
1120 | * @vsi: the VSI to be updated | |
1121 | * | |
1122 | * Update the various stats for this VSI and its related entities. | |
1123 | **/ | |
1124 | void i40e_update_stats(struct i40e_vsi *vsi) | |
1125 | { | |
1126 | struct i40e_pf *pf = vsi->back; | |
1127 | ||
1128 | if (vsi == pf->vsi[pf->lan_vsi]) | |
1129 | i40e_update_pf_stats(pf); | |
1130 | ||
1131 | i40e_update_vsi_stats(vsi); | |
1132 | } | |
1133 | ||
621650ca AL |
1134 | /** |
1135 | * i40e_count_filters - counts VSI mac filters | |
1136 | * @vsi: the VSI to be searched | |
1137 | * | |
1138 | * Returns count of mac filters | |
1139 | **/ | |
1140 | int i40e_count_filters(struct i40e_vsi *vsi) | |
1141 | { | |
1142 | struct i40e_mac_filter *f; | |
1143 | struct hlist_node *h; | |
1144 | int bkt; | |
1145 | int cnt = 0; | |
1146 | ||
1147 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) | |
1148 | ++cnt; | |
1149 | ||
1150 | return cnt; | |
1151 | } | |
1152 | ||
41c445ff JB |
1153 | /** |
1154 | * i40e_find_filter - Search VSI filter list for specific mac/vlan filter | |
1155 | * @vsi: the VSI to be searched | |
1156 | * @macaddr: the MAC address | |
1157 | * @vlan: the vlan | |
41c445ff JB |
1158 | * |
1159 | * Returns ptr to the filter object or NULL | |
1160 | **/ | |
1161 | static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi, | |
6622f5cd | 1162 | const u8 *macaddr, s16 vlan) |
41c445ff JB |
1163 | { |
1164 | struct i40e_mac_filter *f; | |
278e7d0b | 1165 | u64 key; |
41c445ff JB |
1166 | |
1167 | if (!vsi || !macaddr) | |
1168 | return NULL; | |
1169 | ||
278e7d0b JK |
1170 | key = i40e_addr_to_hkey(macaddr); |
1171 | hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) { | |
41c445ff | 1172 | if ((ether_addr_equal(macaddr, f->macaddr)) && |
1bc87e80 | 1173 | (vlan == f->vlan)) |
41c445ff JB |
1174 | return f; |
1175 | } | |
1176 | return NULL; | |
1177 | } | |
1178 | ||
1179 | /** | |
1180 | * i40e_find_mac - Find a mac addr in the macvlan filters list | |
1181 | * @vsi: the VSI to be searched | |
1182 | * @macaddr: the MAC address we are searching for | |
41c445ff JB |
1183 | * |
1184 | * Returns the first filter with the provided MAC address or NULL if | |
1185 | * MAC address was not found | |
1186 | **/ | |
6622f5cd | 1187 | struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr) |
41c445ff JB |
1188 | { |
1189 | struct i40e_mac_filter *f; | |
278e7d0b | 1190 | u64 key; |
41c445ff JB |
1191 | |
1192 | if (!vsi || !macaddr) | |
1193 | return NULL; | |
1194 | ||
278e7d0b JK |
1195 | key = i40e_addr_to_hkey(macaddr); |
1196 | hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) { | |
1bc87e80 | 1197 | if ((ether_addr_equal(macaddr, f->macaddr))) |
41c445ff JB |
1198 | return f; |
1199 | } | |
1200 | return NULL; | |
1201 | } | |
1202 | ||
1203 | /** | |
1204 | * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode | |
1205 | * @vsi: the VSI to be searched | |
1206 | * | |
1207 | * Returns true if VSI is in vlan mode or false otherwise | |
1208 | **/ | |
1209 | bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi) | |
1210 | { | |
cbebb85f JK |
1211 | /* If we have a PVID, always operate in VLAN mode */ |
1212 | if (vsi->info.pvid) | |
1213 | return true; | |
1214 | ||
1215 | /* We need to operate in VLAN mode whenever we have any filters with | |
1216 | * a VLAN other than I40E_VLAN_ALL. We could check the table each | |
1217 | * time, incurring search cost repeatedly. However, we can notice two | |
1218 | * things: | |
1219 | * | |
1220 | * 1) the only place where we can gain a VLAN filter is in | |
1221 | * i40e_add_filter. | |
1222 | * | |
1223 | * 2) the only place where filters are actually removed is in | |
0b7c8b5d | 1224 | * i40e_sync_filters_subtask. |
cbebb85f JK |
1225 | * |
1226 | * Thus, we can simply use a boolean value, has_vlan_filters which we | |
1227 | * will set to true when we add a VLAN filter in i40e_add_filter. Then | |
1228 | * we have to perform the full search after deleting filters in | |
0b7c8b5d | 1229 | * i40e_sync_filters_subtask, but we already have to search |
cbebb85f JK |
1230 | * filters here and can perform the check at the same time. This |
1231 | * results in avoiding embedding a loop for VLAN mode inside another | |
1232 | * loop over all the filters, and should maintain correctness as noted | |
1233 | * above. | |
41c445ff | 1234 | */ |
cbebb85f | 1235 | return vsi->has_vlan_filter; |
41c445ff JB |
1236 | } |
1237 | ||
489a3265 JK |
1238 | /** |
1239 | * i40e_correct_mac_vlan_filters - Correct non-VLAN filters if necessary | |
1240 | * @vsi: the VSI to configure | |
1241 | * @tmp_add_list: list of filters ready to be added | |
1242 | * @tmp_del_list: list of filters ready to be deleted | |
1243 | * @vlan_filters: the number of active VLAN filters | |
1244 | * | |
1245 | * Update VLAN=0 and VLAN=-1 (I40E_VLAN_ANY) filters properly so that they | |
1246 | * behave as expected. If we have any active VLAN filters remaining or about | |
1247 | * to be added then we need to update non-VLAN filters to be marked as VLAN=0 | |
1248 | * so that they only match against untagged traffic. If we no longer have any | |
1249 | * active VLAN filters, we need to make all non-VLAN filters marked as VLAN=-1 | |
1250 | * so that they match against both tagged and untagged traffic. In this way, | |
1251 | * we ensure that we correctly receive the desired traffic. This ensures that | |
1252 | * when we have an active VLAN we will receive only untagged traffic and | |
1253 | * traffic matching active VLANs. If we have no active VLANs then we will | |
1254 | * operate in non-VLAN mode and receive all traffic, tagged or untagged. | |
1255 | * | |
1256 | * Finally, in a similar fashion, this function also corrects filters when | |
1257 | * there is an active PVID assigned to this VSI. | |
1258 | * | |
1259 | * In case of memory allocation failure return -ENOMEM. Otherwise, return 0. | |
1260 | * | |
1261 | * This function is only expected to be called from within | |
1262 | * i40e_sync_vsi_filters. | |
1263 | * | |
1264 | * NOTE: This function expects to be called while under the | |
1265 | * mac_filter_hash_lock | |
1266 | */ | |
1267 | static int i40e_correct_mac_vlan_filters(struct i40e_vsi *vsi, | |
1268 | struct hlist_head *tmp_add_list, | |
1269 | struct hlist_head *tmp_del_list, | |
1270 | int vlan_filters) | |
1271 | { | |
5cb25901 | 1272 | s16 pvid = le16_to_cpu(vsi->info.pvid); |
489a3265 | 1273 | struct i40e_mac_filter *f, *add_head; |
671889e6 | 1274 | struct i40e_new_mac_filter *new; |
489a3265 JK |
1275 | struct hlist_node *h; |
1276 | int bkt, new_vlan; | |
1277 | ||
1278 | /* To determine if a particular filter needs to be replaced we | |
1279 | * have the three following conditions: | |
1280 | * | |
1281 | * a) if we have a PVID assigned, then all filters which are | |
1282 | * not marked as VLAN=PVID must be replaced with filters that | |
1283 | * are. | |
1284 | * b) otherwise, if we have any active VLANS, all filters | |
1285 | * which are marked as VLAN=-1 must be replaced with | |
1286 | * filters marked as VLAN=0 | |
1287 | * c) finally, if we do not have any active VLANS, all filters | |
1288 | * which are marked as VLAN=0 must be replaced with filters | |
1289 | * marked as VLAN=-1 | |
1290 | */ | |
1291 | ||
1292 | /* Update the filters about to be added in place */ | |
671889e6 | 1293 | hlist_for_each_entry(new, tmp_add_list, hlist) { |
5cb25901 JK |
1294 | if (pvid && new->f->vlan != pvid) |
1295 | new->f->vlan = pvid; | |
671889e6 JK |
1296 | else if (vlan_filters && new->f->vlan == I40E_VLAN_ANY) |
1297 | new->f->vlan = 0; | |
1298 | else if (!vlan_filters && new->f->vlan == 0) | |
1299 | new->f->vlan = I40E_VLAN_ANY; | |
489a3265 JK |
1300 | } |
1301 | ||
1302 | /* Update the remaining active filters */ | |
1303 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { | |
1304 | /* Combine the checks for whether a filter needs to be changed | |
1305 | * and then determine the new VLAN inside the if block, in | |
1306 | * order to avoid duplicating code for adding the new filter | |
1307 | * then deleting the old filter. | |
1308 | */ | |
5cb25901 | 1309 | if ((pvid && f->vlan != pvid) || |
489a3265 JK |
1310 | (vlan_filters && f->vlan == I40E_VLAN_ANY) || |
1311 | (!vlan_filters && f->vlan == 0)) { | |
1312 | /* Determine the new vlan we will be adding */ | |
5cb25901 JK |
1313 | if (pvid) |
1314 | new_vlan = pvid; | |
489a3265 JK |
1315 | else if (vlan_filters) |
1316 | new_vlan = 0; | |
1317 | else | |
1318 | new_vlan = I40E_VLAN_ANY; | |
1319 | ||
1320 | /* Create the new filter */ | |
1321 | add_head = i40e_add_filter(vsi, f->macaddr, new_vlan); | |
1322 | if (!add_head) | |
1323 | return -ENOMEM; | |
1324 | ||
671889e6 JK |
1325 | /* Create a temporary i40e_new_mac_filter */ |
1326 | new = kzalloc(sizeof(*new), GFP_ATOMIC); | |
1327 | if (!new) | |
1328 | return -ENOMEM; | |
1329 | ||
1330 | new->f = add_head; | |
1331 | new->state = add_head->state; | |
1332 | ||
1333 | /* Add the new filter to the tmp list */ | |
1334 | hlist_add_head(&new->hlist, tmp_add_list); | |
489a3265 JK |
1335 | |
1336 | /* Put the original filter into the delete list */ | |
1337 | f->state = I40E_FILTER_REMOVE; | |
1338 | hash_del(&f->hlist); | |
1339 | hlist_add_head(&f->hlist, tmp_del_list); | |
1340 | } | |
1341 | } | |
1342 | ||
1343 | vsi->has_vlan_filter = !!vlan_filters; | |
1344 | ||
1345 | return 0; | |
1346 | } | |
1347 | ||
1596b5dd JK |
1348 | /** |
1349 | * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM | |
1350 | * @vsi: the PF Main VSI - inappropriate for any other VSI | |
1351 | * @macaddr: the MAC address | |
1352 | * | |
1353 | * Remove whatever filter the firmware set up so the driver can manage | |
1354 | * its own filtering intelligently. | |
1355 | **/ | |
1356 | static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr) | |
1357 | { | |
1358 | struct i40e_aqc_remove_macvlan_element_data element; | |
1359 | struct i40e_pf *pf = vsi->back; | |
1360 | ||
1361 | /* Only appropriate for the PF main VSI */ | |
1362 | if (vsi->type != I40E_VSI_MAIN) | |
1363 | return; | |
1364 | ||
1365 | memset(&element, 0, sizeof(element)); | |
1366 | ether_addr_copy(element.mac_addr, macaddr); | |
1367 | element.vlan_tag = 0; | |
1368 | /* Ignore error returns, some firmware does it this way... */ | |
1369 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; | |
1370 | i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); | |
1371 | ||
1372 | memset(&element, 0, sizeof(element)); | |
1373 | ether_addr_copy(element.mac_addr, macaddr); | |
1374 | element.vlan_tag = 0; | |
1375 | /* ...and some firmware does it this way. */ | |
1376 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | | |
1377 | I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; | |
1378 | i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); | |
1379 | } | |
1380 | ||
41c445ff JB |
1381 | /** |
1382 | * i40e_add_filter - Add a mac/vlan filter to the VSI | |
1383 | * @vsi: the VSI to be searched | |
1384 | * @macaddr: the MAC address | |
1385 | * @vlan: the vlan | |
41c445ff JB |
1386 | * |
1387 | * Returns ptr to the filter object or NULL when no memory available. | |
21659035 | 1388 | * |
278e7d0b | 1389 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
21659035 | 1390 | * being held. |
41c445ff JB |
1391 | **/ |
1392 | struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, | |
6622f5cd | 1393 | const u8 *macaddr, s16 vlan) |
41c445ff JB |
1394 | { |
1395 | struct i40e_mac_filter *f; | |
278e7d0b | 1396 | u64 key; |
41c445ff JB |
1397 | |
1398 | if (!vsi || !macaddr) | |
1399 | return NULL; | |
1400 | ||
1bc87e80 | 1401 | f = i40e_find_filter(vsi, macaddr, vlan); |
41c445ff JB |
1402 | if (!f) { |
1403 | f = kzalloc(sizeof(*f), GFP_ATOMIC); | |
1404 | if (!f) | |
1bc87e80 | 1405 | return NULL; |
41c445ff | 1406 | |
cbebb85f JK |
1407 | /* Update the boolean indicating if we need to function in |
1408 | * VLAN mode. | |
1409 | */ | |
1410 | if (vlan >= 0) | |
1411 | vsi->has_vlan_filter = true; | |
1412 | ||
9a173901 | 1413 | ether_addr_copy(f->macaddr, macaddr); |
41c445ff | 1414 | f->vlan = vlan; |
7363115e | 1415 | f->state = I40E_FILTER_NEW; |
278e7d0b JK |
1416 | INIT_HLIST_NODE(&f->hlist); |
1417 | ||
1418 | key = i40e_addr_to_hkey(macaddr); | |
1419 | hash_add(vsi->mac_filter_hash, &f->hlist, key); | |
41c445ff | 1420 | |
41c445ff | 1421 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; |
bfe040c3 | 1422 | set_bit(__I40E_MACVLAN_SYNC_PENDING, vsi->back->state); |
41c445ff JB |
1423 | } |
1424 | ||
1bc87e80 JK |
1425 | /* If we're asked to add a filter that has been marked for removal, it |
1426 | * is safe to simply restore it to active state. __i40e_del_filter | |
1427 | * will have simply deleted any filters which were previously marked | |
1428 | * NEW or FAILED, so if it is currently marked REMOVE it must have | |
1429 | * previously been ACTIVE. Since we haven't yet run the sync filters | |
1430 | * task, just restore this filter to the ACTIVE state so that the | |
1431 | * sync task leaves it in place | |
1432 | */ | |
1433 | if (f->state == I40E_FILTER_REMOVE) | |
1434 | f->state = I40E_FILTER_ACTIVE; | |
1435 | ||
41c445ff JB |
1436 | return f; |
1437 | } | |
1438 | ||
1439 | /** | |
290d2557 JK |
1440 | * __i40e_del_filter - Remove a specific filter from the VSI |
1441 | * @vsi: VSI to remove from | |
1442 | * @f: the filter to remove from the list | |
1443 | * | |
1444 | * This function should be called instead of i40e_del_filter only if you know | |
1445 | * the exact filter you will remove already, such as via i40e_find_filter or | |
1446 | * i40e_find_mac. | |
21659035 | 1447 | * |
278e7d0b | 1448 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
21659035 | 1449 | * being held. |
c3c7ea27 MW |
1450 | * ANOTHER NOTE: This function MUST be called from within the context of |
1451 | * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe() | |
1452 | * instead of list_for_each_entry(). | |
41c445ff | 1453 | **/ |
148141bb | 1454 | void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f) |
41c445ff | 1455 | { |
1bc87e80 | 1456 | if (!f) |
41c445ff JB |
1457 | return; |
1458 | ||
a410c821 AB |
1459 | /* If the filter was never added to firmware then we can just delete it |
1460 | * directly and we don't want to set the status to remove or else an | |
1461 | * admin queue command will unnecessarily fire. | |
1462 | */ | |
1bc87e80 JK |
1463 | if ((f->state == I40E_FILTER_FAILED) || |
1464 | (f->state == I40E_FILTER_NEW)) { | |
278e7d0b | 1465 | hash_del(&f->hlist); |
1bc87e80 | 1466 | kfree(f); |
41c445ff | 1467 | } else { |
1bc87e80 | 1468 | f->state = I40E_FILTER_REMOVE; |
41c445ff | 1469 | } |
a410c821 AB |
1470 | |
1471 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
eab077aa | 1472 | set_bit(__I40E_MACVLAN_SYNC_PENDING, vsi->back->state); |
41c445ff JB |
1473 | } |
1474 | ||
290d2557 JK |
1475 | /** |
1476 | * i40e_del_filter - Remove a MAC/VLAN filter from the VSI | |
1477 | * @vsi: the VSI to be searched | |
1478 | * @macaddr: the MAC address | |
1479 | * @vlan: the VLAN | |
1480 | * | |
278e7d0b | 1481 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
290d2557 JK |
1482 | * being held. |
1483 | * ANOTHER NOTE: This function MUST be called from within the context of | |
1484 | * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe() | |
1485 | * instead of list_for_each_entry(). | |
1486 | **/ | |
1487 | void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan) | |
1488 | { | |
1489 | struct i40e_mac_filter *f; | |
1490 | ||
1491 | if (!vsi || !macaddr) | |
1492 | return; | |
1493 | ||
1494 | f = i40e_find_filter(vsi, macaddr, vlan); | |
1495 | __i40e_del_filter(vsi, f); | |
1496 | } | |
1497 | ||
35ec2ff3 | 1498 | /** |
feffdbe4 | 1499 | * i40e_add_mac_filter - Add a MAC filter for all active VLANs |
35ec2ff3 JK |
1500 | * @vsi: the VSI to be searched |
1501 | * @macaddr: the mac address to be filtered | |
1502 | * | |
feffdbe4 JK |
1503 | * If we're not in VLAN mode, just add the filter to I40E_VLAN_ANY. Otherwise, |
1504 | * go through all the macvlan filters and add a macvlan filter for each | |
5feb3d7b JK |
1505 | * unique vlan that already exists. If a PVID has been assigned, instead only |
1506 | * add the macaddr to that VLAN. | |
35ec2ff3 | 1507 | * |
5feb3d7b | 1508 | * Returns last filter added on success, else NULL |
35ec2ff3 | 1509 | **/ |
feffdbe4 JK |
1510 | struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, |
1511 | const u8 *macaddr) | |
35ec2ff3 | 1512 | { |
5feb3d7b | 1513 | struct i40e_mac_filter *f, *add = NULL; |
278e7d0b JK |
1514 | struct hlist_node *h; |
1515 | int bkt; | |
5feb3d7b JK |
1516 | |
1517 | if (vsi->info.pvid) | |
1518 | return i40e_add_filter(vsi, macaddr, | |
1519 | le16_to_cpu(vsi->info.pvid)); | |
35ec2ff3 | 1520 | |
7aaf9536 JK |
1521 | if (!i40e_is_vsi_in_vlan(vsi)) |
1522 | return i40e_add_filter(vsi, macaddr, I40E_VLAN_ANY); | |
1523 | ||
278e7d0b | 1524 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
57b341d6 JK |
1525 | if (f->state == I40E_FILTER_REMOVE) |
1526 | continue; | |
5feb3d7b JK |
1527 | add = i40e_add_filter(vsi, macaddr, f->vlan); |
1528 | if (!add) | |
1529 | return NULL; | |
35ec2ff3 JK |
1530 | } |
1531 | ||
5feb3d7b | 1532 | return add; |
35ec2ff3 JK |
1533 | } |
1534 | ||
1535 | /** | |
feffdbe4 | 1536 | * i40e_del_mac_filter - Remove a MAC filter from all VLANs |
35ec2ff3 JK |
1537 | * @vsi: the VSI to be searched |
1538 | * @macaddr: the mac address to be removed | |
1539 | * | |
feffdbe4 JK |
1540 | * Removes a given MAC address from a VSI regardless of what VLAN it has been |
1541 | * associated with. | |
35ec2ff3 JK |
1542 | * |
1543 | * Returns 0 for success, or error | |
1544 | **/ | |
feffdbe4 | 1545 | int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr) |
35ec2ff3 | 1546 | { |
278e7d0b JK |
1547 | struct i40e_mac_filter *f; |
1548 | struct hlist_node *h; | |
290d2557 | 1549 | bool found = false; |
278e7d0b | 1550 | int bkt; |
35ec2ff3 | 1551 | |
6a9a5ec1 | 1552 | lockdep_assert_held(&vsi->mac_filter_hash_lock); |
278e7d0b | 1553 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
290d2557 JK |
1554 | if (ether_addr_equal(macaddr, f->macaddr)) { |
1555 | __i40e_del_filter(vsi, f); | |
1556 | found = true; | |
1557 | } | |
35ec2ff3 | 1558 | } |
290d2557 JK |
1559 | |
1560 | if (found) | |
35ec2ff3 | 1561 | return 0; |
290d2557 JK |
1562 | else |
1563 | return -ENOENT; | |
35ec2ff3 JK |
1564 | } |
1565 | ||
41c445ff JB |
1566 | /** |
1567 | * i40e_set_mac - NDO callback to set mac address | |
1568 | * @netdev: network interface device structure | |
1569 | * @p: pointer to an address structure | |
1570 | * | |
1571 | * Returns 0 on success, negative on failure | |
1572 | **/ | |
1573 | static int i40e_set_mac(struct net_device *netdev, void *p) | |
1574 | { | |
1575 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1576 | struct i40e_vsi *vsi = np->vsi; | |
30650cc5 SN |
1577 | struct i40e_pf *pf = vsi->back; |
1578 | struct i40e_hw *hw = &pf->hw; | |
41c445ff | 1579 | struct sockaddr *addr = p; |
41c445ff JB |
1580 | |
1581 | if (!is_valid_ether_addr(addr->sa_data)) | |
1582 | return -EADDRNOTAVAIL; | |
1583 | ||
30650cc5 SN |
1584 | if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) { |
1585 | netdev_info(netdev, "already using mac address %pM\n", | |
1586 | addr->sa_data); | |
1587 | return 0; | |
1588 | } | |
41c445ff | 1589 | |
e7bac7af PM |
1590 | if (test_bit(__I40E_DOWN, pf->state) || |
1591 | test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) | |
80f6428f ASJ |
1592 | return -EADDRNOTAVAIL; |
1593 | ||
30650cc5 SN |
1594 | if (ether_addr_equal(hw->mac.addr, addr->sa_data)) |
1595 | netdev_info(netdev, "returning to hw mac address %pM\n", | |
1596 | hw->mac.addr); | |
1597 | else | |
1598 | netdev_info(netdev, "set new mac address %pM\n", addr->sa_data); | |
1599 | ||
458867b2 | 1600 | /* Copy the address first, so that we avoid a possible race with |
158daed1 SA |
1601 | * .set_rx_mode(). |
1602 | * - Remove old address from MAC filter | |
1603 | * - Copy new address | |
1604 | * - Add new address to MAC filter | |
458867b2 | 1605 | */ |
278e7d0b | 1606 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
feffdbe4 | 1607 | i40e_del_mac_filter(vsi, netdev->dev_addr); |
f3956ebb | 1608 | eth_hw_addr_set(netdev, addr->sa_data); |
158daed1 | 1609 | i40e_add_mac_filter(vsi, netdev->dev_addr); |
278e7d0b | 1610 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
158daed1 | 1611 | |
41c445ff JB |
1612 | if (vsi->type == I40E_VSI_MAIN) { |
1613 | i40e_status ret; | |
6995b36c | 1614 | |
e7bac7af | 1615 | ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL, |
41c445ff | 1616 | addr->sa_data, NULL); |
c3c7ea27 MW |
1617 | if (ret) |
1618 | netdev_info(netdev, "Ignoring error from firmware on LAA update, status %s, AQ ret %s\n", | |
1619 | i40e_stat_str(hw, ret), | |
1620 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
30650cc5 SN |
1621 | } |
1622 | ||
c53934c6 JB |
1623 | /* schedule our worker thread which will take care of |
1624 | * applying the new filter changes | |
1625 | */ | |
e7bac7af | 1626 | i40e_service_event_schedule(pf); |
c53934c6 | 1627 | return 0; |
41c445ff JB |
1628 | } |
1629 | ||
a9ce82f7 AN |
1630 | /** |
1631 | * i40e_config_rss_aq - Prepare for RSS using AQ commands | |
1632 | * @vsi: vsi structure | |
1633 | * @seed: RSS hash seed | |
b50f7bca JB |
1634 | * @lut: pointer to lookup table of lut_size |
1635 | * @lut_size: size of the lookup table | |
a9ce82f7 AN |
1636 | **/ |
1637 | static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed, | |
1638 | u8 *lut, u16 lut_size) | |
1639 | { | |
1640 | struct i40e_pf *pf = vsi->back; | |
1641 | struct i40e_hw *hw = &pf->hw; | |
1642 | int ret = 0; | |
1643 | ||
1644 | if (seed) { | |
1645 | struct i40e_aqc_get_set_rss_key_data *seed_dw = | |
1646 | (struct i40e_aqc_get_set_rss_key_data *)seed; | |
1647 | ret = i40e_aq_set_rss_key(hw, vsi->id, seed_dw); | |
1648 | if (ret) { | |
1649 | dev_info(&pf->pdev->dev, | |
1650 | "Cannot set RSS key, err %s aq_err %s\n", | |
1651 | i40e_stat_str(hw, ret), | |
1652 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
1653 | return ret; | |
1654 | } | |
1655 | } | |
1656 | if (lut) { | |
7ff4f063 | 1657 | bool pf_lut = vsi->type == I40E_VSI_MAIN; |
a9ce82f7 AN |
1658 | |
1659 | ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, lut, lut_size); | |
1660 | if (ret) { | |
1661 | dev_info(&pf->pdev->dev, | |
1662 | "Cannot set RSS lut, err %s aq_err %s\n", | |
1663 | i40e_stat_str(hw, ret), | |
1664 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
1665 | return ret; | |
1666 | } | |
1667 | } | |
1668 | return ret; | |
1669 | } | |
1670 | ||
1671 | /** | |
1672 | * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used | |
1673 | * @vsi: VSI structure | |
1674 | **/ | |
1675 | static int i40e_vsi_config_rss(struct i40e_vsi *vsi) | |
1676 | { | |
1677 | struct i40e_pf *pf = vsi->back; | |
1678 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
1679 | u8 *lut; | |
1680 | int ret; | |
1681 | ||
1682 | if (!(pf->hw_features & I40E_HW_RSS_AQ_CAPABLE)) | |
1683 | return 0; | |
1684 | if (!vsi->rss_size) | |
1685 | vsi->rss_size = min_t(int, pf->alloc_rss_size, | |
1686 | vsi->num_queue_pairs); | |
1687 | if (!vsi->rss_size) | |
1688 | return -EINVAL; | |
1689 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); | |
1690 | if (!lut) | |
1691 | return -ENOMEM; | |
1692 | ||
1693 | /* Use the user configured hash keys and lookup table if there is one, | |
1694 | * otherwise use default | |
1695 | */ | |
1696 | if (vsi->rss_lut_user) | |
1697 | memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size); | |
1698 | else | |
1699 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); | |
1700 | if (vsi->rss_hkey_user) | |
1701 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
1702 | else | |
1703 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
1704 | ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size); | |
1705 | kfree(lut); | |
1706 | return ret; | |
1707 | } | |
1708 | ||
1709 | /** | |
1710 | * i40e_vsi_setup_queue_map_mqprio - Prepares mqprio based tc_config | |
1711 | * @vsi: the VSI being configured, | |
1712 | * @ctxt: VSI context structure | |
1713 | * @enabled_tc: number of traffic classes to enable | |
1714 | * | |
1715 | * Prepares VSI tc_config to have queue configurations based on MQPRIO options. | |
1716 | **/ | |
1717 | static int i40e_vsi_setup_queue_map_mqprio(struct i40e_vsi *vsi, | |
1718 | struct i40e_vsi_context *ctxt, | |
1719 | u8 enabled_tc) | |
1720 | { | |
1721 | u16 qcount = 0, max_qcount, qmap, sections = 0; | |
1722 | int i, override_q, pow, num_qps, ret; | |
1723 | u8 netdev_tc = 0, offset = 0; | |
1724 | ||
1725 | if (vsi->type != I40E_VSI_MAIN) | |
1726 | return -EINVAL; | |
1727 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
1728 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
1729 | vsi->tc_config.numtc = vsi->mqprio_qopt.qopt.num_tc; | |
1730 | vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1; | |
1731 | num_qps = vsi->mqprio_qopt.qopt.count[0]; | |
1732 | ||
1733 | /* find the next higher power-of-2 of num queue pairs */ | |
1734 | pow = ilog2(num_qps); | |
1735 | if (!is_power_of_2(num_qps)) | |
1736 | pow++; | |
1737 | qmap = (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
1738 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
1739 | ||
1740 | /* Setup queue offset/count for all TCs for given VSI */ | |
1741 | max_qcount = vsi->mqprio_qopt.qopt.count[0]; | |
1742 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
1743 | /* See if the given TC is enabled for the given VSI */ | |
1744 | if (vsi->tc_config.enabled_tc & BIT(i)) { | |
1745 | offset = vsi->mqprio_qopt.qopt.offset[i]; | |
1746 | qcount = vsi->mqprio_qopt.qopt.count[i]; | |
1747 | if (qcount > max_qcount) | |
1748 | max_qcount = qcount; | |
1749 | vsi->tc_config.tc_info[i].qoffset = offset; | |
1750 | vsi->tc_config.tc_info[i].qcount = qcount; | |
1751 | vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++; | |
1752 | } else { | |
1753 | /* TC is not enabled so set the offset to | |
1754 | * default queue and allocate one queue | |
1755 | * for the given TC. | |
1756 | */ | |
1757 | vsi->tc_config.tc_info[i].qoffset = 0; | |
1758 | vsi->tc_config.tc_info[i].qcount = 1; | |
1759 | vsi->tc_config.tc_info[i].netdev_tc = 0; | |
1760 | } | |
1761 | } | |
1762 | ||
1763 | /* Set actual Tx/Rx queue pairs */ | |
1764 | vsi->num_queue_pairs = offset + qcount; | |
1765 | ||
1766 | /* Setup queue TC[0].qmap for given VSI context */ | |
1767 | ctxt->info.tc_mapping[0] = cpu_to_le16(qmap); | |
1768 | ctxt->info.mapping_flags |= cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
1769 | ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue); | |
1770 | ctxt->info.valid_sections |= cpu_to_le16(sections); | |
1771 | ||
1772 | /* Reconfigure RSS for main VSI with max queue count */ | |
1773 | vsi->rss_size = max_qcount; | |
1774 | ret = i40e_vsi_config_rss(vsi); | |
1775 | if (ret) { | |
1776 | dev_info(&vsi->back->pdev->dev, | |
1777 | "Failed to reconfig rss for num_queues (%u)\n", | |
1778 | max_qcount); | |
1779 | return ret; | |
1780 | } | |
1781 | vsi->reconfig_rss = true; | |
1782 | dev_dbg(&vsi->back->pdev->dev, | |
1783 | "Reconfigured rss with num_queues (%u)\n", max_qcount); | |
1784 | ||
1785 | /* Find queue count available for channel VSIs and starting offset | |
1786 | * for channel VSIs | |
1787 | */ | |
1788 | override_q = vsi->mqprio_qopt.qopt.count[0]; | |
1789 | if (override_q && override_q < vsi->num_queue_pairs) { | |
1790 | vsi->cnt_q_avail = vsi->num_queue_pairs - override_q; | |
1791 | vsi->next_base_queue = override_q; | |
1792 | } | |
1793 | return 0; | |
1794 | } | |
1795 | ||
41c445ff JB |
1796 | /** |
1797 | * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc | |
1798 | * @vsi: the VSI being setup | |
1799 | * @ctxt: VSI context structure | |
1800 | * @enabled_tc: Enabled TCs bitmap | |
1801 | * @is_add: True if called before Add VSI | |
1802 | * | |
1803 | * Setup VSI queue mapping for enabled traffic classes. | |
1804 | **/ | |
1805 | static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi, | |
1806 | struct i40e_vsi_context *ctxt, | |
1807 | u8 enabled_tc, | |
1808 | bool is_add) | |
1809 | { | |
1810 | struct i40e_pf *pf = vsi->back; | |
d2a69fef | 1811 | u16 num_tc_qps = 0; |
41c445ff JB |
1812 | u16 sections = 0; |
1813 | u8 netdev_tc = 0; | |
bc6d33c8 | 1814 | u16 numtc = 1; |
41c445ff JB |
1815 | u16 qcount; |
1816 | u8 offset; | |
1817 | u16 qmap; | |
1818 | int i; | |
1819 | ||
1820 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
1821 | offset = 0; | |
9e0a603c ER |
1822 | /* zero out queue mapping, it will get updated on the end of the function */ |
1823 | memset(ctxt->info.queue_mapping, 0, sizeof(ctxt->info.queue_mapping)); | |
41c445ff | 1824 | |
d2a69fef ER |
1825 | if (vsi->type == I40E_VSI_MAIN) { |
1826 | /* This code helps add more queue to the VSI if we have | |
1827 | * more cores than RSS can support, the higher cores will | |
1828 | * be served by ATR or other filters. Furthermore, the | |
1829 | * non-zero req_queue_pairs says that user requested a new | |
1830 | * queue count via ethtool's set_channels, so use this | |
1831 | * value for queues distribution across traffic classes | |
1832 | */ | |
1833 | if (vsi->req_queue_pairs > 0) | |
1834 | vsi->num_queue_pairs = vsi->req_queue_pairs; | |
1835 | else if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
1836 | vsi->num_queue_pairs = pf->num_lan_msix; | |
1837 | } | |
1838 | ||
bc6d33c8 | 1839 | /* Number of queues per enabled TC */ |
9e0a603c ER |
1840 | if (vsi->type == I40E_VSI_MAIN || |
1841 | (vsi->type == I40E_VSI_SRIOV && vsi->num_queue_pairs != 0)) | |
d2a69fef ER |
1842 | num_tc_qps = vsi->num_queue_pairs; |
1843 | else | |
1844 | num_tc_qps = vsi->alloc_queue_pairs; | |
9e0a603c | 1845 | |
41c445ff JB |
1846 | if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { |
1847 | /* Find numtc from enabled TC bitmap */ | |
bc6d33c8 | 1848 | for (i = 0, numtc = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
75f5cea9 | 1849 | if (enabled_tc & BIT(i)) /* TC is enabled */ |
41c445ff JB |
1850 | numtc++; |
1851 | } | |
1852 | if (!numtc) { | |
1853 | dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n"); | |
1854 | numtc = 1; | |
1855 | } | |
bc6d33c8 AN |
1856 | num_tc_qps = num_tc_qps / numtc; |
1857 | num_tc_qps = min_t(int, num_tc_qps, | |
1858 | i40e_pf_get_max_q_per_tc(pf)); | |
41c445ff JB |
1859 | } |
1860 | ||
1861 | vsi->tc_config.numtc = numtc; | |
1862 | vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1; | |
1863 | ||
1563f2d2 PJ |
1864 | /* Do not allow use more TC queue pairs than MSI-X vectors exist */ |
1865 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
1866 | num_tc_qps = min_t(int, num_tc_qps, pf->num_lan_msix); | |
1867 | ||
41c445ff JB |
1868 | /* Setup queue offset/count for all TCs for given VSI */ |
1869 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
1870 | /* See if the given TC is enabled for the given VSI */ | |
75f5cea9 | 1871 | if (vsi->tc_config.enabled_tc & BIT(i)) { |
41a1d04b | 1872 | /* TC is enabled */ |
41c445ff JB |
1873 | int pow, num_qps; |
1874 | ||
41c445ff JB |
1875 | switch (vsi->type) { |
1876 | case I40E_VSI_MAIN: | |
bc6d33c8 AN |
1877 | if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | |
1878 | I40E_FLAG_FD_ATR_ENABLED)) || | |
1879 | vsi->tc_config.enabled_tc != 1) { | |
1880 | qcount = min_t(int, pf->alloc_rss_size, | |
1881 | num_tc_qps); | |
1882 | break; | |
1883 | } | |
5463fce6 | 1884 | fallthrough; |
41c445ff JB |
1885 | case I40E_VSI_FDIR: |
1886 | case I40E_VSI_SRIOV: | |
1887 | case I40E_VSI_VMDQ2: | |
1888 | default: | |
4e3b35b0 | 1889 | qcount = num_tc_qps; |
41c445ff JB |
1890 | WARN_ON(i != 0); |
1891 | break; | |
1892 | } | |
4e3b35b0 NP |
1893 | vsi->tc_config.tc_info[i].qoffset = offset; |
1894 | vsi->tc_config.tc_info[i].qcount = qcount; | |
41c445ff | 1895 | |
1e200e4a | 1896 | /* find the next higher power-of-2 of num queue pairs */ |
4e3b35b0 | 1897 | num_qps = qcount; |
41c445ff | 1898 | pow = 0; |
41a1d04b | 1899 | while (num_qps && (BIT_ULL(pow) < qcount)) { |
41c445ff JB |
1900 | pow++; |
1901 | num_qps >>= 1; | |
1902 | } | |
1903 | ||
1904 | vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++; | |
1905 | qmap = | |
1906 | (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
1907 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
1908 | ||
4e3b35b0 | 1909 | offset += qcount; |
41c445ff JB |
1910 | } else { |
1911 | /* TC is not enabled so set the offset to | |
1912 | * default queue and allocate one queue | |
1913 | * for the given TC. | |
1914 | */ | |
1915 | vsi->tc_config.tc_info[i].qoffset = 0; | |
1916 | vsi->tc_config.tc_info[i].qcount = 1; | |
1917 | vsi->tc_config.tc_info[i].netdev_tc = 0; | |
1918 | ||
1919 | qmap = 0; | |
1920 | } | |
1921 | ctxt->info.tc_mapping[i] = cpu_to_le16(qmap); | |
1922 | } | |
9e0a603c | 1923 | /* Do not change previously set num_queue_pairs for PFs and VFs*/ |
d2a69fef | 1924 | if ((vsi->type == I40E_VSI_MAIN && numtc != 1) || |
9e0a603c ER |
1925 | (vsi->type == I40E_VSI_SRIOV && vsi->num_queue_pairs == 0) || |
1926 | (vsi->type != I40E_VSI_MAIN && vsi->type != I40E_VSI_SRIOV)) | |
d2a69fef | 1927 | vsi->num_queue_pairs = offset; |
9e0a603c | 1928 | |
41c445ff JB |
1929 | /* Scheduler section valid can only be set for ADD VSI */ |
1930 | if (is_add) { | |
1931 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
1932 | ||
1933 | ctxt->info.up_enable_bits = enabled_tc; | |
1934 | } | |
1935 | if (vsi->type == I40E_VSI_SRIOV) { | |
1936 | ctxt->info.mapping_flags |= | |
1937 | cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); | |
1938 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
1939 | ctxt->info.queue_mapping[i] = | |
1940 | cpu_to_le16(vsi->base_queue + i); | |
1941 | } else { | |
1942 | ctxt->info.mapping_flags |= | |
1943 | cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
1944 | ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue); | |
1945 | } | |
1946 | ctxt->info.valid_sections |= cpu_to_le16(sections); | |
1947 | } | |
1948 | ||
6622f5cd JK |
1949 | /** |
1950 | * i40e_addr_sync - Callback for dev_(mc|uc)_sync to add address | |
1951 | * @netdev: the netdevice | |
1952 | * @addr: address to add | |
1953 | * | |
1954 | * Called by __dev_(mc|uc)_sync when an address needs to be added. We call | |
1955 | * __dev_(uc|mc)_sync from .set_rx_mode and guarantee to hold the hash lock. | |
1956 | */ | |
1957 | static int i40e_addr_sync(struct net_device *netdev, const u8 *addr) | |
1958 | { | |
1959 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1960 | struct i40e_vsi *vsi = np->vsi; | |
6622f5cd | 1961 | |
feffdbe4 | 1962 | if (i40e_add_mac_filter(vsi, addr)) |
6622f5cd JK |
1963 | return 0; |
1964 | else | |
1965 | return -ENOMEM; | |
1966 | } | |
1967 | ||
1968 | /** | |
1969 | * i40e_addr_unsync - Callback for dev_(mc|uc)_sync to remove address | |
1970 | * @netdev: the netdevice | |
1971 | * @addr: address to add | |
1972 | * | |
1973 | * Called by __dev_(mc|uc)_sync when an address needs to be removed. We call | |
1974 | * __dev_(uc|mc)_sync from .set_rx_mode and guarantee to hold the hash lock. | |
1975 | */ | |
1976 | static int i40e_addr_unsync(struct net_device *netdev, const u8 *addr) | |
1977 | { | |
1978 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1979 | struct i40e_vsi *vsi = np->vsi; | |
1980 | ||
458867b2 JK |
1981 | /* Under some circumstances, we might receive a request to delete |
1982 | * our own device address from our uc list. Because we store the | |
1983 | * device address in the VSI's MAC/VLAN filter list, we need to ignore | |
1984 | * such requests and not delete our device address from this list. | |
1985 | */ | |
1986 | if (ether_addr_equal(addr, netdev->dev_addr)) | |
1987 | return 0; | |
1988 | ||
feffdbe4 | 1989 | i40e_del_mac_filter(vsi, addr); |
6622f5cd JK |
1990 | |
1991 | return 0; | |
1992 | } | |
1993 | ||
41c445ff JB |
1994 | /** |
1995 | * i40e_set_rx_mode - NDO callback to set the netdev filters | |
1996 | * @netdev: network interface device structure | |
1997 | **/ | |
1998 | static void i40e_set_rx_mode(struct net_device *netdev) | |
1999 | { | |
2000 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
41c445ff | 2001 | struct i40e_vsi *vsi = np->vsi; |
41c445ff | 2002 | |
278e7d0b | 2003 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 2004 | |
6622f5cd JK |
2005 | __dev_uc_sync(netdev, i40e_addr_sync, i40e_addr_unsync); |
2006 | __dev_mc_sync(netdev, i40e_addr_sync, i40e_addr_unsync); | |
41c445ff | 2007 | |
278e7d0b | 2008 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
2009 | |
2010 | /* check for other flag changes */ | |
2011 | if (vsi->current_netdev_flags != vsi->netdev->flags) { | |
2012 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
bfe040c3 | 2013 | set_bit(__I40E_MACVLAN_SYNC_PENDING, vsi->back->state); |
41c445ff JB |
2014 | } |
2015 | } | |
2016 | ||
21659035 | 2017 | /** |
671889e6 | 2018 | * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries |
4a2ce27b | 2019 | * @vsi: Pointer to VSI struct |
21659035 KP |
2020 | * @from: Pointer to list which contains MAC filter entries - changes to |
2021 | * those entries needs to be undone. | |
2022 | * | |
671889e6 | 2023 | * MAC filter entries from this list were slated for deletion. |
21659035 | 2024 | **/ |
671889e6 JK |
2025 | static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi, |
2026 | struct hlist_head *from) | |
21659035 | 2027 | { |
278e7d0b JK |
2028 | struct i40e_mac_filter *f; |
2029 | struct hlist_node *h; | |
2030 | ||
2031 | hlist_for_each_entry_safe(f, h, from, hlist) { | |
2032 | u64 key = i40e_addr_to_hkey(f->macaddr); | |
21659035 | 2033 | |
21659035 | 2034 | /* Move the element back into MAC filter list*/ |
278e7d0b JK |
2035 | hlist_del(&f->hlist); |
2036 | hash_add(vsi->mac_filter_hash, &f->hlist, key); | |
21659035 KP |
2037 | } |
2038 | } | |
2039 | ||
671889e6 JK |
2040 | /** |
2041 | * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries | |
2042 | * @vsi: Pointer to vsi struct | |
2043 | * @from: Pointer to list which contains MAC filter entries - changes to | |
2044 | * those entries needs to be undone. | |
2045 | * | |
2046 | * MAC filter entries from this list were slated for addition. | |
2047 | **/ | |
2048 | static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi, | |
2049 | struct hlist_head *from) | |
2050 | { | |
2051 | struct i40e_new_mac_filter *new; | |
2052 | struct hlist_node *h; | |
2053 | ||
2054 | hlist_for_each_entry_safe(new, h, from, hlist) { | |
2055 | /* We can simply free the wrapper structure */ | |
2056 | hlist_del(&new->hlist); | |
3116f59c | 2057 | netdev_hw_addr_refcnt(new->f, vsi->netdev, -1); |
671889e6 JK |
2058 | kfree(new); |
2059 | } | |
2060 | } | |
2061 | ||
d88d40b0 | 2062 | /** |
262de08f | 2063 | * i40e_next_filter - Get the next non-broadcast filter from a list |
671889e6 | 2064 | * @next: pointer to filter in list |
d88d40b0 JK |
2065 | * |
2066 | * Returns the next non-broadcast filter in the list. Required so that we | |
2067 | * ignore broadcast filters within the list, since these are not handled via | |
2068 | * the normal firmware update path. | |
2069 | */ | |
671889e6 JK |
2070 | static |
2071 | struct i40e_new_mac_filter *i40e_next_filter(struct i40e_new_mac_filter *next) | |
d88d40b0 | 2072 | { |
584a8870 JK |
2073 | hlist_for_each_entry_continue(next, hlist) { |
2074 | if (!is_broadcast_ether_addr(next->f->macaddr)) | |
2075 | return next; | |
d88d40b0 JK |
2076 | } |
2077 | ||
584a8870 | 2078 | return NULL; |
d88d40b0 JK |
2079 | } |
2080 | ||
21659035 | 2081 | /** |
c3c7ea27 MW |
2082 | * i40e_update_filter_state - Update filter state based on return data |
2083 | * from firmware | |
2084 | * @count: Number of filters added | |
2085 | * @add_list: return data from fw | |
f5254429 | 2086 | * @add_head: pointer to first filter in current batch |
21659035 | 2087 | * |
c3c7ea27 MW |
2088 | * MAC filter entries from list were slated to be added to device. Returns |
2089 | * number of successful filters. Note that 0 does NOT mean success! | |
21659035 | 2090 | **/ |
c3c7ea27 MW |
2091 | static int |
2092 | i40e_update_filter_state(int count, | |
2093 | struct i40e_aqc_add_macvlan_element_data *add_list, | |
671889e6 | 2094 | struct i40e_new_mac_filter *add_head) |
21659035 | 2095 | { |
c3c7ea27 MW |
2096 | int retval = 0; |
2097 | int i; | |
21659035 | 2098 | |
ac9e2390 JK |
2099 | for (i = 0; i < count; i++) { |
2100 | /* Always check status of each filter. We don't need to check | |
2101 | * the firmware return status because we pre-set the filter | |
2102 | * status to I40E_AQC_MM_ERR_NO_RES when sending the filter | |
2103 | * request to the adminq. Thus, if it no longer matches then | |
2104 | * we know the filter is active. | |
c3c7ea27 | 2105 | */ |
ac9e2390 | 2106 | if (add_list[i].match_method == I40E_AQC_MM_ERR_NO_RES) { |
c3c7ea27 | 2107 | add_head->state = I40E_FILTER_FAILED; |
ac9e2390 JK |
2108 | } else { |
2109 | add_head->state = I40E_FILTER_ACTIVE; | |
2110 | retval++; | |
c3c7ea27 | 2111 | } |
ac9e2390 | 2112 | |
d88d40b0 JK |
2113 | add_head = i40e_next_filter(add_head); |
2114 | if (!add_head) | |
2115 | break; | |
21659035 | 2116 | } |
ac9e2390 | 2117 | |
c3c7ea27 | 2118 | return retval; |
21659035 KP |
2119 | } |
2120 | ||
00936319 JK |
2121 | /** |
2122 | * i40e_aqc_del_filters - Request firmware to delete a set of filters | |
2123 | * @vsi: ptr to the VSI | |
2124 | * @vsi_name: name to display in messages | |
2125 | * @list: the list of filters to send to firmware | |
2126 | * @num_del: the number of filters to delete | |
2127 | * @retval: Set to -EIO on failure to delete | |
2128 | * | |
2129 | * Send a request to firmware via AdminQ to delete a set of filters. Uses | |
2130 | * *retval instead of a return value so that success does not force ret_val to | |
2131 | * be set to 0. This ensures that a sequence of calls to this function | |
2132 | * preserve the previous value of *retval on successful delete. | |
2133 | */ | |
2134 | static | |
2135 | void i40e_aqc_del_filters(struct i40e_vsi *vsi, const char *vsi_name, | |
2136 | struct i40e_aqc_remove_macvlan_element_data *list, | |
2137 | int num_del, int *retval) | |
2138 | { | |
2139 | struct i40e_hw *hw = &vsi->back->hw; | |
2140 | i40e_status aq_ret; | |
2141 | int aq_err; | |
2142 | ||
2143 | aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, list, num_del, NULL); | |
2144 | aq_err = hw->aq.asq_last_status; | |
2145 | ||
2146 | /* Explicitly ignore and do not report when firmware returns ENOENT */ | |
2147 | if (aq_ret && !(aq_err == I40E_AQ_RC_ENOENT)) { | |
2148 | *retval = -EIO; | |
2149 | dev_info(&vsi->back->pdev->dev, | |
2150 | "ignoring delete macvlan error on %s, err %s, aq_err %s\n", | |
2151 | vsi_name, i40e_stat_str(hw, aq_ret), | |
2152 | i40e_aq_str(hw, aq_err)); | |
2153 | } | |
2154 | } | |
2155 | ||
2156 | /** | |
2157 | * i40e_aqc_add_filters - Request firmware to add a set of filters | |
2158 | * @vsi: ptr to the VSI | |
2159 | * @vsi_name: name to display in messages | |
2160 | * @list: the list of filters to send to firmware | |
2161 | * @add_head: Position in the add hlist | |
2162 | * @num_add: the number of filters to add | |
00936319 JK |
2163 | * |
2164 | * Send a request to firmware via AdminQ to add a chunk of filters. Will set | |
cc6a96a4 AB |
2165 | * __I40E_VSI_OVERFLOW_PROMISC bit in vsi->state if the firmware has run out of |
2166 | * space for more filters. | |
00936319 JK |
2167 | */ |
2168 | static | |
2169 | void i40e_aqc_add_filters(struct i40e_vsi *vsi, const char *vsi_name, | |
2170 | struct i40e_aqc_add_macvlan_element_data *list, | |
671889e6 | 2171 | struct i40e_new_mac_filter *add_head, |
cc6a96a4 | 2172 | int num_add) |
00936319 JK |
2173 | { |
2174 | struct i40e_hw *hw = &vsi->back->hw; | |
00936319 JK |
2175 | int aq_err, fcnt; |
2176 | ||
ac9e2390 | 2177 | i40e_aq_add_macvlan(hw, vsi->seid, list, num_add, NULL); |
00936319 | 2178 | aq_err = hw->aq.asq_last_status; |
ac9e2390 | 2179 | fcnt = i40e_update_filter_state(num_add, list, add_head); |
00936319 JK |
2180 | |
2181 | if (fcnt != num_add) { | |
735aaafa GS |
2182 | if (vsi->type == I40E_VSI_MAIN) { |
2183 | set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); | |
2184 | dev_warn(&vsi->back->pdev->dev, | |
2185 | "Error %s adding RX filters on %s, promiscuous mode forced on\n", | |
2186 | i40e_aq_str(hw, aq_err), vsi_name); | |
2187 | } else if (vsi->type == I40E_VSI_SRIOV || | |
2188 | vsi->type == I40E_VSI_VMDQ1 || | |
2189 | vsi->type == I40E_VSI_VMDQ2) { | |
2190 | dev_warn(&vsi->back->pdev->dev, | |
2191 | "Error %s adding RX filters on %s, please set promiscuous on manually for %s\n", | |
2192 | i40e_aq_str(hw, aq_err), vsi_name, vsi_name); | |
2193 | } else { | |
2194 | dev_warn(&vsi->back->pdev->dev, | |
2195 | "Error %s adding RX filters on %s, incorrect VSI type: %i.\n", | |
2196 | i40e_aq_str(hw, aq_err), vsi_name, vsi->type); | |
2197 | } | |
00936319 JK |
2198 | } |
2199 | } | |
2200 | ||
435c084a JK |
2201 | /** |
2202 | * i40e_aqc_broadcast_filter - Set promiscuous broadcast flags | |
2203 | * @vsi: pointer to the VSI | |
f5254429 | 2204 | * @vsi_name: the VSI name |
435c084a JK |
2205 | * @f: filter data |
2206 | * | |
2207 | * This function sets or clears the promiscuous broadcast flags for VLAN | |
2208 | * filters in order to properly receive broadcast frames. Assumes that only | |
2209 | * broadcast filters are passed. | |
671889e6 JK |
2210 | * |
2211 | * Returns status indicating success or failure; | |
435c084a | 2212 | **/ |
671889e6 JK |
2213 | static i40e_status |
2214 | i40e_aqc_broadcast_filter(struct i40e_vsi *vsi, const char *vsi_name, | |
2215 | struct i40e_mac_filter *f) | |
435c084a JK |
2216 | { |
2217 | bool enable = f->state == I40E_FILTER_NEW; | |
2218 | struct i40e_hw *hw = &vsi->back->hw; | |
2219 | i40e_status aq_ret; | |
2220 | ||
2221 | if (f->vlan == I40E_VLAN_ANY) { | |
2222 | aq_ret = i40e_aq_set_vsi_broadcast(hw, | |
2223 | vsi->seid, | |
2224 | enable, | |
2225 | NULL); | |
2226 | } else { | |
2227 | aq_ret = i40e_aq_set_vsi_bc_promisc_on_vlan(hw, | |
2228 | vsi->seid, | |
2229 | enable, | |
2230 | f->vlan, | |
2231 | NULL); | |
2232 | } | |
2233 | ||
a48350c2 AB |
2234 | if (aq_ret) { |
2235 | set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); | |
435c084a | 2236 | dev_warn(&vsi->back->pdev->dev, |
a48350c2 | 2237 | "Error %s, forcing overflow promiscuous on %s\n", |
435c084a JK |
2238 | i40e_aq_str(hw, hw->aq.asq_last_status), |
2239 | vsi_name); | |
a48350c2 | 2240 | } |
671889e6 JK |
2241 | |
2242 | return aq_ret; | |
435c084a JK |
2243 | } |
2244 | ||
bd5608b3 AB |
2245 | /** |
2246 | * i40e_set_promiscuous - set promiscuous mode | |
2247 | * @pf: board private structure | |
2248 | * @promisc: promisc on or off | |
2249 | * | |
2250 | * There are different ways of setting promiscuous mode on a PF depending on | |
2251 | * what state/environment we're in. This identifies and sets it appropriately. | |
2252 | * Returns 0 on success. | |
2253 | **/ | |
2254 | static int i40e_set_promiscuous(struct i40e_pf *pf, bool promisc) | |
2255 | { | |
2256 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
2257 | struct i40e_hw *hw = &pf->hw; | |
2258 | i40e_status aq_ret; | |
2259 | ||
2260 | if (vsi->type == I40E_VSI_MAIN && | |
2261 | pf->lan_veb != I40E_NO_VEB && | |
2262 | !(pf->flags & I40E_FLAG_MFP_ENABLED)) { | |
2263 | /* set defport ON for Main VSI instead of true promisc | |
2264 | * this way we will get all unicast/multicast and VLAN | |
2265 | * promisc behavior but will not get VF or VMDq traffic | |
2266 | * replicated on the Main VSI. | |
2267 | */ | |
2268 | if (promisc) | |
2269 | aq_ret = i40e_aq_set_default_vsi(hw, | |
2270 | vsi->seid, | |
2271 | NULL); | |
2272 | else | |
2273 | aq_ret = i40e_aq_clear_default_vsi(hw, | |
2274 | vsi->seid, | |
2275 | NULL); | |
2276 | if (aq_ret) { | |
2277 | dev_info(&pf->pdev->dev, | |
2278 | "Set default VSI failed, err %s, aq_err %s\n", | |
2279 | i40e_stat_str(hw, aq_ret), | |
2280 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
2281 | } | |
2282 | } else { | |
2283 | aq_ret = i40e_aq_set_vsi_unicast_promiscuous( | |
2284 | hw, | |
2285 | vsi->seid, | |
2286 | promisc, NULL, | |
2287 | true); | |
2288 | if (aq_ret) { | |
2289 | dev_info(&pf->pdev->dev, | |
2290 | "set unicast promisc failed, err %s, aq_err %s\n", | |
2291 | i40e_stat_str(hw, aq_ret), | |
2292 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
2293 | } | |
2294 | aq_ret = i40e_aq_set_vsi_multicast_promiscuous( | |
2295 | hw, | |
2296 | vsi->seid, | |
2297 | promisc, NULL); | |
2298 | if (aq_ret) { | |
2299 | dev_info(&pf->pdev->dev, | |
2300 | "set multicast promisc failed, err %s, aq_err %s\n", | |
2301 | i40e_stat_str(hw, aq_ret), | |
2302 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
2303 | } | |
2304 | } | |
2305 | ||
2306 | if (!aq_ret) | |
2307 | pf->cur_promisc = promisc; | |
2308 | ||
2309 | return aq_ret; | |
2310 | } | |
2311 | ||
41c445ff JB |
2312 | /** |
2313 | * i40e_sync_vsi_filters - Update the VSI filter list to the HW | |
2314 | * @vsi: ptr to the VSI | |
2315 | * | |
2316 | * Push any outstanding VSI filter changes through the AdminQ. | |
2317 | * | |
2318 | * Returns 0 or error value | |
2319 | **/ | |
17652c63 | 2320 | int i40e_sync_vsi_filters(struct i40e_vsi *vsi) |
41c445ff | 2321 | { |
278e7d0b | 2322 | struct hlist_head tmp_add_list, tmp_del_list; |
671889e6 JK |
2323 | struct i40e_mac_filter *f; |
2324 | struct i40e_new_mac_filter *new, *add_head = NULL; | |
3e25a8f3 | 2325 | struct i40e_hw *hw = &vsi->back->hw; |
cc6a96a4 | 2326 | bool old_overflow, new_overflow; |
38326218 | 2327 | unsigned int failed_filters = 0; |
84f5ca6c | 2328 | unsigned int vlan_filters = 0; |
2d1de828 | 2329 | char vsi_name[16] = "PF"; |
41c445ff | 2330 | int filter_list_len = 0; |
ea02e90b | 2331 | i40e_status aq_ret = 0; |
84f5ca6c | 2332 | u32 changed_flags = 0; |
278e7d0b | 2333 | struct hlist_node *h; |
41c445ff JB |
2334 | struct i40e_pf *pf; |
2335 | int num_add = 0; | |
2336 | int num_del = 0; | |
84f5ca6c | 2337 | int retval = 0; |
41c445ff | 2338 | u16 cmd_flags; |
c3c7ea27 | 2339 | int list_size; |
278e7d0b | 2340 | int bkt; |
41c445ff JB |
2341 | |
2342 | /* empty array typed pointers, kcalloc later */ | |
2343 | struct i40e_aqc_add_macvlan_element_data *add_list; | |
2344 | struct i40e_aqc_remove_macvlan_element_data *del_list; | |
2345 | ||
0da36b97 | 2346 | while (test_and_set_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state)) |
41c445ff JB |
2347 | usleep_range(1000, 2000); |
2348 | pf = vsi->back; | |
2349 | ||
cc6a96a4 AB |
2350 | old_overflow = test_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
2351 | ||
41c445ff JB |
2352 | if (vsi->netdev) { |
2353 | changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags; | |
2354 | vsi->current_netdev_flags = vsi->netdev->flags; | |
2355 | } | |
2356 | ||
278e7d0b JK |
2357 | INIT_HLIST_HEAD(&tmp_add_list); |
2358 | INIT_HLIST_HEAD(&tmp_del_list); | |
21659035 | 2359 | |
2d1de828 SN |
2360 | if (vsi->type == I40E_VSI_SRIOV) |
2361 | snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id); | |
2362 | else if (vsi->type != I40E_VSI_MAIN) | |
2363 | snprintf(vsi_name, sizeof(vsi_name) - 1, "vsi %d", vsi->seid); | |
2364 | ||
41c445ff JB |
2365 | if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) { |
2366 | vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED; | |
2367 | ||
278e7d0b | 2368 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
c3c7ea27 | 2369 | /* Create a list of filters to delete. */ |
278e7d0b | 2370 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
c3c7ea27 | 2371 | if (f->state == I40E_FILTER_REMOVE) { |
c3c7ea27 | 2372 | /* Move the element into temporary del_list */ |
278e7d0b JK |
2373 | hash_del(&f->hlist); |
2374 | hlist_add_head(&f->hlist, &tmp_del_list); | |
84f5ca6c AB |
2375 | |
2376 | /* Avoid counting removed filters */ | |
2377 | continue; | |
c3c7ea27 MW |
2378 | } |
2379 | if (f->state == I40E_FILTER_NEW) { | |
671889e6 JK |
2380 | /* Create a temporary i40e_new_mac_filter */ |
2381 | new = kzalloc(sizeof(*new), GFP_ATOMIC); | |
2382 | if (!new) | |
2383 | goto err_no_memory_locked; | |
2384 | ||
2385 | /* Store pointer to the real filter */ | |
2386 | new->f = f; | |
2387 | new->state = f->state; | |
2388 | ||
2389 | /* Add it to the hash list */ | |
2390 | hlist_add_head(&new->hlist, &tmp_add_list); | |
21659035 | 2391 | } |
84f5ca6c | 2392 | |
489a3265 JK |
2393 | /* Count the number of active (current and new) VLAN |
2394 | * filters we have now. Does not count filters which | |
2395 | * are marked for deletion. | |
84f5ca6c AB |
2396 | */ |
2397 | if (f->vlan > 0) | |
2398 | vlan_filters++; | |
84f5ca6c AB |
2399 | } |
2400 | ||
489a3265 JK |
2401 | retval = i40e_correct_mac_vlan_filters(vsi, |
2402 | &tmp_add_list, | |
2403 | &tmp_del_list, | |
2404 | vlan_filters); | |
3116f59c DZ |
2405 | |
2406 | hlist_for_each_entry(new, &tmp_add_list, hlist) | |
2407 | netdev_hw_addr_refcnt(new->f, vsi->netdev, 1); | |
2408 | ||
489a3265 JK |
2409 | if (retval) |
2410 | goto err_no_memory_locked; | |
84f5ca6c | 2411 | |
278e7d0b | 2412 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 KP |
2413 | } |
2414 | ||
2415 | /* Now process 'del_list' outside the lock */ | |
278e7d0b | 2416 | if (!hlist_empty(&tmp_del_list)) { |
3e25a8f3 | 2417 | filter_list_len = hw->aq.asq_buf_size / |
21659035 | 2418 | sizeof(struct i40e_aqc_remove_macvlan_element_data); |
c3c7ea27 | 2419 | list_size = filter_list_len * |
f1199998 | 2420 | sizeof(struct i40e_aqc_remove_macvlan_element_data); |
c3c7ea27 | 2421 | del_list = kzalloc(list_size, GFP_ATOMIC); |
4a2ce27b JK |
2422 | if (!del_list) |
2423 | goto err_no_memory; | |
21659035 | 2424 | |
278e7d0b | 2425 | hlist_for_each_entry_safe(f, h, &tmp_del_list, hlist) { |
41c445ff JB |
2426 | cmd_flags = 0; |
2427 | ||
435c084a | 2428 | /* handle broadcast filters by updating the broadcast |
d88d40b0 | 2429 | * promiscuous flag and release filter list. |
435c084a JK |
2430 | */ |
2431 | if (is_broadcast_ether_addr(f->macaddr)) { | |
2432 | i40e_aqc_broadcast_filter(vsi, vsi_name, f); | |
2433 | ||
2434 | hlist_del(&f->hlist); | |
2435 | kfree(f); | |
2436 | continue; | |
2437 | } | |
2438 | ||
41c445ff | 2439 | /* add to delete list */ |
9a173901 | 2440 | ether_addr_copy(del_list[num_del].mac_addr, f->macaddr); |
c3c7ea27 MW |
2441 | if (f->vlan == I40E_VLAN_ANY) { |
2442 | del_list[num_del].vlan_tag = 0; | |
a6cb9146 | 2443 | cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; |
c3c7ea27 MW |
2444 | } else { |
2445 | del_list[num_del].vlan_tag = | |
2446 | cpu_to_le16((u16)(f->vlan)); | |
2447 | } | |
41c445ff | 2448 | |
41c445ff JB |
2449 | cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; |
2450 | del_list[num_del].flags = cmd_flags; | |
2451 | num_del++; | |
2452 | ||
41c445ff JB |
2453 | /* flush a full buffer */ |
2454 | if (num_del == filter_list_len) { | |
00936319 JK |
2455 | i40e_aqc_del_filters(vsi, vsi_name, del_list, |
2456 | num_del, &retval); | |
c3c7ea27 | 2457 | memset(del_list, 0, list_size); |
00936319 | 2458 | num_del = 0; |
41c445ff | 2459 | } |
21659035 KP |
2460 | /* Release memory for MAC filter entries which were |
2461 | * synced up with HW. | |
2462 | */ | |
278e7d0b | 2463 | hlist_del(&f->hlist); |
21659035 | 2464 | kfree(f); |
41c445ff | 2465 | } |
21659035 | 2466 | |
41c445ff | 2467 | if (num_del) { |
00936319 JK |
2468 | i40e_aqc_del_filters(vsi, vsi_name, del_list, |
2469 | num_del, &retval); | |
41c445ff JB |
2470 | } |
2471 | ||
2472 | kfree(del_list); | |
2473 | del_list = NULL; | |
21659035 KP |
2474 | } |
2475 | ||
278e7d0b | 2476 | if (!hlist_empty(&tmp_add_list)) { |
c3c7ea27 | 2477 | /* Do all the adds now. */ |
3e25a8f3 | 2478 | filter_list_len = hw->aq.asq_buf_size / |
f1199998 | 2479 | sizeof(struct i40e_aqc_add_macvlan_element_data); |
c3c7ea27 MW |
2480 | list_size = filter_list_len * |
2481 | sizeof(struct i40e_aqc_add_macvlan_element_data); | |
2482 | add_list = kzalloc(list_size, GFP_ATOMIC); | |
4a2ce27b JK |
2483 | if (!add_list) |
2484 | goto err_no_memory; | |
2485 | ||
c3c7ea27 | 2486 | num_add = 0; |
671889e6 | 2487 | hlist_for_each_entry_safe(new, h, &tmp_add_list, hlist) { |
435c084a JK |
2488 | /* handle broadcast filters by updating the broadcast |
2489 | * promiscuous flag instead of adding a MAC filter. | |
2490 | */ | |
671889e6 JK |
2491 | if (is_broadcast_ether_addr(new->f->macaddr)) { |
2492 | if (i40e_aqc_broadcast_filter(vsi, vsi_name, | |
2493 | new->f)) | |
2494 | new->state = I40E_FILTER_FAILED; | |
2495 | else | |
2496 | new->state = I40E_FILTER_ACTIVE; | |
435c084a JK |
2497 | continue; |
2498 | } | |
2499 | ||
41c445ff | 2500 | /* add to add array */ |
c3c7ea27 | 2501 | if (num_add == 0) |
671889e6 | 2502 | add_head = new; |
c3c7ea27 | 2503 | cmd_flags = 0; |
671889e6 JK |
2504 | ether_addr_copy(add_list[num_add].mac_addr, |
2505 | new->f->macaddr); | |
2506 | if (new->f->vlan == I40E_VLAN_ANY) { | |
c3c7ea27 MW |
2507 | add_list[num_add].vlan_tag = 0; |
2508 | cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; | |
2509 | } else { | |
2510 | add_list[num_add].vlan_tag = | |
671889e6 | 2511 | cpu_to_le16((u16)(new->f->vlan)); |
c3c7ea27 | 2512 | } |
41c445ff | 2513 | add_list[num_add].queue_number = 0; |
ac9e2390 | 2514 | /* set invalid match method for later detection */ |
0266ac45 | 2515 | add_list[num_add].match_method = I40E_AQC_MM_ERR_NO_RES; |
41c445ff | 2516 | cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; |
41c445ff JB |
2517 | add_list[num_add].flags = cpu_to_le16(cmd_flags); |
2518 | num_add++; | |
2519 | ||
2520 | /* flush a full buffer */ | |
2521 | if (num_add == filter_list_len) { | |
00936319 | 2522 | i40e_aqc_add_filters(vsi, vsi_name, add_list, |
cc6a96a4 | 2523 | add_head, num_add); |
c3c7ea27 | 2524 | memset(add_list, 0, list_size); |
41c445ff | 2525 | num_add = 0; |
41c445ff JB |
2526 | } |
2527 | } | |
2528 | if (num_add) { | |
00936319 | 2529 | i40e_aqc_add_filters(vsi, vsi_name, add_list, add_head, |
cc6a96a4 | 2530 | num_add); |
41c445ff | 2531 | } |
c3c7ea27 MW |
2532 | /* Now move all of the filters from the temp add list back to |
2533 | * the VSI's list. | |
2534 | */ | |
278e7d0b | 2535 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
671889e6 JK |
2536 | hlist_for_each_entry_safe(new, h, &tmp_add_list, hlist) { |
2537 | /* Only update the state if we're still NEW */ | |
2538 | if (new->f->state == I40E_FILTER_NEW) | |
2539 | new->f->state = new->state; | |
2540 | hlist_del(&new->hlist); | |
3116f59c | 2541 | netdev_hw_addr_refcnt(new->f, vsi->netdev, -1); |
671889e6 | 2542 | kfree(new); |
c3c7ea27 | 2543 | } |
278e7d0b | 2544 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
2545 | kfree(add_list); |
2546 | add_list = NULL; | |
c3c7ea27 | 2547 | } |
41c445ff | 2548 | |
38326218 JK |
2549 | /* Determine the number of active and failed filters. */ |
2550 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
2551 | vsi->active_filters = 0; | |
2552 | hash_for_each(vsi->mac_filter_hash, bkt, f, hlist) { | |
2553 | if (f->state == I40E_FILTER_ACTIVE) | |
2554 | vsi->active_filters++; | |
2555 | else if (f->state == I40E_FILTER_FAILED) | |
2556 | failed_filters++; | |
2557 | } | |
2558 | spin_unlock_bh(&vsi->mac_filter_hash_lock); | |
2559 | ||
38326218 JK |
2560 | /* Check if we are able to exit overflow promiscuous mode. We can |
2561 | * safely exit if we didn't just enter, we no longer have any failed | |
2562 | * filters, and we have reduced filters below the threshold value. | |
2563 | */ | |
cc6a96a4 AB |
2564 | if (old_overflow && !failed_filters && |
2565 | vsi->active_filters < vsi->promisc_threshold) { | |
38326218 JK |
2566 | dev_info(&pf->pdev->dev, |
2567 | "filter logjam cleared on %s, leaving overflow promiscuous mode\n", | |
2568 | vsi_name); | |
0da36b97 | 2569 | clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
38326218 | 2570 | vsi->promisc_threshold = 0; |
41c445ff JB |
2571 | } |
2572 | ||
a856b5cb ASJ |
2573 | /* if the VF is not trusted do not do promisc */ |
2574 | if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) { | |
0da36b97 | 2575 | clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
a856b5cb ASJ |
2576 | goto out; |
2577 | } | |
2578 | ||
cc6a96a4 AB |
2579 | new_overflow = test_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
2580 | ||
2581 | /* If we are entering overflow promiscuous, we need to calculate a new | |
2582 | * threshold for when we are safe to exit | |
2583 | */ | |
2584 | if (!old_overflow && new_overflow) | |
2585 | vsi->promisc_threshold = (vsi->active_filters * 3) / 4; | |
2586 | ||
41c445ff JB |
2587 | /* check for changes in promiscuous modes */ |
2588 | if (changed_flags & IFF_ALLMULTI) { | |
2589 | bool cur_multipromisc; | |
6995b36c | 2590 | |
41c445ff | 2591 | cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI); |
ea02e90b MW |
2592 | aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw, |
2593 | vsi->seid, | |
2594 | cur_multipromisc, | |
2595 | NULL); | |
2596 | if (aq_ret) { | |
2597 | retval = i40e_aq_rc_to_posix(aq_ret, | |
3e25a8f3 | 2598 | hw->aq.asq_last_status); |
41c445ff | 2599 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
2600 | "set multi promisc failed on %s, err %s aq_err %s\n", |
2601 | vsi_name, | |
3e25a8f3 MW |
2602 | i40e_stat_str(hw, aq_ret), |
2603 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
b603f9dc | 2604 | } else { |
6b5674fe | 2605 | dev_info(&pf->pdev->dev, "%s allmulti mode.\n", |
b603f9dc | 2606 | cur_multipromisc ? "entering" : "leaving"); |
ea02e90b | 2607 | } |
41c445ff | 2608 | } |
e5887239 | 2609 | |
cc6a96a4 | 2610 | if ((changed_flags & IFF_PROMISC) || old_overflow != new_overflow) { |
41c445ff | 2611 | bool cur_promisc; |
6995b36c | 2612 | |
41c445ff | 2613 | cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) || |
cc6a96a4 | 2614 | new_overflow); |
bd5608b3 | 2615 | aq_ret = i40e_set_promiscuous(pf, cur_promisc); |
ea02e90b MW |
2616 | if (aq_ret) { |
2617 | retval = i40e_aq_rc_to_posix(aq_ret, | |
bd5608b3 | 2618 | hw->aq.asq_last_status); |
1a10370a | 2619 | dev_info(&pf->pdev->dev, |
bd5608b3 AB |
2620 | "Setting promiscuous %s failed on %s, err %s aq_err %s\n", |
2621 | cur_promisc ? "on" : "off", | |
2622 | vsi_name, | |
2623 | i40e_stat_str(hw, aq_ret), | |
2624 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
ea02e90b | 2625 | } |
41c445ff | 2626 | } |
ea02e90b | 2627 | out: |
2818ccd9 JB |
2628 | /* if something went wrong then set the changed flag so we try again */ |
2629 | if (retval) | |
2630 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
2631 | ||
0da36b97 | 2632 | clear_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state); |
ea02e90b | 2633 | return retval; |
4a2ce27b JK |
2634 | |
2635 | err_no_memory: | |
2636 | /* Restore elements on the temporary add and delete lists */ | |
2637 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
84f5ca6c | 2638 | err_no_memory_locked: |
671889e6 JK |
2639 | i40e_undo_del_filter_entries(vsi, &tmp_del_list); |
2640 | i40e_undo_add_filter_entries(vsi, &tmp_add_list); | |
4a2ce27b JK |
2641 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
2642 | ||
2643 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
0da36b97 | 2644 | clear_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state); |
4a2ce27b | 2645 | return -ENOMEM; |
41c445ff JB |
2646 | } |
2647 | ||
2648 | /** | |
2649 | * i40e_sync_filters_subtask - Sync the VSI filter list with HW | |
2650 | * @pf: board private structure | |
2651 | **/ | |
2652 | static void i40e_sync_filters_subtask(struct i40e_pf *pf) | |
2653 | { | |
2654 | int v; | |
2655 | ||
bfe040c3 JK |
2656 | if (!pf) |
2657 | return; | |
2658 | if (!test_and_clear_bit(__I40E_MACVLAN_SYNC_PENDING, pf->state)) | |
41c445ff | 2659 | return; |
dc881262 | 2660 | if (test_bit(__I40E_VF_DISABLE, pf->state)) { |
a7542b87 SA |
2661 | set_bit(__I40E_MACVLAN_SYNC_PENDING, pf->state); |
2662 | return; | |
2663 | } | |
41c445ff | 2664 | |
505682cd | 2665 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff | 2666 | if (pf->vsi[v] && |
37d9e304 MM |
2667 | (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED) && |
2668 | !test_bit(__I40E_VSI_RELEASING, pf->vsi[v]->state)) { | |
17652c63 JB |
2669 | int ret = i40e_sync_vsi_filters(pf->vsi[v]); |
2670 | ||
2671 | if (ret) { | |
2672 | /* come back and try again later */ | |
bfe040c3 JK |
2673 | set_bit(__I40E_MACVLAN_SYNC_PENDING, |
2674 | pf->state); | |
17652c63 JB |
2675 | break; |
2676 | } | |
2677 | } | |
41c445ff JB |
2678 | } |
2679 | } | |
2680 | ||
0c8493d9 BT |
2681 | /** |
2682 | * i40e_max_xdp_frame_size - returns the maximum allowed frame size for XDP | |
2683 | * @vsi: the vsi | |
2684 | **/ | |
2685 | static int i40e_max_xdp_frame_size(struct i40e_vsi *vsi) | |
2686 | { | |
2687 | if (PAGE_SIZE >= 8192 || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) | |
2688 | return I40E_RXBUFFER_2048; | |
2689 | else | |
2690 | return I40E_RXBUFFER_3072; | |
2691 | } | |
2692 | ||
41c445ff JB |
2693 | /** |
2694 | * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit | |
2695 | * @netdev: network interface device structure | |
2696 | * @new_mtu: new value for maximum frame size | |
2697 | * | |
2698 | * Returns 0 on success, negative on failure | |
2699 | **/ | |
2700 | static int i40e_change_mtu(struct net_device *netdev, int new_mtu) | |
2701 | { | |
2702 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
41c445ff | 2703 | struct i40e_vsi *vsi = np->vsi; |
0ef2d5af | 2704 | struct i40e_pf *pf = vsi->back; |
41c445ff | 2705 | |
0c8493d9 BT |
2706 | if (i40e_enabled_xdp_vsi(vsi)) { |
2707 | int frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
2708 | ||
2709 | if (frame_size > i40e_max_xdp_frame_size(vsi)) | |
2710 | return -EINVAL; | |
2711 | } | |
2712 | ||
12299132 FF |
2713 | netdev_dbg(netdev, "changing MTU from %d to %d\n", |
2714 | netdev->mtu, new_mtu); | |
41c445ff JB |
2715 | netdev->mtu = new_mtu; |
2716 | if (netif_running(netdev)) | |
2717 | i40e_vsi_reinit_locked(vsi); | |
5f76a704 JK |
2718 | set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state); |
2719 | set_bit(__I40E_CLIENT_L2_CHANGE, pf->state); | |
41c445ff JB |
2720 | return 0; |
2721 | } | |
2722 | ||
beb0dff1 JK |
2723 | /** |
2724 | * i40e_ioctl - Access the hwtstamp interface | |
2725 | * @netdev: network interface device structure | |
2726 | * @ifr: interface request data | |
2727 | * @cmd: ioctl command | |
2728 | **/ | |
2729 | int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
2730 | { | |
2731 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2732 | struct i40e_pf *pf = np->vsi->back; | |
2733 | ||
2734 | switch (cmd) { | |
2735 | case SIOCGHWTSTAMP: | |
2736 | return i40e_ptp_get_ts_config(pf, ifr); | |
2737 | case SIOCSHWTSTAMP: | |
2738 | return i40e_ptp_set_ts_config(pf, ifr); | |
2739 | default: | |
2740 | return -EOPNOTSUPP; | |
2741 | } | |
2742 | } | |
2743 | ||
41c445ff JB |
2744 | /** |
2745 | * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI | |
2746 | * @vsi: the vsi being adjusted | |
2747 | **/ | |
2748 | void i40e_vlan_stripping_enable(struct i40e_vsi *vsi) | |
2749 | { | |
2750 | struct i40e_vsi_context ctxt; | |
2751 | i40e_status ret; | |
2752 | ||
bfb0ebed NN |
2753 | /* Don't modify stripping options if a port VLAN is active */ |
2754 | if (vsi->info.pvid) | |
2755 | return; | |
2756 | ||
41c445ff JB |
2757 | if ((vsi->info.valid_sections & |
2758 | cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && | |
2759 | ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0)) | |
2760 | return; /* already enabled */ | |
2761 | ||
2762 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2763 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | | |
2764 | I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; | |
2765 | ||
2766 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2767 | ctxt.info = vsi->info; |
41c445ff JB |
2768 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2769 | if (ret) { | |
2770 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
2771 | "update vlan stripping failed, err %s aq_err %s\n", |
2772 | i40e_stat_str(&vsi->back->hw, ret), | |
2773 | i40e_aq_str(&vsi->back->hw, | |
2774 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
2775 | } |
2776 | } | |
2777 | ||
2778 | /** | |
2779 | * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI | |
2780 | * @vsi: the vsi being adjusted | |
2781 | **/ | |
2782 | void i40e_vlan_stripping_disable(struct i40e_vsi *vsi) | |
2783 | { | |
2784 | struct i40e_vsi_context ctxt; | |
2785 | i40e_status ret; | |
2786 | ||
bfb0ebed NN |
2787 | /* Don't modify stripping options if a port VLAN is active */ |
2788 | if (vsi->info.pvid) | |
2789 | return; | |
2790 | ||
41c445ff JB |
2791 | if ((vsi->info.valid_sections & |
2792 | cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && | |
2793 | ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) == | |
2794 | I40E_AQ_VSI_PVLAN_EMOD_MASK)) | |
2795 | return; /* already disabled */ | |
2796 | ||
2797 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2798 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | | |
2799 | I40E_AQ_VSI_PVLAN_EMOD_NOTHING; | |
2800 | ||
2801 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2802 | ctxt.info = vsi->info; |
41c445ff JB |
2803 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2804 | if (ret) { | |
2805 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
2806 | "update vlan stripping failed, err %s aq_err %s\n", |
2807 | i40e_stat_str(&vsi->back->hw, ret), | |
2808 | i40e_aq_str(&vsi->back->hw, | |
2809 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
2810 | } |
2811 | } | |
2812 | ||
41c445ff | 2813 | /** |
490a4ad3 | 2814 | * i40e_add_vlan_all_mac - Add a MAC/VLAN filter for each existing MAC address |
41c445ff JB |
2815 | * @vsi: the vsi being configured |
2816 | * @vid: vlan id to be added (0 = untagged only , -1 = any) | |
490a4ad3 JK |
2817 | * |
2818 | * This is a helper function for adding a new MAC/VLAN filter with the | |
2819 | * specified VLAN for each existing MAC address already in the hash table. | |
2820 | * This function does *not* perform any accounting to update filters based on | |
2821 | * VLAN mode. | |
2822 | * | |
2823 | * NOTE: this function expects to be called while under the | |
2824 | * mac_filter_hash_lock | |
41c445ff | 2825 | **/ |
9af52f60 | 2826 | int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid) |
41c445ff | 2827 | { |
490a4ad3 | 2828 | struct i40e_mac_filter *f, *add_f; |
278e7d0b JK |
2829 | struct hlist_node *h; |
2830 | int bkt; | |
41c445ff | 2831 | |
278e7d0b | 2832 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
57b341d6 JK |
2833 | if (f->state == I40E_FILTER_REMOVE) |
2834 | continue; | |
1bc87e80 | 2835 | add_f = i40e_add_filter(vsi, f->macaddr, vid); |
41c445ff JB |
2836 | if (!add_f) { |
2837 | dev_info(&vsi->back->pdev->dev, | |
2838 | "Could not add vlan filter %d for %pM\n", | |
2839 | vid, f->macaddr); | |
2840 | return -ENOMEM; | |
2841 | } | |
2842 | } | |
2843 | ||
490a4ad3 JK |
2844 | return 0; |
2845 | } | |
2846 | ||
2847 | /** | |
2848 | * i40e_vsi_add_vlan - Add VSI membership for given VLAN | |
2849 | * @vsi: the VSI being configured | |
f94484b7 | 2850 | * @vid: VLAN id to be added |
490a4ad3 | 2851 | **/ |
f94484b7 | 2852 | int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid) |
490a4ad3 | 2853 | { |
489a3265 | 2854 | int err; |
490a4ad3 | 2855 | |
fcf6cfc8 | 2856 | if (vsi->info.pvid) |
f94484b7 JK |
2857 | return -EINVAL; |
2858 | ||
fcf6cfc8 JK |
2859 | /* The network stack will attempt to add VID=0, with the intention to |
2860 | * receive priority tagged packets with a VLAN of 0. Our HW receives | |
2861 | * these packets by default when configured to receive untagged | |
2862 | * packets, so we don't need to add a filter for this case. | |
2863 | * Additionally, HW interprets adding a VID=0 filter as meaning to | |
2864 | * receive *only* tagged traffic and stops receiving untagged traffic. | |
2865 | * Thus, we do not want to actually add a filter for VID=0 | |
2866 | */ | |
2867 | if (!vid) | |
2868 | return 0; | |
2869 | ||
490a4ad3 JK |
2870 | /* Locked once because all functions invoked below iterates list*/ |
2871 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
490a4ad3 | 2872 | err = i40e_add_vlan_all_mac(vsi, vid); |
278e7d0b | 2873 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
489a3265 JK |
2874 | if (err) |
2875 | return err; | |
21659035 | 2876 | |
0e4425ed JB |
2877 | /* schedule our worker thread which will take care of |
2878 | * applying the new filter changes | |
2879 | */ | |
2880 | i40e_service_event_schedule(vsi->back); | |
2881 | return 0; | |
41c445ff JB |
2882 | } |
2883 | ||
2884 | /** | |
490a4ad3 | 2885 | * i40e_rm_vlan_all_mac - Remove MAC/VLAN pair for all MAC with the given VLAN |
41c445ff JB |
2886 | * @vsi: the vsi being configured |
2887 | * @vid: vlan id to be removed (0 = untagged only , -1 = any) | |
490a4ad3 JK |
2888 | * |
2889 | * This function should be used to remove all VLAN filters which match the | |
2890 | * given VID. It does not schedule the service event and does not take the | |
2891 | * mac_filter_hash_lock so it may be combined with other operations under | |
2892 | * a single invocation of the mac_filter_hash_lock. | |
2893 | * | |
2894 | * NOTE: this function expects to be called while under the | |
2895 | * mac_filter_hash_lock | |
2896 | */ | |
9af52f60 | 2897 | void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid) |
41c445ff | 2898 | { |
84f5ca6c | 2899 | struct i40e_mac_filter *f; |
278e7d0b | 2900 | struct hlist_node *h; |
278e7d0b | 2901 | int bkt; |
41c445ff | 2902 | |
278e7d0b | 2903 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
290d2557 JK |
2904 | if (f->vlan == vid) |
2905 | __i40e_del_filter(vsi, f); | |
2906 | } | |
490a4ad3 | 2907 | } |
41c445ff | 2908 | |
490a4ad3 JK |
2909 | /** |
2910 | * i40e_vsi_kill_vlan - Remove VSI membership for given VLAN | |
2911 | * @vsi: the VSI being configured | |
f94484b7 | 2912 | * @vid: VLAN id to be removed |
490a4ad3 | 2913 | **/ |
f94484b7 | 2914 | void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid) |
490a4ad3 | 2915 | { |
f94484b7 JK |
2916 | if (!vid || vsi->info.pvid) |
2917 | return; | |
2918 | ||
490a4ad3 JK |
2919 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
2920 | i40e_rm_vlan_all_mac(vsi, vid); | |
278e7d0b | 2921 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 2922 | |
0e4425ed JB |
2923 | /* schedule our worker thread which will take care of |
2924 | * applying the new filter changes | |
2925 | */ | |
2926 | i40e_service_event_schedule(vsi->back); | |
41c445ff JB |
2927 | } |
2928 | ||
2929 | /** | |
2930 | * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload | |
2931 | * @netdev: network interface to be adjusted | |
f5254429 | 2932 | * @proto: unused protocol value |
41c445ff | 2933 | * @vid: vlan id to be added |
078b5876 JB |
2934 | * |
2935 | * net_device_ops implementation for adding vlan ids | |
41c445ff JB |
2936 | **/ |
2937 | static int i40e_vlan_rx_add_vid(struct net_device *netdev, | |
2938 | __always_unused __be16 proto, u16 vid) | |
2939 | { | |
2940 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2941 | struct i40e_vsi *vsi = np->vsi; | |
078b5876 | 2942 | int ret = 0; |
41c445ff | 2943 | |
6a112785 | 2944 | if (vid >= VLAN_N_VID) |
078b5876 JB |
2945 | return -EINVAL; |
2946 | ||
fcf6cfc8 | 2947 | ret = i40e_vsi_add_vlan(vsi, vid); |
6a112785 | 2948 | if (!ret) |
078b5876 | 2949 | set_bit(vid, vsi->active_vlans); |
41c445ff | 2950 | |
078b5876 | 2951 | return ret; |
41c445ff JB |
2952 | } |
2953 | ||
27392e57 PJ |
2954 | /** |
2955 | * i40e_vlan_rx_add_vid_up - Add a vlan id filter to HW offload in UP path | |
2956 | * @netdev: network interface to be adjusted | |
2957 | * @proto: unused protocol value | |
2958 | * @vid: vlan id to be added | |
2959 | **/ | |
2960 | static void i40e_vlan_rx_add_vid_up(struct net_device *netdev, | |
2961 | __always_unused __be16 proto, u16 vid) | |
2962 | { | |
2963 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2964 | struct i40e_vsi *vsi = np->vsi; | |
2965 | ||
2966 | if (vid >= VLAN_N_VID) | |
2967 | return; | |
2968 | set_bit(vid, vsi->active_vlans); | |
2969 | } | |
2970 | ||
41c445ff JB |
2971 | /** |
2972 | * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload | |
2973 | * @netdev: network interface to be adjusted | |
f5254429 | 2974 | * @proto: unused protocol value |
41c445ff | 2975 | * @vid: vlan id to be removed |
078b5876 | 2976 | * |
fdfd943e | 2977 | * net_device_ops implementation for removing vlan ids |
41c445ff JB |
2978 | **/ |
2979 | static int i40e_vlan_rx_kill_vid(struct net_device *netdev, | |
2980 | __always_unused __be16 proto, u16 vid) | |
2981 | { | |
2982 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2983 | struct i40e_vsi *vsi = np->vsi; | |
2984 | ||
41c445ff JB |
2985 | /* return code is ignored as there is nothing a user |
2986 | * can do about failure to remove and a log message was | |
078b5876 | 2987 | * already printed from the other function |
41c445ff JB |
2988 | */ |
2989 | i40e_vsi_kill_vlan(vsi, vid); | |
2990 | ||
2991 | clear_bit(vid, vsi->active_vlans); | |
078b5876 | 2992 | |
41c445ff JB |
2993 | return 0; |
2994 | } | |
2995 | ||
2996 | /** | |
2997 | * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up | |
2998 | * @vsi: the vsi being brought back up | |
2999 | **/ | |
3000 | static void i40e_restore_vlan(struct i40e_vsi *vsi) | |
3001 | { | |
3002 | u16 vid; | |
3003 | ||
3004 | if (!vsi->netdev) | |
3005 | return; | |
3006 | ||
2972b007 JK |
3007 | if (vsi->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) |
3008 | i40e_vlan_stripping_enable(vsi); | |
3009 | else | |
3010 | i40e_vlan_stripping_disable(vsi); | |
41c445ff JB |
3011 | |
3012 | for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID) | |
27392e57 PJ |
3013 | i40e_vlan_rx_add_vid_up(vsi->netdev, htons(ETH_P_8021Q), |
3014 | vid); | |
41c445ff JB |
3015 | } |
3016 | ||
3017 | /** | |
3018 | * i40e_vsi_add_pvid - Add pvid for the VSI | |
3019 | * @vsi: the vsi being adjusted | |
3020 | * @vid: the vlan id to set as a PVID | |
3021 | **/ | |
dcae29be | 3022 | int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid) |
41c445ff JB |
3023 | { |
3024 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 3025 | i40e_status ret; |
41c445ff JB |
3026 | |
3027 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
3028 | vsi->info.pvid = cpu_to_le16(vid); | |
6c12fcbf GR |
3029 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED | |
3030 | I40E_AQ_VSI_PVLAN_INSERT_PVID | | |
b774c7dd | 3031 | I40E_AQ_VSI_PVLAN_EMOD_STR; |
41c445ff JB |
3032 | |
3033 | ctxt.seid = vsi->seid; | |
1a2f6248 | 3034 | ctxt.info = vsi->info; |
f1c7e72e SN |
3035 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
3036 | if (ret) { | |
41c445ff | 3037 | dev_info(&vsi->back->pdev->dev, |
f1c7e72e SN |
3038 | "add pvid failed, err %s aq_err %s\n", |
3039 | i40e_stat_str(&vsi->back->hw, ret), | |
3040 | i40e_aq_str(&vsi->back->hw, | |
3041 | vsi->back->hw.aq.asq_last_status)); | |
dcae29be | 3042 | return -ENOENT; |
41c445ff JB |
3043 | } |
3044 | ||
dcae29be | 3045 | return 0; |
41c445ff JB |
3046 | } |
3047 | ||
3048 | /** | |
3049 | * i40e_vsi_remove_pvid - Remove the pvid from the VSI | |
3050 | * @vsi: the vsi being adjusted | |
3051 | * | |
3052 | * Just use the vlan_rx_register() service to put it back to normal | |
3053 | **/ | |
3054 | void i40e_vsi_remove_pvid(struct i40e_vsi *vsi) | |
3055 | { | |
3056 | vsi->info.pvid = 0; | |
40a23040 GS |
3057 | |
3058 | i40e_vlan_stripping_disable(vsi); | |
41c445ff JB |
3059 | } |
3060 | ||
3061 | /** | |
3062 | * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources | |
3063 | * @vsi: ptr to the VSI | |
3064 | * | |
3065 | * If this function returns with an error, then it's possible one or | |
3066 | * more of the rings is populated (while the rest are not). It is the | |
3067 | * callers duty to clean those orphaned rings. | |
3068 | * | |
3069 | * Return 0 on success, negative on failure | |
3070 | **/ | |
3071 | static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi) | |
3072 | { | |
3073 | int i, err = 0; | |
3074 | ||
3075 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 3076 | err = i40e_setup_tx_descriptors(vsi->tx_rings[i]); |
41c445ff | 3077 | |
74608d17 BT |
3078 | if (!i40e_enabled_xdp_vsi(vsi)) |
3079 | return err; | |
3080 | ||
3081 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
3082 | err = i40e_setup_tx_descriptors(vsi->xdp_rings[i]); | |
3083 | ||
41c445ff JB |
3084 | return err; |
3085 | } | |
3086 | ||
3087 | /** | |
3088 | * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues | |
3089 | * @vsi: ptr to the VSI | |
3090 | * | |
3091 | * Free VSI's transmit software resources | |
3092 | **/ | |
3093 | static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi) | |
3094 | { | |
3095 | int i; | |
3096 | ||
74608d17 BT |
3097 | if (vsi->tx_rings) { |
3098 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
3099 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) | |
3100 | i40e_free_tx_resources(vsi->tx_rings[i]); | |
3101 | } | |
8e9dca53 | 3102 | |
74608d17 BT |
3103 | if (vsi->xdp_rings) { |
3104 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
3105 | if (vsi->xdp_rings[i] && vsi->xdp_rings[i]->desc) | |
3106 | i40e_free_tx_resources(vsi->xdp_rings[i]); | |
3107 | } | |
41c445ff JB |
3108 | } |
3109 | ||
3110 | /** | |
3111 | * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources | |
3112 | * @vsi: ptr to the VSI | |
3113 | * | |
3114 | * If this function returns with an error, then it's possible one or | |
3115 | * more of the rings is populated (while the rest are not). It is the | |
3116 | * callers duty to clean those orphaned rings. | |
3117 | * | |
3118 | * Return 0 on success, negative on failure | |
3119 | **/ | |
3120 | static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi) | |
3121 | { | |
3122 | int i, err = 0; | |
3123 | ||
3124 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 3125 | err = i40e_setup_rx_descriptors(vsi->rx_rings[i]); |
41c445ff JB |
3126 | return err; |
3127 | } | |
3128 | ||
3129 | /** | |
3130 | * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues | |
3131 | * @vsi: ptr to the VSI | |
3132 | * | |
3133 | * Free all receive software resources | |
3134 | **/ | |
3135 | static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi) | |
3136 | { | |
3137 | int i; | |
3138 | ||
8e9dca53 GR |
3139 | if (!vsi->rx_rings) |
3140 | return; | |
3141 | ||
41c445ff | 3142 | for (i = 0; i < vsi->num_queue_pairs; i++) |
8e9dca53 | 3143 | if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc) |
9f65e15b | 3144 | i40e_free_rx_resources(vsi->rx_rings[i]); |
41c445ff JB |
3145 | } |
3146 | ||
3ffa037d NP |
3147 | /** |
3148 | * i40e_config_xps_tx_ring - Configure XPS for a Tx ring | |
3149 | * @ring: The Tx ring to configure | |
3150 | * | |
3151 | * This enables/disables XPS for a given Tx descriptor ring | |
3152 | * based on the TCs enabled for the VSI that ring belongs to. | |
3153 | **/ | |
3154 | static void i40e_config_xps_tx_ring(struct i40e_ring *ring) | |
3155 | { | |
be664cbe | 3156 | int cpu; |
3ffa037d | 3157 | |
8f88b303 | 3158 | if (!ring->q_vector || !ring->netdev || ring->ch) |
9a660eea JB |
3159 | return; |
3160 | ||
6f853d4f JK |
3161 | /* We only initialize XPS once, so as not to overwrite user settings */ |
3162 | if (test_and_set_bit(__I40E_TX_XPS_INIT_DONE, ring->state)) | |
3163 | return; | |
0e4425ed | 3164 | |
6f853d4f JK |
3165 | cpu = cpumask_local_spread(ring->q_vector->v_idx, -1); |
3166 | netif_set_xps_queue(ring->netdev, get_cpu_mask(cpu), | |
3167 | ring->queue_index); | |
3ffa037d NP |
3168 | } |
3169 | ||
b83f28e1 | 3170 | /** |
1742b3d5 | 3171 | * i40e_xsk_pool - Retrieve the AF_XDP buffer pool if XDP and ZC is enabled |
b83f28e1 BT |
3172 | * @ring: The Tx or Rx ring |
3173 | * | |
1742b3d5 | 3174 | * Returns the AF_XDP buffer pool or NULL. |
b83f28e1 | 3175 | **/ |
1742b3d5 | 3176 | static struct xsk_buff_pool *i40e_xsk_pool(struct i40e_ring *ring) |
b83f28e1 BT |
3177 | { |
3178 | bool xdp_on = i40e_enabled_xdp_vsi(ring->vsi); | |
3179 | int qid = ring->queue_index; | |
3180 | ||
3181 | if (ring_is_xdp(ring)) | |
3182 | qid -= ring->vsi->alloc_queue_pairs; | |
3183 | ||
44ddd4f1 | 3184 | if (!xdp_on || !test_bit(qid, ring->vsi->af_xdp_zc_qps)) |
b83f28e1 BT |
3185 | return NULL; |
3186 | ||
c4655761 | 3187 | return xsk_get_pool_from_qid(ring->vsi->netdev, qid); |
b83f28e1 BT |
3188 | } |
3189 | ||
41c445ff JB |
3190 | /** |
3191 | * i40e_configure_tx_ring - Configure a transmit ring context and rest | |
3192 | * @ring: The Tx ring to configure | |
3193 | * | |
3194 | * Configure the Tx descriptor ring in the HMC context. | |
3195 | **/ | |
3196 | static int i40e_configure_tx_ring(struct i40e_ring *ring) | |
3197 | { | |
3198 | struct i40e_vsi *vsi = ring->vsi; | |
3199 | u16 pf_q = vsi->base_queue + ring->queue_index; | |
3200 | struct i40e_hw *hw = &vsi->back->hw; | |
3201 | struct i40e_hmc_obj_txq tx_ctx; | |
3202 | i40e_status err = 0; | |
3203 | u32 qtx_ctl = 0; | |
3204 | ||
1328dcdd | 3205 | if (ring_is_xdp(ring)) |
1742b3d5 | 3206 | ring->xsk_pool = i40e_xsk_pool(ring); |
1328dcdd | 3207 | |
41c445ff | 3208 | /* some ATR related tx ring init */ |
60ea5f83 | 3209 | if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) { |
41c445ff JB |
3210 | ring->atr_sample_rate = vsi->back->atr_sample_rate; |
3211 | ring->atr_count = 0; | |
3212 | } else { | |
3213 | ring->atr_sample_rate = 0; | |
3214 | } | |
3215 | ||
3ffa037d NP |
3216 | /* configure XPS */ |
3217 | i40e_config_xps_tx_ring(ring); | |
41c445ff JB |
3218 | |
3219 | /* clear the context structure first */ | |
3220 | memset(&tx_ctx, 0, sizeof(tx_ctx)); | |
3221 | ||
3222 | tx_ctx.new_context = 1; | |
3223 | tx_ctx.base = (ring->dma / 128); | |
3224 | tx_ctx.qlen = ring->count; | |
60ea5f83 JB |
3225 | tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED | |
3226 | I40E_FLAG_FD_ATR_ENABLED)); | |
beb0dff1 | 3227 | tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP); |
1943d8ba JB |
3228 | /* FDIR VSI tx ring can still use RS bit and writebacks */ |
3229 | if (vsi->type != I40E_VSI_FDIR) | |
3230 | tx_ctx.head_wb_ena = 1; | |
3231 | tx_ctx.head_wb_addr = ring->dma + | |
3232 | (ring->count * sizeof(struct i40e_tx_desc)); | |
41c445ff JB |
3233 | |
3234 | /* As part of VSI creation/update, FW allocates certain | |
3235 | * Tx arbitration queue sets for each TC enabled for | |
3236 | * the VSI. The FW returns the handles to these queue | |
3237 | * sets as part of the response buffer to Add VSI, | |
3238 | * Update VSI, etc. AQ commands. It is expected that | |
3239 | * these queue set handles be associated with the Tx | |
3240 | * queues by the driver as part of the TX queue context | |
3241 | * initialization. This has to be done regardless of | |
3242 | * DCB as by default everything is mapped to TC0. | |
3243 | */ | |
8f88b303 AN |
3244 | |
3245 | if (ring->ch) | |
3246 | tx_ctx.rdylist = | |
3247 | le16_to_cpu(ring->ch->info.qs_handle[ring->dcb_tc]); | |
3248 | ||
3249 | else | |
3250 | tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]); | |
3251 | ||
41c445ff JB |
3252 | tx_ctx.rdylist_act = 0; |
3253 | ||
3254 | /* clear the context in the HMC */ | |
3255 | err = i40e_clear_lan_tx_queue_context(hw, pf_q); | |
3256 | if (err) { | |
3257 | dev_info(&vsi->back->pdev->dev, | |
3258 | "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n", | |
3259 | ring->queue_index, pf_q, err); | |
3260 | return -ENOMEM; | |
3261 | } | |
3262 | ||
3263 | /* set the context in the HMC */ | |
3264 | err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx); | |
3265 | if (err) { | |
3266 | dev_info(&vsi->back->pdev->dev, | |
3267 | "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n", | |
3268 | ring->queue_index, pf_q, err); | |
3269 | return -ENOMEM; | |
3270 | } | |
3271 | ||
3272 | /* Now associate this queue with this PCI function */ | |
8f88b303 AN |
3273 | if (ring->ch) { |
3274 | if (ring->ch->type == I40E_VSI_VMDQ2) | |
3275 | qtx_ctl = I40E_QTX_CTL_VM_QUEUE; | |
3276 | else | |
3277 | return -EINVAL; | |
3278 | ||
3279 | qtx_ctl |= (ring->ch->vsi_number << | |
3280 | I40E_QTX_CTL_VFVM_INDX_SHIFT) & | |
3281 | I40E_QTX_CTL_VFVM_INDX_MASK; | |
7a28d885 | 3282 | } else { |
8f88b303 AN |
3283 | if (vsi->type == I40E_VSI_VMDQ2) { |
3284 | qtx_ctl = I40E_QTX_CTL_VM_QUEUE; | |
3285 | qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) & | |
3286 | I40E_QTX_CTL_VFVM_INDX_MASK; | |
3287 | } else { | |
3288 | qtx_ctl = I40E_QTX_CTL_PF_QUEUE; | |
3289 | } | |
7a28d885 MW |
3290 | } |
3291 | ||
13fd9774 SN |
3292 | qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & |
3293 | I40E_QTX_CTL_PF_INDX_MASK); | |
41c445ff JB |
3294 | wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl); |
3295 | i40e_flush(hw); | |
3296 | ||
41c445ff JB |
3297 | /* cache tail off for easier writes later */ |
3298 | ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q); | |
3299 | ||
3300 | return 0; | |
3301 | } | |
3302 | ||
a8660626 MF |
3303 | /** |
3304 | * i40e_rx_offset - Return expected offset into page to access data | |
3305 | * @rx_ring: Ring we are requesting offset of | |
3306 | * | |
3307 | * Returns the offset value for ring into the data buffer. | |
3308 | */ | |
3309 | static unsigned int i40e_rx_offset(struct i40e_ring *rx_ring) | |
3310 | { | |
3311 | return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0; | |
3312 | } | |
3313 | ||
41c445ff JB |
3314 | /** |
3315 | * i40e_configure_rx_ring - Configure a receive ring context | |
3316 | * @ring: The Rx ring to configure | |
3317 | * | |
3318 | * Configure the Rx descriptor ring in the HMC context. | |
3319 | **/ | |
3320 | static int i40e_configure_rx_ring(struct i40e_ring *ring) | |
3321 | { | |
3322 | struct i40e_vsi *vsi = ring->vsi; | |
3323 | u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len; | |
3324 | u16 pf_q = vsi->base_queue + ring->queue_index; | |
3325 | struct i40e_hw *hw = &vsi->back->hw; | |
3326 | struct i40e_hmc_obj_rxq rx_ctx; | |
3327 | i40e_status err = 0; | |
0a714186 BT |
3328 | bool ok; |
3329 | int ret; | |
41c445ff | 3330 | |
bd6cd4e6 | 3331 | bitmap_zero(ring->state, __I40E_RING_STATE_NBITS); |
41c445ff JB |
3332 | |
3333 | /* clear the context structure first */ | |
3334 | memset(&rx_ctx, 0, sizeof(rx_ctx)); | |
3335 | ||
0a714186 BT |
3336 | if (ring->vsi->type == I40E_VSI_MAIN) |
3337 | xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); | |
3338 | ||
be1222b5 | 3339 | kfree(ring->rx_bi); |
1742b3d5 MK |
3340 | ring->xsk_pool = i40e_xsk_pool(ring); |
3341 | if (ring->xsk_pool) { | |
be1222b5 BT |
3342 | ret = i40e_alloc_rx_bi_zc(ring); |
3343 | if (ret) | |
3344 | return ret; | |
1742b3d5 | 3345 | ring->rx_buf_len = |
c4655761 | 3346 | xsk_pool_get_rx_frame_size(ring->xsk_pool); |
0a714186 BT |
3347 | /* For AF_XDP ZC, we disallow packets to span on |
3348 | * multiple buffers, thus letting us skip that | |
3349 | * handling in the fast-path. | |
3350 | */ | |
3351 | chain_len = 1; | |
0a714186 | 3352 | ret = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, |
3b4f0b66 BT |
3353 | MEM_TYPE_XSK_BUFF_POOL, |
3354 | NULL); | |
0a714186 BT |
3355 | if (ret) |
3356 | return ret; | |
3357 | dev_info(&vsi->back->pdev->dev, | |
3b4f0b66 | 3358 | "Registered XDP mem model MEM_TYPE_XSK_BUFF_POOL on Rx ring %d\n", |
0a714186 BT |
3359 | ring->queue_index); |
3360 | ||
3361 | } else { | |
be1222b5 BT |
3362 | ret = i40e_alloc_rx_bi(ring); |
3363 | if (ret) | |
3364 | return ret; | |
0a714186 BT |
3365 | ring->rx_buf_len = vsi->rx_buf_len; |
3366 | if (ring->vsi->type == I40E_VSI_MAIN) { | |
3367 | ret = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, | |
3368 | MEM_TYPE_PAGE_SHARED, | |
3369 | NULL); | |
3370 | if (ret) | |
3371 | return ret; | |
3372 | } | |
3373 | } | |
41c445ff | 3374 | |
dab86afd AD |
3375 | rx_ctx.dbuff = DIV_ROUND_UP(ring->rx_buf_len, |
3376 | BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT)); | |
41c445ff JB |
3377 | |
3378 | rx_ctx.base = (ring->dma / 128); | |
3379 | rx_ctx.qlen = ring->count; | |
3380 | ||
f0064bfd BT |
3381 | /* use 16 byte descriptors */ |
3382 | rx_ctx.dsize = 0; | |
41c445ff | 3383 | |
bec60fc4 JB |
3384 | /* descriptor type is always zero |
3385 | * rx_ctx.dtype = 0; | |
3386 | */ | |
b32bfa17 | 3387 | rx_ctx.hsplit_0 = 0; |
41c445ff | 3388 | |
b32bfa17 | 3389 | rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len); |
7134f9ce JB |
3390 | if (hw->revision_id == 0) |
3391 | rx_ctx.lrxqthresh = 0; | |
3392 | else | |
7362be9e | 3393 | rx_ctx.lrxqthresh = 1; |
41c445ff JB |
3394 | rx_ctx.crcstrip = 1; |
3395 | rx_ctx.l2tsel = 1; | |
c4bbac39 JB |
3396 | /* this controls whether VLAN is stripped from inner headers */ |
3397 | rx_ctx.showiv = 0; | |
acb3676b CS |
3398 | /* set the prefena field to 1 because the manual says to */ |
3399 | rx_ctx.prefena = 1; | |
41c445ff JB |
3400 | |
3401 | /* clear the context in the HMC */ | |
3402 | err = i40e_clear_lan_rx_queue_context(hw, pf_q); | |
3403 | if (err) { | |
3404 | dev_info(&vsi->back->pdev->dev, | |
3405 | "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", | |
3406 | ring->queue_index, pf_q, err); | |
3407 | return -ENOMEM; | |
3408 | } | |
3409 | ||
3410 | /* set the context in the HMC */ | |
3411 | err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx); | |
3412 | if (err) { | |
3413 | dev_info(&vsi->back->pdev->dev, | |
3414 | "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", | |
3415 | ring->queue_index, pf_q, err); | |
3416 | return -ENOMEM; | |
3417 | } | |
3418 | ||
ca9ec088 AD |
3419 | /* configure Rx buffer alignment */ |
3420 | if (!vsi->netdev || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) | |
3421 | clear_ring_build_skb_enabled(ring); | |
3422 | else | |
3423 | set_ring_build_skb_enabled(ring); | |
3424 | ||
a8660626 MF |
3425 | ring->rx_offset = i40e_rx_offset(ring); |
3426 | ||
41c445ff JB |
3427 | /* cache tail for quicker writes, and clear the reg before use */ |
3428 | ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q); | |
3429 | writel(0, ring->tail); | |
3430 | ||
1742b3d5 | 3431 | if (ring->xsk_pool) { |
c4655761 | 3432 | xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq); |
3b4f0b66 BT |
3433 | ok = i40e_alloc_rx_buffers_zc(ring, I40E_DESC_UNUSED(ring)); |
3434 | } else { | |
3435 | ok = !i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring)); | |
3436 | } | |
0a714186 | 3437 | if (!ok) { |
14ffeb52 MK |
3438 | /* Log this in case the user has forgotten to give the kernel |
3439 | * any buffers, even later in the application. | |
3440 | */ | |
0a714186 | 3441 | dev_info(&vsi->back->pdev->dev, |
14ffeb52 | 3442 | "Failed to allocate some buffers on %sRx ring %d (pf_q %d)\n", |
1742b3d5 | 3443 | ring->xsk_pool ? "AF_XDP ZC enabled " : "", |
0a714186 BT |
3444 | ring->queue_index, pf_q); |
3445 | } | |
41c445ff JB |
3446 | |
3447 | return 0; | |
3448 | } | |
3449 | ||
3450 | /** | |
3451 | * i40e_vsi_configure_tx - Configure the VSI for Tx | |
3452 | * @vsi: VSI structure describing this set of rings and resources | |
3453 | * | |
3454 | * Configure the Tx VSI for operation. | |
3455 | **/ | |
3456 | static int i40e_vsi_configure_tx(struct i40e_vsi *vsi) | |
3457 | { | |
3458 | int err = 0; | |
3459 | u16 i; | |
3460 | ||
9f65e15b AD |
3461 | for (i = 0; (i < vsi->num_queue_pairs) && !err; i++) |
3462 | err = i40e_configure_tx_ring(vsi->tx_rings[i]); | |
41c445ff | 3463 | |
408bfc38 | 3464 | if (err || !i40e_enabled_xdp_vsi(vsi)) |
74608d17 BT |
3465 | return err; |
3466 | ||
3467 | for (i = 0; (i < vsi->num_queue_pairs) && !err; i++) | |
3468 | err = i40e_configure_tx_ring(vsi->xdp_rings[i]); | |
3469 | ||
41c445ff JB |
3470 | return err; |
3471 | } | |
3472 | ||
3473 | /** | |
3474 | * i40e_vsi_configure_rx - Configure the VSI for Rx | |
3475 | * @vsi: the VSI being configured | |
3476 | * | |
3477 | * Configure the Rx VSI for operation. | |
3478 | **/ | |
3479 | static int i40e_vsi_configure_rx(struct i40e_vsi *vsi) | |
3480 | { | |
3481 | int err = 0; | |
3482 | u16 i; | |
3483 | ||
dab86afd AD |
3484 | if (!vsi->netdev || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) { |
3485 | vsi->max_frame = I40E_MAX_RXBUFFER; | |
3486 | vsi->rx_buf_len = I40E_RXBUFFER_2048; | |
3487 | #if (PAGE_SIZE < 8192) | |
ca9ec088 AD |
3488 | } else if (!I40E_2K_TOO_SMALL_WITH_PADDING && |
3489 | (vsi->netdev->mtu <= ETH_DATA_LEN)) { | |
dab86afd AD |
3490 | vsi->max_frame = I40E_RXBUFFER_1536 - NET_IP_ALIGN; |
3491 | vsi->rx_buf_len = I40E_RXBUFFER_1536 - NET_IP_ALIGN; | |
3492 | #endif | |
3493 | } else { | |
3494 | vsi->max_frame = I40E_MAX_RXBUFFER; | |
98efd694 AD |
3495 | vsi->rx_buf_len = (PAGE_SIZE < 8192) ? I40E_RXBUFFER_3072 : |
3496 | I40E_RXBUFFER_2048; | |
dab86afd | 3497 | } |
41c445ff JB |
3498 | |
3499 | /* set up individual rings */ | |
3500 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 3501 | err = i40e_configure_rx_ring(vsi->rx_rings[i]); |
41c445ff JB |
3502 | |
3503 | return err; | |
3504 | } | |
3505 | ||
3506 | /** | |
3507 | * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC | |
3508 | * @vsi: ptr to the VSI | |
3509 | **/ | |
3510 | static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi) | |
3511 | { | |
e7046ee1 | 3512 | struct i40e_ring *tx_ring, *rx_ring; |
41c445ff JB |
3513 | u16 qoffset, qcount; |
3514 | int i, n; | |
3515 | ||
cd238a3e PN |
3516 | if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { |
3517 | /* Reset the TC information */ | |
3518 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
3519 | rx_ring = vsi->rx_rings[i]; | |
3520 | tx_ring = vsi->tx_rings[i]; | |
3521 | rx_ring->dcb_tc = 0; | |
3522 | tx_ring->dcb_tc = 0; | |
3523 | } | |
a9ce82f7 | 3524 | return; |
cd238a3e | 3525 | } |
41c445ff JB |
3526 | |
3527 | for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) { | |
41a1d04b | 3528 | if (!(vsi->tc_config.enabled_tc & BIT_ULL(n))) |
41c445ff JB |
3529 | continue; |
3530 | ||
3531 | qoffset = vsi->tc_config.tc_info[n].qoffset; | |
3532 | qcount = vsi->tc_config.tc_info[n].qcount; | |
3533 | for (i = qoffset; i < (qoffset + qcount); i++) { | |
e7046ee1 AA |
3534 | rx_ring = vsi->rx_rings[i]; |
3535 | tx_ring = vsi->tx_rings[i]; | |
41c445ff JB |
3536 | rx_ring->dcb_tc = n; |
3537 | tx_ring->dcb_tc = n; | |
3538 | } | |
3539 | } | |
3540 | } | |
3541 | ||
3542 | /** | |
3543 | * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI | |
3544 | * @vsi: ptr to the VSI | |
3545 | **/ | |
3546 | static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi) | |
3547 | { | |
3548 | if (vsi->netdev) | |
3549 | i40e_set_rx_mode(vsi->netdev); | |
3550 | } | |
3551 | ||
efca91e8 PP |
3552 | /** |
3553 | * i40e_reset_fdir_filter_cnt - Reset flow director filter counters | |
3554 | * @pf: Pointer to the targeted PF | |
3555 | * | |
3556 | * Set all flow director counters to 0. | |
3557 | */ | |
3558 | static void i40e_reset_fdir_filter_cnt(struct i40e_pf *pf) | |
3559 | { | |
3560 | pf->fd_tcp4_filter_cnt = 0; | |
3561 | pf->fd_udp4_filter_cnt = 0; | |
3562 | pf->fd_sctp4_filter_cnt = 0; | |
3563 | pf->fd_ip4_filter_cnt = 0; | |
3564 | pf->fd_tcp6_filter_cnt = 0; | |
3565 | pf->fd_udp6_filter_cnt = 0; | |
3566 | pf->fd_sctp6_filter_cnt = 0; | |
3567 | pf->fd_ip6_filter_cnt = 0; | |
3568 | } | |
3569 | ||
17a73f6b JG |
3570 | /** |
3571 | * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters | |
3572 | * @vsi: Pointer to the targeted VSI | |
3573 | * | |
3574 | * This function replays the hlist on the hw where all the SB Flow Director | |
3575 | * filters were saved. | |
3576 | **/ | |
3577 | static void i40e_fdir_filter_restore(struct i40e_vsi *vsi) | |
3578 | { | |
3579 | struct i40e_fdir_filter *filter; | |
3580 | struct i40e_pf *pf = vsi->back; | |
3581 | struct hlist_node *node; | |
3582 | ||
55a5e60b ASJ |
3583 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) |
3584 | return; | |
3585 | ||
6d069425 | 3586 | /* Reset FDir counters as we're replaying all existing filters */ |
efca91e8 | 3587 | i40e_reset_fdir_filter_cnt(pf); |
6d069425 | 3588 | |
17a73f6b JG |
3589 | hlist_for_each_entry_safe(filter, node, |
3590 | &pf->fdir_filter_list, fdir_node) { | |
3591 | i40e_add_del_fdir(vsi, filter, true); | |
3592 | } | |
3593 | } | |
3594 | ||
41c445ff JB |
3595 | /** |
3596 | * i40e_vsi_configure - Set up the VSI for action | |
3597 | * @vsi: the VSI being configured | |
3598 | **/ | |
3599 | static int i40e_vsi_configure(struct i40e_vsi *vsi) | |
3600 | { | |
3601 | int err; | |
3602 | ||
3603 | i40e_set_vsi_rx_mode(vsi); | |
3604 | i40e_restore_vlan(vsi); | |
3605 | i40e_vsi_config_dcb_rings(vsi); | |
3606 | err = i40e_vsi_configure_tx(vsi); | |
3607 | if (!err) | |
3608 | err = i40e_vsi_configure_rx(vsi); | |
3609 | ||
3610 | return err; | |
3611 | } | |
3612 | ||
3613 | /** | |
3614 | * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW | |
3615 | * @vsi: the VSI being configured | |
3616 | **/ | |
3617 | static void i40e_vsi_configure_msix(struct i40e_vsi *vsi) | |
3618 | { | |
74608d17 | 3619 | bool has_xdp = i40e_enabled_xdp_vsi(vsi); |
41c445ff | 3620 | struct i40e_pf *pf = vsi->back; |
41c445ff JB |
3621 | struct i40e_hw *hw = &pf->hw; |
3622 | u16 vector; | |
3623 | int i, q; | |
41c445ff JB |
3624 | u32 qp; |
3625 | ||
3626 | /* The interrupt indexing is offset by 1 in the PFINT_ITRn | |
3627 | * and PFINT_LNKLSTn registers, e.g.: | |
3628 | * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts) | |
3629 | */ | |
3630 | qp = vsi->base_queue; | |
3631 | vector = vsi->base_vector; | |
493fb300 | 3632 | for (i = 0; i < vsi->num_q_vectors; i++, vector++) { |
ac26fc13 JB |
3633 | struct i40e_q_vector *q_vector = vsi->q_vectors[i]; |
3634 | ||
a0073a4b | 3635 | q_vector->rx.next_update = jiffies + 1; |
556fdfd6 AD |
3636 | q_vector->rx.target_itr = |
3637 | ITR_TO_REG(vsi->rx_rings[i]->itr_setting); | |
41c445ff | 3638 | wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1), |
998e5166 | 3639 | q_vector->rx.target_itr >> 1); |
556fdfd6 | 3640 | q_vector->rx.current_itr = q_vector->rx.target_itr; |
a0073a4b AD |
3641 | |
3642 | q_vector->tx.next_update = jiffies + 1; | |
556fdfd6 AD |
3643 | q_vector->tx.target_itr = |
3644 | ITR_TO_REG(vsi->tx_rings[i]->itr_setting); | |
41c445ff | 3645 | wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1), |
998e5166 | 3646 | q_vector->tx.target_itr >> 1); |
556fdfd6 | 3647 | q_vector->tx.current_itr = q_vector->tx.target_itr; |
a0073a4b | 3648 | |
ac26fc13 | 3649 | wr32(hw, I40E_PFINT_RATEN(vector - 1), |
1c0e6a36 | 3650 | i40e_intrl_usec_to_reg(vsi->int_rate_limit)); |
41c445ff JB |
3651 | |
3652 | /* Linked list for the queuepairs assigned to this vector */ | |
3653 | wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp); | |
3654 | for (q = 0; q < q_vector->num_ringpairs; q++) { | |
74608d17 | 3655 | u32 nextqp = has_xdp ? qp + vsi->alloc_queue_pairs : qp; |
ac26fc13 JB |
3656 | u32 val; |
3657 | ||
41c445ff | 3658 | val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | |
74608d17 BT |
3659 | (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | |
3660 | (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | | |
3661 | (nextqp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | | |
3662 | (I40E_QUEUE_TYPE_TX << | |
3663 | I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); | |
41c445ff JB |
3664 | |
3665 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
3666 | ||
74608d17 BT |
3667 | if (has_xdp) { |
3668 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
3669 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | |
3670 | (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | | |
3671 | (qp << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | | |
3672 | (I40E_QUEUE_TYPE_TX << | |
3673 | I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
3674 | ||
3675 | wr32(hw, I40E_QINT_TQCTL(nextqp), val); | |
3676 | } | |
3677 | ||
41c445ff | 3678 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | |
74608d17 BT |
3679 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | |
3680 | (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | | |
3681 | ((qp + 1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | | |
3682 | (I40E_QUEUE_TYPE_RX << | |
3683 | I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
41c445ff JB |
3684 | |
3685 | /* Terminate the linked list */ | |
3686 | if (q == (q_vector->num_ringpairs - 1)) | |
74608d17 BT |
3687 | val |= (I40E_QUEUE_END_OF_LIST << |
3688 | I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |
41c445ff JB |
3689 | |
3690 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
3691 | qp++; | |
3692 | } | |
3693 | } | |
3694 | ||
3695 | i40e_flush(hw); | |
3696 | } | |
3697 | ||
3698 | /** | |
3699 | * i40e_enable_misc_int_causes - enable the non-queue interrupts | |
f5254429 | 3700 | * @pf: pointer to private device data structure |
41c445ff | 3701 | **/ |
ab437b5a | 3702 | static void i40e_enable_misc_int_causes(struct i40e_pf *pf) |
41c445ff | 3703 | { |
ab437b5a | 3704 | struct i40e_hw *hw = &pf->hw; |
41c445ff JB |
3705 | u32 val; |
3706 | ||
3707 | /* clear things first */ | |
3708 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ | |
3709 | rd32(hw, I40E_PFINT_ICR0); /* read to clear */ | |
3710 | ||
3711 | val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | | |
3712 | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | | |
3713 | I40E_PFINT_ICR0_ENA_GRST_MASK | | |
3714 | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | | |
3715 | I40E_PFINT_ICR0_ENA_GPIO_MASK | | |
41c445ff JB |
3716 | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | |
3717 | I40E_PFINT_ICR0_ENA_VFLR_MASK | | |
3718 | I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
3719 | ||
0d8e1439 ASJ |
3720 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) |
3721 | val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; | |
3722 | ||
ab437b5a JK |
3723 | if (pf->flags & I40E_FLAG_PTP) |
3724 | val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; | |
3725 | ||
41c445ff JB |
3726 | wr32(hw, I40E_PFINT_ICR0_ENA, val); |
3727 | ||
3728 | /* SW_ITR_IDX = 0, but don't change INTENA */ | |
84ed40e7 ASJ |
3729 | wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | |
3730 | I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); | |
41c445ff JB |
3731 | |
3732 | /* OTHER_ITR_IDX = 0 */ | |
3733 | wr32(hw, I40E_PFINT_STAT_CTL0, 0); | |
3734 | } | |
3735 | ||
3736 | /** | |
3737 | * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW | |
3738 | * @vsi: the VSI being configured | |
3739 | **/ | |
3740 | static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi) | |
3741 | { | |
74608d17 | 3742 | u32 nextqp = i40e_enabled_xdp_vsi(vsi) ? vsi->alloc_queue_pairs : 0; |
493fb300 | 3743 | struct i40e_q_vector *q_vector = vsi->q_vectors[0]; |
41c445ff JB |
3744 | struct i40e_pf *pf = vsi->back; |
3745 | struct i40e_hw *hw = &pf->hw; | |
3746 | u32 val; | |
3747 | ||
3748 | /* set the ITR configuration */ | |
a0073a4b | 3749 | q_vector->rx.next_update = jiffies + 1; |
556fdfd6 | 3750 | q_vector->rx.target_itr = ITR_TO_REG(vsi->rx_rings[0]->itr_setting); |
998e5166 | 3751 | wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.target_itr >> 1); |
556fdfd6 | 3752 | q_vector->rx.current_itr = q_vector->rx.target_itr; |
a0073a4b | 3753 | q_vector->tx.next_update = jiffies + 1; |
556fdfd6 | 3754 | q_vector->tx.target_itr = ITR_TO_REG(vsi->tx_rings[0]->itr_setting); |
998e5166 | 3755 | wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.target_itr >> 1); |
556fdfd6 | 3756 | q_vector->tx.current_itr = q_vector->tx.target_itr; |
41c445ff | 3757 | |
ab437b5a | 3758 | i40e_enable_misc_int_causes(pf); |
41c445ff JB |
3759 | |
3760 | /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ | |
3761 | wr32(hw, I40E_PFINT_LNKLST0, 0); | |
3762 | ||
f29eaa3d | 3763 | /* Associate the queue pair to the vector and enable the queue int */ |
74608d17 BT |
3764 | val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | |
3765 | (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | | |
3766 | (nextqp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)| | |
41c445ff JB |
3767 | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); |
3768 | ||
3769 | wr32(hw, I40E_QINT_RQCTL(0), val); | |
3770 | ||
74608d17 BT |
3771 | if (i40e_enabled_xdp_vsi(vsi)) { |
3772 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
3773 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT)| | |
3774 | (I40E_QUEUE_TYPE_TX | |
3775 | << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
3776 | ||
1d67ad39 | 3777 | wr32(hw, I40E_QINT_TQCTL(nextqp), val); |
74608d17 BT |
3778 | } |
3779 | ||
41c445ff JB |
3780 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | |
3781 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | |
3782 | (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |
3783 | ||
3784 | wr32(hw, I40E_QINT_TQCTL(0), val); | |
3785 | i40e_flush(hw); | |
3786 | } | |
3787 | ||
2ef28cfb MW |
3788 | /** |
3789 | * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0 | |
3790 | * @pf: board private structure | |
3791 | **/ | |
3792 | void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf) | |
3793 | { | |
3794 | struct i40e_hw *hw = &pf->hw; | |
3795 | ||
3796 | wr32(hw, I40E_PFINT_DYN_CTL0, | |
3797 | I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); | |
3798 | i40e_flush(hw); | |
3799 | } | |
3800 | ||
41c445ff JB |
3801 | /** |
3802 | * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0 | |
3803 | * @pf: board private structure | |
3804 | **/ | |
dbadbbe2 | 3805 | void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf) |
41c445ff JB |
3806 | { |
3807 | struct i40e_hw *hw = &pf->hw; | |
3808 | u32 val; | |
3809 | ||
3810 | val = I40E_PFINT_DYN_CTL0_INTENA_MASK | | |
dbadbbe2 | 3811 | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | |
41c445ff JB |
3812 | (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); |
3813 | ||
3814 | wr32(hw, I40E_PFINT_DYN_CTL0, val); | |
3815 | i40e_flush(hw); | |
3816 | } | |
3817 | ||
41c445ff JB |
3818 | /** |
3819 | * i40e_msix_clean_rings - MSIX mode Interrupt Handler | |
3820 | * @irq: interrupt number | |
3821 | * @data: pointer to a q_vector | |
3822 | **/ | |
3823 | static irqreturn_t i40e_msix_clean_rings(int irq, void *data) | |
3824 | { | |
3825 | struct i40e_q_vector *q_vector = data; | |
3826 | ||
cd0b6fa6 | 3827 | if (!q_vector->tx.ring && !q_vector->rx.ring) |
41c445ff JB |
3828 | return IRQ_HANDLED; |
3829 | ||
5d3465a1 | 3830 | napi_schedule_irqoff(&q_vector->napi); |
41c445ff JB |
3831 | |
3832 | return IRQ_HANDLED; | |
3833 | } | |
3834 | ||
96db776a AB |
3835 | /** |
3836 | * i40e_irq_affinity_notify - Callback for affinity changes | |
3837 | * @notify: context as to what irq was changed | |
3838 | * @mask: the new affinity mask | |
3839 | * | |
3840 | * This is a callback function used by the irq_set_affinity_notifier function | |
3841 | * so that we may register to receive changes to the irq affinity masks. | |
3842 | **/ | |
3843 | static void i40e_irq_affinity_notify(struct irq_affinity_notify *notify, | |
3844 | const cpumask_t *mask) | |
3845 | { | |
3846 | struct i40e_q_vector *q_vector = | |
3847 | container_of(notify, struct i40e_q_vector, affinity_notify); | |
3848 | ||
7e4d01e7 | 3849 | cpumask_copy(&q_vector->affinity_mask, mask); |
96db776a AB |
3850 | } |
3851 | ||
3852 | /** | |
3853 | * i40e_irq_affinity_release - Callback for affinity notifier release | |
3854 | * @ref: internal core kernel usage | |
3855 | * | |
3856 | * This is a callback function used by the irq_set_affinity_notifier function | |
3857 | * to inform the current notification subscriber that they will no longer | |
3858 | * receive notifications. | |
3859 | **/ | |
3860 | static void i40e_irq_affinity_release(struct kref *ref) {} | |
3861 | ||
41c445ff JB |
3862 | /** |
3863 | * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts | |
3864 | * @vsi: the VSI being configured | |
3865 | * @basename: name for the vector | |
3866 | * | |
3867 | * Allocates MSI-X vectors and requests interrupts from the kernel. | |
3868 | **/ | |
3869 | static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename) | |
3870 | { | |
3871 | int q_vectors = vsi->num_q_vectors; | |
3872 | struct i40e_pf *pf = vsi->back; | |
3873 | int base = vsi->base_vector; | |
3874 | int rx_int_idx = 0; | |
3875 | int tx_int_idx = 0; | |
3876 | int vector, err; | |
96db776a | 3877 | int irq_num; |
be664cbe | 3878 | int cpu; |
41c445ff JB |
3879 | |
3880 | for (vector = 0; vector < q_vectors; vector++) { | |
493fb300 | 3881 | struct i40e_q_vector *q_vector = vsi->q_vectors[vector]; |
41c445ff | 3882 | |
96db776a AB |
3883 | irq_num = pf->msix_entries[base + vector].vector; |
3884 | ||
cd0b6fa6 | 3885 | if (q_vector->tx.ring && q_vector->rx.ring) { |
41c445ff JB |
3886 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3887 | "%s-%s-%d", basename, "TxRx", rx_int_idx++); | |
3888 | tx_int_idx++; | |
cd0b6fa6 | 3889 | } else if (q_vector->rx.ring) { |
41c445ff JB |
3890 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3891 | "%s-%s-%d", basename, "rx", rx_int_idx++); | |
cd0b6fa6 | 3892 | } else if (q_vector->tx.ring) { |
41c445ff JB |
3893 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3894 | "%s-%s-%d", basename, "tx", tx_int_idx++); | |
3895 | } else { | |
3896 | /* skip this unused q_vector */ | |
3897 | continue; | |
3898 | } | |
96db776a | 3899 | err = request_irq(irq_num, |
41c445ff JB |
3900 | vsi->irq_handler, |
3901 | 0, | |
3902 | q_vector->name, | |
3903 | q_vector); | |
3904 | if (err) { | |
3905 | dev_info(&pf->pdev->dev, | |
fb43201f | 3906 | "MSIX request_irq failed, error: %d\n", err); |
41c445ff JB |
3907 | goto free_queue_irqs; |
3908 | } | |
96db776a AB |
3909 | |
3910 | /* register for affinity change notifications */ | |
3911 | q_vector->affinity_notify.notify = i40e_irq_affinity_notify; | |
3912 | q_vector->affinity_notify.release = i40e_irq_affinity_release; | |
3913 | irq_set_affinity_notifier(irq_num, &q_vector->affinity_notify); | |
be664cbe JK |
3914 | /* Spread affinity hints out across online CPUs. |
3915 | * | |
3916 | * get_cpu_mask returns a static constant mask with | |
3917 | * a permanent lifetime so it's ok to pass to | |
d34c54d1 | 3918 | * irq_update_affinity_hint without making a copy. |
759dc4a7 | 3919 | */ |
be664cbe | 3920 | cpu = cpumask_local_spread(q_vector->v_idx, -1); |
d34c54d1 | 3921 | irq_update_affinity_hint(irq_num, get_cpu_mask(cpu)); |
41c445ff JB |
3922 | } |
3923 | ||
63741846 | 3924 | vsi->irqs_ready = true; |
41c445ff JB |
3925 | return 0; |
3926 | ||
3927 | free_queue_irqs: | |
3928 | while (vector) { | |
3929 | vector--; | |
96db776a AB |
3930 | irq_num = pf->msix_entries[base + vector].vector; |
3931 | irq_set_affinity_notifier(irq_num, NULL); | |
d34c54d1 | 3932 | irq_update_affinity_hint(irq_num, NULL); |
96db776a | 3933 | free_irq(irq_num, &vsi->q_vectors[vector]); |
41c445ff JB |
3934 | } |
3935 | return err; | |
3936 | } | |
3937 | ||
3938 | /** | |
3939 | * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI | |
3940 | * @vsi: the VSI being un-configured | |
3941 | **/ | |
3942 | static void i40e_vsi_disable_irq(struct i40e_vsi *vsi) | |
3943 | { | |
3944 | struct i40e_pf *pf = vsi->back; | |
3945 | struct i40e_hw *hw = &pf->hw; | |
3946 | int base = vsi->base_vector; | |
3947 | int i; | |
3948 | ||
2e5c26ea | 3949 | /* disable interrupt causation from each queue */ |
41c445ff | 3950 | for (i = 0; i < vsi->num_queue_pairs; i++) { |
2e5c26ea SN |
3951 | u32 val; |
3952 | ||
3953 | val = rd32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx)); | |
3954 | val &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK; | |
3955 | wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), val); | |
3956 | ||
3957 | val = rd32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx)); | |
3958 | val &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK; | |
3959 | wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), val); | |
3960 | ||
74608d17 BT |
3961 | if (!i40e_enabled_xdp_vsi(vsi)) |
3962 | continue; | |
3963 | wr32(hw, I40E_QINT_TQCTL(vsi->xdp_rings[i]->reg_idx), 0); | |
41c445ff JB |
3964 | } |
3965 | ||
2e5c26ea | 3966 | /* disable each interrupt */ |
41c445ff JB |
3967 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { |
3968 | for (i = vsi->base_vector; | |
3969 | i < (vsi->num_q_vectors + vsi->base_vector); i++) | |
3970 | wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0); | |
3971 | ||
3972 | i40e_flush(hw); | |
3973 | for (i = 0; i < vsi->num_q_vectors; i++) | |
3974 | synchronize_irq(pf->msix_entries[i + base].vector); | |
3975 | } else { | |
3976 | /* Legacy and MSI mode - this stops all interrupt handling */ | |
3977 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); | |
3978 | wr32(hw, I40E_PFINT_DYN_CTL0, 0); | |
3979 | i40e_flush(hw); | |
3980 | synchronize_irq(pf->pdev->irq); | |
3981 | } | |
3982 | } | |
3983 | ||
3984 | /** | |
3985 | * i40e_vsi_enable_irq - Enable IRQ for the given VSI | |
3986 | * @vsi: the VSI being configured | |
3987 | **/ | |
3988 | static int i40e_vsi_enable_irq(struct i40e_vsi *vsi) | |
3989 | { | |
3990 | struct i40e_pf *pf = vsi->back; | |
3991 | int i; | |
3992 | ||
3993 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
7845548d | 3994 | for (i = 0; i < vsi->num_q_vectors; i++) |
41c445ff JB |
3995 | i40e_irq_dynamic_enable(vsi, i); |
3996 | } else { | |
dbadbbe2 | 3997 | i40e_irq_dynamic_enable_icr0(pf); |
41c445ff JB |
3998 | } |
3999 | ||
1022cb6c | 4000 | i40e_flush(&pf->hw); |
41c445ff JB |
4001 | return 0; |
4002 | } | |
4003 | ||
4004 | /** | |
c17401a1 | 4005 | * i40e_free_misc_vector - Free the vector that handles non-queue events |
41c445ff JB |
4006 | * @pf: board private structure |
4007 | **/ | |
c17401a1 | 4008 | static void i40e_free_misc_vector(struct i40e_pf *pf) |
41c445ff JB |
4009 | { |
4010 | /* Disable ICR 0 */ | |
4011 | wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0); | |
4012 | i40e_flush(&pf->hw); | |
c17401a1 JK |
4013 | |
4014 | if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) { | |
4015 | synchronize_irq(pf->msix_entries[0].vector); | |
4016 | free_irq(pf->msix_entries[0].vector, pf); | |
4017 | clear_bit(__I40E_MISC_IRQ_REQUESTED, pf->state); | |
4018 | } | |
41c445ff JB |
4019 | } |
4020 | ||
4021 | /** | |
4022 | * i40e_intr - MSI/Legacy and non-queue interrupt handler | |
4023 | * @irq: interrupt number | |
4024 | * @data: pointer to a q_vector | |
4025 | * | |
4026 | * This is the handler used for all MSI/Legacy interrupts, and deals | |
4027 | * with both queue and non-queue interrupts. This is also used in | |
4028 | * MSIX mode to handle the non-queue interrupts. | |
4029 | **/ | |
4030 | static irqreturn_t i40e_intr(int irq, void *data) | |
4031 | { | |
4032 | struct i40e_pf *pf = (struct i40e_pf *)data; | |
4033 | struct i40e_hw *hw = &pf->hw; | |
5e823066 | 4034 | irqreturn_t ret = IRQ_NONE; |
41c445ff JB |
4035 | u32 icr0, icr0_remaining; |
4036 | u32 val, ena_mask; | |
4037 | ||
4038 | icr0 = rd32(hw, I40E_PFINT_ICR0); | |
5e823066 | 4039 | ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA); |
41c445ff | 4040 | |
116a57d4 SN |
4041 | /* if sharing a legacy IRQ, we might get called w/o an intr pending */ |
4042 | if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0) | |
5e823066 | 4043 | goto enable_intr; |
41c445ff | 4044 | |
cd92e72f SN |
4045 | /* if interrupt but no bits showing, must be SWINT */ |
4046 | if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) || | |
4047 | (icr0 & I40E_PFINT_ICR0_SWINT_MASK)) | |
4048 | pf->sw_int_count++; | |
4049 | ||
0d8e1439 | 4050 | if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && |
7642984b | 4051 | (icr0 & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) { |
0d8e1439 | 4052 | ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; |
23bb6dc3 | 4053 | dev_dbg(&pf->pdev->dev, "cleared PE_CRITERR\n"); |
7642984b | 4054 | set_bit(__I40E_CORE_RESET_REQUESTED, pf->state); |
0d8e1439 ASJ |
4055 | } |
4056 | ||
41c445ff JB |
4057 | /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */ |
4058 | if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) { | |
5d3465a1 AD |
4059 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
4060 | struct i40e_q_vector *q_vector = vsi->q_vectors[0]; | |
41c445ff | 4061 | |
a16ae2d5 ASJ |
4062 | /* We do not have a way to disarm Queue causes while leaving |
4063 | * interrupt enabled for all other causes, ideally | |
4064 | * interrupt should be disabled while we are in NAPI but | |
4065 | * this is not a performance path and napi_schedule() | |
4066 | * can deal with rescheduling. | |
4067 | */ | |
9e6c9c0f | 4068 | if (!test_bit(__I40E_DOWN, pf->state)) |
5d3465a1 | 4069 | napi_schedule_irqoff(&q_vector->napi); |
41c445ff JB |
4070 | } |
4071 | ||
4072 | if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { | |
4073 | ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
0da36b97 | 4074 | set_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state); |
6e93d0c9 | 4075 | i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n"); |
41c445ff JB |
4076 | } |
4077 | ||
4078 | if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) { | |
4079 | ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; | |
0da36b97 | 4080 | set_bit(__I40E_MDD_EVENT_PENDING, pf->state); |
41c445ff JB |
4081 | } |
4082 | ||
4083 | if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { | |
2980cbd4 SD |
4084 | /* disable any further VFLR event notifications */ |
4085 | if (test_bit(__I40E_VF_RESETS_DISABLED, pf->state)) { | |
4086 | u32 reg = rd32(hw, I40E_PFINT_ICR0_ENA); | |
4087 | ||
4088 | reg &= ~I40E_PFINT_ICR0_VFLR_MASK; | |
4089 | wr32(hw, I40E_PFINT_ICR0_ENA, reg); | |
4090 | } else { | |
4091 | ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK; | |
4092 | set_bit(__I40E_VFLR_EVENT_PENDING, pf->state); | |
4093 | } | |
41c445ff JB |
4094 | } |
4095 | ||
4096 | if (icr0 & I40E_PFINT_ICR0_GRST_MASK) { | |
0da36b97 JK |
4097 | if (!test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
4098 | set_bit(__I40E_RESET_INTR_RECEIVED, pf->state); | |
41c445ff JB |
4099 | ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK; |
4100 | val = rd32(hw, I40E_GLGEN_RSTAT); | |
4101 | val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK) | |
4102 | >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT; | |
4eb3f768 | 4103 | if (val == I40E_RESET_CORER) { |
41c445ff | 4104 | pf->corer_count++; |
4eb3f768 | 4105 | } else if (val == I40E_RESET_GLOBR) { |
41c445ff | 4106 | pf->globr_count++; |
4eb3f768 | 4107 | } else if (val == I40E_RESET_EMPR) { |
41c445ff | 4108 | pf->empr_count++; |
0da36b97 | 4109 | set_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state); |
4eb3f768 | 4110 | } |
41c445ff JB |
4111 | } |
4112 | ||
9c010ee0 ASJ |
4113 | if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) { |
4114 | icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK; | |
4115 | dev_info(&pf->pdev->dev, "HMC error interrupt\n"); | |
25fc0e65 ASJ |
4116 | dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n", |
4117 | rd32(hw, I40E_PFHMC_ERRORINFO), | |
4118 | rd32(hw, I40E_PFHMC_ERRORDATA)); | |
9c010ee0 ASJ |
4119 | } |
4120 | ||
beb0dff1 JK |
4121 | if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) { |
4122 | u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0); | |
4123 | ||
10507130 PK |
4124 | if (prttsyn_stat & I40E_PRTTSYN_STAT_0_EVENT0_MASK) |
4125 | schedule_work(&pf->ptp_extts0_work); | |
4126 | ||
4127 | if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) | |
beb0dff1 | 4128 | i40e_ptp_tx_hwtstamp(pf); |
10507130 PK |
4129 | |
4130 | icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; | |
beb0dff1 JK |
4131 | } |
4132 | ||
41c445ff JB |
4133 | /* If a critical error is pending we have no choice but to reset the |
4134 | * device. | |
4135 | * Report and mask out any remaining unexpected interrupts. | |
4136 | */ | |
4137 | icr0_remaining = icr0 & ena_mask; | |
4138 | if (icr0_remaining) { | |
4139 | dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n", | |
4140 | icr0_remaining); | |
9c010ee0 | 4141 | if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) || |
41c445ff | 4142 | (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) || |
c0c28975 | 4143 | (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) { |
9c010ee0 | 4144 | dev_info(&pf->pdev->dev, "device will be reset\n"); |
0da36b97 | 4145 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
9c010ee0 | 4146 | i40e_service_event_schedule(pf); |
41c445ff JB |
4147 | } |
4148 | ena_mask &= ~icr0_remaining; | |
4149 | } | |
5e823066 | 4150 | ret = IRQ_HANDLED; |
41c445ff | 4151 | |
5e823066 | 4152 | enable_intr: |
41c445ff JB |
4153 | /* re-enable interrupt causes */ |
4154 | wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask); | |
4ff0ee1a AM |
4155 | if (!test_bit(__I40E_DOWN, pf->state) || |
4156 | test_bit(__I40E_RECOVERY_MODE, pf->state)) { | |
41c445ff | 4157 | i40e_service_event_schedule(pf); |
dbadbbe2 | 4158 | i40e_irq_dynamic_enable_icr0(pf); |
41c445ff JB |
4159 | } |
4160 | ||
5e823066 | 4161 | return ret; |
41c445ff JB |
4162 | } |
4163 | ||
cbf61325 ASJ |
4164 | /** |
4165 | * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes | |
4166 | * @tx_ring: tx ring to clean | |
4167 | * @budget: how many cleans we're allowed | |
4168 | * | |
4169 | * Returns true if there's any budget left (e.g. the clean is finished) | |
4170 | **/ | |
4171 | static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget) | |
4172 | { | |
4173 | struct i40e_vsi *vsi = tx_ring->vsi; | |
4174 | u16 i = tx_ring->next_to_clean; | |
4175 | struct i40e_tx_buffer *tx_buf; | |
4176 | struct i40e_tx_desc *tx_desc; | |
4177 | ||
4178 | tx_buf = &tx_ring->tx_bi[i]; | |
4179 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
4180 | i -= tx_ring->count; | |
4181 | ||
4182 | do { | |
4183 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
4184 | ||
4185 | /* if next_to_watch is not set then there is no work pending */ | |
4186 | if (!eop_desc) | |
4187 | break; | |
4188 | ||
4189 | /* prevent any other reads prior to eop_desc */ | |
52c6912f | 4190 | smp_rmb(); |
cbf61325 ASJ |
4191 | |
4192 | /* if the descriptor isn't done, no work yet to do */ | |
4193 | if (!(eop_desc->cmd_type_offset_bsz & | |
4194 | cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE))) | |
4195 | break; | |
4196 | ||
4197 | /* clear next_to_watch to prevent false hangs */ | |
4198 | tx_buf->next_to_watch = NULL; | |
4199 | ||
49d7d933 ASJ |
4200 | tx_desc->buffer_addr = 0; |
4201 | tx_desc->cmd_type_offset_bsz = 0; | |
4202 | /* move past filter desc */ | |
4203 | tx_buf++; | |
4204 | tx_desc++; | |
4205 | i++; | |
4206 | if (unlikely(!i)) { | |
4207 | i -= tx_ring->count; | |
4208 | tx_buf = tx_ring->tx_bi; | |
4209 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
4210 | } | |
cbf61325 ASJ |
4211 | /* unmap skb header data */ |
4212 | dma_unmap_single(tx_ring->dev, | |
4213 | dma_unmap_addr(tx_buf, dma), | |
4214 | dma_unmap_len(tx_buf, len), | |
4215 | DMA_TO_DEVICE); | |
49d7d933 ASJ |
4216 | if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB) |
4217 | kfree(tx_buf->raw_buf); | |
cbf61325 | 4218 | |
49d7d933 ASJ |
4219 | tx_buf->raw_buf = NULL; |
4220 | tx_buf->tx_flags = 0; | |
4221 | tx_buf->next_to_watch = NULL; | |
cbf61325 | 4222 | dma_unmap_len_set(tx_buf, len, 0); |
49d7d933 ASJ |
4223 | tx_desc->buffer_addr = 0; |
4224 | tx_desc->cmd_type_offset_bsz = 0; | |
cbf61325 | 4225 | |
49d7d933 | 4226 | /* move us past the eop_desc for start of next FD desc */ |
cbf61325 ASJ |
4227 | tx_buf++; |
4228 | tx_desc++; | |
4229 | i++; | |
4230 | if (unlikely(!i)) { | |
4231 | i -= tx_ring->count; | |
4232 | tx_buf = tx_ring->tx_bi; | |
4233 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
4234 | } | |
4235 | ||
4236 | /* update budget accounting */ | |
4237 | budget--; | |
4238 | } while (likely(budget)); | |
4239 | ||
4240 | i += tx_ring->count; | |
4241 | tx_ring->next_to_clean = i; | |
4242 | ||
6995b36c | 4243 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) |
7845548d | 4244 | i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx); |
6995b36c | 4245 | |
cbf61325 ASJ |
4246 | return budget > 0; |
4247 | } | |
4248 | ||
4249 | /** | |
4250 | * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring | |
4251 | * @irq: interrupt number | |
4252 | * @data: pointer to a q_vector | |
4253 | **/ | |
4254 | static irqreturn_t i40e_fdir_clean_ring(int irq, void *data) | |
4255 | { | |
4256 | struct i40e_q_vector *q_vector = data; | |
4257 | struct i40e_vsi *vsi; | |
4258 | ||
4259 | if (!q_vector->tx.ring) | |
4260 | return IRQ_HANDLED; | |
4261 | ||
4262 | vsi = q_vector->tx.ring->vsi; | |
4263 | i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit); | |
4264 | ||
4265 | return IRQ_HANDLED; | |
4266 | } | |
4267 | ||
41c445ff | 4268 | /** |
cd0b6fa6 | 4269 | * i40e_map_vector_to_qp - Assigns the queue pair to the vector |
41c445ff JB |
4270 | * @vsi: the VSI being configured |
4271 | * @v_idx: vector index | |
cd0b6fa6 | 4272 | * @qp_idx: queue pair index |
41c445ff | 4273 | **/ |
26cdc443 | 4274 | static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx) |
41c445ff | 4275 | { |
493fb300 | 4276 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; |
9f65e15b AD |
4277 | struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx]; |
4278 | struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx]; | |
41c445ff JB |
4279 | |
4280 | tx_ring->q_vector = q_vector; | |
cd0b6fa6 AD |
4281 | tx_ring->next = q_vector->tx.ring; |
4282 | q_vector->tx.ring = tx_ring; | |
41c445ff | 4283 | q_vector->tx.count++; |
cd0b6fa6 | 4284 | |
74608d17 BT |
4285 | /* Place XDP Tx ring in the same q_vector ring list as regular Tx */ |
4286 | if (i40e_enabled_xdp_vsi(vsi)) { | |
4287 | struct i40e_ring *xdp_ring = vsi->xdp_rings[qp_idx]; | |
4288 | ||
4289 | xdp_ring->q_vector = q_vector; | |
4290 | xdp_ring->next = q_vector->tx.ring; | |
4291 | q_vector->tx.ring = xdp_ring; | |
4292 | q_vector->tx.count++; | |
4293 | } | |
4294 | ||
cd0b6fa6 AD |
4295 | rx_ring->q_vector = q_vector; |
4296 | rx_ring->next = q_vector->rx.ring; | |
4297 | q_vector->rx.ring = rx_ring; | |
4298 | q_vector->rx.count++; | |
41c445ff JB |
4299 | } |
4300 | ||
4301 | /** | |
4302 | * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors | |
4303 | * @vsi: the VSI being configured | |
4304 | * | |
4305 | * This function maps descriptor rings to the queue-specific vectors | |
4306 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
4307 | * one vector per queue pair, but on a constrained vector budget, we | |
4308 | * group the queue pairs as "efficiently" as possible. | |
4309 | **/ | |
4310 | static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi) | |
4311 | { | |
4312 | int qp_remaining = vsi->num_queue_pairs; | |
4313 | int q_vectors = vsi->num_q_vectors; | |
cd0b6fa6 | 4314 | int num_ringpairs; |
41c445ff JB |
4315 | int v_start = 0; |
4316 | int qp_idx = 0; | |
4317 | ||
4318 | /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to | |
4319 | * group them so there are multiple queues per vector. | |
70114ec4 ASJ |
4320 | * It is also important to go through all the vectors available to be |
4321 | * sure that if we don't use all the vectors, that the remaining vectors | |
4322 | * are cleared. This is especially important when decreasing the | |
4323 | * number of queues in use. | |
41c445ff | 4324 | */ |
70114ec4 | 4325 | for (; v_start < q_vectors; v_start++) { |
cd0b6fa6 AD |
4326 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_start]; |
4327 | ||
4328 | num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start); | |
4329 | ||
4330 | q_vector->num_ringpairs = num_ringpairs; | |
a3f9fb5e | 4331 | q_vector->reg_idx = q_vector->v_idx + vsi->base_vector - 1; |
cd0b6fa6 AD |
4332 | |
4333 | q_vector->rx.count = 0; | |
4334 | q_vector->tx.count = 0; | |
4335 | q_vector->rx.ring = NULL; | |
4336 | q_vector->tx.ring = NULL; | |
4337 | ||
4338 | while (num_ringpairs--) { | |
26cdc443 | 4339 | i40e_map_vector_to_qp(vsi, v_start, qp_idx); |
cd0b6fa6 AD |
4340 | qp_idx++; |
4341 | qp_remaining--; | |
41c445ff JB |
4342 | } |
4343 | } | |
4344 | } | |
4345 | ||
4346 | /** | |
4347 | * i40e_vsi_request_irq - Request IRQ from the OS | |
4348 | * @vsi: the VSI being configured | |
4349 | * @basename: name for the vector | |
4350 | **/ | |
4351 | static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename) | |
4352 | { | |
4353 | struct i40e_pf *pf = vsi->back; | |
4354 | int err; | |
4355 | ||
4356 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
4357 | err = i40e_vsi_request_irq_msix(vsi, basename); | |
4358 | else if (pf->flags & I40E_FLAG_MSI_ENABLED) | |
4359 | err = request_irq(pf->pdev->irq, i40e_intr, 0, | |
b294ac70 | 4360 | pf->int_name, pf); |
41c445ff JB |
4361 | else |
4362 | err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED, | |
b294ac70 | 4363 | pf->int_name, pf); |
41c445ff JB |
4364 | |
4365 | if (err) | |
4366 | dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err); | |
4367 | ||
4368 | return err; | |
4369 | } | |
4370 | ||
4371 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
4372 | /** | |
d89d967f | 4373 | * i40e_netpoll - A Polling 'interrupt' handler |
41c445ff JB |
4374 | * @netdev: network interface device structure |
4375 | * | |
4376 | * This is used by netconsole to send skbs without having to re-enable | |
4377 | * interrupts. It's not called while the normal interrupt routine is executing. | |
4378 | **/ | |
4379 | static void i40e_netpoll(struct net_device *netdev) | |
4380 | { | |
4381 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
4382 | struct i40e_vsi *vsi = np->vsi; | |
4383 | struct i40e_pf *pf = vsi->back; | |
4384 | int i; | |
4385 | ||
4386 | /* if interface is down do nothing */ | |
0da36b97 | 4387 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) |
41c445ff JB |
4388 | return; |
4389 | ||
41c445ff JB |
4390 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { |
4391 | for (i = 0; i < vsi->num_q_vectors; i++) | |
493fb300 | 4392 | i40e_msix_clean_rings(0, vsi->q_vectors[i]); |
41c445ff JB |
4393 | } else { |
4394 | i40e_intr(pf->pdev->irq, netdev); | |
4395 | } | |
41c445ff JB |
4396 | } |
4397 | #endif | |
4398 | ||
c768e490 JK |
4399 | #define I40E_QTX_ENA_WAIT_COUNT 50 |
4400 | ||
23527308 NP |
4401 | /** |
4402 | * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled | |
4403 | * @pf: the PF being configured | |
4404 | * @pf_q: the PF queue | |
4405 | * @enable: enable or disable state of the queue | |
4406 | * | |
4407 | * This routine will wait for the given Tx queue of the PF to reach the | |
4408 | * enabled or disabled state. | |
4409 | * Returns -ETIMEDOUT in case of failing to reach the requested state after | |
4410 | * multiple retries; else will return 0 in case of success. | |
4411 | **/ | |
4412 | static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable) | |
4413 | { | |
4414 | int i; | |
4415 | u32 tx_reg; | |
4416 | ||
4417 | for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { | |
4418 | tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q)); | |
4419 | if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) | |
4420 | break; | |
4421 | ||
f98a2006 | 4422 | usleep_range(10, 20); |
23527308 NP |
4423 | } |
4424 | if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) | |
4425 | return -ETIMEDOUT; | |
4426 | ||
4427 | return 0; | |
4428 | } | |
4429 | ||
c768e490 JK |
4430 | /** |
4431 | * i40e_control_tx_q - Start or stop a particular Tx queue | |
4432 | * @pf: the PF structure | |
4433 | * @pf_q: the PF queue to configure | |
4434 | * @enable: start or stop the queue | |
4435 | * | |
4436 | * This function enables or disables a single queue. Note that any delay | |
4437 | * required after the operation is expected to be handled by the caller of | |
4438 | * this function. | |
4439 | **/ | |
4440 | static void i40e_control_tx_q(struct i40e_pf *pf, int pf_q, bool enable) | |
4441 | { | |
4442 | struct i40e_hw *hw = &pf->hw; | |
4443 | u32 tx_reg; | |
4444 | int i; | |
4445 | ||
4446 | /* warn the TX unit of coming changes */ | |
4447 | i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable); | |
4448 | if (!enable) | |
4449 | usleep_range(10, 20); | |
4450 | ||
4451 | for (i = 0; i < I40E_QTX_ENA_WAIT_COUNT; i++) { | |
4452 | tx_reg = rd32(hw, I40E_QTX_ENA(pf_q)); | |
4453 | if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) == | |
4454 | ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1)) | |
4455 | break; | |
4456 | usleep_range(1000, 2000); | |
4457 | } | |
4458 | ||
4459 | /* Skip if the queue is already in the requested state */ | |
4460 | if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) | |
4461 | return; | |
4462 | ||
4463 | /* turn on/off the queue */ | |
4464 | if (enable) { | |
4465 | wr32(hw, I40E_QTX_HEAD(pf_q), 0); | |
4466 | tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK; | |
4467 | } else { | |
4468 | tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; | |
4469 | } | |
4470 | ||
4471 | wr32(hw, I40E_QTX_ENA(pf_q), tx_reg); | |
4472 | } | |
4473 | ||
74608d17 BT |
4474 | /** |
4475 | * i40e_control_wait_tx_q - Start/stop Tx queue and wait for completion | |
4476 | * @seid: VSI SEID | |
4477 | * @pf: the PF structure | |
4478 | * @pf_q: the PF queue to configure | |
4479 | * @is_xdp: true if the queue is used for XDP | |
4480 | * @enable: start or stop the queue | |
4481 | **/ | |
d0fda04d HR |
4482 | int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, |
4483 | bool is_xdp, bool enable) | |
74608d17 BT |
4484 | { |
4485 | int ret; | |
4486 | ||
4487 | i40e_control_tx_q(pf, pf_q, enable); | |
4488 | ||
4489 | /* wait for the change to finish */ | |
4490 | ret = i40e_pf_txq_wait(pf, pf_q, enable); | |
4491 | if (ret) { | |
4492 | dev_info(&pf->pdev->dev, | |
4493 | "VSI seid %d %sTx ring %d %sable timeout\n", | |
4494 | seid, (is_xdp ? "XDP " : ""), pf_q, | |
4495 | (enable ? "en" : "dis")); | |
4496 | } | |
4497 | ||
4498 | return ret; | |
4499 | } | |
4500 | ||
41c445ff | 4501 | /** |
65662a8d | 4502 | * i40e_vsi_enable_tx - Start a VSI's rings |
41c445ff | 4503 | * @vsi: the VSI being configured |
41c445ff | 4504 | **/ |
65662a8d | 4505 | static int i40e_vsi_enable_tx(struct i40e_vsi *vsi) |
41c445ff JB |
4506 | { |
4507 | struct i40e_pf *pf = vsi->back; | |
c768e490 | 4508 | int i, pf_q, ret = 0; |
41c445ff JB |
4509 | |
4510 | pf_q = vsi->base_queue; | |
4511 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
74608d17 BT |
4512 | ret = i40e_control_wait_tx_q(vsi->seid, pf, |
4513 | pf_q, | |
65662a8d | 4514 | false /*is xdp*/, true); |
74608d17 BT |
4515 | if (ret) |
4516 | break; | |
351499ab | 4517 | |
74608d17 BT |
4518 | if (!i40e_enabled_xdp_vsi(vsi)) |
4519 | continue; | |
4520 | ||
4521 | ret = i40e_control_wait_tx_q(vsi->seid, pf, | |
4522 | pf_q + vsi->alloc_queue_pairs, | |
65662a8d | 4523 | true /*is xdp*/, true); |
74608d17 | 4524 | if (ret) |
23527308 | 4525 | break; |
41c445ff | 4526 | } |
23527308 NP |
4527 | return ret; |
4528 | } | |
4529 | ||
4530 | /** | |
4531 | * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled | |
4532 | * @pf: the PF being configured | |
4533 | * @pf_q: the PF queue | |
4534 | * @enable: enable or disable state of the queue | |
4535 | * | |
4536 | * This routine will wait for the given Rx queue of the PF to reach the | |
4537 | * enabled or disabled state. | |
4538 | * Returns -ETIMEDOUT in case of failing to reach the requested state after | |
4539 | * multiple retries; else will return 0 in case of success. | |
4540 | **/ | |
4541 | static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable) | |
4542 | { | |
4543 | int i; | |
4544 | u32 rx_reg; | |
4545 | ||
4546 | for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { | |
4547 | rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q)); | |
4548 | if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) | |
4549 | break; | |
4550 | ||
f98a2006 | 4551 | usleep_range(10, 20); |
23527308 NP |
4552 | } |
4553 | if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) | |
4554 | return -ETIMEDOUT; | |
7134f9ce | 4555 | |
41c445ff JB |
4556 | return 0; |
4557 | } | |
4558 | ||
c768e490 JK |
4559 | /** |
4560 | * i40e_control_rx_q - Start or stop a particular Rx queue | |
4561 | * @pf: the PF structure | |
4562 | * @pf_q: the PF queue to configure | |
4563 | * @enable: start or stop the queue | |
4564 | * | |
d0fda04d HR |
4565 | * This function enables or disables a single queue. Note that |
4566 | * any delay required after the operation is expected to be | |
4567 | * handled by the caller of this function. | |
c768e490 JK |
4568 | **/ |
4569 | static void i40e_control_rx_q(struct i40e_pf *pf, int pf_q, bool enable) | |
4570 | { | |
4571 | struct i40e_hw *hw = &pf->hw; | |
4572 | u32 rx_reg; | |
4573 | int i; | |
4574 | ||
4575 | for (i = 0; i < I40E_QTX_ENA_WAIT_COUNT; i++) { | |
4576 | rx_reg = rd32(hw, I40E_QRX_ENA(pf_q)); | |
4577 | if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) == | |
4578 | ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1)) | |
4579 | break; | |
4580 | usleep_range(1000, 2000); | |
4581 | } | |
4582 | ||
4583 | /* Skip if the queue is already in the requested state */ | |
4584 | if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) | |
4585 | return; | |
4586 | ||
4587 | /* turn on/off the queue */ | |
4588 | if (enable) | |
4589 | rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK; | |
4590 | else | |
4591 | rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; | |
4592 | ||
4593 | wr32(hw, I40E_QRX_ENA(pf_q), rx_reg); | |
4594 | } | |
4595 | ||
d0fda04d HR |
4596 | /** |
4597 | * i40e_control_wait_rx_q | |
4598 | * @pf: the PF structure | |
4599 | * @pf_q: queue being configured | |
4600 | * @enable: start or stop the rings | |
4601 | * | |
4602 | * This function enables or disables a single queue along with waiting | |
4603 | * for the change to finish. The caller of this function should handle | |
4604 | * the delays needed in the case of disabling queues. | |
4605 | **/ | |
4606 | int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable) | |
4607 | { | |
4608 | int ret = 0; | |
4609 | ||
4610 | i40e_control_rx_q(pf, pf_q, enable); | |
4611 | ||
4612 | /* wait for the change to finish */ | |
4613 | ret = i40e_pf_rxq_wait(pf, pf_q, enable); | |
4614 | if (ret) | |
4615 | return ret; | |
4616 | ||
4617 | return ret; | |
4618 | } | |
4619 | ||
41c445ff | 4620 | /** |
65662a8d | 4621 | * i40e_vsi_enable_rx - Start a VSI's rings |
41c445ff | 4622 | * @vsi: the VSI being configured |
41c445ff | 4623 | **/ |
65662a8d | 4624 | static int i40e_vsi_enable_rx(struct i40e_vsi *vsi) |
41c445ff JB |
4625 | { |
4626 | struct i40e_pf *pf = vsi->back; | |
c768e490 | 4627 | int i, pf_q, ret = 0; |
41c445ff JB |
4628 | |
4629 | pf_q = vsi->base_queue; | |
4630 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
65662a8d | 4631 | ret = i40e_control_wait_rx_q(pf, pf_q, true); |
23527308 NP |
4632 | if (ret) { |
4633 | dev_info(&pf->pdev->dev, | |
65662a8d AK |
4634 | "VSI seid %d Rx ring %d enable timeout\n", |
4635 | vsi->seid, pf_q); | |
23527308 | 4636 | break; |
41c445ff JB |
4637 | } |
4638 | } | |
4639 | ||
23527308 | 4640 | return ret; |
41c445ff JB |
4641 | } |
4642 | ||
4643 | /** | |
3aa7b74d | 4644 | * i40e_vsi_start_rings - Start a VSI's rings |
41c445ff | 4645 | * @vsi: the VSI being configured |
41c445ff | 4646 | **/ |
3aa7b74d | 4647 | int i40e_vsi_start_rings(struct i40e_vsi *vsi) |
41c445ff | 4648 | { |
3b867b28 | 4649 | int ret = 0; |
41c445ff JB |
4650 | |
4651 | /* do rx first for enable and last for disable */ | |
65662a8d | 4652 | ret = i40e_vsi_enable_rx(vsi); |
3aa7b74d FS |
4653 | if (ret) |
4654 | return ret; | |
65662a8d | 4655 | ret = i40e_vsi_enable_tx(vsi); |
41c445ff JB |
4656 | |
4657 | return ret; | |
4658 | } | |
4659 | ||
65662a8d AK |
4660 | #define I40E_DISABLE_TX_GAP_MSEC 50 |
4661 | ||
3aa7b74d FS |
4662 | /** |
4663 | * i40e_vsi_stop_rings - Stop a VSI's rings | |
4664 | * @vsi: the VSI being configured | |
4665 | **/ | |
4666 | void i40e_vsi_stop_rings(struct i40e_vsi *vsi) | |
4667 | { | |
65662a8d AK |
4668 | struct i40e_pf *pf = vsi->back; |
4669 | int pf_q, err, q_end; | |
4670 | ||
3480756f | 4671 | /* When port TX is suspended, don't wait */ |
0da36b97 | 4672 | if (test_bit(__I40E_PORT_SUSPENDED, vsi->back->state)) |
3480756f JK |
4673 | return i40e_vsi_stop_rings_no_wait(vsi); |
4674 | ||
65662a8d AK |
4675 | q_end = vsi->base_queue + vsi->num_queue_pairs; |
4676 | for (pf_q = vsi->base_queue; pf_q < q_end; pf_q++) | |
4677 | i40e_pre_tx_queue_cfg(&pf->hw, (u32)pf_q, false); | |
4678 | ||
4679 | for (pf_q = vsi->base_queue; pf_q < q_end; pf_q++) { | |
4680 | err = i40e_control_wait_rx_q(pf, pf_q, false); | |
4681 | if (err) | |
4682 | dev_info(&pf->pdev->dev, | |
6e9078a6 | 4683 | "VSI seid %d Rx ring %d disable timeout\n", |
65662a8d AK |
4684 | vsi->seid, pf_q); |
4685 | } | |
4686 | ||
4687 | msleep(I40E_DISABLE_TX_GAP_MSEC); | |
4688 | pf_q = vsi->base_queue; | |
4689 | for (pf_q = vsi->base_queue; pf_q < q_end; pf_q++) | |
4690 | wr32(&pf->hw, I40E_QTX_ENA(pf_q), 0); | |
4691 | ||
4692 | i40e_vsi_wait_queues_disabled(vsi); | |
3aa7b74d FS |
4693 | } |
4694 | ||
e4b433f4 JK |
4695 | /** |
4696 | * i40e_vsi_stop_rings_no_wait - Stop a VSI's rings and do not delay | |
4697 | * @vsi: the VSI being shutdown | |
4698 | * | |
4699 | * This function stops all the rings for a VSI but does not delay to verify | |
4700 | * that rings have been disabled. It is expected that the caller is shutting | |
4701 | * down multiple VSIs at once and will delay together for all the VSIs after | |
4702 | * initiating the shutdown. This is particularly useful for shutting down lots | |
4703 | * of VFs together. Otherwise, a large delay can be incurred while configuring | |
4704 | * each VSI in serial. | |
4705 | **/ | |
4706 | void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi) | |
4707 | { | |
4708 | struct i40e_pf *pf = vsi->back; | |
4709 | int i, pf_q; | |
4710 | ||
4711 | pf_q = vsi->base_queue; | |
4712 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
4713 | i40e_control_tx_q(pf, pf_q, false); | |
4714 | i40e_control_rx_q(pf, pf_q, false); | |
4715 | } | |
4716 | } | |
4717 | ||
41c445ff JB |
4718 | /** |
4719 | * i40e_vsi_free_irq - Free the irq association with the OS | |
4720 | * @vsi: the VSI being configured | |
4721 | **/ | |
4722 | static void i40e_vsi_free_irq(struct i40e_vsi *vsi) | |
4723 | { | |
4724 | struct i40e_pf *pf = vsi->back; | |
4725 | struct i40e_hw *hw = &pf->hw; | |
4726 | int base = vsi->base_vector; | |
4727 | u32 val, qp; | |
4728 | int i; | |
4729 | ||
4730 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
4731 | if (!vsi->q_vectors) | |
4732 | return; | |
4733 | ||
63741846 SN |
4734 | if (!vsi->irqs_ready) |
4735 | return; | |
4736 | ||
4737 | vsi->irqs_ready = false; | |
41c445ff | 4738 | for (i = 0; i < vsi->num_q_vectors; i++) { |
96db776a AB |
4739 | int irq_num; |
4740 | u16 vector; | |
4741 | ||
4742 | vector = i + base; | |
4743 | irq_num = pf->msix_entries[vector].vector; | |
41c445ff JB |
4744 | |
4745 | /* free only the irqs that were actually requested */ | |
78681b1f SN |
4746 | if (!vsi->q_vectors[i] || |
4747 | !vsi->q_vectors[i]->num_ringpairs) | |
41c445ff JB |
4748 | continue; |
4749 | ||
96db776a AB |
4750 | /* clear the affinity notifier in the IRQ descriptor */ |
4751 | irq_set_affinity_notifier(irq_num, NULL); | |
759dc4a7 | 4752 | /* remove our suggested affinity mask for this IRQ */ |
d34c54d1 | 4753 | irq_update_affinity_hint(irq_num, NULL); |
96db776a AB |
4754 | synchronize_irq(irq_num); |
4755 | free_irq(irq_num, vsi->q_vectors[i]); | |
41c445ff JB |
4756 | |
4757 | /* Tear down the interrupt queue link list | |
4758 | * | |
4759 | * We know that they come in pairs and always | |
4760 | * the Rx first, then the Tx. To clear the | |
4761 | * link list, stick the EOL value into the | |
4762 | * next_q field of the registers. | |
4763 | */ | |
4764 | val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1)); | |
4765 | qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) | |
4766 | >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4767 | val |= I40E_QUEUE_END_OF_LIST | |
4768 | << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4769 | wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val); | |
4770 | ||
4771 | while (qp != I40E_QUEUE_END_OF_LIST) { | |
4772 | u32 next; | |
4773 | ||
4774 | val = rd32(hw, I40E_QINT_RQCTL(qp)); | |
4775 | ||
4776 | val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | | |
4777 | I40E_QINT_RQCTL_MSIX0_INDX_MASK | | |
4778 | I40E_QINT_RQCTL_CAUSE_ENA_MASK | | |
4779 | I40E_QINT_RQCTL_INTEVENT_MASK); | |
4780 | ||
4781 | val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | | |
4782 | I40E_QINT_RQCTL_NEXTQ_INDX_MASK); | |
4783 | ||
4784 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
4785 | ||
4786 | val = rd32(hw, I40E_QINT_TQCTL(qp)); | |
4787 | ||
4788 | next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK) | |
4789 | >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT; | |
4790 | ||
4791 | val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | | |
4792 | I40E_QINT_TQCTL_MSIX0_INDX_MASK | | |
4793 | I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
4794 | I40E_QINT_TQCTL_INTEVENT_MASK); | |
4795 | ||
4796 | val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | | |
4797 | I40E_QINT_TQCTL_NEXTQ_INDX_MASK); | |
4798 | ||
4799 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
4800 | qp = next; | |
4801 | } | |
4802 | } | |
4803 | } else { | |
4804 | free_irq(pf->pdev->irq, pf); | |
4805 | ||
4806 | val = rd32(hw, I40E_PFINT_LNKLST0); | |
4807 | qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) | |
4808 | >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4809 | val |= I40E_QUEUE_END_OF_LIST | |
4810 | << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; | |
4811 | wr32(hw, I40E_PFINT_LNKLST0, val); | |
4812 | ||
4813 | val = rd32(hw, I40E_QINT_RQCTL(qp)); | |
4814 | val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | | |
4815 | I40E_QINT_RQCTL_MSIX0_INDX_MASK | | |
4816 | I40E_QINT_RQCTL_CAUSE_ENA_MASK | | |
4817 | I40E_QINT_RQCTL_INTEVENT_MASK); | |
4818 | ||
4819 | val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | | |
4820 | I40E_QINT_RQCTL_NEXTQ_INDX_MASK); | |
4821 | ||
4822 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
4823 | ||
4824 | val = rd32(hw, I40E_QINT_TQCTL(qp)); | |
4825 | ||
4826 | val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | | |
4827 | I40E_QINT_TQCTL_MSIX0_INDX_MASK | | |
4828 | I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
4829 | I40E_QINT_TQCTL_INTEVENT_MASK); | |
4830 | ||
4831 | val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | | |
4832 | I40E_QINT_TQCTL_NEXTQ_INDX_MASK); | |
4833 | ||
4834 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
4835 | } | |
4836 | } | |
4837 | ||
493fb300 AD |
4838 | /** |
4839 | * i40e_free_q_vector - Free memory allocated for specific interrupt vector | |
4840 | * @vsi: the VSI being configured | |
4841 | * @v_idx: Index of vector to be freed | |
4842 | * | |
4843 | * This function frees the memory allocated to the q_vector. In addition if | |
4844 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4845 | * to freeing the q_vector. | |
4846 | **/ | |
4847 | static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx) | |
4848 | { | |
4849 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; | |
cd0b6fa6 | 4850 | struct i40e_ring *ring; |
493fb300 AD |
4851 | |
4852 | if (!q_vector) | |
4853 | return; | |
4854 | ||
4855 | /* disassociate q_vector from rings */ | |
cd0b6fa6 AD |
4856 | i40e_for_each_ring(ring, q_vector->tx) |
4857 | ring->q_vector = NULL; | |
4858 | ||
4859 | i40e_for_each_ring(ring, q_vector->rx) | |
4860 | ring->q_vector = NULL; | |
493fb300 AD |
4861 | |
4862 | /* only VSI w/ an associated netdev is set up w/ NAPI */ | |
4863 | if (vsi->netdev) | |
4864 | netif_napi_del(&q_vector->napi); | |
4865 | ||
4866 | vsi->q_vectors[v_idx] = NULL; | |
4867 | ||
4868 | kfree_rcu(q_vector, rcu); | |
4869 | } | |
4870 | ||
41c445ff JB |
4871 | /** |
4872 | * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors | |
4873 | * @vsi: the VSI being un-configured | |
4874 | * | |
4875 | * This frees the memory allocated to the q_vectors and | |
4876 | * deletes references to the NAPI struct. | |
4877 | **/ | |
4878 | static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi) | |
4879 | { | |
4880 | int v_idx; | |
4881 | ||
493fb300 AD |
4882 | for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) |
4883 | i40e_free_q_vector(vsi, v_idx); | |
41c445ff JB |
4884 | } |
4885 | ||
4886 | /** | |
4887 | * i40e_reset_interrupt_capability - Disable interrupt setup in OS | |
4888 | * @pf: board private structure | |
4889 | **/ | |
4890 | static void i40e_reset_interrupt_capability(struct i40e_pf *pf) | |
4891 | { | |
4892 | /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */ | |
4893 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
4894 | pci_disable_msix(pf->pdev); | |
4895 | kfree(pf->msix_entries); | |
4896 | pf->msix_entries = NULL; | |
3b444399 SN |
4897 | kfree(pf->irq_pile); |
4898 | pf->irq_pile = NULL; | |
41c445ff JB |
4899 | } else if (pf->flags & I40E_FLAG_MSI_ENABLED) { |
4900 | pci_disable_msi(pf->pdev); | |
4901 | } | |
4902 | pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED); | |
4903 | } | |
4904 | ||
4905 | /** | |
4906 | * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
4907 | * @pf: board private structure | |
4908 | * | |
4909 | * We go through and clear interrupt specific resources and reset the structure | |
4910 | * to pre-load conditions | |
4911 | **/ | |
4912 | static void i40e_clear_interrupt_scheme(struct i40e_pf *pf) | |
4913 | { | |
4914 | int i; | |
4915 | ||
2e5a2057 SD |
4916 | if (test_bit(__I40E_MISC_IRQ_REQUESTED, pf->state)) |
4917 | i40e_free_misc_vector(pf); | |
e147758d | 4918 | |
e3219ce6 ASJ |
4919 | i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector, |
4920 | I40E_IWARP_IRQ_PILE_ID); | |
4921 | ||
41c445ff | 4922 | i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1); |
505682cd | 4923 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
4924 | if (pf->vsi[i]) |
4925 | i40e_vsi_free_q_vectors(pf->vsi[i]); | |
4926 | i40e_reset_interrupt_capability(pf); | |
4927 | } | |
4928 | ||
4929 | /** | |
4930 | * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI | |
4931 | * @vsi: the VSI being configured | |
4932 | **/ | |
4933 | static void i40e_napi_enable_all(struct i40e_vsi *vsi) | |
4934 | { | |
4935 | int q_idx; | |
4936 | ||
4937 | if (!vsi->netdev) | |
4938 | return; | |
4939 | ||
13a8cd19 AD |
4940 | for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) { |
4941 | struct i40e_q_vector *q_vector = vsi->q_vectors[q_idx]; | |
4942 | ||
4943 | if (q_vector->rx.ring || q_vector->tx.ring) | |
4944 | napi_enable(&q_vector->napi); | |
4945 | } | |
41c445ff JB |
4946 | } |
4947 | ||
4948 | /** | |
4949 | * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI | |
4950 | * @vsi: the VSI being configured | |
4951 | **/ | |
4952 | static void i40e_napi_disable_all(struct i40e_vsi *vsi) | |
4953 | { | |
4954 | int q_idx; | |
4955 | ||
4956 | if (!vsi->netdev) | |
4957 | return; | |
4958 | ||
13a8cd19 AD |
4959 | for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) { |
4960 | struct i40e_q_vector *q_vector = vsi->q_vectors[q_idx]; | |
4961 | ||
4962 | if (q_vector->rx.ring || q_vector->tx.ring) | |
4963 | napi_disable(&q_vector->napi); | |
4964 | } | |
41c445ff JB |
4965 | } |
4966 | ||
90ef8d47 SN |
4967 | /** |
4968 | * i40e_vsi_close - Shut down a VSI | |
4969 | * @vsi: the vsi to be quelled | |
4970 | **/ | |
4971 | static void i40e_vsi_close(struct i40e_vsi *vsi) | |
4972 | { | |
0ef2d5af | 4973 | struct i40e_pf *pf = vsi->back; |
0da36b97 | 4974 | if (!test_and_set_bit(__I40E_VSI_DOWN, vsi->state)) |
90ef8d47 SN |
4975 | i40e_down(vsi); |
4976 | i40e_vsi_free_irq(vsi); | |
4977 | i40e_vsi_free_tx_resources(vsi); | |
4978 | i40e_vsi_free_rx_resources(vsi); | |
92faef85 | 4979 | vsi->current_netdev_flags = 0; |
5f76a704 | 4980 | set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state); |
0da36b97 | 4981 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
5f76a704 | 4982 | set_bit(__I40E_CLIENT_RESET, pf->state); |
90ef8d47 SN |
4983 | } |
4984 | ||
41c445ff JB |
4985 | /** |
4986 | * i40e_quiesce_vsi - Pause a given VSI | |
4987 | * @vsi: the VSI being paused | |
4988 | **/ | |
4989 | static void i40e_quiesce_vsi(struct i40e_vsi *vsi) | |
4990 | { | |
0da36b97 | 4991 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) |
41c445ff JB |
4992 | return; |
4993 | ||
0da36b97 | 4994 | set_bit(__I40E_VSI_NEEDS_RESTART, vsi->state); |
6995b36c | 4995 | if (vsi->netdev && netif_running(vsi->netdev)) |
41c445ff | 4996 | vsi->netdev->netdev_ops->ndo_stop(vsi->netdev); |
6995b36c | 4997 | else |
90ef8d47 | 4998 | i40e_vsi_close(vsi); |
41c445ff JB |
4999 | } |
5000 | ||
5001 | /** | |
5002 | * i40e_unquiesce_vsi - Resume a given VSI | |
5003 | * @vsi: the VSI being resumed | |
5004 | **/ | |
5005 | static void i40e_unquiesce_vsi(struct i40e_vsi *vsi) | |
5006 | { | |
0da36b97 | 5007 | if (!test_and_clear_bit(__I40E_VSI_NEEDS_RESTART, vsi->state)) |
41c445ff JB |
5008 | return; |
5009 | ||
41c445ff JB |
5010 | if (vsi->netdev && netif_running(vsi->netdev)) |
5011 | vsi->netdev->netdev_ops->ndo_open(vsi->netdev); | |
5012 | else | |
8276f757 | 5013 | i40e_vsi_open(vsi); /* this clears the DOWN bit */ |
41c445ff JB |
5014 | } |
5015 | ||
5016 | /** | |
5017 | * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF | |
5018 | * @pf: the PF | |
5019 | **/ | |
5020 | static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf) | |
5021 | { | |
5022 | int v; | |
5023 | ||
505682cd | 5024 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
5025 | if (pf->vsi[v]) |
5026 | i40e_quiesce_vsi(pf->vsi[v]); | |
5027 | } | |
5028 | } | |
5029 | ||
5030 | /** | |
5031 | * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF | |
5032 | * @pf: the PF | |
5033 | **/ | |
5034 | static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf) | |
5035 | { | |
5036 | int v; | |
5037 | ||
505682cd | 5038 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
5039 | if (pf->vsi[v]) |
5040 | i40e_unquiesce_vsi(pf->vsi[v]); | |
5041 | } | |
5042 | } | |
5043 | ||
69129dc3 | 5044 | /** |
3fe06f41 | 5045 | * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled |
69129dc3 NP |
5046 | * @vsi: the VSI being configured |
5047 | * | |
af26ce2d | 5048 | * Wait until all queues on a given VSI have been disabled. |
69129dc3 | 5049 | **/ |
e4b433f4 | 5050 | int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi) |
69129dc3 NP |
5051 | { |
5052 | struct i40e_pf *pf = vsi->back; | |
5053 | int i, pf_q, ret; | |
5054 | ||
5055 | pf_q = vsi->base_queue; | |
5056 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
af26ce2d | 5057 | /* Check and wait for the Tx queue */ |
69129dc3 NP |
5058 | ret = i40e_pf_txq_wait(pf, pf_q, false); |
5059 | if (ret) { | |
5060 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
5061 | "VSI seid %d Tx ring %d disable timeout\n", |
5062 | vsi->seid, pf_q); | |
69129dc3 NP |
5063 | return ret; |
5064 | } | |
74608d17 BT |
5065 | |
5066 | if (!i40e_enabled_xdp_vsi(vsi)) | |
5067 | goto wait_rx; | |
5068 | ||
5069 | /* Check and wait for the XDP Tx queue */ | |
5070 | ret = i40e_pf_txq_wait(pf, pf_q + vsi->alloc_queue_pairs, | |
5071 | false); | |
5072 | if (ret) { | |
5073 | dev_info(&pf->pdev->dev, | |
5074 | "VSI seid %d XDP Tx ring %d disable timeout\n", | |
5075 | vsi->seid, pf_q); | |
5076 | return ret; | |
5077 | } | |
5078 | wait_rx: | |
5079 | /* Check and wait for the Rx queue */ | |
3fe06f41 NP |
5080 | ret = i40e_pf_rxq_wait(pf, pf_q, false); |
5081 | if (ret) { | |
5082 | dev_info(&pf->pdev->dev, | |
5083 | "VSI seid %d Rx ring %d disable timeout\n", | |
5084 | vsi->seid, pf_q); | |
5085 | return ret; | |
5086 | } | |
5087 | } | |
5088 | ||
69129dc3 NP |
5089 | return 0; |
5090 | } | |
5091 | ||
e4b433f4 | 5092 | #ifdef CONFIG_I40E_DCB |
69129dc3 | 5093 | /** |
3fe06f41 | 5094 | * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled |
69129dc3 NP |
5095 | * @pf: the PF |
5096 | * | |
3fe06f41 | 5097 | * This function waits for the queues to be in disabled state for all the |
69129dc3 NP |
5098 | * VSIs that are managed by this PF. |
5099 | **/ | |
3fe06f41 | 5100 | static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf) |
69129dc3 NP |
5101 | { |
5102 | int v, ret = 0; | |
5103 | ||
5104 | for (v = 0; v < pf->hw.func_caps.num_vsis; v++) { | |
c76cb6ed | 5105 | if (pf->vsi[v]) { |
3fe06f41 | 5106 | ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]); |
69129dc3 NP |
5107 | if (ret) |
5108 | break; | |
5109 | } | |
5110 | } | |
5111 | ||
5112 | return ret; | |
5113 | } | |
5114 | ||
5115 | #endif | |
b03a8c1f | 5116 | |
63d7e5a4 NP |
5117 | /** |
5118 | * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP | |
b40c82e6 | 5119 | * @pf: pointer to PF |
63d7e5a4 NP |
5120 | * |
5121 | * Get TC map for ISCSI PF type that will include iSCSI TC | |
5122 | * and LAN TC. | |
5123 | **/ | |
5124 | static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf) | |
5125 | { | |
5126 | struct i40e_dcb_app_priority_table app; | |
5127 | struct i40e_hw *hw = &pf->hw; | |
5128 | u8 enabled_tc = 1; /* TC0 is always enabled */ | |
5129 | u8 tc, i; | |
5130 | /* Get the iSCSI APP TLV */ | |
5131 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
5132 | ||
5133 | for (i = 0; i < dcbcfg->numapps; i++) { | |
5134 | app = dcbcfg->app[i]; | |
5135 | if (app.selector == I40E_APP_SEL_TCPIP && | |
5136 | app.protocolid == I40E_APP_PROTOID_ISCSI) { | |
5137 | tc = dcbcfg->etscfg.prioritytable[app.priority]; | |
75f5cea9 | 5138 | enabled_tc |= BIT(tc); |
63d7e5a4 NP |
5139 | break; |
5140 | } | |
5141 | } | |
5142 | ||
5143 | return enabled_tc; | |
5144 | } | |
5145 | ||
41c445ff JB |
5146 | /** |
5147 | * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config | |
5148 | * @dcbcfg: the corresponding DCBx configuration structure | |
5149 | * | |
5150 | * Return the number of TCs from given DCBx configuration | |
5151 | **/ | |
5152 | static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg) | |
5153 | { | |
fbfe12c6 | 5154 | int i, tc_unused = 0; |
078b5876 | 5155 | u8 num_tc = 0; |
fbfe12c6 | 5156 | u8 ret = 0; |
41c445ff JB |
5157 | |
5158 | /* Scan the ETS Config Priority Table to find | |
5159 | * traffic class enabled for a given priority | |
fbfe12c6 | 5160 | * and create a bitmask of enabled TCs |
41c445ff | 5161 | */ |
fbfe12c6 DE |
5162 | for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) |
5163 | num_tc |= BIT(dcbcfg->etscfg.prioritytable[i]); | |
41c445ff | 5164 | |
fbfe12c6 DE |
5165 | /* Now scan the bitmask to check for |
5166 | * contiguous TCs starting with TC0 | |
41c445ff | 5167 | */ |
fbfe12c6 DE |
5168 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
5169 | if (num_tc & BIT(i)) { | |
5170 | if (!tc_unused) { | |
5171 | ret++; | |
5172 | } else { | |
5173 | pr_err("Non-contiguous TC - Disabling DCB\n"); | |
5174 | return 1; | |
5175 | } | |
5176 | } else { | |
5177 | tc_unused = 1; | |
5178 | } | |
5179 | } | |
5180 | ||
5181 | /* There is always at least TC0 */ | |
5182 | if (!ret) | |
5183 | ret = 1; | |
5184 | ||
5185 | return ret; | |
41c445ff JB |
5186 | } |
5187 | ||
5188 | /** | |
5189 | * i40e_dcb_get_enabled_tc - Get enabled traffic classes | |
5190 | * @dcbcfg: the corresponding DCBx configuration structure | |
5191 | * | |
5192 | * Query the current DCB configuration and return the number of | |
5193 | * traffic classes enabled from the given DCBX config | |
5194 | **/ | |
5195 | static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg) | |
5196 | { | |
5197 | u8 num_tc = i40e_dcb_get_num_tc(dcbcfg); | |
5198 | u8 enabled_tc = 1; | |
5199 | u8 i; | |
5200 | ||
5201 | for (i = 0; i < num_tc; i++) | |
41a1d04b | 5202 | enabled_tc |= BIT(i); |
41c445ff JB |
5203 | |
5204 | return enabled_tc; | |
5205 | } | |
5206 | ||
a9ce82f7 AN |
5207 | /** |
5208 | * i40e_mqprio_get_enabled_tc - Get enabled traffic classes | |
5209 | * @pf: PF being queried | |
5210 | * | |
5211 | * Query the current MQPRIO configuration and return the number of | |
5212 | * traffic classes enabled. | |
5213 | **/ | |
5214 | static u8 i40e_mqprio_get_enabled_tc(struct i40e_pf *pf) | |
5215 | { | |
5216 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
5217 | u8 num_tc = vsi->mqprio_qopt.qopt.num_tc; | |
5218 | u8 enabled_tc = 1, i; | |
5219 | ||
5220 | for (i = 1; i < num_tc; i++) | |
5221 | enabled_tc |= BIT(i); | |
5222 | return enabled_tc; | |
5223 | } | |
5224 | ||
41c445ff JB |
5225 | /** |
5226 | * i40e_pf_get_num_tc - Get enabled traffic classes for PF | |
5227 | * @pf: PF being queried | |
5228 | * | |
5229 | * Return number of traffic classes enabled for the given PF | |
5230 | **/ | |
5231 | static u8 i40e_pf_get_num_tc(struct i40e_pf *pf) | |
5232 | { | |
5233 | struct i40e_hw *hw = &pf->hw; | |
52a08caa | 5234 | u8 i, enabled_tc = 1; |
41c445ff JB |
5235 | u8 num_tc = 0; |
5236 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
5237 | ||
a9ce82f7 AN |
5238 | if (pf->flags & I40E_FLAG_TC_MQPRIO) |
5239 | return pf->vsi[pf->lan_vsi]->mqprio_qopt.qopt.num_tc; | |
5240 | ||
5241 | /* If neither MQPRIO nor DCB is enabled, then always use single TC */ | |
41c445ff JB |
5242 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) |
5243 | return 1; | |
5244 | ||
63d7e5a4 NP |
5245 | /* SFP mode will be enabled for all TCs on port */ |
5246 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) | |
5247 | return i40e_dcb_get_num_tc(dcbcfg); | |
5248 | ||
41c445ff | 5249 | /* MFP mode return count of enabled TCs for this PF */ |
63d7e5a4 NP |
5250 | if (pf->hw.func_caps.iscsi) |
5251 | enabled_tc = i40e_get_iscsi_tc_map(pf); | |
5252 | else | |
fc51de96 | 5253 | return 1; /* Only TC0 */ |
41c445ff | 5254 | |
63d7e5a4 | 5255 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
75f5cea9 | 5256 | if (enabled_tc & BIT(i)) |
63d7e5a4 NP |
5257 | num_tc++; |
5258 | } | |
5259 | return num_tc; | |
41c445ff JB |
5260 | } |
5261 | ||
41c445ff | 5262 | /** |
262de08f | 5263 | * i40e_pf_get_tc_map - Get bitmap for enabled traffic classes |
41c445ff JB |
5264 | * @pf: PF being queried |
5265 | * | |
5266 | * Return a bitmap for enabled traffic classes for this PF. | |
5267 | **/ | |
5268 | static u8 i40e_pf_get_tc_map(struct i40e_pf *pf) | |
5269 | { | |
a9ce82f7 AN |
5270 | if (pf->flags & I40E_FLAG_TC_MQPRIO) |
5271 | return i40e_mqprio_get_enabled_tc(pf); | |
5272 | ||
5273 | /* If neither MQPRIO nor DCB is enabled for this PF then just return | |
5274 | * default TC | |
5275 | */ | |
41c445ff | 5276 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) |
ea6acb7e | 5277 | return I40E_DEFAULT_TRAFFIC_CLASS; |
41c445ff | 5278 | |
41c445ff | 5279 | /* SFP mode we want PF to be enabled for all TCs */ |
63d7e5a4 NP |
5280 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) |
5281 | return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config); | |
5282 | ||
fc51de96 | 5283 | /* MFP enabled and iSCSI PF type */ |
63d7e5a4 NP |
5284 | if (pf->hw.func_caps.iscsi) |
5285 | return i40e_get_iscsi_tc_map(pf); | |
5286 | else | |
ea6acb7e | 5287 | return I40E_DEFAULT_TRAFFIC_CLASS; |
41c445ff JB |
5288 | } |
5289 | ||
5290 | /** | |
5291 | * i40e_vsi_get_bw_info - Query VSI BW Information | |
5292 | * @vsi: the VSI being queried | |
5293 | * | |
5294 | * Returns 0 on success, negative value on failure | |
5295 | **/ | |
5296 | static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi) | |
5297 | { | |
5298 | struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0}; | |
5299 | struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0}; | |
5300 | struct i40e_pf *pf = vsi->back; | |
5301 | struct i40e_hw *hw = &pf->hw; | |
f1c7e72e | 5302 | i40e_status ret; |
41c445ff | 5303 | u32 tc_bw_max; |
41c445ff JB |
5304 | int i; |
5305 | ||
5306 | /* Get the VSI level BW configuration */ | |
f1c7e72e SN |
5307 | ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL); |
5308 | if (ret) { | |
41c445ff | 5309 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
5310 | "couldn't get PF vsi bw config, err %s aq_err %s\n", |
5311 | i40e_stat_str(&pf->hw, ret), | |
5312 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
dcae29be | 5313 | return -EINVAL; |
41c445ff JB |
5314 | } |
5315 | ||
5316 | /* Get the VSI level BW configuration per TC */ | |
f1c7e72e SN |
5317 | ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config, |
5318 | NULL); | |
5319 | if (ret) { | |
41c445ff | 5320 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
5321 | "couldn't get PF vsi ets bw config, err %s aq_err %s\n", |
5322 | i40e_stat_str(&pf->hw, ret), | |
5323 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
dcae29be | 5324 | return -EINVAL; |
41c445ff JB |
5325 | } |
5326 | ||
5327 | if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) { | |
5328 | dev_info(&pf->pdev->dev, | |
5329 | "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n", | |
5330 | bw_config.tc_valid_bits, | |
5331 | bw_ets_config.tc_valid_bits); | |
5332 | /* Still continuing */ | |
5333 | } | |
5334 | ||
5335 | vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit); | |
5336 | vsi->bw_max_quanta = bw_config.max_bw; | |
5337 | tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) | | |
5338 | (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16); | |
5339 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
5340 | vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i]; | |
5341 | vsi->bw_ets_limit_credits[i] = | |
5342 | le16_to_cpu(bw_ets_config.credits[i]); | |
5343 | /* 3 bits out of 4 for each TC */ | |
5344 | vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7); | |
5345 | } | |
078b5876 | 5346 | |
dcae29be | 5347 | return 0; |
41c445ff JB |
5348 | } |
5349 | ||
5350 | /** | |
5351 | * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC | |
5352 | * @vsi: the VSI being configured | |
5353 | * @enabled_tc: TC bitmap | |
f5254429 | 5354 | * @bw_share: BW shared credits per TC |
41c445ff JB |
5355 | * |
5356 | * Returns 0 on success, negative value on failure | |
5357 | **/ | |
dcae29be | 5358 | static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc, |
41c445ff JB |
5359 | u8 *bw_share) |
5360 | { | |
5361 | struct i40e_aqc_configure_vsi_tc_bw_data bw_data; | |
fa38e30a | 5362 | struct i40e_pf *pf = vsi->back; |
f1c7e72e | 5363 | i40e_status ret; |
dcae29be | 5364 | int i; |
41c445ff | 5365 | |
fa38e30a MS |
5366 | /* There is no need to reset BW when mqprio mode is on. */ |
5367 | if (pf->flags & I40E_FLAG_TC_MQPRIO) | |
a9ce82f7 | 5368 | return 0; |
fa38e30a | 5369 | if (!vsi->mqprio_qopt.qopt.hw && !(pf->flags & I40E_FLAG_DCB_ENABLED)) { |
2027d4de AN |
5370 | ret = i40e_set_bw_limit(vsi, vsi->seid, 0); |
5371 | if (ret) | |
fa38e30a | 5372 | dev_info(&pf->pdev->dev, |
2027d4de AN |
5373 | "Failed to reset tx rate for vsi->seid %u\n", |
5374 | vsi->seid); | |
5375 | return ret; | |
5376 | } | |
4b208eaa | 5377 | memset(&bw_data, 0, sizeof(bw_data)); |
41c445ff JB |
5378 | bw_data.tc_valid_bits = enabled_tc; |
5379 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
5380 | bw_data.tc_bw_credits[i] = bw_share[i]; | |
5381 | ||
fa38e30a | 5382 | ret = i40e_aq_config_vsi_tc_bw(&pf->hw, vsi->seid, &bw_data, NULL); |
f1c7e72e | 5383 | if (ret) { |
fa38e30a | 5384 | dev_info(&pf->pdev->dev, |
69bfb110 | 5385 | "AQ command Config VSI BW allocation per TC failed = %d\n", |
fa38e30a | 5386 | pf->hw.aq.asq_last_status); |
dcae29be | 5387 | return -EINVAL; |
41c445ff JB |
5388 | } |
5389 | ||
5390 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
5391 | vsi->info.qs_handle[i] = bw_data.qs_handles[i]; | |
5392 | ||
dcae29be | 5393 | return 0; |
41c445ff JB |
5394 | } |
5395 | ||
5396 | /** | |
5397 | * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration | |
5398 | * @vsi: the VSI being configured | |
5399 | * @enabled_tc: TC map to be enabled | |
5400 | * | |
5401 | **/ | |
5402 | static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc) | |
5403 | { | |
5404 | struct net_device *netdev = vsi->netdev; | |
5405 | struct i40e_pf *pf = vsi->back; | |
5406 | struct i40e_hw *hw = &pf->hw; | |
5407 | u8 netdev_tc = 0; | |
5408 | int i; | |
5409 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
5410 | ||
5411 | if (!netdev) | |
5412 | return; | |
5413 | ||
5414 | if (!enabled_tc) { | |
5415 | netdev_reset_tc(netdev); | |
5416 | return; | |
5417 | } | |
5418 | ||
5419 | /* Set up actual enabled TCs on the VSI */ | |
5420 | if (netdev_set_num_tc(netdev, vsi->tc_config.numtc)) | |
5421 | return; | |
5422 | ||
5423 | /* set per TC queues for the VSI */ | |
5424 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
5425 | /* Only set TC queues for enabled tcs | |
5426 | * | |
5427 | * e.g. For a VSI that has TC0 and TC3 enabled the | |
5428 | * enabled_tc bitmap would be 0x00001001; the driver | |
5429 | * will set the numtc for netdev as 2 that will be | |
5430 | * referenced by the netdev layer as TC 0 and 1. | |
5431 | */ | |
75f5cea9 | 5432 | if (vsi->tc_config.enabled_tc & BIT(i)) |
41c445ff JB |
5433 | netdev_set_tc_queue(netdev, |
5434 | vsi->tc_config.tc_info[i].netdev_tc, | |
5435 | vsi->tc_config.tc_info[i].qcount, | |
5436 | vsi->tc_config.tc_info[i].qoffset); | |
5437 | } | |
5438 | ||
a9ce82f7 AN |
5439 | if (pf->flags & I40E_FLAG_TC_MQPRIO) |
5440 | return; | |
5441 | ||
41c445ff JB |
5442 | /* Assign UP2TC map for the VSI */ |
5443 | for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) { | |
5444 | /* Get the actual TC# for the UP */ | |
5445 | u8 ets_tc = dcbcfg->etscfg.prioritytable[i]; | |
5446 | /* Get the mapped netdev TC# for the UP */ | |
5447 | netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc; | |
5448 | netdev_set_prio_tc_map(netdev, i, netdev_tc); | |
5449 | } | |
5450 | } | |
5451 | ||
5452 | /** | |
5453 | * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map | |
5454 | * @vsi: the VSI being configured | |
5455 | * @ctxt: the ctxt buffer returned from AQ VSI update param command | |
5456 | **/ | |
5457 | static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi, | |
5458 | struct i40e_vsi_context *ctxt) | |
5459 | { | |
5460 | /* copy just the sections touched not the entire info | |
5461 | * since not all sections are valid as returned by | |
5462 | * update vsi params | |
5463 | */ | |
5464 | vsi->info.mapping_flags = ctxt->info.mapping_flags; | |
5465 | memcpy(&vsi->info.queue_mapping, | |
5466 | &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping)); | |
5467 | memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping, | |
5468 | sizeof(vsi->info.tc_mapping)); | |
5469 | } | |
5470 | ||
9e0a603c ER |
5471 | /** |
5472 | * i40e_update_adq_vsi_queues - update queue mapping for ADq VSI | |
5473 | * @vsi: the VSI being reconfigured | |
5474 | * @vsi_offset: offset from main VF VSI | |
5475 | */ | |
5476 | int i40e_update_adq_vsi_queues(struct i40e_vsi *vsi, int vsi_offset) | |
5477 | { | |
5478 | struct i40e_vsi_context ctxt = {}; | |
5479 | struct i40e_pf *pf; | |
5480 | struct i40e_hw *hw; | |
5481 | int ret; | |
5482 | ||
5483 | if (!vsi) | |
5484 | return I40E_ERR_PARAM; | |
5485 | pf = vsi->back; | |
5486 | hw = &pf->hw; | |
5487 | ||
5488 | ctxt.seid = vsi->seid; | |
5489 | ctxt.pf_num = hw->pf_id; | |
5490 | ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id + vsi_offset; | |
5491 | ctxt.uplink_seid = vsi->uplink_seid; | |
5492 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; | |
5493 | ctxt.flags = I40E_AQ_VSI_TYPE_VF; | |
5494 | ctxt.info = vsi->info; | |
5495 | ||
5496 | i40e_vsi_setup_queue_map(vsi, &ctxt, vsi->tc_config.enabled_tc, | |
5497 | false); | |
5498 | if (vsi->reconfig_rss) { | |
5499 | vsi->rss_size = min_t(int, pf->alloc_rss_size, | |
5500 | vsi->num_queue_pairs); | |
5501 | ret = i40e_vsi_config_rss(vsi); | |
5502 | if (ret) { | |
5503 | dev_info(&pf->pdev->dev, "Failed to reconfig rss for num_queues\n"); | |
5504 | return ret; | |
5505 | } | |
5506 | vsi->reconfig_rss = false; | |
5507 | } | |
5508 | ||
5509 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); | |
5510 | if (ret) { | |
5511 | dev_info(&pf->pdev->dev, "Update vsi config failed, err %s aq_err %s\n", | |
5512 | i40e_stat_str(hw, ret), | |
5513 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
5514 | return ret; | |
5515 | } | |
5516 | /* update the local VSI info with updated queue map */ | |
5517 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
5518 | vsi->info.valid_sections = 0; | |
5519 | ||
5520 | return ret; | |
5521 | } | |
5522 | ||
41c445ff JB |
5523 | /** |
5524 | * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map | |
5525 | * @vsi: VSI to be configured | |
5526 | * @enabled_tc: TC bitmap | |
5527 | * | |
5528 | * This configures a particular VSI for TCs that are mapped to the | |
5529 | * given TC bitmap. It uses default bandwidth share for TCs across | |
5530 | * VSIs to configure TC for a particular VSI. | |
5531 | * | |
5532 | * NOTE: | |
5533 | * It is expected that the VSI queues have been quisced before calling | |
5534 | * this function. | |
5535 | **/ | |
5536 | static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc) | |
5537 | { | |
5538 | u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0}; | |
d8a87856 MW |
5539 | struct i40e_pf *pf = vsi->back; |
5540 | struct i40e_hw *hw = &pf->hw; | |
41c445ff JB |
5541 | struct i40e_vsi_context ctxt; |
5542 | int ret = 0; | |
5543 | int i; | |
5544 | ||
5545 | /* Check if enabled_tc is same as existing or new TCs */ | |
a9ce82f7 AN |
5546 | if (vsi->tc_config.enabled_tc == enabled_tc && |
5547 | vsi->mqprio_qopt.mode != TC_MQPRIO_MODE_CHANNEL) | |
41c445ff JB |
5548 | return ret; |
5549 | ||
5550 | /* Enable ETS TCs with equal BW Share for now across all VSIs */ | |
5551 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 5552 | if (enabled_tc & BIT(i)) |
41c445ff JB |
5553 | bw_share[i] = 1; |
5554 | } | |
5555 | ||
5556 | ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share); | |
5557 | if (ret) { | |
d8a87856 MW |
5558 | struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0}; |
5559 | ||
bc73234b | 5560 | dev_info(&pf->pdev->dev, |
41c445ff JB |
5561 | "Failed configuring TC map %d for VSI %d\n", |
5562 | enabled_tc, vsi->seid); | |
d8a87856 MW |
5563 | ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, |
5564 | &bw_config, NULL); | |
5565 | if (ret) { | |
5566 | dev_info(&pf->pdev->dev, | |
5567 | "Failed querying vsi bw info, err %s aq_err %s\n", | |
5568 | i40e_stat_str(hw, ret), | |
5569 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
5570 | goto out; | |
5571 | } | |
5572 | if ((bw_config.tc_valid_bits & enabled_tc) != enabled_tc) { | |
5573 | u8 valid_tc = bw_config.tc_valid_bits & enabled_tc; | |
5574 | ||
5575 | if (!valid_tc) | |
5576 | valid_tc = bw_config.tc_valid_bits; | |
5577 | /* Always enable TC0, no matter what */ | |
5578 | valid_tc |= 1; | |
5579 | dev_info(&pf->pdev->dev, | |
5580 | "Requested tc 0x%x, but FW reports 0x%x as valid. Attempting to use 0x%x.\n", | |
5581 | enabled_tc, bw_config.tc_valid_bits, valid_tc); | |
5582 | enabled_tc = valid_tc; | |
5583 | } | |
5584 | ||
5585 | ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share); | |
5586 | if (ret) { | |
5587 | dev_err(&pf->pdev->dev, | |
5588 | "Unable to configure TC map %d for VSI %d\n", | |
5589 | enabled_tc, vsi->seid); | |
5590 | goto out; | |
5591 | } | |
41c445ff JB |
5592 | } |
5593 | ||
5594 | /* Update Queue Pairs Mapping for currently enabled UPs */ | |
5595 | ctxt.seid = vsi->seid; | |
5596 | ctxt.pf_num = vsi->back->hw.pf_id; | |
5597 | ctxt.vf_num = 0; | |
5598 | ctxt.uplink_seid = vsi->uplink_seid; | |
1a2f6248 | 5599 | ctxt.info = vsi->info; |
a9ce82f7 AN |
5600 | if (vsi->back->flags & I40E_FLAG_TC_MQPRIO) { |
5601 | ret = i40e_vsi_setup_queue_map_mqprio(vsi, &ctxt, enabled_tc); | |
5602 | if (ret) | |
5603 | goto out; | |
5604 | } else { | |
5605 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); | |
5606 | } | |
41c445ff | 5607 | |
a9ce82f7 AN |
5608 | /* On destroying the qdisc, reset vsi->rss_size, as number of enabled |
5609 | * queues changed. | |
5610 | */ | |
5611 | if (!vsi->mqprio_qopt.qopt.hw && vsi->reconfig_rss) { | |
5612 | vsi->rss_size = min_t(int, vsi->back->alloc_rss_size, | |
5613 | vsi->num_queue_pairs); | |
5614 | ret = i40e_vsi_config_rss(vsi); | |
5615 | if (ret) { | |
5616 | dev_info(&vsi->back->pdev->dev, | |
5617 | "Failed to reconfig rss for num_queues\n"); | |
5618 | return ret; | |
5619 | } | |
5620 | vsi->reconfig_rss = false; | |
5621 | } | |
e3219ce6 ASJ |
5622 | if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { |
5623 | ctxt.info.valid_sections |= | |
5624 | cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); | |
5625 | ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA; | |
5626 | } | |
5627 | ||
a9ce82f7 AN |
5628 | /* Update the VSI after updating the VSI queue-mapping |
5629 | * information | |
5630 | */ | |
bc73234b | 5631 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); |
41c445ff | 5632 | if (ret) { |
bc73234b | 5633 | dev_info(&pf->pdev->dev, |
f1c7e72e | 5634 | "Update vsi tc config failed, err %s aq_err %s\n", |
bc73234b MW |
5635 | i40e_stat_str(hw, ret), |
5636 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
41c445ff JB |
5637 | goto out; |
5638 | } | |
5639 | /* update the local VSI info with updated queue map */ | |
5640 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
5641 | vsi->info.valid_sections = 0; | |
5642 | ||
5643 | /* Update current VSI BW information */ | |
5644 | ret = i40e_vsi_get_bw_info(vsi); | |
5645 | if (ret) { | |
bc73234b | 5646 | dev_info(&pf->pdev->dev, |
f1c7e72e | 5647 | "Failed updating vsi bw info, err %s aq_err %s\n", |
bc73234b MW |
5648 | i40e_stat_str(hw, ret), |
5649 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
41c445ff JB |
5650 | goto out; |
5651 | } | |
5652 | ||
5653 | /* Update the netdev TC setup */ | |
5654 | i40e_vsi_config_netdev_tc(vsi, enabled_tc); | |
5655 | out: | |
5656 | return ret; | |
5657 | } | |
5658 | ||
4e3b35b0 | 5659 | /** |
5ecae412 AN |
5660 | * i40e_get_link_speed - Returns link speed for the interface |
5661 | * @vsi: VSI to be configured | |
4e3b35b0 | 5662 | * |
4e3b35b0 | 5663 | **/ |
3758d2c7 | 5664 | static int i40e_get_link_speed(struct i40e_vsi *vsi) |
4e3b35b0 | 5665 | { |
5ecae412 | 5666 | struct i40e_pf *pf = vsi->back; |
4e3b35b0 | 5667 | |
5ecae412 AN |
5668 | switch (pf->hw.phy.link_info.link_speed) { |
5669 | case I40E_LINK_SPEED_40GB: | |
5670 | return 40000; | |
5671 | case I40E_LINK_SPEED_25GB: | |
5672 | return 25000; | |
5673 | case I40E_LINK_SPEED_20GB: | |
5674 | return 20000; | |
5675 | case I40E_LINK_SPEED_10GB: | |
5676 | return 10000; | |
5677 | case I40E_LINK_SPEED_1GB: | |
5678 | return 1000; | |
5679 | default: | |
5680 | return -EINVAL; | |
4e3b35b0 | 5681 | } |
4e3b35b0 NP |
5682 | } |
5683 | ||
4e3b35b0 | 5684 | /** |
5ecae412 AN |
5685 | * i40e_set_bw_limit - setup BW limit for Tx traffic based on max_tx_rate |
5686 | * @vsi: VSI to be configured | |
5687 | * @seid: seid of the channel/VSI | |
5688 | * @max_tx_rate: max TX rate to be configured as BW limit | |
4e3b35b0 | 5689 | * |
5ecae412 | 5690 | * Helper function to set BW limit for a given VSI |
4e3b35b0 | 5691 | **/ |
5ecae412 | 5692 | int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate) |
4e3b35b0 | 5693 | { |
5ecae412 | 5694 | struct i40e_pf *pf = vsi->back; |
6c32e0d9 | 5695 | u64 credits = 0; |
5ecae412 AN |
5696 | int speed = 0; |
5697 | int ret = 0; | |
4e3b35b0 | 5698 | |
5ecae412 AN |
5699 | speed = i40e_get_link_speed(vsi); |
5700 | if (max_tx_rate > speed) { | |
5701 | dev_err(&pf->pdev->dev, | |
5702 | "Invalid max tx rate %llu specified for VSI seid %d.", | |
5703 | max_tx_rate, seid); | |
5704 | return -EINVAL; | |
5705 | } | |
5706 | if (max_tx_rate && max_tx_rate < 50) { | |
5707 | dev_warn(&pf->pdev->dev, | |
5708 | "Setting max tx rate to minimum usable value of 50Mbps.\n"); | |
5709 | max_tx_rate = 50; | |
5710 | } | |
5711 | ||
5712 | /* Tx rate credits are in values of 50Mbps, 0 is disabled */ | |
6c32e0d9 AB |
5713 | credits = max_tx_rate; |
5714 | do_div(credits, I40E_BW_CREDIT_DIVISOR); | |
5715 | ret = i40e_aq_config_vsi_bw_limit(&pf->hw, seid, credits, | |
5ecae412 AN |
5716 | I40E_MAX_BW_INACTIVE_ACCUM, NULL); |
5717 | if (ret) | |
5718 | dev_err(&pf->pdev->dev, | |
5719 | "Failed set tx rate (%llu Mbps) for vsi->seid %u, err %s aq_err %s\n", | |
5720 | max_tx_rate, seid, i40e_stat_str(&pf->hw, ret), | |
5721 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
5722 | return ret; | |
5723 | } | |
5724 | ||
8f88b303 AN |
5725 | /** |
5726 | * i40e_remove_queue_channels - Remove queue channels for the TCs | |
5727 | * @vsi: VSI to be configured | |
5728 | * | |
5729 | * Remove queue channels for the TCs | |
5730 | **/ | |
5731 | static void i40e_remove_queue_channels(struct i40e_vsi *vsi) | |
5732 | { | |
2f4b411a AN |
5733 | enum i40e_admin_queue_err last_aq_status; |
5734 | struct i40e_cloud_filter *cfilter; | |
8f88b303 | 5735 | struct i40e_channel *ch, *ch_tmp; |
2f4b411a AN |
5736 | struct i40e_pf *pf = vsi->back; |
5737 | struct hlist_node *node; | |
8f88b303 AN |
5738 | int ret, i; |
5739 | ||
5740 | /* Reset rss size that was stored when reconfiguring rss for | |
5741 | * channel VSIs with non-power-of-2 queue count. | |
5742 | */ | |
5743 | vsi->current_rss_size = 0; | |
5744 | ||
5745 | /* perform cleanup for channels if they exist */ | |
5746 | if (list_empty(&vsi->ch_list)) | |
5747 | return; | |
5748 | ||
5749 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) { | |
5750 | struct i40e_vsi *p_vsi; | |
5751 | ||
5752 | list_del(&ch->list); | |
5753 | p_vsi = ch->parent_vsi; | |
5754 | if (!p_vsi || !ch->initialized) { | |
5755 | kfree(ch); | |
4e3b35b0 | 5756 | continue; |
8f88b303 AN |
5757 | } |
5758 | /* Reset queue contexts */ | |
5759 | for (i = 0; i < ch->num_queue_pairs; i++) { | |
5760 | struct i40e_ring *tx_ring, *rx_ring; | |
5761 | u16 pf_q; | |
5762 | ||
5763 | pf_q = ch->base_queue + i; | |
5764 | tx_ring = vsi->tx_rings[pf_q]; | |
5765 | tx_ring->ch = NULL; | |
5766 | ||
5767 | rx_ring = vsi->rx_rings[pf_q]; | |
5768 | rx_ring->ch = NULL; | |
5769 | } | |
5770 | ||
2027d4de AN |
5771 | /* Reset BW configured for this VSI via mqprio */ |
5772 | ret = i40e_set_bw_limit(vsi, ch->seid, 0); | |
5773 | if (ret) | |
5774 | dev_info(&vsi->back->pdev->dev, | |
5775 | "Failed to reset tx rate for ch->seid %u\n", | |
5776 | ch->seid); | |
5777 | ||
2f4b411a AN |
5778 | /* delete cloud filters associated with this channel */ |
5779 | hlist_for_each_entry_safe(cfilter, node, | |
5780 | &pf->cloud_filter_list, cloud_node) { | |
5781 | if (cfilter->seid != ch->seid) | |
5782 | continue; | |
5783 | ||
5784 | hash_del(&cfilter->cloud_node); | |
5785 | if (cfilter->dst_port) | |
5786 | ret = i40e_add_del_cloud_filter_big_buf(vsi, | |
5787 | cfilter, | |
5788 | false); | |
5789 | else | |
5790 | ret = i40e_add_del_cloud_filter(vsi, cfilter, | |
5791 | false); | |
5792 | last_aq_status = pf->hw.aq.asq_last_status; | |
5793 | if (ret) | |
5794 | dev_info(&pf->pdev->dev, | |
5795 | "Failed to delete cloud filter, err %s aq_err %s\n", | |
5796 | i40e_stat_str(&pf->hw, ret), | |
5797 | i40e_aq_str(&pf->hw, last_aq_status)); | |
5798 | kfree(cfilter); | |
5799 | } | |
5800 | ||
8f88b303 AN |
5801 | /* delete VSI from FW */ |
5802 | ret = i40e_aq_delete_element(&vsi->back->hw, ch->seid, | |
5803 | NULL); | |
5804 | if (ret) | |
5805 | dev_err(&vsi->back->pdev->dev, | |
5806 | "unable to remove channel (%d) for parent VSI(%d)\n", | |
5807 | ch->seid, p_vsi->seid); | |
5808 | kfree(ch); | |
5809 | } | |
5810 | INIT_LIST_HEAD(&vsi->ch_list); | |
5811 | } | |
5812 | ||
8f88b303 AN |
5813 | /** |
5814 | * i40e_get_max_queues_for_channel | |
5815 | * @vsi: ptr to VSI to which channels are associated with | |
5816 | * | |
5817 | * Helper function which returns max value among the queue counts set on the | |
5818 | * channels/TCs created. | |
5819 | **/ | |
5820 | static int i40e_get_max_queues_for_channel(struct i40e_vsi *vsi) | |
5821 | { | |
5822 | struct i40e_channel *ch, *ch_tmp; | |
5823 | int max = 0; | |
5824 | ||
5825 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) { | |
5826 | if (!ch->initialized) | |
5827 | continue; | |
5828 | if (ch->num_queue_pairs > max) | |
5829 | max = ch->num_queue_pairs; | |
5830 | } | |
5831 | ||
5832 | return max; | |
5833 | } | |
5834 | ||
5835 | /** | |
5836 | * i40e_validate_num_queues - validate num_queues w.r.t channel | |
5837 | * @pf: ptr to PF device | |
5838 | * @num_queues: number of queues | |
5839 | * @vsi: the parent VSI | |
5840 | * @reconfig_rss: indicates should the RSS be reconfigured or not | |
5841 | * | |
5842 | * This function validates number of queues in the context of new channel | |
5843 | * which is being established and determines if RSS should be reconfigured | |
5844 | * or not for parent VSI. | |
5845 | **/ | |
5846 | static int i40e_validate_num_queues(struct i40e_pf *pf, int num_queues, | |
5847 | struct i40e_vsi *vsi, bool *reconfig_rss) | |
5848 | { | |
5849 | int max_ch_queues; | |
5850 | ||
5851 | if (!reconfig_rss) | |
5852 | return -EINVAL; | |
5853 | ||
5854 | *reconfig_rss = false; | |
8f88b303 AN |
5855 | if (vsi->current_rss_size) { |
5856 | if (num_queues > vsi->current_rss_size) { | |
5857 | dev_dbg(&pf->pdev->dev, | |
5858 | "Error: num_queues (%d) > vsi's current_size(%d)\n", | |
5859 | num_queues, vsi->current_rss_size); | |
5860 | return -EINVAL; | |
5861 | } else if ((num_queues < vsi->current_rss_size) && | |
5862 | (!is_power_of_2(num_queues))) { | |
5863 | dev_dbg(&pf->pdev->dev, | |
5864 | "Error: num_queues (%d) < vsi's current_size(%d), but not power of 2\n", | |
5865 | num_queues, vsi->current_rss_size); | |
5866 | return -EINVAL; | |
5867 | } | |
5868 | } | |
5869 | ||
5870 | if (!is_power_of_2(num_queues)) { | |
5871 | /* Find the max num_queues configured for channel if channel | |
5872 | * exist. | |
5873 | * if channel exist, then enforce 'num_queues' to be more than | |
5874 | * max ever queues configured for channel. | |
5875 | */ | |
5876 | max_ch_queues = i40e_get_max_queues_for_channel(vsi); | |
5877 | if (num_queues < max_ch_queues) { | |
5878 | dev_dbg(&pf->pdev->dev, | |
5879 | "Error: num_queues (%d) < max queues configured for channel(%d)\n", | |
5880 | num_queues, max_ch_queues); | |
5881 | return -EINVAL; | |
5882 | } | |
5883 | *reconfig_rss = true; | |
5884 | } | |
5885 | ||
5886 | return 0; | |
5887 | } | |
5888 | ||
5889 | /** | |
5890 | * i40e_vsi_reconfig_rss - reconfig RSS based on specified rss_size | |
5891 | * @vsi: the VSI being setup | |
5892 | * @rss_size: size of RSS, accordingly LUT gets reprogrammed | |
5893 | * | |
5894 | * This function reconfigures RSS by reprogramming LUTs using 'rss_size' | |
5895 | **/ | |
5896 | static int i40e_vsi_reconfig_rss(struct i40e_vsi *vsi, u16 rss_size) | |
5897 | { | |
5898 | struct i40e_pf *pf = vsi->back; | |
5899 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
5900 | struct i40e_hw *hw = &pf->hw; | |
5901 | int local_rss_size; | |
5902 | u8 *lut; | |
5903 | int ret; | |
5904 | ||
5905 | if (!vsi->rss_size) | |
5906 | return -EINVAL; | |
5907 | ||
5908 | if (rss_size > vsi->rss_size) | |
5909 | return -EINVAL; | |
5910 | ||
5911 | local_rss_size = min_t(int, vsi->rss_size, rss_size); | |
5912 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); | |
5913 | if (!lut) | |
5914 | return -ENOMEM; | |
5915 | ||
5916 | /* Ignoring user configured lut if there is one */ | |
5917 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, local_rss_size); | |
5918 | ||
5919 | /* Use user configured hash key if there is one, otherwise | |
5920 | * use default. | |
5921 | */ | |
5922 | if (vsi->rss_hkey_user) | |
5923 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
5924 | else | |
5925 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
5926 | ||
5927 | ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size); | |
5928 | if (ret) { | |
5929 | dev_info(&pf->pdev->dev, | |
5930 | "Cannot set RSS lut, err %s aq_err %s\n", | |
5931 | i40e_stat_str(hw, ret), | |
5932 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
5933 | kfree(lut); | |
5934 | return ret; | |
5935 | } | |
5936 | kfree(lut); | |
5937 | ||
5938 | /* Do the update w.r.t. storing rss_size */ | |
5939 | if (!vsi->orig_rss_size) | |
5940 | vsi->orig_rss_size = vsi->rss_size; | |
5941 | vsi->current_rss_size = local_rss_size; | |
5942 | ||
5943 | return ret; | |
5944 | } | |
5945 | ||
5946 | /** | |
5947 | * i40e_channel_setup_queue_map - Setup a channel queue map | |
5948 | * @pf: ptr to PF device | |
8f88b303 AN |
5949 | * @ctxt: VSI context structure |
5950 | * @ch: ptr to channel structure | |
5951 | * | |
5952 | * Setup queue map for a specific channel | |
5953 | **/ | |
5954 | static void i40e_channel_setup_queue_map(struct i40e_pf *pf, | |
5955 | struct i40e_vsi_context *ctxt, | |
5956 | struct i40e_channel *ch) | |
5957 | { | |
5958 | u16 qcount, qmap, sections = 0; | |
5959 | u8 offset = 0; | |
5960 | int pow; | |
5961 | ||
5962 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
5963 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
5964 | ||
5965 | qcount = min_t(int, ch->num_queue_pairs, pf->num_lan_msix); | |
5966 | ch->num_queue_pairs = qcount; | |
5967 | ||
5968 | /* find the next higher power-of-2 of num queue pairs */ | |
5969 | pow = ilog2(qcount); | |
5970 | if (!is_power_of_2(qcount)) | |
5971 | pow++; | |
5972 | ||
5973 | qmap = (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
5974 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
5975 | ||
5976 | /* Setup queue TC[0].qmap for given VSI context */ | |
5977 | ctxt->info.tc_mapping[0] = cpu_to_le16(qmap); | |
5978 | ||
5979 | ctxt->info.up_enable_bits = 0x1; /* TC0 enabled */ | |
5980 | ctxt->info.mapping_flags |= cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
5981 | ctxt->info.queue_mapping[0] = cpu_to_le16(ch->base_queue); | |
5982 | ctxt->info.valid_sections |= cpu_to_le16(sections); | |
5983 | } | |
5984 | ||
5985 | /** | |
5986 | * i40e_add_channel - add a channel by adding VSI | |
5987 | * @pf: ptr to PF device | |
5988 | * @uplink_seid: underlying HW switching element (VEB) ID | |
5989 | * @ch: ptr to channel structure | |
5990 | * | |
5991 | * Add a channel (VSI) using add_vsi and queue_map | |
5992 | **/ | |
5993 | static int i40e_add_channel(struct i40e_pf *pf, u16 uplink_seid, | |
5994 | struct i40e_channel *ch) | |
5995 | { | |
5996 | struct i40e_hw *hw = &pf->hw; | |
5997 | struct i40e_vsi_context ctxt; | |
5998 | u8 enabled_tc = 0x1; /* TC0 enabled */ | |
5999 | int ret; | |
6000 | ||
6001 | if (ch->type != I40E_VSI_VMDQ2) { | |
6002 | dev_info(&pf->pdev->dev, | |
6003 | "add new vsi failed, ch->type %d\n", ch->type); | |
6004 | return -EINVAL; | |
6005 | } | |
6006 | ||
6007 | memset(&ctxt, 0, sizeof(ctxt)); | |
6008 | ctxt.pf_num = hw->pf_id; | |
6009 | ctxt.vf_num = 0; | |
6010 | ctxt.uplink_seid = uplink_seid; | |
6011 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; | |
6012 | if (ch->type == I40E_VSI_VMDQ2) | |
6013 | ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; | |
6014 | ||
6015 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) { | |
6016 | ctxt.info.valid_sections |= | |
6017 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
6018 | ctxt.info.switch_id = | |
6019 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
6020 | } | |
6021 | ||
6022 | /* Set queue map for a given VSI context */ | |
6023 | i40e_channel_setup_queue_map(pf, &ctxt, ch); | |
6024 | ||
6025 | /* Now time to create VSI */ | |
6026 | ret = i40e_aq_add_vsi(hw, &ctxt, NULL); | |
6027 | if (ret) { | |
6028 | dev_info(&pf->pdev->dev, | |
6029 | "add new vsi failed, err %s aq_err %s\n", | |
6030 | i40e_stat_str(&pf->hw, ret), | |
6031 | i40e_aq_str(&pf->hw, | |
6032 | pf->hw.aq.asq_last_status)); | |
6033 | return -ENOENT; | |
6034 | } | |
6035 | ||
1d8d80b4 HR |
6036 | /* Success, update channel, set enabled_tc only if the channel |
6037 | * is not a macvlan | |
6038 | */ | |
6039 | ch->enabled_tc = !i40e_is_channel_macvlan(ch) && enabled_tc; | |
8f88b303 AN |
6040 | ch->seid = ctxt.seid; |
6041 | ch->vsi_number = ctxt.vsi_number; | |
b32cddd2 | 6042 | ch->stat_counter_idx = le16_to_cpu(ctxt.info.stat_counter_idx); |
8f88b303 AN |
6043 | |
6044 | /* copy just the sections touched not the entire info | |
6045 | * since not all sections are valid as returned by | |
6046 | * update vsi params | |
6047 | */ | |
6048 | ch->info.mapping_flags = ctxt.info.mapping_flags; | |
6049 | memcpy(&ch->info.queue_mapping, | |
6050 | &ctxt.info.queue_mapping, sizeof(ctxt.info.queue_mapping)); | |
6051 | memcpy(&ch->info.tc_mapping, ctxt.info.tc_mapping, | |
6052 | sizeof(ctxt.info.tc_mapping)); | |
6053 | ||
6054 | return 0; | |
6055 | } | |
6056 | ||
6057 | static int i40e_channel_config_bw(struct i40e_vsi *vsi, struct i40e_channel *ch, | |
6058 | u8 *bw_share) | |
6059 | { | |
6060 | struct i40e_aqc_configure_vsi_tc_bw_data bw_data; | |
6061 | i40e_status ret; | |
6062 | int i; | |
6063 | ||
4b208eaa | 6064 | memset(&bw_data, 0, sizeof(bw_data)); |
8f88b303 AN |
6065 | bw_data.tc_valid_bits = ch->enabled_tc; |
6066 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
6067 | bw_data.tc_bw_credits[i] = bw_share[i]; | |
6068 | ||
6069 | ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, ch->seid, | |
6070 | &bw_data, NULL); | |
6071 | if (ret) { | |
6072 | dev_info(&vsi->back->pdev->dev, | |
6073 | "Config VSI BW allocation per TC failed, aq_err: %d for new_vsi->seid %u\n", | |
6074 | vsi->back->hw.aq.asq_last_status, ch->seid); | |
6075 | return -EINVAL; | |
6076 | } | |
6077 | ||
6078 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
6079 | ch->info.qs_handle[i] = bw_data.qs_handles[i]; | |
6080 | ||
6081 | return 0; | |
6082 | } | |
6083 | ||
6084 | /** | |
6085 | * i40e_channel_config_tx_ring - config TX ring associated with new channel | |
6086 | * @pf: ptr to PF device | |
6087 | * @vsi: the VSI being setup | |
6088 | * @ch: ptr to channel structure | |
6089 | * | |
6090 | * Configure TX rings associated with channel (VSI) since queues are being | |
6091 | * from parent VSI. | |
6092 | **/ | |
6093 | static int i40e_channel_config_tx_ring(struct i40e_pf *pf, | |
6094 | struct i40e_vsi *vsi, | |
6095 | struct i40e_channel *ch) | |
6096 | { | |
6097 | i40e_status ret; | |
6098 | int i; | |
6099 | u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0}; | |
6100 | ||
6101 | /* Enable ETS TCs with equal BW Share for now across all VSIs */ | |
6102 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
6103 | if (ch->enabled_tc & BIT(i)) | |
6104 | bw_share[i] = 1; | |
6105 | } | |
6106 | ||
6107 | /* configure BW for new VSI */ | |
6108 | ret = i40e_channel_config_bw(vsi, ch, bw_share); | |
6109 | if (ret) { | |
6110 | dev_info(&vsi->back->pdev->dev, | |
6111 | "Failed configuring TC map %d for channel (seid %u)\n", | |
6112 | ch->enabled_tc, ch->seid); | |
6113 | return ret; | |
6114 | } | |
6115 | ||
6116 | for (i = 0; i < ch->num_queue_pairs; i++) { | |
6117 | struct i40e_ring *tx_ring, *rx_ring; | |
6118 | u16 pf_q; | |
6119 | ||
6120 | pf_q = ch->base_queue + i; | |
6121 | ||
6122 | /* Get to TX ring ptr of main VSI, for re-setup TX queue | |
6123 | * context | |
6124 | */ | |
6125 | tx_ring = vsi->tx_rings[pf_q]; | |
6126 | tx_ring->ch = ch; | |
6127 | ||
6128 | /* Get the RX ring ptr */ | |
6129 | rx_ring = vsi->rx_rings[pf_q]; | |
6130 | rx_ring->ch = ch; | |
6131 | } | |
6132 | ||
6133 | return 0; | |
6134 | } | |
6135 | ||
6136 | /** | |
6137 | * i40e_setup_hw_channel - setup new channel | |
6138 | * @pf: ptr to PF device | |
6139 | * @vsi: the VSI being setup | |
6140 | * @ch: ptr to channel structure | |
6141 | * @uplink_seid: underlying HW switching element (VEB) ID | |
6142 | * @type: type of channel to be created (VMDq2/VF) | |
6143 | * | |
6144 | * Setup new channel (VSI) based on specified type (VMDq2/VF) | |
6145 | * and configures TX rings accordingly | |
6146 | **/ | |
6147 | static inline int i40e_setup_hw_channel(struct i40e_pf *pf, | |
6148 | struct i40e_vsi *vsi, | |
6149 | struct i40e_channel *ch, | |
6150 | u16 uplink_seid, u8 type) | |
6151 | { | |
6152 | int ret; | |
6153 | ||
6154 | ch->initialized = false; | |
6155 | ch->base_queue = vsi->next_base_queue; | |
6156 | ch->type = type; | |
6157 | ||
6158 | /* Proceed with creation of channel (VMDq2) VSI */ | |
6159 | ret = i40e_add_channel(pf, uplink_seid, ch); | |
6160 | if (ret) { | |
6161 | dev_info(&pf->pdev->dev, | |
6162 | "failed to add_channel using uplink_seid %u\n", | |
6163 | uplink_seid); | |
6164 | return ret; | |
6165 | } | |
6166 | ||
6167 | /* Mark the successful creation of channel */ | |
6168 | ch->initialized = true; | |
6169 | ||
6170 | /* Reconfigure TX queues using QTX_CTL register */ | |
6171 | ret = i40e_channel_config_tx_ring(pf, vsi, ch); | |
6172 | if (ret) { | |
6173 | dev_info(&pf->pdev->dev, | |
6174 | "failed to configure TX rings for channel %u\n", | |
6175 | ch->seid); | |
6176 | return ret; | |
6177 | } | |
6178 | ||
6179 | /* update 'next_base_queue' */ | |
6180 | vsi->next_base_queue = vsi->next_base_queue + ch->num_queue_pairs; | |
6181 | dev_dbg(&pf->pdev->dev, | |
6182 | "Added channel: vsi_seid %u, vsi_number %u, stat_counter_idx %u, num_queue_pairs %u, pf->next_base_queue %d\n", | |
6183 | ch->seid, ch->vsi_number, ch->stat_counter_idx, | |
6184 | ch->num_queue_pairs, | |
6185 | vsi->next_base_queue); | |
6186 | return ret; | |
6187 | } | |
6188 | ||
6189 | /** | |
6190 | * i40e_setup_channel - setup new channel using uplink element | |
6191 | * @pf: ptr to PF device | |
b50f7bca | 6192 | * @vsi: pointer to the VSI to set up the channel within |
8f88b303 AN |
6193 | * @ch: ptr to channel structure |
6194 | * | |
6195 | * Setup new channel (VSI) based on specified type (VMDq2/VF) | |
6196 | * and uplink switching element (uplink_seid) | |
6197 | **/ | |
6198 | static bool i40e_setup_channel(struct i40e_pf *pf, struct i40e_vsi *vsi, | |
6199 | struct i40e_channel *ch) | |
6200 | { | |
6201 | u8 vsi_type; | |
6202 | u16 seid; | |
6203 | int ret; | |
6204 | ||
6205 | if (vsi->type == I40E_VSI_MAIN) { | |
6206 | vsi_type = I40E_VSI_VMDQ2; | |
6207 | } else { | |
6208 | dev_err(&pf->pdev->dev, "unsupported parent vsi type(%d)\n", | |
6209 | vsi->type); | |
6210 | return false; | |
6211 | } | |
6212 | ||
6213 | /* underlying switching element */ | |
6214 | seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
6215 | ||
6216 | /* create channel (VSI), configure TX rings */ | |
6217 | ret = i40e_setup_hw_channel(pf, vsi, ch, seid, vsi_type); | |
6218 | if (ret) { | |
6219 | dev_err(&pf->pdev->dev, "failed to setup hw_channel\n"); | |
6220 | return false; | |
6221 | } | |
6222 | ||
6223 | return ch->initialized ? true : false; | |
6224 | } | |
6225 | ||
2f4b411a AN |
6226 | /** |
6227 | * i40e_validate_and_set_switch_mode - sets up switch mode correctly | |
6228 | * @vsi: ptr to VSI which has PF backing | |
6229 | * | |
6230 | * Sets up switch mode correctly if it needs to be changed and perform | |
6231 | * what are allowed modes. | |
6232 | **/ | |
6233 | static int i40e_validate_and_set_switch_mode(struct i40e_vsi *vsi) | |
6234 | { | |
6235 | u8 mode; | |
6236 | struct i40e_pf *pf = vsi->back; | |
6237 | struct i40e_hw *hw = &pf->hw; | |
6238 | int ret; | |
6239 | ||
6240 | ret = i40e_get_capabilities(pf, i40e_aqc_opc_list_dev_capabilities); | |
6241 | if (ret) | |
6242 | return -EINVAL; | |
6243 | ||
6244 | if (hw->dev_caps.switch_mode) { | |
6245 | /* if switch mode is set, support mode2 (non-tunneled for | |
6246 | * cloud filter) for now | |
6247 | */ | |
6248 | u32 switch_mode = hw->dev_caps.switch_mode & | |
6249 | I40E_SWITCH_MODE_MASK; | |
6250 | if (switch_mode >= I40E_CLOUD_FILTER_MODE1) { | |
6251 | if (switch_mode == I40E_CLOUD_FILTER_MODE2) | |
6252 | return 0; | |
6253 | dev_err(&pf->pdev->dev, | |
6254 | "Invalid switch_mode (%d), only non-tunneled mode for cloud filter is supported\n", | |
6255 | hw->dev_caps.switch_mode); | |
6256 | return -EINVAL; | |
6257 | } | |
6258 | } | |
6259 | ||
6260 | /* Set Bit 7 to be valid */ | |
6261 | mode = I40E_AQ_SET_SWITCH_BIT7_VALID; | |
6262 | ||
64e711ca AN |
6263 | /* Set L4type for TCP support */ |
6264 | mode |= I40E_AQ_SET_SWITCH_L4_TYPE_TCP; | |
2f4b411a AN |
6265 | |
6266 | /* Set cloud filter mode */ | |
6267 | mode |= I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL; | |
6268 | ||
6269 | /* Prep mode field for set_switch_config */ | |
6270 | ret = i40e_aq_set_switch_config(hw, pf->last_sw_conf_flags, | |
6271 | pf->last_sw_conf_valid_flags, | |
6272 | mode, NULL); | |
6273 | if (ret && hw->aq.asq_last_status != I40E_AQ_RC_ESRCH) | |
6274 | dev_err(&pf->pdev->dev, | |
6275 | "couldn't set switch config bits, err %s aq_err %s\n", | |
6276 | i40e_stat_str(hw, ret), | |
6277 | i40e_aq_str(hw, | |
6278 | hw->aq.asq_last_status)); | |
6279 | ||
6280 | return ret; | |
6281 | } | |
6282 | ||
8f88b303 AN |
6283 | /** |
6284 | * i40e_create_queue_channel - function to create channel | |
6285 | * @vsi: VSI to be configured | |
6286 | * @ch: ptr to channel (it contains channel specific params) | |
6287 | * | |
6288 | * This function creates channel (VSI) using num_queues specified by user, | |
6289 | * reconfigs RSS if needed. | |
6290 | **/ | |
6291 | int i40e_create_queue_channel(struct i40e_vsi *vsi, | |
6292 | struct i40e_channel *ch) | |
6293 | { | |
6294 | struct i40e_pf *pf = vsi->back; | |
6295 | bool reconfig_rss; | |
6296 | int err; | |
6297 | ||
6298 | if (!ch) | |
6299 | return -EINVAL; | |
6300 | ||
6301 | if (!ch->num_queue_pairs) { | |
6302 | dev_err(&pf->pdev->dev, "Invalid num_queues requested: %d\n", | |
6303 | ch->num_queue_pairs); | |
6304 | return -EINVAL; | |
6305 | } | |
6306 | ||
6307 | /* validate user requested num_queues for channel */ | |
6308 | err = i40e_validate_num_queues(pf, ch->num_queue_pairs, vsi, | |
6309 | &reconfig_rss); | |
6310 | if (err) { | |
6311 | dev_info(&pf->pdev->dev, "Failed to validate num_queues (%d)\n", | |
6312 | ch->num_queue_pairs); | |
6313 | return -EINVAL; | |
6314 | } | |
6315 | ||
6316 | /* By default we are in VEPA mode, if this is the first VF/VMDq | |
6317 | * VSI to be added switch to VEB mode. | |
6318 | */ | |
8f88b303 | 6319 | |
2e6d218c JJ |
6320 | if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) { |
6321 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
8f88b303 | 6322 | |
2e6d218c JJ |
6323 | if (vsi->type == I40E_VSI_MAIN) { |
6324 | if (pf->flags & I40E_FLAG_TC_MQPRIO) | |
6325 | i40e_do_reset(pf, I40E_PF_RESET_FLAG, true); | |
6326 | else | |
6327 | i40e_do_reset_safe(pf, I40E_PF_RESET_FLAG); | |
8f88b303 AN |
6328 | } |
6329 | /* now onwards for main VSI, number of queues will be value | |
6330 | * of TC0's queue count | |
6331 | */ | |
6332 | } | |
6333 | ||
6334 | /* By this time, vsi->cnt_q_avail shall be set to non-zero and | |
6335 | * it should be more than num_queues | |
6336 | */ | |
6337 | if (!vsi->cnt_q_avail || vsi->cnt_q_avail < ch->num_queue_pairs) { | |
6338 | dev_dbg(&pf->pdev->dev, | |
6339 | "Error: cnt_q_avail (%u) less than num_queues %d\n", | |
6340 | vsi->cnt_q_avail, ch->num_queue_pairs); | |
6341 | return -EINVAL; | |
6342 | } | |
6343 | ||
6344 | /* reconfig_rss only if vsi type is MAIN_VSI */ | |
6345 | if (reconfig_rss && (vsi->type == I40E_VSI_MAIN)) { | |
6346 | err = i40e_vsi_reconfig_rss(vsi, ch->num_queue_pairs); | |
6347 | if (err) { | |
6348 | dev_info(&pf->pdev->dev, | |
6349 | "Error: unable to reconfig rss for num_queues (%u)\n", | |
6350 | ch->num_queue_pairs); | |
6351 | return -EINVAL; | |
6352 | } | |
6353 | } | |
6354 | ||
6355 | if (!i40e_setup_channel(pf, vsi, ch)) { | |
6356 | dev_info(&pf->pdev->dev, "Failed to setup channel\n"); | |
6357 | return -EINVAL; | |
6358 | } | |
6359 | ||
6360 | dev_info(&pf->pdev->dev, | |
6361 | "Setup channel (id:%u) utilizing num_queues %d\n", | |
6362 | ch->seid, ch->num_queue_pairs); | |
6363 | ||
2027d4de AN |
6364 | /* configure VSI for BW limit */ |
6365 | if (ch->max_tx_rate) { | |
6c32e0d9 AB |
6366 | u64 credits = ch->max_tx_rate; |
6367 | ||
2027d4de AN |
6368 | if (i40e_set_bw_limit(vsi, ch->seid, ch->max_tx_rate)) |
6369 | return -EINVAL; | |
6370 | ||
6c32e0d9 | 6371 | do_div(credits, I40E_BW_CREDIT_DIVISOR); |
2027d4de AN |
6372 | dev_dbg(&pf->pdev->dev, |
6373 | "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n", | |
6374 | ch->max_tx_rate, | |
6c32e0d9 AB |
6375 | credits, |
6376 | ch->seid); | |
2027d4de AN |
6377 | } |
6378 | ||
8f88b303 AN |
6379 | /* in case of VF, this will be main SRIOV VSI */ |
6380 | ch->parent_vsi = vsi; | |
6381 | ||
6382 | /* and update main_vsi's count for queue_available to use */ | |
6383 | vsi->cnt_q_avail -= ch->num_queue_pairs; | |
6384 | ||
6385 | return 0; | |
6386 | } | |
6387 | ||
6388 | /** | |
6389 | * i40e_configure_queue_channels - Add queue channel for the given TCs | |
6390 | * @vsi: VSI to be configured | |
6391 | * | |
6392 | * Configures queue channel mapping to the given TCs | |
6393 | **/ | |
6394 | static int i40e_configure_queue_channels(struct i40e_vsi *vsi) | |
6395 | { | |
6396 | struct i40e_channel *ch; | |
6c32e0d9 | 6397 | u64 max_rate = 0; |
8f88b303 AN |
6398 | int ret = 0, i; |
6399 | ||
6400 | /* Create app vsi with the TCs. Main VSI with TC0 is already set up */ | |
aa5cb02a | 6401 | vsi->tc_seid_map[0] = vsi->seid; |
8f88b303 AN |
6402 | for (i = 1; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
6403 | if (vsi->tc_config.enabled_tc & BIT(i)) { | |
6404 | ch = kzalloc(sizeof(*ch), GFP_KERNEL); | |
6405 | if (!ch) { | |
6406 | ret = -ENOMEM; | |
6407 | goto err_free; | |
6408 | } | |
6409 | ||
6410 | INIT_LIST_HEAD(&ch->list); | |
6411 | ch->num_queue_pairs = | |
6412 | vsi->tc_config.tc_info[i].qcount; | |
6413 | ch->base_queue = | |
6414 | vsi->tc_config.tc_info[i].qoffset; | |
6415 | ||
2027d4de AN |
6416 | /* Bandwidth limit through tc interface is in bytes/s, |
6417 | * change to Mbit/s | |
6418 | */ | |
6c32e0d9 AB |
6419 | max_rate = vsi->mqprio_qopt.max_rate[i]; |
6420 | do_div(max_rate, I40E_BW_MBPS_DIVISOR); | |
6421 | ch->max_tx_rate = max_rate; | |
2027d4de | 6422 | |
8f88b303 AN |
6423 | list_add_tail(&ch->list, &vsi->ch_list); |
6424 | ||
6425 | ret = i40e_create_queue_channel(vsi, ch); | |
6426 | if (ret) { | |
6427 | dev_err(&vsi->back->pdev->dev, | |
6428 | "Failed creating queue channel with TC%d: queues %d\n", | |
6429 | i, ch->num_queue_pairs); | |
6430 | goto err_free; | |
6431 | } | |
aa5cb02a | 6432 | vsi->tc_seid_map[i] = ch->seid; |
8f88b303 AN |
6433 | } |
6434 | } | |
6435 | return ret; | |
6436 | ||
6437 | err_free: | |
6438 | i40e_remove_queue_channels(vsi); | |
6439 | return ret; | |
6440 | } | |
6441 | ||
4e3b35b0 NP |
6442 | /** |
6443 | * i40e_veb_config_tc - Configure TCs for given VEB | |
6444 | * @veb: given VEB | |
6445 | * @enabled_tc: TC bitmap | |
6446 | * | |
6447 | * Configures given TC bitmap for VEB (switching) element | |
6448 | **/ | |
6449 | int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc) | |
6450 | { | |
6451 | struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0}; | |
6452 | struct i40e_pf *pf = veb->pf; | |
6453 | int ret = 0; | |
6454 | int i; | |
6455 | ||
6456 | /* No TCs or already enabled TCs just return */ | |
6457 | if (!enabled_tc || veb->enabled_tc == enabled_tc) | |
6458 | return ret; | |
6459 | ||
6460 | bw_data.tc_valid_bits = enabled_tc; | |
6461 | /* bw_data.absolute_credits is not set (relative) */ | |
6462 | ||
6463 | /* Enable ETS TCs with equal BW Share for now */ | |
6464 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 6465 | if (enabled_tc & BIT(i)) |
4e3b35b0 NP |
6466 | bw_data.tc_bw_share_credits[i] = 1; |
6467 | } | |
6468 | ||
6469 | ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid, | |
6470 | &bw_data, NULL); | |
6471 | if (ret) { | |
6472 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6473 | "VEB bw config failed, err %s aq_err %s\n", |
6474 | i40e_stat_str(&pf->hw, ret), | |
6475 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
6476 | goto out; |
6477 | } | |
6478 | ||
6479 | /* Update the BW information */ | |
6480 | ret = i40e_veb_get_bw_info(veb); | |
6481 | if (ret) { | |
6482 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6483 | "Failed getting veb bw config, err %s aq_err %s\n", |
6484 | i40e_stat_str(&pf->hw, ret), | |
6485 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
6486 | } |
6487 | ||
6488 | out: | |
6489 | return ret; | |
6490 | } | |
6491 | ||
6492 | #ifdef CONFIG_I40E_DCB | |
6493 | /** | |
6494 | * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs | |
6495 | * @pf: PF struct | |
6496 | * | |
6497 | * Reconfigure VEB/VSIs on a given PF; it is assumed that | |
6498 | * the caller would've quiesce all the VSIs before calling | |
6499 | * this function | |
6500 | **/ | |
6501 | static void i40e_dcb_reconfigure(struct i40e_pf *pf) | |
6502 | { | |
6503 | u8 tc_map = 0; | |
6504 | int ret; | |
6505 | u8 v; | |
6506 | ||
6507 | /* Enable the TCs available on PF to all VEBs */ | |
6508 | tc_map = i40e_pf_get_tc_map(pf); | |
4b208eaa AK |
6509 | if (tc_map == I40E_DEFAULT_TRAFFIC_CLASS) |
6510 | return; | |
6511 | ||
4e3b35b0 NP |
6512 | for (v = 0; v < I40E_MAX_VEB; v++) { |
6513 | if (!pf->veb[v]) | |
6514 | continue; | |
6515 | ret = i40e_veb_config_tc(pf->veb[v], tc_map); | |
6516 | if (ret) { | |
6517 | dev_info(&pf->pdev->dev, | |
6518 | "Failed configuring TC for VEB seid=%d\n", | |
6519 | pf->veb[v]->seid); | |
6520 | /* Will try to configure as many components */ | |
6521 | } | |
6522 | } | |
6523 | ||
6524 | /* Update each VSI */ | |
505682cd | 6525 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
4e3b35b0 NP |
6526 | if (!pf->vsi[v]) |
6527 | continue; | |
6528 | ||
6529 | /* - Enable all TCs for the LAN VSI | |
6530 | * - For all others keep them at TC0 for now | |
6531 | */ | |
6532 | if (v == pf->lan_vsi) | |
6533 | tc_map = i40e_pf_get_tc_map(pf); | |
6534 | else | |
ea6acb7e | 6535 | tc_map = I40E_DEFAULT_TRAFFIC_CLASS; |
4e3b35b0 NP |
6536 | |
6537 | ret = i40e_vsi_config_tc(pf->vsi[v], tc_map); | |
6538 | if (ret) { | |
6539 | dev_info(&pf->pdev->dev, | |
6540 | "Failed configuring TC for VSI seid=%d\n", | |
6541 | pf->vsi[v]->seid); | |
6542 | /* Will try to configure as many components */ | |
6543 | } else { | |
0672a091 NP |
6544 | /* Re-configure VSI vectors based on updated TC map */ |
6545 | i40e_vsi_map_rings_to_vectors(pf->vsi[v]); | |
4e3b35b0 NP |
6546 | if (pf->vsi[v]->netdev) |
6547 | i40e_dcbnl_set_all(pf->vsi[v]); | |
6548 | } | |
6549 | } | |
6550 | } | |
6551 | ||
2fd75f31 NP |
6552 | /** |
6553 | * i40e_resume_port_tx - Resume port Tx | |
6554 | * @pf: PF struct | |
6555 | * | |
6556 | * Resume a port's Tx and issue a PF reset in case of failure to | |
6557 | * resume. | |
6558 | **/ | |
6559 | static int i40e_resume_port_tx(struct i40e_pf *pf) | |
6560 | { | |
6561 | struct i40e_hw *hw = &pf->hw; | |
6562 | int ret; | |
6563 | ||
6564 | ret = i40e_aq_resume_port_tx(hw, NULL); | |
6565 | if (ret) { | |
6566 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6567 | "Resume Port Tx failed, err %s aq_err %s\n", |
6568 | i40e_stat_str(&pf->hw, ret), | |
6569 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
2fd75f31 | 6570 | /* Schedule PF reset to recover */ |
0da36b97 | 6571 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
2fd75f31 NP |
6572 | i40e_service_event_schedule(pf); |
6573 | } | |
6574 | ||
6575 | return ret; | |
6576 | } | |
6577 | ||
4b208eaa AK |
6578 | /** |
6579 | * i40e_suspend_port_tx - Suspend port Tx | |
6580 | * @pf: PF struct | |
6581 | * | |
6582 | * Suspend a port's Tx and issue a PF reset in case of failure. | |
6583 | **/ | |
6584 | static int i40e_suspend_port_tx(struct i40e_pf *pf) | |
6585 | { | |
6586 | struct i40e_hw *hw = &pf->hw; | |
6587 | int ret; | |
6588 | ||
6589 | ret = i40e_aq_suspend_port_tx(hw, pf->mac_seid, NULL); | |
6590 | if (ret) { | |
6591 | dev_info(&pf->pdev->dev, | |
6592 | "Suspend Port Tx failed, err %s aq_err %s\n", | |
6593 | i40e_stat_str(&pf->hw, ret), | |
6594 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
6595 | /* Schedule PF reset to recover */ | |
6596 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); | |
6597 | i40e_service_event_schedule(pf); | |
6598 | } | |
6599 | ||
6600 | return ret; | |
6601 | } | |
6602 | ||
6603 | /** | |
6604 | * i40e_hw_set_dcb_config - Program new DCBX settings into HW | |
6605 | * @pf: PF being configured | |
6606 | * @new_cfg: New DCBX configuration | |
6607 | * | |
6608 | * Program DCB settings into HW and reconfigure VEB/VSIs on | |
6609 | * given PF. Uses "Set LLDP MIB" AQC to program the hardware. | |
6610 | **/ | |
6611 | static int i40e_hw_set_dcb_config(struct i40e_pf *pf, | |
6612 | struct i40e_dcbx_config *new_cfg) | |
6613 | { | |
6614 | struct i40e_dcbx_config *old_cfg = &pf->hw.local_dcbx_config; | |
6615 | int ret; | |
6616 | ||
6617 | /* Check if need reconfiguration */ | |
6618 | if (!memcmp(&new_cfg, &old_cfg, sizeof(new_cfg))) { | |
6619 | dev_dbg(&pf->pdev->dev, "No Change in DCB Config required.\n"); | |
6620 | return 0; | |
6621 | } | |
6622 | ||
6623 | /* Config change disable all VSIs */ | |
6624 | i40e_pf_quiesce_all_vsi(pf); | |
6625 | ||
6626 | /* Copy the new config to the current config */ | |
6627 | *old_cfg = *new_cfg; | |
6628 | old_cfg->etsrec = old_cfg->etscfg; | |
6629 | ret = i40e_set_dcb_config(&pf->hw); | |
6630 | if (ret) { | |
6631 | dev_info(&pf->pdev->dev, | |
6632 | "Set DCB Config failed, err %s aq_err %s\n", | |
6633 | i40e_stat_str(&pf->hw, ret), | |
6634 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
6635 | goto out; | |
6636 | } | |
6637 | ||
6638 | /* Changes in configuration update VEB/VSI */ | |
6639 | i40e_dcb_reconfigure(pf); | |
6640 | out: | |
6641 | /* In case of reset do not try to resume anything */ | |
6642 | if (!test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) { | |
6643 | /* Re-start the VSIs if disabled */ | |
6644 | ret = i40e_resume_port_tx(pf); | |
6645 | /* In case of error no point in resuming VSIs */ | |
6646 | if (ret) | |
6647 | goto err; | |
6648 | i40e_pf_unquiesce_all_vsi(pf); | |
6649 | } | |
6650 | err: | |
6651 | return ret; | |
6652 | } | |
6653 | ||
6654 | /** | |
6655 | * i40e_hw_dcb_config - Program new DCBX settings into HW | |
6656 | * @pf: PF being configured | |
6657 | * @new_cfg: New DCBX configuration | |
6658 | * | |
6659 | * Program DCB settings into HW and reconfigure VEB/VSIs on | |
6660 | * given PF | |
6661 | **/ | |
6662 | int i40e_hw_dcb_config(struct i40e_pf *pf, struct i40e_dcbx_config *new_cfg) | |
6663 | { | |
6664 | struct i40e_aqc_configure_switching_comp_ets_data ets_data; | |
6665 | u8 prio_type[I40E_MAX_TRAFFIC_CLASS] = {0}; | |
6666 | u32 mfs_tc[I40E_MAX_TRAFFIC_CLASS]; | |
6667 | struct i40e_dcbx_config *old_cfg; | |
6668 | u8 mode[I40E_MAX_TRAFFIC_CLASS]; | |
6669 | struct i40e_rx_pb_config pb_cfg; | |
6670 | struct i40e_hw *hw = &pf->hw; | |
6671 | u8 num_ports = hw->num_ports; | |
6672 | bool need_reconfig; | |
6673 | int ret = -EINVAL; | |
6674 | u8 lltc_map = 0; | |
6675 | u8 tc_map = 0; | |
6676 | u8 new_numtc; | |
6677 | u8 i; | |
6678 | ||
6679 | dev_dbg(&pf->pdev->dev, "Configuring DCB registers directly\n"); | |
6680 | /* Un-pack information to Program ETS HW via shared API | |
6681 | * numtc, tcmap | |
6682 | * LLTC map | |
6683 | * ETS/NON-ETS arbiter mode | |
6684 | * max exponent (credit refills) | |
6685 | * Total number of ports | |
6686 | * PFC priority bit-map | |
6687 | * Priority Table | |
6688 | * BW % per TC | |
6689 | * Arbiter mode between UPs sharing same TC | |
6690 | * TSA table (ETS or non-ETS) | |
6691 | * EEE enabled or not | |
6692 | * MFS TC table | |
6693 | */ | |
6694 | ||
6695 | new_numtc = i40e_dcb_get_num_tc(new_cfg); | |
6696 | ||
6697 | memset(&ets_data, 0, sizeof(ets_data)); | |
6698 | for (i = 0; i < new_numtc; i++) { | |
6699 | tc_map |= BIT(i); | |
6700 | switch (new_cfg->etscfg.tsatable[i]) { | |
6701 | case I40E_IEEE_TSA_ETS: | |
6702 | prio_type[i] = I40E_DCB_PRIO_TYPE_ETS; | |
6703 | ets_data.tc_bw_share_credits[i] = | |
6704 | new_cfg->etscfg.tcbwtable[i]; | |
6705 | break; | |
6706 | case I40E_IEEE_TSA_STRICT: | |
6707 | prio_type[i] = I40E_DCB_PRIO_TYPE_STRICT; | |
6708 | lltc_map |= BIT(i); | |
6709 | ets_data.tc_bw_share_credits[i] = | |
6710 | I40E_DCB_STRICT_PRIO_CREDITS; | |
6711 | break; | |
6712 | default: | |
6713 | /* Invalid TSA type */ | |
6714 | need_reconfig = false; | |
6715 | goto out; | |
6716 | } | |
6717 | } | |
6718 | ||
6719 | old_cfg = &hw->local_dcbx_config; | |
6720 | /* Check if need reconfiguration */ | |
6721 | need_reconfig = i40e_dcb_need_reconfig(pf, old_cfg, new_cfg); | |
6722 | ||
6723 | /* If needed, enable/disable frame tagging, disable all VSIs | |
6724 | * and suspend port tx | |
6725 | */ | |
6726 | if (need_reconfig) { | |
6727 | /* Enable DCB tagging only when more than one TC */ | |
6728 | if (new_numtc > 1) | |
6729 | pf->flags |= I40E_FLAG_DCB_ENABLED; | |
6730 | else | |
6731 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
6732 | ||
6733 | set_bit(__I40E_PORT_SUSPENDED, pf->state); | |
6734 | /* Reconfiguration needed quiesce all VSIs */ | |
6735 | i40e_pf_quiesce_all_vsi(pf); | |
6736 | ret = i40e_suspend_port_tx(pf); | |
6737 | if (ret) | |
6738 | goto err; | |
6739 | } | |
6740 | ||
6741 | /* Configure Port ETS Tx Scheduler */ | |
6742 | ets_data.tc_valid_bits = tc_map; | |
6743 | ets_data.tc_strict_priority_flags = lltc_map; | |
6744 | ret = i40e_aq_config_switch_comp_ets | |
6745 | (hw, pf->mac_seid, &ets_data, | |
6746 | i40e_aqc_opc_modify_switching_comp_ets, NULL); | |
6747 | if (ret) { | |
6748 | dev_info(&pf->pdev->dev, | |
6749 | "Modify Port ETS failed, err %s aq_err %s\n", | |
6750 | i40e_stat_str(&pf->hw, ret), | |
6751 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
6752 | goto out; | |
6753 | } | |
6754 | ||
6755 | /* Configure Rx ETS HW */ | |
6756 | memset(&mode, I40E_DCB_ARB_MODE_ROUND_ROBIN, sizeof(mode)); | |
6757 | i40e_dcb_hw_set_num_tc(hw, new_numtc); | |
6758 | i40e_dcb_hw_rx_fifo_config(hw, I40E_DCB_ARB_MODE_ROUND_ROBIN, | |
6759 | I40E_DCB_ARB_MODE_STRICT_PRIORITY, | |
6760 | I40E_DCB_DEFAULT_MAX_EXPONENT, | |
6761 | lltc_map); | |
6762 | i40e_dcb_hw_rx_cmd_monitor_config(hw, new_numtc, num_ports); | |
6763 | i40e_dcb_hw_rx_ets_bw_config(hw, new_cfg->etscfg.tcbwtable, mode, | |
6764 | prio_type); | |
6765 | i40e_dcb_hw_pfc_config(hw, new_cfg->pfc.pfcenable, | |
6766 | new_cfg->etscfg.prioritytable); | |
6767 | i40e_dcb_hw_rx_up2tc_config(hw, new_cfg->etscfg.prioritytable); | |
6768 | ||
6769 | /* Configure Rx Packet Buffers in HW */ | |
6770 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
6771 | mfs_tc[i] = pf->vsi[pf->lan_vsi]->netdev->mtu; | |
6772 | mfs_tc[i] += I40E_PACKET_HDR_PAD; | |
6773 | } | |
6774 | ||
6775 | i40e_dcb_hw_calculate_pool_sizes(hw, num_ports, | |
6776 | false, new_cfg->pfc.pfcenable, | |
6777 | mfs_tc, &pb_cfg); | |
6778 | i40e_dcb_hw_rx_pb_config(hw, &pf->pb_cfg, &pb_cfg); | |
6779 | ||
6780 | /* Update the local Rx Packet buffer config */ | |
6781 | pf->pb_cfg = pb_cfg; | |
6782 | ||
6783 | /* Inform the FW about changes to DCB configuration */ | |
6784 | ret = i40e_aq_dcb_updated(&pf->hw, NULL); | |
6785 | if (ret) { | |
6786 | dev_info(&pf->pdev->dev, | |
6787 | "DCB Updated failed, err %s aq_err %s\n", | |
6788 | i40e_stat_str(&pf->hw, ret), | |
6789 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
6790 | goto out; | |
6791 | } | |
6792 | ||
6793 | /* Update the port DCBx configuration */ | |
6794 | *old_cfg = *new_cfg; | |
6795 | ||
6796 | /* Changes in configuration update VEB/VSI */ | |
6797 | i40e_dcb_reconfigure(pf); | |
6798 | out: | |
6799 | /* Re-start the VSIs if disabled */ | |
6800 | if (need_reconfig) { | |
6801 | ret = i40e_resume_port_tx(pf); | |
6802 | ||
6803 | clear_bit(__I40E_PORT_SUSPENDED, pf->state); | |
6804 | /* In case of error no point in resuming VSIs */ | |
6805 | if (ret) | |
6806 | goto err; | |
6807 | ||
6808 | /* Wait for the PF's queues to be disabled */ | |
6809 | ret = i40e_pf_wait_queues_disabled(pf); | |
6810 | if (ret) { | |
6811 | /* Schedule PF reset to recover */ | |
6812 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); | |
6813 | i40e_service_event_schedule(pf); | |
6814 | goto err; | |
6815 | } else { | |
6816 | i40e_pf_unquiesce_all_vsi(pf); | |
6817 | set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state); | |
6818 | set_bit(__I40E_CLIENT_L2_CHANGE, pf->state); | |
6819 | } | |
7a75a841 AK |
6820 | /* registers are set, lets apply */ |
6821 | if (pf->hw_features & I40E_HW_USE_SET_LLDP_MIB) | |
6822 | ret = i40e_hw_set_dcb_config(pf, new_cfg); | |
4b208eaa AK |
6823 | } |
6824 | ||
6825 | err: | |
6826 | return ret; | |
6827 | } | |
6828 | ||
6829 | /** | |
6830 | * i40e_dcb_sw_default_config - Set default DCB configuration when DCB in SW | |
6831 | * @pf: PF being queried | |
6832 | * | |
6833 | * Set default DCB configuration in case DCB is to be done in SW. | |
6834 | **/ | |
6835 | int i40e_dcb_sw_default_config(struct i40e_pf *pf) | |
6836 | { | |
6837 | struct i40e_dcbx_config *dcb_cfg = &pf->hw.local_dcbx_config; | |
6838 | struct i40e_aqc_configure_switching_comp_ets_data ets_data; | |
6839 | struct i40e_hw *hw = &pf->hw; | |
6840 | int err; | |
6841 | ||
6842 | if (pf->hw_features & I40E_HW_USE_SET_LLDP_MIB) { | |
6843 | /* Update the local cached instance with TC0 ETS */ | |
6844 | memset(&pf->tmp_cfg, 0, sizeof(struct i40e_dcbx_config)); | |
6845 | pf->tmp_cfg.etscfg.willing = I40E_IEEE_DEFAULT_ETS_WILLING; | |
6846 | pf->tmp_cfg.etscfg.maxtcs = 0; | |
6847 | pf->tmp_cfg.etscfg.tcbwtable[0] = I40E_IEEE_DEFAULT_ETS_TCBW; | |
6848 | pf->tmp_cfg.etscfg.tsatable[0] = I40E_IEEE_TSA_ETS; | |
6849 | pf->tmp_cfg.pfc.willing = I40E_IEEE_DEFAULT_PFC_WILLING; | |
6850 | pf->tmp_cfg.pfc.pfccap = I40E_MAX_TRAFFIC_CLASS; | |
6851 | /* FW needs one App to configure HW */ | |
6852 | pf->tmp_cfg.numapps = I40E_IEEE_DEFAULT_NUM_APPS; | |
6853 | pf->tmp_cfg.app[0].selector = I40E_APP_SEL_ETHTYPE; | |
6854 | pf->tmp_cfg.app[0].priority = I40E_IEEE_DEFAULT_APP_PRIO; | |
6855 | pf->tmp_cfg.app[0].protocolid = I40E_APP_PROTOID_FCOE; | |
6856 | ||
6857 | return i40e_hw_set_dcb_config(pf, &pf->tmp_cfg); | |
6858 | } | |
6859 | ||
6860 | memset(&ets_data, 0, sizeof(ets_data)); | |
6861 | ets_data.tc_valid_bits = I40E_DEFAULT_TRAFFIC_CLASS; /* TC0 only */ | |
6862 | ets_data.tc_strict_priority_flags = 0; /* ETS */ | |
6863 | ets_data.tc_bw_share_credits[0] = I40E_IEEE_DEFAULT_ETS_TCBW; /* 100% to TC0 */ | |
6864 | ||
6865 | /* Enable ETS on the Physical port */ | |
6866 | err = i40e_aq_config_switch_comp_ets | |
6867 | (hw, pf->mac_seid, &ets_data, | |
6868 | i40e_aqc_opc_enable_switching_comp_ets, NULL); | |
6869 | if (err) { | |
6870 | dev_info(&pf->pdev->dev, | |
6871 | "Enable Port ETS failed, err %s aq_err %s\n", | |
6872 | i40e_stat_str(&pf->hw, err), | |
6873 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
6874 | err = -ENOENT; | |
6875 | goto out; | |
6876 | } | |
6877 | ||
6878 | /* Update the local cached instance with TC0 ETS */ | |
6879 | dcb_cfg->etscfg.willing = I40E_IEEE_DEFAULT_ETS_WILLING; | |
6880 | dcb_cfg->etscfg.cbs = 0; | |
6881 | dcb_cfg->etscfg.maxtcs = I40E_MAX_TRAFFIC_CLASS; | |
6882 | dcb_cfg->etscfg.tcbwtable[0] = I40E_IEEE_DEFAULT_ETS_TCBW; | |
6883 | ||
6884 | out: | |
6885 | return err; | |
6886 | } | |
6887 | ||
4e3b35b0 NP |
6888 | /** |
6889 | * i40e_init_pf_dcb - Initialize DCB configuration | |
6890 | * @pf: PF being configured | |
6891 | * | |
6892 | * Query the current DCB configuration and cache it | |
6893 | * in the hardware structure | |
6894 | **/ | |
6895 | static int i40e_init_pf_dcb(struct i40e_pf *pf) | |
6896 | { | |
6897 | struct i40e_hw *hw = &pf->hw; | |
4b208eaa | 6898 | int err; |
4e3b35b0 | 6899 | |
c61c8fe1 DE |
6900 | /* Do not enable DCB for SW1 and SW2 images even if the FW is capable |
6901 | * Also do not enable DCBx if FW LLDP agent is disabled | |
6902 | */ | |
4b208eaa AK |
6903 | if (pf->hw_features & I40E_HW_NO_DCB_SUPPORT) { |
6904 | dev_info(&pf->pdev->dev, "DCB is not supported.\n"); | |
ee02865e | 6905 | err = I40E_NOT_SUPPORTED; |
025b4a54 | 6906 | goto out; |
ee02865e | 6907 | } |
4b208eaa AK |
6908 | if (pf->flags & I40E_FLAG_DISABLE_FW_LLDP) { |
6909 | dev_info(&pf->pdev->dev, "FW LLDP is disabled, attempting SW DCB\n"); | |
6910 | err = i40e_dcb_sw_default_config(pf); | |
6911 | if (err) { | |
6912 | dev_info(&pf->pdev->dev, "Could not initialize SW DCB\n"); | |
6913 | goto out; | |
6914 | } | |
6915 | dev_info(&pf->pdev->dev, "SW DCB initialization succeeded.\n"); | |
6916 | pf->dcbx_cap = DCB_CAP_DCBX_HOST | | |
6917 | DCB_CAP_DCBX_VER_IEEE; | |
6918 | /* at init capable but disabled */ | |
6919 | pf->flags |= I40E_FLAG_DCB_CAPABLE; | |
6920 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
6921 | goto out; | |
6922 | } | |
541d9731 | 6923 | err = i40e_init_dcb(hw, true); |
4e3b35b0 NP |
6924 | if (!err) { |
6925 | /* Device/Function is not DCBX capable */ | |
6926 | if ((!hw->func_caps.dcb) || | |
6927 | (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) { | |
6928 | dev_info(&pf->pdev->dev, | |
6929 | "DCBX offload is not supported or is disabled for this PF.\n"); | |
4e3b35b0 NP |
6930 | } else { |
6931 | /* When status is not DISABLED then DCBX in FW */ | |
6932 | pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED | | |
6933 | DCB_CAP_DCBX_VER_IEEE; | |
4d9b6043 NP |
6934 | |
6935 | pf->flags |= I40E_FLAG_DCB_CAPABLE; | |
a036244c DE |
6936 | /* Enable DCB tagging only when more than one TC |
6937 | * or explicitly disable if only one TC | |
6938 | */ | |
4d9b6043 NP |
6939 | if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) |
6940 | pf->flags |= I40E_FLAG_DCB_ENABLED; | |
a036244c DE |
6941 | else |
6942 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
9fa61dd2 NP |
6943 | dev_dbg(&pf->pdev->dev, |
6944 | "DCBX offload is supported for this PF.\n"); | |
4e3b35b0 | 6945 | } |
64e1dcbb AB |
6946 | } else if (pf->hw.aq.asq_last_status == I40E_AQ_RC_EPERM) { |
6947 | dev_info(&pf->pdev->dev, "FW LLDP disabled for this PF.\n"); | |
6948 | pf->flags |= I40E_FLAG_DISABLE_FW_LLDP; | |
014269ff | 6949 | } else { |
aebfc816 | 6950 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6951 | "Query for DCB configuration failed, err %s aq_err %s\n", |
6952 | i40e_stat_str(&pf->hw, err), | |
6953 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
6954 | } |
6955 | ||
6956 | out: | |
6957 | return err; | |
6958 | } | |
6959 | #endif /* CONFIG_I40E_DCB */ | |
3c98f9ee | 6960 | |
cf05ed08 JB |
6961 | /** |
6962 | * i40e_print_link_message - print link up or down | |
6963 | * @vsi: the VSI for which link needs a message | |
f5254429 | 6964 | * @isup: true of link is up, false otherwise |
cf05ed08 | 6965 | */ |
c156f856 | 6966 | void i40e_print_link_message(struct i40e_vsi *vsi, bool isup) |
cf05ed08 | 6967 | { |
7ec9ba11 | 6968 | enum i40e_aq_link_speed new_speed; |
3fded466 | 6969 | struct i40e_pf *pf = vsi->back; |
a9165490 SN |
6970 | char *speed = "Unknown"; |
6971 | char *fc = "Unknown"; | |
3e03d7cc | 6972 | char *fec = ""; |
68e49702 | 6973 | char *req_fec = ""; |
3e03d7cc | 6974 | char *an = ""; |
cf05ed08 | 6975 | |
fd835129 SN |
6976 | if (isup) |
6977 | new_speed = pf->hw.phy.link_info.link_speed; | |
6978 | else | |
6979 | new_speed = I40E_LINK_SPEED_UNKNOWN; | |
7ec9ba11 FS |
6980 | |
6981 | if ((vsi->current_isup == isup) && (vsi->current_speed == new_speed)) | |
c156f856 MJ |
6982 | return; |
6983 | vsi->current_isup = isup; | |
7ec9ba11 | 6984 | vsi->current_speed = new_speed; |
cf05ed08 JB |
6985 | if (!isup) { |
6986 | netdev_info(vsi->netdev, "NIC Link is Down\n"); | |
6987 | return; | |
6988 | } | |
6989 | ||
148c2d80 GR |
6990 | /* Warn user if link speed on NPAR enabled partition is not at |
6991 | * least 10GB | |
6992 | */ | |
3fded466 SM |
6993 | if (pf->hw.func_caps.npar_enable && |
6994 | (pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB || | |
6995 | pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB)) | |
148c2d80 GR |
6996 | netdev_warn(vsi->netdev, |
6997 | "The partition detected link speed that is less than 10Gbps\n"); | |
6998 | ||
3fded466 | 6999 | switch (pf->hw.phy.link_info.link_speed) { |
cf05ed08 | 7000 | case I40E_LINK_SPEED_40GB: |
a9165490 | 7001 | speed = "40 G"; |
cf05ed08 | 7002 | break; |
ae24b409 | 7003 | case I40E_LINK_SPEED_20GB: |
a9165490 | 7004 | speed = "20 G"; |
ae24b409 | 7005 | break; |
3123237a CW |
7006 | case I40E_LINK_SPEED_25GB: |
7007 | speed = "25 G"; | |
7008 | break; | |
cf05ed08 | 7009 | case I40E_LINK_SPEED_10GB: |
a9165490 | 7010 | speed = "10 G"; |
cf05ed08 | 7011 | break; |
2e45d3f4 AL |
7012 | case I40E_LINK_SPEED_5GB: |
7013 | speed = "5 G"; | |
7014 | break; | |
7015 | case I40E_LINK_SPEED_2_5GB: | |
7016 | speed = "2.5 G"; | |
7017 | break; | |
cf05ed08 | 7018 | case I40E_LINK_SPEED_1GB: |
a9165490 | 7019 | speed = "1000 M"; |
cf05ed08 | 7020 | break; |
5960d33f | 7021 | case I40E_LINK_SPEED_100MB: |
a9165490 | 7022 | speed = "100 M"; |
5960d33f | 7023 | break; |
cf05ed08 JB |
7024 | default: |
7025 | break; | |
7026 | } | |
7027 | ||
3fded466 | 7028 | switch (pf->hw.fc.current_mode) { |
cf05ed08 | 7029 | case I40E_FC_FULL: |
a9165490 | 7030 | fc = "RX/TX"; |
cf05ed08 JB |
7031 | break; |
7032 | case I40E_FC_TX_PAUSE: | |
a9165490 | 7033 | fc = "TX"; |
cf05ed08 JB |
7034 | break; |
7035 | case I40E_FC_RX_PAUSE: | |
a9165490 | 7036 | fc = "RX"; |
cf05ed08 JB |
7037 | break; |
7038 | default: | |
a9165490 | 7039 | fc = "None"; |
cf05ed08 JB |
7040 | break; |
7041 | } | |
7042 | ||
3fded466 | 7043 | if (pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_25GB) { |
3fc9d8e1 AL |
7044 | req_fec = "None"; |
7045 | fec = "None"; | |
7046 | an = "False"; | |
3e03d7cc | 7047 | |
3fded466 | 7048 | if (pf->hw.phy.link_info.an_info & I40E_AQ_AN_COMPLETED) |
3fc9d8e1 | 7049 | an = "True"; |
3e03d7cc | 7050 | |
3fded466 | 7051 | if (pf->hw.phy.link_info.fec_info & |
3e03d7cc | 7052 | I40E_AQ_CONFIG_FEC_KR_ENA) |
3fc9d8e1 | 7053 | fec = "CL74 FC-FEC/BASE-R"; |
3fded466 | 7054 | else if (pf->hw.phy.link_info.fec_info & |
3e03d7cc | 7055 | I40E_AQ_CONFIG_FEC_RS_ENA) |
3fc9d8e1 | 7056 | fec = "CL108 RS-FEC"; |
68e49702 MS |
7057 | |
7058 | /* 'CL108 RS-FEC' should be displayed when RS is requested, or | |
7059 | * both RS and FC are requested | |
7060 | */ | |
7061 | if (vsi->back->hw.phy.link_info.req_fec_info & | |
7062 | (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS)) { | |
7063 | if (vsi->back->hw.phy.link_info.req_fec_info & | |
7064 | I40E_AQ_REQUEST_FEC_RS) | |
3fc9d8e1 | 7065 | req_fec = "CL108 RS-FEC"; |
68e49702 | 7066 | else |
3fc9d8e1 | 7067 | req_fec = "CL74 FC-FEC/BASE-R"; |
68e49702 | 7068 | } |
30cf856a JG |
7069 | netdev_info(vsi->netdev, |
7070 | "NIC Link is Up, %sbps Full Duplex, Requested FEC: %s, Negotiated FEC: %s, Autoneg: %s, Flow Control: %s\n", | |
7071 | speed, req_fec, fec, an, fc); | |
7072 | } else if (pf->hw.device_id == I40E_DEV_ID_KX_X722) { | |
7073 | req_fec = "None"; | |
7074 | fec = "None"; | |
7075 | an = "False"; | |
7076 | ||
7077 | if (pf->hw.phy.link_info.an_info & I40E_AQ_AN_COMPLETED) | |
7078 | an = "True"; | |
7079 | ||
7080 | if (pf->hw.phy.link_info.fec_info & | |
7081 | I40E_AQ_CONFIG_FEC_KR_ENA) | |
7082 | fec = "CL74 FC-FEC/BASE-R"; | |
7083 | ||
7084 | if (pf->hw.phy.link_info.req_fec_info & | |
7085 | I40E_AQ_REQUEST_FEC_KR) | |
7086 | req_fec = "CL74 FC-FEC/BASE-R"; | |
7087 | ||
22afe2cf CZ |
7088 | netdev_info(vsi->netdev, |
7089 | "NIC Link is Up, %sbps Full Duplex, Requested FEC: %s, Negotiated FEC: %s, Autoneg: %s, Flow Control: %s\n", | |
7090 | speed, req_fec, fec, an, fc); | |
7091 | } else { | |
7092 | netdev_info(vsi->netdev, | |
7093 | "NIC Link is Up, %sbps Full Duplex, Flow Control: %s\n", | |
7094 | speed, fc); | |
3e03d7cc HT |
7095 | } |
7096 | ||
cf05ed08 | 7097 | } |
4e3b35b0 | 7098 | |
41c445ff JB |
7099 | /** |
7100 | * i40e_up_complete - Finish the last steps of bringing up a connection | |
7101 | * @vsi: the VSI being configured | |
7102 | **/ | |
7103 | static int i40e_up_complete(struct i40e_vsi *vsi) | |
7104 | { | |
7105 | struct i40e_pf *pf = vsi->back; | |
7106 | int err; | |
7107 | ||
7108 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
7109 | i40e_vsi_configure_msix(vsi); | |
7110 | else | |
7111 | i40e_configure_msi_and_legacy(vsi); | |
7112 | ||
7113 | /* start rings */ | |
3aa7b74d | 7114 | err = i40e_vsi_start_rings(vsi); |
41c445ff JB |
7115 | if (err) |
7116 | return err; | |
7117 | ||
0da36b97 | 7118 | clear_bit(__I40E_VSI_DOWN, vsi->state); |
41c445ff JB |
7119 | i40e_napi_enable_all(vsi); |
7120 | i40e_vsi_enable_irq(vsi); | |
7121 | ||
7122 | if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) && | |
7123 | (vsi->netdev)) { | |
cf05ed08 | 7124 | i40e_print_link_message(vsi, true); |
41c445ff JB |
7125 | netif_tx_start_all_queues(vsi->netdev); |
7126 | netif_carrier_on(vsi->netdev); | |
7127 | } | |
ca64fa4e ASJ |
7128 | |
7129 | /* replay FDIR SB filters */ | |
1e1be8f6 ASJ |
7130 | if (vsi->type == I40E_VSI_FDIR) { |
7131 | /* reset fd counters */ | |
097dbf52 JK |
7132 | pf->fd_add_err = 0; |
7133 | pf->fd_atr_cnt = 0; | |
ca64fa4e | 7134 | i40e_fdir_filter_restore(vsi); |
1e1be8f6 | 7135 | } |
e3219ce6 ASJ |
7136 | |
7137 | /* On the next run of the service_task, notify any clients of the new | |
7138 | * opened netdev | |
7139 | */ | |
5f76a704 | 7140 | set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state); |
41c445ff JB |
7141 | i40e_service_event_schedule(pf); |
7142 | ||
7143 | return 0; | |
7144 | } | |
7145 | ||
7146 | /** | |
7147 | * i40e_vsi_reinit_locked - Reset the VSI | |
7148 | * @vsi: the VSI being configured | |
7149 | * | |
7150 | * Rebuild the ring structs after some configuration | |
7151 | * has changed, e.g. MTU size. | |
7152 | **/ | |
7153 | static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi) | |
7154 | { | |
7155 | struct i40e_pf *pf = vsi->back; | |
7156 | ||
0da36b97 | 7157 | while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) |
41c445ff JB |
7158 | usleep_range(1000, 2000); |
7159 | i40e_down(vsi); | |
7160 | ||
41c445ff | 7161 | i40e_up(vsi); |
0da36b97 | 7162 | clear_bit(__I40E_CONFIG_BUSY, pf->state); |
41c445ff JB |
7163 | } |
7164 | ||
c3880bd1 MS |
7165 | /** |
7166 | * i40e_force_link_state - Force the link status | |
7167 | * @pf: board private structure | |
7168 | * @is_up: whether the link state should be forced up or down | |
7169 | **/ | |
7170 | static i40e_status i40e_force_link_state(struct i40e_pf *pf, bool is_up) | |
7171 | { | |
7172 | struct i40e_aq_get_phy_abilities_resp abilities; | |
7173 | struct i40e_aq_set_phy_config config = {0}; | |
d5ec9e2c | 7174 | bool non_zero_phy_type = is_up; |
c3880bd1 MS |
7175 | struct i40e_hw *hw = &pf->hw; |
7176 | i40e_status err; | |
7177 | u64 mask; | |
e78d9a39 JS |
7178 | u8 speed; |
7179 | ||
7180 | /* Card might've been put in an unstable state by other drivers | |
7181 | * and applications, which causes incorrect speed values being | |
7182 | * set on startup. In order to clear speed registers, we call | |
7183 | * get_phy_capabilities twice, once to get initial state of | |
7184 | * available speeds, and once to get current PHY config. | |
7185 | */ | |
7186 | err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, | |
7187 | NULL); | |
7188 | if (err) { | |
7189 | dev_err(&pf->pdev->dev, | |
7190 | "failed to get phy cap., ret = %s last_status = %s\n", | |
7191 | i40e_stat_str(hw, err), | |
7192 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
7193 | return err; | |
7194 | } | |
7195 | speed = abilities.link_speed; | |
c3880bd1 MS |
7196 | |
7197 | /* Get the current phy config */ | |
7198 | err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, | |
7199 | NULL); | |
7200 | if (err) { | |
7201 | dev_err(&pf->pdev->dev, | |
7202 | "failed to get phy cap., ret = %s last_status = %s\n", | |
7203 | i40e_stat_str(hw, err), | |
7204 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
7205 | return err; | |
7206 | } | |
7207 | ||
7208 | /* If link needs to go up, but was not forced to go down, | |
e78d9a39 | 7209 | * and its speed values are OK, no need for a flap |
d5ec9e2c | 7210 | * if non_zero_phy_type was set, still need to force up |
c3880bd1 | 7211 | */ |
d5ec9e2c AK |
7212 | if (pf->flags & I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED) |
7213 | non_zero_phy_type = true; | |
7214 | else if (is_up && abilities.phy_type != 0 && abilities.link_speed != 0) | |
c3880bd1 MS |
7215 | return I40E_SUCCESS; |
7216 | ||
7217 | /* To force link we need to set bits for all supported PHY types, | |
7218 | * but there are now more than 32, so we need to split the bitmap | |
7219 | * across two fields. | |
7220 | */ | |
7221 | mask = I40E_PHY_TYPES_BITMASK; | |
d5ec9e2c AK |
7222 | config.phy_type = |
7223 | non_zero_phy_type ? cpu_to_le32((u32)(mask & 0xffffffff)) : 0; | |
7224 | config.phy_type_ext = | |
7225 | non_zero_phy_type ? (u8)((mask >> 32) & 0xff) : 0; | |
c3880bd1 MS |
7226 | /* Copy the old settings, except of phy_type */ |
7227 | config.abilities = abilities.abilities; | |
d5ec9e2c AK |
7228 | if (pf->flags & I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED) { |
7229 | if (is_up) | |
7230 | config.abilities |= I40E_AQ_PHY_ENABLE_LINK; | |
7231 | else | |
7232 | config.abilities &= ~(I40E_AQ_PHY_ENABLE_LINK); | |
7233 | } | |
e78d9a39 JS |
7234 | if (abilities.link_speed != 0) |
7235 | config.link_speed = abilities.link_speed; | |
7236 | else | |
7237 | config.link_speed = speed; | |
c3880bd1 MS |
7238 | config.eee_capability = abilities.eee_capability; |
7239 | config.eeer = abilities.eeer_val; | |
7240 | config.low_power_ctrl = abilities.d3_lpan; | |
1ac2ee23 MS |
7241 | config.fec_config = abilities.fec_cfg_curr_mod_ext_info & |
7242 | I40E_AQ_PHY_FEC_CONFIG_MASK; | |
c3880bd1 MS |
7243 | err = i40e_aq_set_phy_config(hw, &config, NULL); |
7244 | ||
7245 | if (err) { | |
7246 | dev_err(&pf->pdev->dev, | |
7247 | "set phy config ret = %s last_status = %s\n", | |
7248 | i40e_stat_str(&pf->hw, err), | |
7249 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7250 | return err; | |
7251 | } | |
7252 | ||
7253 | /* Update the link info */ | |
7254 | err = i40e_update_link_info(hw); | |
7255 | if (err) { | |
7256 | /* Wait a little bit (on 40G cards it sometimes takes a really | |
7257 | * long time for link to come back from the atomic reset) | |
7258 | * and try once more | |
7259 | */ | |
7260 | msleep(1000); | |
7261 | i40e_update_link_info(hw); | |
7262 | } | |
7263 | ||
d5ec9e2c | 7264 | i40e_aq_set_link_restart_an(hw, is_up, NULL); |
c3880bd1 MS |
7265 | |
7266 | return I40E_SUCCESS; | |
7267 | } | |
7268 | ||
d5ec9e2c AK |
7269 | /** |
7270 | * i40e_up - Bring the connection back up after being down | |
7271 | * @vsi: the VSI being configured | |
7272 | **/ | |
7273 | int i40e_up(struct i40e_vsi *vsi) | |
7274 | { | |
7275 | int err; | |
7276 | ||
7277 | if (vsi->type == I40E_VSI_MAIN && | |
7278 | (vsi->back->flags & I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED || | |
7279 | vsi->back->flags & I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED)) | |
7280 | i40e_force_link_state(vsi->back, true); | |
7281 | ||
7282 | err = i40e_vsi_configure(vsi); | |
7283 | if (!err) | |
7284 | err = i40e_up_complete(vsi); | |
7285 | ||
7286 | return err; | |
7287 | } | |
7288 | ||
41c445ff JB |
7289 | /** |
7290 | * i40e_down - Shutdown the connection processing | |
7291 | * @vsi: the VSI being stopped | |
7292 | **/ | |
7293 | void i40e_down(struct i40e_vsi *vsi) | |
7294 | { | |
7295 | int i; | |
7296 | ||
7297 | /* It is assumed that the caller of this function | |
d19cb64b | 7298 | * sets the vsi->state __I40E_VSI_DOWN bit. |
41c445ff JB |
7299 | */ |
7300 | if (vsi->netdev) { | |
7301 | netif_carrier_off(vsi->netdev); | |
7302 | netif_tx_disable(vsi->netdev); | |
7303 | } | |
7304 | i40e_vsi_disable_irq(vsi); | |
3aa7b74d | 7305 | i40e_vsi_stop_rings(vsi); |
c3880bd1 | 7306 | if (vsi->type == I40E_VSI_MAIN && |
d5ec9e2c AK |
7307 | (vsi->back->flags & I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED || |
7308 | vsi->back->flags & I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED)) | |
c3880bd1 | 7309 | i40e_force_link_state(vsi->back, false); |
41c445ff JB |
7310 | i40e_napi_disable_all(vsi); |
7311 | ||
7312 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
9f65e15b | 7313 | i40e_clean_tx_ring(vsi->tx_rings[i]); |
59eb2a88 | 7314 | if (i40e_enabled_xdp_vsi(vsi)) { |
b3873a5b MM |
7315 | /* Make sure that in-progress ndo_xdp_xmit and |
7316 | * ndo_xsk_wakeup calls are completed. | |
59eb2a88 BT |
7317 | */ |
7318 | synchronize_rcu(); | |
74608d17 | 7319 | i40e_clean_tx_ring(vsi->xdp_rings[i]); |
59eb2a88 | 7320 | } |
9f65e15b | 7321 | i40e_clean_rx_ring(vsi->rx_rings[i]); |
41c445ff | 7322 | } |
f980d445 | 7323 | |
41c445ff JB |
7324 | } |
7325 | ||
a9ce82f7 AN |
7326 | /** |
7327 | * i40e_validate_mqprio_qopt- validate queue mapping info | |
7328 | * @vsi: the VSI being configured | |
7329 | * @mqprio_qopt: queue parametrs | |
7330 | **/ | |
7331 | static int i40e_validate_mqprio_qopt(struct i40e_vsi *vsi, | |
7332 | struct tc_mqprio_qopt_offload *mqprio_qopt) | |
7333 | { | |
2027d4de | 7334 | u64 sum_max_rate = 0; |
6c32e0d9 | 7335 | u64 max_rate = 0; |
a9ce82f7 AN |
7336 | int i; |
7337 | ||
7338 | if (mqprio_qopt->qopt.offset[0] != 0 || | |
7339 | mqprio_qopt->qopt.num_tc < 1 || | |
7340 | mqprio_qopt->qopt.num_tc > I40E_MAX_TRAFFIC_CLASS) | |
7341 | return -EINVAL; | |
7342 | for (i = 0; ; i++) { | |
7343 | if (!mqprio_qopt->qopt.count[i]) | |
7344 | return -EINVAL; | |
2027d4de AN |
7345 | if (mqprio_qopt->min_rate[i]) { |
7346 | dev_err(&vsi->back->pdev->dev, | |
7347 | "Invalid min tx rate (greater than 0) specified\n"); | |
a9ce82f7 | 7348 | return -EINVAL; |
2027d4de | 7349 | } |
6c32e0d9 AB |
7350 | max_rate = mqprio_qopt->max_rate[i]; |
7351 | do_div(max_rate, I40E_BW_MBPS_DIVISOR); | |
7352 | sum_max_rate += max_rate; | |
2027d4de | 7353 | |
a9ce82f7 AN |
7354 | if (i >= mqprio_qopt->qopt.num_tc - 1) |
7355 | break; | |
7356 | if (mqprio_qopt->qopt.offset[i + 1] != | |
7357 | (mqprio_qopt->qopt.offset[i] + mqprio_qopt->qopt.count[i])) | |
7358 | return -EINVAL; | |
7359 | } | |
7360 | if (vsi->num_queue_pairs < | |
7361 | (mqprio_qopt->qopt.offset[i] + mqprio_qopt->qopt.count[i])) { | |
ea52faae JJ |
7362 | dev_err(&vsi->back->pdev->dev, |
7363 | "Failed to create traffic channel, insufficient number of queues.\n"); | |
a9ce82f7 AN |
7364 | return -EINVAL; |
7365 | } | |
2027d4de AN |
7366 | if (sum_max_rate > i40e_get_link_speed(vsi)) { |
7367 | dev_err(&vsi->back->pdev->dev, | |
7368 | "Invalid max tx rate specified\n"); | |
7369 | return -EINVAL; | |
7370 | } | |
a9ce82f7 AN |
7371 | return 0; |
7372 | } | |
7373 | ||
7374 | /** | |
7375 | * i40e_vsi_set_default_tc_config - set default values for tc configuration | |
7376 | * @vsi: the VSI being configured | |
7377 | **/ | |
7378 | static void i40e_vsi_set_default_tc_config(struct i40e_vsi *vsi) | |
7379 | { | |
7380 | u16 qcount; | |
7381 | int i; | |
7382 | ||
7383 | /* Only TC0 is enabled */ | |
7384 | vsi->tc_config.numtc = 1; | |
7385 | vsi->tc_config.enabled_tc = 1; | |
7386 | qcount = min_t(int, vsi->alloc_queue_pairs, | |
7387 | i40e_pf_get_max_q_per_tc(vsi->back)); | |
7388 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
059ff70c | 7389 | /* For the TC that is not enabled set the offset to default |
a9ce82f7 AN |
7390 | * queue and allocate one queue for the given TC. |
7391 | */ | |
7392 | vsi->tc_config.tc_info[i].qoffset = 0; | |
7393 | if (i == 0) | |
7394 | vsi->tc_config.tc_info[i].qcount = qcount; | |
7395 | else | |
7396 | vsi->tc_config.tc_info[i].qcount = 1; | |
7397 | vsi->tc_config.tc_info[i].netdev_tc = 0; | |
7398 | } | |
7399 | } | |
7400 | ||
1d8d80b4 HR |
7401 | /** |
7402 | * i40e_del_macvlan_filter | |
7403 | * @hw: pointer to the HW structure | |
7404 | * @seid: seid of the channel VSI | |
7405 | * @macaddr: the mac address to apply as a filter | |
7406 | * @aq_err: store the admin Q error | |
7407 | * | |
7408 | * This function deletes a mac filter on the channel VSI which serves as the | |
7409 | * macvlan. Returns 0 on success. | |
7410 | **/ | |
7411 | static i40e_status i40e_del_macvlan_filter(struct i40e_hw *hw, u16 seid, | |
7412 | const u8 *macaddr, int *aq_err) | |
7413 | { | |
7414 | struct i40e_aqc_remove_macvlan_element_data element; | |
7415 | i40e_status status; | |
7416 | ||
7417 | memset(&element, 0, sizeof(element)); | |
7418 | ether_addr_copy(element.mac_addr, macaddr); | |
7419 | element.vlan_tag = 0; | |
7420 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; | |
7421 | status = i40e_aq_remove_macvlan(hw, seid, &element, 1, NULL); | |
7422 | *aq_err = hw->aq.asq_last_status; | |
7423 | ||
7424 | return status; | |
7425 | } | |
7426 | ||
7427 | /** | |
7428 | * i40e_add_macvlan_filter | |
7429 | * @hw: pointer to the HW structure | |
7430 | * @seid: seid of the channel VSI | |
7431 | * @macaddr: the mac address to apply as a filter | |
7432 | * @aq_err: store the admin Q error | |
7433 | * | |
7434 | * This function adds a mac filter on the channel VSI which serves as the | |
7435 | * macvlan. Returns 0 on success. | |
7436 | **/ | |
7437 | static i40e_status i40e_add_macvlan_filter(struct i40e_hw *hw, u16 seid, | |
7438 | const u8 *macaddr, int *aq_err) | |
7439 | { | |
7440 | struct i40e_aqc_add_macvlan_element_data element; | |
7441 | i40e_status status; | |
7442 | u16 cmd_flags = 0; | |
7443 | ||
7444 | ether_addr_copy(element.mac_addr, macaddr); | |
7445 | element.vlan_tag = 0; | |
7446 | element.queue_number = 0; | |
7447 | element.match_method = I40E_AQC_MM_ERR_NO_RES; | |
7448 | cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; | |
7449 | element.flags = cpu_to_le16(cmd_flags); | |
7450 | status = i40e_aq_add_macvlan(hw, seid, &element, 1, NULL); | |
7451 | *aq_err = hw->aq.asq_last_status; | |
7452 | ||
7453 | return status; | |
7454 | } | |
7455 | ||
7456 | /** | |
7457 | * i40e_reset_ch_rings - Reset the queue contexts in a channel | |
7458 | * @vsi: the VSI we want to access | |
7459 | * @ch: the channel we want to access | |
7460 | */ | |
7461 | static void i40e_reset_ch_rings(struct i40e_vsi *vsi, struct i40e_channel *ch) | |
7462 | { | |
7463 | struct i40e_ring *tx_ring, *rx_ring; | |
7464 | u16 pf_q; | |
7465 | int i; | |
7466 | ||
7467 | for (i = 0; i < ch->num_queue_pairs; i++) { | |
7468 | pf_q = ch->base_queue + i; | |
7469 | tx_ring = vsi->tx_rings[pf_q]; | |
7470 | tx_ring->ch = NULL; | |
7471 | rx_ring = vsi->rx_rings[pf_q]; | |
7472 | rx_ring->ch = NULL; | |
7473 | } | |
7474 | } | |
7475 | ||
7476 | /** | |
7477 | * i40e_free_macvlan_channels | |
7478 | * @vsi: the VSI we want to access | |
7479 | * | |
7480 | * This function frees the Qs of the channel VSI from | |
7481 | * the stack and also deletes the channel VSIs which | |
7482 | * serve as macvlans. | |
7483 | */ | |
7484 | static void i40e_free_macvlan_channels(struct i40e_vsi *vsi) | |
7485 | { | |
7486 | struct i40e_channel *ch, *ch_tmp; | |
7487 | int ret; | |
7488 | ||
7489 | if (list_empty(&vsi->macvlan_list)) | |
7490 | return; | |
7491 | ||
7492 | list_for_each_entry_safe(ch, ch_tmp, &vsi->macvlan_list, list) { | |
7493 | struct i40e_vsi *parent_vsi; | |
7494 | ||
7495 | if (i40e_is_channel_macvlan(ch)) { | |
7496 | i40e_reset_ch_rings(vsi, ch); | |
7497 | clear_bit(ch->fwd->bit_no, vsi->fwd_bitmask); | |
7498 | netdev_unbind_sb_channel(vsi->netdev, ch->fwd->netdev); | |
7499 | netdev_set_sb_channel(ch->fwd->netdev, 0); | |
7500 | kfree(ch->fwd); | |
7501 | ch->fwd = NULL; | |
7502 | } | |
7503 | ||
7504 | list_del(&ch->list); | |
7505 | parent_vsi = ch->parent_vsi; | |
7506 | if (!parent_vsi || !ch->initialized) { | |
7507 | kfree(ch); | |
7508 | continue; | |
7509 | } | |
7510 | ||
7511 | /* remove the VSI */ | |
7512 | ret = i40e_aq_delete_element(&vsi->back->hw, ch->seid, | |
7513 | NULL); | |
7514 | if (ret) | |
7515 | dev_err(&vsi->back->pdev->dev, | |
7516 | "unable to remove channel (%d) for parent VSI(%d)\n", | |
7517 | ch->seid, parent_vsi->seid); | |
7518 | kfree(ch); | |
7519 | } | |
7520 | vsi->macvlan_cnt = 0; | |
7521 | } | |
7522 | ||
7523 | /** | |
7524 | * i40e_fwd_ring_up - bring the macvlan device up | |
7525 | * @vsi: the VSI we want to access | |
7526 | * @vdev: macvlan netdevice | |
7527 | * @fwd: the private fwd structure | |
7528 | */ | |
7529 | static int i40e_fwd_ring_up(struct i40e_vsi *vsi, struct net_device *vdev, | |
7530 | struct i40e_fwd_adapter *fwd) | |
7531 | { | |
7532 | int ret = 0, num_tc = 1, i, aq_err; | |
7533 | struct i40e_channel *ch, *ch_tmp; | |
7534 | struct i40e_pf *pf = vsi->back; | |
7535 | struct i40e_hw *hw = &pf->hw; | |
7536 | ||
7537 | if (list_empty(&vsi->macvlan_list)) | |
7538 | return -EINVAL; | |
7539 | ||
7540 | /* Go through the list and find an available channel */ | |
7541 | list_for_each_entry_safe(ch, ch_tmp, &vsi->macvlan_list, list) { | |
7542 | if (!i40e_is_channel_macvlan(ch)) { | |
7543 | ch->fwd = fwd; | |
7544 | /* record configuration for macvlan interface in vdev */ | |
7545 | for (i = 0; i < num_tc; i++) | |
7546 | netdev_bind_sb_channel_queue(vsi->netdev, vdev, | |
7547 | i, | |
7548 | ch->num_queue_pairs, | |
7549 | ch->base_queue); | |
7550 | for (i = 0; i < ch->num_queue_pairs; i++) { | |
7551 | struct i40e_ring *tx_ring, *rx_ring; | |
7552 | u16 pf_q; | |
7553 | ||
7554 | pf_q = ch->base_queue + i; | |
7555 | ||
7556 | /* Get to TX ring ptr */ | |
7557 | tx_ring = vsi->tx_rings[pf_q]; | |
7558 | tx_ring->ch = ch; | |
7559 | ||
7560 | /* Get the RX ring ptr */ | |
7561 | rx_ring = vsi->rx_rings[pf_q]; | |
7562 | rx_ring->ch = ch; | |
7563 | } | |
7564 | break; | |
7565 | } | |
7566 | } | |
7567 | ||
7568 | /* Guarantee all rings are updated before we update the | |
7569 | * MAC address filter. | |
7570 | */ | |
7571 | wmb(); | |
7572 | ||
7573 | /* Add a mac filter */ | |
7574 | ret = i40e_add_macvlan_filter(hw, ch->seid, vdev->dev_addr, &aq_err); | |
7575 | if (ret) { | |
7576 | /* if we cannot add the MAC rule then disable the offload */ | |
7577 | macvlan_release_l2fw_offload(vdev); | |
7578 | for (i = 0; i < ch->num_queue_pairs; i++) { | |
7579 | struct i40e_ring *rx_ring; | |
7580 | u16 pf_q; | |
7581 | ||
7582 | pf_q = ch->base_queue + i; | |
7583 | rx_ring = vsi->rx_rings[pf_q]; | |
7584 | rx_ring->netdev = NULL; | |
7585 | } | |
7586 | dev_info(&pf->pdev->dev, | |
7587 | "Error adding mac filter on macvlan err %s, aq_err %s\n", | |
7588 | i40e_stat_str(hw, ret), | |
7589 | i40e_aq_str(hw, aq_err)); | |
7590 | netdev_err(vdev, "L2fwd offload disabled to L2 filter error\n"); | |
7591 | } | |
7592 | ||
7593 | return ret; | |
7594 | } | |
7595 | ||
7596 | /** | |
7597 | * i40e_setup_macvlans - create the channels which will be macvlans | |
7598 | * @vsi: the VSI we want to access | |
7599 | * @macvlan_cnt: no. of macvlans to be setup | |
7600 | * @qcnt: no. of Qs per macvlan | |
7601 | * @vdev: macvlan netdevice | |
7602 | */ | |
7603 | static int i40e_setup_macvlans(struct i40e_vsi *vsi, u16 macvlan_cnt, u16 qcnt, | |
7604 | struct net_device *vdev) | |
7605 | { | |
7606 | struct i40e_pf *pf = vsi->back; | |
7607 | struct i40e_hw *hw = &pf->hw; | |
7608 | struct i40e_vsi_context ctxt; | |
7609 | u16 sections, qmap, num_qps; | |
7610 | struct i40e_channel *ch; | |
7611 | int i, pow, ret = 0; | |
7612 | u8 offset = 0; | |
7613 | ||
7614 | if (vsi->type != I40E_VSI_MAIN || !macvlan_cnt) | |
7615 | return -EINVAL; | |
7616 | ||
7617 | num_qps = vsi->num_queue_pairs - (macvlan_cnt * qcnt); | |
7618 | ||
7619 | /* find the next higher power-of-2 of num queue pairs */ | |
7620 | pow = fls(roundup_pow_of_two(num_qps) - 1); | |
7621 | ||
7622 | qmap = (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
7623 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
7624 | ||
7625 | /* Setup context bits for the main VSI */ | |
7626 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
7627 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
7628 | memset(&ctxt, 0, sizeof(ctxt)); | |
7629 | ctxt.seid = vsi->seid; | |
7630 | ctxt.pf_num = vsi->back->hw.pf_id; | |
7631 | ctxt.vf_num = 0; | |
7632 | ctxt.uplink_seid = vsi->uplink_seid; | |
7633 | ctxt.info = vsi->info; | |
7634 | ctxt.info.tc_mapping[0] = cpu_to_le16(qmap); | |
7635 | ctxt.info.mapping_flags |= cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
7636 | ctxt.info.queue_mapping[0] = cpu_to_le16(vsi->base_queue); | |
7637 | ctxt.info.valid_sections |= cpu_to_le16(sections); | |
7638 | ||
7639 | /* Reconfigure RSS for main VSI with new max queue count */ | |
7640 | vsi->rss_size = max_t(u16, num_qps, qcnt); | |
7641 | ret = i40e_vsi_config_rss(vsi); | |
7642 | if (ret) { | |
7643 | dev_info(&pf->pdev->dev, | |
7644 | "Failed to reconfig RSS for num_queues (%u)\n", | |
7645 | vsi->rss_size); | |
7646 | return ret; | |
7647 | } | |
7648 | vsi->reconfig_rss = true; | |
7649 | dev_dbg(&vsi->back->pdev->dev, | |
7650 | "Reconfigured RSS with num_queues (%u)\n", vsi->rss_size); | |
7651 | vsi->next_base_queue = num_qps; | |
7652 | vsi->cnt_q_avail = vsi->num_queue_pairs - num_qps; | |
7653 | ||
7654 | /* Update the VSI after updating the VSI queue-mapping | |
7655 | * information | |
7656 | */ | |
7657 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); | |
7658 | if (ret) { | |
7659 | dev_info(&pf->pdev->dev, | |
7660 | "Update vsi tc config failed, err %s aq_err %s\n", | |
7661 | i40e_stat_str(hw, ret), | |
7662 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
7663 | return ret; | |
7664 | } | |
7665 | /* update the local VSI info with updated queue map */ | |
7666 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
7667 | vsi->info.valid_sections = 0; | |
7668 | ||
7669 | /* Create channels for macvlans */ | |
7670 | INIT_LIST_HEAD(&vsi->macvlan_list); | |
7671 | for (i = 0; i < macvlan_cnt; i++) { | |
7672 | ch = kzalloc(sizeof(*ch), GFP_KERNEL); | |
7673 | if (!ch) { | |
7674 | ret = -ENOMEM; | |
7675 | goto err_free; | |
7676 | } | |
7677 | INIT_LIST_HEAD(&ch->list); | |
7678 | ch->num_queue_pairs = qcnt; | |
7679 | if (!i40e_setup_channel(pf, vsi, ch)) { | |
7680 | ret = -EINVAL; | |
27d46133 | 7681 | kfree(ch); |
1d8d80b4 HR |
7682 | goto err_free; |
7683 | } | |
7684 | ch->parent_vsi = vsi; | |
7685 | vsi->cnt_q_avail -= ch->num_queue_pairs; | |
7686 | vsi->macvlan_cnt++; | |
7687 | list_add_tail(&ch->list, &vsi->macvlan_list); | |
7688 | } | |
7689 | ||
7690 | return ret; | |
7691 | ||
7692 | err_free: | |
7693 | dev_info(&pf->pdev->dev, "Failed to setup macvlans\n"); | |
7694 | i40e_free_macvlan_channels(vsi); | |
7695 | ||
7696 | return ret; | |
7697 | } | |
7698 | ||
7699 | /** | |
7700 | * i40e_fwd_add - configure macvlans | |
7701 | * @netdev: net device to configure | |
7702 | * @vdev: macvlan netdevice | |
7703 | **/ | |
7704 | static void *i40e_fwd_add(struct net_device *netdev, struct net_device *vdev) | |
7705 | { | |
7706 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
7707 | u16 q_per_macvlan = 0, macvlan_cnt = 0, vectors; | |
7708 | struct i40e_vsi *vsi = np->vsi; | |
7709 | struct i40e_pf *pf = vsi->back; | |
7710 | struct i40e_fwd_adapter *fwd; | |
7711 | int avail_macvlan, ret; | |
7712 | ||
7713 | if ((pf->flags & I40E_FLAG_DCB_ENABLED)) { | |
7714 | netdev_info(netdev, "Macvlans are not supported when DCB is enabled\n"); | |
7715 | return ERR_PTR(-EINVAL); | |
7716 | } | |
7717 | if ((pf->flags & I40E_FLAG_TC_MQPRIO)) { | |
7718 | netdev_info(netdev, "Macvlans are not supported when HW TC offload is on\n"); | |
7719 | return ERR_PTR(-EINVAL); | |
7720 | } | |
7721 | if (pf->num_lan_msix < I40E_MIN_MACVLAN_VECTORS) { | |
7722 | netdev_info(netdev, "Not enough vectors available to support macvlans\n"); | |
7723 | return ERR_PTR(-EINVAL); | |
7724 | } | |
7725 | ||
7726 | /* The macvlan device has to be a single Q device so that the | |
7727 | * tc_to_txq field can be reused to pick the tx queue. | |
7728 | */ | |
7729 | if (netif_is_multiqueue(vdev)) | |
7730 | return ERR_PTR(-ERANGE); | |
7731 | ||
7732 | if (!vsi->macvlan_cnt) { | |
7733 | /* reserve bit 0 for the pf device */ | |
7734 | set_bit(0, vsi->fwd_bitmask); | |
7735 | ||
7736 | /* Try to reserve as many queues as possible for macvlans. First | |
7737 | * reserve 3/4th of max vectors, then half, then quarter and | |
7738 | * calculate Qs per macvlan as you go | |
7739 | */ | |
7740 | vectors = pf->num_lan_msix; | |
7741 | if (vectors <= I40E_MAX_MACVLANS && vectors > 64) { | |
7742 | /* allocate 4 Qs per macvlan and 32 Qs to the PF*/ | |
7743 | q_per_macvlan = 4; | |
7744 | macvlan_cnt = (vectors - 32) / 4; | |
7745 | } else if (vectors <= 64 && vectors > 32) { | |
7746 | /* allocate 2 Qs per macvlan and 16 Qs to the PF*/ | |
7747 | q_per_macvlan = 2; | |
7748 | macvlan_cnt = (vectors - 16) / 2; | |
7749 | } else if (vectors <= 32 && vectors > 16) { | |
7750 | /* allocate 1 Q per macvlan and 16 Qs to the PF*/ | |
7751 | q_per_macvlan = 1; | |
7752 | macvlan_cnt = vectors - 16; | |
7753 | } else if (vectors <= 16 && vectors > 8) { | |
7754 | /* allocate 1 Q per macvlan and 8 Qs to the PF */ | |
7755 | q_per_macvlan = 1; | |
7756 | macvlan_cnt = vectors - 8; | |
7757 | } else { | |
7758 | /* allocate 1 Q per macvlan and 1 Q to the PF */ | |
7759 | q_per_macvlan = 1; | |
7760 | macvlan_cnt = vectors - 1; | |
7761 | } | |
7762 | ||
7763 | if (macvlan_cnt == 0) | |
7764 | return ERR_PTR(-EBUSY); | |
7765 | ||
7766 | /* Quiesce VSI queues */ | |
7767 | i40e_quiesce_vsi(vsi); | |
7768 | ||
7769 | /* sets up the macvlans but does not "enable" them */ | |
7770 | ret = i40e_setup_macvlans(vsi, macvlan_cnt, q_per_macvlan, | |
7771 | vdev); | |
7772 | if (ret) | |
7773 | return ERR_PTR(ret); | |
7774 | ||
7775 | /* Unquiesce VSI */ | |
7776 | i40e_unquiesce_vsi(vsi); | |
7777 | } | |
7778 | avail_macvlan = find_first_zero_bit(vsi->fwd_bitmask, | |
7779 | vsi->macvlan_cnt); | |
7780 | if (avail_macvlan >= I40E_MAX_MACVLANS) | |
7781 | return ERR_PTR(-EBUSY); | |
7782 | ||
7783 | /* create the fwd struct */ | |
7784 | fwd = kzalloc(sizeof(*fwd), GFP_KERNEL); | |
7785 | if (!fwd) | |
7786 | return ERR_PTR(-ENOMEM); | |
7787 | ||
7788 | set_bit(avail_macvlan, vsi->fwd_bitmask); | |
7789 | fwd->bit_no = avail_macvlan; | |
7790 | netdev_set_sb_channel(vdev, avail_macvlan); | |
7791 | fwd->netdev = vdev; | |
7792 | ||
7793 | if (!netif_running(netdev)) | |
7794 | return fwd; | |
7795 | ||
7796 | /* Set fwd ring up */ | |
7797 | ret = i40e_fwd_ring_up(vsi, vdev, fwd); | |
7798 | if (ret) { | |
7799 | /* unbind the queues and drop the subordinate channel config */ | |
7800 | netdev_unbind_sb_channel(netdev, vdev); | |
7801 | netdev_set_sb_channel(vdev, 0); | |
7802 | ||
7803 | kfree(fwd); | |
7804 | return ERR_PTR(-EINVAL); | |
7805 | } | |
7806 | ||
7807 | return fwd; | |
7808 | } | |
7809 | ||
7810 | /** | |
7811 | * i40e_del_all_macvlans - Delete all the mac filters on the channels | |
7812 | * @vsi: the VSI we want to access | |
7813 | */ | |
7814 | static void i40e_del_all_macvlans(struct i40e_vsi *vsi) | |
7815 | { | |
7816 | struct i40e_channel *ch, *ch_tmp; | |
7817 | struct i40e_pf *pf = vsi->back; | |
7818 | struct i40e_hw *hw = &pf->hw; | |
7819 | int aq_err, ret = 0; | |
7820 | ||
7821 | if (list_empty(&vsi->macvlan_list)) | |
7822 | return; | |
7823 | ||
7824 | list_for_each_entry_safe(ch, ch_tmp, &vsi->macvlan_list, list) { | |
7825 | if (i40e_is_channel_macvlan(ch)) { | |
7826 | ret = i40e_del_macvlan_filter(hw, ch->seid, | |
7827 | i40e_channel_mac(ch), | |
7828 | &aq_err); | |
7829 | if (!ret) { | |
7830 | /* Reset queue contexts */ | |
7831 | i40e_reset_ch_rings(vsi, ch); | |
7832 | clear_bit(ch->fwd->bit_no, vsi->fwd_bitmask); | |
7833 | netdev_unbind_sb_channel(vsi->netdev, | |
7834 | ch->fwd->netdev); | |
7835 | netdev_set_sb_channel(ch->fwd->netdev, 0); | |
7836 | kfree(ch->fwd); | |
7837 | ch->fwd = NULL; | |
7838 | } | |
7839 | } | |
7840 | } | |
7841 | } | |
7842 | ||
7843 | /** | |
7844 | * i40e_fwd_del - delete macvlan interfaces | |
7845 | * @netdev: net device to configure | |
7846 | * @vdev: macvlan netdevice | |
7847 | */ | |
7848 | static void i40e_fwd_del(struct net_device *netdev, void *vdev) | |
7849 | { | |
7850 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
7851 | struct i40e_fwd_adapter *fwd = vdev; | |
7852 | struct i40e_channel *ch, *ch_tmp; | |
7853 | struct i40e_vsi *vsi = np->vsi; | |
7854 | struct i40e_pf *pf = vsi->back; | |
7855 | struct i40e_hw *hw = &pf->hw; | |
7856 | int aq_err, ret = 0; | |
7857 | ||
7858 | /* Find the channel associated with the macvlan and del mac filter */ | |
7859 | list_for_each_entry_safe(ch, ch_tmp, &vsi->macvlan_list, list) { | |
7860 | if (i40e_is_channel_macvlan(ch) && | |
7861 | ether_addr_equal(i40e_channel_mac(ch), | |
7862 | fwd->netdev->dev_addr)) { | |
7863 | ret = i40e_del_macvlan_filter(hw, ch->seid, | |
7864 | i40e_channel_mac(ch), | |
7865 | &aq_err); | |
7866 | if (!ret) { | |
7867 | /* Reset queue contexts */ | |
7868 | i40e_reset_ch_rings(vsi, ch); | |
7869 | clear_bit(ch->fwd->bit_no, vsi->fwd_bitmask); | |
7870 | netdev_unbind_sb_channel(netdev, fwd->netdev); | |
7871 | netdev_set_sb_channel(fwd->netdev, 0); | |
7872 | kfree(ch->fwd); | |
7873 | ch->fwd = NULL; | |
7874 | } else { | |
7875 | dev_info(&pf->pdev->dev, | |
7876 | "Error deleting mac filter on macvlan err %s, aq_err %s\n", | |
7877 | i40e_stat_str(hw, ret), | |
7878 | i40e_aq_str(hw, aq_err)); | |
7879 | } | |
7880 | break; | |
7881 | } | |
7882 | } | |
7883 | } | |
7884 | ||
41c445ff JB |
7885 | /** |
7886 | * i40e_setup_tc - configure multiple traffic classes | |
7887 | * @netdev: net device to configure | |
a9ce82f7 | 7888 | * @type_data: tc offload data |
41c445ff | 7889 | **/ |
a9ce82f7 | 7890 | static int i40e_setup_tc(struct net_device *netdev, void *type_data) |
41c445ff | 7891 | { |
a9ce82f7 | 7892 | struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; |
41c445ff JB |
7893 | struct i40e_netdev_priv *np = netdev_priv(netdev); |
7894 | struct i40e_vsi *vsi = np->vsi; | |
7895 | struct i40e_pf *pf = vsi->back; | |
a9ce82f7 AN |
7896 | u8 enabled_tc = 0, num_tc, hw; |
7897 | bool need_reset = false; | |
3e957b37 | 7898 | int old_queue_pairs; |
41c445ff | 7899 | int ret = -EINVAL; |
a9ce82f7 | 7900 | u16 mode; |
41c445ff JB |
7901 | int i; |
7902 | ||
3e957b37 | 7903 | old_queue_pairs = vsi->num_queue_pairs; |
a9ce82f7 AN |
7904 | num_tc = mqprio_qopt->qopt.num_tc; |
7905 | hw = mqprio_qopt->qopt.hw; | |
7906 | mode = mqprio_qopt->mode; | |
7907 | if (!hw) { | |
7908 | pf->flags &= ~I40E_FLAG_TC_MQPRIO; | |
7909 | memcpy(&vsi->mqprio_qopt, mqprio_qopt, sizeof(*mqprio_qopt)); | |
7910 | goto config_tc; | |
41c445ff JB |
7911 | } |
7912 | ||
7913 | /* Check if MFP enabled */ | |
7914 | if (pf->flags & I40E_FLAG_MFP_ENABLED) { | |
a9ce82f7 AN |
7915 | netdev_info(netdev, |
7916 | "Configuring TC not supported in MFP mode\n"); | |
7917 | return ret; | |
41c445ff | 7918 | } |
a9ce82f7 AN |
7919 | switch (mode) { |
7920 | case TC_MQPRIO_MODE_DCB: | |
7921 | pf->flags &= ~I40E_FLAG_TC_MQPRIO; | |
41c445ff | 7922 | |
a9ce82f7 AN |
7923 | /* Check if DCB enabled to continue */ |
7924 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) { | |
7925 | netdev_info(netdev, | |
7926 | "DCB is not enabled for adapter\n"); | |
7927 | return ret; | |
7928 | } | |
7929 | ||
7930 | /* Check whether tc count is within enabled limit */ | |
7931 | if (num_tc > i40e_pf_get_num_tc(pf)) { | |
7932 | netdev_info(netdev, | |
7933 | "TC count greater than enabled on link for adapter\n"); | |
7934 | return ret; | |
7935 | } | |
7936 | break; | |
7937 | case TC_MQPRIO_MODE_CHANNEL: | |
7938 | if (pf->flags & I40E_FLAG_DCB_ENABLED) { | |
7939 | netdev_info(netdev, | |
7940 | "Full offload of TC Mqprio options is not supported when DCB is enabled\n"); | |
7941 | return ret; | |
7942 | } | |
7943 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
7944 | return ret; | |
7945 | ret = i40e_validate_mqprio_qopt(vsi, mqprio_qopt); | |
7946 | if (ret) | |
7947 | return ret; | |
7948 | memcpy(&vsi->mqprio_qopt, mqprio_qopt, | |
7949 | sizeof(*mqprio_qopt)); | |
7950 | pf->flags |= I40E_FLAG_TC_MQPRIO; | |
7951 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
7952 | break; | |
7953 | default: | |
7954 | return -EINVAL; | |
41c445ff JB |
7955 | } |
7956 | ||
a9ce82f7 | 7957 | config_tc: |
41c445ff | 7958 | /* Generate TC map for number of tc requested */ |
a9ce82f7 | 7959 | for (i = 0; i < num_tc; i++) |
75f5cea9 | 7960 | enabled_tc |= BIT(i); |
41c445ff JB |
7961 | |
7962 | /* Requesting same TC configuration as already enabled */ | |
a9ce82f7 AN |
7963 | if (enabled_tc == vsi->tc_config.enabled_tc && |
7964 | mode != TC_MQPRIO_MODE_CHANNEL) | |
41c445ff JB |
7965 | return 0; |
7966 | ||
7967 | /* Quiesce VSI queues */ | |
7968 | i40e_quiesce_vsi(vsi); | |
7969 | ||
a9ce82f7 AN |
7970 | if (!hw && !(pf->flags & I40E_FLAG_TC_MQPRIO)) |
7971 | i40e_remove_queue_channels(vsi); | |
7972 | ||
41c445ff JB |
7973 | /* Configure VSI for enabled TCs */ |
7974 | ret = i40e_vsi_config_tc(vsi, enabled_tc); | |
7975 | if (ret) { | |
7976 | netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n", | |
7977 | vsi->seid); | |
a9ce82f7 | 7978 | need_reset = true; |
41c445ff | 7979 | goto exit; |
2e6d218c JJ |
7980 | } else if (enabled_tc && |
7981 | (!is_power_of_2(vsi->tc_config.tc_info[0].qcount))) { | |
7982 | netdev_info(netdev, | |
7983 | "Failed to create channel. Override queues (%u) not power of 2\n", | |
7984 | vsi->tc_config.tc_info[0].qcount); | |
7985 | ret = -EINVAL; | |
7986 | need_reset = true; | |
7987 | goto exit; | |
41c445ff JB |
7988 | } |
7989 | ||
2e6d218c JJ |
7990 | dev_info(&vsi->back->pdev->dev, |
7991 | "Setup channel (id:%u) utilizing num_queues %d\n", | |
7992 | vsi->seid, vsi->tc_config.tc_info[0].qcount); | |
7993 | ||
8f88b303 | 7994 | if (pf->flags & I40E_FLAG_TC_MQPRIO) { |
2027d4de | 7995 | if (vsi->mqprio_qopt.max_rate[0]) { |
6c32e0d9 AB |
7996 | u64 max_tx_rate = vsi->mqprio_qopt.max_rate[0]; |
7997 | ||
7998 | do_div(max_tx_rate, I40E_BW_MBPS_DIVISOR); | |
2027d4de AN |
7999 | ret = i40e_set_bw_limit(vsi, vsi->seid, max_tx_rate); |
8000 | if (!ret) { | |
6c32e0d9 AB |
8001 | u64 credits = max_tx_rate; |
8002 | ||
8003 | do_div(credits, I40E_BW_CREDIT_DIVISOR); | |
2027d4de AN |
8004 | dev_dbg(&vsi->back->pdev->dev, |
8005 | "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n", | |
8006 | max_tx_rate, | |
6c32e0d9 | 8007 | credits, |
2027d4de AN |
8008 | vsi->seid); |
8009 | } else { | |
8010 | need_reset = true; | |
8011 | goto exit; | |
8012 | } | |
8013 | } | |
8f88b303 | 8014 | ret = i40e_configure_queue_channels(vsi); |
4e3b35b0 | 8015 | if (ret) { |
3e957b37 | 8016 | vsi->num_queue_pairs = old_queue_pairs; |
8f88b303 AN |
8017 | netdev_info(netdev, |
8018 | "Failed configuring queue channels\n"); | |
a9ce82f7 | 8019 | need_reset = true; |
8f88b303 | 8020 | goto exit; |
4e3b35b0 NP |
8021 | } |
8022 | } | |
8023 | ||
41c445ff | 8024 | exit: |
a9ce82f7 AN |
8025 | /* Reset the configuration data to defaults, only TC0 is enabled */ |
8026 | if (need_reset) { | |
8027 | i40e_vsi_set_default_tc_config(vsi); | |
8028 | need_reset = false; | |
8029 | } | |
4e3b35b0 | 8030 | |
8f88b303 AN |
8031 | /* Unquiesce VSI */ |
8032 | i40e_unquiesce_vsi(vsi); | |
41c445ff JB |
8033 | return ret; |
8034 | } | |
4e3b35b0 | 8035 | |
2f4b411a AN |
8036 | /** |
8037 | * i40e_set_cld_element - sets cloud filter element data | |
8038 | * @filter: cloud filter rule | |
8039 | * @cld: ptr to cloud filter element data | |
8040 | * | |
8041 | * This is helper function to copy data into cloud filter element | |
8042 | **/ | |
8043 | static inline void | |
8044 | i40e_set_cld_element(struct i40e_cloud_filter *filter, | |
8045 | struct i40e_aqc_cloud_filters_element_data *cld) | |
8046 | { | |
2f4b411a | 8047 | u32 ipa; |
b32cddd2 | 8048 | int i; |
2f4b411a AN |
8049 | |
8050 | memset(cld, 0, sizeof(*cld)); | |
8051 | ether_addr_copy(cld->outer_mac, filter->dst_mac); | |
8052 | ether_addr_copy(cld->inner_mac, filter->src_mac); | |
8053 | ||
8054 | if (filter->n_proto != ETH_P_IP && filter->n_proto != ETH_P_IPV6) | |
8055 | return; | |
8056 | ||
8057 | if (filter->n_proto == ETH_P_IPV6) { | |
8058 | #define IPV6_MAX_INDEX (ARRAY_SIZE(filter->dst_ipv6) - 1) | |
b32cddd2 | 8059 | for (i = 0; i < ARRAY_SIZE(filter->dst_ipv6); i++) { |
2f4b411a | 8060 | ipa = be32_to_cpu(filter->dst_ipv6[IPV6_MAX_INDEX - i]); |
b32cddd2 NC |
8061 | |
8062 | *(__le32 *)&cld->ipaddr.raw_v6.data[i * 2] = cpu_to_le32(ipa); | |
4e3b35b0 | 8063 | } |
2f4b411a AN |
8064 | } else { |
8065 | ipa = be32_to_cpu(filter->dst_ipv4); | |
b32cddd2 | 8066 | |
2f4b411a | 8067 | memcpy(&cld->ipaddr.v4.data, &ipa, sizeof(ipa)); |
4e3b35b0 | 8068 | } |
2f4b411a AN |
8069 | |
8070 | cld->inner_vlan = cpu_to_le16(ntohs(filter->vlan_id)); | |
8071 | ||
8072 | /* tenant_id is not supported by FW now, once the support is enabled | |
8073 | * fill the cld->tenant_id with cpu_to_le32(filter->tenant_id) | |
8074 | */ | |
8075 | if (filter->tenant_id) | |
8076 | return; | |
4e3b35b0 NP |
8077 | } |
8078 | ||
2fd75f31 | 8079 | /** |
2f4b411a AN |
8080 | * i40e_add_del_cloud_filter - Add/del cloud filter |
8081 | * @vsi: pointer to VSI | |
8082 | * @filter: cloud filter rule | |
8083 | * @add: if true, add, if false, delete | |
2fd75f31 | 8084 | * |
2f4b411a AN |
8085 | * Add or delete a cloud filter for a specific flow spec. |
8086 | * Returns 0 if the filter were successfully added. | |
2fd75f31 | 8087 | **/ |
e284fc28 AD |
8088 | int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, |
8089 | struct i40e_cloud_filter *filter, bool add) | |
2fd75f31 | 8090 | { |
2f4b411a AN |
8091 | struct i40e_aqc_cloud_filters_element_data cld_filter; |
8092 | struct i40e_pf *pf = vsi->back; | |
2fd75f31 | 8093 | int ret; |
2f4b411a AN |
8094 | static const u16 flag_table[128] = { |
8095 | [I40E_CLOUD_FILTER_FLAGS_OMAC] = | |
8096 | I40E_AQC_ADD_CLOUD_FILTER_OMAC, | |
8097 | [I40E_CLOUD_FILTER_FLAGS_IMAC] = | |
8098 | I40E_AQC_ADD_CLOUD_FILTER_IMAC, | |
8099 | [I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN] = | |
8100 | I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN, | |
8101 | [I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID] = | |
8102 | I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID, | |
8103 | [I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC] = | |
8104 | I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC, | |
8105 | [I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID] = | |
8106 | I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID, | |
8107 | [I40E_CLOUD_FILTER_FLAGS_IIP] = | |
8108 | I40E_AQC_ADD_CLOUD_FILTER_IIP, | |
8109 | }; | |
8110 | ||
8111 | if (filter->flags >= ARRAY_SIZE(flag_table)) | |
8112 | return I40E_ERR_CONFIG; | |
8113 | ||
d2c788f7 MP |
8114 | memset(&cld_filter, 0, sizeof(cld_filter)); |
8115 | ||
2f4b411a AN |
8116 | /* copy element needed to add cloud filter from filter */ |
8117 | i40e_set_cld_element(filter, &cld_filter); | |
8118 | ||
8119 | if (filter->tunnel_type != I40E_CLOUD_TNL_TYPE_NONE) | |
8120 | cld_filter.flags = cpu_to_le16(filter->tunnel_type << | |
8121 | I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT); | |
8122 | ||
8123 | if (filter->n_proto == ETH_P_IPV6) | |
8124 | cld_filter.flags |= cpu_to_le16(flag_table[filter->flags] | | |
8125 | I40E_AQC_ADD_CLOUD_FLAGS_IPV6); | |
8126 | else | |
8127 | cld_filter.flags |= cpu_to_le16(flag_table[filter->flags] | | |
8128 | I40E_AQC_ADD_CLOUD_FLAGS_IPV4); | |
2fd75f31 | 8129 | |
2f4b411a AN |
8130 | if (add) |
8131 | ret = i40e_aq_add_cloud_filters(&pf->hw, filter->seid, | |
8132 | &cld_filter, 1); | |
8133 | else | |
8134 | ret = i40e_aq_rem_cloud_filters(&pf->hw, filter->seid, | |
8135 | &cld_filter, 1); | |
8136 | if (ret) | |
8137 | dev_dbg(&pf->pdev->dev, | |
8138 | "Failed to %s cloud filter using l4 port %u, err %d aq_err %d\n", | |
8139 | add ? "add" : "delete", filter->dst_port, ret, | |
8140 | pf->hw.aq.asq_last_status); | |
8141 | else | |
2fd75f31 | 8142 | dev_info(&pf->pdev->dev, |
2f4b411a AN |
8143 | "%s cloud filter for VSI: %d\n", |
8144 | add ? "Added" : "Deleted", filter->seid); | |
2fd75f31 NP |
8145 | return ret; |
8146 | } | |
8147 | ||
4e3b35b0 | 8148 | /** |
2f4b411a AN |
8149 | * i40e_add_del_cloud_filter_big_buf - Add/del cloud filter using big_buf |
8150 | * @vsi: pointer to VSI | |
8151 | * @filter: cloud filter rule | |
8152 | * @add: if true, add, if false, delete | |
4e3b35b0 | 8153 | * |
2f4b411a AN |
8154 | * Add or delete a cloud filter for a specific flow spec using big buffer. |
8155 | * Returns 0 if the filter were successfully added. | |
4e3b35b0 | 8156 | **/ |
e284fc28 AD |
8157 | int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, |
8158 | struct i40e_cloud_filter *filter, | |
8159 | bool add) | |
4e3b35b0 | 8160 | { |
2f4b411a AN |
8161 | struct i40e_aqc_cloud_filters_element_bb cld_filter; |
8162 | struct i40e_pf *pf = vsi->back; | |
8163 | int ret; | |
4e3b35b0 | 8164 | |
2f4b411a AN |
8165 | /* Both (src/dst) valid mac_addr are not supported */ |
8166 | if ((is_valid_ether_addr(filter->dst_mac) && | |
8167 | is_valid_ether_addr(filter->src_mac)) || | |
8168 | (is_multicast_ether_addr(filter->dst_mac) && | |
8169 | is_multicast_ether_addr(filter->src_mac))) | |
64e711ca | 8170 | return -EOPNOTSUPP; |
025b4a54 | 8171 | |
64e711ca AN |
8172 | /* Big buffer cloud filter needs 'L4 port' to be non-zero. Also, UDP |
8173 | * ports are not supported via big buffer now. | |
2f4b411a | 8174 | */ |
64e711ca AN |
8175 | if (!filter->dst_port || filter->ip_proto == IPPROTO_UDP) |
8176 | return -EOPNOTSUPP; | |
4d9b6043 | 8177 | |
2f4b411a | 8178 | /* adding filter using src_port/src_ip is not supported at this stage */ |
61c1e0eb MP |
8179 | if (filter->src_port || |
8180 | (filter->src_ipv4 && filter->n_proto != ETH_P_IPV6) || | |
2f4b411a | 8181 | !ipv6_addr_any(&filter->ip.v6.src_ip6)) |
64e711ca | 8182 | return -EOPNOTSUPP; |
2f4b411a | 8183 | |
d2c788f7 MP |
8184 | memset(&cld_filter, 0, sizeof(cld_filter)); |
8185 | ||
2f4b411a AN |
8186 | /* copy element needed to add cloud filter from filter */ |
8187 | i40e_set_cld_element(filter, &cld_filter.element); | |
8188 | ||
8189 | if (is_valid_ether_addr(filter->dst_mac) || | |
8190 | is_valid_ether_addr(filter->src_mac) || | |
8191 | is_multicast_ether_addr(filter->dst_mac) || | |
8192 | is_multicast_ether_addr(filter->src_mac)) { | |
8193 | /* MAC + IP : unsupported mode */ | |
8194 | if (filter->dst_ipv4) | |
64e711ca | 8195 | return -EOPNOTSUPP; |
2f4b411a AN |
8196 | |
8197 | /* since we validated that L4 port must be valid before | |
8198 | * we get here, start with respective "flags" value | |
8199 | * and update if vlan is present or not | |
8200 | */ | |
8201 | cld_filter.element.flags = | |
8202 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT); | |
8203 | ||
8204 | if (filter->vlan_id) { | |
8205 | cld_filter.element.flags = | |
8206 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT); | |
4e3b35b0 | 8207 | } |
2f4b411a | 8208 | |
61c1e0eb | 8209 | } else if ((filter->dst_ipv4 && filter->n_proto != ETH_P_IPV6) || |
2f4b411a AN |
8210 | !ipv6_addr_any(&filter->ip.v6.dst_ip6)) { |
8211 | cld_filter.element.flags = | |
8212 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_IP_PORT); | |
8213 | if (filter->n_proto == ETH_P_IPV6) | |
8214 | cld_filter.element.flags |= | |
8215 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FLAGS_IPV6); | |
8216 | else | |
8217 | cld_filter.element.flags |= | |
8218 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FLAGS_IPV4); | |
014269ff | 8219 | } else { |
2f4b411a AN |
8220 | dev_err(&pf->pdev->dev, |
8221 | "either mac or ip has to be valid for cloud filter\n"); | |
8222 | return -EINVAL; | |
4e3b35b0 NP |
8223 | } |
8224 | ||
2f4b411a AN |
8225 | /* Now copy L4 port in Byte 6..7 in general fields */ |
8226 | cld_filter.general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0] = | |
8227 | be16_to_cpu(filter->dst_port); | |
8228 | ||
8229 | if (add) { | |
8230 | /* Validate current device switch mode, change if necessary */ | |
8231 | ret = i40e_validate_and_set_switch_mode(vsi); | |
8232 | if (ret) { | |
8233 | dev_err(&pf->pdev->dev, | |
8234 | "failed to set switch mode, ret %d\n", | |
8235 | ret); | |
8236 | return ret; | |
8237 | } | |
8238 | ||
8239 | ret = i40e_aq_add_cloud_filters_bb(&pf->hw, filter->seid, | |
8240 | &cld_filter, 1); | |
8241 | } else { | |
8242 | ret = i40e_aq_rem_cloud_filters_bb(&pf->hw, filter->seid, | |
8243 | &cld_filter, 1); | |
8244 | } | |
8245 | ||
8246 | if (ret) | |
8247 | dev_dbg(&pf->pdev->dev, | |
8248 | "Failed to %s cloud filter(big buffer) err %d aq_err %d\n", | |
8249 | add ? "add" : "delete", ret, pf->hw.aq.asq_last_status); | |
8250 | else | |
8251 | dev_info(&pf->pdev->dev, | |
8252 | "%s cloud filter for VSI: %d, L4 port: %d\n", | |
8253 | add ? "add" : "delete", filter->seid, | |
8254 | ntohs(filter->dst_port)); | |
8255 | return ret; | |
4e3b35b0 | 8256 | } |
2f4b411a | 8257 | |
cf05ed08 | 8258 | /** |
2f4b411a AN |
8259 | * i40e_parse_cls_flower - Parse tc flower filters provided by kernel |
8260 | * @vsi: Pointer to VSI | |
b50f7bca | 8261 | * @f: Pointer to struct flow_cls_offload |
2f4b411a AN |
8262 | * @filter: Pointer to cloud filter structure |
8263 | * | |
8264 | **/ | |
8265 | static int i40e_parse_cls_flower(struct i40e_vsi *vsi, | |
f9e30088 | 8266 | struct flow_cls_offload *f, |
2f4b411a | 8267 | struct i40e_cloud_filter *filter) |
cf05ed08 | 8268 | { |
f9e30088 | 8269 | struct flow_rule *rule = flow_cls_offload_flow_rule(f); |
8f256622 | 8270 | struct flow_dissector *dissector = rule->match.dissector; |
2f4b411a AN |
8271 | u16 n_proto_mask = 0, n_proto_key = 0, addr_type = 0; |
8272 | struct i40e_pf *pf = vsi->back; | |
8273 | u8 field_flags = 0; | |
8274 | ||
8f256622 | 8275 | if (dissector->used_keys & |
2f4b411a AN |
8276 | ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | |
8277 | BIT(FLOW_DISSECTOR_KEY_BASIC) | | |
8278 | BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | | |
8279 | BIT(FLOW_DISSECTOR_KEY_VLAN) | | |
8280 | BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | | |
8281 | BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | | |
8282 | BIT(FLOW_DISSECTOR_KEY_PORTS) | | |
8283 | BIT(FLOW_DISSECTOR_KEY_ENC_KEYID))) { | |
8284 | dev_err(&pf->pdev->dev, "Unsupported key used: 0x%x\n", | |
8f256622 | 8285 | dissector->used_keys); |
2f4b411a AN |
8286 | return -EOPNOTSUPP; |
8287 | } | |
cf05ed08 | 8288 | |
8f256622 PNA |
8289 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_KEYID)) { |
8290 | struct flow_match_enc_keyid match; | |
7ec9ba11 | 8291 | |
8f256622 PNA |
8292 | flow_rule_match_enc_keyid(rule, &match); |
8293 | if (match.mask->keyid != 0) | |
2f4b411a AN |
8294 | field_flags |= I40E_CLOUD_FIELD_TEN_ID; |
8295 | ||
8f256622 | 8296 | filter->tenant_id = be32_to_cpu(match.key->keyid); |
cf05ed08 JB |
8297 | } |
8298 | ||
8f256622 PNA |
8299 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { |
8300 | struct flow_match_basic match; | |
2f4b411a | 8301 | |
8f256622 PNA |
8302 | flow_rule_match_basic(rule, &match); |
8303 | n_proto_key = ntohs(match.key->n_proto); | |
8304 | n_proto_mask = ntohs(match.mask->n_proto); | |
2f4b411a AN |
8305 | |
8306 | if (n_proto_key == ETH_P_ALL) { | |
8307 | n_proto_key = 0; | |
8308 | n_proto_mask = 0; | |
8309 | } | |
8310 | filter->n_proto = n_proto_key & n_proto_mask; | |
8f256622 | 8311 | filter->ip_proto = match.key->ip_proto; |
cf05ed08 JB |
8312 | } |
8313 | ||
8f256622 PNA |
8314 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { |
8315 | struct flow_match_eth_addrs match; | |
2f4b411a | 8316 | |
8f256622 | 8317 | flow_rule_match_eth_addrs(rule, &match); |
2f4b411a AN |
8318 | |
8319 | /* use is_broadcast and is_zero to check for all 0xf or 0 */ | |
8f256622 PNA |
8320 | if (!is_zero_ether_addr(match.mask->dst)) { |
8321 | if (is_broadcast_ether_addr(match.mask->dst)) { | |
2f4b411a AN |
8322 | field_flags |= I40E_CLOUD_FIELD_OMAC; |
8323 | } else { | |
8324 | dev_err(&pf->pdev->dev, "Bad ether dest mask %pM\n", | |
8f256622 | 8325 | match.mask->dst); |
2f4b411a AN |
8326 | return I40E_ERR_CONFIG; |
8327 | } | |
8328 | } | |
8329 | ||
8f256622 PNA |
8330 | if (!is_zero_ether_addr(match.mask->src)) { |
8331 | if (is_broadcast_ether_addr(match.mask->src)) { | |
2f4b411a AN |
8332 | field_flags |= I40E_CLOUD_FIELD_IMAC; |
8333 | } else { | |
8334 | dev_err(&pf->pdev->dev, "Bad ether src mask %pM\n", | |
8f256622 | 8335 | match.mask->src); |
2f4b411a AN |
8336 | return I40E_ERR_CONFIG; |
8337 | } | |
8338 | } | |
8f256622 PNA |
8339 | ether_addr_copy(filter->dst_mac, match.key->dst); |
8340 | ether_addr_copy(filter->src_mac, match.key->src); | |
8341 | } | |
8342 | ||
8343 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { | |
8344 | struct flow_match_vlan match; | |
8345 | ||
8346 | flow_rule_match_vlan(rule, &match); | |
8347 | if (match.mask->vlan_id) { | |
8348 | if (match.mask->vlan_id == VLAN_VID_MASK) { | |
2f4b411a | 8349 | field_flags |= I40E_CLOUD_FIELD_IVLAN; |
3e03d7cc | 8350 | |
2f4b411a AN |
8351 | } else { |
8352 | dev_err(&pf->pdev->dev, "Bad vlan mask 0x%04x\n", | |
8f256622 | 8353 | match.mask->vlan_id); |
2f4b411a AN |
8354 | return I40E_ERR_CONFIG; |
8355 | } | |
8356 | } | |
68e49702 | 8357 | |
8f256622 | 8358 | filter->vlan_id = cpu_to_be16(match.key->vlan_id); |
2f4b411a AN |
8359 | } |
8360 | ||
8f256622 PNA |
8361 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) { |
8362 | struct flow_match_control match; | |
2f4b411a | 8363 | |
8f256622 PNA |
8364 | flow_rule_match_control(rule, &match); |
8365 | addr_type = match.key->addr_type; | |
2f4b411a AN |
8366 | } |
8367 | ||
8368 | if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { | |
8f256622 PNA |
8369 | struct flow_match_ipv4_addrs match; |
8370 | ||
8371 | flow_rule_match_ipv4_addrs(rule, &match); | |
8372 | if (match.mask->dst) { | |
8373 | if (match.mask->dst == cpu_to_be32(0xffffffff)) { | |
2f4b411a AN |
8374 | field_flags |= I40E_CLOUD_FIELD_IIP; |
8375 | } else { | |
bf1099b5 | 8376 | dev_err(&pf->pdev->dev, "Bad ip dst mask %pI4b\n", |
8f256622 | 8377 | &match.mask->dst); |
2f4b411a AN |
8378 | return I40E_ERR_CONFIG; |
8379 | } | |
8380 | } | |
8381 | ||
8f256622 PNA |
8382 | if (match.mask->src) { |
8383 | if (match.mask->src == cpu_to_be32(0xffffffff)) { | |
2f4b411a AN |
8384 | field_flags |= I40E_CLOUD_FIELD_IIP; |
8385 | } else { | |
bf1099b5 | 8386 | dev_err(&pf->pdev->dev, "Bad ip src mask %pI4b\n", |
8f256622 | 8387 | &match.mask->src); |
2f4b411a AN |
8388 | return I40E_ERR_CONFIG; |
8389 | } | |
8390 | } | |
8391 | ||
8392 | if (field_flags & I40E_CLOUD_FIELD_TEN_ID) { | |
8393 | dev_err(&pf->pdev->dev, "Tenant id not allowed for ip filter\n"); | |
8394 | return I40E_ERR_CONFIG; | |
8395 | } | |
8f256622 PNA |
8396 | filter->dst_ipv4 = match.key->dst; |
8397 | filter->src_ipv4 = match.key->src; | |
2f4b411a AN |
8398 | } |
8399 | ||
8400 | if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { | |
8f256622 PNA |
8401 | struct flow_match_ipv6_addrs match; |
8402 | ||
8403 | flow_rule_match_ipv6_addrs(rule, &match); | |
2f4b411a AN |
8404 | |
8405 | /* src and dest IPV6 address should not be LOOPBACK | |
8406 | * (0:0:0:0:0:0:0:1), which can be represented as ::1 | |
68e49702 | 8407 | */ |
8f256622 PNA |
8408 | if (ipv6_addr_loopback(&match.key->dst) || |
8409 | ipv6_addr_loopback(&match.key->src)) { | |
2f4b411a AN |
8410 | dev_err(&pf->pdev->dev, |
8411 | "Bad ipv6, addr is LOOPBACK\n"); | |
8412 | return I40E_ERR_CONFIG; | |
8413 | } | |
8f256622 PNA |
8414 | if (!ipv6_addr_any(&match.mask->dst) || |
8415 | !ipv6_addr_any(&match.mask->src)) | |
2f4b411a AN |
8416 | field_flags |= I40E_CLOUD_FIELD_IIP; |
8417 | ||
8f256622 | 8418 | memcpy(&filter->src_ipv6, &match.key->src.s6_addr32, |
2f4b411a | 8419 | sizeof(filter->src_ipv6)); |
8f256622 | 8420 | memcpy(&filter->dst_ipv6, &match.key->dst.s6_addr32, |
2f4b411a AN |
8421 | sizeof(filter->dst_ipv6)); |
8422 | } | |
8423 | ||
8f256622 PNA |
8424 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) { |
8425 | struct flow_match_ports match; | |
2f4b411a | 8426 | |
8f256622 PNA |
8427 | flow_rule_match_ports(rule, &match); |
8428 | if (match.mask->src) { | |
8429 | if (match.mask->src == cpu_to_be16(0xffff)) { | |
2f4b411a AN |
8430 | field_flags |= I40E_CLOUD_FIELD_IIP; |
8431 | } else { | |
8432 | dev_err(&pf->pdev->dev, "Bad src port mask 0x%04x\n", | |
8f256622 | 8433 | be16_to_cpu(match.mask->src)); |
2f4b411a AN |
8434 | return I40E_ERR_CONFIG; |
8435 | } | |
8436 | } | |
8437 | ||
8f256622 PNA |
8438 | if (match.mask->dst) { |
8439 | if (match.mask->dst == cpu_to_be16(0xffff)) { | |
2f4b411a AN |
8440 | field_flags |= I40E_CLOUD_FIELD_IIP; |
8441 | } else { | |
8442 | dev_err(&pf->pdev->dev, "Bad dst port mask 0x%04x\n", | |
8f256622 | 8443 | be16_to_cpu(match.mask->dst)); |
2f4b411a AN |
8444 | return I40E_ERR_CONFIG; |
8445 | } | |
8446 | } | |
8447 | ||
8f256622 PNA |
8448 | filter->dst_port = match.key->dst; |
8449 | filter->src_port = match.key->src; | |
2f4b411a AN |
8450 | |
8451 | switch (filter->ip_proto) { | |
8452 | case IPPROTO_TCP: | |
8453 | case IPPROTO_UDP: | |
8454 | break; | |
8455 | default: | |
8456 | dev_err(&pf->pdev->dev, | |
8457 | "Only UDP and TCP transport are supported\n"); | |
8458 | return -EINVAL; | |
68e49702 | 8459 | } |
3e03d7cc | 8460 | } |
2f4b411a AN |
8461 | filter->flags = field_flags; |
8462 | return 0; | |
8463 | } | |
3e03d7cc | 8464 | |
2f4b411a AN |
8465 | /** |
8466 | * i40e_handle_tclass: Forward to a traffic class on the device | |
8467 | * @vsi: Pointer to VSI | |
8468 | * @tc: traffic class index on the device | |
8469 | * @filter: Pointer to cloud filter structure | |
8470 | * | |
8471 | **/ | |
8472 | static int i40e_handle_tclass(struct i40e_vsi *vsi, u32 tc, | |
8473 | struct i40e_cloud_filter *filter) | |
8474 | { | |
8475 | struct i40e_channel *ch, *ch_tmp; | |
8476 | ||
8477 | /* direct to a traffic class on the same device */ | |
8478 | if (tc == 0) { | |
8479 | filter->seid = vsi->seid; | |
8480 | return 0; | |
8481 | } else if (vsi->tc_config.enabled_tc & BIT(tc)) { | |
8482 | if (!filter->dst_port) { | |
8483 | dev_err(&vsi->back->pdev->dev, | |
8484 | "Specify destination port to direct to traffic class that is not default\n"); | |
8485 | return -EINVAL; | |
8486 | } | |
8487 | if (list_empty(&vsi->ch_list)) | |
8488 | return -EINVAL; | |
8489 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, | |
8490 | list) { | |
8491 | if (ch->seid == vsi->tc_seid_map[tc]) | |
8492 | filter->seid = ch->seid; | |
8493 | } | |
8494 | return 0; | |
8495 | } | |
8496 | dev_err(&vsi->back->pdev->dev, "TC is not enabled\n"); | |
8497 | return -EINVAL; | |
cf05ed08 | 8498 | } |
4e3b35b0 | 8499 | |
41c445ff | 8500 | /** |
2f4b411a AN |
8501 | * i40e_configure_clsflower - Configure tc flower filters |
8502 | * @vsi: Pointer to VSI | |
f9e30088 | 8503 | * @cls_flower: Pointer to struct flow_cls_offload |
2f4b411a | 8504 | * |
41c445ff | 8505 | **/ |
2f4b411a | 8506 | static int i40e_configure_clsflower(struct i40e_vsi *vsi, |
f9e30088 | 8507 | struct flow_cls_offload *cls_flower) |
41c445ff | 8508 | { |
2f4b411a AN |
8509 | int tc = tc_classid_to_hwtc(vsi->netdev, cls_flower->classid); |
8510 | struct i40e_cloud_filter *filter = NULL; | |
41c445ff | 8511 | struct i40e_pf *pf = vsi->back; |
2f4b411a | 8512 | int err = 0; |
41c445ff | 8513 | |
2f4b411a AN |
8514 | if (tc < 0) { |
8515 | dev_err(&vsi->back->pdev->dev, "Invalid traffic class\n"); | |
bc4244c6 | 8516 | return -EOPNOTSUPP; |
2f4b411a | 8517 | } |
41c445ff | 8518 | |
2f4b411a AN |
8519 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) || |
8520 | test_bit(__I40E_RESET_INTR_RECEIVED, pf->state)) | |
8521 | return -EBUSY; | |
41c445ff | 8522 | |
2f4b411a AN |
8523 | if (pf->fdir_pf_active_filters || |
8524 | (!hlist_empty(&pf->fdir_filter_list))) { | |
8525 | dev_err(&vsi->back->pdev->dev, | |
8526 | "Flow Director Sideband filters exists, turn ntuple off to configure cloud filters\n"); | |
8527 | return -EINVAL; | |
8528 | } | |
41c445ff | 8529 | |
2f4b411a AN |
8530 | if (vsi->back->flags & I40E_FLAG_FD_SB_ENABLED) { |
8531 | dev_err(&vsi->back->pdev->dev, | |
8532 | "Disable Flow Director Sideband, configuring Cloud filters via tc-flower\n"); | |
8533 | vsi->back->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
8534 | vsi->back->flags |= I40E_FLAG_FD_SB_TO_CLOUD_FILTER; | |
41c445ff | 8535 | } |
ca64fa4e | 8536 | |
2f4b411a AN |
8537 | filter = kzalloc(sizeof(*filter), GFP_KERNEL); |
8538 | if (!filter) | |
8539 | return -ENOMEM; | |
8540 | ||
8541 | filter->cookie = cls_flower->cookie; | |
8542 | ||
8543 | err = i40e_parse_cls_flower(vsi, cls_flower, filter); | |
8544 | if (err < 0) | |
8545 | goto err; | |
8546 | ||
8547 | err = i40e_handle_tclass(vsi, tc, filter); | |
8548 | if (err < 0) | |
8549 | goto err; | |
8550 | ||
8551 | /* Add cloud filter */ | |
8552 | if (filter->dst_port) | |
8553 | err = i40e_add_del_cloud_filter_big_buf(vsi, filter, true); | |
8554 | else | |
8555 | err = i40e_add_del_cloud_filter(vsi, filter, true); | |
8556 | ||
8557 | if (err) { | |
5aff430d GS |
8558 | dev_err(&pf->pdev->dev, "Failed to add cloud filter, err %d\n", |
8559 | err); | |
2f4b411a | 8560 | goto err; |
1e1be8f6 | 8561 | } |
e3219ce6 | 8562 | |
2f4b411a AN |
8563 | /* add filter to the ordered list */ |
8564 | INIT_HLIST_NODE(&filter->cloud_node); | |
41c445ff | 8565 | |
2f4b411a AN |
8566 | hlist_add_head(&filter->cloud_node, &pf->cloud_filter_list); |
8567 | ||
8568 | pf->num_cloud_filters++; | |
8569 | ||
8570 | return err; | |
8571 | err: | |
8572 | kfree(filter); | |
8573 | return err; | |
41c445ff JB |
8574 | } |
8575 | ||
8576 | /** | |
2f4b411a AN |
8577 | * i40e_find_cloud_filter - Find the could filter in the list |
8578 | * @vsi: Pointer to VSI | |
8579 | * @cookie: filter specific cookie | |
41c445ff | 8580 | * |
41c445ff | 8581 | **/ |
2f4b411a AN |
8582 | static struct i40e_cloud_filter *i40e_find_cloud_filter(struct i40e_vsi *vsi, |
8583 | unsigned long *cookie) | |
41c445ff | 8584 | { |
2f4b411a AN |
8585 | struct i40e_cloud_filter *filter = NULL; |
8586 | struct hlist_node *node2; | |
41c445ff | 8587 | |
2f4b411a AN |
8588 | hlist_for_each_entry_safe(filter, node2, |
8589 | &vsi->back->cloud_filter_list, cloud_node) | |
8590 | if (!memcmp(cookie, &filter->cookie, sizeof(filter->cookie))) | |
8591 | return filter; | |
8592 | return NULL; | |
41c445ff JB |
8593 | } |
8594 | ||
8595 | /** | |
2f4b411a AN |
8596 | * i40e_delete_clsflower - Remove tc flower filters |
8597 | * @vsi: Pointer to VSI | |
f9e30088 | 8598 | * @cls_flower: Pointer to struct flow_cls_offload |
2f4b411a | 8599 | * |
41c445ff | 8600 | **/ |
2f4b411a | 8601 | static int i40e_delete_clsflower(struct i40e_vsi *vsi, |
f9e30088 | 8602 | struct flow_cls_offload *cls_flower) |
41c445ff | 8603 | { |
2f4b411a AN |
8604 | struct i40e_cloud_filter *filter = NULL; |
8605 | struct i40e_pf *pf = vsi->back; | |
8606 | int err = 0; | |
41c445ff | 8607 | |
2f4b411a | 8608 | filter = i40e_find_cloud_filter(vsi, &cls_flower->cookie); |
41c445ff | 8609 | |
2f4b411a AN |
8610 | if (!filter) |
8611 | return -EINVAL; | |
41c445ff | 8612 | |
2f4b411a | 8613 | hash_del(&filter->cloud_node); |
41c445ff | 8614 | |
2f4b411a AN |
8615 | if (filter->dst_port) |
8616 | err = i40e_add_del_cloud_filter_big_buf(vsi, filter, false); | |
8617 | else | |
8618 | err = i40e_add_del_cloud_filter(vsi, filter, false); | |
41c445ff | 8619 | |
2f4b411a AN |
8620 | kfree(filter); |
8621 | if (err) { | |
8622 | dev_err(&pf->pdev->dev, | |
8623 | "Failed to delete cloud filter, err %s\n", | |
8624 | i40e_stat_str(&pf->hw, err)); | |
8625 | return i40e_aq_rc_to_posix(err, pf->hw.aq.asq_last_status); | |
41c445ff | 8626 | } |
f980d445 | 8627 | |
2f4b411a AN |
8628 | pf->num_cloud_filters--; |
8629 | if (!pf->num_cloud_filters) | |
8630 | if ((pf->flags & I40E_FLAG_FD_SB_TO_CLOUD_FILTER) && | |
8631 | !(pf->flags & I40E_FLAG_FD_SB_INACTIVE)) { | |
8632 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
8633 | pf->flags &= ~I40E_FLAG_FD_SB_TO_CLOUD_FILTER; | |
8634 | pf->flags &= ~I40E_FLAG_FD_SB_INACTIVE; | |
8635 | } | |
8636 | return 0; | |
41c445ff JB |
8637 | } |
8638 | ||
8639 | /** | |
2f4b411a | 8640 | * i40e_setup_tc_cls_flower - flower classifier offloads |
b50f7bca JB |
8641 | * @np: net device to configure |
8642 | * @cls_flower: offload data | |
41c445ff | 8643 | **/ |
2f4b411a | 8644 | static int i40e_setup_tc_cls_flower(struct i40e_netdev_priv *np, |
f9e30088 | 8645 | struct flow_cls_offload *cls_flower) |
41c445ff | 8646 | { |
41c445ff | 8647 | struct i40e_vsi *vsi = np->vsi; |
41c445ff | 8648 | |
2f4b411a | 8649 | switch (cls_flower->command) { |
f9e30088 | 8650 | case FLOW_CLS_REPLACE: |
2f4b411a | 8651 | return i40e_configure_clsflower(vsi, cls_flower); |
f9e30088 | 8652 | case FLOW_CLS_DESTROY: |
2f4b411a | 8653 | return i40e_delete_clsflower(vsi, cls_flower); |
f9e30088 | 8654 | case FLOW_CLS_STATS: |
2f4b411a AN |
8655 | return -EOPNOTSUPP; |
8656 | default: | |
246ab6f0 | 8657 | return -EOPNOTSUPP; |
41c445ff | 8658 | } |
2f4b411a | 8659 | } |
41c445ff | 8660 | |
2f4b411a AN |
8661 | static int i40e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, |
8662 | void *cb_priv) | |
8663 | { | |
8664 | struct i40e_netdev_priv *np = cb_priv; | |
41c445ff | 8665 | |
a0d8637f JK |
8666 | if (!tc_cls_can_offload_and_chain0(np->vsi->netdev, type_data)) |
8667 | return -EOPNOTSUPP; | |
8668 | ||
2f4b411a AN |
8669 | switch (type) { |
8670 | case TC_SETUP_CLSFLOWER: | |
8671 | return i40e_setup_tc_cls_flower(np, type_data); | |
41c445ff | 8672 | |
2f4b411a AN |
8673 | default: |
8674 | return -EOPNOTSUPP; | |
41c445ff | 8675 | } |
2f4b411a | 8676 | } |
41c445ff | 8677 | |
955bcb6e PNA |
8678 | static LIST_HEAD(i40e_block_cb_list); |
8679 | ||
2572ac53 | 8680 | static int __i40e_setup_tc(struct net_device *netdev, enum tc_setup_type type, |
de4784ca | 8681 | void *type_data) |
e4c6734e | 8682 | { |
4e95bc26 PNA |
8683 | struct i40e_netdev_priv *np = netdev_priv(netdev); |
8684 | ||
2f4b411a | 8685 | switch (type) { |
575ed7d3 | 8686 | case TC_SETUP_QDISC_MQPRIO: |
2f4b411a AN |
8687 | return i40e_setup_tc(netdev, type_data); |
8688 | case TC_SETUP_BLOCK: | |
955bcb6e PNA |
8689 | return flow_block_cb_setup_simple(type_data, |
8690 | &i40e_block_cb_list, | |
4e95bc26 PNA |
8691 | i40e_setup_tc_block_cb, |
8692 | np, np, true); | |
2f4b411a | 8693 | default: |
38cf0426 | 8694 | return -EOPNOTSUPP; |
2f4b411a | 8695 | } |
e4c6734e JF |
8696 | } |
8697 | ||
41c445ff JB |
8698 | /** |
8699 | * i40e_open - Called when a network interface is made active | |
8700 | * @netdev: network interface device structure | |
8701 | * | |
8702 | * The open entry point is called when a network interface is made | |
8703 | * active by the system (IFF_UP). At this point all resources needed | |
8704 | * for transmit and receive operations are allocated, the interrupt | |
8705 | * handler is registered with the OS, the netdev watchdog subtask is | |
8706 | * enabled, and the stack is notified that the interface is ready. | |
8707 | * | |
8708 | * Returns 0 on success, negative value on failure | |
8709 | **/ | |
38e00438 | 8710 | int i40e_open(struct net_device *netdev) |
41c445ff JB |
8711 | { |
8712 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
8713 | struct i40e_vsi *vsi = np->vsi; | |
8714 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
8715 | int err; |
8716 | ||
4eb3f768 | 8717 | /* disallow open during test or if eeprom is broken */ |
0da36b97 JK |
8718 | if (test_bit(__I40E_TESTING, pf->state) || |
8719 | test_bit(__I40E_BAD_EEPROM, pf->state)) | |
41c445ff JB |
8720 | return -EBUSY; |
8721 | ||
8722 | netif_carrier_off(netdev); | |
8723 | ||
c3880bd1 MS |
8724 | if (i40e_force_link_state(pf, true)) |
8725 | return -EAGAIN; | |
8726 | ||
6c167f58 EK |
8727 | err = i40e_vsi_open(vsi); |
8728 | if (err) | |
8729 | return err; | |
8730 | ||
059dab69 JB |
8731 | /* configure global TSO hardware offload settings */ |
8732 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH | | |
8733 | TCP_FLAG_FIN) >> 16); | |
8734 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH | | |
8735 | TCP_FLAG_FIN | | |
8736 | TCP_FLAG_CWR) >> 16); | |
8737 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16); | |
06a5f7f1 | 8738 | udp_tunnel_get_rx_info(netdev); |
e3219ce6 | 8739 | |
6c167f58 EK |
8740 | return 0; |
8741 | } | |
8742 | ||
e738451d JJ |
8743 | /** |
8744 | * i40e_netif_set_realnum_tx_rx_queues - Update number of tx/rx queues | |
8745 | * @vsi: vsi structure | |
8746 | * | |
8747 | * This updates netdev's number of tx/rx queues | |
8748 | * | |
8749 | * Returns status of setting tx/rx queues | |
8750 | **/ | |
8751 | static int i40e_netif_set_realnum_tx_rx_queues(struct i40e_vsi *vsi) | |
8752 | { | |
8753 | int ret; | |
8754 | ||
8755 | ret = netif_set_real_num_rx_queues(vsi->netdev, | |
8756 | vsi->num_queue_pairs); | |
8757 | if (ret) | |
8758 | return ret; | |
8759 | ||
8760 | return netif_set_real_num_tx_queues(vsi->netdev, | |
8761 | vsi->num_queue_pairs); | |
8762 | } | |
8763 | ||
6c167f58 EK |
8764 | /** |
8765 | * i40e_vsi_open - | |
8766 | * @vsi: the VSI to open | |
8767 | * | |
8768 | * Finish initialization of the VSI. | |
8769 | * | |
8770 | * Returns 0 on success, negative value on failure | |
373149fc MS |
8771 | * |
8772 | * Note: expects to be called while under rtnl_lock() | |
6c167f58 EK |
8773 | **/ |
8774 | int i40e_vsi_open(struct i40e_vsi *vsi) | |
8775 | { | |
8776 | struct i40e_pf *pf = vsi->back; | |
b294ac70 | 8777 | char int_name[I40E_INT_NAME_STR_LEN]; |
6c167f58 EK |
8778 | int err; |
8779 | ||
41c445ff JB |
8780 | /* allocate descriptors */ |
8781 | err = i40e_vsi_setup_tx_resources(vsi); | |
8782 | if (err) | |
8783 | goto err_setup_tx; | |
8784 | err = i40e_vsi_setup_rx_resources(vsi); | |
8785 | if (err) | |
8786 | goto err_setup_rx; | |
8787 | ||
8788 | err = i40e_vsi_configure(vsi); | |
8789 | if (err) | |
8790 | goto err_setup_rx; | |
8791 | ||
c22e3c6c SN |
8792 | if (vsi->netdev) { |
8793 | snprintf(int_name, sizeof(int_name) - 1, "%s-%s", | |
8794 | dev_driver_string(&pf->pdev->dev), vsi->netdev->name); | |
8795 | err = i40e_vsi_request_irq(vsi, int_name); | |
8796 | if (err) | |
8797 | goto err_setup_rx; | |
41c445ff | 8798 | |
c22e3c6c | 8799 | /* Notify the stack of the actual queue counts. */ |
e738451d | 8800 | err = i40e_netif_set_realnum_tx_rx_queues(vsi); |
c22e3c6c SN |
8801 | if (err) |
8802 | goto err_set_queues; | |
8a9eb7d3 SN |
8803 | |
8804 | } else if (vsi->type == I40E_VSI_FDIR) { | |
e240f674 | 8805 | snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir", |
b2008cbf CW |
8806 | dev_driver_string(&pf->pdev->dev), |
8807 | dev_name(&pf->pdev->dev)); | |
8a9eb7d3 | 8808 | err = i40e_vsi_request_irq(vsi, int_name); |
9c04cfcd DL |
8809 | if (err) |
8810 | goto err_setup_rx; | |
b2008cbf | 8811 | |
c22e3c6c | 8812 | } else { |
ce9ccb17 | 8813 | err = -EINVAL; |
6c167f58 EK |
8814 | goto err_setup_rx; |
8815 | } | |
25946ddb | 8816 | |
41c445ff JB |
8817 | err = i40e_up_complete(vsi); |
8818 | if (err) | |
8819 | goto err_up_complete; | |
8820 | ||
41c445ff JB |
8821 | return 0; |
8822 | ||
8823 | err_up_complete: | |
8824 | i40e_down(vsi); | |
25946ddb | 8825 | err_set_queues: |
41c445ff JB |
8826 | i40e_vsi_free_irq(vsi); |
8827 | err_setup_rx: | |
8828 | i40e_vsi_free_rx_resources(vsi); | |
8829 | err_setup_tx: | |
8830 | i40e_vsi_free_tx_resources(vsi); | |
8831 | if (vsi == pf->vsi[pf->lan_vsi]) | |
ff424188 | 8832 | i40e_do_reset(pf, I40E_PF_RESET_FLAG, true); |
41c445ff JB |
8833 | |
8834 | return err; | |
8835 | } | |
8836 | ||
17a73f6b JG |
8837 | /** |
8838 | * i40e_fdir_filter_exit - Cleans up the Flow Director accounting | |
b40c82e6 | 8839 | * @pf: Pointer to PF |
17a73f6b JG |
8840 | * |
8841 | * This function destroys the hlist where all the Flow Director | |
8842 | * filters were saved. | |
8843 | **/ | |
8844 | static void i40e_fdir_filter_exit(struct i40e_pf *pf) | |
8845 | { | |
8846 | struct i40e_fdir_filter *filter; | |
0e588de1 | 8847 | struct i40e_flex_pit *pit_entry, *tmp; |
17a73f6b JG |
8848 | struct hlist_node *node2; |
8849 | ||
8850 | hlist_for_each_entry_safe(filter, node2, | |
8851 | &pf->fdir_filter_list, fdir_node) { | |
8852 | hlist_del(&filter->fdir_node); | |
8853 | kfree(filter); | |
8854 | } | |
097dbf52 | 8855 | |
0e588de1 JK |
8856 | list_for_each_entry_safe(pit_entry, tmp, &pf->l3_flex_pit_list, list) { |
8857 | list_del(&pit_entry->list); | |
8858 | kfree(pit_entry); | |
8859 | } | |
8860 | INIT_LIST_HEAD(&pf->l3_flex_pit_list); | |
8861 | ||
8862 | list_for_each_entry_safe(pit_entry, tmp, &pf->l4_flex_pit_list, list) { | |
8863 | list_del(&pit_entry->list); | |
8864 | kfree(pit_entry); | |
8865 | } | |
8866 | INIT_LIST_HEAD(&pf->l4_flex_pit_list); | |
8867 | ||
17a73f6b | 8868 | pf->fdir_pf_active_filters = 0; |
efca91e8 | 8869 | i40e_reset_fdir_filter_cnt(pf); |
3bcee1e6 JK |
8870 | |
8871 | /* Reprogram the default input set for TCP/IPv4 */ | |
8872 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_TCP, | |
8873 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
8874 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
8875 | ||
efca91e8 PP |
8876 | /* Reprogram the default input set for TCP/IPv6 */ |
8877 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV6_TCP, | |
8878 | I40E_L3_V6_SRC_MASK | I40E_L3_V6_DST_MASK | | |
8879 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
8880 | ||
3bcee1e6 JK |
8881 | /* Reprogram the default input set for UDP/IPv4 */ |
8882 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_UDP, | |
8883 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
8884 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
8885 | ||
efca91e8 PP |
8886 | /* Reprogram the default input set for UDP/IPv6 */ |
8887 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV6_UDP, | |
8888 | I40E_L3_V6_SRC_MASK | I40E_L3_V6_DST_MASK | | |
8889 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
8890 | ||
3bcee1e6 JK |
8891 | /* Reprogram the default input set for SCTP/IPv4 */ |
8892 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_SCTP, | |
8893 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
8894 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
8895 | ||
efca91e8 PP |
8896 | /* Reprogram the default input set for SCTP/IPv6 */ |
8897 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV6_SCTP, | |
8898 | I40E_L3_V6_SRC_MASK | I40E_L3_V6_DST_MASK | | |
8899 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
8900 | ||
3bcee1e6 JK |
8901 | /* Reprogram the default input set for Other/IPv4 */ |
8902 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_OTHER, | |
8903 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK); | |
02b4016b JK |
8904 | |
8905 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_FRAG_IPV4, | |
8906 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK); | |
efca91e8 PP |
8907 | |
8908 | /* Reprogram the default input set for Other/IPv6 */ | |
8909 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV6_OTHER, | |
8910 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK); | |
8911 | ||
8912 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_FRAG_IPV6, | |
8913 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK); | |
17a73f6b JG |
8914 | } |
8915 | ||
aaf66502 AN |
8916 | /** |
8917 | * i40e_cloud_filter_exit - Cleans up the cloud filters | |
8918 | * @pf: Pointer to PF | |
8919 | * | |
8920 | * This function destroys the hlist where all the cloud filters | |
8921 | * were saved. | |
8922 | **/ | |
8923 | static void i40e_cloud_filter_exit(struct i40e_pf *pf) | |
8924 | { | |
8925 | struct i40e_cloud_filter *cfilter; | |
8926 | struct hlist_node *node; | |
8927 | ||
8928 | hlist_for_each_entry_safe(cfilter, node, | |
8929 | &pf->cloud_filter_list, cloud_node) { | |
8930 | hlist_del(&cfilter->cloud_node); | |
8931 | kfree(cfilter); | |
8932 | } | |
8933 | pf->num_cloud_filters = 0; | |
2f4b411a AN |
8934 | |
8935 | if ((pf->flags & I40E_FLAG_FD_SB_TO_CLOUD_FILTER) && | |
8936 | !(pf->flags & I40E_FLAG_FD_SB_INACTIVE)) { | |
8937 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
8938 | pf->flags &= ~I40E_FLAG_FD_SB_TO_CLOUD_FILTER; | |
8939 | pf->flags &= ~I40E_FLAG_FD_SB_INACTIVE; | |
8940 | } | |
aaf66502 AN |
8941 | } |
8942 | ||
41c445ff JB |
8943 | /** |
8944 | * i40e_close - Disables a network interface | |
8945 | * @netdev: network interface device structure | |
8946 | * | |
8947 | * The close entry point is called when an interface is de-activated | |
8948 | * by the OS. The hardware is still under the driver's control, but | |
8949 | * this netdev interface is disabled. | |
8950 | * | |
8951 | * Returns 0, this is not allowed to fail | |
8952 | **/ | |
38e00438 | 8953 | int i40e_close(struct net_device *netdev) |
41c445ff JB |
8954 | { |
8955 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
8956 | struct i40e_vsi *vsi = np->vsi; | |
8957 | ||
90ef8d47 | 8958 | i40e_vsi_close(vsi); |
41c445ff JB |
8959 | |
8960 | return 0; | |
8961 | } | |
8962 | ||
8963 | /** | |
8964 | * i40e_do_reset - Start a PF or Core Reset sequence | |
8965 | * @pf: board private structure | |
8966 | * @reset_flags: which reset is requested | |
373149fc MS |
8967 | * @lock_acquired: indicates whether or not the lock has been acquired |
8968 | * before this function was called. | |
41c445ff JB |
8969 | * |
8970 | * The essential difference in resets is that the PF Reset | |
8971 | * doesn't clear the packet buffers, doesn't reset the PE | |
8972 | * firmware, and doesn't bother the other PFs on the chip. | |
8973 | **/ | |
373149fc | 8974 | void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired) |
41c445ff JB |
8975 | { |
8976 | u32 val; | |
8977 | ||
41c445ff | 8978 | /* do the biggest reset indicated */ |
41a1d04b | 8979 | if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) { |
41c445ff JB |
8980 | |
8981 | /* Request a Global Reset | |
8982 | * | |
8983 | * This will start the chip's countdown to the actual full | |
8984 | * chip reset event, and a warning interrupt to be sent | |
8985 | * to all PFs, including the requestor. Our handler | |
8986 | * for the warning interrupt will deal with the shutdown | |
8987 | * and recovery of the switch setup. | |
8988 | */ | |
69bfb110 | 8989 | dev_dbg(&pf->pdev->dev, "GlobalR requested\n"); |
41c445ff JB |
8990 | val = rd32(&pf->hw, I40E_GLGEN_RTRIG); |
8991 | val |= I40E_GLGEN_RTRIG_GLOBR_MASK; | |
8992 | wr32(&pf->hw, I40E_GLGEN_RTRIG, val); | |
8993 | ||
41a1d04b | 8994 | } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) { |
41c445ff JB |
8995 | |
8996 | /* Request a Core Reset | |
8997 | * | |
8998 | * Same as Global Reset, except does *not* include the MAC/PHY | |
8999 | */ | |
69bfb110 | 9000 | dev_dbg(&pf->pdev->dev, "CoreR requested\n"); |
41c445ff JB |
9001 | val = rd32(&pf->hw, I40E_GLGEN_RTRIG); |
9002 | val |= I40E_GLGEN_RTRIG_CORER_MASK; | |
9003 | wr32(&pf->hw, I40E_GLGEN_RTRIG, val); | |
9004 | i40e_flush(&pf->hw); | |
9005 | ||
ff424188 | 9006 | } else if (reset_flags & I40E_PF_RESET_FLAG) { |
41c445ff JB |
9007 | |
9008 | /* Request a PF Reset | |
9009 | * | |
9010 | * Resets only the PF-specific registers | |
9011 | * | |
9012 | * This goes directly to the tear-down and rebuild of | |
9013 | * the switch, since we need to do all the recovery as | |
9014 | * for the Core Reset. | |
9015 | */ | |
69bfb110 | 9016 | dev_dbg(&pf->pdev->dev, "PFR requested\n"); |
373149fc | 9017 | i40e_handle_reset_warning(pf, lock_acquired); |
41c445ff | 9018 | |
3ac874fa SD |
9019 | } else if (reset_flags & I40E_PF_RESET_AND_REBUILD_FLAG) { |
9020 | /* Request a PF Reset | |
9021 | * | |
9022 | * Resets PF and reinitializes PFs VSI. | |
9023 | */ | |
4b208eaa | 9024 | i40e_prep_for_reset(pf); |
3ac874fa | 9025 | i40e_reset_and_rebuild(pf, true, lock_acquired); |
28b1208e MP |
9026 | dev_info(&pf->pdev->dev, |
9027 | pf->flags & I40E_FLAG_DISABLE_FW_LLDP ? | |
9028 | "FW LLDP is disabled\n" : | |
9029 | "FW LLDP is enabled\n"); | |
3ac874fa | 9030 | |
41a1d04b | 9031 | } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) { |
41c445ff JB |
9032 | int v; |
9033 | ||
9034 | /* Find the VSI(s) that requested a re-init */ | |
9035 | dev_info(&pf->pdev->dev, | |
9036 | "VSI reinit requested\n"); | |
505682cd | 9037 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff | 9038 | struct i40e_vsi *vsi = pf->vsi[v]; |
6995b36c | 9039 | |
41c445ff | 9040 | if (vsi != NULL && |
d19cb64b | 9041 | test_and_clear_bit(__I40E_VSI_REINIT_REQUESTED, |
0da36b97 | 9042 | vsi->state)) |
41c445ff | 9043 | i40e_vsi_reinit_locked(pf->vsi[v]); |
41c445ff | 9044 | } |
41a1d04b | 9045 | } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) { |
b5d06f05 NP |
9046 | int v; |
9047 | ||
9048 | /* Find the VSI(s) that needs to be brought down */ | |
9049 | dev_info(&pf->pdev->dev, "VSI down requested\n"); | |
9050 | for (v = 0; v < pf->num_alloc_vsi; v++) { | |
9051 | struct i40e_vsi *vsi = pf->vsi[v]; | |
6995b36c | 9052 | |
b5d06f05 | 9053 | if (vsi != NULL && |
d19cb64b | 9054 | test_and_clear_bit(__I40E_VSI_DOWN_REQUESTED, |
0da36b97 JK |
9055 | vsi->state)) { |
9056 | set_bit(__I40E_VSI_DOWN, vsi->state); | |
b5d06f05 | 9057 | i40e_down(vsi); |
b5d06f05 NP |
9058 | } |
9059 | } | |
41c445ff JB |
9060 | } else { |
9061 | dev_info(&pf->pdev->dev, | |
9062 | "bad reset request 0x%08x\n", reset_flags); | |
41c445ff JB |
9063 | } |
9064 | } | |
9065 | ||
4e3b35b0 NP |
9066 | #ifdef CONFIG_I40E_DCB |
9067 | /** | |
9068 | * i40e_dcb_need_reconfig - Check if DCB needs reconfig | |
9069 | * @pf: board private structure | |
9070 | * @old_cfg: current DCB config | |
9071 | * @new_cfg: new DCB config | |
9072 | **/ | |
9073 | bool i40e_dcb_need_reconfig(struct i40e_pf *pf, | |
9074 | struct i40e_dcbx_config *old_cfg, | |
9075 | struct i40e_dcbx_config *new_cfg) | |
9076 | { | |
9077 | bool need_reconfig = false; | |
9078 | ||
9079 | /* Check if ETS configuration has changed */ | |
9080 | if (memcmp(&new_cfg->etscfg, | |
9081 | &old_cfg->etscfg, | |
9082 | sizeof(new_cfg->etscfg))) { | |
9083 | /* If Priority Table has changed reconfig is needed */ | |
9084 | if (memcmp(&new_cfg->etscfg.prioritytable, | |
9085 | &old_cfg->etscfg.prioritytable, | |
9086 | sizeof(new_cfg->etscfg.prioritytable))) { | |
9087 | need_reconfig = true; | |
69bfb110 | 9088 | dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n"); |
4e3b35b0 NP |
9089 | } |
9090 | ||
9091 | if (memcmp(&new_cfg->etscfg.tcbwtable, | |
9092 | &old_cfg->etscfg.tcbwtable, | |
9093 | sizeof(new_cfg->etscfg.tcbwtable))) | |
69bfb110 | 9094 | dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n"); |
4e3b35b0 NP |
9095 | |
9096 | if (memcmp(&new_cfg->etscfg.tsatable, | |
9097 | &old_cfg->etscfg.tsatable, | |
9098 | sizeof(new_cfg->etscfg.tsatable))) | |
69bfb110 | 9099 | dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n"); |
4e3b35b0 NP |
9100 | } |
9101 | ||
9102 | /* Check if PFC configuration has changed */ | |
9103 | if (memcmp(&new_cfg->pfc, | |
9104 | &old_cfg->pfc, | |
9105 | sizeof(new_cfg->pfc))) { | |
9106 | need_reconfig = true; | |
69bfb110 | 9107 | dev_dbg(&pf->pdev->dev, "PFC config change detected.\n"); |
4e3b35b0 NP |
9108 | } |
9109 | ||
9110 | /* Check if APP Table has changed */ | |
9111 | if (memcmp(&new_cfg->app, | |
9112 | &old_cfg->app, | |
3d9667a9 | 9113 | sizeof(new_cfg->app))) { |
4e3b35b0 | 9114 | need_reconfig = true; |
69bfb110 | 9115 | dev_dbg(&pf->pdev->dev, "APP Table change detected.\n"); |
3d9667a9 | 9116 | } |
4e3b35b0 | 9117 | |
fb43201f | 9118 | dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig); |
4e3b35b0 NP |
9119 | return need_reconfig; |
9120 | } | |
9121 | ||
9122 | /** | |
9123 | * i40e_handle_lldp_event - Handle LLDP Change MIB event | |
9124 | * @pf: board private structure | |
9125 | * @e: event info posted on ARQ | |
9126 | **/ | |
9127 | static int i40e_handle_lldp_event(struct i40e_pf *pf, | |
9128 | struct i40e_arq_event_info *e) | |
9129 | { | |
9130 | struct i40e_aqc_lldp_get_mib *mib = | |
9131 | (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw; | |
9132 | struct i40e_hw *hw = &pf->hw; | |
4e3b35b0 NP |
9133 | struct i40e_dcbx_config tmp_dcbx_cfg; |
9134 | bool need_reconfig = false; | |
9135 | int ret = 0; | |
9136 | u8 type; | |
9137 | ||
4b208eaa AK |
9138 | /* X710-T*L 2.5G and 5G speeds don't support DCB */ |
9139 | if (I40E_IS_X710TL_DEVICE(hw->device_id) && | |
9140 | (hw->phy.link_info.link_speed & | |
9141 | ~(I40E_LINK_SPEED_2_5GB | I40E_LINK_SPEED_5GB)) && | |
9142 | !(pf->flags & I40E_FLAG_DCB_CAPABLE)) | |
9143 | /* let firmware decide if the DCB should be disabled */ | |
9144 | pf->flags |= I40E_FLAG_DCB_CAPABLE; | |
9145 | ||
4d9b6043 | 9146 | /* Not DCB capable or capability disabled */ |
ea6acb7e | 9147 | if (!(pf->flags & I40E_FLAG_DCB_CAPABLE)) |
4d9b6043 NP |
9148 | return ret; |
9149 | ||
4e3b35b0 NP |
9150 | /* Ignore if event is not for Nearest Bridge */ |
9151 | type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) | |
9152 | & I40E_AQ_LLDP_BRIDGE_TYPE_MASK); | |
fb43201f | 9153 | dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type); |
4e3b35b0 NP |
9154 | if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE) |
9155 | return ret; | |
9156 | ||
9157 | /* Check MIB Type and return if event for Remote MIB update */ | |
9158 | type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK; | |
9fa61dd2 | 9159 | dev_dbg(&pf->pdev->dev, |
fb43201f | 9160 | "LLDP event mib type %s\n", type ? "remote" : "local"); |
4e3b35b0 NP |
9161 | if (type == I40E_AQ_LLDP_MIB_REMOTE) { |
9162 | /* Update the remote cached instance and return */ | |
9163 | ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE, | |
9164 | I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, | |
9165 | &hw->remote_dcbx_config); | |
9166 | goto exit; | |
9167 | } | |
9168 | ||
9fa61dd2 | 9169 | /* Store the old configuration */ |
1a2f6248 | 9170 | tmp_dcbx_cfg = hw->local_dcbx_config; |
9fa61dd2 | 9171 | |
750fcbcf NP |
9172 | /* Reset the old DCBx configuration data */ |
9173 | memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config)); | |
9fa61dd2 NP |
9174 | /* Get updated DCBX data from firmware */ |
9175 | ret = i40e_get_dcb_config(&pf->hw); | |
4e3b35b0 | 9176 | if (ret) { |
4b208eaa AK |
9177 | /* X710-T*L 2.5G and 5G speeds don't support DCB */ |
9178 | if (I40E_IS_X710TL_DEVICE(hw->device_id) && | |
9179 | (hw->phy.link_info.link_speed & | |
9180 | (I40E_LINK_SPEED_2_5GB | I40E_LINK_SPEED_5GB))) { | |
9181 | dev_warn(&pf->pdev->dev, | |
9182 | "DCB is not supported for X710-T*L 2.5/5G speeds\n"); | |
9183 | pf->flags &= ~I40E_FLAG_DCB_CAPABLE; | |
9184 | } else { | |
9185 | dev_info(&pf->pdev->dev, | |
9186 | "Failed querying DCB configuration data from firmware, err %s aq_err %s\n", | |
9187 | i40e_stat_str(&pf->hw, ret), | |
9188 | i40e_aq_str(&pf->hw, | |
9189 | pf->hw.aq.asq_last_status)); | |
9190 | } | |
4e3b35b0 NP |
9191 | goto exit; |
9192 | } | |
9193 | ||
9194 | /* No change detected in DCBX configs */ | |
750fcbcf NP |
9195 | if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config, |
9196 | sizeof(tmp_dcbx_cfg))) { | |
69bfb110 | 9197 | dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n"); |
4e3b35b0 NP |
9198 | goto exit; |
9199 | } | |
9200 | ||
750fcbcf NP |
9201 | need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg, |
9202 | &hw->local_dcbx_config); | |
4e3b35b0 | 9203 | |
750fcbcf | 9204 | i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config); |
4e3b35b0 NP |
9205 | |
9206 | if (!need_reconfig) | |
9207 | goto exit; | |
9208 | ||
4d9b6043 | 9209 | /* Enable DCB tagging only when more than one TC */ |
750fcbcf | 9210 | if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) |
4d9b6043 NP |
9211 | pf->flags |= I40E_FLAG_DCB_ENABLED; |
9212 | else | |
9213 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
9214 | ||
0da36b97 | 9215 | set_bit(__I40E_PORT_SUSPENDED, pf->state); |
4e3b35b0 NP |
9216 | /* Reconfiguration needed quiesce all VSIs */ |
9217 | i40e_pf_quiesce_all_vsi(pf); | |
9218 | ||
9219 | /* Changes in configuration update VEB/VSI */ | |
9220 | i40e_dcb_reconfigure(pf); | |
9221 | ||
2fd75f31 NP |
9222 | ret = i40e_resume_port_tx(pf); |
9223 | ||
0da36b97 | 9224 | clear_bit(__I40E_PORT_SUSPENDED, pf->state); |
2fd75f31 | 9225 | /* In case of error no point in resuming VSIs */ |
69129dc3 NP |
9226 | if (ret) |
9227 | goto exit; | |
9228 | ||
3fe06f41 NP |
9229 | /* Wait for the PF's queues to be disabled */ |
9230 | ret = i40e_pf_wait_queues_disabled(pf); | |
11e47708 PN |
9231 | if (ret) { |
9232 | /* Schedule PF reset to recover */ | |
0da36b97 | 9233 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
11e47708 PN |
9234 | i40e_service_event_schedule(pf); |
9235 | } else { | |
2fd75f31 | 9236 | i40e_pf_unquiesce_all_vsi(pf); |
d1b3fa86 CIK |
9237 | set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state); |
9238 | set_bit(__I40E_CLIENT_L2_CHANGE, pf->state); | |
11e47708 PN |
9239 | } |
9240 | ||
4e3b35b0 NP |
9241 | exit: |
9242 | return ret; | |
9243 | } | |
9244 | #endif /* CONFIG_I40E_DCB */ | |
9245 | ||
23326186 ASJ |
9246 | /** |
9247 | * i40e_do_reset_safe - Protected reset path for userland calls. | |
9248 | * @pf: board private structure | |
9249 | * @reset_flags: which reset is requested | |
9250 | * | |
9251 | **/ | |
9252 | void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags) | |
9253 | { | |
9254 | rtnl_lock(); | |
373149fc | 9255 | i40e_do_reset(pf, reset_flags, true); |
23326186 ASJ |
9256 | rtnl_unlock(); |
9257 | } | |
9258 | ||
41c445ff JB |
9259 | /** |
9260 | * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event | |
9261 | * @pf: board private structure | |
9262 | * @e: event info posted on ARQ | |
9263 | * | |
9264 | * Handler for LAN Queue Overflow Event generated by the firmware for PF | |
9265 | * and VF queues | |
9266 | **/ | |
9267 | static void i40e_handle_lan_overflow_event(struct i40e_pf *pf, | |
9268 | struct i40e_arq_event_info *e) | |
9269 | { | |
9270 | struct i40e_aqc_lan_overflow *data = | |
9271 | (struct i40e_aqc_lan_overflow *)&e->desc.params.raw; | |
9272 | u32 queue = le32_to_cpu(data->prtdcb_rupto); | |
9273 | u32 qtx_ctl = le32_to_cpu(data->otx_ctl); | |
9274 | struct i40e_hw *hw = &pf->hw; | |
9275 | struct i40e_vf *vf; | |
9276 | u16 vf_id; | |
9277 | ||
69bfb110 JB |
9278 | dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n", |
9279 | queue, qtx_ctl); | |
41c445ff JB |
9280 | |
9281 | /* Queue belongs to VF, find the VF and issue VF reset */ | |
9282 | if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK) | |
9283 | >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) { | |
9284 | vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK) | |
9285 | >> I40E_QTX_CTL_VFVM_INDX_SHIFT); | |
9286 | vf_id -= hw->func_caps.vf_base_id; | |
9287 | vf = &pf->vf[vf_id]; | |
9288 | i40e_vc_notify_vf_reset(vf); | |
9289 | /* Allow VF to process pending reset notification */ | |
9290 | msleep(20); | |
9291 | i40e_reset_vf(vf, false); | |
9292 | } | |
9293 | } | |
9294 | ||
55a5e60b | 9295 | /** |
12957388 ASJ |
9296 | * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters |
9297 | * @pf: board private structure | |
9298 | **/ | |
04294e38 | 9299 | u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf) |
12957388 | 9300 | { |
04294e38 | 9301 | u32 val, fcnt_prog; |
12957388 ASJ |
9302 | |
9303 | val = rd32(&pf->hw, I40E_PFQF_FDSTAT); | |
9304 | fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK); | |
9305 | return fcnt_prog; | |
9306 | } | |
9307 | ||
9308 | /** | |
04294e38 | 9309 | * i40e_get_current_fd_count - Get total FD filters programmed for this PF |
55a5e60b ASJ |
9310 | * @pf: board private structure |
9311 | **/ | |
04294e38 | 9312 | u32 i40e_get_current_fd_count(struct i40e_pf *pf) |
55a5e60b | 9313 | { |
04294e38 ASJ |
9314 | u32 val, fcnt_prog; |
9315 | ||
55a5e60b ASJ |
9316 | val = rd32(&pf->hw, I40E_PFQF_FDSTAT); |
9317 | fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) + | |
9318 | ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >> | |
9319 | I40E_PFQF_FDSTAT_BEST_CNT_SHIFT); | |
9320 | return fcnt_prog; | |
9321 | } | |
1e1be8f6 | 9322 | |
04294e38 ASJ |
9323 | /** |
9324 | * i40e_get_global_fd_count - Get total FD filters programmed on device | |
9325 | * @pf: board private structure | |
9326 | **/ | |
9327 | u32 i40e_get_global_fd_count(struct i40e_pf *pf) | |
9328 | { | |
9329 | u32 val, fcnt_prog; | |
9330 | ||
9331 | val = rd32(&pf->hw, I40E_GLQF_FDCNT_0); | |
9332 | fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) + | |
9333 | ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >> | |
9334 | I40E_GLQF_FDCNT_0_BESTCNT_SHIFT); | |
9335 | return fcnt_prog; | |
9336 | } | |
9337 | ||
01c96952 JK |
9338 | /** |
9339 | * i40e_reenable_fdir_sb - Restore FDir SB capability | |
9340 | * @pf: board private structure | |
9341 | **/ | |
9342 | static void i40e_reenable_fdir_sb(struct i40e_pf *pf) | |
9343 | { | |
134201ae | 9344 | if (test_and_clear_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) |
01c96952 JK |
9345 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
9346 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
9347 | dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n"); | |
01c96952 JK |
9348 | } |
9349 | ||
9350 | /** | |
9351 | * i40e_reenable_fdir_atr - Restore FDir ATR capability | |
9352 | * @pf: board private structure | |
9353 | **/ | |
9354 | static void i40e_reenable_fdir_atr(struct i40e_pf *pf) | |
9355 | { | |
134201ae | 9356 | if (test_and_clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) { |
089915f0 JK |
9357 | /* ATR uses the same filtering logic as SB rules. It only |
9358 | * functions properly if the input set mask is at the default | |
9359 | * settings. It is safe to restore the default input set | |
9360 | * because there are no active TCPv4 filter rules. | |
9361 | */ | |
9362 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_TCP, | |
9363 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
9364 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
9365 | ||
01c96952 JK |
9366 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && |
9367 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
9368 | dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table and there are no conflicting ntuple rules\n"); | |
9369 | } | |
9370 | } | |
9371 | ||
6ac6d5a7 JK |
9372 | /** |
9373 | * i40e_delete_invalid_filter - Delete an invalid FDIR filter | |
9374 | * @pf: board private structure | |
9375 | * @filter: FDir filter to remove | |
9376 | */ | |
9377 | static void i40e_delete_invalid_filter(struct i40e_pf *pf, | |
9378 | struct i40e_fdir_filter *filter) | |
9379 | { | |
9380 | /* Update counters */ | |
9381 | pf->fdir_pf_active_filters--; | |
9382 | pf->fd_inv = 0; | |
9383 | ||
9384 | switch (filter->flow_type) { | |
9385 | case TCP_V4_FLOW: | |
9386 | pf->fd_tcp4_filter_cnt--; | |
9387 | break; | |
9388 | case UDP_V4_FLOW: | |
9389 | pf->fd_udp4_filter_cnt--; | |
9390 | break; | |
9391 | case SCTP_V4_FLOW: | |
9392 | pf->fd_sctp4_filter_cnt--; | |
9393 | break; | |
efca91e8 PP |
9394 | case TCP_V6_FLOW: |
9395 | pf->fd_tcp6_filter_cnt--; | |
9396 | break; | |
9397 | case UDP_V6_FLOW: | |
9398 | pf->fd_udp6_filter_cnt--; | |
9399 | break; | |
9400 | case SCTP_V6_FLOW: | |
9401 | pf->fd_udp6_filter_cnt--; | |
9402 | break; | |
6ac6d5a7 | 9403 | case IP_USER_FLOW: |
efca91e8 | 9404 | switch (filter->ipl4_proto) { |
6ac6d5a7 JK |
9405 | case IPPROTO_TCP: |
9406 | pf->fd_tcp4_filter_cnt--; | |
9407 | break; | |
9408 | case IPPROTO_UDP: | |
9409 | pf->fd_udp4_filter_cnt--; | |
9410 | break; | |
9411 | case IPPROTO_SCTP: | |
9412 | pf->fd_sctp4_filter_cnt--; | |
9413 | break; | |
9414 | case IPPROTO_IP: | |
9415 | pf->fd_ip4_filter_cnt--; | |
9416 | break; | |
9417 | } | |
9418 | break; | |
efca91e8 PP |
9419 | case IPV6_USER_FLOW: |
9420 | switch (filter->ipl4_proto) { | |
9421 | case IPPROTO_TCP: | |
9422 | pf->fd_tcp6_filter_cnt--; | |
9423 | break; | |
9424 | case IPPROTO_UDP: | |
9425 | pf->fd_udp6_filter_cnt--; | |
9426 | break; | |
9427 | case IPPROTO_SCTP: | |
9428 | pf->fd_sctp6_filter_cnt--; | |
9429 | break; | |
9430 | case IPPROTO_IP: | |
9431 | pf->fd_ip6_filter_cnt--; | |
9432 | break; | |
9433 | } | |
9434 | break; | |
6ac6d5a7 JK |
9435 | } |
9436 | ||
9437 | /* Remove the filter from the list and free memory */ | |
9438 | hlist_del(&filter->fdir_node); | |
9439 | kfree(filter); | |
9440 | } | |
9441 | ||
55a5e60b ASJ |
9442 | /** |
9443 | * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled | |
9444 | * @pf: board private structure | |
9445 | **/ | |
9446 | void i40e_fdir_check_and_reenable(struct i40e_pf *pf) | |
9447 | { | |
3487b6c3 | 9448 | struct i40e_fdir_filter *filter; |
55a5e60b | 9449 | u32 fcnt_prog, fcnt_avail; |
3487b6c3 | 9450 | struct hlist_node *node; |
55a5e60b | 9451 | |
0da36b97 | 9452 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) |
1e1be8f6 ASJ |
9453 | return; |
9454 | ||
47994c11 | 9455 | /* Check if we have enough room to re-enable FDir SB capability. */ |
04294e38 | 9456 | fcnt_prog = i40e_get_global_fd_count(pf); |
12957388 | 9457 | fcnt_avail = pf->fdir_pf_filter_count; |
1e1be8f6 ASJ |
9458 | if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) || |
9459 | (pf->fd_add_err == 0) || | |
01c96952 JK |
9460 | (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) |
9461 | i40e_reenable_fdir_sb(pf); | |
a3417d28 | 9462 | |
47994c11 JK |
9463 | /* We should wait for even more space before re-enabling ATR. |
9464 | * Additionally, we cannot enable ATR as long as we still have TCP SB | |
9465 | * rules active. | |
a3417d28 | 9466 | */ |
47994c11 | 9467 | if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) && |
efca91e8 | 9468 | pf->fd_tcp4_filter_cnt == 0 && pf->fd_tcp6_filter_cnt == 0) |
01c96952 | 9469 | i40e_reenable_fdir_atr(pf); |
3487b6c3 CW |
9470 | |
9471 | /* if hw had a problem adding a filter, delete it */ | |
9472 | if (pf->fd_inv > 0) { | |
9473 | hlist_for_each_entry_safe(filter, node, | |
6ac6d5a7 JK |
9474 | &pf->fdir_filter_list, fdir_node) |
9475 | if (filter->fd_id == pf->fd_inv) | |
9476 | i40e_delete_invalid_filter(pf, filter); | |
3487b6c3 | 9477 | } |
55a5e60b ASJ |
9478 | } |
9479 | ||
1e1be8f6 | 9480 | #define I40E_MIN_FD_FLUSH_INTERVAL 10 |
04294e38 | 9481 | #define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30 |
1e1be8f6 ASJ |
9482 | /** |
9483 | * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB | |
9484 | * @pf: board private structure | |
9485 | **/ | |
9486 | static void i40e_fdir_flush_and_replay(struct i40e_pf *pf) | |
9487 | { | |
04294e38 | 9488 | unsigned long min_flush_time; |
1e1be8f6 | 9489 | int flush_wait_retry = 50; |
04294e38 ASJ |
9490 | bool disable_atr = false; |
9491 | int fd_room; | |
1e1be8f6 ASJ |
9492 | int reg; |
9493 | ||
a5fdaf34 JB |
9494 | if (!time_after(jiffies, pf->fd_flush_timestamp + |
9495 | (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) | |
9496 | return; | |
04294e38 | 9497 | |
a5fdaf34 JB |
9498 | /* If the flush is happening too quick and we have mostly SB rules we |
9499 | * should not re-enable ATR for some time. | |
9500 | */ | |
9501 | min_flush_time = pf->fd_flush_timestamp + | |
9502 | (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ); | |
9503 | fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters; | |
9504 | ||
9505 | if (!(time_after(jiffies, min_flush_time)) && | |
9506 | (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) { | |
9507 | if (I40E_DEBUG_FD & pf->hw.debug_mask) | |
9508 | dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n"); | |
9509 | disable_atr = true; | |
9510 | } | |
9511 | ||
9512 | pf->fd_flush_timestamp = jiffies; | |
134201ae | 9513 | set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state); |
a5fdaf34 JB |
9514 | /* flush all filters */ |
9515 | wr32(&pf->hw, I40E_PFQF_CTL_1, | |
9516 | I40E_PFQF_CTL_1_CLEARFDTABLE_MASK); | |
9517 | i40e_flush(&pf->hw); | |
9518 | pf->fd_flush_cnt++; | |
9519 | pf->fd_add_err = 0; | |
9520 | do { | |
9521 | /* Check FD flush status every 5-6msec */ | |
9522 | usleep_range(5000, 6000); | |
9523 | reg = rd32(&pf->hw, I40E_PFQF_CTL_1); | |
9524 | if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK)) | |
9525 | break; | |
9526 | } while (flush_wait_retry--); | |
9527 | if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) { | |
9528 | dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n"); | |
9529 | } else { | |
9530 | /* replay sideband filters */ | |
9531 | i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]); | |
097dbf52 | 9532 | if (!disable_atr && !pf->fd_tcp4_filter_cnt) |
134201ae | 9533 | clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state); |
0da36b97 | 9534 | clear_bit(__I40E_FD_FLUSH_REQUESTED, pf->state); |
a5fdaf34 JB |
9535 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
9536 | dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n"); | |
1e1be8f6 ASJ |
9537 | } |
9538 | } | |
9539 | ||
9540 | /** | |
262de08f | 9541 | * i40e_get_current_atr_cnt - Get the count of total FD ATR filters programmed |
1e1be8f6 ASJ |
9542 | * @pf: board private structure |
9543 | **/ | |
04294e38 | 9544 | u32 i40e_get_current_atr_cnt(struct i40e_pf *pf) |
1e1be8f6 ASJ |
9545 | { |
9546 | return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters; | |
9547 | } | |
9548 | ||
41c445ff JB |
9549 | /** |
9550 | * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table | |
9551 | * @pf: board private structure | |
9552 | **/ | |
9553 | static void i40e_fdir_reinit_subtask(struct i40e_pf *pf) | |
9554 | { | |
41c445ff | 9555 | |
41c445ff | 9556 | /* if interface is down do nothing */ |
9e6c9c0f | 9557 | if (test_bit(__I40E_DOWN, pf->state)) |
41c445ff | 9558 | return; |
1e1be8f6 | 9559 | |
0da36b97 | 9560 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) |
1e1be8f6 ASJ |
9561 | i40e_fdir_flush_and_replay(pf); |
9562 | ||
55a5e60b ASJ |
9563 | i40e_fdir_check_and_reenable(pf); |
9564 | ||
41c445ff JB |
9565 | } |
9566 | ||
9567 | /** | |
9568 | * i40e_vsi_link_event - notify VSI of a link event | |
9569 | * @vsi: vsi to be notified | |
9570 | * @link_up: link up or down | |
9571 | **/ | |
9572 | static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up) | |
9573 | { | |
0da36b97 | 9574 | if (!vsi || test_bit(__I40E_VSI_DOWN, vsi->state)) |
41c445ff JB |
9575 | return; |
9576 | ||
9577 | switch (vsi->type) { | |
9578 | case I40E_VSI_MAIN: | |
9579 | if (!vsi->netdev || !vsi->netdev_registered) | |
9580 | break; | |
9581 | ||
9582 | if (link_up) { | |
9583 | netif_carrier_on(vsi->netdev); | |
9584 | netif_tx_wake_all_queues(vsi->netdev); | |
9585 | } else { | |
9586 | netif_carrier_off(vsi->netdev); | |
9587 | netif_tx_stop_all_queues(vsi->netdev); | |
9588 | } | |
9589 | break; | |
9590 | ||
9591 | case I40E_VSI_SRIOV: | |
41c445ff JB |
9592 | case I40E_VSI_VMDQ2: |
9593 | case I40E_VSI_CTRL: | |
e3219ce6 | 9594 | case I40E_VSI_IWARP: |
41c445ff JB |
9595 | case I40E_VSI_MIRROR: |
9596 | default: | |
9597 | /* there is no notification for other VSIs */ | |
9598 | break; | |
9599 | } | |
9600 | } | |
9601 | ||
9602 | /** | |
9603 | * i40e_veb_link_event - notify elements on the veb of a link event | |
9604 | * @veb: veb to be notified | |
9605 | * @link_up: link up or down | |
9606 | **/ | |
9607 | static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up) | |
9608 | { | |
9609 | struct i40e_pf *pf; | |
9610 | int i; | |
9611 | ||
9612 | if (!veb || !veb->pf) | |
9613 | return; | |
9614 | pf = veb->pf; | |
9615 | ||
9616 | /* depth first... */ | |
9617 | for (i = 0; i < I40E_MAX_VEB; i++) | |
9618 | if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid)) | |
9619 | i40e_veb_link_event(pf->veb[i], link_up); | |
9620 | ||
9621 | /* ... now the local VSIs */ | |
505682cd | 9622 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
9623 | if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid)) |
9624 | i40e_vsi_link_event(pf->vsi[i], link_up); | |
9625 | } | |
9626 | ||
9627 | /** | |
9628 | * i40e_link_event - Update netif_carrier status | |
9629 | * @pf: board private structure | |
9630 | **/ | |
9631 | static void i40e_link_event(struct i40e_pf *pf) | |
9632 | { | |
320684cd | 9633 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
fef59ddf | 9634 | u8 new_link_speed, old_link_speed; |
a72a5abc JB |
9635 | i40e_status status; |
9636 | bool new_link, old_link; | |
4b208eaa AK |
9637 | #ifdef CONFIG_I40E_DCB |
9638 | int err; | |
9639 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff | 9640 | |
1e701e09 JB |
9641 | /* set this to force the get_link_status call to refresh state */ |
9642 | pf->hw.phy.get_link_info = true; | |
41c445ff | 9643 | old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP); |
a72a5abc | 9644 | status = i40e_get_link_status(&pf->hw, &new_link); |
ae136708 HR |
9645 | |
9646 | /* On success, disable temp link polling */ | |
9647 | if (status == I40E_SUCCESS) { | |
0605c45c | 9648 | clear_bit(__I40E_TEMP_LINK_POLLING, pf->state); |
ae136708 HR |
9649 | } else { |
9650 | /* Enable link polling temporarily until i40e_get_link_status | |
9651 | * returns I40E_SUCCESS | |
9652 | */ | |
0605c45c | 9653 | set_bit(__I40E_TEMP_LINK_POLLING, pf->state); |
a72a5abc JB |
9654 | dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n", |
9655 | status); | |
9656 | return; | |
9657 | } | |
9658 | ||
fef59ddf CS |
9659 | old_link_speed = pf->hw.phy.link_info_old.link_speed; |
9660 | new_link_speed = pf->hw.phy.link_info.link_speed; | |
41c445ff | 9661 | |
1e701e09 | 9662 | if (new_link == old_link && |
fef59ddf | 9663 | new_link_speed == old_link_speed && |
0da36b97 | 9664 | (test_bit(__I40E_VSI_DOWN, vsi->state) || |
320684cd | 9665 | new_link == netif_carrier_ok(vsi->netdev))) |
41c445ff | 9666 | return; |
320684cd | 9667 | |
9a03449d | 9668 | i40e_print_link_message(vsi, new_link); |
41c445ff JB |
9669 | |
9670 | /* Notify the base of the switch tree connected to | |
9671 | * the link. Floating VEBs are not notified. | |
9672 | */ | |
f031c722 | 9673 | if (pf->lan_veb < I40E_MAX_VEB && pf->veb[pf->lan_veb]) |
41c445ff JB |
9674 | i40e_veb_link_event(pf->veb[pf->lan_veb], new_link); |
9675 | else | |
320684cd | 9676 | i40e_vsi_link_event(vsi, new_link); |
41c445ff JB |
9677 | |
9678 | if (pf->vf) | |
9679 | i40e_vc_notify_link_state(pf); | |
beb0dff1 JK |
9680 | |
9681 | if (pf->flags & I40E_FLAG_PTP) | |
9682 | i40e_ptp_set_increment(pf); | |
4b208eaa AK |
9683 | #ifdef CONFIG_I40E_DCB |
9684 | if (new_link == old_link) | |
9685 | return; | |
9686 | /* Not SW DCB so firmware will take care of default settings */ | |
9687 | if (pf->dcbx_cap & DCB_CAP_DCBX_LLD_MANAGED) | |
9688 | return; | |
9689 | ||
9690 | /* We cover here only link down, as after link up in case of SW DCB | |
9691 | * SW LLDP agent will take care of setting it up | |
9692 | */ | |
9693 | if (!new_link) { | |
9694 | dev_dbg(&pf->pdev->dev, "Reconfig DCB to single TC as result of Link Down\n"); | |
9695 | memset(&pf->tmp_cfg, 0, sizeof(pf->tmp_cfg)); | |
9696 | err = i40e_dcb_sw_default_config(pf); | |
9697 | if (err) { | |
9698 | pf->flags &= ~(I40E_FLAG_DCB_CAPABLE | | |
9699 | I40E_FLAG_DCB_ENABLED); | |
9700 | } else { | |
9701 | pf->dcbx_cap = DCB_CAP_DCBX_HOST | | |
9702 | DCB_CAP_DCBX_VER_IEEE; | |
9703 | pf->flags |= I40E_FLAG_DCB_CAPABLE; | |
9704 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
9705 | } | |
9706 | } | |
9707 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
9708 | } |
9709 | ||
41c445ff | 9710 | /** |
21536717 | 9711 | * i40e_watchdog_subtask - periodic checks not using event driven response |
41c445ff JB |
9712 | * @pf: board private structure |
9713 | **/ | |
9714 | static void i40e_watchdog_subtask(struct i40e_pf *pf) | |
9715 | { | |
9716 | int i; | |
9717 | ||
9718 | /* if interface is down do nothing */ | |
9e6c9c0f | 9719 | if (test_bit(__I40E_DOWN, pf->state) || |
0da36b97 | 9720 | test_bit(__I40E_CONFIG_BUSY, pf->state)) |
41c445ff JB |
9721 | return; |
9722 | ||
21536717 SN |
9723 | /* make sure we don't do these things too often */ |
9724 | if (time_before(jiffies, (pf->service_timer_previous + | |
9725 | pf->service_timer_period))) | |
9726 | return; | |
9727 | pf->service_timer_previous = jiffies; | |
9728 | ||
ae136708 | 9729 | if ((pf->flags & I40E_FLAG_LINK_POLLING_ENABLED) || |
0605c45c | 9730 | test_bit(__I40E_TEMP_LINK_POLLING, pf->state)) |
9ac77266 | 9731 | i40e_link_event(pf); |
21536717 | 9732 | |
41c445ff JB |
9733 | /* Update the stats for active netdevs so the network stack |
9734 | * can look at updated numbers whenever it cares to | |
9735 | */ | |
505682cd | 9736 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
9737 | if (pf->vsi[i] && pf->vsi[i]->netdev) |
9738 | i40e_update_stats(pf->vsi[i]); | |
9739 | ||
d1a8d275 ASJ |
9740 | if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) { |
9741 | /* Update the stats for the active switching components */ | |
9742 | for (i = 0; i < I40E_MAX_VEB; i++) | |
9743 | if (pf->veb[i]) | |
9744 | i40e_update_veb_stats(pf->veb[i]); | |
9745 | } | |
beb0dff1 | 9746 | |
61189556 | 9747 | i40e_ptp_rx_hang(pf); |
0bc0706b | 9748 | i40e_ptp_tx_hang(pf); |
41c445ff JB |
9749 | } |
9750 | ||
9751 | /** | |
9752 | * i40e_reset_subtask - Set up for resetting the device and driver | |
9753 | * @pf: board private structure | |
9754 | **/ | |
9755 | static void i40e_reset_subtask(struct i40e_pf *pf) | |
9756 | { | |
9757 | u32 reset_flags = 0; | |
9758 | ||
0da36b97 | 9759 | if (test_bit(__I40E_REINIT_REQUESTED, pf->state)) { |
75f5cea9 | 9760 | reset_flags |= BIT(__I40E_REINIT_REQUESTED); |
0da36b97 | 9761 | clear_bit(__I40E_REINIT_REQUESTED, pf->state); |
41c445ff | 9762 | } |
0da36b97 | 9763 | if (test_bit(__I40E_PF_RESET_REQUESTED, pf->state)) { |
75f5cea9 | 9764 | reset_flags |= BIT(__I40E_PF_RESET_REQUESTED); |
0da36b97 | 9765 | clear_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
41c445ff | 9766 | } |
0da36b97 | 9767 | if (test_bit(__I40E_CORE_RESET_REQUESTED, pf->state)) { |
75f5cea9 | 9768 | reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED); |
0da36b97 | 9769 | clear_bit(__I40E_CORE_RESET_REQUESTED, pf->state); |
41c445ff | 9770 | } |
0da36b97 | 9771 | if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state)) { |
75f5cea9 | 9772 | reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED); |
0da36b97 | 9773 | clear_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state); |
41c445ff | 9774 | } |
9e6c9c0f MR |
9775 | if (test_bit(__I40E_DOWN_REQUESTED, pf->state)) { |
9776 | reset_flags |= BIT(__I40E_DOWN_REQUESTED); | |
9777 | clear_bit(__I40E_DOWN_REQUESTED, pf->state); | |
b5d06f05 | 9778 | } |
41c445ff JB |
9779 | |
9780 | /* If there's a recovery already waiting, it takes | |
9781 | * precedence before starting a new reset sequence. | |
9782 | */ | |
0da36b97 | 9783 | if (test_bit(__I40E_RESET_INTR_RECEIVED, pf->state)) { |
4b208eaa | 9784 | i40e_prep_for_reset(pf); |
373149fc MS |
9785 | i40e_reset(pf); |
9786 | i40e_rebuild(pf, false, false); | |
41c445ff JB |
9787 | } |
9788 | ||
9789 | /* If we're already down or resetting, just bail */ | |
9790 | if (reset_flags && | |
9e6c9c0f | 9791 | !test_bit(__I40E_DOWN, pf->state) && |
0da36b97 | 9792 | !test_bit(__I40E_CONFIG_BUSY, pf->state)) { |
dfc4ff64 | 9793 | i40e_do_reset(pf, reset_flags, false); |
373149fc | 9794 | } |
41c445ff JB |
9795 | } |
9796 | ||
9797 | /** | |
9798 | * i40e_handle_link_event - Handle link event | |
9799 | * @pf: board private structure | |
9800 | * @e: event info posted on ARQ | |
9801 | **/ | |
9802 | static void i40e_handle_link_event(struct i40e_pf *pf, | |
9803 | struct i40e_arq_event_info *e) | |
9804 | { | |
41c445ff JB |
9805 | struct i40e_aqc_get_link_status *status = |
9806 | (struct i40e_aqc_get_link_status *)&e->desc.params.raw; | |
41c445ff | 9807 | |
1e701e09 JB |
9808 | /* Do a new status request to re-enable LSE reporting |
9809 | * and load new status information into the hw struct | |
9810 | * This completely ignores any state information | |
9811 | * in the ARQ event info, instead choosing to always | |
9812 | * issue the AQ update link status command. | |
9813 | */ | |
9814 | i40e_link_event(pf); | |
9815 | ||
9a858178 FS |
9816 | /* Check if module meets thermal requirements */ |
9817 | if (status->phy_type == I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP) { | |
7b592f61 | 9818 | dev_err(&pf->pdev->dev, |
9a858178 FS |
9819 | "Rx/Tx is disabled on this device because the module does not meet thermal requirements.\n"); |
9820 | dev_err(&pf->pdev->dev, | |
9821 | "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for a list of supported modules.\n"); | |
9822 | } else { | |
9823 | /* check for unqualified module, if link is down, suppress | |
9824 | * the message if link was forced to be down. | |
9825 | */ | |
9826 | if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) && | |
9827 | (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) && | |
9828 | (!(status->link_info & I40E_AQ_LINK_UP)) && | |
9829 | (!(pf->flags & I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED))) { | |
9830 | dev_err(&pf->pdev->dev, | |
9831 | "Rx/Tx is disabled on this device because an unsupported SFP module type was detected.\n"); | |
9832 | dev_err(&pf->pdev->dev, | |
9833 | "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for a list of supported modules.\n"); | |
9834 | } | |
9835 | } | |
41c445ff JB |
9836 | } |
9837 | ||
9838 | /** | |
9839 | * i40e_clean_adminq_subtask - Clean the AdminQ rings | |
9840 | * @pf: board private structure | |
9841 | **/ | |
9842 | static void i40e_clean_adminq_subtask(struct i40e_pf *pf) | |
9843 | { | |
9844 | struct i40e_arq_event_info event; | |
9845 | struct i40e_hw *hw = &pf->hw; | |
9846 | u16 pending, i = 0; | |
9847 | i40e_status ret; | |
9848 | u16 opcode; | |
86df242b | 9849 | u32 oldval; |
41c445ff JB |
9850 | u32 val; |
9851 | ||
a316f651 | 9852 | /* Do not run clean AQ when PF reset fails */ |
0da36b97 | 9853 | if (test_bit(__I40E_RESET_FAILED, pf->state)) |
a316f651 ASJ |
9854 | return; |
9855 | ||
86df242b SN |
9856 | /* check for error indications */ |
9857 | val = rd32(&pf->hw, pf->hw.aq.arq.len); | |
9858 | oldval = val; | |
9859 | if (val & I40E_PF_ARQLEN_ARQVFE_MASK) { | |
75eb73c1 MW |
9860 | if (hw->debug_mask & I40E_DEBUG_AQ) |
9861 | dev_info(&pf->pdev->dev, "ARQ VF Error detected\n"); | |
86df242b SN |
9862 | val &= ~I40E_PF_ARQLEN_ARQVFE_MASK; |
9863 | } | |
9864 | if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) { | |
75eb73c1 MW |
9865 | if (hw->debug_mask & I40E_DEBUG_AQ) |
9866 | dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n"); | |
86df242b | 9867 | val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK; |
1d0a4ada | 9868 | pf->arq_overflows++; |
86df242b SN |
9869 | } |
9870 | if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) { | |
75eb73c1 MW |
9871 | if (hw->debug_mask & I40E_DEBUG_AQ) |
9872 | dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n"); | |
86df242b SN |
9873 | val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK; |
9874 | } | |
9875 | if (oldval != val) | |
9876 | wr32(&pf->hw, pf->hw.aq.arq.len, val); | |
9877 | ||
9878 | val = rd32(&pf->hw, pf->hw.aq.asq.len); | |
9879 | oldval = val; | |
9880 | if (val & I40E_PF_ATQLEN_ATQVFE_MASK) { | |
75eb73c1 MW |
9881 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
9882 | dev_info(&pf->pdev->dev, "ASQ VF Error detected\n"); | |
86df242b SN |
9883 | val &= ~I40E_PF_ATQLEN_ATQVFE_MASK; |
9884 | } | |
9885 | if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) { | |
75eb73c1 MW |
9886 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
9887 | dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n"); | |
86df242b SN |
9888 | val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK; |
9889 | } | |
9890 | if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) { | |
75eb73c1 MW |
9891 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
9892 | dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n"); | |
86df242b SN |
9893 | val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK; |
9894 | } | |
9895 | if (oldval != val) | |
9896 | wr32(&pf->hw, pf->hw.aq.asq.len, val); | |
9897 | ||
1001dc37 MW |
9898 | event.buf_len = I40E_MAX_AQ_BUF_SIZE; |
9899 | event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL); | |
41c445ff JB |
9900 | if (!event.msg_buf) |
9901 | return; | |
9902 | ||
9903 | do { | |
9904 | ret = i40e_clean_arq_element(hw, &event, &pending); | |
56497978 | 9905 | if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) |
41c445ff | 9906 | break; |
56497978 | 9907 | else if (ret) { |
41c445ff JB |
9908 | dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret); |
9909 | break; | |
9910 | } | |
9911 | ||
9912 | opcode = le16_to_cpu(event.desc.opcode); | |
9913 | switch (opcode) { | |
9914 | ||
9915 | case i40e_aqc_opc_get_link_status: | |
4b208eaa | 9916 | rtnl_lock(); |
41c445ff | 9917 | i40e_handle_link_event(pf, &event); |
4b208eaa | 9918 | rtnl_unlock(); |
41c445ff JB |
9919 | break; |
9920 | case i40e_aqc_opc_send_msg_to_pf: | |
9921 | ret = i40e_vc_process_vf_msg(pf, | |
9922 | le16_to_cpu(event.desc.retval), | |
9923 | le32_to_cpu(event.desc.cookie_high), | |
9924 | le32_to_cpu(event.desc.cookie_low), | |
9925 | event.msg_buf, | |
1001dc37 | 9926 | event.msg_len); |
41c445ff JB |
9927 | break; |
9928 | case i40e_aqc_opc_lldp_update_mib: | |
69bfb110 | 9929 | dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n"); |
4e3b35b0 NP |
9930 | #ifdef CONFIG_I40E_DCB |
9931 | rtnl_lock(); | |
bfe2e5c4 | 9932 | i40e_handle_lldp_event(pf, &event); |
4e3b35b0 NP |
9933 | rtnl_unlock(); |
9934 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
9935 | break; |
9936 | case i40e_aqc_opc_event_lan_overflow: | |
69bfb110 | 9937 | dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n"); |
41c445ff JB |
9938 | i40e_handle_lan_overflow_event(pf, &event); |
9939 | break; | |
0467bc91 SN |
9940 | case i40e_aqc_opc_send_msg_to_peer: |
9941 | dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n"); | |
9942 | break; | |
91a0f930 SN |
9943 | case i40e_aqc_opc_nvm_erase: |
9944 | case i40e_aqc_opc_nvm_update: | |
00ada50d | 9945 | case i40e_aqc_opc_oem_post_update: |
6e93d0c9 SN |
9946 | i40e_debug(&pf->hw, I40E_DEBUG_NVM, |
9947 | "ARQ NVM operation 0x%04x completed\n", | |
9948 | opcode); | |
91a0f930 | 9949 | break; |
41c445ff JB |
9950 | default: |
9951 | dev_info(&pf->pdev->dev, | |
56e5ca68 | 9952 | "ARQ: Unknown event 0x%04x ignored\n", |
0467bc91 | 9953 | opcode); |
41c445ff JB |
9954 | break; |
9955 | } | |
1fca3265 CB |
9956 | } while (i++ < pf->adminq_work_limit); |
9957 | ||
9958 | if (i < pf->adminq_work_limit) | |
0da36b97 | 9959 | clear_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state); |
41c445ff | 9960 | |
41c445ff JB |
9961 | /* re-enable Admin queue interrupt cause */ |
9962 | val = rd32(hw, I40E_PFINT_ICR0_ENA); | |
9963 | val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
9964 | wr32(hw, I40E_PFINT_ICR0_ENA, val); | |
9965 | i40e_flush(hw); | |
9966 | ||
9967 | kfree(event.msg_buf); | |
9968 | } | |
9969 | ||
4eb3f768 SN |
9970 | /** |
9971 | * i40e_verify_eeprom - make sure eeprom is good to use | |
9972 | * @pf: board private structure | |
9973 | **/ | |
9974 | static void i40e_verify_eeprom(struct i40e_pf *pf) | |
9975 | { | |
9976 | int err; | |
9977 | ||
9978 | err = i40e_diag_eeprom_test(&pf->hw); | |
9979 | if (err) { | |
9980 | /* retry in case of garbage read */ | |
9981 | err = i40e_diag_eeprom_test(&pf->hw); | |
9982 | if (err) { | |
9983 | dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n", | |
9984 | err); | |
0da36b97 | 9985 | set_bit(__I40E_BAD_EEPROM, pf->state); |
4eb3f768 SN |
9986 | } |
9987 | } | |
9988 | ||
0da36b97 | 9989 | if (!err && test_bit(__I40E_BAD_EEPROM, pf->state)) { |
4eb3f768 | 9990 | dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n"); |
0da36b97 | 9991 | clear_bit(__I40E_BAD_EEPROM, pf->state); |
4eb3f768 SN |
9992 | } |
9993 | } | |
9994 | ||
386a0afa AA |
9995 | /** |
9996 | * i40e_enable_pf_switch_lb | |
b40c82e6 | 9997 | * @pf: pointer to the PF structure |
386a0afa AA |
9998 | * |
9999 | * enable switch loop back or die - no point in a return value | |
10000 | **/ | |
10001 | static void i40e_enable_pf_switch_lb(struct i40e_pf *pf) | |
10002 | { | |
10003 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
10004 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 10005 | int ret; |
386a0afa AA |
10006 | |
10007 | ctxt.seid = pf->main_vsi_seid; | |
10008 | ctxt.pf_num = pf->hw.pf_id; | |
10009 | ctxt.vf_num = 0; | |
f1c7e72e SN |
10010 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); |
10011 | if (ret) { | |
386a0afa | 10012 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
10013 | "couldn't get PF vsi config, err %s aq_err %s\n", |
10014 | i40e_stat_str(&pf->hw, ret), | |
10015 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
10016 | return; |
10017 | } | |
10018 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
10019 | ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
10020 | ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
10021 | ||
f1c7e72e SN |
10022 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
10023 | if (ret) { | |
386a0afa | 10024 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
10025 | "update vsi switch failed, err %s aq_err %s\n", |
10026 | i40e_stat_str(&pf->hw, ret), | |
10027 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
10028 | } |
10029 | } | |
10030 | ||
10031 | /** | |
10032 | * i40e_disable_pf_switch_lb | |
b40c82e6 | 10033 | * @pf: pointer to the PF structure |
386a0afa AA |
10034 | * |
10035 | * disable switch loop back or die - no point in a return value | |
10036 | **/ | |
10037 | static void i40e_disable_pf_switch_lb(struct i40e_pf *pf) | |
10038 | { | |
10039 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
10040 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 10041 | int ret; |
386a0afa AA |
10042 | |
10043 | ctxt.seid = pf->main_vsi_seid; | |
10044 | ctxt.pf_num = pf->hw.pf_id; | |
10045 | ctxt.vf_num = 0; | |
f1c7e72e SN |
10046 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); |
10047 | if (ret) { | |
386a0afa | 10048 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
10049 | "couldn't get PF vsi config, err %s aq_err %s\n", |
10050 | i40e_stat_str(&pf->hw, ret), | |
10051 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
10052 | return; |
10053 | } | |
10054 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
10055 | ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
10056 | ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
10057 | ||
f1c7e72e SN |
10058 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
10059 | if (ret) { | |
386a0afa | 10060 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
10061 | "update vsi switch failed, err %s aq_err %s\n", |
10062 | i40e_stat_str(&pf->hw, ret), | |
10063 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
10064 | } |
10065 | } | |
10066 | ||
51616018 NP |
10067 | /** |
10068 | * i40e_config_bridge_mode - Configure the HW bridge mode | |
10069 | * @veb: pointer to the bridge instance | |
10070 | * | |
10071 | * Configure the loop back mode for the LAN VSI that is downlink to the | |
10072 | * specified HW bridge instance. It is expected this function is called | |
10073 | * when a new HW bridge is instantiated. | |
10074 | **/ | |
10075 | static void i40e_config_bridge_mode(struct i40e_veb *veb) | |
10076 | { | |
10077 | struct i40e_pf *pf = veb->pf; | |
10078 | ||
6dec1017 SN |
10079 | if (pf->hw.debug_mask & I40E_DEBUG_LAN) |
10080 | dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n", | |
10081 | veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); | |
51616018 NP |
10082 | if (veb->bridge_mode & BRIDGE_MODE_VEPA) |
10083 | i40e_disable_pf_switch_lb(pf); | |
10084 | else | |
10085 | i40e_enable_pf_switch_lb(pf); | |
10086 | } | |
10087 | ||
41c445ff JB |
10088 | /** |
10089 | * i40e_reconstitute_veb - rebuild the VEB and anything connected to it | |
10090 | * @veb: pointer to the VEB instance | |
10091 | * | |
10092 | * This is a recursive function that first builds the attached VSIs then | |
10093 | * recurses in to build the next layer of VEB. We track the connections | |
10094 | * through our own index numbers because the seid's from the HW could | |
10095 | * change across the reset. | |
10096 | **/ | |
10097 | static int i40e_reconstitute_veb(struct i40e_veb *veb) | |
10098 | { | |
10099 | struct i40e_vsi *ctl_vsi = NULL; | |
10100 | struct i40e_pf *pf = veb->pf; | |
10101 | int v, veb_idx; | |
10102 | int ret; | |
10103 | ||
10104 | /* build VSI that owns this VEB, temporarily attached to base VEB */ | |
505682cd | 10105 | for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) { |
41c445ff JB |
10106 | if (pf->vsi[v] && |
10107 | pf->vsi[v]->veb_idx == veb->idx && | |
10108 | pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) { | |
10109 | ctl_vsi = pf->vsi[v]; | |
10110 | break; | |
10111 | } | |
10112 | } | |
10113 | if (!ctl_vsi) { | |
10114 | dev_info(&pf->pdev->dev, | |
10115 | "missing owner VSI for veb_idx %d\n", veb->idx); | |
10116 | ret = -ENOENT; | |
10117 | goto end_reconstitute; | |
10118 | } | |
10119 | if (ctl_vsi != pf->vsi[pf->lan_vsi]) | |
10120 | ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
10121 | ret = i40e_add_vsi(ctl_vsi); | |
10122 | if (ret) { | |
10123 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10124 | "rebuild of veb_idx %d owner VSI failed: %d\n", |
10125 | veb->idx, ret); | |
41c445ff JB |
10126 | goto end_reconstitute; |
10127 | } | |
10128 | i40e_vsi_reset_stats(ctl_vsi); | |
10129 | ||
10130 | /* create the VEB in the switch and move the VSI onto the VEB */ | |
10131 | ret = i40e_add_veb(veb, ctl_vsi); | |
10132 | if (ret) | |
10133 | goto end_reconstitute; | |
10134 | ||
fc60861e ASJ |
10135 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) |
10136 | veb->bridge_mode = BRIDGE_MODE_VEB; | |
10137 | else | |
10138 | veb->bridge_mode = BRIDGE_MODE_VEPA; | |
51616018 | 10139 | i40e_config_bridge_mode(veb); |
b64ba084 | 10140 | |
41c445ff | 10141 | /* create the remaining VSIs attached to this VEB */ |
505682cd | 10142 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
10143 | if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi) |
10144 | continue; | |
10145 | ||
10146 | if (pf->vsi[v]->veb_idx == veb->idx) { | |
10147 | struct i40e_vsi *vsi = pf->vsi[v]; | |
6995b36c | 10148 | |
41c445ff JB |
10149 | vsi->uplink_seid = veb->seid; |
10150 | ret = i40e_add_vsi(vsi); | |
10151 | if (ret) { | |
10152 | dev_info(&pf->pdev->dev, | |
10153 | "rebuild of vsi_idx %d failed: %d\n", | |
10154 | v, ret); | |
10155 | goto end_reconstitute; | |
10156 | } | |
10157 | i40e_vsi_reset_stats(vsi); | |
10158 | } | |
10159 | } | |
10160 | ||
10161 | /* create any VEBs attached to this VEB - RECURSION */ | |
10162 | for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { | |
10163 | if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) { | |
10164 | pf->veb[veb_idx]->uplink_seid = veb->seid; | |
10165 | ret = i40e_reconstitute_veb(pf->veb[veb_idx]); | |
10166 | if (ret) | |
10167 | break; | |
10168 | } | |
10169 | } | |
10170 | ||
10171 | end_reconstitute: | |
10172 | return ret; | |
10173 | } | |
10174 | ||
10175 | /** | |
10176 | * i40e_get_capabilities - get info about the HW | |
10177 | * @pf: the PF struct | |
b50f7bca | 10178 | * @list_type: AQ capability to be queried |
41c445ff | 10179 | **/ |
2f4b411a AN |
10180 | static int i40e_get_capabilities(struct i40e_pf *pf, |
10181 | enum i40e_admin_queue_opc list_type) | |
41c445ff JB |
10182 | { |
10183 | struct i40e_aqc_list_capabilities_element_resp *cap_buf; | |
10184 | u16 data_size; | |
10185 | int buf_len; | |
10186 | int err; | |
10187 | ||
10188 | buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); | |
10189 | do { | |
10190 | cap_buf = kzalloc(buf_len, GFP_KERNEL); | |
10191 | if (!cap_buf) | |
10192 | return -ENOMEM; | |
10193 | ||
10194 | /* this loads the data into the hw struct for us */ | |
10195 | err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len, | |
2f4b411a AN |
10196 | &data_size, list_type, |
10197 | NULL); | |
41c445ff JB |
10198 | /* data loaded, buffer no longer needed */ |
10199 | kfree(cap_buf); | |
10200 | ||
10201 | if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) { | |
10202 | /* retry with a larger buffer */ | |
10203 | buf_len = data_size; | |
857b6c6f | 10204 | } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK || err) { |
41c445ff | 10205 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
10206 | "capability discovery failed, err %s aq_err %s\n", |
10207 | i40e_stat_str(&pf->hw, err), | |
10208 | i40e_aq_str(&pf->hw, | |
10209 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10210 | return -ENODEV; |
10211 | } | |
10212 | } while (err); | |
10213 | ||
2f4b411a AN |
10214 | if (pf->hw.debug_mask & I40E_DEBUG_USER) { |
10215 | if (list_type == i40e_aqc_opc_list_func_capabilities) { | |
10216 | dev_info(&pf->pdev->dev, | |
10217 | "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n", | |
10218 | pf->hw.pf_id, pf->hw.func_caps.num_vfs, | |
10219 | pf->hw.func_caps.num_msix_vectors, | |
10220 | pf->hw.func_caps.num_msix_vectors_vf, | |
10221 | pf->hw.func_caps.fd_filters_guaranteed, | |
10222 | pf->hw.func_caps.fd_filters_best_effort, | |
10223 | pf->hw.func_caps.num_tx_qp, | |
10224 | pf->hw.func_caps.num_vsis); | |
10225 | } else if (list_type == i40e_aqc_opc_list_dev_capabilities) { | |
10226 | dev_info(&pf->pdev->dev, | |
10227 | "switch_mode=0x%04x, function_valid=0x%08x\n", | |
10228 | pf->hw.dev_caps.switch_mode, | |
10229 | pf->hw.dev_caps.valid_functions); | |
10230 | dev_info(&pf->pdev->dev, | |
10231 | "SR-IOV=%d, num_vfs for all function=%u\n", | |
10232 | pf->hw.dev_caps.sr_iov_1_1, | |
10233 | pf->hw.dev_caps.num_vfs); | |
10234 | dev_info(&pf->pdev->dev, | |
10235 | "num_vsis=%u, num_rx:%u, num_tx=%u\n", | |
10236 | pf->hw.dev_caps.num_vsis, | |
10237 | pf->hw.dev_caps.num_rx_qp, | |
10238 | pf->hw.dev_caps.num_tx_qp); | |
10239 | } | |
10240 | } | |
10241 | if (list_type == i40e_aqc_opc_list_func_capabilities) { | |
7134f9ce JB |
10242 | #define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \ |
10243 | + pf->hw.func_caps.num_vfs) | |
2f4b411a AN |
10244 | if (pf->hw.revision_id == 0 && |
10245 | pf->hw.func_caps.num_vsis < DEF_NUM_VSI) { | |
10246 | dev_info(&pf->pdev->dev, | |
10247 | "got num_vsis %d, setting num_vsis to %d\n", | |
10248 | pf->hw.func_caps.num_vsis, DEF_NUM_VSI); | |
10249 | pf->hw.func_caps.num_vsis = DEF_NUM_VSI; | |
10250 | } | |
7134f9ce | 10251 | } |
41c445ff JB |
10252 | return 0; |
10253 | } | |
10254 | ||
cbf61325 ASJ |
10255 | static int i40e_vsi_clear(struct i40e_vsi *vsi); |
10256 | ||
41c445ff | 10257 | /** |
cbf61325 | 10258 | * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband |
41c445ff JB |
10259 | * @pf: board private structure |
10260 | **/ | |
cbf61325 | 10261 | static void i40e_fdir_sb_setup(struct i40e_pf *pf) |
41c445ff JB |
10262 | { |
10263 | struct i40e_vsi *vsi; | |
41c445ff | 10264 | |
407e063c JB |
10265 | /* quick workaround for an NVM issue that leaves a critical register |
10266 | * uninitialized | |
10267 | */ | |
10268 | if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) { | |
10269 | static const u32 hkey[] = { | |
10270 | 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36, | |
10271 | 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb, | |
10272 | 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21, | |
10273 | 0x95b3a76d}; | |
4b816446 | 10274 | int i; |
407e063c JB |
10275 | |
10276 | for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++) | |
10277 | wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]); | |
10278 | } | |
10279 | ||
cbf61325 | 10280 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) |
41c445ff JB |
10281 | return; |
10282 | ||
cbf61325 | 10283 | /* find existing VSI and see if it needs configuring */ |
4b816446 | 10284 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
cbf61325 ASJ |
10285 | |
10286 | /* create a new VSI if none exists */ | |
41c445ff | 10287 | if (!vsi) { |
cbf61325 ASJ |
10288 | vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, |
10289 | pf->vsi[pf->lan_vsi]->seid, 0); | |
41c445ff JB |
10290 | if (!vsi) { |
10291 | dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n"); | |
8a9eb7d3 | 10292 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; |
2f4b411a | 10293 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
8a9eb7d3 | 10294 | return; |
41c445ff | 10295 | } |
cbf61325 | 10296 | } |
41c445ff | 10297 | |
8a9eb7d3 | 10298 | i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring); |
41c445ff JB |
10299 | } |
10300 | ||
10301 | /** | |
10302 | * i40e_fdir_teardown - release the Flow Director resources | |
10303 | * @pf: board private structure | |
10304 | **/ | |
10305 | static void i40e_fdir_teardown(struct i40e_pf *pf) | |
10306 | { | |
4b816446 | 10307 | struct i40e_vsi *vsi; |
41c445ff | 10308 | |
17a73f6b | 10309 | i40e_fdir_filter_exit(pf); |
4b816446 AD |
10310 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
10311 | if (vsi) | |
10312 | i40e_vsi_release(vsi); | |
41c445ff JB |
10313 | } |
10314 | ||
2f4b411a AN |
10315 | /** |
10316 | * i40e_rebuild_cloud_filters - Rebuilds cloud filters for VSIs | |
10317 | * @vsi: PF main vsi | |
10318 | * @seid: seid of main or channel VSIs | |
10319 | * | |
10320 | * Rebuilds cloud filters associated with main VSI and channel VSIs if they | |
10321 | * existed before reset | |
10322 | **/ | |
10323 | static int i40e_rebuild_cloud_filters(struct i40e_vsi *vsi, u16 seid) | |
10324 | { | |
10325 | struct i40e_cloud_filter *cfilter; | |
10326 | struct i40e_pf *pf = vsi->back; | |
10327 | struct hlist_node *node; | |
10328 | i40e_status ret; | |
10329 | ||
10330 | /* Add cloud filters back if they exist */ | |
10331 | hlist_for_each_entry_safe(cfilter, node, &pf->cloud_filter_list, | |
10332 | cloud_node) { | |
10333 | if (cfilter->seid != seid) | |
10334 | continue; | |
10335 | ||
10336 | if (cfilter->dst_port) | |
10337 | ret = i40e_add_del_cloud_filter_big_buf(vsi, cfilter, | |
10338 | true); | |
10339 | else | |
10340 | ret = i40e_add_del_cloud_filter(vsi, cfilter, true); | |
cbf61325 | 10341 | |
2f4b411a AN |
10342 | if (ret) { |
10343 | dev_dbg(&pf->pdev->dev, | |
10344 | "Failed to rebuild cloud filter, err %s aq_err %s\n", | |
10345 | i40e_stat_str(&pf->hw, ret), | |
10346 | i40e_aq_str(&pf->hw, | |
10347 | pf->hw.aq.asq_last_status)); | |
10348 | return ret; | |
41c445ff | 10349 | } |
cbf61325 | 10350 | } |
2f4b411a | 10351 | return 0; |
41c445ff JB |
10352 | } |
10353 | ||
10354 | /** | |
8f88b303 AN |
10355 | * i40e_rebuild_channels - Rebuilds channel VSIs if they existed before reset |
10356 | * @vsi: PF main vsi | |
10357 | * | |
10358 | * Rebuilds channel VSIs if they existed before reset | |
41c445ff | 10359 | **/ |
8f88b303 | 10360 | static int i40e_rebuild_channels(struct i40e_vsi *vsi) |
41c445ff | 10361 | { |
8f88b303 AN |
10362 | struct i40e_channel *ch, *ch_tmp; |
10363 | i40e_status ret; | |
41c445ff | 10364 | |
8f88b303 AN |
10365 | if (list_empty(&vsi->ch_list)) |
10366 | return 0; | |
10367 | ||
10368 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) { | |
10369 | if (!ch->initialized) | |
10370 | break; | |
10371 | /* Proceed with creation of channel (VMDq2) VSI */ | |
10372 | ret = i40e_add_channel(vsi->back, vsi->uplink_seid, ch); | |
10373 | if (ret) { | |
10374 | dev_info(&vsi->back->pdev->dev, | |
10375 | "failed to rebuild channels using uplink_seid %u\n", | |
10376 | vsi->uplink_seid); | |
10377 | return ret; | |
10378 | } | |
bbf0bdd4 AN |
10379 | /* Reconfigure TX queues using QTX_CTL register */ |
10380 | ret = i40e_channel_config_tx_ring(vsi->back, vsi, ch); | |
10381 | if (ret) { | |
10382 | dev_info(&vsi->back->pdev->dev, | |
10383 | "failed to configure TX rings for channel %u\n", | |
10384 | ch->seid); | |
10385 | return ret; | |
10386 | } | |
10387 | /* update 'next_base_queue' */ | |
10388 | vsi->next_base_queue = vsi->next_base_queue + | |
10389 | ch->num_queue_pairs; | |
2027d4de | 10390 | if (ch->max_tx_rate) { |
6c32e0d9 AB |
10391 | u64 credits = ch->max_tx_rate; |
10392 | ||
2027d4de AN |
10393 | if (i40e_set_bw_limit(vsi, ch->seid, |
10394 | ch->max_tx_rate)) | |
10395 | return -EINVAL; | |
10396 | ||
6c32e0d9 | 10397 | do_div(credits, I40E_BW_CREDIT_DIVISOR); |
2027d4de AN |
10398 | dev_dbg(&vsi->back->pdev->dev, |
10399 | "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n", | |
10400 | ch->max_tx_rate, | |
6c32e0d9 | 10401 | credits, |
2027d4de AN |
10402 | ch->seid); |
10403 | } | |
2f4b411a AN |
10404 | ret = i40e_rebuild_cloud_filters(vsi, ch->seid); |
10405 | if (ret) { | |
10406 | dev_dbg(&vsi->back->pdev->dev, | |
10407 | "Failed to rebuild cloud filters for channel VSI %u\n", | |
10408 | ch->seid); | |
10409 | return ret; | |
10410 | } | |
8f88b303 AN |
10411 | } |
10412 | return 0; | |
41c445ff JB |
10413 | } |
10414 | ||
10415 | /** | |
f650a38b | 10416 | * i40e_prep_for_reset - prep for the core to reset |
41c445ff JB |
10417 | * @pf: board private structure |
10418 | * | |
b40c82e6 | 10419 | * Close up the VFs and other things in prep for PF Reset. |
f650a38b | 10420 | **/ |
4b208eaa | 10421 | static void i40e_prep_for_reset(struct i40e_pf *pf) |
41c445ff | 10422 | { |
41c445ff | 10423 | struct i40e_hw *hw = &pf->hw; |
60442dea | 10424 | i40e_status ret = 0; |
41c445ff JB |
10425 | u32 v; |
10426 | ||
0da36b97 JK |
10427 | clear_bit(__I40E_RESET_INTR_RECEIVED, pf->state); |
10428 | if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) | |
23cfbe07 | 10429 | return; |
d3ce5734 MW |
10430 | if (i40e_check_asq_alive(&pf->hw)) |
10431 | i40e_vc_notify_reset(pf); | |
41c445ff | 10432 | |
69bfb110 | 10433 | dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n"); |
41c445ff | 10434 | |
41c445ff JB |
10435 | /* quiesce the VSIs and their queues that are not already DOWN */ |
10436 | i40e_pf_quiesce_all_vsi(pf); | |
10437 | ||
505682cd | 10438 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
10439 | if (pf->vsi[v]) |
10440 | pf->vsi[v]->seid = 0; | |
10441 | } | |
10442 | ||
10443 | i40e_shutdown_adminq(&pf->hw); | |
10444 | ||
f650a38b | 10445 | /* call shutdown HMC */ |
60442dea SN |
10446 | if (hw->hmc.hmc_obj) { |
10447 | ret = i40e_shutdown_lan_hmc(hw); | |
23cfbe07 | 10448 | if (ret) |
60442dea SN |
10449 | dev_warn(&pf->pdev->dev, |
10450 | "shutdown_lan_hmc failed: %d\n", ret); | |
f650a38b | 10451 | } |
bf4bf09b JK |
10452 | |
10453 | /* Save the current PTP time so that we can restore the time after the | |
10454 | * reset completes. | |
10455 | */ | |
10456 | i40e_ptp_save_hw_time(pf); | |
f650a38b ASJ |
10457 | } |
10458 | ||
44033fac JB |
10459 | /** |
10460 | * i40e_send_version - update firmware with driver version | |
10461 | * @pf: PF struct | |
10462 | */ | |
10463 | static void i40e_send_version(struct i40e_pf *pf) | |
10464 | { | |
10465 | struct i40e_driver_version dv; | |
10466 | ||
34a2a3b8 JK |
10467 | dv.major_version = 0xff; |
10468 | dv.minor_version = 0xff; | |
10469 | dv.build_version = 0xff; | |
44033fac | 10470 | dv.subbuild_version = 0; |
34a2a3b8 | 10471 | strlcpy(dv.driver_string, UTS_RELEASE, sizeof(dv.driver_string)); |
44033fac JB |
10472 | i40e_aq_send_driver_version(&pf->hw, &dv, NULL); |
10473 | } | |
10474 | ||
5bbb2e20 FS |
10475 | /** |
10476 | * i40e_get_oem_version - get OEM specific version information | |
10477 | * @hw: pointer to the hardware structure | |
10478 | **/ | |
10479 | static void i40e_get_oem_version(struct i40e_hw *hw) | |
10480 | { | |
10481 | u16 block_offset = 0xffff; | |
10482 | u16 block_length = 0; | |
10483 | u16 capabilities = 0; | |
10484 | u16 gen_snap = 0; | |
10485 | u16 release = 0; | |
10486 | ||
10487 | #define I40E_SR_NVM_OEM_VERSION_PTR 0x1B | |
10488 | #define I40E_NVM_OEM_LENGTH_OFFSET 0x00 | |
10489 | #define I40E_NVM_OEM_CAPABILITIES_OFFSET 0x01 | |
10490 | #define I40E_NVM_OEM_GEN_OFFSET 0x02 | |
10491 | #define I40E_NVM_OEM_RELEASE_OFFSET 0x03 | |
10492 | #define I40E_NVM_OEM_CAPABILITIES_MASK 0x000F | |
10493 | #define I40E_NVM_OEM_LENGTH 3 | |
10494 | ||
10495 | /* Check if pointer to OEM version block is valid. */ | |
10496 | i40e_read_nvm_word(hw, I40E_SR_NVM_OEM_VERSION_PTR, &block_offset); | |
10497 | if (block_offset == 0xffff) | |
10498 | return; | |
10499 | ||
10500 | /* Check if OEM version block has correct length. */ | |
10501 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_LENGTH_OFFSET, | |
10502 | &block_length); | |
10503 | if (block_length < I40E_NVM_OEM_LENGTH) | |
10504 | return; | |
10505 | ||
10506 | /* Check if OEM version format is as expected. */ | |
10507 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_CAPABILITIES_OFFSET, | |
10508 | &capabilities); | |
10509 | if ((capabilities & I40E_NVM_OEM_CAPABILITIES_MASK) != 0) | |
10510 | return; | |
10511 | ||
10512 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_GEN_OFFSET, | |
10513 | &gen_snap); | |
10514 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_RELEASE_OFFSET, | |
10515 | &release); | |
10516 | hw->nvm.oem_ver = (gen_snap << I40E_OEM_SNAP_SHIFT) | release; | |
10517 | hw->nvm.eetrack = I40E_OEM_EETRACK_ID; | |
10518 | } | |
10519 | ||
f650a38b | 10520 | /** |
373149fc | 10521 | * i40e_reset - wait for core reset to finish reset, reset pf if corer not seen |
f650a38b ASJ |
10522 | * @pf: board private structure |
10523 | **/ | |
373149fc | 10524 | static int i40e_reset(struct i40e_pf *pf) |
f650a38b | 10525 | { |
f650a38b ASJ |
10526 | struct i40e_hw *hw = &pf->hw; |
10527 | i40e_status ret; | |
f650a38b | 10528 | |
41c445ff | 10529 | ret = i40e_pf_reset(hw); |
b5565400 | 10530 | if (ret) { |
41c445ff | 10531 | dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret); |
0da36b97 JK |
10532 | set_bit(__I40E_RESET_FAILED, pf->state); |
10533 | clear_bit(__I40E_RESET_RECOVERY_PENDING, pf->state); | |
373149fc MS |
10534 | } else { |
10535 | pf->pfr_count++; | |
b5565400 | 10536 | } |
373149fc MS |
10537 | return ret; |
10538 | } | |
10539 | ||
10540 | /** | |
10541 | * i40e_rebuild - rebuild using a saved config | |
10542 | * @pf: board private structure | |
10543 | * @reinit: if the Main VSI needs to re-initialized. | |
10544 | * @lock_acquired: indicates whether or not the lock has been acquired | |
10545 | * before this function was called. | |
10546 | **/ | |
10547 | static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired) | |
10548 | { | |
4ff0ee1a | 10549 | int old_recovery_mode_bit = test_bit(__I40E_RECOVERY_MODE, pf->state); |
2027d4de | 10550 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
373149fc | 10551 | struct i40e_hw *hw = &pf->hw; |
373149fc MS |
10552 | i40e_status ret; |
10553 | u32 val; | |
10554 | int v; | |
41c445ff | 10555 | |
4ff0ee1a AM |
10556 | if (test_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state) && |
10557 | i40e_check_recovery_mode(pf)) { | |
10558 | i40e_set_ethtool_ops(pf->vsi[pf->lan_vsi]->netdev); | |
10559 | } | |
10560 | ||
10561 | if (test_bit(__I40E_DOWN, pf->state) && | |
10562 | !test_bit(__I40E_RECOVERY_MODE, pf->state) && | |
10563 | !old_recovery_mode_bit) | |
a316f651 | 10564 | goto clear_recovery; |
69bfb110 | 10565 | dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n"); |
41c445ff JB |
10566 | |
10567 | /* rebuild the basics for the AdminQ, HMC, and initial HW switch */ | |
10568 | ret = i40e_init_adminq(&pf->hw); | |
10569 | if (ret) { | |
f1c7e72e SN |
10570 | dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n", |
10571 | i40e_stat_str(&pf->hw, ret), | |
10572 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
a316f651 | 10573 | goto clear_recovery; |
41c445ff | 10574 | } |
5bbb2e20 | 10575 | i40e_get_oem_version(&pf->hw); |
41c445ff | 10576 | |
9b13bd53 JJ |
10577 | if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state)) { |
10578 | /* The following delay is necessary for firmware update. */ | |
10579 | mdelay(1000); | |
1fa51a65 FS |
10580 | } |
10581 | ||
4eb3f768 | 10582 | /* re-verify the eeprom if we just had an EMP reset */ |
0da36b97 | 10583 | if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state)) |
4eb3f768 | 10584 | i40e_verify_eeprom(pf); |
4eb3f768 | 10585 | |
4ff0ee1a AM |
10586 | /* if we are going out of or into recovery mode we have to act |
10587 | * accordingly with regard to resources initialization | |
10588 | * and deinitialization | |
10589 | */ | |
10590 | if (test_bit(__I40E_RECOVERY_MODE, pf->state) || | |
10591 | old_recovery_mode_bit) { | |
10592 | if (i40e_get_capabilities(pf, | |
10593 | i40e_aqc_opc_list_func_capabilities)) | |
10594 | goto end_unlock; | |
10595 | ||
10596 | if (test_bit(__I40E_RECOVERY_MODE, pf->state)) { | |
10597 | /* we're staying in recovery mode so we'll reinitialize | |
10598 | * misc vector here | |
10599 | */ | |
10600 | if (i40e_setup_misc_vector_for_recovery_mode(pf)) | |
10601 | goto end_unlock; | |
10602 | } else { | |
10603 | if (!lock_acquired) | |
10604 | rtnl_lock(); | |
10605 | /* we're going out of recovery mode so we'll free | |
10606 | * the IRQ allocated specifically for recovery mode | |
10607 | * and restore the interrupt scheme | |
10608 | */ | |
10609 | free_irq(pf->pdev->irq, pf); | |
10610 | i40e_clear_interrupt_scheme(pf); | |
10611 | if (i40e_restore_interrupt_scheme(pf)) | |
10612 | goto end_unlock; | |
10613 | } | |
10614 | ||
10615 | /* tell the firmware that we're starting */ | |
10616 | i40e_send_version(pf); | |
10617 | ||
10618 | /* bail out in case recovery mode was detected, as there is | |
10619 | * no need for further configuration. | |
10620 | */ | |
10621 | goto end_unlock; | |
10622 | } | |
10623 | ||
e78ac4bf | 10624 | i40e_clear_pxe_mode(hw); |
2f4b411a | 10625 | ret = i40e_get_capabilities(pf, i40e_aqc_opc_list_func_capabilities); |
f1c7e72e | 10626 | if (ret) |
41c445ff | 10627 | goto end_core_reset; |
41c445ff | 10628 | |
41c445ff | 10629 | ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, |
c76cb6ed | 10630 | hw->func_caps.num_rx_qp, 0, 0); |
41c445ff JB |
10631 | if (ret) { |
10632 | dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret); | |
10633 | goto end_core_reset; | |
10634 | } | |
10635 | ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); | |
10636 | if (ret) { | |
10637 | dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret); | |
10638 | goto end_core_reset; | |
10639 | } | |
10640 | ||
4b208eaa AK |
10641 | #ifdef CONFIG_I40E_DCB |
10642 | /* Enable FW to write a default DCB config on link-up | |
10643 | * unless I40E_FLAG_TC_MQPRIO was enabled or DCB | |
10644 | * is not supported with new link speed | |
10645 | */ | |
10646 | if (pf->flags & I40E_FLAG_TC_MQPRIO) { | |
10647 | i40e_aq_set_dcb_parameters(hw, false, NULL); | |
10648 | } else { | |
10649 | if (I40E_IS_X710TL_DEVICE(hw->device_id) && | |
10650 | (hw->phy.link_info.link_speed & | |
10651 | (I40E_LINK_SPEED_2_5GB | I40E_LINK_SPEED_5GB))) { | |
10652 | i40e_aq_set_dcb_parameters(hw, false, NULL); | |
10653 | dev_warn(&pf->pdev->dev, | |
10654 | "DCB is not supported for X710-T*L 2.5/5G speeds\n"); | |
7a75a841 | 10655 | pf->flags &= ~I40E_FLAG_DCB_CAPABLE; |
4b208eaa AK |
10656 | } else { |
10657 | i40e_aq_set_dcb_parameters(hw, true, NULL); | |
10658 | ret = i40e_init_pf_dcb(pf); | |
10659 | if (ret) { | |
10660 | dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", | |
10661 | ret); | |
10662 | pf->flags &= ~I40E_FLAG_DCB_CAPABLE; | |
10663 | /* Continue without DCB enabled */ | |
10664 | } | |
10665 | } | |
10666 | } | |
10667 | ||
10668 | #endif /* CONFIG_I40E_DCB */ | |
f2916ae9 AK |
10669 | if (!lock_acquired) |
10670 | rtnl_lock(); | |
956e759d | 10671 | ret = i40e_setup_pf_switch(pf, reinit, true); |
f2916ae9 AK |
10672 | if (ret) |
10673 | goto end_unlock; | |
4b208eaa | 10674 | |
2f0aff41 SN |
10675 | /* The driver only wants link up/down and module qualification |
10676 | * reports from firmware. Note the negative logic. | |
7e2453fe JB |
10677 | */ |
10678 | ret = i40e_aq_set_phy_int_mask(&pf->hw, | |
2f0aff41 | 10679 | ~(I40E_AQ_EVENT_LINK_UPDOWN | |
867a79e3 | 10680 | I40E_AQ_EVENT_MEDIA_NA | |
2f0aff41 | 10681 | I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); |
7e2453fe | 10682 | if (ret) |
f1c7e72e SN |
10683 | dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", |
10684 | i40e_stat_str(&pf->hw, ret), | |
10685 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7e2453fe | 10686 | |
41c445ff JB |
10687 | /* Rebuild the VSIs and VEBs that existed before reset. |
10688 | * They are still in our local switch element arrays, so only | |
10689 | * need to rebuild the switch model in the HW. | |
10690 | * | |
10691 | * If there were VEBs but the reconstitution failed, we'll try | |
059ff70c | 10692 | * to recover minimal use by getting the basic PF VSI working. |
41c445ff | 10693 | */ |
2027d4de | 10694 | if (vsi->uplink_seid != pf->mac_seid) { |
69bfb110 | 10695 | dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n"); |
41c445ff JB |
10696 | /* find the one VEB connected to the MAC, and find orphans */ |
10697 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
10698 | if (!pf->veb[v]) | |
10699 | continue; | |
10700 | ||
10701 | if (pf->veb[v]->uplink_seid == pf->mac_seid || | |
10702 | pf->veb[v]->uplink_seid == 0) { | |
10703 | ret = i40e_reconstitute_veb(pf->veb[v]); | |
10704 | ||
10705 | if (!ret) | |
10706 | continue; | |
10707 | ||
10708 | /* If Main VEB failed, we're in deep doodoo, | |
10709 | * so give up rebuilding the switch and set up | |
10710 | * for minimal rebuild of PF VSI. | |
10711 | * If orphan failed, we'll report the error | |
10712 | * but try to keep going. | |
10713 | */ | |
10714 | if (pf->veb[v]->uplink_seid == pf->mac_seid) { | |
10715 | dev_info(&pf->pdev->dev, | |
10716 | "rebuild of switch failed: %d, will try to set up simple PF connection\n", | |
10717 | ret); | |
2027d4de | 10718 | vsi->uplink_seid = pf->mac_seid; |
41c445ff JB |
10719 | break; |
10720 | } else if (pf->veb[v]->uplink_seid == 0) { | |
10721 | dev_info(&pf->pdev->dev, | |
10722 | "rebuild of orphan VEB failed: %d\n", | |
10723 | ret); | |
10724 | } | |
10725 | } | |
10726 | } | |
10727 | } | |
10728 | ||
2027d4de | 10729 | if (vsi->uplink_seid == pf->mac_seid) { |
cde4cbc7 | 10730 | dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n"); |
41c445ff | 10731 | /* no VEB, so rebuild only the Main VSI */ |
2027d4de | 10732 | ret = i40e_add_vsi(vsi); |
41c445ff JB |
10733 | if (ret) { |
10734 | dev_info(&pf->pdev->dev, | |
10735 | "rebuild of Main VSI failed: %d\n", ret); | |
373149fc | 10736 | goto end_unlock; |
41c445ff JB |
10737 | } |
10738 | } | |
10739 | ||
2027d4de | 10740 | if (vsi->mqprio_qopt.max_rate[0]) { |
6c32e0d9 AB |
10741 | u64 max_tx_rate = vsi->mqprio_qopt.max_rate[0]; |
10742 | u64 credits = 0; | |
2027d4de | 10743 | |
6c32e0d9 | 10744 | do_div(max_tx_rate, I40E_BW_MBPS_DIVISOR); |
2027d4de | 10745 | ret = i40e_set_bw_limit(vsi, vsi->seid, max_tx_rate); |
6c32e0d9 | 10746 | if (ret) |
2027d4de | 10747 | goto end_unlock; |
6c32e0d9 AB |
10748 | |
10749 | credits = max_tx_rate; | |
10750 | do_div(credits, I40E_BW_CREDIT_DIVISOR); | |
10751 | dev_dbg(&vsi->back->pdev->dev, | |
10752 | "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n", | |
10753 | max_tx_rate, | |
10754 | credits, | |
10755 | vsi->seid); | |
2027d4de AN |
10756 | } |
10757 | ||
2f4b411a AN |
10758 | ret = i40e_rebuild_cloud_filters(vsi, vsi->seid); |
10759 | if (ret) | |
10760 | goto end_unlock; | |
10761 | ||
8f88b303 AN |
10762 | /* PF Main VSI is rebuild by now, go ahead and rebuild channel VSIs |
10763 | * for this main VSI if they exist | |
10764 | */ | |
2027d4de | 10765 | ret = i40e_rebuild_channels(vsi); |
8f88b303 AN |
10766 | if (ret) |
10767 | goto end_unlock; | |
10768 | ||
4f2f017c ASJ |
10769 | /* Reconfigure hardware for allowing smaller MSS in the case |
10770 | * of TSO, so that we avoid the MDD being fired and causing | |
10771 | * a reset in the case of small MSS+TSO. | |
10772 | */ | |
10773 | #define I40E_REG_MSS 0x000E64DC | |
10774 | #define I40E_REG_MSS_MIN_MASK 0x3FF0000 | |
10775 | #define I40E_64BYTE_MSS 0x400000 | |
10776 | val = rd32(hw, I40E_REG_MSS); | |
10777 | if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { | |
10778 | val &= ~I40E_REG_MSS_MIN_MASK; | |
10779 | val |= I40E_64BYTE_MSS; | |
10780 | wr32(hw, I40E_REG_MSS, val); | |
10781 | } | |
10782 | ||
d36e41dc | 10783 | if (pf->hw_features & I40E_HW_RESTART_AUTONEG) { |
025b4a54 ASJ |
10784 | msleep(75); |
10785 | ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); | |
10786 | if (ret) | |
f1c7e72e SN |
10787 | dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", |
10788 | i40e_stat_str(&pf->hw, ret), | |
10789 | i40e_aq_str(&pf->hw, | |
10790 | pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 10791 | } |
41c445ff JB |
10792 | /* reinit the misc interrupt */ |
10793 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
10794 | ret = i40e_setup_misc_vector(pf); | |
10795 | ||
e7358f54 ASJ |
10796 | /* Add a filter to drop all Flow control frames from any VSI from being |
10797 | * transmitted. By doing so we stop a malicious VF from sending out | |
10798 | * PAUSE or PFC frames and potentially controlling traffic for other | |
10799 | * PF/VF VSIs. | |
10800 | * The FW can still send Flow control frames if enabled. | |
10801 | */ | |
10802 | i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, | |
10803 | pf->main_vsi_seid); | |
10804 | ||
41c445ff JB |
10805 | /* restart the VSIs that were rebuilt and running before the reset */ |
10806 | i40e_pf_unquiesce_all_vsi(pf); | |
10807 | ||
024b05f4 JK |
10808 | /* Release the RTNL lock before we start resetting VFs */ |
10809 | if (!lock_acquired) | |
10810 | rtnl_unlock(); | |
10811 | ||
bd5608b3 AB |
10812 | /* Restore promiscuous settings */ |
10813 | ret = i40e_set_promiscuous(pf, pf->cur_promisc); | |
10814 | if (ret) | |
10815 | dev_warn(&pf->pdev->dev, | |
10816 | "Failed to restore promiscuous setting: %s, err %s aq_err %s\n", | |
10817 | pf->cur_promisc ? "on" : "off", | |
10818 | i40e_stat_str(&pf->hw, ret), | |
10819 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
10820 | ||
e4b433f4 | 10821 | i40e_reset_all_vfs(pf, true); |
69f64b2b | 10822 | |
41c445ff | 10823 | /* tell the firmware that we're starting */ |
44033fac | 10824 | i40e_send_version(pf); |
41c445ff | 10825 | |
024b05f4 JK |
10826 | /* We've already released the lock, so don't do it again */ |
10827 | goto end_core_reset; | |
10828 | ||
373149fc | 10829 | end_unlock: |
024b05f4 JK |
10830 | if (!lock_acquired) |
10831 | rtnl_unlock(); | |
41c445ff | 10832 | end_core_reset: |
0da36b97 | 10833 | clear_bit(__I40E_RESET_FAILED, pf->state); |
a316f651 | 10834 | clear_recovery: |
0da36b97 | 10835 | clear_bit(__I40E_RESET_RECOVERY_PENDING, pf->state); |
d5585b7b | 10836 | clear_bit(__I40E_TIMEOUT_RECOVERY_PENDING, pf->state); |
41c445ff JB |
10837 | } |
10838 | ||
373149fc MS |
10839 | /** |
10840 | * i40e_reset_and_rebuild - reset and rebuild using a saved config | |
10841 | * @pf: board private structure | |
10842 | * @reinit: if the Main VSI needs to re-initialized. | |
10843 | * @lock_acquired: indicates whether or not the lock has been acquired | |
10844 | * before this function was called. | |
10845 | **/ | |
10846 | static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit, | |
10847 | bool lock_acquired) | |
10848 | { | |
10849 | int ret; | |
10850 | /* Now we wait for GRST to settle out. | |
10851 | * We don't have to delete the VEBs or VSIs from the hw switch | |
10852 | * because the reset will make them disappear. | |
10853 | */ | |
10854 | ret = i40e_reset(pf); | |
10855 | if (!ret) | |
10856 | i40e_rebuild(pf, reinit, lock_acquired); | |
10857 | } | |
10858 | ||
f650a38b | 10859 | /** |
b40c82e6 | 10860 | * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild |
f650a38b ASJ |
10861 | * @pf: board private structure |
10862 | * | |
10863 | * Close up the VFs and other things in prep for a Core Reset, | |
10864 | * then get ready to rebuild the world. | |
373149fc MS |
10865 | * @lock_acquired: indicates whether or not the lock has been acquired |
10866 | * before this function was called. | |
f650a38b | 10867 | **/ |
373149fc | 10868 | static void i40e_handle_reset_warning(struct i40e_pf *pf, bool lock_acquired) |
f650a38b | 10869 | { |
4b208eaa | 10870 | i40e_prep_for_reset(pf); |
373149fc | 10871 | i40e_reset_and_rebuild(pf, false, lock_acquired); |
f650a38b ASJ |
10872 | } |
10873 | ||
41c445ff JB |
10874 | /** |
10875 | * i40e_handle_mdd_event | |
b40c82e6 | 10876 | * @pf: pointer to the PF structure |
41c445ff JB |
10877 | * |
10878 | * Called from the MDD irq handler to identify possibly malicious vfs | |
10879 | **/ | |
10880 | static void i40e_handle_mdd_event(struct i40e_pf *pf) | |
10881 | { | |
10882 | struct i40e_hw *hw = &pf->hw; | |
10883 | bool mdd_detected = false; | |
10884 | struct i40e_vf *vf; | |
10885 | u32 reg; | |
10886 | int i; | |
10887 | ||
0da36b97 | 10888 | if (!test_bit(__I40E_MDD_EVENT_PENDING, pf->state)) |
41c445ff JB |
10889 | return; |
10890 | ||
10891 | /* find what triggered the MDD event */ | |
10892 | reg = rd32(hw, I40E_GL_MDET_TX); | |
10893 | if (reg & I40E_GL_MDET_TX_VALID_MASK) { | |
4c33f83a ASJ |
10894 | u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> |
10895 | I40E_GL_MDET_TX_PF_NUM_SHIFT; | |
2089ad03 | 10896 | u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >> |
4c33f83a | 10897 | I40E_GL_MDET_TX_VF_NUM_SHIFT; |
013f6579 | 10898 | u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> |
4c33f83a | 10899 | I40E_GL_MDET_TX_EVENT_SHIFT; |
2089ad03 MW |
10900 | u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >> |
10901 | I40E_GL_MDET_TX_QUEUE_SHIFT) - | |
10902 | pf->hw.func_caps.base_queue; | |
faf32978 | 10903 | if (netif_msg_tx_err(pf)) |
b40c82e6 | 10904 | dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n", |
faf32978 | 10905 | event, queue, pf_num, vf_num); |
41c445ff JB |
10906 | wr32(hw, I40E_GL_MDET_TX, 0xffffffff); |
10907 | mdd_detected = true; | |
10908 | } | |
10909 | reg = rd32(hw, I40E_GL_MDET_RX); | |
10910 | if (reg & I40E_GL_MDET_RX_VALID_MASK) { | |
4c33f83a ASJ |
10911 | u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> |
10912 | I40E_GL_MDET_RX_FUNCTION_SHIFT; | |
013f6579 | 10913 | u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> |
4c33f83a | 10914 | I40E_GL_MDET_RX_EVENT_SHIFT; |
2089ad03 MW |
10915 | u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >> |
10916 | I40E_GL_MDET_RX_QUEUE_SHIFT) - | |
10917 | pf->hw.func_caps.base_queue; | |
faf32978 JB |
10918 | if (netif_msg_rx_err(pf)) |
10919 | dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n", | |
10920 | event, queue, func); | |
41c445ff JB |
10921 | wr32(hw, I40E_GL_MDET_RX, 0xffffffff); |
10922 | mdd_detected = true; | |
10923 | } | |
10924 | ||
df430b12 NP |
10925 | if (mdd_detected) { |
10926 | reg = rd32(hw, I40E_PF_MDET_TX); | |
10927 | if (reg & I40E_PF_MDET_TX_VALID_MASK) { | |
10928 | wr32(hw, I40E_PF_MDET_TX, 0xFFFF); | |
a1df906c | 10929 | dev_dbg(&pf->pdev->dev, "TX driver issue detected on PF\n"); |
df430b12 NP |
10930 | } |
10931 | reg = rd32(hw, I40E_PF_MDET_RX); | |
10932 | if (reg & I40E_PF_MDET_RX_VALID_MASK) { | |
10933 | wr32(hw, I40E_PF_MDET_RX, 0xFFFF); | |
a1df906c | 10934 | dev_dbg(&pf->pdev->dev, "RX driver issue detected on PF\n"); |
df430b12 NP |
10935 | } |
10936 | } | |
10937 | ||
41c445ff JB |
10938 | /* see if one of the VFs needs its hand slapped */ |
10939 | for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) { | |
10940 | vf = &(pf->vf[i]); | |
10941 | reg = rd32(hw, I40E_VP_MDET_TX(i)); | |
10942 | if (reg & I40E_VP_MDET_TX_VALID_MASK) { | |
10943 | wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF); | |
10944 | vf->num_mdd_events++; | |
faf32978 JB |
10945 | dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n", |
10946 | i); | |
a7da7f16 CW |
10947 | dev_info(&pf->pdev->dev, |
10948 | "Use PF Control I/F to re-enable the VF\n"); | |
10949 | set_bit(I40E_VF_STATE_DISABLED, &vf->vf_states); | |
41c445ff JB |
10950 | } |
10951 | ||
10952 | reg = rd32(hw, I40E_VP_MDET_RX(i)); | |
10953 | if (reg & I40E_VP_MDET_RX_VALID_MASK) { | |
10954 | wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF); | |
10955 | vf->num_mdd_events++; | |
faf32978 JB |
10956 | dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n", |
10957 | i); | |
41c445ff JB |
10958 | dev_info(&pf->pdev->dev, |
10959 | "Use PF Control I/F to re-enable the VF\n"); | |
6322e63c | 10960 | set_bit(I40E_VF_STATE_DISABLED, &vf->vf_states); |
41c445ff JB |
10961 | } |
10962 | } | |
10963 | ||
10964 | /* re-enable mdd interrupt cause */ | |
0da36b97 | 10965 | clear_bit(__I40E_MDD_EVENT_PENDING, pf->state); |
41c445ff JB |
10966 | reg = rd32(hw, I40E_PFINT_ICR0_ENA); |
10967 | reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; | |
10968 | wr32(hw, I40E_PFINT_ICR0_ENA, reg); | |
10969 | i40e_flush(hw); | |
10970 | } | |
10971 | ||
10972 | /** | |
10973 | * i40e_service_task - Run the driver's async subtasks | |
10974 | * @work: pointer to work_struct containing our data | |
10975 | **/ | |
10976 | static void i40e_service_task(struct work_struct *work) | |
10977 | { | |
10978 | struct i40e_pf *pf = container_of(work, | |
10979 | struct i40e_pf, | |
10980 | service_task); | |
10981 | unsigned long start_time = jiffies; | |
10982 | ||
e57a2fea | 10983 | /* don't bother with service tasks if a reset is in progress */ |
4ff0ee1a AM |
10984 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) || |
10985 | test_bit(__I40E_SUSPENDED, pf->state)) | |
e57a2fea | 10986 | return; |
e57a2fea | 10987 | |
0da36b97 | 10988 | if (test_and_set_bit(__I40E_SERVICE_SCHED, pf->state)) |
91089033 MW |
10989 | return; |
10990 | ||
4ff0ee1a AM |
10991 | if (!test_bit(__I40E_RECOVERY_MODE, pf->state)) { |
10992 | i40e_detect_recover_hung(pf->vsi[pf->lan_vsi]); | |
10993 | i40e_sync_filters_subtask(pf); | |
10994 | i40e_reset_subtask(pf); | |
10995 | i40e_handle_mdd_event(pf); | |
10996 | i40e_vc_process_vflr_event(pf); | |
10997 | i40e_watchdog_subtask(pf); | |
10998 | i40e_fdir_reinit_subtask(pf); | |
10999 | if (test_and_clear_bit(__I40E_CLIENT_RESET, pf->state)) { | |
11000 | /* Client subtask will reopen next time through. */ | |
11001 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], | |
11002 | true); | |
11003 | } else { | |
11004 | i40e_client_subtask(pf); | |
11005 | if (test_and_clear_bit(__I40E_CLIENT_L2_CHANGE, | |
11006 | pf->state)) | |
11007 | i40e_notify_client_of_l2_param_changes( | |
11008 | pf->vsi[pf->lan_vsi]); | |
11009 | } | |
11010 | i40e_sync_filters_subtask(pf); | |
0ef2d5af | 11011 | } else { |
4ff0ee1a AM |
11012 | i40e_reset_subtask(pf); |
11013 | } | |
11014 | ||
41c445ff JB |
11015 | i40e_clean_adminq_subtask(pf); |
11016 | ||
91089033 MW |
11017 | /* flush memory to make sure state is correct before next watchdog */ |
11018 | smp_mb__before_atomic(); | |
0da36b97 | 11019 | clear_bit(__I40E_SERVICE_SCHED, pf->state); |
41c445ff JB |
11020 | |
11021 | /* If the tasks have taken longer than one timer cycle or there | |
11022 | * is more work to be done, reschedule the service task now | |
11023 | * rather than wait for the timer to tick again. | |
11024 | */ | |
11025 | if (time_after(jiffies, (start_time + pf->service_timer_period)) || | |
0da36b97 JK |
11026 | test_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state) || |
11027 | test_bit(__I40E_MDD_EVENT_PENDING, pf->state) || | |
11028 | test_bit(__I40E_VFLR_EVENT_PENDING, pf->state)) | |
41c445ff JB |
11029 | i40e_service_event_schedule(pf); |
11030 | } | |
11031 | ||
11032 | /** | |
11033 | * i40e_service_timer - timer callback | |
b50f7bca | 11034 | * @t: timer list pointer |
41c445ff | 11035 | **/ |
26566eae | 11036 | static void i40e_service_timer(struct timer_list *t) |
41c445ff | 11037 | { |
26566eae | 11038 | struct i40e_pf *pf = from_timer(pf, t, service_timer); |
41c445ff JB |
11039 | |
11040 | mod_timer(&pf->service_timer, | |
11041 | round_jiffies(jiffies + pf->service_timer_period)); | |
11042 | i40e_service_event_schedule(pf); | |
11043 | } | |
11044 | ||
11045 | /** | |
11046 | * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI | |
11047 | * @vsi: the VSI being configured | |
11048 | **/ | |
11049 | static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi) | |
11050 | { | |
11051 | struct i40e_pf *pf = vsi->back; | |
11052 | ||
11053 | switch (vsi->type) { | |
11054 | case I40E_VSI_MAIN: | |
11055 | vsi->alloc_queue_pairs = pf->num_lan_qps; | |
15369ac3 MF |
11056 | if (!vsi->num_tx_desc) |
11057 | vsi->num_tx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
11058 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
11059 | if (!vsi->num_rx_desc) | |
11060 | vsi->num_rx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
11061 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
41c445ff JB |
11062 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) |
11063 | vsi->num_q_vectors = pf->num_lan_msix; | |
11064 | else | |
11065 | vsi->num_q_vectors = 1; | |
11066 | ||
11067 | break; | |
11068 | ||
11069 | case I40E_VSI_FDIR: | |
11070 | vsi->alloc_queue_pairs = 1; | |
15369ac3 MF |
11071 | vsi->num_tx_desc = ALIGN(I40E_FDIR_RING_COUNT, |
11072 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
11073 | vsi->num_rx_desc = ALIGN(I40E_FDIR_RING_COUNT, | |
11074 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
a70e407f | 11075 | vsi->num_q_vectors = pf->num_fdsb_msix; |
41c445ff JB |
11076 | break; |
11077 | ||
11078 | case I40E_VSI_VMDQ2: | |
11079 | vsi->alloc_queue_pairs = pf->num_vmdq_qps; | |
15369ac3 MF |
11080 | if (!vsi->num_tx_desc) |
11081 | vsi->num_tx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
11082 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
11083 | if (!vsi->num_rx_desc) | |
11084 | vsi->num_rx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
11085 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
41c445ff JB |
11086 | vsi->num_q_vectors = pf->num_vmdq_msix; |
11087 | break; | |
11088 | ||
11089 | case I40E_VSI_SRIOV: | |
11090 | vsi->alloc_queue_pairs = pf->num_vf_qps; | |
15369ac3 MF |
11091 | if (!vsi->num_tx_desc) |
11092 | vsi->num_tx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
11093 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
11094 | if (!vsi->num_rx_desc) | |
11095 | vsi->num_rx_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
11096 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
41c445ff JB |
11097 | break; |
11098 | ||
11099 | default: | |
11100 | WARN_ON(1); | |
11101 | return -ENODATA; | |
11102 | } | |
11103 | ||
dcb75338 CX |
11104 | if (is_kdump_kernel()) { |
11105 | vsi->num_tx_desc = I40E_MIN_NUM_DESCRIPTORS; | |
11106 | vsi->num_rx_desc = I40E_MIN_NUM_DESCRIPTORS; | |
11107 | } | |
11108 | ||
41c445ff JB |
11109 | return 0; |
11110 | } | |
11111 | ||
f650a38b ASJ |
11112 | /** |
11113 | * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi | |
3d7d7a86 | 11114 | * @vsi: VSI pointer |
bc7d338f | 11115 | * @alloc_qvectors: a bool to specify if q_vectors need to be allocated. |
f650a38b ASJ |
11116 | * |
11117 | * On error: returns error code (negative) | |
11118 | * On success: returns 0 | |
11119 | **/ | |
bc7d338f | 11120 | static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors) |
f650a38b | 11121 | { |
74608d17 | 11122 | struct i40e_ring **next_rings; |
f650a38b ASJ |
11123 | int size; |
11124 | int ret = 0; | |
11125 | ||
74608d17 BT |
11126 | /* allocate memory for both Tx, XDP Tx and Rx ring pointers */ |
11127 | size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * | |
11128 | (i40e_enabled_xdp_vsi(vsi) ? 3 : 2); | |
f650a38b ASJ |
11129 | vsi->tx_rings = kzalloc(size, GFP_KERNEL); |
11130 | if (!vsi->tx_rings) | |
11131 | return -ENOMEM; | |
74608d17 BT |
11132 | next_rings = vsi->tx_rings + vsi->alloc_queue_pairs; |
11133 | if (i40e_enabled_xdp_vsi(vsi)) { | |
11134 | vsi->xdp_rings = next_rings; | |
11135 | next_rings += vsi->alloc_queue_pairs; | |
11136 | } | |
11137 | vsi->rx_rings = next_rings; | |
f650a38b | 11138 | |
bc7d338f ASJ |
11139 | if (alloc_qvectors) { |
11140 | /* allocate memory for q_vector pointers */ | |
f57e4fbd | 11141 | size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors; |
bc7d338f ASJ |
11142 | vsi->q_vectors = kzalloc(size, GFP_KERNEL); |
11143 | if (!vsi->q_vectors) { | |
11144 | ret = -ENOMEM; | |
11145 | goto err_vectors; | |
11146 | } | |
f650a38b ASJ |
11147 | } |
11148 | return ret; | |
11149 | ||
11150 | err_vectors: | |
11151 | kfree(vsi->tx_rings); | |
11152 | return ret; | |
11153 | } | |
11154 | ||
41c445ff JB |
11155 | /** |
11156 | * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF | |
11157 | * @pf: board private structure | |
11158 | * @type: type of VSI | |
11159 | * | |
11160 | * On error: returns error code (negative) | |
11161 | * On success: returns vsi index in PF (positive) | |
11162 | **/ | |
11163 | static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type) | |
11164 | { | |
11165 | int ret = -ENODEV; | |
11166 | struct i40e_vsi *vsi; | |
11167 | int vsi_idx; | |
11168 | int i; | |
11169 | ||
11170 | /* Need to protect the allocation of the VSIs at the PF level */ | |
11171 | mutex_lock(&pf->switch_mutex); | |
11172 | ||
11173 | /* VSI list may be fragmented if VSI creation/destruction has | |
11174 | * been happening. We can afford to do a quick scan to look | |
11175 | * for any free VSIs in the list. | |
11176 | * | |
11177 | * find next empty vsi slot, looping back around if necessary | |
11178 | */ | |
11179 | i = pf->next_vsi; | |
505682cd | 11180 | while (i < pf->num_alloc_vsi && pf->vsi[i]) |
41c445ff | 11181 | i++; |
505682cd | 11182 | if (i >= pf->num_alloc_vsi) { |
41c445ff JB |
11183 | i = 0; |
11184 | while (i < pf->next_vsi && pf->vsi[i]) | |
11185 | i++; | |
11186 | } | |
11187 | ||
505682cd | 11188 | if (i < pf->num_alloc_vsi && !pf->vsi[i]) { |
41c445ff JB |
11189 | vsi_idx = i; /* Found one! */ |
11190 | } else { | |
11191 | ret = -ENODEV; | |
493fb300 | 11192 | goto unlock_pf; /* out of VSI slots! */ |
41c445ff JB |
11193 | } |
11194 | pf->next_vsi = ++i; | |
11195 | ||
11196 | vsi = kzalloc(sizeof(*vsi), GFP_KERNEL); | |
11197 | if (!vsi) { | |
11198 | ret = -ENOMEM; | |
493fb300 | 11199 | goto unlock_pf; |
41c445ff JB |
11200 | } |
11201 | vsi->type = type; | |
11202 | vsi->back = pf; | |
0da36b97 | 11203 | set_bit(__I40E_VSI_DOWN, vsi->state); |
41c445ff JB |
11204 | vsi->flags = 0; |
11205 | vsi->idx = vsi_idx; | |
ac26fc13 | 11206 | vsi->int_rate_limit = 0; |
5db4cb59 ASJ |
11207 | vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ? |
11208 | pf->rss_table_size : 64; | |
41c445ff JB |
11209 | vsi->netdev_registered = false; |
11210 | vsi->work_limit = I40E_DEFAULT_IRQ_WORK; | |
278e7d0b | 11211 | hash_init(vsi->mac_filter_hash); |
63741846 | 11212 | vsi->irqs_ready = false; |
41c445ff | 11213 | |
44ddd4f1 BT |
11214 | if (type == I40E_VSI_MAIN) { |
11215 | vsi->af_xdp_zc_qps = bitmap_zalloc(pf->num_lan_qps, GFP_KERNEL); | |
11216 | if (!vsi->af_xdp_zc_qps) | |
11217 | goto err_rings; | |
11218 | } | |
11219 | ||
9f65e15b AD |
11220 | ret = i40e_set_num_rings_in_vsi(vsi); |
11221 | if (ret) | |
11222 | goto err_rings; | |
11223 | ||
bc7d338f | 11224 | ret = i40e_vsi_alloc_arrays(vsi, true); |
f650a38b | 11225 | if (ret) |
9f65e15b | 11226 | goto err_rings; |
493fb300 | 11227 | |
41c445ff JB |
11228 | /* Setup default MSIX irq handler for VSI */ |
11229 | i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings); | |
11230 | ||
21659035 | 11231 | /* Initialize VSI lock */ |
278e7d0b | 11232 | spin_lock_init(&vsi->mac_filter_hash_lock); |
41c445ff JB |
11233 | pf->vsi[vsi_idx] = vsi; |
11234 | ret = vsi_idx; | |
493fb300 AD |
11235 | goto unlock_pf; |
11236 | ||
9f65e15b | 11237 | err_rings: |
44ddd4f1 | 11238 | bitmap_free(vsi->af_xdp_zc_qps); |
493fb300 AD |
11239 | pf->next_vsi = i - 1; |
11240 | kfree(vsi); | |
11241 | unlock_pf: | |
41c445ff JB |
11242 | mutex_unlock(&pf->switch_mutex); |
11243 | return ret; | |
11244 | } | |
11245 | ||
f650a38b ASJ |
11246 | /** |
11247 | * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI | |
f5254429 | 11248 | * @vsi: VSI pointer |
bc7d338f | 11249 | * @free_qvectors: a bool to specify if q_vectors need to be freed. |
f650a38b ASJ |
11250 | * |
11251 | * On error: returns error code (negative) | |
11252 | * On success: returns 0 | |
11253 | **/ | |
bc7d338f | 11254 | static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors) |
f650a38b ASJ |
11255 | { |
11256 | /* free the ring and vector containers */ | |
bc7d338f ASJ |
11257 | if (free_qvectors) { |
11258 | kfree(vsi->q_vectors); | |
11259 | vsi->q_vectors = NULL; | |
11260 | } | |
f650a38b ASJ |
11261 | kfree(vsi->tx_rings); |
11262 | vsi->tx_rings = NULL; | |
11263 | vsi->rx_rings = NULL; | |
74608d17 | 11264 | vsi->xdp_rings = NULL; |
f650a38b ASJ |
11265 | } |
11266 | ||
28c5869f HZ |
11267 | /** |
11268 | * i40e_clear_rss_config_user - clear the user configured RSS hash keys | |
11269 | * and lookup table | |
11270 | * @vsi: Pointer to VSI structure | |
11271 | */ | |
11272 | static void i40e_clear_rss_config_user(struct i40e_vsi *vsi) | |
11273 | { | |
11274 | if (!vsi) | |
11275 | return; | |
11276 | ||
11277 | kfree(vsi->rss_hkey_user); | |
11278 | vsi->rss_hkey_user = NULL; | |
11279 | ||
11280 | kfree(vsi->rss_lut_user); | |
11281 | vsi->rss_lut_user = NULL; | |
11282 | } | |
11283 | ||
41c445ff JB |
11284 | /** |
11285 | * i40e_vsi_clear - Deallocate the VSI provided | |
11286 | * @vsi: the VSI being un-configured | |
11287 | **/ | |
11288 | static int i40e_vsi_clear(struct i40e_vsi *vsi) | |
11289 | { | |
11290 | struct i40e_pf *pf; | |
11291 | ||
11292 | if (!vsi) | |
11293 | return 0; | |
11294 | ||
11295 | if (!vsi->back) | |
11296 | goto free_vsi; | |
11297 | pf = vsi->back; | |
11298 | ||
11299 | mutex_lock(&pf->switch_mutex); | |
11300 | if (!pf->vsi[vsi->idx]) { | |
7be78aa4 MW |
11301 | dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](type %d)\n", |
11302 | vsi->idx, vsi->idx, vsi->type); | |
41c445ff JB |
11303 | goto unlock_vsi; |
11304 | } | |
11305 | ||
11306 | if (pf->vsi[vsi->idx] != vsi) { | |
11307 | dev_err(&pf->pdev->dev, | |
7be78aa4 | 11308 | "pf->vsi[%d](type %d) != vsi[%d](type %d): no free!\n", |
41c445ff | 11309 | pf->vsi[vsi->idx]->idx, |
41c445ff | 11310 | pf->vsi[vsi->idx]->type, |
7be78aa4 | 11311 | vsi->idx, vsi->type); |
41c445ff JB |
11312 | goto unlock_vsi; |
11313 | } | |
11314 | ||
b40c82e6 | 11315 | /* updates the PF for this cleared vsi */ |
41c445ff JB |
11316 | i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); |
11317 | i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx); | |
11318 | ||
44ddd4f1 | 11319 | bitmap_free(vsi->af_xdp_zc_qps); |
bc7d338f | 11320 | i40e_vsi_free_arrays(vsi, true); |
28c5869f | 11321 | i40e_clear_rss_config_user(vsi); |
493fb300 | 11322 | |
41c445ff JB |
11323 | pf->vsi[vsi->idx] = NULL; |
11324 | if (vsi->idx < pf->next_vsi) | |
11325 | pf->next_vsi = vsi->idx; | |
11326 | ||
11327 | unlock_vsi: | |
11328 | mutex_unlock(&pf->switch_mutex); | |
11329 | free_vsi: | |
11330 | kfree(vsi); | |
11331 | ||
11332 | return 0; | |
11333 | } | |
11334 | ||
9f65e15b AD |
11335 | /** |
11336 | * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI | |
11337 | * @vsi: the VSI being cleaned | |
11338 | **/ | |
be1d5eea | 11339 | static void i40e_vsi_clear_rings(struct i40e_vsi *vsi) |
9f65e15b AD |
11340 | { |
11341 | int i; | |
11342 | ||
8e9dca53 | 11343 | if (vsi->tx_rings && vsi->tx_rings[0]) { |
d7397644 | 11344 | for (i = 0; i < vsi->alloc_queue_pairs; i++) { |
00403f04 | 11345 | kfree_rcu(vsi->tx_rings[i], rcu); |
d59e2679 CL |
11346 | WRITE_ONCE(vsi->tx_rings[i], NULL); |
11347 | WRITE_ONCE(vsi->rx_rings[i], NULL); | |
74608d17 | 11348 | if (vsi->xdp_rings) |
d59e2679 | 11349 | WRITE_ONCE(vsi->xdp_rings[i], NULL); |
00403f04 | 11350 | } |
be1d5eea | 11351 | } |
9f65e15b AD |
11352 | } |
11353 | ||
41c445ff JB |
11354 | /** |
11355 | * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI | |
11356 | * @vsi: the VSI being configured | |
11357 | **/ | |
11358 | static int i40e_alloc_rings(struct i40e_vsi *vsi) | |
11359 | { | |
74608d17 | 11360 | int i, qpv = i40e_enabled_xdp_vsi(vsi) ? 3 : 2; |
41c445ff | 11361 | struct i40e_pf *pf = vsi->back; |
74608d17 | 11362 | struct i40e_ring *ring; |
41c445ff | 11363 | |
41c445ff | 11364 | /* Set basic values in the rings to be used later during open() */ |
d7397644 | 11365 | for (i = 0; i < vsi->alloc_queue_pairs; i++) { |
ac6c5e3d | 11366 | /* allocate space for both Tx and Rx in one shot */ |
74608d17 BT |
11367 | ring = kcalloc(qpv, sizeof(struct i40e_ring), GFP_KERNEL); |
11368 | if (!ring) | |
9f65e15b | 11369 | goto err_out; |
41c445ff | 11370 | |
74608d17 BT |
11371 | ring->queue_index = i; |
11372 | ring->reg_idx = vsi->base_queue + i; | |
11373 | ring->ring_active = false; | |
11374 | ring->vsi = vsi; | |
11375 | ring->netdev = vsi->netdev; | |
11376 | ring->dev = &pf->pdev->dev; | |
15369ac3 | 11377 | ring->count = vsi->num_tx_desc; |
74608d17 BT |
11378 | ring->size = 0; |
11379 | ring->dcb_tc = 0; | |
d36e41dc | 11380 | if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE) |
74608d17 | 11381 | ring->flags = I40E_TXR_FLAGS_WB_ON_ITR; |
40588ca6 | 11382 | ring->itr_setting = pf->tx_itr_default; |
d59e2679 | 11383 | WRITE_ONCE(vsi->tx_rings[i], ring++); |
74608d17 BT |
11384 | |
11385 | if (!i40e_enabled_xdp_vsi(vsi)) | |
11386 | goto setup_rx; | |
11387 | ||
11388 | ring->queue_index = vsi->alloc_queue_pairs + i; | |
11389 | ring->reg_idx = vsi->base_queue + ring->queue_index; | |
11390 | ring->ring_active = false; | |
11391 | ring->vsi = vsi; | |
11392 | ring->netdev = NULL; | |
11393 | ring->dev = &pf->pdev->dev; | |
15369ac3 | 11394 | ring->count = vsi->num_tx_desc; |
74608d17 BT |
11395 | ring->size = 0; |
11396 | ring->dcb_tc = 0; | |
d36e41dc | 11397 | if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE) |
74608d17 BT |
11398 | ring->flags = I40E_TXR_FLAGS_WB_ON_ITR; |
11399 | set_ring_xdp(ring); | |
40588ca6 | 11400 | ring->itr_setting = pf->tx_itr_default; |
d59e2679 | 11401 | WRITE_ONCE(vsi->xdp_rings[i], ring++); |
74608d17 BT |
11402 | |
11403 | setup_rx: | |
11404 | ring->queue_index = i; | |
11405 | ring->reg_idx = vsi->base_queue + i; | |
11406 | ring->ring_active = false; | |
11407 | ring->vsi = vsi; | |
11408 | ring->netdev = vsi->netdev; | |
11409 | ring->dev = &pf->pdev->dev; | |
15369ac3 | 11410 | ring->count = vsi->num_rx_desc; |
74608d17 BT |
11411 | ring->size = 0; |
11412 | ring->dcb_tc = 0; | |
40588ca6 | 11413 | ring->itr_setting = pf->rx_itr_default; |
d59e2679 | 11414 | WRITE_ONCE(vsi->rx_rings[i], ring); |
41c445ff JB |
11415 | } |
11416 | ||
11417 | return 0; | |
9f65e15b AD |
11418 | |
11419 | err_out: | |
11420 | i40e_vsi_clear_rings(vsi); | |
11421 | return -ENOMEM; | |
41c445ff JB |
11422 | } |
11423 | ||
11424 | /** | |
11425 | * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel | |
11426 | * @pf: board private structure | |
11427 | * @vectors: the number of MSI-X vectors to request | |
11428 | * | |
11429 | * Returns the number of vectors reserved, or error | |
11430 | **/ | |
11431 | static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors) | |
11432 | { | |
7b37f376 AG |
11433 | vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries, |
11434 | I40E_MIN_MSIX, vectors); | |
11435 | if (vectors < 0) { | |
41c445ff | 11436 | dev_info(&pf->pdev->dev, |
7b37f376 | 11437 | "MSI-X vector reservation failed: %d\n", vectors); |
41c445ff JB |
11438 | vectors = 0; |
11439 | } | |
11440 | ||
11441 | return vectors; | |
11442 | } | |
11443 | ||
11444 | /** | |
11445 | * i40e_init_msix - Setup the MSIX capability | |
11446 | * @pf: board private structure | |
11447 | * | |
11448 | * Work with the OS to set up the MSIX vectors needed. | |
11449 | * | |
3b444399 | 11450 | * Returns the number of vectors reserved or negative on failure |
41c445ff JB |
11451 | **/ |
11452 | static int i40e_init_msix(struct i40e_pf *pf) | |
11453 | { | |
41c445ff | 11454 | struct i40e_hw *hw = &pf->hw; |
c0cf70a6 | 11455 | int cpus, extra_vectors; |
1e200e4a | 11456 | int vectors_left; |
41c445ff | 11457 | int v_budget, i; |
3b444399 | 11458 | int v_actual; |
e3219ce6 | 11459 | int iwarp_requested = 0; |
41c445ff JB |
11460 | |
11461 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
11462 | return -ENODEV; | |
11463 | ||
11464 | /* The number of vectors we'll request will be comprised of: | |
11465 | * - Add 1 for "other" cause for Admin Queue events, etc. | |
11466 | * - The number of LAN queue pairs | |
f8ff1464 ASJ |
11467 | * - Queues being used for RSS. |
11468 | * We don't need as many as max_rss_size vectors. | |
11469 | * use rss_size instead in the calculation since that | |
11470 | * is governed by number of cpus in the system. | |
11471 | * - assumes symmetric Tx/Rx pairing | |
41c445ff | 11472 | * - The number of VMDq pairs |
e3219ce6 | 11473 | * - The CPU count within the NUMA node if iWARP is enabled |
41c445ff JB |
11474 | * Once we count this up, try the request. |
11475 | * | |
11476 | * If we can't get what we want, we'll simplify to nearly nothing | |
11477 | * and try again. If that still fails, we punt. | |
11478 | */ | |
1e200e4a SN |
11479 | vectors_left = hw->func_caps.num_msix_vectors; |
11480 | v_budget = 0; | |
11481 | ||
11482 | /* reserve one vector for miscellaneous handler */ | |
11483 | if (vectors_left) { | |
11484 | v_budget++; | |
11485 | vectors_left--; | |
11486 | } | |
11487 | ||
c0cf70a6 JK |
11488 | /* reserve some vectors for the main PF traffic queues. Initially we |
11489 | * only reserve at most 50% of the available vectors, in the case that | |
11490 | * the number of online CPUs is large. This ensures that we can enable | |
11491 | * extra features as well. Once we've enabled the other features, we | |
11492 | * will use any remaining vectors to reach as close as we can to the | |
11493 | * number of online CPUs. | |
11494 | */ | |
11495 | cpus = num_online_cpus(); | |
11496 | pf->num_lan_msix = min_t(int, cpus, vectors_left / 2); | |
1e200e4a | 11497 | vectors_left -= pf->num_lan_msix; |
1e200e4a SN |
11498 | |
11499 | /* reserve one vector for sideband flow director */ | |
11500 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
11501 | if (vectors_left) { | |
a70e407f | 11502 | pf->num_fdsb_msix = 1; |
1e200e4a SN |
11503 | v_budget++; |
11504 | vectors_left--; | |
11505 | } else { | |
a70e407f | 11506 | pf->num_fdsb_msix = 0; |
1e200e4a SN |
11507 | } |
11508 | } | |
83840e4b | 11509 | |
e3219ce6 ASJ |
11510 | /* can we reserve enough for iWARP? */ |
11511 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { | |
4ce20abc SA |
11512 | iwarp_requested = pf->num_iwarp_msix; |
11513 | ||
e3219ce6 ASJ |
11514 | if (!vectors_left) |
11515 | pf->num_iwarp_msix = 0; | |
11516 | else if (vectors_left < pf->num_iwarp_msix) | |
11517 | pf->num_iwarp_msix = 1; | |
11518 | v_budget += pf->num_iwarp_msix; | |
11519 | vectors_left -= pf->num_iwarp_msix; | |
11520 | } | |
11521 | ||
1e200e4a SN |
11522 | /* any vectors left over go for VMDq support */ |
11523 | if (pf->flags & I40E_FLAG_VMDQ_ENABLED) { | |
9ca57e97 SA |
11524 | if (!vectors_left) { |
11525 | pf->num_vmdq_msix = 0; | |
11526 | pf->num_vmdq_qps = 0; | |
11527 | } else { | |
ca12c9d4 PM |
11528 | int vmdq_vecs_wanted = |
11529 | pf->num_vmdq_vsis * pf->num_vmdq_qps; | |
11530 | int vmdq_vecs = | |
11531 | min_t(int, vectors_left, vmdq_vecs_wanted); | |
11532 | ||
9ca57e97 SA |
11533 | /* if we're short on vectors for what's desired, we limit |
11534 | * the queues per vmdq. If this is still more than are | |
11535 | * available, the user will need to change the number of | |
11536 | * queues/vectors used by the PF later with the ethtool | |
11537 | * channels command | |
11538 | */ | |
ca12c9d4 | 11539 | if (vectors_left < vmdq_vecs_wanted) { |
9ca57e97 | 11540 | pf->num_vmdq_qps = 1; |
ca12c9d4 PM |
11541 | vmdq_vecs_wanted = pf->num_vmdq_vsis; |
11542 | vmdq_vecs = min_t(int, | |
11543 | vectors_left, | |
11544 | vmdq_vecs_wanted); | |
11545 | } | |
9ca57e97 | 11546 | pf->num_vmdq_msix = pf->num_vmdq_qps; |
1e200e4a | 11547 | |
9ca57e97 SA |
11548 | v_budget += vmdq_vecs; |
11549 | vectors_left -= vmdq_vecs; | |
11550 | } | |
1e200e4a | 11551 | } |
41c445ff | 11552 | |
c0cf70a6 JK |
11553 | /* On systems with a large number of SMP cores, we previously limited |
11554 | * the number of vectors for num_lan_msix to be at most 50% of the | |
11555 | * available vectors, to allow for other features. Now, we add back | |
11556 | * the remaining vectors. However, we ensure that the total | |
11557 | * num_lan_msix will not exceed num_online_cpus(). To do this, we | |
11558 | * calculate the number of vectors we can add without going over the | |
11559 | * cap of CPUs. For systems with a small number of CPUs this will be | |
11560 | * zero. | |
11561 | */ | |
11562 | extra_vectors = min_t(int, cpus - pf->num_lan_msix, vectors_left); | |
11563 | pf->num_lan_msix += extra_vectors; | |
11564 | vectors_left -= extra_vectors; | |
11565 | ||
11566 | WARN(vectors_left < 0, | |
11567 | "Calculation of remaining vectors underflowed. This is an accounting bug when determining total MSI-X vectors.\n"); | |
11568 | ||
11569 | v_budget += pf->num_lan_msix; | |
41c445ff JB |
11570 | pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry), |
11571 | GFP_KERNEL); | |
11572 | if (!pf->msix_entries) | |
11573 | return -ENOMEM; | |
11574 | ||
11575 | for (i = 0; i < v_budget; i++) | |
11576 | pf->msix_entries[i].entry = i; | |
3b444399 | 11577 | v_actual = i40e_reserve_msix_vectors(pf, v_budget); |
a34977ba | 11578 | |
3b444399 | 11579 | if (v_actual < I40E_MIN_MSIX) { |
41c445ff JB |
11580 | pf->flags &= ~I40E_FLAG_MSIX_ENABLED; |
11581 | kfree(pf->msix_entries); | |
11582 | pf->msix_entries = NULL; | |
4c95aa5d | 11583 | pci_disable_msix(pf->pdev); |
41c445ff JB |
11584 | return -ENODEV; |
11585 | ||
3b444399 | 11586 | } else if (v_actual == I40E_MIN_MSIX) { |
41c445ff | 11587 | /* Adjust for minimal MSIX use */ |
41c445ff JB |
11588 | pf->num_vmdq_vsis = 0; |
11589 | pf->num_vmdq_qps = 0; | |
41c445ff JB |
11590 | pf->num_lan_qps = 1; |
11591 | pf->num_lan_msix = 1; | |
11592 | ||
3e6b1cf7 | 11593 | } else if (v_actual != v_budget) { |
4ce20abc SA |
11594 | /* If we have limited resources, we will start with no vectors |
11595 | * for the special features and then allocate vectors to some | |
11596 | * of these features based on the policy and at the end disable | |
11597 | * the features that did not get any vectors. | |
11598 | */ | |
3b444399 SN |
11599 | int vec; |
11600 | ||
4ce20abc | 11601 | dev_info(&pf->pdev->dev, |
3e6b1cf7 SN |
11602 | "MSI-X vector limit reached with %d, wanted %d, attempting to redistribute vectors\n", |
11603 | v_actual, v_budget); | |
a34977ba | 11604 | /* reserve the misc vector */ |
3b444399 | 11605 | vec = v_actual - 1; |
a34977ba | 11606 | |
41c445ff JB |
11607 | /* Scale vector usage down */ |
11608 | pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */ | |
a34977ba | 11609 | pf->num_vmdq_vsis = 1; |
1e200e4a | 11610 | pf->num_vmdq_qps = 1; |
41c445ff JB |
11611 | |
11612 | /* partition out the remaining vectors */ | |
11613 | switch (vec) { | |
11614 | case 2: | |
41c445ff JB |
11615 | pf->num_lan_msix = 1; |
11616 | break; | |
11617 | case 3: | |
e3219ce6 ASJ |
11618 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
11619 | pf->num_lan_msix = 1; | |
11620 | pf->num_iwarp_msix = 1; | |
11621 | } else { | |
11622 | pf->num_lan_msix = 2; | |
11623 | } | |
41c445ff JB |
11624 | break; |
11625 | default: | |
e3219ce6 ASJ |
11626 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
11627 | pf->num_iwarp_msix = min_t(int, (vec / 3), | |
11628 | iwarp_requested); | |
11629 | pf->num_vmdq_vsis = min_t(int, (vec / 3), | |
11630 | I40E_DEFAULT_NUM_VMDQ_VSI); | |
11631 | } else { | |
11632 | pf->num_vmdq_vsis = min_t(int, (vec / 2), | |
11633 | I40E_DEFAULT_NUM_VMDQ_VSI); | |
11634 | } | |
abd97a94 SA |
11635 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
11636 | pf->num_fdsb_msix = 1; | |
11637 | vec--; | |
11638 | } | |
e3219ce6 ASJ |
11639 | pf->num_lan_msix = min_t(int, |
11640 | (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)), | |
11641 | pf->num_lan_msix); | |
4ce20abc | 11642 | pf->num_lan_qps = pf->num_lan_msix; |
41c445ff JB |
11643 | break; |
11644 | } | |
11645 | } | |
11646 | ||
abd97a94 SA |
11647 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
11648 | (pf->num_fdsb_msix == 0)) { | |
11649 | dev_info(&pf->pdev->dev, "Sideband Flowdir disabled, not enough MSI-X vectors\n"); | |
11650 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
2f4b411a | 11651 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
abd97a94 | 11652 | } |
a34977ba ASJ |
11653 | if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && |
11654 | (pf->num_vmdq_msix == 0)) { | |
11655 | dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n"); | |
11656 | pf->flags &= ~I40E_FLAG_VMDQ_ENABLED; | |
11657 | } | |
e3219ce6 ASJ |
11658 | |
11659 | if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && | |
11660 | (pf->num_iwarp_msix == 0)) { | |
11661 | dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n"); | |
11662 | pf->flags &= ~I40E_FLAG_IWARP_ENABLED; | |
11663 | } | |
4ce20abc SA |
11664 | i40e_debug(&pf->hw, I40E_DEBUG_INIT, |
11665 | "MSI-X vector distribution: PF %d, VMDq %d, FDSB %d, iWARP %d\n", | |
11666 | pf->num_lan_msix, | |
11667 | pf->num_vmdq_msix * pf->num_vmdq_vsis, | |
11668 | pf->num_fdsb_msix, | |
11669 | pf->num_iwarp_msix); | |
11670 | ||
3b444399 | 11671 | return v_actual; |
41c445ff JB |
11672 | } |
11673 | ||
493fb300 | 11674 | /** |
90e04070 | 11675 | * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector |
493fb300 AD |
11676 | * @vsi: the VSI being configured |
11677 | * @v_idx: index of the vector in the vsi struct | |
11678 | * | |
11679 | * We allocate one q_vector. If allocation fails we return -ENOMEM. | |
11680 | **/ | |
f49be6dc | 11681 | static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx) |
493fb300 AD |
11682 | { |
11683 | struct i40e_q_vector *q_vector; | |
11684 | ||
11685 | /* allocate q_vector */ | |
11686 | q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL); | |
11687 | if (!q_vector) | |
11688 | return -ENOMEM; | |
11689 | ||
11690 | q_vector->vsi = vsi; | |
11691 | q_vector->v_idx = v_idx; | |
759dc4a7 | 11692 | cpumask_copy(&q_vector->affinity_mask, cpu_possible_mask); |
7f6c5539 | 11693 | |
493fb300 AD |
11694 | if (vsi->netdev) |
11695 | netif_napi_add(vsi->netdev, &q_vector->napi, | |
eefeacee | 11696 | i40e_napi_poll, NAPI_POLL_WEIGHT); |
493fb300 AD |
11697 | |
11698 | /* tie q_vector and vsi together */ | |
11699 | vsi->q_vectors[v_idx] = q_vector; | |
11700 | ||
11701 | return 0; | |
11702 | } | |
11703 | ||
41c445ff | 11704 | /** |
90e04070 | 11705 | * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors |
41c445ff JB |
11706 | * @vsi: the VSI being configured |
11707 | * | |
11708 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
11709 | * return -ENOMEM. | |
11710 | **/ | |
90e04070 | 11711 | static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi) |
41c445ff JB |
11712 | { |
11713 | struct i40e_pf *pf = vsi->back; | |
f49be6dc | 11714 | int err, v_idx, num_q_vectors; |
41c445ff JB |
11715 | |
11716 | /* if not MSIX, give the one vector only to the LAN VSI */ | |
11717 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
11718 | num_q_vectors = vsi->num_q_vectors; | |
11719 | else if (vsi == pf->vsi[pf->lan_vsi]) | |
11720 | num_q_vectors = 1; | |
11721 | else | |
11722 | return -EINVAL; | |
11723 | ||
41c445ff | 11724 | for (v_idx = 0; v_idx < num_q_vectors; v_idx++) { |
f49be6dc | 11725 | err = i40e_vsi_alloc_q_vector(vsi, v_idx); |
493fb300 AD |
11726 | if (err) |
11727 | goto err_out; | |
41c445ff JB |
11728 | } |
11729 | ||
11730 | return 0; | |
493fb300 AD |
11731 | |
11732 | err_out: | |
11733 | while (v_idx--) | |
11734 | i40e_free_q_vector(vsi, v_idx); | |
11735 | ||
11736 | return err; | |
41c445ff JB |
11737 | } |
11738 | ||
11739 | /** | |
11740 | * i40e_init_interrupt_scheme - Determine proper interrupt scheme | |
11741 | * @pf: board private structure to initialize | |
11742 | **/ | |
c1147280 | 11743 | static int i40e_init_interrupt_scheme(struct i40e_pf *pf) |
41c445ff | 11744 | { |
3b444399 SN |
11745 | int vectors = 0; |
11746 | ssize_t size; | |
41c445ff JB |
11747 | |
11748 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
3b444399 SN |
11749 | vectors = i40e_init_msix(pf); |
11750 | if (vectors < 0) { | |
60ea5f83 | 11751 | pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | |
e3219ce6 | 11752 | I40E_FLAG_IWARP_ENABLED | |
60ea5f83 | 11753 | I40E_FLAG_RSS_ENABLED | |
4d9b6043 | 11754 | I40E_FLAG_DCB_CAPABLE | |
a036244c | 11755 | I40E_FLAG_DCB_ENABLED | |
60ea5f83 JB |
11756 | I40E_FLAG_SRIOV_ENABLED | |
11757 | I40E_FLAG_FD_SB_ENABLED | | |
11758 | I40E_FLAG_FD_ATR_ENABLED | | |
11759 | I40E_FLAG_VMDQ_ENABLED); | |
2f4b411a | 11760 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
41c445ff JB |
11761 | |
11762 | /* rework the queue expectations without MSIX */ | |
11763 | i40e_determine_queue_usage(pf); | |
11764 | } | |
11765 | } | |
11766 | ||
11767 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) && | |
11768 | (pf->flags & I40E_FLAG_MSI_ENABLED)) { | |
77fa28be | 11769 | dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n"); |
3b444399 SN |
11770 | vectors = pci_enable_msi(pf->pdev); |
11771 | if (vectors < 0) { | |
11772 | dev_info(&pf->pdev->dev, "MSI init failed - %d\n", | |
11773 | vectors); | |
41c445ff JB |
11774 | pf->flags &= ~I40E_FLAG_MSI_ENABLED; |
11775 | } | |
3b444399 | 11776 | vectors = 1; /* one MSI or Legacy vector */ |
41c445ff JB |
11777 | } |
11778 | ||
958a3e3b | 11779 | if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED))) |
77fa28be | 11780 | dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n"); |
958a3e3b | 11781 | |
3b444399 SN |
11782 | /* set up vector assignment tracking */ |
11783 | size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors); | |
11784 | pf->irq_pile = kzalloc(size, GFP_KERNEL); | |
557450c3 | 11785 | if (!pf->irq_pile) |
c1147280 | 11786 | return -ENOMEM; |
557450c3 | 11787 | |
3b444399 SN |
11788 | pf->irq_pile->num_entries = vectors; |
11789 | pf->irq_pile->search_hint = 0; | |
11790 | ||
c1147280 | 11791 | /* track first vector for misc interrupts, ignore return */ |
3b444399 | 11792 | (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1); |
c1147280 JB |
11793 | |
11794 | return 0; | |
41c445ff JB |
11795 | } |
11796 | ||
b980c063 JK |
11797 | /** |
11798 | * i40e_restore_interrupt_scheme - Restore the interrupt scheme | |
11799 | * @pf: private board data structure | |
11800 | * | |
11801 | * Restore the interrupt scheme that was cleared when we suspended the | |
11802 | * device. This should be called during resume to re-allocate the q_vectors | |
11803 | * and reacquire IRQs. | |
11804 | */ | |
11805 | static int i40e_restore_interrupt_scheme(struct i40e_pf *pf) | |
11806 | { | |
11807 | int err, i; | |
11808 | ||
11809 | /* We cleared the MSI and MSI-X flags when disabling the old interrupt | |
11810 | * scheme. We need to re-enabled them here in order to attempt to | |
11811 | * re-acquire the MSI or MSI-X vectors | |
11812 | */ | |
11813 | pf->flags |= (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED); | |
11814 | ||
11815 | err = i40e_init_interrupt_scheme(pf); | |
11816 | if (err) | |
11817 | return err; | |
11818 | ||
11819 | /* Now that we've re-acquired IRQs, we need to remap the vectors and | |
11820 | * rings together again. | |
11821 | */ | |
11822 | for (i = 0; i < pf->num_alloc_vsi; i++) { | |
11823 | if (pf->vsi[i]) { | |
11824 | err = i40e_vsi_alloc_q_vectors(pf->vsi[i]); | |
11825 | if (err) | |
11826 | goto err_unwind; | |
11827 | i40e_vsi_map_rings_to_vectors(pf->vsi[i]); | |
11828 | } | |
11829 | } | |
11830 | ||
11831 | err = i40e_setup_misc_vector(pf); | |
11832 | if (err) | |
11833 | goto err_unwind; | |
11834 | ||
ddbb8d5d SS |
11835 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) |
11836 | i40e_client_update_msix_info(pf); | |
11837 | ||
b980c063 JK |
11838 | return 0; |
11839 | ||
11840 | err_unwind: | |
11841 | while (i--) { | |
11842 | if (pf->vsi[i]) | |
11843 | i40e_vsi_free_q_vectors(pf->vsi[i]); | |
11844 | } | |
11845 | ||
11846 | return err; | |
11847 | } | |
b980c063 | 11848 | |
4ff0ee1a AM |
11849 | /** |
11850 | * i40e_setup_misc_vector_for_recovery_mode - Setup the misc vector to handle | |
11851 | * non queue events in recovery mode | |
11852 | * @pf: board private structure | |
11853 | * | |
11854 | * This sets up the handler for MSIX 0 or MSI/legacy, which is used to manage | |
11855 | * the non-queue interrupts, e.g. AdminQ and errors in recovery mode. | |
11856 | * This is handled differently than in recovery mode since no Tx/Rx resources | |
11857 | * are being allocated. | |
11858 | **/ | |
11859 | static int i40e_setup_misc_vector_for_recovery_mode(struct i40e_pf *pf) | |
11860 | { | |
11861 | int err; | |
11862 | ||
11863 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
11864 | err = i40e_setup_misc_vector(pf); | |
11865 | ||
11866 | if (err) { | |
11867 | dev_info(&pf->pdev->dev, | |
11868 | "MSI-X misc vector request failed, error %d\n", | |
11869 | err); | |
11870 | return err; | |
11871 | } | |
11872 | } else { | |
11873 | u32 flags = pf->flags & I40E_FLAG_MSI_ENABLED ? 0 : IRQF_SHARED; | |
11874 | ||
11875 | err = request_irq(pf->pdev->irq, i40e_intr, flags, | |
11876 | pf->int_name, pf); | |
11877 | ||
11878 | if (err) { | |
11879 | dev_info(&pf->pdev->dev, | |
11880 | "MSI/legacy misc vector request failed, error %d\n", | |
11881 | err); | |
11882 | return err; | |
11883 | } | |
11884 | i40e_enable_misc_int_causes(pf); | |
11885 | i40e_irq_dynamic_enable_icr0(pf); | |
11886 | } | |
11887 | ||
11888 | return 0; | |
11889 | } | |
11890 | ||
41c445ff JB |
11891 | /** |
11892 | * i40e_setup_misc_vector - Setup the misc vector to handle non queue events | |
11893 | * @pf: board private structure | |
11894 | * | |
11895 | * This sets up the handler for MSIX 0, which is used to manage the | |
11896 | * non-queue interrupts, e.g. AdminQ and errors. This is not used | |
11897 | * when in MSI or Legacy interrupt mode. | |
11898 | **/ | |
11899 | static int i40e_setup_misc_vector(struct i40e_pf *pf) | |
11900 | { | |
11901 | struct i40e_hw *hw = &pf->hw; | |
11902 | int err = 0; | |
11903 | ||
c17401a1 JK |
11904 | /* Only request the IRQ once, the first time through. */ |
11905 | if (!test_and_set_bit(__I40E_MISC_IRQ_REQUESTED, pf->state)) { | |
41c445ff | 11906 | err = request_irq(pf->msix_entries[0].vector, |
b294ac70 | 11907 | i40e_intr, 0, pf->int_name, pf); |
41c445ff | 11908 | if (err) { |
c17401a1 | 11909 | clear_bit(__I40E_MISC_IRQ_REQUESTED, pf->state); |
41c445ff | 11910 | dev_info(&pf->pdev->dev, |
77fa28be | 11911 | "request_irq for %s failed: %d\n", |
b294ac70 | 11912 | pf->int_name, err); |
41c445ff JB |
11913 | return -EFAULT; |
11914 | } | |
11915 | } | |
11916 | ||
ab437b5a | 11917 | i40e_enable_misc_int_causes(pf); |
41c445ff JB |
11918 | |
11919 | /* associate no queues to the misc vector */ | |
11920 | wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST); | |
998e5166 | 11921 | wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K >> 1); |
41c445ff JB |
11922 | |
11923 | i40e_flush(hw); | |
11924 | ||
dbadbbe2 | 11925 | i40e_irq_dynamic_enable_icr0(pf); |
41c445ff JB |
11926 | |
11927 | return err; | |
11928 | } | |
11929 | ||
95a73780 ASJ |
11930 | /** |
11931 | * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands | |
11932 | * @vsi: Pointer to vsi structure | |
11933 | * @seed: Buffter to store the hash keys | |
11934 | * @lut: Buffer to store the lookup table entries | |
11935 | * @lut_size: Size of buffer to store the lookup table entries | |
11936 | * | |
11937 | * Return 0 on success, negative on failure | |
11938 | */ | |
11939 | static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed, | |
11940 | u8 *lut, u16 lut_size) | |
11941 | { | |
11942 | struct i40e_pf *pf = vsi->back; | |
11943 | struct i40e_hw *hw = &pf->hw; | |
11944 | int ret = 0; | |
11945 | ||
11946 | if (seed) { | |
11947 | ret = i40e_aq_get_rss_key(hw, vsi->id, | |
11948 | (struct i40e_aqc_get_set_rss_key_data *)seed); | |
11949 | if (ret) { | |
11950 | dev_info(&pf->pdev->dev, | |
11951 | "Cannot get RSS key, err %s aq_err %s\n", | |
11952 | i40e_stat_str(&pf->hw, ret), | |
11953 | i40e_aq_str(&pf->hw, | |
11954 | pf->hw.aq.asq_last_status)); | |
11955 | return ret; | |
11956 | } | |
11957 | } | |
11958 | ||
11959 | if (lut) { | |
7ff4f063 | 11960 | bool pf_lut = vsi->type == I40E_VSI_MAIN; |
95a73780 ASJ |
11961 | |
11962 | ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size); | |
11963 | if (ret) { | |
11964 | dev_info(&pf->pdev->dev, | |
11965 | "Cannot get RSS lut, err %s aq_err %s\n", | |
11966 | i40e_stat_str(&pf->hw, ret), | |
11967 | i40e_aq_str(&pf->hw, | |
11968 | pf->hw.aq.asq_last_status)); | |
11969 | return ret; | |
11970 | } | |
11971 | } | |
11972 | ||
11973 | return ret; | |
11974 | } | |
11975 | ||
e25d00b8 | 11976 | /** |
043dd650 | 11977 | * i40e_config_rss_reg - Configure RSS keys and lut by writing registers |
e69ff813 | 11978 | * @vsi: Pointer to vsi structure |
e25d00b8 | 11979 | * @seed: RSS hash seed |
e69ff813 HZ |
11980 | * @lut: Lookup table |
11981 | * @lut_size: Lookup table size | |
11982 | * | |
11983 | * Returns 0 on success, negative on failure | |
41c445ff | 11984 | **/ |
e69ff813 HZ |
11985 | static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed, |
11986 | const u8 *lut, u16 lut_size) | |
41c445ff | 11987 | { |
e69ff813 | 11988 | struct i40e_pf *pf = vsi->back; |
4617e8c0 | 11989 | struct i40e_hw *hw = &pf->hw; |
c4e1868c | 11990 | u16 vf_id = vsi->vf_id; |
e69ff813 | 11991 | u8 i; |
41c445ff | 11992 | |
e25d00b8 | 11993 | /* Fill out hash function seed */ |
e69ff813 HZ |
11994 | if (seed) { |
11995 | u32 *seed_dw = (u32 *)seed; | |
11996 | ||
c4e1868c MW |
11997 | if (vsi->type == I40E_VSI_MAIN) { |
11998 | for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) | |
26f77e53 | 11999 | wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]); |
c4e1868c MW |
12000 | } else if (vsi->type == I40E_VSI_SRIOV) { |
12001 | for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++) | |
26f77e53 | 12002 | wr32(hw, I40E_VFQF_HKEY1(i, vf_id), seed_dw[i]); |
c4e1868c MW |
12003 | } else { |
12004 | dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n"); | |
12005 | } | |
e69ff813 HZ |
12006 | } |
12007 | ||
12008 | if (lut) { | |
12009 | u32 *lut_dw = (u32 *)lut; | |
12010 | ||
c4e1868c MW |
12011 | if (vsi->type == I40E_VSI_MAIN) { |
12012 | if (lut_size != I40E_HLUT_ARRAY_SIZE) | |
12013 | return -EINVAL; | |
12014 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
12015 | wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]); | |
12016 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
12017 | if (lut_size != I40E_VF_HLUT_ARRAY_SIZE) | |
12018 | return -EINVAL; | |
12019 | for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) | |
26f77e53 | 12020 | wr32(hw, I40E_VFQF_HLUT1(i, vf_id), lut_dw[i]); |
c4e1868c MW |
12021 | } else { |
12022 | dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n"); | |
12023 | } | |
e25d00b8 ASJ |
12024 | } |
12025 | i40e_flush(hw); | |
12026 | ||
12027 | return 0; | |
12028 | } | |
12029 | ||
043dd650 HZ |
12030 | /** |
12031 | * i40e_get_rss_reg - Get the RSS keys and lut by reading registers | |
12032 | * @vsi: Pointer to VSI structure | |
12033 | * @seed: Buffer to store the keys | |
12034 | * @lut: Buffer to store the lookup table entries | |
12035 | * @lut_size: Size of buffer to store the lookup table entries | |
12036 | * | |
12037 | * Returns 0 on success, negative on failure | |
12038 | */ | |
12039 | static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed, | |
12040 | u8 *lut, u16 lut_size) | |
12041 | { | |
12042 | struct i40e_pf *pf = vsi->back; | |
12043 | struct i40e_hw *hw = &pf->hw; | |
12044 | u16 i; | |
12045 | ||
12046 | if (seed) { | |
12047 | u32 *seed_dw = (u32 *)seed; | |
12048 | ||
12049 | for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) | |
272cdaf2 | 12050 | seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i)); |
043dd650 HZ |
12051 | } |
12052 | if (lut) { | |
12053 | u32 *lut_dw = (u32 *)lut; | |
12054 | ||
12055 | if (lut_size != I40E_HLUT_ARRAY_SIZE) | |
12056 | return -EINVAL; | |
12057 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
12058 | lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i)); | |
12059 | } | |
12060 | ||
12061 | return 0; | |
12062 | } | |
12063 | ||
12064 | /** | |
12065 | * i40e_config_rss - Configure RSS keys and lut | |
12066 | * @vsi: Pointer to VSI structure | |
12067 | * @seed: RSS hash seed | |
12068 | * @lut: Lookup table | |
12069 | * @lut_size: Lookup table size | |
12070 | * | |
12071 | * Returns 0 on success, negative on failure | |
12072 | */ | |
12073 | int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) | |
12074 | { | |
12075 | struct i40e_pf *pf = vsi->back; | |
12076 | ||
d36e41dc | 12077 | if (pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) |
043dd650 HZ |
12078 | return i40e_config_rss_aq(vsi, seed, lut, lut_size); |
12079 | else | |
12080 | return i40e_config_rss_reg(vsi, seed, lut, lut_size); | |
12081 | } | |
12082 | ||
12083 | /** | |
12084 | * i40e_get_rss - Get RSS keys and lut | |
12085 | * @vsi: Pointer to VSI structure | |
12086 | * @seed: Buffer to store the keys | |
12087 | * @lut: Buffer to store the lookup table entries | |
f5254429 | 12088 | * @lut_size: Size of buffer to store the lookup table entries |
043dd650 HZ |
12089 | * |
12090 | * Returns 0 on success, negative on failure | |
12091 | */ | |
12092 | int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) | |
12093 | { | |
95a73780 ASJ |
12094 | struct i40e_pf *pf = vsi->back; |
12095 | ||
d36e41dc | 12096 | if (pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) |
95a73780 ASJ |
12097 | return i40e_get_rss_aq(vsi, seed, lut, lut_size); |
12098 | else | |
12099 | return i40e_get_rss_reg(vsi, seed, lut, lut_size); | |
043dd650 HZ |
12100 | } |
12101 | ||
e69ff813 HZ |
12102 | /** |
12103 | * i40e_fill_rss_lut - Fill the RSS lookup table with default values | |
12104 | * @pf: Pointer to board private structure | |
12105 | * @lut: Lookup table | |
12106 | * @rss_table_size: Lookup table size | |
12107 | * @rss_size: Range of queue number for hashing | |
12108 | */ | |
f1582351 AB |
12109 | void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, |
12110 | u16 rss_table_size, u16 rss_size) | |
e69ff813 HZ |
12111 | { |
12112 | u16 i; | |
12113 | ||
12114 | for (i = 0; i < rss_table_size; i++) | |
12115 | lut[i] = i % rss_size; | |
12116 | } | |
12117 | ||
e25d00b8 | 12118 | /** |
043dd650 | 12119 | * i40e_pf_config_rss - Prepare for RSS if used |
e25d00b8 ASJ |
12120 | * @pf: board private structure |
12121 | **/ | |
043dd650 | 12122 | static int i40e_pf_config_rss(struct i40e_pf *pf) |
e25d00b8 ASJ |
12123 | { |
12124 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
12125 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
e69ff813 | 12126 | u8 *lut; |
e25d00b8 ASJ |
12127 | struct i40e_hw *hw = &pf->hw; |
12128 | u32 reg_val; | |
12129 | u64 hena; | |
e69ff813 | 12130 | int ret; |
e25d00b8 | 12131 | |
41c445ff | 12132 | /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */ |
272cdaf2 SN |
12133 | hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) | |
12134 | ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32); | |
e25d00b8 ASJ |
12135 | hena |= i40e_pf_get_default_rss_hena(pf); |
12136 | ||
272cdaf2 SN |
12137 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena); |
12138 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); | |
41c445ff | 12139 | |
e25d00b8 | 12140 | /* Determine the RSS table size based on the hardware capabilities */ |
272cdaf2 | 12141 | reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); |
e25d00b8 ASJ |
12142 | reg_val = (pf->rss_table_size == 512) ? |
12143 | (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) : | |
12144 | (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512); | |
272cdaf2 | 12145 | i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val); |
e157ea30 | 12146 | |
28c5869f | 12147 | /* Determine the RSS size of the VSI */ |
f25571b5 HR |
12148 | if (!vsi->rss_size) { |
12149 | u16 qcount; | |
b356dac8 MW |
12150 | /* If the firmware does something weird during VSI init, we |
12151 | * could end up with zero TCs. Check for that to avoid | |
12152 | * divide-by-zero. It probably won't pass traffic, but it also | |
12153 | * won't panic. | |
12154 | */ | |
12155 | qcount = vsi->num_queue_pairs / | |
12156 | (vsi->tc_config.numtc ? vsi->tc_config.numtc : 1); | |
f25571b5 HR |
12157 | vsi->rss_size = min_t(int, pf->alloc_rss_size, qcount); |
12158 | } | |
a4fa59cc MW |
12159 | if (!vsi->rss_size) |
12160 | return -EINVAL; | |
28c5869f | 12161 | |
e69ff813 HZ |
12162 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); |
12163 | if (!lut) | |
12164 | return -ENOMEM; | |
12165 | ||
28c5869f HZ |
12166 | /* Use user configured lut if there is one, otherwise use default */ |
12167 | if (vsi->rss_lut_user) | |
12168 | memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size); | |
12169 | else | |
12170 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); | |
e69ff813 | 12171 | |
28c5869f HZ |
12172 | /* Use user configured hash key if there is one, otherwise |
12173 | * use default. | |
12174 | */ | |
12175 | if (vsi->rss_hkey_user) | |
12176 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
12177 | else | |
12178 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
043dd650 | 12179 | ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size); |
e69ff813 HZ |
12180 | kfree(lut); |
12181 | ||
12182 | return ret; | |
41c445ff JB |
12183 | } |
12184 | ||
f8ff1464 ASJ |
12185 | /** |
12186 | * i40e_reconfig_rss_queues - change number of queues for rss and rebuild | |
12187 | * @pf: board private structure | |
12188 | * @queue_count: the requested queue count for rss. | |
12189 | * | |
12190 | * returns 0 if rss is not enabled, if enabled returns the final rss queue | |
12191 | * count which may be different from the requested queue count. | |
373149fc | 12192 | * Note: expects to be called while under rtnl_lock() |
f8ff1464 ASJ |
12193 | **/ |
12194 | int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count) | |
12195 | { | |
9a3bd2f1 ASJ |
12196 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
12197 | int new_rss_size; | |
12198 | ||
f8ff1464 ASJ |
12199 | if (!(pf->flags & I40E_FLAG_RSS_ENABLED)) |
12200 | return 0; | |
12201 | ||
3647cd6e | 12202 | queue_count = min_t(int, queue_count, num_online_cpus()); |
9a3bd2f1 | 12203 | new_rss_size = min_t(int, queue_count, pf->rss_size_max); |
f8ff1464 | 12204 | |
9a3bd2f1 | 12205 | if (queue_count != vsi->num_queue_pairs) { |
f25571b5 HR |
12206 | u16 qcount; |
12207 | ||
9a3bd2f1 | 12208 | vsi->req_queue_pairs = queue_count; |
4b208eaa | 12209 | i40e_prep_for_reset(pf); |
f8ff1464 | 12210 | |
acd65448 | 12211 | pf->alloc_rss_size = new_rss_size; |
f8ff1464 | 12212 | |
373149fc | 12213 | i40e_reset_and_rebuild(pf, true, true); |
28c5869f HZ |
12214 | |
12215 | /* Discard the user configured hash keys and lut, if less | |
12216 | * queues are enabled. | |
12217 | */ | |
12218 | if (queue_count < vsi->rss_size) { | |
12219 | i40e_clear_rss_config_user(vsi); | |
12220 | dev_dbg(&pf->pdev->dev, | |
12221 | "discard user configured hash keys and lut\n"); | |
12222 | } | |
12223 | ||
12224 | /* Reset vsi->rss_size, as number of enabled queues changed */ | |
f25571b5 HR |
12225 | qcount = vsi->num_queue_pairs / vsi->tc_config.numtc; |
12226 | vsi->rss_size = min_t(int, pf->alloc_rss_size, qcount); | |
28c5869f | 12227 | |
043dd650 | 12228 | i40e_pf_config_rss(pf); |
f8ff1464 | 12229 | } |
12815057 LY |
12230 | dev_info(&pf->pdev->dev, "User requested queue count/HW max RSS count: %d/%d\n", |
12231 | vsi->req_queue_pairs, pf->rss_size_max); | |
acd65448 | 12232 | return pf->alloc_rss_size; |
f8ff1464 ASJ |
12233 | } |
12234 | ||
f4492db1 | 12235 | /** |
4fc8c676 | 12236 | * i40e_get_partition_bw_setting - Retrieve BW settings for this PF partition |
f4492db1 GR |
12237 | * @pf: board private structure |
12238 | **/ | |
4fc8c676 | 12239 | i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf) |
f4492db1 GR |
12240 | { |
12241 | i40e_status status; | |
12242 | bool min_valid, max_valid; | |
12243 | u32 max_bw, min_bw; | |
12244 | ||
12245 | status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw, | |
12246 | &min_valid, &max_valid); | |
12247 | ||
12248 | if (!status) { | |
12249 | if (min_valid) | |
4fc8c676 | 12250 | pf->min_bw = min_bw; |
f4492db1 | 12251 | if (max_valid) |
4fc8c676 | 12252 | pf->max_bw = max_bw; |
f4492db1 GR |
12253 | } |
12254 | ||
12255 | return status; | |
12256 | } | |
12257 | ||
12258 | /** | |
4fc8c676 | 12259 | * i40e_set_partition_bw_setting - Set BW settings for this PF partition |
f4492db1 GR |
12260 | * @pf: board private structure |
12261 | **/ | |
4fc8c676 | 12262 | i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf) |
f4492db1 GR |
12263 | { |
12264 | struct i40e_aqc_configure_partition_bw_data bw_data; | |
12265 | i40e_status status; | |
12266 | ||
d2c788f7 MP |
12267 | memset(&bw_data, 0, sizeof(bw_data)); |
12268 | ||
b40c82e6 | 12269 | /* Set the valid bit for this PF */ |
41a1d04b | 12270 | bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id)); |
4fc8c676 SN |
12271 | bw_data.max_bw[pf->hw.pf_id] = pf->max_bw & I40E_ALT_BW_VALUE_MASK; |
12272 | bw_data.min_bw[pf->hw.pf_id] = pf->min_bw & I40E_ALT_BW_VALUE_MASK; | |
f4492db1 GR |
12273 | |
12274 | /* Set the new bandwidths */ | |
12275 | status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL); | |
12276 | ||
12277 | return status; | |
12278 | } | |
12279 | ||
12280 | /** | |
4fc8c676 | 12281 | * i40e_commit_partition_bw_setting - Commit BW settings for this PF partition |
f4492db1 GR |
12282 | * @pf: board private structure |
12283 | **/ | |
4fc8c676 | 12284 | i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf) |
f4492db1 GR |
12285 | { |
12286 | /* Commit temporary BW setting to permanent NVM image */ | |
12287 | enum i40e_admin_queue_err last_aq_status; | |
12288 | i40e_status ret; | |
12289 | u16 nvm_word; | |
12290 | ||
12291 | if (pf->hw.partition_id != 1) { | |
12292 | dev_info(&pf->pdev->dev, | |
12293 | "Commit BW only works on partition 1! This is partition %d", | |
12294 | pf->hw.partition_id); | |
12295 | ret = I40E_NOT_SUPPORTED; | |
12296 | goto bw_commit_out; | |
12297 | } | |
12298 | ||
12299 | /* Acquire NVM for read access */ | |
12300 | ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ); | |
12301 | last_aq_status = pf->hw.aq.asq_last_status; | |
12302 | if (ret) { | |
12303 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
12304 | "Cannot acquire NVM for read access, err %s aq_err %s\n", |
12305 | i40e_stat_str(&pf->hw, ret), | |
12306 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
12307 | goto bw_commit_out; |
12308 | } | |
12309 | ||
12310 | /* Read word 0x10 of NVM - SW compatibility word 1 */ | |
12311 | ret = i40e_aq_read_nvm(&pf->hw, | |
12312 | I40E_SR_NVM_CONTROL_WORD, | |
12313 | 0x10, sizeof(nvm_word), &nvm_word, | |
12314 | false, NULL); | |
12315 | /* Save off last admin queue command status before releasing | |
12316 | * the NVM | |
12317 | */ | |
12318 | last_aq_status = pf->hw.aq.asq_last_status; | |
12319 | i40e_release_nvm(&pf->hw); | |
12320 | if (ret) { | |
f1c7e72e SN |
12321 | dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n", |
12322 | i40e_stat_str(&pf->hw, ret), | |
12323 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
12324 | goto bw_commit_out; |
12325 | } | |
12326 | ||
12327 | /* Wait a bit for NVM release to complete */ | |
12328 | msleep(50); | |
12329 | ||
12330 | /* Acquire NVM for write access */ | |
12331 | ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE); | |
12332 | last_aq_status = pf->hw.aq.asq_last_status; | |
12333 | if (ret) { | |
12334 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
12335 | "Cannot acquire NVM for write access, err %s aq_err %s\n", |
12336 | i40e_stat_str(&pf->hw, ret), | |
12337 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
12338 | goto bw_commit_out; |
12339 | } | |
12340 | /* Write it back out unchanged to initiate update NVM, | |
12341 | * which will force a write of the shadow (alt) RAM to | |
12342 | * the NVM - thus storing the bandwidth values permanently. | |
12343 | */ | |
12344 | ret = i40e_aq_update_nvm(&pf->hw, | |
12345 | I40E_SR_NVM_CONTROL_WORD, | |
12346 | 0x10, sizeof(nvm_word), | |
e3a5d6e6 | 12347 | &nvm_word, true, 0, NULL); |
f4492db1 GR |
12348 | /* Save off last admin queue command status before releasing |
12349 | * the NVM | |
12350 | */ | |
12351 | last_aq_status = pf->hw.aq.asq_last_status; | |
12352 | i40e_release_nvm(&pf->hw); | |
12353 | if (ret) | |
12354 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
12355 | "BW settings NOT SAVED, err %s aq_err %s\n", |
12356 | i40e_stat_str(&pf->hw, ret), | |
12357 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
12358 | bw_commit_out: |
12359 | ||
12360 | return ret; | |
12361 | } | |
12362 | ||
d5ec9e2c AK |
12363 | /** |
12364 | * i40e_is_total_port_shutdown_enabled - read NVM and return value | |
12365 | * if total port shutdown feature is enabled for this PF | |
12366 | * @pf: board private structure | |
12367 | **/ | |
12368 | static bool i40e_is_total_port_shutdown_enabled(struct i40e_pf *pf) | |
12369 | { | |
12370 | #define I40E_TOTAL_PORT_SHUTDOWN_ENABLED BIT(4) | |
12371 | #define I40E_FEATURES_ENABLE_PTR 0x2A | |
12372 | #define I40E_CURRENT_SETTING_PTR 0x2B | |
12373 | #define I40E_LINK_BEHAVIOR_WORD_OFFSET 0x2D | |
12374 | #define I40E_LINK_BEHAVIOR_WORD_LENGTH 0x1 | |
12375 | #define I40E_LINK_BEHAVIOR_OS_FORCED_ENABLED BIT(0) | |
12376 | #define I40E_LINK_BEHAVIOR_PORT_BIT_LENGTH 4 | |
12377 | i40e_status read_status = I40E_SUCCESS; | |
12378 | u16 sr_emp_sr_settings_ptr = 0; | |
12379 | u16 features_enable = 0; | |
12380 | u16 link_behavior = 0; | |
12381 | bool ret = false; | |
12382 | ||
12383 | read_status = i40e_read_nvm_word(&pf->hw, | |
12384 | I40E_SR_EMP_SR_SETTINGS_PTR, | |
12385 | &sr_emp_sr_settings_ptr); | |
12386 | if (read_status) | |
12387 | goto err_nvm; | |
12388 | read_status = i40e_read_nvm_word(&pf->hw, | |
12389 | sr_emp_sr_settings_ptr + | |
12390 | I40E_FEATURES_ENABLE_PTR, | |
12391 | &features_enable); | |
12392 | if (read_status) | |
12393 | goto err_nvm; | |
12394 | if (I40E_TOTAL_PORT_SHUTDOWN_ENABLED & features_enable) { | |
12395 | read_status = i40e_read_nvm_module_data(&pf->hw, | |
12396 | I40E_SR_EMP_SR_SETTINGS_PTR, | |
12397 | I40E_CURRENT_SETTING_PTR, | |
12398 | I40E_LINK_BEHAVIOR_WORD_OFFSET, | |
12399 | I40E_LINK_BEHAVIOR_WORD_LENGTH, | |
12400 | &link_behavior); | |
12401 | if (read_status) | |
12402 | goto err_nvm; | |
12403 | link_behavior >>= (pf->hw.port * I40E_LINK_BEHAVIOR_PORT_BIT_LENGTH); | |
12404 | ret = I40E_LINK_BEHAVIOR_OS_FORCED_ENABLED & link_behavior; | |
12405 | } | |
12406 | return ret; | |
12407 | ||
12408 | err_nvm: | |
12409 | dev_warn(&pf->pdev->dev, | |
12410 | "total-port-shutdown feature is off due to read nvm error: %s\n", | |
12411 | i40e_stat_str(&pf->hw, read_status)); | |
12412 | return ret; | |
12413 | } | |
12414 | ||
41c445ff JB |
12415 | /** |
12416 | * i40e_sw_init - Initialize general software structures (struct i40e_pf) | |
12417 | * @pf: board private structure to initialize | |
12418 | * | |
12419 | * i40e_sw_init initializes the Adapter private data structure. | |
12420 | * Fields are initialized based on PCI device information and | |
12421 | * OS network device settings (MTU size). | |
12422 | **/ | |
12423 | static int i40e_sw_init(struct i40e_pf *pf) | |
12424 | { | |
12425 | int err = 0; | |
12426 | int size; | |
4e39a072 | 12427 | u16 pow; |
41c445ff | 12428 | |
41c445ff JB |
12429 | /* Set default capability flags */ |
12430 | pf->flags = I40E_FLAG_RX_CSUM_ENABLED | | |
12431 | I40E_FLAG_MSI_ENABLED | | |
2bc7ee8a MW |
12432 | I40E_FLAG_MSIX_ENABLED; |
12433 | ||
ca99eb99 | 12434 | /* Set default ITR */ |
42702559 JK |
12435 | pf->rx_itr_default = I40E_ITR_RX_DEF; |
12436 | pf->tx_itr_default = I40E_ITR_TX_DEF; | |
ca99eb99 | 12437 | |
7134f9ce JB |
12438 | /* Depending on PF configurations, it is possible that the RSS |
12439 | * maximum might end up larger than the available queues | |
12440 | */ | |
41a1d04b | 12441 | pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width); |
acd65448 | 12442 | pf->alloc_rss_size = 1; |
5db4cb59 | 12443 | pf->rss_table_size = pf->hw.func_caps.rss_table_size; |
7134f9ce JB |
12444 | pf->rss_size_max = min_t(int, pf->rss_size_max, |
12445 | pf->hw.func_caps.num_tx_qp); | |
4e39a072 JX |
12446 | |
12447 | /* find the next higher power-of-2 of num cpus */ | |
12448 | pow = roundup_pow_of_two(num_online_cpus()); | |
12449 | pf->rss_size_max = min_t(int, pf->rss_size_max, pow); | |
12450 | ||
41c445ff JB |
12451 | if (pf->hw.func_caps.rss) { |
12452 | pf->flags |= I40E_FLAG_RSS_ENABLED; | |
acd65448 HZ |
12453 | pf->alloc_rss_size = min_t(int, pf->rss_size_max, |
12454 | num_online_cpus()); | |
41c445ff JB |
12455 | } |
12456 | ||
2050bc65 | 12457 | /* MFP mode enabled */ |
c78b953e | 12458 | if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) { |
2050bc65 CS |
12459 | pf->flags |= I40E_FLAG_MFP_ENABLED; |
12460 | dev_info(&pf->pdev->dev, "MFP mode Enabled\n"); | |
4fc8c676 | 12461 | if (i40e_get_partition_bw_setting(pf)) { |
f4492db1 | 12462 | dev_warn(&pf->pdev->dev, |
4fc8c676 SN |
12463 | "Could not get partition bw settings\n"); |
12464 | } else { | |
f4492db1 | 12465 | dev_info(&pf->pdev->dev, |
4fc8c676 SN |
12466 | "Partition BW Min = %8.8x, Max = %8.8x\n", |
12467 | pf->min_bw, pf->max_bw); | |
12468 | ||
12469 | /* nudge the Tx scheduler */ | |
12470 | i40e_set_partition_bw_setting(pf); | |
12471 | } | |
2050bc65 CS |
12472 | } |
12473 | ||
cbf61325 ASJ |
12474 | if ((pf->hw.func_caps.fd_filters_guaranteed > 0) || |
12475 | (pf->hw.func_caps.fd_filters_best_effort > 0)) { | |
12476 | pf->flags |= I40E_FLAG_FD_ATR_ENABLED; | |
12477 | pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE; | |
6eae9c6a SN |
12478 | if (pf->flags & I40E_FLAG_MFP_ENABLED && |
12479 | pf->hw.num_partitions > 1) | |
cbf61325 | 12480 | dev_info(&pf->pdev->dev, |
0b67584f | 12481 | "Flow Director Sideband mode Disabled in MFP mode\n"); |
6eae9c6a SN |
12482 | else |
12483 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
cbf61325 ASJ |
12484 | pf->fdir_pf_filter_count = |
12485 | pf->hw.func_caps.fd_filters_guaranteed; | |
12486 | pf->hw.fdir_shared_filter_count = | |
12487 | pf->hw.func_caps.fd_filters_best_effort; | |
41c445ff JB |
12488 | } |
12489 | ||
5a433199 | 12490 | if (pf->hw.mac.type == I40E_MAC_X722) { |
d36e41dc JK |
12491 | pf->hw_features |= (I40E_HW_RSS_AQ_CAPABLE | |
12492 | I40E_HW_128_QP_RSS_CAPABLE | | |
12493 | I40E_HW_ATR_EVICT_CAPABLE | | |
12494 | I40E_HW_WB_ON_ITR_CAPABLE | | |
12495 | I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE | | |
12496 | I40E_HW_NO_PCI_LINK_CHECK | | |
12497 | I40E_HW_USE_SET_LLDP_MIB | | |
12498 | I40E_HW_GENEVE_OFFLOAD_CAPABLE | | |
12499 | I40E_HW_PTP_L4_CAPABLE | | |
12500 | I40E_HW_WOL_MC_MAGIC_PKT_WAKE | | |
12501 | I40E_HW_OUTER_UDP_CSUM_CAPABLE); | |
10a955ff ASJ |
12502 | |
12503 | #define I40E_FDEVICT_PCTYPE_DEFAULT 0xc03 | |
12504 | if (rd32(&pf->hw, I40E_GLQF_FDEVICTENA(1)) != | |
12505 | I40E_FDEVICT_PCTYPE_DEFAULT) { | |
12506 | dev_warn(&pf->pdev->dev, | |
12507 | "FD EVICT PCTYPES are not right, disable FD HW EVICT\n"); | |
12508 | pf->hw_features &= ~I40E_HW_ATR_EVICT_CAPABLE; | |
12509 | } | |
5a433199 ASJ |
12510 | } else if ((pf->hw.aq.api_maj_ver > 1) || |
12511 | ((pf->hw.aq.api_maj_ver == 1) && | |
12512 | (pf->hw.aq.api_min_ver > 4))) { | |
12513 | /* Supported in FW API version higher than 1.4 */ | |
d36e41dc | 12514 | pf->hw_features |= I40E_HW_GENEVE_OFFLOAD_CAPABLE; |
5a433199 ASJ |
12515 | } |
12516 | ||
12517 | /* Enable HW ATR eviction if possible */ | |
d36e41dc | 12518 | if (pf->hw_features & I40E_HW_ATR_EVICT_CAPABLE) |
5a433199 ASJ |
12519 | pf->flags |= I40E_FLAG_HW_ATR_EVICT_ENABLED; |
12520 | ||
6de432c5 | 12521 | if ((pf->hw.mac.type == I40E_MAC_XL710) && |
8eed76fa | 12522 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) || |
f1bbad33 | 12523 | (pf->hw.aq.fw_maj_ver < 4))) { |
d36e41dc | 12524 | pf->hw_features |= I40E_HW_RESTART_AUTONEG; |
f1bbad33 | 12525 | /* No DCB support for FW < v4.33 */ |
d36e41dc | 12526 | pf->hw_features |= I40E_HW_NO_DCB_SUPPORT; |
f1bbad33 NP |
12527 | } |
12528 | ||
12529 | /* Disable FW LLDP if FW < v4.3 */ | |
6de432c5 | 12530 | if ((pf->hw.mac.type == I40E_MAC_XL710) && |
f1bbad33 NP |
12531 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) || |
12532 | (pf->hw.aq.fw_maj_ver < 4))) | |
d36e41dc | 12533 | pf->hw_features |= I40E_HW_STOP_FW_LLDP; |
f1bbad33 NP |
12534 | |
12535 | /* Use the FW Set LLDP MIB API if FW > v4.40 */ | |
6de432c5 | 12536 | if ((pf->hw.mac.type == I40E_MAC_XL710) && |
f1bbad33 NP |
12537 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) || |
12538 | (pf->hw.aq.fw_maj_ver >= 5))) | |
d36e41dc | 12539 | pf->hw_features |= I40E_HW_USE_SET_LLDP_MIB; |
8eed76fa | 12540 | |
c3d26b75 AB |
12541 | /* Enable PTP L4 if FW > v6.0 */ |
12542 | if (pf->hw.mac.type == I40E_MAC_XL710 && | |
12543 | pf->hw.aq.fw_maj_ver >= 6) | |
12544 | pf->hw_features |= I40E_HW_PTP_L4_CAPABLE; | |
12545 | ||
69399873 | 12546 | if (pf->hw.func_caps.vmdq && num_online_cpus() != 1) { |
41c445ff | 12547 | pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI; |
e25d00b8 | 12548 | pf->flags |= I40E_FLAG_VMDQ_ENABLED; |
e9e53662 | 12549 | pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf); |
41c445ff JB |
12550 | } |
12551 | ||
69399873 | 12552 | if (pf->hw.func_caps.iwarp && num_online_cpus() != 1) { |
e3219ce6 ASJ |
12553 | pf->flags |= I40E_FLAG_IWARP_ENABLED; |
12554 | /* IWARP needs one extra vector for CQP just like MISC.*/ | |
12555 | pf->num_iwarp_msix = (int)num_online_cpus() + 1; | |
12556 | } | |
5734fe87 PM |
12557 | /* Stopping FW LLDP engine is supported on XL710 and X722 |
12558 | * starting from FW versions determined in i40e_init_adminq. | |
12559 | * Stopping the FW LLDP engine is not supported on XL710 | |
12560 | * if NPAR is functioning so unset this hw flag in this case. | |
7b63435a DE |
12561 | */ |
12562 | if (pf->hw.mac.type == I40E_MAC_XL710 && | |
5734fe87 PM |
12563 | pf->hw.func_caps.npar_enable && |
12564 | (pf->hw.flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE)) | |
12565 | pf->hw.flags &= ~I40E_HW_FLAG_FW_LLDP_STOPPABLE; | |
e3219ce6 | 12566 | |
41c445ff | 12567 | #ifdef CONFIG_PCI_IOV |
ba252f13 | 12568 | if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) { |
41c445ff JB |
12569 | pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF; |
12570 | pf->flags |= I40E_FLAG_SRIOV_ENABLED; | |
12571 | pf->num_req_vfs = min_t(int, | |
12572 | pf->hw.func_caps.num_vfs, | |
12573 | I40E_MAX_VF_COUNT); | |
12574 | } | |
12575 | #endif /* CONFIG_PCI_IOV */ | |
12576 | pf->eeprom_version = 0xDEAD; | |
12577 | pf->lan_veb = I40E_NO_VEB; | |
12578 | pf->lan_vsi = I40E_NO_VSI; | |
12579 | ||
d1a8d275 ASJ |
12580 | /* By default FW has this off for performance reasons */ |
12581 | pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED; | |
12582 | ||
41c445ff JB |
12583 | /* set up queue assignment tracking */ |
12584 | size = sizeof(struct i40e_lump_tracking) | |
12585 | + (sizeof(u16) * pf->hw.func_caps.num_tx_qp); | |
12586 | pf->qp_pile = kzalloc(size, GFP_KERNEL); | |
12587 | if (!pf->qp_pile) { | |
12588 | err = -ENOMEM; | |
12589 | goto sw_init_done; | |
12590 | } | |
12591 | pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp; | |
12592 | pf->qp_pile->search_hint = 0; | |
12593 | ||
327fe04b ASJ |
12594 | pf->tx_timeout_recovery_level = 1; |
12595 | ||
d5ec9e2c AK |
12596 | if (pf->hw.mac.type != I40E_MAC_X722 && |
12597 | i40e_is_total_port_shutdown_enabled(pf)) { | |
12598 | /* Link down on close must be on when total port shutdown | |
12599 | * is enabled for a given port | |
12600 | */ | |
12601 | pf->flags |= (I40E_FLAG_TOTAL_PORT_SHUTDOWN_ENABLED | | |
12602 | I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED); | |
12603 | dev_info(&pf->pdev->dev, | |
12604 | "total-port-shutdown was enabled, link-down-on-close is forced on\n"); | |
12605 | } | |
41c445ff JB |
12606 | mutex_init(&pf->switch_mutex); |
12607 | ||
12608 | sw_init_done: | |
12609 | return err; | |
12610 | } | |
12611 | ||
7c3c288b ASJ |
12612 | /** |
12613 | * i40e_set_ntuple - set the ntuple feature flag and take action | |
12614 | * @pf: board private structure to initialize | |
12615 | * @features: the feature set that the stack is suggesting | |
12616 | * | |
12617 | * returns a bool to indicate if reset needs to happen | |
12618 | **/ | |
12619 | bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features) | |
12620 | { | |
12621 | bool need_reset = false; | |
12622 | ||
12623 | /* Check if Flow Director n-tuple support was enabled or disabled. If | |
12624 | * the state changed, we need to reset. | |
12625 | */ | |
12626 | if (features & NETIF_F_NTUPLE) { | |
12627 | /* Enable filters and mark for reset */ | |
12628 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) | |
12629 | need_reset = true; | |
2f4b411a AN |
12630 | /* enable FD_SB only if there is MSI-X vector and no cloud |
12631 | * filters exist | |
12632 | */ | |
12633 | if (pf->num_fdsb_msix > 0 && !pf->num_cloud_filters) { | |
a70e407f | 12634 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; |
2f4b411a AN |
12635 | pf->flags &= ~I40E_FLAG_FD_SB_INACTIVE; |
12636 | } | |
7c3c288b ASJ |
12637 | } else { |
12638 | /* turn off filters, mark for reset and clear SW filter list */ | |
12639 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
12640 | need_reset = true; | |
12641 | i40e_fdir_filter_exit(pf); | |
12642 | } | |
134201ae JK |
12643 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; |
12644 | clear_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state); | |
2f4b411a AN |
12645 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
12646 | ||
1e1be8f6 | 12647 | /* reset fd counters */ |
097dbf52 JK |
12648 | pf->fd_add_err = 0; |
12649 | pf->fd_atr_cnt = 0; | |
8a4f34fb | 12650 | /* if ATR was auto disabled it can be re-enabled. */ |
134201ae | 12651 | if (test_and_clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) |
47994c11 JK |
12652 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && |
12653 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
234dc4e6 | 12654 | dev_info(&pf->pdev->dev, "ATR re-enabled.\n"); |
7c3c288b ASJ |
12655 | } |
12656 | return need_reset; | |
12657 | } | |
12658 | ||
d8ec9864 AB |
12659 | /** |
12660 | * i40e_clear_rss_lut - clear the rx hash lookup table | |
12661 | * @vsi: the VSI being configured | |
12662 | **/ | |
12663 | static void i40e_clear_rss_lut(struct i40e_vsi *vsi) | |
12664 | { | |
12665 | struct i40e_pf *pf = vsi->back; | |
12666 | struct i40e_hw *hw = &pf->hw; | |
12667 | u16 vf_id = vsi->vf_id; | |
12668 | u8 i; | |
12669 | ||
12670 | if (vsi->type == I40E_VSI_MAIN) { | |
12671 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
12672 | wr32(hw, I40E_PFQF_HLUT(i), 0); | |
12673 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
12674 | for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) | |
12675 | i40e_write_rx_ctl(hw, I40E_VFQF_HLUT1(i, vf_id), 0); | |
12676 | } else { | |
12677 | dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n"); | |
12678 | } | |
12679 | } | |
12680 | ||
41c445ff JB |
12681 | /** |
12682 | * i40e_set_features - set the netdev feature flags | |
12683 | * @netdev: ptr to the netdev being adjusted | |
12684 | * @features: the feature set that the stack is suggesting | |
373149fc | 12685 | * Note: expects to be called while under rtnl_lock() |
41c445ff JB |
12686 | **/ |
12687 | static int i40e_set_features(struct net_device *netdev, | |
12688 | netdev_features_t features) | |
12689 | { | |
12690 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
12691 | struct i40e_vsi *vsi = np->vsi; | |
7c3c288b ASJ |
12692 | struct i40e_pf *pf = vsi->back; |
12693 | bool need_reset; | |
41c445ff | 12694 | |
d8ec9864 AB |
12695 | if (features & NETIF_F_RXHASH && !(netdev->features & NETIF_F_RXHASH)) |
12696 | i40e_pf_config_rss(pf); | |
12697 | else if (!(features & NETIF_F_RXHASH) && | |
12698 | netdev->features & NETIF_F_RXHASH) | |
12699 | i40e_clear_rss_lut(vsi); | |
12700 | ||
41c445ff JB |
12701 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
12702 | i40e_vlan_stripping_enable(vsi); | |
12703 | else | |
12704 | i40e_vlan_stripping_disable(vsi); | |
12705 | ||
2f4b411a AN |
12706 | if (!(features & NETIF_F_HW_TC) && pf->num_cloud_filters) { |
12707 | dev_err(&pf->pdev->dev, | |
12708 | "Offloaded tc filters active, can't turn hw_tc_offload off"); | |
12709 | return -EINVAL; | |
12710 | } | |
12711 | ||
1d8d80b4 HR |
12712 | if (!(features & NETIF_F_HW_L2FW_DOFFLOAD) && vsi->macvlan_cnt) |
12713 | i40e_del_all_macvlans(vsi); | |
12714 | ||
7c3c288b ASJ |
12715 | need_reset = i40e_set_ntuple(pf, features); |
12716 | ||
12717 | if (need_reset) | |
ff424188 | 12718 | i40e_do_reset(pf, I40E_PF_RESET_FLAG, true); |
7c3c288b | 12719 | |
41c445ff JB |
12720 | return 0; |
12721 | } | |
12722 | ||
40a98cb6 JK |
12723 | static int i40e_udp_tunnel_set_port(struct net_device *netdev, |
12724 | unsigned int table, unsigned int idx, | |
12725 | struct udp_tunnel_info *ti) | |
a1c9a9d9 JK |
12726 | { |
12727 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
40a98cb6 JK |
12728 | struct i40e_hw *hw = &np->vsi->back->hw; |
12729 | u8 type, filter_index; | |
12730 | i40e_status ret; | |
a1c9a9d9 | 12731 | |
40a98cb6 JK |
12732 | type = ti->type == UDP_TUNNEL_TYPE_VXLAN ? I40E_AQC_TUNNEL_TYPE_VXLAN : |
12733 | I40E_AQC_TUNNEL_TYPE_NGE; | |
6a899024 | 12734 | |
40a98cb6 JK |
12735 | ret = i40e_aq_add_udp_tunnel(hw, ntohs(ti->port), type, &filter_index, |
12736 | NULL); | |
12737 | if (ret) { | |
12738 | netdev_info(netdev, "add UDP port failed, err %s aq_err %s\n", | |
12739 | i40e_stat_str(hw, ret), | |
12740 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
12741 | return -EIO; | |
6a899024 SA |
12742 | } |
12743 | ||
40a98cb6 JK |
12744 | udp_tunnel_nic_set_port_priv(netdev, table, idx, filter_index); |
12745 | return 0; | |
a1c9a9d9 JK |
12746 | } |
12747 | ||
40a98cb6 JK |
12748 | static int i40e_udp_tunnel_unset_port(struct net_device *netdev, |
12749 | unsigned int table, unsigned int idx, | |
12750 | struct udp_tunnel_info *ti) | |
6a899024 | 12751 | { |
6a899024 | 12752 | struct i40e_netdev_priv *np = netdev_priv(netdev); |
40a98cb6 JK |
12753 | struct i40e_hw *hw = &np->vsi->back->hw; |
12754 | i40e_status ret; | |
6a899024 | 12755 | |
40a98cb6 JK |
12756 | ret = i40e_aq_del_udp_tunnel(hw, ti->hw_priv, NULL); |
12757 | if (ret) { | |
12758 | netdev_info(netdev, "delete UDP port failed, err %s aq_err %s\n", | |
12759 | i40e_stat_str(hw, ret), | |
12760 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
12761 | return -EIO; | |
6a899024 | 12762 | } |
06a5f7f1 | 12763 | |
40a98cb6 | 12764 | return 0; |
6a899024 SA |
12765 | } |
12766 | ||
1f224ad2 | 12767 | static int i40e_get_phys_port_id(struct net_device *netdev, |
02637fce | 12768 | struct netdev_phys_item_id *ppid) |
1f224ad2 NP |
12769 | { |
12770 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
12771 | struct i40e_pf *pf = np->vsi->back; | |
12772 | struct i40e_hw *hw = &pf->hw; | |
12773 | ||
d36e41dc | 12774 | if (!(pf->hw_features & I40E_HW_PORT_ID_VALID)) |
1f224ad2 NP |
12775 | return -EOPNOTSUPP; |
12776 | ||
12777 | ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id)); | |
12778 | memcpy(ppid->id, hw->mac.port_addr, ppid->id_len); | |
12779 | ||
12780 | return 0; | |
12781 | } | |
12782 | ||
2f90ade6 JB |
12783 | /** |
12784 | * i40e_ndo_fdb_add - add an entry to the hardware database | |
12785 | * @ndm: the input from the stack | |
12786 | * @tb: pointer to array of nladdr (unused) | |
12787 | * @dev: the net device pointer | |
12788 | * @addr: the MAC address entry being added | |
f5254429 | 12789 | * @vid: VLAN ID |
2f90ade6 | 12790 | * @flags: instructions from stack about fdb operation |
b50f7bca | 12791 | * @extack: netlink extended ack, unused currently |
2f90ade6 | 12792 | */ |
4ba0dea5 GR |
12793 | static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], |
12794 | struct net_device *dev, | |
f6f6424b | 12795 | const unsigned char *addr, u16 vid, |
87b0984e PM |
12796 | u16 flags, |
12797 | struct netlink_ext_ack *extack) | |
4ba0dea5 GR |
12798 | { |
12799 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
12800 | struct i40e_pf *pf = np->vsi->back; | |
12801 | int err = 0; | |
12802 | ||
12803 | if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED)) | |
12804 | return -EOPNOTSUPP; | |
12805 | ||
65891fea OG |
12806 | if (vid) { |
12807 | pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name); | |
12808 | return -EINVAL; | |
12809 | } | |
12810 | ||
4ba0dea5 GR |
12811 | /* Hardware does not support aging addresses so if a |
12812 | * ndm_state is given only allow permanent addresses | |
12813 | */ | |
12814 | if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) { | |
12815 | netdev_info(dev, "FDB only supports static addresses\n"); | |
12816 | return -EINVAL; | |
12817 | } | |
12818 | ||
12819 | if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) | |
12820 | err = dev_uc_add_excl(dev, addr); | |
12821 | else if (is_multicast_ether_addr(addr)) | |
12822 | err = dev_mc_add_excl(dev, addr); | |
12823 | else | |
12824 | err = -EINVAL; | |
12825 | ||
12826 | /* Only return duplicate errors if NLM_F_EXCL is set */ | |
12827 | if (err == -EEXIST && !(flags & NLM_F_EXCL)) | |
12828 | err = 0; | |
12829 | ||
12830 | return err; | |
12831 | } | |
12832 | ||
51616018 NP |
12833 | /** |
12834 | * i40e_ndo_bridge_setlink - Set the hardware bridge mode | |
12835 | * @dev: the netdev being configured | |
12836 | * @nlh: RTNL message | |
f5254429 | 12837 | * @flags: bridge flags |
2fd527b7 | 12838 | * @extack: netlink extended ack |
51616018 NP |
12839 | * |
12840 | * Inserts a new hardware bridge if not already created and | |
12841 | * enables the bridging mode requested (VEB or VEPA). If the | |
12842 | * hardware bridge has already been inserted and the request | |
12843 | * is to change the mode then that requires a PF reset to | |
12844 | * allow rebuild of the components with required hardware | |
12845 | * bridge mode enabled. | |
373149fc MS |
12846 | * |
12847 | * Note: expects to be called while under rtnl_lock() | |
51616018 NP |
12848 | **/ |
12849 | static int i40e_ndo_bridge_setlink(struct net_device *dev, | |
9df70b66 | 12850 | struct nlmsghdr *nlh, |
2fd527b7 PM |
12851 | u16 flags, |
12852 | struct netlink_ext_ack *extack) | |
51616018 NP |
12853 | { |
12854 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
12855 | struct i40e_vsi *vsi = np->vsi; | |
12856 | struct i40e_pf *pf = vsi->back; | |
12857 | struct i40e_veb *veb = NULL; | |
12858 | struct nlattr *attr, *br_spec; | |
12859 | int i, rem; | |
12860 | ||
12861 | /* Only for PF VSI for now */ | |
12862 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) | |
12863 | return -EOPNOTSUPP; | |
12864 | ||
12865 | /* Find the HW bridge for PF VSI */ | |
12866 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { | |
12867 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
12868 | veb = pf->veb[i]; | |
12869 | } | |
12870 | ||
12871 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
12872 | ||
12873 | nla_for_each_nested(attr, br_spec, rem) { | |
12874 | __u16 mode; | |
12875 | ||
12876 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
12877 | continue; | |
12878 | ||
12879 | mode = nla_get_u16(attr); | |
12880 | if ((mode != BRIDGE_MODE_VEPA) && | |
12881 | (mode != BRIDGE_MODE_VEB)) | |
12882 | return -EINVAL; | |
12883 | ||
12884 | /* Insert a new HW bridge */ | |
12885 | if (!veb) { | |
12886 | veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, | |
12887 | vsi->tc_config.enabled_tc); | |
12888 | if (veb) { | |
12889 | veb->bridge_mode = mode; | |
12890 | i40e_config_bridge_mode(veb); | |
12891 | } else { | |
12892 | /* No Bridge HW offload available */ | |
12893 | return -ENOENT; | |
12894 | } | |
12895 | break; | |
12896 | } else if (mode != veb->bridge_mode) { | |
12897 | /* Existing HW bridge but different mode needs reset */ | |
12898 | veb->bridge_mode = mode; | |
fc60861e ASJ |
12899 | /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */ |
12900 | if (mode == BRIDGE_MODE_VEB) | |
12901 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
12902 | else | |
12903 | pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; | |
ff424188 | 12904 | i40e_do_reset(pf, I40E_PF_RESET_FLAG, true); |
51616018 NP |
12905 | break; |
12906 | } | |
12907 | } | |
12908 | ||
12909 | return 0; | |
12910 | } | |
12911 | ||
12912 | /** | |
12913 | * i40e_ndo_bridge_getlink - Get the hardware bridge mode | |
12914 | * @skb: skb buff | |
12915 | * @pid: process id | |
12916 | * @seq: RTNL message seq # | |
12917 | * @dev: the netdev being configured | |
12918 | * @filter_mask: unused | |
d4b2f9fe | 12919 | * @nlflags: netlink flags passed in |
51616018 NP |
12920 | * |
12921 | * Return the mode in which the hardware bridge is operating in | |
12922 | * i.e VEB or VEPA. | |
12923 | **/ | |
51616018 NP |
12924 | static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, |
12925 | struct net_device *dev, | |
9f4ffc44 CW |
12926 | u32 __always_unused filter_mask, |
12927 | int nlflags) | |
51616018 NP |
12928 | { |
12929 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
12930 | struct i40e_vsi *vsi = np->vsi; | |
12931 | struct i40e_pf *pf = vsi->back; | |
12932 | struct i40e_veb *veb = NULL; | |
12933 | int i; | |
12934 | ||
12935 | /* Only for PF VSI for now */ | |
12936 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) | |
12937 | return -EOPNOTSUPP; | |
12938 | ||
12939 | /* Find the HW bridge for the PF VSI */ | |
12940 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { | |
12941 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
12942 | veb = pf->veb[i]; | |
12943 | } | |
12944 | ||
12945 | if (!veb) | |
12946 | return 0; | |
12947 | ||
46c264da | 12948 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode, |
599b076d | 12949 | 0, 0, nlflags, filter_mask, NULL); |
51616018 | 12950 | } |
51616018 | 12951 | |
f44a75e2 JS |
12952 | /** |
12953 | * i40e_features_check - Validate encapsulated packet conforms to limits | |
12954 | * @skb: skb buff | |
2bc11c63 | 12955 | * @dev: This physical port's netdev |
f44a75e2 JS |
12956 | * @features: Offload features that the stack believes apply |
12957 | **/ | |
12958 | static netdev_features_t i40e_features_check(struct sk_buff *skb, | |
12959 | struct net_device *dev, | |
12960 | netdev_features_t features) | |
12961 | { | |
f114dca2 AD |
12962 | size_t len; |
12963 | ||
12964 | /* No point in doing any of this if neither checksum nor GSO are | |
12965 | * being requested for this frame. We can rule out both by just | |
12966 | * checking for CHECKSUM_PARTIAL | |
12967 | */ | |
12968 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
12969 | return features; | |
12970 | ||
12971 | /* We cannot support GSO if the MSS is going to be less than | |
12972 | * 64 bytes. If it is then we need to drop support for GSO. | |
12973 | */ | |
12974 | if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_size < 64)) | |
12975 | features &= ~NETIF_F_GSO_MASK; | |
12976 | ||
12977 | /* MACLEN can support at most 63 words */ | |
12978 | len = skb_network_header(skb) - skb->data; | |
12979 | if (len & ~(63 * 2)) | |
12980 | goto out_err; | |
12981 | ||
12982 | /* IPLEN and EIPLEN can support at most 127 dwords */ | |
12983 | len = skb_transport_header(skb) - skb_network_header(skb); | |
12984 | if (len & ~(127 * 4)) | |
12985 | goto out_err; | |
12986 | ||
12987 | if (skb->encapsulation) { | |
12988 | /* L4TUNLEN can support 127 words */ | |
12989 | len = skb_inner_network_header(skb) - skb_transport_header(skb); | |
12990 | if (len & ~(127 * 2)) | |
12991 | goto out_err; | |
12992 | ||
12993 | /* IPLEN can support at most 127 dwords */ | |
12994 | len = skb_inner_transport_header(skb) - | |
12995 | skb_inner_network_header(skb); | |
12996 | if (len & ~(127 * 4)) | |
12997 | goto out_err; | |
12998 | } | |
12999 | ||
13000 | /* No need to validate L4LEN as TCP is the only protocol with a | |
13001 | * a flexible value and we support all possible values supported | |
13002 | * by TCP, which is at most 15 dwords | |
13003 | */ | |
f44a75e2 JS |
13004 | |
13005 | return features; | |
f114dca2 AD |
13006 | out_err: |
13007 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
f44a75e2 JS |
13008 | } |
13009 | ||
0c8493d9 BT |
13010 | /** |
13011 | * i40e_xdp_setup - add/remove an XDP program | |
13012 | * @vsi: VSI to changed | |
13013 | * @prog: XDP program | |
613142b0 | 13014 | * @extack: netlink extended ack |
0c8493d9 | 13015 | **/ |
613142b0 ER |
13016 | static int i40e_xdp_setup(struct i40e_vsi *vsi, struct bpf_prog *prog, |
13017 | struct netlink_ext_ack *extack) | |
0c8493d9 BT |
13018 | { |
13019 | int frame_size = vsi->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
13020 | struct i40e_pf *pf = vsi->back; | |
13021 | struct bpf_prog *old_prog; | |
13022 | bool need_reset; | |
13023 | int i; | |
13024 | ||
13025 | /* Don't allow frames that span over multiple buffers */ | |
613142b0 ER |
13026 | if (frame_size > vsi->rx_buf_len) { |
13027 | NL_SET_ERR_MSG_MOD(extack, "MTU too large to enable XDP"); | |
0c8493d9 | 13028 | return -EINVAL; |
613142b0 | 13029 | } |
0c8493d9 | 13030 | |
0c8493d9 BT |
13031 | /* When turning XDP on->off/off->on we reset and rebuild the rings. */ |
13032 | need_reset = (i40e_enabled_xdp_vsi(vsi) != !!prog); | |
13033 | ||
13034 | if (need_reset) | |
4b208eaa | 13035 | i40e_prep_for_reset(pf); |
0c8493d9 BT |
13036 | |
13037 | old_prog = xchg(&vsi->xdp_prog, prog); | |
13038 | ||
b3873a5b MM |
13039 | if (need_reset) { |
13040 | if (!prog) | |
13041 | /* Wait until ndo_xsk_wakeup completes. */ | |
13042 | synchronize_rcu(); | |
0c8493d9 | 13043 | i40e_reset_and_rebuild(pf, true, true); |
b3873a5b | 13044 | } |
0c8493d9 BT |
13045 | |
13046 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
13047 | WRITE_ONCE(vsi->rx_rings[i]->xdp_prog, vsi->xdp_prog); | |
13048 | ||
13049 | if (old_prog) | |
13050 | bpf_prog_put(old_prog); | |
13051 | ||
14ffeb52 MK |
13052 | /* Kick start the NAPI context if there is an AF_XDP socket open |
13053 | * on that queue id. This so that receiving will start. | |
13054 | */ | |
13055 | if (need_reset && prog) | |
13056 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
1742b3d5 | 13057 | if (vsi->xdp_rings[i]->xsk_pool) |
9116e5e2 MK |
13058 | (void)i40e_xsk_wakeup(vsi->netdev, i, |
13059 | XDP_WAKEUP_RX); | |
14ffeb52 | 13060 | |
0c8493d9 BT |
13061 | return 0; |
13062 | } | |
13063 | ||
123cecd4 BT |
13064 | /** |
13065 | * i40e_enter_busy_conf - Enters busy config state | |
13066 | * @vsi: vsi | |
13067 | * | |
13068 | * Returns 0 on success, <0 for failure. | |
13069 | **/ | |
13070 | static int i40e_enter_busy_conf(struct i40e_vsi *vsi) | |
13071 | { | |
13072 | struct i40e_pf *pf = vsi->back; | |
13073 | int timeout = 50; | |
13074 | ||
13075 | while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) { | |
13076 | timeout--; | |
13077 | if (!timeout) | |
13078 | return -EBUSY; | |
13079 | usleep_range(1000, 2000); | |
13080 | } | |
13081 | ||
13082 | return 0; | |
13083 | } | |
13084 | ||
13085 | /** | |
13086 | * i40e_exit_busy_conf - Exits busy config state | |
13087 | * @vsi: vsi | |
13088 | **/ | |
13089 | static void i40e_exit_busy_conf(struct i40e_vsi *vsi) | |
13090 | { | |
13091 | struct i40e_pf *pf = vsi->back; | |
13092 | ||
13093 | clear_bit(__I40E_CONFIG_BUSY, pf->state); | |
13094 | } | |
13095 | ||
13096 | /** | |
13097 | * i40e_queue_pair_reset_stats - Resets all statistics for a queue pair | |
13098 | * @vsi: vsi | |
13099 | * @queue_pair: queue pair | |
13100 | **/ | |
13101 | static void i40e_queue_pair_reset_stats(struct i40e_vsi *vsi, int queue_pair) | |
13102 | { | |
13103 | memset(&vsi->rx_rings[queue_pair]->rx_stats, 0, | |
13104 | sizeof(vsi->rx_rings[queue_pair]->rx_stats)); | |
13105 | memset(&vsi->tx_rings[queue_pair]->stats, 0, | |
13106 | sizeof(vsi->tx_rings[queue_pair]->stats)); | |
13107 | if (i40e_enabled_xdp_vsi(vsi)) { | |
13108 | memset(&vsi->xdp_rings[queue_pair]->stats, 0, | |
13109 | sizeof(vsi->xdp_rings[queue_pair]->stats)); | |
13110 | } | |
13111 | } | |
13112 | ||
13113 | /** | |
13114 | * i40e_queue_pair_clean_rings - Cleans all the rings of a queue pair | |
13115 | * @vsi: vsi | |
13116 | * @queue_pair: queue pair | |
13117 | **/ | |
13118 | static void i40e_queue_pair_clean_rings(struct i40e_vsi *vsi, int queue_pair) | |
13119 | { | |
13120 | i40e_clean_tx_ring(vsi->tx_rings[queue_pair]); | |
59eb2a88 BT |
13121 | if (i40e_enabled_xdp_vsi(vsi)) { |
13122 | /* Make sure that in-progress ndo_xdp_xmit calls are | |
13123 | * completed. | |
13124 | */ | |
13125 | synchronize_rcu(); | |
123cecd4 | 13126 | i40e_clean_tx_ring(vsi->xdp_rings[queue_pair]); |
59eb2a88 | 13127 | } |
123cecd4 BT |
13128 | i40e_clean_rx_ring(vsi->rx_rings[queue_pair]); |
13129 | } | |
13130 | ||
13131 | /** | |
13132 | * i40e_queue_pair_toggle_napi - Enables/disables NAPI for a queue pair | |
13133 | * @vsi: vsi | |
13134 | * @queue_pair: queue pair | |
13135 | * @enable: true for enable, false for disable | |
13136 | **/ | |
13137 | static void i40e_queue_pair_toggle_napi(struct i40e_vsi *vsi, int queue_pair, | |
13138 | bool enable) | |
13139 | { | |
13140 | struct i40e_ring *rxr = vsi->rx_rings[queue_pair]; | |
13141 | struct i40e_q_vector *q_vector = rxr->q_vector; | |
13142 | ||
13143 | if (!vsi->netdev) | |
13144 | return; | |
13145 | ||
13146 | /* All rings in a qp belong to the same qvector. */ | |
13147 | if (q_vector->rx.ring || q_vector->tx.ring) { | |
13148 | if (enable) | |
13149 | napi_enable(&q_vector->napi); | |
13150 | else | |
13151 | napi_disable(&q_vector->napi); | |
13152 | } | |
13153 | } | |
13154 | ||
13155 | /** | |
13156 | * i40e_queue_pair_toggle_rings - Enables/disables all rings for a queue pair | |
13157 | * @vsi: vsi | |
13158 | * @queue_pair: queue pair | |
13159 | * @enable: true for enable, false for disable | |
13160 | * | |
13161 | * Returns 0 on success, <0 on failure. | |
13162 | **/ | |
13163 | static int i40e_queue_pair_toggle_rings(struct i40e_vsi *vsi, int queue_pair, | |
13164 | bool enable) | |
13165 | { | |
13166 | struct i40e_pf *pf = vsi->back; | |
13167 | int pf_q, ret = 0; | |
13168 | ||
13169 | pf_q = vsi->base_queue + queue_pair; | |
13170 | ret = i40e_control_wait_tx_q(vsi->seid, pf, pf_q, | |
13171 | false /*is xdp*/, enable); | |
13172 | if (ret) { | |
13173 | dev_info(&pf->pdev->dev, | |
13174 | "VSI seid %d Tx ring %d %sable timeout\n", | |
13175 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
13176 | return ret; | |
13177 | } | |
13178 | ||
13179 | i40e_control_rx_q(pf, pf_q, enable); | |
13180 | ret = i40e_pf_rxq_wait(pf, pf_q, enable); | |
13181 | if (ret) { | |
13182 | dev_info(&pf->pdev->dev, | |
13183 | "VSI seid %d Rx ring %d %sable timeout\n", | |
13184 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
13185 | return ret; | |
13186 | } | |
13187 | ||
13188 | /* Due to HW errata, on Rx disable only, the register can | |
13189 | * indicate done before it really is. Needs 50ms to be sure | |
13190 | */ | |
13191 | if (!enable) | |
13192 | mdelay(50); | |
13193 | ||
13194 | if (!i40e_enabled_xdp_vsi(vsi)) | |
13195 | return ret; | |
13196 | ||
13197 | ret = i40e_control_wait_tx_q(vsi->seid, pf, | |
13198 | pf_q + vsi->alloc_queue_pairs, | |
13199 | true /*is xdp*/, enable); | |
13200 | if (ret) { | |
13201 | dev_info(&pf->pdev->dev, | |
13202 | "VSI seid %d XDP Tx ring %d %sable timeout\n", | |
13203 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
13204 | } | |
13205 | ||
13206 | return ret; | |
13207 | } | |
13208 | ||
13209 | /** | |
13210 | * i40e_queue_pair_enable_irq - Enables interrupts for a queue pair | |
13211 | * @vsi: vsi | |
13212 | * @queue_pair: queue_pair | |
13213 | **/ | |
13214 | static void i40e_queue_pair_enable_irq(struct i40e_vsi *vsi, int queue_pair) | |
13215 | { | |
13216 | struct i40e_ring *rxr = vsi->rx_rings[queue_pair]; | |
13217 | struct i40e_pf *pf = vsi->back; | |
13218 | struct i40e_hw *hw = &pf->hw; | |
13219 | ||
13220 | /* All rings in a qp belong to the same qvector. */ | |
13221 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
13222 | i40e_irq_dynamic_enable(vsi, rxr->q_vector->v_idx); | |
13223 | else | |
13224 | i40e_irq_dynamic_enable_icr0(pf); | |
13225 | ||
13226 | i40e_flush(hw); | |
13227 | } | |
13228 | ||
13229 | /** | |
13230 | * i40e_queue_pair_disable_irq - Disables interrupts for a queue pair | |
13231 | * @vsi: vsi | |
13232 | * @queue_pair: queue_pair | |
13233 | **/ | |
13234 | static void i40e_queue_pair_disable_irq(struct i40e_vsi *vsi, int queue_pair) | |
13235 | { | |
13236 | struct i40e_ring *rxr = vsi->rx_rings[queue_pair]; | |
13237 | struct i40e_pf *pf = vsi->back; | |
13238 | struct i40e_hw *hw = &pf->hw; | |
13239 | ||
13240 | /* For simplicity, instead of removing the qp interrupt causes | |
13241 | * from the interrupt linked list, we simply disable the interrupt, and | |
13242 | * leave the list intact. | |
13243 | * | |
13244 | * All rings in a qp belong to the same qvector. | |
13245 | */ | |
13246 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
13247 | u32 intpf = vsi->base_vector + rxr->q_vector->v_idx; | |
13248 | ||
13249 | wr32(hw, I40E_PFINT_DYN_CTLN(intpf - 1), 0); | |
13250 | i40e_flush(hw); | |
13251 | synchronize_irq(pf->msix_entries[intpf].vector); | |
13252 | } else { | |
13253 | /* Legacy and MSI mode - this stops all interrupt handling */ | |
13254 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); | |
13255 | wr32(hw, I40E_PFINT_DYN_CTL0, 0); | |
13256 | i40e_flush(hw); | |
13257 | synchronize_irq(pf->pdev->irq); | |
13258 | } | |
13259 | } | |
13260 | ||
13261 | /** | |
13262 | * i40e_queue_pair_disable - Disables a queue pair | |
13263 | * @vsi: vsi | |
13264 | * @queue_pair: queue pair | |
13265 | * | |
13266 | * Returns 0 on success, <0 on failure. | |
13267 | **/ | |
13268 | int i40e_queue_pair_disable(struct i40e_vsi *vsi, int queue_pair) | |
13269 | { | |
13270 | int err; | |
13271 | ||
13272 | err = i40e_enter_busy_conf(vsi); | |
13273 | if (err) | |
13274 | return err; | |
13275 | ||
13276 | i40e_queue_pair_disable_irq(vsi, queue_pair); | |
13277 | err = i40e_queue_pair_toggle_rings(vsi, queue_pair, false /* off */); | |
13278 | i40e_queue_pair_toggle_napi(vsi, queue_pair, false /* off */); | |
13279 | i40e_queue_pair_clean_rings(vsi, queue_pair); | |
13280 | i40e_queue_pair_reset_stats(vsi, queue_pair); | |
13281 | ||
13282 | return err; | |
13283 | } | |
13284 | ||
13285 | /** | |
13286 | * i40e_queue_pair_enable - Enables a queue pair | |
13287 | * @vsi: vsi | |
13288 | * @queue_pair: queue pair | |
13289 | * | |
13290 | * Returns 0 on success, <0 on failure. | |
13291 | **/ | |
13292 | int i40e_queue_pair_enable(struct i40e_vsi *vsi, int queue_pair) | |
13293 | { | |
13294 | int err; | |
13295 | ||
13296 | err = i40e_configure_tx_ring(vsi->tx_rings[queue_pair]); | |
13297 | if (err) | |
13298 | return err; | |
13299 | ||
13300 | if (i40e_enabled_xdp_vsi(vsi)) { | |
13301 | err = i40e_configure_tx_ring(vsi->xdp_rings[queue_pair]); | |
13302 | if (err) | |
13303 | return err; | |
13304 | } | |
13305 | ||
13306 | err = i40e_configure_rx_ring(vsi->rx_rings[queue_pair]); | |
13307 | if (err) | |
13308 | return err; | |
13309 | ||
13310 | err = i40e_queue_pair_toggle_rings(vsi, queue_pair, true /* on */); | |
13311 | i40e_queue_pair_toggle_napi(vsi, queue_pair, true /* on */); | |
13312 | i40e_queue_pair_enable_irq(vsi, queue_pair); | |
13313 | ||
13314 | i40e_exit_busy_conf(vsi); | |
13315 | ||
13316 | return err; | |
13317 | } | |
13318 | ||
0c8493d9 | 13319 | /** |
f4e63525 | 13320 | * i40e_xdp - implements ndo_bpf for i40e |
0c8493d9 BT |
13321 | * @dev: netdevice |
13322 | * @xdp: XDP command | |
13323 | **/ | |
13324 | static int i40e_xdp(struct net_device *dev, | |
f4e63525 | 13325 | struct netdev_bpf *xdp) |
0c8493d9 BT |
13326 | { |
13327 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
13328 | struct i40e_vsi *vsi = np->vsi; | |
13329 | ||
13330 | if (vsi->type != I40E_VSI_MAIN) | |
13331 | return -EINVAL; | |
13332 | ||
13333 | switch (xdp->command) { | |
13334 | case XDP_SETUP_PROG: | |
613142b0 | 13335 | return i40e_xdp_setup(vsi, xdp->prog, xdp->extack); |
1742b3d5 MK |
13336 | case XDP_SETUP_XSK_POOL: |
13337 | return i40e_xsk_pool_setup(vsi, xdp->xsk.pool, | |
0a714186 | 13338 | xdp->xsk.queue_id); |
0c8493d9 BT |
13339 | default: |
13340 | return -EINVAL; | |
13341 | } | |
13342 | } | |
13343 | ||
37a2973a | 13344 | static const struct net_device_ops i40e_netdev_ops = { |
41c445ff JB |
13345 | .ndo_open = i40e_open, |
13346 | .ndo_stop = i40e_close, | |
13347 | .ndo_start_xmit = i40e_lan_xmit_frame, | |
13348 | .ndo_get_stats64 = i40e_get_netdev_stats_struct, | |
13349 | .ndo_set_rx_mode = i40e_set_rx_mode, | |
13350 | .ndo_validate_addr = eth_validate_addr, | |
13351 | .ndo_set_mac_address = i40e_set_mac, | |
13352 | .ndo_change_mtu = i40e_change_mtu, | |
a7605370 | 13353 | .ndo_eth_ioctl = i40e_ioctl, |
41c445ff JB |
13354 | .ndo_tx_timeout = i40e_tx_timeout, |
13355 | .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid, | |
13356 | .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid, | |
13357 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
13358 | .ndo_poll_controller = i40e_netpoll, | |
13359 | #endif | |
e4c6734e | 13360 | .ndo_setup_tc = __i40e_setup_tc, |
89ec1f08 | 13361 | .ndo_select_queue = i40e_lan_select_queue, |
41c445ff JB |
13362 | .ndo_set_features = i40e_set_features, |
13363 | .ndo_set_vf_mac = i40e_ndo_set_vf_mac, | |
13364 | .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan, | |
dc645dae | 13365 | .ndo_get_vf_stats = i40e_get_vf_stats, |
ed616689 | 13366 | .ndo_set_vf_rate = i40e_ndo_set_vf_bw, |
41c445ff | 13367 | .ndo_get_vf_config = i40e_ndo_get_vf_config, |
588aefa0 | 13368 | .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state, |
e6d9004d | 13369 | .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk, |
c3bbbd20 | 13370 | .ndo_set_vf_trust = i40e_ndo_set_vf_trust, |
1f224ad2 | 13371 | .ndo_get_phys_port_id = i40e_get_phys_port_id, |
4ba0dea5 | 13372 | .ndo_fdb_add = i40e_ndo_fdb_add, |
f44a75e2 | 13373 | .ndo_features_check = i40e_features_check, |
51616018 NP |
13374 | .ndo_bridge_getlink = i40e_ndo_bridge_getlink, |
13375 | .ndo_bridge_setlink = i40e_ndo_bridge_setlink, | |
f4e63525 | 13376 | .ndo_bpf = i40e_xdp, |
d9314c47 | 13377 | .ndo_xdp_xmit = i40e_xdp_xmit, |
9116e5e2 | 13378 | .ndo_xsk_wakeup = i40e_xsk_wakeup, |
1d8d80b4 HR |
13379 | .ndo_dfwd_add_station = i40e_fwd_add, |
13380 | .ndo_dfwd_del_station = i40e_fwd_del, | |
41c445ff JB |
13381 | }; |
13382 | ||
13383 | /** | |
13384 | * i40e_config_netdev - Setup the netdev flags | |
13385 | * @vsi: the VSI being configured | |
13386 | * | |
13387 | * Returns 0 on success, negative value on failure | |
13388 | **/ | |
13389 | static int i40e_config_netdev(struct i40e_vsi *vsi) | |
13390 | { | |
13391 | struct i40e_pf *pf = vsi->back; | |
13392 | struct i40e_hw *hw = &pf->hw; | |
13393 | struct i40e_netdev_priv *np; | |
13394 | struct net_device *netdev; | |
435c084a | 13395 | u8 broadcast[ETH_ALEN]; |
41c445ff JB |
13396 | u8 mac_addr[ETH_ALEN]; |
13397 | int etherdev_size; | |
bacd75cf PB |
13398 | netdev_features_t hw_enc_features; |
13399 | netdev_features_t hw_features; | |
41c445ff JB |
13400 | |
13401 | etherdev_size = sizeof(struct i40e_netdev_priv); | |
f8ff1464 | 13402 | netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs); |
41c445ff JB |
13403 | if (!netdev) |
13404 | return -ENOMEM; | |
13405 | ||
13406 | vsi->netdev = netdev; | |
13407 | np = netdev_priv(netdev); | |
13408 | np->vsi = vsi; | |
13409 | ||
bacd75cf PB |
13410 | hw_enc_features = NETIF_F_SG | |
13411 | NETIF_F_IP_CSUM | | |
13412 | NETIF_F_IPV6_CSUM | | |
13413 | NETIF_F_HIGHDMA | | |
13414 | NETIF_F_SOFT_FEATURES | | |
13415 | NETIF_F_TSO | | |
13416 | NETIF_F_TSO_ECN | | |
13417 | NETIF_F_TSO6 | | |
13418 | NETIF_F_GSO_GRE | | |
13419 | NETIF_F_GSO_GRE_CSUM | | |
13420 | NETIF_F_GSO_PARTIAL | | |
ba766b8b JK |
13421 | NETIF_F_GSO_IPXIP4 | |
13422 | NETIF_F_GSO_IPXIP6 | | |
bacd75cf PB |
13423 | NETIF_F_GSO_UDP_TUNNEL | |
13424 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
3fd8ed56 | 13425 | NETIF_F_GSO_UDP_L4 | |
bacd75cf PB |
13426 | NETIF_F_SCTP_CRC | |
13427 | NETIF_F_RXHASH | | |
13428 | NETIF_F_RXCSUM | | |
13429 | 0; | |
41c445ff | 13430 | |
d36e41dc | 13431 | if (!(pf->hw_features & I40E_HW_OUTER_UDP_CSUM_CAPABLE)) |
1c7b4a23 AD |
13432 | netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; |
13433 | ||
40a98cb6 JK |
13434 | netdev->udp_tunnel_nic_info = &pf->udp_tunnel_nic; |
13435 | ||
1c7b4a23 | 13436 | netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; |
b0fe3306 | 13437 | |
bacd75cf PB |
13438 | netdev->hw_enc_features |= hw_enc_features; |
13439 | ||
b0fe3306 | 13440 | /* record features VLANs can make use of */ |
bacd75cf | 13441 | netdev->vlan_features |= hw_enc_features | NETIF_F_TSO_MANGLEID; |
41c445ff | 13442 | |
1d8d80b4 HR |
13443 | /* enable macvlan offloads */ |
13444 | netdev->hw_features |= NETIF_F_HW_L2FW_DOFFLOAD; | |
13445 | ||
bacd75cf PB |
13446 | hw_features = hw_enc_features | |
13447 | NETIF_F_HW_VLAN_CTAG_TX | | |
13448 | NETIF_F_HW_VLAN_CTAG_RX; | |
b0fe3306 | 13449 | |
d5596fd4 JK |
13450 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) |
13451 | hw_features |= NETIF_F_NTUPLE | NETIF_F_HW_TC; | |
13452 | ||
bacd75cf | 13453 | netdev->hw_features |= hw_features; |
2e86a0b6 | 13454 | |
bacd75cf | 13455 | netdev->features |= hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; |
1c7b4a23 | 13456 | netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; |
41c445ff JB |
13457 | |
13458 | if (vsi->type == I40E_VSI_MAIN) { | |
13459 | SET_NETDEV_DEV(netdev, &pf->pdev->dev); | |
9a173901 | 13460 | ether_addr_copy(mac_addr, hw->mac.perm_addr); |
41c4c2b5 JK |
13461 | /* The following steps are necessary for two reasons. First, |
13462 | * some older NVM configurations load a default MAC-VLAN | |
13463 | * filter that will accept any tagged packet, and we want to | |
13464 | * replace this with a normal filter. Additionally, it is | |
13465 | * possible our MAC address was provided by the platform using | |
13466 | * Open Firmware or similar. | |
13467 | * | |
13468 | * Thus, we need to remove the default filter and install one | |
13469 | * specific to the MAC address. | |
1596b5dd JK |
13470 | */ |
13471 | i40e_rm_default_mac_filter(vsi, mac_addr); | |
278e7d0b | 13472 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
9569a9a4 | 13473 | i40e_add_mac_filter(vsi, mac_addr); |
278e7d0b | 13474 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 13475 | } else { |
8c9eb350 JK |
13476 | /* Relate the VSI_VMDQ name to the VSI_MAIN name. Note that we |
13477 | * are still limited by IFNAMSIZ, but we're adding 'v%d\0' to | |
13478 | * the end, which is 4 bytes long, so force truncation of the | |
13479 | * original name by IFNAMSIZ - 4 | |
13480 | */ | |
13481 | snprintf(netdev->name, IFNAMSIZ, "%.*sv%%d", | |
13482 | IFNAMSIZ - 4, | |
41c445ff | 13483 | pf->vsi[pf->lan_vsi]->netdev->name); |
6c1f0a1f | 13484 | eth_random_addr(mac_addr); |
21659035 | 13485 | |
278e7d0b | 13486 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
9569a9a4 | 13487 | i40e_add_mac_filter(vsi, mac_addr); |
278e7d0b | 13488 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 13489 | } |
21659035 | 13490 | |
435c084a JK |
13491 | /* Add the broadcast filter so that we initially will receive |
13492 | * broadcast packets. Note that when a new VLAN is first added the | |
13493 | * driver will convert all filters marked I40E_VLAN_ANY into VLAN | |
13494 | * specific filters as part of transitioning into "vlan" operation. | |
13495 | * When more VLANs are added, the driver will copy each existing MAC | |
13496 | * filter and add it for the new VLAN. | |
13497 | * | |
13498 | * Broadcast filters are handled specially by | |
13499 | * i40e_sync_filters_subtask, as the driver must to set the broadcast | |
13500 | * promiscuous bit instead of adding this directly as a MAC/VLAN | |
13501 | * filter. The subtask will update the correct broadcast promiscuous | |
13502 | * bits as VLANs become active or inactive. | |
13503 | */ | |
13504 | eth_broadcast_addr(broadcast); | |
13505 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
9569a9a4 | 13506 | i40e_add_mac_filter(vsi, broadcast); |
435c084a JK |
13507 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
13508 | ||
f3956ebb | 13509 | eth_hw_addr_set(netdev, mac_addr); |
9a173901 | 13510 | ether_addr_copy(netdev->perm_addr, mac_addr); |
b0fe3306 | 13511 | |
31389b53 KK |
13512 | /* i40iw_net_event() reads 16 bytes from neigh->primary_key */ |
13513 | netdev->neigh_priv_len = sizeof(u32) * 4; | |
13514 | ||
41c445ff JB |
13515 | netdev->priv_flags |= IFF_UNICAST_FLT; |
13516 | netdev->priv_flags |= IFF_SUPP_NOFCS; | |
13517 | /* Setup netdev TC information */ | |
13518 | i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc); | |
13519 | ||
13520 | netdev->netdev_ops = &i40e_netdev_ops; | |
13521 | netdev->watchdog_timeo = 5 * HZ; | |
13522 | i40e_set_ethtool_ops(netdev); | |
13523 | ||
91c527a5 JW |
13524 | /* MTU range: 68 - 9706 */ |
13525 | netdev->min_mtu = ETH_MIN_MTU; | |
1e3a5fd5 | 13526 | netdev->max_mtu = I40E_MAX_RXBUFFER - I40E_PACKET_HDR_PAD; |
91c527a5 | 13527 | |
41c445ff JB |
13528 | return 0; |
13529 | } | |
13530 | ||
13531 | /** | |
13532 | * i40e_vsi_delete - Delete a VSI from the switch | |
13533 | * @vsi: the VSI being removed | |
13534 | * | |
13535 | * Returns 0 on success, negative value on failure | |
13536 | **/ | |
13537 | static void i40e_vsi_delete(struct i40e_vsi *vsi) | |
13538 | { | |
13539 | /* remove default VSI is not allowed */ | |
13540 | if (vsi == vsi->back->vsi[vsi->back->lan_vsi]) | |
13541 | return; | |
13542 | ||
41c445ff | 13543 | i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL); |
41c445ff JB |
13544 | } |
13545 | ||
51616018 NP |
13546 | /** |
13547 | * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB | |
13548 | * @vsi: the VSI being queried | |
13549 | * | |
13550 | * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode | |
13551 | **/ | |
13552 | int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi) | |
13553 | { | |
13554 | struct i40e_veb *veb; | |
13555 | struct i40e_pf *pf = vsi->back; | |
13556 | ||
13557 | /* Uplink is not a bridge so default to VEB */ | |
f031c722 | 13558 | if (vsi->veb_idx >= I40E_MAX_VEB) |
51616018 NP |
13559 | return 1; |
13560 | ||
13561 | veb = pf->veb[vsi->veb_idx]; | |
09603eaa AA |
13562 | if (!veb) { |
13563 | dev_info(&pf->pdev->dev, | |
13564 | "There is no veb associated with the bridge\n"); | |
13565 | return -ENOENT; | |
13566 | } | |
13567 | ||
51616018 | 13568 | /* Uplink is a bridge in VEPA mode */ |
09603eaa | 13569 | if (veb->bridge_mode & BRIDGE_MODE_VEPA) { |
51616018 | 13570 | return 0; |
09603eaa AA |
13571 | } else { |
13572 | /* Uplink is a bridge in VEB mode */ | |
13573 | return 1; | |
13574 | } | |
51616018 | 13575 | |
09603eaa AA |
13576 | /* VEPA is now default bridge, so return 0 */ |
13577 | return 0; | |
51616018 NP |
13578 | } |
13579 | ||
41c445ff JB |
13580 | /** |
13581 | * i40e_add_vsi - Add a VSI to the switch | |
13582 | * @vsi: the VSI being configured | |
13583 | * | |
13584 | * This initializes a VSI context depending on the VSI type to be added and | |
13585 | * passes it down to the add_vsi aq command. | |
13586 | **/ | |
13587 | static int i40e_add_vsi(struct i40e_vsi *vsi) | |
13588 | { | |
13589 | int ret = -ENODEV; | |
41c445ff JB |
13590 | struct i40e_pf *pf = vsi->back; |
13591 | struct i40e_hw *hw = &pf->hw; | |
13592 | struct i40e_vsi_context ctxt; | |
278e7d0b JK |
13593 | struct i40e_mac_filter *f; |
13594 | struct hlist_node *h; | |
13595 | int bkt; | |
21659035 | 13596 | |
41c445ff JB |
13597 | u8 enabled_tc = 0x1; /* TC0 enabled */ |
13598 | int f_count = 0; | |
13599 | ||
13600 | memset(&ctxt, 0, sizeof(ctxt)); | |
13601 | switch (vsi->type) { | |
13602 | case I40E_VSI_MAIN: | |
13603 | /* The PF's main VSI is already setup as part of the | |
13604 | * device initialization, so we'll not bother with | |
13605 | * the add_vsi call, but we will retrieve the current | |
13606 | * VSI context. | |
13607 | */ | |
13608 | ctxt.seid = pf->main_vsi_seid; | |
13609 | ctxt.pf_num = pf->hw.pf_id; | |
13610 | ctxt.vf_num = 0; | |
13611 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); | |
13612 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
13613 | if (ret) { | |
13614 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
13615 | "couldn't get PF vsi config, err %s aq_err %s\n", |
13616 | i40e_stat_str(&pf->hw, ret), | |
13617 | i40e_aq_str(&pf->hw, | |
13618 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
13619 | return -ENOENT; |
13620 | } | |
1a2f6248 | 13621 | vsi->info = ctxt.info; |
41c445ff JB |
13622 | vsi->info.valid_sections = 0; |
13623 | ||
13624 | vsi->seid = ctxt.seid; | |
13625 | vsi->id = ctxt.vsi_number; | |
13626 | ||
13627 | enabled_tc = i40e_pf_get_tc_map(pf); | |
13628 | ||
64615b54 MW |
13629 | /* Source pruning is enabled by default, so the flag is |
13630 | * negative logic - if it's set, we need to fiddle with | |
13631 | * the VSI to disable source pruning. | |
13632 | */ | |
13633 | if (pf->flags & I40E_FLAG_SOURCE_PRUNING_DISABLED) { | |
13634 | memset(&ctxt, 0, sizeof(ctxt)); | |
13635 | ctxt.seid = pf->main_vsi_seid; | |
13636 | ctxt.pf_num = pf->hw.pf_id; | |
13637 | ctxt.vf_num = 0; | |
13638 | ctxt.info.valid_sections |= | |
13639 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
13640 | ctxt.info.switch_id = | |
13641 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB); | |
13642 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); | |
13643 | if (ret) { | |
13644 | dev_info(&pf->pdev->dev, | |
13645 | "update vsi failed, err %s aq_err %s\n", | |
13646 | i40e_stat_str(&pf->hw, ret), | |
13647 | i40e_aq_str(&pf->hw, | |
13648 | pf->hw.aq.asq_last_status)); | |
13649 | ret = -ENOENT; | |
13650 | goto err; | |
13651 | } | |
13652 | } | |
13653 | ||
41c445ff | 13654 | /* MFP mode setup queue map and update VSI */ |
63d7e5a4 NP |
13655 | if ((pf->flags & I40E_FLAG_MFP_ENABLED) && |
13656 | !(pf->hw.func_caps.iscsi)) { /* NIC type PF */ | |
41c445ff JB |
13657 | memset(&ctxt, 0, sizeof(ctxt)); |
13658 | ctxt.seid = pf->main_vsi_seid; | |
13659 | ctxt.pf_num = pf->hw.pf_id; | |
13660 | ctxt.vf_num = 0; | |
13661 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); | |
13662 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); | |
13663 | if (ret) { | |
13664 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
13665 | "update vsi failed, err %s aq_err %s\n", |
13666 | i40e_stat_str(&pf->hw, ret), | |
13667 | i40e_aq_str(&pf->hw, | |
13668 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
13669 | ret = -ENOENT; |
13670 | goto err; | |
13671 | } | |
13672 | /* update the local VSI info queue map */ | |
13673 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
13674 | vsi->info.valid_sections = 0; | |
13675 | } else { | |
13676 | /* Default/Main VSI is only enabled for TC0 | |
13677 | * reconfigure it to enable all TCs that are | |
13678 | * available on the port in SFP mode. | |
63d7e5a4 NP |
13679 | * For MFP case the iSCSI PF would use this |
13680 | * flow to enable LAN+iSCSI TC. | |
41c445ff JB |
13681 | */ |
13682 | ret = i40e_vsi_config_tc(vsi, enabled_tc); | |
13683 | if (ret) { | |
19279235 CW |
13684 | /* Single TC condition is not fatal, |
13685 | * message and continue | |
13686 | */ | |
41c445ff | 13687 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
13688 | "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n", |
13689 | enabled_tc, | |
13690 | i40e_stat_str(&pf->hw, ret), | |
13691 | i40e_aq_str(&pf->hw, | |
13692 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
13693 | } |
13694 | } | |
13695 | break; | |
13696 | ||
13697 | case I40E_VSI_FDIR: | |
cbf61325 ASJ |
13698 | ctxt.pf_num = hw->pf_id; |
13699 | ctxt.vf_num = 0; | |
13700 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 13701 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
cbf61325 | 13702 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; |
fc60861e ASJ |
13703 | if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) && |
13704 | (i40e_is_vsi_uplink_mode_veb(vsi))) { | |
51616018 | 13705 | ctxt.info.valid_sections |= |
fc60861e | 13706 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); |
51616018 | 13707 | ctxt.info.switch_id = |
fc60861e | 13708 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); |
51616018 | 13709 | } |
41c445ff | 13710 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); |
41c445ff JB |
13711 | break; |
13712 | ||
13713 | case I40E_VSI_VMDQ2: | |
13714 | ctxt.pf_num = hw->pf_id; | |
13715 | ctxt.vf_num = 0; | |
13716 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 13717 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
41c445ff JB |
13718 | ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; |
13719 | ||
41c445ff JB |
13720 | /* This VSI is connected to VEB so the switch_id |
13721 | * should be set to zero by default. | |
13722 | */ | |
51616018 NP |
13723 | if (i40e_is_vsi_uplink_mode_veb(vsi)) { |
13724 | ctxt.info.valid_sections |= | |
13725 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
13726 | ctxt.info.switch_id = | |
13727 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
13728 | } | |
41c445ff JB |
13729 | |
13730 | /* Setup the VSI tx/rx queue map for TC0 only for now */ | |
13731 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); | |
13732 | break; | |
13733 | ||
13734 | case I40E_VSI_SRIOV: | |
13735 | ctxt.pf_num = hw->pf_id; | |
13736 | ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id; | |
13737 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 13738 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
41c445ff JB |
13739 | ctxt.flags = I40E_AQ_VSI_TYPE_VF; |
13740 | ||
41c445ff JB |
13741 | /* This VSI is connected to VEB so the switch_id |
13742 | * should be set to zero by default. | |
13743 | */ | |
51616018 NP |
13744 | if (i40e_is_vsi_uplink_mode_veb(vsi)) { |
13745 | ctxt.info.valid_sections |= | |
13746 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
13747 | ctxt.info.switch_id = | |
13748 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
13749 | } | |
41c445ff | 13750 | |
e3219ce6 ASJ |
13751 | if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { |
13752 | ctxt.info.valid_sections |= | |
13753 | cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); | |
13754 | ctxt.info.queueing_opt_flags |= | |
4b28cdba AS |
13755 | (I40E_AQ_VSI_QUE_OPT_TCP_ENA | |
13756 | I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI); | |
e3219ce6 ASJ |
13757 | } |
13758 | ||
41c445ff JB |
13759 | ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); |
13760 | ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; | |
c674d125 MW |
13761 | if (pf->vf[vsi->vf_id].spoofchk) { |
13762 | ctxt.info.valid_sections |= | |
13763 | cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID); | |
13764 | ctxt.info.sec_flags |= | |
13765 | (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK | | |
13766 | I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK); | |
13767 | } | |
41c445ff JB |
13768 | /* Setup the VSI tx/rx queue map for TC0 only for now */ |
13769 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); | |
13770 | break; | |
13771 | ||
e3219ce6 ASJ |
13772 | case I40E_VSI_IWARP: |
13773 | /* send down message to iWARP */ | |
13774 | break; | |
13775 | ||
41c445ff JB |
13776 | default: |
13777 | return -ENODEV; | |
13778 | } | |
13779 | ||
13780 | if (vsi->type != I40E_VSI_MAIN) { | |
13781 | ret = i40e_aq_add_vsi(hw, &ctxt, NULL); | |
13782 | if (ret) { | |
13783 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
13784 | "add vsi failed, err %s aq_err %s\n", |
13785 | i40e_stat_str(&pf->hw, ret), | |
13786 | i40e_aq_str(&pf->hw, | |
13787 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
13788 | ret = -ENOENT; |
13789 | goto err; | |
13790 | } | |
1a2f6248 | 13791 | vsi->info = ctxt.info; |
41c445ff JB |
13792 | vsi->info.valid_sections = 0; |
13793 | vsi->seid = ctxt.seid; | |
13794 | vsi->id = ctxt.vsi_number; | |
13795 | } | |
13796 | ||
c3c7ea27 | 13797 | vsi->active_filters = 0; |
0da36b97 | 13798 | clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
278e7d0b | 13799 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 13800 | /* If macvlan filters already exist, force them to get loaded */ |
278e7d0b | 13801 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
c3c7ea27 | 13802 | f->state = I40E_FILTER_NEW; |
41c445ff | 13803 | f_count++; |
21659035 | 13804 | } |
278e7d0b | 13805 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
30650cc5 | 13806 | |
41c445ff JB |
13807 | if (f_count) { |
13808 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
bfe040c3 | 13809 | set_bit(__I40E_MACVLAN_SYNC_PENDING, pf->state); |
41c445ff JB |
13810 | } |
13811 | ||
13812 | /* Update VSI BW information */ | |
13813 | ret = i40e_vsi_get_bw_info(vsi); | |
13814 | if (ret) { | |
13815 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
13816 | "couldn't get vsi bw info, err %s aq_err %s\n", |
13817 | i40e_stat_str(&pf->hw, ret), | |
13818 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
13819 | /* VSI is already added so not tearing that up */ |
13820 | ret = 0; | |
13821 | } | |
13822 | ||
13823 | err: | |
13824 | return ret; | |
13825 | } | |
13826 | ||
13827 | /** | |
13828 | * i40e_vsi_release - Delete a VSI and free its resources | |
13829 | * @vsi: the VSI being removed | |
13830 | * | |
13831 | * Returns 0 on success or < 0 on error | |
13832 | **/ | |
13833 | int i40e_vsi_release(struct i40e_vsi *vsi) | |
13834 | { | |
278e7d0b JK |
13835 | struct i40e_mac_filter *f; |
13836 | struct hlist_node *h; | |
41c445ff JB |
13837 | struct i40e_veb *veb = NULL; |
13838 | struct i40e_pf *pf; | |
13839 | u16 uplink_seid; | |
278e7d0b | 13840 | int i, n, bkt; |
41c445ff JB |
13841 | |
13842 | pf = vsi->back; | |
13843 | ||
13844 | /* release of a VEB-owner or last VSI is not allowed */ | |
13845 | if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) { | |
13846 | dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n", | |
13847 | vsi->seid, vsi->uplink_seid); | |
13848 | return -ENODEV; | |
13849 | } | |
13850 | if (vsi == pf->vsi[pf->lan_vsi] && | |
9e6c9c0f | 13851 | !test_bit(__I40E_DOWN, pf->state)) { |
41c445ff JB |
13852 | dev_info(&pf->pdev->dev, "Can't remove PF VSI\n"); |
13853 | return -ENODEV; | |
13854 | } | |
37d9e304 | 13855 | set_bit(__I40E_VSI_RELEASING, vsi->state); |
41c445ff JB |
13856 | uplink_seid = vsi->uplink_seid; |
13857 | if (vsi->type != I40E_VSI_SRIOV) { | |
13858 | if (vsi->netdev_registered) { | |
13859 | vsi->netdev_registered = false; | |
13860 | if (vsi->netdev) { | |
13861 | /* results in a call to i40e_close() */ | |
13862 | unregister_netdev(vsi->netdev); | |
41c445ff JB |
13863 | } |
13864 | } else { | |
90ef8d47 | 13865 | i40e_vsi_close(vsi); |
41c445ff JB |
13866 | } |
13867 | i40e_vsi_disable_irq(vsi); | |
13868 | } | |
13869 | ||
278e7d0b | 13870 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
6622f5cd JK |
13871 | |
13872 | /* clear the sync flag on all filters */ | |
13873 | if (vsi->netdev) { | |
13874 | __dev_uc_unsync(vsi->netdev, NULL); | |
13875 | __dev_mc_unsync(vsi->netdev, NULL); | |
13876 | } | |
13877 | ||
13878 | /* make sure any remaining filters are marked for deletion */ | |
278e7d0b | 13879 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) |
290d2557 | 13880 | __i40e_del_filter(vsi, f); |
6622f5cd | 13881 | |
278e7d0b | 13882 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 13883 | |
17652c63 | 13884 | i40e_sync_vsi_filters(vsi); |
41c445ff JB |
13885 | |
13886 | i40e_vsi_delete(vsi); | |
13887 | i40e_vsi_free_q_vectors(vsi); | |
a4866597 SN |
13888 | if (vsi->netdev) { |
13889 | free_netdev(vsi->netdev); | |
13890 | vsi->netdev = NULL; | |
13891 | } | |
41c445ff JB |
13892 | i40e_vsi_clear_rings(vsi); |
13893 | i40e_vsi_clear(vsi); | |
13894 | ||
13895 | /* If this was the last thing on the VEB, except for the | |
13896 | * controlling VSI, remove the VEB, which puts the controlling | |
13897 | * VSI onto the next level down in the switch. | |
13898 | * | |
13899 | * Well, okay, there's one more exception here: don't remove | |
13900 | * the orphan VEBs yet. We'll wait for an explicit remove request | |
13901 | * from up the network stack. | |
13902 | */ | |
505682cd | 13903 | for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
13904 | if (pf->vsi[i] && |
13905 | pf->vsi[i]->uplink_seid == uplink_seid && | |
13906 | (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { | |
13907 | n++; /* count the VSIs */ | |
13908 | } | |
13909 | } | |
13910 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
13911 | if (!pf->veb[i]) | |
13912 | continue; | |
13913 | if (pf->veb[i]->uplink_seid == uplink_seid) | |
13914 | n++; /* count the VEBs */ | |
13915 | if (pf->veb[i]->seid == uplink_seid) | |
13916 | veb = pf->veb[i]; | |
13917 | } | |
13918 | if (n == 0 && veb && veb->uplink_seid != 0) | |
13919 | i40e_veb_release(veb); | |
13920 | ||
13921 | return 0; | |
13922 | } | |
13923 | ||
13924 | /** | |
13925 | * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI | |
13926 | * @vsi: ptr to the VSI | |
13927 | * | |
13928 | * This should only be called after i40e_vsi_mem_alloc() which allocates the | |
13929 | * corresponding SW VSI structure and initializes num_queue_pairs for the | |
13930 | * newly allocated VSI. | |
13931 | * | |
13932 | * Returns 0 on success or negative on failure | |
13933 | **/ | |
13934 | static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi) | |
13935 | { | |
13936 | int ret = -ENOENT; | |
13937 | struct i40e_pf *pf = vsi->back; | |
13938 | ||
493fb300 | 13939 | if (vsi->q_vectors[0]) { |
41c445ff JB |
13940 | dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n", |
13941 | vsi->seid); | |
13942 | return -EEXIST; | |
13943 | } | |
13944 | ||
13945 | if (vsi->base_vector) { | |
f29eaa3d | 13946 | dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n", |
41c445ff JB |
13947 | vsi->seid, vsi->base_vector); |
13948 | return -EEXIST; | |
13949 | } | |
13950 | ||
90e04070 | 13951 | ret = i40e_vsi_alloc_q_vectors(vsi); |
41c445ff JB |
13952 | if (ret) { |
13953 | dev_info(&pf->pdev->dev, | |
13954 | "failed to allocate %d q_vector for VSI %d, ret=%d\n", | |
13955 | vsi->num_q_vectors, vsi->seid, ret); | |
13956 | vsi->num_q_vectors = 0; | |
13957 | goto vector_setup_out; | |
13958 | } | |
13959 | ||
26cdc443 ASJ |
13960 | /* In Legacy mode, we do not have to get any other vector since we |
13961 | * piggyback on the misc/ICR0 for queue interrupts. | |
13962 | */ | |
13963 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
13964 | return ret; | |
958a3e3b SN |
13965 | if (vsi->num_q_vectors) |
13966 | vsi->base_vector = i40e_get_lump(pf, pf->irq_pile, | |
13967 | vsi->num_q_vectors, vsi->idx); | |
41c445ff JB |
13968 | if (vsi->base_vector < 0) { |
13969 | dev_info(&pf->pdev->dev, | |
049a2be8 SN |
13970 | "failed to get tracking for %d vectors for VSI %d, err=%d\n", |
13971 | vsi->num_q_vectors, vsi->seid, vsi->base_vector); | |
41c445ff JB |
13972 | i40e_vsi_free_q_vectors(vsi); |
13973 | ret = -ENOENT; | |
13974 | goto vector_setup_out; | |
13975 | } | |
13976 | ||
13977 | vector_setup_out: | |
13978 | return ret; | |
13979 | } | |
13980 | ||
bc7d338f ASJ |
13981 | /** |
13982 | * i40e_vsi_reinit_setup - return and reallocate resources for a VSI | |
13983 | * @vsi: pointer to the vsi. | |
13984 | * | |
13985 | * This re-allocates a vsi's queue resources. | |
13986 | * | |
13987 | * Returns pointer to the successfully allocated and configured VSI sw struct | |
13988 | * on success, otherwise returns NULL on failure. | |
13989 | **/ | |
13990 | static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi) | |
13991 | { | |
74608d17 | 13992 | u16 alloc_queue_pairs; |
f534039d | 13993 | struct i40e_pf *pf; |
bc7d338f ASJ |
13994 | u8 enabled_tc; |
13995 | int ret; | |
13996 | ||
f534039d JU |
13997 | if (!vsi) |
13998 | return NULL; | |
13999 | ||
14000 | pf = vsi->back; | |
14001 | ||
bc7d338f ASJ |
14002 | i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); |
14003 | i40e_vsi_clear_rings(vsi); | |
14004 | ||
14005 | i40e_vsi_free_arrays(vsi, false); | |
14006 | i40e_set_num_rings_in_vsi(vsi); | |
14007 | ret = i40e_vsi_alloc_arrays(vsi, false); | |
14008 | if (ret) | |
14009 | goto err_vsi; | |
14010 | ||
74608d17 BT |
14011 | alloc_queue_pairs = vsi->alloc_queue_pairs * |
14012 | (i40e_enabled_xdp_vsi(vsi) ? 2 : 1); | |
14013 | ||
14014 | ret = i40e_get_lump(pf, pf->qp_pile, alloc_queue_pairs, vsi->idx); | |
bc7d338f | 14015 | if (ret < 0) { |
049a2be8 | 14016 | dev_info(&pf->pdev->dev, |
f1c7e72e | 14017 | "failed to get tracking for %d queues for VSI %d err %d\n", |
74608d17 | 14018 | alloc_queue_pairs, vsi->seid, ret); |
bc7d338f ASJ |
14019 | goto err_vsi; |
14020 | } | |
14021 | vsi->base_queue = ret; | |
14022 | ||
14023 | /* Update the FW view of the VSI. Force a reset of TC and queue | |
14024 | * layout configurations. | |
14025 | */ | |
14026 | enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; | |
14027 | pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; | |
14028 | pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; | |
14029 | i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); | |
1596b5dd JK |
14030 | if (vsi->type == I40E_VSI_MAIN) |
14031 | i40e_rm_default_mac_filter(vsi, pf->hw.mac.perm_addr); | |
bc7d338f ASJ |
14032 | |
14033 | /* assign it some queues */ | |
14034 | ret = i40e_alloc_rings(vsi); | |
14035 | if (ret) | |
14036 | goto err_rings; | |
14037 | ||
14038 | /* map all of the rings to the q_vectors */ | |
14039 | i40e_vsi_map_rings_to_vectors(vsi); | |
14040 | return vsi; | |
14041 | ||
14042 | err_rings: | |
14043 | i40e_vsi_free_q_vectors(vsi); | |
14044 | if (vsi->netdev_registered) { | |
14045 | vsi->netdev_registered = false; | |
14046 | unregister_netdev(vsi->netdev); | |
14047 | free_netdev(vsi->netdev); | |
14048 | vsi->netdev = NULL; | |
14049 | } | |
14050 | i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); | |
14051 | err_vsi: | |
14052 | i40e_vsi_clear(vsi); | |
14053 | return NULL; | |
14054 | } | |
14055 | ||
41c445ff JB |
14056 | /** |
14057 | * i40e_vsi_setup - Set up a VSI by a given type | |
14058 | * @pf: board private structure | |
14059 | * @type: VSI type | |
14060 | * @uplink_seid: the switch element to link to | |
14061 | * @param1: usage depends upon VSI type. For VF types, indicates VF id | |
14062 | * | |
14063 | * This allocates the sw VSI structure and its queue resources, then add a VSI | |
14064 | * to the identified VEB. | |
14065 | * | |
14066 | * Returns pointer to the successfully allocated and configure VSI sw struct on | |
14067 | * success, otherwise returns NULL on failure. | |
14068 | **/ | |
14069 | struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, | |
14070 | u16 uplink_seid, u32 param1) | |
14071 | { | |
14072 | struct i40e_vsi *vsi = NULL; | |
14073 | struct i40e_veb *veb = NULL; | |
74608d17 | 14074 | u16 alloc_queue_pairs; |
41c445ff JB |
14075 | int ret, i; |
14076 | int v_idx; | |
14077 | ||
14078 | /* The requested uplink_seid must be either | |
14079 | * - the PF's port seid | |
14080 | * no VEB is needed because this is the PF | |
14081 | * or this is a Flow Director special case VSI | |
14082 | * - seid of an existing VEB | |
14083 | * - seid of a VSI that owns an existing VEB | |
14084 | * - seid of a VSI that doesn't own a VEB | |
14085 | * a new VEB is created and the VSI becomes the owner | |
14086 | * - seid of the PF VSI, which is what creates the first VEB | |
14087 | * this is a special case of the previous | |
14088 | * | |
14089 | * Find which uplink_seid we were given and create a new VEB if needed | |
14090 | */ | |
14091 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
14092 | if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) { | |
14093 | veb = pf->veb[i]; | |
14094 | break; | |
14095 | } | |
14096 | } | |
14097 | ||
14098 | if (!veb && uplink_seid != pf->mac_seid) { | |
14099 | ||
505682cd | 14100 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
14101 | if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) { |
14102 | vsi = pf->vsi[i]; | |
14103 | break; | |
14104 | } | |
14105 | } | |
14106 | if (!vsi) { | |
14107 | dev_info(&pf->pdev->dev, "no such uplink_seid %d\n", | |
14108 | uplink_seid); | |
14109 | return NULL; | |
14110 | } | |
14111 | ||
14112 | if (vsi->uplink_seid == pf->mac_seid) | |
14113 | veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid, | |
14114 | vsi->tc_config.enabled_tc); | |
14115 | else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) | |
14116 | veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, | |
14117 | vsi->tc_config.enabled_tc); | |
79c21a82 ASJ |
14118 | if (veb) { |
14119 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) { | |
14120 | dev_info(&vsi->back->pdev->dev, | |
fb43201f | 14121 | "New VSI creation error, uplink seid of LAN VSI expected.\n"); |
79c21a82 ASJ |
14122 | return NULL; |
14123 | } | |
fa11cb3d ASJ |
14124 | /* We come up by default in VEPA mode if SRIOV is not |
14125 | * already enabled, in which case we can't force VEPA | |
14126 | * mode. | |
14127 | */ | |
14128 | if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) { | |
14129 | veb->bridge_mode = BRIDGE_MODE_VEPA; | |
14130 | pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; | |
14131 | } | |
51616018 | 14132 | i40e_config_bridge_mode(veb); |
79c21a82 | 14133 | } |
41c445ff JB |
14134 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { |
14135 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
14136 | veb = pf->veb[i]; | |
14137 | } | |
14138 | if (!veb) { | |
14139 | dev_info(&pf->pdev->dev, "couldn't add VEB\n"); | |
14140 | return NULL; | |
14141 | } | |
14142 | ||
14143 | vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; | |
14144 | uplink_seid = veb->seid; | |
14145 | } | |
14146 | ||
14147 | /* get vsi sw struct */ | |
14148 | v_idx = i40e_vsi_mem_alloc(pf, type); | |
14149 | if (v_idx < 0) | |
14150 | goto err_alloc; | |
14151 | vsi = pf->vsi[v_idx]; | |
cbf61325 ASJ |
14152 | if (!vsi) |
14153 | goto err_alloc; | |
41c445ff JB |
14154 | vsi->type = type; |
14155 | vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB); | |
14156 | ||
14157 | if (type == I40E_VSI_MAIN) | |
14158 | pf->lan_vsi = v_idx; | |
14159 | else if (type == I40E_VSI_SRIOV) | |
14160 | vsi->vf_id = param1; | |
14161 | /* assign it some queues */ | |
74608d17 BT |
14162 | alloc_queue_pairs = vsi->alloc_queue_pairs * |
14163 | (i40e_enabled_xdp_vsi(vsi) ? 2 : 1); | |
14164 | ||
14165 | ret = i40e_get_lump(pf, pf->qp_pile, alloc_queue_pairs, vsi->idx); | |
41c445ff | 14166 | if (ret < 0) { |
049a2be8 SN |
14167 | dev_info(&pf->pdev->dev, |
14168 | "failed to get tracking for %d queues for VSI %d err=%d\n", | |
74608d17 | 14169 | alloc_queue_pairs, vsi->seid, ret); |
41c445ff JB |
14170 | goto err_vsi; |
14171 | } | |
14172 | vsi->base_queue = ret; | |
14173 | ||
14174 | /* get a VSI from the hardware */ | |
14175 | vsi->uplink_seid = uplink_seid; | |
14176 | ret = i40e_add_vsi(vsi); | |
14177 | if (ret) | |
14178 | goto err_vsi; | |
14179 | ||
14180 | switch (vsi->type) { | |
14181 | /* setup the netdev if needed */ | |
14182 | case I40E_VSI_MAIN: | |
14183 | case I40E_VSI_VMDQ2: | |
14184 | ret = i40e_config_netdev(vsi); | |
e738451d JJ |
14185 | if (ret) |
14186 | goto err_netdev; | |
14187 | ret = i40e_netif_set_realnum_tx_rx_queues(vsi); | |
41c445ff JB |
14188 | if (ret) |
14189 | goto err_netdev; | |
14190 | ret = register_netdev(vsi->netdev); | |
14191 | if (ret) | |
14192 | goto err_netdev; | |
14193 | vsi->netdev_registered = true; | |
14194 | netif_carrier_off(vsi->netdev); | |
4e3b35b0 NP |
14195 | #ifdef CONFIG_I40E_DCB |
14196 | /* Setup DCB netlink interface */ | |
14197 | i40e_dcbnl_setup(vsi); | |
14198 | #endif /* CONFIG_I40E_DCB */ | |
5463fce6 | 14199 | fallthrough; |
41c445ff JB |
14200 | case I40E_VSI_FDIR: |
14201 | /* set up vectors and rings if needed */ | |
14202 | ret = i40e_vsi_setup_vectors(vsi); | |
14203 | if (ret) | |
14204 | goto err_msix; | |
14205 | ||
14206 | ret = i40e_alloc_rings(vsi); | |
14207 | if (ret) | |
14208 | goto err_rings; | |
14209 | ||
14210 | /* map all of the rings to the q_vectors */ | |
14211 | i40e_vsi_map_rings_to_vectors(vsi); | |
14212 | ||
14213 | i40e_vsi_reset_stats(vsi); | |
14214 | break; | |
41c445ff JB |
14215 | default: |
14216 | /* no netdev or rings for the other VSI types */ | |
14217 | break; | |
14218 | } | |
14219 | ||
d36e41dc | 14220 | if ((pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) && |
e25d00b8 ASJ |
14221 | (vsi->type == I40E_VSI_VMDQ2)) { |
14222 | ret = i40e_vsi_config_rss(vsi); | |
14223 | } | |
41c445ff JB |
14224 | return vsi; |
14225 | ||
14226 | err_rings: | |
14227 | i40e_vsi_free_q_vectors(vsi); | |
14228 | err_msix: | |
14229 | if (vsi->netdev_registered) { | |
14230 | vsi->netdev_registered = false; | |
14231 | unregister_netdev(vsi->netdev); | |
14232 | free_netdev(vsi->netdev); | |
14233 | vsi->netdev = NULL; | |
14234 | } | |
14235 | err_netdev: | |
14236 | i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); | |
14237 | err_vsi: | |
14238 | i40e_vsi_clear(vsi); | |
14239 | err_alloc: | |
14240 | return NULL; | |
14241 | } | |
14242 | ||
14243 | /** | |
14244 | * i40e_veb_get_bw_info - Query VEB BW information | |
14245 | * @veb: the veb to query | |
14246 | * | |
14247 | * Query the Tx scheduler BW configuration data for given VEB | |
14248 | **/ | |
14249 | static int i40e_veb_get_bw_info(struct i40e_veb *veb) | |
14250 | { | |
14251 | struct i40e_aqc_query_switching_comp_ets_config_resp ets_data; | |
14252 | struct i40e_aqc_query_switching_comp_bw_config_resp bw_data; | |
14253 | struct i40e_pf *pf = veb->pf; | |
14254 | struct i40e_hw *hw = &pf->hw; | |
14255 | u32 tc_bw_max; | |
14256 | int ret = 0; | |
14257 | int i; | |
14258 | ||
14259 | ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid, | |
14260 | &bw_data, NULL); | |
14261 | if (ret) { | |
14262 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
14263 | "query veb bw config failed, err %s aq_err %s\n", |
14264 | i40e_stat_str(&pf->hw, ret), | |
14265 | i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); | |
41c445ff JB |
14266 | goto out; |
14267 | } | |
14268 | ||
14269 | ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid, | |
14270 | &ets_data, NULL); | |
14271 | if (ret) { | |
14272 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
14273 | "query veb bw ets config failed, err %s aq_err %s\n", |
14274 | i40e_stat_str(&pf->hw, ret), | |
14275 | i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); | |
41c445ff JB |
14276 | goto out; |
14277 | } | |
14278 | ||
14279 | veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit); | |
14280 | veb->bw_max_quanta = ets_data.tc_bw_max; | |
14281 | veb->is_abs_credits = bw_data.absolute_credits_enable; | |
23cd1f09 | 14282 | veb->enabled_tc = ets_data.tc_valid_bits; |
41c445ff JB |
14283 | tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) | |
14284 | (le16_to_cpu(bw_data.tc_bw_max[1]) << 16); | |
14285 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
14286 | veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i]; | |
14287 | veb->bw_tc_limit_credits[i] = | |
14288 | le16_to_cpu(bw_data.tc_bw_limits[i]); | |
14289 | veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7); | |
14290 | } | |
14291 | ||
14292 | out: | |
14293 | return ret; | |
14294 | } | |
14295 | ||
14296 | /** | |
14297 | * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF | |
14298 | * @pf: board private structure | |
14299 | * | |
14300 | * On error: returns error code (negative) | |
14301 | * On success: returns vsi index in PF (positive) | |
14302 | **/ | |
14303 | static int i40e_veb_mem_alloc(struct i40e_pf *pf) | |
14304 | { | |
14305 | int ret = -ENOENT; | |
14306 | struct i40e_veb *veb; | |
14307 | int i; | |
14308 | ||
14309 | /* Need to protect the allocation of switch elements at the PF level */ | |
14310 | mutex_lock(&pf->switch_mutex); | |
14311 | ||
14312 | /* VEB list may be fragmented if VEB creation/destruction has | |
14313 | * been happening. We can afford to do a quick scan to look | |
14314 | * for any free slots in the list. | |
14315 | * | |
14316 | * find next empty veb slot, looping back around if necessary | |
14317 | */ | |
14318 | i = 0; | |
14319 | while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL)) | |
14320 | i++; | |
14321 | if (i >= I40E_MAX_VEB) { | |
14322 | ret = -ENOMEM; | |
14323 | goto err_alloc_veb; /* out of VEB slots! */ | |
14324 | } | |
14325 | ||
14326 | veb = kzalloc(sizeof(*veb), GFP_KERNEL); | |
14327 | if (!veb) { | |
14328 | ret = -ENOMEM; | |
14329 | goto err_alloc_veb; | |
14330 | } | |
14331 | veb->pf = pf; | |
14332 | veb->idx = i; | |
14333 | veb->enabled_tc = 1; | |
14334 | ||
14335 | pf->veb[i] = veb; | |
14336 | ret = i; | |
14337 | err_alloc_veb: | |
14338 | mutex_unlock(&pf->switch_mutex); | |
14339 | return ret; | |
14340 | } | |
14341 | ||
14342 | /** | |
14343 | * i40e_switch_branch_release - Delete a branch of the switch tree | |
14344 | * @branch: where to start deleting | |
14345 | * | |
14346 | * This uses recursion to find the tips of the branch to be | |
14347 | * removed, deleting until we get back to and can delete this VEB. | |
14348 | **/ | |
14349 | static void i40e_switch_branch_release(struct i40e_veb *branch) | |
14350 | { | |
14351 | struct i40e_pf *pf = branch->pf; | |
14352 | u16 branch_seid = branch->seid; | |
14353 | u16 veb_idx = branch->idx; | |
14354 | int i; | |
14355 | ||
14356 | /* release any VEBs on this VEB - RECURSION */ | |
14357 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
14358 | if (!pf->veb[i]) | |
14359 | continue; | |
14360 | if (pf->veb[i]->uplink_seid == branch->seid) | |
14361 | i40e_switch_branch_release(pf->veb[i]); | |
14362 | } | |
14363 | ||
14364 | /* Release the VSIs on this VEB, but not the owner VSI. | |
14365 | * | |
14366 | * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing | |
14367 | * the VEB itself, so don't use (*branch) after this loop. | |
14368 | */ | |
505682cd | 14369 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
14370 | if (!pf->vsi[i]) |
14371 | continue; | |
14372 | if (pf->vsi[i]->uplink_seid == branch_seid && | |
14373 | (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { | |
14374 | i40e_vsi_release(pf->vsi[i]); | |
14375 | } | |
14376 | } | |
14377 | ||
14378 | /* There's one corner case where the VEB might not have been | |
14379 | * removed, so double check it here and remove it if needed. | |
14380 | * This case happens if the veb was created from the debugfs | |
14381 | * commands and no VSIs were added to it. | |
14382 | */ | |
14383 | if (pf->veb[veb_idx]) | |
14384 | i40e_veb_release(pf->veb[veb_idx]); | |
14385 | } | |
14386 | ||
14387 | /** | |
14388 | * i40e_veb_clear - remove veb struct | |
14389 | * @veb: the veb to remove | |
14390 | **/ | |
14391 | static void i40e_veb_clear(struct i40e_veb *veb) | |
14392 | { | |
14393 | if (!veb) | |
14394 | return; | |
14395 | ||
14396 | if (veb->pf) { | |
14397 | struct i40e_pf *pf = veb->pf; | |
14398 | ||
14399 | mutex_lock(&pf->switch_mutex); | |
14400 | if (pf->veb[veb->idx] == veb) | |
14401 | pf->veb[veb->idx] = NULL; | |
14402 | mutex_unlock(&pf->switch_mutex); | |
14403 | } | |
14404 | ||
14405 | kfree(veb); | |
14406 | } | |
14407 | ||
14408 | /** | |
14409 | * i40e_veb_release - Delete a VEB and free its resources | |
14410 | * @veb: the VEB being removed | |
14411 | **/ | |
14412 | void i40e_veb_release(struct i40e_veb *veb) | |
14413 | { | |
14414 | struct i40e_vsi *vsi = NULL; | |
14415 | struct i40e_pf *pf; | |
14416 | int i, n = 0; | |
14417 | ||
14418 | pf = veb->pf; | |
14419 | ||
14420 | /* find the remaining VSI and check for extras */ | |
505682cd | 14421 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
14422 | if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) { |
14423 | n++; | |
14424 | vsi = pf->vsi[i]; | |
14425 | } | |
14426 | } | |
14427 | if (n != 1) { | |
14428 | dev_info(&pf->pdev->dev, | |
14429 | "can't remove VEB %d with %d VSIs left\n", | |
14430 | veb->seid, n); | |
14431 | return; | |
14432 | } | |
14433 | ||
14434 | /* move the remaining VSI to uplink veb */ | |
14435 | vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER; | |
14436 | if (veb->uplink_seid) { | |
14437 | vsi->uplink_seid = veb->uplink_seid; | |
14438 | if (veb->uplink_seid == pf->mac_seid) | |
14439 | vsi->veb_idx = I40E_NO_VEB; | |
14440 | else | |
14441 | vsi->veb_idx = veb->veb_idx; | |
14442 | } else { | |
14443 | /* floating VEB */ | |
14444 | vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
14445 | vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx; | |
14446 | } | |
14447 | ||
14448 | i40e_aq_delete_element(&pf->hw, veb->seid, NULL); | |
14449 | i40e_veb_clear(veb); | |
41c445ff JB |
14450 | } |
14451 | ||
14452 | /** | |
14453 | * i40e_add_veb - create the VEB in the switch | |
14454 | * @veb: the VEB to be instantiated | |
14455 | * @vsi: the controlling VSI | |
14456 | **/ | |
14457 | static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi) | |
14458 | { | |
f1c7e72e | 14459 | struct i40e_pf *pf = veb->pf; |
66fc360a | 14460 | bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED); |
41c445ff JB |
14461 | int ret; |
14462 | ||
f1c7e72e | 14463 | ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid, |
5bc16031 | 14464 | veb->enabled_tc, false, |
66fc360a | 14465 | &veb->seid, enable_stats, NULL); |
5bc16031 MW |
14466 | |
14467 | /* get a VEB from the hardware */ | |
41c445ff | 14468 | if (ret) { |
f1c7e72e SN |
14469 | dev_info(&pf->pdev->dev, |
14470 | "couldn't add VEB, err %s aq_err %s\n", | |
14471 | i40e_stat_str(&pf->hw, ret), | |
14472 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
14473 | return -EPERM; |
14474 | } | |
14475 | ||
14476 | /* get statistics counter */ | |
f1c7e72e | 14477 | ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL, |
41c445ff JB |
14478 | &veb->stats_idx, NULL, NULL, NULL); |
14479 | if (ret) { | |
f1c7e72e SN |
14480 | dev_info(&pf->pdev->dev, |
14481 | "couldn't get VEB statistics idx, err %s aq_err %s\n", | |
14482 | i40e_stat_str(&pf->hw, ret), | |
14483 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
14484 | return -EPERM; |
14485 | } | |
14486 | ret = i40e_veb_get_bw_info(veb); | |
14487 | if (ret) { | |
f1c7e72e SN |
14488 | dev_info(&pf->pdev->dev, |
14489 | "couldn't get VEB bw info, err %s aq_err %s\n", | |
14490 | i40e_stat_str(&pf->hw, ret), | |
14491 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
14492 | i40e_aq_delete_element(&pf->hw, veb->seid, NULL); | |
41c445ff JB |
14493 | return -ENOENT; |
14494 | } | |
14495 | ||
14496 | vsi->uplink_seid = veb->seid; | |
14497 | vsi->veb_idx = veb->idx; | |
14498 | vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; | |
14499 | ||
14500 | return 0; | |
14501 | } | |
14502 | ||
14503 | /** | |
14504 | * i40e_veb_setup - Set up a VEB | |
14505 | * @pf: board private structure | |
14506 | * @flags: VEB setup flags | |
14507 | * @uplink_seid: the switch element to link to | |
14508 | * @vsi_seid: the initial VSI seid | |
14509 | * @enabled_tc: Enabled TC bit-map | |
14510 | * | |
14511 | * This allocates the sw VEB structure and links it into the switch | |
14512 | * It is possible and legal for this to be a duplicate of an already | |
14513 | * existing VEB. It is also possible for both uplink and vsi seids | |
14514 | * to be zero, in order to create a floating VEB. | |
14515 | * | |
14516 | * Returns pointer to the successfully allocated VEB sw struct on | |
14517 | * success, otherwise returns NULL on failure. | |
14518 | **/ | |
14519 | struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, | |
14520 | u16 uplink_seid, u16 vsi_seid, | |
14521 | u8 enabled_tc) | |
14522 | { | |
14523 | struct i40e_veb *veb, *uplink_veb = NULL; | |
14524 | int vsi_idx, veb_idx; | |
14525 | int ret; | |
14526 | ||
14527 | /* if one seid is 0, the other must be 0 to create a floating relay */ | |
14528 | if ((uplink_seid == 0 || vsi_seid == 0) && | |
14529 | (uplink_seid + vsi_seid != 0)) { | |
14530 | dev_info(&pf->pdev->dev, | |
14531 | "one, not both seid's are 0: uplink=%d vsi=%d\n", | |
14532 | uplink_seid, vsi_seid); | |
14533 | return NULL; | |
14534 | } | |
14535 | ||
14536 | /* make sure there is such a vsi and uplink */ | |
505682cd | 14537 | for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++) |
41c445ff JB |
14538 | if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid) |
14539 | break; | |
cfe39699 | 14540 | if (vsi_idx == pf->num_alloc_vsi && vsi_seid != 0) { |
41c445ff JB |
14541 | dev_info(&pf->pdev->dev, "vsi seid %d not found\n", |
14542 | vsi_seid); | |
14543 | return NULL; | |
14544 | } | |
14545 | ||
14546 | if (uplink_seid && uplink_seid != pf->mac_seid) { | |
14547 | for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { | |
14548 | if (pf->veb[veb_idx] && | |
14549 | pf->veb[veb_idx]->seid == uplink_seid) { | |
14550 | uplink_veb = pf->veb[veb_idx]; | |
14551 | break; | |
14552 | } | |
14553 | } | |
14554 | if (!uplink_veb) { | |
14555 | dev_info(&pf->pdev->dev, | |
14556 | "uplink seid %d not found\n", uplink_seid); | |
14557 | return NULL; | |
14558 | } | |
14559 | } | |
14560 | ||
14561 | /* get veb sw struct */ | |
14562 | veb_idx = i40e_veb_mem_alloc(pf); | |
14563 | if (veb_idx < 0) | |
14564 | goto err_alloc; | |
14565 | veb = pf->veb[veb_idx]; | |
14566 | veb->flags = flags; | |
14567 | veb->uplink_seid = uplink_seid; | |
14568 | veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB); | |
14569 | veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1); | |
14570 | ||
14571 | /* create the VEB in the switch */ | |
14572 | ret = i40e_add_veb(veb, pf->vsi[vsi_idx]); | |
14573 | if (ret) | |
14574 | goto err_veb; | |
1bb8b935 SN |
14575 | if (vsi_idx == pf->lan_vsi) |
14576 | pf->lan_veb = veb->idx; | |
41c445ff JB |
14577 | |
14578 | return veb; | |
14579 | ||
14580 | err_veb: | |
14581 | i40e_veb_clear(veb); | |
14582 | err_alloc: | |
14583 | return NULL; | |
14584 | } | |
14585 | ||
14586 | /** | |
b40c82e6 | 14587 | * i40e_setup_pf_switch_element - set PF vars based on switch type |
41c445ff JB |
14588 | * @pf: board private structure |
14589 | * @ele: element we are building info from | |
14590 | * @num_reported: total number of elements | |
14591 | * @printconfig: should we print the contents | |
14592 | * | |
14593 | * helper function to assist in extracting a few useful SEID values. | |
14594 | **/ | |
14595 | static void i40e_setup_pf_switch_element(struct i40e_pf *pf, | |
14596 | struct i40e_aqc_switch_config_element_resp *ele, | |
14597 | u16 num_reported, bool printconfig) | |
14598 | { | |
14599 | u16 downlink_seid = le16_to_cpu(ele->downlink_seid); | |
14600 | u16 uplink_seid = le16_to_cpu(ele->uplink_seid); | |
14601 | u8 element_type = ele->element_type; | |
14602 | u16 seid = le16_to_cpu(ele->seid); | |
14603 | ||
14604 | if (printconfig) | |
14605 | dev_info(&pf->pdev->dev, | |
14606 | "type=%d seid=%d uplink=%d downlink=%d\n", | |
14607 | element_type, seid, uplink_seid, downlink_seid); | |
14608 | ||
14609 | switch (element_type) { | |
14610 | case I40E_SWITCH_ELEMENT_TYPE_MAC: | |
14611 | pf->mac_seid = seid; | |
14612 | break; | |
14613 | case I40E_SWITCH_ELEMENT_TYPE_VEB: | |
14614 | /* Main VEB? */ | |
14615 | if (uplink_seid != pf->mac_seid) | |
14616 | break; | |
f031c722 | 14617 | if (pf->lan_veb >= I40E_MAX_VEB) { |
41c445ff JB |
14618 | int v; |
14619 | ||
14620 | /* find existing or else empty VEB */ | |
14621 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
14622 | if (pf->veb[v] && (pf->veb[v]->seid == seid)) { | |
14623 | pf->lan_veb = v; | |
14624 | break; | |
14625 | } | |
14626 | } | |
f031c722 | 14627 | if (pf->lan_veb >= I40E_MAX_VEB) { |
41c445ff JB |
14628 | v = i40e_veb_mem_alloc(pf); |
14629 | if (v < 0) | |
14630 | break; | |
14631 | pf->lan_veb = v; | |
14632 | } | |
14633 | } | |
f031c722 PK |
14634 | if (pf->lan_veb >= I40E_MAX_VEB) |
14635 | break; | |
41c445ff JB |
14636 | |
14637 | pf->veb[pf->lan_veb]->seid = seid; | |
14638 | pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid; | |
14639 | pf->veb[pf->lan_veb]->pf = pf; | |
14640 | pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB; | |
14641 | break; | |
14642 | case I40E_SWITCH_ELEMENT_TYPE_VSI: | |
14643 | if (num_reported != 1) | |
14644 | break; | |
14645 | /* This is immediately after a reset so we can assume this is | |
14646 | * the PF's VSI | |
14647 | */ | |
14648 | pf->mac_seid = uplink_seid; | |
14649 | pf->pf_seid = downlink_seid; | |
14650 | pf->main_vsi_seid = seid; | |
14651 | if (printconfig) | |
14652 | dev_info(&pf->pdev->dev, | |
14653 | "pf_seid=%d main_vsi_seid=%d\n", | |
14654 | pf->pf_seid, pf->main_vsi_seid); | |
14655 | break; | |
14656 | case I40E_SWITCH_ELEMENT_TYPE_PF: | |
14657 | case I40E_SWITCH_ELEMENT_TYPE_VF: | |
14658 | case I40E_SWITCH_ELEMENT_TYPE_EMP: | |
14659 | case I40E_SWITCH_ELEMENT_TYPE_BMC: | |
14660 | case I40E_SWITCH_ELEMENT_TYPE_PE: | |
14661 | case I40E_SWITCH_ELEMENT_TYPE_PA: | |
14662 | /* ignore these for now */ | |
14663 | break; | |
14664 | default: | |
14665 | dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n", | |
14666 | element_type, seid); | |
14667 | break; | |
14668 | } | |
14669 | } | |
14670 | ||
14671 | /** | |
14672 | * i40e_fetch_switch_configuration - Get switch config from firmware | |
14673 | * @pf: board private structure | |
14674 | * @printconfig: should we print the contents | |
14675 | * | |
14676 | * Get the current switch configuration from the device and | |
14677 | * extract a few useful SEID values. | |
14678 | **/ | |
14679 | int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig) | |
14680 | { | |
14681 | struct i40e_aqc_get_switch_config_resp *sw_config; | |
14682 | u16 next_seid = 0; | |
14683 | int ret = 0; | |
14684 | u8 *aq_buf; | |
14685 | int i; | |
14686 | ||
14687 | aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL); | |
14688 | if (!aq_buf) | |
14689 | return -ENOMEM; | |
14690 | ||
14691 | sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; | |
14692 | do { | |
14693 | u16 num_reported, num_total; | |
14694 | ||
14695 | ret = i40e_aq_get_switch_config(&pf->hw, sw_config, | |
14696 | I40E_AQ_LARGE_BUF, | |
14697 | &next_seid, NULL); | |
14698 | if (ret) { | |
14699 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
14700 | "get switch config failed err %s aq_err %s\n", |
14701 | i40e_stat_str(&pf->hw, ret), | |
14702 | i40e_aq_str(&pf->hw, | |
14703 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
14704 | kfree(aq_buf); |
14705 | return -ENOENT; | |
14706 | } | |
14707 | ||
14708 | num_reported = le16_to_cpu(sw_config->header.num_reported); | |
14709 | num_total = le16_to_cpu(sw_config->header.num_total); | |
14710 | ||
14711 | if (printconfig) | |
14712 | dev_info(&pf->pdev->dev, | |
14713 | "header: %d reported %d total\n", | |
14714 | num_reported, num_total); | |
14715 | ||
41c445ff JB |
14716 | for (i = 0; i < num_reported; i++) { |
14717 | struct i40e_aqc_switch_config_element_resp *ele = | |
14718 | &sw_config->element[i]; | |
14719 | ||
14720 | i40e_setup_pf_switch_element(pf, ele, num_reported, | |
14721 | printconfig); | |
14722 | } | |
14723 | } while (next_seid != 0); | |
14724 | ||
14725 | kfree(aq_buf); | |
14726 | return ret; | |
14727 | } | |
14728 | ||
14729 | /** | |
14730 | * i40e_setup_pf_switch - Setup the HW switch on startup or after reset | |
14731 | * @pf: board private structure | |
bc7d338f | 14732 | * @reinit: if the Main VSI needs to re-initialized. |
956e759d | 14733 | * @lock_acquired: indicates whether or not the lock has been acquired |
41c445ff JB |
14734 | * |
14735 | * Returns 0 on success, negative value on failure | |
14736 | **/ | |
956e759d | 14737 | static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit, bool lock_acquired) |
41c445ff | 14738 | { |
b5569892 | 14739 | u16 flags = 0; |
41c445ff JB |
14740 | int ret; |
14741 | ||
14742 | /* find out what's out there already */ | |
14743 | ret = i40e_fetch_switch_configuration(pf, false); | |
14744 | if (ret) { | |
14745 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
14746 | "couldn't fetch switch config, err %s aq_err %s\n", |
14747 | i40e_stat_str(&pf->hw, ret), | |
14748 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
14749 | return ret; |
14750 | } | |
14751 | i40e_pf_reset_stats(pf); | |
14752 | ||
b5569892 ASJ |
14753 | /* set the switch config bit for the whole device to |
14754 | * support limited promisc or true promisc | |
14755 | * when user requests promisc. The default is limited | |
14756 | * promisc. | |
14757 | */ | |
14758 | ||
14759 | if ((pf->hw.pf_id == 0) && | |
2f4b411a | 14760 | !(pf->flags & I40E_FLAG_TRUE_PROMISC_SUPPORT)) { |
b5569892 | 14761 | flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; |
2f4b411a AN |
14762 | pf->last_sw_conf_flags = flags; |
14763 | } | |
b5569892 ASJ |
14764 | |
14765 | if (pf->hw.pf_id == 0) { | |
14766 | u16 valid_flags; | |
14767 | ||
14768 | valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; | |
5efe0c6c | 14769 | ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags, 0, |
b5569892 ASJ |
14770 | NULL); |
14771 | if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) { | |
14772 | dev_info(&pf->pdev->dev, | |
14773 | "couldn't set switch config bits, err %s aq_err %s\n", | |
14774 | i40e_stat_str(&pf->hw, ret), | |
14775 | i40e_aq_str(&pf->hw, | |
14776 | pf->hw.aq.asq_last_status)); | |
14777 | /* not a fatal problem, just keep going */ | |
14778 | } | |
2f4b411a | 14779 | pf->last_sw_conf_valid_flags = valid_flags; |
b5569892 ASJ |
14780 | } |
14781 | ||
41c445ff | 14782 | /* first time setup */ |
bc7d338f | 14783 | if (pf->lan_vsi == I40E_NO_VSI || reinit) { |
41c445ff JB |
14784 | struct i40e_vsi *vsi = NULL; |
14785 | u16 uplink_seid; | |
14786 | ||
14787 | /* Set up the PF VSI associated with the PF's main VSI | |
14788 | * that is already in the HW switch | |
14789 | */ | |
f031c722 | 14790 | if (pf->lan_veb < I40E_MAX_VEB && pf->veb[pf->lan_veb]) |
41c445ff JB |
14791 | uplink_seid = pf->veb[pf->lan_veb]->seid; |
14792 | else | |
14793 | uplink_seid = pf->mac_seid; | |
bc7d338f ASJ |
14794 | if (pf->lan_vsi == I40E_NO_VSI) |
14795 | vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0); | |
14796 | else if (reinit) | |
14797 | vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]); | |
41c445ff JB |
14798 | if (!vsi) { |
14799 | dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n"); | |
aaf66502 | 14800 | i40e_cloud_filter_exit(pf); |
41c445ff JB |
14801 | i40e_fdir_teardown(pf); |
14802 | return -EAGAIN; | |
14803 | } | |
41c445ff JB |
14804 | } else { |
14805 | /* force a reset of TC and queue layout configurations */ | |
14806 | u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; | |
6995b36c | 14807 | |
41c445ff JB |
14808 | pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; |
14809 | pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; | |
14810 | i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); | |
14811 | } | |
14812 | i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]); | |
14813 | ||
cbf61325 ASJ |
14814 | i40e_fdir_sb_setup(pf); |
14815 | ||
41c445ff JB |
14816 | /* Setup static PF queue filter control settings */ |
14817 | ret = i40e_setup_pf_filter_control(pf); | |
14818 | if (ret) { | |
14819 | dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n", | |
14820 | ret); | |
14821 | /* Failure here should not stop continuing other steps */ | |
14822 | } | |
14823 | ||
14824 | /* enable RSS in the HW, even for only one queue, as the stack can use | |
14825 | * the hash | |
14826 | */ | |
14827 | if ((pf->flags & I40E_FLAG_RSS_ENABLED)) | |
043dd650 | 14828 | i40e_pf_config_rss(pf); |
41c445ff JB |
14829 | |
14830 | /* fill in link information and enable LSE reporting */ | |
a34a6711 MW |
14831 | i40e_link_event(pf); |
14832 | ||
d52c20b7 | 14833 | /* Initialize user-specific link properties */ |
41c445ff JB |
14834 | pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info & |
14835 | I40E_AQ_AN_COMPLETED) ? true : false); | |
d52c20b7 | 14836 | |
beb0dff1 JK |
14837 | i40e_ptp_init(pf); |
14838 | ||
956e759d JS |
14839 | if (!lock_acquired) |
14840 | rtnl_lock(); | |
14841 | ||
1f190d93 | 14842 | /* repopulate tunnel port filters */ |
40a98cb6 | 14843 | udp_tunnel_nic_reset_ntf(pf->vsi[pf->lan_vsi]->netdev); |
1f190d93 | 14844 | |
956e759d JS |
14845 | if (!lock_acquired) |
14846 | rtnl_unlock(); | |
14847 | ||
41c445ff JB |
14848 | return ret; |
14849 | } | |
14850 | ||
41c445ff JB |
14851 | /** |
14852 | * i40e_determine_queue_usage - Work out queue distribution | |
14853 | * @pf: board private structure | |
14854 | **/ | |
14855 | static void i40e_determine_queue_usage(struct i40e_pf *pf) | |
14856 | { | |
41c445ff | 14857 | int queues_left; |
e50d5751 | 14858 | int q_max; |
41c445ff JB |
14859 | |
14860 | pf->num_lan_qps = 0; | |
41c445ff JB |
14861 | |
14862 | /* Find the max queues to be put into basic use. We'll always be | |
14863 | * using TC0, whether or not DCB is running, and TC0 will get the | |
14864 | * big RSS set. | |
14865 | */ | |
14866 | queues_left = pf->hw.func_caps.num_tx_qp; | |
14867 | ||
cbf61325 | 14868 | if ((queues_left == 1) || |
9aa7e935 | 14869 | !(pf->flags & I40E_FLAG_MSIX_ENABLED)) { |
41c445ff JB |
14870 | /* one qp for PF, no queues for anything else */ |
14871 | queues_left = 0; | |
acd65448 | 14872 | pf->alloc_rss_size = pf->num_lan_qps = 1; |
41c445ff JB |
14873 | |
14874 | /* make sure all the fancies are disabled */ | |
60ea5f83 | 14875 | pf->flags &= ~(I40E_FLAG_RSS_ENABLED | |
e3219ce6 | 14876 | I40E_FLAG_IWARP_ENABLED | |
60ea5f83 JB |
14877 | I40E_FLAG_FD_SB_ENABLED | |
14878 | I40E_FLAG_FD_ATR_ENABLED | | |
4d9b6043 | 14879 | I40E_FLAG_DCB_CAPABLE | |
a036244c | 14880 | I40E_FLAG_DCB_ENABLED | |
60ea5f83 JB |
14881 | I40E_FLAG_SRIOV_ENABLED | |
14882 | I40E_FLAG_VMDQ_ENABLED); | |
2f4b411a | 14883 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
9aa7e935 FZ |
14884 | } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED | |
14885 | I40E_FLAG_FD_SB_ENABLED | | |
bbe7d0e0 | 14886 | I40E_FLAG_FD_ATR_ENABLED | |
4d9b6043 | 14887 | I40E_FLAG_DCB_CAPABLE))) { |
9aa7e935 | 14888 | /* one qp for PF */ |
acd65448 | 14889 | pf->alloc_rss_size = pf->num_lan_qps = 1; |
9aa7e935 FZ |
14890 | queues_left -= pf->num_lan_qps; |
14891 | ||
14892 | pf->flags &= ~(I40E_FLAG_RSS_ENABLED | | |
e3219ce6 | 14893 | I40E_FLAG_IWARP_ENABLED | |
9aa7e935 FZ |
14894 | I40E_FLAG_FD_SB_ENABLED | |
14895 | I40E_FLAG_FD_ATR_ENABLED | | |
14896 | I40E_FLAG_DCB_ENABLED | | |
14897 | I40E_FLAG_VMDQ_ENABLED); | |
2f4b411a | 14898 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
41c445ff | 14899 | } else { |
cbf61325 | 14900 | /* Not enough queues for all TCs */ |
4d9b6043 | 14901 | if ((pf->flags & I40E_FLAG_DCB_CAPABLE) && |
cbf61325 | 14902 | (queues_left < I40E_MAX_TRAFFIC_CLASS)) { |
a036244c DE |
14903 | pf->flags &= ~(I40E_FLAG_DCB_CAPABLE | |
14904 | I40E_FLAG_DCB_ENABLED); | |
cbf61325 ASJ |
14905 | dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n"); |
14906 | } | |
e50d5751 SN |
14907 | |
14908 | /* limit lan qps to the smaller of qps, cpus or msix */ | |
14909 | q_max = max_t(int, pf->rss_size_max, num_online_cpus()); | |
14910 | q_max = min_t(int, q_max, pf->hw.func_caps.num_tx_qp); | |
14911 | q_max = min_t(int, q_max, pf->hw.func_caps.num_msix_vectors); | |
14912 | pf->num_lan_qps = q_max; | |
9a3bd2f1 | 14913 | |
cbf61325 ASJ |
14914 | queues_left -= pf->num_lan_qps; |
14915 | } | |
14916 | ||
14917 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
14918 | if (queues_left > 1) { | |
14919 | queues_left -= 1; /* save 1 queue for FD */ | |
14920 | } else { | |
14921 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
2f4b411a | 14922 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
cbf61325 ASJ |
14923 | dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n"); |
14924 | } | |
41c445ff JB |
14925 | } |
14926 | ||
14927 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
14928 | pf->num_vf_qps && pf->num_req_vfs && queues_left) { | |
cbf61325 ASJ |
14929 | pf->num_req_vfs = min_t(int, pf->num_req_vfs, |
14930 | (queues_left / pf->num_vf_qps)); | |
41c445ff JB |
14931 | queues_left -= (pf->num_req_vfs * pf->num_vf_qps); |
14932 | } | |
14933 | ||
14934 | if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && | |
14935 | pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) { | |
14936 | pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis, | |
14937 | (queues_left / pf->num_vmdq_qps)); | |
14938 | queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps); | |
14939 | } | |
14940 | ||
f8ff1464 | 14941 | pf->queues_left = queues_left; |
8279e495 NP |
14942 | dev_dbg(&pf->pdev->dev, |
14943 | "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n", | |
14944 | pf->hw.func_caps.num_tx_qp, | |
14945 | !!(pf->flags & I40E_FLAG_FD_SB_ENABLED), | |
acd65448 HZ |
14946 | pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs, |
14947 | pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps, | |
14948 | queues_left); | |
41c445ff JB |
14949 | } |
14950 | ||
14951 | /** | |
14952 | * i40e_setup_pf_filter_control - Setup PF static filter control | |
14953 | * @pf: PF to be setup | |
14954 | * | |
b40c82e6 | 14955 | * i40e_setup_pf_filter_control sets up a PF's initial filter control |
41c445ff JB |
14956 | * settings. If PE/FCoE are enabled then it will also set the per PF |
14957 | * based filter sizes required for them. It also enables Flow director, | |
14958 | * ethertype and macvlan type filter settings for the pf. | |
14959 | * | |
14960 | * Returns 0 on success, negative on failure | |
14961 | **/ | |
14962 | static int i40e_setup_pf_filter_control(struct i40e_pf *pf) | |
14963 | { | |
14964 | struct i40e_filter_control_settings *settings = &pf->filter_settings; | |
14965 | ||
14966 | settings->hash_lut_size = I40E_HASH_LUT_SIZE_128; | |
14967 | ||
14968 | /* Flow Director is enabled */ | |
60ea5f83 | 14969 | if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)) |
41c445ff JB |
14970 | settings->enable_fdir = true; |
14971 | ||
14972 | /* Ethtype and MACVLAN filters enabled for PF */ | |
14973 | settings->enable_ethtype = true; | |
14974 | settings->enable_macvlan = true; | |
14975 | ||
14976 | if (i40e_set_filter_control(&pf->hw, settings)) | |
14977 | return -ENOENT; | |
14978 | ||
14979 | return 0; | |
14980 | } | |
14981 | ||
0c22b3dd | 14982 | #define INFO_STRING_LEN 255 |
7fd89545 | 14983 | #define REMAIN(__x) (INFO_STRING_LEN - (__x)) |
0c22b3dd JB |
14984 | static void i40e_print_features(struct i40e_pf *pf) |
14985 | { | |
14986 | struct i40e_hw *hw = &pf->hw; | |
3b195843 JP |
14987 | char *buf; |
14988 | int i; | |
0c22b3dd | 14989 | |
3b195843 JP |
14990 | buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL); |
14991 | if (!buf) | |
0c22b3dd | 14992 | return; |
0c22b3dd | 14993 | |
3b195843 | 14994 | i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id); |
0c22b3dd | 14995 | #ifdef CONFIG_PCI_IOV |
c28481a8 | 14996 | i += scnprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs); |
0c22b3dd | 14997 | #endif |
c28481a8 | 14998 | i += scnprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d", |
7fd89545 | 14999 | pf->hw.func_caps.num_vsis, |
1a557afc | 15000 | pf->vsi[pf->lan_vsi]->num_queue_pairs); |
0c22b3dd | 15001 | if (pf->flags & I40E_FLAG_RSS_ENABLED) |
c28481a8 | 15002 | i += scnprintf(&buf[i], REMAIN(i), " RSS"); |
0c22b3dd | 15003 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) |
c28481a8 | 15004 | i += scnprintf(&buf[i], REMAIN(i), " FD_ATR"); |
c6423ff1 | 15005 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
c28481a8 TI |
15006 | i += scnprintf(&buf[i], REMAIN(i), " FD_SB"); |
15007 | i += scnprintf(&buf[i], REMAIN(i), " NTUPLE"); | |
c6423ff1 | 15008 | } |
4d9b6043 | 15009 | if (pf->flags & I40E_FLAG_DCB_CAPABLE) |
c28481a8 TI |
15010 | i += scnprintf(&buf[i], REMAIN(i), " DCB"); |
15011 | i += scnprintf(&buf[i], REMAIN(i), " VxLAN"); | |
15012 | i += scnprintf(&buf[i], REMAIN(i), " Geneve"); | |
0c22b3dd | 15013 | if (pf->flags & I40E_FLAG_PTP) |
c28481a8 | 15014 | i += scnprintf(&buf[i], REMAIN(i), " PTP"); |
6dec1017 | 15015 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) |
c28481a8 | 15016 | i += scnprintf(&buf[i], REMAIN(i), " VEB"); |
6dec1017 | 15017 | else |
c28481a8 | 15018 | i += scnprintf(&buf[i], REMAIN(i), " VEPA"); |
0c22b3dd | 15019 | |
3b195843 JP |
15020 | dev_info(&pf->pdev->dev, "%s\n", buf); |
15021 | kfree(buf); | |
7fd89545 | 15022 | WARN_ON(i > INFO_STRING_LEN); |
0c22b3dd JB |
15023 | } |
15024 | ||
b499ffb0 SV |
15025 | /** |
15026 | * i40e_get_platform_mac_addr - get platform-specific MAC address | |
b499ffb0 SV |
15027 | * @pdev: PCI device information struct |
15028 | * @pf: board private structure | |
15029 | * | |
41c4c2b5 JK |
15030 | * Look up the MAC address for the device. First we'll try |
15031 | * eth_platform_get_mac_address, which will check Open Firmware, or arch | |
15032 | * specific fallback. Otherwise, we'll default to the stored value in | |
15033 | * firmware. | |
b499ffb0 SV |
15034 | **/ |
15035 | static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf) | |
15036 | { | |
41c4c2b5 JK |
15037 | if (eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr)) |
15038 | i40e_get_mac_addr(&pf->hw, pf->hw.mac.addr); | |
b499ffb0 SV |
15039 | } |
15040 | ||
1d963401 DD |
15041 | /** |
15042 | * i40e_set_fec_in_flags - helper function for setting FEC options in flags | |
15043 | * @fec_cfg: FEC option to set in flags | |
15044 | * @flags: ptr to flags in which we set FEC option | |
15045 | **/ | |
15046 | void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags) | |
15047 | { | |
15048 | if (fec_cfg & I40E_AQ_SET_FEC_AUTO) | |
15049 | *flags |= I40E_FLAG_RS_FEC | I40E_FLAG_BASE_R_FEC; | |
15050 | if ((fec_cfg & I40E_AQ_SET_FEC_REQUEST_RS) || | |
15051 | (fec_cfg & I40E_AQ_SET_FEC_ABILITY_RS)) { | |
15052 | *flags |= I40E_FLAG_RS_FEC; | |
15053 | *flags &= ~I40E_FLAG_BASE_R_FEC; | |
15054 | } | |
15055 | if ((fec_cfg & I40E_AQ_SET_FEC_REQUEST_KR) || | |
15056 | (fec_cfg & I40E_AQ_SET_FEC_ABILITY_KR)) { | |
15057 | *flags |= I40E_FLAG_BASE_R_FEC; | |
15058 | *flags &= ~I40E_FLAG_RS_FEC; | |
15059 | } | |
15060 | if (fec_cfg == 0) | |
15061 | *flags &= ~(I40E_FLAG_RS_FEC | I40E_FLAG_BASE_R_FEC); | |
15062 | } | |
15063 | ||
4ff0ee1a AM |
15064 | /** |
15065 | * i40e_check_recovery_mode - check if we are running transition firmware | |
15066 | * @pf: board private structure | |
15067 | * | |
15068 | * Check registers indicating the firmware runs in recovery mode. Sets the | |
15069 | * appropriate driver state. | |
15070 | * | |
15071 | * Returns true if the recovery mode was detected, false otherwise | |
15072 | **/ | |
15073 | static bool i40e_check_recovery_mode(struct i40e_pf *pf) | |
15074 | { | |
fffeeddf PK |
15075 | u32 val = rd32(&pf->hw, I40E_GL_FWSTS); |
15076 | ||
15077 | if (val & I40E_GL_FWSTS_FWS1B_MASK) { | |
15078 | dev_crit(&pf->pdev->dev, "Firmware recovery mode detected. Limiting functionality.\n"); | |
15079 | dev_crit(&pf->pdev->dev, "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); | |
4ff0ee1a AM |
15080 | set_bit(__I40E_RECOVERY_MODE, pf->state); |
15081 | ||
15082 | return true; | |
15083 | } | |
fffeeddf PK |
15084 | if (test_bit(__I40E_RECOVERY_MODE, pf->state)) |
15085 | dev_info(&pf->pdev->dev, "Please do Power-On Reset to initialize adapter in normal mode with full functionality.\n"); | |
4ff0ee1a AM |
15086 | |
15087 | return false; | |
15088 | } | |
15089 | ||
a39f165d PK |
15090 | /** |
15091 | * i40e_pf_loop_reset - perform reset in a loop. | |
15092 | * @pf: board private structure | |
15093 | * | |
15094 | * This function is useful when a NIC is about to enter recovery mode. | |
15095 | * When a NIC's internal data structures are corrupted the NIC's | |
15096 | * firmware is going to enter recovery mode. | |
15097 | * Right after a POR it takes about 7 minutes for firmware to enter | |
15098 | * recovery mode. Until that time a NIC is in some kind of intermediate | |
15099 | * state. After that time period the NIC almost surely enters | |
15100 | * recovery mode. The only way for a driver to detect intermediate | |
15101 | * state is to issue a series of pf-resets and check a return value. | |
15102 | * If a PF reset returns success then the firmware could be in recovery | |
15103 | * mode so the caller of this code needs to check for recovery mode | |
15104 | * if this function returns success. There is a little chance that | |
15105 | * firmware will hang in intermediate state forever. | |
15106 | * Since waiting 7 minutes is quite a lot of time this function waits | |
15107 | * 10 seconds and then gives up by returning an error. | |
15108 | * | |
15109 | * Return 0 on success, negative on failure. | |
15110 | **/ | |
15111 | static i40e_status i40e_pf_loop_reset(struct i40e_pf *pf) | |
15112 | { | |
91c534b5 PK |
15113 | /* wait max 10 seconds for PF reset to succeed */ |
15114 | const unsigned long time_end = jiffies + 10 * HZ; | |
15115 | ||
a39f165d PK |
15116 | struct i40e_hw *hw = &pf->hw; |
15117 | i40e_status ret; | |
a39f165d | 15118 | |
91c534b5 PK |
15119 | ret = i40e_pf_reset(hw); |
15120 | while (ret != I40E_SUCCESS && time_before(jiffies, time_end)) { | |
15121 | usleep_range(10000, 20000); | |
a39f165d | 15122 | ret = i40e_pf_reset(hw); |
a39f165d PK |
15123 | } |
15124 | ||
91c534b5 PK |
15125 | if (ret == I40E_SUCCESS) |
15126 | pf->pfr_count++; | |
15127 | else | |
a39f165d | 15128 | dev_info(&pf->pdev->dev, "PF reset failed: %d\n", ret); |
a39f165d | 15129 | |
a39f165d PK |
15130 | return ret; |
15131 | } | |
15132 | ||
fffeeddf PK |
15133 | /** |
15134 | * i40e_check_fw_empr - check if FW issued unexpected EMP Reset | |
15135 | * @pf: board private structure | |
15136 | * | |
15137 | * Check FW registers to determine if FW issued unexpected EMP Reset. | |
15138 | * Every time when unexpected EMP Reset occurs the FW increments | |
15139 | * a counter of unexpected EMP Resets. When the counter reaches 10 | |
15140 | * the FW should enter the Recovery mode | |
15141 | * | |
15142 | * Returns true if FW issued unexpected EMP Reset | |
15143 | **/ | |
15144 | static bool i40e_check_fw_empr(struct i40e_pf *pf) | |
15145 | { | |
15146 | const u32 fw_sts = rd32(&pf->hw, I40E_GL_FWSTS) & | |
15147 | I40E_GL_FWSTS_FWS1B_MASK; | |
15148 | return (fw_sts > I40E_GL_FWSTS_FWS1B_EMPR_0) && | |
15149 | (fw_sts <= I40E_GL_FWSTS_FWS1B_EMPR_10); | |
15150 | } | |
15151 | ||
15152 | /** | |
15153 | * i40e_handle_resets - handle EMP resets and PF resets | |
15154 | * @pf: board private structure | |
15155 | * | |
15156 | * Handle both EMP resets and PF resets and conclude whether there are | |
15157 | * any issues regarding these resets. If there are any issues then | |
15158 | * generate log entry. | |
15159 | * | |
15160 | * Return 0 if NIC is healthy or negative value when there are issues | |
15161 | * with resets | |
15162 | **/ | |
15163 | static i40e_status i40e_handle_resets(struct i40e_pf *pf) | |
15164 | { | |
15165 | const i40e_status pfr = i40e_pf_loop_reset(pf); | |
15166 | const bool is_empr = i40e_check_fw_empr(pf); | |
15167 | ||
15168 | if (is_empr || pfr != I40E_SUCCESS) | |
15169 | dev_crit(&pf->pdev->dev, "Entering recovery mode due to repeated FW resets. This may take several minutes. Refer to the Intel(R) Ethernet Adapters and Devices User Guide.\n"); | |
15170 | ||
15171 | return is_empr ? I40E_ERR_RESET_FAILED : pfr; | |
15172 | } | |
15173 | ||
4ff0ee1a AM |
15174 | /** |
15175 | * i40e_init_recovery_mode - initialize subsystems needed in recovery mode | |
15176 | * @pf: board private structure | |
15177 | * @hw: ptr to the hardware info | |
15178 | * | |
15179 | * This function does a minimal setup of all subsystems needed for running | |
15180 | * recovery mode. | |
15181 | * | |
15182 | * Returns 0 on success, negative on failure | |
15183 | **/ | |
15184 | static int i40e_init_recovery_mode(struct i40e_pf *pf, struct i40e_hw *hw) | |
15185 | { | |
15186 | struct i40e_vsi *vsi; | |
15187 | int err; | |
15188 | int v_idx; | |
15189 | ||
15190 | pci_save_state(pf->pdev); | |
15191 | ||
15192 | /* set up periodic task facility */ | |
15193 | timer_setup(&pf->service_timer, i40e_service_timer, 0); | |
15194 | pf->service_timer_period = HZ; | |
15195 | ||
15196 | INIT_WORK(&pf->service_task, i40e_service_task); | |
15197 | clear_bit(__I40E_SERVICE_SCHED, pf->state); | |
15198 | ||
15199 | err = i40e_init_interrupt_scheme(pf); | |
15200 | if (err) | |
15201 | goto err_switch_setup; | |
15202 | ||
15203 | /* The number of VSIs reported by the FW is the minimum guaranteed | |
15204 | * to us; HW supports far more and we share the remaining pool with | |
15205 | * the other PFs. We allocate space for more than the guarantee with | |
15206 | * the understanding that we might not get them all later. | |
15207 | */ | |
15208 | if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC) | |
15209 | pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC; | |
15210 | else | |
15211 | pf->num_alloc_vsi = pf->hw.func_caps.num_vsis; | |
15212 | ||
15213 | /* Set up the vsi struct and our local tracking of the MAIN PF vsi. */ | |
15214 | pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *), | |
15215 | GFP_KERNEL); | |
15216 | if (!pf->vsi) { | |
15217 | err = -ENOMEM; | |
15218 | goto err_switch_setup; | |
15219 | } | |
15220 | ||
15221 | /* We allocate one VSI which is needed as absolute minimum | |
15222 | * in order to register the netdev | |
15223 | */ | |
15224 | v_idx = i40e_vsi_mem_alloc(pf, I40E_VSI_MAIN); | |
8a1e918d AK |
15225 | if (v_idx < 0) { |
15226 | err = v_idx; | |
4ff0ee1a | 15227 | goto err_switch_setup; |
8a1e918d | 15228 | } |
4ff0ee1a AM |
15229 | pf->lan_vsi = v_idx; |
15230 | vsi = pf->vsi[v_idx]; | |
8a1e918d AK |
15231 | if (!vsi) { |
15232 | err = -EFAULT; | |
4ff0ee1a | 15233 | goto err_switch_setup; |
8a1e918d | 15234 | } |
4ff0ee1a AM |
15235 | vsi->alloc_queue_pairs = 1; |
15236 | err = i40e_config_netdev(vsi); | |
15237 | if (err) | |
15238 | goto err_switch_setup; | |
15239 | err = register_netdev(vsi->netdev); | |
15240 | if (err) | |
15241 | goto err_switch_setup; | |
15242 | vsi->netdev_registered = true; | |
15243 | i40e_dbg_pf_init(pf); | |
15244 | ||
15245 | err = i40e_setup_misc_vector_for_recovery_mode(pf); | |
15246 | if (err) | |
15247 | goto err_switch_setup; | |
15248 | ||
15249 | /* tell the firmware that we're starting */ | |
15250 | i40e_send_version(pf); | |
15251 | ||
15252 | /* since everything's happy, start the service_task timer */ | |
15253 | mod_timer(&pf->service_timer, | |
15254 | round_jiffies(jiffies + pf->service_timer_period)); | |
15255 | ||
15256 | return 0; | |
15257 | ||
15258 | err_switch_setup: | |
15259 | i40e_reset_interrupt_capability(pf); | |
15260 | del_timer_sync(&pf->service_timer); | |
15261 | i40e_shutdown_adminq(hw); | |
15262 | iounmap(hw->hw_addr); | |
15263 | pci_disable_pcie_error_reporting(pf->pdev); | |
15264 | pci_release_mem_regions(pf->pdev); | |
15265 | pci_disable_device(pf->pdev); | |
15266 | kfree(pf); | |
15267 | ||
15268 | return err; | |
15269 | } | |
15270 | ||
10507130 PK |
15271 | /** |
15272 | * i40e_set_subsystem_device_id - set subsystem device id | |
15273 | * @hw: pointer to the hardware info | |
15274 | * | |
15275 | * Set PCI subsystem device id either from a pci_dev structure or | |
15276 | * a specific FW register. | |
15277 | **/ | |
15278 | static inline void i40e_set_subsystem_device_id(struct i40e_hw *hw) | |
15279 | { | |
15280 | struct pci_dev *pdev = ((struct i40e_pf *)hw->back)->pdev; | |
15281 | ||
15282 | hw->subsystem_device_id = pdev->subsystem_device ? | |
15283 | pdev->subsystem_device : | |
15284 | (ushort)(rd32(hw, I40E_PFPCI_SUBSYSID) & USHRT_MAX); | |
15285 | } | |
15286 | ||
41c445ff JB |
15287 | /** |
15288 | * i40e_probe - Device initialization routine | |
15289 | * @pdev: PCI device information struct | |
15290 | * @ent: entry in i40e_pci_tbl | |
15291 | * | |
b40c82e6 JK |
15292 | * i40e_probe initializes a PF identified by a pci_dev structure. |
15293 | * The OS initialization, configuring of the PF private structure, | |
41c445ff JB |
15294 | * and a hardware reset occur. |
15295 | * | |
15296 | * Returns 0 on success, negative on failure | |
15297 | **/ | |
15298 | static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
15299 | { | |
e827845c | 15300 | struct i40e_aq_get_phy_abilities_resp abilities; |
4b208eaa AK |
15301 | #ifdef CONFIG_I40E_DCB |
15302 | enum i40e_get_fw_lldp_status_resp lldp_status; | |
15303 | i40e_status status; | |
15304 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
15305 | struct i40e_pf *pf; |
15306 | struct i40e_hw *hw; | |
93cd765b | 15307 | static u16 pfs_found; |
1d5109d1 | 15308 | u16 wol_nvm_bits; |
d4dfb81a | 15309 | u16 link_status; |
6f66a484 | 15310 | int err; |
4f2f017c | 15311 | u32 val; |
8a9eb7d3 | 15312 | u32 i; |
41c445ff JB |
15313 | |
15314 | err = pci_enable_device_mem(pdev); | |
15315 | if (err) | |
15316 | return err; | |
15317 | ||
15318 | /* set up for high or low dma */ | |
6494294f | 15319 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
6494294f | 15320 | if (err) { |
e3e3bfdd JS |
15321 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
15322 | if (err) { | |
15323 | dev_err(&pdev->dev, | |
15324 | "DMA configuration failed: 0x%x\n", err); | |
15325 | goto err_dma; | |
15326 | } | |
41c445ff JB |
15327 | } |
15328 | ||
15329 | /* set up pci connections */ | |
56d766d6 | 15330 | err = pci_request_mem_regions(pdev, i40e_driver_name); |
41c445ff JB |
15331 | if (err) { |
15332 | dev_info(&pdev->dev, | |
15333 | "pci_request_selected_regions failed %d\n", err); | |
15334 | goto err_pci_reg; | |
15335 | } | |
15336 | ||
15337 | pci_enable_pcie_error_reporting(pdev); | |
15338 | pci_set_master(pdev); | |
15339 | ||
15340 | /* Now that we have a PCI connection, we need to do the | |
15341 | * low level device setup. This is primarily setting up | |
15342 | * the Admin Queue structures and then querying for the | |
15343 | * device's current profile information. | |
15344 | */ | |
15345 | pf = kzalloc(sizeof(*pf), GFP_KERNEL); | |
15346 | if (!pf) { | |
15347 | err = -ENOMEM; | |
15348 | goto err_pf_alloc; | |
15349 | } | |
15350 | pf->next_vsi = 0; | |
15351 | pf->pdev = pdev; | |
9e6c9c0f | 15352 | set_bit(__I40E_DOWN, pf->state); |
41c445ff JB |
15353 | |
15354 | hw = &pf->hw; | |
15355 | hw->back = pf; | |
232f4706 | 15356 | |
2ac8b675 SN |
15357 | pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0), |
15358 | I40E_MAX_CSR_SPACE); | |
fefa9cfd AL |
15359 | /* We believe that the highest register to read is |
15360 | * I40E_GLGEN_STAT_CLEAR, so we check if the BAR size | |
15361 | * is not less than that before mapping to prevent a | |
15362 | * kernel panic. | |
15363 | */ | |
15364 | if (pf->ioremap_len < I40E_GLGEN_STAT_CLEAR) { | |
15365 | dev_err(&pdev->dev, "Cannot map registers, bar size 0x%X too small, aborting\n", | |
15366 | pf->ioremap_len); | |
15367 | err = -ENOMEM; | |
15368 | goto err_ioremap; | |
15369 | } | |
2ac8b675 | 15370 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len); |
41c445ff JB |
15371 | if (!hw->hw_addr) { |
15372 | err = -EIO; | |
15373 | dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n", | |
15374 | (unsigned int)pci_resource_start(pdev, 0), | |
2ac8b675 | 15375 | pf->ioremap_len, err); |
41c445ff JB |
15376 | goto err_ioremap; |
15377 | } | |
15378 | hw->vendor_id = pdev->vendor; | |
15379 | hw->device_id = pdev->device; | |
15380 | pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); | |
15381 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
10507130 | 15382 | i40e_set_subsystem_device_id(hw); |
41c445ff JB |
15383 | hw->bus.device = PCI_SLOT(pdev->devfn); |
15384 | hw->bus.func = PCI_FUNC(pdev->devfn); | |
b3f028fc | 15385 | hw->bus.bus_id = pdev->bus->number; |
93cd765b | 15386 | pf->instance = pfs_found; |
41c445ff | 15387 | |
ab243ec9 SP |
15388 | /* Select something other than the 802.1ad ethertype for the |
15389 | * switch to use internally and drop on ingress. | |
15390 | */ | |
15391 | hw->switch_tag = 0xffff; | |
15392 | hw->first_tag = ETH_P_8021AD; | |
15393 | hw->second_tag = ETH_P_8021Q; | |
15394 | ||
0e588de1 JK |
15395 | INIT_LIST_HEAD(&pf->l3_flex_pit_list); |
15396 | INIT_LIST_HEAD(&pf->l4_flex_pit_list); | |
cdc594e0 | 15397 | INIT_LIST_HEAD(&pf->ddp_old_prof); |
0e588de1 | 15398 | |
de03d2b0 SN |
15399 | /* set up the locks for the AQ, do this only once in probe |
15400 | * and destroy them only once in remove | |
15401 | */ | |
15402 | mutex_init(&hw->aq.asq_mutex); | |
15403 | mutex_init(&hw->aq.arq_mutex); | |
15404 | ||
5d4ca23e AD |
15405 | pf->msg_enable = netif_msg_init(debug, |
15406 | NETIF_MSG_DRV | | |
15407 | NETIF_MSG_PROBE | | |
15408 | NETIF_MSG_LINK); | |
15409 | if (debug < -1) | |
15410 | pf->hw.debug_mask = debug; | |
5b5faa43 | 15411 | |
7134f9ce JB |
15412 | /* do a special CORER for clearing PXE mode once at init */ |
15413 | if (hw->revision_id == 0 && | |
15414 | (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) { | |
15415 | wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK); | |
15416 | i40e_flush(hw); | |
15417 | msleep(200); | |
15418 | pf->corer_count++; | |
15419 | ||
15420 | i40e_clear_pxe_mode(hw); | |
15421 | } | |
15422 | ||
41c445ff | 15423 | /* Reset here to make sure all is clean and to define PF 'n' */ |
838d41d9 | 15424 | i40e_clear_hw(hw); |
a39f165d PK |
15425 | |
15426 | err = i40e_set_mac_type(hw); | |
15427 | if (err) { | |
15428 | dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n", | |
15429 | err); | |
15430 | goto err_pf_reset; | |
15431 | } | |
15432 | ||
fffeeddf PK |
15433 | err = i40e_handle_resets(pf); |
15434 | if (err) | |
a39f165d | 15435 | goto err_pf_reset; |
a39f165d PK |
15436 | |
15437 | i40e_check_recovery_mode(pf); | |
15438 | ||
5c208e9f CX |
15439 | if (is_kdump_kernel()) { |
15440 | hw->aq.num_arq_entries = I40E_MIN_ARQ_LEN; | |
15441 | hw->aq.num_asq_entries = I40E_MIN_ASQ_LEN; | |
15442 | } else { | |
15443 | hw->aq.num_arq_entries = I40E_AQ_LEN; | |
15444 | hw->aq.num_asq_entries = I40E_AQ_LEN; | |
15445 | } | |
41c445ff JB |
15446 | hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE; |
15447 | hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE; | |
15448 | pf->adminq_work_limit = I40E_AQ_WORK_LIMIT; | |
b2008cbf | 15449 | |
b294ac70 | 15450 | snprintf(pf->int_name, sizeof(pf->int_name) - 1, |
b2008cbf CW |
15451 | "%s-%s:misc", |
15452 | dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev)); | |
41c445ff JB |
15453 | |
15454 | err = i40e_init_shared_code(hw); | |
15455 | if (err) { | |
b2a75c58 ASJ |
15456 | dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n", |
15457 | err); | |
41c445ff JB |
15458 | goto err_pf_reset; |
15459 | } | |
15460 | ||
d52c20b7 JB |
15461 | /* set up a default setting for link flow control */ |
15462 | pf->hw.fc.requested_mode = I40E_FC_NONE; | |
15463 | ||
41c445ff | 15464 | err = i40e_init_adminq(hw); |
2b2426a7 CW |
15465 | if (err) { |
15466 | if (err == I40E_ERR_FIRMWARE_API_VERSION) | |
15467 | dev_info(&pdev->dev, | |
4fb29bdd AL |
15468 | "The driver for the device stopped because the NVM image v%u.%u is newer than expected v%u.%u. You must install the most recent version of the network driver.\n", |
15469 | hw->aq.api_maj_ver, | |
15470 | hw->aq.api_min_ver, | |
15471 | I40E_FW_API_VERSION_MAJOR, | |
15472 | I40E_FW_MINOR_VERSION(hw)); | |
2b2426a7 CW |
15473 | else |
15474 | dev_info(&pdev->dev, | |
15475 | "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n"); | |
15476 | ||
15477 | goto err_pf_reset; | |
15478 | } | |
5bbb2e20 | 15479 | i40e_get_oem_version(hw); |
f0b44440 | 15480 | |
a121644c SA |
15481 | /* provide nvm, fw, api versions, vendor:device id, subsys vendor:device id */ |
15482 | dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s [%04x:%04x] [%04x:%04x]\n", | |
6dec1017 SN |
15483 | hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build, |
15484 | hw->aq.api_maj_ver, hw->aq.api_min_ver, | |
a121644c SA |
15485 | i40e_nvm_version_str(hw), hw->vendor_id, hw->device_id, |
15486 | hw->subsystem_vendor_id, hw->subsystem_device_id); | |
f0b44440 | 15487 | |
7aa67613 | 15488 | if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && |
22b96551 | 15489 | hw->aq.api_min_ver > I40E_FW_MINOR_VERSION(hw)) |
40feded8 MP |
15490 | dev_dbg(&pdev->dev, |
15491 | "The driver for the device detected a newer version of the NVM image v%u.%u than v%u.%u.\n", | |
4fb29bdd AL |
15492 | hw->aq.api_maj_ver, |
15493 | hw->aq.api_min_ver, | |
15494 | I40E_FW_API_VERSION_MAJOR, | |
15495 | I40E_FW_MINOR_VERSION(hw)); | |
e04ea002 | 15496 | else if (hw->aq.api_maj_ver == 1 && hw->aq.api_min_ver < 4) |
278b6f62 | 15497 | dev_info(&pdev->dev, |
4fb29bdd AL |
15498 | "The driver for the device detected an older version of the NVM image v%u.%u than expected v%u.%u. Please update the NVM image.\n", |
15499 | hw->aq.api_maj_ver, | |
15500 | hw->aq.api_min_ver, | |
15501 | I40E_FW_API_VERSION_MAJOR, | |
15502 | I40E_FW_MINOR_VERSION(hw)); | |
278b6f62 | 15503 | |
4eb3f768 SN |
15504 | i40e_verify_eeprom(pf); |
15505 | ||
2c5fe33b JB |
15506 | /* Rev 0 hardware was never productized */ |
15507 | if (hw->revision_id < 1) | |
15508 | dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n"); | |
15509 | ||
6ff4ef86 | 15510 | i40e_clear_pxe_mode(hw); |
4ff0ee1a | 15511 | |
2f4b411a | 15512 | err = i40e_get_capabilities(pf, i40e_aqc_opc_list_func_capabilities); |
41c445ff JB |
15513 | if (err) |
15514 | goto err_adminq_setup; | |
15515 | ||
15516 | err = i40e_sw_init(pf); | |
15517 | if (err) { | |
15518 | dev_info(&pdev->dev, "sw_init failed: %d\n", err); | |
15519 | goto err_sw_init; | |
15520 | } | |
15521 | ||
4ff0ee1a AM |
15522 | if (test_bit(__I40E_RECOVERY_MODE, pf->state)) |
15523 | return i40e_init_recovery_mode(pf, hw); | |
15524 | ||
41c445ff | 15525 | err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, |
c76cb6ed | 15526 | hw->func_caps.num_rx_qp, 0, 0); |
41c445ff JB |
15527 | if (err) { |
15528 | dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err); | |
15529 | goto err_init_lan_hmc; | |
15530 | } | |
15531 | ||
15532 | err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); | |
15533 | if (err) { | |
15534 | dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err); | |
15535 | err = -ENOENT; | |
15536 | goto err_configure_lan_hmc; | |
15537 | } | |
15538 | ||
b686ece5 NP |
15539 | /* Disable LLDP for NICs that have firmware versions lower than v4.3. |
15540 | * Ignore error return codes because if it was already disabled via | |
15541 | * hardware settings this will fail | |
15542 | */ | |
d36e41dc | 15543 | if (pf->hw_features & I40E_HW_STOP_FW_LLDP) { |
b686ece5 | 15544 | dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n"); |
c65e78f8 | 15545 | i40e_aq_stop_lldp(hw, true, false, NULL); |
b686ece5 NP |
15546 | } |
15547 | ||
b499ffb0 SV |
15548 | /* allow a platform config to override the HW addr */ |
15549 | i40e_get_platform_mac_addr(pdev, pf); | |
41c4c2b5 | 15550 | |
f62b5060 | 15551 | if (!is_valid_ether_addr(hw->mac.addr)) { |
41c445ff JB |
15552 | dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr); |
15553 | err = -EIO; | |
15554 | goto err_mac_addr; | |
15555 | } | |
15556 | dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr); | |
9a173901 | 15557 | ether_addr_copy(hw->mac.perm_addr, hw->mac.addr); |
1f224ad2 NP |
15558 | i40e_get_port_mac_addr(hw, hw->mac.port_addr); |
15559 | if (is_valid_ether_addr(hw->mac.port_addr)) | |
d36e41dc | 15560 | pf->hw_features |= I40E_HW_PORT_ID_VALID; |
41c445ff | 15561 | |
10507130 | 15562 | i40e_ptp_alloc_pins(pf); |
41c445ff JB |
15563 | pci_set_drvdata(pdev, pf); |
15564 | pci_save_state(pdev); | |
c61c8fe1 | 15565 | |
4b208eaa AK |
15566 | #ifdef CONFIG_I40E_DCB |
15567 | status = i40e_get_fw_lldp_status(&pf->hw, &lldp_status); | |
15568 | (!status && | |
15569 | lldp_status == I40E_GET_FW_LLDP_STATUS_ENABLED) ? | |
15570 | (pf->flags &= ~I40E_FLAG_DISABLE_FW_LLDP) : | |
15571 | (pf->flags |= I40E_FLAG_DISABLE_FW_LLDP); | |
ee02865e AL |
15572 | dev_info(&pdev->dev, |
15573 | (pf->flags & I40E_FLAG_DISABLE_FW_LLDP) ? | |
15574 | "FW LLDP is disabled\n" : | |
15575 | "FW LLDP is enabled\n"); | |
15576 | ||
c61c8fe1 DE |
15577 | /* Enable FW to write default DCB config on link-up */ |
15578 | i40e_aq_set_dcb_parameters(hw, true, NULL); | |
15579 | ||
4e3b35b0 NP |
15580 | err = i40e_init_pf_dcb(pf); |
15581 | if (err) { | |
aebfc816 | 15582 | dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err); |
c17ef430 | 15583 | pf->flags &= ~(I40E_FLAG_DCB_CAPABLE | I40E_FLAG_DCB_ENABLED); |
014269ff | 15584 | /* Continue without DCB enabled */ |
4e3b35b0 NP |
15585 | } |
15586 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
15587 | |
15588 | /* set up periodic task facility */ | |
26566eae | 15589 | timer_setup(&pf->service_timer, i40e_service_timer, 0); |
41c445ff JB |
15590 | pf->service_timer_period = HZ; |
15591 | ||
15592 | INIT_WORK(&pf->service_task, i40e_service_task); | |
0da36b97 | 15593 | clear_bit(__I40E_SERVICE_SCHED, pf->state); |
41c445ff | 15594 | |
1d5109d1 SN |
15595 | /* NVM bit on means WoL disabled for the port */ |
15596 | i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits); | |
75f5cea9 | 15597 | if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1) |
1d5109d1 SN |
15598 | pf->wol_en = false; |
15599 | else | |
15600 | pf->wol_en = true; | |
8e2773ae SN |
15601 | device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en); |
15602 | ||
41c445ff JB |
15603 | /* set up the main switch operations */ |
15604 | i40e_determine_queue_usage(pf); | |
c1147280 JB |
15605 | err = i40e_init_interrupt_scheme(pf); |
15606 | if (err) | |
15607 | goto err_switch_setup; | |
41c445ff | 15608 | |
065aa694 CX |
15609 | /* Reduce Tx and Rx pairs for kdump |
15610 | * When MSI-X is enabled, it's not allowed to use more TC queue | |
15611 | * pairs than MSI-X vectors (pf->num_lan_msix) exist. Thus | |
15612 | * vsi->num_queue_pairs will be equal to pf->num_lan_msix, i.e., 1. | |
15613 | */ | |
15614 | if (is_kdump_kernel()) | |
15615 | pf->num_lan_msix = 1; | |
15616 | ||
40a98cb6 JK |
15617 | pf->udp_tunnel_nic.set_port = i40e_udp_tunnel_set_port; |
15618 | pf->udp_tunnel_nic.unset_port = i40e_udp_tunnel_unset_port; | |
15619 | pf->udp_tunnel_nic.flags = UDP_TUNNEL_NIC_INFO_MAY_SLEEP; | |
15620 | pf->udp_tunnel_nic.shared = &pf->udp_tunnel_shared; | |
15621 | pf->udp_tunnel_nic.tables[0].n_entries = I40E_MAX_PF_UDP_OFFLOAD_PORTS; | |
15622 | pf->udp_tunnel_nic.tables[0].tunnel_types = UDP_TUNNEL_TYPE_VXLAN | | |
15623 | UDP_TUNNEL_TYPE_GENEVE; | |
15624 | ||
505682cd MW |
15625 | /* The number of VSIs reported by the FW is the minimum guaranteed |
15626 | * to us; HW supports far more and we share the remaining pool with | |
15627 | * the other PFs. We allocate space for more than the guarantee with | |
15628 | * the understanding that we might not get them all later. | |
41c445ff | 15629 | */ |
505682cd MW |
15630 | if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC) |
15631 | pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC; | |
15632 | else | |
15633 | pf->num_alloc_vsi = pf->hw.func_caps.num_vsis; | |
40a98cb6 JK |
15634 | if (pf->num_alloc_vsi > UDP_TUNNEL_NIC_MAX_SHARING_DEVICES) { |
15635 | dev_warn(&pf->pdev->dev, | |
15636 | "limiting the VSI count due to UDP tunnel limitation %d > %d\n", | |
15637 | pf->num_alloc_vsi, UDP_TUNNEL_NIC_MAX_SHARING_DEVICES); | |
15638 | pf->num_alloc_vsi = UDP_TUNNEL_NIC_MAX_SHARING_DEVICES; | |
15639 | } | |
505682cd MW |
15640 | |
15641 | /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */ | |
d17038d6 JB |
15642 | pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *), |
15643 | GFP_KERNEL); | |
ed87ac09 WY |
15644 | if (!pf->vsi) { |
15645 | err = -ENOMEM; | |
41c445ff | 15646 | goto err_switch_setup; |
ed87ac09 | 15647 | } |
41c445ff | 15648 | |
fa11cb3d ASJ |
15649 | #ifdef CONFIG_PCI_IOV |
15650 | /* prep for VF support */ | |
15651 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
15652 | (pf->flags & I40E_FLAG_MSIX_ENABLED) && | |
0da36b97 | 15653 | !test_bit(__I40E_BAD_EEPROM, pf->state)) { |
fa11cb3d ASJ |
15654 | if (pci_num_vf(pdev)) |
15655 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
15656 | } | |
15657 | #endif | |
956e759d | 15658 | err = i40e_setup_pf_switch(pf, false, false); |
41c445ff JB |
15659 | if (err) { |
15660 | dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err); | |
15661 | goto err_vsis; | |
15662 | } | |
8f88b303 | 15663 | INIT_LIST_HEAD(&pf->vsi[pf->lan_vsi]->ch_list); |
58fc3267 | 15664 | |
8a9eb7d3 | 15665 | /* if FDIR VSI was set up, start it now */ |
505682cd | 15666 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
8a9eb7d3 SN |
15667 | if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) { |
15668 | i40e_vsi_open(pf->vsi[i]); | |
15669 | break; | |
15670 | } | |
15671 | } | |
41c445ff | 15672 | |
2f0aff41 SN |
15673 | /* The driver only wants link up/down and module qualification |
15674 | * reports from firmware. Note the negative logic. | |
7e2453fe JB |
15675 | */ |
15676 | err = i40e_aq_set_phy_int_mask(&pf->hw, | |
2f0aff41 | 15677 | ~(I40E_AQ_EVENT_LINK_UPDOWN | |
867a79e3 | 15678 | I40E_AQ_EVENT_MEDIA_NA | |
2f0aff41 | 15679 | I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); |
7e2453fe | 15680 | if (err) |
f1c7e72e SN |
15681 | dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", |
15682 | i40e_stat_str(&pf->hw, err), | |
15683 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7e2453fe | 15684 | |
4f2f017c ASJ |
15685 | /* Reconfigure hardware for allowing smaller MSS in the case |
15686 | * of TSO, so that we avoid the MDD being fired and causing | |
15687 | * a reset in the case of small MSS+TSO. | |
15688 | */ | |
15689 | val = rd32(hw, I40E_REG_MSS); | |
15690 | if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { | |
15691 | val &= ~I40E_REG_MSS_MIN_MASK; | |
15692 | val |= I40E_64BYTE_MSS; | |
15693 | wr32(hw, I40E_REG_MSS, val); | |
15694 | } | |
15695 | ||
d36e41dc | 15696 | if (pf->hw_features & I40E_HW_RESTART_AUTONEG) { |
025b4a54 ASJ |
15697 | msleep(75); |
15698 | err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); | |
15699 | if (err) | |
f1c7e72e SN |
15700 | dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", |
15701 | i40e_stat_str(&pf->hw, err), | |
15702 | i40e_aq_str(&pf->hw, | |
15703 | pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 15704 | } |
41c445ff JB |
15705 | /* The main driver is (mostly) up and happy. We need to set this state |
15706 | * before setting up the misc vector or we get a race and the vector | |
15707 | * ends up disabled forever. | |
15708 | */ | |
9e6c9c0f | 15709 | clear_bit(__I40E_DOWN, pf->state); |
41c445ff JB |
15710 | |
15711 | /* In case of MSIX we are going to setup the misc vector right here | |
15712 | * to handle admin queue events etc. In case of legacy and MSI | |
15713 | * the misc functionality and queue processing is combined in | |
15714 | * the same vector and that gets setup at open. | |
15715 | */ | |
15716 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
15717 | err = i40e_setup_misc_vector(pf); | |
15718 | if (err) { | |
15719 | dev_info(&pdev->dev, | |
15720 | "setup of misc vector failed: %d\n", err); | |
58cab46c KS |
15721 | i40e_cloud_filter_exit(pf); |
15722 | i40e_fdir_teardown(pf); | |
41c445ff JB |
15723 | goto err_vsis; |
15724 | } | |
15725 | } | |
15726 | ||
df805f62 | 15727 | #ifdef CONFIG_PCI_IOV |
41c445ff JB |
15728 | /* prep for VF support */ |
15729 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
4eb3f768 | 15730 | (pf->flags & I40E_FLAG_MSIX_ENABLED) && |
0da36b97 | 15731 | !test_bit(__I40E_BAD_EEPROM, pf->state)) { |
41c445ff JB |
15732 | /* disable link interrupts for VFs */ |
15733 | val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM); | |
15734 | val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK; | |
15735 | wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val); | |
15736 | i40e_flush(hw); | |
4aeec010 MW |
15737 | |
15738 | if (pci_num_vf(pdev)) { | |
15739 | dev_info(&pdev->dev, | |
15740 | "Active VFs found, allocating resources.\n"); | |
15741 | err = i40e_alloc_vfs(pf, pci_num_vf(pdev)); | |
15742 | if (err) | |
15743 | dev_info(&pdev->dev, | |
15744 | "Error %d allocating resources for existing VFs\n", | |
15745 | err); | |
15746 | } | |
41c445ff | 15747 | } |
df805f62 | 15748 | #endif /* CONFIG_PCI_IOV */ |
41c445ff | 15749 | |
e3219ce6 ASJ |
15750 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
15751 | pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile, | |
15752 | pf->num_iwarp_msix, | |
15753 | I40E_IWARP_IRQ_PILE_ID); | |
15754 | if (pf->iwarp_base_vector < 0) { | |
15755 | dev_info(&pdev->dev, | |
15756 | "failed to get tracking for %d vectors for IWARP err=%d\n", | |
15757 | pf->num_iwarp_msix, pf->iwarp_base_vector); | |
15758 | pf->flags &= ~I40E_FLAG_IWARP_ENABLED; | |
15759 | } | |
15760 | } | |
93cd765b | 15761 | |
41c445ff JB |
15762 | i40e_dbg_pf_init(pf); |
15763 | ||
15764 | /* tell the firmware that we're starting */ | |
44033fac | 15765 | i40e_send_version(pf); |
41c445ff JB |
15766 | |
15767 | /* since everything's happy, start the service_task timer */ | |
15768 | mod_timer(&pf->service_timer, | |
15769 | round_jiffies(jiffies + pf->service_timer_period)); | |
15770 | ||
e3219ce6 | 15771 | /* add this PF to client device list and launch a client service task */ |
004eb614 MW |
15772 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
15773 | err = i40e_lan_add_device(pf); | |
15774 | if (err) | |
15775 | dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n", | |
15776 | err); | |
15777 | } | |
e3219ce6 | 15778 | |
3fced535 ASJ |
15779 | #define PCI_SPEED_SIZE 8 |
15780 | #define PCI_WIDTH_SIZE 8 | |
15781 | /* Devices on the IOSF bus do not have this information | |
15782 | * and will report PCI Gen 1 x 1 by default so don't bother | |
15783 | * checking them. | |
15784 | */ | |
d36e41dc | 15785 | if (!(pf->hw_features & I40E_HW_NO_PCI_LINK_CHECK)) { |
3fced535 ASJ |
15786 | char speed[PCI_SPEED_SIZE] = "Unknown"; |
15787 | char width[PCI_WIDTH_SIZE] = "Unknown"; | |
15788 | ||
15789 | /* Get the negotiated link width and speed from PCI config | |
15790 | * space | |
15791 | */ | |
15792 | pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, | |
15793 | &link_status); | |
15794 | ||
15795 | i40e_set_pci_config_data(hw, link_status); | |
15796 | ||
15797 | switch (hw->bus.speed) { | |
15798 | case i40e_bus_speed_8000: | |
4ff2d854 | 15799 | strlcpy(speed, "8.0", PCI_SPEED_SIZE); break; |
3fced535 | 15800 | case i40e_bus_speed_5000: |
4ff2d854 | 15801 | strlcpy(speed, "5.0", PCI_SPEED_SIZE); break; |
3fced535 | 15802 | case i40e_bus_speed_2500: |
4ff2d854 | 15803 | strlcpy(speed, "2.5", PCI_SPEED_SIZE); break; |
3fced535 ASJ |
15804 | default: |
15805 | break; | |
15806 | } | |
15807 | switch (hw->bus.width) { | |
15808 | case i40e_bus_width_pcie_x8: | |
4ff2d854 | 15809 | strlcpy(width, "8", PCI_WIDTH_SIZE); break; |
3fced535 | 15810 | case i40e_bus_width_pcie_x4: |
4ff2d854 | 15811 | strlcpy(width, "4", PCI_WIDTH_SIZE); break; |
3fced535 | 15812 | case i40e_bus_width_pcie_x2: |
4ff2d854 | 15813 | strlcpy(width, "2", PCI_WIDTH_SIZE); break; |
3fced535 | 15814 | case i40e_bus_width_pcie_x1: |
4ff2d854 | 15815 | strlcpy(width, "1", PCI_WIDTH_SIZE); break; |
3fced535 ASJ |
15816 | default: |
15817 | break; | |
15818 | } | |
15819 | ||
15820 | dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n", | |
15821 | speed, width); | |
15822 | ||
15823 | if (hw->bus.width < i40e_bus_width_pcie_x8 || | |
15824 | hw->bus.speed < i40e_bus_speed_8000) { | |
15825 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n"); | |
15826 | dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n"); | |
15827 | } | |
d4dfb81a CS |
15828 | } |
15829 | ||
e827845c CS |
15830 | /* get the requested speeds from the fw */ |
15831 | err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL); | |
15832 | if (err) | |
8279e495 NP |
15833 | dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n", |
15834 | i40e_stat_str(&pf->hw, err), | |
15835 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
e827845c CS |
15836 | pf->hw.phy.link_info.requested_speeds = abilities.link_speed; |
15837 | ||
1d963401 DD |
15838 | /* set the FEC config due to the board capabilities */ |
15839 | i40e_set_fec_in_flags(abilities.fec_cfg_curr_mod_ext_info, &pf->flags); | |
15840 | ||
fc72dbce CS |
15841 | /* get the supported phy types from the fw */ |
15842 | err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL); | |
15843 | if (err) | |
15844 | dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n", | |
15845 | i40e_stat_str(&pf->hw, err), | |
15846 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
fc72dbce | 15847 | |
3a2c6ced TF |
15848 | /* make sure the MFS hasn't been set lower than the default */ |
15849 | #define MAX_FRAME_SIZE_DEFAULT 0x2600 | |
15850 | val = (rd32(&pf->hw, I40E_PRTGL_SAH) & | |
15851 | I40E_PRTGL_SAH_MFS_MASK) >> I40E_PRTGL_SAH_MFS_SHIFT; | |
15852 | if (val < MAX_FRAME_SIZE_DEFAULT) | |
15853 | dev_warn(&pdev->dev, "MFS for port %x has been set below the default: %x\n", | |
15854 | i, val); | |
15855 | ||
e7358f54 ASJ |
15856 | /* Add a filter to drop all Flow control frames from any VSI from being |
15857 | * transmitted. By doing so we stop a malicious VF from sending out | |
15858 | * PAUSE or PFC frames and potentially controlling traffic for other | |
15859 | * PF/VF VSIs. | |
15860 | * The FW can still send Flow control frames if enabled. | |
15861 | */ | |
15862 | i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, | |
15863 | pf->main_vsi_seid); | |
15864 | ||
31b606d0 | 15865 | if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) || |
4f9b4307 | 15866 | (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4)) |
d36e41dc | 15867 | pf->hw_features |= I40E_HW_PHY_CONTROLS_LEDS; |
4ad9f4f9 | 15868 | if (pf->hw.device_id == I40E_DEV_ID_SFP_I_X722) |
d36e41dc | 15869 | pf->hw_features |= I40E_HW_HAVE_CRT_RETIMER; |
0c22b3dd JB |
15870 | /* print a string summarizing features */ |
15871 | i40e_print_features(pf); | |
15872 | ||
41c445ff JB |
15873 | return 0; |
15874 | ||
15875 | /* Unwind what we've done if something failed in the setup */ | |
15876 | err_vsis: | |
9e6c9c0f | 15877 | set_bit(__I40E_DOWN, pf->state); |
41c445ff JB |
15878 | i40e_clear_interrupt_scheme(pf); |
15879 | kfree(pf->vsi); | |
04b03013 SN |
15880 | err_switch_setup: |
15881 | i40e_reset_interrupt_capability(pf); | |
41c445ff JB |
15882 | del_timer_sync(&pf->service_timer); |
15883 | err_mac_addr: | |
15884 | err_configure_lan_hmc: | |
15885 | (void)i40e_shutdown_lan_hmc(hw); | |
15886 | err_init_lan_hmc: | |
15887 | kfree(pf->qp_pile); | |
41c445ff JB |
15888 | err_sw_init: |
15889 | err_adminq_setup: | |
41c445ff JB |
15890 | err_pf_reset: |
15891 | iounmap(hw->hw_addr); | |
15892 | err_ioremap: | |
15893 | kfree(pf); | |
15894 | err_pf_alloc: | |
15895 | pci_disable_pcie_error_reporting(pdev); | |
56d766d6 | 15896 | pci_release_mem_regions(pdev); |
41c445ff JB |
15897 | err_pci_reg: |
15898 | err_dma: | |
15899 | pci_disable_device(pdev); | |
15900 | return err; | |
15901 | } | |
15902 | ||
15903 | /** | |
15904 | * i40e_remove - Device removal routine | |
15905 | * @pdev: PCI device information struct | |
15906 | * | |
15907 | * i40e_remove is called by the PCI subsystem to alert the driver | |
15908 | * that is should release a PCI device. This could be caused by a | |
15909 | * Hot-Plug event, or because the driver is going to be removed from | |
15910 | * memory. | |
15911 | **/ | |
15912 | static void i40e_remove(struct pci_dev *pdev) | |
15913 | { | |
15914 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
bcab2db9 | 15915 | struct i40e_hw *hw = &pf->hw; |
41c445ff | 15916 | i40e_status ret_code; |
41c445ff JB |
15917 | int i; |
15918 | ||
15919 | i40e_dbg_pf_exit(pf); | |
15920 | ||
beb0dff1 JK |
15921 | i40e_ptp_stop(pf); |
15922 | ||
bcab2db9 | 15923 | /* Disable RSS in hw */ |
272cdaf2 SN |
15924 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0); |
15925 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0); | |
bcab2db9 | 15926 | |
5b6d4a7f GS |
15927 | while (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
15928 | usleep_range(1000, 2000); | |
15929 | ||
2980cbd4 SD |
15930 | if (pf->flags & I40E_FLAG_SRIOV_ENABLED) { |
15931 | set_bit(__I40E_VF_RESETS_DISABLED, pf->state); | |
15932 | i40e_free_vfs(pf); | |
15933 | pf->flags &= ~I40E_FLAG_SRIOV_ENABLED; | |
15934 | } | |
41c445ff | 15935 | /* no more scheduling of any task */ |
0da36b97 | 15936 | set_bit(__I40E_SUSPENDED, pf->state); |
9e6c9c0f | 15937 | set_bit(__I40E_DOWN, pf->state); |
26566eae | 15938 | if (pf->service_timer.function) |
c99abb4c SN |
15939 | del_timer_sync(&pf->service_timer); |
15940 | if (pf->service_task.func) | |
15941 | cancel_work_sync(&pf->service_task); | |
41c445ff | 15942 | |
4ff0ee1a AM |
15943 | if (test_bit(__I40E_RECOVERY_MODE, pf->state)) { |
15944 | struct i40e_vsi *vsi = pf->vsi[0]; | |
15945 | ||
15946 | /* We know that we have allocated only one vsi for this PF, | |
15947 | * it was just for registering netdevice, so the interface | |
15948 | * could be visible in the 'ifconfig' output | |
15949 | */ | |
15950 | unregister_netdev(vsi->netdev); | |
15951 | free_netdev(vsi->netdev); | |
15952 | ||
15953 | goto unmap; | |
15954 | } | |
15955 | ||
921c467c MW |
15956 | /* Client close must be called explicitly here because the timer |
15957 | * has been stopped. | |
15958 | */ | |
15959 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false); | |
15960 | ||
41c445ff JB |
15961 | i40e_fdir_teardown(pf); |
15962 | ||
15963 | /* If there is a switch structure or any orphans, remove them. | |
15964 | * This will leave only the PF's VSI remaining. | |
15965 | */ | |
15966 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
15967 | if (!pf->veb[i]) | |
15968 | continue; | |
15969 | ||
15970 | if (pf->veb[i]->uplink_seid == pf->mac_seid || | |
15971 | pf->veb[i]->uplink_seid == 0) | |
15972 | i40e_switch_branch_release(pf->veb[i]); | |
15973 | } | |
15974 | ||
15975 | /* Now we can shutdown the PF's VSI, just before we kill | |
15976 | * adminq and hmc. | |
15977 | */ | |
15978 | if (pf->vsi[pf->lan_vsi]) | |
15979 | i40e_vsi_release(pf->vsi[pf->lan_vsi]); | |
15980 | ||
aaf66502 AN |
15981 | i40e_cloud_filter_exit(pf); |
15982 | ||
e3219ce6 | 15983 | /* remove attached clients */ |
004eb614 MW |
15984 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
15985 | ret_code = i40e_lan_del_device(pf); | |
15986 | if (ret_code) | |
15987 | dev_warn(&pdev->dev, "Failed to delete client device: %d\n", | |
15988 | ret_code); | |
e3219ce6 ASJ |
15989 | } |
15990 | ||
41c445ff | 15991 | /* shutdown and destroy the HMC */ |
f734dfff JB |
15992 | if (hw->hmc.hmc_obj) { |
15993 | ret_code = i40e_shutdown_lan_hmc(hw); | |
60442dea SN |
15994 | if (ret_code) |
15995 | dev_warn(&pdev->dev, | |
15996 | "Failed to destroy the HMC resources: %d\n", | |
15997 | ret_code); | |
15998 | } | |
41c445ff | 15999 | |
4ff0ee1a AM |
16000 | unmap: |
16001 | /* Free MSI/legacy interrupt 0 when in recovery mode. */ | |
16002 | if (test_bit(__I40E_RECOVERY_MODE, pf->state) && | |
16003 | !(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
16004 | free_irq(pf->pdev->irq, pf); | |
16005 | ||
41c445ff | 16006 | /* shutdown the adminq */ |
ac9c5c6d | 16007 | i40e_shutdown_adminq(hw); |
41c445ff | 16008 | |
8ddb3326 JB |
16009 | /* destroy the locks only once, here */ |
16010 | mutex_destroy(&hw->aq.arq_mutex); | |
16011 | mutex_destroy(&hw->aq.asq_mutex); | |
16012 | ||
41c445ff | 16013 | /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */ |
5cba17b1 | 16014 | rtnl_lock(); |
41c445ff | 16015 | i40e_clear_interrupt_scheme(pf); |
505682cd | 16016 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff | 16017 | if (pf->vsi[i]) { |
4ff0ee1a AM |
16018 | if (!test_bit(__I40E_RECOVERY_MODE, pf->state)) |
16019 | i40e_vsi_clear_rings(pf->vsi[i]); | |
41c445ff JB |
16020 | i40e_vsi_clear(pf->vsi[i]); |
16021 | pf->vsi[i] = NULL; | |
16022 | } | |
16023 | } | |
5cba17b1 | 16024 | rtnl_unlock(); |
41c445ff JB |
16025 | |
16026 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
16027 | kfree(pf->veb[i]); | |
16028 | pf->veb[i] = NULL; | |
16029 | } | |
16030 | ||
16031 | kfree(pf->qp_pile); | |
41c445ff JB |
16032 | kfree(pf->vsi); |
16033 | ||
f734dfff | 16034 | iounmap(hw->hw_addr); |
41c445ff | 16035 | kfree(pf); |
56d766d6 | 16036 | pci_release_mem_regions(pdev); |
41c445ff JB |
16037 | |
16038 | pci_disable_pcie_error_reporting(pdev); | |
16039 | pci_disable_device(pdev); | |
16040 | } | |
16041 | ||
16042 | /** | |
16043 | * i40e_pci_error_detected - warning that something funky happened in PCI land | |
16044 | * @pdev: PCI device information struct | |
f5254429 | 16045 | * @error: the type of PCI error |
41c445ff JB |
16046 | * |
16047 | * Called to warn that something happened and the error handling steps | |
16048 | * are in progress. Allows the driver to quiesce things, be ready for | |
16049 | * remediation. | |
16050 | **/ | |
16051 | static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev, | |
16d79cd4 | 16052 | pci_channel_state_t error) |
41c445ff JB |
16053 | { |
16054 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
16055 | ||
16056 | dev_info(&pdev->dev, "%s: error %d\n", __func__, error); | |
16057 | ||
edfc23ee GP |
16058 | if (!pf) { |
16059 | dev_info(&pdev->dev, | |
16060 | "Cannot recover - error happened during device probe\n"); | |
16061 | return PCI_ERS_RESULT_DISCONNECT; | |
16062 | } | |
16063 | ||
41c445ff | 16064 | /* shutdown all operations */ |
dfc4ff64 | 16065 | if (!test_bit(__I40E_SUSPENDED, pf->state)) |
4b208eaa | 16066 | i40e_prep_for_reset(pf); |
41c445ff JB |
16067 | |
16068 | /* Request a slot reset */ | |
16069 | return PCI_ERS_RESULT_NEED_RESET; | |
16070 | } | |
16071 | ||
16072 | /** | |
16073 | * i40e_pci_error_slot_reset - a PCI slot reset just happened | |
16074 | * @pdev: PCI device information struct | |
16075 | * | |
16076 | * Called to find if the driver can work with the device now that | |
16077 | * the pci slot has been reset. If a basic connection seems good | |
16078 | * (registers are readable and have sane content) then return a | |
16079 | * happy little PCI_ERS_RESULT_xxx. | |
16080 | **/ | |
16081 | static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev) | |
16082 | { | |
16083 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
16084 | pci_ers_result_t result; | |
41c445ff JB |
16085 | u32 reg; |
16086 | ||
fb43201f | 16087 | dev_dbg(&pdev->dev, "%s\n", __func__); |
41c445ff JB |
16088 | if (pci_enable_device_mem(pdev)) { |
16089 | dev_info(&pdev->dev, | |
16090 | "Cannot re-enable PCI device after reset.\n"); | |
16091 | result = PCI_ERS_RESULT_DISCONNECT; | |
16092 | } else { | |
16093 | pci_set_master(pdev); | |
16094 | pci_restore_state(pdev); | |
16095 | pci_save_state(pdev); | |
16096 | pci_wake_from_d3(pdev, false); | |
16097 | ||
16098 | reg = rd32(&pf->hw, I40E_GLGEN_RTRIG); | |
16099 | if (reg == 0) | |
16100 | result = PCI_ERS_RESULT_RECOVERED; | |
16101 | else | |
16102 | result = PCI_ERS_RESULT_DISCONNECT; | |
16103 | } | |
16104 | ||
41c445ff JB |
16105 | return result; |
16106 | } | |
16107 | ||
19b7960b AB |
16108 | /** |
16109 | * i40e_pci_error_reset_prepare - prepare device driver for pci reset | |
16110 | * @pdev: PCI device information struct | |
16111 | */ | |
16112 | static void i40e_pci_error_reset_prepare(struct pci_dev *pdev) | |
16113 | { | |
16114 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
16115 | ||
4b208eaa | 16116 | i40e_prep_for_reset(pf); |
19b7960b AB |
16117 | } |
16118 | ||
16119 | /** | |
16120 | * i40e_pci_error_reset_done - pci reset done, device driver reset can begin | |
16121 | * @pdev: PCI device information struct | |
16122 | */ | |
16123 | static void i40e_pci_error_reset_done(struct pci_dev *pdev) | |
16124 | { | |
16125 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
16126 | ||
16127 | i40e_reset_and_rebuild(pf, false, false); | |
16128 | } | |
16129 | ||
41c445ff JB |
16130 | /** |
16131 | * i40e_pci_error_resume - restart operations after PCI error recovery | |
16132 | * @pdev: PCI device information struct | |
16133 | * | |
16134 | * Called to allow the driver to bring things back up after PCI error | |
16135 | * and/or reset recovery has finished. | |
16136 | **/ | |
16137 | static void i40e_pci_error_resume(struct pci_dev *pdev) | |
16138 | { | |
16139 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
16140 | ||
fb43201f | 16141 | dev_dbg(&pdev->dev, "%s\n", __func__); |
0da36b97 | 16142 | if (test_bit(__I40E_SUSPENDED, pf->state)) |
9007bccd SN |
16143 | return; |
16144 | ||
dfc4ff64 | 16145 | i40e_handle_reset_warning(pf, false); |
9007bccd SN |
16146 | } |
16147 | ||
1d68005d JH |
16148 | /** |
16149 | * i40e_enable_mc_magic_wake - enable multicast magic packet wake up | |
16150 | * using the mac_address_write admin q function | |
16151 | * @pf: pointer to i40e_pf struct | |
16152 | **/ | |
16153 | static void i40e_enable_mc_magic_wake(struct i40e_pf *pf) | |
16154 | { | |
16155 | struct i40e_hw *hw = &pf->hw; | |
16156 | i40e_status ret; | |
16157 | u8 mac_addr[6]; | |
16158 | u16 flags = 0; | |
16159 | ||
16160 | /* Get current MAC address in case it's an LAA */ | |
16161 | if (pf->vsi[pf->lan_vsi] && pf->vsi[pf->lan_vsi]->netdev) { | |
16162 | ether_addr_copy(mac_addr, | |
16163 | pf->vsi[pf->lan_vsi]->netdev->dev_addr); | |
16164 | } else { | |
16165 | dev_err(&pf->pdev->dev, | |
16166 | "Failed to retrieve MAC address; using default\n"); | |
16167 | ether_addr_copy(mac_addr, hw->mac.addr); | |
16168 | } | |
16169 | ||
16170 | /* The FW expects the mac address write cmd to first be called with | |
16171 | * one of these flags before calling it again with the multicast | |
16172 | * enable flags. | |
16173 | */ | |
16174 | flags = I40E_AQC_WRITE_TYPE_LAA_WOL; | |
16175 | ||
16176 | if (hw->func_caps.flex10_enable && hw->partition_id != 1) | |
16177 | flags = I40E_AQC_WRITE_TYPE_LAA_ONLY; | |
16178 | ||
16179 | ret = i40e_aq_mac_address_write(hw, flags, mac_addr, NULL); | |
16180 | if (ret) { | |
16181 | dev_err(&pf->pdev->dev, | |
16182 | "Failed to update MAC address registers; cannot enable Multicast Magic packet wake up"); | |
16183 | return; | |
16184 | } | |
16185 | ||
16186 | flags = I40E_AQC_MC_MAG_EN | |
16187 | | I40E_AQC_WOL_PRESERVE_ON_PFR | |
16188 | | I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG; | |
16189 | ret = i40e_aq_mac_address_write(hw, flags, mac_addr, NULL); | |
16190 | if (ret) | |
16191 | dev_err(&pf->pdev->dev, | |
16192 | "Failed to enable Multicast Magic Packet wake up\n"); | |
16193 | } | |
16194 | ||
9007bccd SN |
16195 | /** |
16196 | * i40e_shutdown - PCI callback for shutting down | |
16197 | * @pdev: PCI device information struct | |
16198 | **/ | |
16199 | static void i40e_shutdown(struct pci_dev *pdev) | |
16200 | { | |
16201 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
8e2773ae | 16202 | struct i40e_hw *hw = &pf->hw; |
9007bccd | 16203 | |
0da36b97 | 16204 | set_bit(__I40E_SUSPENDED, pf->state); |
9e6c9c0f | 16205 | set_bit(__I40E_DOWN, pf->state); |
8e2773ae | 16206 | |
02b42498 CS |
16207 | del_timer_sync(&pf->service_timer); |
16208 | cancel_work_sync(&pf->service_task); | |
aaf66502 | 16209 | i40e_cloud_filter_exit(pf); |
02b42498 CS |
16210 | i40e_fdir_teardown(pf); |
16211 | ||
921c467c MW |
16212 | /* Client close must be called explicitly here because the timer |
16213 | * has been stopped. | |
16214 | */ | |
16215 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false); | |
16216 | ||
d36e41dc | 16217 | if (pf->wol_en && (pf->hw_features & I40E_HW_WOL_MC_MAGIC_PKT_WAKE)) |
1d68005d JH |
16218 | i40e_enable_mc_magic_wake(pf); |
16219 | ||
4b208eaa | 16220 | i40e_prep_for_reset(pf); |
02b42498 CS |
16221 | |
16222 | wr32(hw, I40E_PFPM_APM, | |
16223 | (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); | |
16224 | wr32(hw, I40E_PFPM_WUFC, | |
16225 | (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
16226 | ||
4ff0ee1a AM |
16227 | /* Free MSI/legacy interrupt 0 when in recovery mode. */ |
16228 | if (test_bit(__I40E_RECOVERY_MODE, pf->state) && | |
16229 | !(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
16230 | free_irq(pf->pdev->irq, pf); | |
16231 | ||
5cba17b1 PM |
16232 | /* Since we're going to destroy queues during the |
16233 | * i40e_clear_interrupt_scheme() we should hold the RTNL lock for this | |
16234 | * whole section | |
16235 | */ | |
16236 | rtnl_lock(); | |
e147758d | 16237 | i40e_clear_interrupt_scheme(pf); |
5cba17b1 | 16238 | rtnl_unlock(); |
e147758d | 16239 | |
9007bccd | 16240 | if (system_state == SYSTEM_POWER_OFF) { |
8e2773ae | 16241 | pci_wake_from_d3(pdev, pf->wol_en); |
9007bccd SN |
16242 | pci_set_power_state(pdev, PCI_D3hot); |
16243 | } | |
16244 | } | |
16245 | ||
9007bccd | 16246 | /** |
0e5d3da4 JK |
16247 | * i40e_suspend - PM callback for moving to D3 |
16248 | * @dev: generic device information structure | |
9007bccd | 16249 | **/ |
254d152a | 16250 | static int __maybe_unused i40e_suspend(struct device *dev) |
9007bccd | 16251 | { |
1c8aa7b1 | 16252 | struct i40e_pf *pf = dev_get_drvdata(dev); |
8e2773ae | 16253 | struct i40e_hw *hw = &pf->hw; |
9007bccd | 16254 | |
401586c2 JK |
16255 | /* If we're already suspended, then there is nothing to do */ |
16256 | if (test_and_set_bit(__I40E_SUSPENDED, pf->state)) | |
16257 | return 0; | |
16258 | ||
9e6c9c0f | 16259 | set_bit(__I40E_DOWN, pf->state); |
3932dbfe | 16260 | |
5c499228 JK |
16261 | /* Ensure service task will not be running */ |
16262 | del_timer_sync(&pf->service_timer); | |
16263 | cancel_work_sync(&pf->service_task); | |
16264 | ||
ddbb8d5d SS |
16265 | /* Client close must be called explicitly here because the timer |
16266 | * has been stopped. | |
16267 | */ | |
16268 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false); | |
16269 | ||
d36e41dc | 16270 | if (pf->wol_en && (pf->hw_features & I40E_HW_WOL_MC_MAGIC_PKT_WAKE)) |
1d68005d JH |
16271 | i40e_enable_mc_magic_wake(pf); |
16272 | ||
f0ee70a0 JK |
16273 | /* Since we're going to destroy queues during the |
16274 | * i40e_clear_interrupt_scheme() we should hold the RTNL lock for this | |
16275 | * whole section | |
16276 | */ | |
16277 | rtnl_lock(); | |
16278 | ||
4b208eaa | 16279 | i40e_prep_for_reset(pf); |
9007bccd | 16280 | |
8e2773ae SN |
16281 | wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); |
16282 | wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
16283 | ||
b980c063 JK |
16284 | /* Clear the interrupt scheme and release our IRQs so that the system |
16285 | * can safely hibernate even when there are a large number of CPUs. | |
16286 | * Otherwise hibernation might fail when mapping all the vectors back | |
16287 | * to CPU0. | |
16288 | */ | |
16289 | i40e_clear_interrupt_scheme(pf); | |
9007bccd | 16290 | |
f0ee70a0 JK |
16291 | rtnl_unlock(); |
16292 | ||
0e5d3da4 | 16293 | return 0; |
41c445ff JB |
16294 | } |
16295 | ||
9007bccd | 16296 | /** |
0e5d3da4 JK |
16297 | * i40e_resume - PM callback for waking up from D3 |
16298 | * @dev: generic device information structure | |
9007bccd | 16299 | **/ |
254d152a | 16300 | static int __maybe_unused i40e_resume(struct device *dev) |
9007bccd | 16301 | { |
1c8aa7b1 | 16302 | struct i40e_pf *pf = dev_get_drvdata(dev); |
b980c063 | 16303 | int err; |
9007bccd | 16304 | |
401586c2 JK |
16305 | /* If we're not suspended, then there is nothing to do */ |
16306 | if (!test_bit(__I40E_SUSPENDED, pf->state)) | |
16307 | return 0; | |
9007bccd | 16308 | |
f0ee70a0 JK |
16309 | /* We need to hold the RTNL lock prior to restoring interrupt schemes, |
16310 | * since we're going to be restoring queues | |
16311 | */ | |
16312 | rtnl_lock(); | |
16313 | ||
b980c063 JK |
16314 | /* We cleared the interrupt scheme when we suspended, so we need to |
16315 | * restore it now to resume device functionality. | |
16316 | */ | |
16317 | err = i40e_restore_interrupt_scheme(pf); | |
9007bccd | 16318 | if (err) { |
1c8aa7b1 | 16319 | dev_err(dev, "Cannot restore interrupt scheme: %d\n", |
b980c063 | 16320 | err); |
9007bccd | 16321 | } |
9007bccd | 16322 | |
401586c2 | 16323 | clear_bit(__I40E_DOWN, pf->state); |
f0ee70a0 JK |
16324 | i40e_reset_and_rebuild(pf, false, true); |
16325 | ||
16326 | rtnl_unlock(); | |
401586c2 JK |
16327 | |
16328 | /* Clear suspended state last after everything is recovered */ | |
16329 | clear_bit(__I40E_SUSPENDED, pf->state); | |
9007bccd | 16330 | |
5c499228 JK |
16331 | /* Restart the service task */ |
16332 | mod_timer(&pf->service_timer, | |
16333 | round_jiffies(jiffies + pf->service_timer_period)); | |
9007bccd SN |
16334 | |
16335 | return 0; | |
16336 | } | |
16337 | ||
41c445ff JB |
16338 | static const struct pci_error_handlers i40e_err_handler = { |
16339 | .error_detected = i40e_pci_error_detected, | |
16340 | .slot_reset = i40e_pci_error_slot_reset, | |
19b7960b AB |
16341 | .reset_prepare = i40e_pci_error_reset_prepare, |
16342 | .reset_done = i40e_pci_error_reset_done, | |
41c445ff JB |
16343 | .resume = i40e_pci_error_resume, |
16344 | }; | |
16345 | ||
0e5d3da4 JK |
16346 | static SIMPLE_DEV_PM_OPS(i40e_pm_ops, i40e_suspend, i40e_resume); |
16347 | ||
41c445ff JB |
16348 | static struct pci_driver i40e_driver = { |
16349 | .name = i40e_driver_name, | |
16350 | .id_table = i40e_pci_tbl, | |
16351 | .probe = i40e_probe, | |
16352 | .remove = i40e_remove, | |
0e5d3da4 JK |
16353 | .driver = { |
16354 | .pm = &i40e_pm_ops, | |
16355 | }, | |
9007bccd | 16356 | .shutdown = i40e_shutdown, |
41c445ff JB |
16357 | .err_handler = &i40e_err_handler, |
16358 | .sriov_configure = i40e_pci_sriov_configure, | |
16359 | }; | |
16360 | ||
16361 | /** | |
16362 | * i40e_init_module - Driver registration routine | |
16363 | * | |
16364 | * i40e_init_module is the first routine called when the driver is | |
16365 | * loaded. All it does is register with the PCI subsystem. | |
16366 | **/ | |
16367 | static int __init i40e_init_module(void) | |
16368 | { | |
34a2a3b8 | 16369 | pr_info("%s: %s\n", i40e_driver_name, i40e_driver_string); |
41c445ff | 16370 | pr_info("%s: %s\n", i40e_driver_name, i40e_copyright); |
96664483 | 16371 | |
4d5957cb JK |
16372 | /* There is no need to throttle the number of active tasks because |
16373 | * each device limits its own task using a state bit for scheduling | |
16374 | * the service task, and the device tasks do not interfere with each | |
16375 | * other, so we don't set a max task limit. We must set WQ_MEM_RECLAIM | |
16376 | * since we need to be able to guarantee forward progress even under | |
16377 | * memory pressure. | |
2803b16c | 16378 | */ |
4d5957cb | 16379 | i40e_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, i40e_driver_name); |
2803b16c JB |
16380 | if (!i40e_wq) { |
16381 | pr_err("%s: Failed to create workqueue\n", i40e_driver_name); | |
16382 | return -ENOMEM; | |
16383 | } | |
16384 | ||
41c445ff JB |
16385 | i40e_dbg_init(); |
16386 | return pci_register_driver(&i40e_driver); | |
16387 | } | |
16388 | module_init(i40e_init_module); | |
16389 | ||
16390 | /** | |
16391 | * i40e_exit_module - Driver exit cleanup routine | |
16392 | * | |
16393 | * i40e_exit_module is called just before the driver is removed | |
16394 | * from memory. | |
16395 | **/ | |
16396 | static void __exit i40e_exit_module(void) | |
16397 | { | |
16398 | pci_unregister_driver(&i40e_driver); | |
2803b16c | 16399 | destroy_workqueue(i40e_wq); |
f4370a85 | 16400 | ida_destroy(&i40e_client_ida); |
41c445ff JB |
16401 | i40e_dbg_exit(); |
16402 | } | |
16403 | module_exit(i40e_exit_module); |