Commit | Line | Data |
---|---|---|
ae06c70b | 1 | // SPDX-License-Identifier: GPL-2.0 |
51dce24b | 2 | /* Copyright(c) 2013 - 2018 Intel Corporation. */ |
41c445ff | 3 | |
b499ffb0 SV |
4 | #include <linux/etherdevice.h> |
5 | #include <linux/of_net.h> | |
6 | #include <linux/pci.h> | |
0c8493d9 | 7 | #include <linux/bpf.h> |
b499ffb0 | 8 | |
41c445ff JB |
9 | /* Local includes */ |
10 | #include "i40e.h" | |
4eb3f768 | 11 | #include "i40e_diag.h" |
0a714186 | 12 | #include "i40e_xsk.h" |
06a5f7f1 | 13 | #include <net/udp_tunnel.h> |
0a714186 | 14 | #include <net/xdp_sock.h> |
ed0980c4 SP |
15 | /* All i40e tracepoints are defined by the include below, which |
16 | * must be included exactly once across the whole kernel with | |
17 | * CREATE_TRACE_POINTS defined | |
18 | */ | |
19 | #define CREATE_TRACE_POINTS | |
20 | #include "i40e_trace.h" | |
41c445ff JB |
21 | |
22 | const char i40e_driver_name[] = "i40e"; | |
23 | static const char i40e_driver_string[] = | |
24 | "Intel(R) Ethernet Connection XL710 Network Driver"; | |
25 | ||
26 | #define DRV_KERN "-k" | |
27 | ||
15990832 | 28 | #define DRV_VERSION_MAJOR 2 |
9f250f15 | 29 | #define DRV_VERSION_MINOR 8 |
d1fc90a9 | 30 | #define DRV_VERSION_BUILD 20 |
41c445ff JB |
31 | #define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \ |
32 | __stringify(DRV_VERSION_MINOR) "." \ | |
33 | __stringify(DRV_VERSION_BUILD) DRV_KERN | |
34 | const char i40e_driver_version_str[] = DRV_VERSION; | |
8fb905b3 | 35 | static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation."; |
41c445ff JB |
36 | |
37 | /* a bit of forward declarations */ | |
38 | static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi); | |
373149fc | 39 | static void i40e_handle_reset_warning(struct i40e_pf *pf, bool lock_acquired); |
41c445ff JB |
40 | static int i40e_add_vsi(struct i40e_vsi *vsi); |
41 | static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi); | |
bc7d338f | 42 | static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit); |
41c445ff JB |
43 | static int i40e_setup_misc_vector(struct i40e_pf *pf); |
44 | static void i40e_determine_queue_usage(struct i40e_pf *pf); | |
45 | static int i40e_setup_pf_filter_control(struct i40e_pf *pf); | |
373149fc MS |
46 | static void i40e_prep_for_reset(struct i40e_pf *pf, bool lock_acquired); |
47 | static int i40e_reset(struct i40e_pf *pf); | |
48 | static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired); | |
4ff0ee1a AM |
49 | static int i40e_setup_misc_vector_for_recovery_mode(struct i40e_pf *pf); |
50 | static int i40e_restore_interrupt_scheme(struct i40e_pf *pf); | |
51 | static bool i40e_check_recovery_mode(struct i40e_pf *pf); | |
52 | static int i40e_init_recovery_mode(struct i40e_pf *pf, struct i40e_hw *hw); | |
cbf61325 | 53 | static void i40e_fdir_sb_setup(struct i40e_pf *pf); |
4e3b35b0 | 54 | static int i40e_veb_get_bw_info(struct i40e_veb *veb); |
2f4b411a AN |
55 | static int i40e_get_capabilities(struct i40e_pf *pf, |
56 | enum i40e_admin_queue_opc list_type); | |
57 | ||
41c445ff JB |
58 | |
59 | /* i40e_pci_tbl - PCI Device ID Table | |
60 | * | |
61 | * Last entry must be all 0s | |
62 | * | |
63 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
64 | * Class, Class Mask, private data (not used) } | |
65 | */ | |
9baa3c34 | 66 | static const struct pci_device_id i40e_pci_tbl[] = { |
ab60085e | 67 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0}, |
ab60085e | 68 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0}, |
ab60085e SN |
69 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0}, |
70 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0}, | |
ab60085e SN |
71 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0}, |
72 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0}, | |
73 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0}, | |
5960d33f | 74 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0}, |
bc5166b9 | 75 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0}, |
35dae51d ASJ |
76 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0}, |
77 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0}, | |
87e6c1d7 ASJ |
78 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0}, |
79 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0}, | |
80 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0}, | |
d6bf58c2 | 81 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0}, |
48a3b512 SN |
82 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0}, |
83 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0}, | |
3123237a CW |
84 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_B), 0}, |
85 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_SFP28), 0}, | |
41c445ff JB |
86 | /* required last entry */ |
87 | {0, } | |
88 | }; | |
89 | MODULE_DEVICE_TABLE(pci, i40e_pci_tbl); | |
90 | ||
91 | #define I40E_MAX_VF_COUNT 128 | |
92 | static int debug = -1; | |
5d4ca23e AD |
93 | module_param(debug, uint, 0); |
94 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all), Debug mask (0x8XXXXXXX)"); | |
41c445ff JB |
95 | |
96 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
97 | MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver"); | |
98674ebe | 98 | MODULE_LICENSE("GPL v2"); |
41c445ff JB |
99 | MODULE_VERSION(DRV_VERSION); |
100 | ||
2803b16c JB |
101 | static struct workqueue_struct *i40e_wq; |
102 | ||
41c445ff JB |
103 | /** |
104 | * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code | |
105 | * @hw: pointer to the HW structure | |
106 | * @mem: ptr to mem struct to fill out | |
107 | * @size: size of memory requested | |
108 | * @alignment: what to align the allocation to | |
109 | **/ | |
110 | int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem, | |
111 | u64 size, u32 alignment) | |
112 | { | |
113 | struct i40e_pf *pf = (struct i40e_pf *)hw->back; | |
114 | ||
115 | mem->size = ALIGN(size, alignment); | |
750afb08 LC |
116 | mem->va = dma_alloc_coherent(&pf->pdev->dev, mem->size, &mem->pa, |
117 | GFP_KERNEL); | |
93bc73b8 JB |
118 | if (!mem->va) |
119 | return -ENOMEM; | |
41c445ff | 120 | |
93bc73b8 | 121 | return 0; |
41c445ff JB |
122 | } |
123 | ||
124 | /** | |
125 | * i40e_free_dma_mem_d - OS specific memory free for shared code | |
126 | * @hw: pointer to the HW structure | |
127 | * @mem: ptr to mem struct to free | |
128 | **/ | |
129 | int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem) | |
130 | { | |
131 | struct i40e_pf *pf = (struct i40e_pf *)hw->back; | |
132 | ||
133 | dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa); | |
134 | mem->va = NULL; | |
135 | mem->pa = 0; | |
136 | mem->size = 0; | |
137 | ||
138 | return 0; | |
139 | } | |
140 | ||
141 | /** | |
142 | * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code | |
143 | * @hw: pointer to the HW structure | |
144 | * @mem: ptr to mem struct to fill out | |
145 | * @size: size of memory requested | |
146 | **/ | |
147 | int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem, | |
148 | u32 size) | |
149 | { | |
150 | mem->size = size; | |
151 | mem->va = kzalloc(size, GFP_KERNEL); | |
152 | ||
93bc73b8 JB |
153 | if (!mem->va) |
154 | return -ENOMEM; | |
41c445ff | 155 | |
93bc73b8 | 156 | return 0; |
41c445ff JB |
157 | } |
158 | ||
159 | /** | |
160 | * i40e_free_virt_mem_d - OS specific memory free for shared code | |
161 | * @hw: pointer to the HW structure | |
162 | * @mem: ptr to mem struct to free | |
163 | **/ | |
164 | int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem) | |
165 | { | |
166 | /* it's ok to kfree a NULL pointer */ | |
167 | kfree(mem->va); | |
168 | mem->va = NULL; | |
169 | mem->size = 0; | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
174 | /** | |
175 | * i40e_get_lump - find a lump of free generic resource | |
176 | * @pf: board private structure | |
177 | * @pile: the pile of resource to search | |
178 | * @needed: the number of items needed | |
179 | * @id: an owner id to stick on the items assigned | |
180 | * | |
181 | * Returns the base item index of the lump, or negative for error | |
182 | * | |
183 | * The search_hint trick and lack of advanced fit-finding only work | |
184 | * because we're highly likely to have all the same size lump requests. | |
185 | * Linear search time and any fragmentation should be minimal. | |
186 | **/ | |
187 | static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile, | |
188 | u16 needed, u16 id) | |
189 | { | |
190 | int ret = -ENOMEM; | |
ddf434ac | 191 | int i, j; |
41c445ff JB |
192 | |
193 | if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) { | |
194 | dev_info(&pf->pdev->dev, | |
7be78aa4 MW |
195 | "param err: pile=%s needed=%d id=0x%04x\n", |
196 | pile ? "<valid>" : "<null>", needed, id); | |
41c445ff JB |
197 | return -EINVAL; |
198 | } | |
199 | ||
200 | /* start the linear search with an imperfect hint */ | |
201 | i = pile->search_hint; | |
ddf434ac | 202 | while (i < pile->num_entries) { |
41c445ff JB |
203 | /* skip already allocated entries */ |
204 | if (pile->list[i] & I40E_PILE_VALID_BIT) { | |
205 | i++; | |
206 | continue; | |
207 | } | |
208 | ||
209 | /* do we have enough in this lump? */ | |
210 | for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) { | |
211 | if (pile->list[i+j] & I40E_PILE_VALID_BIT) | |
212 | break; | |
213 | } | |
214 | ||
215 | if (j == needed) { | |
216 | /* there was enough, so assign it to the requestor */ | |
217 | for (j = 0; j < needed; j++) | |
218 | pile->list[i+j] = id | I40E_PILE_VALID_BIT; | |
219 | ret = i; | |
220 | pile->search_hint = i + j; | |
ddf434ac | 221 | break; |
41c445ff | 222 | } |
6995b36c JB |
223 | |
224 | /* not enough, so skip over it and continue looking */ | |
225 | i += j; | |
41c445ff JB |
226 | } |
227 | ||
228 | return ret; | |
229 | } | |
230 | ||
231 | /** | |
232 | * i40e_put_lump - return a lump of generic resource | |
233 | * @pile: the pile of resource to search | |
234 | * @index: the base item index | |
235 | * @id: the owner id of the items assigned | |
236 | * | |
237 | * Returns the count of items in the lump | |
238 | **/ | |
239 | static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id) | |
240 | { | |
241 | int valid_id = (id | I40E_PILE_VALID_BIT); | |
242 | int count = 0; | |
243 | int i; | |
244 | ||
245 | if (!pile || index >= pile->num_entries) | |
246 | return -EINVAL; | |
247 | ||
248 | for (i = index; | |
249 | i < pile->num_entries && pile->list[i] == valid_id; | |
250 | i++) { | |
251 | pile->list[i] = 0; | |
252 | count++; | |
253 | } | |
254 | ||
255 | if (count && index < pile->search_hint) | |
256 | pile->search_hint = index; | |
257 | ||
258 | return count; | |
259 | } | |
260 | ||
fdf0e0bf ASJ |
261 | /** |
262 | * i40e_find_vsi_from_id - searches for the vsi with the given id | |
f5254429 JK |
263 | * @pf: the pf structure to search for the vsi |
264 | * @id: id of the vsi it is searching for | |
fdf0e0bf ASJ |
265 | **/ |
266 | struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id) | |
267 | { | |
268 | int i; | |
269 | ||
270 | for (i = 0; i < pf->num_alloc_vsi; i++) | |
271 | if (pf->vsi[i] && (pf->vsi[i]->id == id)) | |
272 | return pf->vsi[i]; | |
273 | ||
274 | return NULL; | |
275 | } | |
276 | ||
41c445ff JB |
277 | /** |
278 | * i40e_service_event_schedule - Schedule the service task to wake up | |
279 | * @pf: board private structure | |
280 | * | |
281 | * If not already scheduled, this puts the task into the work queue | |
282 | **/ | |
e3219ce6 | 283 | void i40e_service_event_schedule(struct i40e_pf *pf) |
41c445ff | 284 | { |
4ff0ee1a AM |
285 | if ((!test_bit(__I40E_DOWN, pf->state) && |
286 | !test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) || | |
287 | test_bit(__I40E_RECOVERY_MODE, pf->state)) | |
2803b16c | 288 | queue_work(i40e_wq, &pf->service_task); |
41c445ff JB |
289 | } |
290 | ||
291 | /** | |
292 | * i40e_tx_timeout - Respond to a Tx Hang | |
293 | * @netdev: network interface device structure | |
294 | * | |
295 | * If any port has noticed a Tx timeout, it is likely that the whole | |
296 | * device is munged, not just the one netdev port, so go for the full | |
297 | * reset. | |
298 | **/ | |
299 | static void i40e_tx_timeout(struct net_device *netdev) | |
300 | { | |
301 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
302 | struct i40e_vsi *vsi = np->vsi; | |
303 | struct i40e_pf *pf = vsi->back; | |
b03a8c1f KP |
304 | struct i40e_ring *tx_ring = NULL; |
305 | unsigned int i, hung_queue = 0; | |
306 | u32 head, val; | |
41c445ff JB |
307 | |
308 | pf->tx_timeout_count++; | |
309 | ||
b03a8c1f KP |
310 | /* find the stopped queue the same way the stack does */ |
311 | for (i = 0; i < netdev->num_tx_queues; i++) { | |
312 | struct netdev_queue *q; | |
313 | unsigned long trans_start; | |
314 | ||
315 | q = netdev_get_tx_queue(netdev, i); | |
9b36627a | 316 | trans_start = q->trans_start; |
b03a8c1f KP |
317 | if (netif_xmit_stopped(q) && |
318 | time_after(jiffies, | |
319 | (trans_start + netdev->watchdog_timeo))) { | |
320 | hung_queue = i; | |
321 | break; | |
322 | } | |
323 | } | |
324 | ||
325 | if (i == netdev->num_tx_queues) { | |
326 | netdev_info(netdev, "tx_timeout: no netdev hung queue found\n"); | |
327 | } else { | |
328 | /* now that we have an index, find the tx_ring struct */ | |
329 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
330 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) { | |
331 | if (hung_queue == | |
332 | vsi->tx_rings[i]->queue_index) { | |
333 | tx_ring = vsi->tx_rings[i]; | |
334 | break; | |
335 | } | |
336 | } | |
337 | } | |
338 | } | |
339 | ||
41c445ff | 340 | if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20))) |
b03a8c1f KP |
341 | pf->tx_timeout_recovery_level = 1; /* reset after some time */ |
342 | else if (time_before(jiffies, | |
343 | (pf->tx_timeout_last_recovery + netdev->watchdog_timeo))) | |
344 | return; /* don't do any new action before the next timeout */ | |
345 | ||
d5585b7b AB |
346 | /* don't kick off another recovery if one is already pending */ |
347 | if (test_and_set_bit(__I40E_TIMEOUT_RECOVERY_PENDING, pf->state)) | |
348 | return; | |
349 | ||
b03a8c1f KP |
350 | if (tx_ring) { |
351 | head = i40e_get_head(tx_ring); | |
352 | /* Read interrupt register */ | |
353 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
354 | val = rd32(&pf->hw, | |
355 | I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx + | |
356 | tx_ring->vsi->base_vector - 1)); | |
357 | else | |
358 | val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); | |
359 | ||
360 | netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n", | |
361 | vsi->seid, hung_queue, tx_ring->next_to_clean, | |
362 | head, tx_ring->next_to_use, | |
363 | readl(tx_ring->tail), val); | |
364 | } | |
365 | ||
41c445ff | 366 | pf->tx_timeout_last_recovery = jiffies; |
b03a8c1f KP |
367 | netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n", |
368 | pf->tx_timeout_recovery_level, hung_queue); | |
41c445ff JB |
369 | |
370 | switch (pf->tx_timeout_recovery_level) { | |
41c445ff | 371 | case 1: |
0da36b97 | 372 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
41c445ff JB |
373 | break; |
374 | case 2: | |
0da36b97 | 375 | set_bit(__I40E_CORE_RESET_REQUESTED, pf->state); |
41c445ff JB |
376 | break; |
377 | case 3: | |
0da36b97 | 378 | set_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state); |
41c445ff JB |
379 | break; |
380 | default: | |
381 | netdev_err(netdev, "tx_timeout recovery unsuccessful\n"); | |
41c445ff JB |
382 | break; |
383 | } | |
b03a8c1f | 384 | |
41c445ff JB |
385 | i40e_service_event_schedule(pf); |
386 | pf->tx_timeout_recovery_level++; | |
387 | } | |
388 | ||
41c445ff JB |
389 | /** |
390 | * i40e_get_vsi_stats_struct - Get System Network Statistics | |
391 | * @vsi: the VSI we care about | |
392 | * | |
393 | * Returns the address of the device statistics structure. | |
394 | * The statistics are actually updated from the service task. | |
395 | **/ | |
396 | struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi) | |
397 | { | |
398 | return &vsi->net_stats; | |
399 | } | |
400 | ||
74608d17 BT |
401 | /** |
402 | * i40e_get_netdev_stats_struct_tx - populate stats from a Tx ring | |
403 | * @ring: Tx ring to get statistics from | |
404 | * @stats: statistics entry to be updated | |
405 | **/ | |
406 | static void i40e_get_netdev_stats_struct_tx(struct i40e_ring *ring, | |
407 | struct rtnl_link_stats64 *stats) | |
408 | { | |
409 | u64 bytes, packets; | |
410 | unsigned int start; | |
411 | ||
412 | do { | |
413 | start = u64_stats_fetch_begin_irq(&ring->syncp); | |
414 | packets = ring->stats.packets; | |
415 | bytes = ring->stats.bytes; | |
416 | } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); | |
417 | ||
418 | stats->tx_packets += packets; | |
419 | stats->tx_bytes += bytes; | |
420 | } | |
421 | ||
41c445ff JB |
422 | /** |
423 | * i40e_get_netdev_stats_struct - Get statistics for netdev interface | |
424 | * @netdev: network interface device structure | |
f5254429 | 425 | * @stats: data structure to store statistics |
41c445ff JB |
426 | * |
427 | * Returns the address of the device statistics structure. | |
428 | * The statistics are actually updated from the service task. | |
429 | **/ | |
9eed69a9 | 430 | static void i40e_get_netdev_stats_struct(struct net_device *netdev, |
bc1f4470 | 431 | struct rtnl_link_stats64 *stats) |
41c445ff JB |
432 | { |
433 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
434 | struct i40e_vsi *vsi = np->vsi; | |
980e9b11 | 435 | struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi); |
cdec2141 | 436 | struct i40e_ring *ring; |
980e9b11 AD |
437 | int i; |
438 | ||
0da36b97 | 439 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) |
bc1f4470 | 440 | return; |
bc7d338f | 441 | |
3c325ced | 442 | if (!vsi->tx_rings) |
bc1f4470 | 443 | return; |
3c325ced | 444 | |
980e9b11 AD |
445 | rcu_read_lock(); |
446 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
980e9b11 AD |
447 | u64 bytes, packets; |
448 | unsigned int start; | |
449 | ||
cdec2141 BT |
450 | ring = READ_ONCE(vsi->tx_rings[i]); |
451 | if (!ring) | |
980e9b11 | 452 | continue; |
cdec2141 | 453 | i40e_get_netdev_stats_struct_tx(ring, stats); |
980e9b11 | 454 | |
cdec2141 BT |
455 | if (i40e_enabled_xdp_vsi(vsi)) { |
456 | ring++; | |
457 | i40e_get_netdev_stats_struct_tx(ring, stats); | |
458 | } | |
980e9b11 | 459 | |
cdec2141 | 460 | ring++; |
980e9b11 | 461 | do { |
cdec2141 BT |
462 | start = u64_stats_fetch_begin_irq(&ring->syncp); |
463 | packets = ring->stats.packets; | |
464 | bytes = ring->stats.bytes; | |
465 | } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); | |
41c445ff | 466 | |
980e9b11 AD |
467 | stats->rx_packets += packets; |
468 | stats->rx_bytes += bytes; | |
74608d17 | 469 | |
980e9b11 AD |
470 | } |
471 | rcu_read_unlock(); | |
472 | ||
a5282f44 | 473 | /* following stats updated by i40e_watchdog_subtask() */ |
980e9b11 AD |
474 | stats->multicast = vsi_stats->multicast; |
475 | stats->tx_errors = vsi_stats->tx_errors; | |
476 | stats->tx_dropped = vsi_stats->tx_dropped; | |
477 | stats->rx_errors = vsi_stats->rx_errors; | |
d8201e20 | 478 | stats->rx_dropped = vsi_stats->rx_dropped; |
980e9b11 AD |
479 | stats->rx_crc_errors = vsi_stats->rx_crc_errors; |
480 | stats->rx_length_errors = vsi_stats->rx_length_errors; | |
41c445ff JB |
481 | } |
482 | ||
483 | /** | |
484 | * i40e_vsi_reset_stats - Resets all stats of the given vsi | |
485 | * @vsi: the VSI to have its stats reset | |
486 | **/ | |
487 | void i40e_vsi_reset_stats(struct i40e_vsi *vsi) | |
488 | { | |
489 | struct rtnl_link_stats64 *ns; | |
490 | int i; | |
491 | ||
492 | if (!vsi) | |
493 | return; | |
494 | ||
495 | ns = i40e_get_vsi_stats_struct(vsi); | |
496 | memset(ns, 0, sizeof(*ns)); | |
497 | memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets)); | |
498 | memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats)); | |
499 | memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets)); | |
8e9dca53 | 500 | if (vsi->rx_rings && vsi->rx_rings[0]) { |
41c445ff | 501 | for (i = 0; i < vsi->num_queue_pairs; i++) { |
6995b36c | 502 | memset(&vsi->rx_rings[i]->stats, 0, |
9f65e15b | 503 | sizeof(vsi->rx_rings[i]->stats)); |
6995b36c | 504 | memset(&vsi->rx_rings[i]->rx_stats, 0, |
9f65e15b | 505 | sizeof(vsi->rx_rings[i]->rx_stats)); |
6995b36c | 506 | memset(&vsi->tx_rings[i]->stats, 0, |
9f65e15b AD |
507 | sizeof(vsi->tx_rings[i]->stats)); |
508 | memset(&vsi->tx_rings[i]->tx_stats, 0, | |
509 | sizeof(vsi->tx_rings[i]->tx_stats)); | |
41c445ff | 510 | } |
8e9dca53 | 511 | } |
41c445ff JB |
512 | vsi->stat_offsets_loaded = false; |
513 | } | |
514 | ||
515 | /** | |
b40c82e6 | 516 | * i40e_pf_reset_stats - Reset all of the stats for the given PF |
41c445ff JB |
517 | * @pf: the PF to be reset |
518 | **/ | |
519 | void i40e_pf_reset_stats(struct i40e_pf *pf) | |
520 | { | |
e91fdf76 SN |
521 | int i; |
522 | ||
41c445ff JB |
523 | memset(&pf->stats, 0, sizeof(pf->stats)); |
524 | memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets)); | |
525 | pf->stat_offsets_loaded = false; | |
e91fdf76 SN |
526 | |
527 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
528 | if (pf->veb[i]) { | |
529 | memset(&pf->veb[i]->stats, 0, | |
530 | sizeof(pf->veb[i]->stats)); | |
531 | memset(&pf->veb[i]->stats_offsets, 0, | |
532 | sizeof(pf->veb[i]->stats_offsets)); | |
533 | pf->veb[i]->stat_offsets_loaded = false; | |
534 | } | |
535 | } | |
42bce04e | 536 | pf->hw_csum_rx_error = 0; |
41c445ff JB |
537 | } |
538 | ||
539 | /** | |
540 | * i40e_stat_update48 - read and update a 48 bit stat from the chip | |
541 | * @hw: ptr to the hardware info | |
542 | * @hireg: the high 32 bit reg to read | |
543 | * @loreg: the low 32 bit reg to read | |
544 | * @offset_loaded: has the initial offset been loaded yet | |
545 | * @offset: ptr to current offset value | |
546 | * @stat: ptr to the stat | |
547 | * | |
548 | * Since the device stats are not reset at PFReset, they likely will not | |
549 | * be zeroed when the driver starts. We'll save the first values read | |
550 | * and use them as offsets to be subtracted from the raw values in order | |
551 | * to report stats that count from zero. In the process, we also manage | |
552 | * the potential roll-over. | |
553 | **/ | |
554 | static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg, | |
555 | bool offset_loaded, u64 *offset, u64 *stat) | |
556 | { | |
557 | u64 new_data; | |
558 | ||
ab60085e | 559 | if (hw->device_id == I40E_DEV_ID_QEMU) { |
41c445ff JB |
560 | new_data = rd32(hw, loreg); |
561 | new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; | |
562 | } else { | |
563 | new_data = rd64(hw, loreg); | |
564 | } | |
565 | if (!offset_loaded) | |
566 | *offset = new_data; | |
567 | if (likely(new_data >= *offset)) | |
568 | *stat = new_data - *offset; | |
569 | else | |
41a1d04b | 570 | *stat = (new_data + BIT_ULL(48)) - *offset; |
41c445ff JB |
571 | *stat &= 0xFFFFFFFFFFFFULL; |
572 | } | |
573 | ||
574 | /** | |
575 | * i40e_stat_update32 - read and update a 32 bit stat from the chip | |
576 | * @hw: ptr to the hardware info | |
577 | * @reg: the hw reg to read | |
578 | * @offset_loaded: has the initial offset been loaded yet | |
579 | * @offset: ptr to current offset value | |
580 | * @stat: ptr to the stat | |
581 | **/ | |
582 | static void i40e_stat_update32(struct i40e_hw *hw, u32 reg, | |
583 | bool offset_loaded, u64 *offset, u64 *stat) | |
584 | { | |
585 | u32 new_data; | |
586 | ||
587 | new_data = rd32(hw, reg); | |
588 | if (!offset_loaded) | |
589 | *offset = new_data; | |
590 | if (likely(new_data >= *offset)) | |
591 | *stat = (u32)(new_data - *offset); | |
592 | else | |
41a1d04b | 593 | *stat = (u32)((new_data + BIT_ULL(32)) - *offset); |
41c445ff JB |
594 | } |
595 | ||
0dc8692e MS |
596 | /** |
597 | * i40e_stat_update_and_clear32 - read and clear hw reg, update a 32 bit stat | |
598 | * @hw: ptr to the hardware info | |
599 | * @reg: the hw reg to read and clear | |
600 | * @stat: ptr to the stat | |
601 | **/ | |
602 | static void i40e_stat_update_and_clear32(struct i40e_hw *hw, u32 reg, u64 *stat) | |
603 | { | |
604 | u32 new_data = rd32(hw, reg); | |
605 | ||
606 | wr32(hw, reg, 1); /* must write a nonzero value to clear register */ | |
607 | *stat += new_data; | |
608 | } | |
609 | ||
41c445ff JB |
610 | /** |
611 | * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters. | |
612 | * @vsi: the VSI to be updated | |
613 | **/ | |
614 | void i40e_update_eth_stats(struct i40e_vsi *vsi) | |
615 | { | |
616 | int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx); | |
617 | struct i40e_pf *pf = vsi->back; | |
618 | struct i40e_hw *hw = &pf->hw; | |
619 | struct i40e_eth_stats *oes; | |
620 | struct i40e_eth_stats *es; /* device's eth stats */ | |
621 | ||
622 | es = &vsi->eth_stats; | |
623 | oes = &vsi->eth_stats_offsets; | |
624 | ||
625 | /* Gather up the stats that the hw collects */ | |
626 | i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), | |
627 | vsi->stat_offsets_loaded, | |
628 | &oes->tx_errors, &es->tx_errors); | |
629 | i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), | |
630 | vsi->stat_offsets_loaded, | |
631 | &oes->rx_discards, &es->rx_discards); | |
41a9e55c SN |
632 | i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx), |
633 | vsi->stat_offsets_loaded, | |
634 | &oes->rx_unknown_protocol, &es->rx_unknown_protocol); | |
635 | i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), | |
636 | vsi->stat_offsets_loaded, | |
637 | &oes->tx_errors, &es->tx_errors); | |
41c445ff JB |
638 | |
639 | i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx), | |
640 | I40E_GLV_GORCL(stat_idx), | |
641 | vsi->stat_offsets_loaded, | |
642 | &oes->rx_bytes, &es->rx_bytes); | |
643 | i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx), | |
644 | I40E_GLV_UPRCL(stat_idx), | |
645 | vsi->stat_offsets_loaded, | |
646 | &oes->rx_unicast, &es->rx_unicast); | |
647 | i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx), | |
648 | I40E_GLV_MPRCL(stat_idx), | |
649 | vsi->stat_offsets_loaded, | |
650 | &oes->rx_multicast, &es->rx_multicast); | |
651 | i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx), | |
652 | I40E_GLV_BPRCL(stat_idx), | |
653 | vsi->stat_offsets_loaded, | |
654 | &oes->rx_broadcast, &es->rx_broadcast); | |
655 | ||
656 | i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx), | |
657 | I40E_GLV_GOTCL(stat_idx), | |
658 | vsi->stat_offsets_loaded, | |
659 | &oes->tx_bytes, &es->tx_bytes); | |
660 | i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx), | |
661 | I40E_GLV_UPTCL(stat_idx), | |
662 | vsi->stat_offsets_loaded, | |
663 | &oes->tx_unicast, &es->tx_unicast); | |
664 | i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx), | |
665 | I40E_GLV_MPTCL(stat_idx), | |
666 | vsi->stat_offsets_loaded, | |
667 | &oes->tx_multicast, &es->tx_multicast); | |
668 | i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx), | |
669 | I40E_GLV_BPTCL(stat_idx), | |
670 | vsi->stat_offsets_loaded, | |
671 | &oes->tx_broadcast, &es->tx_broadcast); | |
672 | vsi->stat_offsets_loaded = true; | |
673 | } | |
674 | ||
675 | /** | |
676 | * i40e_update_veb_stats - Update Switch component statistics | |
677 | * @veb: the VEB being updated | |
678 | **/ | |
679 | static void i40e_update_veb_stats(struct i40e_veb *veb) | |
680 | { | |
681 | struct i40e_pf *pf = veb->pf; | |
682 | struct i40e_hw *hw = &pf->hw; | |
683 | struct i40e_eth_stats *oes; | |
684 | struct i40e_eth_stats *es; /* device's eth stats */ | |
fe860afb NP |
685 | struct i40e_veb_tc_stats *veb_oes; |
686 | struct i40e_veb_tc_stats *veb_es; | |
687 | int i, idx = 0; | |
41c445ff JB |
688 | |
689 | idx = veb->stats_idx; | |
690 | es = &veb->stats; | |
691 | oes = &veb->stats_offsets; | |
fe860afb NP |
692 | veb_es = &veb->tc_stats; |
693 | veb_oes = &veb->tc_stats_offsets; | |
41c445ff JB |
694 | |
695 | /* Gather up the stats that the hw collects */ | |
696 | i40e_stat_update32(hw, I40E_GLSW_TDPC(idx), | |
697 | veb->stat_offsets_loaded, | |
698 | &oes->tx_discards, &es->tx_discards); | |
7134f9ce JB |
699 | if (hw->revision_id > 0) |
700 | i40e_stat_update32(hw, I40E_GLSW_RUPP(idx), | |
701 | veb->stat_offsets_loaded, | |
702 | &oes->rx_unknown_protocol, | |
703 | &es->rx_unknown_protocol); | |
41c445ff JB |
704 | i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx), |
705 | veb->stat_offsets_loaded, | |
706 | &oes->rx_bytes, &es->rx_bytes); | |
707 | i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx), | |
708 | veb->stat_offsets_loaded, | |
709 | &oes->rx_unicast, &es->rx_unicast); | |
710 | i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx), | |
711 | veb->stat_offsets_loaded, | |
712 | &oes->rx_multicast, &es->rx_multicast); | |
713 | i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx), | |
714 | veb->stat_offsets_loaded, | |
715 | &oes->rx_broadcast, &es->rx_broadcast); | |
716 | ||
717 | i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx), | |
718 | veb->stat_offsets_loaded, | |
719 | &oes->tx_bytes, &es->tx_bytes); | |
720 | i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx), | |
721 | veb->stat_offsets_loaded, | |
722 | &oes->tx_unicast, &es->tx_unicast); | |
723 | i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx), | |
724 | veb->stat_offsets_loaded, | |
725 | &oes->tx_multicast, &es->tx_multicast); | |
726 | i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx), | |
727 | veb->stat_offsets_loaded, | |
728 | &oes->tx_broadcast, &es->tx_broadcast); | |
fe860afb NP |
729 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
730 | i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx), | |
731 | I40E_GLVEBTC_RPCL(i, idx), | |
732 | veb->stat_offsets_loaded, | |
733 | &veb_oes->tc_rx_packets[i], | |
734 | &veb_es->tc_rx_packets[i]); | |
735 | i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx), | |
736 | I40E_GLVEBTC_RBCL(i, idx), | |
737 | veb->stat_offsets_loaded, | |
738 | &veb_oes->tc_rx_bytes[i], | |
739 | &veb_es->tc_rx_bytes[i]); | |
740 | i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx), | |
741 | I40E_GLVEBTC_TPCL(i, idx), | |
742 | veb->stat_offsets_loaded, | |
743 | &veb_oes->tc_tx_packets[i], | |
744 | &veb_es->tc_tx_packets[i]); | |
745 | i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx), | |
746 | I40E_GLVEBTC_TBCL(i, idx), | |
747 | veb->stat_offsets_loaded, | |
748 | &veb_oes->tc_tx_bytes[i], | |
749 | &veb_es->tc_tx_bytes[i]); | |
750 | } | |
41c445ff JB |
751 | veb->stat_offsets_loaded = true; |
752 | } | |
753 | ||
41c445ff | 754 | /** |
7812fddc | 755 | * i40e_update_vsi_stats - Update the vsi statistics counters. |
41c445ff JB |
756 | * @vsi: the VSI to be updated |
757 | * | |
758 | * There are a few instances where we store the same stat in a | |
759 | * couple of different structs. This is partly because we have | |
760 | * the netdev stats that need to be filled out, which is slightly | |
761 | * different from the "eth_stats" defined by the chip and used in | |
7812fddc | 762 | * VF communications. We sort it out here. |
41c445ff | 763 | **/ |
7812fddc | 764 | static void i40e_update_vsi_stats(struct i40e_vsi *vsi) |
41c445ff JB |
765 | { |
766 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
767 | struct rtnl_link_stats64 *ons; |
768 | struct rtnl_link_stats64 *ns; /* netdev stats */ | |
769 | struct i40e_eth_stats *oes; | |
770 | struct i40e_eth_stats *es; /* device's eth stats */ | |
771 | u32 tx_restart, tx_busy; | |
bf00b376 | 772 | struct i40e_ring *p; |
41c445ff | 773 | u32 rx_page, rx_buf; |
bf00b376 AA |
774 | u64 bytes, packets; |
775 | unsigned int start; | |
2fc3d715 | 776 | u64 tx_linearize; |
164c9f54 | 777 | u64 tx_force_wb; |
41c445ff JB |
778 | u64 rx_p, rx_b; |
779 | u64 tx_p, tx_b; | |
41c445ff JB |
780 | u16 q; |
781 | ||
0da36b97 JK |
782 | if (test_bit(__I40E_VSI_DOWN, vsi->state) || |
783 | test_bit(__I40E_CONFIG_BUSY, pf->state)) | |
41c445ff JB |
784 | return; |
785 | ||
786 | ns = i40e_get_vsi_stats_struct(vsi); | |
787 | ons = &vsi->net_stats_offsets; | |
788 | es = &vsi->eth_stats; | |
789 | oes = &vsi->eth_stats_offsets; | |
790 | ||
791 | /* Gather up the netdev and vsi stats that the driver collects | |
792 | * on the fly during packet processing | |
793 | */ | |
794 | rx_b = rx_p = 0; | |
795 | tx_b = tx_p = 0; | |
164c9f54 | 796 | tx_restart = tx_busy = tx_linearize = tx_force_wb = 0; |
41c445ff JB |
797 | rx_page = 0; |
798 | rx_buf = 0; | |
980e9b11 | 799 | rcu_read_lock(); |
41c445ff | 800 | for (q = 0; q < vsi->num_queue_pairs; q++) { |
980e9b11 | 801 | /* locate Tx ring */ |
6aa7de05 | 802 | p = READ_ONCE(vsi->tx_rings[q]); |
980e9b11 AD |
803 | |
804 | do { | |
57a7744e | 805 | start = u64_stats_fetch_begin_irq(&p->syncp); |
980e9b11 AD |
806 | packets = p->stats.packets; |
807 | bytes = p->stats.bytes; | |
57a7744e | 808 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); |
980e9b11 AD |
809 | tx_b += bytes; |
810 | tx_p += packets; | |
811 | tx_restart += p->tx_stats.restart_queue; | |
812 | tx_busy += p->tx_stats.tx_busy; | |
2fc3d715 | 813 | tx_linearize += p->tx_stats.tx_linearize; |
164c9f54 | 814 | tx_force_wb += p->tx_stats.tx_force_wb; |
41c445ff | 815 | |
980e9b11 AD |
816 | /* Rx queue is part of the same block as Tx queue */ |
817 | p = &p[1]; | |
818 | do { | |
57a7744e | 819 | start = u64_stats_fetch_begin_irq(&p->syncp); |
980e9b11 AD |
820 | packets = p->stats.packets; |
821 | bytes = p->stats.bytes; | |
57a7744e | 822 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); |
980e9b11 AD |
823 | rx_b += bytes; |
824 | rx_p += packets; | |
420136cc MW |
825 | rx_buf += p->rx_stats.alloc_buff_failed; |
826 | rx_page += p->rx_stats.alloc_page_failed; | |
41c445ff | 827 | } |
980e9b11 | 828 | rcu_read_unlock(); |
41c445ff JB |
829 | vsi->tx_restart = tx_restart; |
830 | vsi->tx_busy = tx_busy; | |
2fc3d715 | 831 | vsi->tx_linearize = tx_linearize; |
164c9f54 | 832 | vsi->tx_force_wb = tx_force_wb; |
41c445ff JB |
833 | vsi->rx_page_failed = rx_page; |
834 | vsi->rx_buf_failed = rx_buf; | |
835 | ||
836 | ns->rx_packets = rx_p; | |
837 | ns->rx_bytes = rx_b; | |
838 | ns->tx_packets = tx_p; | |
839 | ns->tx_bytes = tx_b; | |
840 | ||
41c445ff | 841 | /* update netdev stats from eth stats */ |
7812fddc | 842 | i40e_update_eth_stats(vsi); |
41c445ff JB |
843 | ons->tx_errors = oes->tx_errors; |
844 | ns->tx_errors = es->tx_errors; | |
845 | ons->multicast = oes->rx_multicast; | |
846 | ns->multicast = es->rx_multicast; | |
41a9e55c SN |
847 | ons->rx_dropped = oes->rx_discards; |
848 | ns->rx_dropped = es->rx_discards; | |
41c445ff JB |
849 | ons->tx_dropped = oes->tx_discards; |
850 | ns->tx_dropped = es->tx_discards; | |
851 | ||
7812fddc | 852 | /* pull in a couple PF stats if this is the main vsi */ |
41c445ff | 853 | if (vsi == pf->vsi[pf->lan_vsi]) { |
7812fddc SN |
854 | ns->rx_crc_errors = pf->stats.crc_errors; |
855 | ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes; | |
856 | ns->rx_length_errors = pf->stats.rx_length_errors; | |
857 | } | |
858 | } | |
41c445ff | 859 | |
7812fddc | 860 | /** |
b40c82e6 | 861 | * i40e_update_pf_stats - Update the PF statistics counters. |
7812fddc SN |
862 | * @pf: the PF to be updated |
863 | **/ | |
864 | static void i40e_update_pf_stats(struct i40e_pf *pf) | |
865 | { | |
866 | struct i40e_hw_port_stats *osd = &pf->stats_offsets; | |
867 | struct i40e_hw_port_stats *nsd = &pf->stats; | |
868 | struct i40e_hw *hw = &pf->hw; | |
869 | u32 val; | |
870 | int i; | |
41c445ff | 871 | |
7812fddc SN |
872 | i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port), |
873 | I40E_GLPRT_GORCL(hw->port), | |
874 | pf->stat_offsets_loaded, | |
875 | &osd->eth.rx_bytes, &nsd->eth.rx_bytes); | |
876 | i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port), | |
877 | I40E_GLPRT_GOTCL(hw->port), | |
878 | pf->stat_offsets_loaded, | |
879 | &osd->eth.tx_bytes, &nsd->eth.tx_bytes); | |
880 | i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port), | |
881 | pf->stat_offsets_loaded, | |
882 | &osd->eth.rx_discards, | |
883 | &nsd->eth.rx_discards); | |
532d283d SN |
884 | i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port), |
885 | I40E_GLPRT_UPRCL(hw->port), | |
886 | pf->stat_offsets_loaded, | |
887 | &osd->eth.rx_unicast, | |
888 | &nsd->eth.rx_unicast); | |
7812fddc SN |
889 | i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port), |
890 | I40E_GLPRT_MPRCL(hw->port), | |
891 | pf->stat_offsets_loaded, | |
892 | &osd->eth.rx_multicast, | |
893 | &nsd->eth.rx_multicast); | |
532d283d SN |
894 | i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port), |
895 | I40E_GLPRT_BPRCL(hw->port), | |
896 | pf->stat_offsets_loaded, | |
897 | &osd->eth.rx_broadcast, | |
898 | &nsd->eth.rx_broadcast); | |
899 | i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port), | |
900 | I40E_GLPRT_UPTCL(hw->port), | |
901 | pf->stat_offsets_loaded, | |
902 | &osd->eth.tx_unicast, | |
903 | &nsd->eth.tx_unicast); | |
904 | i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port), | |
905 | I40E_GLPRT_MPTCL(hw->port), | |
906 | pf->stat_offsets_loaded, | |
907 | &osd->eth.tx_multicast, | |
908 | &nsd->eth.tx_multicast); | |
909 | i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port), | |
910 | I40E_GLPRT_BPTCL(hw->port), | |
911 | pf->stat_offsets_loaded, | |
912 | &osd->eth.tx_broadcast, | |
913 | &nsd->eth.tx_broadcast); | |
41c445ff | 914 | |
7812fddc SN |
915 | i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port), |
916 | pf->stat_offsets_loaded, | |
917 | &osd->tx_dropped_link_down, | |
918 | &nsd->tx_dropped_link_down); | |
41c445ff | 919 | |
7812fddc SN |
920 | i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port), |
921 | pf->stat_offsets_loaded, | |
922 | &osd->crc_errors, &nsd->crc_errors); | |
41c445ff | 923 | |
7812fddc SN |
924 | i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port), |
925 | pf->stat_offsets_loaded, | |
926 | &osd->illegal_bytes, &nsd->illegal_bytes); | |
41c445ff | 927 | |
7812fddc SN |
928 | i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port), |
929 | pf->stat_offsets_loaded, | |
930 | &osd->mac_local_faults, | |
931 | &nsd->mac_local_faults); | |
932 | i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port), | |
933 | pf->stat_offsets_loaded, | |
934 | &osd->mac_remote_faults, | |
935 | &nsd->mac_remote_faults); | |
41c445ff | 936 | |
7812fddc SN |
937 | i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port), |
938 | pf->stat_offsets_loaded, | |
939 | &osd->rx_length_errors, | |
940 | &nsd->rx_length_errors); | |
41c445ff | 941 | |
7812fddc SN |
942 | i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port), |
943 | pf->stat_offsets_loaded, | |
944 | &osd->link_xon_rx, &nsd->link_xon_rx); | |
945 | i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port), | |
946 | pf->stat_offsets_loaded, | |
947 | &osd->link_xon_tx, &nsd->link_xon_tx); | |
95db239f NP |
948 | i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port), |
949 | pf->stat_offsets_loaded, | |
950 | &osd->link_xoff_rx, &nsd->link_xoff_rx); | |
7812fddc SN |
951 | i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port), |
952 | pf->stat_offsets_loaded, | |
953 | &osd->link_xoff_tx, &nsd->link_xoff_tx); | |
41c445ff | 954 | |
7812fddc | 955 | for (i = 0; i < 8; i++) { |
95db239f NP |
956 | i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i), |
957 | pf->stat_offsets_loaded, | |
958 | &osd->priority_xoff_rx[i], | |
959 | &nsd->priority_xoff_rx[i]); | |
7812fddc | 960 | i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i), |
41c445ff | 961 | pf->stat_offsets_loaded, |
7812fddc SN |
962 | &osd->priority_xon_rx[i], |
963 | &nsd->priority_xon_rx[i]); | |
964 | i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i), | |
41c445ff | 965 | pf->stat_offsets_loaded, |
7812fddc SN |
966 | &osd->priority_xon_tx[i], |
967 | &nsd->priority_xon_tx[i]); | |
968 | i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i), | |
41c445ff | 969 | pf->stat_offsets_loaded, |
7812fddc SN |
970 | &osd->priority_xoff_tx[i], |
971 | &nsd->priority_xoff_tx[i]); | |
972 | i40e_stat_update32(hw, | |
973 | I40E_GLPRT_RXON2OFFCNT(hw->port, i), | |
bee5af7e | 974 | pf->stat_offsets_loaded, |
7812fddc SN |
975 | &osd->priority_xon_2_xoff[i], |
976 | &nsd->priority_xon_2_xoff[i]); | |
41c445ff JB |
977 | } |
978 | ||
7812fddc SN |
979 | i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port), |
980 | I40E_GLPRT_PRC64L(hw->port), | |
981 | pf->stat_offsets_loaded, | |
982 | &osd->rx_size_64, &nsd->rx_size_64); | |
983 | i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port), | |
984 | I40E_GLPRT_PRC127L(hw->port), | |
985 | pf->stat_offsets_loaded, | |
986 | &osd->rx_size_127, &nsd->rx_size_127); | |
987 | i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port), | |
988 | I40E_GLPRT_PRC255L(hw->port), | |
989 | pf->stat_offsets_loaded, | |
990 | &osd->rx_size_255, &nsd->rx_size_255); | |
991 | i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port), | |
992 | I40E_GLPRT_PRC511L(hw->port), | |
993 | pf->stat_offsets_loaded, | |
994 | &osd->rx_size_511, &nsd->rx_size_511); | |
995 | i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port), | |
996 | I40E_GLPRT_PRC1023L(hw->port), | |
997 | pf->stat_offsets_loaded, | |
998 | &osd->rx_size_1023, &nsd->rx_size_1023); | |
999 | i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port), | |
1000 | I40E_GLPRT_PRC1522L(hw->port), | |
1001 | pf->stat_offsets_loaded, | |
1002 | &osd->rx_size_1522, &nsd->rx_size_1522); | |
1003 | i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port), | |
1004 | I40E_GLPRT_PRC9522L(hw->port), | |
1005 | pf->stat_offsets_loaded, | |
1006 | &osd->rx_size_big, &nsd->rx_size_big); | |
1007 | ||
1008 | i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port), | |
1009 | I40E_GLPRT_PTC64L(hw->port), | |
1010 | pf->stat_offsets_loaded, | |
1011 | &osd->tx_size_64, &nsd->tx_size_64); | |
1012 | i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port), | |
1013 | I40E_GLPRT_PTC127L(hw->port), | |
1014 | pf->stat_offsets_loaded, | |
1015 | &osd->tx_size_127, &nsd->tx_size_127); | |
1016 | i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port), | |
1017 | I40E_GLPRT_PTC255L(hw->port), | |
1018 | pf->stat_offsets_loaded, | |
1019 | &osd->tx_size_255, &nsd->tx_size_255); | |
1020 | i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port), | |
1021 | I40E_GLPRT_PTC511L(hw->port), | |
1022 | pf->stat_offsets_loaded, | |
1023 | &osd->tx_size_511, &nsd->tx_size_511); | |
1024 | i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port), | |
1025 | I40E_GLPRT_PTC1023L(hw->port), | |
1026 | pf->stat_offsets_loaded, | |
1027 | &osd->tx_size_1023, &nsd->tx_size_1023); | |
1028 | i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port), | |
1029 | I40E_GLPRT_PTC1522L(hw->port), | |
1030 | pf->stat_offsets_loaded, | |
1031 | &osd->tx_size_1522, &nsd->tx_size_1522); | |
1032 | i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port), | |
1033 | I40E_GLPRT_PTC9522L(hw->port), | |
1034 | pf->stat_offsets_loaded, | |
1035 | &osd->tx_size_big, &nsd->tx_size_big); | |
1036 | ||
1037 | i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port), | |
1038 | pf->stat_offsets_loaded, | |
1039 | &osd->rx_undersize, &nsd->rx_undersize); | |
1040 | i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port), | |
1041 | pf->stat_offsets_loaded, | |
1042 | &osd->rx_fragments, &nsd->rx_fragments); | |
1043 | i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port), | |
1044 | pf->stat_offsets_loaded, | |
1045 | &osd->rx_oversize, &nsd->rx_oversize); | |
1046 | i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port), | |
1047 | pf->stat_offsets_loaded, | |
1048 | &osd->rx_jabber, &nsd->rx_jabber); | |
1049 | ||
433c47de | 1050 | /* FDIR stats */ |
0dc8692e MS |
1051 | i40e_stat_update_and_clear32(hw, |
1052 | I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(hw->pf_id)), | |
1053 | &nsd->fd_atr_match); | |
1054 | i40e_stat_update_and_clear32(hw, | |
1055 | I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(hw->pf_id)), | |
1056 | &nsd->fd_sb_match); | |
1057 | i40e_stat_update_and_clear32(hw, | |
1058 | I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(hw->pf_id)), | |
1059 | &nsd->fd_atr_tunnel_match); | |
433c47de | 1060 | |
7812fddc SN |
1061 | val = rd32(hw, I40E_PRTPM_EEE_STAT); |
1062 | nsd->tx_lpi_status = | |
1063 | (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >> | |
1064 | I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT; | |
1065 | nsd->rx_lpi_status = | |
1066 | (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >> | |
1067 | I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT; | |
1068 | i40e_stat_update32(hw, I40E_PRTPM_TLPIC, | |
1069 | pf->stat_offsets_loaded, | |
1070 | &osd->tx_lpi_count, &nsd->tx_lpi_count); | |
1071 | i40e_stat_update32(hw, I40E_PRTPM_RLPIC, | |
1072 | pf->stat_offsets_loaded, | |
1073 | &osd->rx_lpi_count, &nsd->rx_lpi_count); | |
1074 | ||
d0389e51 | 1075 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED && |
134201ae | 1076 | !test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) |
d0389e51 ASJ |
1077 | nsd->fd_sb_status = true; |
1078 | else | |
1079 | nsd->fd_sb_status = false; | |
1080 | ||
1081 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED && | |
134201ae | 1082 | !test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) |
d0389e51 ASJ |
1083 | nsd->fd_atr_status = true; |
1084 | else | |
1085 | nsd->fd_atr_status = false; | |
1086 | ||
41c445ff JB |
1087 | pf->stat_offsets_loaded = true; |
1088 | } | |
1089 | ||
7812fddc SN |
1090 | /** |
1091 | * i40e_update_stats - Update the various statistics counters. | |
1092 | * @vsi: the VSI to be updated | |
1093 | * | |
1094 | * Update the various stats for this VSI and its related entities. | |
1095 | **/ | |
1096 | void i40e_update_stats(struct i40e_vsi *vsi) | |
1097 | { | |
1098 | struct i40e_pf *pf = vsi->back; | |
1099 | ||
1100 | if (vsi == pf->vsi[pf->lan_vsi]) | |
1101 | i40e_update_pf_stats(pf); | |
1102 | ||
1103 | i40e_update_vsi_stats(vsi); | |
1104 | } | |
1105 | ||
41c445ff JB |
1106 | /** |
1107 | * i40e_find_filter - Search VSI filter list for specific mac/vlan filter | |
1108 | * @vsi: the VSI to be searched | |
1109 | * @macaddr: the MAC address | |
1110 | * @vlan: the vlan | |
41c445ff JB |
1111 | * |
1112 | * Returns ptr to the filter object or NULL | |
1113 | **/ | |
1114 | static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi, | |
6622f5cd | 1115 | const u8 *macaddr, s16 vlan) |
41c445ff JB |
1116 | { |
1117 | struct i40e_mac_filter *f; | |
278e7d0b | 1118 | u64 key; |
41c445ff JB |
1119 | |
1120 | if (!vsi || !macaddr) | |
1121 | return NULL; | |
1122 | ||
278e7d0b JK |
1123 | key = i40e_addr_to_hkey(macaddr); |
1124 | hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) { | |
41c445ff | 1125 | if ((ether_addr_equal(macaddr, f->macaddr)) && |
1bc87e80 | 1126 | (vlan == f->vlan)) |
41c445ff JB |
1127 | return f; |
1128 | } | |
1129 | return NULL; | |
1130 | } | |
1131 | ||
1132 | /** | |
1133 | * i40e_find_mac - Find a mac addr in the macvlan filters list | |
1134 | * @vsi: the VSI to be searched | |
1135 | * @macaddr: the MAC address we are searching for | |
41c445ff JB |
1136 | * |
1137 | * Returns the first filter with the provided MAC address or NULL if | |
1138 | * MAC address was not found | |
1139 | **/ | |
6622f5cd | 1140 | struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr) |
41c445ff JB |
1141 | { |
1142 | struct i40e_mac_filter *f; | |
278e7d0b | 1143 | u64 key; |
41c445ff JB |
1144 | |
1145 | if (!vsi || !macaddr) | |
1146 | return NULL; | |
1147 | ||
278e7d0b JK |
1148 | key = i40e_addr_to_hkey(macaddr); |
1149 | hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) { | |
1bc87e80 | 1150 | if ((ether_addr_equal(macaddr, f->macaddr))) |
41c445ff JB |
1151 | return f; |
1152 | } | |
1153 | return NULL; | |
1154 | } | |
1155 | ||
1156 | /** | |
1157 | * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode | |
1158 | * @vsi: the VSI to be searched | |
1159 | * | |
1160 | * Returns true if VSI is in vlan mode or false otherwise | |
1161 | **/ | |
1162 | bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi) | |
1163 | { | |
cbebb85f JK |
1164 | /* If we have a PVID, always operate in VLAN mode */ |
1165 | if (vsi->info.pvid) | |
1166 | return true; | |
1167 | ||
1168 | /* We need to operate in VLAN mode whenever we have any filters with | |
1169 | * a VLAN other than I40E_VLAN_ALL. We could check the table each | |
1170 | * time, incurring search cost repeatedly. However, we can notice two | |
1171 | * things: | |
1172 | * | |
1173 | * 1) the only place where we can gain a VLAN filter is in | |
1174 | * i40e_add_filter. | |
1175 | * | |
1176 | * 2) the only place where filters are actually removed is in | |
0b7c8b5d | 1177 | * i40e_sync_filters_subtask. |
cbebb85f JK |
1178 | * |
1179 | * Thus, we can simply use a boolean value, has_vlan_filters which we | |
1180 | * will set to true when we add a VLAN filter in i40e_add_filter. Then | |
1181 | * we have to perform the full search after deleting filters in | |
0b7c8b5d | 1182 | * i40e_sync_filters_subtask, but we already have to search |
cbebb85f JK |
1183 | * filters here and can perform the check at the same time. This |
1184 | * results in avoiding embedding a loop for VLAN mode inside another | |
1185 | * loop over all the filters, and should maintain correctness as noted | |
1186 | * above. | |
41c445ff | 1187 | */ |
cbebb85f | 1188 | return vsi->has_vlan_filter; |
41c445ff JB |
1189 | } |
1190 | ||
489a3265 JK |
1191 | /** |
1192 | * i40e_correct_mac_vlan_filters - Correct non-VLAN filters if necessary | |
1193 | * @vsi: the VSI to configure | |
1194 | * @tmp_add_list: list of filters ready to be added | |
1195 | * @tmp_del_list: list of filters ready to be deleted | |
1196 | * @vlan_filters: the number of active VLAN filters | |
1197 | * | |
1198 | * Update VLAN=0 and VLAN=-1 (I40E_VLAN_ANY) filters properly so that they | |
1199 | * behave as expected. If we have any active VLAN filters remaining or about | |
1200 | * to be added then we need to update non-VLAN filters to be marked as VLAN=0 | |
1201 | * so that they only match against untagged traffic. If we no longer have any | |
1202 | * active VLAN filters, we need to make all non-VLAN filters marked as VLAN=-1 | |
1203 | * so that they match against both tagged and untagged traffic. In this way, | |
1204 | * we ensure that we correctly receive the desired traffic. This ensures that | |
1205 | * when we have an active VLAN we will receive only untagged traffic and | |
1206 | * traffic matching active VLANs. If we have no active VLANs then we will | |
1207 | * operate in non-VLAN mode and receive all traffic, tagged or untagged. | |
1208 | * | |
1209 | * Finally, in a similar fashion, this function also corrects filters when | |
1210 | * there is an active PVID assigned to this VSI. | |
1211 | * | |
1212 | * In case of memory allocation failure return -ENOMEM. Otherwise, return 0. | |
1213 | * | |
1214 | * This function is only expected to be called from within | |
1215 | * i40e_sync_vsi_filters. | |
1216 | * | |
1217 | * NOTE: This function expects to be called while under the | |
1218 | * mac_filter_hash_lock | |
1219 | */ | |
1220 | static int i40e_correct_mac_vlan_filters(struct i40e_vsi *vsi, | |
1221 | struct hlist_head *tmp_add_list, | |
1222 | struct hlist_head *tmp_del_list, | |
1223 | int vlan_filters) | |
1224 | { | |
5cb25901 | 1225 | s16 pvid = le16_to_cpu(vsi->info.pvid); |
489a3265 | 1226 | struct i40e_mac_filter *f, *add_head; |
671889e6 | 1227 | struct i40e_new_mac_filter *new; |
489a3265 JK |
1228 | struct hlist_node *h; |
1229 | int bkt, new_vlan; | |
1230 | ||
1231 | /* To determine if a particular filter needs to be replaced we | |
1232 | * have the three following conditions: | |
1233 | * | |
1234 | * a) if we have a PVID assigned, then all filters which are | |
1235 | * not marked as VLAN=PVID must be replaced with filters that | |
1236 | * are. | |
1237 | * b) otherwise, if we have any active VLANS, all filters | |
1238 | * which are marked as VLAN=-1 must be replaced with | |
1239 | * filters marked as VLAN=0 | |
1240 | * c) finally, if we do not have any active VLANS, all filters | |
1241 | * which are marked as VLAN=0 must be replaced with filters | |
1242 | * marked as VLAN=-1 | |
1243 | */ | |
1244 | ||
1245 | /* Update the filters about to be added in place */ | |
671889e6 | 1246 | hlist_for_each_entry(new, tmp_add_list, hlist) { |
5cb25901 JK |
1247 | if (pvid && new->f->vlan != pvid) |
1248 | new->f->vlan = pvid; | |
671889e6 JK |
1249 | else if (vlan_filters && new->f->vlan == I40E_VLAN_ANY) |
1250 | new->f->vlan = 0; | |
1251 | else if (!vlan_filters && new->f->vlan == 0) | |
1252 | new->f->vlan = I40E_VLAN_ANY; | |
489a3265 JK |
1253 | } |
1254 | ||
1255 | /* Update the remaining active filters */ | |
1256 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { | |
1257 | /* Combine the checks for whether a filter needs to be changed | |
1258 | * and then determine the new VLAN inside the if block, in | |
1259 | * order to avoid duplicating code for adding the new filter | |
1260 | * then deleting the old filter. | |
1261 | */ | |
5cb25901 | 1262 | if ((pvid && f->vlan != pvid) || |
489a3265 JK |
1263 | (vlan_filters && f->vlan == I40E_VLAN_ANY) || |
1264 | (!vlan_filters && f->vlan == 0)) { | |
1265 | /* Determine the new vlan we will be adding */ | |
5cb25901 JK |
1266 | if (pvid) |
1267 | new_vlan = pvid; | |
489a3265 JK |
1268 | else if (vlan_filters) |
1269 | new_vlan = 0; | |
1270 | else | |
1271 | new_vlan = I40E_VLAN_ANY; | |
1272 | ||
1273 | /* Create the new filter */ | |
1274 | add_head = i40e_add_filter(vsi, f->macaddr, new_vlan); | |
1275 | if (!add_head) | |
1276 | return -ENOMEM; | |
1277 | ||
671889e6 JK |
1278 | /* Create a temporary i40e_new_mac_filter */ |
1279 | new = kzalloc(sizeof(*new), GFP_ATOMIC); | |
1280 | if (!new) | |
1281 | return -ENOMEM; | |
1282 | ||
1283 | new->f = add_head; | |
1284 | new->state = add_head->state; | |
1285 | ||
1286 | /* Add the new filter to the tmp list */ | |
1287 | hlist_add_head(&new->hlist, tmp_add_list); | |
489a3265 JK |
1288 | |
1289 | /* Put the original filter into the delete list */ | |
1290 | f->state = I40E_FILTER_REMOVE; | |
1291 | hash_del(&f->hlist); | |
1292 | hlist_add_head(&f->hlist, tmp_del_list); | |
1293 | } | |
1294 | } | |
1295 | ||
1296 | vsi->has_vlan_filter = !!vlan_filters; | |
1297 | ||
1298 | return 0; | |
1299 | } | |
1300 | ||
1596b5dd JK |
1301 | /** |
1302 | * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM | |
1303 | * @vsi: the PF Main VSI - inappropriate for any other VSI | |
1304 | * @macaddr: the MAC address | |
1305 | * | |
1306 | * Remove whatever filter the firmware set up so the driver can manage | |
1307 | * its own filtering intelligently. | |
1308 | **/ | |
1309 | static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr) | |
1310 | { | |
1311 | struct i40e_aqc_remove_macvlan_element_data element; | |
1312 | struct i40e_pf *pf = vsi->back; | |
1313 | ||
1314 | /* Only appropriate for the PF main VSI */ | |
1315 | if (vsi->type != I40E_VSI_MAIN) | |
1316 | return; | |
1317 | ||
1318 | memset(&element, 0, sizeof(element)); | |
1319 | ether_addr_copy(element.mac_addr, macaddr); | |
1320 | element.vlan_tag = 0; | |
1321 | /* Ignore error returns, some firmware does it this way... */ | |
1322 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; | |
1323 | i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); | |
1324 | ||
1325 | memset(&element, 0, sizeof(element)); | |
1326 | ether_addr_copy(element.mac_addr, macaddr); | |
1327 | element.vlan_tag = 0; | |
1328 | /* ...and some firmware does it this way. */ | |
1329 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | | |
1330 | I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; | |
1331 | i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); | |
1332 | } | |
1333 | ||
41c445ff JB |
1334 | /** |
1335 | * i40e_add_filter - Add a mac/vlan filter to the VSI | |
1336 | * @vsi: the VSI to be searched | |
1337 | * @macaddr: the MAC address | |
1338 | * @vlan: the vlan | |
41c445ff JB |
1339 | * |
1340 | * Returns ptr to the filter object or NULL when no memory available. | |
21659035 | 1341 | * |
278e7d0b | 1342 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
21659035 | 1343 | * being held. |
41c445ff JB |
1344 | **/ |
1345 | struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, | |
6622f5cd | 1346 | const u8 *macaddr, s16 vlan) |
41c445ff JB |
1347 | { |
1348 | struct i40e_mac_filter *f; | |
278e7d0b | 1349 | u64 key; |
41c445ff JB |
1350 | |
1351 | if (!vsi || !macaddr) | |
1352 | return NULL; | |
1353 | ||
1bc87e80 | 1354 | f = i40e_find_filter(vsi, macaddr, vlan); |
41c445ff JB |
1355 | if (!f) { |
1356 | f = kzalloc(sizeof(*f), GFP_ATOMIC); | |
1357 | if (!f) | |
1bc87e80 | 1358 | return NULL; |
41c445ff | 1359 | |
cbebb85f JK |
1360 | /* Update the boolean indicating if we need to function in |
1361 | * VLAN mode. | |
1362 | */ | |
1363 | if (vlan >= 0) | |
1364 | vsi->has_vlan_filter = true; | |
1365 | ||
9a173901 | 1366 | ether_addr_copy(f->macaddr, macaddr); |
41c445ff | 1367 | f->vlan = vlan; |
7363115e | 1368 | f->state = I40E_FILTER_NEW; |
278e7d0b JK |
1369 | INIT_HLIST_NODE(&f->hlist); |
1370 | ||
1371 | key = i40e_addr_to_hkey(macaddr); | |
1372 | hash_add(vsi->mac_filter_hash, &f->hlist, key); | |
41c445ff | 1373 | |
41c445ff | 1374 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; |
bfe040c3 | 1375 | set_bit(__I40E_MACVLAN_SYNC_PENDING, vsi->back->state); |
41c445ff JB |
1376 | } |
1377 | ||
1bc87e80 JK |
1378 | /* If we're asked to add a filter that has been marked for removal, it |
1379 | * is safe to simply restore it to active state. __i40e_del_filter | |
1380 | * will have simply deleted any filters which were previously marked | |
1381 | * NEW or FAILED, so if it is currently marked REMOVE it must have | |
1382 | * previously been ACTIVE. Since we haven't yet run the sync filters | |
1383 | * task, just restore this filter to the ACTIVE state so that the | |
1384 | * sync task leaves it in place | |
1385 | */ | |
1386 | if (f->state == I40E_FILTER_REMOVE) | |
1387 | f->state = I40E_FILTER_ACTIVE; | |
1388 | ||
41c445ff JB |
1389 | return f; |
1390 | } | |
1391 | ||
1392 | /** | |
290d2557 JK |
1393 | * __i40e_del_filter - Remove a specific filter from the VSI |
1394 | * @vsi: VSI to remove from | |
1395 | * @f: the filter to remove from the list | |
1396 | * | |
1397 | * This function should be called instead of i40e_del_filter only if you know | |
1398 | * the exact filter you will remove already, such as via i40e_find_filter or | |
1399 | * i40e_find_mac. | |
21659035 | 1400 | * |
278e7d0b | 1401 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
21659035 | 1402 | * being held. |
c3c7ea27 MW |
1403 | * ANOTHER NOTE: This function MUST be called from within the context of |
1404 | * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe() | |
1405 | * instead of list_for_each_entry(). | |
41c445ff | 1406 | **/ |
148141bb | 1407 | void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f) |
41c445ff | 1408 | { |
1bc87e80 | 1409 | if (!f) |
41c445ff JB |
1410 | return; |
1411 | ||
a410c821 AB |
1412 | /* If the filter was never added to firmware then we can just delete it |
1413 | * directly and we don't want to set the status to remove or else an | |
1414 | * admin queue command will unnecessarily fire. | |
1415 | */ | |
1bc87e80 JK |
1416 | if ((f->state == I40E_FILTER_FAILED) || |
1417 | (f->state == I40E_FILTER_NEW)) { | |
278e7d0b | 1418 | hash_del(&f->hlist); |
1bc87e80 | 1419 | kfree(f); |
41c445ff | 1420 | } else { |
1bc87e80 | 1421 | f->state = I40E_FILTER_REMOVE; |
41c445ff | 1422 | } |
a410c821 AB |
1423 | |
1424 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
eab077aa | 1425 | set_bit(__I40E_MACVLAN_SYNC_PENDING, vsi->back->state); |
41c445ff JB |
1426 | } |
1427 | ||
290d2557 JK |
1428 | /** |
1429 | * i40e_del_filter - Remove a MAC/VLAN filter from the VSI | |
1430 | * @vsi: the VSI to be searched | |
1431 | * @macaddr: the MAC address | |
1432 | * @vlan: the VLAN | |
1433 | * | |
278e7d0b | 1434 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
290d2557 JK |
1435 | * being held. |
1436 | * ANOTHER NOTE: This function MUST be called from within the context of | |
1437 | * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe() | |
1438 | * instead of list_for_each_entry(). | |
1439 | **/ | |
1440 | void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan) | |
1441 | { | |
1442 | struct i40e_mac_filter *f; | |
1443 | ||
1444 | if (!vsi || !macaddr) | |
1445 | return; | |
1446 | ||
1447 | f = i40e_find_filter(vsi, macaddr, vlan); | |
1448 | __i40e_del_filter(vsi, f); | |
1449 | } | |
1450 | ||
35ec2ff3 | 1451 | /** |
feffdbe4 | 1452 | * i40e_add_mac_filter - Add a MAC filter for all active VLANs |
35ec2ff3 JK |
1453 | * @vsi: the VSI to be searched |
1454 | * @macaddr: the mac address to be filtered | |
1455 | * | |
feffdbe4 JK |
1456 | * If we're not in VLAN mode, just add the filter to I40E_VLAN_ANY. Otherwise, |
1457 | * go through all the macvlan filters and add a macvlan filter for each | |
5feb3d7b JK |
1458 | * unique vlan that already exists. If a PVID has been assigned, instead only |
1459 | * add the macaddr to that VLAN. | |
35ec2ff3 | 1460 | * |
5feb3d7b | 1461 | * Returns last filter added on success, else NULL |
35ec2ff3 | 1462 | **/ |
feffdbe4 JK |
1463 | struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, |
1464 | const u8 *macaddr) | |
35ec2ff3 | 1465 | { |
5feb3d7b | 1466 | struct i40e_mac_filter *f, *add = NULL; |
278e7d0b JK |
1467 | struct hlist_node *h; |
1468 | int bkt; | |
5feb3d7b JK |
1469 | |
1470 | if (vsi->info.pvid) | |
1471 | return i40e_add_filter(vsi, macaddr, | |
1472 | le16_to_cpu(vsi->info.pvid)); | |
35ec2ff3 | 1473 | |
7aaf9536 JK |
1474 | if (!i40e_is_vsi_in_vlan(vsi)) |
1475 | return i40e_add_filter(vsi, macaddr, I40E_VLAN_ANY); | |
1476 | ||
278e7d0b | 1477 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
57b341d6 JK |
1478 | if (f->state == I40E_FILTER_REMOVE) |
1479 | continue; | |
5feb3d7b JK |
1480 | add = i40e_add_filter(vsi, macaddr, f->vlan); |
1481 | if (!add) | |
1482 | return NULL; | |
35ec2ff3 JK |
1483 | } |
1484 | ||
5feb3d7b | 1485 | return add; |
35ec2ff3 JK |
1486 | } |
1487 | ||
1488 | /** | |
feffdbe4 | 1489 | * i40e_del_mac_filter - Remove a MAC filter from all VLANs |
35ec2ff3 JK |
1490 | * @vsi: the VSI to be searched |
1491 | * @macaddr: the mac address to be removed | |
1492 | * | |
feffdbe4 JK |
1493 | * Removes a given MAC address from a VSI regardless of what VLAN it has been |
1494 | * associated with. | |
35ec2ff3 JK |
1495 | * |
1496 | * Returns 0 for success, or error | |
1497 | **/ | |
feffdbe4 | 1498 | int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr) |
35ec2ff3 | 1499 | { |
278e7d0b JK |
1500 | struct i40e_mac_filter *f; |
1501 | struct hlist_node *h; | |
290d2557 | 1502 | bool found = false; |
278e7d0b | 1503 | int bkt; |
35ec2ff3 | 1504 | |
6a9a5ec1 | 1505 | lockdep_assert_held(&vsi->mac_filter_hash_lock); |
278e7d0b | 1506 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
290d2557 JK |
1507 | if (ether_addr_equal(macaddr, f->macaddr)) { |
1508 | __i40e_del_filter(vsi, f); | |
1509 | found = true; | |
1510 | } | |
35ec2ff3 | 1511 | } |
290d2557 JK |
1512 | |
1513 | if (found) | |
35ec2ff3 | 1514 | return 0; |
290d2557 JK |
1515 | else |
1516 | return -ENOENT; | |
35ec2ff3 JK |
1517 | } |
1518 | ||
41c445ff JB |
1519 | /** |
1520 | * i40e_set_mac - NDO callback to set mac address | |
1521 | * @netdev: network interface device structure | |
1522 | * @p: pointer to an address structure | |
1523 | * | |
1524 | * Returns 0 on success, negative on failure | |
1525 | **/ | |
1526 | static int i40e_set_mac(struct net_device *netdev, void *p) | |
1527 | { | |
1528 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1529 | struct i40e_vsi *vsi = np->vsi; | |
30650cc5 SN |
1530 | struct i40e_pf *pf = vsi->back; |
1531 | struct i40e_hw *hw = &pf->hw; | |
41c445ff | 1532 | struct sockaddr *addr = p; |
41c445ff JB |
1533 | |
1534 | if (!is_valid_ether_addr(addr->sa_data)) | |
1535 | return -EADDRNOTAVAIL; | |
1536 | ||
30650cc5 SN |
1537 | if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) { |
1538 | netdev_info(netdev, "already using mac address %pM\n", | |
1539 | addr->sa_data); | |
1540 | return 0; | |
1541 | } | |
41c445ff | 1542 | |
e7bac7af PM |
1543 | if (test_bit(__I40E_DOWN, pf->state) || |
1544 | test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) | |
80f6428f ASJ |
1545 | return -EADDRNOTAVAIL; |
1546 | ||
30650cc5 SN |
1547 | if (ether_addr_equal(hw->mac.addr, addr->sa_data)) |
1548 | netdev_info(netdev, "returning to hw mac address %pM\n", | |
1549 | hw->mac.addr); | |
1550 | else | |
1551 | netdev_info(netdev, "set new mac address %pM\n", addr->sa_data); | |
1552 | ||
458867b2 | 1553 | /* Copy the address first, so that we avoid a possible race with |
158daed1 SA |
1554 | * .set_rx_mode(). |
1555 | * - Remove old address from MAC filter | |
1556 | * - Copy new address | |
1557 | * - Add new address to MAC filter | |
458867b2 | 1558 | */ |
278e7d0b | 1559 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
feffdbe4 | 1560 | i40e_del_mac_filter(vsi, netdev->dev_addr); |
158daed1 SA |
1561 | ether_addr_copy(netdev->dev_addr, addr->sa_data); |
1562 | i40e_add_mac_filter(vsi, netdev->dev_addr); | |
278e7d0b | 1563 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
158daed1 | 1564 | |
41c445ff JB |
1565 | if (vsi->type == I40E_VSI_MAIN) { |
1566 | i40e_status ret; | |
6995b36c | 1567 | |
e7bac7af | 1568 | ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL, |
41c445ff | 1569 | addr->sa_data, NULL); |
c3c7ea27 MW |
1570 | if (ret) |
1571 | netdev_info(netdev, "Ignoring error from firmware on LAA update, status %s, AQ ret %s\n", | |
1572 | i40e_stat_str(hw, ret), | |
1573 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
30650cc5 SN |
1574 | } |
1575 | ||
c53934c6 JB |
1576 | /* schedule our worker thread which will take care of |
1577 | * applying the new filter changes | |
1578 | */ | |
e7bac7af | 1579 | i40e_service_event_schedule(pf); |
c53934c6 | 1580 | return 0; |
41c445ff JB |
1581 | } |
1582 | ||
a9ce82f7 AN |
1583 | /** |
1584 | * i40e_config_rss_aq - Prepare for RSS using AQ commands | |
1585 | * @vsi: vsi structure | |
1586 | * @seed: RSS hash seed | |
1587 | **/ | |
1588 | static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed, | |
1589 | u8 *lut, u16 lut_size) | |
1590 | { | |
1591 | struct i40e_pf *pf = vsi->back; | |
1592 | struct i40e_hw *hw = &pf->hw; | |
1593 | int ret = 0; | |
1594 | ||
1595 | if (seed) { | |
1596 | struct i40e_aqc_get_set_rss_key_data *seed_dw = | |
1597 | (struct i40e_aqc_get_set_rss_key_data *)seed; | |
1598 | ret = i40e_aq_set_rss_key(hw, vsi->id, seed_dw); | |
1599 | if (ret) { | |
1600 | dev_info(&pf->pdev->dev, | |
1601 | "Cannot set RSS key, err %s aq_err %s\n", | |
1602 | i40e_stat_str(hw, ret), | |
1603 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
1604 | return ret; | |
1605 | } | |
1606 | } | |
1607 | if (lut) { | |
1608 | bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false; | |
1609 | ||
1610 | ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, lut, lut_size); | |
1611 | if (ret) { | |
1612 | dev_info(&pf->pdev->dev, | |
1613 | "Cannot set RSS lut, err %s aq_err %s\n", | |
1614 | i40e_stat_str(hw, ret), | |
1615 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
1616 | return ret; | |
1617 | } | |
1618 | } | |
1619 | return ret; | |
1620 | } | |
1621 | ||
1622 | /** | |
1623 | * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used | |
1624 | * @vsi: VSI structure | |
1625 | **/ | |
1626 | static int i40e_vsi_config_rss(struct i40e_vsi *vsi) | |
1627 | { | |
1628 | struct i40e_pf *pf = vsi->back; | |
1629 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
1630 | u8 *lut; | |
1631 | int ret; | |
1632 | ||
1633 | if (!(pf->hw_features & I40E_HW_RSS_AQ_CAPABLE)) | |
1634 | return 0; | |
1635 | if (!vsi->rss_size) | |
1636 | vsi->rss_size = min_t(int, pf->alloc_rss_size, | |
1637 | vsi->num_queue_pairs); | |
1638 | if (!vsi->rss_size) | |
1639 | return -EINVAL; | |
1640 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); | |
1641 | if (!lut) | |
1642 | return -ENOMEM; | |
1643 | ||
1644 | /* Use the user configured hash keys and lookup table if there is one, | |
1645 | * otherwise use default | |
1646 | */ | |
1647 | if (vsi->rss_lut_user) | |
1648 | memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size); | |
1649 | else | |
1650 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); | |
1651 | if (vsi->rss_hkey_user) | |
1652 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
1653 | else | |
1654 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
1655 | ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size); | |
1656 | kfree(lut); | |
1657 | return ret; | |
1658 | } | |
1659 | ||
1660 | /** | |
1661 | * i40e_vsi_setup_queue_map_mqprio - Prepares mqprio based tc_config | |
1662 | * @vsi: the VSI being configured, | |
1663 | * @ctxt: VSI context structure | |
1664 | * @enabled_tc: number of traffic classes to enable | |
1665 | * | |
1666 | * Prepares VSI tc_config to have queue configurations based on MQPRIO options. | |
1667 | **/ | |
1668 | static int i40e_vsi_setup_queue_map_mqprio(struct i40e_vsi *vsi, | |
1669 | struct i40e_vsi_context *ctxt, | |
1670 | u8 enabled_tc) | |
1671 | { | |
1672 | u16 qcount = 0, max_qcount, qmap, sections = 0; | |
1673 | int i, override_q, pow, num_qps, ret; | |
1674 | u8 netdev_tc = 0, offset = 0; | |
1675 | ||
1676 | if (vsi->type != I40E_VSI_MAIN) | |
1677 | return -EINVAL; | |
1678 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
1679 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
1680 | vsi->tc_config.numtc = vsi->mqprio_qopt.qopt.num_tc; | |
1681 | vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1; | |
1682 | num_qps = vsi->mqprio_qopt.qopt.count[0]; | |
1683 | ||
1684 | /* find the next higher power-of-2 of num queue pairs */ | |
1685 | pow = ilog2(num_qps); | |
1686 | if (!is_power_of_2(num_qps)) | |
1687 | pow++; | |
1688 | qmap = (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
1689 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
1690 | ||
1691 | /* Setup queue offset/count for all TCs for given VSI */ | |
1692 | max_qcount = vsi->mqprio_qopt.qopt.count[0]; | |
1693 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
1694 | /* See if the given TC is enabled for the given VSI */ | |
1695 | if (vsi->tc_config.enabled_tc & BIT(i)) { | |
1696 | offset = vsi->mqprio_qopt.qopt.offset[i]; | |
1697 | qcount = vsi->mqprio_qopt.qopt.count[i]; | |
1698 | if (qcount > max_qcount) | |
1699 | max_qcount = qcount; | |
1700 | vsi->tc_config.tc_info[i].qoffset = offset; | |
1701 | vsi->tc_config.tc_info[i].qcount = qcount; | |
1702 | vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++; | |
1703 | } else { | |
1704 | /* TC is not enabled so set the offset to | |
1705 | * default queue and allocate one queue | |
1706 | * for the given TC. | |
1707 | */ | |
1708 | vsi->tc_config.tc_info[i].qoffset = 0; | |
1709 | vsi->tc_config.tc_info[i].qcount = 1; | |
1710 | vsi->tc_config.tc_info[i].netdev_tc = 0; | |
1711 | } | |
1712 | } | |
1713 | ||
1714 | /* Set actual Tx/Rx queue pairs */ | |
1715 | vsi->num_queue_pairs = offset + qcount; | |
1716 | ||
1717 | /* Setup queue TC[0].qmap for given VSI context */ | |
1718 | ctxt->info.tc_mapping[0] = cpu_to_le16(qmap); | |
1719 | ctxt->info.mapping_flags |= cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
1720 | ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue); | |
1721 | ctxt->info.valid_sections |= cpu_to_le16(sections); | |
1722 | ||
1723 | /* Reconfigure RSS for main VSI with max queue count */ | |
1724 | vsi->rss_size = max_qcount; | |
1725 | ret = i40e_vsi_config_rss(vsi); | |
1726 | if (ret) { | |
1727 | dev_info(&vsi->back->pdev->dev, | |
1728 | "Failed to reconfig rss for num_queues (%u)\n", | |
1729 | max_qcount); | |
1730 | return ret; | |
1731 | } | |
1732 | vsi->reconfig_rss = true; | |
1733 | dev_dbg(&vsi->back->pdev->dev, | |
1734 | "Reconfigured rss with num_queues (%u)\n", max_qcount); | |
1735 | ||
1736 | /* Find queue count available for channel VSIs and starting offset | |
1737 | * for channel VSIs | |
1738 | */ | |
1739 | override_q = vsi->mqprio_qopt.qopt.count[0]; | |
1740 | if (override_q && override_q < vsi->num_queue_pairs) { | |
1741 | vsi->cnt_q_avail = vsi->num_queue_pairs - override_q; | |
1742 | vsi->next_base_queue = override_q; | |
1743 | } | |
1744 | return 0; | |
1745 | } | |
1746 | ||
41c445ff JB |
1747 | /** |
1748 | * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc | |
1749 | * @vsi: the VSI being setup | |
1750 | * @ctxt: VSI context structure | |
1751 | * @enabled_tc: Enabled TCs bitmap | |
1752 | * @is_add: True if called before Add VSI | |
1753 | * | |
1754 | * Setup VSI queue mapping for enabled traffic classes. | |
1755 | **/ | |
1756 | static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi, | |
1757 | struct i40e_vsi_context *ctxt, | |
1758 | u8 enabled_tc, | |
1759 | bool is_add) | |
1760 | { | |
1761 | struct i40e_pf *pf = vsi->back; | |
1762 | u16 sections = 0; | |
1763 | u8 netdev_tc = 0; | |
bc6d33c8 | 1764 | u16 numtc = 1; |
41c445ff JB |
1765 | u16 qcount; |
1766 | u8 offset; | |
1767 | u16 qmap; | |
1768 | int i; | |
4e3b35b0 | 1769 | u16 num_tc_qps = 0; |
41c445ff JB |
1770 | |
1771 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
1772 | offset = 0; | |
1773 | ||
bc6d33c8 AN |
1774 | /* Number of queues per enabled TC */ |
1775 | num_tc_qps = vsi->alloc_queue_pairs; | |
41c445ff JB |
1776 | if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { |
1777 | /* Find numtc from enabled TC bitmap */ | |
bc6d33c8 | 1778 | for (i = 0, numtc = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
75f5cea9 | 1779 | if (enabled_tc & BIT(i)) /* TC is enabled */ |
41c445ff JB |
1780 | numtc++; |
1781 | } | |
1782 | if (!numtc) { | |
1783 | dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n"); | |
1784 | numtc = 1; | |
1785 | } | |
bc6d33c8 AN |
1786 | num_tc_qps = num_tc_qps / numtc; |
1787 | num_tc_qps = min_t(int, num_tc_qps, | |
1788 | i40e_pf_get_max_q_per_tc(pf)); | |
41c445ff JB |
1789 | } |
1790 | ||
1791 | vsi->tc_config.numtc = numtc; | |
1792 | vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1; | |
1793 | ||
1563f2d2 PJ |
1794 | /* Do not allow use more TC queue pairs than MSI-X vectors exist */ |
1795 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
1796 | num_tc_qps = min_t(int, num_tc_qps, pf->num_lan_msix); | |
1797 | ||
41c445ff JB |
1798 | /* Setup queue offset/count for all TCs for given VSI */ |
1799 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
1800 | /* See if the given TC is enabled for the given VSI */ | |
75f5cea9 | 1801 | if (vsi->tc_config.enabled_tc & BIT(i)) { |
41a1d04b | 1802 | /* TC is enabled */ |
41c445ff JB |
1803 | int pow, num_qps; |
1804 | ||
41c445ff JB |
1805 | switch (vsi->type) { |
1806 | case I40E_VSI_MAIN: | |
bc6d33c8 AN |
1807 | if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | |
1808 | I40E_FLAG_FD_ATR_ENABLED)) || | |
1809 | vsi->tc_config.enabled_tc != 1) { | |
1810 | qcount = min_t(int, pf->alloc_rss_size, | |
1811 | num_tc_qps); | |
1812 | break; | |
1813 | } | |
1e84374f | 1814 | /* fall through */ |
41c445ff JB |
1815 | case I40E_VSI_FDIR: |
1816 | case I40E_VSI_SRIOV: | |
1817 | case I40E_VSI_VMDQ2: | |
1818 | default: | |
4e3b35b0 | 1819 | qcount = num_tc_qps; |
41c445ff JB |
1820 | WARN_ON(i != 0); |
1821 | break; | |
1822 | } | |
4e3b35b0 NP |
1823 | vsi->tc_config.tc_info[i].qoffset = offset; |
1824 | vsi->tc_config.tc_info[i].qcount = qcount; | |
41c445ff | 1825 | |
1e200e4a | 1826 | /* find the next higher power-of-2 of num queue pairs */ |
4e3b35b0 | 1827 | num_qps = qcount; |
41c445ff | 1828 | pow = 0; |
41a1d04b | 1829 | while (num_qps && (BIT_ULL(pow) < qcount)) { |
41c445ff JB |
1830 | pow++; |
1831 | num_qps >>= 1; | |
1832 | } | |
1833 | ||
1834 | vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++; | |
1835 | qmap = | |
1836 | (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
1837 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
1838 | ||
4e3b35b0 | 1839 | offset += qcount; |
41c445ff JB |
1840 | } else { |
1841 | /* TC is not enabled so set the offset to | |
1842 | * default queue and allocate one queue | |
1843 | * for the given TC. | |
1844 | */ | |
1845 | vsi->tc_config.tc_info[i].qoffset = 0; | |
1846 | vsi->tc_config.tc_info[i].qcount = 1; | |
1847 | vsi->tc_config.tc_info[i].netdev_tc = 0; | |
1848 | ||
1849 | qmap = 0; | |
1850 | } | |
1851 | ctxt->info.tc_mapping[i] = cpu_to_le16(qmap); | |
1852 | } | |
1853 | ||
1854 | /* Set actual Tx/Rx queue pairs */ | |
1855 | vsi->num_queue_pairs = offset; | |
9a3bd2f1 ASJ |
1856 | if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) { |
1857 | if (vsi->req_queue_pairs > 0) | |
1858 | vsi->num_queue_pairs = vsi->req_queue_pairs; | |
26cdc443 | 1859 | else if (pf->flags & I40E_FLAG_MSIX_ENABLED) |
9a3bd2f1 ASJ |
1860 | vsi->num_queue_pairs = pf->num_lan_msix; |
1861 | } | |
41c445ff JB |
1862 | |
1863 | /* Scheduler section valid can only be set for ADD VSI */ | |
1864 | if (is_add) { | |
1865 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
1866 | ||
1867 | ctxt->info.up_enable_bits = enabled_tc; | |
1868 | } | |
1869 | if (vsi->type == I40E_VSI_SRIOV) { | |
1870 | ctxt->info.mapping_flags |= | |
1871 | cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); | |
1872 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
1873 | ctxt->info.queue_mapping[i] = | |
1874 | cpu_to_le16(vsi->base_queue + i); | |
1875 | } else { | |
1876 | ctxt->info.mapping_flags |= | |
1877 | cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
1878 | ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue); | |
1879 | } | |
1880 | ctxt->info.valid_sections |= cpu_to_le16(sections); | |
1881 | } | |
1882 | ||
6622f5cd JK |
1883 | /** |
1884 | * i40e_addr_sync - Callback for dev_(mc|uc)_sync to add address | |
1885 | * @netdev: the netdevice | |
1886 | * @addr: address to add | |
1887 | * | |
1888 | * Called by __dev_(mc|uc)_sync when an address needs to be added. We call | |
1889 | * __dev_(uc|mc)_sync from .set_rx_mode and guarantee to hold the hash lock. | |
1890 | */ | |
1891 | static int i40e_addr_sync(struct net_device *netdev, const u8 *addr) | |
1892 | { | |
1893 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1894 | struct i40e_vsi *vsi = np->vsi; | |
6622f5cd | 1895 | |
feffdbe4 | 1896 | if (i40e_add_mac_filter(vsi, addr)) |
6622f5cd JK |
1897 | return 0; |
1898 | else | |
1899 | return -ENOMEM; | |
1900 | } | |
1901 | ||
1902 | /** | |
1903 | * i40e_addr_unsync - Callback for dev_(mc|uc)_sync to remove address | |
1904 | * @netdev: the netdevice | |
1905 | * @addr: address to add | |
1906 | * | |
1907 | * Called by __dev_(mc|uc)_sync when an address needs to be removed. We call | |
1908 | * __dev_(uc|mc)_sync from .set_rx_mode and guarantee to hold the hash lock. | |
1909 | */ | |
1910 | static int i40e_addr_unsync(struct net_device *netdev, const u8 *addr) | |
1911 | { | |
1912 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1913 | struct i40e_vsi *vsi = np->vsi; | |
1914 | ||
458867b2 JK |
1915 | /* Under some circumstances, we might receive a request to delete |
1916 | * our own device address from our uc list. Because we store the | |
1917 | * device address in the VSI's MAC/VLAN filter list, we need to ignore | |
1918 | * such requests and not delete our device address from this list. | |
1919 | */ | |
1920 | if (ether_addr_equal(addr, netdev->dev_addr)) | |
1921 | return 0; | |
1922 | ||
feffdbe4 | 1923 | i40e_del_mac_filter(vsi, addr); |
6622f5cd JK |
1924 | |
1925 | return 0; | |
1926 | } | |
1927 | ||
41c445ff JB |
1928 | /** |
1929 | * i40e_set_rx_mode - NDO callback to set the netdev filters | |
1930 | * @netdev: network interface device structure | |
1931 | **/ | |
1932 | static void i40e_set_rx_mode(struct net_device *netdev) | |
1933 | { | |
1934 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
41c445ff | 1935 | struct i40e_vsi *vsi = np->vsi; |
41c445ff | 1936 | |
278e7d0b | 1937 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 1938 | |
6622f5cd JK |
1939 | __dev_uc_sync(netdev, i40e_addr_sync, i40e_addr_unsync); |
1940 | __dev_mc_sync(netdev, i40e_addr_sync, i40e_addr_unsync); | |
41c445ff | 1941 | |
278e7d0b | 1942 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
1943 | |
1944 | /* check for other flag changes */ | |
1945 | if (vsi->current_netdev_flags != vsi->netdev->flags) { | |
1946 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
bfe040c3 | 1947 | set_bit(__I40E_MACVLAN_SYNC_PENDING, vsi->back->state); |
41c445ff JB |
1948 | } |
1949 | } | |
1950 | ||
21659035 | 1951 | /** |
671889e6 | 1952 | * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries |
4a2ce27b | 1953 | * @vsi: Pointer to VSI struct |
21659035 KP |
1954 | * @from: Pointer to list which contains MAC filter entries - changes to |
1955 | * those entries needs to be undone. | |
1956 | * | |
671889e6 | 1957 | * MAC filter entries from this list were slated for deletion. |
21659035 | 1958 | **/ |
671889e6 JK |
1959 | static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi, |
1960 | struct hlist_head *from) | |
21659035 | 1961 | { |
278e7d0b JK |
1962 | struct i40e_mac_filter *f; |
1963 | struct hlist_node *h; | |
1964 | ||
1965 | hlist_for_each_entry_safe(f, h, from, hlist) { | |
1966 | u64 key = i40e_addr_to_hkey(f->macaddr); | |
21659035 | 1967 | |
21659035 | 1968 | /* Move the element back into MAC filter list*/ |
278e7d0b JK |
1969 | hlist_del(&f->hlist); |
1970 | hash_add(vsi->mac_filter_hash, &f->hlist, key); | |
21659035 KP |
1971 | } |
1972 | } | |
1973 | ||
671889e6 JK |
1974 | /** |
1975 | * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries | |
1976 | * @vsi: Pointer to vsi struct | |
1977 | * @from: Pointer to list which contains MAC filter entries - changes to | |
1978 | * those entries needs to be undone. | |
1979 | * | |
1980 | * MAC filter entries from this list were slated for addition. | |
1981 | **/ | |
1982 | static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi, | |
1983 | struct hlist_head *from) | |
1984 | { | |
1985 | struct i40e_new_mac_filter *new; | |
1986 | struct hlist_node *h; | |
1987 | ||
1988 | hlist_for_each_entry_safe(new, h, from, hlist) { | |
1989 | /* We can simply free the wrapper structure */ | |
1990 | hlist_del(&new->hlist); | |
1991 | kfree(new); | |
1992 | } | |
1993 | } | |
1994 | ||
d88d40b0 JK |
1995 | /** |
1996 | * i40e_next_entry - Get the next non-broadcast filter from a list | |
671889e6 | 1997 | * @next: pointer to filter in list |
d88d40b0 JK |
1998 | * |
1999 | * Returns the next non-broadcast filter in the list. Required so that we | |
2000 | * ignore broadcast filters within the list, since these are not handled via | |
2001 | * the normal firmware update path. | |
2002 | */ | |
671889e6 JK |
2003 | static |
2004 | struct i40e_new_mac_filter *i40e_next_filter(struct i40e_new_mac_filter *next) | |
d88d40b0 | 2005 | { |
584a8870 JK |
2006 | hlist_for_each_entry_continue(next, hlist) { |
2007 | if (!is_broadcast_ether_addr(next->f->macaddr)) | |
2008 | return next; | |
d88d40b0 JK |
2009 | } |
2010 | ||
584a8870 | 2011 | return NULL; |
d88d40b0 JK |
2012 | } |
2013 | ||
21659035 | 2014 | /** |
c3c7ea27 MW |
2015 | * i40e_update_filter_state - Update filter state based on return data |
2016 | * from firmware | |
2017 | * @count: Number of filters added | |
2018 | * @add_list: return data from fw | |
f5254429 | 2019 | * @add_head: pointer to first filter in current batch |
21659035 | 2020 | * |
c3c7ea27 MW |
2021 | * MAC filter entries from list were slated to be added to device. Returns |
2022 | * number of successful filters. Note that 0 does NOT mean success! | |
21659035 | 2023 | **/ |
c3c7ea27 MW |
2024 | static int |
2025 | i40e_update_filter_state(int count, | |
2026 | struct i40e_aqc_add_macvlan_element_data *add_list, | |
671889e6 | 2027 | struct i40e_new_mac_filter *add_head) |
21659035 | 2028 | { |
c3c7ea27 MW |
2029 | int retval = 0; |
2030 | int i; | |
21659035 | 2031 | |
ac9e2390 JK |
2032 | for (i = 0; i < count; i++) { |
2033 | /* Always check status of each filter. We don't need to check | |
2034 | * the firmware return status because we pre-set the filter | |
2035 | * status to I40E_AQC_MM_ERR_NO_RES when sending the filter | |
2036 | * request to the adminq. Thus, if it no longer matches then | |
2037 | * we know the filter is active. | |
c3c7ea27 | 2038 | */ |
ac9e2390 | 2039 | if (add_list[i].match_method == I40E_AQC_MM_ERR_NO_RES) { |
c3c7ea27 | 2040 | add_head->state = I40E_FILTER_FAILED; |
ac9e2390 JK |
2041 | } else { |
2042 | add_head->state = I40E_FILTER_ACTIVE; | |
2043 | retval++; | |
c3c7ea27 | 2044 | } |
ac9e2390 | 2045 | |
d88d40b0 JK |
2046 | add_head = i40e_next_filter(add_head); |
2047 | if (!add_head) | |
2048 | break; | |
21659035 | 2049 | } |
ac9e2390 | 2050 | |
c3c7ea27 | 2051 | return retval; |
21659035 KP |
2052 | } |
2053 | ||
00936319 JK |
2054 | /** |
2055 | * i40e_aqc_del_filters - Request firmware to delete a set of filters | |
2056 | * @vsi: ptr to the VSI | |
2057 | * @vsi_name: name to display in messages | |
2058 | * @list: the list of filters to send to firmware | |
2059 | * @num_del: the number of filters to delete | |
2060 | * @retval: Set to -EIO on failure to delete | |
2061 | * | |
2062 | * Send a request to firmware via AdminQ to delete a set of filters. Uses | |
2063 | * *retval instead of a return value so that success does not force ret_val to | |
2064 | * be set to 0. This ensures that a sequence of calls to this function | |
2065 | * preserve the previous value of *retval on successful delete. | |
2066 | */ | |
2067 | static | |
2068 | void i40e_aqc_del_filters(struct i40e_vsi *vsi, const char *vsi_name, | |
2069 | struct i40e_aqc_remove_macvlan_element_data *list, | |
2070 | int num_del, int *retval) | |
2071 | { | |
2072 | struct i40e_hw *hw = &vsi->back->hw; | |
2073 | i40e_status aq_ret; | |
2074 | int aq_err; | |
2075 | ||
2076 | aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, list, num_del, NULL); | |
2077 | aq_err = hw->aq.asq_last_status; | |
2078 | ||
2079 | /* Explicitly ignore and do not report when firmware returns ENOENT */ | |
2080 | if (aq_ret && !(aq_err == I40E_AQ_RC_ENOENT)) { | |
2081 | *retval = -EIO; | |
2082 | dev_info(&vsi->back->pdev->dev, | |
2083 | "ignoring delete macvlan error on %s, err %s, aq_err %s\n", | |
2084 | vsi_name, i40e_stat_str(hw, aq_ret), | |
2085 | i40e_aq_str(hw, aq_err)); | |
2086 | } | |
2087 | } | |
2088 | ||
2089 | /** | |
2090 | * i40e_aqc_add_filters - Request firmware to add a set of filters | |
2091 | * @vsi: ptr to the VSI | |
2092 | * @vsi_name: name to display in messages | |
2093 | * @list: the list of filters to send to firmware | |
2094 | * @add_head: Position in the add hlist | |
2095 | * @num_add: the number of filters to add | |
00936319 JK |
2096 | * |
2097 | * Send a request to firmware via AdminQ to add a chunk of filters. Will set | |
cc6a96a4 AB |
2098 | * __I40E_VSI_OVERFLOW_PROMISC bit in vsi->state if the firmware has run out of |
2099 | * space for more filters. | |
00936319 JK |
2100 | */ |
2101 | static | |
2102 | void i40e_aqc_add_filters(struct i40e_vsi *vsi, const char *vsi_name, | |
2103 | struct i40e_aqc_add_macvlan_element_data *list, | |
671889e6 | 2104 | struct i40e_new_mac_filter *add_head, |
cc6a96a4 | 2105 | int num_add) |
00936319 JK |
2106 | { |
2107 | struct i40e_hw *hw = &vsi->back->hw; | |
00936319 JK |
2108 | int aq_err, fcnt; |
2109 | ||
ac9e2390 | 2110 | i40e_aq_add_macvlan(hw, vsi->seid, list, num_add, NULL); |
00936319 | 2111 | aq_err = hw->aq.asq_last_status; |
ac9e2390 | 2112 | fcnt = i40e_update_filter_state(num_add, list, add_head); |
00936319 JK |
2113 | |
2114 | if (fcnt != num_add) { | |
735aaafa GS |
2115 | if (vsi->type == I40E_VSI_MAIN) { |
2116 | set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); | |
2117 | dev_warn(&vsi->back->pdev->dev, | |
2118 | "Error %s adding RX filters on %s, promiscuous mode forced on\n", | |
2119 | i40e_aq_str(hw, aq_err), vsi_name); | |
2120 | } else if (vsi->type == I40E_VSI_SRIOV || | |
2121 | vsi->type == I40E_VSI_VMDQ1 || | |
2122 | vsi->type == I40E_VSI_VMDQ2) { | |
2123 | dev_warn(&vsi->back->pdev->dev, | |
2124 | "Error %s adding RX filters on %s, please set promiscuous on manually for %s\n", | |
2125 | i40e_aq_str(hw, aq_err), vsi_name, vsi_name); | |
2126 | } else { | |
2127 | dev_warn(&vsi->back->pdev->dev, | |
2128 | "Error %s adding RX filters on %s, incorrect VSI type: %i.\n", | |
2129 | i40e_aq_str(hw, aq_err), vsi_name, vsi->type); | |
2130 | } | |
00936319 JK |
2131 | } |
2132 | } | |
2133 | ||
435c084a JK |
2134 | /** |
2135 | * i40e_aqc_broadcast_filter - Set promiscuous broadcast flags | |
2136 | * @vsi: pointer to the VSI | |
f5254429 | 2137 | * @vsi_name: the VSI name |
435c084a JK |
2138 | * @f: filter data |
2139 | * | |
2140 | * This function sets or clears the promiscuous broadcast flags for VLAN | |
2141 | * filters in order to properly receive broadcast frames. Assumes that only | |
2142 | * broadcast filters are passed. | |
671889e6 JK |
2143 | * |
2144 | * Returns status indicating success or failure; | |
435c084a | 2145 | **/ |
671889e6 JK |
2146 | static i40e_status |
2147 | i40e_aqc_broadcast_filter(struct i40e_vsi *vsi, const char *vsi_name, | |
2148 | struct i40e_mac_filter *f) | |
435c084a JK |
2149 | { |
2150 | bool enable = f->state == I40E_FILTER_NEW; | |
2151 | struct i40e_hw *hw = &vsi->back->hw; | |
2152 | i40e_status aq_ret; | |
2153 | ||
2154 | if (f->vlan == I40E_VLAN_ANY) { | |
2155 | aq_ret = i40e_aq_set_vsi_broadcast(hw, | |
2156 | vsi->seid, | |
2157 | enable, | |
2158 | NULL); | |
2159 | } else { | |
2160 | aq_ret = i40e_aq_set_vsi_bc_promisc_on_vlan(hw, | |
2161 | vsi->seid, | |
2162 | enable, | |
2163 | f->vlan, | |
2164 | NULL); | |
2165 | } | |
2166 | ||
a48350c2 AB |
2167 | if (aq_ret) { |
2168 | set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); | |
435c084a | 2169 | dev_warn(&vsi->back->pdev->dev, |
a48350c2 | 2170 | "Error %s, forcing overflow promiscuous on %s\n", |
435c084a JK |
2171 | i40e_aq_str(hw, hw->aq.asq_last_status), |
2172 | vsi_name); | |
a48350c2 | 2173 | } |
671889e6 JK |
2174 | |
2175 | return aq_ret; | |
435c084a JK |
2176 | } |
2177 | ||
bd5608b3 AB |
2178 | /** |
2179 | * i40e_set_promiscuous - set promiscuous mode | |
2180 | * @pf: board private structure | |
2181 | * @promisc: promisc on or off | |
2182 | * | |
2183 | * There are different ways of setting promiscuous mode on a PF depending on | |
2184 | * what state/environment we're in. This identifies and sets it appropriately. | |
2185 | * Returns 0 on success. | |
2186 | **/ | |
2187 | static int i40e_set_promiscuous(struct i40e_pf *pf, bool promisc) | |
2188 | { | |
2189 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
2190 | struct i40e_hw *hw = &pf->hw; | |
2191 | i40e_status aq_ret; | |
2192 | ||
2193 | if (vsi->type == I40E_VSI_MAIN && | |
2194 | pf->lan_veb != I40E_NO_VEB && | |
2195 | !(pf->flags & I40E_FLAG_MFP_ENABLED)) { | |
2196 | /* set defport ON for Main VSI instead of true promisc | |
2197 | * this way we will get all unicast/multicast and VLAN | |
2198 | * promisc behavior but will not get VF or VMDq traffic | |
2199 | * replicated on the Main VSI. | |
2200 | */ | |
2201 | if (promisc) | |
2202 | aq_ret = i40e_aq_set_default_vsi(hw, | |
2203 | vsi->seid, | |
2204 | NULL); | |
2205 | else | |
2206 | aq_ret = i40e_aq_clear_default_vsi(hw, | |
2207 | vsi->seid, | |
2208 | NULL); | |
2209 | if (aq_ret) { | |
2210 | dev_info(&pf->pdev->dev, | |
2211 | "Set default VSI failed, err %s, aq_err %s\n", | |
2212 | i40e_stat_str(hw, aq_ret), | |
2213 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
2214 | } | |
2215 | } else { | |
2216 | aq_ret = i40e_aq_set_vsi_unicast_promiscuous( | |
2217 | hw, | |
2218 | vsi->seid, | |
2219 | promisc, NULL, | |
2220 | true); | |
2221 | if (aq_ret) { | |
2222 | dev_info(&pf->pdev->dev, | |
2223 | "set unicast promisc failed, err %s, aq_err %s\n", | |
2224 | i40e_stat_str(hw, aq_ret), | |
2225 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
2226 | } | |
2227 | aq_ret = i40e_aq_set_vsi_multicast_promiscuous( | |
2228 | hw, | |
2229 | vsi->seid, | |
2230 | promisc, NULL); | |
2231 | if (aq_ret) { | |
2232 | dev_info(&pf->pdev->dev, | |
2233 | "set multicast promisc failed, err %s, aq_err %s\n", | |
2234 | i40e_stat_str(hw, aq_ret), | |
2235 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
2236 | } | |
2237 | } | |
2238 | ||
2239 | if (!aq_ret) | |
2240 | pf->cur_promisc = promisc; | |
2241 | ||
2242 | return aq_ret; | |
2243 | } | |
2244 | ||
41c445ff JB |
2245 | /** |
2246 | * i40e_sync_vsi_filters - Update the VSI filter list to the HW | |
2247 | * @vsi: ptr to the VSI | |
2248 | * | |
2249 | * Push any outstanding VSI filter changes through the AdminQ. | |
2250 | * | |
2251 | * Returns 0 or error value | |
2252 | **/ | |
17652c63 | 2253 | int i40e_sync_vsi_filters(struct i40e_vsi *vsi) |
41c445ff | 2254 | { |
278e7d0b | 2255 | struct hlist_head tmp_add_list, tmp_del_list; |
671889e6 JK |
2256 | struct i40e_mac_filter *f; |
2257 | struct i40e_new_mac_filter *new, *add_head = NULL; | |
3e25a8f3 | 2258 | struct i40e_hw *hw = &vsi->back->hw; |
cc6a96a4 | 2259 | bool old_overflow, new_overflow; |
38326218 | 2260 | unsigned int failed_filters = 0; |
84f5ca6c | 2261 | unsigned int vlan_filters = 0; |
2d1de828 | 2262 | char vsi_name[16] = "PF"; |
41c445ff | 2263 | int filter_list_len = 0; |
ea02e90b | 2264 | i40e_status aq_ret = 0; |
84f5ca6c | 2265 | u32 changed_flags = 0; |
278e7d0b | 2266 | struct hlist_node *h; |
41c445ff JB |
2267 | struct i40e_pf *pf; |
2268 | int num_add = 0; | |
2269 | int num_del = 0; | |
84f5ca6c | 2270 | int retval = 0; |
41c445ff | 2271 | u16 cmd_flags; |
c3c7ea27 | 2272 | int list_size; |
278e7d0b | 2273 | int bkt; |
41c445ff JB |
2274 | |
2275 | /* empty array typed pointers, kcalloc later */ | |
2276 | struct i40e_aqc_add_macvlan_element_data *add_list; | |
2277 | struct i40e_aqc_remove_macvlan_element_data *del_list; | |
2278 | ||
0da36b97 | 2279 | while (test_and_set_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state)) |
41c445ff JB |
2280 | usleep_range(1000, 2000); |
2281 | pf = vsi->back; | |
2282 | ||
cc6a96a4 AB |
2283 | old_overflow = test_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
2284 | ||
41c445ff JB |
2285 | if (vsi->netdev) { |
2286 | changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags; | |
2287 | vsi->current_netdev_flags = vsi->netdev->flags; | |
2288 | } | |
2289 | ||
278e7d0b JK |
2290 | INIT_HLIST_HEAD(&tmp_add_list); |
2291 | INIT_HLIST_HEAD(&tmp_del_list); | |
21659035 | 2292 | |
2d1de828 SN |
2293 | if (vsi->type == I40E_VSI_SRIOV) |
2294 | snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id); | |
2295 | else if (vsi->type != I40E_VSI_MAIN) | |
2296 | snprintf(vsi_name, sizeof(vsi_name) - 1, "vsi %d", vsi->seid); | |
2297 | ||
41c445ff JB |
2298 | if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) { |
2299 | vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED; | |
2300 | ||
278e7d0b | 2301 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
c3c7ea27 | 2302 | /* Create a list of filters to delete. */ |
278e7d0b | 2303 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
c3c7ea27 | 2304 | if (f->state == I40E_FILTER_REMOVE) { |
c3c7ea27 | 2305 | /* Move the element into temporary del_list */ |
278e7d0b JK |
2306 | hash_del(&f->hlist); |
2307 | hlist_add_head(&f->hlist, &tmp_del_list); | |
84f5ca6c AB |
2308 | |
2309 | /* Avoid counting removed filters */ | |
2310 | continue; | |
c3c7ea27 MW |
2311 | } |
2312 | if (f->state == I40E_FILTER_NEW) { | |
671889e6 JK |
2313 | /* Create a temporary i40e_new_mac_filter */ |
2314 | new = kzalloc(sizeof(*new), GFP_ATOMIC); | |
2315 | if (!new) | |
2316 | goto err_no_memory_locked; | |
2317 | ||
2318 | /* Store pointer to the real filter */ | |
2319 | new->f = f; | |
2320 | new->state = f->state; | |
2321 | ||
2322 | /* Add it to the hash list */ | |
2323 | hlist_add_head(&new->hlist, &tmp_add_list); | |
21659035 | 2324 | } |
84f5ca6c | 2325 | |
489a3265 JK |
2326 | /* Count the number of active (current and new) VLAN |
2327 | * filters we have now. Does not count filters which | |
2328 | * are marked for deletion. | |
84f5ca6c AB |
2329 | */ |
2330 | if (f->vlan > 0) | |
2331 | vlan_filters++; | |
84f5ca6c AB |
2332 | } |
2333 | ||
489a3265 JK |
2334 | retval = i40e_correct_mac_vlan_filters(vsi, |
2335 | &tmp_add_list, | |
2336 | &tmp_del_list, | |
2337 | vlan_filters); | |
2338 | if (retval) | |
2339 | goto err_no_memory_locked; | |
84f5ca6c | 2340 | |
278e7d0b | 2341 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 KP |
2342 | } |
2343 | ||
2344 | /* Now process 'del_list' outside the lock */ | |
278e7d0b | 2345 | if (!hlist_empty(&tmp_del_list)) { |
3e25a8f3 | 2346 | filter_list_len = hw->aq.asq_buf_size / |
21659035 | 2347 | sizeof(struct i40e_aqc_remove_macvlan_element_data); |
c3c7ea27 | 2348 | list_size = filter_list_len * |
f1199998 | 2349 | sizeof(struct i40e_aqc_remove_macvlan_element_data); |
c3c7ea27 | 2350 | del_list = kzalloc(list_size, GFP_ATOMIC); |
4a2ce27b JK |
2351 | if (!del_list) |
2352 | goto err_no_memory; | |
21659035 | 2353 | |
278e7d0b | 2354 | hlist_for_each_entry_safe(f, h, &tmp_del_list, hlist) { |
41c445ff JB |
2355 | cmd_flags = 0; |
2356 | ||
435c084a | 2357 | /* handle broadcast filters by updating the broadcast |
d88d40b0 | 2358 | * promiscuous flag and release filter list. |
435c084a JK |
2359 | */ |
2360 | if (is_broadcast_ether_addr(f->macaddr)) { | |
2361 | i40e_aqc_broadcast_filter(vsi, vsi_name, f); | |
2362 | ||
2363 | hlist_del(&f->hlist); | |
2364 | kfree(f); | |
2365 | continue; | |
2366 | } | |
2367 | ||
41c445ff | 2368 | /* add to delete list */ |
9a173901 | 2369 | ether_addr_copy(del_list[num_del].mac_addr, f->macaddr); |
c3c7ea27 MW |
2370 | if (f->vlan == I40E_VLAN_ANY) { |
2371 | del_list[num_del].vlan_tag = 0; | |
a6cb9146 | 2372 | cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; |
c3c7ea27 MW |
2373 | } else { |
2374 | del_list[num_del].vlan_tag = | |
2375 | cpu_to_le16((u16)(f->vlan)); | |
2376 | } | |
41c445ff | 2377 | |
41c445ff JB |
2378 | cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; |
2379 | del_list[num_del].flags = cmd_flags; | |
2380 | num_del++; | |
2381 | ||
41c445ff JB |
2382 | /* flush a full buffer */ |
2383 | if (num_del == filter_list_len) { | |
00936319 JK |
2384 | i40e_aqc_del_filters(vsi, vsi_name, del_list, |
2385 | num_del, &retval); | |
c3c7ea27 | 2386 | memset(del_list, 0, list_size); |
00936319 | 2387 | num_del = 0; |
41c445ff | 2388 | } |
21659035 KP |
2389 | /* Release memory for MAC filter entries which were |
2390 | * synced up with HW. | |
2391 | */ | |
278e7d0b | 2392 | hlist_del(&f->hlist); |
21659035 | 2393 | kfree(f); |
41c445ff | 2394 | } |
21659035 | 2395 | |
41c445ff | 2396 | if (num_del) { |
00936319 JK |
2397 | i40e_aqc_del_filters(vsi, vsi_name, del_list, |
2398 | num_del, &retval); | |
41c445ff JB |
2399 | } |
2400 | ||
2401 | kfree(del_list); | |
2402 | del_list = NULL; | |
21659035 KP |
2403 | } |
2404 | ||
278e7d0b | 2405 | if (!hlist_empty(&tmp_add_list)) { |
c3c7ea27 | 2406 | /* Do all the adds now. */ |
3e25a8f3 | 2407 | filter_list_len = hw->aq.asq_buf_size / |
f1199998 | 2408 | sizeof(struct i40e_aqc_add_macvlan_element_data); |
c3c7ea27 MW |
2409 | list_size = filter_list_len * |
2410 | sizeof(struct i40e_aqc_add_macvlan_element_data); | |
2411 | add_list = kzalloc(list_size, GFP_ATOMIC); | |
4a2ce27b JK |
2412 | if (!add_list) |
2413 | goto err_no_memory; | |
2414 | ||
c3c7ea27 | 2415 | num_add = 0; |
671889e6 | 2416 | hlist_for_each_entry_safe(new, h, &tmp_add_list, hlist) { |
435c084a JK |
2417 | /* handle broadcast filters by updating the broadcast |
2418 | * promiscuous flag instead of adding a MAC filter. | |
2419 | */ | |
671889e6 JK |
2420 | if (is_broadcast_ether_addr(new->f->macaddr)) { |
2421 | if (i40e_aqc_broadcast_filter(vsi, vsi_name, | |
2422 | new->f)) | |
2423 | new->state = I40E_FILTER_FAILED; | |
2424 | else | |
2425 | new->state = I40E_FILTER_ACTIVE; | |
435c084a JK |
2426 | continue; |
2427 | } | |
2428 | ||
41c445ff | 2429 | /* add to add array */ |
c3c7ea27 | 2430 | if (num_add == 0) |
671889e6 | 2431 | add_head = new; |
c3c7ea27 | 2432 | cmd_flags = 0; |
671889e6 JK |
2433 | ether_addr_copy(add_list[num_add].mac_addr, |
2434 | new->f->macaddr); | |
2435 | if (new->f->vlan == I40E_VLAN_ANY) { | |
c3c7ea27 MW |
2436 | add_list[num_add].vlan_tag = 0; |
2437 | cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; | |
2438 | } else { | |
2439 | add_list[num_add].vlan_tag = | |
671889e6 | 2440 | cpu_to_le16((u16)(new->f->vlan)); |
c3c7ea27 | 2441 | } |
41c445ff | 2442 | add_list[num_add].queue_number = 0; |
ac9e2390 | 2443 | /* set invalid match method for later detection */ |
0266ac45 | 2444 | add_list[num_add].match_method = I40E_AQC_MM_ERR_NO_RES; |
41c445ff | 2445 | cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; |
41c445ff JB |
2446 | add_list[num_add].flags = cpu_to_le16(cmd_flags); |
2447 | num_add++; | |
2448 | ||
2449 | /* flush a full buffer */ | |
2450 | if (num_add == filter_list_len) { | |
00936319 | 2451 | i40e_aqc_add_filters(vsi, vsi_name, add_list, |
cc6a96a4 | 2452 | add_head, num_add); |
c3c7ea27 | 2453 | memset(add_list, 0, list_size); |
41c445ff | 2454 | num_add = 0; |
41c445ff JB |
2455 | } |
2456 | } | |
2457 | if (num_add) { | |
00936319 | 2458 | i40e_aqc_add_filters(vsi, vsi_name, add_list, add_head, |
cc6a96a4 | 2459 | num_add); |
41c445ff | 2460 | } |
c3c7ea27 MW |
2461 | /* Now move all of the filters from the temp add list back to |
2462 | * the VSI's list. | |
2463 | */ | |
278e7d0b | 2464 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
671889e6 JK |
2465 | hlist_for_each_entry_safe(new, h, &tmp_add_list, hlist) { |
2466 | /* Only update the state if we're still NEW */ | |
2467 | if (new->f->state == I40E_FILTER_NEW) | |
2468 | new->f->state = new->state; | |
2469 | hlist_del(&new->hlist); | |
2470 | kfree(new); | |
c3c7ea27 | 2471 | } |
278e7d0b | 2472 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
2473 | kfree(add_list); |
2474 | add_list = NULL; | |
c3c7ea27 | 2475 | } |
41c445ff | 2476 | |
38326218 JK |
2477 | /* Determine the number of active and failed filters. */ |
2478 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
2479 | vsi->active_filters = 0; | |
2480 | hash_for_each(vsi->mac_filter_hash, bkt, f, hlist) { | |
2481 | if (f->state == I40E_FILTER_ACTIVE) | |
2482 | vsi->active_filters++; | |
2483 | else if (f->state == I40E_FILTER_FAILED) | |
2484 | failed_filters++; | |
2485 | } | |
2486 | spin_unlock_bh(&vsi->mac_filter_hash_lock); | |
2487 | ||
38326218 JK |
2488 | /* Check if we are able to exit overflow promiscuous mode. We can |
2489 | * safely exit if we didn't just enter, we no longer have any failed | |
2490 | * filters, and we have reduced filters below the threshold value. | |
2491 | */ | |
cc6a96a4 AB |
2492 | if (old_overflow && !failed_filters && |
2493 | vsi->active_filters < vsi->promisc_threshold) { | |
38326218 JK |
2494 | dev_info(&pf->pdev->dev, |
2495 | "filter logjam cleared on %s, leaving overflow promiscuous mode\n", | |
2496 | vsi_name); | |
0da36b97 | 2497 | clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
38326218 | 2498 | vsi->promisc_threshold = 0; |
41c445ff JB |
2499 | } |
2500 | ||
a856b5cb ASJ |
2501 | /* if the VF is not trusted do not do promisc */ |
2502 | if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) { | |
0da36b97 | 2503 | clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
a856b5cb ASJ |
2504 | goto out; |
2505 | } | |
2506 | ||
cc6a96a4 AB |
2507 | new_overflow = test_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
2508 | ||
2509 | /* If we are entering overflow promiscuous, we need to calculate a new | |
2510 | * threshold for when we are safe to exit | |
2511 | */ | |
2512 | if (!old_overflow && new_overflow) | |
2513 | vsi->promisc_threshold = (vsi->active_filters * 3) / 4; | |
2514 | ||
41c445ff JB |
2515 | /* check for changes in promiscuous modes */ |
2516 | if (changed_flags & IFF_ALLMULTI) { | |
2517 | bool cur_multipromisc; | |
6995b36c | 2518 | |
41c445ff | 2519 | cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI); |
ea02e90b MW |
2520 | aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw, |
2521 | vsi->seid, | |
2522 | cur_multipromisc, | |
2523 | NULL); | |
2524 | if (aq_ret) { | |
2525 | retval = i40e_aq_rc_to_posix(aq_ret, | |
3e25a8f3 | 2526 | hw->aq.asq_last_status); |
41c445ff | 2527 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
2528 | "set multi promisc failed on %s, err %s aq_err %s\n", |
2529 | vsi_name, | |
3e25a8f3 MW |
2530 | i40e_stat_str(hw, aq_ret), |
2531 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
ea02e90b | 2532 | } |
41c445ff | 2533 | } |
e5887239 | 2534 | |
cc6a96a4 | 2535 | if ((changed_flags & IFF_PROMISC) || old_overflow != new_overflow) { |
41c445ff | 2536 | bool cur_promisc; |
6995b36c | 2537 | |
41c445ff | 2538 | cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) || |
cc6a96a4 | 2539 | new_overflow); |
bd5608b3 | 2540 | aq_ret = i40e_set_promiscuous(pf, cur_promisc); |
ea02e90b MW |
2541 | if (aq_ret) { |
2542 | retval = i40e_aq_rc_to_posix(aq_ret, | |
bd5608b3 | 2543 | hw->aq.asq_last_status); |
1a10370a | 2544 | dev_info(&pf->pdev->dev, |
bd5608b3 AB |
2545 | "Setting promiscuous %s failed on %s, err %s aq_err %s\n", |
2546 | cur_promisc ? "on" : "off", | |
2547 | vsi_name, | |
2548 | i40e_stat_str(hw, aq_ret), | |
2549 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
ea02e90b | 2550 | } |
41c445ff | 2551 | } |
ea02e90b | 2552 | out: |
2818ccd9 JB |
2553 | /* if something went wrong then set the changed flag so we try again */ |
2554 | if (retval) | |
2555 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
2556 | ||
0da36b97 | 2557 | clear_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state); |
ea02e90b | 2558 | return retval; |
4a2ce27b JK |
2559 | |
2560 | err_no_memory: | |
2561 | /* Restore elements on the temporary add and delete lists */ | |
2562 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
84f5ca6c | 2563 | err_no_memory_locked: |
671889e6 JK |
2564 | i40e_undo_del_filter_entries(vsi, &tmp_del_list); |
2565 | i40e_undo_add_filter_entries(vsi, &tmp_add_list); | |
4a2ce27b JK |
2566 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
2567 | ||
2568 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
0da36b97 | 2569 | clear_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state); |
4a2ce27b | 2570 | return -ENOMEM; |
41c445ff JB |
2571 | } |
2572 | ||
2573 | /** | |
2574 | * i40e_sync_filters_subtask - Sync the VSI filter list with HW | |
2575 | * @pf: board private structure | |
2576 | **/ | |
2577 | static void i40e_sync_filters_subtask(struct i40e_pf *pf) | |
2578 | { | |
2579 | int v; | |
2580 | ||
bfe040c3 JK |
2581 | if (!pf) |
2582 | return; | |
2583 | if (!test_and_clear_bit(__I40E_MACVLAN_SYNC_PENDING, pf->state)) | |
41c445ff | 2584 | return; |
41c445ff | 2585 | |
505682cd | 2586 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff | 2587 | if (pf->vsi[v] && |
17652c63 JB |
2588 | (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) { |
2589 | int ret = i40e_sync_vsi_filters(pf->vsi[v]); | |
2590 | ||
2591 | if (ret) { | |
2592 | /* come back and try again later */ | |
bfe040c3 JK |
2593 | set_bit(__I40E_MACVLAN_SYNC_PENDING, |
2594 | pf->state); | |
17652c63 JB |
2595 | break; |
2596 | } | |
2597 | } | |
41c445ff JB |
2598 | } |
2599 | } | |
2600 | ||
0c8493d9 BT |
2601 | /** |
2602 | * i40e_max_xdp_frame_size - returns the maximum allowed frame size for XDP | |
2603 | * @vsi: the vsi | |
2604 | **/ | |
2605 | static int i40e_max_xdp_frame_size(struct i40e_vsi *vsi) | |
2606 | { | |
2607 | if (PAGE_SIZE >= 8192 || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) | |
2608 | return I40E_RXBUFFER_2048; | |
2609 | else | |
2610 | return I40E_RXBUFFER_3072; | |
2611 | } | |
2612 | ||
41c445ff JB |
2613 | /** |
2614 | * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit | |
2615 | * @netdev: network interface device structure | |
2616 | * @new_mtu: new value for maximum frame size | |
2617 | * | |
2618 | * Returns 0 on success, negative on failure | |
2619 | **/ | |
2620 | static int i40e_change_mtu(struct net_device *netdev, int new_mtu) | |
2621 | { | |
2622 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
41c445ff | 2623 | struct i40e_vsi *vsi = np->vsi; |
0ef2d5af | 2624 | struct i40e_pf *pf = vsi->back; |
41c445ff | 2625 | |
0c8493d9 BT |
2626 | if (i40e_enabled_xdp_vsi(vsi)) { |
2627 | int frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
2628 | ||
2629 | if (frame_size > i40e_max_xdp_frame_size(vsi)) | |
2630 | return -EINVAL; | |
2631 | } | |
2632 | ||
41c445ff JB |
2633 | netdev_info(netdev, "changing MTU from %d to %d\n", |
2634 | netdev->mtu, new_mtu); | |
2635 | netdev->mtu = new_mtu; | |
2636 | if (netif_running(netdev)) | |
2637 | i40e_vsi_reinit_locked(vsi); | |
5f76a704 JK |
2638 | set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state); |
2639 | set_bit(__I40E_CLIENT_L2_CHANGE, pf->state); | |
41c445ff JB |
2640 | return 0; |
2641 | } | |
2642 | ||
beb0dff1 JK |
2643 | /** |
2644 | * i40e_ioctl - Access the hwtstamp interface | |
2645 | * @netdev: network interface device structure | |
2646 | * @ifr: interface request data | |
2647 | * @cmd: ioctl command | |
2648 | **/ | |
2649 | int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
2650 | { | |
2651 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2652 | struct i40e_pf *pf = np->vsi->back; | |
2653 | ||
2654 | switch (cmd) { | |
2655 | case SIOCGHWTSTAMP: | |
2656 | return i40e_ptp_get_ts_config(pf, ifr); | |
2657 | case SIOCSHWTSTAMP: | |
2658 | return i40e_ptp_set_ts_config(pf, ifr); | |
2659 | default: | |
2660 | return -EOPNOTSUPP; | |
2661 | } | |
2662 | } | |
2663 | ||
41c445ff JB |
2664 | /** |
2665 | * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI | |
2666 | * @vsi: the vsi being adjusted | |
2667 | **/ | |
2668 | void i40e_vlan_stripping_enable(struct i40e_vsi *vsi) | |
2669 | { | |
2670 | struct i40e_vsi_context ctxt; | |
2671 | i40e_status ret; | |
2672 | ||
bfb0ebed NN |
2673 | /* Don't modify stripping options if a port VLAN is active */ |
2674 | if (vsi->info.pvid) | |
2675 | return; | |
2676 | ||
41c445ff JB |
2677 | if ((vsi->info.valid_sections & |
2678 | cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && | |
2679 | ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0)) | |
2680 | return; /* already enabled */ | |
2681 | ||
2682 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2683 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | | |
2684 | I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; | |
2685 | ||
2686 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2687 | ctxt.info = vsi->info; |
41c445ff JB |
2688 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2689 | if (ret) { | |
2690 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
2691 | "update vlan stripping failed, err %s aq_err %s\n", |
2692 | i40e_stat_str(&vsi->back->hw, ret), | |
2693 | i40e_aq_str(&vsi->back->hw, | |
2694 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
2695 | } |
2696 | } | |
2697 | ||
2698 | /** | |
2699 | * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI | |
2700 | * @vsi: the vsi being adjusted | |
2701 | **/ | |
2702 | void i40e_vlan_stripping_disable(struct i40e_vsi *vsi) | |
2703 | { | |
2704 | struct i40e_vsi_context ctxt; | |
2705 | i40e_status ret; | |
2706 | ||
bfb0ebed NN |
2707 | /* Don't modify stripping options if a port VLAN is active */ |
2708 | if (vsi->info.pvid) | |
2709 | return; | |
2710 | ||
41c445ff JB |
2711 | if ((vsi->info.valid_sections & |
2712 | cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && | |
2713 | ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) == | |
2714 | I40E_AQ_VSI_PVLAN_EMOD_MASK)) | |
2715 | return; /* already disabled */ | |
2716 | ||
2717 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2718 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | | |
2719 | I40E_AQ_VSI_PVLAN_EMOD_NOTHING; | |
2720 | ||
2721 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2722 | ctxt.info = vsi->info; |
41c445ff JB |
2723 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2724 | if (ret) { | |
2725 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
2726 | "update vlan stripping failed, err %s aq_err %s\n", |
2727 | i40e_stat_str(&vsi->back->hw, ret), | |
2728 | i40e_aq_str(&vsi->back->hw, | |
2729 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
2730 | } |
2731 | } | |
2732 | ||
41c445ff | 2733 | /** |
490a4ad3 | 2734 | * i40e_add_vlan_all_mac - Add a MAC/VLAN filter for each existing MAC address |
41c445ff JB |
2735 | * @vsi: the vsi being configured |
2736 | * @vid: vlan id to be added (0 = untagged only , -1 = any) | |
490a4ad3 JK |
2737 | * |
2738 | * This is a helper function for adding a new MAC/VLAN filter with the | |
2739 | * specified VLAN for each existing MAC address already in the hash table. | |
2740 | * This function does *not* perform any accounting to update filters based on | |
2741 | * VLAN mode. | |
2742 | * | |
2743 | * NOTE: this function expects to be called while under the | |
2744 | * mac_filter_hash_lock | |
41c445ff | 2745 | **/ |
9af52f60 | 2746 | int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid) |
41c445ff | 2747 | { |
490a4ad3 | 2748 | struct i40e_mac_filter *f, *add_f; |
278e7d0b JK |
2749 | struct hlist_node *h; |
2750 | int bkt; | |
41c445ff | 2751 | |
278e7d0b | 2752 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
57b341d6 JK |
2753 | if (f->state == I40E_FILTER_REMOVE) |
2754 | continue; | |
1bc87e80 | 2755 | add_f = i40e_add_filter(vsi, f->macaddr, vid); |
41c445ff JB |
2756 | if (!add_f) { |
2757 | dev_info(&vsi->back->pdev->dev, | |
2758 | "Could not add vlan filter %d for %pM\n", | |
2759 | vid, f->macaddr); | |
2760 | return -ENOMEM; | |
2761 | } | |
2762 | } | |
2763 | ||
490a4ad3 JK |
2764 | return 0; |
2765 | } | |
2766 | ||
2767 | /** | |
2768 | * i40e_vsi_add_vlan - Add VSI membership for given VLAN | |
2769 | * @vsi: the VSI being configured | |
f94484b7 | 2770 | * @vid: VLAN id to be added |
490a4ad3 | 2771 | **/ |
f94484b7 | 2772 | int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid) |
490a4ad3 | 2773 | { |
489a3265 | 2774 | int err; |
490a4ad3 | 2775 | |
fcf6cfc8 | 2776 | if (vsi->info.pvid) |
f94484b7 JK |
2777 | return -EINVAL; |
2778 | ||
fcf6cfc8 JK |
2779 | /* The network stack will attempt to add VID=0, with the intention to |
2780 | * receive priority tagged packets with a VLAN of 0. Our HW receives | |
2781 | * these packets by default when configured to receive untagged | |
2782 | * packets, so we don't need to add a filter for this case. | |
2783 | * Additionally, HW interprets adding a VID=0 filter as meaning to | |
2784 | * receive *only* tagged traffic and stops receiving untagged traffic. | |
2785 | * Thus, we do not want to actually add a filter for VID=0 | |
2786 | */ | |
2787 | if (!vid) | |
2788 | return 0; | |
2789 | ||
490a4ad3 JK |
2790 | /* Locked once because all functions invoked below iterates list*/ |
2791 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
490a4ad3 | 2792 | err = i40e_add_vlan_all_mac(vsi, vid); |
278e7d0b | 2793 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
489a3265 JK |
2794 | if (err) |
2795 | return err; | |
21659035 | 2796 | |
0e4425ed JB |
2797 | /* schedule our worker thread which will take care of |
2798 | * applying the new filter changes | |
2799 | */ | |
2800 | i40e_service_event_schedule(vsi->back); | |
2801 | return 0; | |
41c445ff JB |
2802 | } |
2803 | ||
2804 | /** | |
490a4ad3 | 2805 | * i40e_rm_vlan_all_mac - Remove MAC/VLAN pair for all MAC with the given VLAN |
41c445ff JB |
2806 | * @vsi: the vsi being configured |
2807 | * @vid: vlan id to be removed (0 = untagged only , -1 = any) | |
490a4ad3 JK |
2808 | * |
2809 | * This function should be used to remove all VLAN filters which match the | |
2810 | * given VID. It does not schedule the service event and does not take the | |
2811 | * mac_filter_hash_lock so it may be combined with other operations under | |
2812 | * a single invocation of the mac_filter_hash_lock. | |
2813 | * | |
2814 | * NOTE: this function expects to be called while under the | |
2815 | * mac_filter_hash_lock | |
2816 | */ | |
9af52f60 | 2817 | void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid) |
41c445ff | 2818 | { |
84f5ca6c | 2819 | struct i40e_mac_filter *f; |
278e7d0b | 2820 | struct hlist_node *h; |
278e7d0b | 2821 | int bkt; |
41c445ff | 2822 | |
278e7d0b | 2823 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
290d2557 JK |
2824 | if (f->vlan == vid) |
2825 | __i40e_del_filter(vsi, f); | |
2826 | } | |
490a4ad3 | 2827 | } |
41c445ff | 2828 | |
490a4ad3 JK |
2829 | /** |
2830 | * i40e_vsi_kill_vlan - Remove VSI membership for given VLAN | |
2831 | * @vsi: the VSI being configured | |
f94484b7 | 2832 | * @vid: VLAN id to be removed |
490a4ad3 | 2833 | **/ |
f94484b7 | 2834 | void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid) |
490a4ad3 | 2835 | { |
f94484b7 JK |
2836 | if (!vid || vsi->info.pvid) |
2837 | return; | |
2838 | ||
490a4ad3 JK |
2839 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
2840 | i40e_rm_vlan_all_mac(vsi, vid); | |
278e7d0b | 2841 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 2842 | |
0e4425ed JB |
2843 | /* schedule our worker thread which will take care of |
2844 | * applying the new filter changes | |
2845 | */ | |
2846 | i40e_service_event_schedule(vsi->back); | |
41c445ff JB |
2847 | } |
2848 | ||
2849 | /** | |
2850 | * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload | |
2851 | * @netdev: network interface to be adjusted | |
f5254429 | 2852 | * @proto: unused protocol value |
41c445ff | 2853 | * @vid: vlan id to be added |
078b5876 JB |
2854 | * |
2855 | * net_device_ops implementation for adding vlan ids | |
41c445ff JB |
2856 | **/ |
2857 | static int i40e_vlan_rx_add_vid(struct net_device *netdev, | |
2858 | __always_unused __be16 proto, u16 vid) | |
2859 | { | |
2860 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2861 | struct i40e_vsi *vsi = np->vsi; | |
078b5876 | 2862 | int ret = 0; |
41c445ff | 2863 | |
6a112785 | 2864 | if (vid >= VLAN_N_VID) |
078b5876 JB |
2865 | return -EINVAL; |
2866 | ||
fcf6cfc8 | 2867 | ret = i40e_vsi_add_vlan(vsi, vid); |
6a112785 | 2868 | if (!ret) |
078b5876 | 2869 | set_bit(vid, vsi->active_vlans); |
41c445ff | 2870 | |
078b5876 | 2871 | return ret; |
41c445ff JB |
2872 | } |
2873 | ||
27392e57 PJ |
2874 | /** |
2875 | * i40e_vlan_rx_add_vid_up - Add a vlan id filter to HW offload in UP path | |
2876 | * @netdev: network interface to be adjusted | |
2877 | * @proto: unused protocol value | |
2878 | * @vid: vlan id to be added | |
2879 | **/ | |
2880 | static void i40e_vlan_rx_add_vid_up(struct net_device *netdev, | |
2881 | __always_unused __be16 proto, u16 vid) | |
2882 | { | |
2883 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2884 | struct i40e_vsi *vsi = np->vsi; | |
2885 | ||
2886 | if (vid >= VLAN_N_VID) | |
2887 | return; | |
2888 | set_bit(vid, vsi->active_vlans); | |
2889 | } | |
2890 | ||
41c445ff JB |
2891 | /** |
2892 | * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload | |
2893 | * @netdev: network interface to be adjusted | |
f5254429 | 2894 | * @proto: unused protocol value |
41c445ff | 2895 | * @vid: vlan id to be removed |
078b5876 | 2896 | * |
fdfd943e | 2897 | * net_device_ops implementation for removing vlan ids |
41c445ff JB |
2898 | **/ |
2899 | static int i40e_vlan_rx_kill_vid(struct net_device *netdev, | |
2900 | __always_unused __be16 proto, u16 vid) | |
2901 | { | |
2902 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2903 | struct i40e_vsi *vsi = np->vsi; | |
2904 | ||
41c445ff JB |
2905 | /* return code is ignored as there is nothing a user |
2906 | * can do about failure to remove and a log message was | |
078b5876 | 2907 | * already printed from the other function |
41c445ff JB |
2908 | */ |
2909 | i40e_vsi_kill_vlan(vsi, vid); | |
2910 | ||
2911 | clear_bit(vid, vsi->active_vlans); | |
078b5876 | 2912 | |
41c445ff JB |
2913 | return 0; |
2914 | } | |
2915 | ||
2916 | /** | |
2917 | * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up | |
2918 | * @vsi: the vsi being brought back up | |
2919 | **/ | |
2920 | static void i40e_restore_vlan(struct i40e_vsi *vsi) | |
2921 | { | |
2922 | u16 vid; | |
2923 | ||
2924 | if (!vsi->netdev) | |
2925 | return; | |
2926 | ||
2972b007 JK |
2927 | if (vsi->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) |
2928 | i40e_vlan_stripping_enable(vsi); | |
2929 | else | |
2930 | i40e_vlan_stripping_disable(vsi); | |
41c445ff JB |
2931 | |
2932 | for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID) | |
27392e57 PJ |
2933 | i40e_vlan_rx_add_vid_up(vsi->netdev, htons(ETH_P_8021Q), |
2934 | vid); | |
41c445ff JB |
2935 | } |
2936 | ||
2937 | /** | |
2938 | * i40e_vsi_add_pvid - Add pvid for the VSI | |
2939 | * @vsi: the vsi being adjusted | |
2940 | * @vid: the vlan id to set as a PVID | |
2941 | **/ | |
dcae29be | 2942 | int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid) |
41c445ff JB |
2943 | { |
2944 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 2945 | i40e_status ret; |
41c445ff JB |
2946 | |
2947 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2948 | vsi->info.pvid = cpu_to_le16(vid); | |
6c12fcbf GR |
2949 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED | |
2950 | I40E_AQ_VSI_PVLAN_INSERT_PVID | | |
b774c7dd | 2951 | I40E_AQ_VSI_PVLAN_EMOD_STR; |
41c445ff JB |
2952 | |
2953 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2954 | ctxt.info = vsi->info; |
f1c7e72e SN |
2955 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2956 | if (ret) { | |
41c445ff | 2957 | dev_info(&vsi->back->pdev->dev, |
f1c7e72e SN |
2958 | "add pvid failed, err %s aq_err %s\n", |
2959 | i40e_stat_str(&vsi->back->hw, ret), | |
2960 | i40e_aq_str(&vsi->back->hw, | |
2961 | vsi->back->hw.aq.asq_last_status)); | |
dcae29be | 2962 | return -ENOENT; |
41c445ff JB |
2963 | } |
2964 | ||
dcae29be | 2965 | return 0; |
41c445ff JB |
2966 | } |
2967 | ||
2968 | /** | |
2969 | * i40e_vsi_remove_pvid - Remove the pvid from the VSI | |
2970 | * @vsi: the vsi being adjusted | |
2971 | * | |
2972 | * Just use the vlan_rx_register() service to put it back to normal | |
2973 | **/ | |
2974 | void i40e_vsi_remove_pvid(struct i40e_vsi *vsi) | |
2975 | { | |
6c12fcbf GR |
2976 | i40e_vlan_stripping_disable(vsi); |
2977 | ||
41c445ff | 2978 | vsi->info.pvid = 0; |
41c445ff JB |
2979 | } |
2980 | ||
2981 | /** | |
2982 | * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources | |
2983 | * @vsi: ptr to the VSI | |
2984 | * | |
2985 | * If this function returns with an error, then it's possible one or | |
2986 | * more of the rings is populated (while the rest are not). It is the | |
2987 | * callers duty to clean those orphaned rings. | |
2988 | * | |
2989 | * Return 0 on success, negative on failure | |
2990 | **/ | |
2991 | static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi) | |
2992 | { | |
2993 | int i, err = 0; | |
2994 | ||
2995 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 2996 | err = i40e_setup_tx_descriptors(vsi->tx_rings[i]); |
41c445ff | 2997 | |
74608d17 BT |
2998 | if (!i40e_enabled_xdp_vsi(vsi)) |
2999 | return err; | |
3000 | ||
3001 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
3002 | err = i40e_setup_tx_descriptors(vsi->xdp_rings[i]); | |
3003 | ||
41c445ff JB |
3004 | return err; |
3005 | } | |
3006 | ||
3007 | /** | |
3008 | * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues | |
3009 | * @vsi: ptr to the VSI | |
3010 | * | |
3011 | * Free VSI's transmit software resources | |
3012 | **/ | |
3013 | static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi) | |
3014 | { | |
3015 | int i; | |
3016 | ||
74608d17 BT |
3017 | if (vsi->tx_rings) { |
3018 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
3019 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) | |
3020 | i40e_free_tx_resources(vsi->tx_rings[i]); | |
3021 | } | |
8e9dca53 | 3022 | |
74608d17 BT |
3023 | if (vsi->xdp_rings) { |
3024 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
3025 | if (vsi->xdp_rings[i] && vsi->xdp_rings[i]->desc) | |
3026 | i40e_free_tx_resources(vsi->xdp_rings[i]); | |
3027 | } | |
41c445ff JB |
3028 | } |
3029 | ||
3030 | /** | |
3031 | * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources | |
3032 | * @vsi: ptr to the VSI | |
3033 | * | |
3034 | * If this function returns with an error, then it's possible one or | |
3035 | * more of the rings is populated (while the rest are not). It is the | |
3036 | * callers duty to clean those orphaned rings. | |
3037 | * | |
3038 | * Return 0 on success, negative on failure | |
3039 | **/ | |
3040 | static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi) | |
3041 | { | |
3042 | int i, err = 0; | |
3043 | ||
3044 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 3045 | err = i40e_setup_rx_descriptors(vsi->rx_rings[i]); |
41c445ff JB |
3046 | return err; |
3047 | } | |
3048 | ||
3049 | /** | |
3050 | * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues | |
3051 | * @vsi: ptr to the VSI | |
3052 | * | |
3053 | * Free all receive software resources | |
3054 | **/ | |
3055 | static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi) | |
3056 | { | |
3057 | int i; | |
3058 | ||
8e9dca53 GR |
3059 | if (!vsi->rx_rings) |
3060 | return; | |
3061 | ||
41c445ff | 3062 | for (i = 0; i < vsi->num_queue_pairs; i++) |
8e9dca53 | 3063 | if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc) |
9f65e15b | 3064 | i40e_free_rx_resources(vsi->rx_rings[i]); |
41c445ff JB |
3065 | } |
3066 | ||
3ffa037d NP |
3067 | /** |
3068 | * i40e_config_xps_tx_ring - Configure XPS for a Tx ring | |
3069 | * @ring: The Tx ring to configure | |
3070 | * | |
3071 | * This enables/disables XPS for a given Tx descriptor ring | |
3072 | * based on the TCs enabled for the VSI that ring belongs to. | |
3073 | **/ | |
3074 | static void i40e_config_xps_tx_ring(struct i40e_ring *ring) | |
3075 | { | |
be664cbe | 3076 | int cpu; |
3ffa037d | 3077 | |
8f88b303 | 3078 | if (!ring->q_vector || !ring->netdev || ring->ch) |
9a660eea JB |
3079 | return; |
3080 | ||
6f853d4f JK |
3081 | /* We only initialize XPS once, so as not to overwrite user settings */ |
3082 | if (test_and_set_bit(__I40E_TX_XPS_INIT_DONE, ring->state)) | |
3083 | return; | |
0e4425ed | 3084 | |
6f853d4f JK |
3085 | cpu = cpumask_local_spread(ring->q_vector->v_idx, -1); |
3086 | netif_set_xps_queue(ring->netdev, get_cpu_mask(cpu), | |
3087 | ring->queue_index); | |
3ffa037d NP |
3088 | } |
3089 | ||
b83f28e1 BT |
3090 | /** |
3091 | * i40e_xsk_umem - Retrieve the AF_XDP ZC if XDP and ZC is enabled | |
3092 | * @ring: The Tx or Rx ring | |
3093 | * | |
3094 | * Returns the UMEM or NULL. | |
3095 | **/ | |
3096 | static struct xdp_umem *i40e_xsk_umem(struct i40e_ring *ring) | |
3097 | { | |
3098 | bool xdp_on = i40e_enabled_xdp_vsi(ring->vsi); | |
3099 | int qid = ring->queue_index; | |
3100 | ||
3101 | if (ring_is_xdp(ring)) | |
3102 | qid -= ring->vsi->alloc_queue_pairs; | |
3103 | ||
44ddd4f1 | 3104 | if (!xdp_on || !test_bit(qid, ring->vsi->af_xdp_zc_qps)) |
b83f28e1 BT |
3105 | return NULL; |
3106 | ||
3107 | return xdp_get_umem_from_qid(ring->vsi->netdev, qid); | |
3108 | } | |
3109 | ||
41c445ff JB |
3110 | /** |
3111 | * i40e_configure_tx_ring - Configure a transmit ring context and rest | |
3112 | * @ring: The Tx ring to configure | |
3113 | * | |
3114 | * Configure the Tx descriptor ring in the HMC context. | |
3115 | **/ | |
3116 | static int i40e_configure_tx_ring(struct i40e_ring *ring) | |
3117 | { | |
3118 | struct i40e_vsi *vsi = ring->vsi; | |
3119 | u16 pf_q = vsi->base_queue + ring->queue_index; | |
3120 | struct i40e_hw *hw = &vsi->back->hw; | |
3121 | struct i40e_hmc_obj_txq tx_ctx; | |
3122 | i40e_status err = 0; | |
3123 | u32 qtx_ctl = 0; | |
3124 | ||
1328dcdd MK |
3125 | if (ring_is_xdp(ring)) |
3126 | ring->xsk_umem = i40e_xsk_umem(ring); | |
3127 | ||
41c445ff | 3128 | /* some ATR related tx ring init */ |
60ea5f83 | 3129 | if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) { |
41c445ff JB |
3130 | ring->atr_sample_rate = vsi->back->atr_sample_rate; |
3131 | ring->atr_count = 0; | |
3132 | } else { | |
3133 | ring->atr_sample_rate = 0; | |
3134 | } | |
3135 | ||
3ffa037d NP |
3136 | /* configure XPS */ |
3137 | i40e_config_xps_tx_ring(ring); | |
41c445ff JB |
3138 | |
3139 | /* clear the context structure first */ | |
3140 | memset(&tx_ctx, 0, sizeof(tx_ctx)); | |
3141 | ||
3142 | tx_ctx.new_context = 1; | |
3143 | tx_ctx.base = (ring->dma / 128); | |
3144 | tx_ctx.qlen = ring->count; | |
60ea5f83 JB |
3145 | tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED | |
3146 | I40E_FLAG_FD_ATR_ENABLED)); | |
beb0dff1 | 3147 | tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP); |
1943d8ba JB |
3148 | /* FDIR VSI tx ring can still use RS bit and writebacks */ |
3149 | if (vsi->type != I40E_VSI_FDIR) | |
3150 | tx_ctx.head_wb_ena = 1; | |
3151 | tx_ctx.head_wb_addr = ring->dma + | |
3152 | (ring->count * sizeof(struct i40e_tx_desc)); | |
41c445ff JB |
3153 | |
3154 | /* As part of VSI creation/update, FW allocates certain | |
3155 | * Tx arbitration queue sets for each TC enabled for | |
3156 | * the VSI. The FW returns the handles to these queue | |
3157 | * sets as part of the response buffer to Add VSI, | |
3158 | * Update VSI, etc. AQ commands. It is expected that | |
3159 | * these queue set handles be associated with the Tx | |
3160 | * queues by the driver as part of the TX queue context | |
3161 | * initialization. This has to be done regardless of | |
3162 | * DCB as by default everything is mapped to TC0. | |
3163 | */ | |
8f88b303 AN |
3164 | |
3165 | if (ring->ch) | |
3166 | tx_ctx.rdylist = | |
3167 | le16_to_cpu(ring->ch->info.qs_handle[ring->dcb_tc]); | |
3168 | ||
3169 | else | |
3170 | tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]); | |
3171 | ||
41c445ff JB |
3172 | tx_ctx.rdylist_act = 0; |
3173 | ||
3174 | /* clear the context in the HMC */ | |
3175 | err = i40e_clear_lan_tx_queue_context(hw, pf_q); | |
3176 | if (err) { | |
3177 | dev_info(&vsi->back->pdev->dev, | |
3178 | "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n", | |
3179 | ring->queue_index, pf_q, err); | |
3180 | return -ENOMEM; | |
3181 | } | |
3182 | ||
3183 | /* set the context in the HMC */ | |
3184 | err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx); | |
3185 | if (err) { | |
3186 | dev_info(&vsi->back->pdev->dev, | |
3187 | "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n", | |
3188 | ring->queue_index, pf_q, err); | |
3189 | return -ENOMEM; | |
3190 | } | |
3191 | ||
3192 | /* Now associate this queue with this PCI function */ | |
8f88b303 AN |
3193 | if (ring->ch) { |
3194 | if (ring->ch->type == I40E_VSI_VMDQ2) | |
3195 | qtx_ctl = I40E_QTX_CTL_VM_QUEUE; | |
3196 | else | |
3197 | return -EINVAL; | |
3198 | ||
3199 | qtx_ctl |= (ring->ch->vsi_number << | |
3200 | I40E_QTX_CTL_VFVM_INDX_SHIFT) & | |
3201 | I40E_QTX_CTL_VFVM_INDX_MASK; | |
7a28d885 | 3202 | } else { |
8f88b303 AN |
3203 | if (vsi->type == I40E_VSI_VMDQ2) { |
3204 | qtx_ctl = I40E_QTX_CTL_VM_QUEUE; | |
3205 | qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) & | |
3206 | I40E_QTX_CTL_VFVM_INDX_MASK; | |
3207 | } else { | |
3208 | qtx_ctl = I40E_QTX_CTL_PF_QUEUE; | |
3209 | } | |
7a28d885 MW |
3210 | } |
3211 | ||
13fd9774 SN |
3212 | qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & |
3213 | I40E_QTX_CTL_PF_INDX_MASK); | |
41c445ff JB |
3214 | wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl); |
3215 | i40e_flush(hw); | |
3216 | ||
41c445ff JB |
3217 | /* cache tail off for easier writes later */ |
3218 | ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q); | |
3219 | ||
3220 | return 0; | |
3221 | } | |
3222 | ||
3223 | /** | |
3224 | * i40e_configure_rx_ring - Configure a receive ring context | |
3225 | * @ring: The Rx ring to configure | |
3226 | * | |
3227 | * Configure the Rx descriptor ring in the HMC context. | |
3228 | **/ | |
3229 | static int i40e_configure_rx_ring(struct i40e_ring *ring) | |
3230 | { | |
3231 | struct i40e_vsi *vsi = ring->vsi; | |
3232 | u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len; | |
3233 | u16 pf_q = vsi->base_queue + ring->queue_index; | |
3234 | struct i40e_hw *hw = &vsi->back->hw; | |
3235 | struct i40e_hmc_obj_rxq rx_ctx; | |
3236 | i40e_status err = 0; | |
0a714186 BT |
3237 | bool ok; |
3238 | int ret; | |
41c445ff | 3239 | |
bd6cd4e6 | 3240 | bitmap_zero(ring->state, __I40E_RING_STATE_NBITS); |
41c445ff JB |
3241 | |
3242 | /* clear the context structure first */ | |
3243 | memset(&rx_ctx, 0, sizeof(rx_ctx)); | |
3244 | ||
0a714186 BT |
3245 | if (ring->vsi->type == I40E_VSI_MAIN) |
3246 | xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq); | |
3247 | ||
3248 | ring->xsk_umem = i40e_xsk_umem(ring); | |
3249 | if (ring->xsk_umem) { | |
3250 | ring->rx_buf_len = ring->xsk_umem->chunk_size_nohr - | |
3251 | XDP_PACKET_HEADROOM; | |
3252 | /* For AF_XDP ZC, we disallow packets to span on | |
3253 | * multiple buffers, thus letting us skip that | |
3254 | * handling in the fast-path. | |
3255 | */ | |
3256 | chain_len = 1; | |
3257 | ring->zca.free = i40e_zca_free; | |
3258 | ret = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, | |
3259 | MEM_TYPE_ZERO_COPY, | |
3260 | &ring->zca); | |
3261 | if (ret) | |
3262 | return ret; | |
3263 | dev_info(&vsi->back->pdev->dev, | |
3264 | "Registered XDP mem model MEM_TYPE_ZERO_COPY on Rx ring %d\n", | |
3265 | ring->queue_index); | |
3266 | ||
3267 | } else { | |
3268 | ring->rx_buf_len = vsi->rx_buf_len; | |
3269 | if (ring->vsi->type == I40E_VSI_MAIN) { | |
3270 | ret = xdp_rxq_info_reg_mem_model(&ring->xdp_rxq, | |
3271 | MEM_TYPE_PAGE_SHARED, | |
3272 | NULL); | |
3273 | if (ret) | |
3274 | return ret; | |
3275 | } | |
3276 | } | |
41c445ff | 3277 | |
dab86afd AD |
3278 | rx_ctx.dbuff = DIV_ROUND_UP(ring->rx_buf_len, |
3279 | BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT)); | |
41c445ff JB |
3280 | |
3281 | rx_ctx.base = (ring->dma / 128); | |
3282 | rx_ctx.qlen = ring->count; | |
3283 | ||
bec60fc4 JB |
3284 | /* use 32 byte descriptors */ |
3285 | rx_ctx.dsize = 1; | |
41c445ff | 3286 | |
bec60fc4 JB |
3287 | /* descriptor type is always zero |
3288 | * rx_ctx.dtype = 0; | |
3289 | */ | |
b32bfa17 | 3290 | rx_ctx.hsplit_0 = 0; |
41c445ff | 3291 | |
b32bfa17 | 3292 | rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len); |
7134f9ce JB |
3293 | if (hw->revision_id == 0) |
3294 | rx_ctx.lrxqthresh = 0; | |
3295 | else | |
7362be9e | 3296 | rx_ctx.lrxqthresh = 1; |
41c445ff JB |
3297 | rx_ctx.crcstrip = 1; |
3298 | rx_ctx.l2tsel = 1; | |
c4bbac39 JB |
3299 | /* this controls whether VLAN is stripped from inner headers */ |
3300 | rx_ctx.showiv = 0; | |
acb3676b CS |
3301 | /* set the prefena field to 1 because the manual says to */ |
3302 | rx_ctx.prefena = 1; | |
41c445ff JB |
3303 | |
3304 | /* clear the context in the HMC */ | |
3305 | err = i40e_clear_lan_rx_queue_context(hw, pf_q); | |
3306 | if (err) { | |
3307 | dev_info(&vsi->back->pdev->dev, | |
3308 | "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", | |
3309 | ring->queue_index, pf_q, err); | |
3310 | return -ENOMEM; | |
3311 | } | |
3312 | ||
3313 | /* set the context in the HMC */ | |
3314 | err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx); | |
3315 | if (err) { | |
3316 | dev_info(&vsi->back->pdev->dev, | |
3317 | "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", | |
3318 | ring->queue_index, pf_q, err); | |
3319 | return -ENOMEM; | |
3320 | } | |
3321 | ||
ca9ec088 AD |
3322 | /* configure Rx buffer alignment */ |
3323 | if (!vsi->netdev || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) | |
3324 | clear_ring_build_skb_enabled(ring); | |
3325 | else | |
3326 | set_ring_build_skb_enabled(ring); | |
3327 | ||
41c445ff JB |
3328 | /* cache tail for quicker writes, and clear the reg before use */ |
3329 | ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q); | |
3330 | writel(0, ring->tail); | |
3331 | ||
0a714186 BT |
3332 | ok = ring->xsk_umem ? |
3333 | i40e_alloc_rx_buffers_zc(ring, I40E_DESC_UNUSED(ring)) : | |
3334 | !i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring)); | |
3335 | if (!ok) { | |
14ffeb52 MK |
3336 | /* Log this in case the user has forgotten to give the kernel |
3337 | * any buffers, even later in the application. | |
3338 | */ | |
0a714186 | 3339 | dev_info(&vsi->back->pdev->dev, |
14ffeb52 | 3340 | "Failed to allocate some buffers on %sRx ring %d (pf_q %d)\n", |
0a714186 BT |
3341 | ring->xsk_umem ? "UMEM enabled " : "", |
3342 | ring->queue_index, pf_q); | |
3343 | } | |
41c445ff JB |
3344 | |
3345 | return 0; | |
3346 | } | |
3347 | ||
3348 | /** | |
3349 | * i40e_vsi_configure_tx - Configure the VSI for Tx | |
3350 | * @vsi: VSI structure describing this set of rings and resources | |
3351 | * | |
3352 | * Configure the Tx VSI for operation. | |
3353 | **/ | |
3354 | static int i40e_vsi_configure_tx(struct i40e_vsi *vsi) | |
3355 | { | |
3356 | int err = 0; | |
3357 | u16 i; | |
3358 | ||
9f65e15b AD |
3359 | for (i = 0; (i < vsi->num_queue_pairs) && !err; i++) |
3360 | err = i40e_configure_tx_ring(vsi->tx_rings[i]); | |
41c445ff | 3361 | |
74608d17 BT |
3362 | if (!i40e_enabled_xdp_vsi(vsi)) |
3363 | return err; | |
3364 | ||
3365 | for (i = 0; (i < vsi->num_queue_pairs) && !err; i++) | |
3366 | err = i40e_configure_tx_ring(vsi->xdp_rings[i]); | |
3367 | ||
41c445ff JB |
3368 | return err; |
3369 | } | |
3370 | ||
3371 | /** | |
3372 | * i40e_vsi_configure_rx - Configure the VSI for Rx | |
3373 | * @vsi: the VSI being configured | |
3374 | * | |
3375 | * Configure the Rx VSI for operation. | |
3376 | **/ | |
3377 | static int i40e_vsi_configure_rx(struct i40e_vsi *vsi) | |
3378 | { | |
3379 | int err = 0; | |
3380 | u16 i; | |
3381 | ||
dab86afd AD |
3382 | if (!vsi->netdev || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) { |
3383 | vsi->max_frame = I40E_MAX_RXBUFFER; | |
3384 | vsi->rx_buf_len = I40E_RXBUFFER_2048; | |
3385 | #if (PAGE_SIZE < 8192) | |
ca9ec088 AD |
3386 | } else if (!I40E_2K_TOO_SMALL_WITH_PADDING && |
3387 | (vsi->netdev->mtu <= ETH_DATA_LEN)) { | |
dab86afd AD |
3388 | vsi->max_frame = I40E_RXBUFFER_1536 - NET_IP_ALIGN; |
3389 | vsi->rx_buf_len = I40E_RXBUFFER_1536 - NET_IP_ALIGN; | |
3390 | #endif | |
3391 | } else { | |
3392 | vsi->max_frame = I40E_MAX_RXBUFFER; | |
98efd694 AD |
3393 | vsi->rx_buf_len = (PAGE_SIZE < 8192) ? I40E_RXBUFFER_3072 : |
3394 | I40E_RXBUFFER_2048; | |
dab86afd | 3395 | } |
41c445ff JB |
3396 | |
3397 | /* set up individual rings */ | |
3398 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 3399 | err = i40e_configure_rx_ring(vsi->rx_rings[i]); |
41c445ff JB |
3400 | |
3401 | return err; | |
3402 | } | |
3403 | ||
3404 | /** | |
3405 | * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC | |
3406 | * @vsi: ptr to the VSI | |
3407 | **/ | |
3408 | static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi) | |
3409 | { | |
e7046ee1 | 3410 | struct i40e_ring *tx_ring, *rx_ring; |
41c445ff JB |
3411 | u16 qoffset, qcount; |
3412 | int i, n; | |
3413 | ||
cd238a3e PN |
3414 | if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { |
3415 | /* Reset the TC information */ | |
3416 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
3417 | rx_ring = vsi->rx_rings[i]; | |
3418 | tx_ring = vsi->tx_rings[i]; | |
3419 | rx_ring->dcb_tc = 0; | |
3420 | tx_ring->dcb_tc = 0; | |
3421 | } | |
a9ce82f7 | 3422 | return; |
cd238a3e | 3423 | } |
41c445ff JB |
3424 | |
3425 | for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) { | |
41a1d04b | 3426 | if (!(vsi->tc_config.enabled_tc & BIT_ULL(n))) |
41c445ff JB |
3427 | continue; |
3428 | ||
3429 | qoffset = vsi->tc_config.tc_info[n].qoffset; | |
3430 | qcount = vsi->tc_config.tc_info[n].qcount; | |
3431 | for (i = qoffset; i < (qoffset + qcount); i++) { | |
e7046ee1 AA |
3432 | rx_ring = vsi->rx_rings[i]; |
3433 | tx_ring = vsi->tx_rings[i]; | |
41c445ff JB |
3434 | rx_ring->dcb_tc = n; |
3435 | tx_ring->dcb_tc = n; | |
3436 | } | |
3437 | } | |
3438 | } | |
3439 | ||
3440 | /** | |
3441 | * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI | |
3442 | * @vsi: ptr to the VSI | |
3443 | **/ | |
3444 | static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi) | |
3445 | { | |
3446 | if (vsi->netdev) | |
3447 | i40e_set_rx_mode(vsi->netdev); | |
3448 | } | |
3449 | ||
17a73f6b JG |
3450 | /** |
3451 | * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters | |
3452 | * @vsi: Pointer to the targeted VSI | |
3453 | * | |
3454 | * This function replays the hlist on the hw where all the SB Flow Director | |
3455 | * filters were saved. | |
3456 | **/ | |
3457 | static void i40e_fdir_filter_restore(struct i40e_vsi *vsi) | |
3458 | { | |
3459 | struct i40e_fdir_filter *filter; | |
3460 | struct i40e_pf *pf = vsi->back; | |
3461 | struct hlist_node *node; | |
3462 | ||
55a5e60b ASJ |
3463 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) |
3464 | return; | |
3465 | ||
6d069425 | 3466 | /* Reset FDir counters as we're replaying all existing filters */ |
097dbf52 JK |
3467 | pf->fd_tcp4_filter_cnt = 0; |
3468 | pf->fd_udp4_filter_cnt = 0; | |
f223c875 | 3469 | pf->fd_sctp4_filter_cnt = 0; |
097dbf52 | 3470 | pf->fd_ip4_filter_cnt = 0; |
6d069425 | 3471 | |
17a73f6b JG |
3472 | hlist_for_each_entry_safe(filter, node, |
3473 | &pf->fdir_filter_list, fdir_node) { | |
3474 | i40e_add_del_fdir(vsi, filter, true); | |
3475 | } | |
3476 | } | |
3477 | ||
41c445ff JB |
3478 | /** |
3479 | * i40e_vsi_configure - Set up the VSI for action | |
3480 | * @vsi: the VSI being configured | |
3481 | **/ | |
3482 | static int i40e_vsi_configure(struct i40e_vsi *vsi) | |
3483 | { | |
3484 | int err; | |
3485 | ||
3486 | i40e_set_vsi_rx_mode(vsi); | |
3487 | i40e_restore_vlan(vsi); | |
3488 | i40e_vsi_config_dcb_rings(vsi); | |
3489 | err = i40e_vsi_configure_tx(vsi); | |
3490 | if (!err) | |
3491 | err = i40e_vsi_configure_rx(vsi); | |
3492 | ||
3493 | return err; | |
3494 | } | |
3495 | ||
3496 | /** | |
3497 | * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW | |
3498 | * @vsi: the VSI being configured | |
3499 | **/ | |
3500 | static void i40e_vsi_configure_msix(struct i40e_vsi *vsi) | |
3501 | { | |
74608d17 | 3502 | bool has_xdp = i40e_enabled_xdp_vsi(vsi); |
41c445ff | 3503 | struct i40e_pf *pf = vsi->back; |
41c445ff JB |
3504 | struct i40e_hw *hw = &pf->hw; |
3505 | u16 vector; | |
3506 | int i, q; | |
41c445ff JB |
3507 | u32 qp; |
3508 | ||
3509 | /* The interrupt indexing is offset by 1 in the PFINT_ITRn | |
3510 | * and PFINT_LNKLSTn registers, e.g.: | |
3511 | * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts) | |
3512 | */ | |
3513 | qp = vsi->base_queue; | |
3514 | vector = vsi->base_vector; | |
493fb300 | 3515 | for (i = 0; i < vsi->num_q_vectors; i++, vector++) { |
ac26fc13 JB |
3516 | struct i40e_q_vector *q_vector = vsi->q_vectors[i]; |
3517 | ||
a0073a4b | 3518 | q_vector->rx.next_update = jiffies + 1; |
556fdfd6 AD |
3519 | q_vector->rx.target_itr = |
3520 | ITR_TO_REG(vsi->rx_rings[i]->itr_setting); | |
41c445ff | 3521 | wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1), |
556fdfd6 AD |
3522 | q_vector->rx.target_itr); |
3523 | q_vector->rx.current_itr = q_vector->rx.target_itr; | |
a0073a4b AD |
3524 | |
3525 | q_vector->tx.next_update = jiffies + 1; | |
556fdfd6 AD |
3526 | q_vector->tx.target_itr = |
3527 | ITR_TO_REG(vsi->tx_rings[i]->itr_setting); | |
41c445ff | 3528 | wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1), |
556fdfd6 AD |
3529 | q_vector->tx.target_itr); |
3530 | q_vector->tx.current_itr = q_vector->tx.target_itr; | |
a0073a4b | 3531 | |
ac26fc13 | 3532 | wr32(hw, I40E_PFINT_RATEN(vector - 1), |
1c0e6a36 | 3533 | i40e_intrl_usec_to_reg(vsi->int_rate_limit)); |
41c445ff JB |
3534 | |
3535 | /* Linked list for the queuepairs assigned to this vector */ | |
3536 | wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp); | |
3537 | for (q = 0; q < q_vector->num_ringpairs; q++) { | |
74608d17 | 3538 | u32 nextqp = has_xdp ? qp + vsi->alloc_queue_pairs : qp; |
ac26fc13 JB |
3539 | u32 val; |
3540 | ||
41c445ff | 3541 | val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | |
74608d17 BT |
3542 | (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | |
3543 | (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | | |
3544 | (nextqp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | | |
3545 | (I40E_QUEUE_TYPE_TX << | |
3546 | I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); | |
41c445ff JB |
3547 | |
3548 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
3549 | ||
74608d17 BT |
3550 | if (has_xdp) { |
3551 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
3552 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | |
3553 | (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | | |
3554 | (qp << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | | |
3555 | (I40E_QUEUE_TYPE_TX << | |
3556 | I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
3557 | ||
3558 | wr32(hw, I40E_QINT_TQCTL(nextqp), val); | |
3559 | } | |
3560 | ||
41c445ff | 3561 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | |
74608d17 BT |
3562 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | |
3563 | (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | | |
3564 | ((qp + 1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | | |
3565 | (I40E_QUEUE_TYPE_RX << | |
3566 | I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
41c445ff JB |
3567 | |
3568 | /* Terminate the linked list */ | |
3569 | if (q == (q_vector->num_ringpairs - 1)) | |
74608d17 BT |
3570 | val |= (I40E_QUEUE_END_OF_LIST << |
3571 | I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |
41c445ff JB |
3572 | |
3573 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
3574 | qp++; | |
3575 | } | |
3576 | } | |
3577 | ||
3578 | i40e_flush(hw); | |
3579 | } | |
3580 | ||
3581 | /** | |
3582 | * i40e_enable_misc_int_causes - enable the non-queue interrupts | |
f5254429 | 3583 | * @pf: pointer to private device data structure |
41c445ff | 3584 | **/ |
ab437b5a | 3585 | static void i40e_enable_misc_int_causes(struct i40e_pf *pf) |
41c445ff | 3586 | { |
ab437b5a | 3587 | struct i40e_hw *hw = &pf->hw; |
41c445ff JB |
3588 | u32 val; |
3589 | ||
3590 | /* clear things first */ | |
3591 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ | |
3592 | rd32(hw, I40E_PFINT_ICR0); /* read to clear */ | |
3593 | ||
3594 | val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | | |
3595 | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | | |
3596 | I40E_PFINT_ICR0_ENA_GRST_MASK | | |
3597 | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | | |
3598 | I40E_PFINT_ICR0_ENA_GPIO_MASK | | |
41c445ff JB |
3599 | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | |
3600 | I40E_PFINT_ICR0_ENA_VFLR_MASK | | |
3601 | I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
3602 | ||
0d8e1439 ASJ |
3603 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) |
3604 | val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; | |
3605 | ||
ab437b5a JK |
3606 | if (pf->flags & I40E_FLAG_PTP) |
3607 | val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; | |
3608 | ||
41c445ff JB |
3609 | wr32(hw, I40E_PFINT_ICR0_ENA, val); |
3610 | ||
3611 | /* SW_ITR_IDX = 0, but don't change INTENA */ | |
84ed40e7 ASJ |
3612 | wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | |
3613 | I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); | |
41c445ff JB |
3614 | |
3615 | /* OTHER_ITR_IDX = 0 */ | |
3616 | wr32(hw, I40E_PFINT_STAT_CTL0, 0); | |
3617 | } | |
3618 | ||
3619 | /** | |
3620 | * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW | |
3621 | * @vsi: the VSI being configured | |
3622 | **/ | |
3623 | static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi) | |
3624 | { | |
74608d17 | 3625 | u32 nextqp = i40e_enabled_xdp_vsi(vsi) ? vsi->alloc_queue_pairs : 0; |
493fb300 | 3626 | struct i40e_q_vector *q_vector = vsi->q_vectors[0]; |
41c445ff JB |
3627 | struct i40e_pf *pf = vsi->back; |
3628 | struct i40e_hw *hw = &pf->hw; | |
3629 | u32 val; | |
3630 | ||
3631 | /* set the ITR configuration */ | |
a0073a4b | 3632 | q_vector->rx.next_update = jiffies + 1; |
556fdfd6 | 3633 | q_vector->rx.target_itr = ITR_TO_REG(vsi->rx_rings[0]->itr_setting); |
556fdfd6 AD |
3634 | wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.target_itr); |
3635 | q_vector->rx.current_itr = q_vector->rx.target_itr; | |
a0073a4b | 3636 | q_vector->tx.next_update = jiffies + 1; |
556fdfd6 | 3637 | q_vector->tx.target_itr = ITR_TO_REG(vsi->tx_rings[0]->itr_setting); |
556fdfd6 AD |
3638 | wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.target_itr); |
3639 | q_vector->tx.current_itr = q_vector->tx.target_itr; | |
41c445ff | 3640 | |
ab437b5a | 3641 | i40e_enable_misc_int_causes(pf); |
41c445ff JB |
3642 | |
3643 | /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ | |
3644 | wr32(hw, I40E_PFINT_LNKLST0, 0); | |
3645 | ||
f29eaa3d | 3646 | /* Associate the queue pair to the vector and enable the queue int */ |
74608d17 BT |
3647 | val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | |
3648 | (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | | |
3649 | (nextqp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)| | |
41c445ff JB |
3650 | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); |
3651 | ||
3652 | wr32(hw, I40E_QINT_RQCTL(0), val); | |
3653 | ||
74608d17 BT |
3654 | if (i40e_enabled_xdp_vsi(vsi)) { |
3655 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
3656 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT)| | |
3657 | (I40E_QUEUE_TYPE_TX | |
3658 | << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
3659 | ||
1d67ad39 | 3660 | wr32(hw, I40E_QINT_TQCTL(nextqp), val); |
74608d17 BT |
3661 | } |
3662 | ||
41c445ff JB |
3663 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | |
3664 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | |
3665 | (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |
3666 | ||
3667 | wr32(hw, I40E_QINT_TQCTL(0), val); | |
3668 | i40e_flush(hw); | |
3669 | } | |
3670 | ||
2ef28cfb MW |
3671 | /** |
3672 | * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0 | |
3673 | * @pf: board private structure | |
3674 | **/ | |
3675 | void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf) | |
3676 | { | |
3677 | struct i40e_hw *hw = &pf->hw; | |
3678 | ||
3679 | wr32(hw, I40E_PFINT_DYN_CTL0, | |
3680 | I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); | |
3681 | i40e_flush(hw); | |
3682 | } | |
3683 | ||
41c445ff JB |
3684 | /** |
3685 | * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0 | |
3686 | * @pf: board private structure | |
3687 | **/ | |
dbadbbe2 | 3688 | void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf) |
41c445ff JB |
3689 | { |
3690 | struct i40e_hw *hw = &pf->hw; | |
3691 | u32 val; | |
3692 | ||
3693 | val = I40E_PFINT_DYN_CTL0_INTENA_MASK | | |
dbadbbe2 | 3694 | I40E_PFINT_DYN_CTL0_CLEARPBA_MASK | |
41c445ff JB |
3695 | (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); |
3696 | ||
3697 | wr32(hw, I40E_PFINT_DYN_CTL0, val); | |
3698 | i40e_flush(hw); | |
3699 | } | |
3700 | ||
41c445ff JB |
3701 | /** |
3702 | * i40e_msix_clean_rings - MSIX mode Interrupt Handler | |
3703 | * @irq: interrupt number | |
3704 | * @data: pointer to a q_vector | |
3705 | **/ | |
3706 | static irqreturn_t i40e_msix_clean_rings(int irq, void *data) | |
3707 | { | |
3708 | struct i40e_q_vector *q_vector = data; | |
3709 | ||
cd0b6fa6 | 3710 | if (!q_vector->tx.ring && !q_vector->rx.ring) |
41c445ff JB |
3711 | return IRQ_HANDLED; |
3712 | ||
5d3465a1 | 3713 | napi_schedule_irqoff(&q_vector->napi); |
41c445ff JB |
3714 | |
3715 | return IRQ_HANDLED; | |
3716 | } | |
3717 | ||
96db776a AB |
3718 | /** |
3719 | * i40e_irq_affinity_notify - Callback for affinity changes | |
3720 | * @notify: context as to what irq was changed | |
3721 | * @mask: the new affinity mask | |
3722 | * | |
3723 | * This is a callback function used by the irq_set_affinity_notifier function | |
3724 | * so that we may register to receive changes to the irq affinity masks. | |
3725 | **/ | |
3726 | static void i40e_irq_affinity_notify(struct irq_affinity_notify *notify, | |
3727 | const cpumask_t *mask) | |
3728 | { | |
3729 | struct i40e_q_vector *q_vector = | |
3730 | container_of(notify, struct i40e_q_vector, affinity_notify); | |
3731 | ||
7e4d01e7 | 3732 | cpumask_copy(&q_vector->affinity_mask, mask); |
96db776a AB |
3733 | } |
3734 | ||
3735 | /** | |
3736 | * i40e_irq_affinity_release - Callback for affinity notifier release | |
3737 | * @ref: internal core kernel usage | |
3738 | * | |
3739 | * This is a callback function used by the irq_set_affinity_notifier function | |
3740 | * to inform the current notification subscriber that they will no longer | |
3741 | * receive notifications. | |
3742 | **/ | |
3743 | static void i40e_irq_affinity_release(struct kref *ref) {} | |
3744 | ||
41c445ff JB |
3745 | /** |
3746 | * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts | |
3747 | * @vsi: the VSI being configured | |
3748 | * @basename: name for the vector | |
3749 | * | |
3750 | * Allocates MSI-X vectors and requests interrupts from the kernel. | |
3751 | **/ | |
3752 | static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename) | |
3753 | { | |
3754 | int q_vectors = vsi->num_q_vectors; | |
3755 | struct i40e_pf *pf = vsi->back; | |
3756 | int base = vsi->base_vector; | |
3757 | int rx_int_idx = 0; | |
3758 | int tx_int_idx = 0; | |
3759 | int vector, err; | |
96db776a | 3760 | int irq_num; |
be664cbe | 3761 | int cpu; |
41c445ff JB |
3762 | |
3763 | for (vector = 0; vector < q_vectors; vector++) { | |
493fb300 | 3764 | struct i40e_q_vector *q_vector = vsi->q_vectors[vector]; |
41c445ff | 3765 | |
96db776a AB |
3766 | irq_num = pf->msix_entries[base + vector].vector; |
3767 | ||
cd0b6fa6 | 3768 | if (q_vector->tx.ring && q_vector->rx.ring) { |
41c445ff JB |
3769 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3770 | "%s-%s-%d", basename, "TxRx", rx_int_idx++); | |
3771 | tx_int_idx++; | |
cd0b6fa6 | 3772 | } else if (q_vector->rx.ring) { |
41c445ff JB |
3773 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3774 | "%s-%s-%d", basename, "rx", rx_int_idx++); | |
cd0b6fa6 | 3775 | } else if (q_vector->tx.ring) { |
41c445ff JB |
3776 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3777 | "%s-%s-%d", basename, "tx", tx_int_idx++); | |
3778 | } else { | |
3779 | /* skip this unused q_vector */ | |
3780 | continue; | |
3781 | } | |
96db776a | 3782 | err = request_irq(irq_num, |
41c445ff JB |
3783 | vsi->irq_handler, |
3784 | 0, | |
3785 | q_vector->name, | |
3786 | q_vector); | |
3787 | if (err) { | |
3788 | dev_info(&pf->pdev->dev, | |
fb43201f | 3789 | "MSIX request_irq failed, error: %d\n", err); |
41c445ff JB |
3790 | goto free_queue_irqs; |
3791 | } | |
96db776a AB |
3792 | |
3793 | /* register for affinity change notifications */ | |
3794 | q_vector->affinity_notify.notify = i40e_irq_affinity_notify; | |
3795 | q_vector->affinity_notify.release = i40e_irq_affinity_release; | |
3796 | irq_set_affinity_notifier(irq_num, &q_vector->affinity_notify); | |
be664cbe JK |
3797 | /* Spread affinity hints out across online CPUs. |
3798 | * | |
3799 | * get_cpu_mask returns a static constant mask with | |
3800 | * a permanent lifetime so it's ok to pass to | |
3801 | * irq_set_affinity_hint without making a copy. | |
759dc4a7 | 3802 | */ |
be664cbe JK |
3803 | cpu = cpumask_local_spread(q_vector->v_idx, -1); |
3804 | irq_set_affinity_hint(irq_num, get_cpu_mask(cpu)); | |
41c445ff JB |
3805 | } |
3806 | ||
63741846 | 3807 | vsi->irqs_ready = true; |
41c445ff JB |
3808 | return 0; |
3809 | ||
3810 | free_queue_irqs: | |
3811 | while (vector) { | |
3812 | vector--; | |
96db776a AB |
3813 | irq_num = pf->msix_entries[base + vector].vector; |
3814 | irq_set_affinity_notifier(irq_num, NULL); | |
3815 | irq_set_affinity_hint(irq_num, NULL); | |
3816 | free_irq(irq_num, &vsi->q_vectors[vector]); | |
41c445ff JB |
3817 | } |
3818 | return err; | |
3819 | } | |
3820 | ||
3821 | /** | |
3822 | * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI | |
3823 | * @vsi: the VSI being un-configured | |
3824 | **/ | |
3825 | static void i40e_vsi_disable_irq(struct i40e_vsi *vsi) | |
3826 | { | |
3827 | struct i40e_pf *pf = vsi->back; | |
3828 | struct i40e_hw *hw = &pf->hw; | |
3829 | int base = vsi->base_vector; | |
3830 | int i; | |
3831 | ||
2e5c26ea | 3832 | /* disable interrupt causation from each queue */ |
41c445ff | 3833 | for (i = 0; i < vsi->num_queue_pairs; i++) { |
2e5c26ea SN |
3834 | u32 val; |
3835 | ||
3836 | val = rd32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx)); | |
3837 | val &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK; | |
3838 | wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), val); | |
3839 | ||
3840 | val = rd32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx)); | |
3841 | val &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK; | |
3842 | wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), val); | |
3843 | ||
74608d17 BT |
3844 | if (!i40e_enabled_xdp_vsi(vsi)) |
3845 | continue; | |
3846 | wr32(hw, I40E_QINT_TQCTL(vsi->xdp_rings[i]->reg_idx), 0); | |
41c445ff JB |
3847 | } |
3848 | ||
2e5c26ea | 3849 | /* disable each interrupt */ |
41c445ff JB |
3850 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { |
3851 | for (i = vsi->base_vector; | |
3852 | i < (vsi->num_q_vectors + vsi->base_vector); i++) | |
3853 | wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0); | |
3854 | ||
3855 | i40e_flush(hw); | |
3856 | for (i = 0; i < vsi->num_q_vectors; i++) | |
3857 | synchronize_irq(pf->msix_entries[i + base].vector); | |
3858 | } else { | |
3859 | /* Legacy and MSI mode - this stops all interrupt handling */ | |
3860 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); | |
3861 | wr32(hw, I40E_PFINT_DYN_CTL0, 0); | |
3862 | i40e_flush(hw); | |
3863 | synchronize_irq(pf->pdev->irq); | |
3864 | } | |
3865 | } | |
3866 | ||
3867 | /** | |
3868 | * i40e_vsi_enable_irq - Enable IRQ for the given VSI | |
3869 | * @vsi: the VSI being configured | |
3870 | **/ | |
3871 | static int i40e_vsi_enable_irq(struct i40e_vsi *vsi) | |
3872 | { | |
3873 | struct i40e_pf *pf = vsi->back; | |
3874 | int i; | |
3875 | ||
3876 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
7845548d | 3877 | for (i = 0; i < vsi->num_q_vectors; i++) |
41c445ff JB |
3878 | i40e_irq_dynamic_enable(vsi, i); |
3879 | } else { | |
dbadbbe2 | 3880 | i40e_irq_dynamic_enable_icr0(pf); |
41c445ff JB |
3881 | } |
3882 | ||
1022cb6c | 3883 | i40e_flush(&pf->hw); |
41c445ff JB |
3884 | return 0; |
3885 | } | |
3886 | ||
3887 | /** | |
c17401a1 | 3888 | * i40e_free_misc_vector - Free the vector that handles non-queue events |
41c445ff JB |
3889 | * @pf: board private structure |
3890 | **/ | |
c17401a1 | 3891 | static void i40e_free_misc_vector(struct i40e_pf *pf) |
41c445ff JB |
3892 | { |
3893 | /* Disable ICR 0 */ | |
3894 | wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0); | |
3895 | i40e_flush(&pf->hw); | |
c17401a1 JK |
3896 | |
3897 | if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) { | |
3898 | synchronize_irq(pf->msix_entries[0].vector); | |
3899 | free_irq(pf->msix_entries[0].vector, pf); | |
3900 | clear_bit(__I40E_MISC_IRQ_REQUESTED, pf->state); | |
3901 | } | |
41c445ff JB |
3902 | } |
3903 | ||
3904 | /** | |
3905 | * i40e_intr - MSI/Legacy and non-queue interrupt handler | |
3906 | * @irq: interrupt number | |
3907 | * @data: pointer to a q_vector | |
3908 | * | |
3909 | * This is the handler used for all MSI/Legacy interrupts, and deals | |
3910 | * with both queue and non-queue interrupts. This is also used in | |
3911 | * MSIX mode to handle the non-queue interrupts. | |
3912 | **/ | |
3913 | static irqreturn_t i40e_intr(int irq, void *data) | |
3914 | { | |
3915 | struct i40e_pf *pf = (struct i40e_pf *)data; | |
3916 | struct i40e_hw *hw = &pf->hw; | |
5e823066 | 3917 | irqreturn_t ret = IRQ_NONE; |
41c445ff JB |
3918 | u32 icr0, icr0_remaining; |
3919 | u32 val, ena_mask; | |
3920 | ||
3921 | icr0 = rd32(hw, I40E_PFINT_ICR0); | |
5e823066 | 3922 | ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA); |
41c445ff | 3923 | |
116a57d4 SN |
3924 | /* if sharing a legacy IRQ, we might get called w/o an intr pending */ |
3925 | if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0) | |
5e823066 | 3926 | goto enable_intr; |
41c445ff | 3927 | |
cd92e72f SN |
3928 | /* if interrupt but no bits showing, must be SWINT */ |
3929 | if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) || | |
3930 | (icr0 & I40E_PFINT_ICR0_SWINT_MASK)) | |
3931 | pf->sw_int_count++; | |
3932 | ||
0d8e1439 | 3933 | if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && |
7642984b | 3934 | (icr0 & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) { |
0d8e1439 | 3935 | ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; |
23bb6dc3 | 3936 | dev_dbg(&pf->pdev->dev, "cleared PE_CRITERR\n"); |
7642984b | 3937 | set_bit(__I40E_CORE_RESET_REQUESTED, pf->state); |
0d8e1439 ASJ |
3938 | } |
3939 | ||
41c445ff JB |
3940 | /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */ |
3941 | if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) { | |
5d3465a1 AD |
3942 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
3943 | struct i40e_q_vector *q_vector = vsi->q_vectors[0]; | |
41c445ff | 3944 | |
a16ae2d5 ASJ |
3945 | /* We do not have a way to disarm Queue causes while leaving |
3946 | * interrupt enabled for all other causes, ideally | |
3947 | * interrupt should be disabled while we are in NAPI but | |
3948 | * this is not a performance path and napi_schedule() | |
3949 | * can deal with rescheduling. | |
3950 | */ | |
9e6c9c0f | 3951 | if (!test_bit(__I40E_DOWN, pf->state)) |
5d3465a1 | 3952 | napi_schedule_irqoff(&q_vector->napi); |
41c445ff JB |
3953 | } |
3954 | ||
3955 | if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { | |
3956 | ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
0da36b97 | 3957 | set_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state); |
6e93d0c9 | 3958 | i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n"); |
41c445ff JB |
3959 | } |
3960 | ||
3961 | if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) { | |
3962 | ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; | |
0da36b97 | 3963 | set_bit(__I40E_MDD_EVENT_PENDING, pf->state); |
41c445ff JB |
3964 | } |
3965 | ||
3966 | if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { | |
3967 | ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK; | |
0da36b97 | 3968 | set_bit(__I40E_VFLR_EVENT_PENDING, pf->state); |
41c445ff JB |
3969 | } |
3970 | ||
3971 | if (icr0 & I40E_PFINT_ICR0_GRST_MASK) { | |
0da36b97 JK |
3972 | if (!test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
3973 | set_bit(__I40E_RESET_INTR_RECEIVED, pf->state); | |
41c445ff JB |
3974 | ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK; |
3975 | val = rd32(hw, I40E_GLGEN_RSTAT); | |
3976 | val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK) | |
3977 | >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT; | |
4eb3f768 | 3978 | if (val == I40E_RESET_CORER) { |
41c445ff | 3979 | pf->corer_count++; |
4eb3f768 | 3980 | } else if (val == I40E_RESET_GLOBR) { |
41c445ff | 3981 | pf->globr_count++; |
4eb3f768 | 3982 | } else if (val == I40E_RESET_EMPR) { |
41c445ff | 3983 | pf->empr_count++; |
0da36b97 | 3984 | set_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state); |
4eb3f768 | 3985 | } |
41c445ff JB |
3986 | } |
3987 | ||
9c010ee0 ASJ |
3988 | if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) { |
3989 | icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK; | |
3990 | dev_info(&pf->pdev->dev, "HMC error interrupt\n"); | |
25fc0e65 ASJ |
3991 | dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n", |
3992 | rd32(hw, I40E_PFHMC_ERRORINFO), | |
3993 | rd32(hw, I40E_PFHMC_ERRORDATA)); | |
9c010ee0 ASJ |
3994 | } |
3995 | ||
beb0dff1 JK |
3996 | if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) { |
3997 | u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0); | |
3998 | ||
3999 | if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) { | |
cafa1fca | 4000 | icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; |
beb0dff1 | 4001 | i40e_ptp_tx_hwtstamp(pf); |
beb0dff1 | 4002 | } |
beb0dff1 JK |
4003 | } |
4004 | ||
41c445ff JB |
4005 | /* If a critical error is pending we have no choice but to reset the |
4006 | * device. | |
4007 | * Report and mask out any remaining unexpected interrupts. | |
4008 | */ | |
4009 | icr0_remaining = icr0 & ena_mask; | |
4010 | if (icr0_remaining) { | |
4011 | dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n", | |
4012 | icr0_remaining); | |
9c010ee0 | 4013 | if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) || |
41c445ff | 4014 | (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) || |
c0c28975 | 4015 | (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) { |
9c010ee0 | 4016 | dev_info(&pf->pdev->dev, "device will be reset\n"); |
0da36b97 | 4017 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
9c010ee0 | 4018 | i40e_service_event_schedule(pf); |
41c445ff JB |
4019 | } |
4020 | ena_mask &= ~icr0_remaining; | |
4021 | } | |
5e823066 | 4022 | ret = IRQ_HANDLED; |
41c445ff | 4023 | |
5e823066 | 4024 | enable_intr: |
41c445ff JB |
4025 | /* re-enable interrupt causes */ |
4026 | wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask); | |
4ff0ee1a AM |
4027 | if (!test_bit(__I40E_DOWN, pf->state) || |
4028 | test_bit(__I40E_RECOVERY_MODE, pf->state)) { | |
41c445ff | 4029 | i40e_service_event_schedule(pf); |
dbadbbe2 | 4030 | i40e_irq_dynamic_enable_icr0(pf); |
41c445ff JB |
4031 | } |
4032 | ||
5e823066 | 4033 | return ret; |
41c445ff JB |
4034 | } |
4035 | ||
cbf61325 ASJ |
4036 | /** |
4037 | * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes | |
4038 | * @tx_ring: tx ring to clean | |
4039 | * @budget: how many cleans we're allowed | |
4040 | * | |
4041 | * Returns true if there's any budget left (e.g. the clean is finished) | |
4042 | **/ | |
4043 | static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget) | |
4044 | { | |
4045 | struct i40e_vsi *vsi = tx_ring->vsi; | |
4046 | u16 i = tx_ring->next_to_clean; | |
4047 | struct i40e_tx_buffer *tx_buf; | |
4048 | struct i40e_tx_desc *tx_desc; | |
4049 | ||
4050 | tx_buf = &tx_ring->tx_bi[i]; | |
4051 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
4052 | i -= tx_ring->count; | |
4053 | ||
4054 | do { | |
4055 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
4056 | ||
4057 | /* if next_to_watch is not set then there is no work pending */ | |
4058 | if (!eop_desc) | |
4059 | break; | |
4060 | ||
4061 | /* prevent any other reads prior to eop_desc */ | |
52c6912f | 4062 | smp_rmb(); |
cbf61325 ASJ |
4063 | |
4064 | /* if the descriptor isn't done, no work yet to do */ | |
4065 | if (!(eop_desc->cmd_type_offset_bsz & | |
4066 | cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE))) | |
4067 | break; | |
4068 | ||
4069 | /* clear next_to_watch to prevent false hangs */ | |
4070 | tx_buf->next_to_watch = NULL; | |
4071 | ||
49d7d933 ASJ |
4072 | tx_desc->buffer_addr = 0; |
4073 | tx_desc->cmd_type_offset_bsz = 0; | |
4074 | /* move past filter desc */ | |
4075 | tx_buf++; | |
4076 | tx_desc++; | |
4077 | i++; | |
4078 | if (unlikely(!i)) { | |
4079 | i -= tx_ring->count; | |
4080 | tx_buf = tx_ring->tx_bi; | |
4081 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
4082 | } | |
cbf61325 ASJ |
4083 | /* unmap skb header data */ |
4084 | dma_unmap_single(tx_ring->dev, | |
4085 | dma_unmap_addr(tx_buf, dma), | |
4086 | dma_unmap_len(tx_buf, len), | |
4087 | DMA_TO_DEVICE); | |
49d7d933 ASJ |
4088 | if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB) |
4089 | kfree(tx_buf->raw_buf); | |
cbf61325 | 4090 | |
49d7d933 ASJ |
4091 | tx_buf->raw_buf = NULL; |
4092 | tx_buf->tx_flags = 0; | |
4093 | tx_buf->next_to_watch = NULL; | |
cbf61325 | 4094 | dma_unmap_len_set(tx_buf, len, 0); |
49d7d933 ASJ |
4095 | tx_desc->buffer_addr = 0; |
4096 | tx_desc->cmd_type_offset_bsz = 0; | |
cbf61325 | 4097 | |
49d7d933 | 4098 | /* move us past the eop_desc for start of next FD desc */ |
cbf61325 ASJ |
4099 | tx_buf++; |
4100 | tx_desc++; | |
4101 | i++; | |
4102 | if (unlikely(!i)) { | |
4103 | i -= tx_ring->count; | |
4104 | tx_buf = tx_ring->tx_bi; | |
4105 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
4106 | } | |
4107 | ||
4108 | /* update budget accounting */ | |
4109 | budget--; | |
4110 | } while (likely(budget)); | |
4111 | ||
4112 | i += tx_ring->count; | |
4113 | tx_ring->next_to_clean = i; | |
4114 | ||
6995b36c | 4115 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) |
7845548d | 4116 | i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx); |
6995b36c | 4117 | |
cbf61325 ASJ |
4118 | return budget > 0; |
4119 | } | |
4120 | ||
4121 | /** | |
4122 | * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring | |
4123 | * @irq: interrupt number | |
4124 | * @data: pointer to a q_vector | |
4125 | **/ | |
4126 | static irqreturn_t i40e_fdir_clean_ring(int irq, void *data) | |
4127 | { | |
4128 | struct i40e_q_vector *q_vector = data; | |
4129 | struct i40e_vsi *vsi; | |
4130 | ||
4131 | if (!q_vector->tx.ring) | |
4132 | return IRQ_HANDLED; | |
4133 | ||
4134 | vsi = q_vector->tx.ring->vsi; | |
4135 | i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit); | |
4136 | ||
4137 | return IRQ_HANDLED; | |
4138 | } | |
4139 | ||
41c445ff | 4140 | /** |
cd0b6fa6 | 4141 | * i40e_map_vector_to_qp - Assigns the queue pair to the vector |
41c445ff JB |
4142 | * @vsi: the VSI being configured |
4143 | * @v_idx: vector index | |
cd0b6fa6 | 4144 | * @qp_idx: queue pair index |
41c445ff | 4145 | **/ |
26cdc443 | 4146 | static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx) |
41c445ff | 4147 | { |
493fb300 | 4148 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; |
9f65e15b AD |
4149 | struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx]; |
4150 | struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx]; | |
41c445ff JB |
4151 | |
4152 | tx_ring->q_vector = q_vector; | |
cd0b6fa6 AD |
4153 | tx_ring->next = q_vector->tx.ring; |
4154 | q_vector->tx.ring = tx_ring; | |
41c445ff | 4155 | q_vector->tx.count++; |
cd0b6fa6 | 4156 | |
74608d17 BT |
4157 | /* Place XDP Tx ring in the same q_vector ring list as regular Tx */ |
4158 | if (i40e_enabled_xdp_vsi(vsi)) { | |
4159 | struct i40e_ring *xdp_ring = vsi->xdp_rings[qp_idx]; | |
4160 | ||
4161 | xdp_ring->q_vector = q_vector; | |
4162 | xdp_ring->next = q_vector->tx.ring; | |
4163 | q_vector->tx.ring = xdp_ring; | |
4164 | q_vector->tx.count++; | |
4165 | } | |
4166 | ||
cd0b6fa6 AD |
4167 | rx_ring->q_vector = q_vector; |
4168 | rx_ring->next = q_vector->rx.ring; | |
4169 | q_vector->rx.ring = rx_ring; | |
4170 | q_vector->rx.count++; | |
41c445ff JB |
4171 | } |
4172 | ||
4173 | /** | |
4174 | * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors | |
4175 | * @vsi: the VSI being configured | |
4176 | * | |
4177 | * This function maps descriptor rings to the queue-specific vectors | |
4178 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
4179 | * one vector per queue pair, but on a constrained vector budget, we | |
4180 | * group the queue pairs as "efficiently" as possible. | |
4181 | **/ | |
4182 | static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi) | |
4183 | { | |
4184 | int qp_remaining = vsi->num_queue_pairs; | |
4185 | int q_vectors = vsi->num_q_vectors; | |
cd0b6fa6 | 4186 | int num_ringpairs; |
41c445ff JB |
4187 | int v_start = 0; |
4188 | int qp_idx = 0; | |
4189 | ||
4190 | /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to | |
4191 | * group them so there are multiple queues per vector. | |
70114ec4 ASJ |
4192 | * It is also important to go through all the vectors available to be |
4193 | * sure that if we don't use all the vectors, that the remaining vectors | |
4194 | * are cleared. This is especially important when decreasing the | |
4195 | * number of queues in use. | |
41c445ff | 4196 | */ |
70114ec4 | 4197 | for (; v_start < q_vectors; v_start++) { |
cd0b6fa6 AD |
4198 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_start]; |
4199 | ||
4200 | num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start); | |
4201 | ||
4202 | q_vector->num_ringpairs = num_ringpairs; | |
a3f9fb5e | 4203 | q_vector->reg_idx = q_vector->v_idx + vsi->base_vector - 1; |
cd0b6fa6 AD |
4204 | |
4205 | q_vector->rx.count = 0; | |
4206 | q_vector->tx.count = 0; | |
4207 | q_vector->rx.ring = NULL; | |
4208 | q_vector->tx.ring = NULL; | |
4209 | ||
4210 | while (num_ringpairs--) { | |
26cdc443 | 4211 | i40e_map_vector_to_qp(vsi, v_start, qp_idx); |
cd0b6fa6 AD |
4212 | qp_idx++; |
4213 | qp_remaining--; | |
41c445ff JB |
4214 | } |
4215 | } | |
4216 | } | |
4217 | ||
4218 | /** | |
4219 | * i40e_vsi_request_irq - Request IRQ from the OS | |
4220 | * @vsi: the VSI being configured | |
4221 | * @basename: name for the vector | |
4222 | **/ | |
4223 | static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename) | |
4224 | { | |
4225 | struct i40e_pf *pf = vsi->back; | |
4226 | int err; | |
4227 | ||
4228 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
4229 | err = i40e_vsi_request_irq_msix(vsi, basename); | |
4230 | else if (pf->flags & I40E_FLAG_MSI_ENABLED) | |
4231 | err = request_irq(pf->pdev->irq, i40e_intr, 0, | |
b294ac70 | 4232 | pf->int_name, pf); |
41c445ff JB |
4233 | else |
4234 | err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED, | |
b294ac70 | 4235 | pf->int_name, pf); |
41c445ff JB |
4236 | |
4237 | if (err) | |
4238 | dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err); | |
4239 | ||
4240 | return err; | |
4241 | } | |
4242 | ||
4243 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
4244 | /** | |
d89d967f | 4245 | * i40e_netpoll - A Polling 'interrupt' handler |
41c445ff JB |
4246 | * @netdev: network interface device structure |
4247 | * | |
4248 | * This is used by netconsole to send skbs without having to re-enable | |
4249 | * interrupts. It's not called while the normal interrupt routine is executing. | |
4250 | **/ | |
4251 | static void i40e_netpoll(struct net_device *netdev) | |
4252 | { | |
4253 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
4254 | struct i40e_vsi *vsi = np->vsi; | |
4255 | struct i40e_pf *pf = vsi->back; | |
4256 | int i; | |
4257 | ||
4258 | /* if interface is down do nothing */ | |
0da36b97 | 4259 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) |
41c445ff JB |
4260 | return; |
4261 | ||
41c445ff JB |
4262 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { |
4263 | for (i = 0; i < vsi->num_q_vectors; i++) | |
493fb300 | 4264 | i40e_msix_clean_rings(0, vsi->q_vectors[i]); |
41c445ff JB |
4265 | } else { |
4266 | i40e_intr(pf->pdev->irq, netdev); | |
4267 | } | |
41c445ff JB |
4268 | } |
4269 | #endif | |
4270 | ||
c768e490 JK |
4271 | #define I40E_QTX_ENA_WAIT_COUNT 50 |
4272 | ||
23527308 NP |
4273 | /** |
4274 | * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled | |
4275 | * @pf: the PF being configured | |
4276 | * @pf_q: the PF queue | |
4277 | * @enable: enable or disable state of the queue | |
4278 | * | |
4279 | * This routine will wait for the given Tx queue of the PF to reach the | |
4280 | * enabled or disabled state. | |
4281 | * Returns -ETIMEDOUT in case of failing to reach the requested state after | |
4282 | * multiple retries; else will return 0 in case of success. | |
4283 | **/ | |
4284 | static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable) | |
4285 | { | |
4286 | int i; | |
4287 | u32 tx_reg; | |
4288 | ||
4289 | for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { | |
4290 | tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q)); | |
4291 | if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) | |
4292 | break; | |
4293 | ||
f98a2006 | 4294 | usleep_range(10, 20); |
23527308 NP |
4295 | } |
4296 | if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) | |
4297 | return -ETIMEDOUT; | |
4298 | ||
4299 | return 0; | |
4300 | } | |
4301 | ||
c768e490 JK |
4302 | /** |
4303 | * i40e_control_tx_q - Start or stop a particular Tx queue | |
4304 | * @pf: the PF structure | |
4305 | * @pf_q: the PF queue to configure | |
4306 | * @enable: start or stop the queue | |
4307 | * | |
4308 | * This function enables or disables a single queue. Note that any delay | |
4309 | * required after the operation is expected to be handled by the caller of | |
4310 | * this function. | |
4311 | **/ | |
4312 | static void i40e_control_tx_q(struct i40e_pf *pf, int pf_q, bool enable) | |
4313 | { | |
4314 | struct i40e_hw *hw = &pf->hw; | |
4315 | u32 tx_reg; | |
4316 | int i; | |
4317 | ||
4318 | /* warn the TX unit of coming changes */ | |
4319 | i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable); | |
4320 | if (!enable) | |
4321 | usleep_range(10, 20); | |
4322 | ||
4323 | for (i = 0; i < I40E_QTX_ENA_WAIT_COUNT; i++) { | |
4324 | tx_reg = rd32(hw, I40E_QTX_ENA(pf_q)); | |
4325 | if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) == | |
4326 | ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1)) | |
4327 | break; | |
4328 | usleep_range(1000, 2000); | |
4329 | } | |
4330 | ||
4331 | /* Skip if the queue is already in the requested state */ | |
4332 | if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) | |
4333 | return; | |
4334 | ||
4335 | /* turn on/off the queue */ | |
4336 | if (enable) { | |
4337 | wr32(hw, I40E_QTX_HEAD(pf_q), 0); | |
4338 | tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK; | |
4339 | } else { | |
4340 | tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; | |
4341 | } | |
4342 | ||
4343 | wr32(hw, I40E_QTX_ENA(pf_q), tx_reg); | |
4344 | } | |
4345 | ||
74608d17 BT |
4346 | /** |
4347 | * i40e_control_wait_tx_q - Start/stop Tx queue and wait for completion | |
4348 | * @seid: VSI SEID | |
4349 | * @pf: the PF structure | |
4350 | * @pf_q: the PF queue to configure | |
4351 | * @is_xdp: true if the queue is used for XDP | |
4352 | * @enable: start or stop the queue | |
4353 | **/ | |
d0fda04d HR |
4354 | int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, |
4355 | bool is_xdp, bool enable) | |
74608d17 BT |
4356 | { |
4357 | int ret; | |
4358 | ||
4359 | i40e_control_tx_q(pf, pf_q, enable); | |
4360 | ||
4361 | /* wait for the change to finish */ | |
4362 | ret = i40e_pf_txq_wait(pf, pf_q, enable); | |
4363 | if (ret) { | |
4364 | dev_info(&pf->pdev->dev, | |
4365 | "VSI seid %d %sTx ring %d %sable timeout\n", | |
4366 | seid, (is_xdp ? "XDP " : ""), pf_q, | |
4367 | (enable ? "en" : "dis")); | |
4368 | } | |
4369 | ||
4370 | return ret; | |
4371 | } | |
4372 | ||
41c445ff JB |
4373 | /** |
4374 | * i40e_vsi_control_tx - Start or stop a VSI's rings | |
4375 | * @vsi: the VSI being configured | |
4376 | * @enable: start or stop the rings | |
4377 | **/ | |
4378 | static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable) | |
4379 | { | |
4380 | struct i40e_pf *pf = vsi->back; | |
c768e490 | 4381 | int i, pf_q, ret = 0; |
41c445ff JB |
4382 | |
4383 | pf_q = vsi->base_queue; | |
4384 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
74608d17 BT |
4385 | ret = i40e_control_wait_tx_q(vsi->seid, pf, |
4386 | pf_q, | |
4387 | false /*is xdp*/, enable); | |
4388 | if (ret) | |
4389 | break; | |
351499ab | 4390 | |
74608d17 BT |
4391 | if (!i40e_enabled_xdp_vsi(vsi)) |
4392 | continue; | |
4393 | ||
4394 | ret = i40e_control_wait_tx_q(vsi->seid, pf, | |
4395 | pf_q + vsi->alloc_queue_pairs, | |
4396 | true /*is xdp*/, enable); | |
4397 | if (ret) | |
23527308 | 4398 | break; |
41c445ff | 4399 | } |
23527308 NP |
4400 | return ret; |
4401 | } | |
4402 | ||
4403 | /** | |
4404 | * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled | |
4405 | * @pf: the PF being configured | |
4406 | * @pf_q: the PF queue | |
4407 | * @enable: enable or disable state of the queue | |
4408 | * | |
4409 | * This routine will wait for the given Rx queue of the PF to reach the | |
4410 | * enabled or disabled state. | |
4411 | * Returns -ETIMEDOUT in case of failing to reach the requested state after | |
4412 | * multiple retries; else will return 0 in case of success. | |
4413 | **/ | |
4414 | static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable) | |
4415 | { | |
4416 | int i; | |
4417 | u32 rx_reg; | |
4418 | ||
4419 | for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { | |
4420 | rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q)); | |
4421 | if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) | |
4422 | break; | |
4423 | ||
f98a2006 | 4424 | usleep_range(10, 20); |
23527308 NP |
4425 | } |
4426 | if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) | |
4427 | return -ETIMEDOUT; | |
7134f9ce | 4428 | |
41c445ff JB |
4429 | return 0; |
4430 | } | |
4431 | ||
c768e490 JK |
4432 | /** |
4433 | * i40e_control_rx_q - Start or stop a particular Rx queue | |
4434 | * @pf: the PF structure | |
4435 | * @pf_q: the PF queue to configure | |
4436 | * @enable: start or stop the queue | |
4437 | * | |
d0fda04d HR |
4438 | * This function enables or disables a single queue. Note that |
4439 | * any delay required after the operation is expected to be | |
4440 | * handled by the caller of this function. | |
c768e490 JK |
4441 | **/ |
4442 | static void i40e_control_rx_q(struct i40e_pf *pf, int pf_q, bool enable) | |
4443 | { | |
4444 | struct i40e_hw *hw = &pf->hw; | |
4445 | u32 rx_reg; | |
4446 | int i; | |
4447 | ||
4448 | for (i = 0; i < I40E_QTX_ENA_WAIT_COUNT; i++) { | |
4449 | rx_reg = rd32(hw, I40E_QRX_ENA(pf_q)); | |
4450 | if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) == | |
4451 | ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1)) | |
4452 | break; | |
4453 | usleep_range(1000, 2000); | |
4454 | } | |
4455 | ||
4456 | /* Skip if the queue is already in the requested state */ | |
4457 | if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) | |
4458 | return; | |
4459 | ||
4460 | /* turn on/off the queue */ | |
4461 | if (enable) | |
4462 | rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK; | |
4463 | else | |
4464 | rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; | |
4465 | ||
4466 | wr32(hw, I40E_QRX_ENA(pf_q), rx_reg); | |
4467 | } | |
4468 | ||
d0fda04d HR |
4469 | /** |
4470 | * i40e_control_wait_rx_q | |
4471 | * @pf: the PF structure | |
4472 | * @pf_q: queue being configured | |
4473 | * @enable: start or stop the rings | |
4474 | * | |
4475 | * This function enables or disables a single queue along with waiting | |
4476 | * for the change to finish. The caller of this function should handle | |
4477 | * the delays needed in the case of disabling queues. | |
4478 | **/ | |
4479 | int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable) | |
4480 | { | |
4481 | int ret = 0; | |
4482 | ||
4483 | i40e_control_rx_q(pf, pf_q, enable); | |
4484 | ||
4485 | /* wait for the change to finish */ | |
4486 | ret = i40e_pf_rxq_wait(pf, pf_q, enable); | |
4487 | if (ret) | |
4488 | return ret; | |
4489 | ||
4490 | return ret; | |
4491 | } | |
4492 | ||
41c445ff JB |
4493 | /** |
4494 | * i40e_vsi_control_rx - Start or stop a VSI's rings | |
4495 | * @vsi: the VSI being configured | |
4496 | * @enable: start or stop the rings | |
4497 | **/ | |
4498 | static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable) | |
4499 | { | |
4500 | struct i40e_pf *pf = vsi->back; | |
c768e490 | 4501 | int i, pf_q, ret = 0; |
41c445ff JB |
4502 | |
4503 | pf_q = vsi->base_queue; | |
4504 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
d0fda04d | 4505 | ret = i40e_control_wait_rx_q(pf, pf_q, enable); |
23527308 NP |
4506 | if (ret) { |
4507 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
4508 | "VSI seid %d Rx ring %d %sable timeout\n", |
4509 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
23527308 | 4510 | break; |
41c445ff JB |
4511 | } |
4512 | } | |
4513 | ||
d08a9f6c WC |
4514 | /* Due to HW errata, on Rx disable only, the register can indicate done |
4515 | * before it really is. Needs 50ms to be sure | |
4516 | */ | |
4517 | if (!enable) | |
4518 | mdelay(50); | |
4519 | ||
23527308 | 4520 | return ret; |
41c445ff JB |
4521 | } |
4522 | ||
4523 | /** | |
3aa7b74d | 4524 | * i40e_vsi_start_rings - Start a VSI's rings |
41c445ff | 4525 | * @vsi: the VSI being configured |
41c445ff | 4526 | **/ |
3aa7b74d | 4527 | int i40e_vsi_start_rings(struct i40e_vsi *vsi) |
41c445ff | 4528 | { |
3b867b28 | 4529 | int ret = 0; |
41c445ff JB |
4530 | |
4531 | /* do rx first for enable and last for disable */ | |
3aa7b74d FS |
4532 | ret = i40e_vsi_control_rx(vsi, true); |
4533 | if (ret) | |
4534 | return ret; | |
4535 | ret = i40e_vsi_control_tx(vsi, true); | |
41c445ff JB |
4536 | |
4537 | return ret; | |
4538 | } | |
4539 | ||
3aa7b74d FS |
4540 | /** |
4541 | * i40e_vsi_stop_rings - Stop a VSI's rings | |
4542 | * @vsi: the VSI being configured | |
4543 | **/ | |
4544 | void i40e_vsi_stop_rings(struct i40e_vsi *vsi) | |
4545 | { | |
3480756f | 4546 | /* When port TX is suspended, don't wait */ |
0da36b97 | 4547 | if (test_bit(__I40E_PORT_SUSPENDED, vsi->back->state)) |
3480756f JK |
4548 | return i40e_vsi_stop_rings_no_wait(vsi); |
4549 | ||
3aa7b74d FS |
4550 | /* do rx first for enable and last for disable |
4551 | * Ignore return value, we need to shutdown whatever we can | |
4552 | */ | |
4553 | i40e_vsi_control_tx(vsi, false); | |
4554 | i40e_vsi_control_rx(vsi, false); | |
4555 | } | |
4556 | ||
e4b433f4 JK |
4557 | /** |
4558 | * i40e_vsi_stop_rings_no_wait - Stop a VSI's rings and do not delay | |
4559 | * @vsi: the VSI being shutdown | |
4560 | * | |
4561 | * This function stops all the rings for a VSI but does not delay to verify | |
4562 | * that rings have been disabled. It is expected that the caller is shutting | |
4563 | * down multiple VSIs at once and will delay together for all the VSIs after | |
4564 | * initiating the shutdown. This is particularly useful for shutting down lots | |
4565 | * of VFs together. Otherwise, a large delay can be incurred while configuring | |
4566 | * each VSI in serial. | |
4567 | **/ | |
4568 | void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi) | |
4569 | { | |
4570 | struct i40e_pf *pf = vsi->back; | |
4571 | int i, pf_q; | |
4572 | ||
4573 | pf_q = vsi->base_queue; | |
4574 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
4575 | i40e_control_tx_q(pf, pf_q, false); | |
4576 | i40e_control_rx_q(pf, pf_q, false); | |
4577 | } | |
4578 | } | |
4579 | ||
41c445ff JB |
4580 | /** |
4581 | * i40e_vsi_free_irq - Free the irq association with the OS | |
4582 | * @vsi: the VSI being configured | |
4583 | **/ | |
4584 | static void i40e_vsi_free_irq(struct i40e_vsi *vsi) | |
4585 | { | |
4586 | struct i40e_pf *pf = vsi->back; | |
4587 | struct i40e_hw *hw = &pf->hw; | |
4588 | int base = vsi->base_vector; | |
4589 | u32 val, qp; | |
4590 | int i; | |
4591 | ||
4592 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
4593 | if (!vsi->q_vectors) | |
4594 | return; | |
4595 | ||
63741846 SN |
4596 | if (!vsi->irqs_ready) |
4597 | return; | |
4598 | ||
4599 | vsi->irqs_ready = false; | |
41c445ff | 4600 | for (i = 0; i < vsi->num_q_vectors; i++) { |
96db776a AB |
4601 | int irq_num; |
4602 | u16 vector; | |
4603 | ||
4604 | vector = i + base; | |
4605 | irq_num = pf->msix_entries[vector].vector; | |
41c445ff JB |
4606 | |
4607 | /* free only the irqs that were actually requested */ | |
78681b1f SN |
4608 | if (!vsi->q_vectors[i] || |
4609 | !vsi->q_vectors[i]->num_ringpairs) | |
41c445ff JB |
4610 | continue; |
4611 | ||
96db776a AB |
4612 | /* clear the affinity notifier in the IRQ descriptor */ |
4613 | irq_set_affinity_notifier(irq_num, NULL); | |
759dc4a7 | 4614 | /* remove our suggested affinity mask for this IRQ */ |
96db776a AB |
4615 | irq_set_affinity_hint(irq_num, NULL); |
4616 | synchronize_irq(irq_num); | |
4617 | free_irq(irq_num, vsi->q_vectors[i]); | |
41c445ff JB |
4618 | |
4619 | /* Tear down the interrupt queue link list | |
4620 | * | |
4621 | * We know that they come in pairs and always | |
4622 | * the Rx first, then the Tx. To clear the | |
4623 | * link list, stick the EOL value into the | |
4624 | * next_q field of the registers. | |
4625 | */ | |
4626 | val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1)); | |
4627 | qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) | |
4628 | >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4629 | val |= I40E_QUEUE_END_OF_LIST | |
4630 | << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4631 | wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val); | |
4632 | ||
4633 | while (qp != I40E_QUEUE_END_OF_LIST) { | |
4634 | u32 next; | |
4635 | ||
4636 | val = rd32(hw, I40E_QINT_RQCTL(qp)); | |
4637 | ||
4638 | val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | | |
4639 | I40E_QINT_RQCTL_MSIX0_INDX_MASK | | |
4640 | I40E_QINT_RQCTL_CAUSE_ENA_MASK | | |
4641 | I40E_QINT_RQCTL_INTEVENT_MASK); | |
4642 | ||
4643 | val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | | |
4644 | I40E_QINT_RQCTL_NEXTQ_INDX_MASK); | |
4645 | ||
4646 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
4647 | ||
4648 | val = rd32(hw, I40E_QINT_TQCTL(qp)); | |
4649 | ||
4650 | next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK) | |
4651 | >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT; | |
4652 | ||
4653 | val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | | |
4654 | I40E_QINT_TQCTL_MSIX0_INDX_MASK | | |
4655 | I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
4656 | I40E_QINT_TQCTL_INTEVENT_MASK); | |
4657 | ||
4658 | val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | | |
4659 | I40E_QINT_TQCTL_NEXTQ_INDX_MASK); | |
4660 | ||
4661 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
4662 | qp = next; | |
4663 | } | |
4664 | } | |
4665 | } else { | |
4666 | free_irq(pf->pdev->irq, pf); | |
4667 | ||
4668 | val = rd32(hw, I40E_PFINT_LNKLST0); | |
4669 | qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) | |
4670 | >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4671 | val |= I40E_QUEUE_END_OF_LIST | |
4672 | << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; | |
4673 | wr32(hw, I40E_PFINT_LNKLST0, val); | |
4674 | ||
4675 | val = rd32(hw, I40E_QINT_RQCTL(qp)); | |
4676 | val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | | |
4677 | I40E_QINT_RQCTL_MSIX0_INDX_MASK | | |
4678 | I40E_QINT_RQCTL_CAUSE_ENA_MASK | | |
4679 | I40E_QINT_RQCTL_INTEVENT_MASK); | |
4680 | ||
4681 | val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | | |
4682 | I40E_QINT_RQCTL_NEXTQ_INDX_MASK); | |
4683 | ||
4684 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
4685 | ||
4686 | val = rd32(hw, I40E_QINT_TQCTL(qp)); | |
4687 | ||
4688 | val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | | |
4689 | I40E_QINT_TQCTL_MSIX0_INDX_MASK | | |
4690 | I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
4691 | I40E_QINT_TQCTL_INTEVENT_MASK); | |
4692 | ||
4693 | val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | | |
4694 | I40E_QINT_TQCTL_NEXTQ_INDX_MASK); | |
4695 | ||
4696 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
4697 | } | |
4698 | } | |
4699 | ||
493fb300 AD |
4700 | /** |
4701 | * i40e_free_q_vector - Free memory allocated for specific interrupt vector | |
4702 | * @vsi: the VSI being configured | |
4703 | * @v_idx: Index of vector to be freed | |
4704 | * | |
4705 | * This function frees the memory allocated to the q_vector. In addition if | |
4706 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4707 | * to freeing the q_vector. | |
4708 | **/ | |
4709 | static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx) | |
4710 | { | |
4711 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; | |
cd0b6fa6 | 4712 | struct i40e_ring *ring; |
493fb300 AD |
4713 | |
4714 | if (!q_vector) | |
4715 | return; | |
4716 | ||
4717 | /* disassociate q_vector from rings */ | |
cd0b6fa6 AD |
4718 | i40e_for_each_ring(ring, q_vector->tx) |
4719 | ring->q_vector = NULL; | |
4720 | ||
4721 | i40e_for_each_ring(ring, q_vector->rx) | |
4722 | ring->q_vector = NULL; | |
493fb300 AD |
4723 | |
4724 | /* only VSI w/ an associated netdev is set up w/ NAPI */ | |
4725 | if (vsi->netdev) | |
4726 | netif_napi_del(&q_vector->napi); | |
4727 | ||
4728 | vsi->q_vectors[v_idx] = NULL; | |
4729 | ||
4730 | kfree_rcu(q_vector, rcu); | |
4731 | } | |
4732 | ||
41c445ff JB |
4733 | /** |
4734 | * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors | |
4735 | * @vsi: the VSI being un-configured | |
4736 | * | |
4737 | * This frees the memory allocated to the q_vectors and | |
4738 | * deletes references to the NAPI struct. | |
4739 | **/ | |
4740 | static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi) | |
4741 | { | |
4742 | int v_idx; | |
4743 | ||
493fb300 AD |
4744 | for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) |
4745 | i40e_free_q_vector(vsi, v_idx); | |
41c445ff JB |
4746 | } |
4747 | ||
4748 | /** | |
4749 | * i40e_reset_interrupt_capability - Disable interrupt setup in OS | |
4750 | * @pf: board private structure | |
4751 | **/ | |
4752 | static void i40e_reset_interrupt_capability(struct i40e_pf *pf) | |
4753 | { | |
4754 | /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */ | |
4755 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
4756 | pci_disable_msix(pf->pdev); | |
4757 | kfree(pf->msix_entries); | |
4758 | pf->msix_entries = NULL; | |
3b444399 SN |
4759 | kfree(pf->irq_pile); |
4760 | pf->irq_pile = NULL; | |
41c445ff JB |
4761 | } else if (pf->flags & I40E_FLAG_MSI_ENABLED) { |
4762 | pci_disable_msi(pf->pdev); | |
4763 | } | |
4764 | pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED); | |
4765 | } | |
4766 | ||
4767 | /** | |
4768 | * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
4769 | * @pf: board private structure | |
4770 | * | |
4771 | * We go through and clear interrupt specific resources and reset the structure | |
4772 | * to pre-load conditions | |
4773 | **/ | |
4774 | static void i40e_clear_interrupt_scheme(struct i40e_pf *pf) | |
4775 | { | |
4776 | int i; | |
4777 | ||
c17401a1 | 4778 | i40e_free_misc_vector(pf); |
e147758d | 4779 | |
e3219ce6 ASJ |
4780 | i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector, |
4781 | I40E_IWARP_IRQ_PILE_ID); | |
4782 | ||
41c445ff | 4783 | i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1); |
505682cd | 4784 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
4785 | if (pf->vsi[i]) |
4786 | i40e_vsi_free_q_vectors(pf->vsi[i]); | |
4787 | i40e_reset_interrupt_capability(pf); | |
4788 | } | |
4789 | ||
4790 | /** | |
4791 | * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI | |
4792 | * @vsi: the VSI being configured | |
4793 | **/ | |
4794 | static void i40e_napi_enable_all(struct i40e_vsi *vsi) | |
4795 | { | |
4796 | int q_idx; | |
4797 | ||
4798 | if (!vsi->netdev) | |
4799 | return; | |
4800 | ||
13a8cd19 AD |
4801 | for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) { |
4802 | struct i40e_q_vector *q_vector = vsi->q_vectors[q_idx]; | |
4803 | ||
4804 | if (q_vector->rx.ring || q_vector->tx.ring) | |
4805 | napi_enable(&q_vector->napi); | |
4806 | } | |
41c445ff JB |
4807 | } |
4808 | ||
4809 | /** | |
4810 | * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI | |
4811 | * @vsi: the VSI being configured | |
4812 | **/ | |
4813 | static void i40e_napi_disable_all(struct i40e_vsi *vsi) | |
4814 | { | |
4815 | int q_idx; | |
4816 | ||
4817 | if (!vsi->netdev) | |
4818 | return; | |
4819 | ||
13a8cd19 AD |
4820 | for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) { |
4821 | struct i40e_q_vector *q_vector = vsi->q_vectors[q_idx]; | |
4822 | ||
4823 | if (q_vector->rx.ring || q_vector->tx.ring) | |
4824 | napi_disable(&q_vector->napi); | |
4825 | } | |
41c445ff JB |
4826 | } |
4827 | ||
90ef8d47 SN |
4828 | /** |
4829 | * i40e_vsi_close - Shut down a VSI | |
4830 | * @vsi: the vsi to be quelled | |
4831 | **/ | |
4832 | static void i40e_vsi_close(struct i40e_vsi *vsi) | |
4833 | { | |
0ef2d5af | 4834 | struct i40e_pf *pf = vsi->back; |
0da36b97 | 4835 | if (!test_and_set_bit(__I40E_VSI_DOWN, vsi->state)) |
90ef8d47 SN |
4836 | i40e_down(vsi); |
4837 | i40e_vsi_free_irq(vsi); | |
4838 | i40e_vsi_free_tx_resources(vsi); | |
4839 | i40e_vsi_free_rx_resources(vsi); | |
92faef85 | 4840 | vsi->current_netdev_flags = 0; |
5f76a704 | 4841 | set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state); |
0da36b97 | 4842 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
5f76a704 | 4843 | set_bit(__I40E_CLIENT_RESET, pf->state); |
90ef8d47 SN |
4844 | } |
4845 | ||
41c445ff JB |
4846 | /** |
4847 | * i40e_quiesce_vsi - Pause a given VSI | |
4848 | * @vsi: the VSI being paused | |
4849 | **/ | |
4850 | static void i40e_quiesce_vsi(struct i40e_vsi *vsi) | |
4851 | { | |
0da36b97 | 4852 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) |
41c445ff JB |
4853 | return; |
4854 | ||
0da36b97 | 4855 | set_bit(__I40E_VSI_NEEDS_RESTART, vsi->state); |
6995b36c | 4856 | if (vsi->netdev && netif_running(vsi->netdev)) |
41c445ff | 4857 | vsi->netdev->netdev_ops->ndo_stop(vsi->netdev); |
6995b36c | 4858 | else |
90ef8d47 | 4859 | i40e_vsi_close(vsi); |
41c445ff JB |
4860 | } |
4861 | ||
4862 | /** | |
4863 | * i40e_unquiesce_vsi - Resume a given VSI | |
4864 | * @vsi: the VSI being resumed | |
4865 | **/ | |
4866 | static void i40e_unquiesce_vsi(struct i40e_vsi *vsi) | |
4867 | { | |
0da36b97 | 4868 | if (!test_and_clear_bit(__I40E_VSI_NEEDS_RESTART, vsi->state)) |
41c445ff JB |
4869 | return; |
4870 | ||
41c445ff JB |
4871 | if (vsi->netdev && netif_running(vsi->netdev)) |
4872 | vsi->netdev->netdev_ops->ndo_open(vsi->netdev); | |
4873 | else | |
8276f757 | 4874 | i40e_vsi_open(vsi); /* this clears the DOWN bit */ |
41c445ff JB |
4875 | } |
4876 | ||
4877 | /** | |
4878 | * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF | |
4879 | * @pf: the PF | |
4880 | **/ | |
4881 | static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf) | |
4882 | { | |
4883 | int v; | |
4884 | ||
505682cd | 4885 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
4886 | if (pf->vsi[v]) |
4887 | i40e_quiesce_vsi(pf->vsi[v]); | |
4888 | } | |
4889 | } | |
4890 | ||
4891 | /** | |
4892 | * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF | |
4893 | * @pf: the PF | |
4894 | **/ | |
4895 | static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf) | |
4896 | { | |
4897 | int v; | |
4898 | ||
505682cd | 4899 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
4900 | if (pf->vsi[v]) |
4901 | i40e_unquiesce_vsi(pf->vsi[v]); | |
4902 | } | |
4903 | } | |
4904 | ||
69129dc3 | 4905 | /** |
3fe06f41 | 4906 | * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled |
69129dc3 NP |
4907 | * @vsi: the VSI being configured |
4908 | * | |
af26ce2d | 4909 | * Wait until all queues on a given VSI have been disabled. |
69129dc3 | 4910 | **/ |
e4b433f4 | 4911 | int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi) |
69129dc3 NP |
4912 | { |
4913 | struct i40e_pf *pf = vsi->back; | |
4914 | int i, pf_q, ret; | |
4915 | ||
4916 | pf_q = vsi->base_queue; | |
4917 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
af26ce2d | 4918 | /* Check and wait for the Tx queue */ |
69129dc3 NP |
4919 | ret = i40e_pf_txq_wait(pf, pf_q, false); |
4920 | if (ret) { | |
4921 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
4922 | "VSI seid %d Tx ring %d disable timeout\n", |
4923 | vsi->seid, pf_q); | |
69129dc3 NP |
4924 | return ret; |
4925 | } | |
74608d17 BT |
4926 | |
4927 | if (!i40e_enabled_xdp_vsi(vsi)) | |
4928 | goto wait_rx; | |
4929 | ||
4930 | /* Check and wait for the XDP Tx queue */ | |
4931 | ret = i40e_pf_txq_wait(pf, pf_q + vsi->alloc_queue_pairs, | |
4932 | false); | |
4933 | if (ret) { | |
4934 | dev_info(&pf->pdev->dev, | |
4935 | "VSI seid %d XDP Tx ring %d disable timeout\n", | |
4936 | vsi->seid, pf_q); | |
4937 | return ret; | |
4938 | } | |
4939 | wait_rx: | |
4940 | /* Check and wait for the Rx queue */ | |
3fe06f41 NP |
4941 | ret = i40e_pf_rxq_wait(pf, pf_q, false); |
4942 | if (ret) { | |
4943 | dev_info(&pf->pdev->dev, | |
4944 | "VSI seid %d Rx ring %d disable timeout\n", | |
4945 | vsi->seid, pf_q); | |
4946 | return ret; | |
4947 | } | |
4948 | } | |
4949 | ||
69129dc3 NP |
4950 | return 0; |
4951 | } | |
4952 | ||
e4b433f4 | 4953 | #ifdef CONFIG_I40E_DCB |
69129dc3 | 4954 | /** |
3fe06f41 | 4955 | * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled |
69129dc3 NP |
4956 | * @pf: the PF |
4957 | * | |
3fe06f41 | 4958 | * This function waits for the queues to be in disabled state for all the |
69129dc3 NP |
4959 | * VSIs that are managed by this PF. |
4960 | **/ | |
3fe06f41 | 4961 | static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf) |
69129dc3 NP |
4962 | { |
4963 | int v, ret = 0; | |
4964 | ||
4965 | for (v = 0; v < pf->hw.func_caps.num_vsis; v++) { | |
c76cb6ed | 4966 | if (pf->vsi[v]) { |
3fe06f41 | 4967 | ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]); |
69129dc3 NP |
4968 | if (ret) |
4969 | break; | |
4970 | } | |
4971 | } | |
4972 | ||
4973 | return ret; | |
4974 | } | |
4975 | ||
4976 | #endif | |
b03a8c1f | 4977 | |
63d7e5a4 NP |
4978 | /** |
4979 | * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP | |
b40c82e6 | 4980 | * @pf: pointer to PF |
63d7e5a4 NP |
4981 | * |
4982 | * Get TC map for ISCSI PF type that will include iSCSI TC | |
4983 | * and LAN TC. | |
4984 | **/ | |
4985 | static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf) | |
4986 | { | |
4987 | struct i40e_dcb_app_priority_table app; | |
4988 | struct i40e_hw *hw = &pf->hw; | |
4989 | u8 enabled_tc = 1; /* TC0 is always enabled */ | |
4990 | u8 tc, i; | |
4991 | /* Get the iSCSI APP TLV */ | |
4992 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
4993 | ||
4994 | for (i = 0; i < dcbcfg->numapps; i++) { | |
4995 | app = dcbcfg->app[i]; | |
4996 | if (app.selector == I40E_APP_SEL_TCPIP && | |
4997 | app.protocolid == I40E_APP_PROTOID_ISCSI) { | |
4998 | tc = dcbcfg->etscfg.prioritytable[app.priority]; | |
75f5cea9 | 4999 | enabled_tc |= BIT(tc); |
63d7e5a4 NP |
5000 | break; |
5001 | } | |
5002 | } | |
5003 | ||
5004 | return enabled_tc; | |
5005 | } | |
5006 | ||
41c445ff JB |
5007 | /** |
5008 | * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config | |
5009 | * @dcbcfg: the corresponding DCBx configuration structure | |
5010 | * | |
5011 | * Return the number of TCs from given DCBx configuration | |
5012 | **/ | |
5013 | static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg) | |
5014 | { | |
fbfe12c6 | 5015 | int i, tc_unused = 0; |
078b5876 | 5016 | u8 num_tc = 0; |
fbfe12c6 | 5017 | u8 ret = 0; |
41c445ff JB |
5018 | |
5019 | /* Scan the ETS Config Priority Table to find | |
5020 | * traffic class enabled for a given priority | |
fbfe12c6 | 5021 | * and create a bitmask of enabled TCs |
41c445ff | 5022 | */ |
fbfe12c6 DE |
5023 | for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) |
5024 | num_tc |= BIT(dcbcfg->etscfg.prioritytable[i]); | |
41c445ff | 5025 | |
fbfe12c6 DE |
5026 | /* Now scan the bitmask to check for |
5027 | * contiguous TCs starting with TC0 | |
41c445ff | 5028 | */ |
fbfe12c6 DE |
5029 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
5030 | if (num_tc & BIT(i)) { | |
5031 | if (!tc_unused) { | |
5032 | ret++; | |
5033 | } else { | |
5034 | pr_err("Non-contiguous TC - Disabling DCB\n"); | |
5035 | return 1; | |
5036 | } | |
5037 | } else { | |
5038 | tc_unused = 1; | |
5039 | } | |
5040 | } | |
5041 | ||
5042 | /* There is always at least TC0 */ | |
5043 | if (!ret) | |
5044 | ret = 1; | |
5045 | ||
5046 | return ret; | |
41c445ff JB |
5047 | } |
5048 | ||
5049 | /** | |
5050 | * i40e_dcb_get_enabled_tc - Get enabled traffic classes | |
5051 | * @dcbcfg: the corresponding DCBx configuration structure | |
5052 | * | |
5053 | * Query the current DCB configuration and return the number of | |
5054 | * traffic classes enabled from the given DCBX config | |
5055 | **/ | |
5056 | static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg) | |
5057 | { | |
5058 | u8 num_tc = i40e_dcb_get_num_tc(dcbcfg); | |
5059 | u8 enabled_tc = 1; | |
5060 | u8 i; | |
5061 | ||
5062 | for (i = 0; i < num_tc; i++) | |
41a1d04b | 5063 | enabled_tc |= BIT(i); |
41c445ff JB |
5064 | |
5065 | return enabled_tc; | |
5066 | } | |
5067 | ||
a9ce82f7 AN |
5068 | /** |
5069 | * i40e_mqprio_get_enabled_tc - Get enabled traffic classes | |
5070 | * @pf: PF being queried | |
5071 | * | |
5072 | * Query the current MQPRIO configuration and return the number of | |
5073 | * traffic classes enabled. | |
5074 | **/ | |
5075 | static u8 i40e_mqprio_get_enabled_tc(struct i40e_pf *pf) | |
5076 | { | |
5077 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
5078 | u8 num_tc = vsi->mqprio_qopt.qopt.num_tc; | |
5079 | u8 enabled_tc = 1, i; | |
5080 | ||
5081 | for (i = 1; i < num_tc; i++) | |
5082 | enabled_tc |= BIT(i); | |
5083 | return enabled_tc; | |
5084 | } | |
5085 | ||
41c445ff JB |
5086 | /** |
5087 | * i40e_pf_get_num_tc - Get enabled traffic classes for PF | |
5088 | * @pf: PF being queried | |
5089 | * | |
5090 | * Return number of traffic classes enabled for the given PF | |
5091 | **/ | |
5092 | static u8 i40e_pf_get_num_tc(struct i40e_pf *pf) | |
5093 | { | |
5094 | struct i40e_hw *hw = &pf->hw; | |
52a08caa | 5095 | u8 i, enabled_tc = 1; |
41c445ff JB |
5096 | u8 num_tc = 0; |
5097 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
5098 | ||
a9ce82f7 AN |
5099 | if (pf->flags & I40E_FLAG_TC_MQPRIO) |
5100 | return pf->vsi[pf->lan_vsi]->mqprio_qopt.qopt.num_tc; | |
5101 | ||
5102 | /* If neither MQPRIO nor DCB is enabled, then always use single TC */ | |
41c445ff JB |
5103 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) |
5104 | return 1; | |
5105 | ||
63d7e5a4 NP |
5106 | /* SFP mode will be enabled for all TCs on port */ |
5107 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) | |
5108 | return i40e_dcb_get_num_tc(dcbcfg); | |
5109 | ||
41c445ff | 5110 | /* MFP mode return count of enabled TCs for this PF */ |
63d7e5a4 NP |
5111 | if (pf->hw.func_caps.iscsi) |
5112 | enabled_tc = i40e_get_iscsi_tc_map(pf); | |
5113 | else | |
fc51de96 | 5114 | return 1; /* Only TC0 */ |
41c445ff | 5115 | |
63d7e5a4 | 5116 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
75f5cea9 | 5117 | if (enabled_tc & BIT(i)) |
63d7e5a4 NP |
5118 | num_tc++; |
5119 | } | |
5120 | return num_tc; | |
41c445ff JB |
5121 | } |
5122 | ||
41c445ff JB |
5123 | /** |
5124 | * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes | |
5125 | * @pf: PF being queried | |
5126 | * | |
5127 | * Return a bitmap for enabled traffic classes for this PF. | |
5128 | **/ | |
5129 | static u8 i40e_pf_get_tc_map(struct i40e_pf *pf) | |
5130 | { | |
a9ce82f7 AN |
5131 | if (pf->flags & I40E_FLAG_TC_MQPRIO) |
5132 | return i40e_mqprio_get_enabled_tc(pf); | |
5133 | ||
5134 | /* If neither MQPRIO nor DCB is enabled for this PF then just return | |
5135 | * default TC | |
5136 | */ | |
41c445ff | 5137 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) |
ea6acb7e | 5138 | return I40E_DEFAULT_TRAFFIC_CLASS; |
41c445ff | 5139 | |
41c445ff | 5140 | /* SFP mode we want PF to be enabled for all TCs */ |
63d7e5a4 NP |
5141 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) |
5142 | return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config); | |
5143 | ||
fc51de96 | 5144 | /* MFP enabled and iSCSI PF type */ |
63d7e5a4 NP |
5145 | if (pf->hw.func_caps.iscsi) |
5146 | return i40e_get_iscsi_tc_map(pf); | |
5147 | else | |
ea6acb7e | 5148 | return I40E_DEFAULT_TRAFFIC_CLASS; |
41c445ff JB |
5149 | } |
5150 | ||
5151 | /** | |
5152 | * i40e_vsi_get_bw_info - Query VSI BW Information | |
5153 | * @vsi: the VSI being queried | |
5154 | * | |
5155 | * Returns 0 on success, negative value on failure | |
5156 | **/ | |
5157 | static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi) | |
5158 | { | |
5159 | struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0}; | |
5160 | struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0}; | |
5161 | struct i40e_pf *pf = vsi->back; | |
5162 | struct i40e_hw *hw = &pf->hw; | |
f1c7e72e | 5163 | i40e_status ret; |
41c445ff | 5164 | u32 tc_bw_max; |
41c445ff JB |
5165 | int i; |
5166 | ||
5167 | /* Get the VSI level BW configuration */ | |
f1c7e72e SN |
5168 | ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL); |
5169 | if (ret) { | |
41c445ff | 5170 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
5171 | "couldn't get PF vsi bw config, err %s aq_err %s\n", |
5172 | i40e_stat_str(&pf->hw, ret), | |
5173 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
dcae29be | 5174 | return -EINVAL; |
41c445ff JB |
5175 | } |
5176 | ||
5177 | /* Get the VSI level BW configuration per TC */ | |
f1c7e72e SN |
5178 | ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config, |
5179 | NULL); | |
5180 | if (ret) { | |
41c445ff | 5181 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
5182 | "couldn't get PF vsi ets bw config, err %s aq_err %s\n", |
5183 | i40e_stat_str(&pf->hw, ret), | |
5184 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
dcae29be | 5185 | return -EINVAL; |
41c445ff JB |
5186 | } |
5187 | ||
5188 | if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) { | |
5189 | dev_info(&pf->pdev->dev, | |
5190 | "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n", | |
5191 | bw_config.tc_valid_bits, | |
5192 | bw_ets_config.tc_valid_bits); | |
5193 | /* Still continuing */ | |
5194 | } | |
5195 | ||
5196 | vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit); | |
5197 | vsi->bw_max_quanta = bw_config.max_bw; | |
5198 | tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) | | |
5199 | (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16); | |
5200 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
5201 | vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i]; | |
5202 | vsi->bw_ets_limit_credits[i] = | |
5203 | le16_to_cpu(bw_ets_config.credits[i]); | |
5204 | /* 3 bits out of 4 for each TC */ | |
5205 | vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7); | |
5206 | } | |
078b5876 | 5207 | |
dcae29be | 5208 | return 0; |
41c445ff JB |
5209 | } |
5210 | ||
5211 | /** | |
5212 | * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC | |
5213 | * @vsi: the VSI being configured | |
5214 | * @enabled_tc: TC bitmap | |
f5254429 | 5215 | * @bw_share: BW shared credits per TC |
41c445ff JB |
5216 | * |
5217 | * Returns 0 on success, negative value on failure | |
5218 | **/ | |
dcae29be | 5219 | static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc, |
41c445ff JB |
5220 | u8 *bw_share) |
5221 | { | |
5222 | struct i40e_aqc_configure_vsi_tc_bw_data bw_data; | |
fa38e30a | 5223 | struct i40e_pf *pf = vsi->back; |
f1c7e72e | 5224 | i40e_status ret; |
dcae29be | 5225 | int i; |
41c445ff | 5226 | |
fa38e30a MS |
5227 | /* There is no need to reset BW when mqprio mode is on. */ |
5228 | if (pf->flags & I40E_FLAG_TC_MQPRIO) | |
a9ce82f7 | 5229 | return 0; |
fa38e30a | 5230 | if (!vsi->mqprio_qopt.qopt.hw && !(pf->flags & I40E_FLAG_DCB_ENABLED)) { |
2027d4de AN |
5231 | ret = i40e_set_bw_limit(vsi, vsi->seid, 0); |
5232 | if (ret) | |
fa38e30a | 5233 | dev_info(&pf->pdev->dev, |
2027d4de AN |
5234 | "Failed to reset tx rate for vsi->seid %u\n", |
5235 | vsi->seid); | |
5236 | return ret; | |
5237 | } | |
41c445ff JB |
5238 | bw_data.tc_valid_bits = enabled_tc; |
5239 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
5240 | bw_data.tc_bw_credits[i] = bw_share[i]; | |
5241 | ||
fa38e30a | 5242 | ret = i40e_aq_config_vsi_tc_bw(&pf->hw, vsi->seid, &bw_data, NULL); |
f1c7e72e | 5243 | if (ret) { |
fa38e30a | 5244 | dev_info(&pf->pdev->dev, |
69bfb110 | 5245 | "AQ command Config VSI BW allocation per TC failed = %d\n", |
fa38e30a | 5246 | pf->hw.aq.asq_last_status); |
dcae29be | 5247 | return -EINVAL; |
41c445ff JB |
5248 | } |
5249 | ||
5250 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
5251 | vsi->info.qs_handle[i] = bw_data.qs_handles[i]; | |
5252 | ||
dcae29be | 5253 | return 0; |
41c445ff JB |
5254 | } |
5255 | ||
5256 | /** | |
5257 | * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration | |
5258 | * @vsi: the VSI being configured | |
5259 | * @enabled_tc: TC map to be enabled | |
5260 | * | |
5261 | **/ | |
5262 | static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc) | |
5263 | { | |
5264 | struct net_device *netdev = vsi->netdev; | |
5265 | struct i40e_pf *pf = vsi->back; | |
5266 | struct i40e_hw *hw = &pf->hw; | |
5267 | u8 netdev_tc = 0; | |
5268 | int i; | |
5269 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
5270 | ||
5271 | if (!netdev) | |
5272 | return; | |
5273 | ||
5274 | if (!enabled_tc) { | |
5275 | netdev_reset_tc(netdev); | |
5276 | return; | |
5277 | } | |
5278 | ||
5279 | /* Set up actual enabled TCs on the VSI */ | |
5280 | if (netdev_set_num_tc(netdev, vsi->tc_config.numtc)) | |
5281 | return; | |
5282 | ||
5283 | /* set per TC queues for the VSI */ | |
5284 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
5285 | /* Only set TC queues for enabled tcs | |
5286 | * | |
5287 | * e.g. For a VSI that has TC0 and TC3 enabled the | |
5288 | * enabled_tc bitmap would be 0x00001001; the driver | |
5289 | * will set the numtc for netdev as 2 that will be | |
5290 | * referenced by the netdev layer as TC 0 and 1. | |
5291 | */ | |
75f5cea9 | 5292 | if (vsi->tc_config.enabled_tc & BIT(i)) |
41c445ff JB |
5293 | netdev_set_tc_queue(netdev, |
5294 | vsi->tc_config.tc_info[i].netdev_tc, | |
5295 | vsi->tc_config.tc_info[i].qcount, | |
5296 | vsi->tc_config.tc_info[i].qoffset); | |
5297 | } | |
5298 | ||
a9ce82f7 AN |
5299 | if (pf->flags & I40E_FLAG_TC_MQPRIO) |
5300 | return; | |
5301 | ||
41c445ff JB |
5302 | /* Assign UP2TC map for the VSI */ |
5303 | for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) { | |
5304 | /* Get the actual TC# for the UP */ | |
5305 | u8 ets_tc = dcbcfg->etscfg.prioritytable[i]; | |
5306 | /* Get the mapped netdev TC# for the UP */ | |
5307 | netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc; | |
5308 | netdev_set_prio_tc_map(netdev, i, netdev_tc); | |
5309 | } | |
5310 | } | |
5311 | ||
5312 | /** | |
5313 | * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map | |
5314 | * @vsi: the VSI being configured | |
5315 | * @ctxt: the ctxt buffer returned from AQ VSI update param command | |
5316 | **/ | |
5317 | static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi, | |
5318 | struct i40e_vsi_context *ctxt) | |
5319 | { | |
5320 | /* copy just the sections touched not the entire info | |
5321 | * since not all sections are valid as returned by | |
5322 | * update vsi params | |
5323 | */ | |
5324 | vsi->info.mapping_flags = ctxt->info.mapping_flags; | |
5325 | memcpy(&vsi->info.queue_mapping, | |
5326 | &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping)); | |
5327 | memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping, | |
5328 | sizeof(vsi->info.tc_mapping)); | |
5329 | } | |
5330 | ||
5331 | /** | |
5332 | * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map | |
5333 | * @vsi: VSI to be configured | |
5334 | * @enabled_tc: TC bitmap | |
5335 | * | |
5336 | * This configures a particular VSI for TCs that are mapped to the | |
5337 | * given TC bitmap. It uses default bandwidth share for TCs across | |
5338 | * VSIs to configure TC for a particular VSI. | |
5339 | * | |
5340 | * NOTE: | |
5341 | * It is expected that the VSI queues have been quisced before calling | |
5342 | * this function. | |
5343 | **/ | |
5344 | static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc) | |
5345 | { | |
5346 | u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0}; | |
d8a87856 MW |
5347 | struct i40e_pf *pf = vsi->back; |
5348 | struct i40e_hw *hw = &pf->hw; | |
41c445ff JB |
5349 | struct i40e_vsi_context ctxt; |
5350 | int ret = 0; | |
5351 | int i; | |
5352 | ||
5353 | /* Check if enabled_tc is same as existing or new TCs */ | |
a9ce82f7 AN |
5354 | if (vsi->tc_config.enabled_tc == enabled_tc && |
5355 | vsi->mqprio_qopt.mode != TC_MQPRIO_MODE_CHANNEL) | |
41c445ff JB |
5356 | return ret; |
5357 | ||
5358 | /* Enable ETS TCs with equal BW Share for now across all VSIs */ | |
5359 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 5360 | if (enabled_tc & BIT(i)) |
41c445ff JB |
5361 | bw_share[i] = 1; |
5362 | } | |
5363 | ||
5364 | ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share); | |
5365 | if (ret) { | |
d8a87856 MW |
5366 | struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0}; |
5367 | ||
bc73234b | 5368 | dev_info(&pf->pdev->dev, |
41c445ff JB |
5369 | "Failed configuring TC map %d for VSI %d\n", |
5370 | enabled_tc, vsi->seid); | |
d8a87856 MW |
5371 | ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, |
5372 | &bw_config, NULL); | |
5373 | if (ret) { | |
5374 | dev_info(&pf->pdev->dev, | |
5375 | "Failed querying vsi bw info, err %s aq_err %s\n", | |
5376 | i40e_stat_str(hw, ret), | |
5377 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
5378 | goto out; | |
5379 | } | |
5380 | if ((bw_config.tc_valid_bits & enabled_tc) != enabled_tc) { | |
5381 | u8 valid_tc = bw_config.tc_valid_bits & enabled_tc; | |
5382 | ||
5383 | if (!valid_tc) | |
5384 | valid_tc = bw_config.tc_valid_bits; | |
5385 | /* Always enable TC0, no matter what */ | |
5386 | valid_tc |= 1; | |
5387 | dev_info(&pf->pdev->dev, | |
5388 | "Requested tc 0x%x, but FW reports 0x%x as valid. Attempting to use 0x%x.\n", | |
5389 | enabled_tc, bw_config.tc_valid_bits, valid_tc); | |
5390 | enabled_tc = valid_tc; | |
5391 | } | |
5392 | ||
5393 | ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share); | |
5394 | if (ret) { | |
5395 | dev_err(&pf->pdev->dev, | |
5396 | "Unable to configure TC map %d for VSI %d\n", | |
5397 | enabled_tc, vsi->seid); | |
5398 | goto out; | |
5399 | } | |
41c445ff JB |
5400 | } |
5401 | ||
5402 | /* Update Queue Pairs Mapping for currently enabled UPs */ | |
5403 | ctxt.seid = vsi->seid; | |
5404 | ctxt.pf_num = vsi->back->hw.pf_id; | |
5405 | ctxt.vf_num = 0; | |
5406 | ctxt.uplink_seid = vsi->uplink_seid; | |
1a2f6248 | 5407 | ctxt.info = vsi->info; |
a9ce82f7 AN |
5408 | if (vsi->back->flags & I40E_FLAG_TC_MQPRIO) { |
5409 | ret = i40e_vsi_setup_queue_map_mqprio(vsi, &ctxt, enabled_tc); | |
5410 | if (ret) | |
5411 | goto out; | |
5412 | } else { | |
5413 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); | |
5414 | } | |
41c445ff | 5415 | |
a9ce82f7 AN |
5416 | /* On destroying the qdisc, reset vsi->rss_size, as number of enabled |
5417 | * queues changed. | |
5418 | */ | |
5419 | if (!vsi->mqprio_qopt.qopt.hw && vsi->reconfig_rss) { | |
5420 | vsi->rss_size = min_t(int, vsi->back->alloc_rss_size, | |
5421 | vsi->num_queue_pairs); | |
5422 | ret = i40e_vsi_config_rss(vsi); | |
5423 | if (ret) { | |
5424 | dev_info(&vsi->back->pdev->dev, | |
5425 | "Failed to reconfig rss for num_queues\n"); | |
5426 | return ret; | |
5427 | } | |
5428 | vsi->reconfig_rss = false; | |
5429 | } | |
e3219ce6 ASJ |
5430 | if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { |
5431 | ctxt.info.valid_sections |= | |
5432 | cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); | |
5433 | ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA; | |
5434 | } | |
5435 | ||
a9ce82f7 AN |
5436 | /* Update the VSI after updating the VSI queue-mapping |
5437 | * information | |
5438 | */ | |
bc73234b | 5439 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); |
41c445ff | 5440 | if (ret) { |
bc73234b | 5441 | dev_info(&pf->pdev->dev, |
f1c7e72e | 5442 | "Update vsi tc config failed, err %s aq_err %s\n", |
bc73234b MW |
5443 | i40e_stat_str(hw, ret), |
5444 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
41c445ff JB |
5445 | goto out; |
5446 | } | |
5447 | /* update the local VSI info with updated queue map */ | |
5448 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
5449 | vsi->info.valid_sections = 0; | |
5450 | ||
5451 | /* Update current VSI BW information */ | |
5452 | ret = i40e_vsi_get_bw_info(vsi); | |
5453 | if (ret) { | |
bc73234b | 5454 | dev_info(&pf->pdev->dev, |
f1c7e72e | 5455 | "Failed updating vsi bw info, err %s aq_err %s\n", |
bc73234b MW |
5456 | i40e_stat_str(hw, ret), |
5457 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
41c445ff JB |
5458 | goto out; |
5459 | } | |
5460 | ||
5461 | /* Update the netdev TC setup */ | |
5462 | i40e_vsi_config_netdev_tc(vsi, enabled_tc); | |
5463 | out: | |
5464 | return ret; | |
5465 | } | |
5466 | ||
4e3b35b0 | 5467 | /** |
5ecae412 AN |
5468 | * i40e_get_link_speed - Returns link speed for the interface |
5469 | * @vsi: VSI to be configured | |
4e3b35b0 | 5470 | * |
4e3b35b0 | 5471 | **/ |
3758d2c7 | 5472 | static int i40e_get_link_speed(struct i40e_vsi *vsi) |
4e3b35b0 | 5473 | { |
5ecae412 | 5474 | struct i40e_pf *pf = vsi->back; |
4e3b35b0 | 5475 | |
5ecae412 AN |
5476 | switch (pf->hw.phy.link_info.link_speed) { |
5477 | case I40E_LINK_SPEED_40GB: | |
5478 | return 40000; | |
5479 | case I40E_LINK_SPEED_25GB: | |
5480 | return 25000; | |
5481 | case I40E_LINK_SPEED_20GB: | |
5482 | return 20000; | |
5483 | case I40E_LINK_SPEED_10GB: | |
5484 | return 10000; | |
5485 | case I40E_LINK_SPEED_1GB: | |
5486 | return 1000; | |
5487 | default: | |
5488 | return -EINVAL; | |
4e3b35b0 | 5489 | } |
4e3b35b0 NP |
5490 | } |
5491 | ||
4e3b35b0 | 5492 | /** |
5ecae412 AN |
5493 | * i40e_set_bw_limit - setup BW limit for Tx traffic based on max_tx_rate |
5494 | * @vsi: VSI to be configured | |
5495 | * @seid: seid of the channel/VSI | |
5496 | * @max_tx_rate: max TX rate to be configured as BW limit | |
4e3b35b0 | 5497 | * |
5ecae412 | 5498 | * Helper function to set BW limit for a given VSI |
4e3b35b0 | 5499 | **/ |
5ecae412 | 5500 | int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate) |
4e3b35b0 | 5501 | { |
5ecae412 | 5502 | struct i40e_pf *pf = vsi->back; |
6c32e0d9 | 5503 | u64 credits = 0; |
5ecae412 AN |
5504 | int speed = 0; |
5505 | int ret = 0; | |
4e3b35b0 | 5506 | |
5ecae412 AN |
5507 | speed = i40e_get_link_speed(vsi); |
5508 | if (max_tx_rate > speed) { | |
5509 | dev_err(&pf->pdev->dev, | |
5510 | "Invalid max tx rate %llu specified for VSI seid %d.", | |
5511 | max_tx_rate, seid); | |
5512 | return -EINVAL; | |
5513 | } | |
5514 | if (max_tx_rate && max_tx_rate < 50) { | |
5515 | dev_warn(&pf->pdev->dev, | |
5516 | "Setting max tx rate to minimum usable value of 50Mbps.\n"); | |
5517 | max_tx_rate = 50; | |
5518 | } | |
5519 | ||
5520 | /* Tx rate credits are in values of 50Mbps, 0 is disabled */ | |
6c32e0d9 AB |
5521 | credits = max_tx_rate; |
5522 | do_div(credits, I40E_BW_CREDIT_DIVISOR); | |
5523 | ret = i40e_aq_config_vsi_bw_limit(&pf->hw, seid, credits, | |
5ecae412 AN |
5524 | I40E_MAX_BW_INACTIVE_ACCUM, NULL); |
5525 | if (ret) | |
5526 | dev_err(&pf->pdev->dev, | |
5527 | "Failed set tx rate (%llu Mbps) for vsi->seid %u, err %s aq_err %s\n", | |
5528 | max_tx_rate, seid, i40e_stat_str(&pf->hw, ret), | |
5529 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
5530 | return ret; | |
5531 | } | |
5532 | ||
8f88b303 AN |
5533 | /** |
5534 | * i40e_remove_queue_channels - Remove queue channels for the TCs | |
5535 | * @vsi: VSI to be configured | |
5536 | * | |
5537 | * Remove queue channels for the TCs | |
5538 | **/ | |
5539 | static void i40e_remove_queue_channels(struct i40e_vsi *vsi) | |
5540 | { | |
2f4b411a AN |
5541 | enum i40e_admin_queue_err last_aq_status; |
5542 | struct i40e_cloud_filter *cfilter; | |
8f88b303 | 5543 | struct i40e_channel *ch, *ch_tmp; |
2f4b411a AN |
5544 | struct i40e_pf *pf = vsi->back; |
5545 | struct hlist_node *node; | |
8f88b303 AN |
5546 | int ret, i; |
5547 | ||
5548 | /* Reset rss size that was stored when reconfiguring rss for | |
5549 | * channel VSIs with non-power-of-2 queue count. | |
5550 | */ | |
5551 | vsi->current_rss_size = 0; | |
5552 | ||
5553 | /* perform cleanup for channels if they exist */ | |
5554 | if (list_empty(&vsi->ch_list)) | |
5555 | return; | |
5556 | ||
5557 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) { | |
5558 | struct i40e_vsi *p_vsi; | |
5559 | ||
5560 | list_del(&ch->list); | |
5561 | p_vsi = ch->parent_vsi; | |
5562 | if (!p_vsi || !ch->initialized) { | |
5563 | kfree(ch); | |
4e3b35b0 | 5564 | continue; |
8f88b303 AN |
5565 | } |
5566 | /* Reset queue contexts */ | |
5567 | for (i = 0; i < ch->num_queue_pairs; i++) { | |
5568 | struct i40e_ring *tx_ring, *rx_ring; | |
5569 | u16 pf_q; | |
5570 | ||
5571 | pf_q = ch->base_queue + i; | |
5572 | tx_ring = vsi->tx_rings[pf_q]; | |
5573 | tx_ring->ch = NULL; | |
5574 | ||
5575 | rx_ring = vsi->rx_rings[pf_q]; | |
5576 | rx_ring->ch = NULL; | |
5577 | } | |
5578 | ||
2027d4de AN |
5579 | /* Reset BW configured for this VSI via mqprio */ |
5580 | ret = i40e_set_bw_limit(vsi, ch->seid, 0); | |
5581 | if (ret) | |
5582 | dev_info(&vsi->back->pdev->dev, | |
5583 | "Failed to reset tx rate for ch->seid %u\n", | |
5584 | ch->seid); | |
5585 | ||
2f4b411a AN |
5586 | /* delete cloud filters associated with this channel */ |
5587 | hlist_for_each_entry_safe(cfilter, node, | |
5588 | &pf->cloud_filter_list, cloud_node) { | |
5589 | if (cfilter->seid != ch->seid) | |
5590 | continue; | |
5591 | ||
5592 | hash_del(&cfilter->cloud_node); | |
5593 | if (cfilter->dst_port) | |
5594 | ret = i40e_add_del_cloud_filter_big_buf(vsi, | |
5595 | cfilter, | |
5596 | false); | |
5597 | else | |
5598 | ret = i40e_add_del_cloud_filter(vsi, cfilter, | |
5599 | false); | |
5600 | last_aq_status = pf->hw.aq.asq_last_status; | |
5601 | if (ret) | |
5602 | dev_info(&pf->pdev->dev, | |
5603 | "Failed to delete cloud filter, err %s aq_err %s\n", | |
5604 | i40e_stat_str(&pf->hw, ret), | |
5605 | i40e_aq_str(&pf->hw, last_aq_status)); | |
5606 | kfree(cfilter); | |
5607 | } | |
5608 | ||
8f88b303 AN |
5609 | /* delete VSI from FW */ |
5610 | ret = i40e_aq_delete_element(&vsi->back->hw, ch->seid, | |
5611 | NULL); | |
5612 | if (ret) | |
5613 | dev_err(&vsi->back->pdev->dev, | |
5614 | "unable to remove channel (%d) for parent VSI(%d)\n", | |
5615 | ch->seid, p_vsi->seid); | |
5616 | kfree(ch); | |
5617 | } | |
5618 | INIT_LIST_HEAD(&vsi->ch_list); | |
5619 | } | |
5620 | ||
5621 | /** | |
5622 | * i40e_is_any_channel - channel exist or not | |
5623 | * @vsi: ptr to VSI to which channels are associated with | |
5624 | * | |
5625 | * Returns true or false if channel(s) exist for associated VSI or not | |
5626 | **/ | |
5627 | static bool i40e_is_any_channel(struct i40e_vsi *vsi) | |
5628 | { | |
5629 | struct i40e_channel *ch, *ch_tmp; | |
5630 | ||
5631 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) { | |
5632 | if (ch->initialized) | |
5633 | return true; | |
5634 | } | |
5635 | ||
5636 | return false; | |
5637 | } | |
5638 | ||
5639 | /** | |
5640 | * i40e_get_max_queues_for_channel | |
5641 | * @vsi: ptr to VSI to which channels are associated with | |
5642 | * | |
5643 | * Helper function which returns max value among the queue counts set on the | |
5644 | * channels/TCs created. | |
5645 | **/ | |
5646 | static int i40e_get_max_queues_for_channel(struct i40e_vsi *vsi) | |
5647 | { | |
5648 | struct i40e_channel *ch, *ch_tmp; | |
5649 | int max = 0; | |
5650 | ||
5651 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) { | |
5652 | if (!ch->initialized) | |
5653 | continue; | |
5654 | if (ch->num_queue_pairs > max) | |
5655 | max = ch->num_queue_pairs; | |
5656 | } | |
5657 | ||
5658 | return max; | |
5659 | } | |
5660 | ||
5661 | /** | |
5662 | * i40e_validate_num_queues - validate num_queues w.r.t channel | |
5663 | * @pf: ptr to PF device | |
5664 | * @num_queues: number of queues | |
5665 | * @vsi: the parent VSI | |
5666 | * @reconfig_rss: indicates should the RSS be reconfigured or not | |
5667 | * | |
5668 | * This function validates number of queues in the context of new channel | |
5669 | * which is being established and determines if RSS should be reconfigured | |
5670 | * or not for parent VSI. | |
5671 | **/ | |
5672 | static int i40e_validate_num_queues(struct i40e_pf *pf, int num_queues, | |
5673 | struct i40e_vsi *vsi, bool *reconfig_rss) | |
5674 | { | |
5675 | int max_ch_queues; | |
5676 | ||
5677 | if (!reconfig_rss) | |
5678 | return -EINVAL; | |
5679 | ||
5680 | *reconfig_rss = false; | |
8f88b303 AN |
5681 | if (vsi->current_rss_size) { |
5682 | if (num_queues > vsi->current_rss_size) { | |
5683 | dev_dbg(&pf->pdev->dev, | |
5684 | "Error: num_queues (%d) > vsi's current_size(%d)\n", | |
5685 | num_queues, vsi->current_rss_size); | |
5686 | return -EINVAL; | |
5687 | } else if ((num_queues < vsi->current_rss_size) && | |
5688 | (!is_power_of_2(num_queues))) { | |
5689 | dev_dbg(&pf->pdev->dev, | |
5690 | "Error: num_queues (%d) < vsi's current_size(%d), but not power of 2\n", | |
5691 | num_queues, vsi->current_rss_size); | |
5692 | return -EINVAL; | |
5693 | } | |
5694 | } | |
5695 | ||
5696 | if (!is_power_of_2(num_queues)) { | |
5697 | /* Find the max num_queues configured for channel if channel | |
5698 | * exist. | |
5699 | * if channel exist, then enforce 'num_queues' to be more than | |
5700 | * max ever queues configured for channel. | |
5701 | */ | |
5702 | max_ch_queues = i40e_get_max_queues_for_channel(vsi); | |
5703 | if (num_queues < max_ch_queues) { | |
5704 | dev_dbg(&pf->pdev->dev, | |
5705 | "Error: num_queues (%d) < max queues configured for channel(%d)\n", | |
5706 | num_queues, max_ch_queues); | |
5707 | return -EINVAL; | |
5708 | } | |
5709 | *reconfig_rss = true; | |
5710 | } | |
5711 | ||
5712 | return 0; | |
5713 | } | |
5714 | ||
5715 | /** | |
5716 | * i40e_vsi_reconfig_rss - reconfig RSS based on specified rss_size | |
5717 | * @vsi: the VSI being setup | |
5718 | * @rss_size: size of RSS, accordingly LUT gets reprogrammed | |
5719 | * | |
5720 | * This function reconfigures RSS by reprogramming LUTs using 'rss_size' | |
5721 | **/ | |
5722 | static int i40e_vsi_reconfig_rss(struct i40e_vsi *vsi, u16 rss_size) | |
5723 | { | |
5724 | struct i40e_pf *pf = vsi->back; | |
5725 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
5726 | struct i40e_hw *hw = &pf->hw; | |
5727 | int local_rss_size; | |
5728 | u8 *lut; | |
5729 | int ret; | |
5730 | ||
5731 | if (!vsi->rss_size) | |
5732 | return -EINVAL; | |
5733 | ||
5734 | if (rss_size > vsi->rss_size) | |
5735 | return -EINVAL; | |
5736 | ||
5737 | local_rss_size = min_t(int, vsi->rss_size, rss_size); | |
5738 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); | |
5739 | if (!lut) | |
5740 | return -ENOMEM; | |
5741 | ||
5742 | /* Ignoring user configured lut if there is one */ | |
5743 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, local_rss_size); | |
5744 | ||
5745 | /* Use user configured hash key if there is one, otherwise | |
5746 | * use default. | |
5747 | */ | |
5748 | if (vsi->rss_hkey_user) | |
5749 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
5750 | else | |
5751 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
5752 | ||
5753 | ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size); | |
5754 | if (ret) { | |
5755 | dev_info(&pf->pdev->dev, | |
5756 | "Cannot set RSS lut, err %s aq_err %s\n", | |
5757 | i40e_stat_str(hw, ret), | |
5758 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
5759 | kfree(lut); | |
5760 | return ret; | |
5761 | } | |
5762 | kfree(lut); | |
5763 | ||
5764 | /* Do the update w.r.t. storing rss_size */ | |
5765 | if (!vsi->orig_rss_size) | |
5766 | vsi->orig_rss_size = vsi->rss_size; | |
5767 | vsi->current_rss_size = local_rss_size; | |
5768 | ||
5769 | return ret; | |
5770 | } | |
5771 | ||
5772 | /** | |
5773 | * i40e_channel_setup_queue_map - Setup a channel queue map | |
5774 | * @pf: ptr to PF device | |
5775 | * @vsi: the VSI being setup | |
5776 | * @ctxt: VSI context structure | |
5777 | * @ch: ptr to channel structure | |
5778 | * | |
5779 | * Setup queue map for a specific channel | |
5780 | **/ | |
5781 | static void i40e_channel_setup_queue_map(struct i40e_pf *pf, | |
5782 | struct i40e_vsi_context *ctxt, | |
5783 | struct i40e_channel *ch) | |
5784 | { | |
5785 | u16 qcount, qmap, sections = 0; | |
5786 | u8 offset = 0; | |
5787 | int pow; | |
5788 | ||
5789 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
5790 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
5791 | ||
5792 | qcount = min_t(int, ch->num_queue_pairs, pf->num_lan_msix); | |
5793 | ch->num_queue_pairs = qcount; | |
5794 | ||
5795 | /* find the next higher power-of-2 of num queue pairs */ | |
5796 | pow = ilog2(qcount); | |
5797 | if (!is_power_of_2(qcount)) | |
5798 | pow++; | |
5799 | ||
5800 | qmap = (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
5801 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
5802 | ||
5803 | /* Setup queue TC[0].qmap for given VSI context */ | |
5804 | ctxt->info.tc_mapping[0] = cpu_to_le16(qmap); | |
5805 | ||
5806 | ctxt->info.up_enable_bits = 0x1; /* TC0 enabled */ | |
5807 | ctxt->info.mapping_flags |= cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
5808 | ctxt->info.queue_mapping[0] = cpu_to_le16(ch->base_queue); | |
5809 | ctxt->info.valid_sections |= cpu_to_le16(sections); | |
5810 | } | |
5811 | ||
5812 | /** | |
5813 | * i40e_add_channel - add a channel by adding VSI | |
5814 | * @pf: ptr to PF device | |
5815 | * @uplink_seid: underlying HW switching element (VEB) ID | |
5816 | * @ch: ptr to channel structure | |
5817 | * | |
5818 | * Add a channel (VSI) using add_vsi and queue_map | |
5819 | **/ | |
5820 | static int i40e_add_channel(struct i40e_pf *pf, u16 uplink_seid, | |
5821 | struct i40e_channel *ch) | |
5822 | { | |
5823 | struct i40e_hw *hw = &pf->hw; | |
5824 | struct i40e_vsi_context ctxt; | |
5825 | u8 enabled_tc = 0x1; /* TC0 enabled */ | |
5826 | int ret; | |
5827 | ||
5828 | if (ch->type != I40E_VSI_VMDQ2) { | |
5829 | dev_info(&pf->pdev->dev, | |
5830 | "add new vsi failed, ch->type %d\n", ch->type); | |
5831 | return -EINVAL; | |
5832 | } | |
5833 | ||
5834 | memset(&ctxt, 0, sizeof(ctxt)); | |
5835 | ctxt.pf_num = hw->pf_id; | |
5836 | ctxt.vf_num = 0; | |
5837 | ctxt.uplink_seid = uplink_seid; | |
5838 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; | |
5839 | if (ch->type == I40E_VSI_VMDQ2) | |
5840 | ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; | |
5841 | ||
5842 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) { | |
5843 | ctxt.info.valid_sections |= | |
5844 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
5845 | ctxt.info.switch_id = | |
5846 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
5847 | } | |
5848 | ||
5849 | /* Set queue map for a given VSI context */ | |
5850 | i40e_channel_setup_queue_map(pf, &ctxt, ch); | |
5851 | ||
5852 | /* Now time to create VSI */ | |
5853 | ret = i40e_aq_add_vsi(hw, &ctxt, NULL); | |
5854 | if (ret) { | |
5855 | dev_info(&pf->pdev->dev, | |
5856 | "add new vsi failed, err %s aq_err %s\n", | |
5857 | i40e_stat_str(&pf->hw, ret), | |
5858 | i40e_aq_str(&pf->hw, | |
5859 | pf->hw.aq.asq_last_status)); | |
5860 | return -ENOENT; | |
5861 | } | |
5862 | ||
5863 | /* Success, update channel */ | |
5864 | ch->enabled_tc = enabled_tc; | |
5865 | ch->seid = ctxt.seid; | |
5866 | ch->vsi_number = ctxt.vsi_number; | |
5867 | ch->stat_counter_idx = cpu_to_le16(ctxt.info.stat_counter_idx); | |
5868 | ||
5869 | /* copy just the sections touched not the entire info | |
5870 | * since not all sections are valid as returned by | |
5871 | * update vsi params | |
5872 | */ | |
5873 | ch->info.mapping_flags = ctxt.info.mapping_flags; | |
5874 | memcpy(&ch->info.queue_mapping, | |
5875 | &ctxt.info.queue_mapping, sizeof(ctxt.info.queue_mapping)); | |
5876 | memcpy(&ch->info.tc_mapping, ctxt.info.tc_mapping, | |
5877 | sizeof(ctxt.info.tc_mapping)); | |
5878 | ||
5879 | return 0; | |
5880 | } | |
5881 | ||
5882 | static int i40e_channel_config_bw(struct i40e_vsi *vsi, struct i40e_channel *ch, | |
5883 | u8 *bw_share) | |
5884 | { | |
5885 | struct i40e_aqc_configure_vsi_tc_bw_data bw_data; | |
5886 | i40e_status ret; | |
5887 | int i; | |
5888 | ||
5889 | bw_data.tc_valid_bits = ch->enabled_tc; | |
5890 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
5891 | bw_data.tc_bw_credits[i] = bw_share[i]; | |
5892 | ||
5893 | ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, ch->seid, | |
5894 | &bw_data, NULL); | |
5895 | if (ret) { | |
5896 | dev_info(&vsi->back->pdev->dev, | |
5897 | "Config VSI BW allocation per TC failed, aq_err: %d for new_vsi->seid %u\n", | |
5898 | vsi->back->hw.aq.asq_last_status, ch->seid); | |
5899 | return -EINVAL; | |
5900 | } | |
5901 | ||
5902 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
5903 | ch->info.qs_handle[i] = bw_data.qs_handles[i]; | |
5904 | ||
5905 | return 0; | |
5906 | } | |
5907 | ||
5908 | /** | |
5909 | * i40e_channel_config_tx_ring - config TX ring associated with new channel | |
5910 | * @pf: ptr to PF device | |
5911 | * @vsi: the VSI being setup | |
5912 | * @ch: ptr to channel structure | |
5913 | * | |
5914 | * Configure TX rings associated with channel (VSI) since queues are being | |
5915 | * from parent VSI. | |
5916 | **/ | |
5917 | static int i40e_channel_config_tx_ring(struct i40e_pf *pf, | |
5918 | struct i40e_vsi *vsi, | |
5919 | struct i40e_channel *ch) | |
5920 | { | |
5921 | i40e_status ret; | |
5922 | int i; | |
5923 | u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0}; | |
5924 | ||
5925 | /* Enable ETS TCs with equal BW Share for now across all VSIs */ | |
5926 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
5927 | if (ch->enabled_tc & BIT(i)) | |
5928 | bw_share[i] = 1; | |
5929 | } | |
5930 | ||
5931 | /* configure BW for new VSI */ | |
5932 | ret = i40e_channel_config_bw(vsi, ch, bw_share); | |
5933 | if (ret) { | |
5934 | dev_info(&vsi->back->pdev->dev, | |
5935 | "Failed configuring TC map %d for channel (seid %u)\n", | |
5936 | ch->enabled_tc, ch->seid); | |
5937 | return ret; | |
5938 | } | |
5939 | ||
5940 | for (i = 0; i < ch->num_queue_pairs; i++) { | |
5941 | struct i40e_ring *tx_ring, *rx_ring; | |
5942 | u16 pf_q; | |
5943 | ||
5944 | pf_q = ch->base_queue + i; | |
5945 | ||
5946 | /* Get to TX ring ptr of main VSI, for re-setup TX queue | |
5947 | * context | |
5948 | */ | |
5949 | tx_ring = vsi->tx_rings[pf_q]; | |
5950 | tx_ring->ch = ch; | |
5951 | ||
5952 | /* Get the RX ring ptr */ | |
5953 | rx_ring = vsi->rx_rings[pf_q]; | |
5954 | rx_ring->ch = ch; | |
5955 | } | |
5956 | ||
5957 | return 0; | |
5958 | } | |
5959 | ||
5960 | /** | |
5961 | * i40e_setup_hw_channel - setup new channel | |
5962 | * @pf: ptr to PF device | |
5963 | * @vsi: the VSI being setup | |
5964 | * @ch: ptr to channel structure | |
5965 | * @uplink_seid: underlying HW switching element (VEB) ID | |
5966 | * @type: type of channel to be created (VMDq2/VF) | |
5967 | * | |
5968 | * Setup new channel (VSI) based on specified type (VMDq2/VF) | |
5969 | * and configures TX rings accordingly | |
5970 | **/ | |
5971 | static inline int i40e_setup_hw_channel(struct i40e_pf *pf, | |
5972 | struct i40e_vsi *vsi, | |
5973 | struct i40e_channel *ch, | |
5974 | u16 uplink_seid, u8 type) | |
5975 | { | |
5976 | int ret; | |
5977 | ||
5978 | ch->initialized = false; | |
5979 | ch->base_queue = vsi->next_base_queue; | |
5980 | ch->type = type; | |
5981 | ||
5982 | /* Proceed with creation of channel (VMDq2) VSI */ | |
5983 | ret = i40e_add_channel(pf, uplink_seid, ch); | |
5984 | if (ret) { | |
5985 | dev_info(&pf->pdev->dev, | |
5986 | "failed to add_channel using uplink_seid %u\n", | |
5987 | uplink_seid); | |
5988 | return ret; | |
5989 | } | |
5990 | ||
5991 | /* Mark the successful creation of channel */ | |
5992 | ch->initialized = true; | |
5993 | ||
5994 | /* Reconfigure TX queues using QTX_CTL register */ | |
5995 | ret = i40e_channel_config_tx_ring(pf, vsi, ch); | |
5996 | if (ret) { | |
5997 | dev_info(&pf->pdev->dev, | |
5998 | "failed to configure TX rings for channel %u\n", | |
5999 | ch->seid); | |
6000 | return ret; | |
6001 | } | |
6002 | ||
6003 | /* update 'next_base_queue' */ | |
6004 | vsi->next_base_queue = vsi->next_base_queue + ch->num_queue_pairs; | |
6005 | dev_dbg(&pf->pdev->dev, | |
6006 | "Added channel: vsi_seid %u, vsi_number %u, stat_counter_idx %u, num_queue_pairs %u, pf->next_base_queue %d\n", | |
6007 | ch->seid, ch->vsi_number, ch->stat_counter_idx, | |
6008 | ch->num_queue_pairs, | |
6009 | vsi->next_base_queue); | |
6010 | return ret; | |
6011 | } | |
6012 | ||
6013 | /** | |
6014 | * i40e_setup_channel - setup new channel using uplink element | |
6015 | * @pf: ptr to PF device | |
6016 | * @type: type of channel to be created (VMDq2/VF) | |
6017 | * @uplink_seid: underlying HW switching element (VEB) ID | |
6018 | * @ch: ptr to channel structure | |
6019 | * | |
6020 | * Setup new channel (VSI) based on specified type (VMDq2/VF) | |
6021 | * and uplink switching element (uplink_seid) | |
6022 | **/ | |
6023 | static bool i40e_setup_channel(struct i40e_pf *pf, struct i40e_vsi *vsi, | |
6024 | struct i40e_channel *ch) | |
6025 | { | |
6026 | u8 vsi_type; | |
6027 | u16 seid; | |
6028 | int ret; | |
6029 | ||
6030 | if (vsi->type == I40E_VSI_MAIN) { | |
6031 | vsi_type = I40E_VSI_VMDQ2; | |
6032 | } else { | |
6033 | dev_err(&pf->pdev->dev, "unsupported parent vsi type(%d)\n", | |
6034 | vsi->type); | |
6035 | return false; | |
6036 | } | |
6037 | ||
6038 | /* underlying switching element */ | |
6039 | seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
6040 | ||
6041 | /* create channel (VSI), configure TX rings */ | |
6042 | ret = i40e_setup_hw_channel(pf, vsi, ch, seid, vsi_type); | |
6043 | if (ret) { | |
6044 | dev_err(&pf->pdev->dev, "failed to setup hw_channel\n"); | |
6045 | return false; | |
6046 | } | |
6047 | ||
6048 | return ch->initialized ? true : false; | |
6049 | } | |
6050 | ||
2f4b411a AN |
6051 | /** |
6052 | * i40e_validate_and_set_switch_mode - sets up switch mode correctly | |
6053 | * @vsi: ptr to VSI which has PF backing | |
6054 | * | |
6055 | * Sets up switch mode correctly if it needs to be changed and perform | |
6056 | * what are allowed modes. | |
6057 | **/ | |
6058 | static int i40e_validate_and_set_switch_mode(struct i40e_vsi *vsi) | |
6059 | { | |
6060 | u8 mode; | |
6061 | struct i40e_pf *pf = vsi->back; | |
6062 | struct i40e_hw *hw = &pf->hw; | |
6063 | int ret; | |
6064 | ||
6065 | ret = i40e_get_capabilities(pf, i40e_aqc_opc_list_dev_capabilities); | |
6066 | if (ret) | |
6067 | return -EINVAL; | |
6068 | ||
6069 | if (hw->dev_caps.switch_mode) { | |
6070 | /* if switch mode is set, support mode2 (non-tunneled for | |
6071 | * cloud filter) for now | |
6072 | */ | |
6073 | u32 switch_mode = hw->dev_caps.switch_mode & | |
6074 | I40E_SWITCH_MODE_MASK; | |
6075 | if (switch_mode >= I40E_CLOUD_FILTER_MODE1) { | |
6076 | if (switch_mode == I40E_CLOUD_FILTER_MODE2) | |
6077 | return 0; | |
6078 | dev_err(&pf->pdev->dev, | |
6079 | "Invalid switch_mode (%d), only non-tunneled mode for cloud filter is supported\n", | |
6080 | hw->dev_caps.switch_mode); | |
6081 | return -EINVAL; | |
6082 | } | |
6083 | } | |
6084 | ||
6085 | /* Set Bit 7 to be valid */ | |
6086 | mode = I40E_AQ_SET_SWITCH_BIT7_VALID; | |
6087 | ||
64e711ca AN |
6088 | /* Set L4type for TCP support */ |
6089 | mode |= I40E_AQ_SET_SWITCH_L4_TYPE_TCP; | |
2f4b411a AN |
6090 | |
6091 | /* Set cloud filter mode */ | |
6092 | mode |= I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL; | |
6093 | ||
6094 | /* Prep mode field for set_switch_config */ | |
6095 | ret = i40e_aq_set_switch_config(hw, pf->last_sw_conf_flags, | |
6096 | pf->last_sw_conf_valid_flags, | |
6097 | mode, NULL); | |
6098 | if (ret && hw->aq.asq_last_status != I40E_AQ_RC_ESRCH) | |
6099 | dev_err(&pf->pdev->dev, | |
6100 | "couldn't set switch config bits, err %s aq_err %s\n", | |
6101 | i40e_stat_str(hw, ret), | |
6102 | i40e_aq_str(hw, | |
6103 | hw->aq.asq_last_status)); | |
6104 | ||
6105 | return ret; | |
6106 | } | |
6107 | ||
8f88b303 AN |
6108 | /** |
6109 | * i40e_create_queue_channel - function to create channel | |
6110 | * @vsi: VSI to be configured | |
6111 | * @ch: ptr to channel (it contains channel specific params) | |
6112 | * | |
6113 | * This function creates channel (VSI) using num_queues specified by user, | |
6114 | * reconfigs RSS if needed. | |
6115 | **/ | |
6116 | int i40e_create_queue_channel(struct i40e_vsi *vsi, | |
6117 | struct i40e_channel *ch) | |
6118 | { | |
6119 | struct i40e_pf *pf = vsi->back; | |
6120 | bool reconfig_rss; | |
6121 | int err; | |
6122 | ||
6123 | if (!ch) | |
6124 | return -EINVAL; | |
6125 | ||
6126 | if (!ch->num_queue_pairs) { | |
6127 | dev_err(&pf->pdev->dev, "Invalid num_queues requested: %d\n", | |
6128 | ch->num_queue_pairs); | |
6129 | return -EINVAL; | |
6130 | } | |
6131 | ||
6132 | /* validate user requested num_queues for channel */ | |
6133 | err = i40e_validate_num_queues(pf, ch->num_queue_pairs, vsi, | |
6134 | &reconfig_rss); | |
6135 | if (err) { | |
6136 | dev_info(&pf->pdev->dev, "Failed to validate num_queues (%d)\n", | |
6137 | ch->num_queue_pairs); | |
6138 | return -EINVAL; | |
6139 | } | |
6140 | ||
6141 | /* By default we are in VEPA mode, if this is the first VF/VMDq | |
6142 | * VSI to be added switch to VEB mode. | |
6143 | */ | |
6144 | if ((!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) || | |
6145 | (!i40e_is_any_channel(vsi))) { | |
6146 | if (!is_power_of_2(vsi->tc_config.tc_info[0].qcount)) { | |
6147 | dev_dbg(&pf->pdev->dev, | |
6148 | "Failed to create channel. Override queues (%u) not power of 2\n", | |
6149 | vsi->tc_config.tc_info[0].qcount); | |
6150 | return -EINVAL; | |
6151 | } | |
6152 | ||
6153 | if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) { | |
6154 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
6155 | ||
6156 | if (vsi->type == I40E_VSI_MAIN) { | |
6157 | if (pf->flags & I40E_FLAG_TC_MQPRIO) | |
6158 | i40e_do_reset(pf, I40E_PF_RESET_FLAG, | |
6159 | true); | |
6160 | else | |
6161 | i40e_do_reset_safe(pf, | |
6162 | I40E_PF_RESET_FLAG); | |
6163 | } | |
6164 | } | |
6165 | /* now onwards for main VSI, number of queues will be value | |
6166 | * of TC0's queue count | |
6167 | */ | |
6168 | } | |
6169 | ||
6170 | /* By this time, vsi->cnt_q_avail shall be set to non-zero and | |
6171 | * it should be more than num_queues | |
6172 | */ | |
6173 | if (!vsi->cnt_q_avail || vsi->cnt_q_avail < ch->num_queue_pairs) { | |
6174 | dev_dbg(&pf->pdev->dev, | |
6175 | "Error: cnt_q_avail (%u) less than num_queues %d\n", | |
6176 | vsi->cnt_q_avail, ch->num_queue_pairs); | |
6177 | return -EINVAL; | |
6178 | } | |
6179 | ||
6180 | /* reconfig_rss only if vsi type is MAIN_VSI */ | |
6181 | if (reconfig_rss && (vsi->type == I40E_VSI_MAIN)) { | |
6182 | err = i40e_vsi_reconfig_rss(vsi, ch->num_queue_pairs); | |
6183 | if (err) { | |
6184 | dev_info(&pf->pdev->dev, | |
6185 | "Error: unable to reconfig rss for num_queues (%u)\n", | |
6186 | ch->num_queue_pairs); | |
6187 | return -EINVAL; | |
6188 | } | |
6189 | } | |
6190 | ||
6191 | if (!i40e_setup_channel(pf, vsi, ch)) { | |
6192 | dev_info(&pf->pdev->dev, "Failed to setup channel\n"); | |
6193 | return -EINVAL; | |
6194 | } | |
6195 | ||
6196 | dev_info(&pf->pdev->dev, | |
6197 | "Setup channel (id:%u) utilizing num_queues %d\n", | |
6198 | ch->seid, ch->num_queue_pairs); | |
6199 | ||
2027d4de AN |
6200 | /* configure VSI for BW limit */ |
6201 | if (ch->max_tx_rate) { | |
6c32e0d9 AB |
6202 | u64 credits = ch->max_tx_rate; |
6203 | ||
2027d4de AN |
6204 | if (i40e_set_bw_limit(vsi, ch->seid, ch->max_tx_rate)) |
6205 | return -EINVAL; | |
6206 | ||
6c32e0d9 | 6207 | do_div(credits, I40E_BW_CREDIT_DIVISOR); |
2027d4de AN |
6208 | dev_dbg(&pf->pdev->dev, |
6209 | "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n", | |
6210 | ch->max_tx_rate, | |
6c32e0d9 AB |
6211 | credits, |
6212 | ch->seid); | |
2027d4de AN |
6213 | } |
6214 | ||
8f88b303 AN |
6215 | /* in case of VF, this will be main SRIOV VSI */ |
6216 | ch->parent_vsi = vsi; | |
6217 | ||
6218 | /* and update main_vsi's count for queue_available to use */ | |
6219 | vsi->cnt_q_avail -= ch->num_queue_pairs; | |
6220 | ||
6221 | return 0; | |
6222 | } | |
6223 | ||
6224 | /** | |
6225 | * i40e_configure_queue_channels - Add queue channel for the given TCs | |
6226 | * @vsi: VSI to be configured | |
6227 | * | |
6228 | * Configures queue channel mapping to the given TCs | |
6229 | **/ | |
6230 | static int i40e_configure_queue_channels(struct i40e_vsi *vsi) | |
6231 | { | |
6232 | struct i40e_channel *ch; | |
6c32e0d9 | 6233 | u64 max_rate = 0; |
8f88b303 AN |
6234 | int ret = 0, i; |
6235 | ||
6236 | /* Create app vsi with the TCs. Main VSI with TC0 is already set up */ | |
aa5cb02a | 6237 | vsi->tc_seid_map[0] = vsi->seid; |
8f88b303 AN |
6238 | for (i = 1; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
6239 | if (vsi->tc_config.enabled_tc & BIT(i)) { | |
6240 | ch = kzalloc(sizeof(*ch), GFP_KERNEL); | |
6241 | if (!ch) { | |
6242 | ret = -ENOMEM; | |
6243 | goto err_free; | |
6244 | } | |
6245 | ||
6246 | INIT_LIST_HEAD(&ch->list); | |
6247 | ch->num_queue_pairs = | |
6248 | vsi->tc_config.tc_info[i].qcount; | |
6249 | ch->base_queue = | |
6250 | vsi->tc_config.tc_info[i].qoffset; | |
6251 | ||
2027d4de AN |
6252 | /* Bandwidth limit through tc interface is in bytes/s, |
6253 | * change to Mbit/s | |
6254 | */ | |
6c32e0d9 AB |
6255 | max_rate = vsi->mqprio_qopt.max_rate[i]; |
6256 | do_div(max_rate, I40E_BW_MBPS_DIVISOR); | |
6257 | ch->max_tx_rate = max_rate; | |
2027d4de | 6258 | |
8f88b303 AN |
6259 | list_add_tail(&ch->list, &vsi->ch_list); |
6260 | ||
6261 | ret = i40e_create_queue_channel(vsi, ch); | |
6262 | if (ret) { | |
6263 | dev_err(&vsi->back->pdev->dev, | |
6264 | "Failed creating queue channel with TC%d: queues %d\n", | |
6265 | i, ch->num_queue_pairs); | |
6266 | goto err_free; | |
6267 | } | |
aa5cb02a | 6268 | vsi->tc_seid_map[i] = ch->seid; |
8f88b303 AN |
6269 | } |
6270 | } | |
6271 | return ret; | |
6272 | ||
6273 | err_free: | |
6274 | i40e_remove_queue_channels(vsi); | |
6275 | return ret; | |
6276 | } | |
6277 | ||
4e3b35b0 NP |
6278 | /** |
6279 | * i40e_veb_config_tc - Configure TCs for given VEB | |
6280 | * @veb: given VEB | |
6281 | * @enabled_tc: TC bitmap | |
6282 | * | |
6283 | * Configures given TC bitmap for VEB (switching) element | |
6284 | **/ | |
6285 | int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc) | |
6286 | { | |
6287 | struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0}; | |
6288 | struct i40e_pf *pf = veb->pf; | |
6289 | int ret = 0; | |
6290 | int i; | |
6291 | ||
6292 | /* No TCs or already enabled TCs just return */ | |
6293 | if (!enabled_tc || veb->enabled_tc == enabled_tc) | |
6294 | return ret; | |
6295 | ||
6296 | bw_data.tc_valid_bits = enabled_tc; | |
6297 | /* bw_data.absolute_credits is not set (relative) */ | |
6298 | ||
6299 | /* Enable ETS TCs with equal BW Share for now */ | |
6300 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 6301 | if (enabled_tc & BIT(i)) |
4e3b35b0 NP |
6302 | bw_data.tc_bw_share_credits[i] = 1; |
6303 | } | |
6304 | ||
6305 | ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid, | |
6306 | &bw_data, NULL); | |
6307 | if (ret) { | |
6308 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6309 | "VEB bw config failed, err %s aq_err %s\n", |
6310 | i40e_stat_str(&pf->hw, ret), | |
6311 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
6312 | goto out; |
6313 | } | |
6314 | ||
6315 | /* Update the BW information */ | |
6316 | ret = i40e_veb_get_bw_info(veb); | |
6317 | if (ret) { | |
6318 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6319 | "Failed getting veb bw config, err %s aq_err %s\n", |
6320 | i40e_stat_str(&pf->hw, ret), | |
6321 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
6322 | } |
6323 | ||
6324 | out: | |
6325 | return ret; | |
6326 | } | |
6327 | ||
6328 | #ifdef CONFIG_I40E_DCB | |
6329 | /** | |
6330 | * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs | |
6331 | * @pf: PF struct | |
6332 | * | |
6333 | * Reconfigure VEB/VSIs on a given PF; it is assumed that | |
6334 | * the caller would've quiesce all the VSIs before calling | |
6335 | * this function | |
6336 | **/ | |
6337 | static void i40e_dcb_reconfigure(struct i40e_pf *pf) | |
6338 | { | |
6339 | u8 tc_map = 0; | |
6340 | int ret; | |
6341 | u8 v; | |
6342 | ||
6343 | /* Enable the TCs available on PF to all VEBs */ | |
6344 | tc_map = i40e_pf_get_tc_map(pf); | |
6345 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
6346 | if (!pf->veb[v]) | |
6347 | continue; | |
6348 | ret = i40e_veb_config_tc(pf->veb[v], tc_map); | |
6349 | if (ret) { | |
6350 | dev_info(&pf->pdev->dev, | |
6351 | "Failed configuring TC for VEB seid=%d\n", | |
6352 | pf->veb[v]->seid); | |
6353 | /* Will try to configure as many components */ | |
6354 | } | |
6355 | } | |
6356 | ||
6357 | /* Update each VSI */ | |
505682cd | 6358 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
4e3b35b0 NP |
6359 | if (!pf->vsi[v]) |
6360 | continue; | |
6361 | ||
6362 | /* - Enable all TCs for the LAN VSI | |
6363 | * - For all others keep them at TC0 for now | |
6364 | */ | |
6365 | if (v == pf->lan_vsi) | |
6366 | tc_map = i40e_pf_get_tc_map(pf); | |
6367 | else | |
ea6acb7e | 6368 | tc_map = I40E_DEFAULT_TRAFFIC_CLASS; |
4e3b35b0 NP |
6369 | |
6370 | ret = i40e_vsi_config_tc(pf->vsi[v], tc_map); | |
6371 | if (ret) { | |
6372 | dev_info(&pf->pdev->dev, | |
6373 | "Failed configuring TC for VSI seid=%d\n", | |
6374 | pf->vsi[v]->seid); | |
6375 | /* Will try to configure as many components */ | |
6376 | } else { | |
0672a091 NP |
6377 | /* Re-configure VSI vectors based on updated TC map */ |
6378 | i40e_vsi_map_rings_to_vectors(pf->vsi[v]); | |
4e3b35b0 NP |
6379 | if (pf->vsi[v]->netdev) |
6380 | i40e_dcbnl_set_all(pf->vsi[v]); | |
6381 | } | |
6382 | } | |
6383 | } | |
6384 | ||
2fd75f31 NP |
6385 | /** |
6386 | * i40e_resume_port_tx - Resume port Tx | |
6387 | * @pf: PF struct | |
6388 | * | |
6389 | * Resume a port's Tx and issue a PF reset in case of failure to | |
6390 | * resume. | |
6391 | **/ | |
6392 | static int i40e_resume_port_tx(struct i40e_pf *pf) | |
6393 | { | |
6394 | struct i40e_hw *hw = &pf->hw; | |
6395 | int ret; | |
6396 | ||
6397 | ret = i40e_aq_resume_port_tx(hw, NULL); | |
6398 | if (ret) { | |
6399 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6400 | "Resume Port Tx failed, err %s aq_err %s\n", |
6401 | i40e_stat_str(&pf->hw, ret), | |
6402 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
2fd75f31 | 6403 | /* Schedule PF reset to recover */ |
0da36b97 | 6404 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
2fd75f31 NP |
6405 | i40e_service_event_schedule(pf); |
6406 | } | |
6407 | ||
6408 | return ret; | |
6409 | } | |
6410 | ||
4e3b35b0 NP |
6411 | /** |
6412 | * i40e_init_pf_dcb - Initialize DCB configuration | |
6413 | * @pf: PF being configured | |
6414 | * | |
6415 | * Query the current DCB configuration and cache it | |
6416 | * in the hardware structure | |
6417 | **/ | |
6418 | static int i40e_init_pf_dcb(struct i40e_pf *pf) | |
6419 | { | |
6420 | struct i40e_hw *hw = &pf->hw; | |
6421 | int err = 0; | |
6422 | ||
c61c8fe1 DE |
6423 | /* Do not enable DCB for SW1 and SW2 images even if the FW is capable |
6424 | * Also do not enable DCBx if FW LLDP agent is disabled | |
6425 | */ | |
6426 | if ((pf->hw_features & I40E_HW_NO_DCB_SUPPORT) || | |
6427 | (pf->flags & I40E_FLAG_DISABLE_FW_LLDP)) | |
025b4a54 ASJ |
6428 | goto out; |
6429 | ||
4e3b35b0 | 6430 | /* Get the initial DCB configuration */ |
54dea0e7 | 6431 | err = i40e_init_dcb(hw, true); |
4e3b35b0 NP |
6432 | if (!err) { |
6433 | /* Device/Function is not DCBX capable */ | |
6434 | if ((!hw->func_caps.dcb) || | |
6435 | (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) { | |
6436 | dev_info(&pf->pdev->dev, | |
6437 | "DCBX offload is not supported or is disabled for this PF.\n"); | |
4e3b35b0 NP |
6438 | } else { |
6439 | /* When status is not DISABLED then DCBX in FW */ | |
6440 | pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED | | |
6441 | DCB_CAP_DCBX_VER_IEEE; | |
4d9b6043 NP |
6442 | |
6443 | pf->flags |= I40E_FLAG_DCB_CAPABLE; | |
a036244c DE |
6444 | /* Enable DCB tagging only when more than one TC |
6445 | * or explicitly disable if only one TC | |
6446 | */ | |
4d9b6043 NP |
6447 | if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) |
6448 | pf->flags |= I40E_FLAG_DCB_ENABLED; | |
a036244c DE |
6449 | else |
6450 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
9fa61dd2 NP |
6451 | dev_dbg(&pf->pdev->dev, |
6452 | "DCBX offload is supported for this PF.\n"); | |
4e3b35b0 | 6453 | } |
64e1dcbb AB |
6454 | } else if (pf->hw.aq.asq_last_status == I40E_AQ_RC_EPERM) { |
6455 | dev_info(&pf->pdev->dev, "FW LLDP disabled for this PF.\n"); | |
6456 | pf->flags |= I40E_FLAG_DISABLE_FW_LLDP; | |
014269ff | 6457 | } else { |
aebfc816 | 6458 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6459 | "Query for DCB configuration failed, err %s aq_err %s\n", |
6460 | i40e_stat_str(&pf->hw, err), | |
6461 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
6462 | } |
6463 | ||
6464 | out: | |
6465 | return err; | |
6466 | } | |
6467 | #endif /* CONFIG_I40E_DCB */ | |
cf05ed08 JB |
6468 | #define SPEED_SIZE 14 |
6469 | #define FC_SIZE 8 | |
6470 | /** | |
6471 | * i40e_print_link_message - print link up or down | |
6472 | * @vsi: the VSI for which link needs a message | |
f5254429 | 6473 | * @isup: true of link is up, false otherwise |
cf05ed08 | 6474 | */ |
c156f856 | 6475 | void i40e_print_link_message(struct i40e_vsi *vsi, bool isup) |
cf05ed08 | 6476 | { |
7ec9ba11 | 6477 | enum i40e_aq_link_speed new_speed; |
3fded466 | 6478 | struct i40e_pf *pf = vsi->back; |
a9165490 SN |
6479 | char *speed = "Unknown"; |
6480 | char *fc = "Unknown"; | |
3e03d7cc | 6481 | char *fec = ""; |
68e49702 | 6482 | char *req_fec = ""; |
3e03d7cc | 6483 | char *an = ""; |
cf05ed08 | 6484 | |
fd835129 SN |
6485 | if (isup) |
6486 | new_speed = pf->hw.phy.link_info.link_speed; | |
6487 | else | |
6488 | new_speed = I40E_LINK_SPEED_UNKNOWN; | |
7ec9ba11 FS |
6489 | |
6490 | if ((vsi->current_isup == isup) && (vsi->current_speed == new_speed)) | |
c156f856 MJ |
6491 | return; |
6492 | vsi->current_isup = isup; | |
7ec9ba11 | 6493 | vsi->current_speed = new_speed; |
cf05ed08 JB |
6494 | if (!isup) { |
6495 | netdev_info(vsi->netdev, "NIC Link is Down\n"); | |
6496 | return; | |
6497 | } | |
6498 | ||
148c2d80 GR |
6499 | /* Warn user if link speed on NPAR enabled partition is not at |
6500 | * least 10GB | |
6501 | */ | |
3fded466 SM |
6502 | if (pf->hw.func_caps.npar_enable && |
6503 | (pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB || | |
6504 | pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB)) | |
148c2d80 GR |
6505 | netdev_warn(vsi->netdev, |
6506 | "The partition detected link speed that is less than 10Gbps\n"); | |
6507 | ||
3fded466 | 6508 | switch (pf->hw.phy.link_info.link_speed) { |
cf05ed08 | 6509 | case I40E_LINK_SPEED_40GB: |
a9165490 | 6510 | speed = "40 G"; |
cf05ed08 | 6511 | break; |
ae24b409 | 6512 | case I40E_LINK_SPEED_20GB: |
a9165490 | 6513 | speed = "20 G"; |
ae24b409 | 6514 | break; |
3123237a CW |
6515 | case I40E_LINK_SPEED_25GB: |
6516 | speed = "25 G"; | |
6517 | break; | |
cf05ed08 | 6518 | case I40E_LINK_SPEED_10GB: |
a9165490 | 6519 | speed = "10 G"; |
cf05ed08 JB |
6520 | break; |
6521 | case I40E_LINK_SPEED_1GB: | |
a9165490 | 6522 | speed = "1000 M"; |
cf05ed08 | 6523 | break; |
5960d33f | 6524 | case I40E_LINK_SPEED_100MB: |
a9165490 | 6525 | speed = "100 M"; |
5960d33f | 6526 | break; |
cf05ed08 JB |
6527 | default: |
6528 | break; | |
6529 | } | |
6530 | ||
3fded466 | 6531 | switch (pf->hw.fc.current_mode) { |
cf05ed08 | 6532 | case I40E_FC_FULL: |
a9165490 | 6533 | fc = "RX/TX"; |
cf05ed08 JB |
6534 | break; |
6535 | case I40E_FC_TX_PAUSE: | |
a9165490 | 6536 | fc = "TX"; |
cf05ed08 JB |
6537 | break; |
6538 | case I40E_FC_RX_PAUSE: | |
a9165490 | 6539 | fc = "RX"; |
cf05ed08 JB |
6540 | break; |
6541 | default: | |
a9165490 | 6542 | fc = "None"; |
cf05ed08 JB |
6543 | break; |
6544 | } | |
6545 | ||
3fded466 | 6546 | if (pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_25GB) { |
68e49702 | 6547 | req_fec = ", Requested FEC: None"; |
3e03d7cc HT |
6548 | fec = ", FEC: None"; |
6549 | an = ", Autoneg: False"; | |
6550 | ||
3fded466 | 6551 | if (pf->hw.phy.link_info.an_info & I40E_AQ_AN_COMPLETED) |
3e03d7cc HT |
6552 | an = ", Autoneg: True"; |
6553 | ||
3fded466 | 6554 | if (pf->hw.phy.link_info.fec_info & |
3e03d7cc HT |
6555 | I40E_AQ_CONFIG_FEC_KR_ENA) |
6556 | fec = ", FEC: CL74 FC-FEC/BASE-R"; | |
3fded466 | 6557 | else if (pf->hw.phy.link_info.fec_info & |
3e03d7cc HT |
6558 | I40E_AQ_CONFIG_FEC_RS_ENA) |
6559 | fec = ", FEC: CL108 RS-FEC"; | |
68e49702 MS |
6560 | |
6561 | /* 'CL108 RS-FEC' should be displayed when RS is requested, or | |
6562 | * both RS and FC are requested | |
6563 | */ | |
6564 | if (vsi->back->hw.phy.link_info.req_fec_info & | |
6565 | (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS)) { | |
6566 | if (vsi->back->hw.phy.link_info.req_fec_info & | |
6567 | I40E_AQ_REQUEST_FEC_RS) | |
6568 | req_fec = ", Requested FEC: CL108 RS-FEC"; | |
6569 | else | |
6570 | req_fec = ", Requested FEC: CL74 FC-FEC/BASE-R"; | |
6571 | } | |
3e03d7cc HT |
6572 | } |
6573 | ||
68e49702 MS |
6574 | netdev_info(vsi->netdev, "NIC Link is Up, %sbps Full Duplex%s%s%s, Flow Control: %s\n", |
6575 | speed, req_fec, fec, an, fc); | |
cf05ed08 | 6576 | } |
4e3b35b0 | 6577 | |
41c445ff JB |
6578 | /** |
6579 | * i40e_up_complete - Finish the last steps of bringing up a connection | |
6580 | * @vsi: the VSI being configured | |
6581 | **/ | |
6582 | static int i40e_up_complete(struct i40e_vsi *vsi) | |
6583 | { | |
6584 | struct i40e_pf *pf = vsi->back; | |
6585 | int err; | |
6586 | ||
6587 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
6588 | i40e_vsi_configure_msix(vsi); | |
6589 | else | |
6590 | i40e_configure_msi_and_legacy(vsi); | |
6591 | ||
6592 | /* start rings */ | |
3aa7b74d | 6593 | err = i40e_vsi_start_rings(vsi); |
41c445ff JB |
6594 | if (err) |
6595 | return err; | |
6596 | ||
0da36b97 | 6597 | clear_bit(__I40E_VSI_DOWN, vsi->state); |
41c445ff JB |
6598 | i40e_napi_enable_all(vsi); |
6599 | i40e_vsi_enable_irq(vsi); | |
6600 | ||
6601 | if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) && | |
6602 | (vsi->netdev)) { | |
cf05ed08 | 6603 | i40e_print_link_message(vsi, true); |
41c445ff JB |
6604 | netif_tx_start_all_queues(vsi->netdev); |
6605 | netif_carrier_on(vsi->netdev); | |
6606 | } | |
ca64fa4e ASJ |
6607 | |
6608 | /* replay FDIR SB filters */ | |
1e1be8f6 ASJ |
6609 | if (vsi->type == I40E_VSI_FDIR) { |
6610 | /* reset fd counters */ | |
097dbf52 JK |
6611 | pf->fd_add_err = 0; |
6612 | pf->fd_atr_cnt = 0; | |
ca64fa4e | 6613 | i40e_fdir_filter_restore(vsi); |
1e1be8f6 | 6614 | } |
e3219ce6 ASJ |
6615 | |
6616 | /* On the next run of the service_task, notify any clients of the new | |
6617 | * opened netdev | |
6618 | */ | |
5f76a704 | 6619 | set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state); |
41c445ff JB |
6620 | i40e_service_event_schedule(pf); |
6621 | ||
6622 | return 0; | |
6623 | } | |
6624 | ||
6625 | /** | |
6626 | * i40e_vsi_reinit_locked - Reset the VSI | |
6627 | * @vsi: the VSI being configured | |
6628 | * | |
6629 | * Rebuild the ring structs after some configuration | |
6630 | * has changed, e.g. MTU size. | |
6631 | **/ | |
6632 | static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi) | |
6633 | { | |
6634 | struct i40e_pf *pf = vsi->back; | |
6635 | ||
6636 | WARN_ON(in_interrupt()); | |
0da36b97 | 6637 | while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) |
41c445ff JB |
6638 | usleep_range(1000, 2000); |
6639 | i40e_down(vsi); | |
6640 | ||
41c445ff | 6641 | i40e_up(vsi); |
0da36b97 | 6642 | clear_bit(__I40E_CONFIG_BUSY, pf->state); |
41c445ff JB |
6643 | } |
6644 | ||
6645 | /** | |
6646 | * i40e_up - Bring the connection back up after being down | |
6647 | * @vsi: the VSI being configured | |
6648 | **/ | |
6649 | int i40e_up(struct i40e_vsi *vsi) | |
6650 | { | |
6651 | int err; | |
6652 | ||
6653 | err = i40e_vsi_configure(vsi); | |
6654 | if (!err) | |
6655 | err = i40e_up_complete(vsi); | |
6656 | ||
6657 | return err; | |
6658 | } | |
6659 | ||
c3880bd1 MS |
6660 | /** |
6661 | * i40e_force_link_state - Force the link status | |
6662 | * @pf: board private structure | |
6663 | * @is_up: whether the link state should be forced up or down | |
6664 | **/ | |
6665 | static i40e_status i40e_force_link_state(struct i40e_pf *pf, bool is_up) | |
6666 | { | |
6667 | struct i40e_aq_get_phy_abilities_resp abilities; | |
6668 | struct i40e_aq_set_phy_config config = {0}; | |
6669 | struct i40e_hw *hw = &pf->hw; | |
6670 | i40e_status err; | |
6671 | u64 mask; | |
e78d9a39 JS |
6672 | u8 speed; |
6673 | ||
6674 | /* Card might've been put in an unstable state by other drivers | |
6675 | * and applications, which causes incorrect speed values being | |
6676 | * set on startup. In order to clear speed registers, we call | |
6677 | * get_phy_capabilities twice, once to get initial state of | |
6678 | * available speeds, and once to get current PHY config. | |
6679 | */ | |
6680 | err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, | |
6681 | NULL); | |
6682 | if (err) { | |
6683 | dev_err(&pf->pdev->dev, | |
6684 | "failed to get phy cap., ret = %s last_status = %s\n", | |
6685 | i40e_stat_str(hw, err), | |
6686 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
6687 | return err; | |
6688 | } | |
6689 | speed = abilities.link_speed; | |
c3880bd1 MS |
6690 | |
6691 | /* Get the current phy config */ | |
6692 | err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, | |
6693 | NULL); | |
6694 | if (err) { | |
6695 | dev_err(&pf->pdev->dev, | |
6696 | "failed to get phy cap., ret = %s last_status = %s\n", | |
6697 | i40e_stat_str(hw, err), | |
6698 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
6699 | return err; | |
6700 | } | |
6701 | ||
6702 | /* If link needs to go up, but was not forced to go down, | |
e78d9a39 | 6703 | * and its speed values are OK, no need for a flap |
c3880bd1 | 6704 | */ |
e78d9a39 | 6705 | if (is_up && abilities.phy_type != 0 && abilities.link_speed != 0) |
c3880bd1 MS |
6706 | return I40E_SUCCESS; |
6707 | ||
6708 | /* To force link we need to set bits for all supported PHY types, | |
6709 | * but there are now more than 32, so we need to split the bitmap | |
6710 | * across two fields. | |
6711 | */ | |
6712 | mask = I40E_PHY_TYPES_BITMASK; | |
6713 | config.phy_type = is_up ? cpu_to_le32((u32)(mask & 0xffffffff)) : 0; | |
6714 | config.phy_type_ext = is_up ? (u8)((mask >> 32) & 0xff) : 0; | |
6715 | /* Copy the old settings, except of phy_type */ | |
6716 | config.abilities = abilities.abilities; | |
e78d9a39 JS |
6717 | if (abilities.link_speed != 0) |
6718 | config.link_speed = abilities.link_speed; | |
6719 | else | |
6720 | config.link_speed = speed; | |
c3880bd1 MS |
6721 | config.eee_capability = abilities.eee_capability; |
6722 | config.eeer = abilities.eeer_val; | |
6723 | config.low_power_ctrl = abilities.d3_lpan; | |
1ac2ee23 MS |
6724 | config.fec_config = abilities.fec_cfg_curr_mod_ext_info & |
6725 | I40E_AQ_PHY_FEC_CONFIG_MASK; | |
c3880bd1 MS |
6726 | err = i40e_aq_set_phy_config(hw, &config, NULL); |
6727 | ||
6728 | if (err) { | |
6729 | dev_err(&pf->pdev->dev, | |
6730 | "set phy config ret = %s last_status = %s\n", | |
6731 | i40e_stat_str(&pf->hw, err), | |
6732 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
6733 | return err; | |
6734 | } | |
6735 | ||
6736 | /* Update the link info */ | |
6737 | err = i40e_update_link_info(hw); | |
6738 | if (err) { | |
6739 | /* Wait a little bit (on 40G cards it sometimes takes a really | |
6740 | * long time for link to come back from the atomic reset) | |
6741 | * and try once more | |
6742 | */ | |
6743 | msleep(1000); | |
6744 | i40e_update_link_info(hw); | |
6745 | } | |
6746 | ||
6747 | i40e_aq_set_link_restart_an(hw, true, NULL); | |
6748 | ||
6749 | return I40E_SUCCESS; | |
6750 | } | |
6751 | ||
41c445ff JB |
6752 | /** |
6753 | * i40e_down - Shutdown the connection processing | |
6754 | * @vsi: the VSI being stopped | |
6755 | **/ | |
6756 | void i40e_down(struct i40e_vsi *vsi) | |
6757 | { | |
6758 | int i; | |
6759 | ||
6760 | /* It is assumed that the caller of this function | |
d19cb64b | 6761 | * sets the vsi->state __I40E_VSI_DOWN bit. |
41c445ff JB |
6762 | */ |
6763 | if (vsi->netdev) { | |
6764 | netif_carrier_off(vsi->netdev); | |
6765 | netif_tx_disable(vsi->netdev); | |
6766 | } | |
6767 | i40e_vsi_disable_irq(vsi); | |
3aa7b74d | 6768 | i40e_vsi_stop_rings(vsi); |
c3880bd1 MS |
6769 | if (vsi->type == I40E_VSI_MAIN && |
6770 | vsi->back->flags & I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED) | |
6771 | i40e_force_link_state(vsi->back, false); | |
41c445ff JB |
6772 | i40e_napi_disable_all(vsi); |
6773 | ||
6774 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
9f65e15b | 6775 | i40e_clean_tx_ring(vsi->tx_rings[i]); |
59eb2a88 BT |
6776 | if (i40e_enabled_xdp_vsi(vsi)) { |
6777 | /* Make sure that in-progress ndo_xdp_xmit | |
6778 | * calls are completed. | |
6779 | */ | |
6780 | synchronize_rcu(); | |
74608d17 | 6781 | i40e_clean_tx_ring(vsi->xdp_rings[i]); |
59eb2a88 | 6782 | } |
9f65e15b | 6783 | i40e_clean_rx_ring(vsi->rx_rings[i]); |
41c445ff | 6784 | } |
f980d445 | 6785 | |
41c445ff JB |
6786 | } |
6787 | ||
a9ce82f7 AN |
6788 | /** |
6789 | * i40e_validate_mqprio_qopt- validate queue mapping info | |
6790 | * @vsi: the VSI being configured | |
6791 | * @mqprio_qopt: queue parametrs | |
6792 | **/ | |
6793 | static int i40e_validate_mqprio_qopt(struct i40e_vsi *vsi, | |
6794 | struct tc_mqprio_qopt_offload *mqprio_qopt) | |
6795 | { | |
2027d4de | 6796 | u64 sum_max_rate = 0; |
6c32e0d9 | 6797 | u64 max_rate = 0; |
a9ce82f7 AN |
6798 | int i; |
6799 | ||
6800 | if (mqprio_qopt->qopt.offset[0] != 0 || | |
6801 | mqprio_qopt->qopt.num_tc < 1 || | |
6802 | mqprio_qopt->qopt.num_tc > I40E_MAX_TRAFFIC_CLASS) | |
6803 | return -EINVAL; | |
6804 | for (i = 0; ; i++) { | |
6805 | if (!mqprio_qopt->qopt.count[i]) | |
6806 | return -EINVAL; | |
2027d4de AN |
6807 | if (mqprio_qopt->min_rate[i]) { |
6808 | dev_err(&vsi->back->pdev->dev, | |
6809 | "Invalid min tx rate (greater than 0) specified\n"); | |
a9ce82f7 | 6810 | return -EINVAL; |
2027d4de | 6811 | } |
6c32e0d9 AB |
6812 | max_rate = mqprio_qopt->max_rate[i]; |
6813 | do_div(max_rate, I40E_BW_MBPS_DIVISOR); | |
6814 | sum_max_rate += max_rate; | |
2027d4de | 6815 | |
a9ce82f7 AN |
6816 | if (i >= mqprio_qopt->qopt.num_tc - 1) |
6817 | break; | |
6818 | if (mqprio_qopt->qopt.offset[i + 1] != | |
6819 | (mqprio_qopt->qopt.offset[i] + mqprio_qopt->qopt.count[i])) | |
6820 | return -EINVAL; | |
6821 | } | |
6822 | if (vsi->num_queue_pairs < | |
6823 | (mqprio_qopt->qopt.offset[i] + mqprio_qopt->qopt.count[i])) { | |
6824 | return -EINVAL; | |
6825 | } | |
2027d4de AN |
6826 | if (sum_max_rate > i40e_get_link_speed(vsi)) { |
6827 | dev_err(&vsi->back->pdev->dev, | |
6828 | "Invalid max tx rate specified\n"); | |
6829 | return -EINVAL; | |
6830 | } | |
a9ce82f7 AN |
6831 | return 0; |
6832 | } | |
6833 | ||
6834 | /** | |
6835 | * i40e_vsi_set_default_tc_config - set default values for tc configuration | |
6836 | * @vsi: the VSI being configured | |
6837 | **/ | |
6838 | static void i40e_vsi_set_default_tc_config(struct i40e_vsi *vsi) | |
6839 | { | |
6840 | u16 qcount; | |
6841 | int i; | |
6842 | ||
6843 | /* Only TC0 is enabled */ | |
6844 | vsi->tc_config.numtc = 1; | |
6845 | vsi->tc_config.enabled_tc = 1; | |
6846 | qcount = min_t(int, vsi->alloc_queue_pairs, | |
6847 | i40e_pf_get_max_q_per_tc(vsi->back)); | |
6848 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
6849 | /* For the TC that is not enabled set the offset to to default | |
6850 | * queue and allocate one queue for the given TC. | |
6851 | */ | |
6852 | vsi->tc_config.tc_info[i].qoffset = 0; | |
6853 | if (i == 0) | |
6854 | vsi->tc_config.tc_info[i].qcount = qcount; | |
6855 | else | |
6856 | vsi->tc_config.tc_info[i].qcount = 1; | |
6857 | vsi->tc_config.tc_info[i].netdev_tc = 0; | |
6858 | } | |
6859 | } | |
6860 | ||
41c445ff JB |
6861 | /** |
6862 | * i40e_setup_tc - configure multiple traffic classes | |
6863 | * @netdev: net device to configure | |
a9ce82f7 | 6864 | * @type_data: tc offload data |
41c445ff | 6865 | **/ |
a9ce82f7 | 6866 | static int i40e_setup_tc(struct net_device *netdev, void *type_data) |
41c445ff | 6867 | { |
a9ce82f7 | 6868 | struct tc_mqprio_qopt_offload *mqprio_qopt = type_data; |
41c445ff JB |
6869 | struct i40e_netdev_priv *np = netdev_priv(netdev); |
6870 | struct i40e_vsi *vsi = np->vsi; | |
6871 | struct i40e_pf *pf = vsi->back; | |
a9ce82f7 AN |
6872 | u8 enabled_tc = 0, num_tc, hw; |
6873 | bool need_reset = false; | |
3e957b37 | 6874 | int old_queue_pairs; |
41c445ff | 6875 | int ret = -EINVAL; |
a9ce82f7 | 6876 | u16 mode; |
41c445ff JB |
6877 | int i; |
6878 | ||
3e957b37 | 6879 | old_queue_pairs = vsi->num_queue_pairs; |
a9ce82f7 AN |
6880 | num_tc = mqprio_qopt->qopt.num_tc; |
6881 | hw = mqprio_qopt->qopt.hw; | |
6882 | mode = mqprio_qopt->mode; | |
6883 | if (!hw) { | |
6884 | pf->flags &= ~I40E_FLAG_TC_MQPRIO; | |
6885 | memcpy(&vsi->mqprio_qopt, mqprio_qopt, sizeof(*mqprio_qopt)); | |
6886 | goto config_tc; | |
41c445ff JB |
6887 | } |
6888 | ||
6889 | /* Check if MFP enabled */ | |
6890 | if (pf->flags & I40E_FLAG_MFP_ENABLED) { | |
a9ce82f7 AN |
6891 | netdev_info(netdev, |
6892 | "Configuring TC not supported in MFP mode\n"); | |
6893 | return ret; | |
41c445ff | 6894 | } |
a9ce82f7 AN |
6895 | switch (mode) { |
6896 | case TC_MQPRIO_MODE_DCB: | |
6897 | pf->flags &= ~I40E_FLAG_TC_MQPRIO; | |
41c445ff | 6898 | |
a9ce82f7 AN |
6899 | /* Check if DCB enabled to continue */ |
6900 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) { | |
6901 | netdev_info(netdev, | |
6902 | "DCB is not enabled for adapter\n"); | |
6903 | return ret; | |
6904 | } | |
6905 | ||
6906 | /* Check whether tc count is within enabled limit */ | |
6907 | if (num_tc > i40e_pf_get_num_tc(pf)) { | |
6908 | netdev_info(netdev, | |
6909 | "TC count greater than enabled on link for adapter\n"); | |
6910 | return ret; | |
6911 | } | |
6912 | break; | |
6913 | case TC_MQPRIO_MODE_CHANNEL: | |
6914 | if (pf->flags & I40E_FLAG_DCB_ENABLED) { | |
6915 | netdev_info(netdev, | |
6916 | "Full offload of TC Mqprio options is not supported when DCB is enabled\n"); | |
6917 | return ret; | |
6918 | } | |
6919 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
6920 | return ret; | |
6921 | ret = i40e_validate_mqprio_qopt(vsi, mqprio_qopt); | |
6922 | if (ret) | |
6923 | return ret; | |
6924 | memcpy(&vsi->mqprio_qopt, mqprio_qopt, | |
6925 | sizeof(*mqprio_qopt)); | |
6926 | pf->flags |= I40E_FLAG_TC_MQPRIO; | |
6927 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
6928 | break; | |
6929 | default: | |
6930 | return -EINVAL; | |
41c445ff JB |
6931 | } |
6932 | ||
a9ce82f7 | 6933 | config_tc: |
41c445ff | 6934 | /* Generate TC map for number of tc requested */ |
a9ce82f7 | 6935 | for (i = 0; i < num_tc; i++) |
75f5cea9 | 6936 | enabled_tc |= BIT(i); |
41c445ff JB |
6937 | |
6938 | /* Requesting same TC configuration as already enabled */ | |
a9ce82f7 AN |
6939 | if (enabled_tc == vsi->tc_config.enabled_tc && |
6940 | mode != TC_MQPRIO_MODE_CHANNEL) | |
41c445ff JB |
6941 | return 0; |
6942 | ||
6943 | /* Quiesce VSI queues */ | |
6944 | i40e_quiesce_vsi(vsi); | |
6945 | ||
a9ce82f7 AN |
6946 | if (!hw && !(pf->flags & I40E_FLAG_TC_MQPRIO)) |
6947 | i40e_remove_queue_channels(vsi); | |
6948 | ||
41c445ff JB |
6949 | /* Configure VSI for enabled TCs */ |
6950 | ret = i40e_vsi_config_tc(vsi, enabled_tc); | |
6951 | if (ret) { | |
6952 | netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n", | |
6953 | vsi->seid); | |
a9ce82f7 | 6954 | need_reset = true; |
41c445ff JB |
6955 | goto exit; |
6956 | } | |
6957 | ||
8f88b303 | 6958 | if (pf->flags & I40E_FLAG_TC_MQPRIO) { |
2027d4de | 6959 | if (vsi->mqprio_qopt.max_rate[0]) { |
6c32e0d9 AB |
6960 | u64 max_tx_rate = vsi->mqprio_qopt.max_rate[0]; |
6961 | ||
6962 | do_div(max_tx_rate, I40E_BW_MBPS_DIVISOR); | |
2027d4de AN |
6963 | ret = i40e_set_bw_limit(vsi, vsi->seid, max_tx_rate); |
6964 | if (!ret) { | |
6c32e0d9 AB |
6965 | u64 credits = max_tx_rate; |
6966 | ||
6967 | do_div(credits, I40E_BW_CREDIT_DIVISOR); | |
2027d4de AN |
6968 | dev_dbg(&vsi->back->pdev->dev, |
6969 | "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n", | |
6970 | max_tx_rate, | |
6c32e0d9 | 6971 | credits, |
2027d4de AN |
6972 | vsi->seid); |
6973 | } else { | |
6974 | need_reset = true; | |
6975 | goto exit; | |
6976 | } | |
6977 | } | |
8f88b303 | 6978 | ret = i40e_configure_queue_channels(vsi); |
4e3b35b0 | 6979 | if (ret) { |
3e957b37 | 6980 | vsi->num_queue_pairs = old_queue_pairs; |
8f88b303 AN |
6981 | netdev_info(netdev, |
6982 | "Failed configuring queue channels\n"); | |
a9ce82f7 | 6983 | need_reset = true; |
8f88b303 | 6984 | goto exit; |
4e3b35b0 NP |
6985 | } |
6986 | } | |
6987 | ||
41c445ff | 6988 | exit: |
a9ce82f7 AN |
6989 | /* Reset the configuration data to defaults, only TC0 is enabled */ |
6990 | if (need_reset) { | |
6991 | i40e_vsi_set_default_tc_config(vsi); | |
6992 | need_reset = false; | |
6993 | } | |
4e3b35b0 | 6994 | |
8f88b303 AN |
6995 | /* Unquiesce VSI */ |
6996 | i40e_unquiesce_vsi(vsi); | |
41c445ff JB |
6997 | return ret; |
6998 | } | |
4e3b35b0 | 6999 | |
2f4b411a AN |
7000 | /** |
7001 | * i40e_set_cld_element - sets cloud filter element data | |
7002 | * @filter: cloud filter rule | |
7003 | * @cld: ptr to cloud filter element data | |
7004 | * | |
7005 | * This is helper function to copy data into cloud filter element | |
7006 | **/ | |
7007 | static inline void | |
7008 | i40e_set_cld_element(struct i40e_cloud_filter *filter, | |
7009 | struct i40e_aqc_cloud_filters_element_data *cld) | |
7010 | { | |
7011 | int i, j; | |
7012 | u32 ipa; | |
7013 | ||
7014 | memset(cld, 0, sizeof(*cld)); | |
7015 | ether_addr_copy(cld->outer_mac, filter->dst_mac); | |
7016 | ether_addr_copy(cld->inner_mac, filter->src_mac); | |
7017 | ||
7018 | if (filter->n_proto != ETH_P_IP && filter->n_proto != ETH_P_IPV6) | |
7019 | return; | |
7020 | ||
7021 | if (filter->n_proto == ETH_P_IPV6) { | |
7022 | #define IPV6_MAX_INDEX (ARRAY_SIZE(filter->dst_ipv6) - 1) | |
7023 | for (i = 0, j = 0; i < ARRAY_SIZE(filter->dst_ipv6); | |
7024 | i++, j += 2) { | |
7025 | ipa = be32_to_cpu(filter->dst_ipv6[IPV6_MAX_INDEX - i]); | |
7026 | ipa = cpu_to_le32(ipa); | |
7027 | memcpy(&cld->ipaddr.raw_v6.data[j], &ipa, sizeof(ipa)); | |
4e3b35b0 | 7028 | } |
2f4b411a AN |
7029 | } else { |
7030 | ipa = be32_to_cpu(filter->dst_ipv4); | |
7031 | memcpy(&cld->ipaddr.v4.data, &ipa, sizeof(ipa)); | |
4e3b35b0 | 7032 | } |
2f4b411a AN |
7033 | |
7034 | cld->inner_vlan = cpu_to_le16(ntohs(filter->vlan_id)); | |
7035 | ||
7036 | /* tenant_id is not supported by FW now, once the support is enabled | |
7037 | * fill the cld->tenant_id with cpu_to_le32(filter->tenant_id) | |
7038 | */ | |
7039 | if (filter->tenant_id) | |
7040 | return; | |
4e3b35b0 NP |
7041 | } |
7042 | ||
2fd75f31 | 7043 | /** |
2f4b411a AN |
7044 | * i40e_add_del_cloud_filter - Add/del cloud filter |
7045 | * @vsi: pointer to VSI | |
7046 | * @filter: cloud filter rule | |
7047 | * @add: if true, add, if false, delete | |
2fd75f31 | 7048 | * |
2f4b411a AN |
7049 | * Add or delete a cloud filter for a specific flow spec. |
7050 | * Returns 0 if the filter were successfully added. | |
2fd75f31 | 7051 | **/ |
e284fc28 AD |
7052 | int i40e_add_del_cloud_filter(struct i40e_vsi *vsi, |
7053 | struct i40e_cloud_filter *filter, bool add) | |
2fd75f31 | 7054 | { |
2f4b411a AN |
7055 | struct i40e_aqc_cloud_filters_element_data cld_filter; |
7056 | struct i40e_pf *pf = vsi->back; | |
2fd75f31 | 7057 | int ret; |
2f4b411a AN |
7058 | static const u16 flag_table[128] = { |
7059 | [I40E_CLOUD_FILTER_FLAGS_OMAC] = | |
7060 | I40E_AQC_ADD_CLOUD_FILTER_OMAC, | |
7061 | [I40E_CLOUD_FILTER_FLAGS_IMAC] = | |
7062 | I40E_AQC_ADD_CLOUD_FILTER_IMAC, | |
7063 | [I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN] = | |
7064 | I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN, | |
7065 | [I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID] = | |
7066 | I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID, | |
7067 | [I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC] = | |
7068 | I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC, | |
7069 | [I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID] = | |
7070 | I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID, | |
7071 | [I40E_CLOUD_FILTER_FLAGS_IIP] = | |
7072 | I40E_AQC_ADD_CLOUD_FILTER_IIP, | |
7073 | }; | |
7074 | ||
7075 | if (filter->flags >= ARRAY_SIZE(flag_table)) | |
7076 | return I40E_ERR_CONFIG; | |
7077 | ||
7078 | /* copy element needed to add cloud filter from filter */ | |
7079 | i40e_set_cld_element(filter, &cld_filter); | |
7080 | ||
7081 | if (filter->tunnel_type != I40E_CLOUD_TNL_TYPE_NONE) | |
7082 | cld_filter.flags = cpu_to_le16(filter->tunnel_type << | |
7083 | I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT); | |
7084 | ||
7085 | if (filter->n_proto == ETH_P_IPV6) | |
7086 | cld_filter.flags |= cpu_to_le16(flag_table[filter->flags] | | |
7087 | I40E_AQC_ADD_CLOUD_FLAGS_IPV6); | |
7088 | else | |
7089 | cld_filter.flags |= cpu_to_le16(flag_table[filter->flags] | | |
7090 | I40E_AQC_ADD_CLOUD_FLAGS_IPV4); | |
2fd75f31 | 7091 | |
2f4b411a AN |
7092 | if (add) |
7093 | ret = i40e_aq_add_cloud_filters(&pf->hw, filter->seid, | |
7094 | &cld_filter, 1); | |
7095 | else | |
7096 | ret = i40e_aq_rem_cloud_filters(&pf->hw, filter->seid, | |
7097 | &cld_filter, 1); | |
7098 | if (ret) | |
7099 | dev_dbg(&pf->pdev->dev, | |
7100 | "Failed to %s cloud filter using l4 port %u, err %d aq_err %d\n", | |
7101 | add ? "add" : "delete", filter->dst_port, ret, | |
7102 | pf->hw.aq.asq_last_status); | |
7103 | else | |
2fd75f31 | 7104 | dev_info(&pf->pdev->dev, |
2f4b411a AN |
7105 | "%s cloud filter for VSI: %d\n", |
7106 | add ? "Added" : "Deleted", filter->seid); | |
2fd75f31 NP |
7107 | return ret; |
7108 | } | |
7109 | ||
4e3b35b0 | 7110 | /** |
2f4b411a AN |
7111 | * i40e_add_del_cloud_filter_big_buf - Add/del cloud filter using big_buf |
7112 | * @vsi: pointer to VSI | |
7113 | * @filter: cloud filter rule | |
7114 | * @add: if true, add, if false, delete | |
4e3b35b0 | 7115 | * |
2f4b411a AN |
7116 | * Add or delete a cloud filter for a specific flow spec using big buffer. |
7117 | * Returns 0 if the filter were successfully added. | |
4e3b35b0 | 7118 | **/ |
e284fc28 AD |
7119 | int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi, |
7120 | struct i40e_cloud_filter *filter, | |
7121 | bool add) | |
4e3b35b0 | 7122 | { |
2f4b411a AN |
7123 | struct i40e_aqc_cloud_filters_element_bb cld_filter; |
7124 | struct i40e_pf *pf = vsi->back; | |
7125 | int ret; | |
4e3b35b0 | 7126 | |
2f4b411a AN |
7127 | /* Both (src/dst) valid mac_addr are not supported */ |
7128 | if ((is_valid_ether_addr(filter->dst_mac) && | |
7129 | is_valid_ether_addr(filter->src_mac)) || | |
7130 | (is_multicast_ether_addr(filter->dst_mac) && | |
7131 | is_multicast_ether_addr(filter->src_mac))) | |
64e711ca | 7132 | return -EOPNOTSUPP; |
025b4a54 | 7133 | |
64e711ca AN |
7134 | /* Big buffer cloud filter needs 'L4 port' to be non-zero. Also, UDP |
7135 | * ports are not supported via big buffer now. | |
2f4b411a | 7136 | */ |
64e711ca AN |
7137 | if (!filter->dst_port || filter->ip_proto == IPPROTO_UDP) |
7138 | return -EOPNOTSUPP; | |
4d9b6043 | 7139 | |
2f4b411a AN |
7140 | /* adding filter using src_port/src_ip is not supported at this stage */ |
7141 | if (filter->src_port || filter->src_ipv4 || | |
7142 | !ipv6_addr_any(&filter->ip.v6.src_ip6)) | |
64e711ca | 7143 | return -EOPNOTSUPP; |
2f4b411a AN |
7144 | |
7145 | /* copy element needed to add cloud filter from filter */ | |
7146 | i40e_set_cld_element(filter, &cld_filter.element); | |
7147 | ||
7148 | if (is_valid_ether_addr(filter->dst_mac) || | |
7149 | is_valid_ether_addr(filter->src_mac) || | |
7150 | is_multicast_ether_addr(filter->dst_mac) || | |
7151 | is_multicast_ether_addr(filter->src_mac)) { | |
7152 | /* MAC + IP : unsupported mode */ | |
7153 | if (filter->dst_ipv4) | |
64e711ca | 7154 | return -EOPNOTSUPP; |
2f4b411a AN |
7155 | |
7156 | /* since we validated that L4 port must be valid before | |
7157 | * we get here, start with respective "flags" value | |
7158 | * and update if vlan is present or not | |
7159 | */ | |
7160 | cld_filter.element.flags = | |
7161 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT); | |
7162 | ||
7163 | if (filter->vlan_id) { | |
7164 | cld_filter.element.flags = | |
7165 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT); | |
4e3b35b0 | 7166 | } |
2f4b411a AN |
7167 | |
7168 | } else if (filter->dst_ipv4 || | |
7169 | !ipv6_addr_any(&filter->ip.v6.dst_ip6)) { | |
7170 | cld_filter.element.flags = | |
7171 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_IP_PORT); | |
7172 | if (filter->n_proto == ETH_P_IPV6) | |
7173 | cld_filter.element.flags |= | |
7174 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FLAGS_IPV6); | |
7175 | else | |
7176 | cld_filter.element.flags |= | |
7177 | cpu_to_le16(I40E_AQC_ADD_CLOUD_FLAGS_IPV4); | |
014269ff | 7178 | } else { |
2f4b411a AN |
7179 | dev_err(&pf->pdev->dev, |
7180 | "either mac or ip has to be valid for cloud filter\n"); | |
7181 | return -EINVAL; | |
4e3b35b0 NP |
7182 | } |
7183 | ||
2f4b411a AN |
7184 | /* Now copy L4 port in Byte 6..7 in general fields */ |
7185 | cld_filter.general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0] = | |
7186 | be16_to_cpu(filter->dst_port); | |
7187 | ||
7188 | if (add) { | |
7189 | /* Validate current device switch mode, change if necessary */ | |
7190 | ret = i40e_validate_and_set_switch_mode(vsi); | |
7191 | if (ret) { | |
7192 | dev_err(&pf->pdev->dev, | |
7193 | "failed to set switch mode, ret %d\n", | |
7194 | ret); | |
7195 | return ret; | |
7196 | } | |
7197 | ||
7198 | ret = i40e_aq_add_cloud_filters_bb(&pf->hw, filter->seid, | |
7199 | &cld_filter, 1); | |
7200 | } else { | |
7201 | ret = i40e_aq_rem_cloud_filters_bb(&pf->hw, filter->seid, | |
7202 | &cld_filter, 1); | |
7203 | } | |
7204 | ||
7205 | if (ret) | |
7206 | dev_dbg(&pf->pdev->dev, | |
7207 | "Failed to %s cloud filter(big buffer) err %d aq_err %d\n", | |
7208 | add ? "add" : "delete", ret, pf->hw.aq.asq_last_status); | |
7209 | else | |
7210 | dev_info(&pf->pdev->dev, | |
7211 | "%s cloud filter for VSI: %d, L4 port: %d\n", | |
7212 | add ? "add" : "delete", filter->seid, | |
7213 | ntohs(filter->dst_port)); | |
7214 | return ret; | |
4e3b35b0 | 7215 | } |
2f4b411a | 7216 | |
cf05ed08 | 7217 | /** |
2f4b411a AN |
7218 | * i40e_parse_cls_flower - Parse tc flower filters provided by kernel |
7219 | * @vsi: Pointer to VSI | |
7220 | * @cls_flower: Pointer to struct tc_cls_flower_offload | |
7221 | * @filter: Pointer to cloud filter structure | |
7222 | * | |
7223 | **/ | |
7224 | static int i40e_parse_cls_flower(struct i40e_vsi *vsi, | |
7225 | struct tc_cls_flower_offload *f, | |
7226 | struct i40e_cloud_filter *filter) | |
cf05ed08 | 7227 | { |
8f256622 PNA |
7228 | struct flow_rule *rule = tc_cls_flower_offload_flow_rule(f); |
7229 | struct flow_dissector *dissector = rule->match.dissector; | |
2f4b411a AN |
7230 | u16 n_proto_mask = 0, n_proto_key = 0, addr_type = 0; |
7231 | struct i40e_pf *pf = vsi->back; | |
7232 | u8 field_flags = 0; | |
7233 | ||
8f256622 | 7234 | if (dissector->used_keys & |
2f4b411a AN |
7235 | ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) | |
7236 | BIT(FLOW_DISSECTOR_KEY_BASIC) | | |
7237 | BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) | | |
7238 | BIT(FLOW_DISSECTOR_KEY_VLAN) | | |
7239 | BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) | | |
7240 | BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) | | |
7241 | BIT(FLOW_DISSECTOR_KEY_PORTS) | | |
7242 | BIT(FLOW_DISSECTOR_KEY_ENC_KEYID))) { | |
7243 | dev_err(&pf->pdev->dev, "Unsupported key used: 0x%x\n", | |
8f256622 | 7244 | dissector->used_keys); |
2f4b411a AN |
7245 | return -EOPNOTSUPP; |
7246 | } | |
cf05ed08 | 7247 | |
8f256622 PNA |
7248 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_KEYID)) { |
7249 | struct flow_match_enc_keyid match; | |
7ec9ba11 | 7250 | |
8f256622 PNA |
7251 | flow_rule_match_enc_keyid(rule, &match); |
7252 | if (match.mask->keyid != 0) | |
2f4b411a AN |
7253 | field_flags |= I40E_CLOUD_FIELD_TEN_ID; |
7254 | ||
8f256622 | 7255 | filter->tenant_id = be32_to_cpu(match.key->keyid); |
cf05ed08 JB |
7256 | } |
7257 | ||
8f256622 PNA |
7258 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) { |
7259 | struct flow_match_basic match; | |
2f4b411a | 7260 | |
8f256622 PNA |
7261 | flow_rule_match_basic(rule, &match); |
7262 | n_proto_key = ntohs(match.key->n_proto); | |
7263 | n_proto_mask = ntohs(match.mask->n_proto); | |
2f4b411a AN |
7264 | |
7265 | if (n_proto_key == ETH_P_ALL) { | |
7266 | n_proto_key = 0; | |
7267 | n_proto_mask = 0; | |
7268 | } | |
7269 | filter->n_proto = n_proto_key & n_proto_mask; | |
8f256622 | 7270 | filter->ip_proto = match.key->ip_proto; |
cf05ed08 JB |
7271 | } |
7272 | ||
8f256622 PNA |
7273 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) { |
7274 | struct flow_match_eth_addrs match; | |
2f4b411a | 7275 | |
8f256622 | 7276 | flow_rule_match_eth_addrs(rule, &match); |
2f4b411a AN |
7277 | |
7278 | /* use is_broadcast and is_zero to check for all 0xf or 0 */ | |
8f256622 PNA |
7279 | if (!is_zero_ether_addr(match.mask->dst)) { |
7280 | if (is_broadcast_ether_addr(match.mask->dst)) { | |
2f4b411a AN |
7281 | field_flags |= I40E_CLOUD_FIELD_OMAC; |
7282 | } else { | |
7283 | dev_err(&pf->pdev->dev, "Bad ether dest mask %pM\n", | |
8f256622 | 7284 | match.mask->dst); |
2f4b411a AN |
7285 | return I40E_ERR_CONFIG; |
7286 | } | |
7287 | } | |
7288 | ||
8f256622 PNA |
7289 | if (!is_zero_ether_addr(match.mask->src)) { |
7290 | if (is_broadcast_ether_addr(match.mask->src)) { | |
2f4b411a AN |
7291 | field_flags |= I40E_CLOUD_FIELD_IMAC; |
7292 | } else { | |
7293 | dev_err(&pf->pdev->dev, "Bad ether src mask %pM\n", | |
8f256622 | 7294 | match.mask->src); |
2f4b411a AN |
7295 | return I40E_ERR_CONFIG; |
7296 | } | |
7297 | } | |
8f256622 PNA |
7298 | ether_addr_copy(filter->dst_mac, match.key->dst); |
7299 | ether_addr_copy(filter->src_mac, match.key->src); | |
7300 | } | |
7301 | ||
7302 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN)) { | |
7303 | struct flow_match_vlan match; | |
7304 | ||
7305 | flow_rule_match_vlan(rule, &match); | |
7306 | if (match.mask->vlan_id) { | |
7307 | if (match.mask->vlan_id == VLAN_VID_MASK) { | |
2f4b411a | 7308 | field_flags |= I40E_CLOUD_FIELD_IVLAN; |
3e03d7cc | 7309 | |
2f4b411a AN |
7310 | } else { |
7311 | dev_err(&pf->pdev->dev, "Bad vlan mask 0x%04x\n", | |
8f256622 | 7312 | match.mask->vlan_id); |
2f4b411a AN |
7313 | return I40E_ERR_CONFIG; |
7314 | } | |
7315 | } | |
68e49702 | 7316 | |
8f256622 | 7317 | filter->vlan_id = cpu_to_be16(match.key->vlan_id); |
2f4b411a AN |
7318 | } |
7319 | ||
8f256622 PNA |
7320 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) { |
7321 | struct flow_match_control match; | |
2f4b411a | 7322 | |
8f256622 PNA |
7323 | flow_rule_match_control(rule, &match); |
7324 | addr_type = match.key->addr_type; | |
2f4b411a AN |
7325 | } |
7326 | ||
7327 | if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) { | |
8f256622 PNA |
7328 | struct flow_match_ipv4_addrs match; |
7329 | ||
7330 | flow_rule_match_ipv4_addrs(rule, &match); | |
7331 | if (match.mask->dst) { | |
7332 | if (match.mask->dst == cpu_to_be32(0xffffffff)) { | |
2f4b411a AN |
7333 | field_flags |= I40E_CLOUD_FIELD_IIP; |
7334 | } else { | |
bf1099b5 | 7335 | dev_err(&pf->pdev->dev, "Bad ip dst mask %pI4b\n", |
8f256622 | 7336 | &match.mask->dst); |
2f4b411a AN |
7337 | return I40E_ERR_CONFIG; |
7338 | } | |
7339 | } | |
7340 | ||
8f256622 PNA |
7341 | if (match.mask->src) { |
7342 | if (match.mask->src == cpu_to_be32(0xffffffff)) { | |
2f4b411a AN |
7343 | field_flags |= I40E_CLOUD_FIELD_IIP; |
7344 | } else { | |
bf1099b5 | 7345 | dev_err(&pf->pdev->dev, "Bad ip src mask %pI4b\n", |
8f256622 | 7346 | &match.mask->src); |
2f4b411a AN |
7347 | return I40E_ERR_CONFIG; |
7348 | } | |
7349 | } | |
7350 | ||
7351 | if (field_flags & I40E_CLOUD_FIELD_TEN_ID) { | |
7352 | dev_err(&pf->pdev->dev, "Tenant id not allowed for ip filter\n"); | |
7353 | return I40E_ERR_CONFIG; | |
7354 | } | |
8f256622 PNA |
7355 | filter->dst_ipv4 = match.key->dst; |
7356 | filter->src_ipv4 = match.key->src; | |
2f4b411a AN |
7357 | } |
7358 | ||
7359 | if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) { | |
8f256622 PNA |
7360 | struct flow_match_ipv6_addrs match; |
7361 | ||
7362 | flow_rule_match_ipv6_addrs(rule, &match); | |
2f4b411a AN |
7363 | |
7364 | /* src and dest IPV6 address should not be LOOPBACK | |
7365 | * (0:0:0:0:0:0:0:1), which can be represented as ::1 | |
68e49702 | 7366 | */ |
8f256622 PNA |
7367 | if (ipv6_addr_loopback(&match.key->dst) || |
7368 | ipv6_addr_loopback(&match.key->src)) { | |
2f4b411a AN |
7369 | dev_err(&pf->pdev->dev, |
7370 | "Bad ipv6, addr is LOOPBACK\n"); | |
7371 | return I40E_ERR_CONFIG; | |
7372 | } | |
8f256622 PNA |
7373 | if (!ipv6_addr_any(&match.mask->dst) || |
7374 | !ipv6_addr_any(&match.mask->src)) | |
2f4b411a AN |
7375 | field_flags |= I40E_CLOUD_FIELD_IIP; |
7376 | ||
8f256622 | 7377 | memcpy(&filter->src_ipv6, &match.key->src.s6_addr32, |
2f4b411a | 7378 | sizeof(filter->src_ipv6)); |
8f256622 | 7379 | memcpy(&filter->dst_ipv6, &match.key->dst.s6_addr32, |
2f4b411a AN |
7380 | sizeof(filter->dst_ipv6)); |
7381 | } | |
7382 | ||
8f256622 PNA |
7383 | if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) { |
7384 | struct flow_match_ports match; | |
2f4b411a | 7385 | |
8f256622 PNA |
7386 | flow_rule_match_ports(rule, &match); |
7387 | if (match.mask->src) { | |
7388 | if (match.mask->src == cpu_to_be16(0xffff)) { | |
2f4b411a AN |
7389 | field_flags |= I40E_CLOUD_FIELD_IIP; |
7390 | } else { | |
7391 | dev_err(&pf->pdev->dev, "Bad src port mask 0x%04x\n", | |
8f256622 | 7392 | be16_to_cpu(match.mask->src)); |
2f4b411a AN |
7393 | return I40E_ERR_CONFIG; |
7394 | } | |
7395 | } | |
7396 | ||
8f256622 PNA |
7397 | if (match.mask->dst) { |
7398 | if (match.mask->dst == cpu_to_be16(0xffff)) { | |
2f4b411a AN |
7399 | field_flags |= I40E_CLOUD_FIELD_IIP; |
7400 | } else { | |
7401 | dev_err(&pf->pdev->dev, "Bad dst port mask 0x%04x\n", | |
8f256622 | 7402 | be16_to_cpu(match.mask->dst)); |
2f4b411a AN |
7403 | return I40E_ERR_CONFIG; |
7404 | } | |
7405 | } | |
7406 | ||
8f256622 PNA |
7407 | filter->dst_port = match.key->dst; |
7408 | filter->src_port = match.key->src; | |
2f4b411a AN |
7409 | |
7410 | switch (filter->ip_proto) { | |
7411 | case IPPROTO_TCP: | |
7412 | case IPPROTO_UDP: | |
7413 | break; | |
7414 | default: | |
7415 | dev_err(&pf->pdev->dev, | |
7416 | "Only UDP and TCP transport are supported\n"); | |
7417 | return -EINVAL; | |
68e49702 | 7418 | } |
3e03d7cc | 7419 | } |
2f4b411a AN |
7420 | filter->flags = field_flags; |
7421 | return 0; | |
7422 | } | |
3e03d7cc | 7423 | |
2f4b411a AN |
7424 | /** |
7425 | * i40e_handle_tclass: Forward to a traffic class on the device | |
7426 | * @vsi: Pointer to VSI | |
7427 | * @tc: traffic class index on the device | |
7428 | * @filter: Pointer to cloud filter structure | |
7429 | * | |
7430 | **/ | |
7431 | static int i40e_handle_tclass(struct i40e_vsi *vsi, u32 tc, | |
7432 | struct i40e_cloud_filter *filter) | |
7433 | { | |
7434 | struct i40e_channel *ch, *ch_tmp; | |
7435 | ||
7436 | /* direct to a traffic class on the same device */ | |
7437 | if (tc == 0) { | |
7438 | filter->seid = vsi->seid; | |
7439 | return 0; | |
7440 | } else if (vsi->tc_config.enabled_tc & BIT(tc)) { | |
7441 | if (!filter->dst_port) { | |
7442 | dev_err(&vsi->back->pdev->dev, | |
7443 | "Specify destination port to direct to traffic class that is not default\n"); | |
7444 | return -EINVAL; | |
7445 | } | |
7446 | if (list_empty(&vsi->ch_list)) | |
7447 | return -EINVAL; | |
7448 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, | |
7449 | list) { | |
7450 | if (ch->seid == vsi->tc_seid_map[tc]) | |
7451 | filter->seid = ch->seid; | |
7452 | } | |
7453 | return 0; | |
7454 | } | |
7455 | dev_err(&vsi->back->pdev->dev, "TC is not enabled\n"); | |
7456 | return -EINVAL; | |
cf05ed08 | 7457 | } |
4e3b35b0 | 7458 | |
41c445ff | 7459 | /** |
2f4b411a AN |
7460 | * i40e_configure_clsflower - Configure tc flower filters |
7461 | * @vsi: Pointer to VSI | |
7462 | * @cls_flower: Pointer to struct tc_cls_flower_offload | |
7463 | * | |
41c445ff | 7464 | **/ |
2f4b411a AN |
7465 | static int i40e_configure_clsflower(struct i40e_vsi *vsi, |
7466 | struct tc_cls_flower_offload *cls_flower) | |
41c445ff | 7467 | { |
2f4b411a AN |
7468 | int tc = tc_classid_to_hwtc(vsi->netdev, cls_flower->classid); |
7469 | struct i40e_cloud_filter *filter = NULL; | |
41c445ff | 7470 | struct i40e_pf *pf = vsi->back; |
2f4b411a | 7471 | int err = 0; |
41c445ff | 7472 | |
2f4b411a AN |
7473 | if (tc < 0) { |
7474 | dev_err(&vsi->back->pdev->dev, "Invalid traffic class\n"); | |
bc4244c6 | 7475 | return -EOPNOTSUPP; |
2f4b411a | 7476 | } |
41c445ff | 7477 | |
2f4b411a AN |
7478 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) || |
7479 | test_bit(__I40E_RESET_INTR_RECEIVED, pf->state)) | |
7480 | return -EBUSY; | |
41c445ff | 7481 | |
2f4b411a AN |
7482 | if (pf->fdir_pf_active_filters || |
7483 | (!hlist_empty(&pf->fdir_filter_list))) { | |
7484 | dev_err(&vsi->back->pdev->dev, | |
7485 | "Flow Director Sideband filters exists, turn ntuple off to configure cloud filters\n"); | |
7486 | return -EINVAL; | |
7487 | } | |
41c445ff | 7488 | |
2f4b411a AN |
7489 | if (vsi->back->flags & I40E_FLAG_FD_SB_ENABLED) { |
7490 | dev_err(&vsi->back->pdev->dev, | |
7491 | "Disable Flow Director Sideband, configuring Cloud filters via tc-flower\n"); | |
7492 | vsi->back->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
7493 | vsi->back->flags |= I40E_FLAG_FD_SB_TO_CLOUD_FILTER; | |
41c445ff | 7494 | } |
ca64fa4e | 7495 | |
2f4b411a AN |
7496 | filter = kzalloc(sizeof(*filter), GFP_KERNEL); |
7497 | if (!filter) | |
7498 | return -ENOMEM; | |
7499 | ||
7500 | filter->cookie = cls_flower->cookie; | |
7501 | ||
7502 | err = i40e_parse_cls_flower(vsi, cls_flower, filter); | |
7503 | if (err < 0) | |
7504 | goto err; | |
7505 | ||
7506 | err = i40e_handle_tclass(vsi, tc, filter); | |
7507 | if (err < 0) | |
7508 | goto err; | |
7509 | ||
7510 | /* Add cloud filter */ | |
7511 | if (filter->dst_port) | |
7512 | err = i40e_add_del_cloud_filter_big_buf(vsi, filter, true); | |
7513 | else | |
7514 | err = i40e_add_del_cloud_filter(vsi, filter, true); | |
7515 | ||
7516 | if (err) { | |
7517 | dev_err(&pf->pdev->dev, | |
7518 | "Failed to add cloud filter, err %s\n", | |
7519 | i40e_stat_str(&pf->hw, err)); | |
2f4b411a | 7520 | goto err; |
1e1be8f6 | 7521 | } |
e3219ce6 | 7522 | |
2f4b411a AN |
7523 | /* add filter to the ordered list */ |
7524 | INIT_HLIST_NODE(&filter->cloud_node); | |
41c445ff | 7525 | |
2f4b411a AN |
7526 | hlist_add_head(&filter->cloud_node, &pf->cloud_filter_list); |
7527 | ||
7528 | pf->num_cloud_filters++; | |
7529 | ||
7530 | return err; | |
7531 | err: | |
7532 | kfree(filter); | |
7533 | return err; | |
41c445ff JB |
7534 | } |
7535 | ||
7536 | /** | |
2f4b411a AN |
7537 | * i40e_find_cloud_filter - Find the could filter in the list |
7538 | * @vsi: Pointer to VSI | |
7539 | * @cookie: filter specific cookie | |
41c445ff | 7540 | * |
41c445ff | 7541 | **/ |
2f4b411a AN |
7542 | static struct i40e_cloud_filter *i40e_find_cloud_filter(struct i40e_vsi *vsi, |
7543 | unsigned long *cookie) | |
41c445ff | 7544 | { |
2f4b411a AN |
7545 | struct i40e_cloud_filter *filter = NULL; |
7546 | struct hlist_node *node2; | |
41c445ff | 7547 | |
2f4b411a AN |
7548 | hlist_for_each_entry_safe(filter, node2, |
7549 | &vsi->back->cloud_filter_list, cloud_node) | |
7550 | if (!memcmp(cookie, &filter->cookie, sizeof(filter->cookie))) | |
7551 | return filter; | |
7552 | return NULL; | |
41c445ff JB |
7553 | } |
7554 | ||
7555 | /** | |
2f4b411a AN |
7556 | * i40e_delete_clsflower - Remove tc flower filters |
7557 | * @vsi: Pointer to VSI | |
7558 | * @cls_flower: Pointer to struct tc_cls_flower_offload | |
7559 | * | |
41c445ff | 7560 | **/ |
2f4b411a AN |
7561 | static int i40e_delete_clsflower(struct i40e_vsi *vsi, |
7562 | struct tc_cls_flower_offload *cls_flower) | |
41c445ff | 7563 | { |
2f4b411a AN |
7564 | struct i40e_cloud_filter *filter = NULL; |
7565 | struct i40e_pf *pf = vsi->back; | |
7566 | int err = 0; | |
41c445ff | 7567 | |
2f4b411a | 7568 | filter = i40e_find_cloud_filter(vsi, &cls_flower->cookie); |
41c445ff | 7569 | |
2f4b411a AN |
7570 | if (!filter) |
7571 | return -EINVAL; | |
41c445ff | 7572 | |
2f4b411a | 7573 | hash_del(&filter->cloud_node); |
41c445ff | 7574 | |
2f4b411a AN |
7575 | if (filter->dst_port) |
7576 | err = i40e_add_del_cloud_filter_big_buf(vsi, filter, false); | |
7577 | else | |
7578 | err = i40e_add_del_cloud_filter(vsi, filter, false); | |
41c445ff | 7579 | |
2f4b411a AN |
7580 | kfree(filter); |
7581 | if (err) { | |
7582 | dev_err(&pf->pdev->dev, | |
7583 | "Failed to delete cloud filter, err %s\n", | |
7584 | i40e_stat_str(&pf->hw, err)); | |
7585 | return i40e_aq_rc_to_posix(err, pf->hw.aq.asq_last_status); | |
41c445ff | 7586 | } |
f980d445 | 7587 | |
2f4b411a AN |
7588 | pf->num_cloud_filters--; |
7589 | if (!pf->num_cloud_filters) | |
7590 | if ((pf->flags & I40E_FLAG_FD_SB_TO_CLOUD_FILTER) && | |
7591 | !(pf->flags & I40E_FLAG_FD_SB_INACTIVE)) { | |
7592 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
7593 | pf->flags &= ~I40E_FLAG_FD_SB_TO_CLOUD_FILTER; | |
7594 | pf->flags &= ~I40E_FLAG_FD_SB_INACTIVE; | |
7595 | } | |
7596 | return 0; | |
41c445ff JB |
7597 | } |
7598 | ||
7599 | /** | |
2f4b411a | 7600 | * i40e_setup_tc_cls_flower - flower classifier offloads |
41c445ff | 7601 | * @netdev: net device to configure |
2f4b411a | 7602 | * @type_data: offload data |
41c445ff | 7603 | **/ |
2f4b411a AN |
7604 | static int i40e_setup_tc_cls_flower(struct i40e_netdev_priv *np, |
7605 | struct tc_cls_flower_offload *cls_flower) | |
41c445ff | 7606 | { |
41c445ff | 7607 | struct i40e_vsi *vsi = np->vsi; |
41c445ff | 7608 | |
2f4b411a AN |
7609 | switch (cls_flower->command) { |
7610 | case TC_CLSFLOWER_REPLACE: | |
7611 | return i40e_configure_clsflower(vsi, cls_flower); | |
7612 | case TC_CLSFLOWER_DESTROY: | |
7613 | return i40e_delete_clsflower(vsi, cls_flower); | |
7614 | case TC_CLSFLOWER_STATS: | |
7615 | return -EOPNOTSUPP; | |
7616 | default: | |
246ab6f0 | 7617 | return -EOPNOTSUPP; |
41c445ff | 7618 | } |
2f4b411a | 7619 | } |
41c445ff | 7620 | |
2f4b411a AN |
7621 | static int i40e_setup_tc_block_cb(enum tc_setup_type type, void *type_data, |
7622 | void *cb_priv) | |
7623 | { | |
7624 | struct i40e_netdev_priv *np = cb_priv; | |
41c445ff | 7625 | |
a0d8637f JK |
7626 | if (!tc_cls_can_offload_and_chain0(np->vsi->netdev, type_data)) |
7627 | return -EOPNOTSUPP; | |
7628 | ||
2f4b411a AN |
7629 | switch (type) { |
7630 | case TC_SETUP_CLSFLOWER: | |
7631 | return i40e_setup_tc_cls_flower(np, type_data); | |
41c445ff | 7632 | |
2f4b411a AN |
7633 | default: |
7634 | return -EOPNOTSUPP; | |
41c445ff | 7635 | } |
2f4b411a | 7636 | } |
41c445ff | 7637 | |
2f4b411a AN |
7638 | static int i40e_setup_tc_block(struct net_device *dev, |
7639 | struct tc_block_offload *f) | |
7640 | { | |
7641 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
41c445ff | 7642 | |
2f4b411a AN |
7643 | if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS) |
7644 | return -EOPNOTSUPP; | |
7645 | ||
7646 | switch (f->command) { | |
7647 | case TC_BLOCK_BIND: | |
7648 | return tcf_block_cb_register(f->block, i40e_setup_tc_block_cb, | |
60513bd8 | 7649 | np, np, f->extack); |
2f4b411a AN |
7650 | case TC_BLOCK_UNBIND: |
7651 | tcf_block_cb_unregister(f->block, i40e_setup_tc_block_cb, np); | |
7652 | return 0; | |
7653 | default: | |
7654 | return -EOPNOTSUPP; | |
7655 | } | |
41c445ff JB |
7656 | } |
7657 | ||
2572ac53 | 7658 | static int __i40e_setup_tc(struct net_device *netdev, enum tc_setup_type type, |
de4784ca | 7659 | void *type_data) |
e4c6734e | 7660 | { |
2f4b411a | 7661 | switch (type) { |
575ed7d3 | 7662 | case TC_SETUP_QDISC_MQPRIO: |
2f4b411a AN |
7663 | return i40e_setup_tc(netdev, type_data); |
7664 | case TC_SETUP_BLOCK: | |
7665 | return i40e_setup_tc_block(netdev, type_data); | |
7666 | default: | |
38cf0426 | 7667 | return -EOPNOTSUPP; |
2f4b411a | 7668 | } |
e4c6734e JF |
7669 | } |
7670 | ||
41c445ff JB |
7671 | /** |
7672 | * i40e_open - Called when a network interface is made active | |
7673 | * @netdev: network interface device structure | |
7674 | * | |
7675 | * The open entry point is called when a network interface is made | |
7676 | * active by the system (IFF_UP). At this point all resources needed | |
7677 | * for transmit and receive operations are allocated, the interrupt | |
7678 | * handler is registered with the OS, the netdev watchdog subtask is | |
7679 | * enabled, and the stack is notified that the interface is ready. | |
7680 | * | |
7681 | * Returns 0 on success, negative value on failure | |
7682 | **/ | |
38e00438 | 7683 | int i40e_open(struct net_device *netdev) |
41c445ff JB |
7684 | { |
7685 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
7686 | struct i40e_vsi *vsi = np->vsi; | |
7687 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
7688 | int err; |
7689 | ||
4eb3f768 | 7690 | /* disallow open during test or if eeprom is broken */ |
0da36b97 JK |
7691 | if (test_bit(__I40E_TESTING, pf->state) || |
7692 | test_bit(__I40E_BAD_EEPROM, pf->state)) | |
41c445ff JB |
7693 | return -EBUSY; |
7694 | ||
7695 | netif_carrier_off(netdev); | |
7696 | ||
c3880bd1 MS |
7697 | if (i40e_force_link_state(pf, true)) |
7698 | return -EAGAIN; | |
7699 | ||
6c167f58 EK |
7700 | err = i40e_vsi_open(vsi); |
7701 | if (err) | |
7702 | return err; | |
7703 | ||
059dab69 JB |
7704 | /* configure global TSO hardware offload settings */ |
7705 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH | | |
7706 | TCP_FLAG_FIN) >> 16); | |
7707 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH | | |
7708 | TCP_FLAG_FIN | | |
7709 | TCP_FLAG_CWR) >> 16); | |
7710 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16); | |
7711 | ||
06a5f7f1 | 7712 | udp_tunnel_get_rx_info(netdev); |
e3219ce6 | 7713 | |
6c167f58 EK |
7714 | return 0; |
7715 | } | |
7716 | ||
7717 | /** | |
7718 | * i40e_vsi_open - | |
7719 | * @vsi: the VSI to open | |
7720 | * | |
7721 | * Finish initialization of the VSI. | |
7722 | * | |
7723 | * Returns 0 on success, negative value on failure | |
373149fc MS |
7724 | * |
7725 | * Note: expects to be called while under rtnl_lock() | |
6c167f58 EK |
7726 | **/ |
7727 | int i40e_vsi_open(struct i40e_vsi *vsi) | |
7728 | { | |
7729 | struct i40e_pf *pf = vsi->back; | |
b294ac70 | 7730 | char int_name[I40E_INT_NAME_STR_LEN]; |
6c167f58 EK |
7731 | int err; |
7732 | ||
41c445ff JB |
7733 | /* allocate descriptors */ |
7734 | err = i40e_vsi_setup_tx_resources(vsi); | |
7735 | if (err) | |
7736 | goto err_setup_tx; | |
7737 | err = i40e_vsi_setup_rx_resources(vsi); | |
7738 | if (err) | |
7739 | goto err_setup_rx; | |
7740 | ||
7741 | err = i40e_vsi_configure(vsi); | |
7742 | if (err) | |
7743 | goto err_setup_rx; | |
7744 | ||
c22e3c6c SN |
7745 | if (vsi->netdev) { |
7746 | snprintf(int_name, sizeof(int_name) - 1, "%s-%s", | |
7747 | dev_driver_string(&pf->pdev->dev), vsi->netdev->name); | |
7748 | err = i40e_vsi_request_irq(vsi, int_name); | |
7749 | if (err) | |
7750 | goto err_setup_rx; | |
41c445ff | 7751 | |
c22e3c6c SN |
7752 | /* Notify the stack of the actual queue counts. */ |
7753 | err = netif_set_real_num_tx_queues(vsi->netdev, | |
7754 | vsi->num_queue_pairs); | |
7755 | if (err) | |
7756 | goto err_set_queues; | |
25946ddb | 7757 | |
c22e3c6c SN |
7758 | err = netif_set_real_num_rx_queues(vsi->netdev, |
7759 | vsi->num_queue_pairs); | |
7760 | if (err) | |
7761 | goto err_set_queues; | |
8a9eb7d3 SN |
7762 | |
7763 | } else if (vsi->type == I40E_VSI_FDIR) { | |
e240f674 | 7764 | snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir", |
b2008cbf CW |
7765 | dev_driver_string(&pf->pdev->dev), |
7766 | dev_name(&pf->pdev->dev)); | |
8a9eb7d3 | 7767 | err = i40e_vsi_request_irq(vsi, int_name); |
b2008cbf | 7768 | |
c22e3c6c | 7769 | } else { |
ce9ccb17 | 7770 | err = -EINVAL; |
6c167f58 EK |
7771 | goto err_setup_rx; |
7772 | } | |
25946ddb | 7773 | |
41c445ff JB |
7774 | err = i40e_up_complete(vsi); |
7775 | if (err) | |
7776 | goto err_up_complete; | |
7777 | ||
41c445ff JB |
7778 | return 0; |
7779 | ||
7780 | err_up_complete: | |
7781 | i40e_down(vsi); | |
25946ddb | 7782 | err_set_queues: |
41c445ff JB |
7783 | i40e_vsi_free_irq(vsi); |
7784 | err_setup_rx: | |
7785 | i40e_vsi_free_rx_resources(vsi); | |
7786 | err_setup_tx: | |
7787 | i40e_vsi_free_tx_resources(vsi); | |
7788 | if (vsi == pf->vsi[pf->lan_vsi]) | |
ff424188 | 7789 | i40e_do_reset(pf, I40E_PF_RESET_FLAG, true); |
41c445ff JB |
7790 | |
7791 | return err; | |
7792 | } | |
7793 | ||
17a73f6b JG |
7794 | /** |
7795 | * i40e_fdir_filter_exit - Cleans up the Flow Director accounting | |
b40c82e6 | 7796 | * @pf: Pointer to PF |
17a73f6b JG |
7797 | * |
7798 | * This function destroys the hlist where all the Flow Director | |
7799 | * filters were saved. | |
7800 | **/ | |
7801 | static void i40e_fdir_filter_exit(struct i40e_pf *pf) | |
7802 | { | |
7803 | struct i40e_fdir_filter *filter; | |
0e588de1 | 7804 | struct i40e_flex_pit *pit_entry, *tmp; |
17a73f6b JG |
7805 | struct hlist_node *node2; |
7806 | ||
7807 | hlist_for_each_entry_safe(filter, node2, | |
7808 | &pf->fdir_filter_list, fdir_node) { | |
7809 | hlist_del(&filter->fdir_node); | |
7810 | kfree(filter); | |
7811 | } | |
097dbf52 | 7812 | |
0e588de1 JK |
7813 | list_for_each_entry_safe(pit_entry, tmp, &pf->l3_flex_pit_list, list) { |
7814 | list_del(&pit_entry->list); | |
7815 | kfree(pit_entry); | |
7816 | } | |
7817 | INIT_LIST_HEAD(&pf->l3_flex_pit_list); | |
7818 | ||
7819 | list_for_each_entry_safe(pit_entry, tmp, &pf->l4_flex_pit_list, list) { | |
7820 | list_del(&pit_entry->list); | |
7821 | kfree(pit_entry); | |
7822 | } | |
7823 | INIT_LIST_HEAD(&pf->l4_flex_pit_list); | |
7824 | ||
17a73f6b | 7825 | pf->fdir_pf_active_filters = 0; |
097dbf52 JK |
7826 | pf->fd_tcp4_filter_cnt = 0; |
7827 | pf->fd_udp4_filter_cnt = 0; | |
f223c875 | 7828 | pf->fd_sctp4_filter_cnt = 0; |
097dbf52 | 7829 | pf->fd_ip4_filter_cnt = 0; |
3bcee1e6 JK |
7830 | |
7831 | /* Reprogram the default input set for TCP/IPv4 */ | |
7832 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_TCP, | |
7833 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
7834 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
7835 | ||
7836 | /* Reprogram the default input set for UDP/IPv4 */ | |
7837 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_UDP, | |
7838 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
7839 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
7840 | ||
7841 | /* Reprogram the default input set for SCTP/IPv4 */ | |
7842 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_SCTP, | |
7843 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
7844 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
7845 | ||
7846 | /* Reprogram the default input set for Other/IPv4 */ | |
7847 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_OTHER, | |
7848 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK); | |
02b4016b JK |
7849 | |
7850 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_FRAG_IPV4, | |
7851 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK); | |
17a73f6b JG |
7852 | } |
7853 | ||
aaf66502 AN |
7854 | /** |
7855 | * i40e_cloud_filter_exit - Cleans up the cloud filters | |
7856 | * @pf: Pointer to PF | |
7857 | * | |
7858 | * This function destroys the hlist where all the cloud filters | |
7859 | * were saved. | |
7860 | **/ | |
7861 | static void i40e_cloud_filter_exit(struct i40e_pf *pf) | |
7862 | { | |
7863 | struct i40e_cloud_filter *cfilter; | |
7864 | struct hlist_node *node; | |
7865 | ||
7866 | hlist_for_each_entry_safe(cfilter, node, | |
7867 | &pf->cloud_filter_list, cloud_node) { | |
7868 | hlist_del(&cfilter->cloud_node); | |
7869 | kfree(cfilter); | |
7870 | } | |
7871 | pf->num_cloud_filters = 0; | |
2f4b411a AN |
7872 | |
7873 | if ((pf->flags & I40E_FLAG_FD_SB_TO_CLOUD_FILTER) && | |
7874 | !(pf->flags & I40E_FLAG_FD_SB_INACTIVE)) { | |
7875 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
7876 | pf->flags &= ~I40E_FLAG_FD_SB_TO_CLOUD_FILTER; | |
7877 | pf->flags &= ~I40E_FLAG_FD_SB_INACTIVE; | |
7878 | } | |
aaf66502 AN |
7879 | } |
7880 | ||
41c445ff JB |
7881 | /** |
7882 | * i40e_close - Disables a network interface | |
7883 | * @netdev: network interface device structure | |
7884 | * | |
7885 | * The close entry point is called when an interface is de-activated | |
7886 | * by the OS. The hardware is still under the driver's control, but | |
7887 | * this netdev interface is disabled. | |
7888 | * | |
7889 | * Returns 0, this is not allowed to fail | |
7890 | **/ | |
38e00438 | 7891 | int i40e_close(struct net_device *netdev) |
41c445ff JB |
7892 | { |
7893 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
7894 | struct i40e_vsi *vsi = np->vsi; | |
7895 | ||
90ef8d47 | 7896 | i40e_vsi_close(vsi); |
41c445ff JB |
7897 | |
7898 | return 0; | |
7899 | } | |
7900 | ||
7901 | /** | |
7902 | * i40e_do_reset - Start a PF or Core Reset sequence | |
7903 | * @pf: board private structure | |
7904 | * @reset_flags: which reset is requested | |
373149fc MS |
7905 | * @lock_acquired: indicates whether or not the lock has been acquired |
7906 | * before this function was called. | |
41c445ff JB |
7907 | * |
7908 | * The essential difference in resets is that the PF Reset | |
7909 | * doesn't clear the packet buffers, doesn't reset the PE | |
7910 | * firmware, and doesn't bother the other PFs on the chip. | |
7911 | **/ | |
373149fc | 7912 | void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired) |
41c445ff JB |
7913 | { |
7914 | u32 val; | |
7915 | ||
7916 | WARN_ON(in_interrupt()); | |
7917 | ||
263fc48f | 7918 | |
41c445ff | 7919 | /* do the biggest reset indicated */ |
41a1d04b | 7920 | if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) { |
41c445ff JB |
7921 | |
7922 | /* Request a Global Reset | |
7923 | * | |
7924 | * This will start the chip's countdown to the actual full | |
7925 | * chip reset event, and a warning interrupt to be sent | |
7926 | * to all PFs, including the requestor. Our handler | |
7927 | * for the warning interrupt will deal with the shutdown | |
7928 | * and recovery of the switch setup. | |
7929 | */ | |
69bfb110 | 7930 | dev_dbg(&pf->pdev->dev, "GlobalR requested\n"); |
41c445ff JB |
7931 | val = rd32(&pf->hw, I40E_GLGEN_RTRIG); |
7932 | val |= I40E_GLGEN_RTRIG_GLOBR_MASK; | |
7933 | wr32(&pf->hw, I40E_GLGEN_RTRIG, val); | |
7934 | ||
41a1d04b | 7935 | } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) { |
41c445ff JB |
7936 | |
7937 | /* Request a Core Reset | |
7938 | * | |
7939 | * Same as Global Reset, except does *not* include the MAC/PHY | |
7940 | */ | |
69bfb110 | 7941 | dev_dbg(&pf->pdev->dev, "CoreR requested\n"); |
41c445ff JB |
7942 | val = rd32(&pf->hw, I40E_GLGEN_RTRIG); |
7943 | val |= I40E_GLGEN_RTRIG_CORER_MASK; | |
7944 | wr32(&pf->hw, I40E_GLGEN_RTRIG, val); | |
7945 | i40e_flush(&pf->hw); | |
7946 | ||
ff424188 | 7947 | } else if (reset_flags & I40E_PF_RESET_FLAG) { |
41c445ff JB |
7948 | |
7949 | /* Request a PF Reset | |
7950 | * | |
7951 | * Resets only the PF-specific registers | |
7952 | * | |
7953 | * This goes directly to the tear-down and rebuild of | |
7954 | * the switch, since we need to do all the recovery as | |
7955 | * for the Core Reset. | |
7956 | */ | |
69bfb110 | 7957 | dev_dbg(&pf->pdev->dev, "PFR requested\n"); |
373149fc | 7958 | i40e_handle_reset_warning(pf, lock_acquired); |
41c445ff | 7959 | |
41a1d04b | 7960 | } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) { |
41c445ff JB |
7961 | int v; |
7962 | ||
7963 | /* Find the VSI(s) that requested a re-init */ | |
7964 | dev_info(&pf->pdev->dev, | |
7965 | "VSI reinit requested\n"); | |
505682cd | 7966 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff | 7967 | struct i40e_vsi *vsi = pf->vsi[v]; |
6995b36c | 7968 | |
41c445ff | 7969 | if (vsi != NULL && |
d19cb64b | 7970 | test_and_clear_bit(__I40E_VSI_REINIT_REQUESTED, |
0da36b97 | 7971 | vsi->state)) |
41c445ff | 7972 | i40e_vsi_reinit_locked(pf->vsi[v]); |
41c445ff | 7973 | } |
41a1d04b | 7974 | } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) { |
b5d06f05 NP |
7975 | int v; |
7976 | ||
7977 | /* Find the VSI(s) that needs to be brought down */ | |
7978 | dev_info(&pf->pdev->dev, "VSI down requested\n"); | |
7979 | for (v = 0; v < pf->num_alloc_vsi; v++) { | |
7980 | struct i40e_vsi *vsi = pf->vsi[v]; | |
6995b36c | 7981 | |
b5d06f05 | 7982 | if (vsi != NULL && |
d19cb64b | 7983 | test_and_clear_bit(__I40E_VSI_DOWN_REQUESTED, |
0da36b97 JK |
7984 | vsi->state)) { |
7985 | set_bit(__I40E_VSI_DOWN, vsi->state); | |
b5d06f05 | 7986 | i40e_down(vsi); |
b5d06f05 NP |
7987 | } |
7988 | } | |
41c445ff JB |
7989 | } else { |
7990 | dev_info(&pf->pdev->dev, | |
7991 | "bad reset request 0x%08x\n", reset_flags); | |
41c445ff JB |
7992 | } |
7993 | } | |
7994 | ||
4e3b35b0 NP |
7995 | #ifdef CONFIG_I40E_DCB |
7996 | /** | |
7997 | * i40e_dcb_need_reconfig - Check if DCB needs reconfig | |
7998 | * @pf: board private structure | |
7999 | * @old_cfg: current DCB config | |
8000 | * @new_cfg: new DCB config | |
8001 | **/ | |
8002 | bool i40e_dcb_need_reconfig(struct i40e_pf *pf, | |
8003 | struct i40e_dcbx_config *old_cfg, | |
8004 | struct i40e_dcbx_config *new_cfg) | |
8005 | { | |
8006 | bool need_reconfig = false; | |
8007 | ||
8008 | /* Check if ETS configuration has changed */ | |
8009 | if (memcmp(&new_cfg->etscfg, | |
8010 | &old_cfg->etscfg, | |
8011 | sizeof(new_cfg->etscfg))) { | |
8012 | /* If Priority Table has changed reconfig is needed */ | |
8013 | if (memcmp(&new_cfg->etscfg.prioritytable, | |
8014 | &old_cfg->etscfg.prioritytable, | |
8015 | sizeof(new_cfg->etscfg.prioritytable))) { | |
8016 | need_reconfig = true; | |
69bfb110 | 8017 | dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n"); |
4e3b35b0 NP |
8018 | } |
8019 | ||
8020 | if (memcmp(&new_cfg->etscfg.tcbwtable, | |
8021 | &old_cfg->etscfg.tcbwtable, | |
8022 | sizeof(new_cfg->etscfg.tcbwtable))) | |
69bfb110 | 8023 | dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n"); |
4e3b35b0 NP |
8024 | |
8025 | if (memcmp(&new_cfg->etscfg.tsatable, | |
8026 | &old_cfg->etscfg.tsatable, | |
8027 | sizeof(new_cfg->etscfg.tsatable))) | |
69bfb110 | 8028 | dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n"); |
4e3b35b0 NP |
8029 | } |
8030 | ||
8031 | /* Check if PFC configuration has changed */ | |
8032 | if (memcmp(&new_cfg->pfc, | |
8033 | &old_cfg->pfc, | |
8034 | sizeof(new_cfg->pfc))) { | |
8035 | need_reconfig = true; | |
69bfb110 | 8036 | dev_dbg(&pf->pdev->dev, "PFC config change detected.\n"); |
4e3b35b0 NP |
8037 | } |
8038 | ||
8039 | /* Check if APP Table has changed */ | |
8040 | if (memcmp(&new_cfg->app, | |
8041 | &old_cfg->app, | |
3d9667a9 | 8042 | sizeof(new_cfg->app))) { |
4e3b35b0 | 8043 | need_reconfig = true; |
69bfb110 | 8044 | dev_dbg(&pf->pdev->dev, "APP Table change detected.\n"); |
3d9667a9 | 8045 | } |
4e3b35b0 | 8046 | |
fb43201f | 8047 | dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig); |
4e3b35b0 NP |
8048 | return need_reconfig; |
8049 | } | |
8050 | ||
8051 | /** | |
8052 | * i40e_handle_lldp_event - Handle LLDP Change MIB event | |
8053 | * @pf: board private structure | |
8054 | * @e: event info posted on ARQ | |
8055 | **/ | |
8056 | static int i40e_handle_lldp_event(struct i40e_pf *pf, | |
8057 | struct i40e_arq_event_info *e) | |
8058 | { | |
8059 | struct i40e_aqc_lldp_get_mib *mib = | |
8060 | (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw; | |
8061 | struct i40e_hw *hw = &pf->hw; | |
4e3b35b0 NP |
8062 | struct i40e_dcbx_config tmp_dcbx_cfg; |
8063 | bool need_reconfig = false; | |
8064 | int ret = 0; | |
8065 | u8 type; | |
8066 | ||
4d9b6043 | 8067 | /* Not DCB capable or capability disabled */ |
ea6acb7e | 8068 | if (!(pf->flags & I40E_FLAG_DCB_CAPABLE)) |
4d9b6043 NP |
8069 | return ret; |
8070 | ||
4e3b35b0 NP |
8071 | /* Ignore if event is not for Nearest Bridge */ |
8072 | type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) | |
8073 | & I40E_AQ_LLDP_BRIDGE_TYPE_MASK); | |
fb43201f | 8074 | dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type); |
4e3b35b0 NP |
8075 | if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE) |
8076 | return ret; | |
8077 | ||
8078 | /* Check MIB Type and return if event for Remote MIB update */ | |
8079 | type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK; | |
9fa61dd2 | 8080 | dev_dbg(&pf->pdev->dev, |
fb43201f | 8081 | "LLDP event mib type %s\n", type ? "remote" : "local"); |
4e3b35b0 NP |
8082 | if (type == I40E_AQ_LLDP_MIB_REMOTE) { |
8083 | /* Update the remote cached instance and return */ | |
8084 | ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE, | |
8085 | I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, | |
8086 | &hw->remote_dcbx_config); | |
8087 | goto exit; | |
8088 | } | |
8089 | ||
9fa61dd2 | 8090 | /* Store the old configuration */ |
1a2f6248 | 8091 | tmp_dcbx_cfg = hw->local_dcbx_config; |
9fa61dd2 | 8092 | |
750fcbcf NP |
8093 | /* Reset the old DCBx configuration data */ |
8094 | memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config)); | |
9fa61dd2 NP |
8095 | /* Get updated DCBX data from firmware */ |
8096 | ret = i40e_get_dcb_config(&pf->hw); | |
4e3b35b0 | 8097 | if (ret) { |
f1c7e72e SN |
8098 | dev_info(&pf->pdev->dev, |
8099 | "Failed querying DCB configuration data from firmware, err %s aq_err %s\n", | |
8100 | i40e_stat_str(&pf->hw, ret), | |
8101 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
8102 | goto exit; |
8103 | } | |
8104 | ||
8105 | /* No change detected in DCBX configs */ | |
750fcbcf NP |
8106 | if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config, |
8107 | sizeof(tmp_dcbx_cfg))) { | |
69bfb110 | 8108 | dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n"); |
4e3b35b0 NP |
8109 | goto exit; |
8110 | } | |
8111 | ||
750fcbcf NP |
8112 | need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg, |
8113 | &hw->local_dcbx_config); | |
4e3b35b0 | 8114 | |
750fcbcf | 8115 | i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config); |
4e3b35b0 NP |
8116 | |
8117 | if (!need_reconfig) | |
8118 | goto exit; | |
8119 | ||
4d9b6043 | 8120 | /* Enable DCB tagging only when more than one TC */ |
750fcbcf | 8121 | if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) |
4d9b6043 NP |
8122 | pf->flags |= I40E_FLAG_DCB_ENABLED; |
8123 | else | |
8124 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
8125 | ||
0da36b97 | 8126 | set_bit(__I40E_PORT_SUSPENDED, pf->state); |
4e3b35b0 NP |
8127 | /* Reconfiguration needed quiesce all VSIs */ |
8128 | i40e_pf_quiesce_all_vsi(pf); | |
8129 | ||
8130 | /* Changes in configuration update VEB/VSI */ | |
8131 | i40e_dcb_reconfigure(pf); | |
8132 | ||
2fd75f31 NP |
8133 | ret = i40e_resume_port_tx(pf); |
8134 | ||
0da36b97 | 8135 | clear_bit(__I40E_PORT_SUSPENDED, pf->state); |
2fd75f31 | 8136 | /* In case of error no point in resuming VSIs */ |
69129dc3 NP |
8137 | if (ret) |
8138 | goto exit; | |
8139 | ||
3fe06f41 NP |
8140 | /* Wait for the PF's queues to be disabled */ |
8141 | ret = i40e_pf_wait_queues_disabled(pf); | |
11e47708 PN |
8142 | if (ret) { |
8143 | /* Schedule PF reset to recover */ | |
0da36b97 | 8144 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
11e47708 PN |
8145 | i40e_service_event_schedule(pf); |
8146 | } else { | |
2fd75f31 | 8147 | i40e_pf_unquiesce_all_vsi(pf); |
d1b3fa86 CIK |
8148 | set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state); |
8149 | set_bit(__I40E_CLIENT_L2_CHANGE, pf->state); | |
11e47708 PN |
8150 | } |
8151 | ||
4e3b35b0 NP |
8152 | exit: |
8153 | return ret; | |
8154 | } | |
8155 | #endif /* CONFIG_I40E_DCB */ | |
8156 | ||
23326186 ASJ |
8157 | /** |
8158 | * i40e_do_reset_safe - Protected reset path for userland calls. | |
8159 | * @pf: board private structure | |
8160 | * @reset_flags: which reset is requested | |
8161 | * | |
8162 | **/ | |
8163 | void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags) | |
8164 | { | |
8165 | rtnl_lock(); | |
373149fc | 8166 | i40e_do_reset(pf, reset_flags, true); |
23326186 ASJ |
8167 | rtnl_unlock(); |
8168 | } | |
8169 | ||
41c445ff JB |
8170 | /** |
8171 | * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event | |
8172 | * @pf: board private structure | |
8173 | * @e: event info posted on ARQ | |
8174 | * | |
8175 | * Handler for LAN Queue Overflow Event generated by the firmware for PF | |
8176 | * and VF queues | |
8177 | **/ | |
8178 | static void i40e_handle_lan_overflow_event(struct i40e_pf *pf, | |
8179 | struct i40e_arq_event_info *e) | |
8180 | { | |
8181 | struct i40e_aqc_lan_overflow *data = | |
8182 | (struct i40e_aqc_lan_overflow *)&e->desc.params.raw; | |
8183 | u32 queue = le32_to_cpu(data->prtdcb_rupto); | |
8184 | u32 qtx_ctl = le32_to_cpu(data->otx_ctl); | |
8185 | struct i40e_hw *hw = &pf->hw; | |
8186 | struct i40e_vf *vf; | |
8187 | u16 vf_id; | |
8188 | ||
69bfb110 JB |
8189 | dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n", |
8190 | queue, qtx_ctl); | |
41c445ff JB |
8191 | |
8192 | /* Queue belongs to VF, find the VF and issue VF reset */ | |
8193 | if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK) | |
8194 | >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) { | |
8195 | vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK) | |
8196 | >> I40E_QTX_CTL_VFVM_INDX_SHIFT); | |
8197 | vf_id -= hw->func_caps.vf_base_id; | |
8198 | vf = &pf->vf[vf_id]; | |
8199 | i40e_vc_notify_vf_reset(vf); | |
8200 | /* Allow VF to process pending reset notification */ | |
8201 | msleep(20); | |
8202 | i40e_reset_vf(vf, false); | |
8203 | } | |
8204 | } | |
8205 | ||
55a5e60b | 8206 | /** |
12957388 ASJ |
8207 | * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters |
8208 | * @pf: board private structure | |
8209 | **/ | |
04294e38 | 8210 | u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf) |
12957388 | 8211 | { |
04294e38 | 8212 | u32 val, fcnt_prog; |
12957388 ASJ |
8213 | |
8214 | val = rd32(&pf->hw, I40E_PFQF_FDSTAT); | |
8215 | fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK); | |
8216 | return fcnt_prog; | |
8217 | } | |
8218 | ||
8219 | /** | |
04294e38 | 8220 | * i40e_get_current_fd_count - Get total FD filters programmed for this PF |
55a5e60b ASJ |
8221 | * @pf: board private structure |
8222 | **/ | |
04294e38 | 8223 | u32 i40e_get_current_fd_count(struct i40e_pf *pf) |
55a5e60b | 8224 | { |
04294e38 ASJ |
8225 | u32 val, fcnt_prog; |
8226 | ||
55a5e60b ASJ |
8227 | val = rd32(&pf->hw, I40E_PFQF_FDSTAT); |
8228 | fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) + | |
8229 | ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >> | |
8230 | I40E_PFQF_FDSTAT_BEST_CNT_SHIFT); | |
8231 | return fcnt_prog; | |
8232 | } | |
1e1be8f6 | 8233 | |
04294e38 ASJ |
8234 | /** |
8235 | * i40e_get_global_fd_count - Get total FD filters programmed on device | |
8236 | * @pf: board private structure | |
8237 | **/ | |
8238 | u32 i40e_get_global_fd_count(struct i40e_pf *pf) | |
8239 | { | |
8240 | u32 val, fcnt_prog; | |
8241 | ||
8242 | val = rd32(&pf->hw, I40E_GLQF_FDCNT_0); | |
8243 | fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) + | |
8244 | ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >> | |
8245 | I40E_GLQF_FDCNT_0_BESTCNT_SHIFT); | |
8246 | return fcnt_prog; | |
8247 | } | |
8248 | ||
01c96952 JK |
8249 | /** |
8250 | * i40e_reenable_fdir_sb - Restore FDir SB capability | |
8251 | * @pf: board private structure | |
8252 | **/ | |
8253 | static void i40e_reenable_fdir_sb(struct i40e_pf *pf) | |
8254 | { | |
134201ae | 8255 | if (test_and_clear_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) |
01c96952 JK |
8256 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
8257 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
8258 | dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n"); | |
01c96952 JK |
8259 | } |
8260 | ||
8261 | /** | |
8262 | * i40e_reenable_fdir_atr - Restore FDir ATR capability | |
8263 | * @pf: board private structure | |
8264 | **/ | |
8265 | static void i40e_reenable_fdir_atr(struct i40e_pf *pf) | |
8266 | { | |
134201ae | 8267 | if (test_and_clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) { |
089915f0 JK |
8268 | /* ATR uses the same filtering logic as SB rules. It only |
8269 | * functions properly if the input set mask is at the default | |
8270 | * settings. It is safe to restore the default input set | |
8271 | * because there are no active TCPv4 filter rules. | |
8272 | */ | |
8273 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_TCP, | |
8274 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
8275 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
8276 | ||
01c96952 JK |
8277 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && |
8278 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
8279 | dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table and there are no conflicting ntuple rules\n"); | |
8280 | } | |
8281 | } | |
8282 | ||
6ac6d5a7 JK |
8283 | /** |
8284 | * i40e_delete_invalid_filter - Delete an invalid FDIR filter | |
8285 | * @pf: board private structure | |
8286 | * @filter: FDir filter to remove | |
8287 | */ | |
8288 | static void i40e_delete_invalid_filter(struct i40e_pf *pf, | |
8289 | struct i40e_fdir_filter *filter) | |
8290 | { | |
8291 | /* Update counters */ | |
8292 | pf->fdir_pf_active_filters--; | |
8293 | pf->fd_inv = 0; | |
8294 | ||
8295 | switch (filter->flow_type) { | |
8296 | case TCP_V4_FLOW: | |
8297 | pf->fd_tcp4_filter_cnt--; | |
8298 | break; | |
8299 | case UDP_V4_FLOW: | |
8300 | pf->fd_udp4_filter_cnt--; | |
8301 | break; | |
8302 | case SCTP_V4_FLOW: | |
8303 | pf->fd_sctp4_filter_cnt--; | |
8304 | break; | |
8305 | case IP_USER_FLOW: | |
8306 | switch (filter->ip4_proto) { | |
8307 | case IPPROTO_TCP: | |
8308 | pf->fd_tcp4_filter_cnt--; | |
8309 | break; | |
8310 | case IPPROTO_UDP: | |
8311 | pf->fd_udp4_filter_cnt--; | |
8312 | break; | |
8313 | case IPPROTO_SCTP: | |
8314 | pf->fd_sctp4_filter_cnt--; | |
8315 | break; | |
8316 | case IPPROTO_IP: | |
8317 | pf->fd_ip4_filter_cnt--; | |
8318 | break; | |
8319 | } | |
8320 | break; | |
8321 | } | |
8322 | ||
8323 | /* Remove the filter from the list and free memory */ | |
8324 | hlist_del(&filter->fdir_node); | |
8325 | kfree(filter); | |
8326 | } | |
8327 | ||
55a5e60b ASJ |
8328 | /** |
8329 | * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled | |
8330 | * @pf: board private structure | |
8331 | **/ | |
8332 | void i40e_fdir_check_and_reenable(struct i40e_pf *pf) | |
8333 | { | |
3487b6c3 | 8334 | struct i40e_fdir_filter *filter; |
55a5e60b | 8335 | u32 fcnt_prog, fcnt_avail; |
3487b6c3 | 8336 | struct hlist_node *node; |
55a5e60b | 8337 | |
0da36b97 | 8338 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) |
1e1be8f6 ASJ |
8339 | return; |
8340 | ||
47994c11 | 8341 | /* Check if we have enough room to re-enable FDir SB capability. */ |
04294e38 | 8342 | fcnt_prog = i40e_get_global_fd_count(pf); |
12957388 | 8343 | fcnt_avail = pf->fdir_pf_filter_count; |
1e1be8f6 ASJ |
8344 | if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) || |
8345 | (pf->fd_add_err == 0) || | |
01c96952 JK |
8346 | (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) |
8347 | i40e_reenable_fdir_sb(pf); | |
a3417d28 | 8348 | |
47994c11 JK |
8349 | /* We should wait for even more space before re-enabling ATR. |
8350 | * Additionally, we cannot enable ATR as long as we still have TCP SB | |
8351 | * rules active. | |
a3417d28 | 8352 | */ |
47994c11 | 8353 | if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) && |
01c96952 JK |
8354 | (pf->fd_tcp4_filter_cnt == 0)) |
8355 | i40e_reenable_fdir_atr(pf); | |
3487b6c3 CW |
8356 | |
8357 | /* if hw had a problem adding a filter, delete it */ | |
8358 | if (pf->fd_inv > 0) { | |
8359 | hlist_for_each_entry_safe(filter, node, | |
6ac6d5a7 JK |
8360 | &pf->fdir_filter_list, fdir_node) |
8361 | if (filter->fd_id == pf->fd_inv) | |
8362 | i40e_delete_invalid_filter(pf, filter); | |
3487b6c3 | 8363 | } |
55a5e60b ASJ |
8364 | } |
8365 | ||
1e1be8f6 | 8366 | #define I40E_MIN_FD_FLUSH_INTERVAL 10 |
04294e38 | 8367 | #define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30 |
1e1be8f6 ASJ |
8368 | /** |
8369 | * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB | |
8370 | * @pf: board private structure | |
8371 | **/ | |
8372 | static void i40e_fdir_flush_and_replay(struct i40e_pf *pf) | |
8373 | { | |
04294e38 | 8374 | unsigned long min_flush_time; |
1e1be8f6 | 8375 | int flush_wait_retry = 50; |
04294e38 ASJ |
8376 | bool disable_atr = false; |
8377 | int fd_room; | |
1e1be8f6 ASJ |
8378 | int reg; |
8379 | ||
a5fdaf34 JB |
8380 | if (!time_after(jiffies, pf->fd_flush_timestamp + |
8381 | (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) | |
8382 | return; | |
04294e38 | 8383 | |
a5fdaf34 JB |
8384 | /* If the flush is happening too quick and we have mostly SB rules we |
8385 | * should not re-enable ATR for some time. | |
8386 | */ | |
8387 | min_flush_time = pf->fd_flush_timestamp + | |
8388 | (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ); | |
8389 | fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters; | |
8390 | ||
8391 | if (!(time_after(jiffies, min_flush_time)) && | |
8392 | (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) { | |
8393 | if (I40E_DEBUG_FD & pf->hw.debug_mask) | |
8394 | dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n"); | |
8395 | disable_atr = true; | |
8396 | } | |
8397 | ||
8398 | pf->fd_flush_timestamp = jiffies; | |
134201ae | 8399 | set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state); |
a5fdaf34 JB |
8400 | /* flush all filters */ |
8401 | wr32(&pf->hw, I40E_PFQF_CTL_1, | |
8402 | I40E_PFQF_CTL_1_CLEARFDTABLE_MASK); | |
8403 | i40e_flush(&pf->hw); | |
8404 | pf->fd_flush_cnt++; | |
8405 | pf->fd_add_err = 0; | |
8406 | do { | |
8407 | /* Check FD flush status every 5-6msec */ | |
8408 | usleep_range(5000, 6000); | |
8409 | reg = rd32(&pf->hw, I40E_PFQF_CTL_1); | |
8410 | if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK)) | |
8411 | break; | |
8412 | } while (flush_wait_retry--); | |
8413 | if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) { | |
8414 | dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n"); | |
8415 | } else { | |
8416 | /* replay sideband filters */ | |
8417 | i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]); | |
097dbf52 | 8418 | if (!disable_atr && !pf->fd_tcp4_filter_cnt) |
134201ae | 8419 | clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state); |
0da36b97 | 8420 | clear_bit(__I40E_FD_FLUSH_REQUESTED, pf->state); |
a5fdaf34 JB |
8421 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
8422 | dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n"); | |
1e1be8f6 ASJ |
8423 | } |
8424 | } | |
8425 | ||
8426 | /** | |
8427 | * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed | |
8428 | * @pf: board private structure | |
8429 | **/ | |
04294e38 | 8430 | u32 i40e_get_current_atr_cnt(struct i40e_pf *pf) |
1e1be8f6 ASJ |
8431 | { |
8432 | return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters; | |
8433 | } | |
8434 | ||
8435 | /* We can see up to 256 filter programming desc in transit if the filters are | |
8436 | * being applied really fast; before we see the first | |
8437 | * filter miss error on Rx queue 0. Accumulating enough error messages before | |
8438 | * reacting will make sure we don't cause flush too often. | |
8439 | */ | |
8440 | #define I40E_MAX_FD_PROGRAM_ERROR 256 | |
8441 | ||
41c445ff JB |
8442 | /** |
8443 | * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table | |
8444 | * @pf: board private structure | |
8445 | **/ | |
8446 | static void i40e_fdir_reinit_subtask(struct i40e_pf *pf) | |
8447 | { | |
41c445ff | 8448 | |
41c445ff | 8449 | /* if interface is down do nothing */ |
9e6c9c0f | 8450 | if (test_bit(__I40E_DOWN, pf->state)) |
41c445ff | 8451 | return; |
1e1be8f6 | 8452 | |
0da36b97 | 8453 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) |
1e1be8f6 ASJ |
8454 | i40e_fdir_flush_and_replay(pf); |
8455 | ||
55a5e60b ASJ |
8456 | i40e_fdir_check_and_reenable(pf); |
8457 | ||
41c445ff JB |
8458 | } |
8459 | ||
8460 | /** | |
8461 | * i40e_vsi_link_event - notify VSI of a link event | |
8462 | * @vsi: vsi to be notified | |
8463 | * @link_up: link up or down | |
8464 | **/ | |
8465 | static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up) | |
8466 | { | |
0da36b97 | 8467 | if (!vsi || test_bit(__I40E_VSI_DOWN, vsi->state)) |
41c445ff JB |
8468 | return; |
8469 | ||
8470 | switch (vsi->type) { | |
8471 | case I40E_VSI_MAIN: | |
8472 | if (!vsi->netdev || !vsi->netdev_registered) | |
8473 | break; | |
8474 | ||
8475 | if (link_up) { | |
8476 | netif_carrier_on(vsi->netdev); | |
8477 | netif_tx_wake_all_queues(vsi->netdev); | |
8478 | } else { | |
8479 | netif_carrier_off(vsi->netdev); | |
8480 | netif_tx_stop_all_queues(vsi->netdev); | |
8481 | } | |
8482 | break; | |
8483 | ||
8484 | case I40E_VSI_SRIOV: | |
41c445ff JB |
8485 | case I40E_VSI_VMDQ2: |
8486 | case I40E_VSI_CTRL: | |
e3219ce6 | 8487 | case I40E_VSI_IWARP: |
41c445ff JB |
8488 | case I40E_VSI_MIRROR: |
8489 | default: | |
8490 | /* there is no notification for other VSIs */ | |
8491 | break; | |
8492 | } | |
8493 | } | |
8494 | ||
8495 | /** | |
8496 | * i40e_veb_link_event - notify elements on the veb of a link event | |
8497 | * @veb: veb to be notified | |
8498 | * @link_up: link up or down | |
8499 | **/ | |
8500 | static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up) | |
8501 | { | |
8502 | struct i40e_pf *pf; | |
8503 | int i; | |
8504 | ||
8505 | if (!veb || !veb->pf) | |
8506 | return; | |
8507 | pf = veb->pf; | |
8508 | ||
8509 | /* depth first... */ | |
8510 | for (i = 0; i < I40E_MAX_VEB; i++) | |
8511 | if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid)) | |
8512 | i40e_veb_link_event(pf->veb[i], link_up); | |
8513 | ||
8514 | /* ... now the local VSIs */ | |
505682cd | 8515 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
8516 | if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid)) |
8517 | i40e_vsi_link_event(pf->vsi[i], link_up); | |
8518 | } | |
8519 | ||
8520 | /** | |
8521 | * i40e_link_event - Update netif_carrier status | |
8522 | * @pf: board private structure | |
8523 | **/ | |
8524 | static void i40e_link_event(struct i40e_pf *pf) | |
8525 | { | |
320684cd | 8526 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
fef59ddf | 8527 | u8 new_link_speed, old_link_speed; |
a72a5abc JB |
8528 | i40e_status status; |
8529 | bool new_link, old_link; | |
41c445ff | 8530 | |
1e701e09 JB |
8531 | /* set this to force the get_link_status call to refresh state */ |
8532 | pf->hw.phy.get_link_info = true; | |
41c445ff | 8533 | old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP); |
a72a5abc | 8534 | status = i40e_get_link_status(&pf->hw, &new_link); |
ae136708 HR |
8535 | |
8536 | /* On success, disable temp link polling */ | |
8537 | if (status == I40E_SUCCESS) { | |
0605c45c | 8538 | clear_bit(__I40E_TEMP_LINK_POLLING, pf->state); |
ae136708 HR |
8539 | } else { |
8540 | /* Enable link polling temporarily until i40e_get_link_status | |
8541 | * returns I40E_SUCCESS | |
8542 | */ | |
0605c45c | 8543 | set_bit(__I40E_TEMP_LINK_POLLING, pf->state); |
a72a5abc JB |
8544 | dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n", |
8545 | status); | |
8546 | return; | |
8547 | } | |
8548 | ||
fef59ddf CS |
8549 | old_link_speed = pf->hw.phy.link_info_old.link_speed; |
8550 | new_link_speed = pf->hw.phy.link_info.link_speed; | |
41c445ff | 8551 | |
1e701e09 | 8552 | if (new_link == old_link && |
fef59ddf | 8553 | new_link_speed == old_link_speed && |
0da36b97 | 8554 | (test_bit(__I40E_VSI_DOWN, vsi->state) || |
320684cd | 8555 | new_link == netif_carrier_ok(vsi->netdev))) |
41c445ff | 8556 | return; |
320684cd | 8557 | |
9a03449d | 8558 | i40e_print_link_message(vsi, new_link); |
41c445ff JB |
8559 | |
8560 | /* Notify the base of the switch tree connected to | |
8561 | * the link. Floating VEBs are not notified. | |
8562 | */ | |
8563 | if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb]) | |
8564 | i40e_veb_link_event(pf->veb[pf->lan_veb], new_link); | |
8565 | else | |
320684cd | 8566 | i40e_vsi_link_event(vsi, new_link); |
41c445ff JB |
8567 | |
8568 | if (pf->vf) | |
8569 | i40e_vc_notify_link_state(pf); | |
beb0dff1 JK |
8570 | |
8571 | if (pf->flags & I40E_FLAG_PTP) | |
8572 | i40e_ptp_set_increment(pf); | |
41c445ff JB |
8573 | } |
8574 | ||
41c445ff | 8575 | /** |
21536717 | 8576 | * i40e_watchdog_subtask - periodic checks not using event driven response |
41c445ff JB |
8577 | * @pf: board private structure |
8578 | **/ | |
8579 | static void i40e_watchdog_subtask(struct i40e_pf *pf) | |
8580 | { | |
8581 | int i; | |
8582 | ||
8583 | /* if interface is down do nothing */ | |
9e6c9c0f | 8584 | if (test_bit(__I40E_DOWN, pf->state) || |
0da36b97 | 8585 | test_bit(__I40E_CONFIG_BUSY, pf->state)) |
41c445ff JB |
8586 | return; |
8587 | ||
21536717 SN |
8588 | /* make sure we don't do these things too often */ |
8589 | if (time_before(jiffies, (pf->service_timer_previous + | |
8590 | pf->service_timer_period))) | |
8591 | return; | |
8592 | pf->service_timer_previous = jiffies; | |
8593 | ||
ae136708 | 8594 | if ((pf->flags & I40E_FLAG_LINK_POLLING_ENABLED) || |
0605c45c | 8595 | test_bit(__I40E_TEMP_LINK_POLLING, pf->state)) |
9ac77266 | 8596 | i40e_link_event(pf); |
21536717 | 8597 | |
41c445ff JB |
8598 | /* Update the stats for active netdevs so the network stack |
8599 | * can look at updated numbers whenever it cares to | |
8600 | */ | |
505682cd | 8601 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
8602 | if (pf->vsi[i] && pf->vsi[i]->netdev) |
8603 | i40e_update_stats(pf->vsi[i]); | |
8604 | ||
d1a8d275 ASJ |
8605 | if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) { |
8606 | /* Update the stats for the active switching components */ | |
8607 | for (i = 0; i < I40E_MAX_VEB; i++) | |
8608 | if (pf->veb[i]) | |
8609 | i40e_update_veb_stats(pf->veb[i]); | |
8610 | } | |
beb0dff1 | 8611 | |
61189556 | 8612 | i40e_ptp_rx_hang(pf); |
0bc0706b | 8613 | i40e_ptp_tx_hang(pf); |
41c445ff JB |
8614 | } |
8615 | ||
8616 | /** | |
8617 | * i40e_reset_subtask - Set up for resetting the device and driver | |
8618 | * @pf: board private structure | |
8619 | **/ | |
8620 | static void i40e_reset_subtask(struct i40e_pf *pf) | |
8621 | { | |
8622 | u32 reset_flags = 0; | |
8623 | ||
0da36b97 | 8624 | if (test_bit(__I40E_REINIT_REQUESTED, pf->state)) { |
75f5cea9 | 8625 | reset_flags |= BIT(__I40E_REINIT_REQUESTED); |
0da36b97 | 8626 | clear_bit(__I40E_REINIT_REQUESTED, pf->state); |
41c445ff | 8627 | } |
0da36b97 | 8628 | if (test_bit(__I40E_PF_RESET_REQUESTED, pf->state)) { |
75f5cea9 | 8629 | reset_flags |= BIT(__I40E_PF_RESET_REQUESTED); |
0da36b97 | 8630 | clear_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
41c445ff | 8631 | } |
0da36b97 | 8632 | if (test_bit(__I40E_CORE_RESET_REQUESTED, pf->state)) { |
75f5cea9 | 8633 | reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED); |
0da36b97 | 8634 | clear_bit(__I40E_CORE_RESET_REQUESTED, pf->state); |
41c445ff | 8635 | } |
0da36b97 | 8636 | if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state)) { |
75f5cea9 | 8637 | reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED); |
0da36b97 | 8638 | clear_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state); |
41c445ff | 8639 | } |
9e6c9c0f MR |
8640 | if (test_bit(__I40E_DOWN_REQUESTED, pf->state)) { |
8641 | reset_flags |= BIT(__I40E_DOWN_REQUESTED); | |
8642 | clear_bit(__I40E_DOWN_REQUESTED, pf->state); | |
b5d06f05 | 8643 | } |
41c445ff JB |
8644 | |
8645 | /* If there's a recovery already waiting, it takes | |
8646 | * precedence before starting a new reset sequence. | |
8647 | */ | |
0da36b97 | 8648 | if (test_bit(__I40E_RESET_INTR_RECEIVED, pf->state)) { |
373149fc MS |
8649 | i40e_prep_for_reset(pf, false); |
8650 | i40e_reset(pf); | |
8651 | i40e_rebuild(pf, false, false); | |
41c445ff JB |
8652 | } |
8653 | ||
8654 | /* If we're already down or resetting, just bail */ | |
8655 | if (reset_flags && | |
9e6c9c0f | 8656 | !test_bit(__I40E_DOWN, pf->state) && |
0da36b97 | 8657 | !test_bit(__I40E_CONFIG_BUSY, pf->state)) { |
dfc4ff64 | 8658 | i40e_do_reset(pf, reset_flags, false); |
373149fc | 8659 | } |
41c445ff JB |
8660 | } |
8661 | ||
8662 | /** | |
8663 | * i40e_handle_link_event - Handle link event | |
8664 | * @pf: board private structure | |
8665 | * @e: event info posted on ARQ | |
8666 | **/ | |
8667 | static void i40e_handle_link_event(struct i40e_pf *pf, | |
8668 | struct i40e_arq_event_info *e) | |
8669 | { | |
41c445ff JB |
8670 | struct i40e_aqc_get_link_status *status = |
8671 | (struct i40e_aqc_get_link_status *)&e->desc.params.raw; | |
41c445ff | 8672 | |
1e701e09 JB |
8673 | /* Do a new status request to re-enable LSE reporting |
8674 | * and load new status information into the hw struct | |
8675 | * This completely ignores any state information | |
8676 | * in the ARQ event info, instead choosing to always | |
8677 | * issue the AQ update link status command. | |
8678 | */ | |
8679 | i40e_link_event(pf); | |
8680 | ||
9a858178 FS |
8681 | /* Check if module meets thermal requirements */ |
8682 | if (status->phy_type == I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP) { | |
7b592f61 | 8683 | dev_err(&pf->pdev->dev, |
9a858178 FS |
8684 | "Rx/Tx is disabled on this device because the module does not meet thermal requirements.\n"); |
8685 | dev_err(&pf->pdev->dev, | |
8686 | "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for a list of supported modules.\n"); | |
8687 | } else { | |
8688 | /* check for unqualified module, if link is down, suppress | |
8689 | * the message if link was forced to be down. | |
8690 | */ | |
8691 | if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) && | |
8692 | (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) && | |
8693 | (!(status->link_info & I40E_AQ_LINK_UP)) && | |
8694 | (!(pf->flags & I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED))) { | |
8695 | dev_err(&pf->pdev->dev, | |
8696 | "Rx/Tx is disabled on this device because an unsupported SFP module type was detected.\n"); | |
8697 | dev_err(&pf->pdev->dev, | |
8698 | "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for a list of supported modules.\n"); | |
8699 | } | |
8700 | } | |
41c445ff JB |
8701 | } |
8702 | ||
8703 | /** | |
8704 | * i40e_clean_adminq_subtask - Clean the AdminQ rings | |
8705 | * @pf: board private structure | |
8706 | **/ | |
8707 | static void i40e_clean_adminq_subtask(struct i40e_pf *pf) | |
8708 | { | |
8709 | struct i40e_arq_event_info event; | |
8710 | struct i40e_hw *hw = &pf->hw; | |
8711 | u16 pending, i = 0; | |
8712 | i40e_status ret; | |
8713 | u16 opcode; | |
86df242b | 8714 | u32 oldval; |
41c445ff JB |
8715 | u32 val; |
8716 | ||
a316f651 | 8717 | /* Do not run clean AQ when PF reset fails */ |
0da36b97 | 8718 | if (test_bit(__I40E_RESET_FAILED, pf->state)) |
a316f651 ASJ |
8719 | return; |
8720 | ||
86df242b SN |
8721 | /* check for error indications */ |
8722 | val = rd32(&pf->hw, pf->hw.aq.arq.len); | |
8723 | oldval = val; | |
8724 | if (val & I40E_PF_ARQLEN_ARQVFE_MASK) { | |
75eb73c1 MW |
8725 | if (hw->debug_mask & I40E_DEBUG_AQ) |
8726 | dev_info(&pf->pdev->dev, "ARQ VF Error detected\n"); | |
86df242b SN |
8727 | val &= ~I40E_PF_ARQLEN_ARQVFE_MASK; |
8728 | } | |
8729 | if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) { | |
75eb73c1 MW |
8730 | if (hw->debug_mask & I40E_DEBUG_AQ) |
8731 | dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n"); | |
86df242b | 8732 | val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK; |
1d0a4ada | 8733 | pf->arq_overflows++; |
86df242b SN |
8734 | } |
8735 | if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) { | |
75eb73c1 MW |
8736 | if (hw->debug_mask & I40E_DEBUG_AQ) |
8737 | dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n"); | |
86df242b SN |
8738 | val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK; |
8739 | } | |
8740 | if (oldval != val) | |
8741 | wr32(&pf->hw, pf->hw.aq.arq.len, val); | |
8742 | ||
8743 | val = rd32(&pf->hw, pf->hw.aq.asq.len); | |
8744 | oldval = val; | |
8745 | if (val & I40E_PF_ATQLEN_ATQVFE_MASK) { | |
75eb73c1 MW |
8746 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
8747 | dev_info(&pf->pdev->dev, "ASQ VF Error detected\n"); | |
86df242b SN |
8748 | val &= ~I40E_PF_ATQLEN_ATQVFE_MASK; |
8749 | } | |
8750 | if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) { | |
75eb73c1 MW |
8751 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
8752 | dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n"); | |
86df242b SN |
8753 | val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK; |
8754 | } | |
8755 | if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) { | |
75eb73c1 MW |
8756 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
8757 | dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n"); | |
86df242b SN |
8758 | val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK; |
8759 | } | |
8760 | if (oldval != val) | |
8761 | wr32(&pf->hw, pf->hw.aq.asq.len, val); | |
8762 | ||
1001dc37 MW |
8763 | event.buf_len = I40E_MAX_AQ_BUF_SIZE; |
8764 | event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL); | |
41c445ff JB |
8765 | if (!event.msg_buf) |
8766 | return; | |
8767 | ||
8768 | do { | |
8769 | ret = i40e_clean_arq_element(hw, &event, &pending); | |
56497978 | 8770 | if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) |
41c445ff | 8771 | break; |
56497978 | 8772 | else if (ret) { |
41c445ff JB |
8773 | dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret); |
8774 | break; | |
8775 | } | |
8776 | ||
8777 | opcode = le16_to_cpu(event.desc.opcode); | |
8778 | switch (opcode) { | |
8779 | ||
8780 | case i40e_aqc_opc_get_link_status: | |
8781 | i40e_handle_link_event(pf, &event); | |
8782 | break; | |
8783 | case i40e_aqc_opc_send_msg_to_pf: | |
8784 | ret = i40e_vc_process_vf_msg(pf, | |
8785 | le16_to_cpu(event.desc.retval), | |
8786 | le32_to_cpu(event.desc.cookie_high), | |
8787 | le32_to_cpu(event.desc.cookie_low), | |
8788 | event.msg_buf, | |
1001dc37 | 8789 | event.msg_len); |
41c445ff JB |
8790 | break; |
8791 | case i40e_aqc_opc_lldp_update_mib: | |
69bfb110 | 8792 | dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n"); |
4e3b35b0 NP |
8793 | #ifdef CONFIG_I40E_DCB |
8794 | rtnl_lock(); | |
8795 | ret = i40e_handle_lldp_event(pf, &event); | |
8796 | rtnl_unlock(); | |
8797 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
8798 | break; |
8799 | case i40e_aqc_opc_event_lan_overflow: | |
69bfb110 | 8800 | dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n"); |
41c445ff JB |
8801 | i40e_handle_lan_overflow_event(pf, &event); |
8802 | break; | |
0467bc91 SN |
8803 | case i40e_aqc_opc_send_msg_to_peer: |
8804 | dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n"); | |
8805 | break; | |
91a0f930 SN |
8806 | case i40e_aqc_opc_nvm_erase: |
8807 | case i40e_aqc_opc_nvm_update: | |
00ada50d | 8808 | case i40e_aqc_opc_oem_post_update: |
6e93d0c9 SN |
8809 | i40e_debug(&pf->hw, I40E_DEBUG_NVM, |
8810 | "ARQ NVM operation 0x%04x completed\n", | |
8811 | opcode); | |
91a0f930 | 8812 | break; |
41c445ff JB |
8813 | default: |
8814 | dev_info(&pf->pdev->dev, | |
56e5ca68 | 8815 | "ARQ: Unknown event 0x%04x ignored\n", |
0467bc91 | 8816 | opcode); |
41c445ff JB |
8817 | break; |
8818 | } | |
1fca3265 CB |
8819 | } while (i++ < pf->adminq_work_limit); |
8820 | ||
8821 | if (i < pf->adminq_work_limit) | |
0da36b97 | 8822 | clear_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state); |
41c445ff | 8823 | |
41c445ff JB |
8824 | /* re-enable Admin queue interrupt cause */ |
8825 | val = rd32(hw, I40E_PFINT_ICR0_ENA); | |
8826 | val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
8827 | wr32(hw, I40E_PFINT_ICR0_ENA, val); | |
8828 | i40e_flush(hw); | |
8829 | ||
8830 | kfree(event.msg_buf); | |
8831 | } | |
8832 | ||
4eb3f768 SN |
8833 | /** |
8834 | * i40e_verify_eeprom - make sure eeprom is good to use | |
8835 | * @pf: board private structure | |
8836 | **/ | |
8837 | static void i40e_verify_eeprom(struct i40e_pf *pf) | |
8838 | { | |
8839 | int err; | |
8840 | ||
8841 | err = i40e_diag_eeprom_test(&pf->hw); | |
8842 | if (err) { | |
8843 | /* retry in case of garbage read */ | |
8844 | err = i40e_diag_eeprom_test(&pf->hw); | |
8845 | if (err) { | |
8846 | dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n", | |
8847 | err); | |
0da36b97 | 8848 | set_bit(__I40E_BAD_EEPROM, pf->state); |
4eb3f768 SN |
8849 | } |
8850 | } | |
8851 | ||
0da36b97 | 8852 | if (!err && test_bit(__I40E_BAD_EEPROM, pf->state)) { |
4eb3f768 | 8853 | dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n"); |
0da36b97 | 8854 | clear_bit(__I40E_BAD_EEPROM, pf->state); |
4eb3f768 SN |
8855 | } |
8856 | } | |
8857 | ||
386a0afa AA |
8858 | /** |
8859 | * i40e_enable_pf_switch_lb | |
b40c82e6 | 8860 | * @pf: pointer to the PF structure |
386a0afa AA |
8861 | * |
8862 | * enable switch loop back or die - no point in a return value | |
8863 | **/ | |
8864 | static void i40e_enable_pf_switch_lb(struct i40e_pf *pf) | |
8865 | { | |
8866 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
8867 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 8868 | int ret; |
386a0afa AA |
8869 | |
8870 | ctxt.seid = pf->main_vsi_seid; | |
8871 | ctxt.pf_num = pf->hw.pf_id; | |
8872 | ctxt.vf_num = 0; | |
f1c7e72e SN |
8873 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); |
8874 | if (ret) { | |
386a0afa | 8875 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
8876 | "couldn't get PF vsi config, err %s aq_err %s\n", |
8877 | i40e_stat_str(&pf->hw, ret), | |
8878 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
8879 | return; |
8880 | } | |
8881 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
8882 | ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
8883 | ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
8884 | ||
f1c7e72e SN |
8885 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
8886 | if (ret) { | |
386a0afa | 8887 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
8888 | "update vsi switch failed, err %s aq_err %s\n", |
8889 | i40e_stat_str(&pf->hw, ret), | |
8890 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
8891 | } |
8892 | } | |
8893 | ||
8894 | /** | |
8895 | * i40e_disable_pf_switch_lb | |
b40c82e6 | 8896 | * @pf: pointer to the PF structure |
386a0afa AA |
8897 | * |
8898 | * disable switch loop back or die - no point in a return value | |
8899 | **/ | |
8900 | static void i40e_disable_pf_switch_lb(struct i40e_pf *pf) | |
8901 | { | |
8902 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
8903 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 8904 | int ret; |
386a0afa AA |
8905 | |
8906 | ctxt.seid = pf->main_vsi_seid; | |
8907 | ctxt.pf_num = pf->hw.pf_id; | |
8908 | ctxt.vf_num = 0; | |
f1c7e72e SN |
8909 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); |
8910 | if (ret) { | |
386a0afa | 8911 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
8912 | "couldn't get PF vsi config, err %s aq_err %s\n", |
8913 | i40e_stat_str(&pf->hw, ret), | |
8914 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
8915 | return; |
8916 | } | |
8917 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
8918 | ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
8919 | ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
8920 | ||
f1c7e72e SN |
8921 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
8922 | if (ret) { | |
386a0afa | 8923 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
8924 | "update vsi switch failed, err %s aq_err %s\n", |
8925 | i40e_stat_str(&pf->hw, ret), | |
8926 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
8927 | } |
8928 | } | |
8929 | ||
51616018 NP |
8930 | /** |
8931 | * i40e_config_bridge_mode - Configure the HW bridge mode | |
8932 | * @veb: pointer to the bridge instance | |
8933 | * | |
8934 | * Configure the loop back mode for the LAN VSI that is downlink to the | |
8935 | * specified HW bridge instance. It is expected this function is called | |
8936 | * when a new HW bridge is instantiated. | |
8937 | **/ | |
8938 | static void i40e_config_bridge_mode(struct i40e_veb *veb) | |
8939 | { | |
8940 | struct i40e_pf *pf = veb->pf; | |
8941 | ||
6dec1017 SN |
8942 | if (pf->hw.debug_mask & I40E_DEBUG_LAN) |
8943 | dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n", | |
8944 | veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); | |
51616018 NP |
8945 | if (veb->bridge_mode & BRIDGE_MODE_VEPA) |
8946 | i40e_disable_pf_switch_lb(pf); | |
8947 | else | |
8948 | i40e_enable_pf_switch_lb(pf); | |
8949 | } | |
8950 | ||
41c445ff JB |
8951 | /** |
8952 | * i40e_reconstitute_veb - rebuild the VEB and anything connected to it | |
8953 | * @veb: pointer to the VEB instance | |
8954 | * | |
8955 | * This is a recursive function that first builds the attached VSIs then | |
8956 | * recurses in to build the next layer of VEB. We track the connections | |
8957 | * through our own index numbers because the seid's from the HW could | |
8958 | * change across the reset. | |
8959 | **/ | |
8960 | static int i40e_reconstitute_veb(struct i40e_veb *veb) | |
8961 | { | |
8962 | struct i40e_vsi *ctl_vsi = NULL; | |
8963 | struct i40e_pf *pf = veb->pf; | |
8964 | int v, veb_idx; | |
8965 | int ret; | |
8966 | ||
8967 | /* build VSI that owns this VEB, temporarily attached to base VEB */ | |
505682cd | 8968 | for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) { |
41c445ff JB |
8969 | if (pf->vsi[v] && |
8970 | pf->vsi[v]->veb_idx == veb->idx && | |
8971 | pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) { | |
8972 | ctl_vsi = pf->vsi[v]; | |
8973 | break; | |
8974 | } | |
8975 | } | |
8976 | if (!ctl_vsi) { | |
8977 | dev_info(&pf->pdev->dev, | |
8978 | "missing owner VSI for veb_idx %d\n", veb->idx); | |
8979 | ret = -ENOENT; | |
8980 | goto end_reconstitute; | |
8981 | } | |
8982 | if (ctl_vsi != pf->vsi[pf->lan_vsi]) | |
8983 | ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
8984 | ret = i40e_add_vsi(ctl_vsi); | |
8985 | if (ret) { | |
8986 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
8987 | "rebuild of veb_idx %d owner VSI failed: %d\n", |
8988 | veb->idx, ret); | |
41c445ff JB |
8989 | goto end_reconstitute; |
8990 | } | |
8991 | i40e_vsi_reset_stats(ctl_vsi); | |
8992 | ||
8993 | /* create the VEB in the switch and move the VSI onto the VEB */ | |
8994 | ret = i40e_add_veb(veb, ctl_vsi); | |
8995 | if (ret) | |
8996 | goto end_reconstitute; | |
8997 | ||
fc60861e ASJ |
8998 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) |
8999 | veb->bridge_mode = BRIDGE_MODE_VEB; | |
9000 | else | |
9001 | veb->bridge_mode = BRIDGE_MODE_VEPA; | |
51616018 | 9002 | i40e_config_bridge_mode(veb); |
b64ba084 | 9003 | |
41c445ff | 9004 | /* create the remaining VSIs attached to this VEB */ |
505682cd | 9005 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
9006 | if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi) |
9007 | continue; | |
9008 | ||
9009 | if (pf->vsi[v]->veb_idx == veb->idx) { | |
9010 | struct i40e_vsi *vsi = pf->vsi[v]; | |
6995b36c | 9011 | |
41c445ff JB |
9012 | vsi->uplink_seid = veb->seid; |
9013 | ret = i40e_add_vsi(vsi); | |
9014 | if (ret) { | |
9015 | dev_info(&pf->pdev->dev, | |
9016 | "rebuild of vsi_idx %d failed: %d\n", | |
9017 | v, ret); | |
9018 | goto end_reconstitute; | |
9019 | } | |
9020 | i40e_vsi_reset_stats(vsi); | |
9021 | } | |
9022 | } | |
9023 | ||
9024 | /* create any VEBs attached to this VEB - RECURSION */ | |
9025 | for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { | |
9026 | if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) { | |
9027 | pf->veb[veb_idx]->uplink_seid = veb->seid; | |
9028 | ret = i40e_reconstitute_veb(pf->veb[veb_idx]); | |
9029 | if (ret) | |
9030 | break; | |
9031 | } | |
9032 | } | |
9033 | ||
9034 | end_reconstitute: | |
9035 | return ret; | |
9036 | } | |
9037 | ||
9038 | /** | |
9039 | * i40e_get_capabilities - get info about the HW | |
9040 | * @pf: the PF struct | |
9041 | **/ | |
2f4b411a AN |
9042 | static int i40e_get_capabilities(struct i40e_pf *pf, |
9043 | enum i40e_admin_queue_opc list_type) | |
41c445ff JB |
9044 | { |
9045 | struct i40e_aqc_list_capabilities_element_resp *cap_buf; | |
9046 | u16 data_size; | |
9047 | int buf_len; | |
9048 | int err; | |
9049 | ||
9050 | buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); | |
9051 | do { | |
9052 | cap_buf = kzalloc(buf_len, GFP_KERNEL); | |
9053 | if (!cap_buf) | |
9054 | return -ENOMEM; | |
9055 | ||
9056 | /* this loads the data into the hw struct for us */ | |
9057 | err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len, | |
2f4b411a AN |
9058 | &data_size, list_type, |
9059 | NULL); | |
41c445ff JB |
9060 | /* data loaded, buffer no longer needed */ |
9061 | kfree(cap_buf); | |
9062 | ||
9063 | if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) { | |
9064 | /* retry with a larger buffer */ | |
9065 | buf_len = data_size; | |
9066 | } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) { | |
9067 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9068 | "capability discovery failed, err %s aq_err %s\n", |
9069 | i40e_stat_str(&pf->hw, err), | |
9070 | i40e_aq_str(&pf->hw, | |
9071 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9072 | return -ENODEV; |
9073 | } | |
9074 | } while (err); | |
9075 | ||
2f4b411a AN |
9076 | if (pf->hw.debug_mask & I40E_DEBUG_USER) { |
9077 | if (list_type == i40e_aqc_opc_list_func_capabilities) { | |
9078 | dev_info(&pf->pdev->dev, | |
9079 | "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n", | |
9080 | pf->hw.pf_id, pf->hw.func_caps.num_vfs, | |
9081 | pf->hw.func_caps.num_msix_vectors, | |
9082 | pf->hw.func_caps.num_msix_vectors_vf, | |
9083 | pf->hw.func_caps.fd_filters_guaranteed, | |
9084 | pf->hw.func_caps.fd_filters_best_effort, | |
9085 | pf->hw.func_caps.num_tx_qp, | |
9086 | pf->hw.func_caps.num_vsis); | |
9087 | } else if (list_type == i40e_aqc_opc_list_dev_capabilities) { | |
9088 | dev_info(&pf->pdev->dev, | |
9089 | "switch_mode=0x%04x, function_valid=0x%08x\n", | |
9090 | pf->hw.dev_caps.switch_mode, | |
9091 | pf->hw.dev_caps.valid_functions); | |
9092 | dev_info(&pf->pdev->dev, | |
9093 | "SR-IOV=%d, num_vfs for all function=%u\n", | |
9094 | pf->hw.dev_caps.sr_iov_1_1, | |
9095 | pf->hw.dev_caps.num_vfs); | |
9096 | dev_info(&pf->pdev->dev, | |
9097 | "num_vsis=%u, num_rx:%u, num_tx=%u\n", | |
9098 | pf->hw.dev_caps.num_vsis, | |
9099 | pf->hw.dev_caps.num_rx_qp, | |
9100 | pf->hw.dev_caps.num_tx_qp); | |
9101 | } | |
9102 | } | |
9103 | if (list_type == i40e_aqc_opc_list_func_capabilities) { | |
7134f9ce JB |
9104 | #define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \ |
9105 | + pf->hw.func_caps.num_vfs) | |
2f4b411a AN |
9106 | if (pf->hw.revision_id == 0 && |
9107 | pf->hw.func_caps.num_vsis < DEF_NUM_VSI) { | |
9108 | dev_info(&pf->pdev->dev, | |
9109 | "got num_vsis %d, setting num_vsis to %d\n", | |
9110 | pf->hw.func_caps.num_vsis, DEF_NUM_VSI); | |
9111 | pf->hw.func_caps.num_vsis = DEF_NUM_VSI; | |
9112 | } | |
7134f9ce | 9113 | } |
41c445ff JB |
9114 | return 0; |
9115 | } | |
9116 | ||
cbf61325 ASJ |
9117 | static int i40e_vsi_clear(struct i40e_vsi *vsi); |
9118 | ||
41c445ff | 9119 | /** |
cbf61325 | 9120 | * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband |
41c445ff JB |
9121 | * @pf: board private structure |
9122 | **/ | |
cbf61325 | 9123 | static void i40e_fdir_sb_setup(struct i40e_pf *pf) |
41c445ff JB |
9124 | { |
9125 | struct i40e_vsi *vsi; | |
41c445ff | 9126 | |
407e063c JB |
9127 | /* quick workaround for an NVM issue that leaves a critical register |
9128 | * uninitialized | |
9129 | */ | |
9130 | if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) { | |
9131 | static const u32 hkey[] = { | |
9132 | 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36, | |
9133 | 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb, | |
9134 | 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21, | |
9135 | 0x95b3a76d}; | |
4b816446 | 9136 | int i; |
407e063c JB |
9137 | |
9138 | for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++) | |
9139 | wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]); | |
9140 | } | |
9141 | ||
cbf61325 | 9142 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) |
41c445ff JB |
9143 | return; |
9144 | ||
cbf61325 | 9145 | /* find existing VSI and see if it needs configuring */ |
4b816446 | 9146 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
cbf61325 ASJ |
9147 | |
9148 | /* create a new VSI if none exists */ | |
41c445ff | 9149 | if (!vsi) { |
cbf61325 ASJ |
9150 | vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, |
9151 | pf->vsi[pf->lan_vsi]->seid, 0); | |
41c445ff JB |
9152 | if (!vsi) { |
9153 | dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n"); | |
8a9eb7d3 | 9154 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; |
2f4b411a | 9155 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
8a9eb7d3 | 9156 | return; |
41c445ff | 9157 | } |
cbf61325 | 9158 | } |
41c445ff | 9159 | |
8a9eb7d3 | 9160 | i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring); |
41c445ff JB |
9161 | } |
9162 | ||
9163 | /** | |
9164 | * i40e_fdir_teardown - release the Flow Director resources | |
9165 | * @pf: board private structure | |
9166 | **/ | |
9167 | static void i40e_fdir_teardown(struct i40e_pf *pf) | |
9168 | { | |
4b816446 | 9169 | struct i40e_vsi *vsi; |
41c445ff | 9170 | |
17a73f6b | 9171 | i40e_fdir_filter_exit(pf); |
4b816446 AD |
9172 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
9173 | if (vsi) | |
9174 | i40e_vsi_release(vsi); | |
41c445ff JB |
9175 | } |
9176 | ||
2f4b411a AN |
9177 | /** |
9178 | * i40e_rebuild_cloud_filters - Rebuilds cloud filters for VSIs | |
9179 | * @vsi: PF main vsi | |
9180 | * @seid: seid of main or channel VSIs | |
9181 | * | |
9182 | * Rebuilds cloud filters associated with main VSI and channel VSIs if they | |
9183 | * existed before reset | |
9184 | **/ | |
9185 | static int i40e_rebuild_cloud_filters(struct i40e_vsi *vsi, u16 seid) | |
9186 | { | |
9187 | struct i40e_cloud_filter *cfilter; | |
9188 | struct i40e_pf *pf = vsi->back; | |
9189 | struct hlist_node *node; | |
9190 | i40e_status ret; | |
9191 | ||
9192 | /* Add cloud filters back if they exist */ | |
9193 | hlist_for_each_entry_safe(cfilter, node, &pf->cloud_filter_list, | |
9194 | cloud_node) { | |
9195 | if (cfilter->seid != seid) | |
9196 | continue; | |
9197 | ||
9198 | if (cfilter->dst_port) | |
9199 | ret = i40e_add_del_cloud_filter_big_buf(vsi, cfilter, | |
9200 | true); | |
9201 | else | |
9202 | ret = i40e_add_del_cloud_filter(vsi, cfilter, true); | |
cbf61325 | 9203 | |
2f4b411a AN |
9204 | if (ret) { |
9205 | dev_dbg(&pf->pdev->dev, | |
9206 | "Failed to rebuild cloud filter, err %s aq_err %s\n", | |
9207 | i40e_stat_str(&pf->hw, ret), | |
9208 | i40e_aq_str(&pf->hw, | |
9209 | pf->hw.aq.asq_last_status)); | |
9210 | return ret; | |
41c445ff | 9211 | } |
cbf61325 | 9212 | } |
2f4b411a | 9213 | return 0; |
41c445ff JB |
9214 | } |
9215 | ||
9216 | /** | |
8f88b303 AN |
9217 | * i40e_rebuild_channels - Rebuilds channel VSIs if they existed before reset |
9218 | * @vsi: PF main vsi | |
9219 | * | |
9220 | * Rebuilds channel VSIs if they existed before reset | |
41c445ff | 9221 | **/ |
8f88b303 | 9222 | static int i40e_rebuild_channels(struct i40e_vsi *vsi) |
41c445ff | 9223 | { |
8f88b303 AN |
9224 | struct i40e_channel *ch, *ch_tmp; |
9225 | i40e_status ret; | |
41c445ff | 9226 | |
8f88b303 AN |
9227 | if (list_empty(&vsi->ch_list)) |
9228 | return 0; | |
9229 | ||
9230 | list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) { | |
9231 | if (!ch->initialized) | |
9232 | break; | |
9233 | /* Proceed with creation of channel (VMDq2) VSI */ | |
9234 | ret = i40e_add_channel(vsi->back, vsi->uplink_seid, ch); | |
9235 | if (ret) { | |
9236 | dev_info(&vsi->back->pdev->dev, | |
9237 | "failed to rebuild channels using uplink_seid %u\n", | |
9238 | vsi->uplink_seid); | |
9239 | return ret; | |
9240 | } | |
bbf0bdd4 AN |
9241 | /* Reconfigure TX queues using QTX_CTL register */ |
9242 | ret = i40e_channel_config_tx_ring(vsi->back, vsi, ch); | |
9243 | if (ret) { | |
9244 | dev_info(&vsi->back->pdev->dev, | |
9245 | "failed to configure TX rings for channel %u\n", | |
9246 | ch->seid); | |
9247 | return ret; | |
9248 | } | |
9249 | /* update 'next_base_queue' */ | |
9250 | vsi->next_base_queue = vsi->next_base_queue + | |
9251 | ch->num_queue_pairs; | |
2027d4de | 9252 | if (ch->max_tx_rate) { |
6c32e0d9 AB |
9253 | u64 credits = ch->max_tx_rate; |
9254 | ||
2027d4de AN |
9255 | if (i40e_set_bw_limit(vsi, ch->seid, |
9256 | ch->max_tx_rate)) | |
9257 | return -EINVAL; | |
9258 | ||
6c32e0d9 | 9259 | do_div(credits, I40E_BW_CREDIT_DIVISOR); |
2027d4de AN |
9260 | dev_dbg(&vsi->back->pdev->dev, |
9261 | "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n", | |
9262 | ch->max_tx_rate, | |
6c32e0d9 | 9263 | credits, |
2027d4de AN |
9264 | ch->seid); |
9265 | } | |
2f4b411a AN |
9266 | ret = i40e_rebuild_cloud_filters(vsi, ch->seid); |
9267 | if (ret) { | |
9268 | dev_dbg(&vsi->back->pdev->dev, | |
9269 | "Failed to rebuild cloud filters for channel VSI %u\n", | |
9270 | ch->seid); | |
9271 | return ret; | |
9272 | } | |
8f88b303 AN |
9273 | } |
9274 | return 0; | |
41c445ff JB |
9275 | } |
9276 | ||
9277 | /** | |
f650a38b | 9278 | * i40e_prep_for_reset - prep for the core to reset |
41c445ff | 9279 | * @pf: board private structure |
373149fc MS |
9280 | * @lock_acquired: indicates whether or not the lock has been acquired |
9281 | * before this function was called. | |
41c445ff | 9282 | * |
b40c82e6 | 9283 | * Close up the VFs and other things in prep for PF Reset. |
f650a38b | 9284 | **/ |
373149fc | 9285 | static void i40e_prep_for_reset(struct i40e_pf *pf, bool lock_acquired) |
41c445ff | 9286 | { |
41c445ff | 9287 | struct i40e_hw *hw = &pf->hw; |
60442dea | 9288 | i40e_status ret = 0; |
41c445ff JB |
9289 | u32 v; |
9290 | ||
0da36b97 JK |
9291 | clear_bit(__I40E_RESET_INTR_RECEIVED, pf->state); |
9292 | if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) | |
23cfbe07 | 9293 | return; |
d3ce5734 MW |
9294 | if (i40e_check_asq_alive(&pf->hw)) |
9295 | i40e_vc_notify_reset(pf); | |
41c445ff | 9296 | |
69bfb110 | 9297 | dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n"); |
41c445ff | 9298 | |
41c445ff | 9299 | /* quiesce the VSIs and their queues that are not already DOWN */ |
373149fc MS |
9300 | /* pf_quiesce_all_vsi modifies netdev structures -rtnl_lock needed */ |
9301 | if (!lock_acquired) | |
9302 | rtnl_lock(); | |
41c445ff | 9303 | i40e_pf_quiesce_all_vsi(pf); |
373149fc MS |
9304 | if (!lock_acquired) |
9305 | rtnl_unlock(); | |
41c445ff | 9306 | |
505682cd | 9307 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
9308 | if (pf->vsi[v]) |
9309 | pf->vsi[v]->seid = 0; | |
9310 | } | |
9311 | ||
9312 | i40e_shutdown_adminq(&pf->hw); | |
9313 | ||
f650a38b | 9314 | /* call shutdown HMC */ |
60442dea SN |
9315 | if (hw->hmc.hmc_obj) { |
9316 | ret = i40e_shutdown_lan_hmc(hw); | |
23cfbe07 | 9317 | if (ret) |
60442dea SN |
9318 | dev_warn(&pf->pdev->dev, |
9319 | "shutdown_lan_hmc failed: %d\n", ret); | |
f650a38b | 9320 | } |
bf4bf09b JK |
9321 | |
9322 | /* Save the current PTP time so that we can restore the time after the | |
9323 | * reset completes. | |
9324 | */ | |
9325 | i40e_ptp_save_hw_time(pf); | |
f650a38b ASJ |
9326 | } |
9327 | ||
44033fac JB |
9328 | /** |
9329 | * i40e_send_version - update firmware with driver version | |
9330 | * @pf: PF struct | |
9331 | */ | |
9332 | static void i40e_send_version(struct i40e_pf *pf) | |
9333 | { | |
9334 | struct i40e_driver_version dv; | |
9335 | ||
9336 | dv.major_version = DRV_VERSION_MAJOR; | |
9337 | dv.minor_version = DRV_VERSION_MINOR; | |
9338 | dv.build_version = DRV_VERSION_BUILD; | |
9339 | dv.subbuild_version = 0; | |
35a7d804 | 9340 | strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string)); |
44033fac JB |
9341 | i40e_aq_send_driver_version(&pf->hw, &dv, NULL); |
9342 | } | |
9343 | ||
5bbb2e20 FS |
9344 | /** |
9345 | * i40e_get_oem_version - get OEM specific version information | |
9346 | * @hw: pointer to the hardware structure | |
9347 | **/ | |
9348 | static void i40e_get_oem_version(struct i40e_hw *hw) | |
9349 | { | |
9350 | u16 block_offset = 0xffff; | |
9351 | u16 block_length = 0; | |
9352 | u16 capabilities = 0; | |
9353 | u16 gen_snap = 0; | |
9354 | u16 release = 0; | |
9355 | ||
9356 | #define I40E_SR_NVM_OEM_VERSION_PTR 0x1B | |
9357 | #define I40E_NVM_OEM_LENGTH_OFFSET 0x00 | |
9358 | #define I40E_NVM_OEM_CAPABILITIES_OFFSET 0x01 | |
9359 | #define I40E_NVM_OEM_GEN_OFFSET 0x02 | |
9360 | #define I40E_NVM_OEM_RELEASE_OFFSET 0x03 | |
9361 | #define I40E_NVM_OEM_CAPABILITIES_MASK 0x000F | |
9362 | #define I40E_NVM_OEM_LENGTH 3 | |
9363 | ||
9364 | /* Check if pointer to OEM version block is valid. */ | |
9365 | i40e_read_nvm_word(hw, I40E_SR_NVM_OEM_VERSION_PTR, &block_offset); | |
9366 | if (block_offset == 0xffff) | |
9367 | return; | |
9368 | ||
9369 | /* Check if OEM version block has correct length. */ | |
9370 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_LENGTH_OFFSET, | |
9371 | &block_length); | |
9372 | if (block_length < I40E_NVM_OEM_LENGTH) | |
9373 | return; | |
9374 | ||
9375 | /* Check if OEM version format is as expected. */ | |
9376 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_CAPABILITIES_OFFSET, | |
9377 | &capabilities); | |
9378 | if ((capabilities & I40E_NVM_OEM_CAPABILITIES_MASK) != 0) | |
9379 | return; | |
9380 | ||
9381 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_GEN_OFFSET, | |
9382 | &gen_snap); | |
9383 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_RELEASE_OFFSET, | |
9384 | &release); | |
9385 | hw->nvm.oem_ver = (gen_snap << I40E_OEM_SNAP_SHIFT) | release; | |
9386 | hw->nvm.eetrack = I40E_OEM_EETRACK_ID; | |
9387 | } | |
9388 | ||
f650a38b | 9389 | /** |
373149fc | 9390 | * i40e_reset - wait for core reset to finish reset, reset pf if corer not seen |
f650a38b ASJ |
9391 | * @pf: board private structure |
9392 | **/ | |
373149fc | 9393 | static int i40e_reset(struct i40e_pf *pf) |
f650a38b | 9394 | { |
f650a38b ASJ |
9395 | struct i40e_hw *hw = &pf->hw; |
9396 | i40e_status ret; | |
f650a38b | 9397 | |
41c445ff | 9398 | ret = i40e_pf_reset(hw); |
b5565400 | 9399 | if (ret) { |
41c445ff | 9400 | dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret); |
0da36b97 JK |
9401 | set_bit(__I40E_RESET_FAILED, pf->state); |
9402 | clear_bit(__I40E_RESET_RECOVERY_PENDING, pf->state); | |
373149fc MS |
9403 | } else { |
9404 | pf->pfr_count++; | |
b5565400 | 9405 | } |
373149fc MS |
9406 | return ret; |
9407 | } | |
9408 | ||
9409 | /** | |
9410 | * i40e_rebuild - rebuild using a saved config | |
9411 | * @pf: board private structure | |
9412 | * @reinit: if the Main VSI needs to re-initialized. | |
9413 | * @lock_acquired: indicates whether or not the lock has been acquired | |
9414 | * before this function was called. | |
9415 | **/ | |
9416 | static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired) | |
9417 | { | |
4ff0ee1a | 9418 | int old_recovery_mode_bit = test_bit(__I40E_RECOVERY_MODE, pf->state); |
2027d4de | 9419 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
373149fc MS |
9420 | struct i40e_hw *hw = &pf->hw; |
9421 | u8 set_fc_aq_fail = 0; | |
9422 | i40e_status ret; | |
9423 | u32 val; | |
9424 | int v; | |
41c445ff | 9425 | |
4ff0ee1a AM |
9426 | if (test_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state) && |
9427 | i40e_check_recovery_mode(pf)) { | |
9428 | i40e_set_ethtool_ops(pf->vsi[pf->lan_vsi]->netdev); | |
9429 | } | |
9430 | ||
9431 | if (test_bit(__I40E_DOWN, pf->state) && | |
9432 | !test_bit(__I40E_RECOVERY_MODE, pf->state) && | |
9433 | !old_recovery_mode_bit) | |
a316f651 | 9434 | goto clear_recovery; |
69bfb110 | 9435 | dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n"); |
41c445ff JB |
9436 | |
9437 | /* rebuild the basics for the AdminQ, HMC, and initial HW switch */ | |
9438 | ret = i40e_init_adminq(&pf->hw); | |
9439 | if (ret) { | |
f1c7e72e SN |
9440 | dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n", |
9441 | i40e_stat_str(&pf->hw, ret), | |
9442 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
a316f651 | 9443 | goto clear_recovery; |
41c445ff | 9444 | } |
5bbb2e20 | 9445 | i40e_get_oem_version(&pf->hw); |
41c445ff | 9446 | |
1fa51a65 FS |
9447 | if (test_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state) && |
9448 | ((hw->aq.fw_maj_ver == 4 && hw->aq.fw_min_ver <= 33) || | |
9449 | hw->aq.fw_maj_ver < 4) && hw->mac.type == I40E_MAC_XL710) { | |
9450 | /* The following delay is necessary for 4.33 firmware and older | |
9451 | * to recover after EMP reset. 200 ms should suffice but we | |
9452 | * put here 300 ms to be sure that FW is ready to operate | |
9453 | * after reset. | |
9454 | */ | |
9455 | mdelay(300); | |
9456 | } | |
9457 | ||
4eb3f768 | 9458 | /* re-verify the eeprom if we just had an EMP reset */ |
0da36b97 | 9459 | if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state)) |
4eb3f768 | 9460 | i40e_verify_eeprom(pf); |
4eb3f768 | 9461 | |
4ff0ee1a AM |
9462 | /* if we are going out of or into recovery mode we have to act |
9463 | * accordingly with regard to resources initialization | |
9464 | * and deinitialization | |
9465 | */ | |
9466 | if (test_bit(__I40E_RECOVERY_MODE, pf->state) || | |
9467 | old_recovery_mode_bit) { | |
9468 | if (i40e_get_capabilities(pf, | |
9469 | i40e_aqc_opc_list_func_capabilities)) | |
9470 | goto end_unlock; | |
9471 | ||
9472 | if (test_bit(__I40E_RECOVERY_MODE, pf->state)) { | |
9473 | /* we're staying in recovery mode so we'll reinitialize | |
9474 | * misc vector here | |
9475 | */ | |
9476 | if (i40e_setup_misc_vector_for_recovery_mode(pf)) | |
9477 | goto end_unlock; | |
9478 | } else { | |
9479 | if (!lock_acquired) | |
9480 | rtnl_lock(); | |
9481 | /* we're going out of recovery mode so we'll free | |
9482 | * the IRQ allocated specifically for recovery mode | |
9483 | * and restore the interrupt scheme | |
9484 | */ | |
9485 | free_irq(pf->pdev->irq, pf); | |
9486 | i40e_clear_interrupt_scheme(pf); | |
9487 | if (i40e_restore_interrupt_scheme(pf)) | |
9488 | goto end_unlock; | |
9489 | } | |
9490 | ||
9491 | /* tell the firmware that we're starting */ | |
9492 | i40e_send_version(pf); | |
9493 | ||
9494 | /* bail out in case recovery mode was detected, as there is | |
9495 | * no need for further configuration. | |
9496 | */ | |
9497 | goto end_unlock; | |
9498 | } | |
9499 | ||
e78ac4bf | 9500 | i40e_clear_pxe_mode(hw); |
2f4b411a | 9501 | ret = i40e_get_capabilities(pf, i40e_aqc_opc_list_func_capabilities); |
f1c7e72e | 9502 | if (ret) |
41c445ff | 9503 | goto end_core_reset; |
41c445ff | 9504 | |
41c445ff | 9505 | ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, |
c76cb6ed | 9506 | hw->func_caps.num_rx_qp, 0, 0); |
41c445ff JB |
9507 | if (ret) { |
9508 | dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret); | |
9509 | goto end_core_reset; | |
9510 | } | |
9511 | ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); | |
9512 | if (ret) { | |
9513 | dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret); | |
9514 | goto end_core_reset; | |
9515 | } | |
9516 | ||
c61c8fe1 DE |
9517 | /* Enable FW to write a default DCB config on link-up */ |
9518 | i40e_aq_set_dcb_parameters(hw, true, NULL); | |
9519 | ||
4e3b35b0 NP |
9520 | #ifdef CONFIG_I40E_DCB |
9521 | ret = i40e_init_pf_dcb(pf); | |
9522 | if (ret) { | |
aebfc816 SN |
9523 | dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret); |
9524 | pf->flags &= ~I40E_FLAG_DCB_CAPABLE; | |
9525 | /* Continue without DCB enabled */ | |
4e3b35b0 NP |
9526 | } |
9527 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff | 9528 | /* do basic switch setup */ |
373149fc MS |
9529 | if (!lock_acquired) |
9530 | rtnl_lock(); | |
bc7d338f | 9531 | ret = i40e_setup_pf_switch(pf, reinit); |
41c445ff | 9532 | if (ret) |
373149fc | 9533 | goto end_unlock; |
41c445ff | 9534 | |
2f0aff41 SN |
9535 | /* The driver only wants link up/down and module qualification |
9536 | * reports from firmware. Note the negative logic. | |
7e2453fe JB |
9537 | */ |
9538 | ret = i40e_aq_set_phy_int_mask(&pf->hw, | |
2f0aff41 | 9539 | ~(I40E_AQ_EVENT_LINK_UPDOWN | |
867a79e3 | 9540 | I40E_AQ_EVENT_MEDIA_NA | |
2f0aff41 | 9541 | I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); |
7e2453fe | 9542 | if (ret) |
f1c7e72e SN |
9543 | dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", |
9544 | i40e_stat_str(&pf->hw, ret), | |
9545 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7e2453fe | 9546 | |
cafa2ee6 ASJ |
9547 | /* make sure our flow control settings are restored */ |
9548 | ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true); | |
9549 | if (ret) | |
8279e495 NP |
9550 | dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n", |
9551 | i40e_stat_str(&pf->hw, ret), | |
9552 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 9553 | |
41c445ff JB |
9554 | /* Rebuild the VSIs and VEBs that existed before reset. |
9555 | * They are still in our local switch element arrays, so only | |
9556 | * need to rebuild the switch model in the HW. | |
9557 | * | |
9558 | * If there were VEBs but the reconstitution failed, we'll try | |
9559 | * try to recover minimal use by getting the basic PF VSI working. | |
9560 | */ | |
2027d4de | 9561 | if (vsi->uplink_seid != pf->mac_seid) { |
69bfb110 | 9562 | dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n"); |
41c445ff JB |
9563 | /* find the one VEB connected to the MAC, and find orphans */ |
9564 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
9565 | if (!pf->veb[v]) | |
9566 | continue; | |
9567 | ||
9568 | if (pf->veb[v]->uplink_seid == pf->mac_seid || | |
9569 | pf->veb[v]->uplink_seid == 0) { | |
9570 | ret = i40e_reconstitute_veb(pf->veb[v]); | |
9571 | ||
9572 | if (!ret) | |
9573 | continue; | |
9574 | ||
9575 | /* If Main VEB failed, we're in deep doodoo, | |
9576 | * so give up rebuilding the switch and set up | |
9577 | * for minimal rebuild of PF VSI. | |
9578 | * If orphan failed, we'll report the error | |
9579 | * but try to keep going. | |
9580 | */ | |
9581 | if (pf->veb[v]->uplink_seid == pf->mac_seid) { | |
9582 | dev_info(&pf->pdev->dev, | |
9583 | "rebuild of switch failed: %d, will try to set up simple PF connection\n", | |
9584 | ret); | |
2027d4de | 9585 | vsi->uplink_seid = pf->mac_seid; |
41c445ff JB |
9586 | break; |
9587 | } else if (pf->veb[v]->uplink_seid == 0) { | |
9588 | dev_info(&pf->pdev->dev, | |
9589 | "rebuild of orphan VEB failed: %d\n", | |
9590 | ret); | |
9591 | } | |
9592 | } | |
9593 | } | |
9594 | } | |
9595 | ||
2027d4de | 9596 | if (vsi->uplink_seid == pf->mac_seid) { |
cde4cbc7 | 9597 | dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n"); |
41c445ff | 9598 | /* no VEB, so rebuild only the Main VSI */ |
2027d4de | 9599 | ret = i40e_add_vsi(vsi); |
41c445ff JB |
9600 | if (ret) { |
9601 | dev_info(&pf->pdev->dev, | |
9602 | "rebuild of Main VSI failed: %d\n", ret); | |
373149fc | 9603 | goto end_unlock; |
41c445ff JB |
9604 | } |
9605 | } | |
9606 | ||
2027d4de | 9607 | if (vsi->mqprio_qopt.max_rate[0]) { |
6c32e0d9 AB |
9608 | u64 max_tx_rate = vsi->mqprio_qopt.max_rate[0]; |
9609 | u64 credits = 0; | |
2027d4de | 9610 | |
6c32e0d9 | 9611 | do_div(max_tx_rate, I40E_BW_MBPS_DIVISOR); |
2027d4de | 9612 | ret = i40e_set_bw_limit(vsi, vsi->seid, max_tx_rate); |
6c32e0d9 | 9613 | if (ret) |
2027d4de | 9614 | goto end_unlock; |
6c32e0d9 AB |
9615 | |
9616 | credits = max_tx_rate; | |
9617 | do_div(credits, I40E_BW_CREDIT_DIVISOR); | |
9618 | dev_dbg(&vsi->back->pdev->dev, | |
9619 | "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n", | |
9620 | max_tx_rate, | |
9621 | credits, | |
9622 | vsi->seid); | |
2027d4de AN |
9623 | } |
9624 | ||
2f4b411a AN |
9625 | ret = i40e_rebuild_cloud_filters(vsi, vsi->seid); |
9626 | if (ret) | |
9627 | goto end_unlock; | |
9628 | ||
8f88b303 AN |
9629 | /* PF Main VSI is rebuild by now, go ahead and rebuild channel VSIs |
9630 | * for this main VSI if they exist | |
9631 | */ | |
2027d4de | 9632 | ret = i40e_rebuild_channels(vsi); |
8f88b303 AN |
9633 | if (ret) |
9634 | goto end_unlock; | |
9635 | ||
4f2f017c ASJ |
9636 | /* Reconfigure hardware for allowing smaller MSS in the case |
9637 | * of TSO, so that we avoid the MDD being fired and causing | |
9638 | * a reset in the case of small MSS+TSO. | |
9639 | */ | |
9640 | #define I40E_REG_MSS 0x000E64DC | |
9641 | #define I40E_REG_MSS_MIN_MASK 0x3FF0000 | |
9642 | #define I40E_64BYTE_MSS 0x400000 | |
9643 | val = rd32(hw, I40E_REG_MSS); | |
9644 | if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { | |
9645 | val &= ~I40E_REG_MSS_MIN_MASK; | |
9646 | val |= I40E_64BYTE_MSS; | |
9647 | wr32(hw, I40E_REG_MSS, val); | |
9648 | } | |
9649 | ||
d36e41dc | 9650 | if (pf->hw_features & I40E_HW_RESTART_AUTONEG) { |
025b4a54 ASJ |
9651 | msleep(75); |
9652 | ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); | |
9653 | if (ret) | |
f1c7e72e SN |
9654 | dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", |
9655 | i40e_stat_str(&pf->hw, ret), | |
9656 | i40e_aq_str(&pf->hw, | |
9657 | pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 9658 | } |
41c445ff JB |
9659 | /* reinit the misc interrupt */ |
9660 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
9661 | ret = i40e_setup_misc_vector(pf); | |
9662 | ||
e7358f54 ASJ |
9663 | /* Add a filter to drop all Flow control frames from any VSI from being |
9664 | * transmitted. By doing so we stop a malicious VF from sending out | |
9665 | * PAUSE or PFC frames and potentially controlling traffic for other | |
9666 | * PF/VF VSIs. | |
9667 | * The FW can still send Flow control frames if enabled. | |
9668 | */ | |
9669 | i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, | |
9670 | pf->main_vsi_seid); | |
9671 | ||
41c445ff JB |
9672 | /* restart the VSIs that were rebuilt and running before the reset */ |
9673 | i40e_pf_unquiesce_all_vsi(pf); | |
9674 | ||
024b05f4 JK |
9675 | /* Release the RTNL lock before we start resetting VFs */ |
9676 | if (!lock_acquired) | |
9677 | rtnl_unlock(); | |
9678 | ||
bd5608b3 AB |
9679 | /* Restore promiscuous settings */ |
9680 | ret = i40e_set_promiscuous(pf, pf->cur_promisc); | |
9681 | if (ret) | |
9682 | dev_warn(&pf->pdev->dev, | |
9683 | "Failed to restore promiscuous setting: %s, err %s aq_err %s\n", | |
9684 | pf->cur_promisc ? "on" : "off", | |
9685 | i40e_stat_str(&pf->hw, ret), | |
9686 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
9687 | ||
e4b433f4 | 9688 | i40e_reset_all_vfs(pf, true); |
69f64b2b | 9689 | |
41c445ff | 9690 | /* tell the firmware that we're starting */ |
44033fac | 9691 | i40e_send_version(pf); |
41c445ff | 9692 | |
024b05f4 JK |
9693 | /* We've already released the lock, so don't do it again */ |
9694 | goto end_core_reset; | |
9695 | ||
373149fc | 9696 | end_unlock: |
024b05f4 JK |
9697 | if (!lock_acquired) |
9698 | rtnl_unlock(); | |
41c445ff | 9699 | end_core_reset: |
0da36b97 | 9700 | clear_bit(__I40E_RESET_FAILED, pf->state); |
a316f651 | 9701 | clear_recovery: |
0da36b97 | 9702 | clear_bit(__I40E_RESET_RECOVERY_PENDING, pf->state); |
d5585b7b | 9703 | clear_bit(__I40E_TIMEOUT_RECOVERY_PENDING, pf->state); |
41c445ff JB |
9704 | } |
9705 | ||
373149fc MS |
9706 | /** |
9707 | * i40e_reset_and_rebuild - reset and rebuild using a saved config | |
9708 | * @pf: board private structure | |
9709 | * @reinit: if the Main VSI needs to re-initialized. | |
9710 | * @lock_acquired: indicates whether or not the lock has been acquired | |
9711 | * before this function was called. | |
9712 | **/ | |
9713 | static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit, | |
9714 | bool lock_acquired) | |
9715 | { | |
9716 | int ret; | |
9717 | /* Now we wait for GRST to settle out. | |
9718 | * We don't have to delete the VEBs or VSIs from the hw switch | |
9719 | * because the reset will make them disappear. | |
9720 | */ | |
9721 | ret = i40e_reset(pf); | |
9722 | if (!ret) | |
9723 | i40e_rebuild(pf, reinit, lock_acquired); | |
9724 | } | |
9725 | ||
f650a38b | 9726 | /** |
b40c82e6 | 9727 | * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild |
f650a38b ASJ |
9728 | * @pf: board private structure |
9729 | * | |
9730 | * Close up the VFs and other things in prep for a Core Reset, | |
9731 | * then get ready to rebuild the world. | |
373149fc MS |
9732 | * @lock_acquired: indicates whether or not the lock has been acquired |
9733 | * before this function was called. | |
f650a38b | 9734 | **/ |
373149fc | 9735 | static void i40e_handle_reset_warning(struct i40e_pf *pf, bool lock_acquired) |
f650a38b | 9736 | { |
373149fc MS |
9737 | i40e_prep_for_reset(pf, lock_acquired); |
9738 | i40e_reset_and_rebuild(pf, false, lock_acquired); | |
f650a38b ASJ |
9739 | } |
9740 | ||
41c445ff JB |
9741 | /** |
9742 | * i40e_handle_mdd_event | |
b40c82e6 | 9743 | * @pf: pointer to the PF structure |
41c445ff JB |
9744 | * |
9745 | * Called from the MDD irq handler to identify possibly malicious vfs | |
9746 | **/ | |
9747 | static void i40e_handle_mdd_event(struct i40e_pf *pf) | |
9748 | { | |
9749 | struct i40e_hw *hw = &pf->hw; | |
9750 | bool mdd_detected = false; | |
9751 | struct i40e_vf *vf; | |
9752 | u32 reg; | |
9753 | int i; | |
9754 | ||
0da36b97 | 9755 | if (!test_bit(__I40E_MDD_EVENT_PENDING, pf->state)) |
41c445ff JB |
9756 | return; |
9757 | ||
9758 | /* find what triggered the MDD event */ | |
9759 | reg = rd32(hw, I40E_GL_MDET_TX); | |
9760 | if (reg & I40E_GL_MDET_TX_VALID_MASK) { | |
4c33f83a ASJ |
9761 | u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> |
9762 | I40E_GL_MDET_TX_PF_NUM_SHIFT; | |
2089ad03 | 9763 | u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >> |
4c33f83a | 9764 | I40E_GL_MDET_TX_VF_NUM_SHIFT; |
013f6579 | 9765 | u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> |
4c33f83a | 9766 | I40E_GL_MDET_TX_EVENT_SHIFT; |
2089ad03 MW |
9767 | u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >> |
9768 | I40E_GL_MDET_TX_QUEUE_SHIFT) - | |
9769 | pf->hw.func_caps.base_queue; | |
faf32978 | 9770 | if (netif_msg_tx_err(pf)) |
b40c82e6 | 9771 | dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n", |
faf32978 | 9772 | event, queue, pf_num, vf_num); |
41c445ff JB |
9773 | wr32(hw, I40E_GL_MDET_TX, 0xffffffff); |
9774 | mdd_detected = true; | |
9775 | } | |
9776 | reg = rd32(hw, I40E_GL_MDET_RX); | |
9777 | if (reg & I40E_GL_MDET_RX_VALID_MASK) { | |
4c33f83a ASJ |
9778 | u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> |
9779 | I40E_GL_MDET_RX_FUNCTION_SHIFT; | |
013f6579 | 9780 | u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> |
4c33f83a | 9781 | I40E_GL_MDET_RX_EVENT_SHIFT; |
2089ad03 MW |
9782 | u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >> |
9783 | I40E_GL_MDET_RX_QUEUE_SHIFT) - | |
9784 | pf->hw.func_caps.base_queue; | |
faf32978 JB |
9785 | if (netif_msg_rx_err(pf)) |
9786 | dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n", | |
9787 | event, queue, func); | |
41c445ff JB |
9788 | wr32(hw, I40E_GL_MDET_RX, 0xffffffff); |
9789 | mdd_detected = true; | |
9790 | } | |
9791 | ||
df430b12 NP |
9792 | if (mdd_detected) { |
9793 | reg = rd32(hw, I40E_PF_MDET_TX); | |
9794 | if (reg & I40E_PF_MDET_TX_VALID_MASK) { | |
9795 | wr32(hw, I40E_PF_MDET_TX, 0xFFFF); | |
a1df906c | 9796 | dev_dbg(&pf->pdev->dev, "TX driver issue detected on PF\n"); |
df430b12 NP |
9797 | } |
9798 | reg = rd32(hw, I40E_PF_MDET_RX); | |
9799 | if (reg & I40E_PF_MDET_RX_VALID_MASK) { | |
9800 | wr32(hw, I40E_PF_MDET_RX, 0xFFFF); | |
a1df906c | 9801 | dev_dbg(&pf->pdev->dev, "RX driver issue detected on PF\n"); |
df430b12 NP |
9802 | } |
9803 | } | |
9804 | ||
41c445ff JB |
9805 | /* see if one of the VFs needs its hand slapped */ |
9806 | for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) { | |
9807 | vf = &(pf->vf[i]); | |
9808 | reg = rd32(hw, I40E_VP_MDET_TX(i)); | |
9809 | if (reg & I40E_VP_MDET_TX_VALID_MASK) { | |
9810 | wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF); | |
9811 | vf->num_mdd_events++; | |
faf32978 JB |
9812 | dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n", |
9813 | i); | |
a7da7f16 CW |
9814 | dev_info(&pf->pdev->dev, |
9815 | "Use PF Control I/F to re-enable the VF\n"); | |
9816 | set_bit(I40E_VF_STATE_DISABLED, &vf->vf_states); | |
41c445ff JB |
9817 | } |
9818 | ||
9819 | reg = rd32(hw, I40E_VP_MDET_RX(i)); | |
9820 | if (reg & I40E_VP_MDET_RX_VALID_MASK) { | |
9821 | wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF); | |
9822 | vf->num_mdd_events++; | |
faf32978 JB |
9823 | dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n", |
9824 | i); | |
41c445ff JB |
9825 | dev_info(&pf->pdev->dev, |
9826 | "Use PF Control I/F to re-enable the VF\n"); | |
6322e63c | 9827 | set_bit(I40E_VF_STATE_DISABLED, &vf->vf_states); |
41c445ff JB |
9828 | } |
9829 | } | |
9830 | ||
9831 | /* re-enable mdd interrupt cause */ | |
0da36b97 | 9832 | clear_bit(__I40E_MDD_EVENT_PENDING, pf->state); |
41c445ff JB |
9833 | reg = rd32(hw, I40E_PFINT_ICR0_ENA); |
9834 | reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; | |
9835 | wr32(hw, I40E_PFINT_ICR0_ENA, reg); | |
9836 | i40e_flush(hw); | |
9837 | } | |
9838 | ||
5305d0fe | 9839 | static const char *i40e_tunnel_name(u8 type) |
d8b2c700 | 9840 | { |
5305d0fe | 9841 | switch (type) { |
d8b2c700 JK |
9842 | case UDP_TUNNEL_TYPE_VXLAN: |
9843 | return "vxlan"; | |
9844 | case UDP_TUNNEL_TYPE_GENEVE: | |
9845 | return "geneve"; | |
9846 | default: | |
9847 | return "unknown"; | |
9848 | } | |
9849 | } | |
9850 | ||
1f190d93 AD |
9851 | /** |
9852 | * i40e_sync_udp_filters - Trigger a sync event for existing UDP filters | |
9853 | * @pf: board private structure | |
9854 | **/ | |
9855 | static void i40e_sync_udp_filters(struct i40e_pf *pf) | |
9856 | { | |
9857 | int i; | |
9858 | ||
9859 | /* loop through and set pending bit for all active UDP filters */ | |
9860 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { | |
9861 | if (pf->udp_ports[i].port) | |
9862 | pf->pending_udp_bitmap |= BIT_ULL(i); | |
9863 | } | |
9864 | ||
41898c66 | 9865 | set_bit(__I40E_UDP_FILTER_SYNC_PENDING, pf->state); |
1f190d93 AD |
9866 | } |
9867 | ||
a1c9a9d9 | 9868 | /** |
6a899024 | 9869 | * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW |
a1c9a9d9 JK |
9870 | * @pf: board private structure |
9871 | **/ | |
6a899024 | 9872 | static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf) |
a1c9a9d9 | 9873 | { |
a1c9a9d9 | 9874 | struct i40e_hw *hw = &pf->hw; |
5305d0fe | 9875 | u8 filter_index, type; |
fe0b0cd9 | 9876 | u16 port; |
a1c9a9d9 JK |
9877 | int i; |
9878 | ||
41898c66 | 9879 | if (!test_and_clear_bit(__I40E_UDP_FILTER_SYNC_PENDING, pf->state)) |
a1c9a9d9 JK |
9880 | return; |
9881 | ||
5305d0fe AD |
9882 | /* acquire RTNL to maintain state of flags and port requests */ |
9883 | rtnl_lock(); | |
9884 | ||
a1c9a9d9 | 9885 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { |
6a899024 | 9886 | if (pf->pending_udp_bitmap & BIT_ULL(i)) { |
5305d0fe AD |
9887 | struct i40e_udp_port_config *udp_port; |
9888 | i40e_status ret = 0; | |
9889 | ||
9890 | udp_port = &pf->udp_ports[i]; | |
6a899024 | 9891 | pf->pending_udp_bitmap &= ~BIT_ULL(i); |
5305d0fe AD |
9892 | |
9893 | port = READ_ONCE(udp_port->port); | |
9894 | type = READ_ONCE(udp_port->type); | |
9895 | filter_index = READ_ONCE(udp_port->filter_index); | |
9896 | ||
9897 | /* release RTNL while we wait on AQ command */ | |
9898 | rtnl_unlock(); | |
9899 | ||
c22c06c8 | 9900 | if (port) |
b3f5c7bc | 9901 | ret = i40e_aq_add_udp_tunnel(hw, port, |
5305d0fe AD |
9902 | type, |
9903 | &filter_index, | |
9904 | NULL); | |
9905 | else if (filter_index != I40E_UDP_PORT_INDEX_UNUSED) | |
9906 | ret = i40e_aq_del_udp_tunnel(hw, filter_index, | |
9907 | NULL); | |
9908 | ||
9909 | /* reacquire RTNL so we can update filter_index */ | |
9910 | rtnl_lock(); | |
a1c9a9d9 JK |
9911 | |
9912 | if (ret) { | |
d8b2c700 JK |
9913 | dev_info(&pf->pdev->dev, |
9914 | "%s %s port %d, index %d failed, err %s aq_err %s\n", | |
5305d0fe | 9915 | i40e_tunnel_name(type), |
d8b2c700 | 9916 | port ? "add" : "delete", |
5305d0fe AD |
9917 | port, |
9918 | filter_index, | |
d8b2c700 JK |
9919 | i40e_stat_str(&pf->hw, ret), |
9920 | i40e_aq_str(&pf->hw, | |
9921 | pf->hw.aq.asq_last_status)); | |
5305d0fe AD |
9922 | if (port) { |
9923 | /* failed to add, just reset port, | |
9924 | * drop pending bit for any deletion | |
9925 | */ | |
9926 | udp_port->port = 0; | |
9927 | pf->pending_udp_bitmap &= ~BIT_ULL(i); | |
9928 | } | |
9929 | } else if (port) { | |
9930 | /* record filter index on success */ | |
9931 | udp_port->filter_index = filter_index; | |
a1c9a9d9 JK |
9932 | } |
9933 | } | |
9934 | } | |
5305d0fe AD |
9935 | |
9936 | rtnl_unlock(); | |
a1c9a9d9 JK |
9937 | } |
9938 | ||
41c445ff JB |
9939 | /** |
9940 | * i40e_service_task - Run the driver's async subtasks | |
9941 | * @work: pointer to work_struct containing our data | |
9942 | **/ | |
9943 | static void i40e_service_task(struct work_struct *work) | |
9944 | { | |
9945 | struct i40e_pf *pf = container_of(work, | |
9946 | struct i40e_pf, | |
9947 | service_task); | |
9948 | unsigned long start_time = jiffies; | |
9949 | ||
e57a2fea | 9950 | /* don't bother with service tasks if a reset is in progress */ |
4ff0ee1a AM |
9951 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) || |
9952 | test_bit(__I40E_SUSPENDED, pf->state)) | |
e57a2fea | 9953 | return; |
e57a2fea | 9954 | |
0da36b97 | 9955 | if (test_and_set_bit(__I40E_SERVICE_SCHED, pf->state)) |
91089033 MW |
9956 | return; |
9957 | ||
4ff0ee1a AM |
9958 | if (!test_bit(__I40E_RECOVERY_MODE, pf->state)) { |
9959 | i40e_detect_recover_hung(pf->vsi[pf->lan_vsi]); | |
9960 | i40e_sync_filters_subtask(pf); | |
9961 | i40e_reset_subtask(pf); | |
9962 | i40e_handle_mdd_event(pf); | |
9963 | i40e_vc_process_vflr_event(pf); | |
9964 | i40e_watchdog_subtask(pf); | |
9965 | i40e_fdir_reinit_subtask(pf); | |
9966 | if (test_and_clear_bit(__I40E_CLIENT_RESET, pf->state)) { | |
9967 | /* Client subtask will reopen next time through. */ | |
9968 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], | |
9969 | true); | |
9970 | } else { | |
9971 | i40e_client_subtask(pf); | |
9972 | if (test_and_clear_bit(__I40E_CLIENT_L2_CHANGE, | |
9973 | pf->state)) | |
9974 | i40e_notify_client_of_l2_param_changes( | |
9975 | pf->vsi[pf->lan_vsi]); | |
9976 | } | |
9977 | i40e_sync_filters_subtask(pf); | |
9978 | i40e_sync_udp_filters_subtask(pf); | |
0ef2d5af | 9979 | } else { |
4ff0ee1a AM |
9980 | i40e_reset_subtask(pf); |
9981 | } | |
9982 | ||
41c445ff JB |
9983 | i40e_clean_adminq_subtask(pf); |
9984 | ||
91089033 MW |
9985 | /* flush memory to make sure state is correct before next watchdog */ |
9986 | smp_mb__before_atomic(); | |
0da36b97 | 9987 | clear_bit(__I40E_SERVICE_SCHED, pf->state); |
41c445ff JB |
9988 | |
9989 | /* If the tasks have taken longer than one timer cycle or there | |
9990 | * is more work to be done, reschedule the service task now | |
9991 | * rather than wait for the timer to tick again. | |
9992 | */ | |
9993 | if (time_after(jiffies, (start_time + pf->service_timer_period)) || | |
0da36b97 JK |
9994 | test_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state) || |
9995 | test_bit(__I40E_MDD_EVENT_PENDING, pf->state) || | |
9996 | test_bit(__I40E_VFLR_EVENT_PENDING, pf->state)) | |
41c445ff JB |
9997 | i40e_service_event_schedule(pf); |
9998 | } | |
9999 | ||
10000 | /** | |
10001 | * i40e_service_timer - timer callback | |
10002 | * @data: pointer to PF struct | |
10003 | **/ | |
26566eae | 10004 | static void i40e_service_timer(struct timer_list *t) |
41c445ff | 10005 | { |
26566eae | 10006 | struct i40e_pf *pf = from_timer(pf, t, service_timer); |
41c445ff JB |
10007 | |
10008 | mod_timer(&pf->service_timer, | |
10009 | round_jiffies(jiffies + pf->service_timer_period)); | |
10010 | i40e_service_event_schedule(pf); | |
10011 | } | |
10012 | ||
10013 | /** | |
10014 | * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI | |
10015 | * @vsi: the VSI being configured | |
10016 | **/ | |
10017 | static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi) | |
10018 | { | |
10019 | struct i40e_pf *pf = vsi->back; | |
10020 | ||
10021 | switch (vsi->type) { | |
10022 | case I40E_VSI_MAIN: | |
10023 | vsi->alloc_queue_pairs = pf->num_lan_qps; | |
10024 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
10025 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
10026 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
10027 | vsi->num_q_vectors = pf->num_lan_msix; | |
10028 | else | |
10029 | vsi->num_q_vectors = 1; | |
10030 | ||
10031 | break; | |
10032 | ||
10033 | case I40E_VSI_FDIR: | |
10034 | vsi->alloc_queue_pairs = 1; | |
10035 | vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT, | |
10036 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
a70e407f | 10037 | vsi->num_q_vectors = pf->num_fdsb_msix; |
41c445ff JB |
10038 | break; |
10039 | ||
10040 | case I40E_VSI_VMDQ2: | |
10041 | vsi->alloc_queue_pairs = pf->num_vmdq_qps; | |
10042 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
10043 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
10044 | vsi->num_q_vectors = pf->num_vmdq_msix; | |
10045 | break; | |
10046 | ||
10047 | case I40E_VSI_SRIOV: | |
10048 | vsi->alloc_queue_pairs = pf->num_vf_qps; | |
10049 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
10050 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
10051 | break; | |
10052 | ||
10053 | default: | |
10054 | WARN_ON(1); | |
10055 | return -ENODATA; | |
10056 | } | |
10057 | ||
10058 | return 0; | |
10059 | } | |
10060 | ||
f650a38b ASJ |
10061 | /** |
10062 | * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi | |
3d7d7a86 | 10063 | * @vsi: VSI pointer |
bc7d338f | 10064 | * @alloc_qvectors: a bool to specify if q_vectors need to be allocated. |
f650a38b ASJ |
10065 | * |
10066 | * On error: returns error code (negative) | |
10067 | * On success: returns 0 | |
10068 | **/ | |
bc7d338f | 10069 | static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors) |
f650a38b | 10070 | { |
74608d17 | 10071 | struct i40e_ring **next_rings; |
f650a38b ASJ |
10072 | int size; |
10073 | int ret = 0; | |
10074 | ||
74608d17 BT |
10075 | /* allocate memory for both Tx, XDP Tx and Rx ring pointers */ |
10076 | size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * | |
10077 | (i40e_enabled_xdp_vsi(vsi) ? 3 : 2); | |
f650a38b ASJ |
10078 | vsi->tx_rings = kzalloc(size, GFP_KERNEL); |
10079 | if (!vsi->tx_rings) | |
10080 | return -ENOMEM; | |
74608d17 BT |
10081 | next_rings = vsi->tx_rings + vsi->alloc_queue_pairs; |
10082 | if (i40e_enabled_xdp_vsi(vsi)) { | |
10083 | vsi->xdp_rings = next_rings; | |
10084 | next_rings += vsi->alloc_queue_pairs; | |
10085 | } | |
10086 | vsi->rx_rings = next_rings; | |
f650a38b | 10087 | |
bc7d338f ASJ |
10088 | if (alloc_qvectors) { |
10089 | /* allocate memory for q_vector pointers */ | |
f57e4fbd | 10090 | size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors; |
bc7d338f ASJ |
10091 | vsi->q_vectors = kzalloc(size, GFP_KERNEL); |
10092 | if (!vsi->q_vectors) { | |
10093 | ret = -ENOMEM; | |
10094 | goto err_vectors; | |
10095 | } | |
f650a38b ASJ |
10096 | } |
10097 | return ret; | |
10098 | ||
10099 | err_vectors: | |
10100 | kfree(vsi->tx_rings); | |
10101 | return ret; | |
10102 | } | |
10103 | ||
41c445ff JB |
10104 | /** |
10105 | * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF | |
10106 | * @pf: board private structure | |
10107 | * @type: type of VSI | |
10108 | * | |
10109 | * On error: returns error code (negative) | |
10110 | * On success: returns vsi index in PF (positive) | |
10111 | **/ | |
10112 | static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type) | |
10113 | { | |
10114 | int ret = -ENODEV; | |
10115 | struct i40e_vsi *vsi; | |
10116 | int vsi_idx; | |
10117 | int i; | |
10118 | ||
10119 | /* Need to protect the allocation of the VSIs at the PF level */ | |
10120 | mutex_lock(&pf->switch_mutex); | |
10121 | ||
10122 | /* VSI list may be fragmented if VSI creation/destruction has | |
10123 | * been happening. We can afford to do a quick scan to look | |
10124 | * for any free VSIs in the list. | |
10125 | * | |
10126 | * find next empty vsi slot, looping back around if necessary | |
10127 | */ | |
10128 | i = pf->next_vsi; | |
505682cd | 10129 | while (i < pf->num_alloc_vsi && pf->vsi[i]) |
41c445ff | 10130 | i++; |
505682cd | 10131 | if (i >= pf->num_alloc_vsi) { |
41c445ff JB |
10132 | i = 0; |
10133 | while (i < pf->next_vsi && pf->vsi[i]) | |
10134 | i++; | |
10135 | } | |
10136 | ||
505682cd | 10137 | if (i < pf->num_alloc_vsi && !pf->vsi[i]) { |
41c445ff JB |
10138 | vsi_idx = i; /* Found one! */ |
10139 | } else { | |
10140 | ret = -ENODEV; | |
493fb300 | 10141 | goto unlock_pf; /* out of VSI slots! */ |
41c445ff JB |
10142 | } |
10143 | pf->next_vsi = ++i; | |
10144 | ||
10145 | vsi = kzalloc(sizeof(*vsi), GFP_KERNEL); | |
10146 | if (!vsi) { | |
10147 | ret = -ENOMEM; | |
493fb300 | 10148 | goto unlock_pf; |
41c445ff JB |
10149 | } |
10150 | vsi->type = type; | |
10151 | vsi->back = pf; | |
0da36b97 | 10152 | set_bit(__I40E_VSI_DOWN, vsi->state); |
41c445ff JB |
10153 | vsi->flags = 0; |
10154 | vsi->idx = vsi_idx; | |
ac26fc13 | 10155 | vsi->int_rate_limit = 0; |
5db4cb59 ASJ |
10156 | vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ? |
10157 | pf->rss_table_size : 64; | |
41c445ff JB |
10158 | vsi->netdev_registered = false; |
10159 | vsi->work_limit = I40E_DEFAULT_IRQ_WORK; | |
278e7d0b | 10160 | hash_init(vsi->mac_filter_hash); |
63741846 | 10161 | vsi->irqs_ready = false; |
41c445ff | 10162 | |
44ddd4f1 BT |
10163 | if (type == I40E_VSI_MAIN) { |
10164 | vsi->af_xdp_zc_qps = bitmap_zalloc(pf->num_lan_qps, GFP_KERNEL); | |
10165 | if (!vsi->af_xdp_zc_qps) | |
10166 | goto err_rings; | |
10167 | } | |
10168 | ||
9f65e15b AD |
10169 | ret = i40e_set_num_rings_in_vsi(vsi); |
10170 | if (ret) | |
10171 | goto err_rings; | |
10172 | ||
bc7d338f | 10173 | ret = i40e_vsi_alloc_arrays(vsi, true); |
f650a38b | 10174 | if (ret) |
9f65e15b | 10175 | goto err_rings; |
493fb300 | 10176 | |
41c445ff JB |
10177 | /* Setup default MSIX irq handler for VSI */ |
10178 | i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings); | |
10179 | ||
21659035 | 10180 | /* Initialize VSI lock */ |
278e7d0b | 10181 | spin_lock_init(&vsi->mac_filter_hash_lock); |
41c445ff JB |
10182 | pf->vsi[vsi_idx] = vsi; |
10183 | ret = vsi_idx; | |
493fb300 AD |
10184 | goto unlock_pf; |
10185 | ||
9f65e15b | 10186 | err_rings: |
44ddd4f1 | 10187 | bitmap_free(vsi->af_xdp_zc_qps); |
493fb300 AD |
10188 | pf->next_vsi = i - 1; |
10189 | kfree(vsi); | |
10190 | unlock_pf: | |
41c445ff JB |
10191 | mutex_unlock(&pf->switch_mutex); |
10192 | return ret; | |
10193 | } | |
10194 | ||
f650a38b ASJ |
10195 | /** |
10196 | * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI | |
f5254429 | 10197 | * @vsi: VSI pointer |
bc7d338f | 10198 | * @free_qvectors: a bool to specify if q_vectors need to be freed. |
f650a38b ASJ |
10199 | * |
10200 | * On error: returns error code (negative) | |
10201 | * On success: returns 0 | |
10202 | **/ | |
bc7d338f | 10203 | static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors) |
f650a38b ASJ |
10204 | { |
10205 | /* free the ring and vector containers */ | |
bc7d338f ASJ |
10206 | if (free_qvectors) { |
10207 | kfree(vsi->q_vectors); | |
10208 | vsi->q_vectors = NULL; | |
10209 | } | |
f650a38b ASJ |
10210 | kfree(vsi->tx_rings); |
10211 | vsi->tx_rings = NULL; | |
10212 | vsi->rx_rings = NULL; | |
74608d17 | 10213 | vsi->xdp_rings = NULL; |
f650a38b ASJ |
10214 | } |
10215 | ||
28c5869f HZ |
10216 | /** |
10217 | * i40e_clear_rss_config_user - clear the user configured RSS hash keys | |
10218 | * and lookup table | |
10219 | * @vsi: Pointer to VSI structure | |
10220 | */ | |
10221 | static void i40e_clear_rss_config_user(struct i40e_vsi *vsi) | |
10222 | { | |
10223 | if (!vsi) | |
10224 | return; | |
10225 | ||
10226 | kfree(vsi->rss_hkey_user); | |
10227 | vsi->rss_hkey_user = NULL; | |
10228 | ||
10229 | kfree(vsi->rss_lut_user); | |
10230 | vsi->rss_lut_user = NULL; | |
10231 | } | |
10232 | ||
41c445ff JB |
10233 | /** |
10234 | * i40e_vsi_clear - Deallocate the VSI provided | |
10235 | * @vsi: the VSI being un-configured | |
10236 | **/ | |
10237 | static int i40e_vsi_clear(struct i40e_vsi *vsi) | |
10238 | { | |
10239 | struct i40e_pf *pf; | |
10240 | ||
10241 | if (!vsi) | |
10242 | return 0; | |
10243 | ||
10244 | if (!vsi->back) | |
10245 | goto free_vsi; | |
10246 | pf = vsi->back; | |
10247 | ||
10248 | mutex_lock(&pf->switch_mutex); | |
10249 | if (!pf->vsi[vsi->idx]) { | |
7be78aa4 MW |
10250 | dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](type %d)\n", |
10251 | vsi->idx, vsi->idx, vsi->type); | |
41c445ff JB |
10252 | goto unlock_vsi; |
10253 | } | |
10254 | ||
10255 | if (pf->vsi[vsi->idx] != vsi) { | |
10256 | dev_err(&pf->pdev->dev, | |
7be78aa4 | 10257 | "pf->vsi[%d](type %d) != vsi[%d](type %d): no free!\n", |
41c445ff | 10258 | pf->vsi[vsi->idx]->idx, |
41c445ff | 10259 | pf->vsi[vsi->idx]->type, |
7be78aa4 | 10260 | vsi->idx, vsi->type); |
41c445ff JB |
10261 | goto unlock_vsi; |
10262 | } | |
10263 | ||
b40c82e6 | 10264 | /* updates the PF for this cleared vsi */ |
41c445ff JB |
10265 | i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); |
10266 | i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx); | |
10267 | ||
44ddd4f1 | 10268 | bitmap_free(vsi->af_xdp_zc_qps); |
bc7d338f | 10269 | i40e_vsi_free_arrays(vsi, true); |
28c5869f | 10270 | i40e_clear_rss_config_user(vsi); |
493fb300 | 10271 | |
41c445ff JB |
10272 | pf->vsi[vsi->idx] = NULL; |
10273 | if (vsi->idx < pf->next_vsi) | |
10274 | pf->next_vsi = vsi->idx; | |
10275 | ||
10276 | unlock_vsi: | |
10277 | mutex_unlock(&pf->switch_mutex); | |
10278 | free_vsi: | |
10279 | kfree(vsi); | |
10280 | ||
10281 | return 0; | |
10282 | } | |
10283 | ||
9f65e15b AD |
10284 | /** |
10285 | * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI | |
10286 | * @vsi: the VSI being cleaned | |
10287 | **/ | |
be1d5eea | 10288 | static void i40e_vsi_clear_rings(struct i40e_vsi *vsi) |
9f65e15b AD |
10289 | { |
10290 | int i; | |
10291 | ||
8e9dca53 | 10292 | if (vsi->tx_rings && vsi->tx_rings[0]) { |
d7397644 | 10293 | for (i = 0; i < vsi->alloc_queue_pairs; i++) { |
00403f04 MW |
10294 | kfree_rcu(vsi->tx_rings[i], rcu); |
10295 | vsi->tx_rings[i] = NULL; | |
10296 | vsi->rx_rings[i] = NULL; | |
74608d17 BT |
10297 | if (vsi->xdp_rings) |
10298 | vsi->xdp_rings[i] = NULL; | |
00403f04 | 10299 | } |
be1d5eea | 10300 | } |
9f65e15b AD |
10301 | } |
10302 | ||
41c445ff JB |
10303 | /** |
10304 | * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI | |
10305 | * @vsi: the VSI being configured | |
10306 | **/ | |
10307 | static int i40e_alloc_rings(struct i40e_vsi *vsi) | |
10308 | { | |
74608d17 | 10309 | int i, qpv = i40e_enabled_xdp_vsi(vsi) ? 3 : 2; |
41c445ff | 10310 | struct i40e_pf *pf = vsi->back; |
74608d17 | 10311 | struct i40e_ring *ring; |
41c445ff | 10312 | |
41c445ff | 10313 | /* Set basic values in the rings to be used later during open() */ |
d7397644 | 10314 | for (i = 0; i < vsi->alloc_queue_pairs; i++) { |
ac6c5e3d | 10315 | /* allocate space for both Tx and Rx in one shot */ |
74608d17 BT |
10316 | ring = kcalloc(qpv, sizeof(struct i40e_ring), GFP_KERNEL); |
10317 | if (!ring) | |
9f65e15b | 10318 | goto err_out; |
41c445ff | 10319 | |
74608d17 BT |
10320 | ring->queue_index = i; |
10321 | ring->reg_idx = vsi->base_queue + i; | |
10322 | ring->ring_active = false; | |
10323 | ring->vsi = vsi; | |
10324 | ring->netdev = vsi->netdev; | |
10325 | ring->dev = &pf->pdev->dev; | |
10326 | ring->count = vsi->num_desc; | |
10327 | ring->size = 0; | |
10328 | ring->dcb_tc = 0; | |
d36e41dc | 10329 | if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE) |
74608d17 | 10330 | ring->flags = I40E_TXR_FLAGS_WB_ON_ITR; |
40588ca6 | 10331 | ring->itr_setting = pf->tx_itr_default; |
74608d17 BT |
10332 | vsi->tx_rings[i] = ring++; |
10333 | ||
10334 | if (!i40e_enabled_xdp_vsi(vsi)) | |
10335 | goto setup_rx; | |
10336 | ||
10337 | ring->queue_index = vsi->alloc_queue_pairs + i; | |
10338 | ring->reg_idx = vsi->base_queue + ring->queue_index; | |
10339 | ring->ring_active = false; | |
10340 | ring->vsi = vsi; | |
10341 | ring->netdev = NULL; | |
10342 | ring->dev = &pf->pdev->dev; | |
10343 | ring->count = vsi->num_desc; | |
10344 | ring->size = 0; | |
10345 | ring->dcb_tc = 0; | |
d36e41dc | 10346 | if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE) |
74608d17 BT |
10347 | ring->flags = I40E_TXR_FLAGS_WB_ON_ITR; |
10348 | set_ring_xdp(ring); | |
40588ca6 | 10349 | ring->itr_setting = pf->tx_itr_default; |
74608d17 BT |
10350 | vsi->xdp_rings[i] = ring++; |
10351 | ||
10352 | setup_rx: | |
10353 | ring->queue_index = i; | |
10354 | ring->reg_idx = vsi->base_queue + i; | |
10355 | ring->ring_active = false; | |
10356 | ring->vsi = vsi; | |
10357 | ring->netdev = vsi->netdev; | |
10358 | ring->dev = &pf->pdev->dev; | |
10359 | ring->count = vsi->num_desc; | |
10360 | ring->size = 0; | |
10361 | ring->dcb_tc = 0; | |
40588ca6 | 10362 | ring->itr_setting = pf->rx_itr_default; |
74608d17 | 10363 | vsi->rx_rings[i] = ring; |
41c445ff JB |
10364 | } |
10365 | ||
10366 | return 0; | |
9f65e15b AD |
10367 | |
10368 | err_out: | |
10369 | i40e_vsi_clear_rings(vsi); | |
10370 | return -ENOMEM; | |
41c445ff JB |
10371 | } |
10372 | ||
10373 | /** | |
10374 | * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel | |
10375 | * @pf: board private structure | |
10376 | * @vectors: the number of MSI-X vectors to request | |
10377 | * | |
10378 | * Returns the number of vectors reserved, or error | |
10379 | **/ | |
10380 | static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors) | |
10381 | { | |
7b37f376 AG |
10382 | vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries, |
10383 | I40E_MIN_MSIX, vectors); | |
10384 | if (vectors < 0) { | |
41c445ff | 10385 | dev_info(&pf->pdev->dev, |
7b37f376 | 10386 | "MSI-X vector reservation failed: %d\n", vectors); |
41c445ff JB |
10387 | vectors = 0; |
10388 | } | |
10389 | ||
10390 | return vectors; | |
10391 | } | |
10392 | ||
10393 | /** | |
10394 | * i40e_init_msix - Setup the MSIX capability | |
10395 | * @pf: board private structure | |
10396 | * | |
10397 | * Work with the OS to set up the MSIX vectors needed. | |
10398 | * | |
3b444399 | 10399 | * Returns the number of vectors reserved or negative on failure |
41c445ff JB |
10400 | **/ |
10401 | static int i40e_init_msix(struct i40e_pf *pf) | |
10402 | { | |
41c445ff | 10403 | struct i40e_hw *hw = &pf->hw; |
c0cf70a6 | 10404 | int cpus, extra_vectors; |
1e200e4a | 10405 | int vectors_left; |
41c445ff | 10406 | int v_budget, i; |
3b444399 | 10407 | int v_actual; |
e3219ce6 | 10408 | int iwarp_requested = 0; |
41c445ff JB |
10409 | |
10410 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
10411 | return -ENODEV; | |
10412 | ||
10413 | /* The number of vectors we'll request will be comprised of: | |
10414 | * - Add 1 for "other" cause for Admin Queue events, etc. | |
10415 | * - The number of LAN queue pairs | |
f8ff1464 ASJ |
10416 | * - Queues being used for RSS. |
10417 | * We don't need as many as max_rss_size vectors. | |
10418 | * use rss_size instead in the calculation since that | |
10419 | * is governed by number of cpus in the system. | |
10420 | * - assumes symmetric Tx/Rx pairing | |
41c445ff | 10421 | * - The number of VMDq pairs |
e3219ce6 | 10422 | * - The CPU count within the NUMA node if iWARP is enabled |
41c445ff JB |
10423 | * Once we count this up, try the request. |
10424 | * | |
10425 | * If we can't get what we want, we'll simplify to nearly nothing | |
10426 | * and try again. If that still fails, we punt. | |
10427 | */ | |
1e200e4a SN |
10428 | vectors_left = hw->func_caps.num_msix_vectors; |
10429 | v_budget = 0; | |
10430 | ||
10431 | /* reserve one vector for miscellaneous handler */ | |
10432 | if (vectors_left) { | |
10433 | v_budget++; | |
10434 | vectors_left--; | |
10435 | } | |
10436 | ||
c0cf70a6 JK |
10437 | /* reserve some vectors for the main PF traffic queues. Initially we |
10438 | * only reserve at most 50% of the available vectors, in the case that | |
10439 | * the number of online CPUs is large. This ensures that we can enable | |
10440 | * extra features as well. Once we've enabled the other features, we | |
10441 | * will use any remaining vectors to reach as close as we can to the | |
10442 | * number of online CPUs. | |
10443 | */ | |
10444 | cpus = num_online_cpus(); | |
10445 | pf->num_lan_msix = min_t(int, cpus, vectors_left / 2); | |
1e200e4a | 10446 | vectors_left -= pf->num_lan_msix; |
1e200e4a SN |
10447 | |
10448 | /* reserve one vector for sideband flow director */ | |
10449 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
10450 | if (vectors_left) { | |
a70e407f | 10451 | pf->num_fdsb_msix = 1; |
1e200e4a SN |
10452 | v_budget++; |
10453 | vectors_left--; | |
10454 | } else { | |
a70e407f | 10455 | pf->num_fdsb_msix = 0; |
1e200e4a SN |
10456 | } |
10457 | } | |
83840e4b | 10458 | |
e3219ce6 ASJ |
10459 | /* can we reserve enough for iWARP? */ |
10460 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { | |
4ce20abc SA |
10461 | iwarp_requested = pf->num_iwarp_msix; |
10462 | ||
e3219ce6 ASJ |
10463 | if (!vectors_left) |
10464 | pf->num_iwarp_msix = 0; | |
10465 | else if (vectors_left < pf->num_iwarp_msix) | |
10466 | pf->num_iwarp_msix = 1; | |
10467 | v_budget += pf->num_iwarp_msix; | |
10468 | vectors_left -= pf->num_iwarp_msix; | |
10469 | } | |
10470 | ||
1e200e4a SN |
10471 | /* any vectors left over go for VMDq support */ |
10472 | if (pf->flags & I40E_FLAG_VMDQ_ENABLED) { | |
9ca57e97 SA |
10473 | if (!vectors_left) { |
10474 | pf->num_vmdq_msix = 0; | |
10475 | pf->num_vmdq_qps = 0; | |
10476 | } else { | |
ca12c9d4 PM |
10477 | int vmdq_vecs_wanted = |
10478 | pf->num_vmdq_vsis * pf->num_vmdq_qps; | |
10479 | int vmdq_vecs = | |
10480 | min_t(int, vectors_left, vmdq_vecs_wanted); | |
10481 | ||
9ca57e97 SA |
10482 | /* if we're short on vectors for what's desired, we limit |
10483 | * the queues per vmdq. If this is still more than are | |
10484 | * available, the user will need to change the number of | |
10485 | * queues/vectors used by the PF later with the ethtool | |
10486 | * channels command | |
10487 | */ | |
ca12c9d4 | 10488 | if (vectors_left < vmdq_vecs_wanted) { |
9ca57e97 | 10489 | pf->num_vmdq_qps = 1; |
ca12c9d4 PM |
10490 | vmdq_vecs_wanted = pf->num_vmdq_vsis; |
10491 | vmdq_vecs = min_t(int, | |
10492 | vectors_left, | |
10493 | vmdq_vecs_wanted); | |
10494 | } | |
9ca57e97 | 10495 | pf->num_vmdq_msix = pf->num_vmdq_qps; |
1e200e4a | 10496 | |
9ca57e97 SA |
10497 | v_budget += vmdq_vecs; |
10498 | vectors_left -= vmdq_vecs; | |
10499 | } | |
1e200e4a | 10500 | } |
41c445ff | 10501 | |
c0cf70a6 JK |
10502 | /* On systems with a large number of SMP cores, we previously limited |
10503 | * the number of vectors for num_lan_msix to be at most 50% of the | |
10504 | * available vectors, to allow for other features. Now, we add back | |
10505 | * the remaining vectors. However, we ensure that the total | |
10506 | * num_lan_msix will not exceed num_online_cpus(). To do this, we | |
10507 | * calculate the number of vectors we can add without going over the | |
10508 | * cap of CPUs. For systems with a small number of CPUs this will be | |
10509 | * zero. | |
10510 | */ | |
10511 | extra_vectors = min_t(int, cpus - pf->num_lan_msix, vectors_left); | |
10512 | pf->num_lan_msix += extra_vectors; | |
10513 | vectors_left -= extra_vectors; | |
10514 | ||
10515 | WARN(vectors_left < 0, | |
10516 | "Calculation of remaining vectors underflowed. This is an accounting bug when determining total MSI-X vectors.\n"); | |
10517 | ||
10518 | v_budget += pf->num_lan_msix; | |
41c445ff JB |
10519 | pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry), |
10520 | GFP_KERNEL); | |
10521 | if (!pf->msix_entries) | |
10522 | return -ENOMEM; | |
10523 | ||
10524 | for (i = 0; i < v_budget; i++) | |
10525 | pf->msix_entries[i].entry = i; | |
3b444399 | 10526 | v_actual = i40e_reserve_msix_vectors(pf, v_budget); |
a34977ba | 10527 | |
3b444399 | 10528 | if (v_actual < I40E_MIN_MSIX) { |
41c445ff JB |
10529 | pf->flags &= ~I40E_FLAG_MSIX_ENABLED; |
10530 | kfree(pf->msix_entries); | |
10531 | pf->msix_entries = NULL; | |
4c95aa5d | 10532 | pci_disable_msix(pf->pdev); |
41c445ff JB |
10533 | return -ENODEV; |
10534 | ||
3b444399 | 10535 | } else if (v_actual == I40E_MIN_MSIX) { |
41c445ff | 10536 | /* Adjust for minimal MSIX use */ |
41c445ff JB |
10537 | pf->num_vmdq_vsis = 0; |
10538 | pf->num_vmdq_qps = 0; | |
41c445ff JB |
10539 | pf->num_lan_qps = 1; |
10540 | pf->num_lan_msix = 1; | |
10541 | ||
3e6b1cf7 | 10542 | } else if (v_actual != v_budget) { |
4ce20abc SA |
10543 | /* If we have limited resources, we will start with no vectors |
10544 | * for the special features and then allocate vectors to some | |
10545 | * of these features based on the policy and at the end disable | |
10546 | * the features that did not get any vectors. | |
10547 | */ | |
3b444399 SN |
10548 | int vec; |
10549 | ||
4ce20abc | 10550 | dev_info(&pf->pdev->dev, |
3e6b1cf7 SN |
10551 | "MSI-X vector limit reached with %d, wanted %d, attempting to redistribute vectors\n", |
10552 | v_actual, v_budget); | |
a34977ba | 10553 | /* reserve the misc vector */ |
3b444399 | 10554 | vec = v_actual - 1; |
a34977ba | 10555 | |
41c445ff JB |
10556 | /* Scale vector usage down */ |
10557 | pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */ | |
a34977ba | 10558 | pf->num_vmdq_vsis = 1; |
1e200e4a | 10559 | pf->num_vmdq_qps = 1; |
41c445ff JB |
10560 | |
10561 | /* partition out the remaining vectors */ | |
10562 | switch (vec) { | |
10563 | case 2: | |
41c445ff JB |
10564 | pf->num_lan_msix = 1; |
10565 | break; | |
10566 | case 3: | |
e3219ce6 ASJ |
10567 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
10568 | pf->num_lan_msix = 1; | |
10569 | pf->num_iwarp_msix = 1; | |
10570 | } else { | |
10571 | pf->num_lan_msix = 2; | |
10572 | } | |
41c445ff JB |
10573 | break; |
10574 | default: | |
e3219ce6 ASJ |
10575 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
10576 | pf->num_iwarp_msix = min_t(int, (vec / 3), | |
10577 | iwarp_requested); | |
10578 | pf->num_vmdq_vsis = min_t(int, (vec / 3), | |
10579 | I40E_DEFAULT_NUM_VMDQ_VSI); | |
10580 | } else { | |
10581 | pf->num_vmdq_vsis = min_t(int, (vec / 2), | |
10582 | I40E_DEFAULT_NUM_VMDQ_VSI); | |
10583 | } | |
abd97a94 SA |
10584 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
10585 | pf->num_fdsb_msix = 1; | |
10586 | vec--; | |
10587 | } | |
e3219ce6 ASJ |
10588 | pf->num_lan_msix = min_t(int, |
10589 | (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)), | |
10590 | pf->num_lan_msix); | |
4ce20abc | 10591 | pf->num_lan_qps = pf->num_lan_msix; |
41c445ff JB |
10592 | break; |
10593 | } | |
10594 | } | |
10595 | ||
abd97a94 SA |
10596 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
10597 | (pf->num_fdsb_msix == 0)) { | |
10598 | dev_info(&pf->pdev->dev, "Sideband Flowdir disabled, not enough MSI-X vectors\n"); | |
10599 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
2f4b411a | 10600 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
abd97a94 | 10601 | } |
a34977ba ASJ |
10602 | if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && |
10603 | (pf->num_vmdq_msix == 0)) { | |
10604 | dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n"); | |
10605 | pf->flags &= ~I40E_FLAG_VMDQ_ENABLED; | |
10606 | } | |
e3219ce6 ASJ |
10607 | |
10608 | if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && | |
10609 | (pf->num_iwarp_msix == 0)) { | |
10610 | dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n"); | |
10611 | pf->flags &= ~I40E_FLAG_IWARP_ENABLED; | |
10612 | } | |
4ce20abc SA |
10613 | i40e_debug(&pf->hw, I40E_DEBUG_INIT, |
10614 | "MSI-X vector distribution: PF %d, VMDq %d, FDSB %d, iWARP %d\n", | |
10615 | pf->num_lan_msix, | |
10616 | pf->num_vmdq_msix * pf->num_vmdq_vsis, | |
10617 | pf->num_fdsb_msix, | |
10618 | pf->num_iwarp_msix); | |
10619 | ||
3b444399 | 10620 | return v_actual; |
41c445ff JB |
10621 | } |
10622 | ||
493fb300 | 10623 | /** |
90e04070 | 10624 | * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector |
493fb300 AD |
10625 | * @vsi: the VSI being configured |
10626 | * @v_idx: index of the vector in the vsi struct | |
7f6c5539 | 10627 | * @cpu: cpu to be used on affinity_mask |
493fb300 AD |
10628 | * |
10629 | * We allocate one q_vector. If allocation fails we return -ENOMEM. | |
10630 | **/ | |
7f6c5539 | 10631 | static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx, int cpu) |
493fb300 AD |
10632 | { |
10633 | struct i40e_q_vector *q_vector; | |
10634 | ||
10635 | /* allocate q_vector */ | |
10636 | q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL); | |
10637 | if (!q_vector) | |
10638 | return -ENOMEM; | |
10639 | ||
10640 | q_vector->vsi = vsi; | |
10641 | q_vector->v_idx = v_idx; | |
759dc4a7 | 10642 | cpumask_copy(&q_vector->affinity_mask, cpu_possible_mask); |
7f6c5539 | 10643 | |
493fb300 AD |
10644 | if (vsi->netdev) |
10645 | netif_napi_add(vsi->netdev, &q_vector->napi, | |
eefeacee | 10646 | i40e_napi_poll, NAPI_POLL_WEIGHT); |
493fb300 AD |
10647 | |
10648 | /* tie q_vector and vsi together */ | |
10649 | vsi->q_vectors[v_idx] = q_vector; | |
10650 | ||
10651 | return 0; | |
10652 | } | |
10653 | ||
41c445ff | 10654 | /** |
90e04070 | 10655 | * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors |
41c445ff JB |
10656 | * @vsi: the VSI being configured |
10657 | * | |
10658 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
10659 | * return -ENOMEM. | |
10660 | **/ | |
90e04070 | 10661 | static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi) |
41c445ff JB |
10662 | { |
10663 | struct i40e_pf *pf = vsi->back; | |
7f6c5539 | 10664 | int err, v_idx, num_q_vectors, current_cpu; |
41c445ff JB |
10665 | |
10666 | /* if not MSIX, give the one vector only to the LAN VSI */ | |
10667 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
10668 | num_q_vectors = vsi->num_q_vectors; | |
10669 | else if (vsi == pf->vsi[pf->lan_vsi]) | |
10670 | num_q_vectors = 1; | |
10671 | else | |
10672 | return -EINVAL; | |
10673 | ||
7f6c5539 GP |
10674 | current_cpu = cpumask_first(cpu_online_mask); |
10675 | ||
41c445ff | 10676 | for (v_idx = 0; v_idx < num_q_vectors; v_idx++) { |
7f6c5539 | 10677 | err = i40e_vsi_alloc_q_vector(vsi, v_idx, current_cpu); |
493fb300 AD |
10678 | if (err) |
10679 | goto err_out; | |
7f6c5539 GP |
10680 | current_cpu = cpumask_next(current_cpu, cpu_online_mask); |
10681 | if (unlikely(current_cpu >= nr_cpu_ids)) | |
10682 | current_cpu = cpumask_first(cpu_online_mask); | |
41c445ff JB |
10683 | } |
10684 | ||
10685 | return 0; | |
493fb300 AD |
10686 | |
10687 | err_out: | |
10688 | while (v_idx--) | |
10689 | i40e_free_q_vector(vsi, v_idx); | |
10690 | ||
10691 | return err; | |
41c445ff JB |
10692 | } |
10693 | ||
10694 | /** | |
10695 | * i40e_init_interrupt_scheme - Determine proper interrupt scheme | |
10696 | * @pf: board private structure to initialize | |
10697 | **/ | |
c1147280 | 10698 | static int i40e_init_interrupt_scheme(struct i40e_pf *pf) |
41c445ff | 10699 | { |
3b444399 SN |
10700 | int vectors = 0; |
10701 | ssize_t size; | |
41c445ff JB |
10702 | |
10703 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
3b444399 SN |
10704 | vectors = i40e_init_msix(pf); |
10705 | if (vectors < 0) { | |
60ea5f83 | 10706 | pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | |
e3219ce6 | 10707 | I40E_FLAG_IWARP_ENABLED | |
60ea5f83 | 10708 | I40E_FLAG_RSS_ENABLED | |
4d9b6043 | 10709 | I40E_FLAG_DCB_CAPABLE | |
a036244c | 10710 | I40E_FLAG_DCB_ENABLED | |
60ea5f83 JB |
10711 | I40E_FLAG_SRIOV_ENABLED | |
10712 | I40E_FLAG_FD_SB_ENABLED | | |
10713 | I40E_FLAG_FD_ATR_ENABLED | | |
10714 | I40E_FLAG_VMDQ_ENABLED); | |
2f4b411a | 10715 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
41c445ff JB |
10716 | |
10717 | /* rework the queue expectations without MSIX */ | |
10718 | i40e_determine_queue_usage(pf); | |
10719 | } | |
10720 | } | |
10721 | ||
10722 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) && | |
10723 | (pf->flags & I40E_FLAG_MSI_ENABLED)) { | |
77fa28be | 10724 | dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n"); |
3b444399 SN |
10725 | vectors = pci_enable_msi(pf->pdev); |
10726 | if (vectors < 0) { | |
10727 | dev_info(&pf->pdev->dev, "MSI init failed - %d\n", | |
10728 | vectors); | |
41c445ff JB |
10729 | pf->flags &= ~I40E_FLAG_MSI_ENABLED; |
10730 | } | |
3b444399 | 10731 | vectors = 1; /* one MSI or Legacy vector */ |
41c445ff JB |
10732 | } |
10733 | ||
958a3e3b | 10734 | if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED))) |
77fa28be | 10735 | dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n"); |
958a3e3b | 10736 | |
3b444399 SN |
10737 | /* set up vector assignment tracking */ |
10738 | size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors); | |
10739 | pf->irq_pile = kzalloc(size, GFP_KERNEL); | |
557450c3 | 10740 | if (!pf->irq_pile) |
c1147280 | 10741 | return -ENOMEM; |
557450c3 | 10742 | |
3b444399 SN |
10743 | pf->irq_pile->num_entries = vectors; |
10744 | pf->irq_pile->search_hint = 0; | |
10745 | ||
c1147280 | 10746 | /* track first vector for misc interrupts, ignore return */ |
3b444399 | 10747 | (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1); |
c1147280 JB |
10748 | |
10749 | return 0; | |
41c445ff JB |
10750 | } |
10751 | ||
b980c063 JK |
10752 | /** |
10753 | * i40e_restore_interrupt_scheme - Restore the interrupt scheme | |
10754 | * @pf: private board data structure | |
10755 | * | |
10756 | * Restore the interrupt scheme that was cleared when we suspended the | |
10757 | * device. This should be called during resume to re-allocate the q_vectors | |
10758 | * and reacquire IRQs. | |
10759 | */ | |
10760 | static int i40e_restore_interrupt_scheme(struct i40e_pf *pf) | |
10761 | { | |
10762 | int err, i; | |
10763 | ||
10764 | /* We cleared the MSI and MSI-X flags when disabling the old interrupt | |
10765 | * scheme. We need to re-enabled them here in order to attempt to | |
10766 | * re-acquire the MSI or MSI-X vectors | |
10767 | */ | |
10768 | pf->flags |= (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED); | |
10769 | ||
10770 | err = i40e_init_interrupt_scheme(pf); | |
10771 | if (err) | |
10772 | return err; | |
10773 | ||
10774 | /* Now that we've re-acquired IRQs, we need to remap the vectors and | |
10775 | * rings together again. | |
10776 | */ | |
10777 | for (i = 0; i < pf->num_alloc_vsi; i++) { | |
10778 | if (pf->vsi[i]) { | |
10779 | err = i40e_vsi_alloc_q_vectors(pf->vsi[i]); | |
10780 | if (err) | |
10781 | goto err_unwind; | |
10782 | i40e_vsi_map_rings_to_vectors(pf->vsi[i]); | |
10783 | } | |
10784 | } | |
10785 | ||
10786 | err = i40e_setup_misc_vector(pf); | |
10787 | if (err) | |
10788 | goto err_unwind; | |
10789 | ||
ddbb8d5d SS |
10790 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) |
10791 | i40e_client_update_msix_info(pf); | |
10792 | ||
b980c063 JK |
10793 | return 0; |
10794 | ||
10795 | err_unwind: | |
10796 | while (i--) { | |
10797 | if (pf->vsi[i]) | |
10798 | i40e_vsi_free_q_vectors(pf->vsi[i]); | |
10799 | } | |
10800 | ||
10801 | return err; | |
10802 | } | |
b980c063 | 10803 | |
4ff0ee1a AM |
10804 | /** |
10805 | * i40e_setup_misc_vector_for_recovery_mode - Setup the misc vector to handle | |
10806 | * non queue events in recovery mode | |
10807 | * @pf: board private structure | |
10808 | * | |
10809 | * This sets up the handler for MSIX 0 or MSI/legacy, which is used to manage | |
10810 | * the non-queue interrupts, e.g. AdminQ and errors in recovery mode. | |
10811 | * This is handled differently than in recovery mode since no Tx/Rx resources | |
10812 | * are being allocated. | |
10813 | **/ | |
10814 | static int i40e_setup_misc_vector_for_recovery_mode(struct i40e_pf *pf) | |
10815 | { | |
10816 | int err; | |
10817 | ||
10818 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
10819 | err = i40e_setup_misc_vector(pf); | |
10820 | ||
10821 | if (err) { | |
10822 | dev_info(&pf->pdev->dev, | |
10823 | "MSI-X misc vector request failed, error %d\n", | |
10824 | err); | |
10825 | return err; | |
10826 | } | |
10827 | } else { | |
10828 | u32 flags = pf->flags & I40E_FLAG_MSI_ENABLED ? 0 : IRQF_SHARED; | |
10829 | ||
10830 | err = request_irq(pf->pdev->irq, i40e_intr, flags, | |
10831 | pf->int_name, pf); | |
10832 | ||
10833 | if (err) { | |
10834 | dev_info(&pf->pdev->dev, | |
10835 | "MSI/legacy misc vector request failed, error %d\n", | |
10836 | err); | |
10837 | return err; | |
10838 | } | |
10839 | i40e_enable_misc_int_causes(pf); | |
10840 | i40e_irq_dynamic_enable_icr0(pf); | |
10841 | } | |
10842 | ||
10843 | return 0; | |
10844 | } | |
10845 | ||
41c445ff JB |
10846 | /** |
10847 | * i40e_setup_misc_vector - Setup the misc vector to handle non queue events | |
10848 | * @pf: board private structure | |
10849 | * | |
10850 | * This sets up the handler for MSIX 0, which is used to manage the | |
10851 | * non-queue interrupts, e.g. AdminQ and errors. This is not used | |
10852 | * when in MSI or Legacy interrupt mode. | |
10853 | **/ | |
10854 | static int i40e_setup_misc_vector(struct i40e_pf *pf) | |
10855 | { | |
10856 | struct i40e_hw *hw = &pf->hw; | |
10857 | int err = 0; | |
10858 | ||
c17401a1 JK |
10859 | /* Only request the IRQ once, the first time through. */ |
10860 | if (!test_and_set_bit(__I40E_MISC_IRQ_REQUESTED, pf->state)) { | |
41c445ff | 10861 | err = request_irq(pf->msix_entries[0].vector, |
b294ac70 | 10862 | i40e_intr, 0, pf->int_name, pf); |
41c445ff | 10863 | if (err) { |
c17401a1 | 10864 | clear_bit(__I40E_MISC_IRQ_REQUESTED, pf->state); |
41c445ff | 10865 | dev_info(&pf->pdev->dev, |
77fa28be | 10866 | "request_irq for %s failed: %d\n", |
b294ac70 | 10867 | pf->int_name, err); |
41c445ff JB |
10868 | return -EFAULT; |
10869 | } | |
10870 | } | |
10871 | ||
ab437b5a | 10872 | i40e_enable_misc_int_causes(pf); |
41c445ff JB |
10873 | |
10874 | /* associate no queues to the misc vector */ | |
10875 | wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST); | |
10876 | wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K); | |
10877 | ||
10878 | i40e_flush(hw); | |
10879 | ||
dbadbbe2 | 10880 | i40e_irq_dynamic_enable_icr0(pf); |
41c445ff JB |
10881 | |
10882 | return err; | |
10883 | } | |
10884 | ||
95a73780 ASJ |
10885 | /** |
10886 | * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands | |
10887 | * @vsi: Pointer to vsi structure | |
10888 | * @seed: Buffter to store the hash keys | |
10889 | * @lut: Buffer to store the lookup table entries | |
10890 | * @lut_size: Size of buffer to store the lookup table entries | |
10891 | * | |
10892 | * Return 0 on success, negative on failure | |
10893 | */ | |
10894 | static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed, | |
10895 | u8 *lut, u16 lut_size) | |
10896 | { | |
10897 | struct i40e_pf *pf = vsi->back; | |
10898 | struct i40e_hw *hw = &pf->hw; | |
10899 | int ret = 0; | |
10900 | ||
10901 | if (seed) { | |
10902 | ret = i40e_aq_get_rss_key(hw, vsi->id, | |
10903 | (struct i40e_aqc_get_set_rss_key_data *)seed); | |
10904 | if (ret) { | |
10905 | dev_info(&pf->pdev->dev, | |
10906 | "Cannot get RSS key, err %s aq_err %s\n", | |
10907 | i40e_stat_str(&pf->hw, ret), | |
10908 | i40e_aq_str(&pf->hw, | |
10909 | pf->hw.aq.asq_last_status)); | |
10910 | return ret; | |
10911 | } | |
10912 | } | |
10913 | ||
10914 | if (lut) { | |
10915 | bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false; | |
10916 | ||
10917 | ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size); | |
10918 | if (ret) { | |
10919 | dev_info(&pf->pdev->dev, | |
10920 | "Cannot get RSS lut, err %s aq_err %s\n", | |
10921 | i40e_stat_str(&pf->hw, ret), | |
10922 | i40e_aq_str(&pf->hw, | |
10923 | pf->hw.aq.asq_last_status)); | |
10924 | return ret; | |
10925 | } | |
10926 | } | |
10927 | ||
10928 | return ret; | |
10929 | } | |
10930 | ||
e25d00b8 | 10931 | /** |
043dd650 | 10932 | * i40e_config_rss_reg - Configure RSS keys and lut by writing registers |
e69ff813 | 10933 | * @vsi: Pointer to vsi structure |
e25d00b8 | 10934 | * @seed: RSS hash seed |
e69ff813 HZ |
10935 | * @lut: Lookup table |
10936 | * @lut_size: Lookup table size | |
10937 | * | |
10938 | * Returns 0 on success, negative on failure | |
41c445ff | 10939 | **/ |
e69ff813 HZ |
10940 | static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed, |
10941 | const u8 *lut, u16 lut_size) | |
41c445ff | 10942 | { |
e69ff813 | 10943 | struct i40e_pf *pf = vsi->back; |
4617e8c0 | 10944 | struct i40e_hw *hw = &pf->hw; |
c4e1868c | 10945 | u16 vf_id = vsi->vf_id; |
e69ff813 | 10946 | u8 i; |
41c445ff | 10947 | |
e25d00b8 | 10948 | /* Fill out hash function seed */ |
e69ff813 HZ |
10949 | if (seed) { |
10950 | u32 *seed_dw = (u32 *)seed; | |
10951 | ||
c4e1868c MW |
10952 | if (vsi->type == I40E_VSI_MAIN) { |
10953 | for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) | |
26f77e53 | 10954 | wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]); |
c4e1868c MW |
10955 | } else if (vsi->type == I40E_VSI_SRIOV) { |
10956 | for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++) | |
26f77e53 | 10957 | wr32(hw, I40E_VFQF_HKEY1(i, vf_id), seed_dw[i]); |
c4e1868c MW |
10958 | } else { |
10959 | dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n"); | |
10960 | } | |
e69ff813 HZ |
10961 | } |
10962 | ||
10963 | if (lut) { | |
10964 | u32 *lut_dw = (u32 *)lut; | |
10965 | ||
c4e1868c MW |
10966 | if (vsi->type == I40E_VSI_MAIN) { |
10967 | if (lut_size != I40E_HLUT_ARRAY_SIZE) | |
10968 | return -EINVAL; | |
10969 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
10970 | wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]); | |
10971 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
10972 | if (lut_size != I40E_VF_HLUT_ARRAY_SIZE) | |
10973 | return -EINVAL; | |
10974 | for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) | |
26f77e53 | 10975 | wr32(hw, I40E_VFQF_HLUT1(i, vf_id), lut_dw[i]); |
c4e1868c MW |
10976 | } else { |
10977 | dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n"); | |
10978 | } | |
e25d00b8 ASJ |
10979 | } |
10980 | i40e_flush(hw); | |
10981 | ||
10982 | return 0; | |
10983 | } | |
10984 | ||
043dd650 HZ |
10985 | /** |
10986 | * i40e_get_rss_reg - Get the RSS keys and lut by reading registers | |
10987 | * @vsi: Pointer to VSI structure | |
10988 | * @seed: Buffer to store the keys | |
10989 | * @lut: Buffer to store the lookup table entries | |
10990 | * @lut_size: Size of buffer to store the lookup table entries | |
10991 | * | |
10992 | * Returns 0 on success, negative on failure | |
10993 | */ | |
10994 | static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed, | |
10995 | u8 *lut, u16 lut_size) | |
10996 | { | |
10997 | struct i40e_pf *pf = vsi->back; | |
10998 | struct i40e_hw *hw = &pf->hw; | |
10999 | u16 i; | |
11000 | ||
11001 | if (seed) { | |
11002 | u32 *seed_dw = (u32 *)seed; | |
11003 | ||
11004 | for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) | |
272cdaf2 | 11005 | seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i)); |
043dd650 HZ |
11006 | } |
11007 | if (lut) { | |
11008 | u32 *lut_dw = (u32 *)lut; | |
11009 | ||
11010 | if (lut_size != I40E_HLUT_ARRAY_SIZE) | |
11011 | return -EINVAL; | |
11012 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
11013 | lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i)); | |
11014 | } | |
11015 | ||
11016 | return 0; | |
11017 | } | |
11018 | ||
11019 | /** | |
11020 | * i40e_config_rss - Configure RSS keys and lut | |
11021 | * @vsi: Pointer to VSI structure | |
11022 | * @seed: RSS hash seed | |
11023 | * @lut: Lookup table | |
11024 | * @lut_size: Lookup table size | |
11025 | * | |
11026 | * Returns 0 on success, negative on failure | |
11027 | */ | |
11028 | int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) | |
11029 | { | |
11030 | struct i40e_pf *pf = vsi->back; | |
11031 | ||
d36e41dc | 11032 | if (pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) |
043dd650 HZ |
11033 | return i40e_config_rss_aq(vsi, seed, lut, lut_size); |
11034 | else | |
11035 | return i40e_config_rss_reg(vsi, seed, lut, lut_size); | |
11036 | } | |
11037 | ||
11038 | /** | |
11039 | * i40e_get_rss - Get RSS keys and lut | |
11040 | * @vsi: Pointer to VSI structure | |
11041 | * @seed: Buffer to store the keys | |
11042 | * @lut: Buffer to store the lookup table entries | |
f5254429 | 11043 | * @lut_size: Size of buffer to store the lookup table entries |
043dd650 HZ |
11044 | * |
11045 | * Returns 0 on success, negative on failure | |
11046 | */ | |
11047 | int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) | |
11048 | { | |
95a73780 ASJ |
11049 | struct i40e_pf *pf = vsi->back; |
11050 | ||
d36e41dc | 11051 | if (pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) |
95a73780 ASJ |
11052 | return i40e_get_rss_aq(vsi, seed, lut, lut_size); |
11053 | else | |
11054 | return i40e_get_rss_reg(vsi, seed, lut, lut_size); | |
043dd650 HZ |
11055 | } |
11056 | ||
e69ff813 HZ |
11057 | /** |
11058 | * i40e_fill_rss_lut - Fill the RSS lookup table with default values | |
11059 | * @pf: Pointer to board private structure | |
11060 | * @lut: Lookup table | |
11061 | * @rss_table_size: Lookup table size | |
11062 | * @rss_size: Range of queue number for hashing | |
11063 | */ | |
f1582351 AB |
11064 | void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, |
11065 | u16 rss_table_size, u16 rss_size) | |
e69ff813 HZ |
11066 | { |
11067 | u16 i; | |
11068 | ||
11069 | for (i = 0; i < rss_table_size; i++) | |
11070 | lut[i] = i % rss_size; | |
11071 | } | |
11072 | ||
e25d00b8 | 11073 | /** |
043dd650 | 11074 | * i40e_pf_config_rss - Prepare for RSS if used |
e25d00b8 ASJ |
11075 | * @pf: board private structure |
11076 | **/ | |
043dd650 | 11077 | static int i40e_pf_config_rss(struct i40e_pf *pf) |
e25d00b8 ASJ |
11078 | { |
11079 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
11080 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
e69ff813 | 11081 | u8 *lut; |
e25d00b8 ASJ |
11082 | struct i40e_hw *hw = &pf->hw; |
11083 | u32 reg_val; | |
11084 | u64 hena; | |
e69ff813 | 11085 | int ret; |
e25d00b8 | 11086 | |
41c445ff | 11087 | /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */ |
272cdaf2 SN |
11088 | hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) | |
11089 | ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32); | |
e25d00b8 ASJ |
11090 | hena |= i40e_pf_get_default_rss_hena(pf); |
11091 | ||
272cdaf2 SN |
11092 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena); |
11093 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); | |
41c445ff | 11094 | |
e25d00b8 | 11095 | /* Determine the RSS table size based on the hardware capabilities */ |
272cdaf2 | 11096 | reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); |
e25d00b8 ASJ |
11097 | reg_val = (pf->rss_table_size == 512) ? |
11098 | (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) : | |
11099 | (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512); | |
272cdaf2 | 11100 | i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val); |
e157ea30 | 11101 | |
28c5869f | 11102 | /* Determine the RSS size of the VSI */ |
f25571b5 HR |
11103 | if (!vsi->rss_size) { |
11104 | u16 qcount; | |
b356dac8 MW |
11105 | /* If the firmware does something weird during VSI init, we |
11106 | * could end up with zero TCs. Check for that to avoid | |
11107 | * divide-by-zero. It probably won't pass traffic, but it also | |
11108 | * won't panic. | |
11109 | */ | |
11110 | qcount = vsi->num_queue_pairs / | |
11111 | (vsi->tc_config.numtc ? vsi->tc_config.numtc : 1); | |
f25571b5 HR |
11112 | vsi->rss_size = min_t(int, pf->alloc_rss_size, qcount); |
11113 | } | |
a4fa59cc MW |
11114 | if (!vsi->rss_size) |
11115 | return -EINVAL; | |
28c5869f | 11116 | |
e69ff813 HZ |
11117 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); |
11118 | if (!lut) | |
11119 | return -ENOMEM; | |
11120 | ||
28c5869f HZ |
11121 | /* Use user configured lut if there is one, otherwise use default */ |
11122 | if (vsi->rss_lut_user) | |
11123 | memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size); | |
11124 | else | |
11125 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); | |
e69ff813 | 11126 | |
28c5869f HZ |
11127 | /* Use user configured hash key if there is one, otherwise |
11128 | * use default. | |
11129 | */ | |
11130 | if (vsi->rss_hkey_user) | |
11131 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
11132 | else | |
11133 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
043dd650 | 11134 | ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size); |
e69ff813 HZ |
11135 | kfree(lut); |
11136 | ||
11137 | return ret; | |
41c445ff JB |
11138 | } |
11139 | ||
f8ff1464 ASJ |
11140 | /** |
11141 | * i40e_reconfig_rss_queues - change number of queues for rss and rebuild | |
11142 | * @pf: board private structure | |
11143 | * @queue_count: the requested queue count for rss. | |
11144 | * | |
11145 | * returns 0 if rss is not enabled, if enabled returns the final rss queue | |
11146 | * count which may be different from the requested queue count. | |
373149fc | 11147 | * Note: expects to be called while under rtnl_lock() |
f8ff1464 ASJ |
11148 | **/ |
11149 | int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count) | |
11150 | { | |
9a3bd2f1 ASJ |
11151 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
11152 | int new_rss_size; | |
11153 | ||
f8ff1464 ASJ |
11154 | if (!(pf->flags & I40E_FLAG_RSS_ENABLED)) |
11155 | return 0; | |
11156 | ||
3647cd6e | 11157 | queue_count = min_t(int, queue_count, num_online_cpus()); |
9a3bd2f1 | 11158 | new_rss_size = min_t(int, queue_count, pf->rss_size_max); |
f8ff1464 | 11159 | |
9a3bd2f1 | 11160 | if (queue_count != vsi->num_queue_pairs) { |
f25571b5 HR |
11161 | u16 qcount; |
11162 | ||
9a3bd2f1 | 11163 | vsi->req_queue_pairs = queue_count; |
373149fc | 11164 | i40e_prep_for_reset(pf, true); |
f8ff1464 | 11165 | |
acd65448 | 11166 | pf->alloc_rss_size = new_rss_size; |
f8ff1464 | 11167 | |
373149fc | 11168 | i40e_reset_and_rebuild(pf, true, true); |
28c5869f HZ |
11169 | |
11170 | /* Discard the user configured hash keys and lut, if less | |
11171 | * queues are enabled. | |
11172 | */ | |
11173 | if (queue_count < vsi->rss_size) { | |
11174 | i40e_clear_rss_config_user(vsi); | |
11175 | dev_dbg(&pf->pdev->dev, | |
11176 | "discard user configured hash keys and lut\n"); | |
11177 | } | |
11178 | ||
11179 | /* Reset vsi->rss_size, as number of enabled queues changed */ | |
f25571b5 HR |
11180 | qcount = vsi->num_queue_pairs / vsi->tc_config.numtc; |
11181 | vsi->rss_size = min_t(int, pf->alloc_rss_size, qcount); | |
28c5869f | 11182 | |
043dd650 | 11183 | i40e_pf_config_rss(pf); |
f8ff1464 | 11184 | } |
12815057 LY |
11185 | dev_info(&pf->pdev->dev, "User requested queue count/HW max RSS count: %d/%d\n", |
11186 | vsi->req_queue_pairs, pf->rss_size_max); | |
acd65448 | 11187 | return pf->alloc_rss_size; |
f8ff1464 ASJ |
11188 | } |
11189 | ||
f4492db1 | 11190 | /** |
4fc8c676 | 11191 | * i40e_get_partition_bw_setting - Retrieve BW settings for this PF partition |
f4492db1 GR |
11192 | * @pf: board private structure |
11193 | **/ | |
4fc8c676 | 11194 | i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf) |
f4492db1 GR |
11195 | { |
11196 | i40e_status status; | |
11197 | bool min_valid, max_valid; | |
11198 | u32 max_bw, min_bw; | |
11199 | ||
11200 | status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw, | |
11201 | &min_valid, &max_valid); | |
11202 | ||
11203 | if (!status) { | |
11204 | if (min_valid) | |
4fc8c676 | 11205 | pf->min_bw = min_bw; |
f4492db1 | 11206 | if (max_valid) |
4fc8c676 | 11207 | pf->max_bw = max_bw; |
f4492db1 GR |
11208 | } |
11209 | ||
11210 | return status; | |
11211 | } | |
11212 | ||
11213 | /** | |
4fc8c676 | 11214 | * i40e_set_partition_bw_setting - Set BW settings for this PF partition |
f4492db1 GR |
11215 | * @pf: board private structure |
11216 | **/ | |
4fc8c676 | 11217 | i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf) |
f4492db1 GR |
11218 | { |
11219 | struct i40e_aqc_configure_partition_bw_data bw_data; | |
11220 | i40e_status status; | |
11221 | ||
b40c82e6 | 11222 | /* Set the valid bit for this PF */ |
41a1d04b | 11223 | bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id)); |
4fc8c676 SN |
11224 | bw_data.max_bw[pf->hw.pf_id] = pf->max_bw & I40E_ALT_BW_VALUE_MASK; |
11225 | bw_data.min_bw[pf->hw.pf_id] = pf->min_bw & I40E_ALT_BW_VALUE_MASK; | |
f4492db1 GR |
11226 | |
11227 | /* Set the new bandwidths */ | |
11228 | status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL); | |
11229 | ||
11230 | return status; | |
11231 | } | |
11232 | ||
11233 | /** | |
4fc8c676 | 11234 | * i40e_commit_partition_bw_setting - Commit BW settings for this PF partition |
f4492db1 GR |
11235 | * @pf: board private structure |
11236 | **/ | |
4fc8c676 | 11237 | i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf) |
f4492db1 GR |
11238 | { |
11239 | /* Commit temporary BW setting to permanent NVM image */ | |
11240 | enum i40e_admin_queue_err last_aq_status; | |
11241 | i40e_status ret; | |
11242 | u16 nvm_word; | |
11243 | ||
11244 | if (pf->hw.partition_id != 1) { | |
11245 | dev_info(&pf->pdev->dev, | |
11246 | "Commit BW only works on partition 1! This is partition %d", | |
11247 | pf->hw.partition_id); | |
11248 | ret = I40E_NOT_SUPPORTED; | |
11249 | goto bw_commit_out; | |
11250 | } | |
11251 | ||
11252 | /* Acquire NVM for read access */ | |
11253 | ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ); | |
11254 | last_aq_status = pf->hw.aq.asq_last_status; | |
11255 | if (ret) { | |
11256 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
11257 | "Cannot acquire NVM for read access, err %s aq_err %s\n", |
11258 | i40e_stat_str(&pf->hw, ret), | |
11259 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
11260 | goto bw_commit_out; |
11261 | } | |
11262 | ||
11263 | /* Read word 0x10 of NVM - SW compatibility word 1 */ | |
11264 | ret = i40e_aq_read_nvm(&pf->hw, | |
11265 | I40E_SR_NVM_CONTROL_WORD, | |
11266 | 0x10, sizeof(nvm_word), &nvm_word, | |
11267 | false, NULL); | |
11268 | /* Save off last admin queue command status before releasing | |
11269 | * the NVM | |
11270 | */ | |
11271 | last_aq_status = pf->hw.aq.asq_last_status; | |
11272 | i40e_release_nvm(&pf->hw); | |
11273 | if (ret) { | |
f1c7e72e SN |
11274 | dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n", |
11275 | i40e_stat_str(&pf->hw, ret), | |
11276 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
11277 | goto bw_commit_out; |
11278 | } | |
11279 | ||
11280 | /* Wait a bit for NVM release to complete */ | |
11281 | msleep(50); | |
11282 | ||
11283 | /* Acquire NVM for write access */ | |
11284 | ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE); | |
11285 | last_aq_status = pf->hw.aq.asq_last_status; | |
11286 | if (ret) { | |
11287 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
11288 | "Cannot acquire NVM for write access, err %s aq_err %s\n", |
11289 | i40e_stat_str(&pf->hw, ret), | |
11290 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
11291 | goto bw_commit_out; |
11292 | } | |
11293 | /* Write it back out unchanged to initiate update NVM, | |
11294 | * which will force a write of the shadow (alt) RAM to | |
11295 | * the NVM - thus storing the bandwidth values permanently. | |
11296 | */ | |
11297 | ret = i40e_aq_update_nvm(&pf->hw, | |
11298 | I40E_SR_NVM_CONTROL_WORD, | |
11299 | 0x10, sizeof(nvm_word), | |
e3a5d6e6 | 11300 | &nvm_word, true, 0, NULL); |
f4492db1 GR |
11301 | /* Save off last admin queue command status before releasing |
11302 | * the NVM | |
11303 | */ | |
11304 | last_aq_status = pf->hw.aq.asq_last_status; | |
11305 | i40e_release_nvm(&pf->hw); | |
11306 | if (ret) | |
11307 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
11308 | "BW settings NOT SAVED, err %s aq_err %s\n", |
11309 | i40e_stat_str(&pf->hw, ret), | |
11310 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
11311 | bw_commit_out: |
11312 | ||
11313 | return ret; | |
11314 | } | |
11315 | ||
41c445ff JB |
11316 | /** |
11317 | * i40e_sw_init - Initialize general software structures (struct i40e_pf) | |
11318 | * @pf: board private structure to initialize | |
11319 | * | |
11320 | * i40e_sw_init initializes the Adapter private data structure. | |
11321 | * Fields are initialized based on PCI device information and | |
11322 | * OS network device settings (MTU size). | |
11323 | **/ | |
11324 | static int i40e_sw_init(struct i40e_pf *pf) | |
11325 | { | |
11326 | int err = 0; | |
11327 | int size; | |
11328 | ||
41c445ff JB |
11329 | /* Set default capability flags */ |
11330 | pf->flags = I40E_FLAG_RX_CSUM_ENABLED | | |
11331 | I40E_FLAG_MSI_ENABLED | | |
2bc7ee8a MW |
11332 | I40E_FLAG_MSIX_ENABLED; |
11333 | ||
ca99eb99 | 11334 | /* Set default ITR */ |
42702559 JK |
11335 | pf->rx_itr_default = I40E_ITR_RX_DEF; |
11336 | pf->tx_itr_default = I40E_ITR_TX_DEF; | |
ca99eb99 | 11337 | |
7134f9ce JB |
11338 | /* Depending on PF configurations, it is possible that the RSS |
11339 | * maximum might end up larger than the available queues | |
11340 | */ | |
41a1d04b | 11341 | pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width); |
acd65448 | 11342 | pf->alloc_rss_size = 1; |
5db4cb59 | 11343 | pf->rss_table_size = pf->hw.func_caps.rss_table_size; |
7134f9ce JB |
11344 | pf->rss_size_max = min_t(int, pf->rss_size_max, |
11345 | pf->hw.func_caps.num_tx_qp); | |
41c445ff JB |
11346 | if (pf->hw.func_caps.rss) { |
11347 | pf->flags |= I40E_FLAG_RSS_ENABLED; | |
acd65448 HZ |
11348 | pf->alloc_rss_size = min_t(int, pf->rss_size_max, |
11349 | num_online_cpus()); | |
41c445ff JB |
11350 | } |
11351 | ||
2050bc65 | 11352 | /* MFP mode enabled */ |
c78b953e | 11353 | if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) { |
2050bc65 CS |
11354 | pf->flags |= I40E_FLAG_MFP_ENABLED; |
11355 | dev_info(&pf->pdev->dev, "MFP mode Enabled\n"); | |
4fc8c676 | 11356 | if (i40e_get_partition_bw_setting(pf)) { |
f4492db1 | 11357 | dev_warn(&pf->pdev->dev, |
4fc8c676 SN |
11358 | "Could not get partition bw settings\n"); |
11359 | } else { | |
f4492db1 | 11360 | dev_info(&pf->pdev->dev, |
4fc8c676 SN |
11361 | "Partition BW Min = %8.8x, Max = %8.8x\n", |
11362 | pf->min_bw, pf->max_bw); | |
11363 | ||
11364 | /* nudge the Tx scheduler */ | |
11365 | i40e_set_partition_bw_setting(pf); | |
11366 | } | |
2050bc65 CS |
11367 | } |
11368 | ||
cbf61325 ASJ |
11369 | if ((pf->hw.func_caps.fd_filters_guaranteed > 0) || |
11370 | (pf->hw.func_caps.fd_filters_best_effort > 0)) { | |
11371 | pf->flags |= I40E_FLAG_FD_ATR_ENABLED; | |
11372 | pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE; | |
6eae9c6a SN |
11373 | if (pf->flags & I40E_FLAG_MFP_ENABLED && |
11374 | pf->hw.num_partitions > 1) | |
cbf61325 | 11375 | dev_info(&pf->pdev->dev, |
0b67584f | 11376 | "Flow Director Sideband mode Disabled in MFP mode\n"); |
6eae9c6a SN |
11377 | else |
11378 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
cbf61325 ASJ |
11379 | pf->fdir_pf_filter_count = |
11380 | pf->hw.func_caps.fd_filters_guaranteed; | |
11381 | pf->hw.fdir_shared_filter_count = | |
11382 | pf->hw.func_caps.fd_filters_best_effort; | |
41c445ff JB |
11383 | } |
11384 | ||
5a433199 | 11385 | if (pf->hw.mac.type == I40E_MAC_X722) { |
d36e41dc JK |
11386 | pf->hw_features |= (I40E_HW_RSS_AQ_CAPABLE | |
11387 | I40E_HW_128_QP_RSS_CAPABLE | | |
11388 | I40E_HW_ATR_EVICT_CAPABLE | | |
11389 | I40E_HW_WB_ON_ITR_CAPABLE | | |
11390 | I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE | | |
11391 | I40E_HW_NO_PCI_LINK_CHECK | | |
11392 | I40E_HW_USE_SET_LLDP_MIB | | |
11393 | I40E_HW_GENEVE_OFFLOAD_CAPABLE | | |
11394 | I40E_HW_PTP_L4_CAPABLE | | |
11395 | I40E_HW_WOL_MC_MAGIC_PKT_WAKE | | |
11396 | I40E_HW_OUTER_UDP_CSUM_CAPABLE); | |
10a955ff ASJ |
11397 | |
11398 | #define I40E_FDEVICT_PCTYPE_DEFAULT 0xc03 | |
11399 | if (rd32(&pf->hw, I40E_GLQF_FDEVICTENA(1)) != | |
11400 | I40E_FDEVICT_PCTYPE_DEFAULT) { | |
11401 | dev_warn(&pf->pdev->dev, | |
11402 | "FD EVICT PCTYPES are not right, disable FD HW EVICT\n"); | |
11403 | pf->hw_features &= ~I40E_HW_ATR_EVICT_CAPABLE; | |
11404 | } | |
5a433199 ASJ |
11405 | } else if ((pf->hw.aq.api_maj_ver > 1) || |
11406 | ((pf->hw.aq.api_maj_ver == 1) && | |
11407 | (pf->hw.aq.api_min_ver > 4))) { | |
11408 | /* Supported in FW API version higher than 1.4 */ | |
d36e41dc | 11409 | pf->hw_features |= I40E_HW_GENEVE_OFFLOAD_CAPABLE; |
5a433199 ASJ |
11410 | } |
11411 | ||
11412 | /* Enable HW ATR eviction if possible */ | |
d36e41dc | 11413 | if (pf->hw_features & I40E_HW_ATR_EVICT_CAPABLE) |
5a433199 ASJ |
11414 | pf->flags |= I40E_FLAG_HW_ATR_EVICT_ENABLED; |
11415 | ||
6de432c5 | 11416 | if ((pf->hw.mac.type == I40E_MAC_XL710) && |
8eed76fa | 11417 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) || |
f1bbad33 | 11418 | (pf->hw.aq.fw_maj_ver < 4))) { |
d36e41dc | 11419 | pf->hw_features |= I40E_HW_RESTART_AUTONEG; |
f1bbad33 | 11420 | /* No DCB support for FW < v4.33 */ |
d36e41dc | 11421 | pf->hw_features |= I40E_HW_NO_DCB_SUPPORT; |
f1bbad33 NP |
11422 | } |
11423 | ||
11424 | /* Disable FW LLDP if FW < v4.3 */ | |
6de432c5 | 11425 | if ((pf->hw.mac.type == I40E_MAC_XL710) && |
f1bbad33 NP |
11426 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) || |
11427 | (pf->hw.aq.fw_maj_ver < 4))) | |
d36e41dc | 11428 | pf->hw_features |= I40E_HW_STOP_FW_LLDP; |
f1bbad33 NP |
11429 | |
11430 | /* Use the FW Set LLDP MIB API if FW > v4.40 */ | |
6de432c5 | 11431 | if ((pf->hw.mac.type == I40E_MAC_XL710) && |
f1bbad33 NP |
11432 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) || |
11433 | (pf->hw.aq.fw_maj_ver >= 5))) | |
d36e41dc | 11434 | pf->hw_features |= I40E_HW_USE_SET_LLDP_MIB; |
8eed76fa | 11435 | |
c3d26b75 AB |
11436 | /* Enable PTP L4 if FW > v6.0 */ |
11437 | if (pf->hw.mac.type == I40E_MAC_XL710 && | |
11438 | pf->hw.aq.fw_maj_ver >= 6) | |
11439 | pf->hw_features |= I40E_HW_PTP_L4_CAPABLE; | |
11440 | ||
69399873 | 11441 | if (pf->hw.func_caps.vmdq && num_online_cpus() != 1) { |
41c445ff | 11442 | pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI; |
e25d00b8 | 11443 | pf->flags |= I40E_FLAG_VMDQ_ENABLED; |
e9e53662 | 11444 | pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf); |
41c445ff JB |
11445 | } |
11446 | ||
69399873 | 11447 | if (pf->hw.func_caps.iwarp && num_online_cpus() != 1) { |
e3219ce6 ASJ |
11448 | pf->flags |= I40E_FLAG_IWARP_ENABLED; |
11449 | /* IWARP needs one extra vector for CQP just like MISC.*/ | |
11450 | pf->num_iwarp_msix = (int)num_online_cpus() + 1; | |
11451 | } | |
5734fe87 PM |
11452 | /* Stopping FW LLDP engine is supported on XL710 and X722 |
11453 | * starting from FW versions determined in i40e_init_adminq. | |
11454 | * Stopping the FW LLDP engine is not supported on XL710 | |
11455 | * if NPAR is functioning so unset this hw flag in this case. | |
7b63435a DE |
11456 | */ |
11457 | if (pf->hw.mac.type == I40E_MAC_XL710 && | |
5734fe87 PM |
11458 | pf->hw.func_caps.npar_enable && |
11459 | (pf->hw.flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE)) | |
11460 | pf->hw.flags &= ~I40E_HW_FLAG_FW_LLDP_STOPPABLE; | |
e3219ce6 | 11461 | |
41c445ff | 11462 | #ifdef CONFIG_PCI_IOV |
ba252f13 | 11463 | if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) { |
41c445ff JB |
11464 | pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF; |
11465 | pf->flags |= I40E_FLAG_SRIOV_ENABLED; | |
11466 | pf->num_req_vfs = min_t(int, | |
11467 | pf->hw.func_caps.num_vfs, | |
11468 | I40E_MAX_VF_COUNT); | |
11469 | } | |
11470 | #endif /* CONFIG_PCI_IOV */ | |
11471 | pf->eeprom_version = 0xDEAD; | |
11472 | pf->lan_veb = I40E_NO_VEB; | |
11473 | pf->lan_vsi = I40E_NO_VSI; | |
11474 | ||
d1a8d275 ASJ |
11475 | /* By default FW has this off for performance reasons */ |
11476 | pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED; | |
11477 | ||
41c445ff JB |
11478 | /* set up queue assignment tracking */ |
11479 | size = sizeof(struct i40e_lump_tracking) | |
11480 | + (sizeof(u16) * pf->hw.func_caps.num_tx_qp); | |
11481 | pf->qp_pile = kzalloc(size, GFP_KERNEL); | |
11482 | if (!pf->qp_pile) { | |
11483 | err = -ENOMEM; | |
11484 | goto sw_init_done; | |
11485 | } | |
11486 | pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp; | |
11487 | pf->qp_pile->search_hint = 0; | |
11488 | ||
327fe04b ASJ |
11489 | pf->tx_timeout_recovery_level = 1; |
11490 | ||
41c445ff JB |
11491 | mutex_init(&pf->switch_mutex); |
11492 | ||
11493 | sw_init_done: | |
11494 | return err; | |
11495 | } | |
11496 | ||
7c3c288b ASJ |
11497 | /** |
11498 | * i40e_set_ntuple - set the ntuple feature flag and take action | |
11499 | * @pf: board private structure to initialize | |
11500 | * @features: the feature set that the stack is suggesting | |
11501 | * | |
11502 | * returns a bool to indicate if reset needs to happen | |
11503 | **/ | |
11504 | bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features) | |
11505 | { | |
11506 | bool need_reset = false; | |
11507 | ||
11508 | /* Check if Flow Director n-tuple support was enabled or disabled. If | |
11509 | * the state changed, we need to reset. | |
11510 | */ | |
11511 | if (features & NETIF_F_NTUPLE) { | |
11512 | /* Enable filters and mark for reset */ | |
11513 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) | |
11514 | need_reset = true; | |
2f4b411a AN |
11515 | /* enable FD_SB only if there is MSI-X vector and no cloud |
11516 | * filters exist | |
11517 | */ | |
11518 | if (pf->num_fdsb_msix > 0 && !pf->num_cloud_filters) { | |
a70e407f | 11519 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; |
2f4b411a AN |
11520 | pf->flags &= ~I40E_FLAG_FD_SB_INACTIVE; |
11521 | } | |
7c3c288b ASJ |
11522 | } else { |
11523 | /* turn off filters, mark for reset and clear SW filter list */ | |
11524 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
11525 | need_reset = true; | |
11526 | i40e_fdir_filter_exit(pf); | |
11527 | } | |
134201ae JK |
11528 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; |
11529 | clear_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state); | |
2f4b411a AN |
11530 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
11531 | ||
1e1be8f6 | 11532 | /* reset fd counters */ |
097dbf52 JK |
11533 | pf->fd_add_err = 0; |
11534 | pf->fd_atr_cnt = 0; | |
8a4f34fb | 11535 | /* if ATR was auto disabled it can be re-enabled. */ |
134201ae | 11536 | if (test_and_clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) |
47994c11 JK |
11537 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && |
11538 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
234dc4e6 | 11539 | dev_info(&pf->pdev->dev, "ATR re-enabled.\n"); |
7c3c288b ASJ |
11540 | } |
11541 | return need_reset; | |
11542 | } | |
11543 | ||
d8ec9864 AB |
11544 | /** |
11545 | * i40e_clear_rss_lut - clear the rx hash lookup table | |
11546 | * @vsi: the VSI being configured | |
11547 | **/ | |
11548 | static void i40e_clear_rss_lut(struct i40e_vsi *vsi) | |
11549 | { | |
11550 | struct i40e_pf *pf = vsi->back; | |
11551 | struct i40e_hw *hw = &pf->hw; | |
11552 | u16 vf_id = vsi->vf_id; | |
11553 | u8 i; | |
11554 | ||
11555 | if (vsi->type == I40E_VSI_MAIN) { | |
11556 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
11557 | wr32(hw, I40E_PFQF_HLUT(i), 0); | |
11558 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
11559 | for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) | |
11560 | i40e_write_rx_ctl(hw, I40E_VFQF_HLUT1(i, vf_id), 0); | |
11561 | } else { | |
11562 | dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n"); | |
11563 | } | |
11564 | } | |
11565 | ||
41c445ff JB |
11566 | /** |
11567 | * i40e_set_features - set the netdev feature flags | |
11568 | * @netdev: ptr to the netdev being adjusted | |
11569 | * @features: the feature set that the stack is suggesting | |
373149fc | 11570 | * Note: expects to be called while under rtnl_lock() |
41c445ff JB |
11571 | **/ |
11572 | static int i40e_set_features(struct net_device *netdev, | |
11573 | netdev_features_t features) | |
11574 | { | |
11575 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
11576 | struct i40e_vsi *vsi = np->vsi; | |
7c3c288b ASJ |
11577 | struct i40e_pf *pf = vsi->back; |
11578 | bool need_reset; | |
41c445ff | 11579 | |
d8ec9864 AB |
11580 | if (features & NETIF_F_RXHASH && !(netdev->features & NETIF_F_RXHASH)) |
11581 | i40e_pf_config_rss(pf); | |
11582 | else if (!(features & NETIF_F_RXHASH) && | |
11583 | netdev->features & NETIF_F_RXHASH) | |
11584 | i40e_clear_rss_lut(vsi); | |
11585 | ||
41c445ff JB |
11586 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
11587 | i40e_vlan_stripping_enable(vsi); | |
11588 | else | |
11589 | i40e_vlan_stripping_disable(vsi); | |
11590 | ||
2f4b411a AN |
11591 | if (!(features & NETIF_F_HW_TC) && pf->num_cloud_filters) { |
11592 | dev_err(&pf->pdev->dev, | |
11593 | "Offloaded tc filters active, can't turn hw_tc_offload off"); | |
11594 | return -EINVAL; | |
11595 | } | |
11596 | ||
7c3c288b ASJ |
11597 | need_reset = i40e_set_ntuple(pf, features); |
11598 | ||
11599 | if (need_reset) | |
ff424188 | 11600 | i40e_do_reset(pf, I40E_PF_RESET_FLAG, true); |
7c3c288b | 11601 | |
41c445ff JB |
11602 | return 0; |
11603 | } | |
11604 | ||
a1c9a9d9 | 11605 | /** |
6a899024 | 11606 | * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port |
a1c9a9d9 JK |
11607 | * @pf: board private structure |
11608 | * @port: The UDP port to look up | |
11609 | * | |
11610 | * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found | |
11611 | **/ | |
fe0b0cd9 | 11612 | static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, u16 port) |
a1c9a9d9 JK |
11613 | { |
11614 | u8 i; | |
11615 | ||
11616 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { | |
5305d0fe AD |
11617 | /* Do not report ports with pending deletions as |
11618 | * being available. | |
11619 | */ | |
11620 | if (!port && (pf->pending_udp_bitmap & BIT_ULL(i))) | |
11621 | continue; | |
27826fd5 | 11622 | if (pf->udp_ports[i].port == port) |
a1c9a9d9 JK |
11623 | return i; |
11624 | } | |
11625 | ||
11626 | return i; | |
11627 | } | |
11628 | ||
11629 | /** | |
06a5f7f1 | 11630 | * i40e_udp_tunnel_add - Get notifications about UDP tunnel ports that come up |
a1c9a9d9 | 11631 | * @netdev: This physical port's netdev |
06a5f7f1 | 11632 | * @ti: Tunnel endpoint information |
a1c9a9d9 | 11633 | **/ |
06a5f7f1 AD |
11634 | static void i40e_udp_tunnel_add(struct net_device *netdev, |
11635 | struct udp_tunnel_info *ti) | |
a1c9a9d9 JK |
11636 | { |
11637 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
11638 | struct i40e_vsi *vsi = np->vsi; | |
11639 | struct i40e_pf *pf = vsi->back; | |
fe0b0cd9 | 11640 | u16 port = ntohs(ti->port); |
a1c9a9d9 JK |
11641 | u8 next_idx; |
11642 | u8 idx; | |
11643 | ||
6a899024 | 11644 | idx = i40e_get_udp_port_idx(pf, port); |
a1c9a9d9 JK |
11645 | |
11646 | /* Check if port already exists */ | |
11647 | if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) { | |
fe0b0cd9 | 11648 | netdev_info(netdev, "port %d already offloaded\n", port); |
a1c9a9d9 JK |
11649 | return; |
11650 | } | |
11651 | ||
11652 | /* Now check if there is space to add the new port */ | |
6a899024 | 11653 | next_idx = i40e_get_udp_port_idx(pf, 0); |
a1c9a9d9 JK |
11654 | |
11655 | if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) { | |
06a5f7f1 | 11656 | netdev_info(netdev, "maximum number of offloaded UDP ports reached, not adding port %d\n", |
fe0b0cd9 | 11657 | port); |
6a899024 SA |
11658 | return; |
11659 | } | |
11660 | ||
06a5f7f1 AD |
11661 | switch (ti->type) { |
11662 | case UDP_TUNNEL_TYPE_VXLAN: | |
11663 | pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN; | |
11664 | break; | |
11665 | case UDP_TUNNEL_TYPE_GENEVE: | |
d36e41dc | 11666 | if (!(pf->hw_features & I40E_HW_GENEVE_OFFLOAD_CAPABLE)) |
06a5f7f1 AD |
11667 | return; |
11668 | pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE; | |
11669 | break; | |
11670 | default: | |
6a899024 SA |
11671 | return; |
11672 | } | |
11673 | ||
11674 | /* New port: add it and mark its index in the bitmap */ | |
27826fd5 | 11675 | pf->udp_ports[next_idx].port = port; |
5305d0fe | 11676 | pf->udp_ports[next_idx].filter_index = I40E_UDP_PORT_INDEX_UNUSED; |
6a899024 | 11677 | pf->pending_udp_bitmap |= BIT_ULL(next_idx); |
41898c66 | 11678 | set_bit(__I40E_UDP_FILTER_SYNC_PENDING, pf->state); |
a1c9a9d9 JK |
11679 | } |
11680 | ||
6a899024 | 11681 | /** |
06a5f7f1 | 11682 | * i40e_udp_tunnel_del - Get notifications about UDP tunnel ports that go away |
6a899024 | 11683 | * @netdev: This physical port's netdev |
06a5f7f1 | 11684 | * @ti: Tunnel endpoint information |
6a899024 | 11685 | **/ |
06a5f7f1 AD |
11686 | static void i40e_udp_tunnel_del(struct net_device *netdev, |
11687 | struct udp_tunnel_info *ti) | |
6a899024 | 11688 | { |
6a899024 SA |
11689 | struct i40e_netdev_priv *np = netdev_priv(netdev); |
11690 | struct i40e_vsi *vsi = np->vsi; | |
11691 | struct i40e_pf *pf = vsi->back; | |
fe0b0cd9 | 11692 | u16 port = ntohs(ti->port); |
6a899024 SA |
11693 | u8 idx; |
11694 | ||
6a899024 SA |
11695 | idx = i40e_get_udp_port_idx(pf, port); |
11696 | ||
11697 | /* Check if port already exists */ | |
06a5f7f1 AD |
11698 | if (idx >= I40E_MAX_PF_UDP_OFFLOAD_PORTS) |
11699 | goto not_found; | |
6a899024 | 11700 | |
06a5f7f1 AD |
11701 | switch (ti->type) { |
11702 | case UDP_TUNNEL_TYPE_VXLAN: | |
11703 | if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_VXLAN) | |
11704 | goto not_found; | |
11705 | break; | |
11706 | case UDP_TUNNEL_TYPE_GENEVE: | |
11707 | if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_NGE) | |
11708 | goto not_found; | |
11709 | break; | |
11710 | default: | |
11711 | goto not_found; | |
6a899024 | 11712 | } |
06a5f7f1 AD |
11713 | |
11714 | /* if port exists, set it to 0 (mark for deletion) | |
11715 | * and make it pending | |
11716 | */ | |
27826fd5 | 11717 | pf->udp_ports[idx].port = 0; |
5305d0fe AD |
11718 | |
11719 | /* Toggle pending bit instead of setting it. This way if we are | |
11720 | * deleting a port that has yet to be added we just clear the pending | |
11721 | * bit and don't have to worry about it. | |
11722 | */ | |
11723 | pf->pending_udp_bitmap ^= BIT_ULL(idx); | |
41898c66 | 11724 | set_bit(__I40E_UDP_FILTER_SYNC_PENDING, pf->state); |
06a5f7f1 AD |
11725 | |
11726 | return; | |
11727 | not_found: | |
11728 | netdev_warn(netdev, "UDP port %d was not found, not deleting\n", | |
fe0b0cd9 | 11729 | port); |
6a899024 SA |
11730 | } |
11731 | ||
1f224ad2 | 11732 | static int i40e_get_phys_port_id(struct net_device *netdev, |
02637fce | 11733 | struct netdev_phys_item_id *ppid) |
1f224ad2 NP |
11734 | { |
11735 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
11736 | struct i40e_pf *pf = np->vsi->back; | |
11737 | struct i40e_hw *hw = &pf->hw; | |
11738 | ||
d36e41dc | 11739 | if (!(pf->hw_features & I40E_HW_PORT_ID_VALID)) |
1f224ad2 NP |
11740 | return -EOPNOTSUPP; |
11741 | ||
11742 | ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id)); | |
11743 | memcpy(ppid->id, hw->mac.port_addr, ppid->id_len); | |
11744 | ||
11745 | return 0; | |
11746 | } | |
11747 | ||
2f90ade6 JB |
11748 | /** |
11749 | * i40e_ndo_fdb_add - add an entry to the hardware database | |
11750 | * @ndm: the input from the stack | |
11751 | * @tb: pointer to array of nladdr (unused) | |
11752 | * @dev: the net device pointer | |
11753 | * @addr: the MAC address entry being added | |
f5254429 | 11754 | * @vid: VLAN ID |
2f90ade6 JB |
11755 | * @flags: instructions from stack about fdb operation |
11756 | */ | |
4ba0dea5 GR |
11757 | static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], |
11758 | struct net_device *dev, | |
f6f6424b | 11759 | const unsigned char *addr, u16 vid, |
87b0984e PM |
11760 | u16 flags, |
11761 | struct netlink_ext_ack *extack) | |
4ba0dea5 GR |
11762 | { |
11763 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
11764 | struct i40e_pf *pf = np->vsi->back; | |
11765 | int err = 0; | |
11766 | ||
11767 | if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED)) | |
11768 | return -EOPNOTSUPP; | |
11769 | ||
65891fea OG |
11770 | if (vid) { |
11771 | pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name); | |
11772 | return -EINVAL; | |
11773 | } | |
11774 | ||
4ba0dea5 GR |
11775 | /* Hardware does not support aging addresses so if a |
11776 | * ndm_state is given only allow permanent addresses | |
11777 | */ | |
11778 | if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) { | |
11779 | netdev_info(dev, "FDB only supports static addresses\n"); | |
11780 | return -EINVAL; | |
11781 | } | |
11782 | ||
11783 | if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) | |
11784 | err = dev_uc_add_excl(dev, addr); | |
11785 | else if (is_multicast_ether_addr(addr)) | |
11786 | err = dev_mc_add_excl(dev, addr); | |
11787 | else | |
11788 | err = -EINVAL; | |
11789 | ||
11790 | /* Only return duplicate errors if NLM_F_EXCL is set */ | |
11791 | if (err == -EEXIST && !(flags & NLM_F_EXCL)) | |
11792 | err = 0; | |
11793 | ||
11794 | return err; | |
11795 | } | |
11796 | ||
51616018 NP |
11797 | /** |
11798 | * i40e_ndo_bridge_setlink - Set the hardware bridge mode | |
11799 | * @dev: the netdev being configured | |
11800 | * @nlh: RTNL message | |
f5254429 | 11801 | * @flags: bridge flags |
2fd527b7 | 11802 | * @extack: netlink extended ack |
51616018 NP |
11803 | * |
11804 | * Inserts a new hardware bridge if not already created and | |
11805 | * enables the bridging mode requested (VEB or VEPA). If the | |
11806 | * hardware bridge has already been inserted and the request | |
11807 | * is to change the mode then that requires a PF reset to | |
11808 | * allow rebuild of the components with required hardware | |
11809 | * bridge mode enabled. | |
373149fc MS |
11810 | * |
11811 | * Note: expects to be called while under rtnl_lock() | |
51616018 NP |
11812 | **/ |
11813 | static int i40e_ndo_bridge_setlink(struct net_device *dev, | |
9df70b66 | 11814 | struct nlmsghdr *nlh, |
2fd527b7 PM |
11815 | u16 flags, |
11816 | struct netlink_ext_ack *extack) | |
51616018 NP |
11817 | { |
11818 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
11819 | struct i40e_vsi *vsi = np->vsi; | |
11820 | struct i40e_pf *pf = vsi->back; | |
11821 | struct i40e_veb *veb = NULL; | |
11822 | struct nlattr *attr, *br_spec; | |
11823 | int i, rem; | |
11824 | ||
11825 | /* Only for PF VSI for now */ | |
11826 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) | |
11827 | return -EOPNOTSUPP; | |
11828 | ||
11829 | /* Find the HW bridge for PF VSI */ | |
11830 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { | |
11831 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
11832 | veb = pf->veb[i]; | |
11833 | } | |
11834 | ||
11835 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
11836 | ||
11837 | nla_for_each_nested(attr, br_spec, rem) { | |
11838 | __u16 mode; | |
11839 | ||
11840 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
11841 | continue; | |
11842 | ||
11843 | mode = nla_get_u16(attr); | |
11844 | if ((mode != BRIDGE_MODE_VEPA) && | |
11845 | (mode != BRIDGE_MODE_VEB)) | |
11846 | return -EINVAL; | |
11847 | ||
11848 | /* Insert a new HW bridge */ | |
11849 | if (!veb) { | |
11850 | veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, | |
11851 | vsi->tc_config.enabled_tc); | |
11852 | if (veb) { | |
11853 | veb->bridge_mode = mode; | |
11854 | i40e_config_bridge_mode(veb); | |
11855 | } else { | |
11856 | /* No Bridge HW offload available */ | |
11857 | return -ENOENT; | |
11858 | } | |
11859 | break; | |
11860 | } else if (mode != veb->bridge_mode) { | |
11861 | /* Existing HW bridge but different mode needs reset */ | |
11862 | veb->bridge_mode = mode; | |
fc60861e ASJ |
11863 | /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */ |
11864 | if (mode == BRIDGE_MODE_VEB) | |
11865 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
11866 | else | |
11867 | pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; | |
ff424188 | 11868 | i40e_do_reset(pf, I40E_PF_RESET_FLAG, true); |
51616018 NP |
11869 | break; |
11870 | } | |
11871 | } | |
11872 | ||
11873 | return 0; | |
11874 | } | |
11875 | ||
11876 | /** | |
11877 | * i40e_ndo_bridge_getlink - Get the hardware bridge mode | |
11878 | * @skb: skb buff | |
11879 | * @pid: process id | |
11880 | * @seq: RTNL message seq # | |
11881 | * @dev: the netdev being configured | |
11882 | * @filter_mask: unused | |
d4b2f9fe | 11883 | * @nlflags: netlink flags passed in |
51616018 NP |
11884 | * |
11885 | * Return the mode in which the hardware bridge is operating in | |
11886 | * i.e VEB or VEPA. | |
11887 | **/ | |
51616018 NP |
11888 | static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, |
11889 | struct net_device *dev, | |
9f4ffc44 CW |
11890 | u32 __always_unused filter_mask, |
11891 | int nlflags) | |
51616018 NP |
11892 | { |
11893 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
11894 | struct i40e_vsi *vsi = np->vsi; | |
11895 | struct i40e_pf *pf = vsi->back; | |
11896 | struct i40e_veb *veb = NULL; | |
11897 | int i; | |
11898 | ||
11899 | /* Only for PF VSI for now */ | |
11900 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) | |
11901 | return -EOPNOTSUPP; | |
11902 | ||
11903 | /* Find the HW bridge for the PF VSI */ | |
11904 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { | |
11905 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
11906 | veb = pf->veb[i]; | |
11907 | } | |
11908 | ||
11909 | if (!veb) | |
11910 | return 0; | |
11911 | ||
46c264da | 11912 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode, |
599b076d | 11913 | 0, 0, nlflags, filter_mask, NULL); |
51616018 | 11914 | } |
51616018 | 11915 | |
f44a75e2 JS |
11916 | /** |
11917 | * i40e_features_check - Validate encapsulated packet conforms to limits | |
11918 | * @skb: skb buff | |
2bc11c63 | 11919 | * @dev: This physical port's netdev |
f44a75e2 JS |
11920 | * @features: Offload features that the stack believes apply |
11921 | **/ | |
11922 | static netdev_features_t i40e_features_check(struct sk_buff *skb, | |
11923 | struct net_device *dev, | |
11924 | netdev_features_t features) | |
11925 | { | |
f114dca2 AD |
11926 | size_t len; |
11927 | ||
11928 | /* No point in doing any of this if neither checksum nor GSO are | |
11929 | * being requested for this frame. We can rule out both by just | |
11930 | * checking for CHECKSUM_PARTIAL | |
11931 | */ | |
11932 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
11933 | return features; | |
11934 | ||
11935 | /* We cannot support GSO if the MSS is going to be less than | |
11936 | * 64 bytes. If it is then we need to drop support for GSO. | |
11937 | */ | |
11938 | if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_size < 64)) | |
11939 | features &= ~NETIF_F_GSO_MASK; | |
11940 | ||
11941 | /* MACLEN can support at most 63 words */ | |
11942 | len = skb_network_header(skb) - skb->data; | |
11943 | if (len & ~(63 * 2)) | |
11944 | goto out_err; | |
11945 | ||
11946 | /* IPLEN and EIPLEN can support at most 127 dwords */ | |
11947 | len = skb_transport_header(skb) - skb_network_header(skb); | |
11948 | if (len & ~(127 * 4)) | |
11949 | goto out_err; | |
11950 | ||
11951 | if (skb->encapsulation) { | |
11952 | /* L4TUNLEN can support 127 words */ | |
11953 | len = skb_inner_network_header(skb) - skb_transport_header(skb); | |
11954 | if (len & ~(127 * 2)) | |
11955 | goto out_err; | |
11956 | ||
11957 | /* IPLEN can support at most 127 dwords */ | |
11958 | len = skb_inner_transport_header(skb) - | |
11959 | skb_inner_network_header(skb); | |
11960 | if (len & ~(127 * 4)) | |
11961 | goto out_err; | |
11962 | } | |
11963 | ||
11964 | /* No need to validate L4LEN as TCP is the only protocol with a | |
11965 | * a flexible value and we support all possible values supported | |
11966 | * by TCP, which is at most 15 dwords | |
11967 | */ | |
f44a75e2 JS |
11968 | |
11969 | return features; | |
f114dca2 AD |
11970 | out_err: |
11971 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
f44a75e2 JS |
11972 | } |
11973 | ||
0c8493d9 BT |
11974 | /** |
11975 | * i40e_xdp_setup - add/remove an XDP program | |
11976 | * @vsi: VSI to changed | |
11977 | * @prog: XDP program | |
11978 | **/ | |
11979 | static int i40e_xdp_setup(struct i40e_vsi *vsi, | |
11980 | struct bpf_prog *prog) | |
11981 | { | |
11982 | int frame_size = vsi->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
11983 | struct i40e_pf *pf = vsi->back; | |
11984 | struct bpf_prog *old_prog; | |
11985 | bool need_reset; | |
11986 | int i; | |
11987 | ||
11988 | /* Don't allow frames that span over multiple buffers */ | |
11989 | if (frame_size > vsi->rx_buf_len) | |
11990 | return -EINVAL; | |
11991 | ||
11992 | if (!i40e_enabled_xdp_vsi(vsi) && !prog) | |
11993 | return 0; | |
11994 | ||
11995 | /* When turning XDP on->off/off->on we reset and rebuild the rings. */ | |
11996 | need_reset = (i40e_enabled_xdp_vsi(vsi) != !!prog); | |
11997 | ||
11998 | if (need_reset) | |
11999 | i40e_prep_for_reset(pf, true); | |
12000 | ||
12001 | old_prog = xchg(&vsi->xdp_prog, prog); | |
12002 | ||
12003 | if (need_reset) | |
12004 | i40e_reset_and_rebuild(pf, true, true); | |
12005 | ||
12006 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
12007 | WRITE_ONCE(vsi->rx_rings[i]->xdp_prog, vsi->xdp_prog); | |
12008 | ||
12009 | if (old_prog) | |
12010 | bpf_prog_put(old_prog); | |
12011 | ||
14ffeb52 MK |
12012 | /* Kick start the NAPI context if there is an AF_XDP socket open |
12013 | * on that queue id. This so that receiving will start. | |
12014 | */ | |
12015 | if (need_reset && prog) | |
12016 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
12017 | if (vsi->xdp_rings[i]->xsk_umem) | |
12018 | (void)i40e_xsk_async_xmit(vsi->netdev, i); | |
12019 | ||
0c8493d9 BT |
12020 | return 0; |
12021 | } | |
12022 | ||
123cecd4 BT |
12023 | /** |
12024 | * i40e_enter_busy_conf - Enters busy config state | |
12025 | * @vsi: vsi | |
12026 | * | |
12027 | * Returns 0 on success, <0 for failure. | |
12028 | **/ | |
12029 | static int i40e_enter_busy_conf(struct i40e_vsi *vsi) | |
12030 | { | |
12031 | struct i40e_pf *pf = vsi->back; | |
12032 | int timeout = 50; | |
12033 | ||
12034 | while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) { | |
12035 | timeout--; | |
12036 | if (!timeout) | |
12037 | return -EBUSY; | |
12038 | usleep_range(1000, 2000); | |
12039 | } | |
12040 | ||
12041 | return 0; | |
12042 | } | |
12043 | ||
12044 | /** | |
12045 | * i40e_exit_busy_conf - Exits busy config state | |
12046 | * @vsi: vsi | |
12047 | **/ | |
12048 | static void i40e_exit_busy_conf(struct i40e_vsi *vsi) | |
12049 | { | |
12050 | struct i40e_pf *pf = vsi->back; | |
12051 | ||
12052 | clear_bit(__I40E_CONFIG_BUSY, pf->state); | |
12053 | } | |
12054 | ||
12055 | /** | |
12056 | * i40e_queue_pair_reset_stats - Resets all statistics for a queue pair | |
12057 | * @vsi: vsi | |
12058 | * @queue_pair: queue pair | |
12059 | **/ | |
12060 | static void i40e_queue_pair_reset_stats(struct i40e_vsi *vsi, int queue_pair) | |
12061 | { | |
12062 | memset(&vsi->rx_rings[queue_pair]->rx_stats, 0, | |
12063 | sizeof(vsi->rx_rings[queue_pair]->rx_stats)); | |
12064 | memset(&vsi->tx_rings[queue_pair]->stats, 0, | |
12065 | sizeof(vsi->tx_rings[queue_pair]->stats)); | |
12066 | if (i40e_enabled_xdp_vsi(vsi)) { | |
12067 | memset(&vsi->xdp_rings[queue_pair]->stats, 0, | |
12068 | sizeof(vsi->xdp_rings[queue_pair]->stats)); | |
12069 | } | |
12070 | } | |
12071 | ||
12072 | /** | |
12073 | * i40e_queue_pair_clean_rings - Cleans all the rings of a queue pair | |
12074 | * @vsi: vsi | |
12075 | * @queue_pair: queue pair | |
12076 | **/ | |
12077 | static void i40e_queue_pair_clean_rings(struct i40e_vsi *vsi, int queue_pair) | |
12078 | { | |
12079 | i40e_clean_tx_ring(vsi->tx_rings[queue_pair]); | |
59eb2a88 BT |
12080 | if (i40e_enabled_xdp_vsi(vsi)) { |
12081 | /* Make sure that in-progress ndo_xdp_xmit calls are | |
12082 | * completed. | |
12083 | */ | |
12084 | synchronize_rcu(); | |
123cecd4 | 12085 | i40e_clean_tx_ring(vsi->xdp_rings[queue_pair]); |
59eb2a88 | 12086 | } |
123cecd4 BT |
12087 | i40e_clean_rx_ring(vsi->rx_rings[queue_pair]); |
12088 | } | |
12089 | ||
12090 | /** | |
12091 | * i40e_queue_pair_toggle_napi - Enables/disables NAPI for a queue pair | |
12092 | * @vsi: vsi | |
12093 | * @queue_pair: queue pair | |
12094 | * @enable: true for enable, false for disable | |
12095 | **/ | |
12096 | static void i40e_queue_pair_toggle_napi(struct i40e_vsi *vsi, int queue_pair, | |
12097 | bool enable) | |
12098 | { | |
12099 | struct i40e_ring *rxr = vsi->rx_rings[queue_pair]; | |
12100 | struct i40e_q_vector *q_vector = rxr->q_vector; | |
12101 | ||
12102 | if (!vsi->netdev) | |
12103 | return; | |
12104 | ||
12105 | /* All rings in a qp belong to the same qvector. */ | |
12106 | if (q_vector->rx.ring || q_vector->tx.ring) { | |
12107 | if (enable) | |
12108 | napi_enable(&q_vector->napi); | |
12109 | else | |
12110 | napi_disable(&q_vector->napi); | |
12111 | } | |
12112 | } | |
12113 | ||
12114 | /** | |
12115 | * i40e_queue_pair_toggle_rings - Enables/disables all rings for a queue pair | |
12116 | * @vsi: vsi | |
12117 | * @queue_pair: queue pair | |
12118 | * @enable: true for enable, false for disable | |
12119 | * | |
12120 | * Returns 0 on success, <0 on failure. | |
12121 | **/ | |
12122 | static int i40e_queue_pair_toggle_rings(struct i40e_vsi *vsi, int queue_pair, | |
12123 | bool enable) | |
12124 | { | |
12125 | struct i40e_pf *pf = vsi->back; | |
12126 | int pf_q, ret = 0; | |
12127 | ||
12128 | pf_q = vsi->base_queue + queue_pair; | |
12129 | ret = i40e_control_wait_tx_q(vsi->seid, pf, pf_q, | |
12130 | false /*is xdp*/, enable); | |
12131 | if (ret) { | |
12132 | dev_info(&pf->pdev->dev, | |
12133 | "VSI seid %d Tx ring %d %sable timeout\n", | |
12134 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
12135 | return ret; | |
12136 | } | |
12137 | ||
12138 | i40e_control_rx_q(pf, pf_q, enable); | |
12139 | ret = i40e_pf_rxq_wait(pf, pf_q, enable); | |
12140 | if (ret) { | |
12141 | dev_info(&pf->pdev->dev, | |
12142 | "VSI seid %d Rx ring %d %sable timeout\n", | |
12143 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
12144 | return ret; | |
12145 | } | |
12146 | ||
12147 | /* Due to HW errata, on Rx disable only, the register can | |
12148 | * indicate done before it really is. Needs 50ms to be sure | |
12149 | */ | |
12150 | if (!enable) | |
12151 | mdelay(50); | |
12152 | ||
12153 | if (!i40e_enabled_xdp_vsi(vsi)) | |
12154 | return ret; | |
12155 | ||
12156 | ret = i40e_control_wait_tx_q(vsi->seid, pf, | |
12157 | pf_q + vsi->alloc_queue_pairs, | |
12158 | true /*is xdp*/, enable); | |
12159 | if (ret) { | |
12160 | dev_info(&pf->pdev->dev, | |
12161 | "VSI seid %d XDP Tx ring %d %sable timeout\n", | |
12162 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
12163 | } | |
12164 | ||
12165 | return ret; | |
12166 | } | |
12167 | ||
12168 | /** | |
12169 | * i40e_queue_pair_enable_irq - Enables interrupts for a queue pair | |
12170 | * @vsi: vsi | |
12171 | * @queue_pair: queue_pair | |
12172 | **/ | |
12173 | static void i40e_queue_pair_enable_irq(struct i40e_vsi *vsi, int queue_pair) | |
12174 | { | |
12175 | struct i40e_ring *rxr = vsi->rx_rings[queue_pair]; | |
12176 | struct i40e_pf *pf = vsi->back; | |
12177 | struct i40e_hw *hw = &pf->hw; | |
12178 | ||
12179 | /* All rings in a qp belong to the same qvector. */ | |
12180 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
12181 | i40e_irq_dynamic_enable(vsi, rxr->q_vector->v_idx); | |
12182 | else | |
12183 | i40e_irq_dynamic_enable_icr0(pf); | |
12184 | ||
12185 | i40e_flush(hw); | |
12186 | } | |
12187 | ||
12188 | /** | |
12189 | * i40e_queue_pair_disable_irq - Disables interrupts for a queue pair | |
12190 | * @vsi: vsi | |
12191 | * @queue_pair: queue_pair | |
12192 | **/ | |
12193 | static void i40e_queue_pair_disable_irq(struct i40e_vsi *vsi, int queue_pair) | |
12194 | { | |
12195 | struct i40e_ring *rxr = vsi->rx_rings[queue_pair]; | |
12196 | struct i40e_pf *pf = vsi->back; | |
12197 | struct i40e_hw *hw = &pf->hw; | |
12198 | ||
12199 | /* For simplicity, instead of removing the qp interrupt causes | |
12200 | * from the interrupt linked list, we simply disable the interrupt, and | |
12201 | * leave the list intact. | |
12202 | * | |
12203 | * All rings in a qp belong to the same qvector. | |
12204 | */ | |
12205 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
12206 | u32 intpf = vsi->base_vector + rxr->q_vector->v_idx; | |
12207 | ||
12208 | wr32(hw, I40E_PFINT_DYN_CTLN(intpf - 1), 0); | |
12209 | i40e_flush(hw); | |
12210 | synchronize_irq(pf->msix_entries[intpf].vector); | |
12211 | } else { | |
12212 | /* Legacy and MSI mode - this stops all interrupt handling */ | |
12213 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); | |
12214 | wr32(hw, I40E_PFINT_DYN_CTL0, 0); | |
12215 | i40e_flush(hw); | |
12216 | synchronize_irq(pf->pdev->irq); | |
12217 | } | |
12218 | } | |
12219 | ||
12220 | /** | |
12221 | * i40e_queue_pair_disable - Disables a queue pair | |
12222 | * @vsi: vsi | |
12223 | * @queue_pair: queue pair | |
12224 | * | |
12225 | * Returns 0 on success, <0 on failure. | |
12226 | **/ | |
12227 | int i40e_queue_pair_disable(struct i40e_vsi *vsi, int queue_pair) | |
12228 | { | |
12229 | int err; | |
12230 | ||
12231 | err = i40e_enter_busy_conf(vsi); | |
12232 | if (err) | |
12233 | return err; | |
12234 | ||
12235 | i40e_queue_pair_disable_irq(vsi, queue_pair); | |
12236 | err = i40e_queue_pair_toggle_rings(vsi, queue_pair, false /* off */); | |
12237 | i40e_queue_pair_toggle_napi(vsi, queue_pair, false /* off */); | |
12238 | i40e_queue_pair_clean_rings(vsi, queue_pair); | |
12239 | i40e_queue_pair_reset_stats(vsi, queue_pair); | |
12240 | ||
12241 | return err; | |
12242 | } | |
12243 | ||
12244 | /** | |
12245 | * i40e_queue_pair_enable - Enables a queue pair | |
12246 | * @vsi: vsi | |
12247 | * @queue_pair: queue pair | |
12248 | * | |
12249 | * Returns 0 on success, <0 on failure. | |
12250 | **/ | |
12251 | int i40e_queue_pair_enable(struct i40e_vsi *vsi, int queue_pair) | |
12252 | { | |
12253 | int err; | |
12254 | ||
12255 | err = i40e_configure_tx_ring(vsi->tx_rings[queue_pair]); | |
12256 | if (err) | |
12257 | return err; | |
12258 | ||
12259 | if (i40e_enabled_xdp_vsi(vsi)) { | |
12260 | err = i40e_configure_tx_ring(vsi->xdp_rings[queue_pair]); | |
12261 | if (err) | |
12262 | return err; | |
12263 | } | |
12264 | ||
12265 | err = i40e_configure_rx_ring(vsi->rx_rings[queue_pair]); | |
12266 | if (err) | |
12267 | return err; | |
12268 | ||
12269 | err = i40e_queue_pair_toggle_rings(vsi, queue_pair, true /* on */); | |
12270 | i40e_queue_pair_toggle_napi(vsi, queue_pair, true /* on */); | |
12271 | i40e_queue_pair_enable_irq(vsi, queue_pair); | |
12272 | ||
12273 | i40e_exit_busy_conf(vsi); | |
12274 | ||
12275 | return err; | |
12276 | } | |
12277 | ||
0c8493d9 | 12278 | /** |
f4e63525 | 12279 | * i40e_xdp - implements ndo_bpf for i40e |
0c8493d9 BT |
12280 | * @dev: netdevice |
12281 | * @xdp: XDP command | |
12282 | **/ | |
12283 | static int i40e_xdp(struct net_device *dev, | |
f4e63525 | 12284 | struct netdev_bpf *xdp) |
0c8493d9 BT |
12285 | { |
12286 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
12287 | struct i40e_vsi *vsi = np->vsi; | |
12288 | ||
12289 | if (vsi->type != I40E_VSI_MAIN) | |
12290 | return -EINVAL; | |
12291 | ||
12292 | switch (xdp->command) { | |
12293 | case XDP_SETUP_PROG: | |
12294 | return i40e_xdp_setup(vsi, xdp->prog); | |
12295 | case XDP_QUERY_PROG: | |
eb23039f | 12296 | xdp->prog_id = vsi->xdp_prog ? vsi->xdp_prog->aux->id : 0; |
0c8493d9 | 12297 | return 0; |
0a714186 BT |
12298 | case XDP_SETUP_XSK_UMEM: |
12299 | return i40e_xsk_umem_setup(vsi, xdp->xsk.umem, | |
12300 | xdp->xsk.queue_id); | |
0c8493d9 BT |
12301 | default: |
12302 | return -EINVAL; | |
12303 | } | |
12304 | } | |
12305 | ||
37a2973a | 12306 | static const struct net_device_ops i40e_netdev_ops = { |
41c445ff JB |
12307 | .ndo_open = i40e_open, |
12308 | .ndo_stop = i40e_close, | |
12309 | .ndo_start_xmit = i40e_lan_xmit_frame, | |
12310 | .ndo_get_stats64 = i40e_get_netdev_stats_struct, | |
12311 | .ndo_set_rx_mode = i40e_set_rx_mode, | |
12312 | .ndo_validate_addr = eth_validate_addr, | |
12313 | .ndo_set_mac_address = i40e_set_mac, | |
12314 | .ndo_change_mtu = i40e_change_mtu, | |
beb0dff1 | 12315 | .ndo_do_ioctl = i40e_ioctl, |
41c445ff JB |
12316 | .ndo_tx_timeout = i40e_tx_timeout, |
12317 | .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid, | |
12318 | .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid, | |
12319 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
12320 | .ndo_poll_controller = i40e_netpoll, | |
12321 | #endif | |
e4c6734e | 12322 | .ndo_setup_tc = __i40e_setup_tc, |
41c445ff JB |
12323 | .ndo_set_features = i40e_set_features, |
12324 | .ndo_set_vf_mac = i40e_ndo_set_vf_mac, | |
12325 | .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan, | |
ed616689 | 12326 | .ndo_set_vf_rate = i40e_ndo_set_vf_bw, |
41c445ff | 12327 | .ndo_get_vf_config = i40e_ndo_get_vf_config, |
588aefa0 | 12328 | .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state, |
e6d9004d | 12329 | .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk, |
c3bbbd20 | 12330 | .ndo_set_vf_trust = i40e_ndo_set_vf_trust, |
06a5f7f1 AD |
12331 | .ndo_udp_tunnel_add = i40e_udp_tunnel_add, |
12332 | .ndo_udp_tunnel_del = i40e_udp_tunnel_del, | |
1f224ad2 | 12333 | .ndo_get_phys_port_id = i40e_get_phys_port_id, |
4ba0dea5 | 12334 | .ndo_fdb_add = i40e_ndo_fdb_add, |
f44a75e2 | 12335 | .ndo_features_check = i40e_features_check, |
51616018 NP |
12336 | .ndo_bridge_getlink = i40e_ndo_bridge_getlink, |
12337 | .ndo_bridge_setlink = i40e_ndo_bridge_setlink, | |
f4e63525 | 12338 | .ndo_bpf = i40e_xdp, |
d9314c47 | 12339 | .ndo_xdp_xmit = i40e_xdp_xmit, |
1328dcdd | 12340 | .ndo_xsk_async_xmit = i40e_xsk_async_xmit, |
41c445ff JB |
12341 | }; |
12342 | ||
12343 | /** | |
12344 | * i40e_config_netdev - Setup the netdev flags | |
12345 | * @vsi: the VSI being configured | |
12346 | * | |
12347 | * Returns 0 on success, negative value on failure | |
12348 | **/ | |
12349 | static int i40e_config_netdev(struct i40e_vsi *vsi) | |
12350 | { | |
12351 | struct i40e_pf *pf = vsi->back; | |
12352 | struct i40e_hw *hw = &pf->hw; | |
12353 | struct i40e_netdev_priv *np; | |
12354 | struct net_device *netdev; | |
435c084a | 12355 | u8 broadcast[ETH_ALEN]; |
41c445ff JB |
12356 | u8 mac_addr[ETH_ALEN]; |
12357 | int etherdev_size; | |
bacd75cf PB |
12358 | netdev_features_t hw_enc_features; |
12359 | netdev_features_t hw_features; | |
41c445ff JB |
12360 | |
12361 | etherdev_size = sizeof(struct i40e_netdev_priv); | |
f8ff1464 | 12362 | netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs); |
41c445ff JB |
12363 | if (!netdev) |
12364 | return -ENOMEM; | |
12365 | ||
12366 | vsi->netdev = netdev; | |
12367 | np = netdev_priv(netdev); | |
12368 | np->vsi = vsi; | |
12369 | ||
bacd75cf PB |
12370 | hw_enc_features = NETIF_F_SG | |
12371 | NETIF_F_IP_CSUM | | |
12372 | NETIF_F_IPV6_CSUM | | |
12373 | NETIF_F_HIGHDMA | | |
12374 | NETIF_F_SOFT_FEATURES | | |
12375 | NETIF_F_TSO | | |
12376 | NETIF_F_TSO_ECN | | |
12377 | NETIF_F_TSO6 | | |
12378 | NETIF_F_GSO_GRE | | |
12379 | NETIF_F_GSO_GRE_CSUM | | |
12380 | NETIF_F_GSO_PARTIAL | | |
ba766b8b JK |
12381 | NETIF_F_GSO_IPXIP4 | |
12382 | NETIF_F_GSO_IPXIP6 | | |
bacd75cf PB |
12383 | NETIF_F_GSO_UDP_TUNNEL | |
12384 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
12385 | NETIF_F_SCTP_CRC | | |
12386 | NETIF_F_RXHASH | | |
12387 | NETIF_F_RXCSUM | | |
12388 | 0; | |
41c445ff | 12389 | |
d36e41dc | 12390 | if (!(pf->hw_features & I40E_HW_OUTER_UDP_CSUM_CAPABLE)) |
1c7b4a23 AD |
12391 | netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; |
12392 | ||
12393 | netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; | |
b0fe3306 | 12394 | |
bacd75cf PB |
12395 | netdev->hw_enc_features |= hw_enc_features; |
12396 | ||
b0fe3306 | 12397 | /* record features VLANs can make use of */ |
bacd75cf | 12398 | netdev->vlan_features |= hw_enc_features | NETIF_F_TSO_MANGLEID; |
41c445ff | 12399 | |
bacd75cf PB |
12400 | hw_features = hw_enc_features | |
12401 | NETIF_F_HW_VLAN_CTAG_TX | | |
12402 | NETIF_F_HW_VLAN_CTAG_RX; | |
b0fe3306 | 12403 | |
d5596fd4 JK |
12404 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) |
12405 | hw_features |= NETIF_F_NTUPLE | NETIF_F_HW_TC; | |
12406 | ||
bacd75cf | 12407 | netdev->hw_features |= hw_features; |
2e86a0b6 | 12408 | |
bacd75cf | 12409 | netdev->features |= hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; |
1c7b4a23 | 12410 | netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; |
41c445ff JB |
12411 | |
12412 | if (vsi->type == I40E_VSI_MAIN) { | |
12413 | SET_NETDEV_DEV(netdev, &pf->pdev->dev); | |
9a173901 | 12414 | ether_addr_copy(mac_addr, hw->mac.perm_addr); |
41c4c2b5 JK |
12415 | /* The following steps are necessary for two reasons. First, |
12416 | * some older NVM configurations load a default MAC-VLAN | |
12417 | * filter that will accept any tagged packet, and we want to | |
12418 | * replace this with a normal filter. Additionally, it is | |
12419 | * possible our MAC address was provided by the platform using | |
12420 | * Open Firmware or similar. | |
12421 | * | |
12422 | * Thus, we need to remove the default filter and install one | |
12423 | * specific to the MAC address. | |
1596b5dd JK |
12424 | */ |
12425 | i40e_rm_default_mac_filter(vsi, mac_addr); | |
278e7d0b | 12426 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
9569a9a4 | 12427 | i40e_add_mac_filter(vsi, mac_addr); |
278e7d0b | 12428 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 12429 | } else { |
8c9eb350 JK |
12430 | /* Relate the VSI_VMDQ name to the VSI_MAIN name. Note that we |
12431 | * are still limited by IFNAMSIZ, but we're adding 'v%d\0' to | |
12432 | * the end, which is 4 bytes long, so force truncation of the | |
12433 | * original name by IFNAMSIZ - 4 | |
12434 | */ | |
12435 | snprintf(netdev->name, IFNAMSIZ, "%.*sv%%d", | |
12436 | IFNAMSIZ - 4, | |
41c445ff | 12437 | pf->vsi[pf->lan_vsi]->netdev->name); |
6c1f0a1f | 12438 | eth_random_addr(mac_addr); |
21659035 | 12439 | |
278e7d0b | 12440 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
9569a9a4 | 12441 | i40e_add_mac_filter(vsi, mac_addr); |
278e7d0b | 12442 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 12443 | } |
21659035 | 12444 | |
435c084a JK |
12445 | /* Add the broadcast filter so that we initially will receive |
12446 | * broadcast packets. Note that when a new VLAN is first added the | |
12447 | * driver will convert all filters marked I40E_VLAN_ANY into VLAN | |
12448 | * specific filters as part of transitioning into "vlan" operation. | |
12449 | * When more VLANs are added, the driver will copy each existing MAC | |
12450 | * filter and add it for the new VLAN. | |
12451 | * | |
12452 | * Broadcast filters are handled specially by | |
12453 | * i40e_sync_filters_subtask, as the driver must to set the broadcast | |
12454 | * promiscuous bit instead of adding this directly as a MAC/VLAN | |
12455 | * filter. The subtask will update the correct broadcast promiscuous | |
12456 | * bits as VLANs become active or inactive. | |
12457 | */ | |
12458 | eth_broadcast_addr(broadcast); | |
12459 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
9569a9a4 | 12460 | i40e_add_mac_filter(vsi, broadcast); |
435c084a JK |
12461 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
12462 | ||
9a173901 GR |
12463 | ether_addr_copy(netdev->dev_addr, mac_addr); |
12464 | ether_addr_copy(netdev->perm_addr, mac_addr); | |
b0fe3306 | 12465 | |
31389b53 KK |
12466 | /* i40iw_net_event() reads 16 bytes from neigh->primary_key */ |
12467 | netdev->neigh_priv_len = sizeof(u32) * 4; | |
12468 | ||
41c445ff JB |
12469 | netdev->priv_flags |= IFF_UNICAST_FLT; |
12470 | netdev->priv_flags |= IFF_SUPP_NOFCS; | |
12471 | /* Setup netdev TC information */ | |
12472 | i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc); | |
12473 | ||
12474 | netdev->netdev_ops = &i40e_netdev_ops; | |
12475 | netdev->watchdog_timeo = 5 * HZ; | |
12476 | i40e_set_ethtool_ops(netdev); | |
12477 | ||
91c527a5 JW |
12478 | /* MTU range: 68 - 9706 */ |
12479 | netdev->min_mtu = ETH_MIN_MTU; | |
1e3a5fd5 | 12480 | netdev->max_mtu = I40E_MAX_RXBUFFER - I40E_PACKET_HDR_PAD; |
91c527a5 | 12481 | |
41c445ff JB |
12482 | return 0; |
12483 | } | |
12484 | ||
12485 | /** | |
12486 | * i40e_vsi_delete - Delete a VSI from the switch | |
12487 | * @vsi: the VSI being removed | |
12488 | * | |
12489 | * Returns 0 on success, negative value on failure | |
12490 | **/ | |
12491 | static void i40e_vsi_delete(struct i40e_vsi *vsi) | |
12492 | { | |
12493 | /* remove default VSI is not allowed */ | |
12494 | if (vsi == vsi->back->vsi[vsi->back->lan_vsi]) | |
12495 | return; | |
12496 | ||
41c445ff | 12497 | i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL); |
41c445ff JB |
12498 | } |
12499 | ||
51616018 NP |
12500 | /** |
12501 | * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB | |
12502 | * @vsi: the VSI being queried | |
12503 | * | |
12504 | * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode | |
12505 | **/ | |
12506 | int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi) | |
12507 | { | |
12508 | struct i40e_veb *veb; | |
12509 | struct i40e_pf *pf = vsi->back; | |
12510 | ||
12511 | /* Uplink is not a bridge so default to VEB */ | |
12512 | if (vsi->veb_idx == I40E_NO_VEB) | |
12513 | return 1; | |
12514 | ||
12515 | veb = pf->veb[vsi->veb_idx]; | |
09603eaa AA |
12516 | if (!veb) { |
12517 | dev_info(&pf->pdev->dev, | |
12518 | "There is no veb associated with the bridge\n"); | |
12519 | return -ENOENT; | |
12520 | } | |
12521 | ||
51616018 | 12522 | /* Uplink is a bridge in VEPA mode */ |
09603eaa | 12523 | if (veb->bridge_mode & BRIDGE_MODE_VEPA) { |
51616018 | 12524 | return 0; |
09603eaa AA |
12525 | } else { |
12526 | /* Uplink is a bridge in VEB mode */ | |
12527 | return 1; | |
12528 | } | |
51616018 | 12529 | |
09603eaa AA |
12530 | /* VEPA is now default bridge, so return 0 */ |
12531 | return 0; | |
51616018 NP |
12532 | } |
12533 | ||
41c445ff JB |
12534 | /** |
12535 | * i40e_add_vsi - Add a VSI to the switch | |
12536 | * @vsi: the VSI being configured | |
12537 | * | |
12538 | * This initializes a VSI context depending on the VSI type to be added and | |
12539 | * passes it down to the add_vsi aq command. | |
12540 | **/ | |
12541 | static int i40e_add_vsi(struct i40e_vsi *vsi) | |
12542 | { | |
12543 | int ret = -ENODEV; | |
41c445ff JB |
12544 | struct i40e_pf *pf = vsi->back; |
12545 | struct i40e_hw *hw = &pf->hw; | |
12546 | struct i40e_vsi_context ctxt; | |
278e7d0b JK |
12547 | struct i40e_mac_filter *f; |
12548 | struct hlist_node *h; | |
12549 | int bkt; | |
21659035 | 12550 | |
41c445ff JB |
12551 | u8 enabled_tc = 0x1; /* TC0 enabled */ |
12552 | int f_count = 0; | |
12553 | ||
12554 | memset(&ctxt, 0, sizeof(ctxt)); | |
12555 | switch (vsi->type) { | |
12556 | case I40E_VSI_MAIN: | |
12557 | /* The PF's main VSI is already setup as part of the | |
12558 | * device initialization, so we'll not bother with | |
12559 | * the add_vsi call, but we will retrieve the current | |
12560 | * VSI context. | |
12561 | */ | |
12562 | ctxt.seid = pf->main_vsi_seid; | |
12563 | ctxt.pf_num = pf->hw.pf_id; | |
12564 | ctxt.vf_num = 0; | |
12565 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); | |
12566 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
12567 | if (ret) { | |
12568 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
12569 | "couldn't get PF vsi config, err %s aq_err %s\n", |
12570 | i40e_stat_str(&pf->hw, ret), | |
12571 | i40e_aq_str(&pf->hw, | |
12572 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
12573 | return -ENOENT; |
12574 | } | |
1a2f6248 | 12575 | vsi->info = ctxt.info; |
41c445ff JB |
12576 | vsi->info.valid_sections = 0; |
12577 | ||
12578 | vsi->seid = ctxt.seid; | |
12579 | vsi->id = ctxt.vsi_number; | |
12580 | ||
12581 | enabled_tc = i40e_pf_get_tc_map(pf); | |
12582 | ||
64615b54 MW |
12583 | /* Source pruning is enabled by default, so the flag is |
12584 | * negative logic - if it's set, we need to fiddle with | |
12585 | * the VSI to disable source pruning. | |
12586 | */ | |
12587 | if (pf->flags & I40E_FLAG_SOURCE_PRUNING_DISABLED) { | |
12588 | memset(&ctxt, 0, sizeof(ctxt)); | |
12589 | ctxt.seid = pf->main_vsi_seid; | |
12590 | ctxt.pf_num = pf->hw.pf_id; | |
12591 | ctxt.vf_num = 0; | |
12592 | ctxt.info.valid_sections |= | |
12593 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
12594 | ctxt.info.switch_id = | |
12595 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB); | |
12596 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); | |
12597 | if (ret) { | |
12598 | dev_info(&pf->pdev->dev, | |
12599 | "update vsi failed, err %s aq_err %s\n", | |
12600 | i40e_stat_str(&pf->hw, ret), | |
12601 | i40e_aq_str(&pf->hw, | |
12602 | pf->hw.aq.asq_last_status)); | |
12603 | ret = -ENOENT; | |
12604 | goto err; | |
12605 | } | |
12606 | } | |
12607 | ||
41c445ff | 12608 | /* MFP mode setup queue map and update VSI */ |
63d7e5a4 NP |
12609 | if ((pf->flags & I40E_FLAG_MFP_ENABLED) && |
12610 | !(pf->hw.func_caps.iscsi)) { /* NIC type PF */ | |
41c445ff JB |
12611 | memset(&ctxt, 0, sizeof(ctxt)); |
12612 | ctxt.seid = pf->main_vsi_seid; | |
12613 | ctxt.pf_num = pf->hw.pf_id; | |
12614 | ctxt.vf_num = 0; | |
12615 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); | |
12616 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); | |
12617 | if (ret) { | |
12618 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
12619 | "update vsi failed, err %s aq_err %s\n", |
12620 | i40e_stat_str(&pf->hw, ret), | |
12621 | i40e_aq_str(&pf->hw, | |
12622 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
12623 | ret = -ENOENT; |
12624 | goto err; | |
12625 | } | |
12626 | /* update the local VSI info queue map */ | |
12627 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
12628 | vsi->info.valid_sections = 0; | |
12629 | } else { | |
12630 | /* Default/Main VSI is only enabled for TC0 | |
12631 | * reconfigure it to enable all TCs that are | |
12632 | * available on the port in SFP mode. | |
63d7e5a4 NP |
12633 | * For MFP case the iSCSI PF would use this |
12634 | * flow to enable LAN+iSCSI TC. | |
41c445ff JB |
12635 | */ |
12636 | ret = i40e_vsi_config_tc(vsi, enabled_tc); | |
12637 | if (ret) { | |
19279235 CW |
12638 | /* Single TC condition is not fatal, |
12639 | * message and continue | |
12640 | */ | |
41c445ff | 12641 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
12642 | "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n", |
12643 | enabled_tc, | |
12644 | i40e_stat_str(&pf->hw, ret), | |
12645 | i40e_aq_str(&pf->hw, | |
12646 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
12647 | } |
12648 | } | |
12649 | break; | |
12650 | ||
12651 | case I40E_VSI_FDIR: | |
cbf61325 ASJ |
12652 | ctxt.pf_num = hw->pf_id; |
12653 | ctxt.vf_num = 0; | |
12654 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 12655 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
cbf61325 | 12656 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; |
fc60861e ASJ |
12657 | if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) && |
12658 | (i40e_is_vsi_uplink_mode_veb(vsi))) { | |
51616018 | 12659 | ctxt.info.valid_sections |= |
fc60861e | 12660 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); |
51616018 | 12661 | ctxt.info.switch_id = |
fc60861e | 12662 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); |
51616018 | 12663 | } |
41c445ff | 12664 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); |
41c445ff JB |
12665 | break; |
12666 | ||
12667 | case I40E_VSI_VMDQ2: | |
12668 | ctxt.pf_num = hw->pf_id; | |
12669 | ctxt.vf_num = 0; | |
12670 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 12671 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
41c445ff JB |
12672 | ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; |
12673 | ||
41c445ff JB |
12674 | /* This VSI is connected to VEB so the switch_id |
12675 | * should be set to zero by default. | |
12676 | */ | |
51616018 NP |
12677 | if (i40e_is_vsi_uplink_mode_veb(vsi)) { |
12678 | ctxt.info.valid_sections |= | |
12679 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
12680 | ctxt.info.switch_id = | |
12681 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
12682 | } | |
41c445ff JB |
12683 | |
12684 | /* Setup the VSI tx/rx queue map for TC0 only for now */ | |
12685 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); | |
12686 | break; | |
12687 | ||
12688 | case I40E_VSI_SRIOV: | |
12689 | ctxt.pf_num = hw->pf_id; | |
12690 | ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id; | |
12691 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 12692 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
41c445ff JB |
12693 | ctxt.flags = I40E_AQ_VSI_TYPE_VF; |
12694 | ||
41c445ff JB |
12695 | /* This VSI is connected to VEB so the switch_id |
12696 | * should be set to zero by default. | |
12697 | */ | |
51616018 NP |
12698 | if (i40e_is_vsi_uplink_mode_veb(vsi)) { |
12699 | ctxt.info.valid_sections |= | |
12700 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
12701 | ctxt.info.switch_id = | |
12702 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
12703 | } | |
41c445ff | 12704 | |
e3219ce6 ASJ |
12705 | if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { |
12706 | ctxt.info.valid_sections |= | |
12707 | cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); | |
12708 | ctxt.info.queueing_opt_flags |= | |
4b28cdba AS |
12709 | (I40E_AQ_VSI_QUE_OPT_TCP_ENA | |
12710 | I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI); | |
e3219ce6 ASJ |
12711 | } |
12712 | ||
41c445ff JB |
12713 | ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); |
12714 | ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; | |
c674d125 MW |
12715 | if (pf->vf[vsi->vf_id].spoofchk) { |
12716 | ctxt.info.valid_sections |= | |
12717 | cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID); | |
12718 | ctxt.info.sec_flags |= | |
12719 | (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK | | |
12720 | I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK); | |
12721 | } | |
41c445ff JB |
12722 | /* Setup the VSI tx/rx queue map for TC0 only for now */ |
12723 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); | |
12724 | break; | |
12725 | ||
e3219ce6 ASJ |
12726 | case I40E_VSI_IWARP: |
12727 | /* send down message to iWARP */ | |
12728 | break; | |
12729 | ||
41c445ff JB |
12730 | default: |
12731 | return -ENODEV; | |
12732 | } | |
12733 | ||
12734 | if (vsi->type != I40E_VSI_MAIN) { | |
12735 | ret = i40e_aq_add_vsi(hw, &ctxt, NULL); | |
12736 | if (ret) { | |
12737 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
12738 | "add vsi failed, err %s aq_err %s\n", |
12739 | i40e_stat_str(&pf->hw, ret), | |
12740 | i40e_aq_str(&pf->hw, | |
12741 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
12742 | ret = -ENOENT; |
12743 | goto err; | |
12744 | } | |
1a2f6248 | 12745 | vsi->info = ctxt.info; |
41c445ff JB |
12746 | vsi->info.valid_sections = 0; |
12747 | vsi->seid = ctxt.seid; | |
12748 | vsi->id = ctxt.vsi_number; | |
12749 | } | |
12750 | ||
c3c7ea27 | 12751 | vsi->active_filters = 0; |
0da36b97 | 12752 | clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
278e7d0b | 12753 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 12754 | /* If macvlan filters already exist, force them to get loaded */ |
278e7d0b | 12755 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
c3c7ea27 | 12756 | f->state = I40E_FILTER_NEW; |
41c445ff | 12757 | f_count++; |
21659035 | 12758 | } |
278e7d0b | 12759 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
30650cc5 | 12760 | |
41c445ff JB |
12761 | if (f_count) { |
12762 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
bfe040c3 | 12763 | set_bit(__I40E_MACVLAN_SYNC_PENDING, pf->state); |
41c445ff JB |
12764 | } |
12765 | ||
12766 | /* Update VSI BW information */ | |
12767 | ret = i40e_vsi_get_bw_info(vsi); | |
12768 | if (ret) { | |
12769 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
12770 | "couldn't get vsi bw info, err %s aq_err %s\n", |
12771 | i40e_stat_str(&pf->hw, ret), | |
12772 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
12773 | /* VSI is already added so not tearing that up */ |
12774 | ret = 0; | |
12775 | } | |
12776 | ||
12777 | err: | |
12778 | return ret; | |
12779 | } | |
12780 | ||
12781 | /** | |
12782 | * i40e_vsi_release - Delete a VSI and free its resources | |
12783 | * @vsi: the VSI being removed | |
12784 | * | |
12785 | * Returns 0 on success or < 0 on error | |
12786 | **/ | |
12787 | int i40e_vsi_release(struct i40e_vsi *vsi) | |
12788 | { | |
278e7d0b JK |
12789 | struct i40e_mac_filter *f; |
12790 | struct hlist_node *h; | |
41c445ff JB |
12791 | struct i40e_veb *veb = NULL; |
12792 | struct i40e_pf *pf; | |
12793 | u16 uplink_seid; | |
278e7d0b | 12794 | int i, n, bkt; |
41c445ff JB |
12795 | |
12796 | pf = vsi->back; | |
12797 | ||
12798 | /* release of a VEB-owner or last VSI is not allowed */ | |
12799 | if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) { | |
12800 | dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n", | |
12801 | vsi->seid, vsi->uplink_seid); | |
12802 | return -ENODEV; | |
12803 | } | |
12804 | if (vsi == pf->vsi[pf->lan_vsi] && | |
9e6c9c0f | 12805 | !test_bit(__I40E_DOWN, pf->state)) { |
41c445ff JB |
12806 | dev_info(&pf->pdev->dev, "Can't remove PF VSI\n"); |
12807 | return -ENODEV; | |
12808 | } | |
12809 | ||
12810 | uplink_seid = vsi->uplink_seid; | |
12811 | if (vsi->type != I40E_VSI_SRIOV) { | |
12812 | if (vsi->netdev_registered) { | |
12813 | vsi->netdev_registered = false; | |
12814 | if (vsi->netdev) { | |
12815 | /* results in a call to i40e_close() */ | |
12816 | unregister_netdev(vsi->netdev); | |
41c445ff JB |
12817 | } |
12818 | } else { | |
90ef8d47 | 12819 | i40e_vsi_close(vsi); |
41c445ff JB |
12820 | } |
12821 | i40e_vsi_disable_irq(vsi); | |
12822 | } | |
12823 | ||
278e7d0b | 12824 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
6622f5cd JK |
12825 | |
12826 | /* clear the sync flag on all filters */ | |
12827 | if (vsi->netdev) { | |
12828 | __dev_uc_unsync(vsi->netdev, NULL); | |
12829 | __dev_mc_unsync(vsi->netdev, NULL); | |
12830 | } | |
12831 | ||
12832 | /* make sure any remaining filters are marked for deletion */ | |
278e7d0b | 12833 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) |
290d2557 | 12834 | __i40e_del_filter(vsi, f); |
6622f5cd | 12835 | |
278e7d0b | 12836 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 12837 | |
17652c63 | 12838 | i40e_sync_vsi_filters(vsi); |
41c445ff JB |
12839 | |
12840 | i40e_vsi_delete(vsi); | |
12841 | i40e_vsi_free_q_vectors(vsi); | |
a4866597 SN |
12842 | if (vsi->netdev) { |
12843 | free_netdev(vsi->netdev); | |
12844 | vsi->netdev = NULL; | |
12845 | } | |
41c445ff JB |
12846 | i40e_vsi_clear_rings(vsi); |
12847 | i40e_vsi_clear(vsi); | |
12848 | ||
12849 | /* If this was the last thing on the VEB, except for the | |
12850 | * controlling VSI, remove the VEB, which puts the controlling | |
12851 | * VSI onto the next level down in the switch. | |
12852 | * | |
12853 | * Well, okay, there's one more exception here: don't remove | |
12854 | * the orphan VEBs yet. We'll wait for an explicit remove request | |
12855 | * from up the network stack. | |
12856 | */ | |
505682cd | 12857 | for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
12858 | if (pf->vsi[i] && |
12859 | pf->vsi[i]->uplink_seid == uplink_seid && | |
12860 | (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { | |
12861 | n++; /* count the VSIs */ | |
12862 | } | |
12863 | } | |
12864 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
12865 | if (!pf->veb[i]) | |
12866 | continue; | |
12867 | if (pf->veb[i]->uplink_seid == uplink_seid) | |
12868 | n++; /* count the VEBs */ | |
12869 | if (pf->veb[i]->seid == uplink_seid) | |
12870 | veb = pf->veb[i]; | |
12871 | } | |
12872 | if (n == 0 && veb && veb->uplink_seid != 0) | |
12873 | i40e_veb_release(veb); | |
12874 | ||
12875 | return 0; | |
12876 | } | |
12877 | ||
12878 | /** | |
12879 | * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI | |
12880 | * @vsi: ptr to the VSI | |
12881 | * | |
12882 | * This should only be called after i40e_vsi_mem_alloc() which allocates the | |
12883 | * corresponding SW VSI structure and initializes num_queue_pairs for the | |
12884 | * newly allocated VSI. | |
12885 | * | |
12886 | * Returns 0 on success or negative on failure | |
12887 | **/ | |
12888 | static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi) | |
12889 | { | |
12890 | int ret = -ENOENT; | |
12891 | struct i40e_pf *pf = vsi->back; | |
12892 | ||
493fb300 | 12893 | if (vsi->q_vectors[0]) { |
41c445ff JB |
12894 | dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n", |
12895 | vsi->seid); | |
12896 | return -EEXIST; | |
12897 | } | |
12898 | ||
12899 | if (vsi->base_vector) { | |
f29eaa3d | 12900 | dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n", |
41c445ff JB |
12901 | vsi->seid, vsi->base_vector); |
12902 | return -EEXIST; | |
12903 | } | |
12904 | ||
90e04070 | 12905 | ret = i40e_vsi_alloc_q_vectors(vsi); |
41c445ff JB |
12906 | if (ret) { |
12907 | dev_info(&pf->pdev->dev, | |
12908 | "failed to allocate %d q_vector for VSI %d, ret=%d\n", | |
12909 | vsi->num_q_vectors, vsi->seid, ret); | |
12910 | vsi->num_q_vectors = 0; | |
12911 | goto vector_setup_out; | |
12912 | } | |
12913 | ||
26cdc443 ASJ |
12914 | /* In Legacy mode, we do not have to get any other vector since we |
12915 | * piggyback on the misc/ICR0 for queue interrupts. | |
12916 | */ | |
12917 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
12918 | return ret; | |
958a3e3b SN |
12919 | if (vsi->num_q_vectors) |
12920 | vsi->base_vector = i40e_get_lump(pf, pf->irq_pile, | |
12921 | vsi->num_q_vectors, vsi->idx); | |
41c445ff JB |
12922 | if (vsi->base_vector < 0) { |
12923 | dev_info(&pf->pdev->dev, | |
049a2be8 SN |
12924 | "failed to get tracking for %d vectors for VSI %d, err=%d\n", |
12925 | vsi->num_q_vectors, vsi->seid, vsi->base_vector); | |
41c445ff JB |
12926 | i40e_vsi_free_q_vectors(vsi); |
12927 | ret = -ENOENT; | |
12928 | goto vector_setup_out; | |
12929 | } | |
12930 | ||
12931 | vector_setup_out: | |
12932 | return ret; | |
12933 | } | |
12934 | ||
bc7d338f ASJ |
12935 | /** |
12936 | * i40e_vsi_reinit_setup - return and reallocate resources for a VSI | |
12937 | * @vsi: pointer to the vsi. | |
12938 | * | |
12939 | * This re-allocates a vsi's queue resources. | |
12940 | * | |
12941 | * Returns pointer to the successfully allocated and configured VSI sw struct | |
12942 | * on success, otherwise returns NULL on failure. | |
12943 | **/ | |
12944 | static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi) | |
12945 | { | |
74608d17 | 12946 | u16 alloc_queue_pairs; |
f534039d | 12947 | struct i40e_pf *pf; |
bc7d338f ASJ |
12948 | u8 enabled_tc; |
12949 | int ret; | |
12950 | ||
f534039d JU |
12951 | if (!vsi) |
12952 | return NULL; | |
12953 | ||
12954 | pf = vsi->back; | |
12955 | ||
bc7d338f ASJ |
12956 | i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); |
12957 | i40e_vsi_clear_rings(vsi); | |
12958 | ||
12959 | i40e_vsi_free_arrays(vsi, false); | |
12960 | i40e_set_num_rings_in_vsi(vsi); | |
12961 | ret = i40e_vsi_alloc_arrays(vsi, false); | |
12962 | if (ret) | |
12963 | goto err_vsi; | |
12964 | ||
74608d17 BT |
12965 | alloc_queue_pairs = vsi->alloc_queue_pairs * |
12966 | (i40e_enabled_xdp_vsi(vsi) ? 2 : 1); | |
12967 | ||
12968 | ret = i40e_get_lump(pf, pf->qp_pile, alloc_queue_pairs, vsi->idx); | |
bc7d338f | 12969 | if (ret < 0) { |
049a2be8 | 12970 | dev_info(&pf->pdev->dev, |
f1c7e72e | 12971 | "failed to get tracking for %d queues for VSI %d err %d\n", |
74608d17 | 12972 | alloc_queue_pairs, vsi->seid, ret); |
bc7d338f ASJ |
12973 | goto err_vsi; |
12974 | } | |
12975 | vsi->base_queue = ret; | |
12976 | ||
12977 | /* Update the FW view of the VSI. Force a reset of TC and queue | |
12978 | * layout configurations. | |
12979 | */ | |
12980 | enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; | |
12981 | pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; | |
12982 | pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; | |
12983 | i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); | |
1596b5dd JK |
12984 | if (vsi->type == I40E_VSI_MAIN) |
12985 | i40e_rm_default_mac_filter(vsi, pf->hw.mac.perm_addr); | |
bc7d338f ASJ |
12986 | |
12987 | /* assign it some queues */ | |
12988 | ret = i40e_alloc_rings(vsi); | |
12989 | if (ret) | |
12990 | goto err_rings; | |
12991 | ||
12992 | /* map all of the rings to the q_vectors */ | |
12993 | i40e_vsi_map_rings_to_vectors(vsi); | |
12994 | return vsi; | |
12995 | ||
12996 | err_rings: | |
12997 | i40e_vsi_free_q_vectors(vsi); | |
12998 | if (vsi->netdev_registered) { | |
12999 | vsi->netdev_registered = false; | |
13000 | unregister_netdev(vsi->netdev); | |
13001 | free_netdev(vsi->netdev); | |
13002 | vsi->netdev = NULL; | |
13003 | } | |
13004 | i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); | |
13005 | err_vsi: | |
13006 | i40e_vsi_clear(vsi); | |
13007 | return NULL; | |
13008 | } | |
13009 | ||
41c445ff JB |
13010 | /** |
13011 | * i40e_vsi_setup - Set up a VSI by a given type | |
13012 | * @pf: board private structure | |
13013 | * @type: VSI type | |
13014 | * @uplink_seid: the switch element to link to | |
13015 | * @param1: usage depends upon VSI type. For VF types, indicates VF id | |
13016 | * | |
13017 | * This allocates the sw VSI structure and its queue resources, then add a VSI | |
13018 | * to the identified VEB. | |
13019 | * | |
13020 | * Returns pointer to the successfully allocated and configure VSI sw struct on | |
13021 | * success, otherwise returns NULL on failure. | |
13022 | **/ | |
13023 | struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, | |
13024 | u16 uplink_seid, u32 param1) | |
13025 | { | |
13026 | struct i40e_vsi *vsi = NULL; | |
13027 | struct i40e_veb *veb = NULL; | |
74608d17 | 13028 | u16 alloc_queue_pairs; |
41c445ff JB |
13029 | int ret, i; |
13030 | int v_idx; | |
13031 | ||
13032 | /* The requested uplink_seid must be either | |
13033 | * - the PF's port seid | |
13034 | * no VEB is needed because this is the PF | |
13035 | * or this is a Flow Director special case VSI | |
13036 | * - seid of an existing VEB | |
13037 | * - seid of a VSI that owns an existing VEB | |
13038 | * - seid of a VSI that doesn't own a VEB | |
13039 | * a new VEB is created and the VSI becomes the owner | |
13040 | * - seid of the PF VSI, which is what creates the first VEB | |
13041 | * this is a special case of the previous | |
13042 | * | |
13043 | * Find which uplink_seid we were given and create a new VEB if needed | |
13044 | */ | |
13045 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
13046 | if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) { | |
13047 | veb = pf->veb[i]; | |
13048 | break; | |
13049 | } | |
13050 | } | |
13051 | ||
13052 | if (!veb && uplink_seid != pf->mac_seid) { | |
13053 | ||
505682cd | 13054 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
13055 | if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) { |
13056 | vsi = pf->vsi[i]; | |
13057 | break; | |
13058 | } | |
13059 | } | |
13060 | if (!vsi) { | |
13061 | dev_info(&pf->pdev->dev, "no such uplink_seid %d\n", | |
13062 | uplink_seid); | |
13063 | return NULL; | |
13064 | } | |
13065 | ||
13066 | if (vsi->uplink_seid == pf->mac_seid) | |
13067 | veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid, | |
13068 | vsi->tc_config.enabled_tc); | |
13069 | else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) | |
13070 | veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, | |
13071 | vsi->tc_config.enabled_tc); | |
79c21a82 ASJ |
13072 | if (veb) { |
13073 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) { | |
13074 | dev_info(&vsi->back->pdev->dev, | |
fb43201f | 13075 | "New VSI creation error, uplink seid of LAN VSI expected.\n"); |
79c21a82 ASJ |
13076 | return NULL; |
13077 | } | |
fa11cb3d ASJ |
13078 | /* We come up by default in VEPA mode if SRIOV is not |
13079 | * already enabled, in which case we can't force VEPA | |
13080 | * mode. | |
13081 | */ | |
13082 | if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) { | |
13083 | veb->bridge_mode = BRIDGE_MODE_VEPA; | |
13084 | pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; | |
13085 | } | |
51616018 | 13086 | i40e_config_bridge_mode(veb); |
79c21a82 | 13087 | } |
41c445ff JB |
13088 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { |
13089 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
13090 | veb = pf->veb[i]; | |
13091 | } | |
13092 | if (!veb) { | |
13093 | dev_info(&pf->pdev->dev, "couldn't add VEB\n"); | |
13094 | return NULL; | |
13095 | } | |
13096 | ||
13097 | vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; | |
13098 | uplink_seid = veb->seid; | |
13099 | } | |
13100 | ||
13101 | /* get vsi sw struct */ | |
13102 | v_idx = i40e_vsi_mem_alloc(pf, type); | |
13103 | if (v_idx < 0) | |
13104 | goto err_alloc; | |
13105 | vsi = pf->vsi[v_idx]; | |
cbf61325 ASJ |
13106 | if (!vsi) |
13107 | goto err_alloc; | |
41c445ff JB |
13108 | vsi->type = type; |
13109 | vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB); | |
13110 | ||
13111 | if (type == I40E_VSI_MAIN) | |
13112 | pf->lan_vsi = v_idx; | |
13113 | else if (type == I40E_VSI_SRIOV) | |
13114 | vsi->vf_id = param1; | |
13115 | /* assign it some queues */ | |
74608d17 BT |
13116 | alloc_queue_pairs = vsi->alloc_queue_pairs * |
13117 | (i40e_enabled_xdp_vsi(vsi) ? 2 : 1); | |
13118 | ||
13119 | ret = i40e_get_lump(pf, pf->qp_pile, alloc_queue_pairs, vsi->idx); | |
41c445ff | 13120 | if (ret < 0) { |
049a2be8 SN |
13121 | dev_info(&pf->pdev->dev, |
13122 | "failed to get tracking for %d queues for VSI %d err=%d\n", | |
74608d17 | 13123 | alloc_queue_pairs, vsi->seid, ret); |
41c445ff JB |
13124 | goto err_vsi; |
13125 | } | |
13126 | vsi->base_queue = ret; | |
13127 | ||
13128 | /* get a VSI from the hardware */ | |
13129 | vsi->uplink_seid = uplink_seid; | |
13130 | ret = i40e_add_vsi(vsi); | |
13131 | if (ret) | |
13132 | goto err_vsi; | |
13133 | ||
13134 | switch (vsi->type) { | |
13135 | /* setup the netdev if needed */ | |
13136 | case I40E_VSI_MAIN: | |
13137 | case I40E_VSI_VMDQ2: | |
13138 | ret = i40e_config_netdev(vsi); | |
13139 | if (ret) | |
13140 | goto err_netdev; | |
13141 | ret = register_netdev(vsi->netdev); | |
13142 | if (ret) | |
13143 | goto err_netdev; | |
13144 | vsi->netdev_registered = true; | |
13145 | netif_carrier_off(vsi->netdev); | |
4e3b35b0 NP |
13146 | #ifdef CONFIG_I40E_DCB |
13147 | /* Setup DCB netlink interface */ | |
13148 | i40e_dcbnl_setup(vsi); | |
13149 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
13150 | /* fall through */ |
13151 | ||
13152 | case I40E_VSI_FDIR: | |
13153 | /* set up vectors and rings if needed */ | |
13154 | ret = i40e_vsi_setup_vectors(vsi); | |
13155 | if (ret) | |
13156 | goto err_msix; | |
13157 | ||
13158 | ret = i40e_alloc_rings(vsi); | |
13159 | if (ret) | |
13160 | goto err_rings; | |
13161 | ||
13162 | /* map all of the rings to the q_vectors */ | |
13163 | i40e_vsi_map_rings_to_vectors(vsi); | |
13164 | ||
13165 | i40e_vsi_reset_stats(vsi); | |
13166 | break; | |
13167 | ||
13168 | default: | |
13169 | /* no netdev or rings for the other VSI types */ | |
13170 | break; | |
13171 | } | |
13172 | ||
d36e41dc | 13173 | if ((pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) && |
e25d00b8 ASJ |
13174 | (vsi->type == I40E_VSI_VMDQ2)) { |
13175 | ret = i40e_vsi_config_rss(vsi); | |
13176 | } | |
41c445ff JB |
13177 | return vsi; |
13178 | ||
13179 | err_rings: | |
13180 | i40e_vsi_free_q_vectors(vsi); | |
13181 | err_msix: | |
13182 | if (vsi->netdev_registered) { | |
13183 | vsi->netdev_registered = false; | |
13184 | unregister_netdev(vsi->netdev); | |
13185 | free_netdev(vsi->netdev); | |
13186 | vsi->netdev = NULL; | |
13187 | } | |
13188 | err_netdev: | |
13189 | i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); | |
13190 | err_vsi: | |
13191 | i40e_vsi_clear(vsi); | |
13192 | err_alloc: | |
13193 | return NULL; | |
13194 | } | |
13195 | ||
13196 | /** | |
13197 | * i40e_veb_get_bw_info - Query VEB BW information | |
13198 | * @veb: the veb to query | |
13199 | * | |
13200 | * Query the Tx scheduler BW configuration data for given VEB | |
13201 | **/ | |
13202 | static int i40e_veb_get_bw_info(struct i40e_veb *veb) | |
13203 | { | |
13204 | struct i40e_aqc_query_switching_comp_ets_config_resp ets_data; | |
13205 | struct i40e_aqc_query_switching_comp_bw_config_resp bw_data; | |
13206 | struct i40e_pf *pf = veb->pf; | |
13207 | struct i40e_hw *hw = &pf->hw; | |
13208 | u32 tc_bw_max; | |
13209 | int ret = 0; | |
13210 | int i; | |
13211 | ||
13212 | ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid, | |
13213 | &bw_data, NULL); | |
13214 | if (ret) { | |
13215 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
13216 | "query veb bw config failed, err %s aq_err %s\n", |
13217 | i40e_stat_str(&pf->hw, ret), | |
13218 | i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); | |
41c445ff JB |
13219 | goto out; |
13220 | } | |
13221 | ||
13222 | ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid, | |
13223 | &ets_data, NULL); | |
13224 | if (ret) { | |
13225 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
13226 | "query veb bw ets config failed, err %s aq_err %s\n", |
13227 | i40e_stat_str(&pf->hw, ret), | |
13228 | i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); | |
41c445ff JB |
13229 | goto out; |
13230 | } | |
13231 | ||
13232 | veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit); | |
13233 | veb->bw_max_quanta = ets_data.tc_bw_max; | |
13234 | veb->is_abs_credits = bw_data.absolute_credits_enable; | |
23cd1f09 | 13235 | veb->enabled_tc = ets_data.tc_valid_bits; |
41c445ff JB |
13236 | tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) | |
13237 | (le16_to_cpu(bw_data.tc_bw_max[1]) << 16); | |
13238 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
13239 | veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i]; | |
13240 | veb->bw_tc_limit_credits[i] = | |
13241 | le16_to_cpu(bw_data.tc_bw_limits[i]); | |
13242 | veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7); | |
13243 | } | |
13244 | ||
13245 | out: | |
13246 | return ret; | |
13247 | } | |
13248 | ||
13249 | /** | |
13250 | * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF | |
13251 | * @pf: board private structure | |
13252 | * | |
13253 | * On error: returns error code (negative) | |
13254 | * On success: returns vsi index in PF (positive) | |
13255 | **/ | |
13256 | static int i40e_veb_mem_alloc(struct i40e_pf *pf) | |
13257 | { | |
13258 | int ret = -ENOENT; | |
13259 | struct i40e_veb *veb; | |
13260 | int i; | |
13261 | ||
13262 | /* Need to protect the allocation of switch elements at the PF level */ | |
13263 | mutex_lock(&pf->switch_mutex); | |
13264 | ||
13265 | /* VEB list may be fragmented if VEB creation/destruction has | |
13266 | * been happening. We can afford to do a quick scan to look | |
13267 | * for any free slots in the list. | |
13268 | * | |
13269 | * find next empty veb slot, looping back around if necessary | |
13270 | */ | |
13271 | i = 0; | |
13272 | while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL)) | |
13273 | i++; | |
13274 | if (i >= I40E_MAX_VEB) { | |
13275 | ret = -ENOMEM; | |
13276 | goto err_alloc_veb; /* out of VEB slots! */ | |
13277 | } | |
13278 | ||
13279 | veb = kzalloc(sizeof(*veb), GFP_KERNEL); | |
13280 | if (!veb) { | |
13281 | ret = -ENOMEM; | |
13282 | goto err_alloc_veb; | |
13283 | } | |
13284 | veb->pf = pf; | |
13285 | veb->idx = i; | |
13286 | veb->enabled_tc = 1; | |
13287 | ||
13288 | pf->veb[i] = veb; | |
13289 | ret = i; | |
13290 | err_alloc_veb: | |
13291 | mutex_unlock(&pf->switch_mutex); | |
13292 | return ret; | |
13293 | } | |
13294 | ||
13295 | /** | |
13296 | * i40e_switch_branch_release - Delete a branch of the switch tree | |
13297 | * @branch: where to start deleting | |
13298 | * | |
13299 | * This uses recursion to find the tips of the branch to be | |
13300 | * removed, deleting until we get back to and can delete this VEB. | |
13301 | **/ | |
13302 | static void i40e_switch_branch_release(struct i40e_veb *branch) | |
13303 | { | |
13304 | struct i40e_pf *pf = branch->pf; | |
13305 | u16 branch_seid = branch->seid; | |
13306 | u16 veb_idx = branch->idx; | |
13307 | int i; | |
13308 | ||
13309 | /* release any VEBs on this VEB - RECURSION */ | |
13310 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
13311 | if (!pf->veb[i]) | |
13312 | continue; | |
13313 | if (pf->veb[i]->uplink_seid == branch->seid) | |
13314 | i40e_switch_branch_release(pf->veb[i]); | |
13315 | } | |
13316 | ||
13317 | /* Release the VSIs on this VEB, but not the owner VSI. | |
13318 | * | |
13319 | * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing | |
13320 | * the VEB itself, so don't use (*branch) after this loop. | |
13321 | */ | |
505682cd | 13322 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
13323 | if (!pf->vsi[i]) |
13324 | continue; | |
13325 | if (pf->vsi[i]->uplink_seid == branch_seid && | |
13326 | (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { | |
13327 | i40e_vsi_release(pf->vsi[i]); | |
13328 | } | |
13329 | } | |
13330 | ||
13331 | /* There's one corner case where the VEB might not have been | |
13332 | * removed, so double check it here and remove it if needed. | |
13333 | * This case happens if the veb was created from the debugfs | |
13334 | * commands and no VSIs were added to it. | |
13335 | */ | |
13336 | if (pf->veb[veb_idx]) | |
13337 | i40e_veb_release(pf->veb[veb_idx]); | |
13338 | } | |
13339 | ||
13340 | /** | |
13341 | * i40e_veb_clear - remove veb struct | |
13342 | * @veb: the veb to remove | |
13343 | **/ | |
13344 | static void i40e_veb_clear(struct i40e_veb *veb) | |
13345 | { | |
13346 | if (!veb) | |
13347 | return; | |
13348 | ||
13349 | if (veb->pf) { | |
13350 | struct i40e_pf *pf = veb->pf; | |
13351 | ||
13352 | mutex_lock(&pf->switch_mutex); | |
13353 | if (pf->veb[veb->idx] == veb) | |
13354 | pf->veb[veb->idx] = NULL; | |
13355 | mutex_unlock(&pf->switch_mutex); | |
13356 | } | |
13357 | ||
13358 | kfree(veb); | |
13359 | } | |
13360 | ||
13361 | /** | |
13362 | * i40e_veb_release - Delete a VEB and free its resources | |
13363 | * @veb: the VEB being removed | |
13364 | **/ | |
13365 | void i40e_veb_release(struct i40e_veb *veb) | |
13366 | { | |
13367 | struct i40e_vsi *vsi = NULL; | |
13368 | struct i40e_pf *pf; | |
13369 | int i, n = 0; | |
13370 | ||
13371 | pf = veb->pf; | |
13372 | ||
13373 | /* find the remaining VSI and check for extras */ | |
505682cd | 13374 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
13375 | if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) { |
13376 | n++; | |
13377 | vsi = pf->vsi[i]; | |
13378 | } | |
13379 | } | |
13380 | if (n != 1) { | |
13381 | dev_info(&pf->pdev->dev, | |
13382 | "can't remove VEB %d with %d VSIs left\n", | |
13383 | veb->seid, n); | |
13384 | return; | |
13385 | } | |
13386 | ||
13387 | /* move the remaining VSI to uplink veb */ | |
13388 | vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER; | |
13389 | if (veb->uplink_seid) { | |
13390 | vsi->uplink_seid = veb->uplink_seid; | |
13391 | if (veb->uplink_seid == pf->mac_seid) | |
13392 | vsi->veb_idx = I40E_NO_VEB; | |
13393 | else | |
13394 | vsi->veb_idx = veb->veb_idx; | |
13395 | } else { | |
13396 | /* floating VEB */ | |
13397 | vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
13398 | vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx; | |
13399 | } | |
13400 | ||
13401 | i40e_aq_delete_element(&pf->hw, veb->seid, NULL); | |
13402 | i40e_veb_clear(veb); | |
41c445ff JB |
13403 | } |
13404 | ||
13405 | /** | |
13406 | * i40e_add_veb - create the VEB in the switch | |
13407 | * @veb: the VEB to be instantiated | |
13408 | * @vsi: the controlling VSI | |
13409 | **/ | |
13410 | static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi) | |
13411 | { | |
f1c7e72e | 13412 | struct i40e_pf *pf = veb->pf; |
66fc360a | 13413 | bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED); |
41c445ff JB |
13414 | int ret; |
13415 | ||
f1c7e72e | 13416 | ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid, |
5bc16031 | 13417 | veb->enabled_tc, false, |
66fc360a | 13418 | &veb->seid, enable_stats, NULL); |
5bc16031 MW |
13419 | |
13420 | /* get a VEB from the hardware */ | |
41c445ff | 13421 | if (ret) { |
f1c7e72e SN |
13422 | dev_info(&pf->pdev->dev, |
13423 | "couldn't add VEB, err %s aq_err %s\n", | |
13424 | i40e_stat_str(&pf->hw, ret), | |
13425 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
13426 | return -EPERM; |
13427 | } | |
13428 | ||
13429 | /* get statistics counter */ | |
f1c7e72e | 13430 | ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL, |
41c445ff JB |
13431 | &veb->stats_idx, NULL, NULL, NULL); |
13432 | if (ret) { | |
f1c7e72e SN |
13433 | dev_info(&pf->pdev->dev, |
13434 | "couldn't get VEB statistics idx, err %s aq_err %s\n", | |
13435 | i40e_stat_str(&pf->hw, ret), | |
13436 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
13437 | return -EPERM; |
13438 | } | |
13439 | ret = i40e_veb_get_bw_info(veb); | |
13440 | if (ret) { | |
f1c7e72e SN |
13441 | dev_info(&pf->pdev->dev, |
13442 | "couldn't get VEB bw info, err %s aq_err %s\n", | |
13443 | i40e_stat_str(&pf->hw, ret), | |
13444 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
13445 | i40e_aq_delete_element(&pf->hw, veb->seid, NULL); | |
41c445ff JB |
13446 | return -ENOENT; |
13447 | } | |
13448 | ||
13449 | vsi->uplink_seid = veb->seid; | |
13450 | vsi->veb_idx = veb->idx; | |
13451 | vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; | |
13452 | ||
13453 | return 0; | |
13454 | } | |
13455 | ||
13456 | /** | |
13457 | * i40e_veb_setup - Set up a VEB | |
13458 | * @pf: board private structure | |
13459 | * @flags: VEB setup flags | |
13460 | * @uplink_seid: the switch element to link to | |
13461 | * @vsi_seid: the initial VSI seid | |
13462 | * @enabled_tc: Enabled TC bit-map | |
13463 | * | |
13464 | * This allocates the sw VEB structure and links it into the switch | |
13465 | * It is possible and legal for this to be a duplicate of an already | |
13466 | * existing VEB. It is also possible for both uplink and vsi seids | |
13467 | * to be zero, in order to create a floating VEB. | |
13468 | * | |
13469 | * Returns pointer to the successfully allocated VEB sw struct on | |
13470 | * success, otherwise returns NULL on failure. | |
13471 | **/ | |
13472 | struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, | |
13473 | u16 uplink_seid, u16 vsi_seid, | |
13474 | u8 enabled_tc) | |
13475 | { | |
13476 | struct i40e_veb *veb, *uplink_veb = NULL; | |
13477 | int vsi_idx, veb_idx; | |
13478 | int ret; | |
13479 | ||
13480 | /* if one seid is 0, the other must be 0 to create a floating relay */ | |
13481 | if ((uplink_seid == 0 || vsi_seid == 0) && | |
13482 | (uplink_seid + vsi_seid != 0)) { | |
13483 | dev_info(&pf->pdev->dev, | |
13484 | "one, not both seid's are 0: uplink=%d vsi=%d\n", | |
13485 | uplink_seid, vsi_seid); | |
13486 | return NULL; | |
13487 | } | |
13488 | ||
13489 | /* make sure there is such a vsi and uplink */ | |
505682cd | 13490 | for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++) |
41c445ff JB |
13491 | if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid) |
13492 | break; | |
cfe39699 | 13493 | if (vsi_idx == pf->num_alloc_vsi && vsi_seid != 0) { |
41c445ff JB |
13494 | dev_info(&pf->pdev->dev, "vsi seid %d not found\n", |
13495 | vsi_seid); | |
13496 | return NULL; | |
13497 | } | |
13498 | ||
13499 | if (uplink_seid && uplink_seid != pf->mac_seid) { | |
13500 | for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { | |
13501 | if (pf->veb[veb_idx] && | |
13502 | pf->veb[veb_idx]->seid == uplink_seid) { | |
13503 | uplink_veb = pf->veb[veb_idx]; | |
13504 | break; | |
13505 | } | |
13506 | } | |
13507 | if (!uplink_veb) { | |
13508 | dev_info(&pf->pdev->dev, | |
13509 | "uplink seid %d not found\n", uplink_seid); | |
13510 | return NULL; | |
13511 | } | |
13512 | } | |
13513 | ||
13514 | /* get veb sw struct */ | |
13515 | veb_idx = i40e_veb_mem_alloc(pf); | |
13516 | if (veb_idx < 0) | |
13517 | goto err_alloc; | |
13518 | veb = pf->veb[veb_idx]; | |
13519 | veb->flags = flags; | |
13520 | veb->uplink_seid = uplink_seid; | |
13521 | veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB); | |
13522 | veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1); | |
13523 | ||
13524 | /* create the VEB in the switch */ | |
13525 | ret = i40e_add_veb(veb, pf->vsi[vsi_idx]); | |
13526 | if (ret) | |
13527 | goto err_veb; | |
1bb8b935 SN |
13528 | if (vsi_idx == pf->lan_vsi) |
13529 | pf->lan_veb = veb->idx; | |
41c445ff JB |
13530 | |
13531 | return veb; | |
13532 | ||
13533 | err_veb: | |
13534 | i40e_veb_clear(veb); | |
13535 | err_alloc: | |
13536 | return NULL; | |
13537 | } | |
13538 | ||
13539 | /** | |
b40c82e6 | 13540 | * i40e_setup_pf_switch_element - set PF vars based on switch type |
41c445ff JB |
13541 | * @pf: board private structure |
13542 | * @ele: element we are building info from | |
13543 | * @num_reported: total number of elements | |
13544 | * @printconfig: should we print the contents | |
13545 | * | |
13546 | * helper function to assist in extracting a few useful SEID values. | |
13547 | **/ | |
13548 | static void i40e_setup_pf_switch_element(struct i40e_pf *pf, | |
13549 | struct i40e_aqc_switch_config_element_resp *ele, | |
13550 | u16 num_reported, bool printconfig) | |
13551 | { | |
13552 | u16 downlink_seid = le16_to_cpu(ele->downlink_seid); | |
13553 | u16 uplink_seid = le16_to_cpu(ele->uplink_seid); | |
13554 | u8 element_type = ele->element_type; | |
13555 | u16 seid = le16_to_cpu(ele->seid); | |
13556 | ||
13557 | if (printconfig) | |
13558 | dev_info(&pf->pdev->dev, | |
13559 | "type=%d seid=%d uplink=%d downlink=%d\n", | |
13560 | element_type, seid, uplink_seid, downlink_seid); | |
13561 | ||
13562 | switch (element_type) { | |
13563 | case I40E_SWITCH_ELEMENT_TYPE_MAC: | |
13564 | pf->mac_seid = seid; | |
13565 | break; | |
13566 | case I40E_SWITCH_ELEMENT_TYPE_VEB: | |
13567 | /* Main VEB? */ | |
13568 | if (uplink_seid != pf->mac_seid) | |
13569 | break; | |
13570 | if (pf->lan_veb == I40E_NO_VEB) { | |
13571 | int v; | |
13572 | ||
13573 | /* find existing or else empty VEB */ | |
13574 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
13575 | if (pf->veb[v] && (pf->veb[v]->seid == seid)) { | |
13576 | pf->lan_veb = v; | |
13577 | break; | |
13578 | } | |
13579 | } | |
13580 | if (pf->lan_veb == I40E_NO_VEB) { | |
13581 | v = i40e_veb_mem_alloc(pf); | |
13582 | if (v < 0) | |
13583 | break; | |
13584 | pf->lan_veb = v; | |
13585 | } | |
13586 | } | |
13587 | ||
13588 | pf->veb[pf->lan_veb]->seid = seid; | |
13589 | pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid; | |
13590 | pf->veb[pf->lan_veb]->pf = pf; | |
13591 | pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB; | |
13592 | break; | |
13593 | case I40E_SWITCH_ELEMENT_TYPE_VSI: | |
13594 | if (num_reported != 1) | |
13595 | break; | |
13596 | /* This is immediately after a reset so we can assume this is | |
13597 | * the PF's VSI | |
13598 | */ | |
13599 | pf->mac_seid = uplink_seid; | |
13600 | pf->pf_seid = downlink_seid; | |
13601 | pf->main_vsi_seid = seid; | |
13602 | if (printconfig) | |
13603 | dev_info(&pf->pdev->dev, | |
13604 | "pf_seid=%d main_vsi_seid=%d\n", | |
13605 | pf->pf_seid, pf->main_vsi_seid); | |
13606 | break; | |
13607 | case I40E_SWITCH_ELEMENT_TYPE_PF: | |
13608 | case I40E_SWITCH_ELEMENT_TYPE_VF: | |
13609 | case I40E_SWITCH_ELEMENT_TYPE_EMP: | |
13610 | case I40E_SWITCH_ELEMENT_TYPE_BMC: | |
13611 | case I40E_SWITCH_ELEMENT_TYPE_PE: | |
13612 | case I40E_SWITCH_ELEMENT_TYPE_PA: | |
13613 | /* ignore these for now */ | |
13614 | break; | |
13615 | default: | |
13616 | dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n", | |
13617 | element_type, seid); | |
13618 | break; | |
13619 | } | |
13620 | } | |
13621 | ||
13622 | /** | |
13623 | * i40e_fetch_switch_configuration - Get switch config from firmware | |
13624 | * @pf: board private structure | |
13625 | * @printconfig: should we print the contents | |
13626 | * | |
13627 | * Get the current switch configuration from the device and | |
13628 | * extract a few useful SEID values. | |
13629 | **/ | |
13630 | int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig) | |
13631 | { | |
13632 | struct i40e_aqc_get_switch_config_resp *sw_config; | |
13633 | u16 next_seid = 0; | |
13634 | int ret = 0; | |
13635 | u8 *aq_buf; | |
13636 | int i; | |
13637 | ||
13638 | aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL); | |
13639 | if (!aq_buf) | |
13640 | return -ENOMEM; | |
13641 | ||
13642 | sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; | |
13643 | do { | |
13644 | u16 num_reported, num_total; | |
13645 | ||
13646 | ret = i40e_aq_get_switch_config(&pf->hw, sw_config, | |
13647 | I40E_AQ_LARGE_BUF, | |
13648 | &next_seid, NULL); | |
13649 | if (ret) { | |
13650 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
13651 | "get switch config failed err %s aq_err %s\n", |
13652 | i40e_stat_str(&pf->hw, ret), | |
13653 | i40e_aq_str(&pf->hw, | |
13654 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
13655 | kfree(aq_buf); |
13656 | return -ENOENT; | |
13657 | } | |
13658 | ||
13659 | num_reported = le16_to_cpu(sw_config->header.num_reported); | |
13660 | num_total = le16_to_cpu(sw_config->header.num_total); | |
13661 | ||
13662 | if (printconfig) | |
13663 | dev_info(&pf->pdev->dev, | |
13664 | "header: %d reported %d total\n", | |
13665 | num_reported, num_total); | |
13666 | ||
41c445ff JB |
13667 | for (i = 0; i < num_reported; i++) { |
13668 | struct i40e_aqc_switch_config_element_resp *ele = | |
13669 | &sw_config->element[i]; | |
13670 | ||
13671 | i40e_setup_pf_switch_element(pf, ele, num_reported, | |
13672 | printconfig); | |
13673 | } | |
13674 | } while (next_seid != 0); | |
13675 | ||
13676 | kfree(aq_buf); | |
13677 | return ret; | |
13678 | } | |
13679 | ||
13680 | /** | |
13681 | * i40e_setup_pf_switch - Setup the HW switch on startup or after reset | |
13682 | * @pf: board private structure | |
bc7d338f | 13683 | * @reinit: if the Main VSI needs to re-initialized. |
41c445ff JB |
13684 | * |
13685 | * Returns 0 on success, negative value on failure | |
13686 | **/ | |
bc7d338f | 13687 | static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit) |
41c445ff | 13688 | { |
b5569892 | 13689 | u16 flags = 0; |
41c445ff JB |
13690 | int ret; |
13691 | ||
13692 | /* find out what's out there already */ | |
13693 | ret = i40e_fetch_switch_configuration(pf, false); | |
13694 | if (ret) { | |
13695 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
13696 | "couldn't fetch switch config, err %s aq_err %s\n", |
13697 | i40e_stat_str(&pf->hw, ret), | |
13698 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
13699 | return ret; |
13700 | } | |
13701 | i40e_pf_reset_stats(pf); | |
13702 | ||
b5569892 ASJ |
13703 | /* set the switch config bit for the whole device to |
13704 | * support limited promisc or true promisc | |
13705 | * when user requests promisc. The default is limited | |
13706 | * promisc. | |
13707 | */ | |
13708 | ||
13709 | if ((pf->hw.pf_id == 0) && | |
2f4b411a | 13710 | !(pf->flags & I40E_FLAG_TRUE_PROMISC_SUPPORT)) { |
b5569892 | 13711 | flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; |
2f4b411a AN |
13712 | pf->last_sw_conf_flags = flags; |
13713 | } | |
b5569892 ASJ |
13714 | |
13715 | if (pf->hw.pf_id == 0) { | |
13716 | u16 valid_flags; | |
13717 | ||
13718 | valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; | |
5efe0c6c | 13719 | ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags, 0, |
b5569892 ASJ |
13720 | NULL); |
13721 | if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) { | |
13722 | dev_info(&pf->pdev->dev, | |
13723 | "couldn't set switch config bits, err %s aq_err %s\n", | |
13724 | i40e_stat_str(&pf->hw, ret), | |
13725 | i40e_aq_str(&pf->hw, | |
13726 | pf->hw.aq.asq_last_status)); | |
13727 | /* not a fatal problem, just keep going */ | |
13728 | } | |
2f4b411a | 13729 | pf->last_sw_conf_valid_flags = valid_flags; |
b5569892 ASJ |
13730 | } |
13731 | ||
41c445ff | 13732 | /* first time setup */ |
bc7d338f | 13733 | if (pf->lan_vsi == I40E_NO_VSI || reinit) { |
41c445ff JB |
13734 | struct i40e_vsi *vsi = NULL; |
13735 | u16 uplink_seid; | |
13736 | ||
13737 | /* Set up the PF VSI associated with the PF's main VSI | |
13738 | * that is already in the HW switch | |
13739 | */ | |
13740 | if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb]) | |
13741 | uplink_seid = pf->veb[pf->lan_veb]->seid; | |
13742 | else | |
13743 | uplink_seid = pf->mac_seid; | |
bc7d338f ASJ |
13744 | if (pf->lan_vsi == I40E_NO_VSI) |
13745 | vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0); | |
13746 | else if (reinit) | |
13747 | vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]); | |
41c445ff JB |
13748 | if (!vsi) { |
13749 | dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n"); | |
aaf66502 | 13750 | i40e_cloud_filter_exit(pf); |
41c445ff JB |
13751 | i40e_fdir_teardown(pf); |
13752 | return -EAGAIN; | |
13753 | } | |
41c445ff JB |
13754 | } else { |
13755 | /* force a reset of TC and queue layout configurations */ | |
13756 | u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; | |
6995b36c | 13757 | |
41c445ff JB |
13758 | pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; |
13759 | pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; | |
13760 | i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); | |
13761 | } | |
13762 | i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]); | |
13763 | ||
cbf61325 ASJ |
13764 | i40e_fdir_sb_setup(pf); |
13765 | ||
41c445ff JB |
13766 | /* Setup static PF queue filter control settings */ |
13767 | ret = i40e_setup_pf_filter_control(pf); | |
13768 | if (ret) { | |
13769 | dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n", | |
13770 | ret); | |
13771 | /* Failure here should not stop continuing other steps */ | |
13772 | } | |
13773 | ||
13774 | /* enable RSS in the HW, even for only one queue, as the stack can use | |
13775 | * the hash | |
13776 | */ | |
13777 | if ((pf->flags & I40E_FLAG_RSS_ENABLED)) | |
043dd650 | 13778 | i40e_pf_config_rss(pf); |
41c445ff JB |
13779 | |
13780 | /* fill in link information and enable LSE reporting */ | |
a34a6711 MW |
13781 | i40e_link_event(pf); |
13782 | ||
d52c20b7 | 13783 | /* Initialize user-specific link properties */ |
41c445ff JB |
13784 | pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info & |
13785 | I40E_AQ_AN_COMPLETED) ? true : false); | |
d52c20b7 | 13786 | |
beb0dff1 JK |
13787 | i40e_ptp_init(pf); |
13788 | ||
1f190d93 AD |
13789 | /* repopulate tunnel port filters */ |
13790 | i40e_sync_udp_filters(pf); | |
13791 | ||
41c445ff JB |
13792 | return ret; |
13793 | } | |
13794 | ||
41c445ff JB |
13795 | /** |
13796 | * i40e_determine_queue_usage - Work out queue distribution | |
13797 | * @pf: board private structure | |
13798 | **/ | |
13799 | static void i40e_determine_queue_usage(struct i40e_pf *pf) | |
13800 | { | |
41c445ff | 13801 | int queues_left; |
e50d5751 | 13802 | int q_max; |
41c445ff JB |
13803 | |
13804 | pf->num_lan_qps = 0; | |
41c445ff JB |
13805 | |
13806 | /* Find the max queues to be put into basic use. We'll always be | |
13807 | * using TC0, whether or not DCB is running, and TC0 will get the | |
13808 | * big RSS set. | |
13809 | */ | |
13810 | queues_left = pf->hw.func_caps.num_tx_qp; | |
13811 | ||
cbf61325 | 13812 | if ((queues_left == 1) || |
9aa7e935 | 13813 | !(pf->flags & I40E_FLAG_MSIX_ENABLED)) { |
41c445ff JB |
13814 | /* one qp for PF, no queues for anything else */ |
13815 | queues_left = 0; | |
acd65448 | 13816 | pf->alloc_rss_size = pf->num_lan_qps = 1; |
41c445ff JB |
13817 | |
13818 | /* make sure all the fancies are disabled */ | |
60ea5f83 | 13819 | pf->flags &= ~(I40E_FLAG_RSS_ENABLED | |
e3219ce6 | 13820 | I40E_FLAG_IWARP_ENABLED | |
60ea5f83 JB |
13821 | I40E_FLAG_FD_SB_ENABLED | |
13822 | I40E_FLAG_FD_ATR_ENABLED | | |
4d9b6043 | 13823 | I40E_FLAG_DCB_CAPABLE | |
a036244c | 13824 | I40E_FLAG_DCB_ENABLED | |
60ea5f83 JB |
13825 | I40E_FLAG_SRIOV_ENABLED | |
13826 | I40E_FLAG_VMDQ_ENABLED); | |
2f4b411a | 13827 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
9aa7e935 FZ |
13828 | } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED | |
13829 | I40E_FLAG_FD_SB_ENABLED | | |
bbe7d0e0 | 13830 | I40E_FLAG_FD_ATR_ENABLED | |
4d9b6043 | 13831 | I40E_FLAG_DCB_CAPABLE))) { |
9aa7e935 | 13832 | /* one qp for PF */ |
acd65448 | 13833 | pf->alloc_rss_size = pf->num_lan_qps = 1; |
9aa7e935 FZ |
13834 | queues_left -= pf->num_lan_qps; |
13835 | ||
13836 | pf->flags &= ~(I40E_FLAG_RSS_ENABLED | | |
e3219ce6 | 13837 | I40E_FLAG_IWARP_ENABLED | |
9aa7e935 FZ |
13838 | I40E_FLAG_FD_SB_ENABLED | |
13839 | I40E_FLAG_FD_ATR_ENABLED | | |
13840 | I40E_FLAG_DCB_ENABLED | | |
13841 | I40E_FLAG_VMDQ_ENABLED); | |
2f4b411a | 13842 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
41c445ff | 13843 | } else { |
cbf61325 | 13844 | /* Not enough queues for all TCs */ |
4d9b6043 | 13845 | if ((pf->flags & I40E_FLAG_DCB_CAPABLE) && |
cbf61325 | 13846 | (queues_left < I40E_MAX_TRAFFIC_CLASS)) { |
a036244c DE |
13847 | pf->flags &= ~(I40E_FLAG_DCB_CAPABLE | |
13848 | I40E_FLAG_DCB_ENABLED); | |
cbf61325 ASJ |
13849 | dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n"); |
13850 | } | |
e50d5751 SN |
13851 | |
13852 | /* limit lan qps to the smaller of qps, cpus or msix */ | |
13853 | q_max = max_t(int, pf->rss_size_max, num_online_cpus()); | |
13854 | q_max = min_t(int, q_max, pf->hw.func_caps.num_tx_qp); | |
13855 | q_max = min_t(int, q_max, pf->hw.func_caps.num_msix_vectors); | |
13856 | pf->num_lan_qps = q_max; | |
9a3bd2f1 | 13857 | |
cbf61325 ASJ |
13858 | queues_left -= pf->num_lan_qps; |
13859 | } | |
13860 | ||
13861 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
13862 | if (queues_left > 1) { | |
13863 | queues_left -= 1; /* save 1 queue for FD */ | |
13864 | } else { | |
13865 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
2f4b411a | 13866 | pf->flags |= I40E_FLAG_FD_SB_INACTIVE; |
cbf61325 ASJ |
13867 | dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n"); |
13868 | } | |
41c445ff JB |
13869 | } |
13870 | ||
13871 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
13872 | pf->num_vf_qps && pf->num_req_vfs && queues_left) { | |
cbf61325 ASJ |
13873 | pf->num_req_vfs = min_t(int, pf->num_req_vfs, |
13874 | (queues_left / pf->num_vf_qps)); | |
41c445ff JB |
13875 | queues_left -= (pf->num_req_vfs * pf->num_vf_qps); |
13876 | } | |
13877 | ||
13878 | if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && | |
13879 | pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) { | |
13880 | pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis, | |
13881 | (queues_left / pf->num_vmdq_qps)); | |
13882 | queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps); | |
13883 | } | |
13884 | ||
f8ff1464 | 13885 | pf->queues_left = queues_left; |
8279e495 NP |
13886 | dev_dbg(&pf->pdev->dev, |
13887 | "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n", | |
13888 | pf->hw.func_caps.num_tx_qp, | |
13889 | !!(pf->flags & I40E_FLAG_FD_SB_ENABLED), | |
acd65448 HZ |
13890 | pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs, |
13891 | pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps, | |
13892 | queues_left); | |
41c445ff JB |
13893 | } |
13894 | ||
13895 | /** | |
13896 | * i40e_setup_pf_filter_control - Setup PF static filter control | |
13897 | * @pf: PF to be setup | |
13898 | * | |
b40c82e6 | 13899 | * i40e_setup_pf_filter_control sets up a PF's initial filter control |
41c445ff JB |
13900 | * settings. If PE/FCoE are enabled then it will also set the per PF |
13901 | * based filter sizes required for them. It also enables Flow director, | |
13902 | * ethertype and macvlan type filter settings for the pf. | |
13903 | * | |
13904 | * Returns 0 on success, negative on failure | |
13905 | **/ | |
13906 | static int i40e_setup_pf_filter_control(struct i40e_pf *pf) | |
13907 | { | |
13908 | struct i40e_filter_control_settings *settings = &pf->filter_settings; | |
13909 | ||
13910 | settings->hash_lut_size = I40E_HASH_LUT_SIZE_128; | |
13911 | ||
13912 | /* Flow Director is enabled */ | |
60ea5f83 | 13913 | if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)) |
41c445ff JB |
13914 | settings->enable_fdir = true; |
13915 | ||
13916 | /* Ethtype and MACVLAN filters enabled for PF */ | |
13917 | settings->enable_ethtype = true; | |
13918 | settings->enable_macvlan = true; | |
13919 | ||
13920 | if (i40e_set_filter_control(&pf->hw, settings)) | |
13921 | return -ENOENT; | |
13922 | ||
13923 | return 0; | |
13924 | } | |
13925 | ||
0c22b3dd | 13926 | #define INFO_STRING_LEN 255 |
7fd89545 | 13927 | #define REMAIN(__x) (INFO_STRING_LEN - (__x)) |
0c22b3dd JB |
13928 | static void i40e_print_features(struct i40e_pf *pf) |
13929 | { | |
13930 | struct i40e_hw *hw = &pf->hw; | |
3b195843 JP |
13931 | char *buf; |
13932 | int i; | |
0c22b3dd | 13933 | |
3b195843 JP |
13934 | buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL); |
13935 | if (!buf) | |
0c22b3dd | 13936 | return; |
0c22b3dd | 13937 | |
3b195843 | 13938 | i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id); |
0c22b3dd | 13939 | #ifdef CONFIG_PCI_IOV |
3b195843 | 13940 | i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs); |
0c22b3dd | 13941 | #endif |
1a557afc | 13942 | i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d", |
7fd89545 | 13943 | pf->hw.func_caps.num_vsis, |
1a557afc | 13944 | pf->vsi[pf->lan_vsi]->num_queue_pairs); |
0c22b3dd | 13945 | if (pf->flags & I40E_FLAG_RSS_ENABLED) |
3b195843 | 13946 | i += snprintf(&buf[i], REMAIN(i), " RSS"); |
0c22b3dd | 13947 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) |
3b195843 | 13948 | i += snprintf(&buf[i], REMAIN(i), " FD_ATR"); |
c6423ff1 | 13949 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
3b195843 JP |
13950 | i += snprintf(&buf[i], REMAIN(i), " FD_SB"); |
13951 | i += snprintf(&buf[i], REMAIN(i), " NTUPLE"); | |
c6423ff1 | 13952 | } |
4d9b6043 | 13953 | if (pf->flags & I40E_FLAG_DCB_CAPABLE) |
3b195843 | 13954 | i += snprintf(&buf[i], REMAIN(i), " DCB"); |
3b195843 | 13955 | i += snprintf(&buf[i], REMAIN(i), " VxLAN"); |
6a899024 | 13956 | i += snprintf(&buf[i], REMAIN(i), " Geneve"); |
0c22b3dd | 13957 | if (pf->flags & I40E_FLAG_PTP) |
3b195843 | 13958 | i += snprintf(&buf[i], REMAIN(i), " PTP"); |
6dec1017 | 13959 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) |
3b195843 | 13960 | i += snprintf(&buf[i], REMAIN(i), " VEB"); |
6dec1017 | 13961 | else |
3b195843 | 13962 | i += snprintf(&buf[i], REMAIN(i), " VEPA"); |
0c22b3dd | 13963 | |
3b195843 JP |
13964 | dev_info(&pf->pdev->dev, "%s\n", buf); |
13965 | kfree(buf); | |
7fd89545 | 13966 | WARN_ON(i > INFO_STRING_LEN); |
0c22b3dd JB |
13967 | } |
13968 | ||
b499ffb0 SV |
13969 | /** |
13970 | * i40e_get_platform_mac_addr - get platform-specific MAC address | |
b499ffb0 SV |
13971 | * @pdev: PCI device information struct |
13972 | * @pf: board private structure | |
13973 | * | |
41c4c2b5 JK |
13974 | * Look up the MAC address for the device. First we'll try |
13975 | * eth_platform_get_mac_address, which will check Open Firmware, or arch | |
13976 | * specific fallback. Otherwise, we'll default to the stored value in | |
13977 | * firmware. | |
b499ffb0 SV |
13978 | **/ |
13979 | static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf) | |
13980 | { | |
41c4c2b5 JK |
13981 | if (eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr)) |
13982 | i40e_get_mac_addr(&pf->hw, pf->hw.mac.addr); | |
b499ffb0 SV |
13983 | } |
13984 | ||
1d963401 DD |
13985 | /** |
13986 | * i40e_set_fec_in_flags - helper function for setting FEC options in flags | |
13987 | * @fec_cfg: FEC option to set in flags | |
13988 | * @flags: ptr to flags in which we set FEC option | |
13989 | **/ | |
13990 | void i40e_set_fec_in_flags(u8 fec_cfg, u32 *flags) | |
13991 | { | |
13992 | if (fec_cfg & I40E_AQ_SET_FEC_AUTO) | |
13993 | *flags |= I40E_FLAG_RS_FEC | I40E_FLAG_BASE_R_FEC; | |
13994 | if ((fec_cfg & I40E_AQ_SET_FEC_REQUEST_RS) || | |
13995 | (fec_cfg & I40E_AQ_SET_FEC_ABILITY_RS)) { | |
13996 | *flags |= I40E_FLAG_RS_FEC; | |
13997 | *flags &= ~I40E_FLAG_BASE_R_FEC; | |
13998 | } | |
13999 | if ((fec_cfg & I40E_AQ_SET_FEC_REQUEST_KR) || | |
14000 | (fec_cfg & I40E_AQ_SET_FEC_ABILITY_KR)) { | |
14001 | *flags |= I40E_FLAG_BASE_R_FEC; | |
14002 | *flags &= ~I40E_FLAG_RS_FEC; | |
14003 | } | |
14004 | if (fec_cfg == 0) | |
14005 | *flags &= ~(I40E_FLAG_RS_FEC | I40E_FLAG_BASE_R_FEC); | |
14006 | } | |
14007 | ||
4ff0ee1a AM |
14008 | /** |
14009 | * i40e_check_recovery_mode - check if we are running transition firmware | |
14010 | * @pf: board private structure | |
14011 | * | |
14012 | * Check registers indicating the firmware runs in recovery mode. Sets the | |
14013 | * appropriate driver state. | |
14014 | * | |
14015 | * Returns true if the recovery mode was detected, false otherwise | |
14016 | **/ | |
14017 | static bool i40e_check_recovery_mode(struct i40e_pf *pf) | |
14018 | { | |
14019 | u32 val = rd32(&pf->hw, I40E_GL_FWSTS); | |
14020 | ||
14021 | if (val & I40E_GL_FWSTS_FWS1B_MASK) { | |
14022 | dev_notice(&pf->pdev->dev, "Firmware recovery mode detected. Limiting functionality.\n"); | |
14023 | dev_notice(&pf->pdev->dev, "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n"); | |
14024 | set_bit(__I40E_RECOVERY_MODE, pf->state); | |
14025 | ||
14026 | return true; | |
14027 | } | |
14028 | if (test_and_clear_bit(__I40E_RECOVERY_MODE, pf->state)) | |
14029 | dev_info(&pf->pdev->dev, "Reinitializing in normal mode with full functionality.\n"); | |
14030 | ||
14031 | return false; | |
14032 | } | |
14033 | ||
14034 | /** | |
14035 | * i40e_init_recovery_mode - initialize subsystems needed in recovery mode | |
14036 | * @pf: board private structure | |
14037 | * @hw: ptr to the hardware info | |
14038 | * | |
14039 | * This function does a minimal setup of all subsystems needed for running | |
14040 | * recovery mode. | |
14041 | * | |
14042 | * Returns 0 on success, negative on failure | |
14043 | **/ | |
14044 | static int i40e_init_recovery_mode(struct i40e_pf *pf, struct i40e_hw *hw) | |
14045 | { | |
14046 | struct i40e_vsi *vsi; | |
14047 | int err; | |
14048 | int v_idx; | |
14049 | ||
14050 | pci_save_state(pf->pdev); | |
14051 | ||
14052 | /* set up periodic task facility */ | |
14053 | timer_setup(&pf->service_timer, i40e_service_timer, 0); | |
14054 | pf->service_timer_period = HZ; | |
14055 | ||
14056 | INIT_WORK(&pf->service_task, i40e_service_task); | |
14057 | clear_bit(__I40E_SERVICE_SCHED, pf->state); | |
14058 | ||
14059 | err = i40e_init_interrupt_scheme(pf); | |
14060 | if (err) | |
14061 | goto err_switch_setup; | |
14062 | ||
14063 | /* The number of VSIs reported by the FW is the minimum guaranteed | |
14064 | * to us; HW supports far more and we share the remaining pool with | |
14065 | * the other PFs. We allocate space for more than the guarantee with | |
14066 | * the understanding that we might not get them all later. | |
14067 | */ | |
14068 | if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC) | |
14069 | pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC; | |
14070 | else | |
14071 | pf->num_alloc_vsi = pf->hw.func_caps.num_vsis; | |
14072 | ||
14073 | /* Set up the vsi struct and our local tracking of the MAIN PF vsi. */ | |
14074 | pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *), | |
14075 | GFP_KERNEL); | |
14076 | if (!pf->vsi) { | |
14077 | err = -ENOMEM; | |
14078 | goto err_switch_setup; | |
14079 | } | |
14080 | ||
14081 | /* We allocate one VSI which is needed as absolute minimum | |
14082 | * in order to register the netdev | |
14083 | */ | |
14084 | v_idx = i40e_vsi_mem_alloc(pf, I40E_VSI_MAIN); | |
14085 | if (v_idx < 0) | |
14086 | goto err_switch_setup; | |
14087 | pf->lan_vsi = v_idx; | |
14088 | vsi = pf->vsi[v_idx]; | |
14089 | if (!vsi) | |
14090 | goto err_switch_setup; | |
14091 | vsi->alloc_queue_pairs = 1; | |
14092 | err = i40e_config_netdev(vsi); | |
14093 | if (err) | |
14094 | goto err_switch_setup; | |
14095 | err = register_netdev(vsi->netdev); | |
14096 | if (err) | |
14097 | goto err_switch_setup; | |
14098 | vsi->netdev_registered = true; | |
14099 | i40e_dbg_pf_init(pf); | |
14100 | ||
14101 | err = i40e_setup_misc_vector_for_recovery_mode(pf); | |
14102 | if (err) | |
14103 | goto err_switch_setup; | |
14104 | ||
14105 | /* tell the firmware that we're starting */ | |
14106 | i40e_send_version(pf); | |
14107 | ||
14108 | /* since everything's happy, start the service_task timer */ | |
14109 | mod_timer(&pf->service_timer, | |
14110 | round_jiffies(jiffies + pf->service_timer_period)); | |
14111 | ||
14112 | return 0; | |
14113 | ||
14114 | err_switch_setup: | |
14115 | i40e_reset_interrupt_capability(pf); | |
14116 | del_timer_sync(&pf->service_timer); | |
14117 | i40e_shutdown_adminq(hw); | |
14118 | iounmap(hw->hw_addr); | |
14119 | pci_disable_pcie_error_reporting(pf->pdev); | |
14120 | pci_release_mem_regions(pf->pdev); | |
14121 | pci_disable_device(pf->pdev); | |
14122 | kfree(pf); | |
14123 | ||
14124 | return err; | |
14125 | } | |
14126 | ||
41c445ff JB |
14127 | /** |
14128 | * i40e_probe - Device initialization routine | |
14129 | * @pdev: PCI device information struct | |
14130 | * @ent: entry in i40e_pci_tbl | |
14131 | * | |
b40c82e6 JK |
14132 | * i40e_probe initializes a PF identified by a pci_dev structure. |
14133 | * The OS initialization, configuring of the PF private structure, | |
41c445ff JB |
14134 | * and a hardware reset occur. |
14135 | * | |
14136 | * Returns 0 on success, negative on failure | |
14137 | **/ | |
14138 | static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
14139 | { | |
e827845c | 14140 | struct i40e_aq_get_phy_abilities_resp abilities; |
41c445ff JB |
14141 | struct i40e_pf *pf; |
14142 | struct i40e_hw *hw; | |
93cd765b | 14143 | static u16 pfs_found; |
1d5109d1 | 14144 | u16 wol_nvm_bits; |
d4dfb81a | 14145 | u16 link_status; |
6f66a484 | 14146 | int err; |
4f2f017c | 14147 | u32 val; |
8a9eb7d3 | 14148 | u32 i; |
58fc3267 | 14149 | u8 set_fc_aq_fail; |
41c445ff JB |
14150 | |
14151 | err = pci_enable_device_mem(pdev); | |
14152 | if (err) | |
14153 | return err; | |
14154 | ||
14155 | /* set up for high or low dma */ | |
6494294f | 14156 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
6494294f | 14157 | if (err) { |
e3e3bfdd JS |
14158 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
14159 | if (err) { | |
14160 | dev_err(&pdev->dev, | |
14161 | "DMA configuration failed: 0x%x\n", err); | |
14162 | goto err_dma; | |
14163 | } | |
41c445ff JB |
14164 | } |
14165 | ||
14166 | /* set up pci connections */ | |
56d766d6 | 14167 | err = pci_request_mem_regions(pdev, i40e_driver_name); |
41c445ff JB |
14168 | if (err) { |
14169 | dev_info(&pdev->dev, | |
14170 | "pci_request_selected_regions failed %d\n", err); | |
14171 | goto err_pci_reg; | |
14172 | } | |
14173 | ||
14174 | pci_enable_pcie_error_reporting(pdev); | |
14175 | pci_set_master(pdev); | |
14176 | ||
14177 | /* Now that we have a PCI connection, we need to do the | |
14178 | * low level device setup. This is primarily setting up | |
14179 | * the Admin Queue structures and then querying for the | |
14180 | * device's current profile information. | |
14181 | */ | |
14182 | pf = kzalloc(sizeof(*pf), GFP_KERNEL); | |
14183 | if (!pf) { | |
14184 | err = -ENOMEM; | |
14185 | goto err_pf_alloc; | |
14186 | } | |
14187 | pf->next_vsi = 0; | |
14188 | pf->pdev = pdev; | |
9e6c9c0f | 14189 | set_bit(__I40E_DOWN, pf->state); |
41c445ff JB |
14190 | |
14191 | hw = &pf->hw; | |
14192 | hw->back = pf; | |
232f4706 | 14193 | |
2ac8b675 SN |
14194 | pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0), |
14195 | I40E_MAX_CSR_SPACE); | |
232f4706 | 14196 | |
2ac8b675 | 14197 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len); |
41c445ff JB |
14198 | if (!hw->hw_addr) { |
14199 | err = -EIO; | |
14200 | dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n", | |
14201 | (unsigned int)pci_resource_start(pdev, 0), | |
2ac8b675 | 14202 | pf->ioremap_len, err); |
41c445ff JB |
14203 | goto err_ioremap; |
14204 | } | |
14205 | hw->vendor_id = pdev->vendor; | |
14206 | hw->device_id = pdev->device; | |
14207 | pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); | |
14208 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
14209 | hw->subsystem_device_id = pdev->subsystem_device; | |
14210 | hw->bus.device = PCI_SLOT(pdev->devfn); | |
14211 | hw->bus.func = PCI_FUNC(pdev->devfn); | |
b3f028fc | 14212 | hw->bus.bus_id = pdev->bus->number; |
93cd765b | 14213 | pf->instance = pfs_found; |
41c445ff | 14214 | |
ab243ec9 SP |
14215 | /* Select something other than the 802.1ad ethertype for the |
14216 | * switch to use internally and drop on ingress. | |
14217 | */ | |
14218 | hw->switch_tag = 0xffff; | |
14219 | hw->first_tag = ETH_P_8021AD; | |
14220 | hw->second_tag = ETH_P_8021Q; | |
14221 | ||
0e588de1 JK |
14222 | INIT_LIST_HEAD(&pf->l3_flex_pit_list); |
14223 | INIT_LIST_HEAD(&pf->l4_flex_pit_list); | |
cdc594e0 | 14224 | INIT_LIST_HEAD(&pf->ddp_old_prof); |
0e588de1 | 14225 | |
de03d2b0 SN |
14226 | /* set up the locks for the AQ, do this only once in probe |
14227 | * and destroy them only once in remove | |
14228 | */ | |
14229 | mutex_init(&hw->aq.asq_mutex); | |
14230 | mutex_init(&hw->aq.arq_mutex); | |
14231 | ||
5d4ca23e AD |
14232 | pf->msg_enable = netif_msg_init(debug, |
14233 | NETIF_MSG_DRV | | |
14234 | NETIF_MSG_PROBE | | |
14235 | NETIF_MSG_LINK); | |
14236 | if (debug < -1) | |
14237 | pf->hw.debug_mask = debug; | |
5b5faa43 | 14238 | |
7134f9ce JB |
14239 | /* do a special CORER for clearing PXE mode once at init */ |
14240 | if (hw->revision_id == 0 && | |
14241 | (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) { | |
14242 | wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK); | |
14243 | i40e_flush(hw); | |
14244 | msleep(200); | |
14245 | pf->corer_count++; | |
14246 | ||
14247 | i40e_clear_pxe_mode(hw); | |
14248 | } | |
14249 | ||
41c445ff | 14250 | /* Reset here to make sure all is clean and to define PF 'n' */ |
838d41d9 | 14251 | i40e_clear_hw(hw); |
4ff0ee1a AM |
14252 | if (!i40e_check_recovery_mode(pf)) { |
14253 | err = i40e_pf_reset(hw); | |
14254 | if (err) { | |
14255 | dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err); | |
14256 | goto err_pf_reset; | |
14257 | } | |
14258 | pf->pfr_count++; | |
41c445ff | 14259 | } |
41c445ff JB |
14260 | hw->aq.num_arq_entries = I40E_AQ_LEN; |
14261 | hw->aq.num_asq_entries = I40E_AQ_LEN; | |
14262 | hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE; | |
14263 | hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE; | |
14264 | pf->adminq_work_limit = I40E_AQ_WORK_LIMIT; | |
b2008cbf | 14265 | |
b294ac70 | 14266 | snprintf(pf->int_name, sizeof(pf->int_name) - 1, |
b2008cbf CW |
14267 | "%s-%s:misc", |
14268 | dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev)); | |
41c445ff JB |
14269 | |
14270 | err = i40e_init_shared_code(hw); | |
14271 | if (err) { | |
b2a75c58 ASJ |
14272 | dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n", |
14273 | err); | |
41c445ff JB |
14274 | goto err_pf_reset; |
14275 | } | |
14276 | ||
d52c20b7 JB |
14277 | /* set up a default setting for link flow control */ |
14278 | pf->hw.fc.requested_mode = I40E_FC_NONE; | |
14279 | ||
41c445ff | 14280 | err = i40e_init_adminq(hw); |
2b2426a7 CW |
14281 | if (err) { |
14282 | if (err == I40E_ERR_FIRMWARE_API_VERSION) | |
14283 | dev_info(&pdev->dev, | |
4fb29bdd AL |
14284 | "The driver for the device stopped because the NVM image v%u.%u is newer than expected v%u.%u. You must install the most recent version of the network driver.\n", |
14285 | hw->aq.api_maj_ver, | |
14286 | hw->aq.api_min_ver, | |
14287 | I40E_FW_API_VERSION_MAJOR, | |
14288 | I40E_FW_MINOR_VERSION(hw)); | |
2b2426a7 CW |
14289 | else |
14290 | dev_info(&pdev->dev, | |
14291 | "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n"); | |
14292 | ||
14293 | goto err_pf_reset; | |
14294 | } | |
5bbb2e20 | 14295 | i40e_get_oem_version(hw); |
f0b44440 | 14296 | |
a121644c SA |
14297 | /* provide nvm, fw, api versions, vendor:device id, subsys vendor:device id */ |
14298 | dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s [%04x:%04x] [%04x:%04x]\n", | |
6dec1017 SN |
14299 | hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build, |
14300 | hw->aq.api_maj_ver, hw->aq.api_min_ver, | |
a121644c SA |
14301 | i40e_nvm_version_str(hw), hw->vendor_id, hw->device_id, |
14302 | hw->subsystem_vendor_id, hw->subsystem_device_id); | |
f0b44440 | 14303 | |
7aa67613 | 14304 | if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && |
22b96551 | 14305 | hw->aq.api_min_ver > I40E_FW_MINOR_VERSION(hw)) |
278b6f62 | 14306 | dev_info(&pdev->dev, |
4fb29bdd AL |
14307 | "The driver for the device detected a newer version of the NVM image v%u.%u than expected v%u.%u. Please install the most recent version of the network driver.\n", |
14308 | hw->aq.api_maj_ver, | |
14309 | hw->aq.api_min_ver, | |
14310 | I40E_FW_API_VERSION_MAJOR, | |
14311 | I40E_FW_MINOR_VERSION(hw)); | |
e04ea002 | 14312 | else if (hw->aq.api_maj_ver == 1 && hw->aq.api_min_ver < 4) |
278b6f62 | 14313 | dev_info(&pdev->dev, |
4fb29bdd AL |
14314 | "The driver for the device detected an older version of the NVM image v%u.%u than expected v%u.%u. Please update the NVM image.\n", |
14315 | hw->aq.api_maj_ver, | |
14316 | hw->aq.api_min_ver, | |
14317 | I40E_FW_API_VERSION_MAJOR, | |
14318 | I40E_FW_MINOR_VERSION(hw)); | |
278b6f62 | 14319 | |
4eb3f768 SN |
14320 | i40e_verify_eeprom(pf); |
14321 | ||
2c5fe33b JB |
14322 | /* Rev 0 hardware was never productized */ |
14323 | if (hw->revision_id < 1) | |
14324 | dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n"); | |
14325 | ||
6ff4ef86 | 14326 | i40e_clear_pxe_mode(hw); |
4ff0ee1a | 14327 | |
2f4b411a | 14328 | err = i40e_get_capabilities(pf, i40e_aqc_opc_list_func_capabilities); |
41c445ff JB |
14329 | if (err) |
14330 | goto err_adminq_setup; | |
14331 | ||
14332 | err = i40e_sw_init(pf); | |
14333 | if (err) { | |
14334 | dev_info(&pdev->dev, "sw_init failed: %d\n", err); | |
14335 | goto err_sw_init; | |
14336 | } | |
14337 | ||
4ff0ee1a AM |
14338 | if (test_bit(__I40E_RECOVERY_MODE, pf->state)) |
14339 | return i40e_init_recovery_mode(pf, hw); | |
14340 | ||
41c445ff | 14341 | err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, |
c76cb6ed | 14342 | hw->func_caps.num_rx_qp, 0, 0); |
41c445ff JB |
14343 | if (err) { |
14344 | dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err); | |
14345 | goto err_init_lan_hmc; | |
14346 | } | |
14347 | ||
14348 | err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); | |
14349 | if (err) { | |
14350 | dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err); | |
14351 | err = -ENOENT; | |
14352 | goto err_configure_lan_hmc; | |
14353 | } | |
14354 | ||
b686ece5 NP |
14355 | /* Disable LLDP for NICs that have firmware versions lower than v4.3. |
14356 | * Ignore error return codes because if it was already disabled via | |
14357 | * hardware settings this will fail | |
14358 | */ | |
d36e41dc | 14359 | if (pf->hw_features & I40E_HW_STOP_FW_LLDP) { |
b686ece5 | 14360 | dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n"); |
c65e78f8 | 14361 | i40e_aq_stop_lldp(hw, true, false, NULL); |
b686ece5 NP |
14362 | } |
14363 | ||
b499ffb0 SV |
14364 | /* allow a platform config to override the HW addr */ |
14365 | i40e_get_platform_mac_addr(pdev, pf); | |
41c4c2b5 | 14366 | |
f62b5060 | 14367 | if (!is_valid_ether_addr(hw->mac.addr)) { |
41c445ff JB |
14368 | dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr); |
14369 | err = -EIO; | |
14370 | goto err_mac_addr; | |
14371 | } | |
14372 | dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr); | |
9a173901 | 14373 | ether_addr_copy(hw->mac.perm_addr, hw->mac.addr); |
1f224ad2 NP |
14374 | i40e_get_port_mac_addr(hw, hw->mac.port_addr); |
14375 | if (is_valid_ether_addr(hw->mac.port_addr)) | |
d36e41dc | 14376 | pf->hw_features |= I40E_HW_PORT_ID_VALID; |
41c445ff JB |
14377 | |
14378 | pci_set_drvdata(pdev, pf); | |
14379 | pci_save_state(pdev); | |
c61c8fe1 DE |
14380 | |
14381 | /* Enable FW to write default DCB config on link-up */ | |
14382 | i40e_aq_set_dcb_parameters(hw, true, NULL); | |
14383 | ||
4e3b35b0 NP |
14384 | #ifdef CONFIG_I40E_DCB |
14385 | err = i40e_init_pf_dcb(pf); | |
14386 | if (err) { | |
aebfc816 | 14387 | dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err); |
c17ef430 | 14388 | pf->flags &= ~(I40E_FLAG_DCB_CAPABLE | I40E_FLAG_DCB_ENABLED); |
014269ff | 14389 | /* Continue without DCB enabled */ |
4e3b35b0 NP |
14390 | } |
14391 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
14392 | |
14393 | /* set up periodic task facility */ | |
26566eae | 14394 | timer_setup(&pf->service_timer, i40e_service_timer, 0); |
41c445ff JB |
14395 | pf->service_timer_period = HZ; |
14396 | ||
14397 | INIT_WORK(&pf->service_task, i40e_service_task); | |
0da36b97 | 14398 | clear_bit(__I40E_SERVICE_SCHED, pf->state); |
41c445ff | 14399 | |
1d5109d1 SN |
14400 | /* NVM bit on means WoL disabled for the port */ |
14401 | i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits); | |
75f5cea9 | 14402 | if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1) |
1d5109d1 SN |
14403 | pf->wol_en = false; |
14404 | else | |
14405 | pf->wol_en = true; | |
8e2773ae SN |
14406 | device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en); |
14407 | ||
41c445ff JB |
14408 | /* set up the main switch operations */ |
14409 | i40e_determine_queue_usage(pf); | |
c1147280 JB |
14410 | err = i40e_init_interrupt_scheme(pf); |
14411 | if (err) | |
14412 | goto err_switch_setup; | |
41c445ff | 14413 | |
505682cd MW |
14414 | /* The number of VSIs reported by the FW is the minimum guaranteed |
14415 | * to us; HW supports far more and we share the remaining pool with | |
14416 | * the other PFs. We allocate space for more than the guarantee with | |
14417 | * the understanding that we might not get them all later. | |
41c445ff | 14418 | */ |
505682cd MW |
14419 | if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC) |
14420 | pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC; | |
14421 | else | |
14422 | pf->num_alloc_vsi = pf->hw.func_caps.num_vsis; | |
14423 | ||
14424 | /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */ | |
d17038d6 JB |
14425 | pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *), |
14426 | GFP_KERNEL); | |
ed87ac09 WY |
14427 | if (!pf->vsi) { |
14428 | err = -ENOMEM; | |
41c445ff | 14429 | goto err_switch_setup; |
ed87ac09 | 14430 | } |
41c445ff | 14431 | |
fa11cb3d ASJ |
14432 | #ifdef CONFIG_PCI_IOV |
14433 | /* prep for VF support */ | |
14434 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
14435 | (pf->flags & I40E_FLAG_MSIX_ENABLED) && | |
0da36b97 | 14436 | !test_bit(__I40E_BAD_EEPROM, pf->state)) { |
fa11cb3d ASJ |
14437 | if (pci_num_vf(pdev)) |
14438 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
14439 | } | |
14440 | #endif | |
bc7d338f | 14441 | err = i40e_setup_pf_switch(pf, false); |
41c445ff JB |
14442 | if (err) { |
14443 | dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err); | |
14444 | goto err_vsis; | |
14445 | } | |
8f88b303 | 14446 | INIT_LIST_HEAD(&pf->vsi[pf->lan_vsi]->ch_list); |
58fc3267 HZ |
14447 | |
14448 | /* Make sure flow control is set according to current settings */ | |
14449 | err = i40e_set_fc(hw, &set_fc_aq_fail, true); | |
14450 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET) | |
14451 | dev_dbg(&pf->pdev->dev, | |
14452 | "Set fc with err %s aq_err %s on get_phy_cap\n", | |
14453 | i40e_stat_str(hw, err), | |
14454 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
14455 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET) | |
14456 | dev_dbg(&pf->pdev->dev, | |
14457 | "Set fc with err %s aq_err %s on set_phy_config\n", | |
14458 | i40e_stat_str(hw, err), | |
14459 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
14460 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE) | |
14461 | dev_dbg(&pf->pdev->dev, | |
14462 | "Set fc with err %s aq_err %s on get_link_info\n", | |
14463 | i40e_stat_str(hw, err), | |
14464 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
14465 | ||
8a9eb7d3 | 14466 | /* if FDIR VSI was set up, start it now */ |
505682cd | 14467 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
8a9eb7d3 SN |
14468 | if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) { |
14469 | i40e_vsi_open(pf->vsi[i]); | |
14470 | break; | |
14471 | } | |
14472 | } | |
41c445ff | 14473 | |
2f0aff41 SN |
14474 | /* The driver only wants link up/down and module qualification |
14475 | * reports from firmware. Note the negative logic. | |
7e2453fe JB |
14476 | */ |
14477 | err = i40e_aq_set_phy_int_mask(&pf->hw, | |
2f0aff41 | 14478 | ~(I40E_AQ_EVENT_LINK_UPDOWN | |
867a79e3 | 14479 | I40E_AQ_EVENT_MEDIA_NA | |
2f0aff41 | 14480 | I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); |
7e2453fe | 14481 | if (err) |
f1c7e72e SN |
14482 | dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", |
14483 | i40e_stat_str(&pf->hw, err), | |
14484 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7e2453fe | 14485 | |
4f2f017c ASJ |
14486 | /* Reconfigure hardware for allowing smaller MSS in the case |
14487 | * of TSO, so that we avoid the MDD being fired and causing | |
14488 | * a reset in the case of small MSS+TSO. | |
14489 | */ | |
14490 | val = rd32(hw, I40E_REG_MSS); | |
14491 | if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { | |
14492 | val &= ~I40E_REG_MSS_MIN_MASK; | |
14493 | val |= I40E_64BYTE_MSS; | |
14494 | wr32(hw, I40E_REG_MSS, val); | |
14495 | } | |
14496 | ||
d36e41dc | 14497 | if (pf->hw_features & I40E_HW_RESTART_AUTONEG) { |
025b4a54 ASJ |
14498 | msleep(75); |
14499 | err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); | |
14500 | if (err) | |
f1c7e72e SN |
14501 | dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", |
14502 | i40e_stat_str(&pf->hw, err), | |
14503 | i40e_aq_str(&pf->hw, | |
14504 | pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 14505 | } |
41c445ff JB |
14506 | /* The main driver is (mostly) up and happy. We need to set this state |
14507 | * before setting up the misc vector or we get a race and the vector | |
14508 | * ends up disabled forever. | |
14509 | */ | |
9e6c9c0f | 14510 | clear_bit(__I40E_DOWN, pf->state); |
41c445ff JB |
14511 | |
14512 | /* In case of MSIX we are going to setup the misc vector right here | |
14513 | * to handle admin queue events etc. In case of legacy and MSI | |
14514 | * the misc functionality and queue processing is combined in | |
14515 | * the same vector and that gets setup at open. | |
14516 | */ | |
14517 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
14518 | err = i40e_setup_misc_vector(pf); | |
14519 | if (err) { | |
14520 | dev_info(&pdev->dev, | |
14521 | "setup of misc vector failed: %d\n", err); | |
14522 | goto err_vsis; | |
14523 | } | |
14524 | } | |
14525 | ||
df805f62 | 14526 | #ifdef CONFIG_PCI_IOV |
41c445ff JB |
14527 | /* prep for VF support */ |
14528 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
4eb3f768 | 14529 | (pf->flags & I40E_FLAG_MSIX_ENABLED) && |
0da36b97 | 14530 | !test_bit(__I40E_BAD_EEPROM, pf->state)) { |
41c445ff JB |
14531 | /* disable link interrupts for VFs */ |
14532 | val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM); | |
14533 | val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK; | |
14534 | wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val); | |
14535 | i40e_flush(hw); | |
4aeec010 MW |
14536 | |
14537 | if (pci_num_vf(pdev)) { | |
14538 | dev_info(&pdev->dev, | |
14539 | "Active VFs found, allocating resources.\n"); | |
14540 | err = i40e_alloc_vfs(pf, pci_num_vf(pdev)); | |
14541 | if (err) | |
14542 | dev_info(&pdev->dev, | |
14543 | "Error %d allocating resources for existing VFs\n", | |
14544 | err); | |
14545 | } | |
41c445ff | 14546 | } |
df805f62 | 14547 | #endif /* CONFIG_PCI_IOV */ |
41c445ff | 14548 | |
e3219ce6 ASJ |
14549 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
14550 | pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile, | |
14551 | pf->num_iwarp_msix, | |
14552 | I40E_IWARP_IRQ_PILE_ID); | |
14553 | if (pf->iwarp_base_vector < 0) { | |
14554 | dev_info(&pdev->dev, | |
14555 | "failed to get tracking for %d vectors for IWARP err=%d\n", | |
14556 | pf->num_iwarp_msix, pf->iwarp_base_vector); | |
14557 | pf->flags &= ~I40E_FLAG_IWARP_ENABLED; | |
14558 | } | |
14559 | } | |
93cd765b | 14560 | |
41c445ff JB |
14561 | i40e_dbg_pf_init(pf); |
14562 | ||
14563 | /* tell the firmware that we're starting */ | |
44033fac | 14564 | i40e_send_version(pf); |
41c445ff JB |
14565 | |
14566 | /* since everything's happy, start the service_task timer */ | |
14567 | mod_timer(&pf->service_timer, | |
14568 | round_jiffies(jiffies + pf->service_timer_period)); | |
14569 | ||
e3219ce6 | 14570 | /* add this PF to client device list and launch a client service task */ |
004eb614 MW |
14571 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
14572 | err = i40e_lan_add_device(pf); | |
14573 | if (err) | |
14574 | dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n", | |
14575 | err); | |
14576 | } | |
e3219ce6 | 14577 | |
3fced535 ASJ |
14578 | #define PCI_SPEED_SIZE 8 |
14579 | #define PCI_WIDTH_SIZE 8 | |
14580 | /* Devices on the IOSF bus do not have this information | |
14581 | * and will report PCI Gen 1 x 1 by default so don't bother | |
14582 | * checking them. | |
14583 | */ | |
d36e41dc | 14584 | if (!(pf->hw_features & I40E_HW_NO_PCI_LINK_CHECK)) { |
3fced535 ASJ |
14585 | char speed[PCI_SPEED_SIZE] = "Unknown"; |
14586 | char width[PCI_WIDTH_SIZE] = "Unknown"; | |
14587 | ||
14588 | /* Get the negotiated link width and speed from PCI config | |
14589 | * space | |
14590 | */ | |
14591 | pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, | |
14592 | &link_status); | |
14593 | ||
14594 | i40e_set_pci_config_data(hw, link_status); | |
14595 | ||
14596 | switch (hw->bus.speed) { | |
14597 | case i40e_bus_speed_8000: | |
4ff2d854 | 14598 | strlcpy(speed, "8.0", PCI_SPEED_SIZE); break; |
3fced535 | 14599 | case i40e_bus_speed_5000: |
4ff2d854 | 14600 | strlcpy(speed, "5.0", PCI_SPEED_SIZE); break; |
3fced535 | 14601 | case i40e_bus_speed_2500: |
4ff2d854 | 14602 | strlcpy(speed, "2.5", PCI_SPEED_SIZE); break; |
3fced535 ASJ |
14603 | default: |
14604 | break; | |
14605 | } | |
14606 | switch (hw->bus.width) { | |
14607 | case i40e_bus_width_pcie_x8: | |
4ff2d854 | 14608 | strlcpy(width, "8", PCI_WIDTH_SIZE); break; |
3fced535 | 14609 | case i40e_bus_width_pcie_x4: |
4ff2d854 | 14610 | strlcpy(width, "4", PCI_WIDTH_SIZE); break; |
3fced535 | 14611 | case i40e_bus_width_pcie_x2: |
4ff2d854 | 14612 | strlcpy(width, "2", PCI_WIDTH_SIZE); break; |
3fced535 | 14613 | case i40e_bus_width_pcie_x1: |
4ff2d854 | 14614 | strlcpy(width, "1", PCI_WIDTH_SIZE); break; |
3fced535 ASJ |
14615 | default: |
14616 | break; | |
14617 | } | |
14618 | ||
14619 | dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n", | |
14620 | speed, width); | |
14621 | ||
14622 | if (hw->bus.width < i40e_bus_width_pcie_x8 || | |
14623 | hw->bus.speed < i40e_bus_speed_8000) { | |
14624 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n"); | |
14625 | dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n"); | |
14626 | } | |
d4dfb81a CS |
14627 | } |
14628 | ||
e827845c CS |
14629 | /* get the requested speeds from the fw */ |
14630 | err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL); | |
14631 | if (err) | |
8279e495 NP |
14632 | dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n", |
14633 | i40e_stat_str(&pf->hw, err), | |
14634 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
e827845c CS |
14635 | pf->hw.phy.link_info.requested_speeds = abilities.link_speed; |
14636 | ||
1d963401 DD |
14637 | /* set the FEC config due to the board capabilities */ |
14638 | i40e_set_fec_in_flags(abilities.fec_cfg_curr_mod_ext_info, &pf->flags); | |
14639 | ||
fc72dbce CS |
14640 | /* get the supported phy types from the fw */ |
14641 | err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL); | |
14642 | if (err) | |
14643 | dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n", | |
14644 | i40e_stat_str(&pf->hw, err), | |
14645 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
fc72dbce | 14646 | |
e7358f54 ASJ |
14647 | /* Add a filter to drop all Flow control frames from any VSI from being |
14648 | * transmitted. By doing so we stop a malicious VF from sending out | |
14649 | * PAUSE or PFC frames and potentially controlling traffic for other | |
14650 | * PF/VF VSIs. | |
14651 | * The FW can still send Flow control frames if enabled. | |
14652 | */ | |
14653 | i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, | |
14654 | pf->main_vsi_seid); | |
14655 | ||
31b606d0 | 14656 | if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) || |
4f9b4307 | 14657 | (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4)) |
d36e41dc | 14658 | pf->hw_features |= I40E_HW_PHY_CONTROLS_LEDS; |
4ad9f4f9 | 14659 | if (pf->hw.device_id == I40E_DEV_ID_SFP_I_X722) |
d36e41dc | 14660 | pf->hw_features |= I40E_HW_HAVE_CRT_RETIMER; |
0c22b3dd JB |
14661 | /* print a string summarizing features */ |
14662 | i40e_print_features(pf); | |
14663 | ||
41c445ff JB |
14664 | return 0; |
14665 | ||
14666 | /* Unwind what we've done if something failed in the setup */ | |
14667 | err_vsis: | |
9e6c9c0f | 14668 | set_bit(__I40E_DOWN, pf->state); |
41c445ff JB |
14669 | i40e_clear_interrupt_scheme(pf); |
14670 | kfree(pf->vsi); | |
04b03013 SN |
14671 | err_switch_setup: |
14672 | i40e_reset_interrupt_capability(pf); | |
41c445ff JB |
14673 | del_timer_sync(&pf->service_timer); |
14674 | err_mac_addr: | |
14675 | err_configure_lan_hmc: | |
14676 | (void)i40e_shutdown_lan_hmc(hw); | |
14677 | err_init_lan_hmc: | |
14678 | kfree(pf->qp_pile); | |
41c445ff JB |
14679 | err_sw_init: |
14680 | err_adminq_setup: | |
41c445ff JB |
14681 | err_pf_reset: |
14682 | iounmap(hw->hw_addr); | |
14683 | err_ioremap: | |
14684 | kfree(pf); | |
14685 | err_pf_alloc: | |
14686 | pci_disable_pcie_error_reporting(pdev); | |
56d766d6 | 14687 | pci_release_mem_regions(pdev); |
41c445ff JB |
14688 | err_pci_reg: |
14689 | err_dma: | |
14690 | pci_disable_device(pdev); | |
14691 | return err; | |
14692 | } | |
14693 | ||
14694 | /** | |
14695 | * i40e_remove - Device removal routine | |
14696 | * @pdev: PCI device information struct | |
14697 | * | |
14698 | * i40e_remove is called by the PCI subsystem to alert the driver | |
14699 | * that is should release a PCI device. This could be caused by a | |
14700 | * Hot-Plug event, or because the driver is going to be removed from | |
14701 | * memory. | |
14702 | **/ | |
14703 | static void i40e_remove(struct pci_dev *pdev) | |
14704 | { | |
14705 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
bcab2db9 | 14706 | struct i40e_hw *hw = &pf->hw; |
41c445ff | 14707 | i40e_status ret_code; |
41c445ff JB |
14708 | int i; |
14709 | ||
14710 | i40e_dbg_pf_exit(pf); | |
14711 | ||
beb0dff1 JK |
14712 | i40e_ptp_stop(pf); |
14713 | ||
bcab2db9 | 14714 | /* Disable RSS in hw */ |
272cdaf2 SN |
14715 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0); |
14716 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0); | |
bcab2db9 | 14717 | |
41c445ff | 14718 | /* no more scheduling of any task */ |
0da36b97 | 14719 | set_bit(__I40E_SUSPENDED, pf->state); |
9e6c9c0f | 14720 | set_bit(__I40E_DOWN, pf->state); |
26566eae | 14721 | if (pf->service_timer.function) |
c99abb4c SN |
14722 | del_timer_sync(&pf->service_timer); |
14723 | if (pf->service_task.func) | |
14724 | cancel_work_sync(&pf->service_task); | |
41c445ff | 14725 | |
4ff0ee1a AM |
14726 | if (test_bit(__I40E_RECOVERY_MODE, pf->state)) { |
14727 | struct i40e_vsi *vsi = pf->vsi[0]; | |
14728 | ||
14729 | /* We know that we have allocated only one vsi for this PF, | |
14730 | * it was just for registering netdevice, so the interface | |
14731 | * could be visible in the 'ifconfig' output | |
14732 | */ | |
14733 | unregister_netdev(vsi->netdev); | |
14734 | free_netdev(vsi->netdev); | |
14735 | ||
14736 | goto unmap; | |
14737 | } | |
14738 | ||
921c467c MW |
14739 | /* Client close must be called explicitly here because the timer |
14740 | * has been stopped. | |
14741 | */ | |
14742 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false); | |
14743 | ||
eb2d80bc MW |
14744 | if (pf->flags & I40E_FLAG_SRIOV_ENABLED) { |
14745 | i40e_free_vfs(pf); | |
14746 | pf->flags &= ~I40E_FLAG_SRIOV_ENABLED; | |
14747 | } | |
14748 | ||
41c445ff JB |
14749 | i40e_fdir_teardown(pf); |
14750 | ||
14751 | /* If there is a switch structure or any orphans, remove them. | |
14752 | * This will leave only the PF's VSI remaining. | |
14753 | */ | |
14754 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
14755 | if (!pf->veb[i]) | |
14756 | continue; | |
14757 | ||
14758 | if (pf->veb[i]->uplink_seid == pf->mac_seid || | |
14759 | pf->veb[i]->uplink_seid == 0) | |
14760 | i40e_switch_branch_release(pf->veb[i]); | |
14761 | } | |
14762 | ||
14763 | /* Now we can shutdown the PF's VSI, just before we kill | |
14764 | * adminq and hmc. | |
14765 | */ | |
14766 | if (pf->vsi[pf->lan_vsi]) | |
14767 | i40e_vsi_release(pf->vsi[pf->lan_vsi]); | |
14768 | ||
aaf66502 AN |
14769 | i40e_cloud_filter_exit(pf); |
14770 | ||
e3219ce6 | 14771 | /* remove attached clients */ |
004eb614 MW |
14772 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
14773 | ret_code = i40e_lan_del_device(pf); | |
14774 | if (ret_code) | |
14775 | dev_warn(&pdev->dev, "Failed to delete client device: %d\n", | |
14776 | ret_code); | |
e3219ce6 ASJ |
14777 | } |
14778 | ||
41c445ff | 14779 | /* shutdown and destroy the HMC */ |
f734dfff JB |
14780 | if (hw->hmc.hmc_obj) { |
14781 | ret_code = i40e_shutdown_lan_hmc(hw); | |
60442dea SN |
14782 | if (ret_code) |
14783 | dev_warn(&pdev->dev, | |
14784 | "Failed to destroy the HMC resources: %d\n", | |
14785 | ret_code); | |
14786 | } | |
41c445ff | 14787 | |
4ff0ee1a AM |
14788 | unmap: |
14789 | /* Free MSI/legacy interrupt 0 when in recovery mode. */ | |
14790 | if (test_bit(__I40E_RECOVERY_MODE, pf->state) && | |
14791 | !(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
14792 | free_irq(pf->pdev->irq, pf); | |
14793 | ||
41c445ff | 14794 | /* shutdown the adminq */ |
ac9c5c6d | 14795 | i40e_shutdown_adminq(hw); |
41c445ff | 14796 | |
8ddb3326 JB |
14797 | /* destroy the locks only once, here */ |
14798 | mutex_destroy(&hw->aq.arq_mutex); | |
14799 | mutex_destroy(&hw->aq.asq_mutex); | |
14800 | ||
41c445ff | 14801 | /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */ |
5cba17b1 | 14802 | rtnl_lock(); |
41c445ff | 14803 | i40e_clear_interrupt_scheme(pf); |
505682cd | 14804 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff | 14805 | if (pf->vsi[i]) { |
4ff0ee1a AM |
14806 | if (!test_bit(__I40E_RECOVERY_MODE, pf->state)) |
14807 | i40e_vsi_clear_rings(pf->vsi[i]); | |
41c445ff JB |
14808 | i40e_vsi_clear(pf->vsi[i]); |
14809 | pf->vsi[i] = NULL; | |
14810 | } | |
14811 | } | |
5cba17b1 | 14812 | rtnl_unlock(); |
41c445ff JB |
14813 | |
14814 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
14815 | kfree(pf->veb[i]); | |
14816 | pf->veb[i] = NULL; | |
14817 | } | |
14818 | ||
14819 | kfree(pf->qp_pile); | |
41c445ff JB |
14820 | kfree(pf->vsi); |
14821 | ||
f734dfff | 14822 | iounmap(hw->hw_addr); |
41c445ff | 14823 | kfree(pf); |
56d766d6 | 14824 | pci_release_mem_regions(pdev); |
41c445ff JB |
14825 | |
14826 | pci_disable_pcie_error_reporting(pdev); | |
14827 | pci_disable_device(pdev); | |
14828 | } | |
14829 | ||
14830 | /** | |
14831 | * i40e_pci_error_detected - warning that something funky happened in PCI land | |
14832 | * @pdev: PCI device information struct | |
f5254429 | 14833 | * @error: the type of PCI error |
41c445ff JB |
14834 | * |
14835 | * Called to warn that something happened and the error handling steps | |
14836 | * are in progress. Allows the driver to quiesce things, be ready for | |
14837 | * remediation. | |
14838 | **/ | |
14839 | static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev, | |
14840 | enum pci_channel_state error) | |
14841 | { | |
14842 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
14843 | ||
14844 | dev_info(&pdev->dev, "%s: error %d\n", __func__, error); | |
14845 | ||
edfc23ee GP |
14846 | if (!pf) { |
14847 | dev_info(&pdev->dev, | |
14848 | "Cannot recover - error happened during device probe\n"); | |
14849 | return PCI_ERS_RESULT_DISCONNECT; | |
14850 | } | |
14851 | ||
41c445ff | 14852 | /* shutdown all operations */ |
dfc4ff64 JK |
14853 | if (!test_bit(__I40E_SUSPENDED, pf->state)) |
14854 | i40e_prep_for_reset(pf, false); | |
41c445ff JB |
14855 | |
14856 | /* Request a slot reset */ | |
14857 | return PCI_ERS_RESULT_NEED_RESET; | |
14858 | } | |
14859 | ||
14860 | /** | |
14861 | * i40e_pci_error_slot_reset - a PCI slot reset just happened | |
14862 | * @pdev: PCI device information struct | |
14863 | * | |
14864 | * Called to find if the driver can work with the device now that | |
14865 | * the pci slot has been reset. If a basic connection seems good | |
14866 | * (registers are readable and have sane content) then return a | |
14867 | * happy little PCI_ERS_RESULT_xxx. | |
14868 | **/ | |
14869 | static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev) | |
14870 | { | |
14871 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
14872 | pci_ers_result_t result; | |
41c445ff JB |
14873 | u32 reg; |
14874 | ||
fb43201f | 14875 | dev_dbg(&pdev->dev, "%s\n", __func__); |
41c445ff JB |
14876 | if (pci_enable_device_mem(pdev)) { |
14877 | dev_info(&pdev->dev, | |
14878 | "Cannot re-enable PCI device after reset.\n"); | |
14879 | result = PCI_ERS_RESULT_DISCONNECT; | |
14880 | } else { | |
14881 | pci_set_master(pdev); | |
14882 | pci_restore_state(pdev); | |
14883 | pci_save_state(pdev); | |
14884 | pci_wake_from_d3(pdev, false); | |
14885 | ||
14886 | reg = rd32(&pf->hw, I40E_GLGEN_RTRIG); | |
14887 | if (reg == 0) | |
14888 | result = PCI_ERS_RESULT_RECOVERED; | |
14889 | else | |
14890 | result = PCI_ERS_RESULT_DISCONNECT; | |
14891 | } | |
14892 | ||
41c445ff JB |
14893 | return result; |
14894 | } | |
14895 | ||
19b7960b AB |
14896 | /** |
14897 | * i40e_pci_error_reset_prepare - prepare device driver for pci reset | |
14898 | * @pdev: PCI device information struct | |
14899 | */ | |
14900 | static void i40e_pci_error_reset_prepare(struct pci_dev *pdev) | |
14901 | { | |
14902 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
14903 | ||
14904 | i40e_prep_for_reset(pf, false); | |
14905 | } | |
14906 | ||
14907 | /** | |
14908 | * i40e_pci_error_reset_done - pci reset done, device driver reset can begin | |
14909 | * @pdev: PCI device information struct | |
14910 | */ | |
14911 | static void i40e_pci_error_reset_done(struct pci_dev *pdev) | |
14912 | { | |
14913 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
14914 | ||
14915 | i40e_reset_and_rebuild(pf, false, false); | |
14916 | } | |
14917 | ||
41c445ff JB |
14918 | /** |
14919 | * i40e_pci_error_resume - restart operations after PCI error recovery | |
14920 | * @pdev: PCI device information struct | |
14921 | * | |
14922 | * Called to allow the driver to bring things back up after PCI error | |
14923 | * and/or reset recovery has finished. | |
14924 | **/ | |
14925 | static void i40e_pci_error_resume(struct pci_dev *pdev) | |
14926 | { | |
14927 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
14928 | ||
fb43201f | 14929 | dev_dbg(&pdev->dev, "%s\n", __func__); |
0da36b97 | 14930 | if (test_bit(__I40E_SUSPENDED, pf->state)) |
9007bccd SN |
14931 | return; |
14932 | ||
dfc4ff64 | 14933 | i40e_handle_reset_warning(pf, false); |
9007bccd SN |
14934 | } |
14935 | ||
1d68005d JH |
14936 | /** |
14937 | * i40e_enable_mc_magic_wake - enable multicast magic packet wake up | |
14938 | * using the mac_address_write admin q function | |
14939 | * @pf: pointer to i40e_pf struct | |
14940 | **/ | |
14941 | static void i40e_enable_mc_magic_wake(struct i40e_pf *pf) | |
14942 | { | |
14943 | struct i40e_hw *hw = &pf->hw; | |
14944 | i40e_status ret; | |
14945 | u8 mac_addr[6]; | |
14946 | u16 flags = 0; | |
14947 | ||
14948 | /* Get current MAC address in case it's an LAA */ | |
14949 | if (pf->vsi[pf->lan_vsi] && pf->vsi[pf->lan_vsi]->netdev) { | |
14950 | ether_addr_copy(mac_addr, | |
14951 | pf->vsi[pf->lan_vsi]->netdev->dev_addr); | |
14952 | } else { | |
14953 | dev_err(&pf->pdev->dev, | |
14954 | "Failed to retrieve MAC address; using default\n"); | |
14955 | ether_addr_copy(mac_addr, hw->mac.addr); | |
14956 | } | |
14957 | ||
14958 | /* The FW expects the mac address write cmd to first be called with | |
14959 | * one of these flags before calling it again with the multicast | |
14960 | * enable flags. | |
14961 | */ | |
14962 | flags = I40E_AQC_WRITE_TYPE_LAA_WOL; | |
14963 | ||
14964 | if (hw->func_caps.flex10_enable && hw->partition_id != 1) | |
14965 | flags = I40E_AQC_WRITE_TYPE_LAA_ONLY; | |
14966 | ||
14967 | ret = i40e_aq_mac_address_write(hw, flags, mac_addr, NULL); | |
14968 | if (ret) { | |
14969 | dev_err(&pf->pdev->dev, | |
14970 | "Failed to update MAC address registers; cannot enable Multicast Magic packet wake up"); | |
14971 | return; | |
14972 | } | |
14973 | ||
14974 | flags = I40E_AQC_MC_MAG_EN | |
14975 | | I40E_AQC_WOL_PRESERVE_ON_PFR | |
14976 | | I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG; | |
14977 | ret = i40e_aq_mac_address_write(hw, flags, mac_addr, NULL); | |
14978 | if (ret) | |
14979 | dev_err(&pf->pdev->dev, | |
14980 | "Failed to enable Multicast Magic Packet wake up\n"); | |
14981 | } | |
14982 | ||
9007bccd SN |
14983 | /** |
14984 | * i40e_shutdown - PCI callback for shutting down | |
14985 | * @pdev: PCI device information struct | |
14986 | **/ | |
14987 | static void i40e_shutdown(struct pci_dev *pdev) | |
14988 | { | |
14989 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
8e2773ae | 14990 | struct i40e_hw *hw = &pf->hw; |
9007bccd | 14991 | |
0da36b97 | 14992 | set_bit(__I40E_SUSPENDED, pf->state); |
9e6c9c0f | 14993 | set_bit(__I40E_DOWN, pf->state); |
8e2773ae | 14994 | |
02b42498 CS |
14995 | del_timer_sync(&pf->service_timer); |
14996 | cancel_work_sync(&pf->service_task); | |
aaf66502 | 14997 | i40e_cloud_filter_exit(pf); |
02b42498 CS |
14998 | i40e_fdir_teardown(pf); |
14999 | ||
921c467c MW |
15000 | /* Client close must be called explicitly here because the timer |
15001 | * has been stopped. | |
15002 | */ | |
15003 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false); | |
15004 | ||
d36e41dc | 15005 | if (pf->wol_en && (pf->hw_features & I40E_HW_WOL_MC_MAGIC_PKT_WAKE)) |
1d68005d JH |
15006 | i40e_enable_mc_magic_wake(pf); |
15007 | ||
dfc4ff64 | 15008 | i40e_prep_for_reset(pf, false); |
02b42498 CS |
15009 | |
15010 | wr32(hw, I40E_PFPM_APM, | |
15011 | (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); | |
15012 | wr32(hw, I40E_PFPM_WUFC, | |
15013 | (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
15014 | ||
4ff0ee1a AM |
15015 | /* Free MSI/legacy interrupt 0 when in recovery mode. */ |
15016 | if (test_bit(__I40E_RECOVERY_MODE, pf->state) && | |
15017 | !(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
15018 | free_irq(pf->pdev->irq, pf); | |
15019 | ||
5cba17b1 PM |
15020 | /* Since we're going to destroy queues during the |
15021 | * i40e_clear_interrupt_scheme() we should hold the RTNL lock for this | |
15022 | * whole section | |
15023 | */ | |
15024 | rtnl_lock(); | |
e147758d | 15025 | i40e_clear_interrupt_scheme(pf); |
5cba17b1 | 15026 | rtnl_unlock(); |
e147758d | 15027 | |
9007bccd | 15028 | if (system_state == SYSTEM_POWER_OFF) { |
8e2773ae | 15029 | pci_wake_from_d3(pdev, pf->wol_en); |
9007bccd SN |
15030 | pci_set_power_state(pdev, PCI_D3hot); |
15031 | } | |
15032 | } | |
15033 | ||
9007bccd | 15034 | /** |
0e5d3da4 JK |
15035 | * i40e_suspend - PM callback for moving to D3 |
15036 | * @dev: generic device information structure | |
9007bccd | 15037 | **/ |
254d152a | 15038 | static int __maybe_unused i40e_suspend(struct device *dev) |
9007bccd | 15039 | { |
0e5d3da4 | 15040 | struct pci_dev *pdev = to_pci_dev(dev); |
9007bccd | 15041 | struct i40e_pf *pf = pci_get_drvdata(pdev); |
8e2773ae | 15042 | struct i40e_hw *hw = &pf->hw; |
9007bccd | 15043 | |
401586c2 JK |
15044 | /* If we're already suspended, then there is nothing to do */ |
15045 | if (test_and_set_bit(__I40E_SUSPENDED, pf->state)) | |
15046 | return 0; | |
15047 | ||
9e6c9c0f | 15048 | set_bit(__I40E_DOWN, pf->state); |
3932dbfe | 15049 | |
5c499228 JK |
15050 | /* Ensure service task will not be running */ |
15051 | del_timer_sync(&pf->service_timer); | |
15052 | cancel_work_sync(&pf->service_task); | |
15053 | ||
ddbb8d5d SS |
15054 | /* Client close must be called explicitly here because the timer |
15055 | * has been stopped. | |
15056 | */ | |
15057 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false); | |
15058 | ||
d36e41dc | 15059 | if (pf->wol_en && (pf->hw_features & I40E_HW_WOL_MC_MAGIC_PKT_WAKE)) |
1d68005d JH |
15060 | i40e_enable_mc_magic_wake(pf); |
15061 | ||
f0ee70a0 JK |
15062 | /* Since we're going to destroy queues during the |
15063 | * i40e_clear_interrupt_scheme() we should hold the RTNL lock for this | |
15064 | * whole section | |
15065 | */ | |
15066 | rtnl_lock(); | |
15067 | ||
15068 | i40e_prep_for_reset(pf, true); | |
9007bccd | 15069 | |
8e2773ae SN |
15070 | wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); |
15071 | wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
15072 | ||
b980c063 JK |
15073 | /* Clear the interrupt scheme and release our IRQs so that the system |
15074 | * can safely hibernate even when there are a large number of CPUs. | |
15075 | * Otherwise hibernation might fail when mapping all the vectors back | |
15076 | * to CPU0. | |
15077 | */ | |
15078 | i40e_clear_interrupt_scheme(pf); | |
9007bccd | 15079 | |
f0ee70a0 JK |
15080 | rtnl_unlock(); |
15081 | ||
0e5d3da4 | 15082 | return 0; |
41c445ff JB |
15083 | } |
15084 | ||
9007bccd | 15085 | /** |
0e5d3da4 JK |
15086 | * i40e_resume - PM callback for waking up from D3 |
15087 | * @dev: generic device information structure | |
9007bccd | 15088 | **/ |
254d152a | 15089 | static int __maybe_unused i40e_resume(struct device *dev) |
9007bccd | 15090 | { |
0e5d3da4 | 15091 | struct pci_dev *pdev = to_pci_dev(dev); |
9007bccd | 15092 | struct i40e_pf *pf = pci_get_drvdata(pdev); |
b980c063 | 15093 | int err; |
9007bccd | 15094 | |
401586c2 JK |
15095 | /* If we're not suspended, then there is nothing to do */ |
15096 | if (!test_bit(__I40E_SUSPENDED, pf->state)) | |
15097 | return 0; | |
9007bccd | 15098 | |
f0ee70a0 JK |
15099 | /* We need to hold the RTNL lock prior to restoring interrupt schemes, |
15100 | * since we're going to be restoring queues | |
15101 | */ | |
15102 | rtnl_lock(); | |
15103 | ||
b980c063 JK |
15104 | /* We cleared the interrupt scheme when we suspended, so we need to |
15105 | * restore it now to resume device functionality. | |
15106 | */ | |
15107 | err = i40e_restore_interrupt_scheme(pf); | |
9007bccd | 15108 | if (err) { |
b980c063 JK |
15109 | dev_err(&pdev->dev, "Cannot restore interrupt scheme: %d\n", |
15110 | err); | |
9007bccd | 15111 | } |
9007bccd | 15112 | |
401586c2 | 15113 | clear_bit(__I40E_DOWN, pf->state); |
f0ee70a0 JK |
15114 | i40e_reset_and_rebuild(pf, false, true); |
15115 | ||
15116 | rtnl_unlock(); | |
401586c2 JK |
15117 | |
15118 | /* Clear suspended state last after everything is recovered */ | |
15119 | clear_bit(__I40E_SUSPENDED, pf->state); | |
9007bccd | 15120 | |
5c499228 JK |
15121 | /* Restart the service task */ |
15122 | mod_timer(&pf->service_timer, | |
15123 | round_jiffies(jiffies + pf->service_timer_period)); | |
9007bccd SN |
15124 | |
15125 | return 0; | |
15126 | } | |
15127 | ||
41c445ff JB |
15128 | static const struct pci_error_handlers i40e_err_handler = { |
15129 | .error_detected = i40e_pci_error_detected, | |
15130 | .slot_reset = i40e_pci_error_slot_reset, | |
19b7960b AB |
15131 | .reset_prepare = i40e_pci_error_reset_prepare, |
15132 | .reset_done = i40e_pci_error_reset_done, | |
41c445ff JB |
15133 | .resume = i40e_pci_error_resume, |
15134 | }; | |
15135 | ||
0e5d3da4 JK |
15136 | static SIMPLE_DEV_PM_OPS(i40e_pm_ops, i40e_suspend, i40e_resume); |
15137 | ||
41c445ff JB |
15138 | static struct pci_driver i40e_driver = { |
15139 | .name = i40e_driver_name, | |
15140 | .id_table = i40e_pci_tbl, | |
15141 | .probe = i40e_probe, | |
15142 | .remove = i40e_remove, | |
0e5d3da4 JK |
15143 | .driver = { |
15144 | .pm = &i40e_pm_ops, | |
15145 | }, | |
9007bccd | 15146 | .shutdown = i40e_shutdown, |
41c445ff JB |
15147 | .err_handler = &i40e_err_handler, |
15148 | .sriov_configure = i40e_pci_sriov_configure, | |
15149 | }; | |
15150 | ||
15151 | /** | |
15152 | * i40e_init_module - Driver registration routine | |
15153 | * | |
15154 | * i40e_init_module is the first routine called when the driver is | |
15155 | * loaded. All it does is register with the PCI subsystem. | |
15156 | **/ | |
15157 | static int __init i40e_init_module(void) | |
15158 | { | |
15159 | pr_info("%s: %s - version %s\n", i40e_driver_name, | |
15160 | i40e_driver_string, i40e_driver_version_str); | |
15161 | pr_info("%s: %s\n", i40e_driver_name, i40e_copyright); | |
96664483 | 15162 | |
4d5957cb JK |
15163 | /* There is no need to throttle the number of active tasks because |
15164 | * each device limits its own task using a state bit for scheduling | |
15165 | * the service task, and the device tasks do not interfere with each | |
15166 | * other, so we don't set a max task limit. We must set WQ_MEM_RECLAIM | |
15167 | * since we need to be able to guarantee forward progress even under | |
15168 | * memory pressure. | |
2803b16c | 15169 | */ |
4d5957cb | 15170 | i40e_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, i40e_driver_name); |
2803b16c JB |
15171 | if (!i40e_wq) { |
15172 | pr_err("%s: Failed to create workqueue\n", i40e_driver_name); | |
15173 | return -ENOMEM; | |
15174 | } | |
15175 | ||
41c445ff JB |
15176 | i40e_dbg_init(); |
15177 | return pci_register_driver(&i40e_driver); | |
15178 | } | |
15179 | module_init(i40e_init_module); | |
15180 | ||
15181 | /** | |
15182 | * i40e_exit_module - Driver exit cleanup routine | |
15183 | * | |
15184 | * i40e_exit_module is called just before the driver is removed | |
15185 | * from memory. | |
15186 | **/ | |
15187 | static void __exit i40e_exit_module(void) | |
15188 | { | |
15189 | pci_unregister_driver(&i40e_driver); | |
2803b16c | 15190 | destroy_workqueue(i40e_wq); |
41c445ff JB |
15191 | i40e_dbg_exit(); |
15192 | } | |
15193 | module_exit(i40e_exit_module); |