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41c445ff JB |
1 | /******************************************************************************* |
2 | * | |
3 | * Intel Ethernet Controller XL710 Family Linux Driver | |
4fc8c676 | 4 | * Copyright(c) 2013 - 2017 Intel Corporation. |
41c445ff JB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms and conditions of the GNU General Public License, | |
8 | * version 2, as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
dc641b73 GR |
15 | * You should have received a copy of the GNU General Public License along |
16 | * with this program. If not, see <http://www.gnu.org/licenses/>. | |
41c445ff JB |
17 | * |
18 | * The full GNU General Public License is included in this distribution in | |
19 | * the file called "COPYING". | |
20 | * | |
21 | * Contact Information: | |
22 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
23 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
24 | * | |
25 | ******************************************************************************/ | |
26 | ||
b499ffb0 SV |
27 | #include <linux/etherdevice.h> |
28 | #include <linux/of_net.h> | |
29 | #include <linux/pci.h> | |
0c8493d9 | 30 | #include <linux/bpf.h> |
b499ffb0 | 31 | |
41c445ff JB |
32 | /* Local includes */ |
33 | #include "i40e.h" | |
4eb3f768 | 34 | #include "i40e_diag.h" |
06a5f7f1 | 35 | #include <net/udp_tunnel.h> |
ed0980c4 SP |
36 | /* All i40e tracepoints are defined by the include below, which |
37 | * must be included exactly once across the whole kernel with | |
38 | * CREATE_TRACE_POINTS defined | |
39 | */ | |
40 | #define CREATE_TRACE_POINTS | |
41 | #include "i40e_trace.h" | |
41c445ff JB |
42 | |
43 | const char i40e_driver_name[] = "i40e"; | |
44 | static const char i40e_driver_string[] = | |
45 | "Intel(R) Ethernet Connection XL710 Network Driver"; | |
46 | ||
47 | #define DRV_KERN "-k" | |
48 | ||
15990832 BP |
49 | #define DRV_VERSION_MAJOR 2 |
50 | #define DRV_VERSION_MINOR 1 | |
2318b401 | 51 | #define DRV_VERSION_BUILD 14 |
41c445ff JB |
52 | #define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \ |
53 | __stringify(DRV_VERSION_MINOR) "." \ | |
54 | __stringify(DRV_VERSION_BUILD) DRV_KERN | |
55 | const char i40e_driver_version_str[] = DRV_VERSION; | |
8fb905b3 | 56 | static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation."; |
41c445ff JB |
57 | |
58 | /* a bit of forward declarations */ | |
59 | static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi); | |
373149fc | 60 | static void i40e_handle_reset_warning(struct i40e_pf *pf, bool lock_acquired); |
41c445ff JB |
61 | static int i40e_add_vsi(struct i40e_vsi *vsi); |
62 | static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi); | |
bc7d338f | 63 | static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit); |
41c445ff JB |
64 | static int i40e_setup_misc_vector(struct i40e_pf *pf); |
65 | static void i40e_determine_queue_usage(struct i40e_pf *pf); | |
66 | static int i40e_setup_pf_filter_control(struct i40e_pf *pf); | |
373149fc MS |
67 | static void i40e_prep_for_reset(struct i40e_pf *pf, bool lock_acquired); |
68 | static int i40e_reset(struct i40e_pf *pf); | |
69 | static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired); | |
cbf61325 | 70 | static void i40e_fdir_sb_setup(struct i40e_pf *pf); |
4e3b35b0 | 71 | static int i40e_veb_get_bw_info(struct i40e_veb *veb); |
41c445ff JB |
72 | |
73 | /* i40e_pci_tbl - PCI Device ID Table | |
74 | * | |
75 | * Last entry must be all 0s | |
76 | * | |
77 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
78 | * Class, Class Mask, private data (not used) } | |
79 | */ | |
9baa3c34 | 80 | static const struct pci_device_id i40e_pci_tbl[] = { |
ab60085e | 81 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0}, |
ab60085e | 82 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0}, |
ab60085e SN |
83 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0}, |
84 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0}, | |
ab60085e SN |
85 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0}, |
86 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0}, | |
87 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0}, | |
5960d33f | 88 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0}, |
bc5166b9 | 89 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0}, |
35dae51d ASJ |
90 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0}, |
91 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0}, | |
87e6c1d7 ASJ |
92 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0}, |
93 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0}, | |
94 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0}, | |
d6bf58c2 | 95 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0}, |
48a3b512 SN |
96 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0}, |
97 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0}, | |
3123237a CW |
98 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_B), 0}, |
99 | {PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_SFP28), 0}, | |
41c445ff JB |
100 | /* required last entry */ |
101 | {0, } | |
102 | }; | |
103 | MODULE_DEVICE_TABLE(pci, i40e_pci_tbl); | |
104 | ||
105 | #define I40E_MAX_VF_COUNT 128 | |
106 | static int debug = -1; | |
5d4ca23e AD |
107 | module_param(debug, uint, 0); |
108 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all), Debug mask (0x8XXXXXXX)"); | |
41c445ff JB |
109 | |
110 | MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); | |
111 | MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver"); | |
112 | MODULE_LICENSE("GPL"); | |
113 | MODULE_VERSION(DRV_VERSION); | |
114 | ||
2803b16c JB |
115 | static struct workqueue_struct *i40e_wq; |
116 | ||
41c445ff JB |
117 | /** |
118 | * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code | |
119 | * @hw: pointer to the HW structure | |
120 | * @mem: ptr to mem struct to fill out | |
121 | * @size: size of memory requested | |
122 | * @alignment: what to align the allocation to | |
123 | **/ | |
124 | int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem, | |
125 | u64 size, u32 alignment) | |
126 | { | |
127 | struct i40e_pf *pf = (struct i40e_pf *)hw->back; | |
128 | ||
129 | mem->size = ALIGN(size, alignment); | |
130 | mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size, | |
131 | &mem->pa, GFP_KERNEL); | |
93bc73b8 JB |
132 | if (!mem->va) |
133 | return -ENOMEM; | |
41c445ff | 134 | |
93bc73b8 | 135 | return 0; |
41c445ff JB |
136 | } |
137 | ||
138 | /** | |
139 | * i40e_free_dma_mem_d - OS specific memory free for shared code | |
140 | * @hw: pointer to the HW structure | |
141 | * @mem: ptr to mem struct to free | |
142 | **/ | |
143 | int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem) | |
144 | { | |
145 | struct i40e_pf *pf = (struct i40e_pf *)hw->back; | |
146 | ||
147 | dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa); | |
148 | mem->va = NULL; | |
149 | mem->pa = 0; | |
150 | mem->size = 0; | |
151 | ||
152 | return 0; | |
153 | } | |
154 | ||
155 | /** | |
156 | * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code | |
157 | * @hw: pointer to the HW structure | |
158 | * @mem: ptr to mem struct to fill out | |
159 | * @size: size of memory requested | |
160 | **/ | |
161 | int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem, | |
162 | u32 size) | |
163 | { | |
164 | mem->size = size; | |
165 | mem->va = kzalloc(size, GFP_KERNEL); | |
166 | ||
93bc73b8 JB |
167 | if (!mem->va) |
168 | return -ENOMEM; | |
41c445ff | 169 | |
93bc73b8 | 170 | return 0; |
41c445ff JB |
171 | } |
172 | ||
173 | /** | |
174 | * i40e_free_virt_mem_d - OS specific memory free for shared code | |
175 | * @hw: pointer to the HW structure | |
176 | * @mem: ptr to mem struct to free | |
177 | **/ | |
178 | int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem) | |
179 | { | |
180 | /* it's ok to kfree a NULL pointer */ | |
181 | kfree(mem->va); | |
182 | mem->va = NULL; | |
183 | mem->size = 0; | |
184 | ||
185 | return 0; | |
186 | } | |
187 | ||
188 | /** | |
189 | * i40e_get_lump - find a lump of free generic resource | |
190 | * @pf: board private structure | |
191 | * @pile: the pile of resource to search | |
192 | * @needed: the number of items needed | |
193 | * @id: an owner id to stick on the items assigned | |
194 | * | |
195 | * Returns the base item index of the lump, or negative for error | |
196 | * | |
197 | * The search_hint trick and lack of advanced fit-finding only work | |
198 | * because we're highly likely to have all the same size lump requests. | |
199 | * Linear search time and any fragmentation should be minimal. | |
200 | **/ | |
201 | static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile, | |
202 | u16 needed, u16 id) | |
203 | { | |
204 | int ret = -ENOMEM; | |
ddf434ac | 205 | int i, j; |
41c445ff JB |
206 | |
207 | if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) { | |
208 | dev_info(&pf->pdev->dev, | |
209 | "param err: pile=%p needed=%d id=0x%04x\n", | |
210 | pile, needed, id); | |
211 | return -EINVAL; | |
212 | } | |
213 | ||
214 | /* start the linear search with an imperfect hint */ | |
215 | i = pile->search_hint; | |
ddf434ac | 216 | while (i < pile->num_entries) { |
41c445ff JB |
217 | /* skip already allocated entries */ |
218 | if (pile->list[i] & I40E_PILE_VALID_BIT) { | |
219 | i++; | |
220 | continue; | |
221 | } | |
222 | ||
223 | /* do we have enough in this lump? */ | |
224 | for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) { | |
225 | if (pile->list[i+j] & I40E_PILE_VALID_BIT) | |
226 | break; | |
227 | } | |
228 | ||
229 | if (j == needed) { | |
230 | /* there was enough, so assign it to the requestor */ | |
231 | for (j = 0; j < needed; j++) | |
232 | pile->list[i+j] = id | I40E_PILE_VALID_BIT; | |
233 | ret = i; | |
234 | pile->search_hint = i + j; | |
ddf434ac | 235 | break; |
41c445ff | 236 | } |
6995b36c JB |
237 | |
238 | /* not enough, so skip over it and continue looking */ | |
239 | i += j; | |
41c445ff JB |
240 | } |
241 | ||
242 | return ret; | |
243 | } | |
244 | ||
245 | /** | |
246 | * i40e_put_lump - return a lump of generic resource | |
247 | * @pile: the pile of resource to search | |
248 | * @index: the base item index | |
249 | * @id: the owner id of the items assigned | |
250 | * | |
251 | * Returns the count of items in the lump | |
252 | **/ | |
253 | static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id) | |
254 | { | |
255 | int valid_id = (id | I40E_PILE_VALID_BIT); | |
256 | int count = 0; | |
257 | int i; | |
258 | ||
259 | if (!pile || index >= pile->num_entries) | |
260 | return -EINVAL; | |
261 | ||
262 | for (i = index; | |
263 | i < pile->num_entries && pile->list[i] == valid_id; | |
264 | i++) { | |
265 | pile->list[i] = 0; | |
266 | count++; | |
267 | } | |
268 | ||
269 | if (count && index < pile->search_hint) | |
270 | pile->search_hint = index; | |
271 | ||
272 | return count; | |
273 | } | |
274 | ||
fdf0e0bf ASJ |
275 | /** |
276 | * i40e_find_vsi_from_id - searches for the vsi with the given id | |
277 | * @pf - the pf structure to search for the vsi | |
278 | * @id - id of the vsi it is searching for | |
279 | **/ | |
280 | struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id) | |
281 | { | |
282 | int i; | |
283 | ||
284 | for (i = 0; i < pf->num_alloc_vsi; i++) | |
285 | if (pf->vsi[i] && (pf->vsi[i]->id == id)) | |
286 | return pf->vsi[i]; | |
287 | ||
288 | return NULL; | |
289 | } | |
290 | ||
41c445ff JB |
291 | /** |
292 | * i40e_service_event_schedule - Schedule the service task to wake up | |
293 | * @pf: board private structure | |
294 | * | |
295 | * If not already scheduled, this puts the task into the work queue | |
296 | **/ | |
e3219ce6 | 297 | void i40e_service_event_schedule(struct i40e_pf *pf) |
41c445ff | 298 | { |
9e6c9c0f | 299 | if (!test_bit(__I40E_DOWN, pf->state) && |
0da36b97 | 300 | !test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
2803b16c | 301 | queue_work(i40e_wq, &pf->service_task); |
41c445ff JB |
302 | } |
303 | ||
304 | /** | |
305 | * i40e_tx_timeout - Respond to a Tx Hang | |
306 | * @netdev: network interface device structure | |
307 | * | |
308 | * If any port has noticed a Tx timeout, it is likely that the whole | |
309 | * device is munged, not just the one netdev port, so go for the full | |
310 | * reset. | |
311 | **/ | |
312 | static void i40e_tx_timeout(struct net_device *netdev) | |
313 | { | |
314 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
315 | struct i40e_vsi *vsi = np->vsi; | |
316 | struct i40e_pf *pf = vsi->back; | |
b03a8c1f KP |
317 | struct i40e_ring *tx_ring = NULL; |
318 | unsigned int i, hung_queue = 0; | |
319 | u32 head, val; | |
41c445ff JB |
320 | |
321 | pf->tx_timeout_count++; | |
322 | ||
b03a8c1f KP |
323 | /* find the stopped queue the same way the stack does */ |
324 | for (i = 0; i < netdev->num_tx_queues; i++) { | |
325 | struct netdev_queue *q; | |
326 | unsigned long trans_start; | |
327 | ||
328 | q = netdev_get_tx_queue(netdev, i); | |
9b36627a | 329 | trans_start = q->trans_start; |
b03a8c1f KP |
330 | if (netif_xmit_stopped(q) && |
331 | time_after(jiffies, | |
332 | (trans_start + netdev->watchdog_timeo))) { | |
333 | hung_queue = i; | |
334 | break; | |
335 | } | |
336 | } | |
337 | ||
338 | if (i == netdev->num_tx_queues) { | |
339 | netdev_info(netdev, "tx_timeout: no netdev hung queue found\n"); | |
340 | } else { | |
341 | /* now that we have an index, find the tx_ring struct */ | |
342 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
343 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) { | |
344 | if (hung_queue == | |
345 | vsi->tx_rings[i]->queue_index) { | |
346 | tx_ring = vsi->tx_rings[i]; | |
347 | break; | |
348 | } | |
349 | } | |
350 | } | |
351 | } | |
352 | ||
41c445ff | 353 | if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20))) |
b03a8c1f KP |
354 | pf->tx_timeout_recovery_level = 1; /* reset after some time */ |
355 | else if (time_before(jiffies, | |
356 | (pf->tx_timeout_last_recovery + netdev->watchdog_timeo))) | |
357 | return; /* don't do any new action before the next timeout */ | |
358 | ||
359 | if (tx_ring) { | |
360 | head = i40e_get_head(tx_ring); | |
361 | /* Read interrupt register */ | |
362 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
363 | val = rd32(&pf->hw, | |
364 | I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx + | |
365 | tx_ring->vsi->base_vector - 1)); | |
366 | else | |
367 | val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); | |
368 | ||
369 | netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n", | |
370 | vsi->seid, hung_queue, tx_ring->next_to_clean, | |
371 | head, tx_ring->next_to_use, | |
372 | readl(tx_ring->tail), val); | |
373 | } | |
374 | ||
41c445ff | 375 | pf->tx_timeout_last_recovery = jiffies; |
b03a8c1f KP |
376 | netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n", |
377 | pf->tx_timeout_recovery_level, hung_queue); | |
41c445ff JB |
378 | |
379 | switch (pf->tx_timeout_recovery_level) { | |
41c445ff | 380 | case 1: |
0da36b97 | 381 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
41c445ff JB |
382 | break; |
383 | case 2: | |
0da36b97 | 384 | set_bit(__I40E_CORE_RESET_REQUESTED, pf->state); |
41c445ff JB |
385 | break; |
386 | case 3: | |
0da36b97 | 387 | set_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state); |
41c445ff JB |
388 | break; |
389 | default: | |
390 | netdev_err(netdev, "tx_timeout recovery unsuccessful\n"); | |
41c445ff JB |
391 | break; |
392 | } | |
b03a8c1f | 393 | |
41c445ff JB |
394 | i40e_service_event_schedule(pf); |
395 | pf->tx_timeout_recovery_level++; | |
396 | } | |
397 | ||
41c445ff JB |
398 | /** |
399 | * i40e_get_vsi_stats_struct - Get System Network Statistics | |
400 | * @vsi: the VSI we care about | |
401 | * | |
402 | * Returns the address of the device statistics structure. | |
403 | * The statistics are actually updated from the service task. | |
404 | **/ | |
405 | struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi) | |
406 | { | |
407 | return &vsi->net_stats; | |
408 | } | |
409 | ||
74608d17 BT |
410 | /** |
411 | * i40e_get_netdev_stats_struct_tx - populate stats from a Tx ring | |
412 | * @ring: Tx ring to get statistics from | |
413 | * @stats: statistics entry to be updated | |
414 | **/ | |
415 | static void i40e_get_netdev_stats_struct_tx(struct i40e_ring *ring, | |
416 | struct rtnl_link_stats64 *stats) | |
417 | { | |
418 | u64 bytes, packets; | |
419 | unsigned int start; | |
420 | ||
421 | do { | |
422 | start = u64_stats_fetch_begin_irq(&ring->syncp); | |
423 | packets = ring->stats.packets; | |
424 | bytes = ring->stats.bytes; | |
425 | } while (u64_stats_fetch_retry_irq(&ring->syncp, start)); | |
426 | ||
427 | stats->tx_packets += packets; | |
428 | stats->tx_bytes += bytes; | |
429 | } | |
430 | ||
41c445ff JB |
431 | /** |
432 | * i40e_get_netdev_stats_struct - Get statistics for netdev interface | |
433 | * @netdev: network interface device structure | |
434 | * | |
435 | * Returns the address of the device statistics structure. | |
436 | * The statistics are actually updated from the service task. | |
437 | **/ | |
9eed69a9 | 438 | static void i40e_get_netdev_stats_struct(struct net_device *netdev, |
bc1f4470 | 439 | struct rtnl_link_stats64 *stats) |
41c445ff JB |
440 | { |
441 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
e7046ee1 | 442 | struct i40e_ring *tx_ring, *rx_ring; |
41c445ff | 443 | struct i40e_vsi *vsi = np->vsi; |
980e9b11 AD |
444 | struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi); |
445 | int i; | |
446 | ||
0da36b97 | 447 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) |
bc1f4470 | 448 | return; |
bc7d338f | 449 | |
3c325ced | 450 | if (!vsi->tx_rings) |
bc1f4470 | 451 | return; |
3c325ced | 452 | |
980e9b11 AD |
453 | rcu_read_lock(); |
454 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
980e9b11 AD |
455 | u64 bytes, packets; |
456 | unsigned int start; | |
457 | ||
458 | tx_ring = ACCESS_ONCE(vsi->tx_rings[i]); | |
459 | if (!tx_ring) | |
460 | continue; | |
74608d17 | 461 | i40e_get_netdev_stats_struct_tx(tx_ring, stats); |
980e9b11 | 462 | |
980e9b11 AD |
463 | rx_ring = &tx_ring[1]; |
464 | ||
465 | do { | |
57a7744e | 466 | start = u64_stats_fetch_begin_irq(&rx_ring->syncp); |
980e9b11 AD |
467 | packets = rx_ring->stats.packets; |
468 | bytes = rx_ring->stats.bytes; | |
57a7744e | 469 | } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start)); |
41c445ff | 470 | |
980e9b11 AD |
471 | stats->rx_packets += packets; |
472 | stats->rx_bytes += bytes; | |
74608d17 BT |
473 | |
474 | if (i40e_enabled_xdp_vsi(vsi)) | |
475 | i40e_get_netdev_stats_struct_tx(&rx_ring[1], stats); | |
980e9b11 AD |
476 | } |
477 | rcu_read_unlock(); | |
478 | ||
a5282f44 | 479 | /* following stats updated by i40e_watchdog_subtask() */ |
980e9b11 AD |
480 | stats->multicast = vsi_stats->multicast; |
481 | stats->tx_errors = vsi_stats->tx_errors; | |
482 | stats->tx_dropped = vsi_stats->tx_dropped; | |
483 | stats->rx_errors = vsi_stats->rx_errors; | |
d8201e20 | 484 | stats->rx_dropped = vsi_stats->rx_dropped; |
980e9b11 AD |
485 | stats->rx_crc_errors = vsi_stats->rx_crc_errors; |
486 | stats->rx_length_errors = vsi_stats->rx_length_errors; | |
41c445ff JB |
487 | } |
488 | ||
489 | /** | |
490 | * i40e_vsi_reset_stats - Resets all stats of the given vsi | |
491 | * @vsi: the VSI to have its stats reset | |
492 | **/ | |
493 | void i40e_vsi_reset_stats(struct i40e_vsi *vsi) | |
494 | { | |
495 | struct rtnl_link_stats64 *ns; | |
496 | int i; | |
497 | ||
498 | if (!vsi) | |
499 | return; | |
500 | ||
501 | ns = i40e_get_vsi_stats_struct(vsi); | |
502 | memset(ns, 0, sizeof(*ns)); | |
503 | memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets)); | |
504 | memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats)); | |
505 | memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets)); | |
8e9dca53 | 506 | if (vsi->rx_rings && vsi->rx_rings[0]) { |
41c445ff | 507 | for (i = 0; i < vsi->num_queue_pairs; i++) { |
6995b36c | 508 | memset(&vsi->rx_rings[i]->stats, 0, |
9f65e15b | 509 | sizeof(vsi->rx_rings[i]->stats)); |
6995b36c | 510 | memset(&vsi->rx_rings[i]->rx_stats, 0, |
9f65e15b | 511 | sizeof(vsi->rx_rings[i]->rx_stats)); |
6995b36c | 512 | memset(&vsi->tx_rings[i]->stats, 0, |
9f65e15b AD |
513 | sizeof(vsi->tx_rings[i]->stats)); |
514 | memset(&vsi->tx_rings[i]->tx_stats, 0, | |
515 | sizeof(vsi->tx_rings[i]->tx_stats)); | |
41c445ff | 516 | } |
8e9dca53 | 517 | } |
41c445ff JB |
518 | vsi->stat_offsets_loaded = false; |
519 | } | |
520 | ||
521 | /** | |
b40c82e6 | 522 | * i40e_pf_reset_stats - Reset all of the stats for the given PF |
41c445ff JB |
523 | * @pf: the PF to be reset |
524 | **/ | |
525 | void i40e_pf_reset_stats(struct i40e_pf *pf) | |
526 | { | |
e91fdf76 SN |
527 | int i; |
528 | ||
41c445ff JB |
529 | memset(&pf->stats, 0, sizeof(pf->stats)); |
530 | memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets)); | |
531 | pf->stat_offsets_loaded = false; | |
e91fdf76 SN |
532 | |
533 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
534 | if (pf->veb[i]) { | |
535 | memset(&pf->veb[i]->stats, 0, | |
536 | sizeof(pf->veb[i]->stats)); | |
537 | memset(&pf->veb[i]->stats_offsets, 0, | |
538 | sizeof(pf->veb[i]->stats_offsets)); | |
539 | pf->veb[i]->stat_offsets_loaded = false; | |
540 | } | |
541 | } | |
42bce04e | 542 | pf->hw_csum_rx_error = 0; |
41c445ff JB |
543 | } |
544 | ||
545 | /** | |
546 | * i40e_stat_update48 - read and update a 48 bit stat from the chip | |
547 | * @hw: ptr to the hardware info | |
548 | * @hireg: the high 32 bit reg to read | |
549 | * @loreg: the low 32 bit reg to read | |
550 | * @offset_loaded: has the initial offset been loaded yet | |
551 | * @offset: ptr to current offset value | |
552 | * @stat: ptr to the stat | |
553 | * | |
554 | * Since the device stats are not reset at PFReset, they likely will not | |
555 | * be zeroed when the driver starts. We'll save the first values read | |
556 | * and use them as offsets to be subtracted from the raw values in order | |
557 | * to report stats that count from zero. In the process, we also manage | |
558 | * the potential roll-over. | |
559 | **/ | |
560 | static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg, | |
561 | bool offset_loaded, u64 *offset, u64 *stat) | |
562 | { | |
563 | u64 new_data; | |
564 | ||
ab60085e | 565 | if (hw->device_id == I40E_DEV_ID_QEMU) { |
41c445ff JB |
566 | new_data = rd32(hw, loreg); |
567 | new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32; | |
568 | } else { | |
569 | new_data = rd64(hw, loreg); | |
570 | } | |
571 | if (!offset_loaded) | |
572 | *offset = new_data; | |
573 | if (likely(new_data >= *offset)) | |
574 | *stat = new_data - *offset; | |
575 | else | |
41a1d04b | 576 | *stat = (new_data + BIT_ULL(48)) - *offset; |
41c445ff JB |
577 | *stat &= 0xFFFFFFFFFFFFULL; |
578 | } | |
579 | ||
580 | /** | |
581 | * i40e_stat_update32 - read and update a 32 bit stat from the chip | |
582 | * @hw: ptr to the hardware info | |
583 | * @reg: the hw reg to read | |
584 | * @offset_loaded: has the initial offset been loaded yet | |
585 | * @offset: ptr to current offset value | |
586 | * @stat: ptr to the stat | |
587 | **/ | |
588 | static void i40e_stat_update32(struct i40e_hw *hw, u32 reg, | |
589 | bool offset_loaded, u64 *offset, u64 *stat) | |
590 | { | |
591 | u32 new_data; | |
592 | ||
593 | new_data = rd32(hw, reg); | |
594 | if (!offset_loaded) | |
595 | *offset = new_data; | |
596 | if (likely(new_data >= *offset)) | |
597 | *stat = (u32)(new_data - *offset); | |
598 | else | |
41a1d04b | 599 | *stat = (u32)((new_data + BIT_ULL(32)) - *offset); |
41c445ff JB |
600 | } |
601 | ||
0dc8692e MS |
602 | /** |
603 | * i40e_stat_update_and_clear32 - read and clear hw reg, update a 32 bit stat | |
604 | * @hw: ptr to the hardware info | |
605 | * @reg: the hw reg to read and clear | |
606 | * @stat: ptr to the stat | |
607 | **/ | |
608 | static void i40e_stat_update_and_clear32(struct i40e_hw *hw, u32 reg, u64 *stat) | |
609 | { | |
610 | u32 new_data = rd32(hw, reg); | |
611 | ||
612 | wr32(hw, reg, 1); /* must write a nonzero value to clear register */ | |
613 | *stat += new_data; | |
614 | } | |
615 | ||
41c445ff JB |
616 | /** |
617 | * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters. | |
618 | * @vsi: the VSI to be updated | |
619 | **/ | |
620 | void i40e_update_eth_stats(struct i40e_vsi *vsi) | |
621 | { | |
622 | int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx); | |
623 | struct i40e_pf *pf = vsi->back; | |
624 | struct i40e_hw *hw = &pf->hw; | |
625 | struct i40e_eth_stats *oes; | |
626 | struct i40e_eth_stats *es; /* device's eth stats */ | |
627 | ||
628 | es = &vsi->eth_stats; | |
629 | oes = &vsi->eth_stats_offsets; | |
630 | ||
631 | /* Gather up the stats that the hw collects */ | |
632 | i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), | |
633 | vsi->stat_offsets_loaded, | |
634 | &oes->tx_errors, &es->tx_errors); | |
635 | i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx), | |
636 | vsi->stat_offsets_loaded, | |
637 | &oes->rx_discards, &es->rx_discards); | |
41a9e55c SN |
638 | i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx), |
639 | vsi->stat_offsets_loaded, | |
640 | &oes->rx_unknown_protocol, &es->rx_unknown_protocol); | |
641 | i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx), | |
642 | vsi->stat_offsets_loaded, | |
643 | &oes->tx_errors, &es->tx_errors); | |
41c445ff JB |
644 | |
645 | i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx), | |
646 | I40E_GLV_GORCL(stat_idx), | |
647 | vsi->stat_offsets_loaded, | |
648 | &oes->rx_bytes, &es->rx_bytes); | |
649 | i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx), | |
650 | I40E_GLV_UPRCL(stat_idx), | |
651 | vsi->stat_offsets_loaded, | |
652 | &oes->rx_unicast, &es->rx_unicast); | |
653 | i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx), | |
654 | I40E_GLV_MPRCL(stat_idx), | |
655 | vsi->stat_offsets_loaded, | |
656 | &oes->rx_multicast, &es->rx_multicast); | |
657 | i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx), | |
658 | I40E_GLV_BPRCL(stat_idx), | |
659 | vsi->stat_offsets_loaded, | |
660 | &oes->rx_broadcast, &es->rx_broadcast); | |
661 | ||
662 | i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx), | |
663 | I40E_GLV_GOTCL(stat_idx), | |
664 | vsi->stat_offsets_loaded, | |
665 | &oes->tx_bytes, &es->tx_bytes); | |
666 | i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx), | |
667 | I40E_GLV_UPTCL(stat_idx), | |
668 | vsi->stat_offsets_loaded, | |
669 | &oes->tx_unicast, &es->tx_unicast); | |
670 | i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx), | |
671 | I40E_GLV_MPTCL(stat_idx), | |
672 | vsi->stat_offsets_loaded, | |
673 | &oes->tx_multicast, &es->tx_multicast); | |
674 | i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx), | |
675 | I40E_GLV_BPTCL(stat_idx), | |
676 | vsi->stat_offsets_loaded, | |
677 | &oes->tx_broadcast, &es->tx_broadcast); | |
678 | vsi->stat_offsets_loaded = true; | |
679 | } | |
680 | ||
681 | /** | |
682 | * i40e_update_veb_stats - Update Switch component statistics | |
683 | * @veb: the VEB being updated | |
684 | **/ | |
685 | static void i40e_update_veb_stats(struct i40e_veb *veb) | |
686 | { | |
687 | struct i40e_pf *pf = veb->pf; | |
688 | struct i40e_hw *hw = &pf->hw; | |
689 | struct i40e_eth_stats *oes; | |
690 | struct i40e_eth_stats *es; /* device's eth stats */ | |
fe860afb NP |
691 | struct i40e_veb_tc_stats *veb_oes; |
692 | struct i40e_veb_tc_stats *veb_es; | |
693 | int i, idx = 0; | |
41c445ff JB |
694 | |
695 | idx = veb->stats_idx; | |
696 | es = &veb->stats; | |
697 | oes = &veb->stats_offsets; | |
fe860afb NP |
698 | veb_es = &veb->tc_stats; |
699 | veb_oes = &veb->tc_stats_offsets; | |
41c445ff JB |
700 | |
701 | /* Gather up the stats that the hw collects */ | |
702 | i40e_stat_update32(hw, I40E_GLSW_TDPC(idx), | |
703 | veb->stat_offsets_loaded, | |
704 | &oes->tx_discards, &es->tx_discards); | |
7134f9ce JB |
705 | if (hw->revision_id > 0) |
706 | i40e_stat_update32(hw, I40E_GLSW_RUPP(idx), | |
707 | veb->stat_offsets_loaded, | |
708 | &oes->rx_unknown_protocol, | |
709 | &es->rx_unknown_protocol); | |
41c445ff JB |
710 | i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx), |
711 | veb->stat_offsets_loaded, | |
712 | &oes->rx_bytes, &es->rx_bytes); | |
713 | i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx), | |
714 | veb->stat_offsets_loaded, | |
715 | &oes->rx_unicast, &es->rx_unicast); | |
716 | i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx), | |
717 | veb->stat_offsets_loaded, | |
718 | &oes->rx_multicast, &es->rx_multicast); | |
719 | i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx), | |
720 | veb->stat_offsets_loaded, | |
721 | &oes->rx_broadcast, &es->rx_broadcast); | |
722 | ||
723 | i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx), | |
724 | veb->stat_offsets_loaded, | |
725 | &oes->tx_bytes, &es->tx_bytes); | |
726 | i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx), | |
727 | veb->stat_offsets_loaded, | |
728 | &oes->tx_unicast, &es->tx_unicast); | |
729 | i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx), | |
730 | veb->stat_offsets_loaded, | |
731 | &oes->tx_multicast, &es->tx_multicast); | |
732 | i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx), | |
733 | veb->stat_offsets_loaded, | |
734 | &oes->tx_broadcast, &es->tx_broadcast); | |
fe860afb NP |
735 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
736 | i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx), | |
737 | I40E_GLVEBTC_RPCL(i, idx), | |
738 | veb->stat_offsets_loaded, | |
739 | &veb_oes->tc_rx_packets[i], | |
740 | &veb_es->tc_rx_packets[i]); | |
741 | i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx), | |
742 | I40E_GLVEBTC_RBCL(i, idx), | |
743 | veb->stat_offsets_loaded, | |
744 | &veb_oes->tc_rx_bytes[i], | |
745 | &veb_es->tc_rx_bytes[i]); | |
746 | i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx), | |
747 | I40E_GLVEBTC_TPCL(i, idx), | |
748 | veb->stat_offsets_loaded, | |
749 | &veb_oes->tc_tx_packets[i], | |
750 | &veb_es->tc_tx_packets[i]); | |
751 | i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx), | |
752 | I40E_GLVEBTC_TBCL(i, idx), | |
753 | veb->stat_offsets_loaded, | |
754 | &veb_oes->tc_tx_bytes[i], | |
755 | &veb_es->tc_tx_bytes[i]); | |
756 | } | |
41c445ff JB |
757 | veb->stat_offsets_loaded = true; |
758 | } | |
759 | ||
41c445ff | 760 | /** |
7812fddc | 761 | * i40e_update_vsi_stats - Update the vsi statistics counters. |
41c445ff JB |
762 | * @vsi: the VSI to be updated |
763 | * | |
764 | * There are a few instances where we store the same stat in a | |
765 | * couple of different structs. This is partly because we have | |
766 | * the netdev stats that need to be filled out, which is slightly | |
767 | * different from the "eth_stats" defined by the chip and used in | |
7812fddc | 768 | * VF communications. We sort it out here. |
41c445ff | 769 | **/ |
7812fddc | 770 | static void i40e_update_vsi_stats(struct i40e_vsi *vsi) |
41c445ff JB |
771 | { |
772 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
773 | struct rtnl_link_stats64 *ons; |
774 | struct rtnl_link_stats64 *ns; /* netdev stats */ | |
775 | struct i40e_eth_stats *oes; | |
776 | struct i40e_eth_stats *es; /* device's eth stats */ | |
777 | u32 tx_restart, tx_busy; | |
bf00b376 | 778 | struct i40e_ring *p; |
41c445ff | 779 | u32 rx_page, rx_buf; |
bf00b376 AA |
780 | u64 bytes, packets; |
781 | unsigned int start; | |
2fc3d715 | 782 | u64 tx_linearize; |
164c9f54 | 783 | u64 tx_force_wb; |
41c445ff JB |
784 | u64 rx_p, rx_b; |
785 | u64 tx_p, tx_b; | |
41c445ff JB |
786 | u16 q; |
787 | ||
0da36b97 JK |
788 | if (test_bit(__I40E_VSI_DOWN, vsi->state) || |
789 | test_bit(__I40E_CONFIG_BUSY, pf->state)) | |
41c445ff JB |
790 | return; |
791 | ||
792 | ns = i40e_get_vsi_stats_struct(vsi); | |
793 | ons = &vsi->net_stats_offsets; | |
794 | es = &vsi->eth_stats; | |
795 | oes = &vsi->eth_stats_offsets; | |
796 | ||
797 | /* Gather up the netdev and vsi stats that the driver collects | |
798 | * on the fly during packet processing | |
799 | */ | |
800 | rx_b = rx_p = 0; | |
801 | tx_b = tx_p = 0; | |
164c9f54 | 802 | tx_restart = tx_busy = tx_linearize = tx_force_wb = 0; |
41c445ff JB |
803 | rx_page = 0; |
804 | rx_buf = 0; | |
980e9b11 | 805 | rcu_read_lock(); |
41c445ff | 806 | for (q = 0; q < vsi->num_queue_pairs; q++) { |
980e9b11 AD |
807 | /* locate Tx ring */ |
808 | p = ACCESS_ONCE(vsi->tx_rings[q]); | |
809 | ||
810 | do { | |
57a7744e | 811 | start = u64_stats_fetch_begin_irq(&p->syncp); |
980e9b11 AD |
812 | packets = p->stats.packets; |
813 | bytes = p->stats.bytes; | |
57a7744e | 814 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); |
980e9b11 AD |
815 | tx_b += bytes; |
816 | tx_p += packets; | |
817 | tx_restart += p->tx_stats.restart_queue; | |
818 | tx_busy += p->tx_stats.tx_busy; | |
2fc3d715 | 819 | tx_linearize += p->tx_stats.tx_linearize; |
164c9f54 | 820 | tx_force_wb += p->tx_stats.tx_force_wb; |
41c445ff | 821 | |
980e9b11 AD |
822 | /* Rx queue is part of the same block as Tx queue */ |
823 | p = &p[1]; | |
824 | do { | |
57a7744e | 825 | start = u64_stats_fetch_begin_irq(&p->syncp); |
980e9b11 AD |
826 | packets = p->stats.packets; |
827 | bytes = p->stats.bytes; | |
57a7744e | 828 | } while (u64_stats_fetch_retry_irq(&p->syncp, start)); |
980e9b11 AD |
829 | rx_b += bytes; |
830 | rx_p += packets; | |
420136cc MW |
831 | rx_buf += p->rx_stats.alloc_buff_failed; |
832 | rx_page += p->rx_stats.alloc_page_failed; | |
41c445ff | 833 | } |
980e9b11 | 834 | rcu_read_unlock(); |
41c445ff JB |
835 | vsi->tx_restart = tx_restart; |
836 | vsi->tx_busy = tx_busy; | |
2fc3d715 | 837 | vsi->tx_linearize = tx_linearize; |
164c9f54 | 838 | vsi->tx_force_wb = tx_force_wb; |
41c445ff JB |
839 | vsi->rx_page_failed = rx_page; |
840 | vsi->rx_buf_failed = rx_buf; | |
841 | ||
842 | ns->rx_packets = rx_p; | |
843 | ns->rx_bytes = rx_b; | |
844 | ns->tx_packets = tx_p; | |
845 | ns->tx_bytes = tx_b; | |
846 | ||
41c445ff | 847 | /* update netdev stats from eth stats */ |
7812fddc | 848 | i40e_update_eth_stats(vsi); |
41c445ff JB |
849 | ons->tx_errors = oes->tx_errors; |
850 | ns->tx_errors = es->tx_errors; | |
851 | ons->multicast = oes->rx_multicast; | |
852 | ns->multicast = es->rx_multicast; | |
41a9e55c SN |
853 | ons->rx_dropped = oes->rx_discards; |
854 | ns->rx_dropped = es->rx_discards; | |
41c445ff JB |
855 | ons->tx_dropped = oes->tx_discards; |
856 | ns->tx_dropped = es->tx_discards; | |
857 | ||
7812fddc | 858 | /* pull in a couple PF stats if this is the main vsi */ |
41c445ff | 859 | if (vsi == pf->vsi[pf->lan_vsi]) { |
7812fddc SN |
860 | ns->rx_crc_errors = pf->stats.crc_errors; |
861 | ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes; | |
862 | ns->rx_length_errors = pf->stats.rx_length_errors; | |
863 | } | |
864 | } | |
41c445ff | 865 | |
7812fddc | 866 | /** |
b40c82e6 | 867 | * i40e_update_pf_stats - Update the PF statistics counters. |
7812fddc SN |
868 | * @pf: the PF to be updated |
869 | **/ | |
870 | static void i40e_update_pf_stats(struct i40e_pf *pf) | |
871 | { | |
872 | struct i40e_hw_port_stats *osd = &pf->stats_offsets; | |
873 | struct i40e_hw_port_stats *nsd = &pf->stats; | |
874 | struct i40e_hw *hw = &pf->hw; | |
875 | u32 val; | |
876 | int i; | |
41c445ff | 877 | |
7812fddc SN |
878 | i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port), |
879 | I40E_GLPRT_GORCL(hw->port), | |
880 | pf->stat_offsets_loaded, | |
881 | &osd->eth.rx_bytes, &nsd->eth.rx_bytes); | |
882 | i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port), | |
883 | I40E_GLPRT_GOTCL(hw->port), | |
884 | pf->stat_offsets_loaded, | |
885 | &osd->eth.tx_bytes, &nsd->eth.tx_bytes); | |
886 | i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port), | |
887 | pf->stat_offsets_loaded, | |
888 | &osd->eth.rx_discards, | |
889 | &nsd->eth.rx_discards); | |
532d283d SN |
890 | i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port), |
891 | I40E_GLPRT_UPRCL(hw->port), | |
892 | pf->stat_offsets_loaded, | |
893 | &osd->eth.rx_unicast, | |
894 | &nsd->eth.rx_unicast); | |
7812fddc SN |
895 | i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port), |
896 | I40E_GLPRT_MPRCL(hw->port), | |
897 | pf->stat_offsets_loaded, | |
898 | &osd->eth.rx_multicast, | |
899 | &nsd->eth.rx_multicast); | |
532d283d SN |
900 | i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port), |
901 | I40E_GLPRT_BPRCL(hw->port), | |
902 | pf->stat_offsets_loaded, | |
903 | &osd->eth.rx_broadcast, | |
904 | &nsd->eth.rx_broadcast); | |
905 | i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port), | |
906 | I40E_GLPRT_UPTCL(hw->port), | |
907 | pf->stat_offsets_loaded, | |
908 | &osd->eth.tx_unicast, | |
909 | &nsd->eth.tx_unicast); | |
910 | i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port), | |
911 | I40E_GLPRT_MPTCL(hw->port), | |
912 | pf->stat_offsets_loaded, | |
913 | &osd->eth.tx_multicast, | |
914 | &nsd->eth.tx_multicast); | |
915 | i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port), | |
916 | I40E_GLPRT_BPTCL(hw->port), | |
917 | pf->stat_offsets_loaded, | |
918 | &osd->eth.tx_broadcast, | |
919 | &nsd->eth.tx_broadcast); | |
41c445ff | 920 | |
7812fddc SN |
921 | i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port), |
922 | pf->stat_offsets_loaded, | |
923 | &osd->tx_dropped_link_down, | |
924 | &nsd->tx_dropped_link_down); | |
41c445ff | 925 | |
7812fddc SN |
926 | i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port), |
927 | pf->stat_offsets_loaded, | |
928 | &osd->crc_errors, &nsd->crc_errors); | |
41c445ff | 929 | |
7812fddc SN |
930 | i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port), |
931 | pf->stat_offsets_loaded, | |
932 | &osd->illegal_bytes, &nsd->illegal_bytes); | |
41c445ff | 933 | |
7812fddc SN |
934 | i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port), |
935 | pf->stat_offsets_loaded, | |
936 | &osd->mac_local_faults, | |
937 | &nsd->mac_local_faults); | |
938 | i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port), | |
939 | pf->stat_offsets_loaded, | |
940 | &osd->mac_remote_faults, | |
941 | &nsd->mac_remote_faults); | |
41c445ff | 942 | |
7812fddc SN |
943 | i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port), |
944 | pf->stat_offsets_loaded, | |
945 | &osd->rx_length_errors, | |
946 | &nsd->rx_length_errors); | |
41c445ff | 947 | |
7812fddc SN |
948 | i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port), |
949 | pf->stat_offsets_loaded, | |
950 | &osd->link_xon_rx, &nsd->link_xon_rx); | |
951 | i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port), | |
952 | pf->stat_offsets_loaded, | |
953 | &osd->link_xon_tx, &nsd->link_xon_tx); | |
95db239f NP |
954 | i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port), |
955 | pf->stat_offsets_loaded, | |
956 | &osd->link_xoff_rx, &nsd->link_xoff_rx); | |
7812fddc SN |
957 | i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port), |
958 | pf->stat_offsets_loaded, | |
959 | &osd->link_xoff_tx, &nsd->link_xoff_tx); | |
41c445ff | 960 | |
7812fddc | 961 | for (i = 0; i < 8; i++) { |
95db239f NP |
962 | i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i), |
963 | pf->stat_offsets_loaded, | |
964 | &osd->priority_xoff_rx[i], | |
965 | &nsd->priority_xoff_rx[i]); | |
7812fddc | 966 | i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i), |
41c445ff | 967 | pf->stat_offsets_loaded, |
7812fddc SN |
968 | &osd->priority_xon_rx[i], |
969 | &nsd->priority_xon_rx[i]); | |
970 | i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i), | |
41c445ff | 971 | pf->stat_offsets_loaded, |
7812fddc SN |
972 | &osd->priority_xon_tx[i], |
973 | &nsd->priority_xon_tx[i]); | |
974 | i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i), | |
41c445ff | 975 | pf->stat_offsets_loaded, |
7812fddc SN |
976 | &osd->priority_xoff_tx[i], |
977 | &nsd->priority_xoff_tx[i]); | |
978 | i40e_stat_update32(hw, | |
979 | I40E_GLPRT_RXON2OFFCNT(hw->port, i), | |
bee5af7e | 980 | pf->stat_offsets_loaded, |
7812fddc SN |
981 | &osd->priority_xon_2_xoff[i], |
982 | &nsd->priority_xon_2_xoff[i]); | |
41c445ff JB |
983 | } |
984 | ||
7812fddc SN |
985 | i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port), |
986 | I40E_GLPRT_PRC64L(hw->port), | |
987 | pf->stat_offsets_loaded, | |
988 | &osd->rx_size_64, &nsd->rx_size_64); | |
989 | i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port), | |
990 | I40E_GLPRT_PRC127L(hw->port), | |
991 | pf->stat_offsets_loaded, | |
992 | &osd->rx_size_127, &nsd->rx_size_127); | |
993 | i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port), | |
994 | I40E_GLPRT_PRC255L(hw->port), | |
995 | pf->stat_offsets_loaded, | |
996 | &osd->rx_size_255, &nsd->rx_size_255); | |
997 | i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port), | |
998 | I40E_GLPRT_PRC511L(hw->port), | |
999 | pf->stat_offsets_loaded, | |
1000 | &osd->rx_size_511, &nsd->rx_size_511); | |
1001 | i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port), | |
1002 | I40E_GLPRT_PRC1023L(hw->port), | |
1003 | pf->stat_offsets_loaded, | |
1004 | &osd->rx_size_1023, &nsd->rx_size_1023); | |
1005 | i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port), | |
1006 | I40E_GLPRT_PRC1522L(hw->port), | |
1007 | pf->stat_offsets_loaded, | |
1008 | &osd->rx_size_1522, &nsd->rx_size_1522); | |
1009 | i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port), | |
1010 | I40E_GLPRT_PRC9522L(hw->port), | |
1011 | pf->stat_offsets_loaded, | |
1012 | &osd->rx_size_big, &nsd->rx_size_big); | |
1013 | ||
1014 | i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port), | |
1015 | I40E_GLPRT_PTC64L(hw->port), | |
1016 | pf->stat_offsets_loaded, | |
1017 | &osd->tx_size_64, &nsd->tx_size_64); | |
1018 | i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port), | |
1019 | I40E_GLPRT_PTC127L(hw->port), | |
1020 | pf->stat_offsets_loaded, | |
1021 | &osd->tx_size_127, &nsd->tx_size_127); | |
1022 | i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port), | |
1023 | I40E_GLPRT_PTC255L(hw->port), | |
1024 | pf->stat_offsets_loaded, | |
1025 | &osd->tx_size_255, &nsd->tx_size_255); | |
1026 | i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port), | |
1027 | I40E_GLPRT_PTC511L(hw->port), | |
1028 | pf->stat_offsets_loaded, | |
1029 | &osd->tx_size_511, &nsd->tx_size_511); | |
1030 | i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port), | |
1031 | I40E_GLPRT_PTC1023L(hw->port), | |
1032 | pf->stat_offsets_loaded, | |
1033 | &osd->tx_size_1023, &nsd->tx_size_1023); | |
1034 | i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port), | |
1035 | I40E_GLPRT_PTC1522L(hw->port), | |
1036 | pf->stat_offsets_loaded, | |
1037 | &osd->tx_size_1522, &nsd->tx_size_1522); | |
1038 | i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port), | |
1039 | I40E_GLPRT_PTC9522L(hw->port), | |
1040 | pf->stat_offsets_loaded, | |
1041 | &osd->tx_size_big, &nsd->tx_size_big); | |
1042 | ||
1043 | i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port), | |
1044 | pf->stat_offsets_loaded, | |
1045 | &osd->rx_undersize, &nsd->rx_undersize); | |
1046 | i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port), | |
1047 | pf->stat_offsets_loaded, | |
1048 | &osd->rx_fragments, &nsd->rx_fragments); | |
1049 | i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port), | |
1050 | pf->stat_offsets_loaded, | |
1051 | &osd->rx_oversize, &nsd->rx_oversize); | |
1052 | i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port), | |
1053 | pf->stat_offsets_loaded, | |
1054 | &osd->rx_jabber, &nsd->rx_jabber); | |
1055 | ||
433c47de | 1056 | /* FDIR stats */ |
0dc8692e MS |
1057 | i40e_stat_update_and_clear32(hw, |
1058 | I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(hw->pf_id)), | |
1059 | &nsd->fd_atr_match); | |
1060 | i40e_stat_update_and_clear32(hw, | |
1061 | I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(hw->pf_id)), | |
1062 | &nsd->fd_sb_match); | |
1063 | i40e_stat_update_and_clear32(hw, | |
1064 | I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(hw->pf_id)), | |
1065 | &nsd->fd_atr_tunnel_match); | |
433c47de | 1066 | |
7812fddc SN |
1067 | val = rd32(hw, I40E_PRTPM_EEE_STAT); |
1068 | nsd->tx_lpi_status = | |
1069 | (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >> | |
1070 | I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT; | |
1071 | nsd->rx_lpi_status = | |
1072 | (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >> | |
1073 | I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT; | |
1074 | i40e_stat_update32(hw, I40E_PRTPM_TLPIC, | |
1075 | pf->stat_offsets_loaded, | |
1076 | &osd->tx_lpi_count, &nsd->tx_lpi_count); | |
1077 | i40e_stat_update32(hw, I40E_PRTPM_RLPIC, | |
1078 | pf->stat_offsets_loaded, | |
1079 | &osd->rx_lpi_count, &nsd->rx_lpi_count); | |
1080 | ||
d0389e51 | 1081 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED && |
47994c11 | 1082 | !(pf->flags & I40E_FLAG_FD_SB_AUTO_DISABLED)) |
d0389e51 ASJ |
1083 | nsd->fd_sb_status = true; |
1084 | else | |
1085 | nsd->fd_sb_status = false; | |
1086 | ||
1087 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED && | |
47994c11 | 1088 | !(pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED)) |
d0389e51 ASJ |
1089 | nsd->fd_atr_status = true; |
1090 | else | |
1091 | nsd->fd_atr_status = false; | |
1092 | ||
41c445ff JB |
1093 | pf->stat_offsets_loaded = true; |
1094 | } | |
1095 | ||
7812fddc SN |
1096 | /** |
1097 | * i40e_update_stats - Update the various statistics counters. | |
1098 | * @vsi: the VSI to be updated | |
1099 | * | |
1100 | * Update the various stats for this VSI and its related entities. | |
1101 | **/ | |
1102 | void i40e_update_stats(struct i40e_vsi *vsi) | |
1103 | { | |
1104 | struct i40e_pf *pf = vsi->back; | |
1105 | ||
1106 | if (vsi == pf->vsi[pf->lan_vsi]) | |
1107 | i40e_update_pf_stats(pf); | |
1108 | ||
1109 | i40e_update_vsi_stats(vsi); | |
1110 | } | |
1111 | ||
41c445ff JB |
1112 | /** |
1113 | * i40e_find_filter - Search VSI filter list for specific mac/vlan filter | |
1114 | * @vsi: the VSI to be searched | |
1115 | * @macaddr: the MAC address | |
1116 | * @vlan: the vlan | |
41c445ff JB |
1117 | * |
1118 | * Returns ptr to the filter object or NULL | |
1119 | **/ | |
1120 | static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi, | |
6622f5cd | 1121 | const u8 *macaddr, s16 vlan) |
41c445ff JB |
1122 | { |
1123 | struct i40e_mac_filter *f; | |
278e7d0b | 1124 | u64 key; |
41c445ff JB |
1125 | |
1126 | if (!vsi || !macaddr) | |
1127 | return NULL; | |
1128 | ||
278e7d0b JK |
1129 | key = i40e_addr_to_hkey(macaddr); |
1130 | hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) { | |
41c445ff | 1131 | if ((ether_addr_equal(macaddr, f->macaddr)) && |
1bc87e80 | 1132 | (vlan == f->vlan)) |
41c445ff JB |
1133 | return f; |
1134 | } | |
1135 | return NULL; | |
1136 | } | |
1137 | ||
1138 | /** | |
1139 | * i40e_find_mac - Find a mac addr in the macvlan filters list | |
1140 | * @vsi: the VSI to be searched | |
1141 | * @macaddr: the MAC address we are searching for | |
41c445ff JB |
1142 | * |
1143 | * Returns the first filter with the provided MAC address or NULL if | |
1144 | * MAC address was not found | |
1145 | **/ | |
6622f5cd | 1146 | struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr) |
41c445ff JB |
1147 | { |
1148 | struct i40e_mac_filter *f; | |
278e7d0b | 1149 | u64 key; |
41c445ff JB |
1150 | |
1151 | if (!vsi || !macaddr) | |
1152 | return NULL; | |
1153 | ||
278e7d0b JK |
1154 | key = i40e_addr_to_hkey(macaddr); |
1155 | hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) { | |
1bc87e80 | 1156 | if ((ether_addr_equal(macaddr, f->macaddr))) |
41c445ff JB |
1157 | return f; |
1158 | } | |
1159 | return NULL; | |
1160 | } | |
1161 | ||
1162 | /** | |
1163 | * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode | |
1164 | * @vsi: the VSI to be searched | |
1165 | * | |
1166 | * Returns true if VSI is in vlan mode or false otherwise | |
1167 | **/ | |
1168 | bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi) | |
1169 | { | |
cbebb85f JK |
1170 | /* If we have a PVID, always operate in VLAN mode */ |
1171 | if (vsi->info.pvid) | |
1172 | return true; | |
1173 | ||
1174 | /* We need to operate in VLAN mode whenever we have any filters with | |
1175 | * a VLAN other than I40E_VLAN_ALL. We could check the table each | |
1176 | * time, incurring search cost repeatedly. However, we can notice two | |
1177 | * things: | |
1178 | * | |
1179 | * 1) the only place where we can gain a VLAN filter is in | |
1180 | * i40e_add_filter. | |
1181 | * | |
1182 | * 2) the only place where filters are actually removed is in | |
0b7c8b5d | 1183 | * i40e_sync_filters_subtask. |
cbebb85f JK |
1184 | * |
1185 | * Thus, we can simply use a boolean value, has_vlan_filters which we | |
1186 | * will set to true when we add a VLAN filter in i40e_add_filter. Then | |
1187 | * we have to perform the full search after deleting filters in | |
0b7c8b5d | 1188 | * i40e_sync_filters_subtask, but we already have to search |
cbebb85f JK |
1189 | * filters here and can perform the check at the same time. This |
1190 | * results in avoiding embedding a loop for VLAN mode inside another | |
1191 | * loop over all the filters, and should maintain correctness as noted | |
1192 | * above. | |
41c445ff | 1193 | */ |
cbebb85f | 1194 | return vsi->has_vlan_filter; |
41c445ff JB |
1195 | } |
1196 | ||
489a3265 JK |
1197 | /** |
1198 | * i40e_correct_mac_vlan_filters - Correct non-VLAN filters if necessary | |
1199 | * @vsi: the VSI to configure | |
1200 | * @tmp_add_list: list of filters ready to be added | |
1201 | * @tmp_del_list: list of filters ready to be deleted | |
1202 | * @vlan_filters: the number of active VLAN filters | |
1203 | * | |
1204 | * Update VLAN=0 and VLAN=-1 (I40E_VLAN_ANY) filters properly so that they | |
1205 | * behave as expected. If we have any active VLAN filters remaining or about | |
1206 | * to be added then we need to update non-VLAN filters to be marked as VLAN=0 | |
1207 | * so that they only match against untagged traffic. If we no longer have any | |
1208 | * active VLAN filters, we need to make all non-VLAN filters marked as VLAN=-1 | |
1209 | * so that they match against both tagged and untagged traffic. In this way, | |
1210 | * we ensure that we correctly receive the desired traffic. This ensures that | |
1211 | * when we have an active VLAN we will receive only untagged traffic and | |
1212 | * traffic matching active VLANs. If we have no active VLANs then we will | |
1213 | * operate in non-VLAN mode and receive all traffic, tagged or untagged. | |
1214 | * | |
1215 | * Finally, in a similar fashion, this function also corrects filters when | |
1216 | * there is an active PVID assigned to this VSI. | |
1217 | * | |
1218 | * In case of memory allocation failure return -ENOMEM. Otherwise, return 0. | |
1219 | * | |
1220 | * This function is only expected to be called from within | |
1221 | * i40e_sync_vsi_filters. | |
1222 | * | |
1223 | * NOTE: This function expects to be called while under the | |
1224 | * mac_filter_hash_lock | |
1225 | */ | |
1226 | static int i40e_correct_mac_vlan_filters(struct i40e_vsi *vsi, | |
1227 | struct hlist_head *tmp_add_list, | |
1228 | struct hlist_head *tmp_del_list, | |
1229 | int vlan_filters) | |
1230 | { | |
5cb25901 | 1231 | s16 pvid = le16_to_cpu(vsi->info.pvid); |
489a3265 | 1232 | struct i40e_mac_filter *f, *add_head; |
671889e6 | 1233 | struct i40e_new_mac_filter *new; |
489a3265 JK |
1234 | struct hlist_node *h; |
1235 | int bkt, new_vlan; | |
1236 | ||
1237 | /* To determine if a particular filter needs to be replaced we | |
1238 | * have the three following conditions: | |
1239 | * | |
1240 | * a) if we have a PVID assigned, then all filters which are | |
1241 | * not marked as VLAN=PVID must be replaced with filters that | |
1242 | * are. | |
1243 | * b) otherwise, if we have any active VLANS, all filters | |
1244 | * which are marked as VLAN=-1 must be replaced with | |
1245 | * filters marked as VLAN=0 | |
1246 | * c) finally, if we do not have any active VLANS, all filters | |
1247 | * which are marked as VLAN=0 must be replaced with filters | |
1248 | * marked as VLAN=-1 | |
1249 | */ | |
1250 | ||
1251 | /* Update the filters about to be added in place */ | |
671889e6 | 1252 | hlist_for_each_entry(new, tmp_add_list, hlist) { |
5cb25901 JK |
1253 | if (pvid && new->f->vlan != pvid) |
1254 | new->f->vlan = pvid; | |
671889e6 JK |
1255 | else if (vlan_filters && new->f->vlan == I40E_VLAN_ANY) |
1256 | new->f->vlan = 0; | |
1257 | else if (!vlan_filters && new->f->vlan == 0) | |
1258 | new->f->vlan = I40E_VLAN_ANY; | |
489a3265 JK |
1259 | } |
1260 | ||
1261 | /* Update the remaining active filters */ | |
1262 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { | |
1263 | /* Combine the checks for whether a filter needs to be changed | |
1264 | * and then determine the new VLAN inside the if block, in | |
1265 | * order to avoid duplicating code for adding the new filter | |
1266 | * then deleting the old filter. | |
1267 | */ | |
5cb25901 | 1268 | if ((pvid && f->vlan != pvid) || |
489a3265 JK |
1269 | (vlan_filters && f->vlan == I40E_VLAN_ANY) || |
1270 | (!vlan_filters && f->vlan == 0)) { | |
1271 | /* Determine the new vlan we will be adding */ | |
5cb25901 JK |
1272 | if (pvid) |
1273 | new_vlan = pvid; | |
489a3265 JK |
1274 | else if (vlan_filters) |
1275 | new_vlan = 0; | |
1276 | else | |
1277 | new_vlan = I40E_VLAN_ANY; | |
1278 | ||
1279 | /* Create the new filter */ | |
1280 | add_head = i40e_add_filter(vsi, f->macaddr, new_vlan); | |
1281 | if (!add_head) | |
1282 | return -ENOMEM; | |
1283 | ||
671889e6 JK |
1284 | /* Create a temporary i40e_new_mac_filter */ |
1285 | new = kzalloc(sizeof(*new), GFP_ATOMIC); | |
1286 | if (!new) | |
1287 | return -ENOMEM; | |
1288 | ||
1289 | new->f = add_head; | |
1290 | new->state = add_head->state; | |
1291 | ||
1292 | /* Add the new filter to the tmp list */ | |
1293 | hlist_add_head(&new->hlist, tmp_add_list); | |
489a3265 JK |
1294 | |
1295 | /* Put the original filter into the delete list */ | |
1296 | f->state = I40E_FILTER_REMOVE; | |
1297 | hash_del(&f->hlist); | |
1298 | hlist_add_head(&f->hlist, tmp_del_list); | |
1299 | } | |
1300 | } | |
1301 | ||
1302 | vsi->has_vlan_filter = !!vlan_filters; | |
1303 | ||
1304 | return 0; | |
1305 | } | |
1306 | ||
1596b5dd JK |
1307 | /** |
1308 | * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM | |
1309 | * @vsi: the PF Main VSI - inappropriate for any other VSI | |
1310 | * @macaddr: the MAC address | |
1311 | * | |
1312 | * Remove whatever filter the firmware set up so the driver can manage | |
1313 | * its own filtering intelligently. | |
1314 | **/ | |
1315 | static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr) | |
1316 | { | |
1317 | struct i40e_aqc_remove_macvlan_element_data element; | |
1318 | struct i40e_pf *pf = vsi->back; | |
1319 | ||
1320 | /* Only appropriate for the PF main VSI */ | |
1321 | if (vsi->type != I40E_VSI_MAIN) | |
1322 | return; | |
1323 | ||
1324 | memset(&element, 0, sizeof(element)); | |
1325 | ether_addr_copy(element.mac_addr, macaddr); | |
1326 | element.vlan_tag = 0; | |
1327 | /* Ignore error returns, some firmware does it this way... */ | |
1328 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; | |
1329 | i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); | |
1330 | ||
1331 | memset(&element, 0, sizeof(element)); | |
1332 | ether_addr_copy(element.mac_addr, macaddr); | |
1333 | element.vlan_tag = 0; | |
1334 | /* ...and some firmware does it this way. */ | |
1335 | element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH | | |
1336 | I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; | |
1337 | i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL); | |
1338 | } | |
1339 | ||
41c445ff JB |
1340 | /** |
1341 | * i40e_add_filter - Add a mac/vlan filter to the VSI | |
1342 | * @vsi: the VSI to be searched | |
1343 | * @macaddr: the MAC address | |
1344 | * @vlan: the vlan | |
41c445ff JB |
1345 | * |
1346 | * Returns ptr to the filter object or NULL when no memory available. | |
21659035 | 1347 | * |
278e7d0b | 1348 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
21659035 | 1349 | * being held. |
41c445ff JB |
1350 | **/ |
1351 | struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi, | |
6622f5cd | 1352 | const u8 *macaddr, s16 vlan) |
41c445ff JB |
1353 | { |
1354 | struct i40e_mac_filter *f; | |
278e7d0b | 1355 | u64 key; |
41c445ff JB |
1356 | |
1357 | if (!vsi || !macaddr) | |
1358 | return NULL; | |
1359 | ||
1bc87e80 | 1360 | f = i40e_find_filter(vsi, macaddr, vlan); |
41c445ff JB |
1361 | if (!f) { |
1362 | f = kzalloc(sizeof(*f), GFP_ATOMIC); | |
1363 | if (!f) | |
1bc87e80 | 1364 | return NULL; |
41c445ff | 1365 | |
cbebb85f JK |
1366 | /* Update the boolean indicating if we need to function in |
1367 | * VLAN mode. | |
1368 | */ | |
1369 | if (vlan >= 0) | |
1370 | vsi->has_vlan_filter = true; | |
1371 | ||
9a173901 | 1372 | ether_addr_copy(f->macaddr, macaddr); |
41c445ff | 1373 | f->vlan = vlan; |
c3c7ea27 MW |
1374 | /* If we're in overflow promisc mode, set the state directly |
1375 | * to failed, so we don't bother to try sending the filter | |
1376 | * to the hardware. | |
1377 | */ | |
0da36b97 | 1378 | if (test_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state)) |
c3c7ea27 MW |
1379 | f->state = I40E_FILTER_FAILED; |
1380 | else | |
1381 | f->state = I40E_FILTER_NEW; | |
278e7d0b JK |
1382 | INIT_HLIST_NODE(&f->hlist); |
1383 | ||
1384 | key = i40e_addr_to_hkey(macaddr); | |
1385 | hash_add(vsi->mac_filter_hash, &f->hlist, key); | |
41c445ff | 1386 | |
41c445ff JB |
1387 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; |
1388 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
1389 | } | |
1390 | ||
1bc87e80 JK |
1391 | /* If we're asked to add a filter that has been marked for removal, it |
1392 | * is safe to simply restore it to active state. __i40e_del_filter | |
1393 | * will have simply deleted any filters which were previously marked | |
1394 | * NEW or FAILED, so if it is currently marked REMOVE it must have | |
1395 | * previously been ACTIVE. Since we haven't yet run the sync filters | |
1396 | * task, just restore this filter to the ACTIVE state so that the | |
1397 | * sync task leaves it in place | |
1398 | */ | |
1399 | if (f->state == I40E_FILTER_REMOVE) | |
1400 | f->state = I40E_FILTER_ACTIVE; | |
1401 | ||
41c445ff JB |
1402 | return f; |
1403 | } | |
1404 | ||
1405 | /** | |
290d2557 JK |
1406 | * __i40e_del_filter - Remove a specific filter from the VSI |
1407 | * @vsi: VSI to remove from | |
1408 | * @f: the filter to remove from the list | |
1409 | * | |
1410 | * This function should be called instead of i40e_del_filter only if you know | |
1411 | * the exact filter you will remove already, such as via i40e_find_filter or | |
1412 | * i40e_find_mac. | |
21659035 | 1413 | * |
278e7d0b | 1414 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
21659035 | 1415 | * being held. |
c3c7ea27 MW |
1416 | * ANOTHER NOTE: This function MUST be called from within the context of |
1417 | * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe() | |
1418 | * instead of list_for_each_entry(). | |
41c445ff | 1419 | **/ |
148141bb | 1420 | void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f) |
41c445ff | 1421 | { |
1bc87e80 | 1422 | if (!f) |
41c445ff JB |
1423 | return; |
1424 | ||
a410c821 AB |
1425 | /* If the filter was never added to firmware then we can just delete it |
1426 | * directly and we don't want to set the status to remove or else an | |
1427 | * admin queue command will unnecessarily fire. | |
1428 | */ | |
1bc87e80 JK |
1429 | if ((f->state == I40E_FILTER_FAILED) || |
1430 | (f->state == I40E_FILTER_NEW)) { | |
278e7d0b | 1431 | hash_del(&f->hlist); |
1bc87e80 | 1432 | kfree(f); |
41c445ff | 1433 | } else { |
1bc87e80 | 1434 | f->state = I40E_FILTER_REMOVE; |
41c445ff | 1435 | } |
a410c821 AB |
1436 | |
1437 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
1438 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
41c445ff JB |
1439 | } |
1440 | ||
290d2557 JK |
1441 | /** |
1442 | * i40e_del_filter - Remove a MAC/VLAN filter from the VSI | |
1443 | * @vsi: the VSI to be searched | |
1444 | * @macaddr: the MAC address | |
1445 | * @vlan: the VLAN | |
1446 | * | |
278e7d0b | 1447 | * NOTE: This function is expected to be called with mac_filter_hash_lock |
290d2557 JK |
1448 | * being held. |
1449 | * ANOTHER NOTE: This function MUST be called from within the context of | |
1450 | * the "safe" variants of any list iterators, e.g. list_for_each_entry_safe() | |
1451 | * instead of list_for_each_entry(). | |
1452 | **/ | |
1453 | void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan) | |
1454 | { | |
1455 | struct i40e_mac_filter *f; | |
1456 | ||
1457 | if (!vsi || !macaddr) | |
1458 | return; | |
1459 | ||
1460 | f = i40e_find_filter(vsi, macaddr, vlan); | |
1461 | __i40e_del_filter(vsi, f); | |
1462 | } | |
1463 | ||
35ec2ff3 | 1464 | /** |
feffdbe4 | 1465 | * i40e_add_mac_filter - Add a MAC filter for all active VLANs |
35ec2ff3 JK |
1466 | * @vsi: the VSI to be searched |
1467 | * @macaddr: the mac address to be filtered | |
1468 | * | |
feffdbe4 JK |
1469 | * If we're not in VLAN mode, just add the filter to I40E_VLAN_ANY. Otherwise, |
1470 | * go through all the macvlan filters and add a macvlan filter for each | |
5feb3d7b JK |
1471 | * unique vlan that already exists. If a PVID has been assigned, instead only |
1472 | * add the macaddr to that VLAN. | |
35ec2ff3 | 1473 | * |
5feb3d7b | 1474 | * Returns last filter added on success, else NULL |
35ec2ff3 | 1475 | **/ |
feffdbe4 JK |
1476 | struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi, |
1477 | const u8 *macaddr) | |
35ec2ff3 | 1478 | { |
5feb3d7b | 1479 | struct i40e_mac_filter *f, *add = NULL; |
278e7d0b JK |
1480 | struct hlist_node *h; |
1481 | int bkt; | |
5feb3d7b JK |
1482 | |
1483 | if (vsi->info.pvid) | |
1484 | return i40e_add_filter(vsi, macaddr, | |
1485 | le16_to_cpu(vsi->info.pvid)); | |
35ec2ff3 | 1486 | |
7aaf9536 JK |
1487 | if (!i40e_is_vsi_in_vlan(vsi)) |
1488 | return i40e_add_filter(vsi, macaddr, I40E_VLAN_ANY); | |
1489 | ||
278e7d0b | 1490 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
57b341d6 JK |
1491 | if (f->state == I40E_FILTER_REMOVE) |
1492 | continue; | |
5feb3d7b JK |
1493 | add = i40e_add_filter(vsi, macaddr, f->vlan); |
1494 | if (!add) | |
1495 | return NULL; | |
35ec2ff3 JK |
1496 | } |
1497 | ||
5feb3d7b | 1498 | return add; |
35ec2ff3 JK |
1499 | } |
1500 | ||
1501 | /** | |
feffdbe4 | 1502 | * i40e_del_mac_filter - Remove a MAC filter from all VLANs |
35ec2ff3 JK |
1503 | * @vsi: the VSI to be searched |
1504 | * @macaddr: the mac address to be removed | |
1505 | * | |
feffdbe4 JK |
1506 | * Removes a given MAC address from a VSI regardless of what VLAN it has been |
1507 | * associated with. | |
35ec2ff3 JK |
1508 | * |
1509 | * Returns 0 for success, or error | |
1510 | **/ | |
feffdbe4 | 1511 | int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr) |
35ec2ff3 | 1512 | { |
278e7d0b JK |
1513 | struct i40e_mac_filter *f; |
1514 | struct hlist_node *h; | |
290d2557 | 1515 | bool found = false; |
278e7d0b | 1516 | int bkt; |
35ec2ff3 | 1517 | |
278e7d0b JK |
1518 | WARN(!spin_is_locked(&vsi->mac_filter_hash_lock), |
1519 | "Missing mac_filter_hash_lock\n"); | |
1520 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { | |
290d2557 JK |
1521 | if (ether_addr_equal(macaddr, f->macaddr)) { |
1522 | __i40e_del_filter(vsi, f); | |
1523 | found = true; | |
1524 | } | |
35ec2ff3 | 1525 | } |
290d2557 JK |
1526 | |
1527 | if (found) | |
35ec2ff3 | 1528 | return 0; |
290d2557 JK |
1529 | else |
1530 | return -ENOENT; | |
35ec2ff3 JK |
1531 | } |
1532 | ||
41c445ff JB |
1533 | /** |
1534 | * i40e_set_mac - NDO callback to set mac address | |
1535 | * @netdev: network interface device structure | |
1536 | * @p: pointer to an address structure | |
1537 | * | |
1538 | * Returns 0 on success, negative on failure | |
1539 | **/ | |
1540 | static int i40e_set_mac(struct net_device *netdev, void *p) | |
1541 | { | |
1542 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1543 | struct i40e_vsi *vsi = np->vsi; | |
30650cc5 SN |
1544 | struct i40e_pf *pf = vsi->back; |
1545 | struct i40e_hw *hw = &pf->hw; | |
41c445ff | 1546 | struct sockaddr *addr = p; |
41c445ff JB |
1547 | |
1548 | if (!is_valid_ether_addr(addr->sa_data)) | |
1549 | return -EADDRNOTAVAIL; | |
1550 | ||
30650cc5 SN |
1551 | if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) { |
1552 | netdev_info(netdev, "already using mac address %pM\n", | |
1553 | addr->sa_data); | |
1554 | return 0; | |
1555 | } | |
41c445ff | 1556 | |
0da36b97 JK |
1557 | if (test_bit(__I40E_VSI_DOWN, vsi->back->state) || |
1558 | test_bit(__I40E_RESET_RECOVERY_PENDING, vsi->back->state)) | |
80f6428f ASJ |
1559 | return -EADDRNOTAVAIL; |
1560 | ||
30650cc5 SN |
1561 | if (ether_addr_equal(hw->mac.addr, addr->sa_data)) |
1562 | netdev_info(netdev, "returning to hw mac address %pM\n", | |
1563 | hw->mac.addr); | |
1564 | else | |
1565 | netdev_info(netdev, "set new mac address %pM\n", addr->sa_data); | |
1566 | ||
278e7d0b | 1567 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
feffdbe4 JK |
1568 | i40e_del_mac_filter(vsi, netdev->dev_addr); |
1569 | i40e_add_mac_filter(vsi, addr->sa_data); | |
278e7d0b | 1570 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
c3c7ea27 | 1571 | ether_addr_copy(netdev->dev_addr, addr->sa_data); |
41c445ff JB |
1572 | if (vsi->type == I40E_VSI_MAIN) { |
1573 | i40e_status ret; | |
6995b36c | 1574 | |
41c445ff | 1575 | ret = i40e_aq_mac_address_write(&vsi->back->hw, |
cc41222c | 1576 | I40E_AQC_WRITE_TYPE_LAA_WOL, |
41c445ff | 1577 | addr->sa_data, NULL); |
c3c7ea27 MW |
1578 | if (ret) |
1579 | netdev_info(netdev, "Ignoring error from firmware on LAA update, status %s, AQ ret %s\n", | |
1580 | i40e_stat_str(hw, ret), | |
1581 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
30650cc5 SN |
1582 | } |
1583 | ||
c53934c6 JB |
1584 | /* schedule our worker thread which will take care of |
1585 | * applying the new filter changes | |
1586 | */ | |
1587 | i40e_service_event_schedule(vsi->back); | |
1588 | return 0; | |
41c445ff JB |
1589 | } |
1590 | ||
1591 | /** | |
1592 | * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc | |
1593 | * @vsi: the VSI being setup | |
1594 | * @ctxt: VSI context structure | |
1595 | * @enabled_tc: Enabled TCs bitmap | |
1596 | * @is_add: True if called before Add VSI | |
1597 | * | |
1598 | * Setup VSI queue mapping for enabled traffic classes. | |
1599 | **/ | |
1600 | static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi, | |
1601 | struct i40e_vsi_context *ctxt, | |
1602 | u8 enabled_tc, | |
1603 | bool is_add) | |
1604 | { | |
1605 | struct i40e_pf *pf = vsi->back; | |
1606 | u16 sections = 0; | |
1607 | u8 netdev_tc = 0; | |
1608 | u16 numtc = 0; | |
1609 | u16 qcount; | |
1610 | u8 offset; | |
1611 | u16 qmap; | |
1612 | int i; | |
4e3b35b0 | 1613 | u16 num_tc_qps = 0; |
41c445ff JB |
1614 | |
1615 | sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID; | |
1616 | offset = 0; | |
1617 | ||
1618 | if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { | |
1619 | /* Find numtc from enabled TC bitmap */ | |
1620 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 1621 | if (enabled_tc & BIT(i)) /* TC is enabled */ |
41c445ff JB |
1622 | numtc++; |
1623 | } | |
1624 | if (!numtc) { | |
1625 | dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n"); | |
1626 | numtc = 1; | |
1627 | } | |
1628 | } else { | |
1629 | /* At least TC0 is enabled in case of non-DCB case */ | |
1630 | numtc = 1; | |
1631 | } | |
1632 | ||
1633 | vsi->tc_config.numtc = numtc; | |
1634 | vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1; | |
4e3b35b0 | 1635 | /* Number of queues per enabled TC */ |
7d64402f CS |
1636 | qcount = vsi->alloc_queue_pairs; |
1637 | ||
7f9ff476 | 1638 | num_tc_qps = qcount / numtc; |
e25d00b8 | 1639 | num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf)); |
41c445ff JB |
1640 | |
1641 | /* Setup queue offset/count for all TCs for given VSI */ | |
1642 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
1643 | /* See if the given TC is enabled for the given VSI */ | |
75f5cea9 | 1644 | if (vsi->tc_config.enabled_tc & BIT(i)) { |
41a1d04b | 1645 | /* TC is enabled */ |
41c445ff JB |
1646 | int pow, num_qps; |
1647 | ||
41c445ff JB |
1648 | switch (vsi->type) { |
1649 | case I40E_VSI_MAIN: | |
acd65448 HZ |
1650 | qcount = min_t(int, pf->alloc_rss_size, |
1651 | num_tc_qps); | |
41c445ff JB |
1652 | break; |
1653 | case I40E_VSI_FDIR: | |
1654 | case I40E_VSI_SRIOV: | |
1655 | case I40E_VSI_VMDQ2: | |
1656 | default: | |
4e3b35b0 | 1657 | qcount = num_tc_qps; |
41c445ff JB |
1658 | WARN_ON(i != 0); |
1659 | break; | |
1660 | } | |
4e3b35b0 NP |
1661 | vsi->tc_config.tc_info[i].qoffset = offset; |
1662 | vsi->tc_config.tc_info[i].qcount = qcount; | |
41c445ff | 1663 | |
1e200e4a | 1664 | /* find the next higher power-of-2 of num queue pairs */ |
4e3b35b0 | 1665 | num_qps = qcount; |
41c445ff | 1666 | pow = 0; |
41a1d04b | 1667 | while (num_qps && (BIT_ULL(pow) < qcount)) { |
41c445ff JB |
1668 | pow++; |
1669 | num_qps >>= 1; | |
1670 | } | |
1671 | ||
1672 | vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++; | |
1673 | qmap = | |
1674 | (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) | | |
1675 | (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT); | |
1676 | ||
4e3b35b0 | 1677 | offset += qcount; |
41c445ff JB |
1678 | } else { |
1679 | /* TC is not enabled so set the offset to | |
1680 | * default queue and allocate one queue | |
1681 | * for the given TC. | |
1682 | */ | |
1683 | vsi->tc_config.tc_info[i].qoffset = 0; | |
1684 | vsi->tc_config.tc_info[i].qcount = 1; | |
1685 | vsi->tc_config.tc_info[i].netdev_tc = 0; | |
1686 | ||
1687 | qmap = 0; | |
1688 | } | |
1689 | ctxt->info.tc_mapping[i] = cpu_to_le16(qmap); | |
1690 | } | |
1691 | ||
1692 | /* Set actual Tx/Rx queue pairs */ | |
1693 | vsi->num_queue_pairs = offset; | |
9a3bd2f1 ASJ |
1694 | if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) { |
1695 | if (vsi->req_queue_pairs > 0) | |
1696 | vsi->num_queue_pairs = vsi->req_queue_pairs; | |
26cdc443 | 1697 | else if (pf->flags & I40E_FLAG_MSIX_ENABLED) |
9a3bd2f1 ASJ |
1698 | vsi->num_queue_pairs = pf->num_lan_msix; |
1699 | } | |
41c445ff JB |
1700 | |
1701 | /* Scheduler section valid can only be set for ADD VSI */ | |
1702 | if (is_add) { | |
1703 | sections |= I40E_AQ_VSI_PROP_SCHED_VALID; | |
1704 | ||
1705 | ctxt->info.up_enable_bits = enabled_tc; | |
1706 | } | |
1707 | if (vsi->type == I40E_VSI_SRIOV) { | |
1708 | ctxt->info.mapping_flags |= | |
1709 | cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG); | |
1710 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
1711 | ctxt->info.queue_mapping[i] = | |
1712 | cpu_to_le16(vsi->base_queue + i); | |
1713 | } else { | |
1714 | ctxt->info.mapping_flags |= | |
1715 | cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG); | |
1716 | ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue); | |
1717 | } | |
1718 | ctxt->info.valid_sections |= cpu_to_le16(sections); | |
1719 | } | |
1720 | ||
6622f5cd JK |
1721 | /** |
1722 | * i40e_addr_sync - Callback for dev_(mc|uc)_sync to add address | |
1723 | * @netdev: the netdevice | |
1724 | * @addr: address to add | |
1725 | * | |
1726 | * Called by __dev_(mc|uc)_sync when an address needs to be added. We call | |
1727 | * __dev_(uc|mc)_sync from .set_rx_mode and guarantee to hold the hash lock. | |
1728 | */ | |
1729 | static int i40e_addr_sync(struct net_device *netdev, const u8 *addr) | |
1730 | { | |
1731 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1732 | struct i40e_vsi *vsi = np->vsi; | |
6622f5cd | 1733 | |
feffdbe4 | 1734 | if (i40e_add_mac_filter(vsi, addr)) |
6622f5cd JK |
1735 | return 0; |
1736 | else | |
1737 | return -ENOMEM; | |
1738 | } | |
1739 | ||
1740 | /** | |
1741 | * i40e_addr_unsync - Callback for dev_(mc|uc)_sync to remove address | |
1742 | * @netdev: the netdevice | |
1743 | * @addr: address to add | |
1744 | * | |
1745 | * Called by __dev_(mc|uc)_sync when an address needs to be removed. We call | |
1746 | * __dev_(uc|mc)_sync from .set_rx_mode and guarantee to hold the hash lock. | |
1747 | */ | |
1748 | static int i40e_addr_unsync(struct net_device *netdev, const u8 *addr) | |
1749 | { | |
1750 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
1751 | struct i40e_vsi *vsi = np->vsi; | |
1752 | ||
feffdbe4 | 1753 | i40e_del_mac_filter(vsi, addr); |
6622f5cd JK |
1754 | |
1755 | return 0; | |
1756 | } | |
1757 | ||
41c445ff JB |
1758 | /** |
1759 | * i40e_set_rx_mode - NDO callback to set the netdev filters | |
1760 | * @netdev: network interface device structure | |
1761 | **/ | |
1762 | static void i40e_set_rx_mode(struct net_device *netdev) | |
1763 | { | |
1764 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
41c445ff | 1765 | struct i40e_vsi *vsi = np->vsi; |
41c445ff | 1766 | |
278e7d0b | 1767 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 1768 | |
6622f5cd JK |
1769 | __dev_uc_sync(netdev, i40e_addr_sync, i40e_addr_unsync); |
1770 | __dev_mc_sync(netdev, i40e_addr_sync, i40e_addr_unsync); | |
41c445ff | 1771 | |
278e7d0b | 1772 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
1773 | |
1774 | /* check for other flag changes */ | |
1775 | if (vsi->current_netdev_flags != vsi->netdev->flags) { | |
1776 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
1777 | vsi->back->flags |= I40E_FLAG_FILTER_SYNC; | |
1778 | } | |
1779 | } | |
1780 | ||
21659035 | 1781 | /** |
671889e6 | 1782 | * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries |
4a2ce27b | 1783 | * @vsi: Pointer to VSI struct |
21659035 KP |
1784 | * @from: Pointer to list which contains MAC filter entries - changes to |
1785 | * those entries needs to be undone. | |
1786 | * | |
671889e6 | 1787 | * MAC filter entries from this list were slated for deletion. |
21659035 | 1788 | **/ |
671889e6 JK |
1789 | static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi, |
1790 | struct hlist_head *from) | |
21659035 | 1791 | { |
278e7d0b JK |
1792 | struct i40e_mac_filter *f; |
1793 | struct hlist_node *h; | |
1794 | ||
1795 | hlist_for_each_entry_safe(f, h, from, hlist) { | |
1796 | u64 key = i40e_addr_to_hkey(f->macaddr); | |
21659035 | 1797 | |
21659035 | 1798 | /* Move the element back into MAC filter list*/ |
278e7d0b JK |
1799 | hlist_del(&f->hlist); |
1800 | hash_add(vsi->mac_filter_hash, &f->hlist, key); | |
21659035 KP |
1801 | } |
1802 | } | |
1803 | ||
671889e6 JK |
1804 | /** |
1805 | * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries | |
1806 | * @vsi: Pointer to vsi struct | |
1807 | * @from: Pointer to list which contains MAC filter entries - changes to | |
1808 | * those entries needs to be undone. | |
1809 | * | |
1810 | * MAC filter entries from this list were slated for addition. | |
1811 | **/ | |
1812 | static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi, | |
1813 | struct hlist_head *from) | |
1814 | { | |
1815 | struct i40e_new_mac_filter *new; | |
1816 | struct hlist_node *h; | |
1817 | ||
1818 | hlist_for_each_entry_safe(new, h, from, hlist) { | |
1819 | /* We can simply free the wrapper structure */ | |
1820 | hlist_del(&new->hlist); | |
1821 | kfree(new); | |
1822 | } | |
1823 | } | |
1824 | ||
d88d40b0 JK |
1825 | /** |
1826 | * i40e_next_entry - Get the next non-broadcast filter from a list | |
671889e6 | 1827 | * @next: pointer to filter in list |
d88d40b0 JK |
1828 | * |
1829 | * Returns the next non-broadcast filter in the list. Required so that we | |
1830 | * ignore broadcast filters within the list, since these are not handled via | |
1831 | * the normal firmware update path. | |
1832 | */ | |
671889e6 JK |
1833 | static |
1834 | struct i40e_new_mac_filter *i40e_next_filter(struct i40e_new_mac_filter *next) | |
d88d40b0 | 1835 | { |
584a8870 JK |
1836 | hlist_for_each_entry_continue(next, hlist) { |
1837 | if (!is_broadcast_ether_addr(next->f->macaddr)) | |
1838 | return next; | |
d88d40b0 JK |
1839 | } |
1840 | ||
584a8870 | 1841 | return NULL; |
d88d40b0 JK |
1842 | } |
1843 | ||
21659035 | 1844 | /** |
c3c7ea27 MW |
1845 | * i40e_update_filter_state - Update filter state based on return data |
1846 | * from firmware | |
1847 | * @count: Number of filters added | |
1848 | * @add_list: return data from fw | |
1849 | * @head: pointer to first filter in current batch | |
21659035 | 1850 | * |
c3c7ea27 MW |
1851 | * MAC filter entries from list were slated to be added to device. Returns |
1852 | * number of successful filters. Note that 0 does NOT mean success! | |
21659035 | 1853 | **/ |
c3c7ea27 MW |
1854 | static int |
1855 | i40e_update_filter_state(int count, | |
1856 | struct i40e_aqc_add_macvlan_element_data *add_list, | |
671889e6 | 1857 | struct i40e_new_mac_filter *add_head) |
21659035 | 1858 | { |
c3c7ea27 MW |
1859 | int retval = 0; |
1860 | int i; | |
21659035 | 1861 | |
ac9e2390 JK |
1862 | for (i = 0; i < count; i++) { |
1863 | /* Always check status of each filter. We don't need to check | |
1864 | * the firmware return status because we pre-set the filter | |
1865 | * status to I40E_AQC_MM_ERR_NO_RES when sending the filter | |
1866 | * request to the adminq. Thus, if it no longer matches then | |
1867 | * we know the filter is active. | |
c3c7ea27 | 1868 | */ |
ac9e2390 | 1869 | if (add_list[i].match_method == I40E_AQC_MM_ERR_NO_RES) { |
c3c7ea27 | 1870 | add_head->state = I40E_FILTER_FAILED; |
ac9e2390 JK |
1871 | } else { |
1872 | add_head->state = I40E_FILTER_ACTIVE; | |
1873 | retval++; | |
c3c7ea27 | 1874 | } |
ac9e2390 | 1875 | |
d88d40b0 JK |
1876 | add_head = i40e_next_filter(add_head); |
1877 | if (!add_head) | |
1878 | break; | |
21659035 | 1879 | } |
ac9e2390 | 1880 | |
c3c7ea27 | 1881 | return retval; |
21659035 KP |
1882 | } |
1883 | ||
00936319 JK |
1884 | /** |
1885 | * i40e_aqc_del_filters - Request firmware to delete a set of filters | |
1886 | * @vsi: ptr to the VSI | |
1887 | * @vsi_name: name to display in messages | |
1888 | * @list: the list of filters to send to firmware | |
1889 | * @num_del: the number of filters to delete | |
1890 | * @retval: Set to -EIO on failure to delete | |
1891 | * | |
1892 | * Send a request to firmware via AdminQ to delete a set of filters. Uses | |
1893 | * *retval instead of a return value so that success does not force ret_val to | |
1894 | * be set to 0. This ensures that a sequence of calls to this function | |
1895 | * preserve the previous value of *retval on successful delete. | |
1896 | */ | |
1897 | static | |
1898 | void i40e_aqc_del_filters(struct i40e_vsi *vsi, const char *vsi_name, | |
1899 | struct i40e_aqc_remove_macvlan_element_data *list, | |
1900 | int num_del, int *retval) | |
1901 | { | |
1902 | struct i40e_hw *hw = &vsi->back->hw; | |
1903 | i40e_status aq_ret; | |
1904 | int aq_err; | |
1905 | ||
1906 | aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, list, num_del, NULL); | |
1907 | aq_err = hw->aq.asq_last_status; | |
1908 | ||
1909 | /* Explicitly ignore and do not report when firmware returns ENOENT */ | |
1910 | if (aq_ret && !(aq_err == I40E_AQ_RC_ENOENT)) { | |
1911 | *retval = -EIO; | |
1912 | dev_info(&vsi->back->pdev->dev, | |
1913 | "ignoring delete macvlan error on %s, err %s, aq_err %s\n", | |
1914 | vsi_name, i40e_stat_str(hw, aq_ret), | |
1915 | i40e_aq_str(hw, aq_err)); | |
1916 | } | |
1917 | } | |
1918 | ||
1919 | /** | |
1920 | * i40e_aqc_add_filters - Request firmware to add a set of filters | |
1921 | * @vsi: ptr to the VSI | |
1922 | * @vsi_name: name to display in messages | |
1923 | * @list: the list of filters to send to firmware | |
1924 | * @add_head: Position in the add hlist | |
1925 | * @num_add: the number of filters to add | |
1926 | * @promisc_change: set to true on exit if promiscuous mode was forced on | |
1927 | * | |
1928 | * Send a request to firmware via AdminQ to add a chunk of filters. Will set | |
1929 | * promisc_changed to true if the firmware has run out of space for more | |
1930 | * filters. | |
1931 | */ | |
1932 | static | |
1933 | void i40e_aqc_add_filters(struct i40e_vsi *vsi, const char *vsi_name, | |
1934 | struct i40e_aqc_add_macvlan_element_data *list, | |
671889e6 | 1935 | struct i40e_new_mac_filter *add_head, |
00936319 JK |
1936 | int num_add, bool *promisc_changed) |
1937 | { | |
1938 | struct i40e_hw *hw = &vsi->back->hw; | |
00936319 JK |
1939 | int aq_err, fcnt; |
1940 | ||
ac9e2390 | 1941 | i40e_aq_add_macvlan(hw, vsi->seid, list, num_add, NULL); |
00936319 | 1942 | aq_err = hw->aq.asq_last_status; |
ac9e2390 | 1943 | fcnt = i40e_update_filter_state(num_add, list, add_head); |
00936319 JK |
1944 | |
1945 | if (fcnt != num_add) { | |
1946 | *promisc_changed = true; | |
0da36b97 | 1947 | set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
00936319 JK |
1948 | dev_warn(&vsi->back->pdev->dev, |
1949 | "Error %s adding RX filters on %s, promiscuous mode forced on\n", | |
1950 | i40e_aq_str(hw, aq_err), | |
1951 | vsi_name); | |
1952 | } | |
1953 | } | |
1954 | ||
435c084a JK |
1955 | /** |
1956 | * i40e_aqc_broadcast_filter - Set promiscuous broadcast flags | |
1957 | * @vsi: pointer to the VSI | |
1958 | * @f: filter data | |
1959 | * | |
1960 | * This function sets or clears the promiscuous broadcast flags for VLAN | |
1961 | * filters in order to properly receive broadcast frames. Assumes that only | |
1962 | * broadcast filters are passed. | |
671889e6 JK |
1963 | * |
1964 | * Returns status indicating success or failure; | |
435c084a | 1965 | **/ |
671889e6 JK |
1966 | static i40e_status |
1967 | i40e_aqc_broadcast_filter(struct i40e_vsi *vsi, const char *vsi_name, | |
1968 | struct i40e_mac_filter *f) | |
435c084a JK |
1969 | { |
1970 | bool enable = f->state == I40E_FILTER_NEW; | |
1971 | struct i40e_hw *hw = &vsi->back->hw; | |
1972 | i40e_status aq_ret; | |
1973 | ||
1974 | if (f->vlan == I40E_VLAN_ANY) { | |
1975 | aq_ret = i40e_aq_set_vsi_broadcast(hw, | |
1976 | vsi->seid, | |
1977 | enable, | |
1978 | NULL); | |
1979 | } else { | |
1980 | aq_ret = i40e_aq_set_vsi_bc_promisc_on_vlan(hw, | |
1981 | vsi->seid, | |
1982 | enable, | |
1983 | f->vlan, | |
1984 | NULL); | |
1985 | } | |
1986 | ||
671889e6 | 1987 | if (aq_ret) |
435c084a JK |
1988 | dev_warn(&vsi->back->pdev->dev, |
1989 | "Error %s setting broadcast promiscuous mode on %s\n", | |
1990 | i40e_aq_str(hw, hw->aq.asq_last_status), | |
1991 | vsi_name); | |
671889e6 JK |
1992 | |
1993 | return aq_ret; | |
435c084a JK |
1994 | } |
1995 | ||
41c445ff JB |
1996 | /** |
1997 | * i40e_sync_vsi_filters - Update the VSI filter list to the HW | |
1998 | * @vsi: ptr to the VSI | |
1999 | * | |
2000 | * Push any outstanding VSI filter changes through the AdminQ. | |
2001 | * | |
2002 | * Returns 0 or error value | |
2003 | **/ | |
17652c63 | 2004 | int i40e_sync_vsi_filters(struct i40e_vsi *vsi) |
41c445ff | 2005 | { |
278e7d0b | 2006 | struct hlist_head tmp_add_list, tmp_del_list; |
671889e6 JK |
2007 | struct i40e_mac_filter *f; |
2008 | struct i40e_new_mac_filter *new, *add_head = NULL; | |
3e25a8f3 | 2009 | struct i40e_hw *hw = &vsi->back->hw; |
38326218 | 2010 | unsigned int failed_filters = 0; |
84f5ca6c | 2011 | unsigned int vlan_filters = 0; |
c3c7ea27 | 2012 | bool promisc_changed = false; |
2d1de828 | 2013 | char vsi_name[16] = "PF"; |
41c445ff | 2014 | int filter_list_len = 0; |
ea02e90b | 2015 | i40e_status aq_ret = 0; |
84f5ca6c | 2016 | u32 changed_flags = 0; |
278e7d0b | 2017 | struct hlist_node *h; |
41c445ff JB |
2018 | struct i40e_pf *pf; |
2019 | int num_add = 0; | |
2020 | int num_del = 0; | |
84f5ca6c | 2021 | int retval = 0; |
41c445ff | 2022 | u16 cmd_flags; |
c3c7ea27 | 2023 | int list_size; |
278e7d0b | 2024 | int bkt; |
41c445ff JB |
2025 | |
2026 | /* empty array typed pointers, kcalloc later */ | |
2027 | struct i40e_aqc_add_macvlan_element_data *add_list; | |
2028 | struct i40e_aqc_remove_macvlan_element_data *del_list; | |
2029 | ||
0da36b97 | 2030 | while (test_and_set_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state)) |
41c445ff JB |
2031 | usleep_range(1000, 2000); |
2032 | pf = vsi->back; | |
2033 | ||
2034 | if (vsi->netdev) { | |
2035 | changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags; | |
2036 | vsi->current_netdev_flags = vsi->netdev->flags; | |
2037 | } | |
2038 | ||
278e7d0b JK |
2039 | INIT_HLIST_HEAD(&tmp_add_list); |
2040 | INIT_HLIST_HEAD(&tmp_del_list); | |
21659035 | 2041 | |
2d1de828 SN |
2042 | if (vsi->type == I40E_VSI_SRIOV) |
2043 | snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id); | |
2044 | else if (vsi->type != I40E_VSI_MAIN) | |
2045 | snprintf(vsi_name, sizeof(vsi_name) - 1, "vsi %d", vsi->seid); | |
2046 | ||
41c445ff JB |
2047 | if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) { |
2048 | vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED; | |
2049 | ||
278e7d0b | 2050 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
c3c7ea27 | 2051 | /* Create a list of filters to delete. */ |
278e7d0b | 2052 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
c3c7ea27 | 2053 | if (f->state == I40E_FILTER_REMOVE) { |
c3c7ea27 | 2054 | /* Move the element into temporary del_list */ |
278e7d0b JK |
2055 | hash_del(&f->hlist); |
2056 | hlist_add_head(&f->hlist, &tmp_del_list); | |
84f5ca6c AB |
2057 | |
2058 | /* Avoid counting removed filters */ | |
2059 | continue; | |
c3c7ea27 MW |
2060 | } |
2061 | if (f->state == I40E_FILTER_NEW) { | |
671889e6 JK |
2062 | /* Create a temporary i40e_new_mac_filter */ |
2063 | new = kzalloc(sizeof(*new), GFP_ATOMIC); | |
2064 | if (!new) | |
2065 | goto err_no_memory_locked; | |
2066 | ||
2067 | /* Store pointer to the real filter */ | |
2068 | new->f = f; | |
2069 | new->state = f->state; | |
2070 | ||
2071 | /* Add it to the hash list */ | |
2072 | hlist_add_head(&new->hlist, &tmp_add_list); | |
21659035 | 2073 | } |
84f5ca6c | 2074 | |
489a3265 JK |
2075 | /* Count the number of active (current and new) VLAN |
2076 | * filters we have now. Does not count filters which | |
2077 | * are marked for deletion. | |
84f5ca6c AB |
2078 | */ |
2079 | if (f->vlan > 0) | |
2080 | vlan_filters++; | |
84f5ca6c AB |
2081 | } |
2082 | ||
489a3265 JK |
2083 | retval = i40e_correct_mac_vlan_filters(vsi, |
2084 | &tmp_add_list, | |
2085 | &tmp_del_list, | |
2086 | vlan_filters); | |
2087 | if (retval) | |
2088 | goto err_no_memory_locked; | |
84f5ca6c | 2089 | |
278e7d0b | 2090 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 KP |
2091 | } |
2092 | ||
2093 | /* Now process 'del_list' outside the lock */ | |
278e7d0b | 2094 | if (!hlist_empty(&tmp_del_list)) { |
3e25a8f3 | 2095 | filter_list_len = hw->aq.asq_buf_size / |
21659035 | 2096 | sizeof(struct i40e_aqc_remove_macvlan_element_data); |
c3c7ea27 | 2097 | list_size = filter_list_len * |
f1199998 | 2098 | sizeof(struct i40e_aqc_remove_macvlan_element_data); |
c3c7ea27 | 2099 | del_list = kzalloc(list_size, GFP_ATOMIC); |
4a2ce27b JK |
2100 | if (!del_list) |
2101 | goto err_no_memory; | |
21659035 | 2102 | |
278e7d0b | 2103 | hlist_for_each_entry_safe(f, h, &tmp_del_list, hlist) { |
41c445ff JB |
2104 | cmd_flags = 0; |
2105 | ||
435c084a | 2106 | /* handle broadcast filters by updating the broadcast |
d88d40b0 | 2107 | * promiscuous flag and release filter list. |
435c084a JK |
2108 | */ |
2109 | if (is_broadcast_ether_addr(f->macaddr)) { | |
2110 | i40e_aqc_broadcast_filter(vsi, vsi_name, f); | |
2111 | ||
2112 | hlist_del(&f->hlist); | |
2113 | kfree(f); | |
2114 | continue; | |
2115 | } | |
2116 | ||
41c445ff | 2117 | /* add to delete list */ |
9a173901 | 2118 | ether_addr_copy(del_list[num_del].mac_addr, f->macaddr); |
c3c7ea27 MW |
2119 | if (f->vlan == I40E_VLAN_ANY) { |
2120 | del_list[num_del].vlan_tag = 0; | |
a6cb9146 | 2121 | cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN; |
c3c7ea27 MW |
2122 | } else { |
2123 | del_list[num_del].vlan_tag = | |
2124 | cpu_to_le16((u16)(f->vlan)); | |
2125 | } | |
41c445ff | 2126 | |
41c445ff JB |
2127 | cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH; |
2128 | del_list[num_del].flags = cmd_flags; | |
2129 | num_del++; | |
2130 | ||
41c445ff JB |
2131 | /* flush a full buffer */ |
2132 | if (num_del == filter_list_len) { | |
00936319 JK |
2133 | i40e_aqc_del_filters(vsi, vsi_name, del_list, |
2134 | num_del, &retval); | |
c3c7ea27 | 2135 | memset(del_list, 0, list_size); |
00936319 | 2136 | num_del = 0; |
41c445ff | 2137 | } |
21659035 KP |
2138 | /* Release memory for MAC filter entries which were |
2139 | * synced up with HW. | |
2140 | */ | |
278e7d0b | 2141 | hlist_del(&f->hlist); |
21659035 | 2142 | kfree(f); |
41c445ff | 2143 | } |
21659035 | 2144 | |
41c445ff | 2145 | if (num_del) { |
00936319 JK |
2146 | i40e_aqc_del_filters(vsi, vsi_name, del_list, |
2147 | num_del, &retval); | |
41c445ff JB |
2148 | } |
2149 | ||
2150 | kfree(del_list); | |
2151 | del_list = NULL; | |
21659035 KP |
2152 | } |
2153 | ||
278e7d0b | 2154 | if (!hlist_empty(&tmp_add_list)) { |
c3c7ea27 | 2155 | /* Do all the adds now. */ |
3e25a8f3 | 2156 | filter_list_len = hw->aq.asq_buf_size / |
f1199998 | 2157 | sizeof(struct i40e_aqc_add_macvlan_element_data); |
c3c7ea27 MW |
2158 | list_size = filter_list_len * |
2159 | sizeof(struct i40e_aqc_add_macvlan_element_data); | |
2160 | add_list = kzalloc(list_size, GFP_ATOMIC); | |
4a2ce27b JK |
2161 | if (!add_list) |
2162 | goto err_no_memory; | |
2163 | ||
c3c7ea27 | 2164 | num_add = 0; |
671889e6 | 2165 | hlist_for_each_entry_safe(new, h, &tmp_add_list, hlist) { |
d19cb64b | 2166 | if (test_bit(__I40E_VSI_OVERFLOW_PROMISC, |
0da36b97 | 2167 | vsi->state)) { |
671889e6 | 2168 | new->state = I40E_FILTER_FAILED; |
c3c7ea27 MW |
2169 | continue; |
2170 | } | |
435c084a JK |
2171 | |
2172 | /* handle broadcast filters by updating the broadcast | |
2173 | * promiscuous flag instead of adding a MAC filter. | |
2174 | */ | |
671889e6 JK |
2175 | if (is_broadcast_ether_addr(new->f->macaddr)) { |
2176 | if (i40e_aqc_broadcast_filter(vsi, vsi_name, | |
2177 | new->f)) | |
2178 | new->state = I40E_FILTER_FAILED; | |
2179 | else | |
2180 | new->state = I40E_FILTER_ACTIVE; | |
435c084a JK |
2181 | continue; |
2182 | } | |
2183 | ||
41c445ff | 2184 | /* add to add array */ |
c3c7ea27 | 2185 | if (num_add == 0) |
671889e6 | 2186 | add_head = new; |
c3c7ea27 | 2187 | cmd_flags = 0; |
671889e6 JK |
2188 | ether_addr_copy(add_list[num_add].mac_addr, |
2189 | new->f->macaddr); | |
2190 | if (new->f->vlan == I40E_VLAN_ANY) { | |
c3c7ea27 MW |
2191 | add_list[num_add].vlan_tag = 0; |
2192 | cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN; | |
2193 | } else { | |
2194 | add_list[num_add].vlan_tag = | |
671889e6 | 2195 | cpu_to_le16((u16)(new->f->vlan)); |
c3c7ea27 | 2196 | } |
41c445ff | 2197 | add_list[num_add].queue_number = 0; |
ac9e2390 | 2198 | /* set invalid match method for later detection */ |
0266ac45 | 2199 | add_list[num_add].match_method = I40E_AQC_MM_ERR_NO_RES; |
41c445ff | 2200 | cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH; |
41c445ff JB |
2201 | add_list[num_add].flags = cpu_to_le16(cmd_flags); |
2202 | num_add++; | |
2203 | ||
2204 | /* flush a full buffer */ | |
2205 | if (num_add == filter_list_len) { | |
00936319 JK |
2206 | i40e_aqc_add_filters(vsi, vsi_name, add_list, |
2207 | add_head, num_add, | |
2208 | &promisc_changed); | |
c3c7ea27 | 2209 | memset(add_list, 0, list_size); |
41c445ff | 2210 | num_add = 0; |
41c445ff JB |
2211 | } |
2212 | } | |
2213 | if (num_add) { | |
00936319 JK |
2214 | i40e_aqc_add_filters(vsi, vsi_name, add_list, add_head, |
2215 | num_add, &promisc_changed); | |
41c445ff | 2216 | } |
c3c7ea27 MW |
2217 | /* Now move all of the filters from the temp add list back to |
2218 | * the VSI's list. | |
2219 | */ | |
278e7d0b | 2220 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
671889e6 JK |
2221 | hlist_for_each_entry_safe(new, h, &tmp_add_list, hlist) { |
2222 | /* Only update the state if we're still NEW */ | |
2223 | if (new->f->state == I40E_FILTER_NEW) | |
2224 | new->f->state = new->state; | |
2225 | hlist_del(&new->hlist); | |
2226 | kfree(new); | |
c3c7ea27 | 2227 | } |
278e7d0b | 2228 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff JB |
2229 | kfree(add_list); |
2230 | add_list = NULL; | |
c3c7ea27 | 2231 | } |
41c445ff | 2232 | |
38326218 JK |
2233 | /* Determine the number of active and failed filters. */ |
2234 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
2235 | vsi->active_filters = 0; | |
2236 | hash_for_each(vsi->mac_filter_hash, bkt, f, hlist) { | |
2237 | if (f->state == I40E_FILTER_ACTIVE) | |
2238 | vsi->active_filters++; | |
2239 | else if (f->state == I40E_FILTER_FAILED) | |
2240 | failed_filters++; | |
2241 | } | |
2242 | spin_unlock_bh(&vsi->mac_filter_hash_lock); | |
2243 | ||
2244 | /* If promiscuous mode has changed, we need to calculate a new | |
2245 | * threshold for when we are safe to exit | |
2246 | */ | |
2247 | if (promisc_changed) | |
2248 | vsi->promisc_threshold = (vsi->active_filters * 3) / 4; | |
2249 | ||
2250 | /* Check if we are able to exit overflow promiscuous mode. We can | |
2251 | * safely exit if we didn't just enter, we no longer have any failed | |
2252 | * filters, and we have reduced filters below the threshold value. | |
2253 | */ | |
0da36b97 | 2254 | if (test_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state) && |
38326218 | 2255 | !promisc_changed && !failed_filters && |
c3c7ea27 | 2256 | (vsi->active_filters < vsi->promisc_threshold)) { |
38326218 JK |
2257 | dev_info(&pf->pdev->dev, |
2258 | "filter logjam cleared on %s, leaving overflow promiscuous mode\n", | |
2259 | vsi_name); | |
0da36b97 | 2260 | clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
38326218 JK |
2261 | promisc_changed = true; |
2262 | vsi->promisc_threshold = 0; | |
41c445ff JB |
2263 | } |
2264 | ||
a856b5cb ASJ |
2265 | /* if the VF is not trusted do not do promisc */ |
2266 | if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) { | |
0da36b97 | 2267 | clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
a856b5cb ASJ |
2268 | goto out; |
2269 | } | |
2270 | ||
41c445ff JB |
2271 | /* check for changes in promiscuous modes */ |
2272 | if (changed_flags & IFF_ALLMULTI) { | |
2273 | bool cur_multipromisc; | |
6995b36c | 2274 | |
41c445ff | 2275 | cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI); |
ea02e90b MW |
2276 | aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw, |
2277 | vsi->seid, | |
2278 | cur_multipromisc, | |
2279 | NULL); | |
2280 | if (aq_ret) { | |
2281 | retval = i40e_aq_rc_to_posix(aq_ret, | |
3e25a8f3 | 2282 | hw->aq.asq_last_status); |
41c445ff | 2283 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
2284 | "set multi promisc failed on %s, err %s aq_err %s\n", |
2285 | vsi_name, | |
3e25a8f3 MW |
2286 | i40e_stat_str(hw, aq_ret), |
2287 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
ea02e90b | 2288 | } |
41c445ff | 2289 | } |
e5887239 AB |
2290 | |
2291 | if ((changed_flags & IFF_PROMISC) || promisc_changed) { | |
41c445ff | 2292 | bool cur_promisc; |
6995b36c | 2293 | |
41c445ff | 2294 | cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) || |
d19cb64b | 2295 | test_bit(__I40E_VSI_OVERFLOW_PROMISC, |
0da36b97 | 2296 | vsi->state)); |
6784ed5a ASJ |
2297 | if ((vsi->type == I40E_VSI_MAIN) && |
2298 | (pf->lan_veb != I40E_NO_VEB) && | |
2299 | !(pf->flags & I40E_FLAG_MFP_ENABLED)) { | |
92faef85 ASJ |
2300 | /* set defport ON for Main VSI instead of true promisc |
2301 | * this way we will get all unicast/multicast and VLAN | |
2302 | * promisc behavior but will not get VF or VMDq traffic | |
2303 | * replicated on the Main VSI. | |
2304 | */ | |
2305 | if (pf->cur_promisc != cur_promisc) { | |
2306 | pf->cur_promisc = cur_promisc; | |
5bc16031 MW |
2307 | if (cur_promisc) |
2308 | aq_ret = | |
2309 | i40e_aq_set_default_vsi(hw, | |
2310 | vsi->seid, | |
2311 | NULL); | |
2312 | else | |
2313 | aq_ret = | |
2314 | i40e_aq_clear_default_vsi(hw, | |
2315 | vsi->seid, | |
2316 | NULL); | |
2317 | if (aq_ret) { | |
2318 | retval = i40e_aq_rc_to_posix(aq_ret, | |
2319 | hw->aq.asq_last_status); | |
2320 | dev_info(&pf->pdev->dev, | |
2d1de828 SN |
2321 | "Set default VSI failed on %s, err %s, aq_err %s\n", |
2322 | vsi_name, | |
5bc16031 MW |
2323 | i40e_stat_str(hw, aq_ret), |
2324 | i40e_aq_str(hw, | |
2325 | hw->aq.asq_last_status)); | |
2326 | } | |
92faef85 ASJ |
2327 | } |
2328 | } else { | |
ea02e90b | 2329 | aq_ret = i40e_aq_set_vsi_unicast_promiscuous( |
3e25a8f3 | 2330 | hw, |
f1c7e72e | 2331 | vsi->seid, |
b5569892 ASJ |
2332 | cur_promisc, NULL, |
2333 | true); | |
ea02e90b MW |
2334 | if (aq_ret) { |
2335 | retval = | |
2336 | i40e_aq_rc_to_posix(aq_ret, | |
3e25a8f3 | 2337 | hw->aq.asq_last_status); |
92faef85 | 2338 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
2339 | "set unicast promisc failed on %s, err %s, aq_err %s\n", |
2340 | vsi_name, | |
3e25a8f3 MW |
2341 | i40e_stat_str(hw, aq_ret), |
2342 | i40e_aq_str(hw, | |
2343 | hw->aq.asq_last_status)); | |
ea02e90b MW |
2344 | } |
2345 | aq_ret = i40e_aq_set_vsi_multicast_promiscuous( | |
3e25a8f3 | 2346 | hw, |
92faef85 ASJ |
2347 | vsi->seid, |
2348 | cur_promisc, NULL); | |
ea02e90b MW |
2349 | if (aq_ret) { |
2350 | retval = | |
2351 | i40e_aq_rc_to_posix(aq_ret, | |
3e25a8f3 | 2352 | hw->aq.asq_last_status); |
92faef85 | 2353 | dev_info(&pf->pdev->dev, |
2d1de828 SN |
2354 | "set multicast promisc failed on %s, err %s, aq_err %s\n", |
2355 | vsi_name, | |
3e25a8f3 MW |
2356 | i40e_stat_str(hw, aq_ret), |
2357 | i40e_aq_str(hw, | |
2358 | hw->aq.asq_last_status)); | |
ea02e90b | 2359 | } |
92faef85 | 2360 | } |
ea02e90b MW |
2361 | aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw, |
2362 | vsi->seid, | |
2363 | cur_promisc, NULL); | |
2364 | if (aq_ret) { | |
2365 | retval = i40e_aq_rc_to_posix(aq_ret, | |
2366 | pf->hw.aq.asq_last_status); | |
1a10370a | 2367 | dev_info(&pf->pdev->dev, |
f1c7e72e | 2368 | "set brdcast promisc failed, err %s, aq_err %s\n", |
3e25a8f3 MW |
2369 | i40e_stat_str(hw, aq_ret), |
2370 | i40e_aq_str(hw, | |
2371 | hw->aq.asq_last_status)); | |
ea02e90b | 2372 | } |
41c445ff | 2373 | } |
ea02e90b | 2374 | out: |
2818ccd9 JB |
2375 | /* if something went wrong then set the changed flag so we try again */ |
2376 | if (retval) | |
2377 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
2378 | ||
0da36b97 | 2379 | clear_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state); |
ea02e90b | 2380 | return retval; |
4a2ce27b JK |
2381 | |
2382 | err_no_memory: | |
2383 | /* Restore elements on the temporary add and delete lists */ | |
2384 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
84f5ca6c | 2385 | err_no_memory_locked: |
671889e6 JK |
2386 | i40e_undo_del_filter_entries(vsi, &tmp_del_list); |
2387 | i40e_undo_add_filter_entries(vsi, &tmp_add_list); | |
4a2ce27b JK |
2388 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
2389 | ||
2390 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
0da36b97 | 2391 | clear_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state); |
4a2ce27b | 2392 | return -ENOMEM; |
41c445ff JB |
2393 | } |
2394 | ||
2395 | /** | |
2396 | * i40e_sync_filters_subtask - Sync the VSI filter list with HW | |
2397 | * @pf: board private structure | |
2398 | **/ | |
2399 | static void i40e_sync_filters_subtask(struct i40e_pf *pf) | |
2400 | { | |
2401 | int v; | |
2402 | ||
2403 | if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC)) | |
2404 | return; | |
2405 | pf->flags &= ~I40E_FLAG_FILTER_SYNC; | |
2406 | ||
505682cd | 2407 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff | 2408 | if (pf->vsi[v] && |
17652c63 JB |
2409 | (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) { |
2410 | int ret = i40e_sync_vsi_filters(pf->vsi[v]); | |
2411 | ||
2412 | if (ret) { | |
2413 | /* come back and try again later */ | |
2414 | pf->flags |= I40E_FLAG_FILTER_SYNC; | |
2415 | break; | |
2416 | } | |
2417 | } | |
41c445ff JB |
2418 | } |
2419 | } | |
2420 | ||
0c8493d9 BT |
2421 | /** |
2422 | * i40e_max_xdp_frame_size - returns the maximum allowed frame size for XDP | |
2423 | * @vsi: the vsi | |
2424 | **/ | |
2425 | static int i40e_max_xdp_frame_size(struct i40e_vsi *vsi) | |
2426 | { | |
2427 | if (PAGE_SIZE >= 8192 || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) | |
2428 | return I40E_RXBUFFER_2048; | |
2429 | else | |
2430 | return I40E_RXBUFFER_3072; | |
2431 | } | |
2432 | ||
41c445ff JB |
2433 | /** |
2434 | * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit | |
2435 | * @netdev: network interface device structure | |
2436 | * @new_mtu: new value for maximum frame size | |
2437 | * | |
2438 | * Returns 0 on success, negative on failure | |
2439 | **/ | |
2440 | static int i40e_change_mtu(struct net_device *netdev, int new_mtu) | |
2441 | { | |
2442 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
41c445ff | 2443 | struct i40e_vsi *vsi = np->vsi; |
0ef2d5af | 2444 | struct i40e_pf *pf = vsi->back; |
41c445ff | 2445 | |
0c8493d9 BT |
2446 | if (i40e_enabled_xdp_vsi(vsi)) { |
2447 | int frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
2448 | ||
2449 | if (frame_size > i40e_max_xdp_frame_size(vsi)) | |
2450 | return -EINVAL; | |
2451 | } | |
2452 | ||
41c445ff JB |
2453 | netdev_info(netdev, "changing MTU from %d to %d\n", |
2454 | netdev->mtu, new_mtu); | |
2455 | netdev->mtu = new_mtu; | |
2456 | if (netif_running(netdev)) | |
2457 | i40e_vsi_reinit_locked(vsi); | |
0ef2d5af MW |
2458 | pf->flags |= (I40E_FLAG_SERVICE_CLIENT_REQUESTED | |
2459 | I40E_FLAG_CLIENT_L2_CHANGE); | |
41c445ff JB |
2460 | return 0; |
2461 | } | |
2462 | ||
beb0dff1 JK |
2463 | /** |
2464 | * i40e_ioctl - Access the hwtstamp interface | |
2465 | * @netdev: network interface device structure | |
2466 | * @ifr: interface request data | |
2467 | * @cmd: ioctl command | |
2468 | **/ | |
2469 | int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |
2470 | { | |
2471 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2472 | struct i40e_pf *pf = np->vsi->back; | |
2473 | ||
2474 | switch (cmd) { | |
2475 | case SIOCGHWTSTAMP: | |
2476 | return i40e_ptp_get_ts_config(pf, ifr); | |
2477 | case SIOCSHWTSTAMP: | |
2478 | return i40e_ptp_set_ts_config(pf, ifr); | |
2479 | default: | |
2480 | return -EOPNOTSUPP; | |
2481 | } | |
2482 | } | |
2483 | ||
41c445ff JB |
2484 | /** |
2485 | * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI | |
2486 | * @vsi: the vsi being adjusted | |
2487 | **/ | |
2488 | void i40e_vlan_stripping_enable(struct i40e_vsi *vsi) | |
2489 | { | |
2490 | struct i40e_vsi_context ctxt; | |
2491 | i40e_status ret; | |
2492 | ||
2493 | if ((vsi->info.valid_sections & | |
2494 | cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && | |
2495 | ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0)) | |
2496 | return; /* already enabled */ | |
2497 | ||
2498 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2499 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | | |
2500 | I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH; | |
2501 | ||
2502 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2503 | ctxt.info = vsi->info; |
41c445ff JB |
2504 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2505 | if (ret) { | |
2506 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
2507 | "update vlan stripping failed, err %s aq_err %s\n", |
2508 | i40e_stat_str(&vsi->back->hw, ret), | |
2509 | i40e_aq_str(&vsi->back->hw, | |
2510 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
2511 | } |
2512 | } | |
2513 | ||
2514 | /** | |
2515 | * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI | |
2516 | * @vsi: the vsi being adjusted | |
2517 | **/ | |
2518 | void i40e_vlan_stripping_disable(struct i40e_vsi *vsi) | |
2519 | { | |
2520 | struct i40e_vsi_context ctxt; | |
2521 | i40e_status ret; | |
2522 | ||
2523 | if ((vsi->info.valid_sections & | |
2524 | cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) && | |
2525 | ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) == | |
2526 | I40E_AQ_VSI_PVLAN_EMOD_MASK)) | |
2527 | return; /* already disabled */ | |
2528 | ||
2529 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2530 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL | | |
2531 | I40E_AQ_VSI_PVLAN_EMOD_NOTHING; | |
2532 | ||
2533 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2534 | ctxt.info = vsi->info; |
41c445ff JB |
2535 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2536 | if (ret) { | |
2537 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
2538 | "update vlan stripping failed, err %s aq_err %s\n", |
2539 | i40e_stat_str(&vsi->back->hw, ret), | |
2540 | i40e_aq_str(&vsi->back->hw, | |
2541 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
2542 | } |
2543 | } | |
2544 | ||
2545 | /** | |
2546 | * i40e_vlan_rx_register - Setup or shutdown vlan offload | |
2547 | * @netdev: network interface to be adjusted | |
2548 | * @features: netdev features to test if VLAN offload is enabled or not | |
2549 | **/ | |
2550 | static void i40e_vlan_rx_register(struct net_device *netdev, u32 features) | |
2551 | { | |
2552 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2553 | struct i40e_vsi *vsi = np->vsi; | |
2554 | ||
2555 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2556 | i40e_vlan_stripping_enable(vsi); | |
2557 | else | |
2558 | i40e_vlan_stripping_disable(vsi); | |
2559 | } | |
2560 | ||
2561 | /** | |
490a4ad3 | 2562 | * i40e_add_vlan_all_mac - Add a MAC/VLAN filter for each existing MAC address |
41c445ff JB |
2563 | * @vsi: the vsi being configured |
2564 | * @vid: vlan id to be added (0 = untagged only , -1 = any) | |
490a4ad3 JK |
2565 | * |
2566 | * This is a helper function for adding a new MAC/VLAN filter with the | |
2567 | * specified VLAN for each existing MAC address already in the hash table. | |
2568 | * This function does *not* perform any accounting to update filters based on | |
2569 | * VLAN mode. | |
2570 | * | |
2571 | * NOTE: this function expects to be called while under the | |
2572 | * mac_filter_hash_lock | |
41c445ff | 2573 | **/ |
9af52f60 | 2574 | int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid) |
41c445ff | 2575 | { |
490a4ad3 | 2576 | struct i40e_mac_filter *f, *add_f; |
278e7d0b JK |
2577 | struct hlist_node *h; |
2578 | int bkt; | |
41c445ff | 2579 | |
278e7d0b | 2580 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
57b341d6 JK |
2581 | if (f->state == I40E_FILTER_REMOVE) |
2582 | continue; | |
1bc87e80 | 2583 | add_f = i40e_add_filter(vsi, f->macaddr, vid); |
41c445ff JB |
2584 | if (!add_f) { |
2585 | dev_info(&vsi->back->pdev->dev, | |
2586 | "Could not add vlan filter %d for %pM\n", | |
2587 | vid, f->macaddr); | |
2588 | return -ENOMEM; | |
2589 | } | |
2590 | } | |
2591 | ||
490a4ad3 JK |
2592 | return 0; |
2593 | } | |
2594 | ||
2595 | /** | |
2596 | * i40e_vsi_add_vlan - Add VSI membership for given VLAN | |
2597 | * @vsi: the VSI being configured | |
f94484b7 | 2598 | * @vid: VLAN id to be added |
490a4ad3 | 2599 | **/ |
f94484b7 | 2600 | int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid) |
490a4ad3 | 2601 | { |
489a3265 | 2602 | int err; |
490a4ad3 | 2603 | |
fcf6cfc8 | 2604 | if (vsi->info.pvid) |
f94484b7 JK |
2605 | return -EINVAL; |
2606 | ||
fcf6cfc8 JK |
2607 | /* The network stack will attempt to add VID=0, with the intention to |
2608 | * receive priority tagged packets with a VLAN of 0. Our HW receives | |
2609 | * these packets by default when configured to receive untagged | |
2610 | * packets, so we don't need to add a filter for this case. | |
2611 | * Additionally, HW interprets adding a VID=0 filter as meaning to | |
2612 | * receive *only* tagged traffic and stops receiving untagged traffic. | |
2613 | * Thus, we do not want to actually add a filter for VID=0 | |
2614 | */ | |
2615 | if (!vid) | |
2616 | return 0; | |
2617 | ||
490a4ad3 JK |
2618 | /* Locked once because all functions invoked below iterates list*/ |
2619 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
490a4ad3 | 2620 | err = i40e_add_vlan_all_mac(vsi, vid); |
278e7d0b | 2621 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
489a3265 JK |
2622 | if (err) |
2623 | return err; | |
21659035 | 2624 | |
0e4425ed JB |
2625 | /* schedule our worker thread which will take care of |
2626 | * applying the new filter changes | |
2627 | */ | |
2628 | i40e_service_event_schedule(vsi->back); | |
2629 | return 0; | |
41c445ff JB |
2630 | } |
2631 | ||
2632 | /** | |
490a4ad3 | 2633 | * i40e_rm_vlan_all_mac - Remove MAC/VLAN pair for all MAC with the given VLAN |
41c445ff JB |
2634 | * @vsi: the vsi being configured |
2635 | * @vid: vlan id to be removed (0 = untagged only , -1 = any) | |
490a4ad3 JK |
2636 | * |
2637 | * This function should be used to remove all VLAN filters which match the | |
2638 | * given VID. It does not schedule the service event and does not take the | |
2639 | * mac_filter_hash_lock so it may be combined with other operations under | |
2640 | * a single invocation of the mac_filter_hash_lock. | |
2641 | * | |
2642 | * NOTE: this function expects to be called while under the | |
2643 | * mac_filter_hash_lock | |
2644 | */ | |
9af52f60 | 2645 | void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid) |
41c445ff | 2646 | { |
84f5ca6c | 2647 | struct i40e_mac_filter *f; |
278e7d0b | 2648 | struct hlist_node *h; |
278e7d0b | 2649 | int bkt; |
41c445ff | 2650 | |
278e7d0b | 2651 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
290d2557 JK |
2652 | if (f->vlan == vid) |
2653 | __i40e_del_filter(vsi, f); | |
2654 | } | |
490a4ad3 | 2655 | } |
41c445ff | 2656 | |
490a4ad3 JK |
2657 | /** |
2658 | * i40e_vsi_kill_vlan - Remove VSI membership for given VLAN | |
2659 | * @vsi: the VSI being configured | |
f94484b7 | 2660 | * @vid: VLAN id to be removed |
490a4ad3 | 2661 | **/ |
f94484b7 | 2662 | void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid) |
490a4ad3 | 2663 | { |
f94484b7 JK |
2664 | if (!vid || vsi->info.pvid) |
2665 | return; | |
2666 | ||
490a4ad3 JK |
2667 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
2668 | i40e_rm_vlan_all_mac(vsi, vid); | |
278e7d0b | 2669 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 2670 | |
0e4425ed JB |
2671 | /* schedule our worker thread which will take care of |
2672 | * applying the new filter changes | |
2673 | */ | |
2674 | i40e_service_event_schedule(vsi->back); | |
41c445ff JB |
2675 | } |
2676 | ||
2677 | /** | |
2678 | * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload | |
2679 | * @netdev: network interface to be adjusted | |
2680 | * @vid: vlan id to be added | |
078b5876 JB |
2681 | * |
2682 | * net_device_ops implementation for adding vlan ids | |
41c445ff JB |
2683 | **/ |
2684 | static int i40e_vlan_rx_add_vid(struct net_device *netdev, | |
2685 | __always_unused __be16 proto, u16 vid) | |
2686 | { | |
2687 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2688 | struct i40e_vsi *vsi = np->vsi; | |
078b5876 | 2689 | int ret = 0; |
41c445ff | 2690 | |
6a112785 | 2691 | if (vid >= VLAN_N_VID) |
078b5876 JB |
2692 | return -EINVAL; |
2693 | ||
fcf6cfc8 | 2694 | ret = i40e_vsi_add_vlan(vsi, vid); |
6a112785 | 2695 | if (!ret) |
078b5876 | 2696 | set_bit(vid, vsi->active_vlans); |
41c445ff | 2697 | |
078b5876 | 2698 | return ret; |
41c445ff JB |
2699 | } |
2700 | ||
2701 | /** | |
2702 | * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload | |
2703 | * @netdev: network interface to be adjusted | |
2704 | * @vid: vlan id to be removed | |
078b5876 | 2705 | * |
fdfd943e | 2706 | * net_device_ops implementation for removing vlan ids |
41c445ff JB |
2707 | **/ |
2708 | static int i40e_vlan_rx_kill_vid(struct net_device *netdev, | |
2709 | __always_unused __be16 proto, u16 vid) | |
2710 | { | |
2711 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
2712 | struct i40e_vsi *vsi = np->vsi; | |
2713 | ||
41c445ff JB |
2714 | /* return code is ignored as there is nothing a user |
2715 | * can do about failure to remove and a log message was | |
078b5876 | 2716 | * already printed from the other function |
41c445ff JB |
2717 | */ |
2718 | i40e_vsi_kill_vlan(vsi, vid); | |
2719 | ||
2720 | clear_bit(vid, vsi->active_vlans); | |
078b5876 | 2721 | |
41c445ff JB |
2722 | return 0; |
2723 | } | |
2724 | ||
2725 | /** | |
2726 | * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up | |
2727 | * @vsi: the vsi being brought back up | |
2728 | **/ | |
2729 | static void i40e_restore_vlan(struct i40e_vsi *vsi) | |
2730 | { | |
2731 | u16 vid; | |
2732 | ||
2733 | if (!vsi->netdev) | |
2734 | return; | |
2735 | ||
2736 | i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features); | |
2737 | ||
2738 | for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID) | |
2739 | i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q), | |
2740 | vid); | |
2741 | } | |
2742 | ||
2743 | /** | |
2744 | * i40e_vsi_add_pvid - Add pvid for the VSI | |
2745 | * @vsi: the vsi being adjusted | |
2746 | * @vid: the vlan id to set as a PVID | |
2747 | **/ | |
dcae29be | 2748 | int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid) |
41c445ff JB |
2749 | { |
2750 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 2751 | i40e_status ret; |
41c445ff JB |
2752 | |
2753 | vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); | |
2754 | vsi->info.pvid = cpu_to_le16(vid); | |
6c12fcbf GR |
2755 | vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED | |
2756 | I40E_AQ_VSI_PVLAN_INSERT_PVID | | |
b774c7dd | 2757 | I40E_AQ_VSI_PVLAN_EMOD_STR; |
41c445ff JB |
2758 | |
2759 | ctxt.seid = vsi->seid; | |
1a2f6248 | 2760 | ctxt.info = vsi->info; |
f1c7e72e SN |
2761 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
2762 | if (ret) { | |
41c445ff | 2763 | dev_info(&vsi->back->pdev->dev, |
f1c7e72e SN |
2764 | "add pvid failed, err %s aq_err %s\n", |
2765 | i40e_stat_str(&vsi->back->hw, ret), | |
2766 | i40e_aq_str(&vsi->back->hw, | |
2767 | vsi->back->hw.aq.asq_last_status)); | |
dcae29be | 2768 | return -ENOENT; |
41c445ff JB |
2769 | } |
2770 | ||
dcae29be | 2771 | return 0; |
41c445ff JB |
2772 | } |
2773 | ||
2774 | /** | |
2775 | * i40e_vsi_remove_pvid - Remove the pvid from the VSI | |
2776 | * @vsi: the vsi being adjusted | |
2777 | * | |
2778 | * Just use the vlan_rx_register() service to put it back to normal | |
2779 | **/ | |
2780 | void i40e_vsi_remove_pvid(struct i40e_vsi *vsi) | |
2781 | { | |
6c12fcbf GR |
2782 | i40e_vlan_stripping_disable(vsi); |
2783 | ||
41c445ff | 2784 | vsi->info.pvid = 0; |
41c445ff JB |
2785 | } |
2786 | ||
2787 | /** | |
2788 | * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources | |
2789 | * @vsi: ptr to the VSI | |
2790 | * | |
2791 | * If this function returns with an error, then it's possible one or | |
2792 | * more of the rings is populated (while the rest are not). It is the | |
2793 | * callers duty to clean those orphaned rings. | |
2794 | * | |
2795 | * Return 0 on success, negative on failure | |
2796 | **/ | |
2797 | static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi) | |
2798 | { | |
2799 | int i, err = 0; | |
2800 | ||
2801 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 2802 | err = i40e_setup_tx_descriptors(vsi->tx_rings[i]); |
41c445ff | 2803 | |
74608d17 BT |
2804 | if (!i40e_enabled_xdp_vsi(vsi)) |
2805 | return err; | |
2806 | ||
2807 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
2808 | err = i40e_setup_tx_descriptors(vsi->xdp_rings[i]); | |
2809 | ||
41c445ff JB |
2810 | return err; |
2811 | } | |
2812 | ||
2813 | /** | |
2814 | * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues | |
2815 | * @vsi: ptr to the VSI | |
2816 | * | |
2817 | * Free VSI's transmit software resources | |
2818 | **/ | |
2819 | static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi) | |
2820 | { | |
2821 | int i; | |
2822 | ||
74608d17 BT |
2823 | if (vsi->tx_rings) { |
2824 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
2825 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) | |
2826 | i40e_free_tx_resources(vsi->tx_rings[i]); | |
2827 | } | |
8e9dca53 | 2828 | |
74608d17 BT |
2829 | if (vsi->xdp_rings) { |
2830 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
2831 | if (vsi->xdp_rings[i] && vsi->xdp_rings[i]->desc) | |
2832 | i40e_free_tx_resources(vsi->xdp_rings[i]); | |
2833 | } | |
41c445ff JB |
2834 | } |
2835 | ||
2836 | /** | |
2837 | * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources | |
2838 | * @vsi: ptr to the VSI | |
2839 | * | |
2840 | * If this function returns with an error, then it's possible one or | |
2841 | * more of the rings is populated (while the rest are not). It is the | |
2842 | * callers duty to clean those orphaned rings. | |
2843 | * | |
2844 | * Return 0 on success, negative on failure | |
2845 | **/ | |
2846 | static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi) | |
2847 | { | |
2848 | int i, err = 0; | |
2849 | ||
2850 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 2851 | err = i40e_setup_rx_descriptors(vsi->rx_rings[i]); |
41c445ff JB |
2852 | return err; |
2853 | } | |
2854 | ||
2855 | /** | |
2856 | * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues | |
2857 | * @vsi: ptr to the VSI | |
2858 | * | |
2859 | * Free all receive software resources | |
2860 | **/ | |
2861 | static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi) | |
2862 | { | |
2863 | int i; | |
2864 | ||
8e9dca53 GR |
2865 | if (!vsi->rx_rings) |
2866 | return; | |
2867 | ||
41c445ff | 2868 | for (i = 0; i < vsi->num_queue_pairs; i++) |
8e9dca53 | 2869 | if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc) |
9f65e15b | 2870 | i40e_free_rx_resources(vsi->rx_rings[i]); |
41c445ff JB |
2871 | } |
2872 | ||
3ffa037d NP |
2873 | /** |
2874 | * i40e_config_xps_tx_ring - Configure XPS for a Tx ring | |
2875 | * @ring: The Tx ring to configure | |
2876 | * | |
2877 | * This enables/disables XPS for a given Tx descriptor ring | |
2878 | * based on the TCs enabled for the VSI that ring belongs to. | |
2879 | **/ | |
2880 | static void i40e_config_xps_tx_ring(struct i40e_ring *ring) | |
2881 | { | |
2882 | struct i40e_vsi *vsi = ring->vsi; | |
be664cbe | 2883 | int cpu; |
3ffa037d | 2884 | |
9a660eea JB |
2885 | if (!ring->q_vector || !ring->netdev) |
2886 | return; | |
2887 | ||
ba4460d4 | 2888 | if ((vsi->tc_config.numtc <= 1) && |
bd6cd4e6 | 2889 | !test_and_set_bit(__I40E_TX_XPS_INIT_DONE, ring->state)) { |
be664cbe JK |
2890 | cpu = cpumask_local_spread(ring->q_vector->v_idx, -1); |
2891 | netif_set_xps_queue(ring->netdev, get_cpu_mask(cpu), | |
ba4460d4 | 2892 | ring->queue_index); |
3ffa037d | 2893 | } |
0e4425ed JB |
2894 | |
2895 | /* schedule our worker thread which will take care of | |
2896 | * applying the new filter changes | |
2897 | */ | |
2898 | i40e_service_event_schedule(vsi->back); | |
3ffa037d NP |
2899 | } |
2900 | ||
41c445ff JB |
2901 | /** |
2902 | * i40e_configure_tx_ring - Configure a transmit ring context and rest | |
2903 | * @ring: The Tx ring to configure | |
2904 | * | |
2905 | * Configure the Tx descriptor ring in the HMC context. | |
2906 | **/ | |
2907 | static int i40e_configure_tx_ring(struct i40e_ring *ring) | |
2908 | { | |
2909 | struct i40e_vsi *vsi = ring->vsi; | |
2910 | u16 pf_q = vsi->base_queue + ring->queue_index; | |
2911 | struct i40e_hw *hw = &vsi->back->hw; | |
2912 | struct i40e_hmc_obj_txq tx_ctx; | |
2913 | i40e_status err = 0; | |
2914 | u32 qtx_ctl = 0; | |
2915 | ||
2916 | /* some ATR related tx ring init */ | |
60ea5f83 | 2917 | if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) { |
41c445ff JB |
2918 | ring->atr_sample_rate = vsi->back->atr_sample_rate; |
2919 | ring->atr_count = 0; | |
2920 | } else { | |
2921 | ring->atr_sample_rate = 0; | |
2922 | } | |
2923 | ||
3ffa037d NP |
2924 | /* configure XPS */ |
2925 | i40e_config_xps_tx_ring(ring); | |
41c445ff JB |
2926 | |
2927 | /* clear the context structure first */ | |
2928 | memset(&tx_ctx, 0, sizeof(tx_ctx)); | |
2929 | ||
2930 | tx_ctx.new_context = 1; | |
2931 | tx_ctx.base = (ring->dma / 128); | |
2932 | tx_ctx.qlen = ring->count; | |
60ea5f83 JB |
2933 | tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED | |
2934 | I40E_FLAG_FD_ATR_ENABLED)); | |
beb0dff1 | 2935 | tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP); |
1943d8ba JB |
2936 | /* FDIR VSI tx ring can still use RS bit and writebacks */ |
2937 | if (vsi->type != I40E_VSI_FDIR) | |
2938 | tx_ctx.head_wb_ena = 1; | |
2939 | tx_ctx.head_wb_addr = ring->dma + | |
2940 | (ring->count * sizeof(struct i40e_tx_desc)); | |
41c445ff JB |
2941 | |
2942 | /* As part of VSI creation/update, FW allocates certain | |
2943 | * Tx arbitration queue sets for each TC enabled for | |
2944 | * the VSI. The FW returns the handles to these queue | |
2945 | * sets as part of the response buffer to Add VSI, | |
2946 | * Update VSI, etc. AQ commands. It is expected that | |
2947 | * these queue set handles be associated with the Tx | |
2948 | * queues by the driver as part of the TX queue context | |
2949 | * initialization. This has to be done regardless of | |
2950 | * DCB as by default everything is mapped to TC0. | |
2951 | */ | |
2952 | tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]); | |
2953 | tx_ctx.rdylist_act = 0; | |
2954 | ||
2955 | /* clear the context in the HMC */ | |
2956 | err = i40e_clear_lan_tx_queue_context(hw, pf_q); | |
2957 | if (err) { | |
2958 | dev_info(&vsi->back->pdev->dev, | |
2959 | "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n", | |
2960 | ring->queue_index, pf_q, err); | |
2961 | return -ENOMEM; | |
2962 | } | |
2963 | ||
2964 | /* set the context in the HMC */ | |
2965 | err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx); | |
2966 | if (err) { | |
2967 | dev_info(&vsi->back->pdev->dev, | |
2968 | "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n", | |
2969 | ring->queue_index, pf_q, err); | |
2970 | return -ENOMEM; | |
2971 | } | |
2972 | ||
2973 | /* Now associate this queue with this PCI function */ | |
7a28d885 | 2974 | if (vsi->type == I40E_VSI_VMDQ2) { |
9d8bf547 | 2975 | qtx_ctl = I40E_QTX_CTL_VM_QUEUE; |
7a28d885 MW |
2976 | qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) & |
2977 | I40E_QTX_CTL_VFVM_INDX_MASK; | |
2978 | } else { | |
9d8bf547 | 2979 | qtx_ctl = I40E_QTX_CTL_PF_QUEUE; |
7a28d885 MW |
2980 | } |
2981 | ||
13fd9774 SN |
2982 | qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) & |
2983 | I40E_QTX_CTL_PF_INDX_MASK); | |
41c445ff JB |
2984 | wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl); |
2985 | i40e_flush(hw); | |
2986 | ||
41c445ff JB |
2987 | /* cache tail off for easier writes later */ |
2988 | ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q); | |
2989 | ||
2990 | return 0; | |
2991 | } | |
2992 | ||
2993 | /** | |
2994 | * i40e_configure_rx_ring - Configure a receive ring context | |
2995 | * @ring: The Rx ring to configure | |
2996 | * | |
2997 | * Configure the Rx descriptor ring in the HMC context. | |
2998 | **/ | |
2999 | static int i40e_configure_rx_ring(struct i40e_ring *ring) | |
3000 | { | |
3001 | struct i40e_vsi *vsi = ring->vsi; | |
3002 | u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len; | |
3003 | u16 pf_q = vsi->base_queue + ring->queue_index; | |
3004 | struct i40e_hw *hw = &vsi->back->hw; | |
3005 | struct i40e_hmc_obj_rxq rx_ctx; | |
3006 | i40e_status err = 0; | |
3007 | ||
bd6cd4e6 | 3008 | bitmap_zero(ring->state, __I40E_RING_STATE_NBITS); |
41c445ff JB |
3009 | |
3010 | /* clear the context structure first */ | |
3011 | memset(&rx_ctx, 0, sizeof(rx_ctx)); | |
3012 | ||
3013 | ring->rx_buf_len = vsi->rx_buf_len; | |
41c445ff | 3014 | |
dab86afd AD |
3015 | rx_ctx.dbuff = DIV_ROUND_UP(ring->rx_buf_len, |
3016 | BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT)); | |
41c445ff JB |
3017 | |
3018 | rx_ctx.base = (ring->dma / 128); | |
3019 | rx_ctx.qlen = ring->count; | |
3020 | ||
bec60fc4 JB |
3021 | /* use 32 byte descriptors */ |
3022 | rx_ctx.dsize = 1; | |
41c445ff | 3023 | |
bec60fc4 JB |
3024 | /* descriptor type is always zero |
3025 | * rx_ctx.dtype = 0; | |
3026 | */ | |
b32bfa17 | 3027 | rx_ctx.hsplit_0 = 0; |
41c445ff | 3028 | |
b32bfa17 | 3029 | rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len); |
7134f9ce JB |
3030 | if (hw->revision_id == 0) |
3031 | rx_ctx.lrxqthresh = 0; | |
3032 | else | |
3033 | rx_ctx.lrxqthresh = 2; | |
41c445ff JB |
3034 | rx_ctx.crcstrip = 1; |
3035 | rx_ctx.l2tsel = 1; | |
c4bbac39 JB |
3036 | /* this controls whether VLAN is stripped from inner headers */ |
3037 | rx_ctx.showiv = 0; | |
acb3676b CS |
3038 | /* set the prefena field to 1 because the manual says to */ |
3039 | rx_ctx.prefena = 1; | |
41c445ff JB |
3040 | |
3041 | /* clear the context in the HMC */ | |
3042 | err = i40e_clear_lan_rx_queue_context(hw, pf_q); | |
3043 | if (err) { | |
3044 | dev_info(&vsi->back->pdev->dev, | |
3045 | "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", | |
3046 | ring->queue_index, pf_q, err); | |
3047 | return -ENOMEM; | |
3048 | } | |
3049 | ||
3050 | /* set the context in the HMC */ | |
3051 | err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx); | |
3052 | if (err) { | |
3053 | dev_info(&vsi->back->pdev->dev, | |
3054 | "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n", | |
3055 | ring->queue_index, pf_q, err); | |
3056 | return -ENOMEM; | |
3057 | } | |
3058 | ||
ca9ec088 AD |
3059 | /* configure Rx buffer alignment */ |
3060 | if (!vsi->netdev || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) | |
3061 | clear_ring_build_skb_enabled(ring); | |
3062 | else | |
3063 | set_ring_build_skb_enabled(ring); | |
3064 | ||
41c445ff JB |
3065 | /* cache tail for quicker writes, and clear the reg before use */ |
3066 | ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q); | |
3067 | writel(0, ring->tail); | |
3068 | ||
1a557afc | 3069 | i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring)); |
41c445ff JB |
3070 | |
3071 | return 0; | |
3072 | } | |
3073 | ||
3074 | /** | |
3075 | * i40e_vsi_configure_tx - Configure the VSI for Tx | |
3076 | * @vsi: VSI structure describing this set of rings and resources | |
3077 | * | |
3078 | * Configure the Tx VSI for operation. | |
3079 | **/ | |
3080 | static int i40e_vsi_configure_tx(struct i40e_vsi *vsi) | |
3081 | { | |
3082 | int err = 0; | |
3083 | u16 i; | |
3084 | ||
9f65e15b AD |
3085 | for (i = 0; (i < vsi->num_queue_pairs) && !err; i++) |
3086 | err = i40e_configure_tx_ring(vsi->tx_rings[i]); | |
41c445ff | 3087 | |
74608d17 BT |
3088 | if (!i40e_enabled_xdp_vsi(vsi)) |
3089 | return err; | |
3090 | ||
3091 | for (i = 0; (i < vsi->num_queue_pairs) && !err; i++) | |
3092 | err = i40e_configure_tx_ring(vsi->xdp_rings[i]); | |
3093 | ||
41c445ff JB |
3094 | return err; |
3095 | } | |
3096 | ||
3097 | /** | |
3098 | * i40e_vsi_configure_rx - Configure the VSI for Rx | |
3099 | * @vsi: the VSI being configured | |
3100 | * | |
3101 | * Configure the Rx VSI for operation. | |
3102 | **/ | |
3103 | static int i40e_vsi_configure_rx(struct i40e_vsi *vsi) | |
3104 | { | |
3105 | int err = 0; | |
3106 | u16 i; | |
3107 | ||
dab86afd AD |
3108 | if (!vsi->netdev || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) { |
3109 | vsi->max_frame = I40E_MAX_RXBUFFER; | |
3110 | vsi->rx_buf_len = I40E_RXBUFFER_2048; | |
3111 | #if (PAGE_SIZE < 8192) | |
ca9ec088 AD |
3112 | } else if (!I40E_2K_TOO_SMALL_WITH_PADDING && |
3113 | (vsi->netdev->mtu <= ETH_DATA_LEN)) { | |
dab86afd AD |
3114 | vsi->max_frame = I40E_RXBUFFER_1536 - NET_IP_ALIGN; |
3115 | vsi->rx_buf_len = I40E_RXBUFFER_1536 - NET_IP_ALIGN; | |
3116 | #endif | |
3117 | } else { | |
3118 | vsi->max_frame = I40E_MAX_RXBUFFER; | |
98efd694 AD |
3119 | vsi->rx_buf_len = (PAGE_SIZE < 8192) ? I40E_RXBUFFER_3072 : |
3120 | I40E_RXBUFFER_2048; | |
dab86afd | 3121 | } |
41c445ff JB |
3122 | |
3123 | /* set up individual rings */ | |
3124 | for (i = 0; i < vsi->num_queue_pairs && !err; i++) | |
9f65e15b | 3125 | err = i40e_configure_rx_ring(vsi->rx_rings[i]); |
41c445ff JB |
3126 | |
3127 | return err; | |
3128 | } | |
3129 | ||
3130 | /** | |
3131 | * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC | |
3132 | * @vsi: ptr to the VSI | |
3133 | **/ | |
3134 | static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi) | |
3135 | { | |
e7046ee1 | 3136 | struct i40e_ring *tx_ring, *rx_ring; |
41c445ff JB |
3137 | u16 qoffset, qcount; |
3138 | int i, n; | |
3139 | ||
cd238a3e PN |
3140 | if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) { |
3141 | /* Reset the TC information */ | |
3142 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
3143 | rx_ring = vsi->rx_rings[i]; | |
3144 | tx_ring = vsi->tx_rings[i]; | |
3145 | rx_ring->dcb_tc = 0; | |
3146 | tx_ring->dcb_tc = 0; | |
3147 | } | |
3148 | } | |
41c445ff JB |
3149 | |
3150 | for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) { | |
41a1d04b | 3151 | if (!(vsi->tc_config.enabled_tc & BIT_ULL(n))) |
41c445ff JB |
3152 | continue; |
3153 | ||
3154 | qoffset = vsi->tc_config.tc_info[n].qoffset; | |
3155 | qcount = vsi->tc_config.tc_info[n].qcount; | |
3156 | for (i = qoffset; i < (qoffset + qcount); i++) { | |
e7046ee1 AA |
3157 | rx_ring = vsi->rx_rings[i]; |
3158 | tx_ring = vsi->tx_rings[i]; | |
41c445ff JB |
3159 | rx_ring->dcb_tc = n; |
3160 | tx_ring->dcb_tc = n; | |
3161 | } | |
3162 | } | |
3163 | } | |
3164 | ||
3165 | /** | |
3166 | * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI | |
3167 | * @vsi: ptr to the VSI | |
3168 | **/ | |
3169 | static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi) | |
3170 | { | |
3171 | if (vsi->netdev) | |
3172 | i40e_set_rx_mode(vsi->netdev); | |
3173 | } | |
3174 | ||
17a73f6b JG |
3175 | /** |
3176 | * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters | |
3177 | * @vsi: Pointer to the targeted VSI | |
3178 | * | |
3179 | * This function replays the hlist on the hw where all the SB Flow Director | |
3180 | * filters were saved. | |
3181 | **/ | |
3182 | static void i40e_fdir_filter_restore(struct i40e_vsi *vsi) | |
3183 | { | |
3184 | struct i40e_fdir_filter *filter; | |
3185 | struct i40e_pf *pf = vsi->back; | |
3186 | struct hlist_node *node; | |
3187 | ||
55a5e60b ASJ |
3188 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) |
3189 | return; | |
3190 | ||
6d069425 | 3191 | /* Reset FDir counters as we're replaying all existing filters */ |
097dbf52 JK |
3192 | pf->fd_tcp4_filter_cnt = 0; |
3193 | pf->fd_udp4_filter_cnt = 0; | |
f223c875 | 3194 | pf->fd_sctp4_filter_cnt = 0; |
097dbf52 | 3195 | pf->fd_ip4_filter_cnt = 0; |
6d069425 | 3196 | |
17a73f6b JG |
3197 | hlist_for_each_entry_safe(filter, node, |
3198 | &pf->fdir_filter_list, fdir_node) { | |
3199 | i40e_add_del_fdir(vsi, filter, true); | |
3200 | } | |
3201 | } | |
3202 | ||
41c445ff JB |
3203 | /** |
3204 | * i40e_vsi_configure - Set up the VSI for action | |
3205 | * @vsi: the VSI being configured | |
3206 | **/ | |
3207 | static int i40e_vsi_configure(struct i40e_vsi *vsi) | |
3208 | { | |
3209 | int err; | |
3210 | ||
3211 | i40e_set_vsi_rx_mode(vsi); | |
3212 | i40e_restore_vlan(vsi); | |
3213 | i40e_vsi_config_dcb_rings(vsi); | |
3214 | err = i40e_vsi_configure_tx(vsi); | |
3215 | if (!err) | |
3216 | err = i40e_vsi_configure_rx(vsi); | |
3217 | ||
3218 | return err; | |
3219 | } | |
3220 | ||
3221 | /** | |
3222 | * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW | |
3223 | * @vsi: the VSI being configured | |
3224 | **/ | |
3225 | static void i40e_vsi_configure_msix(struct i40e_vsi *vsi) | |
3226 | { | |
74608d17 | 3227 | bool has_xdp = i40e_enabled_xdp_vsi(vsi); |
41c445ff | 3228 | struct i40e_pf *pf = vsi->back; |
41c445ff JB |
3229 | struct i40e_hw *hw = &pf->hw; |
3230 | u16 vector; | |
3231 | int i, q; | |
41c445ff JB |
3232 | u32 qp; |
3233 | ||
3234 | /* The interrupt indexing is offset by 1 in the PFINT_ITRn | |
3235 | * and PFINT_LNKLSTn registers, e.g.: | |
3236 | * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts) | |
3237 | */ | |
3238 | qp = vsi->base_queue; | |
3239 | vector = vsi->base_vector; | |
493fb300 | 3240 | for (i = 0; i < vsi->num_q_vectors; i++, vector++) { |
ac26fc13 JB |
3241 | struct i40e_q_vector *q_vector = vsi->q_vectors[i]; |
3242 | ||
ee2319cf | 3243 | q_vector->itr_countdown = ITR_COUNTDOWN_START; |
a75e8005 | 3244 | q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting); |
41c445ff JB |
3245 | q_vector->rx.latency_range = I40E_LOW_LATENCY; |
3246 | wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1), | |
3247 | q_vector->rx.itr); | |
a75e8005 | 3248 | q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting); |
41c445ff JB |
3249 | q_vector->tx.latency_range = I40E_LOW_LATENCY; |
3250 | wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1), | |
3251 | q_vector->tx.itr); | |
ac26fc13 | 3252 | wr32(hw, I40E_PFINT_RATEN(vector - 1), |
1c0e6a36 | 3253 | i40e_intrl_usec_to_reg(vsi->int_rate_limit)); |
41c445ff JB |
3254 | |
3255 | /* Linked list for the queuepairs assigned to this vector */ | |
3256 | wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp); | |
3257 | for (q = 0; q < q_vector->num_ringpairs; q++) { | |
74608d17 | 3258 | u32 nextqp = has_xdp ? qp + vsi->alloc_queue_pairs : qp; |
ac26fc13 JB |
3259 | u32 val; |
3260 | ||
41c445ff | 3261 | val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | |
74608d17 BT |
3262 | (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | |
3263 | (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) | | |
3264 | (nextqp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) | | |
3265 | (I40E_QUEUE_TYPE_TX << | |
3266 | I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT); | |
41c445ff JB |
3267 | |
3268 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
3269 | ||
74608d17 BT |
3270 | if (has_xdp) { |
3271 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
3272 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | |
3273 | (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | | |
3274 | (qp << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | | |
3275 | (I40E_QUEUE_TYPE_TX << | |
3276 | I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
3277 | ||
3278 | wr32(hw, I40E_QINT_TQCTL(nextqp), val); | |
3279 | } | |
3280 | ||
41c445ff | 3281 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | |
74608d17 BT |
3282 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | |
3283 | (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) | | |
3284 | ((qp + 1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) | | |
3285 | (I40E_QUEUE_TYPE_RX << | |
3286 | I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
41c445ff JB |
3287 | |
3288 | /* Terminate the linked list */ | |
3289 | if (q == (q_vector->num_ringpairs - 1)) | |
74608d17 BT |
3290 | val |= (I40E_QUEUE_END_OF_LIST << |
3291 | I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |
41c445ff JB |
3292 | |
3293 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
3294 | qp++; | |
3295 | } | |
3296 | } | |
3297 | ||
3298 | i40e_flush(hw); | |
3299 | } | |
3300 | ||
3301 | /** | |
3302 | * i40e_enable_misc_int_causes - enable the non-queue interrupts | |
3303 | * @hw: ptr to the hardware info | |
3304 | **/ | |
ab437b5a | 3305 | static void i40e_enable_misc_int_causes(struct i40e_pf *pf) |
41c445ff | 3306 | { |
ab437b5a | 3307 | struct i40e_hw *hw = &pf->hw; |
41c445ff JB |
3308 | u32 val; |
3309 | ||
3310 | /* clear things first */ | |
3311 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */ | |
3312 | rd32(hw, I40E_PFINT_ICR0); /* read to clear */ | |
3313 | ||
3314 | val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | | |
3315 | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | | |
3316 | I40E_PFINT_ICR0_ENA_GRST_MASK | | |
3317 | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | | |
3318 | I40E_PFINT_ICR0_ENA_GPIO_MASK | | |
41c445ff JB |
3319 | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | |
3320 | I40E_PFINT_ICR0_ENA_VFLR_MASK | | |
3321 | I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
3322 | ||
0d8e1439 ASJ |
3323 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) |
3324 | val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; | |
3325 | ||
ab437b5a JK |
3326 | if (pf->flags & I40E_FLAG_PTP) |
3327 | val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; | |
3328 | ||
41c445ff JB |
3329 | wr32(hw, I40E_PFINT_ICR0_ENA, val); |
3330 | ||
3331 | /* SW_ITR_IDX = 0, but don't change INTENA */ | |
84ed40e7 ASJ |
3332 | wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK | |
3333 | I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK); | |
41c445ff JB |
3334 | |
3335 | /* OTHER_ITR_IDX = 0 */ | |
3336 | wr32(hw, I40E_PFINT_STAT_CTL0, 0); | |
3337 | } | |
3338 | ||
3339 | /** | |
3340 | * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW | |
3341 | * @vsi: the VSI being configured | |
3342 | **/ | |
3343 | static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi) | |
3344 | { | |
74608d17 | 3345 | u32 nextqp = i40e_enabled_xdp_vsi(vsi) ? vsi->alloc_queue_pairs : 0; |
493fb300 | 3346 | struct i40e_q_vector *q_vector = vsi->q_vectors[0]; |
41c445ff JB |
3347 | struct i40e_pf *pf = vsi->back; |
3348 | struct i40e_hw *hw = &pf->hw; | |
3349 | u32 val; | |
3350 | ||
3351 | /* set the ITR configuration */ | |
ee2319cf | 3352 | q_vector->itr_countdown = ITR_COUNTDOWN_START; |
a75e8005 | 3353 | q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting); |
41c445ff JB |
3354 | q_vector->rx.latency_range = I40E_LOW_LATENCY; |
3355 | wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr); | |
a75e8005 | 3356 | q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting); |
41c445ff JB |
3357 | q_vector->tx.latency_range = I40E_LOW_LATENCY; |
3358 | wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr); | |
3359 | ||
ab437b5a | 3360 | i40e_enable_misc_int_causes(pf); |
41c445ff JB |
3361 | |
3362 | /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ | |
3363 | wr32(hw, I40E_PFINT_LNKLST0, 0); | |
3364 | ||
f29eaa3d | 3365 | /* Associate the queue pair to the vector and enable the queue int */ |
74608d17 BT |
3366 | val = I40E_QINT_RQCTL_CAUSE_ENA_MASK | |
3367 | (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) | | |
3368 | (nextqp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)| | |
41c445ff JB |
3369 | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); |
3370 | ||
3371 | wr32(hw, I40E_QINT_RQCTL(0), val); | |
3372 | ||
74608d17 BT |
3373 | if (i40e_enabled_xdp_vsi(vsi)) { |
3374 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
3375 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT)| | |
3376 | (I40E_QUEUE_TYPE_TX | |
3377 | << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT); | |
3378 | ||
3379 | wr32(hw, I40E_QINT_TQCTL(nextqp), val); | |
3380 | } | |
3381 | ||
41c445ff JB |
3382 | val = I40E_QINT_TQCTL_CAUSE_ENA_MASK | |
3383 | (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) | | |
3384 | (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT); | |
3385 | ||
3386 | wr32(hw, I40E_QINT_TQCTL(0), val); | |
3387 | i40e_flush(hw); | |
3388 | } | |
3389 | ||
2ef28cfb MW |
3390 | /** |
3391 | * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0 | |
3392 | * @pf: board private structure | |
3393 | **/ | |
3394 | void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf) | |
3395 | { | |
3396 | struct i40e_hw *hw = &pf->hw; | |
3397 | ||
3398 | wr32(hw, I40E_PFINT_DYN_CTL0, | |
3399 | I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT); | |
3400 | i40e_flush(hw); | |
3401 | } | |
3402 | ||
41c445ff JB |
3403 | /** |
3404 | * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0 | |
3405 | * @pf: board private structure | |
40d72a50 | 3406 | * @clearpba: true when all pending interrupt events should be cleared |
41c445ff | 3407 | **/ |
40d72a50 | 3408 | void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba) |
41c445ff JB |
3409 | { |
3410 | struct i40e_hw *hw = &pf->hw; | |
3411 | u32 val; | |
3412 | ||
3413 | val = I40E_PFINT_DYN_CTL0_INTENA_MASK | | |
40d72a50 | 3414 | (clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) | |
41c445ff JB |
3415 | (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT); |
3416 | ||
3417 | wr32(hw, I40E_PFINT_DYN_CTL0, val); | |
3418 | i40e_flush(hw); | |
3419 | } | |
3420 | ||
41c445ff JB |
3421 | /** |
3422 | * i40e_msix_clean_rings - MSIX mode Interrupt Handler | |
3423 | * @irq: interrupt number | |
3424 | * @data: pointer to a q_vector | |
3425 | **/ | |
3426 | static irqreturn_t i40e_msix_clean_rings(int irq, void *data) | |
3427 | { | |
3428 | struct i40e_q_vector *q_vector = data; | |
3429 | ||
cd0b6fa6 | 3430 | if (!q_vector->tx.ring && !q_vector->rx.ring) |
41c445ff JB |
3431 | return IRQ_HANDLED; |
3432 | ||
5d3465a1 | 3433 | napi_schedule_irqoff(&q_vector->napi); |
41c445ff JB |
3434 | |
3435 | return IRQ_HANDLED; | |
3436 | } | |
3437 | ||
96db776a AB |
3438 | /** |
3439 | * i40e_irq_affinity_notify - Callback for affinity changes | |
3440 | * @notify: context as to what irq was changed | |
3441 | * @mask: the new affinity mask | |
3442 | * | |
3443 | * This is a callback function used by the irq_set_affinity_notifier function | |
3444 | * so that we may register to receive changes to the irq affinity masks. | |
3445 | **/ | |
3446 | static void i40e_irq_affinity_notify(struct irq_affinity_notify *notify, | |
3447 | const cpumask_t *mask) | |
3448 | { | |
3449 | struct i40e_q_vector *q_vector = | |
3450 | container_of(notify, struct i40e_q_vector, affinity_notify); | |
3451 | ||
7e4d01e7 | 3452 | cpumask_copy(&q_vector->affinity_mask, mask); |
96db776a AB |
3453 | } |
3454 | ||
3455 | /** | |
3456 | * i40e_irq_affinity_release - Callback for affinity notifier release | |
3457 | * @ref: internal core kernel usage | |
3458 | * | |
3459 | * This is a callback function used by the irq_set_affinity_notifier function | |
3460 | * to inform the current notification subscriber that they will no longer | |
3461 | * receive notifications. | |
3462 | **/ | |
3463 | static void i40e_irq_affinity_release(struct kref *ref) {} | |
3464 | ||
41c445ff JB |
3465 | /** |
3466 | * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts | |
3467 | * @vsi: the VSI being configured | |
3468 | * @basename: name for the vector | |
3469 | * | |
3470 | * Allocates MSI-X vectors and requests interrupts from the kernel. | |
3471 | **/ | |
3472 | static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename) | |
3473 | { | |
3474 | int q_vectors = vsi->num_q_vectors; | |
3475 | struct i40e_pf *pf = vsi->back; | |
3476 | int base = vsi->base_vector; | |
3477 | int rx_int_idx = 0; | |
3478 | int tx_int_idx = 0; | |
3479 | int vector, err; | |
96db776a | 3480 | int irq_num; |
be664cbe | 3481 | int cpu; |
41c445ff JB |
3482 | |
3483 | for (vector = 0; vector < q_vectors; vector++) { | |
493fb300 | 3484 | struct i40e_q_vector *q_vector = vsi->q_vectors[vector]; |
41c445ff | 3485 | |
96db776a AB |
3486 | irq_num = pf->msix_entries[base + vector].vector; |
3487 | ||
cd0b6fa6 | 3488 | if (q_vector->tx.ring && q_vector->rx.ring) { |
41c445ff JB |
3489 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3490 | "%s-%s-%d", basename, "TxRx", rx_int_idx++); | |
3491 | tx_int_idx++; | |
cd0b6fa6 | 3492 | } else if (q_vector->rx.ring) { |
41c445ff JB |
3493 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3494 | "%s-%s-%d", basename, "rx", rx_int_idx++); | |
cd0b6fa6 | 3495 | } else if (q_vector->tx.ring) { |
41c445ff JB |
3496 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
3497 | "%s-%s-%d", basename, "tx", tx_int_idx++); | |
3498 | } else { | |
3499 | /* skip this unused q_vector */ | |
3500 | continue; | |
3501 | } | |
96db776a | 3502 | err = request_irq(irq_num, |
41c445ff JB |
3503 | vsi->irq_handler, |
3504 | 0, | |
3505 | q_vector->name, | |
3506 | q_vector); | |
3507 | if (err) { | |
3508 | dev_info(&pf->pdev->dev, | |
fb43201f | 3509 | "MSIX request_irq failed, error: %d\n", err); |
41c445ff JB |
3510 | goto free_queue_irqs; |
3511 | } | |
96db776a AB |
3512 | |
3513 | /* register for affinity change notifications */ | |
3514 | q_vector->affinity_notify.notify = i40e_irq_affinity_notify; | |
3515 | q_vector->affinity_notify.release = i40e_irq_affinity_release; | |
3516 | irq_set_affinity_notifier(irq_num, &q_vector->affinity_notify); | |
be664cbe JK |
3517 | /* Spread affinity hints out across online CPUs. |
3518 | * | |
3519 | * get_cpu_mask returns a static constant mask with | |
3520 | * a permanent lifetime so it's ok to pass to | |
3521 | * irq_set_affinity_hint without making a copy. | |
759dc4a7 | 3522 | */ |
be664cbe JK |
3523 | cpu = cpumask_local_spread(q_vector->v_idx, -1); |
3524 | irq_set_affinity_hint(irq_num, get_cpu_mask(cpu)); | |
41c445ff JB |
3525 | } |
3526 | ||
63741846 | 3527 | vsi->irqs_ready = true; |
41c445ff JB |
3528 | return 0; |
3529 | ||
3530 | free_queue_irqs: | |
3531 | while (vector) { | |
3532 | vector--; | |
96db776a AB |
3533 | irq_num = pf->msix_entries[base + vector].vector; |
3534 | irq_set_affinity_notifier(irq_num, NULL); | |
3535 | irq_set_affinity_hint(irq_num, NULL); | |
3536 | free_irq(irq_num, &vsi->q_vectors[vector]); | |
41c445ff JB |
3537 | } |
3538 | return err; | |
3539 | } | |
3540 | ||
3541 | /** | |
3542 | * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI | |
3543 | * @vsi: the VSI being un-configured | |
3544 | **/ | |
3545 | static void i40e_vsi_disable_irq(struct i40e_vsi *vsi) | |
3546 | { | |
3547 | struct i40e_pf *pf = vsi->back; | |
3548 | struct i40e_hw *hw = &pf->hw; | |
3549 | int base = vsi->base_vector; | |
3550 | int i; | |
3551 | ||
2e5c26ea | 3552 | /* disable interrupt causation from each queue */ |
41c445ff | 3553 | for (i = 0; i < vsi->num_queue_pairs; i++) { |
2e5c26ea SN |
3554 | u32 val; |
3555 | ||
3556 | val = rd32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx)); | |
3557 | val &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK; | |
3558 | wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), val); | |
3559 | ||
3560 | val = rd32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx)); | |
3561 | val &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK; | |
3562 | wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), val); | |
3563 | ||
74608d17 BT |
3564 | if (!i40e_enabled_xdp_vsi(vsi)) |
3565 | continue; | |
3566 | wr32(hw, I40E_QINT_TQCTL(vsi->xdp_rings[i]->reg_idx), 0); | |
41c445ff JB |
3567 | } |
3568 | ||
2e5c26ea | 3569 | /* disable each interrupt */ |
41c445ff JB |
3570 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { |
3571 | for (i = vsi->base_vector; | |
3572 | i < (vsi->num_q_vectors + vsi->base_vector); i++) | |
3573 | wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0); | |
3574 | ||
3575 | i40e_flush(hw); | |
3576 | for (i = 0; i < vsi->num_q_vectors; i++) | |
3577 | synchronize_irq(pf->msix_entries[i + base].vector); | |
3578 | } else { | |
3579 | /* Legacy and MSI mode - this stops all interrupt handling */ | |
3580 | wr32(hw, I40E_PFINT_ICR0_ENA, 0); | |
3581 | wr32(hw, I40E_PFINT_DYN_CTL0, 0); | |
3582 | i40e_flush(hw); | |
3583 | synchronize_irq(pf->pdev->irq); | |
3584 | } | |
3585 | } | |
3586 | ||
3587 | /** | |
3588 | * i40e_vsi_enable_irq - Enable IRQ for the given VSI | |
3589 | * @vsi: the VSI being configured | |
3590 | **/ | |
3591 | static int i40e_vsi_enable_irq(struct i40e_vsi *vsi) | |
3592 | { | |
3593 | struct i40e_pf *pf = vsi->back; | |
3594 | int i; | |
3595 | ||
3596 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
7845548d | 3597 | for (i = 0; i < vsi->num_q_vectors; i++) |
41c445ff JB |
3598 | i40e_irq_dynamic_enable(vsi, i); |
3599 | } else { | |
40d72a50 | 3600 | i40e_irq_dynamic_enable_icr0(pf, true); |
41c445ff JB |
3601 | } |
3602 | ||
1022cb6c | 3603 | i40e_flush(&pf->hw); |
41c445ff JB |
3604 | return 0; |
3605 | } | |
3606 | ||
3607 | /** | |
c17401a1 | 3608 | * i40e_free_misc_vector - Free the vector that handles non-queue events |
41c445ff JB |
3609 | * @pf: board private structure |
3610 | **/ | |
c17401a1 | 3611 | static void i40e_free_misc_vector(struct i40e_pf *pf) |
41c445ff JB |
3612 | { |
3613 | /* Disable ICR 0 */ | |
3614 | wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0); | |
3615 | i40e_flush(&pf->hw); | |
c17401a1 JK |
3616 | |
3617 | if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) { | |
3618 | synchronize_irq(pf->msix_entries[0].vector); | |
3619 | free_irq(pf->msix_entries[0].vector, pf); | |
3620 | clear_bit(__I40E_MISC_IRQ_REQUESTED, pf->state); | |
3621 | } | |
41c445ff JB |
3622 | } |
3623 | ||
3624 | /** | |
3625 | * i40e_intr - MSI/Legacy and non-queue interrupt handler | |
3626 | * @irq: interrupt number | |
3627 | * @data: pointer to a q_vector | |
3628 | * | |
3629 | * This is the handler used for all MSI/Legacy interrupts, and deals | |
3630 | * with both queue and non-queue interrupts. This is also used in | |
3631 | * MSIX mode to handle the non-queue interrupts. | |
3632 | **/ | |
3633 | static irqreturn_t i40e_intr(int irq, void *data) | |
3634 | { | |
3635 | struct i40e_pf *pf = (struct i40e_pf *)data; | |
3636 | struct i40e_hw *hw = &pf->hw; | |
5e823066 | 3637 | irqreturn_t ret = IRQ_NONE; |
41c445ff JB |
3638 | u32 icr0, icr0_remaining; |
3639 | u32 val, ena_mask; | |
3640 | ||
3641 | icr0 = rd32(hw, I40E_PFINT_ICR0); | |
5e823066 | 3642 | ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA); |
41c445ff | 3643 | |
116a57d4 SN |
3644 | /* if sharing a legacy IRQ, we might get called w/o an intr pending */ |
3645 | if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0) | |
5e823066 | 3646 | goto enable_intr; |
41c445ff | 3647 | |
cd92e72f SN |
3648 | /* if interrupt but no bits showing, must be SWINT */ |
3649 | if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) || | |
3650 | (icr0 & I40E_PFINT_ICR0_SWINT_MASK)) | |
3651 | pf->sw_int_count++; | |
3652 | ||
0d8e1439 | 3653 | if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && |
7642984b | 3654 | (icr0 & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) { |
0d8e1439 | 3655 | ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK; |
23bb6dc3 | 3656 | dev_dbg(&pf->pdev->dev, "cleared PE_CRITERR\n"); |
7642984b | 3657 | set_bit(__I40E_CORE_RESET_REQUESTED, pf->state); |
0d8e1439 ASJ |
3658 | } |
3659 | ||
41c445ff JB |
3660 | /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */ |
3661 | if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) { | |
5d3465a1 AD |
3662 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
3663 | struct i40e_q_vector *q_vector = vsi->q_vectors[0]; | |
41c445ff | 3664 | |
a16ae2d5 ASJ |
3665 | /* We do not have a way to disarm Queue causes while leaving |
3666 | * interrupt enabled for all other causes, ideally | |
3667 | * interrupt should be disabled while we are in NAPI but | |
3668 | * this is not a performance path and napi_schedule() | |
3669 | * can deal with rescheduling. | |
3670 | */ | |
9e6c9c0f | 3671 | if (!test_bit(__I40E_DOWN, pf->state)) |
5d3465a1 | 3672 | napi_schedule_irqoff(&q_vector->napi); |
41c445ff JB |
3673 | } |
3674 | ||
3675 | if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) { | |
3676 | ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
0da36b97 | 3677 | set_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state); |
6e93d0c9 | 3678 | i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n"); |
41c445ff JB |
3679 | } |
3680 | ||
3681 | if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) { | |
3682 | ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; | |
0da36b97 | 3683 | set_bit(__I40E_MDD_EVENT_PENDING, pf->state); |
41c445ff JB |
3684 | } |
3685 | ||
3686 | if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) { | |
3687 | ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK; | |
0da36b97 | 3688 | set_bit(__I40E_VFLR_EVENT_PENDING, pf->state); |
41c445ff JB |
3689 | } |
3690 | ||
3691 | if (icr0 & I40E_PFINT_ICR0_GRST_MASK) { | |
0da36b97 JK |
3692 | if (!test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
3693 | set_bit(__I40E_RESET_INTR_RECEIVED, pf->state); | |
41c445ff JB |
3694 | ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK; |
3695 | val = rd32(hw, I40E_GLGEN_RSTAT); | |
3696 | val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK) | |
3697 | >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT; | |
4eb3f768 | 3698 | if (val == I40E_RESET_CORER) { |
41c445ff | 3699 | pf->corer_count++; |
4eb3f768 | 3700 | } else if (val == I40E_RESET_GLOBR) { |
41c445ff | 3701 | pf->globr_count++; |
4eb3f768 | 3702 | } else if (val == I40E_RESET_EMPR) { |
41c445ff | 3703 | pf->empr_count++; |
0da36b97 | 3704 | set_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state); |
4eb3f768 | 3705 | } |
41c445ff JB |
3706 | } |
3707 | ||
9c010ee0 ASJ |
3708 | if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) { |
3709 | icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK; | |
3710 | dev_info(&pf->pdev->dev, "HMC error interrupt\n"); | |
25fc0e65 ASJ |
3711 | dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n", |
3712 | rd32(hw, I40E_PFHMC_ERRORINFO), | |
3713 | rd32(hw, I40E_PFHMC_ERRORDATA)); | |
9c010ee0 ASJ |
3714 | } |
3715 | ||
beb0dff1 JK |
3716 | if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) { |
3717 | u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0); | |
3718 | ||
3719 | if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) { | |
cafa1fca | 3720 | icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK; |
beb0dff1 | 3721 | i40e_ptp_tx_hwtstamp(pf); |
beb0dff1 | 3722 | } |
beb0dff1 JK |
3723 | } |
3724 | ||
41c445ff JB |
3725 | /* If a critical error is pending we have no choice but to reset the |
3726 | * device. | |
3727 | * Report and mask out any remaining unexpected interrupts. | |
3728 | */ | |
3729 | icr0_remaining = icr0 & ena_mask; | |
3730 | if (icr0_remaining) { | |
3731 | dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n", | |
3732 | icr0_remaining); | |
9c010ee0 | 3733 | if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) || |
41c445ff | 3734 | (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) || |
c0c28975 | 3735 | (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) { |
9c010ee0 | 3736 | dev_info(&pf->pdev->dev, "device will be reset\n"); |
0da36b97 | 3737 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
9c010ee0 | 3738 | i40e_service_event_schedule(pf); |
41c445ff JB |
3739 | } |
3740 | ena_mask &= ~icr0_remaining; | |
3741 | } | |
5e823066 | 3742 | ret = IRQ_HANDLED; |
41c445ff | 3743 | |
5e823066 | 3744 | enable_intr: |
41c445ff JB |
3745 | /* re-enable interrupt causes */ |
3746 | wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask); | |
9e6c9c0f | 3747 | if (!test_bit(__I40E_DOWN, pf->state)) { |
41c445ff | 3748 | i40e_service_event_schedule(pf); |
40d72a50 | 3749 | i40e_irq_dynamic_enable_icr0(pf, false); |
41c445ff JB |
3750 | } |
3751 | ||
5e823066 | 3752 | return ret; |
41c445ff JB |
3753 | } |
3754 | ||
cbf61325 ASJ |
3755 | /** |
3756 | * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes | |
3757 | * @tx_ring: tx ring to clean | |
3758 | * @budget: how many cleans we're allowed | |
3759 | * | |
3760 | * Returns true if there's any budget left (e.g. the clean is finished) | |
3761 | **/ | |
3762 | static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget) | |
3763 | { | |
3764 | struct i40e_vsi *vsi = tx_ring->vsi; | |
3765 | u16 i = tx_ring->next_to_clean; | |
3766 | struct i40e_tx_buffer *tx_buf; | |
3767 | struct i40e_tx_desc *tx_desc; | |
3768 | ||
3769 | tx_buf = &tx_ring->tx_bi[i]; | |
3770 | tx_desc = I40E_TX_DESC(tx_ring, i); | |
3771 | i -= tx_ring->count; | |
3772 | ||
3773 | do { | |
3774 | struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch; | |
3775 | ||
3776 | /* if next_to_watch is not set then there is no work pending */ | |
3777 | if (!eop_desc) | |
3778 | break; | |
3779 | ||
3780 | /* prevent any other reads prior to eop_desc */ | |
3781 | read_barrier_depends(); | |
3782 | ||
3783 | /* if the descriptor isn't done, no work yet to do */ | |
3784 | if (!(eop_desc->cmd_type_offset_bsz & | |
3785 | cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE))) | |
3786 | break; | |
3787 | ||
3788 | /* clear next_to_watch to prevent false hangs */ | |
3789 | tx_buf->next_to_watch = NULL; | |
3790 | ||
49d7d933 ASJ |
3791 | tx_desc->buffer_addr = 0; |
3792 | tx_desc->cmd_type_offset_bsz = 0; | |
3793 | /* move past filter desc */ | |
3794 | tx_buf++; | |
3795 | tx_desc++; | |
3796 | i++; | |
3797 | if (unlikely(!i)) { | |
3798 | i -= tx_ring->count; | |
3799 | tx_buf = tx_ring->tx_bi; | |
3800 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
3801 | } | |
cbf61325 ASJ |
3802 | /* unmap skb header data */ |
3803 | dma_unmap_single(tx_ring->dev, | |
3804 | dma_unmap_addr(tx_buf, dma), | |
3805 | dma_unmap_len(tx_buf, len), | |
3806 | DMA_TO_DEVICE); | |
49d7d933 ASJ |
3807 | if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB) |
3808 | kfree(tx_buf->raw_buf); | |
cbf61325 | 3809 | |
49d7d933 ASJ |
3810 | tx_buf->raw_buf = NULL; |
3811 | tx_buf->tx_flags = 0; | |
3812 | tx_buf->next_to_watch = NULL; | |
cbf61325 | 3813 | dma_unmap_len_set(tx_buf, len, 0); |
49d7d933 ASJ |
3814 | tx_desc->buffer_addr = 0; |
3815 | tx_desc->cmd_type_offset_bsz = 0; | |
cbf61325 | 3816 | |
49d7d933 | 3817 | /* move us past the eop_desc for start of next FD desc */ |
cbf61325 ASJ |
3818 | tx_buf++; |
3819 | tx_desc++; | |
3820 | i++; | |
3821 | if (unlikely(!i)) { | |
3822 | i -= tx_ring->count; | |
3823 | tx_buf = tx_ring->tx_bi; | |
3824 | tx_desc = I40E_TX_DESC(tx_ring, 0); | |
3825 | } | |
3826 | ||
3827 | /* update budget accounting */ | |
3828 | budget--; | |
3829 | } while (likely(budget)); | |
3830 | ||
3831 | i += tx_ring->count; | |
3832 | tx_ring->next_to_clean = i; | |
3833 | ||
6995b36c | 3834 | if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) |
7845548d | 3835 | i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx); |
6995b36c | 3836 | |
cbf61325 ASJ |
3837 | return budget > 0; |
3838 | } | |
3839 | ||
3840 | /** | |
3841 | * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring | |
3842 | * @irq: interrupt number | |
3843 | * @data: pointer to a q_vector | |
3844 | **/ | |
3845 | static irqreturn_t i40e_fdir_clean_ring(int irq, void *data) | |
3846 | { | |
3847 | struct i40e_q_vector *q_vector = data; | |
3848 | struct i40e_vsi *vsi; | |
3849 | ||
3850 | if (!q_vector->tx.ring) | |
3851 | return IRQ_HANDLED; | |
3852 | ||
3853 | vsi = q_vector->tx.ring->vsi; | |
3854 | i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit); | |
3855 | ||
3856 | return IRQ_HANDLED; | |
3857 | } | |
3858 | ||
41c445ff | 3859 | /** |
cd0b6fa6 | 3860 | * i40e_map_vector_to_qp - Assigns the queue pair to the vector |
41c445ff JB |
3861 | * @vsi: the VSI being configured |
3862 | * @v_idx: vector index | |
cd0b6fa6 | 3863 | * @qp_idx: queue pair index |
41c445ff | 3864 | **/ |
26cdc443 | 3865 | static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx) |
41c445ff | 3866 | { |
493fb300 | 3867 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; |
9f65e15b AD |
3868 | struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx]; |
3869 | struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx]; | |
41c445ff JB |
3870 | |
3871 | tx_ring->q_vector = q_vector; | |
cd0b6fa6 AD |
3872 | tx_ring->next = q_vector->tx.ring; |
3873 | q_vector->tx.ring = tx_ring; | |
41c445ff | 3874 | q_vector->tx.count++; |
cd0b6fa6 | 3875 | |
74608d17 BT |
3876 | /* Place XDP Tx ring in the same q_vector ring list as regular Tx */ |
3877 | if (i40e_enabled_xdp_vsi(vsi)) { | |
3878 | struct i40e_ring *xdp_ring = vsi->xdp_rings[qp_idx]; | |
3879 | ||
3880 | xdp_ring->q_vector = q_vector; | |
3881 | xdp_ring->next = q_vector->tx.ring; | |
3882 | q_vector->tx.ring = xdp_ring; | |
3883 | q_vector->tx.count++; | |
3884 | } | |
3885 | ||
cd0b6fa6 AD |
3886 | rx_ring->q_vector = q_vector; |
3887 | rx_ring->next = q_vector->rx.ring; | |
3888 | q_vector->rx.ring = rx_ring; | |
3889 | q_vector->rx.count++; | |
41c445ff JB |
3890 | } |
3891 | ||
3892 | /** | |
3893 | * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors | |
3894 | * @vsi: the VSI being configured | |
3895 | * | |
3896 | * This function maps descriptor rings to the queue-specific vectors | |
3897 | * we were allotted through the MSI-X enabling code. Ideally, we'd have | |
3898 | * one vector per queue pair, but on a constrained vector budget, we | |
3899 | * group the queue pairs as "efficiently" as possible. | |
3900 | **/ | |
3901 | static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi) | |
3902 | { | |
3903 | int qp_remaining = vsi->num_queue_pairs; | |
3904 | int q_vectors = vsi->num_q_vectors; | |
cd0b6fa6 | 3905 | int num_ringpairs; |
41c445ff JB |
3906 | int v_start = 0; |
3907 | int qp_idx = 0; | |
3908 | ||
3909 | /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to | |
3910 | * group them so there are multiple queues per vector. | |
70114ec4 ASJ |
3911 | * It is also important to go through all the vectors available to be |
3912 | * sure that if we don't use all the vectors, that the remaining vectors | |
3913 | * are cleared. This is especially important when decreasing the | |
3914 | * number of queues in use. | |
41c445ff | 3915 | */ |
70114ec4 | 3916 | for (; v_start < q_vectors; v_start++) { |
cd0b6fa6 AD |
3917 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_start]; |
3918 | ||
3919 | num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start); | |
3920 | ||
3921 | q_vector->num_ringpairs = num_ringpairs; | |
3922 | ||
3923 | q_vector->rx.count = 0; | |
3924 | q_vector->tx.count = 0; | |
3925 | q_vector->rx.ring = NULL; | |
3926 | q_vector->tx.ring = NULL; | |
3927 | ||
3928 | while (num_ringpairs--) { | |
26cdc443 | 3929 | i40e_map_vector_to_qp(vsi, v_start, qp_idx); |
cd0b6fa6 AD |
3930 | qp_idx++; |
3931 | qp_remaining--; | |
41c445ff JB |
3932 | } |
3933 | } | |
3934 | } | |
3935 | ||
3936 | /** | |
3937 | * i40e_vsi_request_irq - Request IRQ from the OS | |
3938 | * @vsi: the VSI being configured | |
3939 | * @basename: name for the vector | |
3940 | **/ | |
3941 | static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename) | |
3942 | { | |
3943 | struct i40e_pf *pf = vsi->back; | |
3944 | int err; | |
3945 | ||
3946 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
3947 | err = i40e_vsi_request_irq_msix(vsi, basename); | |
3948 | else if (pf->flags & I40E_FLAG_MSI_ENABLED) | |
3949 | err = request_irq(pf->pdev->irq, i40e_intr, 0, | |
b294ac70 | 3950 | pf->int_name, pf); |
41c445ff JB |
3951 | else |
3952 | err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED, | |
b294ac70 | 3953 | pf->int_name, pf); |
41c445ff JB |
3954 | |
3955 | if (err) | |
3956 | dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err); | |
3957 | ||
3958 | return err; | |
3959 | } | |
3960 | ||
3961 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3962 | /** | |
d89d967f | 3963 | * i40e_netpoll - A Polling 'interrupt' handler |
41c445ff JB |
3964 | * @netdev: network interface device structure |
3965 | * | |
3966 | * This is used by netconsole to send skbs without having to re-enable | |
3967 | * interrupts. It's not called while the normal interrupt routine is executing. | |
3968 | **/ | |
3969 | static void i40e_netpoll(struct net_device *netdev) | |
3970 | { | |
3971 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
3972 | struct i40e_vsi *vsi = np->vsi; | |
3973 | struct i40e_pf *pf = vsi->back; | |
3974 | int i; | |
3975 | ||
3976 | /* if interface is down do nothing */ | |
0da36b97 | 3977 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) |
41c445ff JB |
3978 | return; |
3979 | ||
41c445ff JB |
3980 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { |
3981 | for (i = 0; i < vsi->num_q_vectors; i++) | |
493fb300 | 3982 | i40e_msix_clean_rings(0, vsi->q_vectors[i]); |
41c445ff JB |
3983 | } else { |
3984 | i40e_intr(pf->pdev->irq, netdev); | |
3985 | } | |
41c445ff JB |
3986 | } |
3987 | #endif | |
3988 | ||
c768e490 JK |
3989 | #define I40E_QTX_ENA_WAIT_COUNT 50 |
3990 | ||
23527308 NP |
3991 | /** |
3992 | * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled | |
3993 | * @pf: the PF being configured | |
3994 | * @pf_q: the PF queue | |
3995 | * @enable: enable or disable state of the queue | |
3996 | * | |
3997 | * This routine will wait for the given Tx queue of the PF to reach the | |
3998 | * enabled or disabled state. | |
3999 | * Returns -ETIMEDOUT in case of failing to reach the requested state after | |
4000 | * multiple retries; else will return 0 in case of success. | |
4001 | **/ | |
4002 | static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable) | |
4003 | { | |
4004 | int i; | |
4005 | u32 tx_reg; | |
4006 | ||
4007 | for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { | |
4008 | tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q)); | |
4009 | if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) | |
4010 | break; | |
4011 | ||
f98a2006 | 4012 | usleep_range(10, 20); |
23527308 NP |
4013 | } |
4014 | if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) | |
4015 | return -ETIMEDOUT; | |
4016 | ||
4017 | return 0; | |
4018 | } | |
4019 | ||
c768e490 JK |
4020 | /** |
4021 | * i40e_control_tx_q - Start or stop a particular Tx queue | |
4022 | * @pf: the PF structure | |
4023 | * @pf_q: the PF queue to configure | |
4024 | * @enable: start or stop the queue | |
4025 | * | |
4026 | * This function enables or disables a single queue. Note that any delay | |
4027 | * required after the operation is expected to be handled by the caller of | |
4028 | * this function. | |
4029 | **/ | |
4030 | static void i40e_control_tx_q(struct i40e_pf *pf, int pf_q, bool enable) | |
4031 | { | |
4032 | struct i40e_hw *hw = &pf->hw; | |
4033 | u32 tx_reg; | |
4034 | int i; | |
4035 | ||
4036 | /* warn the TX unit of coming changes */ | |
4037 | i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable); | |
4038 | if (!enable) | |
4039 | usleep_range(10, 20); | |
4040 | ||
4041 | for (i = 0; i < I40E_QTX_ENA_WAIT_COUNT; i++) { | |
4042 | tx_reg = rd32(hw, I40E_QTX_ENA(pf_q)); | |
4043 | if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) == | |
4044 | ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1)) | |
4045 | break; | |
4046 | usleep_range(1000, 2000); | |
4047 | } | |
4048 | ||
4049 | /* Skip if the queue is already in the requested state */ | |
4050 | if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK)) | |
4051 | return; | |
4052 | ||
4053 | /* turn on/off the queue */ | |
4054 | if (enable) { | |
4055 | wr32(hw, I40E_QTX_HEAD(pf_q), 0); | |
4056 | tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK; | |
4057 | } else { | |
4058 | tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK; | |
4059 | } | |
4060 | ||
4061 | wr32(hw, I40E_QTX_ENA(pf_q), tx_reg); | |
4062 | } | |
4063 | ||
74608d17 BT |
4064 | /** |
4065 | * i40e_control_wait_tx_q - Start/stop Tx queue and wait for completion | |
4066 | * @seid: VSI SEID | |
4067 | * @pf: the PF structure | |
4068 | * @pf_q: the PF queue to configure | |
4069 | * @is_xdp: true if the queue is used for XDP | |
4070 | * @enable: start or stop the queue | |
4071 | **/ | |
4072 | static int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, | |
4073 | bool is_xdp, bool enable) | |
4074 | { | |
4075 | int ret; | |
4076 | ||
4077 | i40e_control_tx_q(pf, pf_q, enable); | |
4078 | ||
4079 | /* wait for the change to finish */ | |
4080 | ret = i40e_pf_txq_wait(pf, pf_q, enable); | |
4081 | if (ret) { | |
4082 | dev_info(&pf->pdev->dev, | |
4083 | "VSI seid %d %sTx ring %d %sable timeout\n", | |
4084 | seid, (is_xdp ? "XDP " : ""), pf_q, | |
4085 | (enable ? "en" : "dis")); | |
4086 | } | |
4087 | ||
4088 | return ret; | |
4089 | } | |
4090 | ||
41c445ff JB |
4091 | /** |
4092 | * i40e_vsi_control_tx - Start or stop a VSI's rings | |
4093 | * @vsi: the VSI being configured | |
4094 | * @enable: start or stop the rings | |
4095 | **/ | |
4096 | static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable) | |
4097 | { | |
4098 | struct i40e_pf *pf = vsi->back; | |
c768e490 | 4099 | int i, pf_q, ret = 0; |
41c445ff JB |
4100 | |
4101 | pf_q = vsi->base_queue; | |
4102 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
74608d17 BT |
4103 | ret = i40e_control_wait_tx_q(vsi->seid, pf, |
4104 | pf_q, | |
4105 | false /*is xdp*/, enable); | |
4106 | if (ret) | |
4107 | break; | |
351499ab | 4108 | |
74608d17 BT |
4109 | if (!i40e_enabled_xdp_vsi(vsi)) |
4110 | continue; | |
4111 | ||
4112 | ret = i40e_control_wait_tx_q(vsi->seid, pf, | |
4113 | pf_q + vsi->alloc_queue_pairs, | |
4114 | true /*is xdp*/, enable); | |
4115 | if (ret) | |
23527308 | 4116 | break; |
41c445ff JB |
4117 | } |
4118 | ||
23527308 NP |
4119 | return ret; |
4120 | } | |
4121 | ||
4122 | /** | |
4123 | * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled | |
4124 | * @pf: the PF being configured | |
4125 | * @pf_q: the PF queue | |
4126 | * @enable: enable or disable state of the queue | |
4127 | * | |
4128 | * This routine will wait for the given Rx queue of the PF to reach the | |
4129 | * enabled or disabled state. | |
4130 | * Returns -ETIMEDOUT in case of failing to reach the requested state after | |
4131 | * multiple retries; else will return 0 in case of success. | |
4132 | **/ | |
4133 | static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable) | |
4134 | { | |
4135 | int i; | |
4136 | u32 rx_reg; | |
4137 | ||
4138 | for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) { | |
4139 | rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q)); | |
4140 | if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) | |
4141 | break; | |
4142 | ||
f98a2006 | 4143 | usleep_range(10, 20); |
23527308 NP |
4144 | } |
4145 | if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT) | |
4146 | return -ETIMEDOUT; | |
7134f9ce | 4147 | |
41c445ff JB |
4148 | return 0; |
4149 | } | |
4150 | ||
c768e490 JK |
4151 | /** |
4152 | * i40e_control_rx_q - Start or stop a particular Rx queue | |
4153 | * @pf: the PF structure | |
4154 | * @pf_q: the PF queue to configure | |
4155 | * @enable: start or stop the queue | |
4156 | * | |
4157 | * This function enables or disables a single queue. Note that any delay | |
4158 | * required after the operation is expected to be handled by the caller of | |
4159 | * this function. | |
4160 | **/ | |
4161 | static void i40e_control_rx_q(struct i40e_pf *pf, int pf_q, bool enable) | |
4162 | { | |
4163 | struct i40e_hw *hw = &pf->hw; | |
4164 | u32 rx_reg; | |
4165 | int i; | |
4166 | ||
4167 | for (i = 0; i < I40E_QTX_ENA_WAIT_COUNT; i++) { | |
4168 | rx_reg = rd32(hw, I40E_QRX_ENA(pf_q)); | |
4169 | if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) == | |
4170 | ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1)) | |
4171 | break; | |
4172 | usleep_range(1000, 2000); | |
4173 | } | |
4174 | ||
4175 | /* Skip if the queue is already in the requested state */ | |
4176 | if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK)) | |
4177 | return; | |
4178 | ||
4179 | /* turn on/off the queue */ | |
4180 | if (enable) | |
4181 | rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK; | |
4182 | else | |
4183 | rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK; | |
4184 | ||
4185 | wr32(hw, I40E_QRX_ENA(pf_q), rx_reg); | |
4186 | } | |
4187 | ||
41c445ff JB |
4188 | /** |
4189 | * i40e_vsi_control_rx - Start or stop a VSI's rings | |
4190 | * @vsi: the VSI being configured | |
4191 | * @enable: start or stop the rings | |
4192 | **/ | |
4193 | static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable) | |
4194 | { | |
4195 | struct i40e_pf *pf = vsi->back; | |
c768e490 | 4196 | int i, pf_q, ret = 0; |
41c445ff JB |
4197 | |
4198 | pf_q = vsi->base_queue; | |
4199 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
c768e490 | 4200 | i40e_control_rx_q(pf, pf_q, enable); |
41c445ff | 4201 | |
41c445ff | 4202 | /* wait for the change to finish */ |
23527308 NP |
4203 | ret = i40e_pf_rxq_wait(pf, pf_q, enable); |
4204 | if (ret) { | |
4205 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
4206 | "VSI seid %d Rx ring %d %sable timeout\n", |
4207 | vsi->seid, pf_q, (enable ? "en" : "dis")); | |
23527308 | 4208 | break; |
41c445ff JB |
4209 | } |
4210 | } | |
4211 | ||
d08a9f6c WC |
4212 | /* Due to HW errata, on Rx disable only, the register can indicate done |
4213 | * before it really is. Needs 50ms to be sure | |
4214 | */ | |
4215 | if (!enable) | |
4216 | mdelay(50); | |
4217 | ||
23527308 | 4218 | return ret; |
41c445ff JB |
4219 | } |
4220 | ||
4221 | /** | |
3aa7b74d | 4222 | * i40e_vsi_start_rings - Start a VSI's rings |
41c445ff | 4223 | * @vsi: the VSI being configured |
41c445ff | 4224 | **/ |
3aa7b74d | 4225 | int i40e_vsi_start_rings(struct i40e_vsi *vsi) |
41c445ff | 4226 | { |
3b867b28 | 4227 | int ret = 0; |
41c445ff JB |
4228 | |
4229 | /* do rx first for enable and last for disable */ | |
3aa7b74d FS |
4230 | ret = i40e_vsi_control_rx(vsi, true); |
4231 | if (ret) | |
4232 | return ret; | |
4233 | ret = i40e_vsi_control_tx(vsi, true); | |
41c445ff JB |
4234 | |
4235 | return ret; | |
4236 | } | |
4237 | ||
3aa7b74d FS |
4238 | /** |
4239 | * i40e_vsi_stop_rings - Stop a VSI's rings | |
4240 | * @vsi: the VSI being configured | |
4241 | **/ | |
4242 | void i40e_vsi_stop_rings(struct i40e_vsi *vsi) | |
4243 | { | |
3480756f | 4244 | /* When port TX is suspended, don't wait */ |
0da36b97 | 4245 | if (test_bit(__I40E_PORT_SUSPENDED, vsi->back->state)) |
3480756f JK |
4246 | return i40e_vsi_stop_rings_no_wait(vsi); |
4247 | ||
3aa7b74d FS |
4248 | /* do rx first for enable and last for disable |
4249 | * Ignore return value, we need to shutdown whatever we can | |
4250 | */ | |
4251 | i40e_vsi_control_tx(vsi, false); | |
4252 | i40e_vsi_control_rx(vsi, false); | |
4253 | } | |
4254 | ||
e4b433f4 JK |
4255 | /** |
4256 | * i40e_vsi_stop_rings_no_wait - Stop a VSI's rings and do not delay | |
4257 | * @vsi: the VSI being shutdown | |
4258 | * | |
4259 | * This function stops all the rings for a VSI but does not delay to verify | |
4260 | * that rings have been disabled. It is expected that the caller is shutting | |
4261 | * down multiple VSIs at once and will delay together for all the VSIs after | |
4262 | * initiating the shutdown. This is particularly useful for shutting down lots | |
4263 | * of VFs together. Otherwise, a large delay can be incurred while configuring | |
4264 | * each VSI in serial. | |
4265 | **/ | |
4266 | void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi) | |
4267 | { | |
4268 | struct i40e_pf *pf = vsi->back; | |
4269 | int i, pf_q; | |
4270 | ||
4271 | pf_q = vsi->base_queue; | |
4272 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
4273 | i40e_control_tx_q(pf, pf_q, false); | |
4274 | i40e_control_rx_q(pf, pf_q, false); | |
4275 | } | |
4276 | } | |
4277 | ||
41c445ff JB |
4278 | /** |
4279 | * i40e_vsi_free_irq - Free the irq association with the OS | |
4280 | * @vsi: the VSI being configured | |
4281 | **/ | |
4282 | static void i40e_vsi_free_irq(struct i40e_vsi *vsi) | |
4283 | { | |
4284 | struct i40e_pf *pf = vsi->back; | |
4285 | struct i40e_hw *hw = &pf->hw; | |
4286 | int base = vsi->base_vector; | |
4287 | u32 val, qp; | |
4288 | int i; | |
4289 | ||
4290 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
4291 | if (!vsi->q_vectors) | |
4292 | return; | |
4293 | ||
63741846 SN |
4294 | if (!vsi->irqs_ready) |
4295 | return; | |
4296 | ||
4297 | vsi->irqs_ready = false; | |
41c445ff | 4298 | for (i = 0; i < vsi->num_q_vectors; i++) { |
96db776a AB |
4299 | int irq_num; |
4300 | u16 vector; | |
4301 | ||
4302 | vector = i + base; | |
4303 | irq_num = pf->msix_entries[vector].vector; | |
41c445ff JB |
4304 | |
4305 | /* free only the irqs that were actually requested */ | |
78681b1f SN |
4306 | if (!vsi->q_vectors[i] || |
4307 | !vsi->q_vectors[i]->num_ringpairs) | |
41c445ff JB |
4308 | continue; |
4309 | ||
96db776a AB |
4310 | /* clear the affinity notifier in the IRQ descriptor */ |
4311 | irq_set_affinity_notifier(irq_num, NULL); | |
759dc4a7 | 4312 | /* remove our suggested affinity mask for this IRQ */ |
96db776a AB |
4313 | irq_set_affinity_hint(irq_num, NULL); |
4314 | synchronize_irq(irq_num); | |
4315 | free_irq(irq_num, vsi->q_vectors[i]); | |
41c445ff JB |
4316 | |
4317 | /* Tear down the interrupt queue link list | |
4318 | * | |
4319 | * We know that they come in pairs and always | |
4320 | * the Rx first, then the Tx. To clear the | |
4321 | * link list, stick the EOL value into the | |
4322 | * next_q field of the registers. | |
4323 | */ | |
4324 | val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1)); | |
4325 | qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) | |
4326 | >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4327 | val |= I40E_QUEUE_END_OF_LIST | |
4328 | << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4329 | wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val); | |
4330 | ||
4331 | while (qp != I40E_QUEUE_END_OF_LIST) { | |
4332 | u32 next; | |
4333 | ||
4334 | val = rd32(hw, I40E_QINT_RQCTL(qp)); | |
4335 | ||
4336 | val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | | |
4337 | I40E_QINT_RQCTL_MSIX0_INDX_MASK | | |
4338 | I40E_QINT_RQCTL_CAUSE_ENA_MASK | | |
4339 | I40E_QINT_RQCTL_INTEVENT_MASK); | |
4340 | ||
4341 | val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | | |
4342 | I40E_QINT_RQCTL_NEXTQ_INDX_MASK); | |
4343 | ||
4344 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
4345 | ||
4346 | val = rd32(hw, I40E_QINT_TQCTL(qp)); | |
4347 | ||
4348 | next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK) | |
4349 | >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT; | |
4350 | ||
4351 | val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | | |
4352 | I40E_QINT_TQCTL_MSIX0_INDX_MASK | | |
4353 | I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
4354 | I40E_QINT_TQCTL_INTEVENT_MASK); | |
4355 | ||
4356 | val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | | |
4357 | I40E_QINT_TQCTL_NEXTQ_INDX_MASK); | |
4358 | ||
4359 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
4360 | qp = next; | |
4361 | } | |
4362 | } | |
4363 | } else { | |
4364 | free_irq(pf->pdev->irq, pf); | |
4365 | ||
4366 | val = rd32(hw, I40E_PFINT_LNKLST0); | |
4367 | qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK) | |
4368 | >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT; | |
4369 | val |= I40E_QUEUE_END_OF_LIST | |
4370 | << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT; | |
4371 | wr32(hw, I40E_PFINT_LNKLST0, val); | |
4372 | ||
4373 | val = rd32(hw, I40E_QINT_RQCTL(qp)); | |
4374 | val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK | | |
4375 | I40E_QINT_RQCTL_MSIX0_INDX_MASK | | |
4376 | I40E_QINT_RQCTL_CAUSE_ENA_MASK | | |
4377 | I40E_QINT_RQCTL_INTEVENT_MASK); | |
4378 | ||
4379 | val |= (I40E_QINT_RQCTL_ITR_INDX_MASK | | |
4380 | I40E_QINT_RQCTL_NEXTQ_INDX_MASK); | |
4381 | ||
4382 | wr32(hw, I40E_QINT_RQCTL(qp), val); | |
4383 | ||
4384 | val = rd32(hw, I40E_QINT_TQCTL(qp)); | |
4385 | ||
4386 | val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK | | |
4387 | I40E_QINT_TQCTL_MSIX0_INDX_MASK | | |
4388 | I40E_QINT_TQCTL_CAUSE_ENA_MASK | | |
4389 | I40E_QINT_TQCTL_INTEVENT_MASK); | |
4390 | ||
4391 | val |= (I40E_QINT_TQCTL_ITR_INDX_MASK | | |
4392 | I40E_QINT_TQCTL_NEXTQ_INDX_MASK); | |
4393 | ||
4394 | wr32(hw, I40E_QINT_TQCTL(qp), val); | |
4395 | } | |
4396 | } | |
4397 | ||
493fb300 AD |
4398 | /** |
4399 | * i40e_free_q_vector - Free memory allocated for specific interrupt vector | |
4400 | * @vsi: the VSI being configured | |
4401 | * @v_idx: Index of vector to be freed | |
4402 | * | |
4403 | * This function frees the memory allocated to the q_vector. In addition if | |
4404 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4405 | * to freeing the q_vector. | |
4406 | **/ | |
4407 | static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx) | |
4408 | { | |
4409 | struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx]; | |
cd0b6fa6 | 4410 | struct i40e_ring *ring; |
493fb300 AD |
4411 | |
4412 | if (!q_vector) | |
4413 | return; | |
4414 | ||
4415 | /* disassociate q_vector from rings */ | |
cd0b6fa6 AD |
4416 | i40e_for_each_ring(ring, q_vector->tx) |
4417 | ring->q_vector = NULL; | |
4418 | ||
4419 | i40e_for_each_ring(ring, q_vector->rx) | |
4420 | ring->q_vector = NULL; | |
493fb300 AD |
4421 | |
4422 | /* only VSI w/ an associated netdev is set up w/ NAPI */ | |
4423 | if (vsi->netdev) | |
4424 | netif_napi_del(&q_vector->napi); | |
4425 | ||
4426 | vsi->q_vectors[v_idx] = NULL; | |
4427 | ||
4428 | kfree_rcu(q_vector, rcu); | |
4429 | } | |
4430 | ||
41c445ff JB |
4431 | /** |
4432 | * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors | |
4433 | * @vsi: the VSI being un-configured | |
4434 | * | |
4435 | * This frees the memory allocated to the q_vectors and | |
4436 | * deletes references to the NAPI struct. | |
4437 | **/ | |
4438 | static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi) | |
4439 | { | |
4440 | int v_idx; | |
4441 | ||
493fb300 AD |
4442 | for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++) |
4443 | i40e_free_q_vector(vsi, v_idx); | |
41c445ff JB |
4444 | } |
4445 | ||
4446 | /** | |
4447 | * i40e_reset_interrupt_capability - Disable interrupt setup in OS | |
4448 | * @pf: board private structure | |
4449 | **/ | |
4450 | static void i40e_reset_interrupt_capability(struct i40e_pf *pf) | |
4451 | { | |
4452 | /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */ | |
4453 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
4454 | pci_disable_msix(pf->pdev); | |
4455 | kfree(pf->msix_entries); | |
4456 | pf->msix_entries = NULL; | |
3b444399 SN |
4457 | kfree(pf->irq_pile); |
4458 | pf->irq_pile = NULL; | |
41c445ff JB |
4459 | } else if (pf->flags & I40E_FLAG_MSI_ENABLED) { |
4460 | pci_disable_msi(pf->pdev); | |
4461 | } | |
4462 | pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED); | |
4463 | } | |
4464 | ||
4465 | /** | |
4466 | * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
4467 | * @pf: board private structure | |
4468 | * | |
4469 | * We go through and clear interrupt specific resources and reset the structure | |
4470 | * to pre-load conditions | |
4471 | **/ | |
4472 | static void i40e_clear_interrupt_scheme(struct i40e_pf *pf) | |
4473 | { | |
4474 | int i; | |
4475 | ||
c17401a1 | 4476 | i40e_free_misc_vector(pf); |
e147758d | 4477 | |
e3219ce6 ASJ |
4478 | i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector, |
4479 | I40E_IWARP_IRQ_PILE_ID); | |
4480 | ||
41c445ff | 4481 | i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1); |
505682cd | 4482 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
4483 | if (pf->vsi[i]) |
4484 | i40e_vsi_free_q_vectors(pf->vsi[i]); | |
4485 | i40e_reset_interrupt_capability(pf); | |
4486 | } | |
4487 | ||
4488 | /** | |
4489 | * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI | |
4490 | * @vsi: the VSI being configured | |
4491 | **/ | |
4492 | static void i40e_napi_enable_all(struct i40e_vsi *vsi) | |
4493 | { | |
4494 | int q_idx; | |
4495 | ||
4496 | if (!vsi->netdev) | |
4497 | return; | |
4498 | ||
13a8cd19 AD |
4499 | for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) { |
4500 | struct i40e_q_vector *q_vector = vsi->q_vectors[q_idx]; | |
4501 | ||
4502 | if (q_vector->rx.ring || q_vector->tx.ring) | |
4503 | napi_enable(&q_vector->napi); | |
4504 | } | |
41c445ff JB |
4505 | } |
4506 | ||
4507 | /** | |
4508 | * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI | |
4509 | * @vsi: the VSI being configured | |
4510 | **/ | |
4511 | static void i40e_napi_disable_all(struct i40e_vsi *vsi) | |
4512 | { | |
4513 | int q_idx; | |
4514 | ||
4515 | if (!vsi->netdev) | |
4516 | return; | |
4517 | ||
13a8cd19 AD |
4518 | for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) { |
4519 | struct i40e_q_vector *q_vector = vsi->q_vectors[q_idx]; | |
4520 | ||
4521 | if (q_vector->rx.ring || q_vector->tx.ring) | |
4522 | napi_disable(&q_vector->napi); | |
4523 | } | |
41c445ff JB |
4524 | } |
4525 | ||
90ef8d47 SN |
4526 | /** |
4527 | * i40e_vsi_close - Shut down a VSI | |
4528 | * @vsi: the vsi to be quelled | |
4529 | **/ | |
4530 | static void i40e_vsi_close(struct i40e_vsi *vsi) | |
4531 | { | |
0ef2d5af | 4532 | struct i40e_pf *pf = vsi->back; |
0da36b97 | 4533 | if (!test_and_set_bit(__I40E_VSI_DOWN, vsi->state)) |
90ef8d47 SN |
4534 | i40e_down(vsi); |
4535 | i40e_vsi_free_irq(vsi); | |
4536 | i40e_vsi_free_tx_resources(vsi); | |
4537 | i40e_vsi_free_rx_resources(vsi); | |
92faef85 | 4538 | vsi->current_netdev_flags = 0; |
0ef2d5af | 4539 | pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED; |
0da36b97 | 4540 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
0ef2d5af | 4541 | pf->flags |= I40E_FLAG_CLIENT_RESET; |
90ef8d47 SN |
4542 | } |
4543 | ||
41c445ff JB |
4544 | /** |
4545 | * i40e_quiesce_vsi - Pause a given VSI | |
4546 | * @vsi: the VSI being paused | |
4547 | **/ | |
4548 | static void i40e_quiesce_vsi(struct i40e_vsi *vsi) | |
4549 | { | |
0da36b97 | 4550 | if (test_bit(__I40E_VSI_DOWN, vsi->state)) |
41c445ff JB |
4551 | return; |
4552 | ||
0da36b97 | 4553 | set_bit(__I40E_VSI_NEEDS_RESTART, vsi->state); |
6995b36c | 4554 | if (vsi->netdev && netif_running(vsi->netdev)) |
41c445ff | 4555 | vsi->netdev->netdev_ops->ndo_stop(vsi->netdev); |
6995b36c | 4556 | else |
90ef8d47 | 4557 | i40e_vsi_close(vsi); |
41c445ff JB |
4558 | } |
4559 | ||
4560 | /** | |
4561 | * i40e_unquiesce_vsi - Resume a given VSI | |
4562 | * @vsi: the VSI being resumed | |
4563 | **/ | |
4564 | static void i40e_unquiesce_vsi(struct i40e_vsi *vsi) | |
4565 | { | |
0da36b97 | 4566 | if (!test_and_clear_bit(__I40E_VSI_NEEDS_RESTART, vsi->state)) |
41c445ff JB |
4567 | return; |
4568 | ||
41c445ff JB |
4569 | if (vsi->netdev && netif_running(vsi->netdev)) |
4570 | vsi->netdev->netdev_ops->ndo_open(vsi->netdev); | |
4571 | else | |
8276f757 | 4572 | i40e_vsi_open(vsi); /* this clears the DOWN bit */ |
41c445ff JB |
4573 | } |
4574 | ||
4575 | /** | |
4576 | * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF | |
4577 | * @pf: the PF | |
4578 | **/ | |
4579 | static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf) | |
4580 | { | |
4581 | int v; | |
4582 | ||
505682cd | 4583 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
4584 | if (pf->vsi[v]) |
4585 | i40e_quiesce_vsi(pf->vsi[v]); | |
4586 | } | |
4587 | } | |
4588 | ||
4589 | /** | |
4590 | * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF | |
4591 | * @pf: the PF | |
4592 | **/ | |
4593 | static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf) | |
4594 | { | |
4595 | int v; | |
4596 | ||
505682cd | 4597 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
4598 | if (pf->vsi[v]) |
4599 | i40e_unquiesce_vsi(pf->vsi[v]); | |
4600 | } | |
4601 | } | |
4602 | ||
69129dc3 | 4603 | /** |
3fe06f41 | 4604 | * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled |
69129dc3 NP |
4605 | * @vsi: the VSI being configured |
4606 | * | |
af26ce2d | 4607 | * Wait until all queues on a given VSI have been disabled. |
69129dc3 | 4608 | **/ |
e4b433f4 | 4609 | int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi) |
69129dc3 NP |
4610 | { |
4611 | struct i40e_pf *pf = vsi->back; | |
4612 | int i, pf_q, ret; | |
4613 | ||
4614 | pf_q = vsi->base_queue; | |
4615 | for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) { | |
af26ce2d | 4616 | /* Check and wait for the Tx queue */ |
69129dc3 NP |
4617 | ret = i40e_pf_txq_wait(pf, pf_q, false); |
4618 | if (ret) { | |
4619 | dev_info(&pf->pdev->dev, | |
fb43201f SN |
4620 | "VSI seid %d Tx ring %d disable timeout\n", |
4621 | vsi->seid, pf_q); | |
69129dc3 NP |
4622 | return ret; |
4623 | } | |
74608d17 BT |
4624 | |
4625 | if (!i40e_enabled_xdp_vsi(vsi)) | |
4626 | goto wait_rx; | |
4627 | ||
4628 | /* Check and wait for the XDP Tx queue */ | |
4629 | ret = i40e_pf_txq_wait(pf, pf_q + vsi->alloc_queue_pairs, | |
4630 | false); | |
4631 | if (ret) { | |
4632 | dev_info(&pf->pdev->dev, | |
4633 | "VSI seid %d XDP Tx ring %d disable timeout\n", | |
4634 | vsi->seid, pf_q); | |
4635 | return ret; | |
4636 | } | |
4637 | wait_rx: | |
4638 | /* Check and wait for the Rx queue */ | |
3fe06f41 NP |
4639 | ret = i40e_pf_rxq_wait(pf, pf_q, false); |
4640 | if (ret) { | |
4641 | dev_info(&pf->pdev->dev, | |
4642 | "VSI seid %d Rx ring %d disable timeout\n", | |
4643 | vsi->seid, pf_q); | |
4644 | return ret; | |
4645 | } | |
4646 | } | |
4647 | ||
69129dc3 NP |
4648 | return 0; |
4649 | } | |
4650 | ||
e4b433f4 | 4651 | #ifdef CONFIG_I40E_DCB |
69129dc3 | 4652 | /** |
3fe06f41 | 4653 | * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled |
69129dc3 NP |
4654 | * @pf: the PF |
4655 | * | |
3fe06f41 | 4656 | * This function waits for the queues to be in disabled state for all the |
69129dc3 NP |
4657 | * VSIs that are managed by this PF. |
4658 | **/ | |
3fe06f41 | 4659 | static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf) |
69129dc3 NP |
4660 | { |
4661 | int v, ret = 0; | |
4662 | ||
4663 | for (v = 0; v < pf->hw.func_caps.num_vsis; v++) { | |
c76cb6ed | 4664 | if (pf->vsi[v]) { |
3fe06f41 | 4665 | ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]); |
69129dc3 NP |
4666 | if (ret) |
4667 | break; | |
4668 | } | |
4669 | } | |
4670 | ||
4671 | return ret; | |
4672 | } | |
4673 | ||
4674 | #endif | |
b03a8c1f KP |
4675 | |
4676 | /** | |
4677 | * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue | |
4678 | * @q_idx: TX queue number | |
4679 | * @vsi: Pointer to VSI struct | |
4680 | * | |
4681 | * This function checks specified queue for given VSI. Detects hung condition. | |
17daabb5 AB |
4682 | * We proactively detect hung TX queues by checking if interrupts are disabled |
4683 | * but there are pending descriptors. If it appears hung, attempt to recover | |
4684 | * by triggering a SW interrupt. | |
b03a8c1f KP |
4685 | **/ |
4686 | static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi) | |
4687 | { | |
4688 | struct i40e_ring *tx_ring = NULL; | |
4689 | struct i40e_pf *pf; | |
17daabb5 | 4690 | u32 val, tx_pending; |
b03a8c1f KP |
4691 | int i; |
4692 | ||
4693 | pf = vsi->back; | |
4694 | ||
4695 | /* now that we have an index, find the tx_ring struct */ | |
4696 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
4697 | if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) { | |
4698 | if (q_idx == vsi->tx_rings[i]->queue_index) { | |
4699 | tx_ring = vsi->tx_rings[i]; | |
4700 | break; | |
4701 | } | |
4702 | } | |
4703 | } | |
4704 | ||
4705 | if (!tx_ring) | |
4706 | return; | |
4707 | ||
4708 | /* Read interrupt register */ | |
4709 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
4710 | val = rd32(&pf->hw, | |
4711 | I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx + | |
4712 | tx_ring->vsi->base_vector - 1)); | |
4713 | else | |
4714 | val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0); | |
4715 | ||
17daabb5 | 4716 | tx_pending = i40e_get_tx_pending(tx_ring); |
b03a8c1f | 4717 | |
17daabb5 AB |
4718 | /* Interrupts are disabled and TX pending is non-zero, |
4719 | * trigger the SW interrupt (don't wait). Worst case | |
4720 | * there will be one extra interrupt which may result | |
4721 | * into not cleaning any queues because queues are cleaned. | |
b03a8c1f | 4722 | */ |
17daabb5 AB |
4723 | if (tx_pending && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) |
4724 | i40e_force_wb(vsi, tx_ring->q_vector); | |
b03a8c1f KP |
4725 | } |
4726 | ||
4727 | /** | |
4728 | * i40e_detect_recover_hung - Function to detect and recover hung_queues | |
4729 | * @pf: pointer to PF struct | |
4730 | * | |
4731 | * LAN VSI has netdev and netdev has TX queues. This function is to check | |
4732 | * each of those TX queues if they are hung, trigger recovery by issuing | |
4733 | * SW interrupt. | |
4734 | **/ | |
4735 | static void i40e_detect_recover_hung(struct i40e_pf *pf) | |
4736 | { | |
4737 | struct net_device *netdev; | |
4738 | struct i40e_vsi *vsi; | |
b85c94b6 | 4739 | unsigned int i; |
b03a8c1f KP |
4740 | |
4741 | /* Only for LAN VSI */ | |
4742 | vsi = pf->vsi[pf->lan_vsi]; | |
4743 | ||
4744 | if (!vsi) | |
4745 | return; | |
4746 | ||
4747 | /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */ | |
0da36b97 JK |
4748 | if (test_bit(__I40E_VSI_DOWN, vsi->back->state) || |
4749 | test_bit(__I40E_RESET_RECOVERY_PENDING, vsi->back->state)) | |
b03a8c1f KP |
4750 | return; |
4751 | ||
4752 | /* Make sure type is MAIN VSI */ | |
4753 | if (vsi->type != I40E_VSI_MAIN) | |
4754 | return; | |
4755 | ||
4756 | netdev = vsi->netdev; | |
4757 | if (!netdev) | |
4758 | return; | |
4759 | ||
4760 | /* Bail out if netif_carrier is not OK */ | |
4761 | if (!netif_carrier_ok(netdev)) | |
4762 | return; | |
4763 | ||
4764 | /* Go thru' TX queues for netdev */ | |
4765 | for (i = 0; i < netdev->num_tx_queues; i++) { | |
4766 | struct netdev_queue *q; | |
4767 | ||
4768 | q = netdev_get_tx_queue(netdev, i); | |
4769 | if (q) | |
4770 | i40e_detect_recover_hung_queue(i, vsi); | |
4771 | } | |
4772 | } | |
4773 | ||
63d7e5a4 NP |
4774 | /** |
4775 | * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP | |
b40c82e6 | 4776 | * @pf: pointer to PF |
63d7e5a4 NP |
4777 | * |
4778 | * Get TC map for ISCSI PF type that will include iSCSI TC | |
4779 | * and LAN TC. | |
4780 | **/ | |
4781 | static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf) | |
4782 | { | |
4783 | struct i40e_dcb_app_priority_table app; | |
4784 | struct i40e_hw *hw = &pf->hw; | |
4785 | u8 enabled_tc = 1; /* TC0 is always enabled */ | |
4786 | u8 tc, i; | |
4787 | /* Get the iSCSI APP TLV */ | |
4788 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
4789 | ||
4790 | for (i = 0; i < dcbcfg->numapps; i++) { | |
4791 | app = dcbcfg->app[i]; | |
4792 | if (app.selector == I40E_APP_SEL_TCPIP && | |
4793 | app.protocolid == I40E_APP_PROTOID_ISCSI) { | |
4794 | tc = dcbcfg->etscfg.prioritytable[app.priority]; | |
75f5cea9 | 4795 | enabled_tc |= BIT(tc); |
63d7e5a4 NP |
4796 | break; |
4797 | } | |
4798 | } | |
4799 | ||
4800 | return enabled_tc; | |
4801 | } | |
4802 | ||
41c445ff JB |
4803 | /** |
4804 | * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config | |
4805 | * @dcbcfg: the corresponding DCBx configuration structure | |
4806 | * | |
4807 | * Return the number of TCs from given DCBx configuration | |
4808 | **/ | |
4809 | static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg) | |
4810 | { | |
fbfe12c6 | 4811 | int i, tc_unused = 0; |
078b5876 | 4812 | u8 num_tc = 0; |
fbfe12c6 | 4813 | u8 ret = 0; |
41c445ff JB |
4814 | |
4815 | /* Scan the ETS Config Priority Table to find | |
4816 | * traffic class enabled for a given priority | |
fbfe12c6 | 4817 | * and create a bitmask of enabled TCs |
41c445ff | 4818 | */ |
fbfe12c6 DE |
4819 | for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) |
4820 | num_tc |= BIT(dcbcfg->etscfg.prioritytable[i]); | |
41c445ff | 4821 | |
fbfe12c6 DE |
4822 | /* Now scan the bitmask to check for |
4823 | * contiguous TCs starting with TC0 | |
41c445ff | 4824 | */ |
fbfe12c6 DE |
4825 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
4826 | if (num_tc & BIT(i)) { | |
4827 | if (!tc_unused) { | |
4828 | ret++; | |
4829 | } else { | |
4830 | pr_err("Non-contiguous TC - Disabling DCB\n"); | |
4831 | return 1; | |
4832 | } | |
4833 | } else { | |
4834 | tc_unused = 1; | |
4835 | } | |
4836 | } | |
4837 | ||
4838 | /* There is always at least TC0 */ | |
4839 | if (!ret) | |
4840 | ret = 1; | |
4841 | ||
4842 | return ret; | |
41c445ff JB |
4843 | } |
4844 | ||
4845 | /** | |
4846 | * i40e_dcb_get_enabled_tc - Get enabled traffic classes | |
4847 | * @dcbcfg: the corresponding DCBx configuration structure | |
4848 | * | |
4849 | * Query the current DCB configuration and return the number of | |
4850 | * traffic classes enabled from the given DCBX config | |
4851 | **/ | |
4852 | static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg) | |
4853 | { | |
4854 | u8 num_tc = i40e_dcb_get_num_tc(dcbcfg); | |
4855 | u8 enabled_tc = 1; | |
4856 | u8 i; | |
4857 | ||
4858 | for (i = 0; i < num_tc; i++) | |
41a1d04b | 4859 | enabled_tc |= BIT(i); |
41c445ff JB |
4860 | |
4861 | return enabled_tc; | |
4862 | } | |
4863 | ||
4864 | /** | |
4865 | * i40e_pf_get_num_tc - Get enabled traffic classes for PF | |
4866 | * @pf: PF being queried | |
4867 | * | |
4868 | * Return number of traffic classes enabled for the given PF | |
4869 | **/ | |
4870 | static u8 i40e_pf_get_num_tc(struct i40e_pf *pf) | |
4871 | { | |
4872 | struct i40e_hw *hw = &pf->hw; | |
52a08caa | 4873 | u8 i, enabled_tc = 1; |
41c445ff JB |
4874 | u8 num_tc = 0; |
4875 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
4876 | ||
4877 | /* If DCB is not enabled then always in single TC */ | |
4878 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) | |
4879 | return 1; | |
4880 | ||
63d7e5a4 NP |
4881 | /* SFP mode will be enabled for all TCs on port */ |
4882 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) | |
4883 | return i40e_dcb_get_num_tc(dcbcfg); | |
4884 | ||
41c445ff | 4885 | /* MFP mode return count of enabled TCs for this PF */ |
63d7e5a4 NP |
4886 | if (pf->hw.func_caps.iscsi) |
4887 | enabled_tc = i40e_get_iscsi_tc_map(pf); | |
4888 | else | |
fc51de96 | 4889 | return 1; /* Only TC0 */ |
41c445ff | 4890 | |
63d7e5a4 | 4891 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { |
75f5cea9 | 4892 | if (enabled_tc & BIT(i)) |
63d7e5a4 NP |
4893 | num_tc++; |
4894 | } | |
4895 | return num_tc; | |
41c445ff JB |
4896 | } |
4897 | ||
41c445ff JB |
4898 | /** |
4899 | * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes | |
4900 | * @pf: PF being queried | |
4901 | * | |
4902 | * Return a bitmap for enabled traffic classes for this PF. | |
4903 | **/ | |
4904 | static u8 i40e_pf_get_tc_map(struct i40e_pf *pf) | |
4905 | { | |
4906 | /* If DCB is not enabled for this PF then just return default TC */ | |
4907 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) | |
ea6acb7e | 4908 | return I40E_DEFAULT_TRAFFIC_CLASS; |
41c445ff | 4909 | |
41c445ff | 4910 | /* SFP mode we want PF to be enabled for all TCs */ |
63d7e5a4 NP |
4911 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) |
4912 | return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config); | |
4913 | ||
fc51de96 | 4914 | /* MFP enabled and iSCSI PF type */ |
63d7e5a4 NP |
4915 | if (pf->hw.func_caps.iscsi) |
4916 | return i40e_get_iscsi_tc_map(pf); | |
4917 | else | |
ea6acb7e | 4918 | return I40E_DEFAULT_TRAFFIC_CLASS; |
41c445ff JB |
4919 | } |
4920 | ||
4921 | /** | |
4922 | * i40e_vsi_get_bw_info - Query VSI BW Information | |
4923 | * @vsi: the VSI being queried | |
4924 | * | |
4925 | * Returns 0 on success, negative value on failure | |
4926 | **/ | |
4927 | static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi) | |
4928 | { | |
4929 | struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0}; | |
4930 | struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0}; | |
4931 | struct i40e_pf *pf = vsi->back; | |
4932 | struct i40e_hw *hw = &pf->hw; | |
f1c7e72e | 4933 | i40e_status ret; |
41c445ff | 4934 | u32 tc_bw_max; |
41c445ff JB |
4935 | int i; |
4936 | ||
4937 | /* Get the VSI level BW configuration */ | |
f1c7e72e SN |
4938 | ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL); |
4939 | if (ret) { | |
41c445ff | 4940 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
4941 | "couldn't get PF vsi bw config, err %s aq_err %s\n", |
4942 | i40e_stat_str(&pf->hw, ret), | |
4943 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
dcae29be | 4944 | return -EINVAL; |
41c445ff JB |
4945 | } |
4946 | ||
4947 | /* Get the VSI level BW configuration per TC */ | |
f1c7e72e SN |
4948 | ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config, |
4949 | NULL); | |
4950 | if (ret) { | |
41c445ff | 4951 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
4952 | "couldn't get PF vsi ets bw config, err %s aq_err %s\n", |
4953 | i40e_stat_str(&pf->hw, ret), | |
4954 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
dcae29be | 4955 | return -EINVAL; |
41c445ff JB |
4956 | } |
4957 | ||
4958 | if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) { | |
4959 | dev_info(&pf->pdev->dev, | |
4960 | "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n", | |
4961 | bw_config.tc_valid_bits, | |
4962 | bw_ets_config.tc_valid_bits); | |
4963 | /* Still continuing */ | |
4964 | } | |
4965 | ||
4966 | vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit); | |
4967 | vsi->bw_max_quanta = bw_config.max_bw; | |
4968 | tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) | | |
4969 | (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16); | |
4970 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
4971 | vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i]; | |
4972 | vsi->bw_ets_limit_credits[i] = | |
4973 | le16_to_cpu(bw_ets_config.credits[i]); | |
4974 | /* 3 bits out of 4 for each TC */ | |
4975 | vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7); | |
4976 | } | |
078b5876 | 4977 | |
dcae29be | 4978 | return 0; |
41c445ff JB |
4979 | } |
4980 | ||
4981 | /** | |
4982 | * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC | |
4983 | * @vsi: the VSI being configured | |
4984 | * @enabled_tc: TC bitmap | |
4985 | * @bw_credits: BW shared credits per TC | |
4986 | * | |
4987 | * Returns 0 on success, negative value on failure | |
4988 | **/ | |
dcae29be | 4989 | static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc, |
41c445ff JB |
4990 | u8 *bw_share) |
4991 | { | |
4992 | struct i40e_aqc_configure_vsi_tc_bw_data bw_data; | |
f1c7e72e | 4993 | i40e_status ret; |
dcae29be | 4994 | int i; |
41c445ff JB |
4995 | |
4996 | bw_data.tc_valid_bits = enabled_tc; | |
4997 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
4998 | bw_data.tc_bw_credits[i] = bw_share[i]; | |
4999 | ||
f1c7e72e SN |
5000 | ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data, |
5001 | NULL); | |
5002 | if (ret) { | |
41c445ff | 5003 | dev_info(&vsi->back->pdev->dev, |
69bfb110 JB |
5004 | "AQ command Config VSI BW allocation per TC failed = %d\n", |
5005 | vsi->back->hw.aq.asq_last_status); | |
dcae29be | 5006 | return -EINVAL; |
41c445ff JB |
5007 | } |
5008 | ||
5009 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) | |
5010 | vsi->info.qs_handle[i] = bw_data.qs_handles[i]; | |
5011 | ||
dcae29be | 5012 | return 0; |
41c445ff JB |
5013 | } |
5014 | ||
5015 | /** | |
5016 | * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration | |
5017 | * @vsi: the VSI being configured | |
5018 | * @enabled_tc: TC map to be enabled | |
5019 | * | |
5020 | **/ | |
5021 | static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc) | |
5022 | { | |
5023 | struct net_device *netdev = vsi->netdev; | |
5024 | struct i40e_pf *pf = vsi->back; | |
5025 | struct i40e_hw *hw = &pf->hw; | |
5026 | u8 netdev_tc = 0; | |
5027 | int i; | |
5028 | struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config; | |
5029 | ||
5030 | if (!netdev) | |
5031 | return; | |
5032 | ||
5033 | if (!enabled_tc) { | |
5034 | netdev_reset_tc(netdev); | |
5035 | return; | |
5036 | } | |
5037 | ||
5038 | /* Set up actual enabled TCs on the VSI */ | |
5039 | if (netdev_set_num_tc(netdev, vsi->tc_config.numtc)) | |
5040 | return; | |
5041 | ||
5042 | /* set per TC queues for the VSI */ | |
5043 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
5044 | /* Only set TC queues for enabled tcs | |
5045 | * | |
5046 | * e.g. For a VSI that has TC0 and TC3 enabled the | |
5047 | * enabled_tc bitmap would be 0x00001001; the driver | |
5048 | * will set the numtc for netdev as 2 that will be | |
5049 | * referenced by the netdev layer as TC 0 and 1. | |
5050 | */ | |
75f5cea9 | 5051 | if (vsi->tc_config.enabled_tc & BIT(i)) |
41c445ff JB |
5052 | netdev_set_tc_queue(netdev, |
5053 | vsi->tc_config.tc_info[i].netdev_tc, | |
5054 | vsi->tc_config.tc_info[i].qcount, | |
5055 | vsi->tc_config.tc_info[i].qoffset); | |
5056 | } | |
5057 | ||
5058 | /* Assign UP2TC map for the VSI */ | |
5059 | for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) { | |
5060 | /* Get the actual TC# for the UP */ | |
5061 | u8 ets_tc = dcbcfg->etscfg.prioritytable[i]; | |
5062 | /* Get the mapped netdev TC# for the UP */ | |
5063 | netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc; | |
5064 | netdev_set_prio_tc_map(netdev, i, netdev_tc); | |
5065 | } | |
5066 | } | |
5067 | ||
5068 | /** | |
5069 | * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map | |
5070 | * @vsi: the VSI being configured | |
5071 | * @ctxt: the ctxt buffer returned from AQ VSI update param command | |
5072 | **/ | |
5073 | static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi, | |
5074 | struct i40e_vsi_context *ctxt) | |
5075 | { | |
5076 | /* copy just the sections touched not the entire info | |
5077 | * since not all sections are valid as returned by | |
5078 | * update vsi params | |
5079 | */ | |
5080 | vsi->info.mapping_flags = ctxt->info.mapping_flags; | |
5081 | memcpy(&vsi->info.queue_mapping, | |
5082 | &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping)); | |
5083 | memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping, | |
5084 | sizeof(vsi->info.tc_mapping)); | |
5085 | } | |
5086 | ||
5087 | /** | |
5088 | * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map | |
5089 | * @vsi: VSI to be configured | |
5090 | * @enabled_tc: TC bitmap | |
5091 | * | |
5092 | * This configures a particular VSI for TCs that are mapped to the | |
5093 | * given TC bitmap. It uses default bandwidth share for TCs across | |
5094 | * VSIs to configure TC for a particular VSI. | |
5095 | * | |
5096 | * NOTE: | |
5097 | * It is expected that the VSI queues have been quisced before calling | |
5098 | * this function. | |
5099 | **/ | |
5100 | static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc) | |
5101 | { | |
5102 | u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0}; | |
5103 | struct i40e_vsi_context ctxt; | |
5104 | int ret = 0; | |
5105 | int i; | |
5106 | ||
5107 | /* Check if enabled_tc is same as existing or new TCs */ | |
5108 | if (vsi->tc_config.enabled_tc == enabled_tc) | |
5109 | return ret; | |
5110 | ||
5111 | /* Enable ETS TCs with equal BW Share for now across all VSIs */ | |
5112 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 5113 | if (enabled_tc & BIT(i)) |
41c445ff JB |
5114 | bw_share[i] = 1; |
5115 | } | |
5116 | ||
5117 | ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share); | |
5118 | if (ret) { | |
5119 | dev_info(&vsi->back->pdev->dev, | |
5120 | "Failed configuring TC map %d for VSI %d\n", | |
5121 | enabled_tc, vsi->seid); | |
5122 | goto out; | |
5123 | } | |
5124 | ||
5125 | /* Update Queue Pairs Mapping for currently enabled UPs */ | |
5126 | ctxt.seid = vsi->seid; | |
5127 | ctxt.pf_num = vsi->back->hw.pf_id; | |
5128 | ctxt.vf_num = 0; | |
5129 | ctxt.uplink_seid = vsi->uplink_seid; | |
1a2f6248 | 5130 | ctxt.info = vsi->info; |
41c445ff JB |
5131 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); |
5132 | ||
e3219ce6 ASJ |
5133 | if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { |
5134 | ctxt.info.valid_sections |= | |
5135 | cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); | |
5136 | ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA; | |
5137 | } | |
5138 | ||
41c445ff JB |
5139 | /* Update the VSI after updating the VSI queue-mapping information */ |
5140 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); | |
5141 | if (ret) { | |
5142 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
5143 | "Update vsi tc config failed, err %s aq_err %s\n", |
5144 | i40e_stat_str(&vsi->back->hw, ret), | |
5145 | i40e_aq_str(&vsi->back->hw, | |
5146 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
5147 | goto out; |
5148 | } | |
5149 | /* update the local VSI info with updated queue map */ | |
5150 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
5151 | vsi->info.valid_sections = 0; | |
5152 | ||
5153 | /* Update current VSI BW information */ | |
5154 | ret = i40e_vsi_get_bw_info(vsi); | |
5155 | if (ret) { | |
5156 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
5157 | "Failed updating vsi bw info, err %s aq_err %s\n", |
5158 | i40e_stat_str(&vsi->back->hw, ret), | |
5159 | i40e_aq_str(&vsi->back->hw, | |
5160 | vsi->back->hw.aq.asq_last_status)); | |
41c445ff JB |
5161 | goto out; |
5162 | } | |
5163 | ||
5164 | /* Update the netdev TC setup */ | |
5165 | i40e_vsi_config_netdev_tc(vsi, enabled_tc); | |
5166 | out: | |
5167 | return ret; | |
5168 | } | |
5169 | ||
4e3b35b0 NP |
5170 | /** |
5171 | * i40e_veb_config_tc - Configure TCs for given VEB | |
5172 | * @veb: given VEB | |
5173 | * @enabled_tc: TC bitmap | |
5174 | * | |
5175 | * Configures given TC bitmap for VEB (switching) element | |
5176 | **/ | |
5177 | int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc) | |
5178 | { | |
5179 | struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0}; | |
5180 | struct i40e_pf *pf = veb->pf; | |
5181 | int ret = 0; | |
5182 | int i; | |
5183 | ||
5184 | /* No TCs or already enabled TCs just return */ | |
5185 | if (!enabled_tc || veb->enabled_tc == enabled_tc) | |
5186 | return ret; | |
5187 | ||
5188 | bw_data.tc_valid_bits = enabled_tc; | |
5189 | /* bw_data.absolute_credits is not set (relative) */ | |
5190 | ||
5191 | /* Enable ETS TCs with equal BW Share for now */ | |
5192 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
75f5cea9 | 5193 | if (enabled_tc & BIT(i)) |
4e3b35b0 NP |
5194 | bw_data.tc_bw_share_credits[i] = 1; |
5195 | } | |
5196 | ||
5197 | ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid, | |
5198 | &bw_data, NULL); | |
5199 | if (ret) { | |
5200 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
5201 | "VEB bw config failed, err %s aq_err %s\n", |
5202 | i40e_stat_str(&pf->hw, ret), | |
5203 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
5204 | goto out; |
5205 | } | |
5206 | ||
5207 | /* Update the BW information */ | |
5208 | ret = i40e_veb_get_bw_info(veb); | |
5209 | if (ret) { | |
5210 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
5211 | "Failed getting veb bw config, err %s aq_err %s\n", |
5212 | i40e_stat_str(&pf->hw, ret), | |
5213 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
5214 | } |
5215 | ||
5216 | out: | |
5217 | return ret; | |
5218 | } | |
5219 | ||
5220 | #ifdef CONFIG_I40E_DCB | |
5221 | /** | |
5222 | * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs | |
5223 | * @pf: PF struct | |
5224 | * | |
5225 | * Reconfigure VEB/VSIs on a given PF; it is assumed that | |
5226 | * the caller would've quiesce all the VSIs before calling | |
5227 | * this function | |
5228 | **/ | |
5229 | static void i40e_dcb_reconfigure(struct i40e_pf *pf) | |
5230 | { | |
5231 | u8 tc_map = 0; | |
5232 | int ret; | |
5233 | u8 v; | |
5234 | ||
5235 | /* Enable the TCs available on PF to all VEBs */ | |
5236 | tc_map = i40e_pf_get_tc_map(pf); | |
5237 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
5238 | if (!pf->veb[v]) | |
5239 | continue; | |
5240 | ret = i40e_veb_config_tc(pf->veb[v], tc_map); | |
5241 | if (ret) { | |
5242 | dev_info(&pf->pdev->dev, | |
5243 | "Failed configuring TC for VEB seid=%d\n", | |
5244 | pf->veb[v]->seid); | |
5245 | /* Will try to configure as many components */ | |
5246 | } | |
5247 | } | |
5248 | ||
5249 | /* Update each VSI */ | |
505682cd | 5250 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
4e3b35b0 NP |
5251 | if (!pf->vsi[v]) |
5252 | continue; | |
5253 | ||
5254 | /* - Enable all TCs for the LAN VSI | |
5255 | * - For all others keep them at TC0 for now | |
5256 | */ | |
5257 | if (v == pf->lan_vsi) | |
5258 | tc_map = i40e_pf_get_tc_map(pf); | |
5259 | else | |
ea6acb7e | 5260 | tc_map = I40E_DEFAULT_TRAFFIC_CLASS; |
4e3b35b0 NP |
5261 | |
5262 | ret = i40e_vsi_config_tc(pf->vsi[v], tc_map); | |
5263 | if (ret) { | |
5264 | dev_info(&pf->pdev->dev, | |
5265 | "Failed configuring TC for VSI seid=%d\n", | |
5266 | pf->vsi[v]->seid); | |
5267 | /* Will try to configure as many components */ | |
5268 | } else { | |
0672a091 NP |
5269 | /* Re-configure VSI vectors based on updated TC map */ |
5270 | i40e_vsi_map_rings_to_vectors(pf->vsi[v]); | |
4e3b35b0 NP |
5271 | if (pf->vsi[v]->netdev) |
5272 | i40e_dcbnl_set_all(pf->vsi[v]); | |
5273 | } | |
5274 | } | |
5275 | } | |
5276 | ||
2fd75f31 NP |
5277 | /** |
5278 | * i40e_resume_port_tx - Resume port Tx | |
5279 | * @pf: PF struct | |
5280 | * | |
5281 | * Resume a port's Tx and issue a PF reset in case of failure to | |
5282 | * resume. | |
5283 | **/ | |
5284 | static int i40e_resume_port_tx(struct i40e_pf *pf) | |
5285 | { | |
5286 | struct i40e_hw *hw = &pf->hw; | |
5287 | int ret; | |
5288 | ||
5289 | ret = i40e_aq_resume_port_tx(hw, NULL); | |
5290 | if (ret) { | |
5291 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
5292 | "Resume Port Tx failed, err %s aq_err %s\n", |
5293 | i40e_stat_str(&pf->hw, ret), | |
5294 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
2fd75f31 | 5295 | /* Schedule PF reset to recover */ |
0da36b97 | 5296 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
2fd75f31 NP |
5297 | i40e_service_event_schedule(pf); |
5298 | } | |
5299 | ||
5300 | return ret; | |
5301 | } | |
5302 | ||
4e3b35b0 NP |
5303 | /** |
5304 | * i40e_init_pf_dcb - Initialize DCB configuration | |
5305 | * @pf: PF being configured | |
5306 | * | |
5307 | * Query the current DCB configuration and cache it | |
5308 | * in the hardware structure | |
5309 | **/ | |
5310 | static int i40e_init_pf_dcb(struct i40e_pf *pf) | |
5311 | { | |
5312 | struct i40e_hw *hw = &pf->hw; | |
5313 | int err = 0; | |
5314 | ||
025b4a54 | 5315 | /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */ |
d36e41dc | 5316 | if (pf->hw_features & I40E_HW_NO_DCB_SUPPORT) |
025b4a54 ASJ |
5317 | goto out; |
5318 | ||
4e3b35b0 NP |
5319 | /* Get the initial DCB configuration */ |
5320 | err = i40e_init_dcb(hw); | |
5321 | if (!err) { | |
5322 | /* Device/Function is not DCBX capable */ | |
5323 | if ((!hw->func_caps.dcb) || | |
5324 | (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) { | |
5325 | dev_info(&pf->pdev->dev, | |
5326 | "DCBX offload is not supported or is disabled for this PF.\n"); | |
4e3b35b0 NP |
5327 | } else { |
5328 | /* When status is not DISABLED then DCBX in FW */ | |
5329 | pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED | | |
5330 | DCB_CAP_DCBX_VER_IEEE; | |
4d9b6043 NP |
5331 | |
5332 | pf->flags |= I40E_FLAG_DCB_CAPABLE; | |
a036244c DE |
5333 | /* Enable DCB tagging only when more than one TC |
5334 | * or explicitly disable if only one TC | |
5335 | */ | |
4d9b6043 NP |
5336 | if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) |
5337 | pf->flags |= I40E_FLAG_DCB_ENABLED; | |
a036244c DE |
5338 | else |
5339 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
9fa61dd2 NP |
5340 | dev_dbg(&pf->pdev->dev, |
5341 | "DCBX offload is supported for this PF.\n"); | |
4e3b35b0 | 5342 | } |
014269ff | 5343 | } else { |
aebfc816 | 5344 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
5345 | "Query for DCB configuration failed, err %s aq_err %s\n", |
5346 | i40e_stat_str(&pf->hw, err), | |
5347 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
5348 | } |
5349 | ||
5350 | out: | |
5351 | return err; | |
5352 | } | |
5353 | #endif /* CONFIG_I40E_DCB */ | |
cf05ed08 JB |
5354 | #define SPEED_SIZE 14 |
5355 | #define FC_SIZE 8 | |
5356 | /** | |
5357 | * i40e_print_link_message - print link up or down | |
5358 | * @vsi: the VSI for which link needs a message | |
5359 | */ | |
c156f856 | 5360 | void i40e_print_link_message(struct i40e_vsi *vsi, bool isup) |
cf05ed08 | 5361 | { |
7ec9ba11 | 5362 | enum i40e_aq_link_speed new_speed; |
3fded466 | 5363 | struct i40e_pf *pf = vsi->back; |
a9165490 SN |
5364 | char *speed = "Unknown"; |
5365 | char *fc = "Unknown"; | |
3e03d7cc | 5366 | char *fec = ""; |
68e49702 | 5367 | char *req_fec = ""; |
3e03d7cc | 5368 | char *an = ""; |
cf05ed08 | 5369 | |
3fded466 | 5370 | new_speed = pf->hw.phy.link_info.link_speed; |
7ec9ba11 FS |
5371 | |
5372 | if ((vsi->current_isup == isup) && (vsi->current_speed == new_speed)) | |
c156f856 MJ |
5373 | return; |
5374 | vsi->current_isup = isup; | |
7ec9ba11 | 5375 | vsi->current_speed = new_speed; |
cf05ed08 JB |
5376 | if (!isup) { |
5377 | netdev_info(vsi->netdev, "NIC Link is Down\n"); | |
5378 | return; | |
5379 | } | |
5380 | ||
148c2d80 GR |
5381 | /* Warn user if link speed on NPAR enabled partition is not at |
5382 | * least 10GB | |
5383 | */ | |
3fded466 SM |
5384 | if (pf->hw.func_caps.npar_enable && |
5385 | (pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB || | |
5386 | pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB)) | |
148c2d80 GR |
5387 | netdev_warn(vsi->netdev, |
5388 | "The partition detected link speed that is less than 10Gbps\n"); | |
5389 | ||
3fded466 | 5390 | switch (pf->hw.phy.link_info.link_speed) { |
cf05ed08 | 5391 | case I40E_LINK_SPEED_40GB: |
a9165490 | 5392 | speed = "40 G"; |
cf05ed08 | 5393 | break; |
ae24b409 | 5394 | case I40E_LINK_SPEED_20GB: |
a9165490 | 5395 | speed = "20 G"; |
ae24b409 | 5396 | break; |
3123237a CW |
5397 | case I40E_LINK_SPEED_25GB: |
5398 | speed = "25 G"; | |
5399 | break; | |
cf05ed08 | 5400 | case I40E_LINK_SPEED_10GB: |
a9165490 | 5401 | speed = "10 G"; |
cf05ed08 JB |
5402 | break; |
5403 | case I40E_LINK_SPEED_1GB: | |
a9165490 | 5404 | speed = "1000 M"; |
cf05ed08 | 5405 | break; |
5960d33f | 5406 | case I40E_LINK_SPEED_100MB: |
a9165490 | 5407 | speed = "100 M"; |
5960d33f | 5408 | break; |
cf05ed08 JB |
5409 | default: |
5410 | break; | |
5411 | } | |
5412 | ||
3fded466 | 5413 | switch (pf->hw.fc.current_mode) { |
cf05ed08 | 5414 | case I40E_FC_FULL: |
a9165490 | 5415 | fc = "RX/TX"; |
cf05ed08 JB |
5416 | break; |
5417 | case I40E_FC_TX_PAUSE: | |
a9165490 | 5418 | fc = "TX"; |
cf05ed08 JB |
5419 | break; |
5420 | case I40E_FC_RX_PAUSE: | |
a9165490 | 5421 | fc = "RX"; |
cf05ed08 JB |
5422 | break; |
5423 | default: | |
a9165490 | 5424 | fc = "None"; |
cf05ed08 JB |
5425 | break; |
5426 | } | |
5427 | ||
3fded466 | 5428 | if (pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_25GB) { |
68e49702 | 5429 | req_fec = ", Requested FEC: None"; |
3e03d7cc HT |
5430 | fec = ", FEC: None"; |
5431 | an = ", Autoneg: False"; | |
5432 | ||
3fded466 | 5433 | if (pf->hw.phy.link_info.an_info & I40E_AQ_AN_COMPLETED) |
3e03d7cc HT |
5434 | an = ", Autoneg: True"; |
5435 | ||
3fded466 | 5436 | if (pf->hw.phy.link_info.fec_info & |
3e03d7cc HT |
5437 | I40E_AQ_CONFIG_FEC_KR_ENA) |
5438 | fec = ", FEC: CL74 FC-FEC/BASE-R"; | |
3fded466 | 5439 | else if (pf->hw.phy.link_info.fec_info & |
3e03d7cc HT |
5440 | I40E_AQ_CONFIG_FEC_RS_ENA) |
5441 | fec = ", FEC: CL108 RS-FEC"; | |
68e49702 MS |
5442 | |
5443 | /* 'CL108 RS-FEC' should be displayed when RS is requested, or | |
5444 | * both RS and FC are requested | |
5445 | */ | |
5446 | if (vsi->back->hw.phy.link_info.req_fec_info & | |
5447 | (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS)) { | |
5448 | if (vsi->back->hw.phy.link_info.req_fec_info & | |
5449 | I40E_AQ_REQUEST_FEC_RS) | |
5450 | req_fec = ", Requested FEC: CL108 RS-FEC"; | |
5451 | else | |
5452 | req_fec = ", Requested FEC: CL74 FC-FEC/BASE-R"; | |
5453 | } | |
3e03d7cc HT |
5454 | } |
5455 | ||
68e49702 MS |
5456 | netdev_info(vsi->netdev, "NIC Link is Up, %sbps Full Duplex%s%s%s, Flow Control: %s\n", |
5457 | speed, req_fec, fec, an, fc); | |
cf05ed08 | 5458 | } |
4e3b35b0 | 5459 | |
41c445ff JB |
5460 | /** |
5461 | * i40e_up_complete - Finish the last steps of bringing up a connection | |
5462 | * @vsi: the VSI being configured | |
5463 | **/ | |
5464 | static int i40e_up_complete(struct i40e_vsi *vsi) | |
5465 | { | |
5466 | struct i40e_pf *pf = vsi->back; | |
5467 | int err; | |
5468 | ||
5469 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
5470 | i40e_vsi_configure_msix(vsi); | |
5471 | else | |
5472 | i40e_configure_msi_and_legacy(vsi); | |
5473 | ||
5474 | /* start rings */ | |
3aa7b74d | 5475 | err = i40e_vsi_start_rings(vsi); |
41c445ff JB |
5476 | if (err) |
5477 | return err; | |
5478 | ||
0da36b97 | 5479 | clear_bit(__I40E_VSI_DOWN, vsi->state); |
41c445ff JB |
5480 | i40e_napi_enable_all(vsi); |
5481 | i40e_vsi_enable_irq(vsi); | |
5482 | ||
5483 | if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) && | |
5484 | (vsi->netdev)) { | |
cf05ed08 | 5485 | i40e_print_link_message(vsi, true); |
41c445ff JB |
5486 | netif_tx_start_all_queues(vsi->netdev); |
5487 | netif_carrier_on(vsi->netdev); | |
5488 | } | |
ca64fa4e ASJ |
5489 | |
5490 | /* replay FDIR SB filters */ | |
1e1be8f6 ASJ |
5491 | if (vsi->type == I40E_VSI_FDIR) { |
5492 | /* reset fd counters */ | |
097dbf52 JK |
5493 | pf->fd_add_err = 0; |
5494 | pf->fd_atr_cnt = 0; | |
ca64fa4e | 5495 | i40e_fdir_filter_restore(vsi); |
1e1be8f6 | 5496 | } |
e3219ce6 ASJ |
5497 | |
5498 | /* On the next run of the service_task, notify any clients of the new | |
5499 | * opened netdev | |
5500 | */ | |
5501 | pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED; | |
41c445ff JB |
5502 | i40e_service_event_schedule(pf); |
5503 | ||
5504 | return 0; | |
5505 | } | |
5506 | ||
5507 | /** | |
5508 | * i40e_vsi_reinit_locked - Reset the VSI | |
5509 | * @vsi: the VSI being configured | |
5510 | * | |
5511 | * Rebuild the ring structs after some configuration | |
5512 | * has changed, e.g. MTU size. | |
5513 | **/ | |
5514 | static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi) | |
5515 | { | |
5516 | struct i40e_pf *pf = vsi->back; | |
5517 | ||
5518 | WARN_ON(in_interrupt()); | |
0da36b97 | 5519 | while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state)) |
41c445ff JB |
5520 | usleep_range(1000, 2000); |
5521 | i40e_down(vsi); | |
5522 | ||
41c445ff | 5523 | i40e_up(vsi); |
0da36b97 | 5524 | clear_bit(__I40E_CONFIG_BUSY, pf->state); |
41c445ff JB |
5525 | } |
5526 | ||
5527 | /** | |
5528 | * i40e_up - Bring the connection back up after being down | |
5529 | * @vsi: the VSI being configured | |
5530 | **/ | |
5531 | int i40e_up(struct i40e_vsi *vsi) | |
5532 | { | |
5533 | int err; | |
5534 | ||
5535 | err = i40e_vsi_configure(vsi); | |
5536 | if (!err) | |
5537 | err = i40e_up_complete(vsi); | |
5538 | ||
5539 | return err; | |
5540 | } | |
5541 | ||
5542 | /** | |
5543 | * i40e_down - Shutdown the connection processing | |
5544 | * @vsi: the VSI being stopped | |
5545 | **/ | |
5546 | void i40e_down(struct i40e_vsi *vsi) | |
5547 | { | |
5548 | int i; | |
5549 | ||
5550 | /* It is assumed that the caller of this function | |
d19cb64b | 5551 | * sets the vsi->state __I40E_VSI_DOWN bit. |
41c445ff JB |
5552 | */ |
5553 | if (vsi->netdev) { | |
5554 | netif_carrier_off(vsi->netdev); | |
5555 | netif_tx_disable(vsi->netdev); | |
5556 | } | |
5557 | i40e_vsi_disable_irq(vsi); | |
3aa7b74d | 5558 | i40e_vsi_stop_rings(vsi); |
41c445ff JB |
5559 | i40e_napi_disable_all(vsi); |
5560 | ||
5561 | for (i = 0; i < vsi->num_queue_pairs; i++) { | |
9f65e15b | 5562 | i40e_clean_tx_ring(vsi->tx_rings[i]); |
74608d17 BT |
5563 | if (i40e_enabled_xdp_vsi(vsi)) |
5564 | i40e_clean_tx_ring(vsi->xdp_rings[i]); | |
9f65e15b | 5565 | i40e_clean_rx_ring(vsi->rx_rings[i]); |
41c445ff | 5566 | } |
f980d445 | 5567 | |
41c445ff JB |
5568 | } |
5569 | ||
5570 | /** | |
5571 | * i40e_setup_tc - configure multiple traffic classes | |
5572 | * @netdev: net device to configure | |
5573 | * @tc: number of traffic classes to enable | |
5574 | **/ | |
5575 | static int i40e_setup_tc(struct net_device *netdev, u8 tc) | |
5576 | { | |
5577 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
5578 | struct i40e_vsi *vsi = np->vsi; | |
5579 | struct i40e_pf *pf = vsi->back; | |
5580 | u8 enabled_tc = 0; | |
5581 | int ret = -EINVAL; | |
5582 | int i; | |
5583 | ||
5584 | /* Check if DCB enabled to continue */ | |
5585 | if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) { | |
5586 | netdev_info(netdev, "DCB is not enabled for adapter\n"); | |
5587 | goto exit; | |
5588 | } | |
5589 | ||
5590 | /* Check if MFP enabled */ | |
5591 | if (pf->flags & I40E_FLAG_MFP_ENABLED) { | |
5592 | netdev_info(netdev, "Configuring TC not supported in MFP mode\n"); | |
5593 | goto exit; | |
5594 | } | |
5595 | ||
5596 | /* Check whether tc count is within enabled limit */ | |
5597 | if (tc > i40e_pf_get_num_tc(pf)) { | |
5598 | netdev_info(netdev, "TC count greater than enabled on link for adapter\n"); | |
5599 | goto exit; | |
5600 | } | |
5601 | ||
5602 | /* Generate TC map for number of tc requested */ | |
5603 | for (i = 0; i < tc; i++) | |
75f5cea9 | 5604 | enabled_tc |= BIT(i); |
41c445ff JB |
5605 | |
5606 | /* Requesting same TC configuration as already enabled */ | |
5607 | if (enabled_tc == vsi->tc_config.enabled_tc) | |
5608 | return 0; | |
5609 | ||
5610 | /* Quiesce VSI queues */ | |
5611 | i40e_quiesce_vsi(vsi); | |
5612 | ||
5613 | /* Configure VSI for enabled TCs */ | |
5614 | ret = i40e_vsi_config_tc(vsi, enabled_tc); | |
5615 | if (ret) { | |
5616 | netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n", | |
5617 | vsi->seid); | |
5618 | goto exit; | |
5619 | } | |
5620 | ||
5621 | /* Unquiesce VSI */ | |
5622 | i40e_unquiesce_vsi(vsi); | |
5623 | ||
5624 | exit: | |
5625 | return ret; | |
5626 | } | |
5627 | ||
2572ac53 | 5628 | static int __i40e_setup_tc(struct net_device *netdev, enum tc_setup_type type, |
de4784ca | 5629 | void *type_data) |
e4c6734e | 5630 | { |
de4784ca JP |
5631 | struct tc_mqprio_qopt *mqprio = type_data; |
5632 | ||
2572ac53 | 5633 | if (type != TC_SETUP_MQPRIO) |
38cf0426 | 5634 | return -EOPNOTSUPP; |
56f36acd | 5635 | |
de4784ca | 5636 | mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS; |
56f36acd | 5637 | |
de4784ca | 5638 | return i40e_setup_tc(netdev, mqprio->num_tc); |
e4c6734e JF |
5639 | } |
5640 | ||
41c445ff JB |
5641 | /** |
5642 | * i40e_open - Called when a network interface is made active | |
5643 | * @netdev: network interface device structure | |
5644 | * | |
5645 | * The open entry point is called when a network interface is made | |
5646 | * active by the system (IFF_UP). At this point all resources needed | |
5647 | * for transmit and receive operations are allocated, the interrupt | |
5648 | * handler is registered with the OS, the netdev watchdog subtask is | |
5649 | * enabled, and the stack is notified that the interface is ready. | |
5650 | * | |
5651 | * Returns 0 on success, negative value on failure | |
5652 | **/ | |
38e00438 | 5653 | int i40e_open(struct net_device *netdev) |
41c445ff JB |
5654 | { |
5655 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
5656 | struct i40e_vsi *vsi = np->vsi; | |
5657 | struct i40e_pf *pf = vsi->back; | |
41c445ff JB |
5658 | int err; |
5659 | ||
4eb3f768 | 5660 | /* disallow open during test or if eeprom is broken */ |
0da36b97 JK |
5661 | if (test_bit(__I40E_TESTING, pf->state) || |
5662 | test_bit(__I40E_BAD_EEPROM, pf->state)) | |
41c445ff JB |
5663 | return -EBUSY; |
5664 | ||
5665 | netif_carrier_off(netdev); | |
5666 | ||
6c167f58 EK |
5667 | err = i40e_vsi_open(vsi); |
5668 | if (err) | |
5669 | return err; | |
5670 | ||
059dab69 JB |
5671 | /* configure global TSO hardware offload settings */ |
5672 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH | | |
5673 | TCP_FLAG_FIN) >> 16); | |
5674 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH | | |
5675 | TCP_FLAG_FIN | | |
5676 | TCP_FLAG_CWR) >> 16); | |
5677 | wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16); | |
5678 | ||
06a5f7f1 | 5679 | udp_tunnel_get_rx_info(netdev); |
e3219ce6 | 5680 | |
6c167f58 EK |
5681 | return 0; |
5682 | } | |
5683 | ||
5684 | /** | |
5685 | * i40e_vsi_open - | |
5686 | * @vsi: the VSI to open | |
5687 | * | |
5688 | * Finish initialization of the VSI. | |
5689 | * | |
5690 | * Returns 0 on success, negative value on failure | |
373149fc MS |
5691 | * |
5692 | * Note: expects to be called while under rtnl_lock() | |
6c167f58 EK |
5693 | **/ |
5694 | int i40e_vsi_open(struct i40e_vsi *vsi) | |
5695 | { | |
5696 | struct i40e_pf *pf = vsi->back; | |
b294ac70 | 5697 | char int_name[I40E_INT_NAME_STR_LEN]; |
6c167f58 EK |
5698 | int err; |
5699 | ||
41c445ff JB |
5700 | /* allocate descriptors */ |
5701 | err = i40e_vsi_setup_tx_resources(vsi); | |
5702 | if (err) | |
5703 | goto err_setup_tx; | |
5704 | err = i40e_vsi_setup_rx_resources(vsi); | |
5705 | if (err) | |
5706 | goto err_setup_rx; | |
5707 | ||
5708 | err = i40e_vsi_configure(vsi); | |
5709 | if (err) | |
5710 | goto err_setup_rx; | |
5711 | ||
c22e3c6c SN |
5712 | if (vsi->netdev) { |
5713 | snprintf(int_name, sizeof(int_name) - 1, "%s-%s", | |
5714 | dev_driver_string(&pf->pdev->dev), vsi->netdev->name); | |
5715 | err = i40e_vsi_request_irq(vsi, int_name); | |
5716 | if (err) | |
5717 | goto err_setup_rx; | |
41c445ff | 5718 | |
c22e3c6c SN |
5719 | /* Notify the stack of the actual queue counts. */ |
5720 | err = netif_set_real_num_tx_queues(vsi->netdev, | |
5721 | vsi->num_queue_pairs); | |
5722 | if (err) | |
5723 | goto err_set_queues; | |
25946ddb | 5724 | |
c22e3c6c SN |
5725 | err = netif_set_real_num_rx_queues(vsi->netdev, |
5726 | vsi->num_queue_pairs); | |
5727 | if (err) | |
5728 | goto err_set_queues; | |
8a9eb7d3 SN |
5729 | |
5730 | } else if (vsi->type == I40E_VSI_FDIR) { | |
e240f674 | 5731 | snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir", |
b2008cbf CW |
5732 | dev_driver_string(&pf->pdev->dev), |
5733 | dev_name(&pf->pdev->dev)); | |
8a9eb7d3 | 5734 | err = i40e_vsi_request_irq(vsi, int_name); |
b2008cbf | 5735 | |
c22e3c6c | 5736 | } else { |
ce9ccb17 | 5737 | err = -EINVAL; |
6c167f58 EK |
5738 | goto err_setup_rx; |
5739 | } | |
25946ddb | 5740 | |
41c445ff JB |
5741 | err = i40e_up_complete(vsi); |
5742 | if (err) | |
5743 | goto err_up_complete; | |
5744 | ||
41c445ff JB |
5745 | return 0; |
5746 | ||
5747 | err_up_complete: | |
5748 | i40e_down(vsi); | |
25946ddb | 5749 | err_set_queues: |
41c445ff JB |
5750 | i40e_vsi_free_irq(vsi); |
5751 | err_setup_rx: | |
5752 | i40e_vsi_free_rx_resources(vsi); | |
5753 | err_setup_tx: | |
5754 | i40e_vsi_free_tx_resources(vsi); | |
5755 | if (vsi == pf->vsi[pf->lan_vsi]) | |
373149fc | 5756 | i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED), true); |
41c445ff JB |
5757 | |
5758 | return err; | |
5759 | } | |
5760 | ||
17a73f6b JG |
5761 | /** |
5762 | * i40e_fdir_filter_exit - Cleans up the Flow Director accounting | |
b40c82e6 | 5763 | * @pf: Pointer to PF |
17a73f6b JG |
5764 | * |
5765 | * This function destroys the hlist where all the Flow Director | |
5766 | * filters were saved. | |
5767 | **/ | |
5768 | static void i40e_fdir_filter_exit(struct i40e_pf *pf) | |
5769 | { | |
5770 | struct i40e_fdir_filter *filter; | |
0e588de1 | 5771 | struct i40e_flex_pit *pit_entry, *tmp; |
17a73f6b JG |
5772 | struct hlist_node *node2; |
5773 | ||
5774 | hlist_for_each_entry_safe(filter, node2, | |
5775 | &pf->fdir_filter_list, fdir_node) { | |
5776 | hlist_del(&filter->fdir_node); | |
5777 | kfree(filter); | |
5778 | } | |
097dbf52 | 5779 | |
0e588de1 JK |
5780 | list_for_each_entry_safe(pit_entry, tmp, &pf->l3_flex_pit_list, list) { |
5781 | list_del(&pit_entry->list); | |
5782 | kfree(pit_entry); | |
5783 | } | |
5784 | INIT_LIST_HEAD(&pf->l3_flex_pit_list); | |
5785 | ||
5786 | list_for_each_entry_safe(pit_entry, tmp, &pf->l4_flex_pit_list, list) { | |
5787 | list_del(&pit_entry->list); | |
5788 | kfree(pit_entry); | |
5789 | } | |
5790 | INIT_LIST_HEAD(&pf->l4_flex_pit_list); | |
5791 | ||
17a73f6b | 5792 | pf->fdir_pf_active_filters = 0; |
097dbf52 JK |
5793 | pf->fd_tcp4_filter_cnt = 0; |
5794 | pf->fd_udp4_filter_cnt = 0; | |
f223c875 | 5795 | pf->fd_sctp4_filter_cnt = 0; |
097dbf52 | 5796 | pf->fd_ip4_filter_cnt = 0; |
3bcee1e6 JK |
5797 | |
5798 | /* Reprogram the default input set for TCP/IPv4 */ | |
5799 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_TCP, | |
5800 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
5801 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
5802 | ||
5803 | /* Reprogram the default input set for UDP/IPv4 */ | |
5804 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_UDP, | |
5805 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
5806 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
5807 | ||
5808 | /* Reprogram the default input set for SCTP/IPv4 */ | |
5809 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_SCTP, | |
5810 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK | | |
5811 | I40E_L4_SRC_MASK | I40E_L4_DST_MASK); | |
5812 | ||
5813 | /* Reprogram the default input set for Other/IPv4 */ | |
5814 | i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_OTHER, | |
5815 | I40E_L3_SRC_MASK | I40E_L3_DST_MASK); | |
17a73f6b JG |
5816 | } |
5817 | ||
41c445ff JB |
5818 | /** |
5819 | * i40e_close - Disables a network interface | |
5820 | * @netdev: network interface device structure | |
5821 | * | |
5822 | * The close entry point is called when an interface is de-activated | |
5823 | * by the OS. The hardware is still under the driver's control, but | |
5824 | * this netdev interface is disabled. | |
5825 | * | |
5826 | * Returns 0, this is not allowed to fail | |
5827 | **/ | |
38e00438 | 5828 | int i40e_close(struct net_device *netdev) |
41c445ff JB |
5829 | { |
5830 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
5831 | struct i40e_vsi *vsi = np->vsi; | |
5832 | ||
90ef8d47 | 5833 | i40e_vsi_close(vsi); |
41c445ff JB |
5834 | |
5835 | return 0; | |
5836 | } | |
5837 | ||
5838 | /** | |
5839 | * i40e_do_reset - Start a PF or Core Reset sequence | |
5840 | * @pf: board private structure | |
5841 | * @reset_flags: which reset is requested | |
373149fc MS |
5842 | * @lock_acquired: indicates whether or not the lock has been acquired |
5843 | * before this function was called. | |
41c445ff JB |
5844 | * |
5845 | * The essential difference in resets is that the PF Reset | |
5846 | * doesn't clear the packet buffers, doesn't reset the PE | |
5847 | * firmware, and doesn't bother the other PFs on the chip. | |
5848 | **/ | |
373149fc | 5849 | void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired) |
41c445ff JB |
5850 | { |
5851 | u32 val; | |
5852 | ||
5853 | WARN_ON(in_interrupt()); | |
5854 | ||
263fc48f | 5855 | |
41c445ff | 5856 | /* do the biggest reset indicated */ |
41a1d04b | 5857 | if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) { |
41c445ff JB |
5858 | |
5859 | /* Request a Global Reset | |
5860 | * | |
5861 | * This will start the chip's countdown to the actual full | |
5862 | * chip reset event, and a warning interrupt to be sent | |
5863 | * to all PFs, including the requestor. Our handler | |
5864 | * for the warning interrupt will deal with the shutdown | |
5865 | * and recovery of the switch setup. | |
5866 | */ | |
69bfb110 | 5867 | dev_dbg(&pf->pdev->dev, "GlobalR requested\n"); |
41c445ff JB |
5868 | val = rd32(&pf->hw, I40E_GLGEN_RTRIG); |
5869 | val |= I40E_GLGEN_RTRIG_GLOBR_MASK; | |
5870 | wr32(&pf->hw, I40E_GLGEN_RTRIG, val); | |
5871 | ||
41a1d04b | 5872 | } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) { |
41c445ff JB |
5873 | |
5874 | /* Request a Core Reset | |
5875 | * | |
5876 | * Same as Global Reset, except does *not* include the MAC/PHY | |
5877 | */ | |
69bfb110 | 5878 | dev_dbg(&pf->pdev->dev, "CoreR requested\n"); |
41c445ff JB |
5879 | val = rd32(&pf->hw, I40E_GLGEN_RTRIG); |
5880 | val |= I40E_GLGEN_RTRIG_CORER_MASK; | |
5881 | wr32(&pf->hw, I40E_GLGEN_RTRIG, val); | |
5882 | i40e_flush(&pf->hw); | |
5883 | ||
41a1d04b | 5884 | } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) { |
41c445ff JB |
5885 | |
5886 | /* Request a PF Reset | |
5887 | * | |
5888 | * Resets only the PF-specific registers | |
5889 | * | |
5890 | * This goes directly to the tear-down and rebuild of | |
5891 | * the switch, since we need to do all the recovery as | |
5892 | * for the Core Reset. | |
5893 | */ | |
69bfb110 | 5894 | dev_dbg(&pf->pdev->dev, "PFR requested\n"); |
373149fc | 5895 | i40e_handle_reset_warning(pf, lock_acquired); |
41c445ff | 5896 | |
41a1d04b | 5897 | } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) { |
41c445ff JB |
5898 | int v; |
5899 | ||
5900 | /* Find the VSI(s) that requested a re-init */ | |
5901 | dev_info(&pf->pdev->dev, | |
5902 | "VSI reinit requested\n"); | |
505682cd | 5903 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff | 5904 | struct i40e_vsi *vsi = pf->vsi[v]; |
6995b36c | 5905 | |
41c445ff | 5906 | if (vsi != NULL && |
d19cb64b | 5907 | test_and_clear_bit(__I40E_VSI_REINIT_REQUESTED, |
0da36b97 | 5908 | vsi->state)) |
41c445ff | 5909 | i40e_vsi_reinit_locked(pf->vsi[v]); |
41c445ff | 5910 | } |
41a1d04b | 5911 | } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) { |
b5d06f05 NP |
5912 | int v; |
5913 | ||
5914 | /* Find the VSI(s) that needs to be brought down */ | |
5915 | dev_info(&pf->pdev->dev, "VSI down requested\n"); | |
5916 | for (v = 0; v < pf->num_alloc_vsi; v++) { | |
5917 | struct i40e_vsi *vsi = pf->vsi[v]; | |
6995b36c | 5918 | |
b5d06f05 | 5919 | if (vsi != NULL && |
d19cb64b | 5920 | test_and_clear_bit(__I40E_VSI_DOWN_REQUESTED, |
0da36b97 JK |
5921 | vsi->state)) { |
5922 | set_bit(__I40E_VSI_DOWN, vsi->state); | |
b5d06f05 | 5923 | i40e_down(vsi); |
b5d06f05 NP |
5924 | } |
5925 | } | |
41c445ff JB |
5926 | } else { |
5927 | dev_info(&pf->pdev->dev, | |
5928 | "bad reset request 0x%08x\n", reset_flags); | |
41c445ff JB |
5929 | } |
5930 | } | |
5931 | ||
4e3b35b0 NP |
5932 | #ifdef CONFIG_I40E_DCB |
5933 | /** | |
5934 | * i40e_dcb_need_reconfig - Check if DCB needs reconfig | |
5935 | * @pf: board private structure | |
5936 | * @old_cfg: current DCB config | |
5937 | * @new_cfg: new DCB config | |
5938 | **/ | |
5939 | bool i40e_dcb_need_reconfig(struct i40e_pf *pf, | |
5940 | struct i40e_dcbx_config *old_cfg, | |
5941 | struct i40e_dcbx_config *new_cfg) | |
5942 | { | |
5943 | bool need_reconfig = false; | |
5944 | ||
5945 | /* Check if ETS configuration has changed */ | |
5946 | if (memcmp(&new_cfg->etscfg, | |
5947 | &old_cfg->etscfg, | |
5948 | sizeof(new_cfg->etscfg))) { | |
5949 | /* If Priority Table has changed reconfig is needed */ | |
5950 | if (memcmp(&new_cfg->etscfg.prioritytable, | |
5951 | &old_cfg->etscfg.prioritytable, | |
5952 | sizeof(new_cfg->etscfg.prioritytable))) { | |
5953 | need_reconfig = true; | |
69bfb110 | 5954 | dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n"); |
4e3b35b0 NP |
5955 | } |
5956 | ||
5957 | if (memcmp(&new_cfg->etscfg.tcbwtable, | |
5958 | &old_cfg->etscfg.tcbwtable, | |
5959 | sizeof(new_cfg->etscfg.tcbwtable))) | |
69bfb110 | 5960 | dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n"); |
4e3b35b0 NP |
5961 | |
5962 | if (memcmp(&new_cfg->etscfg.tsatable, | |
5963 | &old_cfg->etscfg.tsatable, | |
5964 | sizeof(new_cfg->etscfg.tsatable))) | |
69bfb110 | 5965 | dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n"); |
4e3b35b0 NP |
5966 | } |
5967 | ||
5968 | /* Check if PFC configuration has changed */ | |
5969 | if (memcmp(&new_cfg->pfc, | |
5970 | &old_cfg->pfc, | |
5971 | sizeof(new_cfg->pfc))) { | |
5972 | need_reconfig = true; | |
69bfb110 | 5973 | dev_dbg(&pf->pdev->dev, "PFC config change detected.\n"); |
4e3b35b0 NP |
5974 | } |
5975 | ||
5976 | /* Check if APP Table has changed */ | |
5977 | if (memcmp(&new_cfg->app, | |
5978 | &old_cfg->app, | |
3d9667a9 | 5979 | sizeof(new_cfg->app))) { |
4e3b35b0 | 5980 | need_reconfig = true; |
69bfb110 | 5981 | dev_dbg(&pf->pdev->dev, "APP Table change detected.\n"); |
3d9667a9 | 5982 | } |
4e3b35b0 | 5983 | |
fb43201f | 5984 | dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig); |
4e3b35b0 NP |
5985 | return need_reconfig; |
5986 | } | |
5987 | ||
5988 | /** | |
5989 | * i40e_handle_lldp_event - Handle LLDP Change MIB event | |
5990 | * @pf: board private structure | |
5991 | * @e: event info posted on ARQ | |
5992 | **/ | |
5993 | static int i40e_handle_lldp_event(struct i40e_pf *pf, | |
5994 | struct i40e_arq_event_info *e) | |
5995 | { | |
5996 | struct i40e_aqc_lldp_get_mib *mib = | |
5997 | (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw; | |
5998 | struct i40e_hw *hw = &pf->hw; | |
4e3b35b0 NP |
5999 | struct i40e_dcbx_config tmp_dcbx_cfg; |
6000 | bool need_reconfig = false; | |
6001 | int ret = 0; | |
6002 | u8 type; | |
6003 | ||
4d9b6043 | 6004 | /* Not DCB capable or capability disabled */ |
ea6acb7e | 6005 | if (!(pf->flags & I40E_FLAG_DCB_CAPABLE)) |
4d9b6043 NP |
6006 | return ret; |
6007 | ||
4e3b35b0 NP |
6008 | /* Ignore if event is not for Nearest Bridge */ |
6009 | type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) | |
6010 | & I40E_AQ_LLDP_BRIDGE_TYPE_MASK); | |
fb43201f | 6011 | dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type); |
4e3b35b0 NP |
6012 | if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE) |
6013 | return ret; | |
6014 | ||
6015 | /* Check MIB Type and return if event for Remote MIB update */ | |
6016 | type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK; | |
9fa61dd2 | 6017 | dev_dbg(&pf->pdev->dev, |
fb43201f | 6018 | "LLDP event mib type %s\n", type ? "remote" : "local"); |
4e3b35b0 NP |
6019 | if (type == I40E_AQ_LLDP_MIB_REMOTE) { |
6020 | /* Update the remote cached instance and return */ | |
6021 | ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE, | |
6022 | I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE, | |
6023 | &hw->remote_dcbx_config); | |
6024 | goto exit; | |
6025 | } | |
6026 | ||
9fa61dd2 | 6027 | /* Store the old configuration */ |
1a2f6248 | 6028 | tmp_dcbx_cfg = hw->local_dcbx_config; |
9fa61dd2 | 6029 | |
750fcbcf NP |
6030 | /* Reset the old DCBx configuration data */ |
6031 | memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config)); | |
9fa61dd2 NP |
6032 | /* Get updated DCBX data from firmware */ |
6033 | ret = i40e_get_dcb_config(&pf->hw); | |
4e3b35b0 | 6034 | if (ret) { |
f1c7e72e SN |
6035 | dev_info(&pf->pdev->dev, |
6036 | "Failed querying DCB configuration data from firmware, err %s aq_err %s\n", | |
6037 | i40e_stat_str(&pf->hw, ret), | |
6038 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
4e3b35b0 NP |
6039 | goto exit; |
6040 | } | |
6041 | ||
6042 | /* No change detected in DCBX configs */ | |
750fcbcf NP |
6043 | if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config, |
6044 | sizeof(tmp_dcbx_cfg))) { | |
69bfb110 | 6045 | dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n"); |
4e3b35b0 NP |
6046 | goto exit; |
6047 | } | |
6048 | ||
750fcbcf NP |
6049 | need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg, |
6050 | &hw->local_dcbx_config); | |
4e3b35b0 | 6051 | |
750fcbcf | 6052 | i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config); |
4e3b35b0 NP |
6053 | |
6054 | if (!need_reconfig) | |
6055 | goto exit; | |
6056 | ||
4d9b6043 | 6057 | /* Enable DCB tagging only when more than one TC */ |
750fcbcf | 6058 | if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1) |
4d9b6043 NP |
6059 | pf->flags |= I40E_FLAG_DCB_ENABLED; |
6060 | else | |
6061 | pf->flags &= ~I40E_FLAG_DCB_ENABLED; | |
6062 | ||
0da36b97 | 6063 | set_bit(__I40E_PORT_SUSPENDED, pf->state); |
4e3b35b0 NP |
6064 | /* Reconfiguration needed quiesce all VSIs */ |
6065 | i40e_pf_quiesce_all_vsi(pf); | |
6066 | ||
6067 | /* Changes in configuration update VEB/VSI */ | |
6068 | i40e_dcb_reconfigure(pf); | |
6069 | ||
2fd75f31 NP |
6070 | ret = i40e_resume_port_tx(pf); |
6071 | ||
0da36b97 | 6072 | clear_bit(__I40E_PORT_SUSPENDED, pf->state); |
2fd75f31 | 6073 | /* In case of error no point in resuming VSIs */ |
69129dc3 NP |
6074 | if (ret) |
6075 | goto exit; | |
6076 | ||
3fe06f41 NP |
6077 | /* Wait for the PF's queues to be disabled */ |
6078 | ret = i40e_pf_wait_queues_disabled(pf); | |
11e47708 PN |
6079 | if (ret) { |
6080 | /* Schedule PF reset to recover */ | |
0da36b97 | 6081 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
11e47708 PN |
6082 | i40e_service_event_schedule(pf); |
6083 | } else { | |
2fd75f31 | 6084 | i40e_pf_unquiesce_all_vsi(pf); |
0ef2d5af MW |
6085 | pf->flags |= (I40E_FLAG_SERVICE_CLIENT_REQUESTED | |
6086 | I40E_FLAG_CLIENT_L2_CHANGE); | |
11e47708 PN |
6087 | } |
6088 | ||
4e3b35b0 NP |
6089 | exit: |
6090 | return ret; | |
6091 | } | |
6092 | #endif /* CONFIG_I40E_DCB */ | |
6093 | ||
23326186 ASJ |
6094 | /** |
6095 | * i40e_do_reset_safe - Protected reset path for userland calls. | |
6096 | * @pf: board private structure | |
6097 | * @reset_flags: which reset is requested | |
6098 | * | |
6099 | **/ | |
6100 | void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags) | |
6101 | { | |
6102 | rtnl_lock(); | |
373149fc | 6103 | i40e_do_reset(pf, reset_flags, true); |
23326186 ASJ |
6104 | rtnl_unlock(); |
6105 | } | |
6106 | ||
41c445ff JB |
6107 | /** |
6108 | * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event | |
6109 | * @pf: board private structure | |
6110 | * @e: event info posted on ARQ | |
6111 | * | |
6112 | * Handler for LAN Queue Overflow Event generated by the firmware for PF | |
6113 | * and VF queues | |
6114 | **/ | |
6115 | static void i40e_handle_lan_overflow_event(struct i40e_pf *pf, | |
6116 | struct i40e_arq_event_info *e) | |
6117 | { | |
6118 | struct i40e_aqc_lan_overflow *data = | |
6119 | (struct i40e_aqc_lan_overflow *)&e->desc.params.raw; | |
6120 | u32 queue = le32_to_cpu(data->prtdcb_rupto); | |
6121 | u32 qtx_ctl = le32_to_cpu(data->otx_ctl); | |
6122 | struct i40e_hw *hw = &pf->hw; | |
6123 | struct i40e_vf *vf; | |
6124 | u16 vf_id; | |
6125 | ||
69bfb110 JB |
6126 | dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n", |
6127 | queue, qtx_ctl); | |
41c445ff JB |
6128 | |
6129 | /* Queue belongs to VF, find the VF and issue VF reset */ | |
6130 | if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK) | |
6131 | >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) { | |
6132 | vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK) | |
6133 | >> I40E_QTX_CTL_VFVM_INDX_SHIFT); | |
6134 | vf_id -= hw->func_caps.vf_base_id; | |
6135 | vf = &pf->vf[vf_id]; | |
6136 | i40e_vc_notify_vf_reset(vf); | |
6137 | /* Allow VF to process pending reset notification */ | |
6138 | msleep(20); | |
6139 | i40e_reset_vf(vf, false); | |
6140 | } | |
6141 | } | |
6142 | ||
55a5e60b | 6143 | /** |
12957388 ASJ |
6144 | * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters |
6145 | * @pf: board private structure | |
6146 | **/ | |
04294e38 | 6147 | u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf) |
12957388 | 6148 | { |
04294e38 | 6149 | u32 val, fcnt_prog; |
12957388 ASJ |
6150 | |
6151 | val = rd32(&pf->hw, I40E_PFQF_FDSTAT); | |
6152 | fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK); | |
6153 | return fcnt_prog; | |
6154 | } | |
6155 | ||
6156 | /** | |
04294e38 | 6157 | * i40e_get_current_fd_count - Get total FD filters programmed for this PF |
55a5e60b ASJ |
6158 | * @pf: board private structure |
6159 | **/ | |
04294e38 | 6160 | u32 i40e_get_current_fd_count(struct i40e_pf *pf) |
55a5e60b | 6161 | { |
04294e38 ASJ |
6162 | u32 val, fcnt_prog; |
6163 | ||
55a5e60b ASJ |
6164 | val = rd32(&pf->hw, I40E_PFQF_FDSTAT); |
6165 | fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) + | |
6166 | ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >> | |
6167 | I40E_PFQF_FDSTAT_BEST_CNT_SHIFT); | |
6168 | return fcnt_prog; | |
6169 | } | |
1e1be8f6 | 6170 | |
04294e38 ASJ |
6171 | /** |
6172 | * i40e_get_global_fd_count - Get total FD filters programmed on device | |
6173 | * @pf: board private structure | |
6174 | **/ | |
6175 | u32 i40e_get_global_fd_count(struct i40e_pf *pf) | |
6176 | { | |
6177 | u32 val, fcnt_prog; | |
6178 | ||
6179 | val = rd32(&pf->hw, I40E_GLQF_FDCNT_0); | |
6180 | fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) + | |
6181 | ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >> | |
6182 | I40E_GLQF_FDCNT_0_BESTCNT_SHIFT); | |
6183 | return fcnt_prog; | |
6184 | } | |
6185 | ||
55a5e60b ASJ |
6186 | /** |
6187 | * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled | |
6188 | * @pf: board private structure | |
6189 | **/ | |
6190 | void i40e_fdir_check_and_reenable(struct i40e_pf *pf) | |
6191 | { | |
3487b6c3 | 6192 | struct i40e_fdir_filter *filter; |
55a5e60b | 6193 | u32 fcnt_prog, fcnt_avail; |
3487b6c3 | 6194 | struct hlist_node *node; |
55a5e60b | 6195 | |
0da36b97 | 6196 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) |
1e1be8f6 ASJ |
6197 | return; |
6198 | ||
47994c11 | 6199 | /* Check if we have enough room to re-enable FDir SB capability. */ |
04294e38 | 6200 | fcnt_prog = i40e_get_global_fd_count(pf); |
12957388 | 6201 | fcnt_avail = pf->fdir_pf_filter_count; |
1e1be8f6 ASJ |
6202 | if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) || |
6203 | (pf->fd_add_err == 0) || | |
6204 | (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) { | |
47994c11 JK |
6205 | if (pf->flags & I40E_FLAG_FD_SB_AUTO_DISABLED) { |
6206 | pf->flags &= ~I40E_FLAG_FD_SB_AUTO_DISABLED; | |
6207 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && | |
6208 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
2e4875e3 | 6209 | dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n"); |
55a5e60b ASJ |
6210 | } |
6211 | } | |
a3417d28 | 6212 | |
47994c11 JK |
6213 | /* We should wait for even more space before re-enabling ATR. |
6214 | * Additionally, we cannot enable ATR as long as we still have TCP SB | |
6215 | * rules active. | |
a3417d28 | 6216 | */ |
47994c11 JK |
6217 | if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) && |
6218 | (pf->fd_tcp4_filter_cnt == 0)) { | |
6219 | if (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED) { | |
6220 | pf->flags &= ~I40E_FLAG_FD_ATR_AUTO_DISABLED; | |
6221 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && | |
6222 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
a3417d28 | 6223 | dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table and there are no conflicting ntuple rules\n"); |
55a5e60b ASJ |
6224 | } |
6225 | } | |
3487b6c3 CW |
6226 | |
6227 | /* if hw had a problem adding a filter, delete it */ | |
6228 | if (pf->fd_inv > 0) { | |
6229 | hlist_for_each_entry_safe(filter, node, | |
6230 | &pf->fdir_filter_list, fdir_node) { | |
6231 | if (filter->fd_id == pf->fd_inv) { | |
6232 | hlist_del(&filter->fdir_node); | |
6233 | kfree(filter); | |
6234 | pf->fdir_pf_active_filters--; | |
6235 | } | |
6236 | } | |
6237 | } | |
55a5e60b ASJ |
6238 | } |
6239 | ||
1e1be8f6 | 6240 | #define I40E_MIN_FD_FLUSH_INTERVAL 10 |
04294e38 | 6241 | #define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30 |
1e1be8f6 ASJ |
6242 | /** |
6243 | * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB | |
6244 | * @pf: board private structure | |
6245 | **/ | |
6246 | static void i40e_fdir_flush_and_replay(struct i40e_pf *pf) | |
6247 | { | |
04294e38 | 6248 | unsigned long min_flush_time; |
1e1be8f6 | 6249 | int flush_wait_retry = 50; |
04294e38 ASJ |
6250 | bool disable_atr = false; |
6251 | int fd_room; | |
1e1be8f6 ASJ |
6252 | int reg; |
6253 | ||
a5fdaf34 JB |
6254 | if (!time_after(jiffies, pf->fd_flush_timestamp + |
6255 | (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) | |
6256 | return; | |
04294e38 | 6257 | |
a5fdaf34 JB |
6258 | /* If the flush is happening too quick and we have mostly SB rules we |
6259 | * should not re-enable ATR for some time. | |
6260 | */ | |
6261 | min_flush_time = pf->fd_flush_timestamp + | |
6262 | (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ); | |
6263 | fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters; | |
6264 | ||
6265 | if (!(time_after(jiffies, min_flush_time)) && | |
6266 | (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) { | |
6267 | if (I40E_DEBUG_FD & pf->hw.debug_mask) | |
6268 | dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n"); | |
6269 | disable_atr = true; | |
6270 | } | |
6271 | ||
6272 | pf->fd_flush_timestamp = jiffies; | |
47994c11 | 6273 | pf->flags |= I40E_FLAG_FD_ATR_AUTO_DISABLED; |
a5fdaf34 JB |
6274 | /* flush all filters */ |
6275 | wr32(&pf->hw, I40E_PFQF_CTL_1, | |
6276 | I40E_PFQF_CTL_1_CLEARFDTABLE_MASK); | |
6277 | i40e_flush(&pf->hw); | |
6278 | pf->fd_flush_cnt++; | |
6279 | pf->fd_add_err = 0; | |
6280 | do { | |
6281 | /* Check FD flush status every 5-6msec */ | |
6282 | usleep_range(5000, 6000); | |
6283 | reg = rd32(&pf->hw, I40E_PFQF_CTL_1); | |
6284 | if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK)) | |
6285 | break; | |
6286 | } while (flush_wait_retry--); | |
6287 | if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) { | |
6288 | dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n"); | |
6289 | } else { | |
6290 | /* replay sideband filters */ | |
6291 | i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]); | |
097dbf52 | 6292 | if (!disable_atr && !pf->fd_tcp4_filter_cnt) |
47994c11 | 6293 | pf->flags &= ~I40E_FLAG_FD_ATR_AUTO_DISABLED; |
0da36b97 | 6294 | clear_bit(__I40E_FD_FLUSH_REQUESTED, pf->state); |
a5fdaf34 JB |
6295 | if (I40E_DEBUG_FD & pf->hw.debug_mask) |
6296 | dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n"); | |
1e1be8f6 ASJ |
6297 | } |
6298 | } | |
6299 | ||
6300 | /** | |
6301 | * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed | |
6302 | * @pf: board private structure | |
6303 | **/ | |
04294e38 | 6304 | u32 i40e_get_current_atr_cnt(struct i40e_pf *pf) |
1e1be8f6 ASJ |
6305 | { |
6306 | return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters; | |
6307 | } | |
6308 | ||
6309 | /* We can see up to 256 filter programming desc in transit if the filters are | |
6310 | * being applied really fast; before we see the first | |
6311 | * filter miss error on Rx queue 0. Accumulating enough error messages before | |
6312 | * reacting will make sure we don't cause flush too often. | |
6313 | */ | |
6314 | #define I40E_MAX_FD_PROGRAM_ERROR 256 | |
6315 | ||
41c445ff JB |
6316 | /** |
6317 | * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table | |
6318 | * @pf: board private structure | |
6319 | **/ | |
6320 | static void i40e_fdir_reinit_subtask(struct i40e_pf *pf) | |
6321 | { | |
41c445ff | 6322 | |
41c445ff | 6323 | /* if interface is down do nothing */ |
9e6c9c0f | 6324 | if (test_bit(__I40E_DOWN, pf->state)) |
41c445ff | 6325 | return; |
1e1be8f6 | 6326 | |
0da36b97 | 6327 | if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state)) |
1e1be8f6 ASJ |
6328 | i40e_fdir_flush_and_replay(pf); |
6329 | ||
55a5e60b ASJ |
6330 | i40e_fdir_check_and_reenable(pf); |
6331 | ||
41c445ff JB |
6332 | } |
6333 | ||
6334 | /** | |
6335 | * i40e_vsi_link_event - notify VSI of a link event | |
6336 | * @vsi: vsi to be notified | |
6337 | * @link_up: link up or down | |
6338 | **/ | |
6339 | static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up) | |
6340 | { | |
0da36b97 | 6341 | if (!vsi || test_bit(__I40E_VSI_DOWN, vsi->state)) |
41c445ff JB |
6342 | return; |
6343 | ||
6344 | switch (vsi->type) { | |
6345 | case I40E_VSI_MAIN: | |
6346 | if (!vsi->netdev || !vsi->netdev_registered) | |
6347 | break; | |
6348 | ||
6349 | if (link_up) { | |
6350 | netif_carrier_on(vsi->netdev); | |
6351 | netif_tx_wake_all_queues(vsi->netdev); | |
6352 | } else { | |
6353 | netif_carrier_off(vsi->netdev); | |
6354 | netif_tx_stop_all_queues(vsi->netdev); | |
6355 | } | |
6356 | break; | |
6357 | ||
6358 | case I40E_VSI_SRIOV: | |
41c445ff JB |
6359 | case I40E_VSI_VMDQ2: |
6360 | case I40E_VSI_CTRL: | |
e3219ce6 | 6361 | case I40E_VSI_IWARP: |
41c445ff JB |
6362 | case I40E_VSI_MIRROR: |
6363 | default: | |
6364 | /* there is no notification for other VSIs */ | |
6365 | break; | |
6366 | } | |
6367 | } | |
6368 | ||
6369 | /** | |
6370 | * i40e_veb_link_event - notify elements on the veb of a link event | |
6371 | * @veb: veb to be notified | |
6372 | * @link_up: link up or down | |
6373 | **/ | |
6374 | static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up) | |
6375 | { | |
6376 | struct i40e_pf *pf; | |
6377 | int i; | |
6378 | ||
6379 | if (!veb || !veb->pf) | |
6380 | return; | |
6381 | pf = veb->pf; | |
6382 | ||
6383 | /* depth first... */ | |
6384 | for (i = 0; i < I40E_MAX_VEB; i++) | |
6385 | if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid)) | |
6386 | i40e_veb_link_event(pf->veb[i], link_up); | |
6387 | ||
6388 | /* ... now the local VSIs */ | |
505682cd | 6389 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
6390 | if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid)) |
6391 | i40e_vsi_link_event(pf->vsi[i], link_up); | |
6392 | } | |
6393 | ||
6394 | /** | |
6395 | * i40e_link_event - Update netif_carrier status | |
6396 | * @pf: board private structure | |
6397 | **/ | |
6398 | static void i40e_link_event(struct i40e_pf *pf) | |
6399 | { | |
320684cd | 6400 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
fef59ddf | 6401 | u8 new_link_speed, old_link_speed; |
a72a5abc JB |
6402 | i40e_status status; |
6403 | bool new_link, old_link; | |
41c445ff | 6404 | |
1f9610e4 CS |
6405 | /* save off old link status information */ |
6406 | pf->hw.phy.link_info_old = pf->hw.phy.link_info; | |
6407 | ||
1e701e09 JB |
6408 | /* set this to force the get_link_status call to refresh state */ |
6409 | pf->hw.phy.get_link_info = true; | |
6410 | ||
41c445ff | 6411 | old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP); |
a72a5abc JB |
6412 | |
6413 | status = i40e_get_link_status(&pf->hw, &new_link); | |
ae136708 HR |
6414 | |
6415 | /* On success, disable temp link polling */ | |
6416 | if (status == I40E_SUCCESS) { | |
6417 | if (pf->flags & I40E_FLAG_TEMP_LINK_POLLING) | |
6418 | pf->flags &= ~I40E_FLAG_TEMP_LINK_POLLING; | |
6419 | } else { | |
6420 | /* Enable link polling temporarily until i40e_get_link_status | |
6421 | * returns I40E_SUCCESS | |
6422 | */ | |
6423 | pf->flags |= I40E_FLAG_TEMP_LINK_POLLING; | |
a72a5abc JB |
6424 | dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n", |
6425 | status); | |
6426 | return; | |
6427 | } | |
6428 | ||
fef59ddf CS |
6429 | old_link_speed = pf->hw.phy.link_info_old.link_speed; |
6430 | new_link_speed = pf->hw.phy.link_info.link_speed; | |
41c445ff | 6431 | |
1e701e09 | 6432 | if (new_link == old_link && |
fef59ddf | 6433 | new_link_speed == old_link_speed && |
0da36b97 | 6434 | (test_bit(__I40E_VSI_DOWN, vsi->state) || |
320684cd | 6435 | new_link == netif_carrier_ok(vsi->netdev))) |
41c445ff | 6436 | return; |
320684cd | 6437 | |
9a03449d | 6438 | i40e_print_link_message(vsi, new_link); |
41c445ff JB |
6439 | |
6440 | /* Notify the base of the switch tree connected to | |
6441 | * the link. Floating VEBs are not notified. | |
6442 | */ | |
6443 | if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb]) | |
6444 | i40e_veb_link_event(pf->veb[pf->lan_veb], new_link); | |
6445 | else | |
320684cd | 6446 | i40e_vsi_link_event(vsi, new_link); |
41c445ff JB |
6447 | |
6448 | if (pf->vf) | |
6449 | i40e_vc_notify_link_state(pf); | |
beb0dff1 JK |
6450 | |
6451 | if (pf->flags & I40E_FLAG_PTP) | |
6452 | i40e_ptp_set_increment(pf); | |
41c445ff JB |
6453 | } |
6454 | ||
41c445ff | 6455 | /** |
21536717 | 6456 | * i40e_watchdog_subtask - periodic checks not using event driven response |
41c445ff JB |
6457 | * @pf: board private structure |
6458 | **/ | |
6459 | static void i40e_watchdog_subtask(struct i40e_pf *pf) | |
6460 | { | |
6461 | int i; | |
6462 | ||
6463 | /* if interface is down do nothing */ | |
9e6c9c0f | 6464 | if (test_bit(__I40E_DOWN, pf->state) || |
0da36b97 | 6465 | test_bit(__I40E_CONFIG_BUSY, pf->state)) |
41c445ff JB |
6466 | return; |
6467 | ||
21536717 SN |
6468 | /* make sure we don't do these things too often */ |
6469 | if (time_before(jiffies, (pf->service_timer_previous + | |
6470 | pf->service_timer_period))) | |
6471 | return; | |
6472 | pf->service_timer_previous = jiffies; | |
6473 | ||
ae136708 HR |
6474 | if ((pf->flags & I40E_FLAG_LINK_POLLING_ENABLED) || |
6475 | (pf->flags & I40E_FLAG_TEMP_LINK_POLLING)) | |
9ac77266 | 6476 | i40e_link_event(pf); |
21536717 | 6477 | |
41c445ff JB |
6478 | /* Update the stats for active netdevs so the network stack |
6479 | * can look at updated numbers whenever it cares to | |
6480 | */ | |
505682cd | 6481 | for (i = 0; i < pf->num_alloc_vsi; i++) |
41c445ff JB |
6482 | if (pf->vsi[i] && pf->vsi[i]->netdev) |
6483 | i40e_update_stats(pf->vsi[i]); | |
6484 | ||
d1a8d275 ASJ |
6485 | if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) { |
6486 | /* Update the stats for the active switching components */ | |
6487 | for (i = 0; i < I40E_MAX_VEB; i++) | |
6488 | if (pf->veb[i]) | |
6489 | i40e_update_veb_stats(pf->veb[i]); | |
6490 | } | |
beb0dff1 | 6491 | |
61189556 | 6492 | i40e_ptp_rx_hang(pf); |
0bc0706b | 6493 | i40e_ptp_tx_hang(pf); |
41c445ff JB |
6494 | } |
6495 | ||
6496 | /** | |
6497 | * i40e_reset_subtask - Set up for resetting the device and driver | |
6498 | * @pf: board private structure | |
6499 | **/ | |
6500 | static void i40e_reset_subtask(struct i40e_pf *pf) | |
6501 | { | |
6502 | u32 reset_flags = 0; | |
6503 | ||
0da36b97 | 6504 | if (test_bit(__I40E_REINIT_REQUESTED, pf->state)) { |
75f5cea9 | 6505 | reset_flags |= BIT(__I40E_REINIT_REQUESTED); |
0da36b97 | 6506 | clear_bit(__I40E_REINIT_REQUESTED, pf->state); |
41c445ff | 6507 | } |
0da36b97 | 6508 | if (test_bit(__I40E_PF_RESET_REQUESTED, pf->state)) { |
75f5cea9 | 6509 | reset_flags |= BIT(__I40E_PF_RESET_REQUESTED); |
0da36b97 | 6510 | clear_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
41c445ff | 6511 | } |
0da36b97 | 6512 | if (test_bit(__I40E_CORE_RESET_REQUESTED, pf->state)) { |
75f5cea9 | 6513 | reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED); |
0da36b97 | 6514 | clear_bit(__I40E_CORE_RESET_REQUESTED, pf->state); |
41c445ff | 6515 | } |
0da36b97 | 6516 | if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state)) { |
75f5cea9 | 6517 | reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED); |
0da36b97 | 6518 | clear_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state); |
41c445ff | 6519 | } |
9e6c9c0f MR |
6520 | if (test_bit(__I40E_DOWN_REQUESTED, pf->state)) { |
6521 | reset_flags |= BIT(__I40E_DOWN_REQUESTED); | |
6522 | clear_bit(__I40E_DOWN_REQUESTED, pf->state); | |
b5d06f05 | 6523 | } |
41c445ff JB |
6524 | |
6525 | /* If there's a recovery already waiting, it takes | |
6526 | * precedence before starting a new reset sequence. | |
6527 | */ | |
0da36b97 | 6528 | if (test_bit(__I40E_RESET_INTR_RECEIVED, pf->state)) { |
373149fc MS |
6529 | i40e_prep_for_reset(pf, false); |
6530 | i40e_reset(pf); | |
6531 | i40e_rebuild(pf, false, false); | |
41c445ff JB |
6532 | } |
6533 | ||
6534 | /* If we're already down or resetting, just bail */ | |
6535 | if (reset_flags && | |
9e6c9c0f | 6536 | !test_bit(__I40E_DOWN, pf->state) && |
0da36b97 | 6537 | !test_bit(__I40E_CONFIG_BUSY, pf->state)) { |
dfc4ff64 | 6538 | i40e_do_reset(pf, reset_flags, false); |
373149fc | 6539 | } |
41c445ff JB |
6540 | } |
6541 | ||
6542 | /** | |
6543 | * i40e_handle_link_event - Handle link event | |
6544 | * @pf: board private structure | |
6545 | * @e: event info posted on ARQ | |
6546 | **/ | |
6547 | static void i40e_handle_link_event(struct i40e_pf *pf, | |
6548 | struct i40e_arq_event_info *e) | |
6549 | { | |
41c445ff JB |
6550 | struct i40e_aqc_get_link_status *status = |
6551 | (struct i40e_aqc_get_link_status *)&e->desc.params.raw; | |
41c445ff | 6552 | |
1e701e09 JB |
6553 | /* Do a new status request to re-enable LSE reporting |
6554 | * and load new status information into the hw struct | |
6555 | * This completely ignores any state information | |
6556 | * in the ARQ event info, instead choosing to always | |
6557 | * issue the AQ update link status command. | |
6558 | */ | |
6559 | i40e_link_event(pf); | |
6560 | ||
7b592f61 CW |
6561 | /* check for unqualified module, if link is down */ |
6562 | if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) && | |
6563 | (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) && | |
6564 | (!(status->link_info & I40E_AQ_LINK_UP))) | |
6565 | dev_err(&pf->pdev->dev, | |
6566 | "The driver failed to link because an unqualified module was detected.\n"); | |
41c445ff JB |
6567 | } |
6568 | ||
6569 | /** | |
6570 | * i40e_clean_adminq_subtask - Clean the AdminQ rings | |
6571 | * @pf: board private structure | |
6572 | **/ | |
6573 | static void i40e_clean_adminq_subtask(struct i40e_pf *pf) | |
6574 | { | |
6575 | struct i40e_arq_event_info event; | |
6576 | struct i40e_hw *hw = &pf->hw; | |
6577 | u16 pending, i = 0; | |
6578 | i40e_status ret; | |
6579 | u16 opcode; | |
86df242b | 6580 | u32 oldval; |
41c445ff JB |
6581 | u32 val; |
6582 | ||
a316f651 | 6583 | /* Do not run clean AQ when PF reset fails */ |
0da36b97 | 6584 | if (test_bit(__I40E_RESET_FAILED, pf->state)) |
a316f651 ASJ |
6585 | return; |
6586 | ||
86df242b SN |
6587 | /* check for error indications */ |
6588 | val = rd32(&pf->hw, pf->hw.aq.arq.len); | |
6589 | oldval = val; | |
6590 | if (val & I40E_PF_ARQLEN_ARQVFE_MASK) { | |
75eb73c1 MW |
6591 | if (hw->debug_mask & I40E_DEBUG_AQ) |
6592 | dev_info(&pf->pdev->dev, "ARQ VF Error detected\n"); | |
86df242b SN |
6593 | val &= ~I40E_PF_ARQLEN_ARQVFE_MASK; |
6594 | } | |
6595 | if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) { | |
75eb73c1 MW |
6596 | if (hw->debug_mask & I40E_DEBUG_AQ) |
6597 | dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n"); | |
86df242b | 6598 | val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK; |
1d0a4ada | 6599 | pf->arq_overflows++; |
86df242b SN |
6600 | } |
6601 | if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) { | |
75eb73c1 MW |
6602 | if (hw->debug_mask & I40E_DEBUG_AQ) |
6603 | dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n"); | |
86df242b SN |
6604 | val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK; |
6605 | } | |
6606 | if (oldval != val) | |
6607 | wr32(&pf->hw, pf->hw.aq.arq.len, val); | |
6608 | ||
6609 | val = rd32(&pf->hw, pf->hw.aq.asq.len); | |
6610 | oldval = val; | |
6611 | if (val & I40E_PF_ATQLEN_ATQVFE_MASK) { | |
75eb73c1 MW |
6612 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
6613 | dev_info(&pf->pdev->dev, "ASQ VF Error detected\n"); | |
86df242b SN |
6614 | val &= ~I40E_PF_ATQLEN_ATQVFE_MASK; |
6615 | } | |
6616 | if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) { | |
75eb73c1 MW |
6617 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
6618 | dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n"); | |
86df242b SN |
6619 | val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK; |
6620 | } | |
6621 | if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) { | |
75eb73c1 MW |
6622 | if (pf->hw.debug_mask & I40E_DEBUG_AQ) |
6623 | dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n"); | |
86df242b SN |
6624 | val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK; |
6625 | } | |
6626 | if (oldval != val) | |
6627 | wr32(&pf->hw, pf->hw.aq.asq.len, val); | |
6628 | ||
1001dc37 MW |
6629 | event.buf_len = I40E_MAX_AQ_BUF_SIZE; |
6630 | event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL); | |
41c445ff JB |
6631 | if (!event.msg_buf) |
6632 | return; | |
6633 | ||
6634 | do { | |
6635 | ret = i40e_clean_arq_element(hw, &event, &pending); | |
56497978 | 6636 | if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK) |
41c445ff | 6637 | break; |
56497978 | 6638 | else if (ret) { |
41c445ff JB |
6639 | dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret); |
6640 | break; | |
6641 | } | |
6642 | ||
6643 | opcode = le16_to_cpu(event.desc.opcode); | |
6644 | switch (opcode) { | |
6645 | ||
6646 | case i40e_aqc_opc_get_link_status: | |
6647 | i40e_handle_link_event(pf, &event); | |
6648 | break; | |
6649 | case i40e_aqc_opc_send_msg_to_pf: | |
6650 | ret = i40e_vc_process_vf_msg(pf, | |
6651 | le16_to_cpu(event.desc.retval), | |
6652 | le32_to_cpu(event.desc.cookie_high), | |
6653 | le32_to_cpu(event.desc.cookie_low), | |
6654 | event.msg_buf, | |
1001dc37 | 6655 | event.msg_len); |
41c445ff JB |
6656 | break; |
6657 | case i40e_aqc_opc_lldp_update_mib: | |
69bfb110 | 6658 | dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n"); |
4e3b35b0 NP |
6659 | #ifdef CONFIG_I40E_DCB |
6660 | rtnl_lock(); | |
6661 | ret = i40e_handle_lldp_event(pf, &event); | |
6662 | rtnl_unlock(); | |
6663 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
6664 | break; |
6665 | case i40e_aqc_opc_event_lan_overflow: | |
69bfb110 | 6666 | dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n"); |
41c445ff JB |
6667 | i40e_handle_lan_overflow_event(pf, &event); |
6668 | break; | |
0467bc91 SN |
6669 | case i40e_aqc_opc_send_msg_to_peer: |
6670 | dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n"); | |
6671 | break; | |
91a0f930 SN |
6672 | case i40e_aqc_opc_nvm_erase: |
6673 | case i40e_aqc_opc_nvm_update: | |
00ada50d | 6674 | case i40e_aqc_opc_oem_post_update: |
6e93d0c9 SN |
6675 | i40e_debug(&pf->hw, I40E_DEBUG_NVM, |
6676 | "ARQ NVM operation 0x%04x completed\n", | |
6677 | opcode); | |
91a0f930 | 6678 | break; |
41c445ff JB |
6679 | default: |
6680 | dev_info(&pf->pdev->dev, | |
56e5ca68 | 6681 | "ARQ: Unknown event 0x%04x ignored\n", |
0467bc91 | 6682 | opcode); |
41c445ff JB |
6683 | break; |
6684 | } | |
1fca3265 CB |
6685 | } while (i++ < pf->adminq_work_limit); |
6686 | ||
6687 | if (i < pf->adminq_work_limit) | |
0da36b97 | 6688 | clear_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state); |
41c445ff | 6689 | |
41c445ff JB |
6690 | /* re-enable Admin queue interrupt cause */ |
6691 | val = rd32(hw, I40E_PFINT_ICR0_ENA); | |
6692 | val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK; | |
6693 | wr32(hw, I40E_PFINT_ICR0_ENA, val); | |
6694 | i40e_flush(hw); | |
6695 | ||
6696 | kfree(event.msg_buf); | |
6697 | } | |
6698 | ||
4eb3f768 SN |
6699 | /** |
6700 | * i40e_verify_eeprom - make sure eeprom is good to use | |
6701 | * @pf: board private structure | |
6702 | **/ | |
6703 | static void i40e_verify_eeprom(struct i40e_pf *pf) | |
6704 | { | |
6705 | int err; | |
6706 | ||
6707 | err = i40e_diag_eeprom_test(&pf->hw); | |
6708 | if (err) { | |
6709 | /* retry in case of garbage read */ | |
6710 | err = i40e_diag_eeprom_test(&pf->hw); | |
6711 | if (err) { | |
6712 | dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n", | |
6713 | err); | |
0da36b97 | 6714 | set_bit(__I40E_BAD_EEPROM, pf->state); |
4eb3f768 SN |
6715 | } |
6716 | } | |
6717 | ||
0da36b97 | 6718 | if (!err && test_bit(__I40E_BAD_EEPROM, pf->state)) { |
4eb3f768 | 6719 | dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n"); |
0da36b97 | 6720 | clear_bit(__I40E_BAD_EEPROM, pf->state); |
4eb3f768 SN |
6721 | } |
6722 | } | |
6723 | ||
386a0afa AA |
6724 | /** |
6725 | * i40e_enable_pf_switch_lb | |
b40c82e6 | 6726 | * @pf: pointer to the PF structure |
386a0afa AA |
6727 | * |
6728 | * enable switch loop back or die - no point in a return value | |
6729 | **/ | |
6730 | static void i40e_enable_pf_switch_lb(struct i40e_pf *pf) | |
6731 | { | |
6732 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
6733 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 6734 | int ret; |
386a0afa AA |
6735 | |
6736 | ctxt.seid = pf->main_vsi_seid; | |
6737 | ctxt.pf_num = pf->hw.pf_id; | |
6738 | ctxt.vf_num = 0; | |
f1c7e72e SN |
6739 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); |
6740 | if (ret) { | |
386a0afa | 6741 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6742 | "couldn't get PF vsi config, err %s aq_err %s\n", |
6743 | i40e_stat_str(&pf->hw, ret), | |
6744 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
6745 | return; |
6746 | } | |
6747 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
6748 | ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
6749 | ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
6750 | ||
f1c7e72e SN |
6751 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
6752 | if (ret) { | |
386a0afa | 6753 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6754 | "update vsi switch failed, err %s aq_err %s\n", |
6755 | i40e_stat_str(&pf->hw, ret), | |
6756 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
6757 | } |
6758 | } | |
6759 | ||
6760 | /** | |
6761 | * i40e_disable_pf_switch_lb | |
b40c82e6 | 6762 | * @pf: pointer to the PF structure |
386a0afa AA |
6763 | * |
6764 | * disable switch loop back or die - no point in a return value | |
6765 | **/ | |
6766 | static void i40e_disable_pf_switch_lb(struct i40e_pf *pf) | |
6767 | { | |
6768 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
6769 | struct i40e_vsi_context ctxt; | |
f1c7e72e | 6770 | int ret; |
386a0afa AA |
6771 | |
6772 | ctxt.seid = pf->main_vsi_seid; | |
6773 | ctxt.pf_num = pf->hw.pf_id; | |
6774 | ctxt.vf_num = 0; | |
f1c7e72e SN |
6775 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); |
6776 | if (ret) { | |
386a0afa | 6777 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6778 | "couldn't get PF vsi config, err %s aq_err %s\n", |
6779 | i40e_stat_str(&pf->hw, ret), | |
6780 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
6781 | return; |
6782 | } | |
6783 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
6784 | ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
6785 | ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
6786 | ||
f1c7e72e SN |
6787 | ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL); |
6788 | if (ret) { | |
386a0afa | 6789 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
6790 | "update vsi switch failed, err %s aq_err %s\n", |
6791 | i40e_stat_str(&pf->hw, ret), | |
6792 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
386a0afa AA |
6793 | } |
6794 | } | |
6795 | ||
51616018 NP |
6796 | /** |
6797 | * i40e_config_bridge_mode - Configure the HW bridge mode | |
6798 | * @veb: pointer to the bridge instance | |
6799 | * | |
6800 | * Configure the loop back mode for the LAN VSI that is downlink to the | |
6801 | * specified HW bridge instance. It is expected this function is called | |
6802 | * when a new HW bridge is instantiated. | |
6803 | **/ | |
6804 | static void i40e_config_bridge_mode(struct i40e_veb *veb) | |
6805 | { | |
6806 | struct i40e_pf *pf = veb->pf; | |
6807 | ||
6dec1017 SN |
6808 | if (pf->hw.debug_mask & I40E_DEBUG_LAN) |
6809 | dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n", | |
6810 | veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB"); | |
51616018 NP |
6811 | if (veb->bridge_mode & BRIDGE_MODE_VEPA) |
6812 | i40e_disable_pf_switch_lb(pf); | |
6813 | else | |
6814 | i40e_enable_pf_switch_lb(pf); | |
6815 | } | |
6816 | ||
41c445ff JB |
6817 | /** |
6818 | * i40e_reconstitute_veb - rebuild the VEB and anything connected to it | |
6819 | * @veb: pointer to the VEB instance | |
6820 | * | |
6821 | * This is a recursive function that first builds the attached VSIs then | |
6822 | * recurses in to build the next layer of VEB. We track the connections | |
6823 | * through our own index numbers because the seid's from the HW could | |
6824 | * change across the reset. | |
6825 | **/ | |
6826 | static int i40e_reconstitute_veb(struct i40e_veb *veb) | |
6827 | { | |
6828 | struct i40e_vsi *ctl_vsi = NULL; | |
6829 | struct i40e_pf *pf = veb->pf; | |
6830 | int v, veb_idx; | |
6831 | int ret; | |
6832 | ||
6833 | /* build VSI that owns this VEB, temporarily attached to base VEB */ | |
505682cd | 6834 | for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) { |
41c445ff JB |
6835 | if (pf->vsi[v] && |
6836 | pf->vsi[v]->veb_idx == veb->idx && | |
6837 | pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) { | |
6838 | ctl_vsi = pf->vsi[v]; | |
6839 | break; | |
6840 | } | |
6841 | } | |
6842 | if (!ctl_vsi) { | |
6843 | dev_info(&pf->pdev->dev, | |
6844 | "missing owner VSI for veb_idx %d\n", veb->idx); | |
6845 | ret = -ENOENT; | |
6846 | goto end_reconstitute; | |
6847 | } | |
6848 | if (ctl_vsi != pf->vsi[pf->lan_vsi]) | |
6849 | ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
6850 | ret = i40e_add_vsi(ctl_vsi); | |
6851 | if (ret) { | |
6852 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6853 | "rebuild of veb_idx %d owner VSI failed: %d\n", |
6854 | veb->idx, ret); | |
41c445ff JB |
6855 | goto end_reconstitute; |
6856 | } | |
6857 | i40e_vsi_reset_stats(ctl_vsi); | |
6858 | ||
6859 | /* create the VEB in the switch and move the VSI onto the VEB */ | |
6860 | ret = i40e_add_veb(veb, ctl_vsi); | |
6861 | if (ret) | |
6862 | goto end_reconstitute; | |
6863 | ||
fc60861e ASJ |
6864 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) |
6865 | veb->bridge_mode = BRIDGE_MODE_VEB; | |
6866 | else | |
6867 | veb->bridge_mode = BRIDGE_MODE_VEPA; | |
51616018 | 6868 | i40e_config_bridge_mode(veb); |
b64ba084 | 6869 | |
41c445ff | 6870 | /* create the remaining VSIs attached to this VEB */ |
505682cd | 6871 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
6872 | if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi) |
6873 | continue; | |
6874 | ||
6875 | if (pf->vsi[v]->veb_idx == veb->idx) { | |
6876 | struct i40e_vsi *vsi = pf->vsi[v]; | |
6995b36c | 6877 | |
41c445ff JB |
6878 | vsi->uplink_seid = veb->seid; |
6879 | ret = i40e_add_vsi(vsi); | |
6880 | if (ret) { | |
6881 | dev_info(&pf->pdev->dev, | |
6882 | "rebuild of vsi_idx %d failed: %d\n", | |
6883 | v, ret); | |
6884 | goto end_reconstitute; | |
6885 | } | |
6886 | i40e_vsi_reset_stats(vsi); | |
6887 | } | |
6888 | } | |
6889 | ||
6890 | /* create any VEBs attached to this VEB - RECURSION */ | |
6891 | for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { | |
6892 | if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) { | |
6893 | pf->veb[veb_idx]->uplink_seid = veb->seid; | |
6894 | ret = i40e_reconstitute_veb(pf->veb[veb_idx]); | |
6895 | if (ret) | |
6896 | break; | |
6897 | } | |
6898 | } | |
6899 | ||
6900 | end_reconstitute: | |
6901 | return ret; | |
6902 | } | |
6903 | ||
6904 | /** | |
6905 | * i40e_get_capabilities - get info about the HW | |
6906 | * @pf: the PF struct | |
6907 | **/ | |
6908 | static int i40e_get_capabilities(struct i40e_pf *pf) | |
6909 | { | |
6910 | struct i40e_aqc_list_capabilities_element_resp *cap_buf; | |
6911 | u16 data_size; | |
6912 | int buf_len; | |
6913 | int err; | |
6914 | ||
6915 | buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp); | |
6916 | do { | |
6917 | cap_buf = kzalloc(buf_len, GFP_KERNEL); | |
6918 | if (!cap_buf) | |
6919 | return -ENOMEM; | |
6920 | ||
6921 | /* this loads the data into the hw struct for us */ | |
6922 | err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len, | |
6923 | &data_size, | |
6924 | i40e_aqc_opc_list_func_capabilities, | |
6925 | NULL); | |
6926 | /* data loaded, buffer no longer needed */ | |
6927 | kfree(cap_buf); | |
6928 | ||
6929 | if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) { | |
6930 | /* retry with a larger buffer */ | |
6931 | buf_len = data_size; | |
6932 | } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) { | |
6933 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
6934 | "capability discovery failed, err %s aq_err %s\n", |
6935 | i40e_stat_str(&pf->hw, err), | |
6936 | i40e_aq_str(&pf->hw, | |
6937 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
6938 | return -ENODEV; |
6939 | } | |
6940 | } while (err); | |
6941 | ||
6942 | if (pf->hw.debug_mask & I40E_DEBUG_USER) | |
6943 | dev_info(&pf->pdev->dev, | |
6944 | "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n", | |
6945 | pf->hw.pf_id, pf->hw.func_caps.num_vfs, | |
6946 | pf->hw.func_caps.num_msix_vectors, | |
6947 | pf->hw.func_caps.num_msix_vectors_vf, | |
6948 | pf->hw.func_caps.fd_filters_guaranteed, | |
6949 | pf->hw.func_caps.fd_filters_best_effort, | |
6950 | pf->hw.func_caps.num_tx_qp, | |
6951 | pf->hw.func_caps.num_vsis); | |
6952 | ||
7134f9ce JB |
6953 | #define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \ |
6954 | + pf->hw.func_caps.num_vfs) | |
6955 | if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) { | |
6956 | dev_info(&pf->pdev->dev, | |
6957 | "got num_vsis %d, setting num_vsis to %d\n", | |
6958 | pf->hw.func_caps.num_vsis, DEF_NUM_VSI); | |
6959 | pf->hw.func_caps.num_vsis = DEF_NUM_VSI; | |
6960 | } | |
6961 | ||
41c445ff JB |
6962 | return 0; |
6963 | } | |
6964 | ||
cbf61325 ASJ |
6965 | static int i40e_vsi_clear(struct i40e_vsi *vsi); |
6966 | ||
41c445ff | 6967 | /** |
cbf61325 | 6968 | * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband |
41c445ff JB |
6969 | * @pf: board private structure |
6970 | **/ | |
cbf61325 | 6971 | static void i40e_fdir_sb_setup(struct i40e_pf *pf) |
41c445ff JB |
6972 | { |
6973 | struct i40e_vsi *vsi; | |
41c445ff | 6974 | |
407e063c JB |
6975 | /* quick workaround for an NVM issue that leaves a critical register |
6976 | * uninitialized | |
6977 | */ | |
6978 | if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) { | |
6979 | static const u32 hkey[] = { | |
6980 | 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36, | |
6981 | 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb, | |
6982 | 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21, | |
6983 | 0x95b3a76d}; | |
4b816446 | 6984 | int i; |
407e063c JB |
6985 | |
6986 | for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++) | |
6987 | wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]); | |
6988 | } | |
6989 | ||
cbf61325 | 6990 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) |
41c445ff JB |
6991 | return; |
6992 | ||
cbf61325 | 6993 | /* find existing VSI and see if it needs configuring */ |
4b816446 | 6994 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
cbf61325 ASJ |
6995 | |
6996 | /* create a new VSI if none exists */ | |
41c445ff | 6997 | if (!vsi) { |
cbf61325 ASJ |
6998 | vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, |
6999 | pf->vsi[pf->lan_vsi]->seid, 0); | |
41c445ff JB |
7000 | if (!vsi) { |
7001 | dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n"); | |
8a9eb7d3 SN |
7002 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; |
7003 | return; | |
41c445ff | 7004 | } |
cbf61325 | 7005 | } |
41c445ff | 7006 | |
8a9eb7d3 | 7007 | i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring); |
41c445ff JB |
7008 | } |
7009 | ||
7010 | /** | |
7011 | * i40e_fdir_teardown - release the Flow Director resources | |
7012 | * @pf: board private structure | |
7013 | **/ | |
7014 | static void i40e_fdir_teardown(struct i40e_pf *pf) | |
7015 | { | |
4b816446 | 7016 | struct i40e_vsi *vsi; |
41c445ff | 7017 | |
17a73f6b | 7018 | i40e_fdir_filter_exit(pf); |
4b816446 AD |
7019 | vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR); |
7020 | if (vsi) | |
7021 | i40e_vsi_release(vsi); | |
41c445ff JB |
7022 | } |
7023 | ||
7024 | /** | |
f650a38b | 7025 | * i40e_prep_for_reset - prep for the core to reset |
41c445ff | 7026 | * @pf: board private structure |
373149fc MS |
7027 | * @lock_acquired: indicates whether or not the lock has been acquired |
7028 | * before this function was called. | |
41c445ff | 7029 | * |
b40c82e6 | 7030 | * Close up the VFs and other things in prep for PF Reset. |
f650a38b | 7031 | **/ |
373149fc | 7032 | static void i40e_prep_for_reset(struct i40e_pf *pf, bool lock_acquired) |
41c445ff | 7033 | { |
41c445ff | 7034 | struct i40e_hw *hw = &pf->hw; |
60442dea | 7035 | i40e_status ret = 0; |
41c445ff JB |
7036 | u32 v; |
7037 | ||
0da36b97 JK |
7038 | clear_bit(__I40E_RESET_INTR_RECEIVED, pf->state); |
7039 | if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) | |
23cfbe07 | 7040 | return; |
d3ce5734 MW |
7041 | if (i40e_check_asq_alive(&pf->hw)) |
7042 | i40e_vc_notify_reset(pf); | |
41c445ff | 7043 | |
69bfb110 | 7044 | dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n"); |
41c445ff | 7045 | |
41c445ff | 7046 | /* quiesce the VSIs and their queues that are not already DOWN */ |
373149fc MS |
7047 | /* pf_quiesce_all_vsi modifies netdev structures -rtnl_lock needed */ |
7048 | if (!lock_acquired) | |
7049 | rtnl_lock(); | |
41c445ff | 7050 | i40e_pf_quiesce_all_vsi(pf); |
373149fc MS |
7051 | if (!lock_acquired) |
7052 | rtnl_unlock(); | |
41c445ff | 7053 | |
505682cd | 7054 | for (v = 0; v < pf->num_alloc_vsi; v++) { |
41c445ff JB |
7055 | if (pf->vsi[v]) |
7056 | pf->vsi[v]->seid = 0; | |
7057 | } | |
7058 | ||
7059 | i40e_shutdown_adminq(&pf->hw); | |
7060 | ||
f650a38b | 7061 | /* call shutdown HMC */ |
60442dea SN |
7062 | if (hw->hmc.hmc_obj) { |
7063 | ret = i40e_shutdown_lan_hmc(hw); | |
23cfbe07 | 7064 | if (ret) |
60442dea SN |
7065 | dev_warn(&pf->pdev->dev, |
7066 | "shutdown_lan_hmc failed: %d\n", ret); | |
f650a38b | 7067 | } |
f650a38b ASJ |
7068 | } |
7069 | ||
44033fac JB |
7070 | /** |
7071 | * i40e_send_version - update firmware with driver version | |
7072 | * @pf: PF struct | |
7073 | */ | |
7074 | static void i40e_send_version(struct i40e_pf *pf) | |
7075 | { | |
7076 | struct i40e_driver_version dv; | |
7077 | ||
7078 | dv.major_version = DRV_VERSION_MAJOR; | |
7079 | dv.minor_version = DRV_VERSION_MINOR; | |
7080 | dv.build_version = DRV_VERSION_BUILD; | |
7081 | dv.subbuild_version = 0; | |
35a7d804 | 7082 | strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string)); |
44033fac JB |
7083 | i40e_aq_send_driver_version(&pf->hw, &dv, NULL); |
7084 | } | |
7085 | ||
5bbb2e20 FS |
7086 | /** |
7087 | * i40e_get_oem_version - get OEM specific version information | |
7088 | * @hw: pointer to the hardware structure | |
7089 | **/ | |
7090 | static void i40e_get_oem_version(struct i40e_hw *hw) | |
7091 | { | |
7092 | u16 block_offset = 0xffff; | |
7093 | u16 block_length = 0; | |
7094 | u16 capabilities = 0; | |
7095 | u16 gen_snap = 0; | |
7096 | u16 release = 0; | |
7097 | ||
7098 | #define I40E_SR_NVM_OEM_VERSION_PTR 0x1B | |
7099 | #define I40E_NVM_OEM_LENGTH_OFFSET 0x00 | |
7100 | #define I40E_NVM_OEM_CAPABILITIES_OFFSET 0x01 | |
7101 | #define I40E_NVM_OEM_GEN_OFFSET 0x02 | |
7102 | #define I40E_NVM_OEM_RELEASE_OFFSET 0x03 | |
7103 | #define I40E_NVM_OEM_CAPABILITIES_MASK 0x000F | |
7104 | #define I40E_NVM_OEM_LENGTH 3 | |
7105 | ||
7106 | /* Check if pointer to OEM version block is valid. */ | |
7107 | i40e_read_nvm_word(hw, I40E_SR_NVM_OEM_VERSION_PTR, &block_offset); | |
7108 | if (block_offset == 0xffff) | |
7109 | return; | |
7110 | ||
7111 | /* Check if OEM version block has correct length. */ | |
7112 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_LENGTH_OFFSET, | |
7113 | &block_length); | |
7114 | if (block_length < I40E_NVM_OEM_LENGTH) | |
7115 | return; | |
7116 | ||
7117 | /* Check if OEM version format is as expected. */ | |
7118 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_CAPABILITIES_OFFSET, | |
7119 | &capabilities); | |
7120 | if ((capabilities & I40E_NVM_OEM_CAPABILITIES_MASK) != 0) | |
7121 | return; | |
7122 | ||
7123 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_GEN_OFFSET, | |
7124 | &gen_snap); | |
7125 | i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_RELEASE_OFFSET, | |
7126 | &release); | |
7127 | hw->nvm.oem_ver = (gen_snap << I40E_OEM_SNAP_SHIFT) | release; | |
7128 | hw->nvm.eetrack = I40E_OEM_EETRACK_ID; | |
7129 | } | |
7130 | ||
f650a38b | 7131 | /** |
373149fc | 7132 | * i40e_reset - wait for core reset to finish reset, reset pf if corer not seen |
f650a38b ASJ |
7133 | * @pf: board private structure |
7134 | **/ | |
373149fc | 7135 | static int i40e_reset(struct i40e_pf *pf) |
f650a38b | 7136 | { |
f650a38b ASJ |
7137 | struct i40e_hw *hw = &pf->hw; |
7138 | i40e_status ret; | |
f650a38b | 7139 | |
41c445ff | 7140 | ret = i40e_pf_reset(hw); |
b5565400 | 7141 | if (ret) { |
41c445ff | 7142 | dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret); |
0da36b97 JK |
7143 | set_bit(__I40E_RESET_FAILED, pf->state); |
7144 | clear_bit(__I40E_RESET_RECOVERY_PENDING, pf->state); | |
373149fc MS |
7145 | } else { |
7146 | pf->pfr_count++; | |
b5565400 | 7147 | } |
373149fc MS |
7148 | return ret; |
7149 | } | |
7150 | ||
7151 | /** | |
7152 | * i40e_rebuild - rebuild using a saved config | |
7153 | * @pf: board private structure | |
7154 | * @reinit: if the Main VSI needs to re-initialized. | |
7155 | * @lock_acquired: indicates whether or not the lock has been acquired | |
7156 | * before this function was called. | |
7157 | **/ | |
7158 | static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired) | |
7159 | { | |
7160 | struct i40e_hw *hw = &pf->hw; | |
7161 | u8 set_fc_aq_fail = 0; | |
7162 | i40e_status ret; | |
7163 | u32 val; | |
7164 | int v; | |
41c445ff | 7165 | |
9e6c9c0f | 7166 | if (test_bit(__I40E_DOWN, pf->state)) |
a316f651 | 7167 | goto clear_recovery; |
69bfb110 | 7168 | dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n"); |
41c445ff JB |
7169 | |
7170 | /* rebuild the basics for the AdminQ, HMC, and initial HW switch */ | |
7171 | ret = i40e_init_adminq(&pf->hw); | |
7172 | if (ret) { | |
f1c7e72e SN |
7173 | dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n", |
7174 | i40e_stat_str(&pf->hw, ret), | |
7175 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
a316f651 | 7176 | goto clear_recovery; |
41c445ff | 7177 | } |
5bbb2e20 | 7178 | i40e_get_oem_version(&pf->hw); |
41c445ff | 7179 | |
4eb3f768 | 7180 | /* re-verify the eeprom if we just had an EMP reset */ |
0da36b97 | 7181 | if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state)) |
4eb3f768 | 7182 | i40e_verify_eeprom(pf); |
4eb3f768 | 7183 | |
e78ac4bf | 7184 | i40e_clear_pxe_mode(hw); |
41c445ff | 7185 | ret = i40e_get_capabilities(pf); |
f1c7e72e | 7186 | if (ret) |
41c445ff | 7187 | goto end_core_reset; |
41c445ff | 7188 | |
41c445ff | 7189 | ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, |
c76cb6ed | 7190 | hw->func_caps.num_rx_qp, 0, 0); |
41c445ff JB |
7191 | if (ret) { |
7192 | dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret); | |
7193 | goto end_core_reset; | |
7194 | } | |
7195 | ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); | |
7196 | if (ret) { | |
7197 | dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret); | |
7198 | goto end_core_reset; | |
7199 | } | |
7200 | ||
4e3b35b0 NP |
7201 | #ifdef CONFIG_I40E_DCB |
7202 | ret = i40e_init_pf_dcb(pf); | |
7203 | if (ret) { | |
aebfc816 SN |
7204 | dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret); |
7205 | pf->flags &= ~I40E_FLAG_DCB_CAPABLE; | |
7206 | /* Continue without DCB enabled */ | |
4e3b35b0 NP |
7207 | } |
7208 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff | 7209 | /* do basic switch setup */ |
373149fc MS |
7210 | if (!lock_acquired) |
7211 | rtnl_lock(); | |
bc7d338f | 7212 | ret = i40e_setup_pf_switch(pf, reinit); |
41c445ff | 7213 | if (ret) |
373149fc | 7214 | goto end_unlock; |
41c445ff | 7215 | |
2f0aff41 SN |
7216 | /* The driver only wants link up/down and module qualification |
7217 | * reports from firmware. Note the negative logic. | |
7e2453fe JB |
7218 | */ |
7219 | ret = i40e_aq_set_phy_int_mask(&pf->hw, | |
2f0aff41 | 7220 | ~(I40E_AQ_EVENT_LINK_UPDOWN | |
867a79e3 | 7221 | I40E_AQ_EVENT_MEDIA_NA | |
2f0aff41 | 7222 | I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); |
7e2453fe | 7223 | if (ret) |
f1c7e72e SN |
7224 | dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", |
7225 | i40e_stat_str(&pf->hw, ret), | |
7226 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7e2453fe | 7227 | |
cafa2ee6 ASJ |
7228 | /* make sure our flow control settings are restored */ |
7229 | ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true); | |
7230 | if (ret) | |
8279e495 NP |
7231 | dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n", |
7232 | i40e_stat_str(&pf->hw, ret), | |
7233 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 7234 | |
41c445ff JB |
7235 | /* Rebuild the VSIs and VEBs that existed before reset. |
7236 | * They are still in our local switch element arrays, so only | |
7237 | * need to rebuild the switch model in the HW. | |
7238 | * | |
7239 | * If there were VEBs but the reconstitution failed, we'll try | |
7240 | * try to recover minimal use by getting the basic PF VSI working. | |
7241 | */ | |
7242 | if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) { | |
69bfb110 | 7243 | dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n"); |
41c445ff JB |
7244 | /* find the one VEB connected to the MAC, and find orphans */ |
7245 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
7246 | if (!pf->veb[v]) | |
7247 | continue; | |
7248 | ||
7249 | if (pf->veb[v]->uplink_seid == pf->mac_seid || | |
7250 | pf->veb[v]->uplink_seid == 0) { | |
7251 | ret = i40e_reconstitute_veb(pf->veb[v]); | |
7252 | ||
7253 | if (!ret) | |
7254 | continue; | |
7255 | ||
7256 | /* If Main VEB failed, we're in deep doodoo, | |
7257 | * so give up rebuilding the switch and set up | |
7258 | * for minimal rebuild of PF VSI. | |
7259 | * If orphan failed, we'll report the error | |
7260 | * but try to keep going. | |
7261 | */ | |
7262 | if (pf->veb[v]->uplink_seid == pf->mac_seid) { | |
7263 | dev_info(&pf->pdev->dev, | |
7264 | "rebuild of switch failed: %d, will try to set up simple PF connection\n", | |
7265 | ret); | |
7266 | pf->vsi[pf->lan_vsi]->uplink_seid | |
7267 | = pf->mac_seid; | |
7268 | break; | |
7269 | } else if (pf->veb[v]->uplink_seid == 0) { | |
7270 | dev_info(&pf->pdev->dev, | |
7271 | "rebuild of orphan VEB failed: %d\n", | |
7272 | ret); | |
7273 | } | |
7274 | } | |
7275 | } | |
7276 | } | |
7277 | ||
7278 | if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) { | |
cde4cbc7 | 7279 | dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n"); |
41c445ff JB |
7280 | /* no VEB, so rebuild only the Main VSI */ |
7281 | ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]); | |
7282 | if (ret) { | |
7283 | dev_info(&pf->pdev->dev, | |
7284 | "rebuild of Main VSI failed: %d\n", ret); | |
373149fc | 7285 | goto end_unlock; |
41c445ff JB |
7286 | } |
7287 | } | |
7288 | ||
4f2f017c ASJ |
7289 | /* Reconfigure hardware for allowing smaller MSS in the case |
7290 | * of TSO, so that we avoid the MDD being fired and causing | |
7291 | * a reset in the case of small MSS+TSO. | |
7292 | */ | |
7293 | #define I40E_REG_MSS 0x000E64DC | |
7294 | #define I40E_REG_MSS_MIN_MASK 0x3FF0000 | |
7295 | #define I40E_64BYTE_MSS 0x400000 | |
7296 | val = rd32(hw, I40E_REG_MSS); | |
7297 | if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { | |
7298 | val &= ~I40E_REG_MSS_MIN_MASK; | |
7299 | val |= I40E_64BYTE_MSS; | |
7300 | wr32(hw, I40E_REG_MSS, val); | |
7301 | } | |
7302 | ||
d36e41dc | 7303 | if (pf->hw_features & I40E_HW_RESTART_AUTONEG) { |
025b4a54 ASJ |
7304 | msleep(75); |
7305 | ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); | |
7306 | if (ret) | |
f1c7e72e SN |
7307 | dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", |
7308 | i40e_stat_str(&pf->hw, ret), | |
7309 | i40e_aq_str(&pf->hw, | |
7310 | pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 7311 | } |
41c445ff JB |
7312 | /* reinit the misc interrupt */ |
7313 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
7314 | ret = i40e_setup_misc_vector(pf); | |
7315 | ||
e7358f54 ASJ |
7316 | /* Add a filter to drop all Flow control frames from any VSI from being |
7317 | * transmitted. By doing so we stop a malicious VF from sending out | |
7318 | * PAUSE or PFC frames and potentially controlling traffic for other | |
7319 | * PF/VF VSIs. | |
7320 | * The FW can still send Flow control frames if enabled. | |
7321 | */ | |
7322 | i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, | |
7323 | pf->main_vsi_seid); | |
7324 | ||
41c445ff JB |
7325 | /* restart the VSIs that were rebuilt and running before the reset */ |
7326 | i40e_pf_unquiesce_all_vsi(pf); | |
7327 | ||
024b05f4 JK |
7328 | /* Release the RTNL lock before we start resetting VFs */ |
7329 | if (!lock_acquired) | |
7330 | rtnl_unlock(); | |
7331 | ||
e4b433f4 | 7332 | i40e_reset_all_vfs(pf, true); |
69f64b2b | 7333 | |
41c445ff | 7334 | /* tell the firmware that we're starting */ |
44033fac | 7335 | i40e_send_version(pf); |
41c445ff | 7336 | |
024b05f4 JK |
7337 | /* We've already released the lock, so don't do it again */ |
7338 | goto end_core_reset; | |
7339 | ||
373149fc | 7340 | end_unlock: |
024b05f4 JK |
7341 | if (!lock_acquired) |
7342 | rtnl_unlock(); | |
41c445ff | 7343 | end_core_reset: |
0da36b97 | 7344 | clear_bit(__I40E_RESET_FAILED, pf->state); |
a316f651 | 7345 | clear_recovery: |
0da36b97 | 7346 | clear_bit(__I40E_RESET_RECOVERY_PENDING, pf->state); |
41c445ff JB |
7347 | } |
7348 | ||
373149fc MS |
7349 | /** |
7350 | * i40e_reset_and_rebuild - reset and rebuild using a saved config | |
7351 | * @pf: board private structure | |
7352 | * @reinit: if the Main VSI needs to re-initialized. | |
7353 | * @lock_acquired: indicates whether or not the lock has been acquired | |
7354 | * before this function was called. | |
7355 | **/ | |
7356 | static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit, | |
7357 | bool lock_acquired) | |
7358 | { | |
7359 | int ret; | |
7360 | /* Now we wait for GRST to settle out. | |
7361 | * We don't have to delete the VEBs or VSIs from the hw switch | |
7362 | * because the reset will make them disappear. | |
7363 | */ | |
7364 | ret = i40e_reset(pf); | |
7365 | if (!ret) | |
7366 | i40e_rebuild(pf, reinit, lock_acquired); | |
7367 | } | |
7368 | ||
f650a38b | 7369 | /** |
b40c82e6 | 7370 | * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild |
f650a38b ASJ |
7371 | * @pf: board private structure |
7372 | * | |
7373 | * Close up the VFs and other things in prep for a Core Reset, | |
7374 | * then get ready to rebuild the world. | |
373149fc MS |
7375 | * @lock_acquired: indicates whether or not the lock has been acquired |
7376 | * before this function was called. | |
f650a38b | 7377 | **/ |
373149fc | 7378 | static void i40e_handle_reset_warning(struct i40e_pf *pf, bool lock_acquired) |
f650a38b | 7379 | { |
373149fc MS |
7380 | i40e_prep_for_reset(pf, lock_acquired); |
7381 | i40e_reset_and_rebuild(pf, false, lock_acquired); | |
f650a38b ASJ |
7382 | } |
7383 | ||
41c445ff JB |
7384 | /** |
7385 | * i40e_handle_mdd_event | |
b40c82e6 | 7386 | * @pf: pointer to the PF structure |
41c445ff JB |
7387 | * |
7388 | * Called from the MDD irq handler to identify possibly malicious vfs | |
7389 | **/ | |
7390 | static void i40e_handle_mdd_event(struct i40e_pf *pf) | |
7391 | { | |
7392 | struct i40e_hw *hw = &pf->hw; | |
7393 | bool mdd_detected = false; | |
df430b12 | 7394 | bool pf_mdd_detected = false; |
41c445ff JB |
7395 | struct i40e_vf *vf; |
7396 | u32 reg; | |
7397 | int i; | |
7398 | ||
0da36b97 | 7399 | if (!test_bit(__I40E_MDD_EVENT_PENDING, pf->state)) |
41c445ff JB |
7400 | return; |
7401 | ||
7402 | /* find what triggered the MDD event */ | |
7403 | reg = rd32(hw, I40E_GL_MDET_TX); | |
7404 | if (reg & I40E_GL_MDET_TX_VALID_MASK) { | |
4c33f83a ASJ |
7405 | u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >> |
7406 | I40E_GL_MDET_TX_PF_NUM_SHIFT; | |
2089ad03 | 7407 | u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >> |
4c33f83a | 7408 | I40E_GL_MDET_TX_VF_NUM_SHIFT; |
013f6579 | 7409 | u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >> |
4c33f83a | 7410 | I40E_GL_MDET_TX_EVENT_SHIFT; |
2089ad03 MW |
7411 | u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >> |
7412 | I40E_GL_MDET_TX_QUEUE_SHIFT) - | |
7413 | pf->hw.func_caps.base_queue; | |
faf32978 | 7414 | if (netif_msg_tx_err(pf)) |
b40c82e6 | 7415 | dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n", |
faf32978 | 7416 | event, queue, pf_num, vf_num); |
41c445ff JB |
7417 | wr32(hw, I40E_GL_MDET_TX, 0xffffffff); |
7418 | mdd_detected = true; | |
7419 | } | |
7420 | reg = rd32(hw, I40E_GL_MDET_RX); | |
7421 | if (reg & I40E_GL_MDET_RX_VALID_MASK) { | |
4c33f83a ASJ |
7422 | u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >> |
7423 | I40E_GL_MDET_RX_FUNCTION_SHIFT; | |
013f6579 | 7424 | u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >> |
4c33f83a | 7425 | I40E_GL_MDET_RX_EVENT_SHIFT; |
2089ad03 MW |
7426 | u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >> |
7427 | I40E_GL_MDET_RX_QUEUE_SHIFT) - | |
7428 | pf->hw.func_caps.base_queue; | |
faf32978 JB |
7429 | if (netif_msg_rx_err(pf)) |
7430 | dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n", | |
7431 | event, queue, func); | |
41c445ff JB |
7432 | wr32(hw, I40E_GL_MDET_RX, 0xffffffff); |
7433 | mdd_detected = true; | |
7434 | } | |
7435 | ||
df430b12 NP |
7436 | if (mdd_detected) { |
7437 | reg = rd32(hw, I40E_PF_MDET_TX); | |
7438 | if (reg & I40E_PF_MDET_TX_VALID_MASK) { | |
7439 | wr32(hw, I40E_PF_MDET_TX, 0xFFFF); | |
faf32978 | 7440 | dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n"); |
df430b12 NP |
7441 | pf_mdd_detected = true; |
7442 | } | |
7443 | reg = rd32(hw, I40E_PF_MDET_RX); | |
7444 | if (reg & I40E_PF_MDET_RX_VALID_MASK) { | |
7445 | wr32(hw, I40E_PF_MDET_RX, 0xFFFF); | |
faf32978 | 7446 | dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n"); |
df430b12 NP |
7447 | pf_mdd_detected = true; |
7448 | } | |
7449 | /* Queue belongs to the PF, initiate a reset */ | |
7450 | if (pf_mdd_detected) { | |
0da36b97 | 7451 | set_bit(__I40E_PF_RESET_REQUESTED, pf->state); |
df430b12 NP |
7452 | i40e_service_event_schedule(pf); |
7453 | } | |
7454 | } | |
7455 | ||
41c445ff JB |
7456 | /* see if one of the VFs needs its hand slapped */ |
7457 | for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) { | |
7458 | vf = &(pf->vf[i]); | |
7459 | reg = rd32(hw, I40E_VP_MDET_TX(i)); | |
7460 | if (reg & I40E_VP_MDET_TX_VALID_MASK) { | |
7461 | wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF); | |
7462 | vf->num_mdd_events++; | |
faf32978 JB |
7463 | dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n", |
7464 | i); | |
41c445ff JB |
7465 | } |
7466 | ||
7467 | reg = rd32(hw, I40E_VP_MDET_RX(i)); | |
7468 | if (reg & I40E_VP_MDET_RX_VALID_MASK) { | |
7469 | wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF); | |
7470 | vf->num_mdd_events++; | |
faf32978 JB |
7471 | dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n", |
7472 | i); | |
41c445ff JB |
7473 | } |
7474 | ||
7475 | if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) { | |
7476 | dev_info(&pf->pdev->dev, | |
7477 | "Too many MDD events on VF %d, disabled\n", i); | |
7478 | dev_info(&pf->pdev->dev, | |
7479 | "Use PF Control I/F to re-enable the VF\n"); | |
6322e63c | 7480 | set_bit(I40E_VF_STATE_DISABLED, &vf->vf_states); |
41c445ff JB |
7481 | } |
7482 | } | |
7483 | ||
7484 | /* re-enable mdd interrupt cause */ | |
0da36b97 | 7485 | clear_bit(__I40E_MDD_EVENT_PENDING, pf->state); |
41c445ff JB |
7486 | reg = rd32(hw, I40E_PFINT_ICR0_ENA); |
7487 | reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK; | |
7488 | wr32(hw, I40E_PFINT_ICR0_ENA, reg); | |
7489 | i40e_flush(hw); | |
7490 | } | |
7491 | ||
d8b2c700 JK |
7492 | static const char *i40e_tunnel_name(struct i40e_udp_port_config *port) |
7493 | { | |
7494 | switch (port->type) { | |
7495 | case UDP_TUNNEL_TYPE_VXLAN: | |
7496 | return "vxlan"; | |
7497 | case UDP_TUNNEL_TYPE_GENEVE: | |
7498 | return "geneve"; | |
7499 | default: | |
7500 | return "unknown"; | |
7501 | } | |
7502 | } | |
7503 | ||
1f190d93 AD |
7504 | /** |
7505 | * i40e_sync_udp_filters - Trigger a sync event for existing UDP filters | |
7506 | * @pf: board private structure | |
7507 | **/ | |
7508 | static void i40e_sync_udp_filters(struct i40e_pf *pf) | |
7509 | { | |
7510 | int i; | |
7511 | ||
7512 | /* loop through and set pending bit for all active UDP filters */ | |
7513 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { | |
7514 | if (pf->udp_ports[i].port) | |
7515 | pf->pending_udp_bitmap |= BIT_ULL(i); | |
7516 | } | |
7517 | ||
7518 | pf->flags |= I40E_FLAG_UDP_FILTER_SYNC; | |
7519 | } | |
7520 | ||
a1c9a9d9 | 7521 | /** |
6a899024 | 7522 | * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW |
a1c9a9d9 JK |
7523 | * @pf: board private structure |
7524 | **/ | |
6a899024 | 7525 | static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf) |
a1c9a9d9 | 7526 | { |
a1c9a9d9 JK |
7527 | struct i40e_hw *hw = &pf->hw; |
7528 | i40e_status ret; | |
fe0b0cd9 | 7529 | u16 port; |
a1c9a9d9 JK |
7530 | int i; |
7531 | ||
6a899024 | 7532 | if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC)) |
a1c9a9d9 JK |
7533 | return; |
7534 | ||
6a899024 | 7535 | pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC; |
a1c9a9d9 JK |
7536 | |
7537 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { | |
6a899024 SA |
7538 | if (pf->pending_udp_bitmap & BIT_ULL(i)) { |
7539 | pf->pending_udp_bitmap &= ~BIT_ULL(i); | |
27826fd5 | 7540 | port = pf->udp_ports[i].port; |
c22c06c8 | 7541 | if (port) |
b3f5c7bc CW |
7542 | ret = i40e_aq_add_udp_tunnel(hw, port, |
7543 | pf->udp_ports[i].type, | |
7544 | NULL, NULL); | |
c22c06c8 SN |
7545 | else |
7546 | ret = i40e_aq_del_udp_tunnel(hw, i, NULL); | |
a1c9a9d9 JK |
7547 | |
7548 | if (ret) { | |
d8b2c700 JK |
7549 | dev_info(&pf->pdev->dev, |
7550 | "%s %s port %d, index %d failed, err %s aq_err %s\n", | |
7551 | i40e_tunnel_name(&pf->udp_ports[i]), | |
7552 | port ? "add" : "delete", | |
7553 | port, i, | |
7554 | i40e_stat_str(&pf->hw, ret), | |
7555 | i40e_aq_str(&pf->hw, | |
7556 | pf->hw.aq.asq_last_status)); | |
27826fd5 | 7557 | pf->udp_ports[i].port = 0; |
a1c9a9d9 JK |
7558 | } |
7559 | } | |
7560 | } | |
7561 | } | |
7562 | ||
41c445ff JB |
7563 | /** |
7564 | * i40e_service_task - Run the driver's async subtasks | |
7565 | * @work: pointer to work_struct containing our data | |
7566 | **/ | |
7567 | static void i40e_service_task(struct work_struct *work) | |
7568 | { | |
7569 | struct i40e_pf *pf = container_of(work, | |
7570 | struct i40e_pf, | |
7571 | service_task); | |
7572 | unsigned long start_time = jiffies; | |
7573 | ||
e57a2fea | 7574 | /* don't bother with service tasks if a reset is in progress */ |
0da36b97 | 7575 | if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state)) |
e57a2fea | 7576 | return; |
e57a2fea | 7577 | |
0da36b97 | 7578 | if (test_and_set_bit(__I40E_SERVICE_SCHED, pf->state)) |
91089033 MW |
7579 | return; |
7580 | ||
b03a8c1f | 7581 | i40e_detect_recover_hung(pf); |
2818ccd9 | 7582 | i40e_sync_filters_subtask(pf); |
41c445ff JB |
7583 | i40e_reset_subtask(pf); |
7584 | i40e_handle_mdd_event(pf); | |
7585 | i40e_vc_process_vflr_event(pf); | |
7586 | i40e_watchdog_subtask(pf); | |
7587 | i40e_fdir_reinit_subtask(pf); | |
0ef2d5af MW |
7588 | if (pf->flags & I40E_FLAG_CLIENT_RESET) { |
7589 | /* Client subtask will reopen next time through. */ | |
7590 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], true); | |
7591 | pf->flags &= ~I40E_FLAG_CLIENT_RESET; | |
7592 | } else { | |
7593 | i40e_client_subtask(pf); | |
7594 | if (pf->flags & I40E_FLAG_CLIENT_L2_CHANGE) { | |
7595 | i40e_notify_client_of_l2_param_changes( | |
7596 | pf->vsi[pf->lan_vsi]); | |
7597 | pf->flags &= ~I40E_FLAG_CLIENT_L2_CHANGE; | |
7598 | } | |
7599 | } | |
41c445ff | 7600 | i40e_sync_filters_subtask(pf); |
6a899024 | 7601 | i40e_sync_udp_filters_subtask(pf); |
41c445ff JB |
7602 | i40e_clean_adminq_subtask(pf); |
7603 | ||
91089033 MW |
7604 | /* flush memory to make sure state is correct before next watchdog */ |
7605 | smp_mb__before_atomic(); | |
0da36b97 | 7606 | clear_bit(__I40E_SERVICE_SCHED, pf->state); |
41c445ff JB |
7607 | |
7608 | /* If the tasks have taken longer than one timer cycle or there | |
7609 | * is more work to be done, reschedule the service task now | |
7610 | * rather than wait for the timer to tick again. | |
7611 | */ | |
7612 | if (time_after(jiffies, (start_time + pf->service_timer_period)) || | |
0da36b97 JK |
7613 | test_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state) || |
7614 | test_bit(__I40E_MDD_EVENT_PENDING, pf->state) || | |
7615 | test_bit(__I40E_VFLR_EVENT_PENDING, pf->state)) | |
41c445ff JB |
7616 | i40e_service_event_schedule(pf); |
7617 | } | |
7618 | ||
7619 | /** | |
7620 | * i40e_service_timer - timer callback | |
7621 | * @data: pointer to PF struct | |
7622 | **/ | |
7623 | static void i40e_service_timer(unsigned long data) | |
7624 | { | |
7625 | struct i40e_pf *pf = (struct i40e_pf *)data; | |
7626 | ||
7627 | mod_timer(&pf->service_timer, | |
7628 | round_jiffies(jiffies + pf->service_timer_period)); | |
7629 | i40e_service_event_schedule(pf); | |
7630 | } | |
7631 | ||
7632 | /** | |
7633 | * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI | |
7634 | * @vsi: the VSI being configured | |
7635 | **/ | |
7636 | static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi) | |
7637 | { | |
7638 | struct i40e_pf *pf = vsi->back; | |
7639 | ||
7640 | switch (vsi->type) { | |
7641 | case I40E_VSI_MAIN: | |
7642 | vsi->alloc_queue_pairs = pf->num_lan_qps; | |
7643 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
7644 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
7645 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
7646 | vsi->num_q_vectors = pf->num_lan_msix; | |
7647 | else | |
7648 | vsi->num_q_vectors = 1; | |
7649 | ||
7650 | break; | |
7651 | ||
7652 | case I40E_VSI_FDIR: | |
7653 | vsi->alloc_queue_pairs = 1; | |
7654 | vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT, | |
7655 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
a70e407f | 7656 | vsi->num_q_vectors = pf->num_fdsb_msix; |
41c445ff JB |
7657 | break; |
7658 | ||
7659 | case I40E_VSI_VMDQ2: | |
7660 | vsi->alloc_queue_pairs = pf->num_vmdq_qps; | |
7661 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
7662 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
7663 | vsi->num_q_vectors = pf->num_vmdq_msix; | |
7664 | break; | |
7665 | ||
7666 | case I40E_VSI_SRIOV: | |
7667 | vsi->alloc_queue_pairs = pf->num_vf_qps; | |
7668 | vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS, | |
7669 | I40E_REQ_DESCRIPTOR_MULTIPLE); | |
7670 | break; | |
7671 | ||
7672 | default: | |
7673 | WARN_ON(1); | |
7674 | return -ENODATA; | |
7675 | } | |
7676 | ||
7677 | return 0; | |
7678 | } | |
7679 | ||
f650a38b ASJ |
7680 | /** |
7681 | * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi | |
7682 | * @type: VSI pointer | |
bc7d338f | 7683 | * @alloc_qvectors: a bool to specify if q_vectors need to be allocated. |
f650a38b ASJ |
7684 | * |
7685 | * On error: returns error code (negative) | |
7686 | * On success: returns 0 | |
7687 | **/ | |
bc7d338f | 7688 | static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors) |
f650a38b | 7689 | { |
74608d17 | 7690 | struct i40e_ring **next_rings; |
f650a38b ASJ |
7691 | int size; |
7692 | int ret = 0; | |
7693 | ||
74608d17 BT |
7694 | /* allocate memory for both Tx, XDP Tx and Rx ring pointers */ |
7695 | size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * | |
7696 | (i40e_enabled_xdp_vsi(vsi) ? 3 : 2); | |
f650a38b ASJ |
7697 | vsi->tx_rings = kzalloc(size, GFP_KERNEL); |
7698 | if (!vsi->tx_rings) | |
7699 | return -ENOMEM; | |
74608d17 BT |
7700 | next_rings = vsi->tx_rings + vsi->alloc_queue_pairs; |
7701 | if (i40e_enabled_xdp_vsi(vsi)) { | |
7702 | vsi->xdp_rings = next_rings; | |
7703 | next_rings += vsi->alloc_queue_pairs; | |
7704 | } | |
7705 | vsi->rx_rings = next_rings; | |
f650a38b | 7706 | |
bc7d338f ASJ |
7707 | if (alloc_qvectors) { |
7708 | /* allocate memory for q_vector pointers */ | |
f57e4fbd | 7709 | size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors; |
bc7d338f ASJ |
7710 | vsi->q_vectors = kzalloc(size, GFP_KERNEL); |
7711 | if (!vsi->q_vectors) { | |
7712 | ret = -ENOMEM; | |
7713 | goto err_vectors; | |
7714 | } | |
f650a38b ASJ |
7715 | } |
7716 | return ret; | |
7717 | ||
7718 | err_vectors: | |
7719 | kfree(vsi->tx_rings); | |
7720 | return ret; | |
7721 | } | |
7722 | ||
41c445ff JB |
7723 | /** |
7724 | * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF | |
7725 | * @pf: board private structure | |
7726 | * @type: type of VSI | |
7727 | * | |
7728 | * On error: returns error code (negative) | |
7729 | * On success: returns vsi index in PF (positive) | |
7730 | **/ | |
7731 | static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type) | |
7732 | { | |
7733 | int ret = -ENODEV; | |
7734 | struct i40e_vsi *vsi; | |
7735 | int vsi_idx; | |
7736 | int i; | |
7737 | ||
7738 | /* Need to protect the allocation of the VSIs at the PF level */ | |
7739 | mutex_lock(&pf->switch_mutex); | |
7740 | ||
7741 | /* VSI list may be fragmented if VSI creation/destruction has | |
7742 | * been happening. We can afford to do a quick scan to look | |
7743 | * for any free VSIs in the list. | |
7744 | * | |
7745 | * find next empty vsi slot, looping back around if necessary | |
7746 | */ | |
7747 | i = pf->next_vsi; | |
505682cd | 7748 | while (i < pf->num_alloc_vsi && pf->vsi[i]) |
41c445ff | 7749 | i++; |
505682cd | 7750 | if (i >= pf->num_alloc_vsi) { |
41c445ff JB |
7751 | i = 0; |
7752 | while (i < pf->next_vsi && pf->vsi[i]) | |
7753 | i++; | |
7754 | } | |
7755 | ||
505682cd | 7756 | if (i < pf->num_alloc_vsi && !pf->vsi[i]) { |
41c445ff JB |
7757 | vsi_idx = i; /* Found one! */ |
7758 | } else { | |
7759 | ret = -ENODEV; | |
493fb300 | 7760 | goto unlock_pf; /* out of VSI slots! */ |
41c445ff JB |
7761 | } |
7762 | pf->next_vsi = ++i; | |
7763 | ||
7764 | vsi = kzalloc(sizeof(*vsi), GFP_KERNEL); | |
7765 | if (!vsi) { | |
7766 | ret = -ENOMEM; | |
493fb300 | 7767 | goto unlock_pf; |
41c445ff JB |
7768 | } |
7769 | vsi->type = type; | |
7770 | vsi->back = pf; | |
0da36b97 | 7771 | set_bit(__I40E_VSI_DOWN, vsi->state); |
41c445ff JB |
7772 | vsi->flags = 0; |
7773 | vsi->idx = vsi_idx; | |
ac26fc13 | 7774 | vsi->int_rate_limit = 0; |
5db4cb59 ASJ |
7775 | vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ? |
7776 | pf->rss_table_size : 64; | |
41c445ff JB |
7777 | vsi->netdev_registered = false; |
7778 | vsi->work_limit = I40E_DEFAULT_IRQ_WORK; | |
278e7d0b | 7779 | hash_init(vsi->mac_filter_hash); |
63741846 | 7780 | vsi->irqs_ready = false; |
41c445ff | 7781 | |
9f65e15b AD |
7782 | ret = i40e_set_num_rings_in_vsi(vsi); |
7783 | if (ret) | |
7784 | goto err_rings; | |
7785 | ||
bc7d338f | 7786 | ret = i40e_vsi_alloc_arrays(vsi, true); |
f650a38b | 7787 | if (ret) |
9f65e15b | 7788 | goto err_rings; |
493fb300 | 7789 | |
41c445ff JB |
7790 | /* Setup default MSIX irq handler for VSI */ |
7791 | i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings); | |
7792 | ||
21659035 | 7793 | /* Initialize VSI lock */ |
278e7d0b | 7794 | spin_lock_init(&vsi->mac_filter_hash_lock); |
41c445ff JB |
7795 | pf->vsi[vsi_idx] = vsi; |
7796 | ret = vsi_idx; | |
493fb300 AD |
7797 | goto unlock_pf; |
7798 | ||
9f65e15b | 7799 | err_rings: |
493fb300 AD |
7800 | pf->next_vsi = i - 1; |
7801 | kfree(vsi); | |
7802 | unlock_pf: | |
41c445ff JB |
7803 | mutex_unlock(&pf->switch_mutex); |
7804 | return ret; | |
7805 | } | |
7806 | ||
f650a38b ASJ |
7807 | /** |
7808 | * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI | |
7809 | * @type: VSI pointer | |
bc7d338f | 7810 | * @free_qvectors: a bool to specify if q_vectors need to be freed. |
f650a38b ASJ |
7811 | * |
7812 | * On error: returns error code (negative) | |
7813 | * On success: returns 0 | |
7814 | **/ | |
bc7d338f | 7815 | static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors) |
f650a38b ASJ |
7816 | { |
7817 | /* free the ring and vector containers */ | |
bc7d338f ASJ |
7818 | if (free_qvectors) { |
7819 | kfree(vsi->q_vectors); | |
7820 | vsi->q_vectors = NULL; | |
7821 | } | |
f650a38b ASJ |
7822 | kfree(vsi->tx_rings); |
7823 | vsi->tx_rings = NULL; | |
7824 | vsi->rx_rings = NULL; | |
74608d17 | 7825 | vsi->xdp_rings = NULL; |
f650a38b ASJ |
7826 | } |
7827 | ||
28c5869f HZ |
7828 | /** |
7829 | * i40e_clear_rss_config_user - clear the user configured RSS hash keys | |
7830 | * and lookup table | |
7831 | * @vsi: Pointer to VSI structure | |
7832 | */ | |
7833 | static void i40e_clear_rss_config_user(struct i40e_vsi *vsi) | |
7834 | { | |
7835 | if (!vsi) | |
7836 | return; | |
7837 | ||
7838 | kfree(vsi->rss_hkey_user); | |
7839 | vsi->rss_hkey_user = NULL; | |
7840 | ||
7841 | kfree(vsi->rss_lut_user); | |
7842 | vsi->rss_lut_user = NULL; | |
7843 | } | |
7844 | ||
41c445ff JB |
7845 | /** |
7846 | * i40e_vsi_clear - Deallocate the VSI provided | |
7847 | * @vsi: the VSI being un-configured | |
7848 | **/ | |
7849 | static int i40e_vsi_clear(struct i40e_vsi *vsi) | |
7850 | { | |
7851 | struct i40e_pf *pf; | |
7852 | ||
7853 | if (!vsi) | |
7854 | return 0; | |
7855 | ||
7856 | if (!vsi->back) | |
7857 | goto free_vsi; | |
7858 | pf = vsi->back; | |
7859 | ||
7860 | mutex_lock(&pf->switch_mutex); | |
7861 | if (!pf->vsi[vsi->idx]) { | |
7862 | dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n", | |
7863 | vsi->idx, vsi->idx, vsi, vsi->type); | |
7864 | goto unlock_vsi; | |
7865 | } | |
7866 | ||
7867 | if (pf->vsi[vsi->idx] != vsi) { | |
7868 | dev_err(&pf->pdev->dev, | |
7869 | "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n", | |
7870 | pf->vsi[vsi->idx]->idx, | |
7871 | pf->vsi[vsi->idx], | |
7872 | pf->vsi[vsi->idx]->type, | |
7873 | vsi->idx, vsi, vsi->type); | |
7874 | goto unlock_vsi; | |
7875 | } | |
7876 | ||
b40c82e6 | 7877 | /* updates the PF for this cleared vsi */ |
41c445ff JB |
7878 | i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); |
7879 | i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx); | |
7880 | ||
bc7d338f | 7881 | i40e_vsi_free_arrays(vsi, true); |
28c5869f | 7882 | i40e_clear_rss_config_user(vsi); |
493fb300 | 7883 | |
41c445ff JB |
7884 | pf->vsi[vsi->idx] = NULL; |
7885 | if (vsi->idx < pf->next_vsi) | |
7886 | pf->next_vsi = vsi->idx; | |
7887 | ||
7888 | unlock_vsi: | |
7889 | mutex_unlock(&pf->switch_mutex); | |
7890 | free_vsi: | |
7891 | kfree(vsi); | |
7892 | ||
7893 | return 0; | |
7894 | } | |
7895 | ||
9f65e15b AD |
7896 | /** |
7897 | * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI | |
7898 | * @vsi: the VSI being cleaned | |
7899 | **/ | |
be1d5eea | 7900 | static void i40e_vsi_clear_rings(struct i40e_vsi *vsi) |
9f65e15b AD |
7901 | { |
7902 | int i; | |
7903 | ||
8e9dca53 | 7904 | if (vsi->tx_rings && vsi->tx_rings[0]) { |
d7397644 | 7905 | for (i = 0; i < vsi->alloc_queue_pairs; i++) { |
00403f04 MW |
7906 | kfree_rcu(vsi->tx_rings[i], rcu); |
7907 | vsi->tx_rings[i] = NULL; | |
7908 | vsi->rx_rings[i] = NULL; | |
74608d17 BT |
7909 | if (vsi->xdp_rings) |
7910 | vsi->xdp_rings[i] = NULL; | |
00403f04 | 7911 | } |
be1d5eea | 7912 | } |
9f65e15b AD |
7913 | } |
7914 | ||
41c445ff JB |
7915 | /** |
7916 | * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI | |
7917 | * @vsi: the VSI being configured | |
7918 | **/ | |
7919 | static int i40e_alloc_rings(struct i40e_vsi *vsi) | |
7920 | { | |
74608d17 | 7921 | int i, qpv = i40e_enabled_xdp_vsi(vsi) ? 3 : 2; |
41c445ff | 7922 | struct i40e_pf *pf = vsi->back; |
74608d17 | 7923 | struct i40e_ring *ring; |
41c445ff | 7924 | |
41c445ff | 7925 | /* Set basic values in the rings to be used later during open() */ |
d7397644 | 7926 | for (i = 0; i < vsi->alloc_queue_pairs; i++) { |
ac6c5e3d | 7927 | /* allocate space for both Tx and Rx in one shot */ |
74608d17 BT |
7928 | ring = kcalloc(qpv, sizeof(struct i40e_ring), GFP_KERNEL); |
7929 | if (!ring) | |
9f65e15b | 7930 | goto err_out; |
41c445ff | 7931 | |
74608d17 BT |
7932 | ring->queue_index = i; |
7933 | ring->reg_idx = vsi->base_queue + i; | |
7934 | ring->ring_active = false; | |
7935 | ring->vsi = vsi; | |
7936 | ring->netdev = vsi->netdev; | |
7937 | ring->dev = &pf->pdev->dev; | |
7938 | ring->count = vsi->num_desc; | |
7939 | ring->size = 0; | |
7940 | ring->dcb_tc = 0; | |
d36e41dc | 7941 | if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE) |
74608d17 BT |
7942 | ring->flags = I40E_TXR_FLAGS_WB_ON_ITR; |
7943 | ring->tx_itr_setting = pf->tx_itr_default; | |
7944 | vsi->tx_rings[i] = ring++; | |
7945 | ||
7946 | if (!i40e_enabled_xdp_vsi(vsi)) | |
7947 | goto setup_rx; | |
7948 | ||
7949 | ring->queue_index = vsi->alloc_queue_pairs + i; | |
7950 | ring->reg_idx = vsi->base_queue + ring->queue_index; | |
7951 | ring->ring_active = false; | |
7952 | ring->vsi = vsi; | |
7953 | ring->netdev = NULL; | |
7954 | ring->dev = &pf->pdev->dev; | |
7955 | ring->count = vsi->num_desc; | |
7956 | ring->size = 0; | |
7957 | ring->dcb_tc = 0; | |
d36e41dc | 7958 | if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE) |
74608d17 BT |
7959 | ring->flags = I40E_TXR_FLAGS_WB_ON_ITR; |
7960 | set_ring_xdp(ring); | |
7961 | ring->tx_itr_setting = pf->tx_itr_default; | |
7962 | vsi->xdp_rings[i] = ring++; | |
7963 | ||
7964 | setup_rx: | |
7965 | ring->queue_index = i; | |
7966 | ring->reg_idx = vsi->base_queue + i; | |
7967 | ring->ring_active = false; | |
7968 | ring->vsi = vsi; | |
7969 | ring->netdev = vsi->netdev; | |
7970 | ring->dev = &pf->pdev->dev; | |
7971 | ring->count = vsi->num_desc; | |
7972 | ring->size = 0; | |
7973 | ring->dcb_tc = 0; | |
7974 | ring->rx_itr_setting = pf->rx_itr_default; | |
7975 | vsi->rx_rings[i] = ring; | |
41c445ff JB |
7976 | } |
7977 | ||
7978 | return 0; | |
9f65e15b AD |
7979 | |
7980 | err_out: | |
7981 | i40e_vsi_clear_rings(vsi); | |
7982 | return -ENOMEM; | |
41c445ff JB |
7983 | } |
7984 | ||
7985 | /** | |
7986 | * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel | |
7987 | * @pf: board private structure | |
7988 | * @vectors: the number of MSI-X vectors to request | |
7989 | * | |
7990 | * Returns the number of vectors reserved, or error | |
7991 | **/ | |
7992 | static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors) | |
7993 | { | |
7b37f376 AG |
7994 | vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries, |
7995 | I40E_MIN_MSIX, vectors); | |
7996 | if (vectors < 0) { | |
41c445ff | 7997 | dev_info(&pf->pdev->dev, |
7b37f376 | 7998 | "MSI-X vector reservation failed: %d\n", vectors); |
41c445ff JB |
7999 | vectors = 0; |
8000 | } | |
8001 | ||
8002 | return vectors; | |
8003 | } | |
8004 | ||
8005 | /** | |
8006 | * i40e_init_msix - Setup the MSIX capability | |
8007 | * @pf: board private structure | |
8008 | * | |
8009 | * Work with the OS to set up the MSIX vectors needed. | |
8010 | * | |
3b444399 | 8011 | * Returns the number of vectors reserved or negative on failure |
41c445ff JB |
8012 | **/ |
8013 | static int i40e_init_msix(struct i40e_pf *pf) | |
8014 | { | |
41c445ff | 8015 | struct i40e_hw *hw = &pf->hw; |
c0cf70a6 | 8016 | int cpus, extra_vectors; |
1e200e4a | 8017 | int vectors_left; |
41c445ff | 8018 | int v_budget, i; |
3b444399 | 8019 | int v_actual; |
e3219ce6 | 8020 | int iwarp_requested = 0; |
41c445ff JB |
8021 | |
8022 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
8023 | return -ENODEV; | |
8024 | ||
8025 | /* The number of vectors we'll request will be comprised of: | |
8026 | * - Add 1 for "other" cause for Admin Queue events, etc. | |
8027 | * - The number of LAN queue pairs | |
f8ff1464 ASJ |
8028 | * - Queues being used for RSS. |
8029 | * We don't need as many as max_rss_size vectors. | |
8030 | * use rss_size instead in the calculation since that | |
8031 | * is governed by number of cpus in the system. | |
8032 | * - assumes symmetric Tx/Rx pairing | |
41c445ff | 8033 | * - The number of VMDq pairs |
e3219ce6 | 8034 | * - The CPU count within the NUMA node if iWARP is enabled |
41c445ff JB |
8035 | * Once we count this up, try the request. |
8036 | * | |
8037 | * If we can't get what we want, we'll simplify to nearly nothing | |
8038 | * and try again. If that still fails, we punt. | |
8039 | */ | |
1e200e4a SN |
8040 | vectors_left = hw->func_caps.num_msix_vectors; |
8041 | v_budget = 0; | |
8042 | ||
8043 | /* reserve one vector for miscellaneous handler */ | |
8044 | if (vectors_left) { | |
8045 | v_budget++; | |
8046 | vectors_left--; | |
8047 | } | |
8048 | ||
c0cf70a6 JK |
8049 | /* reserve some vectors for the main PF traffic queues. Initially we |
8050 | * only reserve at most 50% of the available vectors, in the case that | |
8051 | * the number of online CPUs is large. This ensures that we can enable | |
8052 | * extra features as well. Once we've enabled the other features, we | |
8053 | * will use any remaining vectors to reach as close as we can to the | |
8054 | * number of online CPUs. | |
8055 | */ | |
8056 | cpus = num_online_cpus(); | |
8057 | pf->num_lan_msix = min_t(int, cpus, vectors_left / 2); | |
1e200e4a | 8058 | vectors_left -= pf->num_lan_msix; |
1e200e4a SN |
8059 | |
8060 | /* reserve one vector for sideband flow director */ | |
8061 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
8062 | if (vectors_left) { | |
a70e407f | 8063 | pf->num_fdsb_msix = 1; |
1e200e4a SN |
8064 | v_budget++; |
8065 | vectors_left--; | |
8066 | } else { | |
a70e407f | 8067 | pf->num_fdsb_msix = 0; |
1e200e4a SN |
8068 | } |
8069 | } | |
83840e4b | 8070 | |
e3219ce6 ASJ |
8071 | /* can we reserve enough for iWARP? */ |
8072 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { | |
4ce20abc SA |
8073 | iwarp_requested = pf->num_iwarp_msix; |
8074 | ||
e3219ce6 ASJ |
8075 | if (!vectors_left) |
8076 | pf->num_iwarp_msix = 0; | |
8077 | else if (vectors_left < pf->num_iwarp_msix) | |
8078 | pf->num_iwarp_msix = 1; | |
8079 | v_budget += pf->num_iwarp_msix; | |
8080 | vectors_left -= pf->num_iwarp_msix; | |
8081 | } | |
8082 | ||
1e200e4a SN |
8083 | /* any vectors left over go for VMDq support */ |
8084 | if (pf->flags & I40E_FLAG_VMDQ_ENABLED) { | |
8085 | int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps; | |
8086 | int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted); | |
8087 | ||
9ca57e97 SA |
8088 | if (!vectors_left) { |
8089 | pf->num_vmdq_msix = 0; | |
8090 | pf->num_vmdq_qps = 0; | |
8091 | } else { | |
8092 | /* if we're short on vectors for what's desired, we limit | |
8093 | * the queues per vmdq. If this is still more than are | |
8094 | * available, the user will need to change the number of | |
8095 | * queues/vectors used by the PF later with the ethtool | |
8096 | * channels command | |
8097 | */ | |
8098 | if (vmdq_vecs < vmdq_vecs_wanted) | |
8099 | pf->num_vmdq_qps = 1; | |
8100 | pf->num_vmdq_msix = pf->num_vmdq_qps; | |
1e200e4a | 8101 | |
9ca57e97 SA |
8102 | v_budget += vmdq_vecs; |
8103 | vectors_left -= vmdq_vecs; | |
8104 | } | |
1e200e4a | 8105 | } |
41c445ff | 8106 | |
c0cf70a6 JK |
8107 | /* On systems with a large number of SMP cores, we previously limited |
8108 | * the number of vectors for num_lan_msix to be at most 50% of the | |
8109 | * available vectors, to allow for other features. Now, we add back | |
8110 | * the remaining vectors. However, we ensure that the total | |
8111 | * num_lan_msix will not exceed num_online_cpus(). To do this, we | |
8112 | * calculate the number of vectors we can add without going over the | |
8113 | * cap of CPUs. For systems with a small number of CPUs this will be | |
8114 | * zero. | |
8115 | */ | |
8116 | extra_vectors = min_t(int, cpus - pf->num_lan_msix, vectors_left); | |
8117 | pf->num_lan_msix += extra_vectors; | |
8118 | vectors_left -= extra_vectors; | |
8119 | ||
8120 | WARN(vectors_left < 0, | |
8121 | "Calculation of remaining vectors underflowed. This is an accounting bug when determining total MSI-X vectors.\n"); | |
8122 | ||
8123 | v_budget += pf->num_lan_msix; | |
41c445ff JB |
8124 | pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry), |
8125 | GFP_KERNEL); | |
8126 | if (!pf->msix_entries) | |
8127 | return -ENOMEM; | |
8128 | ||
8129 | for (i = 0; i < v_budget; i++) | |
8130 | pf->msix_entries[i].entry = i; | |
3b444399 | 8131 | v_actual = i40e_reserve_msix_vectors(pf, v_budget); |
a34977ba | 8132 | |
3b444399 | 8133 | if (v_actual < I40E_MIN_MSIX) { |
41c445ff JB |
8134 | pf->flags &= ~I40E_FLAG_MSIX_ENABLED; |
8135 | kfree(pf->msix_entries); | |
8136 | pf->msix_entries = NULL; | |
4c95aa5d | 8137 | pci_disable_msix(pf->pdev); |
41c445ff JB |
8138 | return -ENODEV; |
8139 | ||
3b444399 | 8140 | } else if (v_actual == I40E_MIN_MSIX) { |
41c445ff | 8141 | /* Adjust for minimal MSIX use */ |
41c445ff JB |
8142 | pf->num_vmdq_vsis = 0; |
8143 | pf->num_vmdq_qps = 0; | |
41c445ff JB |
8144 | pf->num_lan_qps = 1; |
8145 | pf->num_lan_msix = 1; | |
8146 | ||
4ce20abc SA |
8147 | } else if (!vectors_left) { |
8148 | /* If we have limited resources, we will start with no vectors | |
8149 | * for the special features and then allocate vectors to some | |
8150 | * of these features based on the policy and at the end disable | |
8151 | * the features that did not get any vectors. | |
8152 | */ | |
3b444399 SN |
8153 | int vec; |
8154 | ||
4ce20abc SA |
8155 | dev_info(&pf->pdev->dev, |
8156 | "MSI-X vector limit reached, attempting to redistribute vectors\n"); | |
a34977ba | 8157 | /* reserve the misc vector */ |
3b444399 | 8158 | vec = v_actual - 1; |
a34977ba | 8159 | |
41c445ff JB |
8160 | /* Scale vector usage down */ |
8161 | pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */ | |
a34977ba | 8162 | pf->num_vmdq_vsis = 1; |
1e200e4a | 8163 | pf->num_vmdq_qps = 1; |
41c445ff JB |
8164 | |
8165 | /* partition out the remaining vectors */ | |
8166 | switch (vec) { | |
8167 | case 2: | |
41c445ff JB |
8168 | pf->num_lan_msix = 1; |
8169 | break; | |
8170 | case 3: | |
e3219ce6 ASJ |
8171 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
8172 | pf->num_lan_msix = 1; | |
8173 | pf->num_iwarp_msix = 1; | |
8174 | } else { | |
8175 | pf->num_lan_msix = 2; | |
8176 | } | |
41c445ff JB |
8177 | break; |
8178 | default: | |
e3219ce6 ASJ |
8179 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
8180 | pf->num_iwarp_msix = min_t(int, (vec / 3), | |
8181 | iwarp_requested); | |
8182 | pf->num_vmdq_vsis = min_t(int, (vec / 3), | |
8183 | I40E_DEFAULT_NUM_VMDQ_VSI); | |
8184 | } else { | |
8185 | pf->num_vmdq_vsis = min_t(int, (vec / 2), | |
8186 | I40E_DEFAULT_NUM_VMDQ_VSI); | |
8187 | } | |
abd97a94 SA |
8188 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
8189 | pf->num_fdsb_msix = 1; | |
8190 | vec--; | |
8191 | } | |
e3219ce6 ASJ |
8192 | pf->num_lan_msix = min_t(int, |
8193 | (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)), | |
8194 | pf->num_lan_msix); | |
4ce20abc | 8195 | pf->num_lan_qps = pf->num_lan_msix; |
41c445ff JB |
8196 | break; |
8197 | } | |
8198 | } | |
8199 | ||
abd97a94 SA |
8200 | if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) && |
8201 | (pf->num_fdsb_msix == 0)) { | |
8202 | dev_info(&pf->pdev->dev, "Sideband Flowdir disabled, not enough MSI-X vectors\n"); | |
8203 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
8204 | } | |
a34977ba ASJ |
8205 | if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && |
8206 | (pf->num_vmdq_msix == 0)) { | |
8207 | dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n"); | |
8208 | pf->flags &= ~I40E_FLAG_VMDQ_ENABLED; | |
8209 | } | |
e3219ce6 ASJ |
8210 | |
8211 | if ((pf->flags & I40E_FLAG_IWARP_ENABLED) && | |
8212 | (pf->num_iwarp_msix == 0)) { | |
8213 | dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n"); | |
8214 | pf->flags &= ~I40E_FLAG_IWARP_ENABLED; | |
8215 | } | |
4ce20abc SA |
8216 | i40e_debug(&pf->hw, I40E_DEBUG_INIT, |
8217 | "MSI-X vector distribution: PF %d, VMDq %d, FDSB %d, iWARP %d\n", | |
8218 | pf->num_lan_msix, | |
8219 | pf->num_vmdq_msix * pf->num_vmdq_vsis, | |
8220 | pf->num_fdsb_msix, | |
8221 | pf->num_iwarp_msix); | |
8222 | ||
3b444399 | 8223 | return v_actual; |
41c445ff JB |
8224 | } |
8225 | ||
493fb300 | 8226 | /** |
90e04070 | 8227 | * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector |
493fb300 AD |
8228 | * @vsi: the VSI being configured |
8229 | * @v_idx: index of the vector in the vsi struct | |
7f6c5539 | 8230 | * @cpu: cpu to be used on affinity_mask |
493fb300 AD |
8231 | * |
8232 | * We allocate one q_vector. If allocation fails we return -ENOMEM. | |
8233 | **/ | |
7f6c5539 | 8234 | static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx, int cpu) |
493fb300 AD |
8235 | { |
8236 | struct i40e_q_vector *q_vector; | |
8237 | ||
8238 | /* allocate q_vector */ | |
8239 | q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL); | |
8240 | if (!q_vector) | |
8241 | return -ENOMEM; | |
8242 | ||
8243 | q_vector->vsi = vsi; | |
8244 | q_vector->v_idx = v_idx; | |
759dc4a7 | 8245 | cpumask_copy(&q_vector->affinity_mask, cpu_possible_mask); |
7f6c5539 | 8246 | |
493fb300 AD |
8247 | if (vsi->netdev) |
8248 | netif_napi_add(vsi->netdev, &q_vector->napi, | |
eefeacee | 8249 | i40e_napi_poll, NAPI_POLL_WEIGHT); |
493fb300 | 8250 | |
cd0b6fa6 AD |
8251 | q_vector->rx.latency_range = I40E_LOW_LATENCY; |
8252 | q_vector->tx.latency_range = I40E_LOW_LATENCY; | |
8253 | ||
493fb300 AD |
8254 | /* tie q_vector and vsi together */ |
8255 | vsi->q_vectors[v_idx] = q_vector; | |
8256 | ||
8257 | return 0; | |
8258 | } | |
8259 | ||
41c445ff | 8260 | /** |
90e04070 | 8261 | * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors |
41c445ff JB |
8262 | * @vsi: the VSI being configured |
8263 | * | |
8264 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
8265 | * return -ENOMEM. | |
8266 | **/ | |
90e04070 | 8267 | static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi) |
41c445ff JB |
8268 | { |
8269 | struct i40e_pf *pf = vsi->back; | |
7f6c5539 | 8270 | int err, v_idx, num_q_vectors, current_cpu; |
41c445ff JB |
8271 | |
8272 | /* if not MSIX, give the one vector only to the LAN VSI */ | |
8273 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) | |
8274 | num_q_vectors = vsi->num_q_vectors; | |
8275 | else if (vsi == pf->vsi[pf->lan_vsi]) | |
8276 | num_q_vectors = 1; | |
8277 | else | |
8278 | return -EINVAL; | |
8279 | ||
7f6c5539 GP |
8280 | current_cpu = cpumask_first(cpu_online_mask); |
8281 | ||
41c445ff | 8282 | for (v_idx = 0; v_idx < num_q_vectors; v_idx++) { |
7f6c5539 | 8283 | err = i40e_vsi_alloc_q_vector(vsi, v_idx, current_cpu); |
493fb300 AD |
8284 | if (err) |
8285 | goto err_out; | |
7f6c5539 GP |
8286 | current_cpu = cpumask_next(current_cpu, cpu_online_mask); |
8287 | if (unlikely(current_cpu >= nr_cpu_ids)) | |
8288 | current_cpu = cpumask_first(cpu_online_mask); | |
41c445ff JB |
8289 | } |
8290 | ||
8291 | return 0; | |
493fb300 AD |
8292 | |
8293 | err_out: | |
8294 | while (v_idx--) | |
8295 | i40e_free_q_vector(vsi, v_idx); | |
8296 | ||
8297 | return err; | |
41c445ff JB |
8298 | } |
8299 | ||
8300 | /** | |
8301 | * i40e_init_interrupt_scheme - Determine proper interrupt scheme | |
8302 | * @pf: board private structure to initialize | |
8303 | **/ | |
c1147280 | 8304 | static int i40e_init_interrupt_scheme(struct i40e_pf *pf) |
41c445ff | 8305 | { |
3b444399 SN |
8306 | int vectors = 0; |
8307 | ssize_t size; | |
41c445ff JB |
8308 | |
8309 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
3b444399 SN |
8310 | vectors = i40e_init_msix(pf); |
8311 | if (vectors < 0) { | |
60ea5f83 | 8312 | pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | |
e3219ce6 | 8313 | I40E_FLAG_IWARP_ENABLED | |
60ea5f83 | 8314 | I40E_FLAG_RSS_ENABLED | |
4d9b6043 | 8315 | I40E_FLAG_DCB_CAPABLE | |
a036244c | 8316 | I40E_FLAG_DCB_ENABLED | |
60ea5f83 JB |
8317 | I40E_FLAG_SRIOV_ENABLED | |
8318 | I40E_FLAG_FD_SB_ENABLED | | |
8319 | I40E_FLAG_FD_ATR_ENABLED | | |
8320 | I40E_FLAG_VMDQ_ENABLED); | |
41c445ff JB |
8321 | |
8322 | /* rework the queue expectations without MSIX */ | |
8323 | i40e_determine_queue_usage(pf); | |
8324 | } | |
8325 | } | |
8326 | ||
8327 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) && | |
8328 | (pf->flags & I40E_FLAG_MSI_ENABLED)) { | |
77fa28be | 8329 | dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n"); |
3b444399 SN |
8330 | vectors = pci_enable_msi(pf->pdev); |
8331 | if (vectors < 0) { | |
8332 | dev_info(&pf->pdev->dev, "MSI init failed - %d\n", | |
8333 | vectors); | |
41c445ff JB |
8334 | pf->flags &= ~I40E_FLAG_MSI_ENABLED; |
8335 | } | |
3b444399 | 8336 | vectors = 1; /* one MSI or Legacy vector */ |
41c445ff JB |
8337 | } |
8338 | ||
958a3e3b | 8339 | if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED))) |
77fa28be | 8340 | dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n"); |
958a3e3b | 8341 | |
3b444399 SN |
8342 | /* set up vector assignment tracking */ |
8343 | size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors); | |
8344 | pf->irq_pile = kzalloc(size, GFP_KERNEL); | |
c1147280 JB |
8345 | if (!pf->irq_pile) { |
8346 | dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n"); | |
8347 | return -ENOMEM; | |
8348 | } | |
3b444399 SN |
8349 | pf->irq_pile->num_entries = vectors; |
8350 | pf->irq_pile->search_hint = 0; | |
8351 | ||
c1147280 | 8352 | /* track first vector for misc interrupts, ignore return */ |
3b444399 | 8353 | (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1); |
c1147280 JB |
8354 | |
8355 | return 0; | |
41c445ff JB |
8356 | } |
8357 | ||
b980c063 JK |
8358 | #ifdef CONFIG_PM |
8359 | /** | |
8360 | * i40e_restore_interrupt_scheme - Restore the interrupt scheme | |
8361 | * @pf: private board data structure | |
8362 | * | |
8363 | * Restore the interrupt scheme that was cleared when we suspended the | |
8364 | * device. This should be called during resume to re-allocate the q_vectors | |
8365 | * and reacquire IRQs. | |
8366 | */ | |
8367 | static int i40e_restore_interrupt_scheme(struct i40e_pf *pf) | |
8368 | { | |
8369 | int err, i; | |
8370 | ||
8371 | /* We cleared the MSI and MSI-X flags when disabling the old interrupt | |
8372 | * scheme. We need to re-enabled them here in order to attempt to | |
8373 | * re-acquire the MSI or MSI-X vectors | |
8374 | */ | |
8375 | pf->flags |= (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED); | |
8376 | ||
8377 | err = i40e_init_interrupt_scheme(pf); | |
8378 | if (err) | |
8379 | return err; | |
8380 | ||
8381 | /* Now that we've re-acquired IRQs, we need to remap the vectors and | |
8382 | * rings together again. | |
8383 | */ | |
8384 | for (i = 0; i < pf->num_alloc_vsi; i++) { | |
8385 | if (pf->vsi[i]) { | |
8386 | err = i40e_vsi_alloc_q_vectors(pf->vsi[i]); | |
8387 | if (err) | |
8388 | goto err_unwind; | |
8389 | i40e_vsi_map_rings_to_vectors(pf->vsi[i]); | |
8390 | } | |
8391 | } | |
8392 | ||
8393 | err = i40e_setup_misc_vector(pf); | |
8394 | if (err) | |
8395 | goto err_unwind; | |
8396 | ||
8397 | return 0; | |
8398 | ||
8399 | err_unwind: | |
8400 | while (i--) { | |
8401 | if (pf->vsi[i]) | |
8402 | i40e_vsi_free_q_vectors(pf->vsi[i]); | |
8403 | } | |
8404 | ||
8405 | return err; | |
8406 | } | |
8407 | #endif /* CONFIG_PM */ | |
8408 | ||
41c445ff JB |
8409 | /** |
8410 | * i40e_setup_misc_vector - Setup the misc vector to handle non queue events | |
8411 | * @pf: board private structure | |
8412 | * | |
8413 | * This sets up the handler for MSIX 0, which is used to manage the | |
8414 | * non-queue interrupts, e.g. AdminQ and errors. This is not used | |
8415 | * when in MSI or Legacy interrupt mode. | |
8416 | **/ | |
8417 | static int i40e_setup_misc_vector(struct i40e_pf *pf) | |
8418 | { | |
8419 | struct i40e_hw *hw = &pf->hw; | |
8420 | int err = 0; | |
8421 | ||
c17401a1 JK |
8422 | /* Only request the IRQ once, the first time through. */ |
8423 | if (!test_and_set_bit(__I40E_MISC_IRQ_REQUESTED, pf->state)) { | |
41c445ff | 8424 | err = request_irq(pf->msix_entries[0].vector, |
b294ac70 | 8425 | i40e_intr, 0, pf->int_name, pf); |
41c445ff | 8426 | if (err) { |
c17401a1 | 8427 | clear_bit(__I40E_MISC_IRQ_REQUESTED, pf->state); |
41c445ff | 8428 | dev_info(&pf->pdev->dev, |
77fa28be | 8429 | "request_irq for %s failed: %d\n", |
b294ac70 | 8430 | pf->int_name, err); |
41c445ff JB |
8431 | return -EFAULT; |
8432 | } | |
8433 | } | |
8434 | ||
ab437b5a | 8435 | i40e_enable_misc_int_causes(pf); |
41c445ff JB |
8436 | |
8437 | /* associate no queues to the misc vector */ | |
8438 | wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST); | |
8439 | wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K); | |
8440 | ||
8441 | i40e_flush(hw); | |
8442 | ||
40d72a50 | 8443 | i40e_irq_dynamic_enable_icr0(pf, true); |
41c445ff JB |
8444 | |
8445 | return err; | |
8446 | } | |
8447 | ||
8448 | /** | |
e25d00b8 ASJ |
8449 | * i40e_config_rss_aq - Prepare for RSS using AQ commands |
8450 | * @vsi: vsi structure | |
8451 | * @seed: RSS hash seed | |
8452 | **/ | |
e69ff813 HZ |
8453 | static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed, |
8454 | u8 *lut, u16 lut_size) | |
e25d00b8 | 8455 | { |
e25d00b8 ASJ |
8456 | struct i40e_pf *pf = vsi->back; |
8457 | struct i40e_hw *hw = &pf->hw; | |
776b2e15 | 8458 | int ret = 0; |
e25d00b8 | 8459 | |
776b2e15 JK |
8460 | if (seed) { |
8461 | struct i40e_aqc_get_set_rss_key_data *seed_dw = | |
8462 | (struct i40e_aqc_get_set_rss_key_data *)seed; | |
8463 | ret = i40e_aq_set_rss_key(hw, vsi->id, seed_dw); | |
8464 | if (ret) { | |
8465 | dev_info(&pf->pdev->dev, | |
8466 | "Cannot set RSS key, err %s aq_err %s\n", | |
8467 | i40e_stat_str(hw, ret), | |
8468 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
8469 | return ret; | |
8470 | } | |
e25d00b8 | 8471 | } |
776b2e15 JK |
8472 | if (lut) { |
8473 | bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false; | |
e25d00b8 | 8474 | |
776b2e15 JK |
8475 | ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, lut, lut_size); |
8476 | if (ret) { | |
8477 | dev_info(&pf->pdev->dev, | |
8478 | "Cannot set RSS lut, err %s aq_err %s\n", | |
8479 | i40e_stat_str(hw, ret), | |
8480 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
8481 | return ret; | |
8482 | } | |
8483 | } | |
e25d00b8 ASJ |
8484 | return ret; |
8485 | } | |
8486 | ||
95a73780 ASJ |
8487 | /** |
8488 | * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands | |
8489 | * @vsi: Pointer to vsi structure | |
8490 | * @seed: Buffter to store the hash keys | |
8491 | * @lut: Buffer to store the lookup table entries | |
8492 | * @lut_size: Size of buffer to store the lookup table entries | |
8493 | * | |
8494 | * Return 0 on success, negative on failure | |
8495 | */ | |
8496 | static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed, | |
8497 | u8 *lut, u16 lut_size) | |
8498 | { | |
8499 | struct i40e_pf *pf = vsi->back; | |
8500 | struct i40e_hw *hw = &pf->hw; | |
8501 | int ret = 0; | |
8502 | ||
8503 | if (seed) { | |
8504 | ret = i40e_aq_get_rss_key(hw, vsi->id, | |
8505 | (struct i40e_aqc_get_set_rss_key_data *)seed); | |
8506 | if (ret) { | |
8507 | dev_info(&pf->pdev->dev, | |
8508 | "Cannot get RSS key, err %s aq_err %s\n", | |
8509 | i40e_stat_str(&pf->hw, ret), | |
8510 | i40e_aq_str(&pf->hw, | |
8511 | pf->hw.aq.asq_last_status)); | |
8512 | return ret; | |
8513 | } | |
8514 | } | |
8515 | ||
8516 | if (lut) { | |
8517 | bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false; | |
8518 | ||
8519 | ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size); | |
8520 | if (ret) { | |
8521 | dev_info(&pf->pdev->dev, | |
8522 | "Cannot get RSS lut, err %s aq_err %s\n", | |
8523 | i40e_stat_str(&pf->hw, ret), | |
8524 | i40e_aq_str(&pf->hw, | |
8525 | pf->hw.aq.asq_last_status)); | |
8526 | return ret; | |
8527 | } | |
8528 | } | |
8529 | ||
8530 | return ret; | |
8531 | } | |
8532 | ||
0582b964 JK |
8533 | /** |
8534 | * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used | |
8535 | * @vsi: VSI structure | |
8536 | **/ | |
8537 | static int i40e_vsi_config_rss(struct i40e_vsi *vsi) | |
8538 | { | |
8539 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
8540 | struct i40e_pf *pf = vsi->back; | |
8541 | u8 *lut; | |
8542 | int ret; | |
8543 | ||
d36e41dc | 8544 | if (!(pf->hw_features & I40E_HW_RSS_AQ_CAPABLE)) |
0582b964 JK |
8545 | return 0; |
8546 | ||
552b9962 JK |
8547 | if (!vsi->rss_size) |
8548 | vsi->rss_size = min_t(int, pf->alloc_rss_size, | |
8549 | vsi->num_queue_pairs); | |
8550 | if (!vsi->rss_size) | |
8551 | return -EINVAL; | |
8552 | ||
0582b964 JK |
8553 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); |
8554 | if (!lut) | |
8555 | return -ENOMEM; | |
552b9962 JK |
8556 | /* Use the user configured hash keys and lookup table if there is one, |
8557 | * otherwise use default | |
8558 | */ | |
8559 | if (vsi->rss_lut_user) | |
8560 | memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size); | |
8561 | else | |
8562 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); | |
8563 | if (vsi->rss_hkey_user) | |
8564 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
8565 | else | |
8566 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
0582b964 JK |
8567 | ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size); |
8568 | kfree(lut); | |
8569 | ||
8570 | return ret; | |
8571 | } | |
8572 | ||
e25d00b8 | 8573 | /** |
043dd650 | 8574 | * i40e_config_rss_reg - Configure RSS keys and lut by writing registers |
e69ff813 | 8575 | * @vsi: Pointer to vsi structure |
e25d00b8 | 8576 | * @seed: RSS hash seed |
e69ff813 HZ |
8577 | * @lut: Lookup table |
8578 | * @lut_size: Lookup table size | |
8579 | * | |
8580 | * Returns 0 on success, negative on failure | |
41c445ff | 8581 | **/ |
e69ff813 HZ |
8582 | static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed, |
8583 | const u8 *lut, u16 lut_size) | |
41c445ff | 8584 | { |
e69ff813 | 8585 | struct i40e_pf *pf = vsi->back; |
4617e8c0 | 8586 | struct i40e_hw *hw = &pf->hw; |
c4e1868c | 8587 | u16 vf_id = vsi->vf_id; |
e69ff813 | 8588 | u8 i; |
41c445ff | 8589 | |
e25d00b8 | 8590 | /* Fill out hash function seed */ |
e69ff813 HZ |
8591 | if (seed) { |
8592 | u32 *seed_dw = (u32 *)seed; | |
8593 | ||
c4e1868c MW |
8594 | if (vsi->type == I40E_VSI_MAIN) { |
8595 | for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) | |
26f77e53 | 8596 | wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]); |
c4e1868c MW |
8597 | } else if (vsi->type == I40E_VSI_SRIOV) { |
8598 | for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++) | |
26f77e53 | 8599 | wr32(hw, I40E_VFQF_HKEY1(i, vf_id), seed_dw[i]); |
c4e1868c MW |
8600 | } else { |
8601 | dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n"); | |
8602 | } | |
e69ff813 HZ |
8603 | } |
8604 | ||
8605 | if (lut) { | |
8606 | u32 *lut_dw = (u32 *)lut; | |
8607 | ||
c4e1868c MW |
8608 | if (vsi->type == I40E_VSI_MAIN) { |
8609 | if (lut_size != I40E_HLUT_ARRAY_SIZE) | |
8610 | return -EINVAL; | |
8611 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
8612 | wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]); | |
8613 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
8614 | if (lut_size != I40E_VF_HLUT_ARRAY_SIZE) | |
8615 | return -EINVAL; | |
8616 | for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) | |
26f77e53 | 8617 | wr32(hw, I40E_VFQF_HLUT1(i, vf_id), lut_dw[i]); |
c4e1868c MW |
8618 | } else { |
8619 | dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n"); | |
8620 | } | |
e25d00b8 ASJ |
8621 | } |
8622 | i40e_flush(hw); | |
8623 | ||
8624 | return 0; | |
8625 | } | |
8626 | ||
043dd650 HZ |
8627 | /** |
8628 | * i40e_get_rss_reg - Get the RSS keys and lut by reading registers | |
8629 | * @vsi: Pointer to VSI structure | |
8630 | * @seed: Buffer to store the keys | |
8631 | * @lut: Buffer to store the lookup table entries | |
8632 | * @lut_size: Size of buffer to store the lookup table entries | |
8633 | * | |
8634 | * Returns 0 on success, negative on failure | |
8635 | */ | |
8636 | static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed, | |
8637 | u8 *lut, u16 lut_size) | |
8638 | { | |
8639 | struct i40e_pf *pf = vsi->back; | |
8640 | struct i40e_hw *hw = &pf->hw; | |
8641 | u16 i; | |
8642 | ||
8643 | if (seed) { | |
8644 | u32 *seed_dw = (u32 *)seed; | |
8645 | ||
8646 | for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) | |
272cdaf2 | 8647 | seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i)); |
043dd650 HZ |
8648 | } |
8649 | if (lut) { | |
8650 | u32 *lut_dw = (u32 *)lut; | |
8651 | ||
8652 | if (lut_size != I40E_HLUT_ARRAY_SIZE) | |
8653 | return -EINVAL; | |
8654 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
8655 | lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i)); | |
8656 | } | |
8657 | ||
8658 | return 0; | |
8659 | } | |
8660 | ||
8661 | /** | |
8662 | * i40e_config_rss - Configure RSS keys and lut | |
8663 | * @vsi: Pointer to VSI structure | |
8664 | * @seed: RSS hash seed | |
8665 | * @lut: Lookup table | |
8666 | * @lut_size: Lookup table size | |
8667 | * | |
8668 | * Returns 0 on success, negative on failure | |
8669 | */ | |
8670 | int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) | |
8671 | { | |
8672 | struct i40e_pf *pf = vsi->back; | |
8673 | ||
d36e41dc | 8674 | if (pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) |
043dd650 HZ |
8675 | return i40e_config_rss_aq(vsi, seed, lut, lut_size); |
8676 | else | |
8677 | return i40e_config_rss_reg(vsi, seed, lut, lut_size); | |
8678 | } | |
8679 | ||
8680 | /** | |
8681 | * i40e_get_rss - Get RSS keys and lut | |
8682 | * @vsi: Pointer to VSI structure | |
8683 | * @seed: Buffer to store the keys | |
8684 | * @lut: Buffer to store the lookup table entries | |
8685 | * lut_size: Size of buffer to store the lookup table entries | |
8686 | * | |
8687 | * Returns 0 on success, negative on failure | |
8688 | */ | |
8689 | int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size) | |
8690 | { | |
95a73780 ASJ |
8691 | struct i40e_pf *pf = vsi->back; |
8692 | ||
d36e41dc | 8693 | if (pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) |
95a73780 ASJ |
8694 | return i40e_get_rss_aq(vsi, seed, lut, lut_size); |
8695 | else | |
8696 | return i40e_get_rss_reg(vsi, seed, lut, lut_size); | |
043dd650 HZ |
8697 | } |
8698 | ||
e69ff813 HZ |
8699 | /** |
8700 | * i40e_fill_rss_lut - Fill the RSS lookup table with default values | |
8701 | * @pf: Pointer to board private structure | |
8702 | * @lut: Lookup table | |
8703 | * @rss_table_size: Lookup table size | |
8704 | * @rss_size: Range of queue number for hashing | |
8705 | */ | |
f1582351 AB |
8706 | void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut, |
8707 | u16 rss_table_size, u16 rss_size) | |
e69ff813 HZ |
8708 | { |
8709 | u16 i; | |
8710 | ||
8711 | for (i = 0; i < rss_table_size; i++) | |
8712 | lut[i] = i % rss_size; | |
8713 | } | |
8714 | ||
e25d00b8 | 8715 | /** |
043dd650 | 8716 | * i40e_pf_config_rss - Prepare for RSS if used |
e25d00b8 ASJ |
8717 | * @pf: board private structure |
8718 | **/ | |
043dd650 | 8719 | static int i40e_pf_config_rss(struct i40e_pf *pf) |
e25d00b8 ASJ |
8720 | { |
8721 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; | |
8722 | u8 seed[I40E_HKEY_ARRAY_SIZE]; | |
e69ff813 | 8723 | u8 *lut; |
e25d00b8 ASJ |
8724 | struct i40e_hw *hw = &pf->hw; |
8725 | u32 reg_val; | |
8726 | u64 hena; | |
e69ff813 | 8727 | int ret; |
e25d00b8 | 8728 | |
41c445ff | 8729 | /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */ |
272cdaf2 SN |
8730 | hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) | |
8731 | ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32); | |
e25d00b8 ASJ |
8732 | hena |= i40e_pf_get_default_rss_hena(pf); |
8733 | ||
272cdaf2 SN |
8734 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena); |
8735 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32)); | |
41c445ff | 8736 | |
e25d00b8 | 8737 | /* Determine the RSS table size based on the hardware capabilities */ |
272cdaf2 | 8738 | reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0); |
e25d00b8 ASJ |
8739 | reg_val = (pf->rss_table_size == 512) ? |
8740 | (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) : | |
8741 | (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512); | |
272cdaf2 | 8742 | i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val); |
e157ea30 | 8743 | |
28c5869f | 8744 | /* Determine the RSS size of the VSI */ |
f25571b5 HR |
8745 | if (!vsi->rss_size) { |
8746 | u16 qcount; | |
8747 | ||
8748 | qcount = vsi->num_queue_pairs / vsi->tc_config.numtc; | |
8749 | vsi->rss_size = min_t(int, pf->alloc_rss_size, qcount); | |
8750 | } | |
a4fa59cc MW |
8751 | if (!vsi->rss_size) |
8752 | return -EINVAL; | |
28c5869f | 8753 | |
e69ff813 HZ |
8754 | lut = kzalloc(vsi->rss_table_size, GFP_KERNEL); |
8755 | if (!lut) | |
8756 | return -ENOMEM; | |
8757 | ||
28c5869f HZ |
8758 | /* Use user configured lut if there is one, otherwise use default */ |
8759 | if (vsi->rss_lut_user) | |
8760 | memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size); | |
8761 | else | |
8762 | i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size); | |
e69ff813 | 8763 | |
28c5869f HZ |
8764 | /* Use user configured hash key if there is one, otherwise |
8765 | * use default. | |
8766 | */ | |
8767 | if (vsi->rss_hkey_user) | |
8768 | memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE); | |
8769 | else | |
8770 | netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE); | |
043dd650 | 8771 | ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size); |
e69ff813 HZ |
8772 | kfree(lut); |
8773 | ||
8774 | return ret; | |
41c445ff JB |
8775 | } |
8776 | ||
f8ff1464 ASJ |
8777 | /** |
8778 | * i40e_reconfig_rss_queues - change number of queues for rss and rebuild | |
8779 | * @pf: board private structure | |
8780 | * @queue_count: the requested queue count for rss. | |
8781 | * | |
8782 | * returns 0 if rss is not enabled, if enabled returns the final rss queue | |
8783 | * count which may be different from the requested queue count. | |
373149fc | 8784 | * Note: expects to be called while under rtnl_lock() |
f8ff1464 ASJ |
8785 | **/ |
8786 | int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count) | |
8787 | { | |
9a3bd2f1 ASJ |
8788 | struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi]; |
8789 | int new_rss_size; | |
8790 | ||
f8ff1464 ASJ |
8791 | if (!(pf->flags & I40E_FLAG_RSS_ENABLED)) |
8792 | return 0; | |
8793 | ||
9a3bd2f1 | 8794 | new_rss_size = min_t(int, queue_count, pf->rss_size_max); |
f8ff1464 | 8795 | |
9a3bd2f1 | 8796 | if (queue_count != vsi->num_queue_pairs) { |
f25571b5 HR |
8797 | u16 qcount; |
8798 | ||
9a3bd2f1 | 8799 | vsi->req_queue_pairs = queue_count; |
373149fc | 8800 | i40e_prep_for_reset(pf, true); |
f8ff1464 | 8801 | |
acd65448 | 8802 | pf->alloc_rss_size = new_rss_size; |
f8ff1464 | 8803 | |
373149fc | 8804 | i40e_reset_and_rebuild(pf, true, true); |
28c5869f HZ |
8805 | |
8806 | /* Discard the user configured hash keys and lut, if less | |
8807 | * queues are enabled. | |
8808 | */ | |
8809 | if (queue_count < vsi->rss_size) { | |
8810 | i40e_clear_rss_config_user(vsi); | |
8811 | dev_dbg(&pf->pdev->dev, | |
8812 | "discard user configured hash keys and lut\n"); | |
8813 | } | |
8814 | ||
8815 | /* Reset vsi->rss_size, as number of enabled queues changed */ | |
f25571b5 HR |
8816 | qcount = vsi->num_queue_pairs / vsi->tc_config.numtc; |
8817 | vsi->rss_size = min_t(int, pf->alloc_rss_size, qcount); | |
28c5869f | 8818 | |
043dd650 | 8819 | i40e_pf_config_rss(pf); |
f8ff1464 | 8820 | } |
12815057 LY |
8821 | dev_info(&pf->pdev->dev, "User requested queue count/HW max RSS count: %d/%d\n", |
8822 | vsi->req_queue_pairs, pf->rss_size_max); | |
acd65448 | 8823 | return pf->alloc_rss_size; |
f8ff1464 ASJ |
8824 | } |
8825 | ||
f4492db1 | 8826 | /** |
4fc8c676 | 8827 | * i40e_get_partition_bw_setting - Retrieve BW settings for this PF partition |
f4492db1 GR |
8828 | * @pf: board private structure |
8829 | **/ | |
4fc8c676 | 8830 | i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf) |
f4492db1 GR |
8831 | { |
8832 | i40e_status status; | |
8833 | bool min_valid, max_valid; | |
8834 | u32 max_bw, min_bw; | |
8835 | ||
8836 | status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw, | |
8837 | &min_valid, &max_valid); | |
8838 | ||
8839 | if (!status) { | |
8840 | if (min_valid) | |
4fc8c676 | 8841 | pf->min_bw = min_bw; |
f4492db1 | 8842 | if (max_valid) |
4fc8c676 | 8843 | pf->max_bw = max_bw; |
f4492db1 GR |
8844 | } |
8845 | ||
8846 | return status; | |
8847 | } | |
8848 | ||
8849 | /** | |
4fc8c676 | 8850 | * i40e_set_partition_bw_setting - Set BW settings for this PF partition |
f4492db1 GR |
8851 | * @pf: board private structure |
8852 | **/ | |
4fc8c676 | 8853 | i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf) |
f4492db1 GR |
8854 | { |
8855 | struct i40e_aqc_configure_partition_bw_data bw_data; | |
8856 | i40e_status status; | |
8857 | ||
b40c82e6 | 8858 | /* Set the valid bit for this PF */ |
41a1d04b | 8859 | bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id)); |
4fc8c676 SN |
8860 | bw_data.max_bw[pf->hw.pf_id] = pf->max_bw & I40E_ALT_BW_VALUE_MASK; |
8861 | bw_data.min_bw[pf->hw.pf_id] = pf->min_bw & I40E_ALT_BW_VALUE_MASK; | |
f4492db1 GR |
8862 | |
8863 | /* Set the new bandwidths */ | |
8864 | status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL); | |
8865 | ||
8866 | return status; | |
8867 | } | |
8868 | ||
8869 | /** | |
4fc8c676 | 8870 | * i40e_commit_partition_bw_setting - Commit BW settings for this PF partition |
f4492db1 GR |
8871 | * @pf: board private structure |
8872 | **/ | |
4fc8c676 | 8873 | i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf) |
f4492db1 GR |
8874 | { |
8875 | /* Commit temporary BW setting to permanent NVM image */ | |
8876 | enum i40e_admin_queue_err last_aq_status; | |
8877 | i40e_status ret; | |
8878 | u16 nvm_word; | |
8879 | ||
8880 | if (pf->hw.partition_id != 1) { | |
8881 | dev_info(&pf->pdev->dev, | |
8882 | "Commit BW only works on partition 1! This is partition %d", | |
8883 | pf->hw.partition_id); | |
8884 | ret = I40E_NOT_SUPPORTED; | |
8885 | goto bw_commit_out; | |
8886 | } | |
8887 | ||
8888 | /* Acquire NVM for read access */ | |
8889 | ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ); | |
8890 | last_aq_status = pf->hw.aq.asq_last_status; | |
8891 | if (ret) { | |
8892 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
8893 | "Cannot acquire NVM for read access, err %s aq_err %s\n", |
8894 | i40e_stat_str(&pf->hw, ret), | |
8895 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
8896 | goto bw_commit_out; |
8897 | } | |
8898 | ||
8899 | /* Read word 0x10 of NVM - SW compatibility word 1 */ | |
8900 | ret = i40e_aq_read_nvm(&pf->hw, | |
8901 | I40E_SR_NVM_CONTROL_WORD, | |
8902 | 0x10, sizeof(nvm_word), &nvm_word, | |
8903 | false, NULL); | |
8904 | /* Save off last admin queue command status before releasing | |
8905 | * the NVM | |
8906 | */ | |
8907 | last_aq_status = pf->hw.aq.asq_last_status; | |
8908 | i40e_release_nvm(&pf->hw); | |
8909 | if (ret) { | |
f1c7e72e SN |
8910 | dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n", |
8911 | i40e_stat_str(&pf->hw, ret), | |
8912 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
8913 | goto bw_commit_out; |
8914 | } | |
8915 | ||
8916 | /* Wait a bit for NVM release to complete */ | |
8917 | msleep(50); | |
8918 | ||
8919 | /* Acquire NVM for write access */ | |
8920 | ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE); | |
8921 | last_aq_status = pf->hw.aq.asq_last_status; | |
8922 | if (ret) { | |
8923 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
8924 | "Cannot acquire NVM for write access, err %s aq_err %s\n", |
8925 | i40e_stat_str(&pf->hw, ret), | |
8926 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
8927 | goto bw_commit_out; |
8928 | } | |
8929 | /* Write it back out unchanged to initiate update NVM, | |
8930 | * which will force a write of the shadow (alt) RAM to | |
8931 | * the NVM - thus storing the bandwidth values permanently. | |
8932 | */ | |
8933 | ret = i40e_aq_update_nvm(&pf->hw, | |
8934 | I40E_SR_NVM_CONTROL_WORD, | |
8935 | 0x10, sizeof(nvm_word), | |
8936 | &nvm_word, true, NULL); | |
8937 | /* Save off last admin queue command status before releasing | |
8938 | * the NVM | |
8939 | */ | |
8940 | last_aq_status = pf->hw.aq.asq_last_status; | |
8941 | i40e_release_nvm(&pf->hw); | |
8942 | if (ret) | |
8943 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
8944 | "BW settings NOT SAVED, err %s aq_err %s\n", |
8945 | i40e_stat_str(&pf->hw, ret), | |
8946 | i40e_aq_str(&pf->hw, last_aq_status)); | |
f4492db1 GR |
8947 | bw_commit_out: |
8948 | ||
8949 | return ret; | |
8950 | } | |
8951 | ||
41c445ff JB |
8952 | /** |
8953 | * i40e_sw_init - Initialize general software structures (struct i40e_pf) | |
8954 | * @pf: board private structure to initialize | |
8955 | * | |
8956 | * i40e_sw_init initializes the Adapter private data structure. | |
8957 | * Fields are initialized based on PCI device information and | |
8958 | * OS network device settings (MTU size). | |
8959 | **/ | |
8960 | static int i40e_sw_init(struct i40e_pf *pf) | |
8961 | { | |
8962 | int err = 0; | |
8963 | int size; | |
8964 | ||
41c445ff JB |
8965 | /* Set default capability flags */ |
8966 | pf->flags = I40E_FLAG_RX_CSUM_ENABLED | | |
8967 | I40E_FLAG_MSI_ENABLED | | |
2bc7ee8a MW |
8968 | I40E_FLAG_MSIX_ENABLED; |
8969 | ||
ca99eb99 MW |
8970 | /* Set default ITR */ |
8971 | pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF; | |
8972 | pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF; | |
8973 | ||
7134f9ce JB |
8974 | /* Depending on PF configurations, it is possible that the RSS |
8975 | * maximum might end up larger than the available queues | |
8976 | */ | |
41a1d04b | 8977 | pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width); |
acd65448 | 8978 | pf->alloc_rss_size = 1; |
5db4cb59 | 8979 | pf->rss_table_size = pf->hw.func_caps.rss_table_size; |
7134f9ce JB |
8980 | pf->rss_size_max = min_t(int, pf->rss_size_max, |
8981 | pf->hw.func_caps.num_tx_qp); | |
41c445ff JB |
8982 | if (pf->hw.func_caps.rss) { |
8983 | pf->flags |= I40E_FLAG_RSS_ENABLED; | |
acd65448 HZ |
8984 | pf->alloc_rss_size = min_t(int, pf->rss_size_max, |
8985 | num_online_cpus()); | |
41c445ff JB |
8986 | } |
8987 | ||
2050bc65 | 8988 | /* MFP mode enabled */ |
c78b953e | 8989 | if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) { |
2050bc65 CS |
8990 | pf->flags |= I40E_FLAG_MFP_ENABLED; |
8991 | dev_info(&pf->pdev->dev, "MFP mode Enabled\n"); | |
4fc8c676 | 8992 | if (i40e_get_partition_bw_setting(pf)) { |
f4492db1 | 8993 | dev_warn(&pf->pdev->dev, |
4fc8c676 SN |
8994 | "Could not get partition bw settings\n"); |
8995 | } else { | |
f4492db1 | 8996 | dev_info(&pf->pdev->dev, |
4fc8c676 SN |
8997 | "Partition BW Min = %8.8x, Max = %8.8x\n", |
8998 | pf->min_bw, pf->max_bw); | |
8999 | ||
9000 | /* nudge the Tx scheduler */ | |
9001 | i40e_set_partition_bw_setting(pf); | |
9002 | } | |
2050bc65 CS |
9003 | } |
9004 | ||
cbf61325 ASJ |
9005 | if ((pf->hw.func_caps.fd_filters_guaranteed > 0) || |
9006 | (pf->hw.func_caps.fd_filters_best_effort > 0)) { | |
9007 | pf->flags |= I40E_FLAG_FD_ATR_ENABLED; | |
9008 | pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE; | |
6eae9c6a SN |
9009 | if (pf->flags & I40E_FLAG_MFP_ENABLED && |
9010 | pf->hw.num_partitions > 1) | |
cbf61325 | 9011 | dev_info(&pf->pdev->dev, |
0b67584f | 9012 | "Flow Director Sideband mode Disabled in MFP mode\n"); |
6eae9c6a SN |
9013 | else |
9014 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
cbf61325 ASJ |
9015 | pf->fdir_pf_filter_count = |
9016 | pf->hw.func_caps.fd_filters_guaranteed; | |
9017 | pf->hw.fdir_shared_filter_count = | |
9018 | pf->hw.func_caps.fd_filters_best_effort; | |
41c445ff JB |
9019 | } |
9020 | ||
5a433199 | 9021 | if (pf->hw.mac.type == I40E_MAC_X722) { |
d36e41dc JK |
9022 | pf->hw_features |= (I40E_HW_RSS_AQ_CAPABLE | |
9023 | I40E_HW_128_QP_RSS_CAPABLE | | |
9024 | I40E_HW_ATR_EVICT_CAPABLE | | |
9025 | I40E_HW_WB_ON_ITR_CAPABLE | | |
9026 | I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE | | |
9027 | I40E_HW_NO_PCI_LINK_CHECK | | |
9028 | I40E_HW_USE_SET_LLDP_MIB | | |
9029 | I40E_HW_GENEVE_OFFLOAD_CAPABLE | | |
9030 | I40E_HW_PTP_L4_CAPABLE | | |
9031 | I40E_HW_WOL_MC_MAGIC_PKT_WAKE | | |
9032 | I40E_HW_OUTER_UDP_CSUM_CAPABLE); | |
10a955ff ASJ |
9033 | |
9034 | #define I40E_FDEVICT_PCTYPE_DEFAULT 0xc03 | |
9035 | if (rd32(&pf->hw, I40E_GLQF_FDEVICTENA(1)) != | |
9036 | I40E_FDEVICT_PCTYPE_DEFAULT) { | |
9037 | dev_warn(&pf->pdev->dev, | |
9038 | "FD EVICT PCTYPES are not right, disable FD HW EVICT\n"); | |
9039 | pf->hw_features &= ~I40E_HW_ATR_EVICT_CAPABLE; | |
9040 | } | |
5a433199 ASJ |
9041 | } else if ((pf->hw.aq.api_maj_ver > 1) || |
9042 | ((pf->hw.aq.api_maj_ver == 1) && | |
9043 | (pf->hw.aq.api_min_ver > 4))) { | |
9044 | /* Supported in FW API version higher than 1.4 */ | |
d36e41dc | 9045 | pf->hw_features |= I40E_HW_GENEVE_OFFLOAD_CAPABLE; |
5a433199 ASJ |
9046 | } |
9047 | ||
9048 | /* Enable HW ATR eviction if possible */ | |
d36e41dc | 9049 | if (pf->hw_features & I40E_HW_ATR_EVICT_CAPABLE) |
5a433199 ASJ |
9050 | pf->flags |= I40E_FLAG_HW_ATR_EVICT_ENABLED; |
9051 | ||
6de432c5 | 9052 | if ((pf->hw.mac.type == I40E_MAC_XL710) && |
8eed76fa | 9053 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) || |
f1bbad33 | 9054 | (pf->hw.aq.fw_maj_ver < 4))) { |
d36e41dc | 9055 | pf->hw_features |= I40E_HW_RESTART_AUTONEG; |
f1bbad33 | 9056 | /* No DCB support for FW < v4.33 */ |
d36e41dc | 9057 | pf->hw_features |= I40E_HW_NO_DCB_SUPPORT; |
f1bbad33 NP |
9058 | } |
9059 | ||
9060 | /* Disable FW LLDP if FW < v4.3 */ | |
6de432c5 | 9061 | if ((pf->hw.mac.type == I40E_MAC_XL710) && |
f1bbad33 NP |
9062 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) || |
9063 | (pf->hw.aq.fw_maj_ver < 4))) | |
d36e41dc | 9064 | pf->hw_features |= I40E_HW_STOP_FW_LLDP; |
f1bbad33 NP |
9065 | |
9066 | /* Use the FW Set LLDP MIB API if FW > v4.40 */ | |
6de432c5 | 9067 | if ((pf->hw.mac.type == I40E_MAC_XL710) && |
f1bbad33 NP |
9068 | (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) || |
9069 | (pf->hw.aq.fw_maj_ver >= 5))) | |
d36e41dc | 9070 | pf->hw_features |= I40E_HW_USE_SET_LLDP_MIB; |
8eed76fa | 9071 | |
c3d26b75 AB |
9072 | /* Enable PTP L4 if FW > v6.0 */ |
9073 | if (pf->hw.mac.type == I40E_MAC_XL710 && | |
9074 | pf->hw.aq.fw_maj_ver >= 6) | |
9075 | pf->hw_features |= I40E_HW_PTP_L4_CAPABLE; | |
9076 | ||
41c445ff | 9077 | if (pf->hw.func_caps.vmdq) { |
41c445ff | 9078 | pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI; |
e25d00b8 | 9079 | pf->flags |= I40E_FLAG_VMDQ_ENABLED; |
e9e53662 | 9080 | pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf); |
41c445ff JB |
9081 | } |
9082 | ||
e3219ce6 ASJ |
9083 | if (pf->hw.func_caps.iwarp) { |
9084 | pf->flags |= I40E_FLAG_IWARP_ENABLED; | |
9085 | /* IWARP needs one extra vector for CQP just like MISC.*/ | |
9086 | pf->num_iwarp_msix = (int)num_online_cpus() + 1; | |
9087 | } | |
9088 | ||
41c445ff | 9089 | #ifdef CONFIG_PCI_IOV |
ba252f13 | 9090 | if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) { |
41c445ff JB |
9091 | pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF; |
9092 | pf->flags |= I40E_FLAG_SRIOV_ENABLED; | |
9093 | pf->num_req_vfs = min_t(int, | |
9094 | pf->hw.func_caps.num_vfs, | |
9095 | I40E_MAX_VF_COUNT); | |
9096 | } | |
9097 | #endif /* CONFIG_PCI_IOV */ | |
9098 | pf->eeprom_version = 0xDEAD; | |
9099 | pf->lan_veb = I40E_NO_VEB; | |
9100 | pf->lan_vsi = I40E_NO_VSI; | |
9101 | ||
d1a8d275 ASJ |
9102 | /* By default FW has this off for performance reasons */ |
9103 | pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED; | |
9104 | ||
41c445ff JB |
9105 | /* set up queue assignment tracking */ |
9106 | size = sizeof(struct i40e_lump_tracking) | |
9107 | + (sizeof(u16) * pf->hw.func_caps.num_tx_qp); | |
9108 | pf->qp_pile = kzalloc(size, GFP_KERNEL); | |
9109 | if (!pf->qp_pile) { | |
9110 | err = -ENOMEM; | |
9111 | goto sw_init_done; | |
9112 | } | |
9113 | pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp; | |
9114 | pf->qp_pile->search_hint = 0; | |
9115 | ||
327fe04b ASJ |
9116 | pf->tx_timeout_recovery_level = 1; |
9117 | ||
41c445ff JB |
9118 | mutex_init(&pf->switch_mutex); |
9119 | ||
9120 | sw_init_done: | |
9121 | return err; | |
9122 | } | |
9123 | ||
7c3c288b ASJ |
9124 | /** |
9125 | * i40e_set_ntuple - set the ntuple feature flag and take action | |
9126 | * @pf: board private structure to initialize | |
9127 | * @features: the feature set that the stack is suggesting | |
9128 | * | |
9129 | * returns a bool to indicate if reset needs to happen | |
9130 | **/ | |
9131 | bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features) | |
9132 | { | |
9133 | bool need_reset = false; | |
9134 | ||
9135 | /* Check if Flow Director n-tuple support was enabled or disabled. If | |
9136 | * the state changed, we need to reset. | |
9137 | */ | |
9138 | if (features & NETIF_F_NTUPLE) { | |
9139 | /* Enable filters and mark for reset */ | |
9140 | if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED)) | |
9141 | need_reset = true; | |
a70e407f TD |
9142 | /* enable FD_SB only if there is MSI-X vector */ |
9143 | if (pf->num_fdsb_msix > 0) | |
9144 | pf->flags |= I40E_FLAG_FD_SB_ENABLED; | |
7c3c288b ASJ |
9145 | } else { |
9146 | /* turn off filters, mark for reset and clear SW filter list */ | |
9147 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
9148 | need_reset = true; | |
9149 | i40e_fdir_filter_exit(pf); | |
9150 | } | |
47994c11 JK |
9151 | pf->flags &= ~(I40E_FLAG_FD_SB_ENABLED | |
9152 | I40E_FLAG_FD_SB_AUTO_DISABLED); | |
1e1be8f6 | 9153 | /* reset fd counters */ |
097dbf52 JK |
9154 | pf->fd_add_err = 0; |
9155 | pf->fd_atr_cnt = 0; | |
8a4f34fb | 9156 | /* if ATR was auto disabled it can be re-enabled. */ |
47994c11 JK |
9157 | if (pf->flags & I40E_FLAG_FD_ATR_AUTO_DISABLED) { |
9158 | pf->flags &= ~I40E_FLAG_FD_ATR_AUTO_DISABLED; | |
9159 | if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) && | |
9160 | (I40E_DEBUG_FD & pf->hw.debug_mask)) | |
234dc4e6 JK |
9161 | dev_info(&pf->pdev->dev, "ATR re-enabled.\n"); |
9162 | } | |
7c3c288b ASJ |
9163 | } |
9164 | return need_reset; | |
9165 | } | |
9166 | ||
d8ec9864 AB |
9167 | /** |
9168 | * i40e_clear_rss_lut - clear the rx hash lookup table | |
9169 | * @vsi: the VSI being configured | |
9170 | **/ | |
9171 | static void i40e_clear_rss_lut(struct i40e_vsi *vsi) | |
9172 | { | |
9173 | struct i40e_pf *pf = vsi->back; | |
9174 | struct i40e_hw *hw = &pf->hw; | |
9175 | u16 vf_id = vsi->vf_id; | |
9176 | u8 i; | |
9177 | ||
9178 | if (vsi->type == I40E_VSI_MAIN) { | |
9179 | for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++) | |
9180 | wr32(hw, I40E_PFQF_HLUT(i), 0); | |
9181 | } else if (vsi->type == I40E_VSI_SRIOV) { | |
9182 | for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++) | |
9183 | i40e_write_rx_ctl(hw, I40E_VFQF_HLUT1(i, vf_id), 0); | |
9184 | } else { | |
9185 | dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n"); | |
9186 | } | |
9187 | } | |
9188 | ||
41c445ff JB |
9189 | /** |
9190 | * i40e_set_features - set the netdev feature flags | |
9191 | * @netdev: ptr to the netdev being adjusted | |
9192 | * @features: the feature set that the stack is suggesting | |
373149fc | 9193 | * Note: expects to be called while under rtnl_lock() |
41c445ff JB |
9194 | **/ |
9195 | static int i40e_set_features(struct net_device *netdev, | |
9196 | netdev_features_t features) | |
9197 | { | |
9198 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
9199 | struct i40e_vsi *vsi = np->vsi; | |
7c3c288b ASJ |
9200 | struct i40e_pf *pf = vsi->back; |
9201 | bool need_reset; | |
41c445ff | 9202 | |
d8ec9864 AB |
9203 | if (features & NETIF_F_RXHASH && !(netdev->features & NETIF_F_RXHASH)) |
9204 | i40e_pf_config_rss(pf); | |
9205 | else if (!(features & NETIF_F_RXHASH) && | |
9206 | netdev->features & NETIF_F_RXHASH) | |
9207 | i40e_clear_rss_lut(vsi); | |
9208 | ||
41c445ff JB |
9209 | if (features & NETIF_F_HW_VLAN_CTAG_RX) |
9210 | i40e_vlan_stripping_enable(vsi); | |
9211 | else | |
9212 | i40e_vlan_stripping_disable(vsi); | |
9213 | ||
7c3c288b ASJ |
9214 | need_reset = i40e_set_ntuple(pf, features); |
9215 | ||
9216 | if (need_reset) | |
373149fc | 9217 | i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED), true); |
7c3c288b | 9218 | |
41c445ff JB |
9219 | return 0; |
9220 | } | |
9221 | ||
a1c9a9d9 | 9222 | /** |
6a899024 | 9223 | * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port |
a1c9a9d9 JK |
9224 | * @pf: board private structure |
9225 | * @port: The UDP port to look up | |
9226 | * | |
9227 | * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found | |
9228 | **/ | |
fe0b0cd9 | 9229 | static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, u16 port) |
a1c9a9d9 JK |
9230 | { |
9231 | u8 i; | |
9232 | ||
9233 | for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) { | |
27826fd5 | 9234 | if (pf->udp_ports[i].port == port) |
a1c9a9d9 JK |
9235 | return i; |
9236 | } | |
9237 | ||
9238 | return i; | |
9239 | } | |
9240 | ||
9241 | /** | |
06a5f7f1 | 9242 | * i40e_udp_tunnel_add - Get notifications about UDP tunnel ports that come up |
a1c9a9d9 | 9243 | * @netdev: This physical port's netdev |
06a5f7f1 | 9244 | * @ti: Tunnel endpoint information |
a1c9a9d9 | 9245 | **/ |
06a5f7f1 AD |
9246 | static void i40e_udp_tunnel_add(struct net_device *netdev, |
9247 | struct udp_tunnel_info *ti) | |
a1c9a9d9 JK |
9248 | { |
9249 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
9250 | struct i40e_vsi *vsi = np->vsi; | |
9251 | struct i40e_pf *pf = vsi->back; | |
fe0b0cd9 | 9252 | u16 port = ntohs(ti->port); |
a1c9a9d9 JK |
9253 | u8 next_idx; |
9254 | u8 idx; | |
9255 | ||
6a899024 | 9256 | idx = i40e_get_udp_port_idx(pf, port); |
a1c9a9d9 JK |
9257 | |
9258 | /* Check if port already exists */ | |
9259 | if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) { | |
fe0b0cd9 | 9260 | netdev_info(netdev, "port %d already offloaded\n", port); |
a1c9a9d9 JK |
9261 | return; |
9262 | } | |
9263 | ||
9264 | /* Now check if there is space to add the new port */ | |
6a899024 | 9265 | next_idx = i40e_get_udp_port_idx(pf, 0); |
a1c9a9d9 JK |
9266 | |
9267 | if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) { | |
06a5f7f1 | 9268 | netdev_info(netdev, "maximum number of offloaded UDP ports reached, not adding port %d\n", |
fe0b0cd9 | 9269 | port); |
6a899024 SA |
9270 | return; |
9271 | } | |
9272 | ||
06a5f7f1 AD |
9273 | switch (ti->type) { |
9274 | case UDP_TUNNEL_TYPE_VXLAN: | |
9275 | pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN; | |
9276 | break; | |
9277 | case UDP_TUNNEL_TYPE_GENEVE: | |
d36e41dc | 9278 | if (!(pf->hw_features & I40E_HW_GENEVE_OFFLOAD_CAPABLE)) |
06a5f7f1 AD |
9279 | return; |
9280 | pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE; | |
9281 | break; | |
9282 | default: | |
6a899024 SA |
9283 | return; |
9284 | } | |
9285 | ||
9286 | /* New port: add it and mark its index in the bitmap */ | |
27826fd5 | 9287 | pf->udp_ports[next_idx].port = port; |
6a899024 SA |
9288 | pf->pending_udp_bitmap |= BIT_ULL(next_idx); |
9289 | pf->flags |= I40E_FLAG_UDP_FILTER_SYNC; | |
a1c9a9d9 JK |
9290 | } |
9291 | ||
6a899024 | 9292 | /** |
06a5f7f1 | 9293 | * i40e_udp_tunnel_del - Get notifications about UDP tunnel ports that go away |
6a899024 | 9294 | * @netdev: This physical port's netdev |
06a5f7f1 | 9295 | * @ti: Tunnel endpoint information |
6a899024 | 9296 | **/ |
06a5f7f1 AD |
9297 | static void i40e_udp_tunnel_del(struct net_device *netdev, |
9298 | struct udp_tunnel_info *ti) | |
6a899024 | 9299 | { |
6a899024 SA |
9300 | struct i40e_netdev_priv *np = netdev_priv(netdev); |
9301 | struct i40e_vsi *vsi = np->vsi; | |
9302 | struct i40e_pf *pf = vsi->back; | |
fe0b0cd9 | 9303 | u16 port = ntohs(ti->port); |
6a899024 SA |
9304 | u8 idx; |
9305 | ||
6a899024 SA |
9306 | idx = i40e_get_udp_port_idx(pf, port); |
9307 | ||
9308 | /* Check if port already exists */ | |
06a5f7f1 AD |
9309 | if (idx >= I40E_MAX_PF_UDP_OFFLOAD_PORTS) |
9310 | goto not_found; | |
6a899024 | 9311 | |
06a5f7f1 AD |
9312 | switch (ti->type) { |
9313 | case UDP_TUNNEL_TYPE_VXLAN: | |
9314 | if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_VXLAN) | |
9315 | goto not_found; | |
9316 | break; | |
9317 | case UDP_TUNNEL_TYPE_GENEVE: | |
9318 | if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_NGE) | |
9319 | goto not_found; | |
9320 | break; | |
9321 | default: | |
9322 | goto not_found; | |
6a899024 | 9323 | } |
06a5f7f1 AD |
9324 | |
9325 | /* if port exists, set it to 0 (mark for deletion) | |
9326 | * and make it pending | |
9327 | */ | |
27826fd5 | 9328 | pf->udp_ports[idx].port = 0; |
06a5f7f1 AD |
9329 | pf->pending_udp_bitmap |= BIT_ULL(idx); |
9330 | pf->flags |= I40E_FLAG_UDP_FILTER_SYNC; | |
9331 | ||
9332 | return; | |
9333 | not_found: | |
9334 | netdev_warn(netdev, "UDP port %d was not found, not deleting\n", | |
fe0b0cd9 | 9335 | port); |
6a899024 SA |
9336 | } |
9337 | ||
1f224ad2 | 9338 | static int i40e_get_phys_port_id(struct net_device *netdev, |
02637fce | 9339 | struct netdev_phys_item_id *ppid) |
1f224ad2 NP |
9340 | { |
9341 | struct i40e_netdev_priv *np = netdev_priv(netdev); | |
9342 | struct i40e_pf *pf = np->vsi->back; | |
9343 | struct i40e_hw *hw = &pf->hw; | |
9344 | ||
d36e41dc | 9345 | if (!(pf->hw_features & I40E_HW_PORT_ID_VALID)) |
1f224ad2 NP |
9346 | return -EOPNOTSUPP; |
9347 | ||
9348 | ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id)); | |
9349 | memcpy(ppid->id, hw->mac.port_addr, ppid->id_len); | |
9350 | ||
9351 | return 0; | |
9352 | } | |
9353 | ||
2f90ade6 JB |
9354 | /** |
9355 | * i40e_ndo_fdb_add - add an entry to the hardware database | |
9356 | * @ndm: the input from the stack | |
9357 | * @tb: pointer to array of nladdr (unused) | |
9358 | * @dev: the net device pointer | |
9359 | * @addr: the MAC address entry being added | |
9360 | * @flags: instructions from stack about fdb operation | |
9361 | */ | |
4ba0dea5 GR |
9362 | static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[], |
9363 | struct net_device *dev, | |
f6f6424b | 9364 | const unsigned char *addr, u16 vid, |
4ba0dea5 | 9365 | u16 flags) |
4ba0dea5 GR |
9366 | { |
9367 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
9368 | struct i40e_pf *pf = np->vsi->back; | |
9369 | int err = 0; | |
9370 | ||
9371 | if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED)) | |
9372 | return -EOPNOTSUPP; | |
9373 | ||
65891fea OG |
9374 | if (vid) { |
9375 | pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name); | |
9376 | return -EINVAL; | |
9377 | } | |
9378 | ||
4ba0dea5 GR |
9379 | /* Hardware does not support aging addresses so if a |
9380 | * ndm_state is given only allow permanent addresses | |
9381 | */ | |
9382 | if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) { | |
9383 | netdev_info(dev, "FDB only supports static addresses\n"); | |
9384 | return -EINVAL; | |
9385 | } | |
9386 | ||
9387 | if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) | |
9388 | err = dev_uc_add_excl(dev, addr); | |
9389 | else if (is_multicast_ether_addr(addr)) | |
9390 | err = dev_mc_add_excl(dev, addr); | |
9391 | else | |
9392 | err = -EINVAL; | |
9393 | ||
9394 | /* Only return duplicate errors if NLM_F_EXCL is set */ | |
9395 | if (err == -EEXIST && !(flags & NLM_F_EXCL)) | |
9396 | err = 0; | |
9397 | ||
9398 | return err; | |
9399 | } | |
9400 | ||
51616018 NP |
9401 | /** |
9402 | * i40e_ndo_bridge_setlink - Set the hardware bridge mode | |
9403 | * @dev: the netdev being configured | |
9404 | * @nlh: RTNL message | |
9405 | * | |
9406 | * Inserts a new hardware bridge if not already created and | |
9407 | * enables the bridging mode requested (VEB or VEPA). If the | |
9408 | * hardware bridge has already been inserted and the request | |
9409 | * is to change the mode then that requires a PF reset to | |
9410 | * allow rebuild of the components with required hardware | |
9411 | * bridge mode enabled. | |
373149fc MS |
9412 | * |
9413 | * Note: expects to be called while under rtnl_lock() | |
51616018 NP |
9414 | **/ |
9415 | static int i40e_ndo_bridge_setlink(struct net_device *dev, | |
9df70b66 CW |
9416 | struct nlmsghdr *nlh, |
9417 | u16 flags) | |
51616018 NP |
9418 | { |
9419 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
9420 | struct i40e_vsi *vsi = np->vsi; | |
9421 | struct i40e_pf *pf = vsi->back; | |
9422 | struct i40e_veb *veb = NULL; | |
9423 | struct nlattr *attr, *br_spec; | |
9424 | int i, rem; | |
9425 | ||
9426 | /* Only for PF VSI for now */ | |
9427 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) | |
9428 | return -EOPNOTSUPP; | |
9429 | ||
9430 | /* Find the HW bridge for PF VSI */ | |
9431 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { | |
9432 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
9433 | veb = pf->veb[i]; | |
9434 | } | |
9435 | ||
9436 | br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC); | |
9437 | ||
9438 | nla_for_each_nested(attr, br_spec, rem) { | |
9439 | __u16 mode; | |
9440 | ||
9441 | if (nla_type(attr) != IFLA_BRIDGE_MODE) | |
9442 | continue; | |
9443 | ||
9444 | mode = nla_get_u16(attr); | |
9445 | if ((mode != BRIDGE_MODE_VEPA) && | |
9446 | (mode != BRIDGE_MODE_VEB)) | |
9447 | return -EINVAL; | |
9448 | ||
9449 | /* Insert a new HW bridge */ | |
9450 | if (!veb) { | |
9451 | veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, | |
9452 | vsi->tc_config.enabled_tc); | |
9453 | if (veb) { | |
9454 | veb->bridge_mode = mode; | |
9455 | i40e_config_bridge_mode(veb); | |
9456 | } else { | |
9457 | /* No Bridge HW offload available */ | |
9458 | return -ENOENT; | |
9459 | } | |
9460 | break; | |
9461 | } else if (mode != veb->bridge_mode) { | |
9462 | /* Existing HW bridge but different mode needs reset */ | |
9463 | veb->bridge_mode = mode; | |
fc60861e ASJ |
9464 | /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */ |
9465 | if (mode == BRIDGE_MODE_VEB) | |
9466 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
9467 | else | |
9468 | pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; | |
373149fc MS |
9469 | i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED), |
9470 | true); | |
51616018 NP |
9471 | break; |
9472 | } | |
9473 | } | |
9474 | ||
9475 | return 0; | |
9476 | } | |
9477 | ||
9478 | /** | |
9479 | * i40e_ndo_bridge_getlink - Get the hardware bridge mode | |
9480 | * @skb: skb buff | |
9481 | * @pid: process id | |
9482 | * @seq: RTNL message seq # | |
9483 | * @dev: the netdev being configured | |
9484 | * @filter_mask: unused | |
d4b2f9fe | 9485 | * @nlflags: netlink flags passed in |
51616018 NP |
9486 | * |
9487 | * Return the mode in which the hardware bridge is operating in | |
9488 | * i.e VEB or VEPA. | |
9489 | **/ | |
51616018 NP |
9490 | static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq, |
9491 | struct net_device *dev, | |
9f4ffc44 CW |
9492 | u32 __always_unused filter_mask, |
9493 | int nlflags) | |
51616018 NP |
9494 | { |
9495 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
9496 | struct i40e_vsi *vsi = np->vsi; | |
9497 | struct i40e_pf *pf = vsi->back; | |
9498 | struct i40e_veb *veb = NULL; | |
9499 | int i; | |
9500 | ||
9501 | /* Only for PF VSI for now */ | |
9502 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) | |
9503 | return -EOPNOTSUPP; | |
9504 | ||
9505 | /* Find the HW bridge for the PF VSI */ | |
9506 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { | |
9507 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
9508 | veb = pf->veb[i]; | |
9509 | } | |
9510 | ||
9511 | if (!veb) | |
9512 | return 0; | |
9513 | ||
46c264da | 9514 | return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode, |
599b076d | 9515 | 0, 0, nlflags, filter_mask, NULL); |
51616018 | 9516 | } |
51616018 | 9517 | |
f44a75e2 JS |
9518 | /** |
9519 | * i40e_features_check - Validate encapsulated packet conforms to limits | |
9520 | * @skb: skb buff | |
2bc11c63 | 9521 | * @dev: This physical port's netdev |
f44a75e2 JS |
9522 | * @features: Offload features that the stack believes apply |
9523 | **/ | |
9524 | static netdev_features_t i40e_features_check(struct sk_buff *skb, | |
9525 | struct net_device *dev, | |
9526 | netdev_features_t features) | |
9527 | { | |
f114dca2 AD |
9528 | size_t len; |
9529 | ||
9530 | /* No point in doing any of this if neither checksum nor GSO are | |
9531 | * being requested for this frame. We can rule out both by just | |
9532 | * checking for CHECKSUM_PARTIAL | |
9533 | */ | |
9534 | if (skb->ip_summed != CHECKSUM_PARTIAL) | |
9535 | return features; | |
9536 | ||
9537 | /* We cannot support GSO if the MSS is going to be less than | |
9538 | * 64 bytes. If it is then we need to drop support for GSO. | |
9539 | */ | |
9540 | if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_size < 64)) | |
9541 | features &= ~NETIF_F_GSO_MASK; | |
9542 | ||
9543 | /* MACLEN can support at most 63 words */ | |
9544 | len = skb_network_header(skb) - skb->data; | |
9545 | if (len & ~(63 * 2)) | |
9546 | goto out_err; | |
9547 | ||
9548 | /* IPLEN and EIPLEN can support at most 127 dwords */ | |
9549 | len = skb_transport_header(skb) - skb_network_header(skb); | |
9550 | if (len & ~(127 * 4)) | |
9551 | goto out_err; | |
9552 | ||
9553 | if (skb->encapsulation) { | |
9554 | /* L4TUNLEN can support 127 words */ | |
9555 | len = skb_inner_network_header(skb) - skb_transport_header(skb); | |
9556 | if (len & ~(127 * 2)) | |
9557 | goto out_err; | |
9558 | ||
9559 | /* IPLEN can support at most 127 dwords */ | |
9560 | len = skb_inner_transport_header(skb) - | |
9561 | skb_inner_network_header(skb); | |
9562 | if (len & ~(127 * 4)) | |
9563 | goto out_err; | |
9564 | } | |
9565 | ||
9566 | /* No need to validate L4LEN as TCP is the only protocol with a | |
9567 | * a flexible value and we support all possible values supported | |
9568 | * by TCP, which is at most 15 dwords | |
9569 | */ | |
f44a75e2 JS |
9570 | |
9571 | return features; | |
f114dca2 AD |
9572 | out_err: |
9573 | return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); | |
f44a75e2 JS |
9574 | } |
9575 | ||
0c8493d9 BT |
9576 | /** |
9577 | * i40e_xdp_setup - add/remove an XDP program | |
9578 | * @vsi: VSI to changed | |
9579 | * @prog: XDP program | |
9580 | **/ | |
9581 | static int i40e_xdp_setup(struct i40e_vsi *vsi, | |
9582 | struct bpf_prog *prog) | |
9583 | { | |
9584 | int frame_size = vsi->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; | |
9585 | struct i40e_pf *pf = vsi->back; | |
9586 | struct bpf_prog *old_prog; | |
9587 | bool need_reset; | |
9588 | int i; | |
9589 | ||
9590 | /* Don't allow frames that span over multiple buffers */ | |
9591 | if (frame_size > vsi->rx_buf_len) | |
9592 | return -EINVAL; | |
9593 | ||
9594 | if (!i40e_enabled_xdp_vsi(vsi) && !prog) | |
9595 | return 0; | |
9596 | ||
9597 | /* When turning XDP on->off/off->on we reset and rebuild the rings. */ | |
9598 | need_reset = (i40e_enabled_xdp_vsi(vsi) != !!prog); | |
9599 | ||
9600 | if (need_reset) | |
9601 | i40e_prep_for_reset(pf, true); | |
9602 | ||
9603 | old_prog = xchg(&vsi->xdp_prog, prog); | |
9604 | ||
9605 | if (need_reset) | |
9606 | i40e_reset_and_rebuild(pf, true, true); | |
9607 | ||
9608 | for (i = 0; i < vsi->num_queue_pairs; i++) | |
9609 | WRITE_ONCE(vsi->rx_rings[i]->xdp_prog, vsi->xdp_prog); | |
9610 | ||
9611 | if (old_prog) | |
9612 | bpf_prog_put(old_prog); | |
9613 | ||
9614 | return 0; | |
9615 | } | |
9616 | ||
9617 | /** | |
9618 | * i40e_xdp - implements ndo_xdp for i40e | |
9619 | * @dev: netdevice | |
9620 | * @xdp: XDP command | |
9621 | **/ | |
9622 | static int i40e_xdp(struct net_device *dev, | |
9623 | struct netdev_xdp *xdp) | |
9624 | { | |
9625 | struct i40e_netdev_priv *np = netdev_priv(dev); | |
9626 | struct i40e_vsi *vsi = np->vsi; | |
9627 | ||
9628 | if (vsi->type != I40E_VSI_MAIN) | |
9629 | return -EINVAL; | |
9630 | ||
9631 | switch (xdp->command) { | |
9632 | case XDP_SETUP_PROG: | |
9633 | return i40e_xdp_setup(vsi, xdp->prog); | |
9634 | case XDP_QUERY_PROG: | |
9635 | xdp->prog_attached = i40e_enabled_xdp_vsi(vsi); | |
eb23039f | 9636 | xdp->prog_id = vsi->xdp_prog ? vsi->xdp_prog->aux->id : 0; |
0c8493d9 BT |
9637 | return 0; |
9638 | default: | |
9639 | return -EINVAL; | |
9640 | } | |
9641 | } | |
9642 | ||
37a2973a | 9643 | static const struct net_device_ops i40e_netdev_ops = { |
41c445ff JB |
9644 | .ndo_open = i40e_open, |
9645 | .ndo_stop = i40e_close, | |
9646 | .ndo_start_xmit = i40e_lan_xmit_frame, | |
9647 | .ndo_get_stats64 = i40e_get_netdev_stats_struct, | |
9648 | .ndo_set_rx_mode = i40e_set_rx_mode, | |
9649 | .ndo_validate_addr = eth_validate_addr, | |
9650 | .ndo_set_mac_address = i40e_set_mac, | |
9651 | .ndo_change_mtu = i40e_change_mtu, | |
beb0dff1 | 9652 | .ndo_do_ioctl = i40e_ioctl, |
41c445ff JB |
9653 | .ndo_tx_timeout = i40e_tx_timeout, |
9654 | .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid, | |
9655 | .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid, | |
9656 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
9657 | .ndo_poll_controller = i40e_netpoll, | |
9658 | #endif | |
e4c6734e | 9659 | .ndo_setup_tc = __i40e_setup_tc, |
41c445ff JB |
9660 | .ndo_set_features = i40e_set_features, |
9661 | .ndo_set_vf_mac = i40e_ndo_set_vf_mac, | |
9662 | .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan, | |
ed616689 | 9663 | .ndo_set_vf_rate = i40e_ndo_set_vf_bw, |
41c445ff | 9664 | .ndo_get_vf_config = i40e_ndo_get_vf_config, |
588aefa0 | 9665 | .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state, |
e6d9004d | 9666 | .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk, |
c3bbbd20 | 9667 | .ndo_set_vf_trust = i40e_ndo_set_vf_trust, |
06a5f7f1 AD |
9668 | .ndo_udp_tunnel_add = i40e_udp_tunnel_add, |
9669 | .ndo_udp_tunnel_del = i40e_udp_tunnel_del, | |
1f224ad2 | 9670 | .ndo_get_phys_port_id = i40e_get_phys_port_id, |
4ba0dea5 | 9671 | .ndo_fdb_add = i40e_ndo_fdb_add, |
f44a75e2 | 9672 | .ndo_features_check = i40e_features_check, |
51616018 NP |
9673 | .ndo_bridge_getlink = i40e_ndo_bridge_getlink, |
9674 | .ndo_bridge_setlink = i40e_ndo_bridge_setlink, | |
0c8493d9 | 9675 | .ndo_xdp = i40e_xdp, |
41c445ff JB |
9676 | }; |
9677 | ||
9678 | /** | |
9679 | * i40e_config_netdev - Setup the netdev flags | |
9680 | * @vsi: the VSI being configured | |
9681 | * | |
9682 | * Returns 0 on success, negative value on failure | |
9683 | **/ | |
9684 | static int i40e_config_netdev(struct i40e_vsi *vsi) | |
9685 | { | |
9686 | struct i40e_pf *pf = vsi->back; | |
9687 | struct i40e_hw *hw = &pf->hw; | |
9688 | struct i40e_netdev_priv *np; | |
9689 | struct net_device *netdev; | |
435c084a | 9690 | u8 broadcast[ETH_ALEN]; |
41c445ff JB |
9691 | u8 mac_addr[ETH_ALEN]; |
9692 | int etherdev_size; | |
bacd75cf PB |
9693 | netdev_features_t hw_enc_features; |
9694 | netdev_features_t hw_features; | |
41c445ff JB |
9695 | |
9696 | etherdev_size = sizeof(struct i40e_netdev_priv); | |
f8ff1464 | 9697 | netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs); |
41c445ff JB |
9698 | if (!netdev) |
9699 | return -ENOMEM; | |
9700 | ||
9701 | vsi->netdev = netdev; | |
9702 | np = netdev_priv(netdev); | |
9703 | np->vsi = vsi; | |
9704 | ||
bacd75cf PB |
9705 | hw_enc_features = NETIF_F_SG | |
9706 | NETIF_F_IP_CSUM | | |
9707 | NETIF_F_IPV6_CSUM | | |
9708 | NETIF_F_HIGHDMA | | |
9709 | NETIF_F_SOFT_FEATURES | | |
9710 | NETIF_F_TSO | | |
9711 | NETIF_F_TSO_ECN | | |
9712 | NETIF_F_TSO6 | | |
9713 | NETIF_F_GSO_GRE | | |
9714 | NETIF_F_GSO_GRE_CSUM | | |
9715 | NETIF_F_GSO_PARTIAL | | |
9716 | NETIF_F_GSO_UDP_TUNNEL | | |
9717 | NETIF_F_GSO_UDP_TUNNEL_CSUM | | |
9718 | NETIF_F_SCTP_CRC | | |
9719 | NETIF_F_RXHASH | | |
9720 | NETIF_F_RXCSUM | | |
9721 | 0; | |
41c445ff | 9722 | |
d36e41dc | 9723 | if (!(pf->hw_features & I40E_HW_OUTER_UDP_CSUM_CAPABLE)) |
1c7b4a23 AD |
9724 | netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; |
9725 | ||
9726 | netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM; | |
b0fe3306 | 9727 | |
bacd75cf PB |
9728 | netdev->hw_enc_features |= hw_enc_features; |
9729 | ||
b0fe3306 | 9730 | /* record features VLANs can make use of */ |
bacd75cf | 9731 | netdev->vlan_features |= hw_enc_features | NETIF_F_TSO_MANGLEID; |
41c445ff | 9732 | |
2e86a0b6 | 9733 | if (!(pf->flags & I40E_FLAG_MFP_ENABLED)) |
b0fe3306 | 9734 | netdev->hw_features |= NETIF_F_NTUPLE; |
bacd75cf PB |
9735 | hw_features = hw_enc_features | |
9736 | NETIF_F_HW_VLAN_CTAG_TX | | |
9737 | NETIF_F_HW_VLAN_CTAG_RX; | |
b0fe3306 | 9738 | |
bacd75cf | 9739 | netdev->hw_features |= hw_features; |
2e86a0b6 | 9740 | |
bacd75cf | 9741 | netdev->features |= hw_features | NETIF_F_HW_VLAN_CTAG_FILTER; |
1c7b4a23 | 9742 | netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID; |
41c445ff JB |
9743 | |
9744 | if (vsi->type == I40E_VSI_MAIN) { | |
9745 | SET_NETDEV_DEV(netdev, &pf->pdev->dev); | |
9a173901 | 9746 | ether_addr_copy(mac_addr, hw->mac.perm_addr); |
41c4c2b5 JK |
9747 | /* The following steps are necessary for two reasons. First, |
9748 | * some older NVM configurations load a default MAC-VLAN | |
9749 | * filter that will accept any tagged packet, and we want to | |
9750 | * replace this with a normal filter. Additionally, it is | |
9751 | * possible our MAC address was provided by the platform using | |
9752 | * Open Firmware or similar. | |
9753 | * | |
9754 | * Thus, we need to remove the default filter and install one | |
9755 | * specific to the MAC address. | |
1596b5dd JK |
9756 | */ |
9757 | i40e_rm_default_mac_filter(vsi, mac_addr); | |
278e7d0b | 9758 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
9569a9a4 | 9759 | i40e_add_mac_filter(vsi, mac_addr); |
278e7d0b | 9760 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 9761 | } else { |
8c9eb350 JK |
9762 | /* Relate the VSI_VMDQ name to the VSI_MAIN name. Note that we |
9763 | * are still limited by IFNAMSIZ, but we're adding 'v%d\0' to | |
9764 | * the end, which is 4 bytes long, so force truncation of the | |
9765 | * original name by IFNAMSIZ - 4 | |
9766 | */ | |
9767 | snprintf(netdev->name, IFNAMSIZ, "%.*sv%%d", | |
9768 | IFNAMSIZ - 4, | |
41c445ff JB |
9769 | pf->vsi[pf->lan_vsi]->netdev->name); |
9770 | random_ether_addr(mac_addr); | |
21659035 | 9771 | |
278e7d0b | 9772 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
9569a9a4 | 9773 | i40e_add_mac_filter(vsi, mac_addr); |
278e7d0b | 9774 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 9775 | } |
21659035 | 9776 | |
435c084a JK |
9777 | /* Add the broadcast filter so that we initially will receive |
9778 | * broadcast packets. Note that when a new VLAN is first added the | |
9779 | * driver will convert all filters marked I40E_VLAN_ANY into VLAN | |
9780 | * specific filters as part of transitioning into "vlan" operation. | |
9781 | * When more VLANs are added, the driver will copy each existing MAC | |
9782 | * filter and add it for the new VLAN. | |
9783 | * | |
9784 | * Broadcast filters are handled specially by | |
9785 | * i40e_sync_filters_subtask, as the driver must to set the broadcast | |
9786 | * promiscuous bit instead of adding this directly as a MAC/VLAN | |
9787 | * filter. The subtask will update the correct broadcast promiscuous | |
9788 | * bits as VLANs become active or inactive. | |
9789 | */ | |
9790 | eth_broadcast_addr(broadcast); | |
9791 | spin_lock_bh(&vsi->mac_filter_hash_lock); | |
9569a9a4 | 9792 | i40e_add_mac_filter(vsi, broadcast); |
435c084a JK |
9793 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
9794 | ||
9a173901 GR |
9795 | ether_addr_copy(netdev->dev_addr, mac_addr); |
9796 | ether_addr_copy(netdev->perm_addr, mac_addr); | |
b0fe3306 | 9797 | |
41c445ff JB |
9798 | netdev->priv_flags |= IFF_UNICAST_FLT; |
9799 | netdev->priv_flags |= IFF_SUPP_NOFCS; | |
9800 | /* Setup netdev TC information */ | |
9801 | i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc); | |
9802 | ||
9803 | netdev->netdev_ops = &i40e_netdev_ops; | |
9804 | netdev->watchdog_timeo = 5 * HZ; | |
9805 | i40e_set_ethtool_ops(netdev); | |
9806 | ||
91c527a5 JW |
9807 | /* MTU range: 68 - 9706 */ |
9808 | netdev->min_mtu = ETH_MIN_MTU; | |
1e3a5fd5 | 9809 | netdev->max_mtu = I40E_MAX_RXBUFFER - I40E_PACKET_HDR_PAD; |
91c527a5 | 9810 | |
41c445ff JB |
9811 | return 0; |
9812 | } | |
9813 | ||
9814 | /** | |
9815 | * i40e_vsi_delete - Delete a VSI from the switch | |
9816 | * @vsi: the VSI being removed | |
9817 | * | |
9818 | * Returns 0 on success, negative value on failure | |
9819 | **/ | |
9820 | static void i40e_vsi_delete(struct i40e_vsi *vsi) | |
9821 | { | |
9822 | /* remove default VSI is not allowed */ | |
9823 | if (vsi == vsi->back->vsi[vsi->back->lan_vsi]) | |
9824 | return; | |
9825 | ||
41c445ff | 9826 | i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL); |
41c445ff JB |
9827 | } |
9828 | ||
51616018 NP |
9829 | /** |
9830 | * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB | |
9831 | * @vsi: the VSI being queried | |
9832 | * | |
9833 | * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode | |
9834 | **/ | |
9835 | int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi) | |
9836 | { | |
9837 | struct i40e_veb *veb; | |
9838 | struct i40e_pf *pf = vsi->back; | |
9839 | ||
9840 | /* Uplink is not a bridge so default to VEB */ | |
9841 | if (vsi->veb_idx == I40E_NO_VEB) | |
9842 | return 1; | |
9843 | ||
9844 | veb = pf->veb[vsi->veb_idx]; | |
09603eaa AA |
9845 | if (!veb) { |
9846 | dev_info(&pf->pdev->dev, | |
9847 | "There is no veb associated with the bridge\n"); | |
9848 | return -ENOENT; | |
9849 | } | |
9850 | ||
51616018 | 9851 | /* Uplink is a bridge in VEPA mode */ |
09603eaa | 9852 | if (veb->bridge_mode & BRIDGE_MODE_VEPA) { |
51616018 | 9853 | return 0; |
09603eaa AA |
9854 | } else { |
9855 | /* Uplink is a bridge in VEB mode */ | |
9856 | return 1; | |
9857 | } | |
51616018 | 9858 | |
09603eaa AA |
9859 | /* VEPA is now default bridge, so return 0 */ |
9860 | return 0; | |
51616018 NP |
9861 | } |
9862 | ||
41c445ff JB |
9863 | /** |
9864 | * i40e_add_vsi - Add a VSI to the switch | |
9865 | * @vsi: the VSI being configured | |
9866 | * | |
9867 | * This initializes a VSI context depending on the VSI type to be added and | |
9868 | * passes it down to the add_vsi aq command. | |
9869 | **/ | |
9870 | static int i40e_add_vsi(struct i40e_vsi *vsi) | |
9871 | { | |
9872 | int ret = -ENODEV; | |
41c445ff JB |
9873 | struct i40e_pf *pf = vsi->back; |
9874 | struct i40e_hw *hw = &pf->hw; | |
9875 | struct i40e_vsi_context ctxt; | |
278e7d0b JK |
9876 | struct i40e_mac_filter *f; |
9877 | struct hlist_node *h; | |
9878 | int bkt; | |
21659035 | 9879 | |
41c445ff JB |
9880 | u8 enabled_tc = 0x1; /* TC0 enabled */ |
9881 | int f_count = 0; | |
9882 | ||
9883 | memset(&ctxt, 0, sizeof(ctxt)); | |
9884 | switch (vsi->type) { | |
9885 | case I40E_VSI_MAIN: | |
9886 | /* The PF's main VSI is already setup as part of the | |
9887 | * device initialization, so we'll not bother with | |
9888 | * the add_vsi call, but we will retrieve the current | |
9889 | * VSI context. | |
9890 | */ | |
9891 | ctxt.seid = pf->main_vsi_seid; | |
9892 | ctxt.pf_num = pf->hw.pf_id; | |
9893 | ctxt.vf_num = 0; | |
9894 | ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL); | |
9895 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; | |
9896 | if (ret) { | |
9897 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9898 | "couldn't get PF vsi config, err %s aq_err %s\n", |
9899 | i40e_stat_str(&pf->hw, ret), | |
9900 | i40e_aq_str(&pf->hw, | |
9901 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9902 | return -ENOENT; |
9903 | } | |
1a2f6248 | 9904 | vsi->info = ctxt.info; |
41c445ff JB |
9905 | vsi->info.valid_sections = 0; |
9906 | ||
9907 | vsi->seid = ctxt.seid; | |
9908 | vsi->id = ctxt.vsi_number; | |
9909 | ||
9910 | enabled_tc = i40e_pf_get_tc_map(pf); | |
9911 | ||
64615b54 MW |
9912 | /* Source pruning is enabled by default, so the flag is |
9913 | * negative logic - if it's set, we need to fiddle with | |
9914 | * the VSI to disable source pruning. | |
9915 | */ | |
9916 | if (pf->flags & I40E_FLAG_SOURCE_PRUNING_DISABLED) { | |
9917 | memset(&ctxt, 0, sizeof(ctxt)); | |
9918 | ctxt.seid = pf->main_vsi_seid; | |
9919 | ctxt.pf_num = pf->hw.pf_id; | |
9920 | ctxt.vf_num = 0; | |
9921 | ctxt.info.valid_sections |= | |
9922 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
9923 | ctxt.info.switch_id = | |
9924 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB); | |
9925 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); | |
9926 | if (ret) { | |
9927 | dev_info(&pf->pdev->dev, | |
9928 | "update vsi failed, err %s aq_err %s\n", | |
9929 | i40e_stat_str(&pf->hw, ret), | |
9930 | i40e_aq_str(&pf->hw, | |
9931 | pf->hw.aq.asq_last_status)); | |
9932 | ret = -ENOENT; | |
9933 | goto err; | |
9934 | } | |
9935 | } | |
9936 | ||
41c445ff | 9937 | /* MFP mode setup queue map and update VSI */ |
63d7e5a4 NP |
9938 | if ((pf->flags & I40E_FLAG_MFP_ENABLED) && |
9939 | !(pf->hw.func_caps.iscsi)) { /* NIC type PF */ | |
41c445ff JB |
9940 | memset(&ctxt, 0, sizeof(ctxt)); |
9941 | ctxt.seid = pf->main_vsi_seid; | |
9942 | ctxt.pf_num = pf->hw.pf_id; | |
9943 | ctxt.vf_num = 0; | |
9944 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false); | |
9945 | ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL); | |
9946 | if (ret) { | |
9947 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
9948 | "update vsi failed, err %s aq_err %s\n", |
9949 | i40e_stat_str(&pf->hw, ret), | |
9950 | i40e_aq_str(&pf->hw, | |
9951 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9952 | ret = -ENOENT; |
9953 | goto err; | |
9954 | } | |
9955 | /* update the local VSI info queue map */ | |
9956 | i40e_vsi_update_queue_map(vsi, &ctxt); | |
9957 | vsi->info.valid_sections = 0; | |
9958 | } else { | |
9959 | /* Default/Main VSI is only enabled for TC0 | |
9960 | * reconfigure it to enable all TCs that are | |
9961 | * available on the port in SFP mode. | |
63d7e5a4 NP |
9962 | * For MFP case the iSCSI PF would use this |
9963 | * flow to enable LAN+iSCSI TC. | |
41c445ff JB |
9964 | */ |
9965 | ret = i40e_vsi_config_tc(vsi, enabled_tc); | |
9966 | if (ret) { | |
19279235 CW |
9967 | /* Single TC condition is not fatal, |
9968 | * message and continue | |
9969 | */ | |
41c445ff | 9970 | dev_info(&pf->pdev->dev, |
f1c7e72e SN |
9971 | "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n", |
9972 | enabled_tc, | |
9973 | i40e_stat_str(&pf->hw, ret), | |
9974 | i40e_aq_str(&pf->hw, | |
9975 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
9976 | } |
9977 | } | |
9978 | break; | |
9979 | ||
9980 | case I40E_VSI_FDIR: | |
cbf61325 ASJ |
9981 | ctxt.pf_num = hw->pf_id; |
9982 | ctxt.vf_num = 0; | |
9983 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 9984 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
cbf61325 | 9985 | ctxt.flags = I40E_AQ_VSI_TYPE_PF; |
fc60861e ASJ |
9986 | if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) && |
9987 | (i40e_is_vsi_uplink_mode_veb(vsi))) { | |
51616018 | 9988 | ctxt.info.valid_sections |= |
fc60861e | 9989 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); |
51616018 | 9990 | ctxt.info.switch_id = |
fc60861e | 9991 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); |
51616018 | 9992 | } |
41c445ff | 9993 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); |
41c445ff JB |
9994 | break; |
9995 | ||
9996 | case I40E_VSI_VMDQ2: | |
9997 | ctxt.pf_num = hw->pf_id; | |
9998 | ctxt.vf_num = 0; | |
9999 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 10000 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
41c445ff JB |
10001 | ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2; |
10002 | ||
41c445ff JB |
10003 | /* This VSI is connected to VEB so the switch_id |
10004 | * should be set to zero by default. | |
10005 | */ | |
51616018 NP |
10006 | if (i40e_is_vsi_uplink_mode_veb(vsi)) { |
10007 | ctxt.info.valid_sections |= | |
10008 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
10009 | ctxt.info.switch_id = | |
10010 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
10011 | } | |
41c445ff JB |
10012 | |
10013 | /* Setup the VSI tx/rx queue map for TC0 only for now */ | |
10014 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); | |
10015 | break; | |
10016 | ||
10017 | case I40E_VSI_SRIOV: | |
10018 | ctxt.pf_num = hw->pf_id; | |
10019 | ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id; | |
10020 | ctxt.uplink_seid = vsi->uplink_seid; | |
2b18e591 | 10021 | ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL; |
41c445ff JB |
10022 | ctxt.flags = I40E_AQ_VSI_TYPE_VF; |
10023 | ||
41c445ff JB |
10024 | /* This VSI is connected to VEB so the switch_id |
10025 | * should be set to zero by default. | |
10026 | */ | |
51616018 NP |
10027 | if (i40e_is_vsi_uplink_mode_veb(vsi)) { |
10028 | ctxt.info.valid_sections |= | |
10029 | cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID); | |
10030 | ctxt.info.switch_id = | |
10031 | cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB); | |
10032 | } | |
41c445ff | 10033 | |
e3219ce6 ASJ |
10034 | if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) { |
10035 | ctxt.info.valid_sections |= | |
10036 | cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID); | |
10037 | ctxt.info.queueing_opt_flags |= | |
4b28cdba AS |
10038 | (I40E_AQ_VSI_QUE_OPT_TCP_ENA | |
10039 | I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI); | |
e3219ce6 ASJ |
10040 | } |
10041 | ||
41c445ff JB |
10042 | ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID); |
10043 | ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL; | |
c674d125 MW |
10044 | if (pf->vf[vsi->vf_id].spoofchk) { |
10045 | ctxt.info.valid_sections |= | |
10046 | cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID); | |
10047 | ctxt.info.sec_flags |= | |
10048 | (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK | | |
10049 | I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK); | |
10050 | } | |
41c445ff JB |
10051 | /* Setup the VSI tx/rx queue map for TC0 only for now */ |
10052 | i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true); | |
10053 | break; | |
10054 | ||
e3219ce6 ASJ |
10055 | case I40E_VSI_IWARP: |
10056 | /* send down message to iWARP */ | |
10057 | break; | |
10058 | ||
41c445ff JB |
10059 | default: |
10060 | return -ENODEV; | |
10061 | } | |
10062 | ||
10063 | if (vsi->type != I40E_VSI_MAIN) { | |
10064 | ret = i40e_aq_add_vsi(hw, &ctxt, NULL); | |
10065 | if (ret) { | |
10066 | dev_info(&vsi->back->pdev->dev, | |
f1c7e72e SN |
10067 | "add vsi failed, err %s aq_err %s\n", |
10068 | i40e_stat_str(&pf->hw, ret), | |
10069 | i40e_aq_str(&pf->hw, | |
10070 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10071 | ret = -ENOENT; |
10072 | goto err; | |
10073 | } | |
1a2f6248 | 10074 | vsi->info = ctxt.info; |
41c445ff JB |
10075 | vsi->info.valid_sections = 0; |
10076 | vsi->seid = ctxt.seid; | |
10077 | vsi->id = ctxt.vsi_number; | |
10078 | } | |
10079 | ||
c3c7ea27 | 10080 | vsi->active_filters = 0; |
0da36b97 | 10081 | clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state); |
278e7d0b | 10082 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
41c445ff | 10083 | /* If macvlan filters already exist, force them to get loaded */ |
278e7d0b | 10084 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) { |
c3c7ea27 | 10085 | f->state = I40E_FILTER_NEW; |
41c445ff | 10086 | f_count++; |
21659035 | 10087 | } |
278e7d0b | 10088 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
30650cc5 | 10089 | |
41c445ff JB |
10090 | if (f_count) { |
10091 | vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED; | |
10092 | pf->flags |= I40E_FLAG_FILTER_SYNC; | |
10093 | } | |
10094 | ||
10095 | /* Update VSI BW information */ | |
10096 | ret = i40e_vsi_get_bw_info(vsi); | |
10097 | if (ret) { | |
10098 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10099 | "couldn't get vsi bw info, err %s aq_err %s\n", |
10100 | i40e_stat_str(&pf->hw, ret), | |
10101 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10102 | /* VSI is already added so not tearing that up */ |
10103 | ret = 0; | |
10104 | } | |
10105 | ||
10106 | err: | |
10107 | return ret; | |
10108 | } | |
10109 | ||
10110 | /** | |
10111 | * i40e_vsi_release - Delete a VSI and free its resources | |
10112 | * @vsi: the VSI being removed | |
10113 | * | |
10114 | * Returns 0 on success or < 0 on error | |
10115 | **/ | |
10116 | int i40e_vsi_release(struct i40e_vsi *vsi) | |
10117 | { | |
278e7d0b JK |
10118 | struct i40e_mac_filter *f; |
10119 | struct hlist_node *h; | |
41c445ff JB |
10120 | struct i40e_veb *veb = NULL; |
10121 | struct i40e_pf *pf; | |
10122 | u16 uplink_seid; | |
278e7d0b | 10123 | int i, n, bkt; |
41c445ff JB |
10124 | |
10125 | pf = vsi->back; | |
10126 | ||
10127 | /* release of a VEB-owner or last VSI is not allowed */ | |
10128 | if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) { | |
10129 | dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n", | |
10130 | vsi->seid, vsi->uplink_seid); | |
10131 | return -ENODEV; | |
10132 | } | |
10133 | if (vsi == pf->vsi[pf->lan_vsi] && | |
9e6c9c0f | 10134 | !test_bit(__I40E_DOWN, pf->state)) { |
41c445ff JB |
10135 | dev_info(&pf->pdev->dev, "Can't remove PF VSI\n"); |
10136 | return -ENODEV; | |
10137 | } | |
10138 | ||
10139 | uplink_seid = vsi->uplink_seid; | |
10140 | if (vsi->type != I40E_VSI_SRIOV) { | |
10141 | if (vsi->netdev_registered) { | |
10142 | vsi->netdev_registered = false; | |
10143 | if (vsi->netdev) { | |
10144 | /* results in a call to i40e_close() */ | |
10145 | unregister_netdev(vsi->netdev); | |
41c445ff JB |
10146 | } |
10147 | } else { | |
90ef8d47 | 10148 | i40e_vsi_close(vsi); |
41c445ff JB |
10149 | } |
10150 | i40e_vsi_disable_irq(vsi); | |
10151 | } | |
10152 | ||
278e7d0b | 10153 | spin_lock_bh(&vsi->mac_filter_hash_lock); |
6622f5cd JK |
10154 | |
10155 | /* clear the sync flag on all filters */ | |
10156 | if (vsi->netdev) { | |
10157 | __dev_uc_unsync(vsi->netdev, NULL); | |
10158 | __dev_mc_unsync(vsi->netdev, NULL); | |
10159 | } | |
10160 | ||
10161 | /* make sure any remaining filters are marked for deletion */ | |
278e7d0b | 10162 | hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) |
290d2557 | 10163 | __i40e_del_filter(vsi, f); |
6622f5cd | 10164 | |
278e7d0b | 10165 | spin_unlock_bh(&vsi->mac_filter_hash_lock); |
21659035 | 10166 | |
17652c63 | 10167 | i40e_sync_vsi_filters(vsi); |
41c445ff JB |
10168 | |
10169 | i40e_vsi_delete(vsi); | |
10170 | i40e_vsi_free_q_vectors(vsi); | |
a4866597 SN |
10171 | if (vsi->netdev) { |
10172 | free_netdev(vsi->netdev); | |
10173 | vsi->netdev = NULL; | |
10174 | } | |
41c445ff JB |
10175 | i40e_vsi_clear_rings(vsi); |
10176 | i40e_vsi_clear(vsi); | |
10177 | ||
10178 | /* If this was the last thing on the VEB, except for the | |
10179 | * controlling VSI, remove the VEB, which puts the controlling | |
10180 | * VSI onto the next level down in the switch. | |
10181 | * | |
10182 | * Well, okay, there's one more exception here: don't remove | |
10183 | * the orphan VEBs yet. We'll wait for an explicit remove request | |
10184 | * from up the network stack. | |
10185 | */ | |
505682cd | 10186 | for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
10187 | if (pf->vsi[i] && |
10188 | pf->vsi[i]->uplink_seid == uplink_seid && | |
10189 | (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { | |
10190 | n++; /* count the VSIs */ | |
10191 | } | |
10192 | } | |
10193 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
10194 | if (!pf->veb[i]) | |
10195 | continue; | |
10196 | if (pf->veb[i]->uplink_seid == uplink_seid) | |
10197 | n++; /* count the VEBs */ | |
10198 | if (pf->veb[i]->seid == uplink_seid) | |
10199 | veb = pf->veb[i]; | |
10200 | } | |
10201 | if (n == 0 && veb && veb->uplink_seid != 0) | |
10202 | i40e_veb_release(veb); | |
10203 | ||
10204 | return 0; | |
10205 | } | |
10206 | ||
10207 | /** | |
10208 | * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI | |
10209 | * @vsi: ptr to the VSI | |
10210 | * | |
10211 | * This should only be called after i40e_vsi_mem_alloc() which allocates the | |
10212 | * corresponding SW VSI structure and initializes num_queue_pairs for the | |
10213 | * newly allocated VSI. | |
10214 | * | |
10215 | * Returns 0 on success or negative on failure | |
10216 | **/ | |
10217 | static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi) | |
10218 | { | |
10219 | int ret = -ENOENT; | |
10220 | struct i40e_pf *pf = vsi->back; | |
10221 | ||
493fb300 | 10222 | if (vsi->q_vectors[0]) { |
41c445ff JB |
10223 | dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n", |
10224 | vsi->seid); | |
10225 | return -EEXIST; | |
10226 | } | |
10227 | ||
10228 | if (vsi->base_vector) { | |
f29eaa3d | 10229 | dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n", |
41c445ff JB |
10230 | vsi->seid, vsi->base_vector); |
10231 | return -EEXIST; | |
10232 | } | |
10233 | ||
90e04070 | 10234 | ret = i40e_vsi_alloc_q_vectors(vsi); |
41c445ff JB |
10235 | if (ret) { |
10236 | dev_info(&pf->pdev->dev, | |
10237 | "failed to allocate %d q_vector for VSI %d, ret=%d\n", | |
10238 | vsi->num_q_vectors, vsi->seid, ret); | |
10239 | vsi->num_q_vectors = 0; | |
10240 | goto vector_setup_out; | |
10241 | } | |
10242 | ||
26cdc443 ASJ |
10243 | /* In Legacy mode, we do not have to get any other vector since we |
10244 | * piggyback on the misc/ICR0 for queue interrupts. | |
10245 | */ | |
10246 | if (!(pf->flags & I40E_FLAG_MSIX_ENABLED)) | |
10247 | return ret; | |
958a3e3b SN |
10248 | if (vsi->num_q_vectors) |
10249 | vsi->base_vector = i40e_get_lump(pf, pf->irq_pile, | |
10250 | vsi->num_q_vectors, vsi->idx); | |
41c445ff JB |
10251 | if (vsi->base_vector < 0) { |
10252 | dev_info(&pf->pdev->dev, | |
049a2be8 SN |
10253 | "failed to get tracking for %d vectors for VSI %d, err=%d\n", |
10254 | vsi->num_q_vectors, vsi->seid, vsi->base_vector); | |
41c445ff JB |
10255 | i40e_vsi_free_q_vectors(vsi); |
10256 | ret = -ENOENT; | |
10257 | goto vector_setup_out; | |
10258 | } | |
10259 | ||
10260 | vector_setup_out: | |
10261 | return ret; | |
10262 | } | |
10263 | ||
bc7d338f ASJ |
10264 | /** |
10265 | * i40e_vsi_reinit_setup - return and reallocate resources for a VSI | |
10266 | * @vsi: pointer to the vsi. | |
10267 | * | |
10268 | * This re-allocates a vsi's queue resources. | |
10269 | * | |
10270 | * Returns pointer to the successfully allocated and configured VSI sw struct | |
10271 | * on success, otherwise returns NULL on failure. | |
10272 | **/ | |
10273 | static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi) | |
10274 | { | |
74608d17 | 10275 | u16 alloc_queue_pairs; |
f534039d | 10276 | struct i40e_pf *pf; |
bc7d338f ASJ |
10277 | u8 enabled_tc; |
10278 | int ret; | |
10279 | ||
f534039d JU |
10280 | if (!vsi) |
10281 | return NULL; | |
10282 | ||
10283 | pf = vsi->back; | |
10284 | ||
bc7d338f ASJ |
10285 | i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx); |
10286 | i40e_vsi_clear_rings(vsi); | |
10287 | ||
10288 | i40e_vsi_free_arrays(vsi, false); | |
10289 | i40e_set_num_rings_in_vsi(vsi); | |
10290 | ret = i40e_vsi_alloc_arrays(vsi, false); | |
10291 | if (ret) | |
10292 | goto err_vsi; | |
10293 | ||
74608d17 BT |
10294 | alloc_queue_pairs = vsi->alloc_queue_pairs * |
10295 | (i40e_enabled_xdp_vsi(vsi) ? 2 : 1); | |
10296 | ||
10297 | ret = i40e_get_lump(pf, pf->qp_pile, alloc_queue_pairs, vsi->idx); | |
bc7d338f | 10298 | if (ret < 0) { |
049a2be8 | 10299 | dev_info(&pf->pdev->dev, |
f1c7e72e | 10300 | "failed to get tracking for %d queues for VSI %d err %d\n", |
74608d17 | 10301 | alloc_queue_pairs, vsi->seid, ret); |
bc7d338f ASJ |
10302 | goto err_vsi; |
10303 | } | |
10304 | vsi->base_queue = ret; | |
10305 | ||
10306 | /* Update the FW view of the VSI. Force a reset of TC and queue | |
10307 | * layout configurations. | |
10308 | */ | |
10309 | enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; | |
10310 | pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; | |
10311 | pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; | |
10312 | i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); | |
1596b5dd JK |
10313 | if (vsi->type == I40E_VSI_MAIN) |
10314 | i40e_rm_default_mac_filter(vsi, pf->hw.mac.perm_addr); | |
bc7d338f ASJ |
10315 | |
10316 | /* assign it some queues */ | |
10317 | ret = i40e_alloc_rings(vsi); | |
10318 | if (ret) | |
10319 | goto err_rings; | |
10320 | ||
10321 | /* map all of the rings to the q_vectors */ | |
10322 | i40e_vsi_map_rings_to_vectors(vsi); | |
10323 | return vsi; | |
10324 | ||
10325 | err_rings: | |
10326 | i40e_vsi_free_q_vectors(vsi); | |
10327 | if (vsi->netdev_registered) { | |
10328 | vsi->netdev_registered = false; | |
10329 | unregister_netdev(vsi->netdev); | |
10330 | free_netdev(vsi->netdev); | |
10331 | vsi->netdev = NULL; | |
10332 | } | |
10333 | i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); | |
10334 | err_vsi: | |
10335 | i40e_vsi_clear(vsi); | |
10336 | return NULL; | |
10337 | } | |
10338 | ||
41c445ff JB |
10339 | /** |
10340 | * i40e_vsi_setup - Set up a VSI by a given type | |
10341 | * @pf: board private structure | |
10342 | * @type: VSI type | |
10343 | * @uplink_seid: the switch element to link to | |
10344 | * @param1: usage depends upon VSI type. For VF types, indicates VF id | |
10345 | * | |
10346 | * This allocates the sw VSI structure and its queue resources, then add a VSI | |
10347 | * to the identified VEB. | |
10348 | * | |
10349 | * Returns pointer to the successfully allocated and configure VSI sw struct on | |
10350 | * success, otherwise returns NULL on failure. | |
10351 | **/ | |
10352 | struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type, | |
10353 | u16 uplink_seid, u32 param1) | |
10354 | { | |
10355 | struct i40e_vsi *vsi = NULL; | |
10356 | struct i40e_veb *veb = NULL; | |
74608d17 | 10357 | u16 alloc_queue_pairs; |
41c445ff JB |
10358 | int ret, i; |
10359 | int v_idx; | |
10360 | ||
10361 | /* The requested uplink_seid must be either | |
10362 | * - the PF's port seid | |
10363 | * no VEB is needed because this is the PF | |
10364 | * or this is a Flow Director special case VSI | |
10365 | * - seid of an existing VEB | |
10366 | * - seid of a VSI that owns an existing VEB | |
10367 | * - seid of a VSI that doesn't own a VEB | |
10368 | * a new VEB is created and the VSI becomes the owner | |
10369 | * - seid of the PF VSI, which is what creates the first VEB | |
10370 | * this is a special case of the previous | |
10371 | * | |
10372 | * Find which uplink_seid we were given and create a new VEB if needed | |
10373 | */ | |
10374 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
10375 | if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) { | |
10376 | veb = pf->veb[i]; | |
10377 | break; | |
10378 | } | |
10379 | } | |
10380 | ||
10381 | if (!veb && uplink_seid != pf->mac_seid) { | |
10382 | ||
505682cd | 10383 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
10384 | if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) { |
10385 | vsi = pf->vsi[i]; | |
10386 | break; | |
10387 | } | |
10388 | } | |
10389 | if (!vsi) { | |
10390 | dev_info(&pf->pdev->dev, "no such uplink_seid %d\n", | |
10391 | uplink_seid); | |
10392 | return NULL; | |
10393 | } | |
10394 | ||
10395 | if (vsi->uplink_seid == pf->mac_seid) | |
10396 | veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid, | |
10397 | vsi->tc_config.enabled_tc); | |
10398 | else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) | |
10399 | veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid, | |
10400 | vsi->tc_config.enabled_tc); | |
79c21a82 ASJ |
10401 | if (veb) { |
10402 | if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) { | |
10403 | dev_info(&vsi->back->pdev->dev, | |
fb43201f | 10404 | "New VSI creation error, uplink seid of LAN VSI expected.\n"); |
79c21a82 ASJ |
10405 | return NULL; |
10406 | } | |
fa11cb3d ASJ |
10407 | /* We come up by default in VEPA mode if SRIOV is not |
10408 | * already enabled, in which case we can't force VEPA | |
10409 | * mode. | |
10410 | */ | |
10411 | if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) { | |
10412 | veb->bridge_mode = BRIDGE_MODE_VEPA; | |
10413 | pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED; | |
10414 | } | |
51616018 | 10415 | i40e_config_bridge_mode(veb); |
79c21a82 | 10416 | } |
41c445ff JB |
10417 | for (i = 0; i < I40E_MAX_VEB && !veb; i++) { |
10418 | if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid) | |
10419 | veb = pf->veb[i]; | |
10420 | } | |
10421 | if (!veb) { | |
10422 | dev_info(&pf->pdev->dev, "couldn't add VEB\n"); | |
10423 | return NULL; | |
10424 | } | |
10425 | ||
10426 | vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; | |
10427 | uplink_seid = veb->seid; | |
10428 | } | |
10429 | ||
10430 | /* get vsi sw struct */ | |
10431 | v_idx = i40e_vsi_mem_alloc(pf, type); | |
10432 | if (v_idx < 0) | |
10433 | goto err_alloc; | |
10434 | vsi = pf->vsi[v_idx]; | |
cbf61325 ASJ |
10435 | if (!vsi) |
10436 | goto err_alloc; | |
41c445ff JB |
10437 | vsi->type = type; |
10438 | vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB); | |
10439 | ||
10440 | if (type == I40E_VSI_MAIN) | |
10441 | pf->lan_vsi = v_idx; | |
10442 | else if (type == I40E_VSI_SRIOV) | |
10443 | vsi->vf_id = param1; | |
10444 | /* assign it some queues */ | |
74608d17 BT |
10445 | alloc_queue_pairs = vsi->alloc_queue_pairs * |
10446 | (i40e_enabled_xdp_vsi(vsi) ? 2 : 1); | |
10447 | ||
10448 | ret = i40e_get_lump(pf, pf->qp_pile, alloc_queue_pairs, vsi->idx); | |
41c445ff | 10449 | if (ret < 0) { |
049a2be8 SN |
10450 | dev_info(&pf->pdev->dev, |
10451 | "failed to get tracking for %d queues for VSI %d err=%d\n", | |
74608d17 | 10452 | alloc_queue_pairs, vsi->seid, ret); |
41c445ff JB |
10453 | goto err_vsi; |
10454 | } | |
10455 | vsi->base_queue = ret; | |
10456 | ||
10457 | /* get a VSI from the hardware */ | |
10458 | vsi->uplink_seid = uplink_seid; | |
10459 | ret = i40e_add_vsi(vsi); | |
10460 | if (ret) | |
10461 | goto err_vsi; | |
10462 | ||
10463 | switch (vsi->type) { | |
10464 | /* setup the netdev if needed */ | |
10465 | case I40E_VSI_MAIN: | |
10466 | case I40E_VSI_VMDQ2: | |
10467 | ret = i40e_config_netdev(vsi); | |
10468 | if (ret) | |
10469 | goto err_netdev; | |
10470 | ret = register_netdev(vsi->netdev); | |
10471 | if (ret) | |
10472 | goto err_netdev; | |
10473 | vsi->netdev_registered = true; | |
10474 | netif_carrier_off(vsi->netdev); | |
4e3b35b0 NP |
10475 | #ifdef CONFIG_I40E_DCB |
10476 | /* Setup DCB netlink interface */ | |
10477 | i40e_dcbnl_setup(vsi); | |
10478 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
10479 | /* fall through */ |
10480 | ||
10481 | case I40E_VSI_FDIR: | |
10482 | /* set up vectors and rings if needed */ | |
10483 | ret = i40e_vsi_setup_vectors(vsi); | |
10484 | if (ret) | |
10485 | goto err_msix; | |
10486 | ||
10487 | ret = i40e_alloc_rings(vsi); | |
10488 | if (ret) | |
10489 | goto err_rings; | |
10490 | ||
10491 | /* map all of the rings to the q_vectors */ | |
10492 | i40e_vsi_map_rings_to_vectors(vsi); | |
10493 | ||
10494 | i40e_vsi_reset_stats(vsi); | |
10495 | break; | |
10496 | ||
10497 | default: | |
10498 | /* no netdev or rings for the other VSI types */ | |
10499 | break; | |
10500 | } | |
10501 | ||
d36e41dc | 10502 | if ((pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) && |
e25d00b8 ASJ |
10503 | (vsi->type == I40E_VSI_VMDQ2)) { |
10504 | ret = i40e_vsi_config_rss(vsi); | |
10505 | } | |
41c445ff JB |
10506 | return vsi; |
10507 | ||
10508 | err_rings: | |
10509 | i40e_vsi_free_q_vectors(vsi); | |
10510 | err_msix: | |
10511 | if (vsi->netdev_registered) { | |
10512 | vsi->netdev_registered = false; | |
10513 | unregister_netdev(vsi->netdev); | |
10514 | free_netdev(vsi->netdev); | |
10515 | vsi->netdev = NULL; | |
10516 | } | |
10517 | err_netdev: | |
10518 | i40e_aq_delete_element(&pf->hw, vsi->seid, NULL); | |
10519 | err_vsi: | |
10520 | i40e_vsi_clear(vsi); | |
10521 | err_alloc: | |
10522 | return NULL; | |
10523 | } | |
10524 | ||
10525 | /** | |
10526 | * i40e_veb_get_bw_info - Query VEB BW information | |
10527 | * @veb: the veb to query | |
10528 | * | |
10529 | * Query the Tx scheduler BW configuration data for given VEB | |
10530 | **/ | |
10531 | static int i40e_veb_get_bw_info(struct i40e_veb *veb) | |
10532 | { | |
10533 | struct i40e_aqc_query_switching_comp_ets_config_resp ets_data; | |
10534 | struct i40e_aqc_query_switching_comp_bw_config_resp bw_data; | |
10535 | struct i40e_pf *pf = veb->pf; | |
10536 | struct i40e_hw *hw = &pf->hw; | |
10537 | u32 tc_bw_max; | |
10538 | int ret = 0; | |
10539 | int i; | |
10540 | ||
10541 | ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid, | |
10542 | &bw_data, NULL); | |
10543 | if (ret) { | |
10544 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10545 | "query veb bw config failed, err %s aq_err %s\n", |
10546 | i40e_stat_str(&pf->hw, ret), | |
10547 | i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); | |
41c445ff JB |
10548 | goto out; |
10549 | } | |
10550 | ||
10551 | ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid, | |
10552 | &ets_data, NULL); | |
10553 | if (ret) { | |
10554 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10555 | "query veb bw ets config failed, err %s aq_err %s\n", |
10556 | i40e_stat_str(&pf->hw, ret), | |
10557 | i40e_aq_str(&pf->hw, hw->aq.asq_last_status)); | |
41c445ff JB |
10558 | goto out; |
10559 | } | |
10560 | ||
10561 | veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit); | |
10562 | veb->bw_max_quanta = ets_data.tc_bw_max; | |
10563 | veb->is_abs_credits = bw_data.absolute_credits_enable; | |
23cd1f09 | 10564 | veb->enabled_tc = ets_data.tc_valid_bits; |
41c445ff JB |
10565 | tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) | |
10566 | (le16_to_cpu(bw_data.tc_bw_max[1]) << 16); | |
10567 | for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) { | |
10568 | veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i]; | |
10569 | veb->bw_tc_limit_credits[i] = | |
10570 | le16_to_cpu(bw_data.tc_bw_limits[i]); | |
10571 | veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7); | |
10572 | } | |
10573 | ||
10574 | out: | |
10575 | return ret; | |
10576 | } | |
10577 | ||
10578 | /** | |
10579 | * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF | |
10580 | * @pf: board private structure | |
10581 | * | |
10582 | * On error: returns error code (negative) | |
10583 | * On success: returns vsi index in PF (positive) | |
10584 | **/ | |
10585 | static int i40e_veb_mem_alloc(struct i40e_pf *pf) | |
10586 | { | |
10587 | int ret = -ENOENT; | |
10588 | struct i40e_veb *veb; | |
10589 | int i; | |
10590 | ||
10591 | /* Need to protect the allocation of switch elements at the PF level */ | |
10592 | mutex_lock(&pf->switch_mutex); | |
10593 | ||
10594 | /* VEB list may be fragmented if VEB creation/destruction has | |
10595 | * been happening. We can afford to do a quick scan to look | |
10596 | * for any free slots in the list. | |
10597 | * | |
10598 | * find next empty veb slot, looping back around if necessary | |
10599 | */ | |
10600 | i = 0; | |
10601 | while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL)) | |
10602 | i++; | |
10603 | if (i >= I40E_MAX_VEB) { | |
10604 | ret = -ENOMEM; | |
10605 | goto err_alloc_veb; /* out of VEB slots! */ | |
10606 | } | |
10607 | ||
10608 | veb = kzalloc(sizeof(*veb), GFP_KERNEL); | |
10609 | if (!veb) { | |
10610 | ret = -ENOMEM; | |
10611 | goto err_alloc_veb; | |
10612 | } | |
10613 | veb->pf = pf; | |
10614 | veb->idx = i; | |
10615 | veb->enabled_tc = 1; | |
10616 | ||
10617 | pf->veb[i] = veb; | |
10618 | ret = i; | |
10619 | err_alloc_veb: | |
10620 | mutex_unlock(&pf->switch_mutex); | |
10621 | return ret; | |
10622 | } | |
10623 | ||
10624 | /** | |
10625 | * i40e_switch_branch_release - Delete a branch of the switch tree | |
10626 | * @branch: where to start deleting | |
10627 | * | |
10628 | * This uses recursion to find the tips of the branch to be | |
10629 | * removed, deleting until we get back to and can delete this VEB. | |
10630 | **/ | |
10631 | static void i40e_switch_branch_release(struct i40e_veb *branch) | |
10632 | { | |
10633 | struct i40e_pf *pf = branch->pf; | |
10634 | u16 branch_seid = branch->seid; | |
10635 | u16 veb_idx = branch->idx; | |
10636 | int i; | |
10637 | ||
10638 | /* release any VEBs on this VEB - RECURSION */ | |
10639 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
10640 | if (!pf->veb[i]) | |
10641 | continue; | |
10642 | if (pf->veb[i]->uplink_seid == branch->seid) | |
10643 | i40e_switch_branch_release(pf->veb[i]); | |
10644 | } | |
10645 | ||
10646 | /* Release the VSIs on this VEB, but not the owner VSI. | |
10647 | * | |
10648 | * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing | |
10649 | * the VEB itself, so don't use (*branch) after this loop. | |
10650 | */ | |
505682cd | 10651 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
10652 | if (!pf->vsi[i]) |
10653 | continue; | |
10654 | if (pf->vsi[i]->uplink_seid == branch_seid && | |
10655 | (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) { | |
10656 | i40e_vsi_release(pf->vsi[i]); | |
10657 | } | |
10658 | } | |
10659 | ||
10660 | /* There's one corner case where the VEB might not have been | |
10661 | * removed, so double check it here and remove it if needed. | |
10662 | * This case happens if the veb was created from the debugfs | |
10663 | * commands and no VSIs were added to it. | |
10664 | */ | |
10665 | if (pf->veb[veb_idx]) | |
10666 | i40e_veb_release(pf->veb[veb_idx]); | |
10667 | } | |
10668 | ||
10669 | /** | |
10670 | * i40e_veb_clear - remove veb struct | |
10671 | * @veb: the veb to remove | |
10672 | **/ | |
10673 | static void i40e_veb_clear(struct i40e_veb *veb) | |
10674 | { | |
10675 | if (!veb) | |
10676 | return; | |
10677 | ||
10678 | if (veb->pf) { | |
10679 | struct i40e_pf *pf = veb->pf; | |
10680 | ||
10681 | mutex_lock(&pf->switch_mutex); | |
10682 | if (pf->veb[veb->idx] == veb) | |
10683 | pf->veb[veb->idx] = NULL; | |
10684 | mutex_unlock(&pf->switch_mutex); | |
10685 | } | |
10686 | ||
10687 | kfree(veb); | |
10688 | } | |
10689 | ||
10690 | /** | |
10691 | * i40e_veb_release - Delete a VEB and free its resources | |
10692 | * @veb: the VEB being removed | |
10693 | **/ | |
10694 | void i40e_veb_release(struct i40e_veb *veb) | |
10695 | { | |
10696 | struct i40e_vsi *vsi = NULL; | |
10697 | struct i40e_pf *pf; | |
10698 | int i, n = 0; | |
10699 | ||
10700 | pf = veb->pf; | |
10701 | ||
10702 | /* find the remaining VSI and check for extras */ | |
505682cd | 10703 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
10704 | if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) { |
10705 | n++; | |
10706 | vsi = pf->vsi[i]; | |
10707 | } | |
10708 | } | |
10709 | if (n != 1) { | |
10710 | dev_info(&pf->pdev->dev, | |
10711 | "can't remove VEB %d with %d VSIs left\n", | |
10712 | veb->seid, n); | |
10713 | return; | |
10714 | } | |
10715 | ||
10716 | /* move the remaining VSI to uplink veb */ | |
10717 | vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER; | |
10718 | if (veb->uplink_seid) { | |
10719 | vsi->uplink_seid = veb->uplink_seid; | |
10720 | if (veb->uplink_seid == pf->mac_seid) | |
10721 | vsi->veb_idx = I40E_NO_VEB; | |
10722 | else | |
10723 | vsi->veb_idx = veb->veb_idx; | |
10724 | } else { | |
10725 | /* floating VEB */ | |
10726 | vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid; | |
10727 | vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx; | |
10728 | } | |
10729 | ||
10730 | i40e_aq_delete_element(&pf->hw, veb->seid, NULL); | |
10731 | i40e_veb_clear(veb); | |
41c445ff JB |
10732 | } |
10733 | ||
10734 | /** | |
10735 | * i40e_add_veb - create the VEB in the switch | |
10736 | * @veb: the VEB to be instantiated | |
10737 | * @vsi: the controlling VSI | |
10738 | **/ | |
10739 | static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi) | |
10740 | { | |
f1c7e72e | 10741 | struct i40e_pf *pf = veb->pf; |
66fc360a | 10742 | bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED); |
41c445ff JB |
10743 | int ret; |
10744 | ||
f1c7e72e | 10745 | ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid, |
5bc16031 | 10746 | veb->enabled_tc, false, |
66fc360a | 10747 | &veb->seid, enable_stats, NULL); |
5bc16031 MW |
10748 | |
10749 | /* get a VEB from the hardware */ | |
41c445ff | 10750 | if (ret) { |
f1c7e72e SN |
10751 | dev_info(&pf->pdev->dev, |
10752 | "couldn't add VEB, err %s aq_err %s\n", | |
10753 | i40e_stat_str(&pf->hw, ret), | |
10754 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10755 | return -EPERM; |
10756 | } | |
10757 | ||
10758 | /* get statistics counter */ | |
f1c7e72e | 10759 | ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL, |
41c445ff JB |
10760 | &veb->stats_idx, NULL, NULL, NULL); |
10761 | if (ret) { | |
f1c7e72e SN |
10762 | dev_info(&pf->pdev->dev, |
10763 | "couldn't get VEB statistics idx, err %s aq_err %s\n", | |
10764 | i40e_stat_str(&pf->hw, ret), | |
10765 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10766 | return -EPERM; |
10767 | } | |
10768 | ret = i40e_veb_get_bw_info(veb); | |
10769 | if (ret) { | |
f1c7e72e SN |
10770 | dev_info(&pf->pdev->dev, |
10771 | "couldn't get VEB bw info, err %s aq_err %s\n", | |
10772 | i40e_stat_str(&pf->hw, ret), | |
10773 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
10774 | i40e_aq_delete_element(&pf->hw, veb->seid, NULL); | |
41c445ff JB |
10775 | return -ENOENT; |
10776 | } | |
10777 | ||
10778 | vsi->uplink_seid = veb->seid; | |
10779 | vsi->veb_idx = veb->idx; | |
10780 | vsi->flags |= I40E_VSI_FLAG_VEB_OWNER; | |
10781 | ||
10782 | return 0; | |
10783 | } | |
10784 | ||
10785 | /** | |
10786 | * i40e_veb_setup - Set up a VEB | |
10787 | * @pf: board private structure | |
10788 | * @flags: VEB setup flags | |
10789 | * @uplink_seid: the switch element to link to | |
10790 | * @vsi_seid: the initial VSI seid | |
10791 | * @enabled_tc: Enabled TC bit-map | |
10792 | * | |
10793 | * This allocates the sw VEB structure and links it into the switch | |
10794 | * It is possible and legal for this to be a duplicate of an already | |
10795 | * existing VEB. It is also possible for both uplink and vsi seids | |
10796 | * to be zero, in order to create a floating VEB. | |
10797 | * | |
10798 | * Returns pointer to the successfully allocated VEB sw struct on | |
10799 | * success, otherwise returns NULL on failure. | |
10800 | **/ | |
10801 | struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, | |
10802 | u16 uplink_seid, u16 vsi_seid, | |
10803 | u8 enabled_tc) | |
10804 | { | |
10805 | struct i40e_veb *veb, *uplink_veb = NULL; | |
10806 | int vsi_idx, veb_idx; | |
10807 | int ret; | |
10808 | ||
10809 | /* if one seid is 0, the other must be 0 to create a floating relay */ | |
10810 | if ((uplink_seid == 0 || vsi_seid == 0) && | |
10811 | (uplink_seid + vsi_seid != 0)) { | |
10812 | dev_info(&pf->pdev->dev, | |
10813 | "one, not both seid's are 0: uplink=%d vsi=%d\n", | |
10814 | uplink_seid, vsi_seid); | |
10815 | return NULL; | |
10816 | } | |
10817 | ||
10818 | /* make sure there is such a vsi and uplink */ | |
505682cd | 10819 | for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++) |
41c445ff JB |
10820 | if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid) |
10821 | break; | |
505682cd | 10822 | if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) { |
41c445ff JB |
10823 | dev_info(&pf->pdev->dev, "vsi seid %d not found\n", |
10824 | vsi_seid); | |
10825 | return NULL; | |
10826 | } | |
10827 | ||
10828 | if (uplink_seid && uplink_seid != pf->mac_seid) { | |
10829 | for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) { | |
10830 | if (pf->veb[veb_idx] && | |
10831 | pf->veb[veb_idx]->seid == uplink_seid) { | |
10832 | uplink_veb = pf->veb[veb_idx]; | |
10833 | break; | |
10834 | } | |
10835 | } | |
10836 | if (!uplink_veb) { | |
10837 | dev_info(&pf->pdev->dev, | |
10838 | "uplink seid %d not found\n", uplink_seid); | |
10839 | return NULL; | |
10840 | } | |
10841 | } | |
10842 | ||
10843 | /* get veb sw struct */ | |
10844 | veb_idx = i40e_veb_mem_alloc(pf); | |
10845 | if (veb_idx < 0) | |
10846 | goto err_alloc; | |
10847 | veb = pf->veb[veb_idx]; | |
10848 | veb->flags = flags; | |
10849 | veb->uplink_seid = uplink_seid; | |
10850 | veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB); | |
10851 | veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1); | |
10852 | ||
10853 | /* create the VEB in the switch */ | |
10854 | ret = i40e_add_veb(veb, pf->vsi[vsi_idx]); | |
10855 | if (ret) | |
10856 | goto err_veb; | |
1bb8b935 SN |
10857 | if (vsi_idx == pf->lan_vsi) |
10858 | pf->lan_veb = veb->idx; | |
41c445ff JB |
10859 | |
10860 | return veb; | |
10861 | ||
10862 | err_veb: | |
10863 | i40e_veb_clear(veb); | |
10864 | err_alloc: | |
10865 | return NULL; | |
10866 | } | |
10867 | ||
10868 | /** | |
b40c82e6 | 10869 | * i40e_setup_pf_switch_element - set PF vars based on switch type |
41c445ff JB |
10870 | * @pf: board private structure |
10871 | * @ele: element we are building info from | |
10872 | * @num_reported: total number of elements | |
10873 | * @printconfig: should we print the contents | |
10874 | * | |
10875 | * helper function to assist in extracting a few useful SEID values. | |
10876 | **/ | |
10877 | static void i40e_setup_pf_switch_element(struct i40e_pf *pf, | |
10878 | struct i40e_aqc_switch_config_element_resp *ele, | |
10879 | u16 num_reported, bool printconfig) | |
10880 | { | |
10881 | u16 downlink_seid = le16_to_cpu(ele->downlink_seid); | |
10882 | u16 uplink_seid = le16_to_cpu(ele->uplink_seid); | |
10883 | u8 element_type = ele->element_type; | |
10884 | u16 seid = le16_to_cpu(ele->seid); | |
10885 | ||
10886 | if (printconfig) | |
10887 | dev_info(&pf->pdev->dev, | |
10888 | "type=%d seid=%d uplink=%d downlink=%d\n", | |
10889 | element_type, seid, uplink_seid, downlink_seid); | |
10890 | ||
10891 | switch (element_type) { | |
10892 | case I40E_SWITCH_ELEMENT_TYPE_MAC: | |
10893 | pf->mac_seid = seid; | |
10894 | break; | |
10895 | case I40E_SWITCH_ELEMENT_TYPE_VEB: | |
10896 | /* Main VEB? */ | |
10897 | if (uplink_seid != pf->mac_seid) | |
10898 | break; | |
10899 | if (pf->lan_veb == I40E_NO_VEB) { | |
10900 | int v; | |
10901 | ||
10902 | /* find existing or else empty VEB */ | |
10903 | for (v = 0; v < I40E_MAX_VEB; v++) { | |
10904 | if (pf->veb[v] && (pf->veb[v]->seid == seid)) { | |
10905 | pf->lan_veb = v; | |
10906 | break; | |
10907 | } | |
10908 | } | |
10909 | if (pf->lan_veb == I40E_NO_VEB) { | |
10910 | v = i40e_veb_mem_alloc(pf); | |
10911 | if (v < 0) | |
10912 | break; | |
10913 | pf->lan_veb = v; | |
10914 | } | |
10915 | } | |
10916 | ||
10917 | pf->veb[pf->lan_veb]->seid = seid; | |
10918 | pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid; | |
10919 | pf->veb[pf->lan_veb]->pf = pf; | |
10920 | pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB; | |
10921 | break; | |
10922 | case I40E_SWITCH_ELEMENT_TYPE_VSI: | |
10923 | if (num_reported != 1) | |
10924 | break; | |
10925 | /* This is immediately after a reset so we can assume this is | |
10926 | * the PF's VSI | |
10927 | */ | |
10928 | pf->mac_seid = uplink_seid; | |
10929 | pf->pf_seid = downlink_seid; | |
10930 | pf->main_vsi_seid = seid; | |
10931 | if (printconfig) | |
10932 | dev_info(&pf->pdev->dev, | |
10933 | "pf_seid=%d main_vsi_seid=%d\n", | |
10934 | pf->pf_seid, pf->main_vsi_seid); | |
10935 | break; | |
10936 | case I40E_SWITCH_ELEMENT_TYPE_PF: | |
10937 | case I40E_SWITCH_ELEMENT_TYPE_VF: | |
10938 | case I40E_SWITCH_ELEMENT_TYPE_EMP: | |
10939 | case I40E_SWITCH_ELEMENT_TYPE_BMC: | |
10940 | case I40E_SWITCH_ELEMENT_TYPE_PE: | |
10941 | case I40E_SWITCH_ELEMENT_TYPE_PA: | |
10942 | /* ignore these for now */ | |
10943 | break; | |
10944 | default: | |
10945 | dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n", | |
10946 | element_type, seid); | |
10947 | break; | |
10948 | } | |
10949 | } | |
10950 | ||
10951 | /** | |
10952 | * i40e_fetch_switch_configuration - Get switch config from firmware | |
10953 | * @pf: board private structure | |
10954 | * @printconfig: should we print the contents | |
10955 | * | |
10956 | * Get the current switch configuration from the device and | |
10957 | * extract a few useful SEID values. | |
10958 | **/ | |
10959 | int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig) | |
10960 | { | |
10961 | struct i40e_aqc_get_switch_config_resp *sw_config; | |
10962 | u16 next_seid = 0; | |
10963 | int ret = 0; | |
10964 | u8 *aq_buf; | |
10965 | int i; | |
10966 | ||
10967 | aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL); | |
10968 | if (!aq_buf) | |
10969 | return -ENOMEM; | |
10970 | ||
10971 | sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf; | |
10972 | do { | |
10973 | u16 num_reported, num_total; | |
10974 | ||
10975 | ret = i40e_aq_get_switch_config(&pf->hw, sw_config, | |
10976 | I40E_AQ_LARGE_BUF, | |
10977 | &next_seid, NULL); | |
10978 | if (ret) { | |
10979 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
10980 | "get switch config failed err %s aq_err %s\n", |
10981 | i40e_stat_str(&pf->hw, ret), | |
10982 | i40e_aq_str(&pf->hw, | |
10983 | pf->hw.aq.asq_last_status)); | |
41c445ff JB |
10984 | kfree(aq_buf); |
10985 | return -ENOENT; | |
10986 | } | |
10987 | ||
10988 | num_reported = le16_to_cpu(sw_config->header.num_reported); | |
10989 | num_total = le16_to_cpu(sw_config->header.num_total); | |
10990 | ||
10991 | if (printconfig) | |
10992 | dev_info(&pf->pdev->dev, | |
10993 | "header: %d reported %d total\n", | |
10994 | num_reported, num_total); | |
10995 | ||
41c445ff JB |
10996 | for (i = 0; i < num_reported; i++) { |
10997 | struct i40e_aqc_switch_config_element_resp *ele = | |
10998 | &sw_config->element[i]; | |
10999 | ||
11000 | i40e_setup_pf_switch_element(pf, ele, num_reported, | |
11001 | printconfig); | |
11002 | } | |
11003 | } while (next_seid != 0); | |
11004 | ||
11005 | kfree(aq_buf); | |
11006 | return ret; | |
11007 | } | |
11008 | ||
11009 | /** | |
11010 | * i40e_setup_pf_switch - Setup the HW switch on startup or after reset | |
11011 | * @pf: board private structure | |
bc7d338f | 11012 | * @reinit: if the Main VSI needs to re-initialized. |
41c445ff JB |
11013 | * |
11014 | * Returns 0 on success, negative value on failure | |
11015 | **/ | |
bc7d338f | 11016 | static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit) |
41c445ff | 11017 | { |
b5569892 | 11018 | u16 flags = 0; |
41c445ff JB |
11019 | int ret; |
11020 | ||
11021 | /* find out what's out there already */ | |
11022 | ret = i40e_fetch_switch_configuration(pf, false); | |
11023 | if (ret) { | |
11024 | dev_info(&pf->pdev->dev, | |
f1c7e72e SN |
11025 | "couldn't fetch switch config, err %s aq_err %s\n", |
11026 | i40e_stat_str(&pf->hw, ret), | |
11027 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
41c445ff JB |
11028 | return ret; |
11029 | } | |
11030 | i40e_pf_reset_stats(pf); | |
11031 | ||
b5569892 ASJ |
11032 | /* set the switch config bit for the whole device to |
11033 | * support limited promisc or true promisc | |
11034 | * when user requests promisc. The default is limited | |
11035 | * promisc. | |
11036 | */ | |
11037 | ||
11038 | if ((pf->hw.pf_id == 0) && | |
11039 | !(pf->flags & I40E_FLAG_TRUE_PROMISC_SUPPORT)) | |
11040 | flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; | |
11041 | ||
11042 | if (pf->hw.pf_id == 0) { | |
11043 | u16 valid_flags; | |
11044 | ||
11045 | valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC; | |
11046 | ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags, | |
11047 | NULL); | |
11048 | if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) { | |
11049 | dev_info(&pf->pdev->dev, | |
11050 | "couldn't set switch config bits, err %s aq_err %s\n", | |
11051 | i40e_stat_str(&pf->hw, ret), | |
11052 | i40e_aq_str(&pf->hw, | |
11053 | pf->hw.aq.asq_last_status)); | |
11054 | /* not a fatal problem, just keep going */ | |
11055 | } | |
11056 | } | |
11057 | ||
41c445ff | 11058 | /* first time setup */ |
bc7d338f | 11059 | if (pf->lan_vsi == I40E_NO_VSI || reinit) { |
41c445ff JB |
11060 | struct i40e_vsi *vsi = NULL; |
11061 | u16 uplink_seid; | |
11062 | ||
11063 | /* Set up the PF VSI associated with the PF's main VSI | |
11064 | * that is already in the HW switch | |
11065 | */ | |
11066 | if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb]) | |
11067 | uplink_seid = pf->veb[pf->lan_veb]->seid; | |
11068 | else | |
11069 | uplink_seid = pf->mac_seid; | |
bc7d338f ASJ |
11070 | if (pf->lan_vsi == I40E_NO_VSI) |
11071 | vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0); | |
11072 | else if (reinit) | |
11073 | vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]); | |
41c445ff JB |
11074 | if (!vsi) { |
11075 | dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n"); | |
11076 | i40e_fdir_teardown(pf); | |
11077 | return -EAGAIN; | |
11078 | } | |
41c445ff JB |
11079 | } else { |
11080 | /* force a reset of TC and queue layout configurations */ | |
11081 | u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc; | |
6995b36c | 11082 | |
41c445ff JB |
11083 | pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0; |
11084 | pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid; | |
11085 | i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc); | |
11086 | } | |
11087 | i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]); | |
11088 | ||
cbf61325 ASJ |
11089 | i40e_fdir_sb_setup(pf); |
11090 | ||
41c445ff JB |
11091 | /* Setup static PF queue filter control settings */ |
11092 | ret = i40e_setup_pf_filter_control(pf); | |
11093 | if (ret) { | |
11094 | dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n", | |
11095 | ret); | |
11096 | /* Failure here should not stop continuing other steps */ | |
11097 | } | |
11098 | ||
11099 | /* enable RSS in the HW, even for only one queue, as the stack can use | |
11100 | * the hash | |
11101 | */ | |
11102 | if ((pf->flags & I40E_FLAG_RSS_ENABLED)) | |
043dd650 | 11103 | i40e_pf_config_rss(pf); |
41c445ff JB |
11104 | |
11105 | /* fill in link information and enable LSE reporting */ | |
a34a6711 MW |
11106 | i40e_link_event(pf); |
11107 | ||
d52c20b7 | 11108 | /* Initialize user-specific link properties */ |
41c445ff JB |
11109 | pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info & |
11110 | I40E_AQ_AN_COMPLETED) ? true : false); | |
d52c20b7 | 11111 | |
beb0dff1 JK |
11112 | i40e_ptp_init(pf); |
11113 | ||
1f190d93 AD |
11114 | /* repopulate tunnel port filters */ |
11115 | i40e_sync_udp_filters(pf); | |
11116 | ||
41c445ff JB |
11117 | return ret; |
11118 | } | |
11119 | ||
41c445ff JB |
11120 | /** |
11121 | * i40e_determine_queue_usage - Work out queue distribution | |
11122 | * @pf: board private structure | |
11123 | **/ | |
11124 | static void i40e_determine_queue_usage(struct i40e_pf *pf) | |
11125 | { | |
41c445ff | 11126 | int queues_left; |
e50d5751 | 11127 | int q_max; |
41c445ff JB |
11128 | |
11129 | pf->num_lan_qps = 0; | |
41c445ff JB |
11130 | |
11131 | /* Find the max queues to be put into basic use. We'll always be | |
11132 | * using TC0, whether or not DCB is running, and TC0 will get the | |
11133 | * big RSS set. | |
11134 | */ | |
11135 | queues_left = pf->hw.func_caps.num_tx_qp; | |
11136 | ||
cbf61325 | 11137 | if ((queues_left == 1) || |
9aa7e935 | 11138 | !(pf->flags & I40E_FLAG_MSIX_ENABLED)) { |
41c445ff JB |
11139 | /* one qp for PF, no queues for anything else */ |
11140 | queues_left = 0; | |
acd65448 | 11141 | pf->alloc_rss_size = pf->num_lan_qps = 1; |
41c445ff JB |
11142 | |
11143 | /* make sure all the fancies are disabled */ | |
60ea5f83 | 11144 | pf->flags &= ~(I40E_FLAG_RSS_ENABLED | |
e3219ce6 | 11145 | I40E_FLAG_IWARP_ENABLED | |
60ea5f83 JB |
11146 | I40E_FLAG_FD_SB_ENABLED | |
11147 | I40E_FLAG_FD_ATR_ENABLED | | |
4d9b6043 | 11148 | I40E_FLAG_DCB_CAPABLE | |
a036244c | 11149 | I40E_FLAG_DCB_ENABLED | |
60ea5f83 JB |
11150 | I40E_FLAG_SRIOV_ENABLED | |
11151 | I40E_FLAG_VMDQ_ENABLED); | |
9aa7e935 FZ |
11152 | } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED | |
11153 | I40E_FLAG_FD_SB_ENABLED | | |
bbe7d0e0 | 11154 | I40E_FLAG_FD_ATR_ENABLED | |
4d9b6043 | 11155 | I40E_FLAG_DCB_CAPABLE))) { |
9aa7e935 | 11156 | /* one qp for PF */ |
acd65448 | 11157 | pf->alloc_rss_size = pf->num_lan_qps = 1; |
9aa7e935 FZ |
11158 | queues_left -= pf->num_lan_qps; |
11159 | ||
11160 | pf->flags &= ~(I40E_FLAG_RSS_ENABLED | | |
e3219ce6 | 11161 | I40E_FLAG_IWARP_ENABLED | |
9aa7e935 FZ |
11162 | I40E_FLAG_FD_SB_ENABLED | |
11163 | I40E_FLAG_FD_ATR_ENABLED | | |
11164 | I40E_FLAG_DCB_ENABLED | | |
11165 | I40E_FLAG_VMDQ_ENABLED); | |
41c445ff | 11166 | } else { |
cbf61325 | 11167 | /* Not enough queues for all TCs */ |
4d9b6043 | 11168 | if ((pf->flags & I40E_FLAG_DCB_CAPABLE) && |
cbf61325 | 11169 | (queues_left < I40E_MAX_TRAFFIC_CLASS)) { |
a036244c DE |
11170 | pf->flags &= ~(I40E_FLAG_DCB_CAPABLE | |
11171 | I40E_FLAG_DCB_ENABLED); | |
cbf61325 ASJ |
11172 | dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n"); |
11173 | } | |
e50d5751 SN |
11174 | |
11175 | /* limit lan qps to the smaller of qps, cpus or msix */ | |
11176 | q_max = max_t(int, pf->rss_size_max, num_online_cpus()); | |
11177 | q_max = min_t(int, q_max, pf->hw.func_caps.num_tx_qp); | |
11178 | q_max = min_t(int, q_max, pf->hw.func_caps.num_msix_vectors); | |
11179 | pf->num_lan_qps = q_max; | |
9a3bd2f1 | 11180 | |
cbf61325 ASJ |
11181 | queues_left -= pf->num_lan_qps; |
11182 | } | |
11183 | ||
11184 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { | |
11185 | if (queues_left > 1) { | |
11186 | queues_left -= 1; /* save 1 queue for FD */ | |
11187 | } else { | |
11188 | pf->flags &= ~I40E_FLAG_FD_SB_ENABLED; | |
11189 | dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n"); | |
11190 | } | |
41c445ff JB |
11191 | } |
11192 | ||
11193 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
11194 | pf->num_vf_qps && pf->num_req_vfs && queues_left) { | |
cbf61325 ASJ |
11195 | pf->num_req_vfs = min_t(int, pf->num_req_vfs, |
11196 | (queues_left / pf->num_vf_qps)); | |
41c445ff JB |
11197 | queues_left -= (pf->num_req_vfs * pf->num_vf_qps); |
11198 | } | |
11199 | ||
11200 | if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) && | |
11201 | pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) { | |
11202 | pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis, | |
11203 | (queues_left / pf->num_vmdq_qps)); | |
11204 | queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps); | |
11205 | } | |
11206 | ||
f8ff1464 | 11207 | pf->queues_left = queues_left; |
8279e495 NP |
11208 | dev_dbg(&pf->pdev->dev, |
11209 | "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n", | |
11210 | pf->hw.func_caps.num_tx_qp, | |
11211 | !!(pf->flags & I40E_FLAG_FD_SB_ENABLED), | |
acd65448 HZ |
11212 | pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs, |
11213 | pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps, | |
11214 | queues_left); | |
41c445ff JB |
11215 | } |
11216 | ||
11217 | /** | |
11218 | * i40e_setup_pf_filter_control - Setup PF static filter control | |
11219 | * @pf: PF to be setup | |
11220 | * | |
b40c82e6 | 11221 | * i40e_setup_pf_filter_control sets up a PF's initial filter control |
41c445ff JB |
11222 | * settings. If PE/FCoE are enabled then it will also set the per PF |
11223 | * based filter sizes required for them. It also enables Flow director, | |
11224 | * ethertype and macvlan type filter settings for the pf. | |
11225 | * | |
11226 | * Returns 0 on success, negative on failure | |
11227 | **/ | |
11228 | static int i40e_setup_pf_filter_control(struct i40e_pf *pf) | |
11229 | { | |
11230 | struct i40e_filter_control_settings *settings = &pf->filter_settings; | |
11231 | ||
11232 | settings->hash_lut_size = I40E_HASH_LUT_SIZE_128; | |
11233 | ||
11234 | /* Flow Director is enabled */ | |
60ea5f83 | 11235 | if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)) |
41c445ff JB |
11236 | settings->enable_fdir = true; |
11237 | ||
11238 | /* Ethtype and MACVLAN filters enabled for PF */ | |
11239 | settings->enable_ethtype = true; | |
11240 | settings->enable_macvlan = true; | |
11241 | ||
11242 | if (i40e_set_filter_control(&pf->hw, settings)) | |
11243 | return -ENOENT; | |
11244 | ||
11245 | return 0; | |
11246 | } | |
11247 | ||
0c22b3dd | 11248 | #define INFO_STRING_LEN 255 |
7fd89545 | 11249 | #define REMAIN(__x) (INFO_STRING_LEN - (__x)) |
0c22b3dd JB |
11250 | static void i40e_print_features(struct i40e_pf *pf) |
11251 | { | |
11252 | struct i40e_hw *hw = &pf->hw; | |
3b195843 JP |
11253 | char *buf; |
11254 | int i; | |
0c22b3dd | 11255 | |
3b195843 JP |
11256 | buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL); |
11257 | if (!buf) | |
0c22b3dd | 11258 | return; |
0c22b3dd | 11259 | |
3b195843 | 11260 | i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id); |
0c22b3dd | 11261 | #ifdef CONFIG_PCI_IOV |
3b195843 | 11262 | i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs); |
0c22b3dd | 11263 | #endif |
1a557afc | 11264 | i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d", |
7fd89545 | 11265 | pf->hw.func_caps.num_vsis, |
1a557afc | 11266 | pf->vsi[pf->lan_vsi]->num_queue_pairs); |
0c22b3dd | 11267 | if (pf->flags & I40E_FLAG_RSS_ENABLED) |
3b195843 | 11268 | i += snprintf(&buf[i], REMAIN(i), " RSS"); |
0c22b3dd | 11269 | if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) |
3b195843 | 11270 | i += snprintf(&buf[i], REMAIN(i), " FD_ATR"); |
c6423ff1 | 11271 | if (pf->flags & I40E_FLAG_FD_SB_ENABLED) { |
3b195843 JP |
11272 | i += snprintf(&buf[i], REMAIN(i), " FD_SB"); |
11273 | i += snprintf(&buf[i], REMAIN(i), " NTUPLE"); | |
c6423ff1 | 11274 | } |
4d9b6043 | 11275 | if (pf->flags & I40E_FLAG_DCB_CAPABLE) |
3b195843 | 11276 | i += snprintf(&buf[i], REMAIN(i), " DCB"); |
3b195843 | 11277 | i += snprintf(&buf[i], REMAIN(i), " VxLAN"); |
6a899024 | 11278 | i += snprintf(&buf[i], REMAIN(i), " Geneve"); |
0c22b3dd | 11279 | if (pf->flags & I40E_FLAG_PTP) |
3b195843 | 11280 | i += snprintf(&buf[i], REMAIN(i), " PTP"); |
6dec1017 | 11281 | if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) |
3b195843 | 11282 | i += snprintf(&buf[i], REMAIN(i), " VEB"); |
6dec1017 | 11283 | else |
3b195843 | 11284 | i += snprintf(&buf[i], REMAIN(i), " VEPA"); |
0c22b3dd | 11285 | |
3b195843 JP |
11286 | dev_info(&pf->pdev->dev, "%s\n", buf); |
11287 | kfree(buf); | |
7fd89545 | 11288 | WARN_ON(i > INFO_STRING_LEN); |
0c22b3dd JB |
11289 | } |
11290 | ||
b499ffb0 SV |
11291 | /** |
11292 | * i40e_get_platform_mac_addr - get platform-specific MAC address | |
b499ffb0 SV |
11293 | * @pdev: PCI device information struct |
11294 | * @pf: board private structure | |
11295 | * | |
41c4c2b5 JK |
11296 | * Look up the MAC address for the device. First we'll try |
11297 | * eth_platform_get_mac_address, which will check Open Firmware, or arch | |
11298 | * specific fallback. Otherwise, we'll default to the stored value in | |
11299 | * firmware. | |
b499ffb0 SV |
11300 | **/ |
11301 | static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf) | |
11302 | { | |
41c4c2b5 JK |
11303 | if (eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr)) |
11304 | i40e_get_mac_addr(&pf->hw, pf->hw.mac.addr); | |
b499ffb0 SV |
11305 | } |
11306 | ||
41c445ff JB |
11307 | /** |
11308 | * i40e_probe - Device initialization routine | |
11309 | * @pdev: PCI device information struct | |
11310 | * @ent: entry in i40e_pci_tbl | |
11311 | * | |
b40c82e6 JK |
11312 | * i40e_probe initializes a PF identified by a pci_dev structure. |
11313 | * The OS initialization, configuring of the PF private structure, | |
41c445ff JB |
11314 | * and a hardware reset occur. |
11315 | * | |
11316 | * Returns 0 on success, negative on failure | |
11317 | **/ | |
11318 | static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
11319 | { | |
e827845c | 11320 | struct i40e_aq_get_phy_abilities_resp abilities; |
41c445ff JB |
11321 | struct i40e_pf *pf; |
11322 | struct i40e_hw *hw; | |
93cd765b | 11323 | static u16 pfs_found; |
1d5109d1 | 11324 | u16 wol_nvm_bits; |
d4dfb81a | 11325 | u16 link_status; |
6f66a484 | 11326 | int err; |
4f2f017c | 11327 | u32 val; |
8a9eb7d3 | 11328 | u32 i; |
58fc3267 | 11329 | u8 set_fc_aq_fail; |
41c445ff JB |
11330 | |
11331 | err = pci_enable_device_mem(pdev); | |
11332 | if (err) | |
11333 | return err; | |
11334 | ||
11335 | /* set up for high or low dma */ | |
6494294f | 11336 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
6494294f | 11337 | if (err) { |
e3e3bfdd JS |
11338 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
11339 | if (err) { | |
11340 | dev_err(&pdev->dev, | |
11341 | "DMA configuration failed: 0x%x\n", err); | |
11342 | goto err_dma; | |
11343 | } | |
41c445ff JB |
11344 | } |
11345 | ||
11346 | /* set up pci connections */ | |
56d766d6 | 11347 | err = pci_request_mem_regions(pdev, i40e_driver_name); |
41c445ff JB |
11348 | if (err) { |
11349 | dev_info(&pdev->dev, | |
11350 | "pci_request_selected_regions failed %d\n", err); | |
11351 | goto err_pci_reg; | |
11352 | } | |
11353 | ||
11354 | pci_enable_pcie_error_reporting(pdev); | |
11355 | pci_set_master(pdev); | |
11356 | ||
11357 | /* Now that we have a PCI connection, we need to do the | |
11358 | * low level device setup. This is primarily setting up | |
11359 | * the Admin Queue structures and then querying for the | |
11360 | * device's current profile information. | |
11361 | */ | |
11362 | pf = kzalloc(sizeof(*pf), GFP_KERNEL); | |
11363 | if (!pf) { | |
11364 | err = -ENOMEM; | |
11365 | goto err_pf_alloc; | |
11366 | } | |
11367 | pf->next_vsi = 0; | |
11368 | pf->pdev = pdev; | |
9e6c9c0f | 11369 | set_bit(__I40E_DOWN, pf->state); |
41c445ff JB |
11370 | |
11371 | hw = &pf->hw; | |
11372 | hw->back = pf; | |
232f4706 | 11373 | |
2ac8b675 SN |
11374 | pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0), |
11375 | I40E_MAX_CSR_SPACE); | |
232f4706 | 11376 | |
2ac8b675 | 11377 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len); |
41c445ff JB |
11378 | if (!hw->hw_addr) { |
11379 | err = -EIO; | |
11380 | dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n", | |
11381 | (unsigned int)pci_resource_start(pdev, 0), | |
2ac8b675 | 11382 | pf->ioremap_len, err); |
41c445ff JB |
11383 | goto err_ioremap; |
11384 | } | |
11385 | hw->vendor_id = pdev->vendor; | |
11386 | hw->device_id = pdev->device; | |
11387 | pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id); | |
11388 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
11389 | hw->subsystem_device_id = pdev->subsystem_device; | |
11390 | hw->bus.device = PCI_SLOT(pdev->devfn); | |
11391 | hw->bus.func = PCI_FUNC(pdev->devfn); | |
b3f028fc | 11392 | hw->bus.bus_id = pdev->bus->number; |
93cd765b | 11393 | pf->instance = pfs_found; |
41c445ff | 11394 | |
ab243ec9 SP |
11395 | /* Select something other than the 802.1ad ethertype for the |
11396 | * switch to use internally and drop on ingress. | |
11397 | */ | |
11398 | hw->switch_tag = 0xffff; | |
11399 | hw->first_tag = ETH_P_8021AD; | |
11400 | hw->second_tag = ETH_P_8021Q; | |
11401 | ||
0e588de1 JK |
11402 | INIT_LIST_HEAD(&pf->l3_flex_pit_list); |
11403 | INIT_LIST_HEAD(&pf->l4_flex_pit_list); | |
11404 | ||
de03d2b0 SN |
11405 | /* set up the locks for the AQ, do this only once in probe |
11406 | * and destroy them only once in remove | |
11407 | */ | |
11408 | mutex_init(&hw->aq.asq_mutex); | |
11409 | mutex_init(&hw->aq.arq_mutex); | |
11410 | ||
5d4ca23e AD |
11411 | pf->msg_enable = netif_msg_init(debug, |
11412 | NETIF_MSG_DRV | | |
11413 | NETIF_MSG_PROBE | | |
11414 | NETIF_MSG_LINK); | |
11415 | if (debug < -1) | |
11416 | pf->hw.debug_mask = debug; | |
5b5faa43 | 11417 | |
7134f9ce JB |
11418 | /* do a special CORER for clearing PXE mode once at init */ |
11419 | if (hw->revision_id == 0 && | |
11420 | (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) { | |
11421 | wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK); | |
11422 | i40e_flush(hw); | |
11423 | msleep(200); | |
11424 | pf->corer_count++; | |
11425 | ||
11426 | i40e_clear_pxe_mode(hw); | |
11427 | } | |
11428 | ||
41c445ff | 11429 | /* Reset here to make sure all is clean and to define PF 'n' */ |
838d41d9 | 11430 | i40e_clear_hw(hw); |
41c445ff JB |
11431 | err = i40e_pf_reset(hw); |
11432 | if (err) { | |
11433 | dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err); | |
11434 | goto err_pf_reset; | |
11435 | } | |
11436 | pf->pfr_count++; | |
11437 | ||
11438 | hw->aq.num_arq_entries = I40E_AQ_LEN; | |
11439 | hw->aq.num_asq_entries = I40E_AQ_LEN; | |
11440 | hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE; | |
11441 | hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE; | |
11442 | pf->adminq_work_limit = I40E_AQ_WORK_LIMIT; | |
b2008cbf | 11443 | |
b294ac70 | 11444 | snprintf(pf->int_name, sizeof(pf->int_name) - 1, |
b2008cbf CW |
11445 | "%s-%s:misc", |
11446 | dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev)); | |
41c445ff JB |
11447 | |
11448 | err = i40e_init_shared_code(hw); | |
11449 | if (err) { | |
b2a75c58 ASJ |
11450 | dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n", |
11451 | err); | |
41c445ff JB |
11452 | goto err_pf_reset; |
11453 | } | |
11454 | ||
d52c20b7 JB |
11455 | /* set up a default setting for link flow control */ |
11456 | pf->hw.fc.requested_mode = I40E_FC_NONE; | |
11457 | ||
41c445ff | 11458 | err = i40e_init_adminq(hw); |
2b2426a7 CW |
11459 | if (err) { |
11460 | if (err == I40E_ERR_FIRMWARE_API_VERSION) | |
11461 | dev_info(&pdev->dev, | |
11462 | "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n"); | |
11463 | else | |
11464 | dev_info(&pdev->dev, | |
11465 | "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n"); | |
11466 | ||
11467 | goto err_pf_reset; | |
11468 | } | |
5bbb2e20 | 11469 | i40e_get_oem_version(hw); |
f0b44440 | 11470 | |
6dec1017 SN |
11471 | /* provide nvm, fw, api versions */ |
11472 | dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n", | |
11473 | hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build, | |
11474 | hw->aq.api_maj_ver, hw->aq.api_min_ver, | |
11475 | i40e_nvm_version_str(hw)); | |
f0b44440 | 11476 | |
7aa67613 | 11477 | if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR && |
22b96551 | 11478 | hw->aq.api_min_ver > I40E_FW_MINOR_VERSION(hw)) |
278b6f62 | 11479 | dev_info(&pdev->dev, |
7aa67613 | 11480 | "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n"); |
e04ea002 | 11481 | else if (hw->aq.api_maj_ver == 1 && hw->aq.api_min_ver < 4) |
278b6f62 | 11482 | dev_info(&pdev->dev, |
7aa67613 | 11483 | "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n"); |
278b6f62 | 11484 | |
4eb3f768 SN |
11485 | i40e_verify_eeprom(pf); |
11486 | ||
2c5fe33b JB |
11487 | /* Rev 0 hardware was never productized */ |
11488 | if (hw->revision_id < 1) | |
11489 | dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n"); | |
11490 | ||
6ff4ef86 | 11491 | i40e_clear_pxe_mode(hw); |
41c445ff JB |
11492 | err = i40e_get_capabilities(pf); |
11493 | if (err) | |
11494 | goto err_adminq_setup; | |
11495 | ||
11496 | err = i40e_sw_init(pf); | |
11497 | if (err) { | |
11498 | dev_info(&pdev->dev, "sw_init failed: %d\n", err); | |
11499 | goto err_sw_init; | |
11500 | } | |
11501 | ||
11502 | err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp, | |
c76cb6ed | 11503 | hw->func_caps.num_rx_qp, 0, 0); |
41c445ff JB |
11504 | if (err) { |
11505 | dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err); | |
11506 | goto err_init_lan_hmc; | |
11507 | } | |
11508 | ||
11509 | err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY); | |
11510 | if (err) { | |
11511 | dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err); | |
11512 | err = -ENOENT; | |
11513 | goto err_configure_lan_hmc; | |
11514 | } | |
11515 | ||
b686ece5 NP |
11516 | /* Disable LLDP for NICs that have firmware versions lower than v4.3. |
11517 | * Ignore error return codes because if it was already disabled via | |
11518 | * hardware settings this will fail | |
11519 | */ | |
d36e41dc | 11520 | if (pf->hw_features & I40E_HW_STOP_FW_LLDP) { |
b686ece5 NP |
11521 | dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n"); |
11522 | i40e_aq_stop_lldp(hw, true, NULL); | |
11523 | } | |
11524 | ||
b499ffb0 SV |
11525 | /* allow a platform config to override the HW addr */ |
11526 | i40e_get_platform_mac_addr(pdev, pf); | |
41c4c2b5 | 11527 | |
f62b5060 | 11528 | if (!is_valid_ether_addr(hw->mac.addr)) { |
41c445ff JB |
11529 | dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr); |
11530 | err = -EIO; | |
11531 | goto err_mac_addr; | |
11532 | } | |
11533 | dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr); | |
9a173901 | 11534 | ether_addr_copy(hw->mac.perm_addr, hw->mac.addr); |
1f224ad2 NP |
11535 | i40e_get_port_mac_addr(hw, hw->mac.port_addr); |
11536 | if (is_valid_ether_addr(hw->mac.port_addr)) | |
d36e41dc | 11537 | pf->hw_features |= I40E_HW_PORT_ID_VALID; |
41c445ff JB |
11538 | |
11539 | pci_set_drvdata(pdev, pf); | |
11540 | pci_save_state(pdev); | |
4e3b35b0 NP |
11541 | #ifdef CONFIG_I40E_DCB |
11542 | err = i40e_init_pf_dcb(pf); | |
11543 | if (err) { | |
aebfc816 | 11544 | dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err); |
c17ef430 | 11545 | pf->flags &= ~(I40E_FLAG_DCB_CAPABLE | I40E_FLAG_DCB_ENABLED); |
014269ff | 11546 | /* Continue without DCB enabled */ |
4e3b35b0 NP |
11547 | } |
11548 | #endif /* CONFIG_I40E_DCB */ | |
41c445ff JB |
11549 | |
11550 | /* set up periodic task facility */ | |
11551 | setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf); | |
11552 | pf->service_timer_period = HZ; | |
11553 | ||
11554 | INIT_WORK(&pf->service_task, i40e_service_task); | |
0da36b97 | 11555 | clear_bit(__I40E_SERVICE_SCHED, pf->state); |
41c445ff | 11556 | |
1d5109d1 SN |
11557 | /* NVM bit on means WoL disabled for the port */ |
11558 | i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits); | |
75f5cea9 | 11559 | if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1) |
1d5109d1 SN |
11560 | pf->wol_en = false; |
11561 | else | |
11562 | pf->wol_en = true; | |
8e2773ae SN |
11563 | device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en); |
11564 | ||
41c445ff JB |
11565 | /* set up the main switch operations */ |
11566 | i40e_determine_queue_usage(pf); | |
c1147280 JB |
11567 | err = i40e_init_interrupt_scheme(pf); |
11568 | if (err) | |
11569 | goto err_switch_setup; | |
41c445ff | 11570 | |
505682cd MW |
11571 | /* The number of VSIs reported by the FW is the minimum guaranteed |
11572 | * to us; HW supports far more and we share the remaining pool with | |
11573 | * the other PFs. We allocate space for more than the guarantee with | |
11574 | * the understanding that we might not get them all later. | |
41c445ff | 11575 | */ |
505682cd MW |
11576 | if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC) |
11577 | pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC; | |
11578 | else | |
11579 | pf->num_alloc_vsi = pf->hw.func_caps.num_vsis; | |
11580 | ||
11581 | /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */ | |
d17038d6 JB |
11582 | pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *), |
11583 | GFP_KERNEL); | |
ed87ac09 WY |
11584 | if (!pf->vsi) { |
11585 | err = -ENOMEM; | |
41c445ff | 11586 | goto err_switch_setup; |
ed87ac09 | 11587 | } |
41c445ff | 11588 | |
fa11cb3d ASJ |
11589 | #ifdef CONFIG_PCI_IOV |
11590 | /* prep for VF support */ | |
11591 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
11592 | (pf->flags & I40E_FLAG_MSIX_ENABLED) && | |
0da36b97 | 11593 | !test_bit(__I40E_BAD_EEPROM, pf->state)) { |
fa11cb3d ASJ |
11594 | if (pci_num_vf(pdev)) |
11595 | pf->flags |= I40E_FLAG_VEB_MODE_ENABLED; | |
11596 | } | |
11597 | #endif | |
bc7d338f | 11598 | err = i40e_setup_pf_switch(pf, false); |
41c445ff JB |
11599 | if (err) { |
11600 | dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err); | |
11601 | goto err_vsis; | |
11602 | } | |
58fc3267 HZ |
11603 | |
11604 | /* Make sure flow control is set according to current settings */ | |
11605 | err = i40e_set_fc(hw, &set_fc_aq_fail, true); | |
11606 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET) | |
11607 | dev_dbg(&pf->pdev->dev, | |
11608 | "Set fc with err %s aq_err %s on get_phy_cap\n", | |
11609 | i40e_stat_str(hw, err), | |
11610 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
11611 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET) | |
11612 | dev_dbg(&pf->pdev->dev, | |
11613 | "Set fc with err %s aq_err %s on set_phy_config\n", | |
11614 | i40e_stat_str(hw, err), | |
11615 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
11616 | if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE) | |
11617 | dev_dbg(&pf->pdev->dev, | |
11618 | "Set fc with err %s aq_err %s on get_link_info\n", | |
11619 | i40e_stat_str(hw, err), | |
11620 | i40e_aq_str(hw, hw->aq.asq_last_status)); | |
11621 | ||
8a9eb7d3 | 11622 | /* if FDIR VSI was set up, start it now */ |
505682cd | 11623 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
8a9eb7d3 SN |
11624 | if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) { |
11625 | i40e_vsi_open(pf->vsi[i]); | |
11626 | break; | |
11627 | } | |
11628 | } | |
41c445ff | 11629 | |
2f0aff41 SN |
11630 | /* The driver only wants link up/down and module qualification |
11631 | * reports from firmware. Note the negative logic. | |
7e2453fe JB |
11632 | */ |
11633 | err = i40e_aq_set_phy_int_mask(&pf->hw, | |
2f0aff41 | 11634 | ~(I40E_AQ_EVENT_LINK_UPDOWN | |
867a79e3 | 11635 | I40E_AQ_EVENT_MEDIA_NA | |
2f0aff41 | 11636 | I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL); |
7e2453fe | 11637 | if (err) |
f1c7e72e SN |
11638 | dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n", |
11639 | i40e_stat_str(&pf->hw, err), | |
11640 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
7e2453fe | 11641 | |
4f2f017c ASJ |
11642 | /* Reconfigure hardware for allowing smaller MSS in the case |
11643 | * of TSO, so that we avoid the MDD being fired and causing | |
11644 | * a reset in the case of small MSS+TSO. | |
11645 | */ | |
11646 | val = rd32(hw, I40E_REG_MSS); | |
11647 | if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) { | |
11648 | val &= ~I40E_REG_MSS_MIN_MASK; | |
11649 | val |= I40E_64BYTE_MSS; | |
11650 | wr32(hw, I40E_REG_MSS, val); | |
11651 | } | |
11652 | ||
d36e41dc | 11653 | if (pf->hw_features & I40E_HW_RESTART_AUTONEG) { |
025b4a54 ASJ |
11654 | msleep(75); |
11655 | err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL); | |
11656 | if (err) | |
f1c7e72e SN |
11657 | dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n", |
11658 | i40e_stat_str(&pf->hw, err), | |
11659 | i40e_aq_str(&pf->hw, | |
11660 | pf->hw.aq.asq_last_status)); | |
cafa2ee6 | 11661 | } |
41c445ff JB |
11662 | /* The main driver is (mostly) up and happy. We need to set this state |
11663 | * before setting up the misc vector or we get a race and the vector | |
11664 | * ends up disabled forever. | |
11665 | */ | |
9e6c9c0f | 11666 | clear_bit(__I40E_DOWN, pf->state); |
41c445ff JB |
11667 | |
11668 | /* In case of MSIX we are going to setup the misc vector right here | |
11669 | * to handle admin queue events etc. In case of legacy and MSI | |
11670 | * the misc functionality and queue processing is combined in | |
11671 | * the same vector and that gets setup at open. | |
11672 | */ | |
11673 | if (pf->flags & I40E_FLAG_MSIX_ENABLED) { | |
11674 | err = i40e_setup_misc_vector(pf); | |
11675 | if (err) { | |
11676 | dev_info(&pdev->dev, | |
11677 | "setup of misc vector failed: %d\n", err); | |
11678 | goto err_vsis; | |
11679 | } | |
11680 | } | |
11681 | ||
df805f62 | 11682 | #ifdef CONFIG_PCI_IOV |
41c445ff JB |
11683 | /* prep for VF support */ |
11684 | if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) && | |
4eb3f768 | 11685 | (pf->flags & I40E_FLAG_MSIX_ENABLED) && |
0da36b97 | 11686 | !test_bit(__I40E_BAD_EEPROM, pf->state)) { |
41c445ff JB |
11687 | /* disable link interrupts for VFs */ |
11688 | val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM); | |
11689 | val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK; | |
11690 | wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val); | |
11691 | i40e_flush(hw); | |
4aeec010 MW |
11692 | |
11693 | if (pci_num_vf(pdev)) { | |
11694 | dev_info(&pdev->dev, | |
11695 | "Active VFs found, allocating resources.\n"); | |
11696 | err = i40e_alloc_vfs(pf, pci_num_vf(pdev)); | |
11697 | if (err) | |
11698 | dev_info(&pdev->dev, | |
11699 | "Error %d allocating resources for existing VFs\n", | |
11700 | err); | |
11701 | } | |
41c445ff | 11702 | } |
df805f62 | 11703 | #endif /* CONFIG_PCI_IOV */ |
41c445ff | 11704 | |
e3219ce6 ASJ |
11705 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
11706 | pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile, | |
11707 | pf->num_iwarp_msix, | |
11708 | I40E_IWARP_IRQ_PILE_ID); | |
11709 | if (pf->iwarp_base_vector < 0) { | |
11710 | dev_info(&pdev->dev, | |
11711 | "failed to get tracking for %d vectors for IWARP err=%d\n", | |
11712 | pf->num_iwarp_msix, pf->iwarp_base_vector); | |
11713 | pf->flags &= ~I40E_FLAG_IWARP_ENABLED; | |
11714 | } | |
11715 | } | |
93cd765b | 11716 | |
41c445ff JB |
11717 | i40e_dbg_pf_init(pf); |
11718 | ||
11719 | /* tell the firmware that we're starting */ | |
44033fac | 11720 | i40e_send_version(pf); |
41c445ff JB |
11721 | |
11722 | /* since everything's happy, start the service_task timer */ | |
11723 | mod_timer(&pf->service_timer, | |
11724 | round_jiffies(jiffies + pf->service_timer_period)); | |
11725 | ||
e3219ce6 | 11726 | /* add this PF to client device list and launch a client service task */ |
004eb614 MW |
11727 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
11728 | err = i40e_lan_add_device(pf); | |
11729 | if (err) | |
11730 | dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n", | |
11731 | err); | |
11732 | } | |
e3219ce6 | 11733 | |
3fced535 ASJ |
11734 | #define PCI_SPEED_SIZE 8 |
11735 | #define PCI_WIDTH_SIZE 8 | |
11736 | /* Devices on the IOSF bus do not have this information | |
11737 | * and will report PCI Gen 1 x 1 by default so don't bother | |
11738 | * checking them. | |
11739 | */ | |
d36e41dc | 11740 | if (!(pf->hw_features & I40E_HW_NO_PCI_LINK_CHECK)) { |
3fced535 ASJ |
11741 | char speed[PCI_SPEED_SIZE] = "Unknown"; |
11742 | char width[PCI_WIDTH_SIZE] = "Unknown"; | |
11743 | ||
11744 | /* Get the negotiated link width and speed from PCI config | |
11745 | * space | |
11746 | */ | |
11747 | pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA, | |
11748 | &link_status); | |
11749 | ||
11750 | i40e_set_pci_config_data(hw, link_status); | |
11751 | ||
11752 | switch (hw->bus.speed) { | |
11753 | case i40e_bus_speed_8000: | |
11754 | strncpy(speed, "8.0", PCI_SPEED_SIZE); break; | |
11755 | case i40e_bus_speed_5000: | |
11756 | strncpy(speed, "5.0", PCI_SPEED_SIZE); break; | |
11757 | case i40e_bus_speed_2500: | |
11758 | strncpy(speed, "2.5", PCI_SPEED_SIZE); break; | |
11759 | default: | |
11760 | break; | |
11761 | } | |
11762 | switch (hw->bus.width) { | |
11763 | case i40e_bus_width_pcie_x8: | |
11764 | strncpy(width, "8", PCI_WIDTH_SIZE); break; | |
11765 | case i40e_bus_width_pcie_x4: | |
11766 | strncpy(width, "4", PCI_WIDTH_SIZE); break; | |
11767 | case i40e_bus_width_pcie_x2: | |
11768 | strncpy(width, "2", PCI_WIDTH_SIZE); break; | |
11769 | case i40e_bus_width_pcie_x1: | |
11770 | strncpy(width, "1", PCI_WIDTH_SIZE); break; | |
11771 | default: | |
11772 | break; | |
11773 | } | |
11774 | ||
11775 | dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n", | |
11776 | speed, width); | |
11777 | ||
11778 | if (hw->bus.width < i40e_bus_width_pcie_x8 || | |
11779 | hw->bus.speed < i40e_bus_speed_8000) { | |
11780 | dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n"); | |
11781 | dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n"); | |
11782 | } | |
d4dfb81a CS |
11783 | } |
11784 | ||
e827845c CS |
11785 | /* get the requested speeds from the fw */ |
11786 | err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL); | |
11787 | if (err) | |
8279e495 NP |
11788 | dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n", |
11789 | i40e_stat_str(&pf->hw, err), | |
11790 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
e827845c CS |
11791 | pf->hw.phy.link_info.requested_speeds = abilities.link_speed; |
11792 | ||
fc72dbce CS |
11793 | /* get the supported phy types from the fw */ |
11794 | err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL); | |
11795 | if (err) | |
11796 | dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n", | |
11797 | i40e_stat_str(&pf->hw, err), | |
11798 | i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status)); | |
fc72dbce | 11799 | |
e7358f54 ASJ |
11800 | /* Add a filter to drop all Flow control frames from any VSI from being |
11801 | * transmitted. By doing so we stop a malicious VF from sending out | |
11802 | * PAUSE or PFC frames and potentially controlling traffic for other | |
11803 | * PF/VF VSIs. | |
11804 | * The FW can still send Flow control frames if enabled. | |
11805 | */ | |
11806 | i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw, | |
11807 | pf->main_vsi_seid); | |
11808 | ||
31b606d0 | 11809 | if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) || |
4f9b4307 | 11810 | (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4)) |
d36e41dc | 11811 | pf->hw_features |= I40E_HW_PHY_CONTROLS_LEDS; |
4ad9f4f9 | 11812 | if (pf->hw.device_id == I40E_DEV_ID_SFP_I_X722) |
d36e41dc | 11813 | pf->hw_features |= I40E_HW_HAVE_CRT_RETIMER; |
0c22b3dd JB |
11814 | /* print a string summarizing features */ |
11815 | i40e_print_features(pf); | |
11816 | ||
41c445ff JB |
11817 | return 0; |
11818 | ||
11819 | /* Unwind what we've done if something failed in the setup */ | |
11820 | err_vsis: | |
9e6c9c0f | 11821 | set_bit(__I40E_DOWN, pf->state); |
41c445ff JB |
11822 | i40e_clear_interrupt_scheme(pf); |
11823 | kfree(pf->vsi); | |
04b03013 SN |
11824 | err_switch_setup: |
11825 | i40e_reset_interrupt_capability(pf); | |
41c445ff JB |
11826 | del_timer_sync(&pf->service_timer); |
11827 | err_mac_addr: | |
11828 | err_configure_lan_hmc: | |
11829 | (void)i40e_shutdown_lan_hmc(hw); | |
11830 | err_init_lan_hmc: | |
11831 | kfree(pf->qp_pile); | |
41c445ff JB |
11832 | err_sw_init: |
11833 | err_adminq_setup: | |
41c445ff JB |
11834 | err_pf_reset: |
11835 | iounmap(hw->hw_addr); | |
11836 | err_ioremap: | |
11837 | kfree(pf); | |
11838 | err_pf_alloc: | |
11839 | pci_disable_pcie_error_reporting(pdev); | |
56d766d6 | 11840 | pci_release_mem_regions(pdev); |
41c445ff JB |
11841 | err_pci_reg: |
11842 | err_dma: | |
11843 | pci_disable_device(pdev); | |
11844 | return err; | |
11845 | } | |
11846 | ||
11847 | /** | |
11848 | * i40e_remove - Device removal routine | |
11849 | * @pdev: PCI device information struct | |
11850 | * | |
11851 | * i40e_remove is called by the PCI subsystem to alert the driver | |
11852 | * that is should release a PCI device. This could be caused by a | |
11853 | * Hot-Plug event, or because the driver is going to be removed from | |
11854 | * memory. | |
11855 | **/ | |
11856 | static void i40e_remove(struct pci_dev *pdev) | |
11857 | { | |
11858 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
bcab2db9 | 11859 | struct i40e_hw *hw = &pf->hw; |
41c445ff | 11860 | i40e_status ret_code; |
41c445ff JB |
11861 | int i; |
11862 | ||
11863 | i40e_dbg_pf_exit(pf); | |
11864 | ||
beb0dff1 JK |
11865 | i40e_ptp_stop(pf); |
11866 | ||
bcab2db9 | 11867 | /* Disable RSS in hw */ |
272cdaf2 SN |
11868 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0); |
11869 | i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0); | |
bcab2db9 | 11870 | |
41c445ff | 11871 | /* no more scheduling of any task */ |
0da36b97 | 11872 | set_bit(__I40E_SUSPENDED, pf->state); |
9e6c9c0f | 11873 | set_bit(__I40E_DOWN, pf->state); |
c99abb4c SN |
11874 | if (pf->service_timer.data) |
11875 | del_timer_sync(&pf->service_timer); | |
11876 | if (pf->service_task.func) | |
11877 | cancel_work_sync(&pf->service_task); | |
41c445ff | 11878 | |
921c467c MW |
11879 | /* Client close must be called explicitly here because the timer |
11880 | * has been stopped. | |
11881 | */ | |
11882 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false); | |
11883 | ||
eb2d80bc MW |
11884 | if (pf->flags & I40E_FLAG_SRIOV_ENABLED) { |
11885 | i40e_free_vfs(pf); | |
11886 | pf->flags &= ~I40E_FLAG_SRIOV_ENABLED; | |
11887 | } | |
11888 | ||
41c445ff JB |
11889 | i40e_fdir_teardown(pf); |
11890 | ||
11891 | /* If there is a switch structure or any orphans, remove them. | |
11892 | * This will leave only the PF's VSI remaining. | |
11893 | */ | |
11894 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
11895 | if (!pf->veb[i]) | |
11896 | continue; | |
11897 | ||
11898 | if (pf->veb[i]->uplink_seid == pf->mac_seid || | |
11899 | pf->veb[i]->uplink_seid == 0) | |
11900 | i40e_switch_branch_release(pf->veb[i]); | |
11901 | } | |
11902 | ||
11903 | /* Now we can shutdown the PF's VSI, just before we kill | |
11904 | * adminq and hmc. | |
11905 | */ | |
11906 | if (pf->vsi[pf->lan_vsi]) | |
11907 | i40e_vsi_release(pf->vsi[pf->lan_vsi]); | |
11908 | ||
e3219ce6 | 11909 | /* remove attached clients */ |
004eb614 MW |
11910 | if (pf->flags & I40E_FLAG_IWARP_ENABLED) { |
11911 | ret_code = i40e_lan_del_device(pf); | |
11912 | if (ret_code) | |
11913 | dev_warn(&pdev->dev, "Failed to delete client device: %d\n", | |
11914 | ret_code); | |
e3219ce6 ASJ |
11915 | } |
11916 | ||
41c445ff | 11917 | /* shutdown and destroy the HMC */ |
f734dfff JB |
11918 | if (hw->hmc.hmc_obj) { |
11919 | ret_code = i40e_shutdown_lan_hmc(hw); | |
60442dea SN |
11920 | if (ret_code) |
11921 | dev_warn(&pdev->dev, | |
11922 | "Failed to destroy the HMC resources: %d\n", | |
11923 | ret_code); | |
11924 | } | |
41c445ff JB |
11925 | |
11926 | /* shutdown the adminq */ | |
ac9c5c6d | 11927 | i40e_shutdown_adminq(hw); |
41c445ff | 11928 | |
8ddb3326 JB |
11929 | /* destroy the locks only once, here */ |
11930 | mutex_destroy(&hw->aq.arq_mutex); | |
11931 | mutex_destroy(&hw->aq.asq_mutex); | |
11932 | ||
41c445ff JB |
11933 | /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */ |
11934 | i40e_clear_interrupt_scheme(pf); | |
505682cd | 11935 | for (i = 0; i < pf->num_alloc_vsi; i++) { |
41c445ff JB |
11936 | if (pf->vsi[i]) { |
11937 | i40e_vsi_clear_rings(pf->vsi[i]); | |
11938 | i40e_vsi_clear(pf->vsi[i]); | |
11939 | pf->vsi[i] = NULL; | |
11940 | } | |
11941 | } | |
11942 | ||
11943 | for (i = 0; i < I40E_MAX_VEB; i++) { | |
11944 | kfree(pf->veb[i]); | |
11945 | pf->veb[i] = NULL; | |
11946 | } | |
11947 | ||
11948 | kfree(pf->qp_pile); | |
41c445ff JB |
11949 | kfree(pf->vsi); |
11950 | ||
f734dfff | 11951 | iounmap(hw->hw_addr); |
41c445ff | 11952 | kfree(pf); |
56d766d6 | 11953 | pci_release_mem_regions(pdev); |
41c445ff JB |
11954 | |
11955 | pci_disable_pcie_error_reporting(pdev); | |
11956 | pci_disable_device(pdev); | |
11957 | } | |
11958 | ||
11959 | /** | |
11960 | * i40e_pci_error_detected - warning that something funky happened in PCI land | |
11961 | * @pdev: PCI device information struct | |
11962 | * | |
11963 | * Called to warn that something happened and the error handling steps | |
11964 | * are in progress. Allows the driver to quiesce things, be ready for | |
11965 | * remediation. | |
11966 | **/ | |
11967 | static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev, | |
11968 | enum pci_channel_state error) | |
11969 | { | |
11970 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
11971 | ||
11972 | dev_info(&pdev->dev, "%s: error %d\n", __func__, error); | |
11973 | ||
edfc23ee GP |
11974 | if (!pf) { |
11975 | dev_info(&pdev->dev, | |
11976 | "Cannot recover - error happened during device probe\n"); | |
11977 | return PCI_ERS_RESULT_DISCONNECT; | |
11978 | } | |
11979 | ||
41c445ff | 11980 | /* shutdown all operations */ |
dfc4ff64 JK |
11981 | if (!test_bit(__I40E_SUSPENDED, pf->state)) |
11982 | i40e_prep_for_reset(pf, false); | |
41c445ff JB |
11983 | |
11984 | /* Request a slot reset */ | |
11985 | return PCI_ERS_RESULT_NEED_RESET; | |
11986 | } | |
11987 | ||
11988 | /** | |
11989 | * i40e_pci_error_slot_reset - a PCI slot reset just happened | |
11990 | * @pdev: PCI device information struct | |
11991 | * | |
11992 | * Called to find if the driver can work with the device now that | |
11993 | * the pci slot has been reset. If a basic connection seems good | |
11994 | * (registers are readable and have sane content) then return a | |
11995 | * happy little PCI_ERS_RESULT_xxx. | |
11996 | **/ | |
11997 | static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev) | |
11998 | { | |
11999 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
12000 | pci_ers_result_t result; | |
12001 | int err; | |
12002 | u32 reg; | |
12003 | ||
fb43201f | 12004 | dev_dbg(&pdev->dev, "%s\n", __func__); |
41c445ff JB |
12005 | if (pci_enable_device_mem(pdev)) { |
12006 | dev_info(&pdev->dev, | |
12007 | "Cannot re-enable PCI device after reset.\n"); | |
12008 | result = PCI_ERS_RESULT_DISCONNECT; | |
12009 | } else { | |
12010 | pci_set_master(pdev); | |
12011 | pci_restore_state(pdev); | |
12012 | pci_save_state(pdev); | |
12013 | pci_wake_from_d3(pdev, false); | |
12014 | ||
12015 | reg = rd32(&pf->hw, I40E_GLGEN_RTRIG); | |
12016 | if (reg == 0) | |
12017 | result = PCI_ERS_RESULT_RECOVERED; | |
12018 | else | |
12019 | result = PCI_ERS_RESULT_DISCONNECT; | |
12020 | } | |
12021 | ||
12022 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
12023 | if (err) { | |
12024 | dev_info(&pdev->dev, | |
12025 | "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", | |
12026 | err); | |
12027 | /* non-fatal, continue */ | |
12028 | } | |
12029 | ||
12030 | return result; | |
12031 | } | |
12032 | ||
12033 | /** | |
12034 | * i40e_pci_error_resume - restart operations after PCI error recovery | |
12035 | * @pdev: PCI device information struct | |
12036 | * | |
12037 | * Called to allow the driver to bring things back up after PCI error | |
12038 | * and/or reset recovery has finished. | |
12039 | **/ | |
12040 | static void i40e_pci_error_resume(struct pci_dev *pdev) | |
12041 | { | |
12042 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
12043 | ||
fb43201f | 12044 | dev_dbg(&pdev->dev, "%s\n", __func__); |
0da36b97 | 12045 | if (test_bit(__I40E_SUSPENDED, pf->state)) |
9007bccd SN |
12046 | return; |
12047 | ||
dfc4ff64 | 12048 | i40e_handle_reset_warning(pf, false); |
9007bccd SN |
12049 | } |
12050 | ||
1d68005d JH |
12051 | /** |
12052 | * i40e_enable_mc_magic_wake - enable multicast magic packet wake up | |
12053 | * using the mac_address_write admin q function | |
12054 | * @pf: pointer to i40e_pf struct | |
12055 | **/ | |
12056 | static void i40e_enable_mc_magic_wake(struct i40e_pf *pf) | |
12057 | { | |
12058 | struct i40e_hw *hw = &pf->hw; | |
12059 | i40e_status ret; | |
12060 | u8 mac_addr[6]; | |
12061 | u16 flags = 0; | |
12062 | ||
12063 | /* Get current MAC address in case it's an LAA */ | |
12064 | if (pf->vsi[pf->lan_vsi] && pf->vsi[pf->lan_vsi]->netdev) { | |
12065 | ether_addr_copy(mac_addr, | |
12066 | pf->vsi[pf->lan_vsi]->netdev->dev_addr); | |
12067 | } else { | |
12068 | dev_err(&pf->pdev->dev, | |
12069 | "Failed to retrieve MAC address; using default\n"); | |
12070 | ether_addr_copy(mac_addr, hw->mac.addr); | |
12071 | } | |
12072 | ||
12073 | /* The FW expects the mac address write cmd to first be called with | |
12074 | * one of these flags before calling it again with the multicast | |
12075 | * enable flags. | |
12076 | */ | |
12077 | flags = I40E_AQC_WRITE_TYPE_LAA_WOL; | |
12078 | ||
12079 | if (hw->func_caps.flex10_enable && hw->partition_id != 1) | |
12080 | flags = I40E_AQC_WRITE_TYPE_LAA_ONLY; | |
12081 | ||
12082 | ret = i40e_aq_mac_address_write(hw, flags, mac_addr, NULL); | |
12083 | if (ret) { | |
12084 | dev_err(&pf->pdev->dev, | |
12085 | "Failed to update MAC address registers; cannot enable Multicast Magic packet wake up"); | |
12086 | return; | |
12087 | } | |
12088 | ||
12089 | flags = I40E_AQC_MC_MAG_EN | |
12090 | | I40E_AQC_WOL_PRESERVE_ON_PFR | |
12091 | | I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG; | |
12092 | ret = i40e_aq_mac_address_write(hw, flags, mac_addr, NULL); | |
12093 | if (ret) | |
12094 | dev_err(&pf->pdev->dev, | |
12095 | "Failed to enable Multicast Magic Packet wake up\n"); | |
12096 | } | |
12097 | ||
9007bccd SN |
12098 | /** |
12099 | * i40e_shutdown - PCI callback for shutting down | |
12100 | * @pdev: PCI device information struct | |
12101 | **/ | |
12102 | static void i40e_shutdown(struct pci_dev *pdev) | |
12103 | { | |
12104 | struct i40e_pf *pf = pci_get_drvdata(pdev); | |
8e2773ae | 12105 | struct i40e_hw *hw = &pf->hw; |
9007bccd | 12106 | |
0da36b97 | 12107 | set_bit(__I40E_SUSPENDED, pf->state); |
9e6c9c0f | 12108 | set_bit(__I40E_DOWN, pf->state); |
9007bccd | 12109 | rtnl_lock(); |
373149fc | 12110 | i40e_prep_for_reset(pf, true); |
9007bccd SN |
12111 | rtnl_unlock(); |
12112 | ||
8e2773ae SN |
12113 | wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); |
12114 | wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
12115 | ||
02b42498 CS |
12116 | del_timer_sync(&pf->service_timer); |
12117 | cancel_work_sync(&pf->service_task); | |
12118 | i40e_fdir_teardown(pf); | |
12119 | ||
921c467c MW |
12120 | /* Client close must be called explicitly here because the timer |
12121 | * has been stopped. | |
12122 | */ | |
12123 | i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false); | |
12124 | ||
d36e41dc | 12125 | if (pf->wol_en && (pf->hw_features & I40E_HW_WOL_MC_MAGIC_PKT_WAKE)) |
1d68005d JH |
12126 | i40e_enable_mc_magic_wake(pf); |
12127 | ||
dfc4ff64 | 12128 | i40e_prep_for_reset(pf, false); |
02b42498 CS |
12129 | |
12130 | wr32(hw, I40E_PFPM_APM, | |
12131 | (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); | |
12132 | wr32(hw, I40E_PFPM_WUFC, | |
12133 | (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
12134 | ||
e147758d SN |
12135 | i40e_clear_interrupt_scheme(pf); |
12136 | ||
9007bccd | 12137 | if (system_state == SYSTEM_POWER_OFF) { |
8e2773ae | 12138 | pci_wake_from_d3(pdev, pf->wol_en); |
9007bccd SN |
12139 | pci_set_power_state(pdev, PCI_D3hot); |
12140 | } | |
12141 | } | |
12142 | ||
12143 | #ifdef CONFIG_PM | |
12144 | /** | |
0e5d3da4 JK |
12145 | * i40e_suspend - PM callback for moving to D3 |
12146 | * @dev: generic device information structure | |
9007bccd | 12147 | **/ |
0e5d3da4 | 12148 | static int i40e_suspend(struct device *dev) |
9007bccd | 12149 | { |
0e5d3da4 | 12150 | struct pci_dev *pdev = to_pci_dev(dev); |
9007bccd | 12151 | struct i40e_pf *pf = pci_get_drvdata(pdev); |
8e2773ae | 12152 | struct i40e_hw *hw = &pf->hw; |
9007bccd | 12153 | |
401586c2 JK |
12154 | /* If we're already suspended, then there is nothing to do */ |
12155 | if (test_and_set_bit(__I40E_SUSPENDED, pf->state)) | |
12156 | return 0; | |
12157 | ||
9e6c9c0f | 12158 | set_bit(__I40E_DOWN, pf->state); |
3932dbfe | 12159 | |
5c499228 JK |
12160 | /* Ensure service task will not be running */ |
12161 | del_timer_sync(&pf->service_timer); | |
12162 | cancel_work_sync(&pf->service_task); | |
12163 | ||
d36e41dc | 12164 | if (pf->wol_en && (pf->hw_features & I40E_HW_WOL_MC_MAGIC_PKT_WAKE)) |
1d68005d JH |
12165 | i40e_enable_mc_magic_wake(pf); |
12166 | ||
dfc4ff64 | 12167 | i40e_prep_for_reset(pf, false); |
9007bccd | 12168 | |
8e2773ae SN |
12169 | wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0)); |
12170 | wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0)); | |
12171 | ||
b980c063 JK |
12172 | /* Clear the interrupt scheme and release our IRQs so that the system |
12173 | * can safely hibernate even when there are a large number of CPUs. | |
12174 | * Otherwise hibernation might fail when mapping all the vectors back | |
12175 | * to CPU0. | |
12176 | */ | |
12177 | i40e_clear_interrupt_scheme(pf); | |
c17401a1 | 12178 | |
0e5d3da4 | 12179 | return 0; |
41c445ff JB |
12180 | } |
12181 | ||
9007bccd | 12182 | /** |
0e5d3da4 JK |
12183 | * i40e_resume - PM callback for waking up from D3 |
12184 | * @dev: generic device information structure | |
9007bccd | 12185 | **/ |
0e5d3da4 | 12186 | static int i40e_resume(struct device *dev) |
9007bccd | 12187 | { |
0e5d3da4 | 12188 | struct pci_dev *pdev = to_pci_dev(dev); |
9007bccd | 12189 | struct i40e_pf *pf = pci_get_drvdata(pdev); |
b980c063 | 12190 | int err; |
9007bccd | 12191 | |
401586c2 JK |
12192 | /* If we're not suspended, then there is nothing to do */ |
12193 | if (!test_bit(__I40E_SUSPENDED, pf->state)) | |
12194 | return 0; | |
12195 | ||
b980c063 JK |
12196 | /* We cleared the interrupt scheme when we suspended, so we need to |
12197 | * restore it now to resume device functionality. | |
12198 | */ | |
12199 | err = i40e_restore_interrupt_scheme(pf); | |
12200 | if (err) { | |
12201 | dev_err(&pdev->dev, "Cannot restore interrupt scheme: %d\n", | |
12202 | err); | |
12203 | } | |
12204 | ||
401586c2 JK |
12205 | clear_bit(__I40E_DOWN, pf->state); |
12206 | i40e_reset_and_rebuild(pf, false, false); | |
12207 | ||
12208 | /* Clear suspended state last after everything is recovered */ | |
12209 | clear_bit(__I40E_SUSPENDED, pf->state); | |
9007bccd | 12210 | |
5c499228 JK |
12211 | /* Restart the service task */ |
12212 | mod_timer(&pf->service_timer, | |
12213 | round_jiffies(jiffies + pf->service_timer_period)); | |
12214 | ||
9007bccd SN |
12215 | return 0; |
12216 | } | |
12217 | ||
0e5d3da4 JK |
12218 | #endif /* CONFIG_PM */ |
12219 | ||
41c445ff JB |
12220 | static const struct pci_error_handlers i40e_err_handler = { |
12221 | .error_detected = i40e_pci_error_detected, | |
12222 | .slot_reset = i40e_pci_error_slot_reset, | |
12223 | .resume = i40e_pci_error_resume, | |
12224 | }; | |
12225 | ||
0e5d3da4 JK |
12226 | static SIMPLE_DEV_PM_OPS(i40e_pm_ops, i40e_suspend, i40e_resume); |
12227 | ||
41c445ff JB |
12228 | static struct pci_driver i40e_driver = { |
12229 | .name = i40e_driver_name, | |
12230 | .id_table = i40e_pci_tbl, | |
12231 | .probe = i40e_probe, | |
12232 | .remove = i40e_remove, | |
9007bccd | 12233 | #ifdef CONFIG_PM |
0e5d3da4 JK |
12234 | .driver = { |
12235 | .pm = &i40e_pm_ops, | |
12236 | }, | |
12237 | #endif /* CONFIG_PM */ | |
9007bccd | 12238 | .shutdown = i40e_shutdown, |
41c445ff JB |
12239 | .err_handler = &i40e_err_handler, |
12240 | .sriov_configure = i40e_pci_sriov_configure, | |
12241 | }; | |
12242 | ||
12243 | /** | |
12244 | * i40e_init_module - Driver registration routine | |
12245 | * | |
12246 | * i40e_init_module is the first routine called when the driver is | |
12247 | * loaded. All it does is register with the PCI subsystem. | |
12248 | **/ | |
12249 | static int __init i40e_init_module(void) | |
12250 | { | |
12251 | pr_info("%s: %s - version %s\n", i40e_driver_name, | |
12252 | i40e_driver_string, i40e_driver_version_str); | |
12253 | pr_info("%s: %s\n", i40e_driver_name, i40e_copyright); | |
96664483 | 12254 | |
4d5957cb JK |
12255 | /* There is no need to throttle the number of active tasks because |
12256 | * each device limits its own task using a state bit for scheduling | |
12257 | * the service task, and the device tasks do not interfere with each | |
12258 | * other, so we don't set a max task limit. We must set WQ_MEM_RECLAIM | |
12259 | * since we need to be able to guarantee forward progress even under | |
12260 | * memory pressure. | |
2803b16c | 12261 | */ |
4d5957cb | 12262 | i40e_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, i40e_driver_name); |
2803b16c JB |
12263 | if (!i40e_wq) { |
12264 | pr_err("%s: Failed to create workqueue\n", i40e_driver_name); | |
12265 | return -ENOMEM; | |
12266 | } | |
12267 | ||
41c445ff JB |
12268 | i40e_dbg_init(); |
12269 | return pci_register_driver(&i40e_driver); | |
12270 | } | |
12271 | module_init(i40e_init_module); | |
12272 | ||
12273 | /** | |
12274 | * i40e_exit_module - Driver exit cleanup routine | |
12275 | * | |
12276 | * i40e_exit_module is called just before the driver is removed | |
12277 | * from memory. | |
12278 | **/ | |
12279 | static void __exit i40e_exit_module(void) | |
12280 | { | |
12281 | pci_unregister_driver(&i40e_driver); | |
2803b16c | 12282 | destroy_workqueue(i40e_wq); |
41c445ff JB |
12283 | i40e_dbg_exit(); |
12284 | } | |
12285 | module_exit(i40e_exit_module); |