projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch '40GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next...
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
2818ccd9 4 * Copyright(c) 2013 - 2016 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
b499ffb0
SV		 27#include <linux/etherdevice.h>
28#include <linux/of_net.h>
29#include <linux/pci.h>
30
41c445ff
JB		 31/* Local includes */
32#include "i40e.h"
4eb3f768 33#include "i40e_diag.h"
06a5f7f1 34#include <net/udp_tunnel.h>
41c445ff
JB		 35
36const char i40e_driver_name[] = "i40e";
37static const char i40e_driver_string[] =
38 "Intel(R) Ethernet Connection XL710 Network Driver";
39
40#define DRV_KERN "-k"
41
e8e724db 42#define DRV_VERSION_MAJOR 1
07061958
BP		 43#define DRV_VERSION_MINOR 6
44#define DRV_VERSION_BUILD 4
41c445ff
JB		 45#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
46 __stringify(DRV_VERSION_MINOR) "." \
47 __stringify(DRV_VERSION_BUILD) DRV_KERN
48const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 49static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 50
51/* a bit of forward declarations */
52static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
53static void i40e_handle_reset_warning(struct i40e_pf *pf);
54static int i40e_add_vsi(struct i40e_vsi *vsi);
55static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 56static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 57static int i40e_setup_misc_vector(struct i40e_pf *pf);
58static void i40e_determine_queue_usage(struct i40e_pf *pf);
59static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 60static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
61 u16 rss_table_size, u16 rss_size);
cbf61325 62static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 63static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 64
65/* i40e_pci_tbl - PCI Device ID Table
66 *
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
9baa3c34 72static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e 74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
ab60085e
SN		 75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
35dae51d
ASJ		 83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0},
87e6c1d7
ASJ		 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
d6bf58c2 88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0},
a3aa5036 89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_I_X722), 0},
48a3b512
SN		 90 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
91 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 92 /* required last entry */
93 {0, }
94};
95MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
96
97#define I40E_MAX_VF_COUNT 128
98static int debug = -1;
99module_param(debug, int, 0);
100MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
101
102MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
103MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
104MODULE_LICENSE("GPL");
105MODULE_VERSION(DRV_VERSION);
106
2803b16c
JB		 107static struct workqueue_struct *i40e_wq;
108
41c445ff
JB		 109/**
110 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
111 * @hw: pointer to the HW structure
112 * @mem: ptr to mem struct to fill out
113 * @size: size of memory requested
114 * @alignment: what to align the allocation to
115 **/
116int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
117 u64 size, u32 alignment)
118{
119 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
120
121 mem->size = ALIGN(size, alignment);
122 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
123 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 124 if (!mem->va)
125 return -ENOMEM;
41c445ff 126
93bc73b8 127 return 0;
41c445ff
JB		 128}
129
130/**
131 * i40e_free_dma_mem_d - OS specific memory free for shared code
132 * @hw: pointer to the HW structure
133 * @mem: ptr to mem struct to free
134 **/
135int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
136{
137 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
138
139 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
140 mem->va = NULL;
141 mem->pa = 0;
142 mem->size = 0;
143
144 return 0;
145}
146
147/**
148 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
149 * @hw: pointer to the HW structure
150 * @mem: ptr to mem struct to fill out
151 * @size: size of memory requested
152 **/
153int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
154 u32 size)
155{
156 mem->size = size;
157 mem->va = kzalloc(size, GFP_KERNEL);
158
93bc73b8
JB		 159 if (!mem->va)
160 return -ENOMEM;
41c445ff 161
93bc73b8 162 return 0;
41c445ff
JB		 163}
164
165/**
166 * i40e_free_virt_mem_d - OS specific memory free for shared code
167 * @hw: pointer to the HW structure
168 * @mem: ptr to mem struct to free
169 **/
170int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
171{
172 /* it's ok to kfree a NULL pointer */
173 kfree(mem->va);
174 mem->va = NULL;
175 mem->size = 0;
176
177 return 0;
178}
179
180/**
181 * i40e_get_lump - find a lump of free generic resource
182 * @pf: board private structure
183 * @pile: the pile of resource to search
184 * @needed: the number of items needed
185 * @id: an owner id to stick on the items assigned
186 *
187 * Returns the base item index of the lump, or negative for error
188 *
189 * The search_hint trick and lack of advanced fit-finding only work
190 * because we're highly likely to have all the same size lump requests.
191 * Linear search time and any fragmentation should be minimal.
192 **/
193static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
194 u16 needed, u16 id)
195{
196 int ret = -ENOMEM;
ddf434ac 197 int i, j;
41c445ff
JB		 198
199 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
200 dev_info(&pf->pdev->dev,
201 "param err: pile=%p needed=%d id=0x%04x\n",
202 pile, needed, id);
203 return -EINVAL;
204 }
205
206 /* start the linear search with an imperfect hint */
207 i = pile->search_hint;
ddf434ac 208 while (i < pile->num_entries) {
41c445ff
JB		 209 /* skip already allocated entries */
210 if (pile->list[i] & I40E_PILE_VALID_BIT) {
211 i++;
212 continue;
213 }
214
215 /* do we have enough in this lump? */
216 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
217 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
218 break;
219 }
220
221 if (j == needed) {
222 /* there was enough, so assign it to the requestor */
223 for (j = 0; j < needed; j++)
224 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
225 ret = i;
226 pile->search_hint = i + j;
ddf434ac 227 break;
41c445ff 228 }
6995b36c
JB		 229
230 /* not enough, so skip over it and continue looking */
231 i += j;
41c445ff
JB		 232 }
233
234 return ret;
235}
236
237/**
238 * i40e_put_lump - return a lump of generic resource
239 * @pile: the pile of resource to search
240 * @index: the base item index
241 * @id: the owner id of the items assigned
242 *
243 * Returns the count of items in the lump
244 **/
245static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
246{
247 int valid_id = (id | I40E_PILE_VALID_BIT);
248 int count = 0;
249 int i;
250
251 if (!pile || index >= pile->num_entries)
252 return -EINVAL;
253
254 for (i = index;
255 i < pile->num_entries && pile->list[i] == valid_id;
256 i++) {
257 pile->list[i] = 0;
258 count++;
259 }
260
261 if (count && index < pile->search_hint)
262 pile->search_hint = index;
263
264 return count;
265}
266
fdf0e0bf
ASJ		 267/**
268 * i40e_find_vsi_from_id - searches for the vsi with the given id
269 * @pf - the pf structure to search for the vsi
270 * @id - id of the vsi it is searching for
271 **/
272struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
273{
274 int i;
275
276 for (i = 0; i < pf->num_alloc_vsi; i++)
277 if (pf->vsi[i] && (pf->vsi[i]->id == id))
278 return pf->vsi[i];
279
280 return NULL;
281}
282
41c445ff
JB		 283/**
284 * i40e_service_event_schedule - Schedule the service task to wake up
285 * @pf: board private structure
286 *
287 * If not already scheduled, this puts the task into the work queue
288 **/
e3219ce6 289void i40e_service_event_schedule(struct i40e_pf *pf)
41c445ff
JB		 290{
291 if (!test_bit(__I40E_DOWN, &pf->state) &&
292 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
293 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
2803b16c 294 queue_work(i40e_wq, &pf->service_task);
41c445ff
JB		 295}
296
297/**
298 * i40e_tx_timeout - Respond to a Tx Hang
299 * @netdev: network interface device structure
300 *
301 * If any port has noticed a Tx timeout, it is likely that the whole
302 * device is munged, not just the one netdev port, so go for the full
303 * reset.
304 **/
38e00438
VD		 305#ifdef I40E_FCOE
306void i40e_tx_timeout(struct net_device *netdev)
307#else
41c445ff 308static void i40e_tx_timeout(struct net_device *netdev)
38e00438 309#endif
41c445ff
JB		 310{
311 struct i40e_netdev_priv *np = netdev_priv(netdev);
312 struct i40e_vsi *vsi = np->vsi;
313 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 314 struct i40e_ring *tx_ring = NULL;
315 unsigned int i, hung_queue = 0;
316 u32 head, val;
41c445ff
JB		 317
318 pf->tx_timeout_count++;
319
b03a8c1f
KP		 320 /* find the stopped queue the same way the stack does */
321 for (i = 0; i < netdev->num_tx_queues; i++) {
322 struct netdev_queue *q;
323 unsigned long trans_start;
324
325 q = netdev_get_tx_queue(netdev, i);
9b36627a 326 trans_start = q->trans_start;
b03a8c1f
KP		 327 if (netif_xmit_stopped(q) &&
328 time_after(jiffies,
329 (trans_start + netdev->watchdog_timeo))) {
330 hung_queue = i;
331 break;
332 }
333 }
334
335 if (i == netdev->num_tx_queues) {
336 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
337 } else {
338 /* now that we have an index, find the tx_ring struct */
339 for (i = 0; i < vsi->num_queue_pairs; i++) {
340 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
341 if (hung_queue ==
342 vsi->tx_rings[i]->queue_index) {
343 tx_ring = vsi->tx_rings[i];
344 break;
345 }
346 }
347 }
348 }
349
41c445ff 350 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 351 pf->tx_timeout_recovery_level = 1; /* reset after some time */
352 else if (time_before(jiffies,
353 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
354 return; /* don't do any new action before the next timeout */
355
356 if (tx_ring) {
357 head = i40e_get_head(tx_ring);
358 /* Read interrupt register */
359 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
360 val = rd32(&pf->hw,
361 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
362 tx_ring->vsi->base_vector - 1));
363 else
364 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
365
366 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
367 vsi->seid, hung_queue, tx_ring->next_to_clean,
368 head, tx_ring->next_to_use,
369 readl(tx_ring->tail), val);
370 }
371
41c445ff 372 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 373 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
374 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 375
376 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 377 case 1:
378 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
379 break;
380 case 2:
381 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
382 break;
383 case 3:
384 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
385 break;
386 default:
387 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 388 break;
389 }
b03a8c1f 390
41c445ff
JB		 391 i40e_service_event_schedule(pf);
392 pf->tx_timeout_recovery_level++;
393}
394
41c445ff
JB		 395/**
396 * i40e_get_vsi_stats_struct - Get System Network Statistics
397 * @vsi: the VSI we care about
398 *
399 * Returns the address of the device statistics structure.
400 * The statistics are actually updated from the service task.
401 **/
402struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
403{
404 return &vsi->net_stats;
405}
406
407/**
408 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
409 * @netdev: network interface device structure
410 *
411 * Returns the address of the device statistics structure.
412 * The statistics are actually updated from the service task.
413 **/
38e00438
VD		 414#ifdef I40E_FCOE
415struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
416 struct net_device *netdev,
417 struct rtnl_link_stats64 *stats)
418#else
41c445ff
JB		 419static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
420 struct net_device *netdev,
980e9b11 421 struct rtnl_link_stats64 *stats)
38e00438 422#endif
41c445ff
JB		 423{
424 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 425 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 426 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 427 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
428 int i;
429
bc7d338f
ASJ		 430 if (test_bit(__I40E_DOWN, &vsi->state))
431 return stats;
432
3c325ced
JB		 433 if (!vsi->tx_rings)
434 return stats;
435
980e9b11
AD		 436 rcu_read_lock();
437 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 438 u64 bytes, packets;
439 unsigned int start;
440
441 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
442 if (!tx_ring)
443 continue;
444
445 do {
57a7744e 446 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 447 packets = tx_ring->stats.packets;
448 bytes = tx_ring->stats.bytes;
57a7744e 449 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 450
451 stats->tx_packets += packets;
452 stats->tx_bytes += bytes;
453 rx_ring = &tx_ring[1];
454
455 do {
57a7744e 456 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 457 packets = rx_ring->stats.packets;
458 bytes = rx_ring->stats.bytes;
57a7744e 459 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 460
980e9b11
AD		 461 stats->rx_packets += packets;
462 stats->rx_bytes += bytes;
463 }
464 rcu_read_unlock();
465
a5282f44 466 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 467 stats->multicast = vsi_stats->multicast;
468 stats->tx_errors = vsi_stats->tx_errors;
469 stats->tx_dropped = vsi_stats->tx_dropped;
470 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 471 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 472 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
473 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 474
980e9b11 475 return stats;
41c445ff
JB		 476}
477
478/**
479 * i40e_vsi_reset_stats - Resets all stats of the given vsi
480 * @vsi: the VSI to have its stats reset
481 **/
482void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
483{
484 struct rtnl_link_stats64 *ns;
485 int i;
486
487 if (!vsi)
488 return;
489
490 ns = i40e_get_vsi_stats_struct(vsi);
491 memset(ns, 0, sizeof(*ns));
492 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
493 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
494 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 495 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 496 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 497 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 498 sizeof(vsi->rx_rings[i]->stats));
6995b36c 499 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 500 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 501 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 502 sizeof(vsi->tx_rings[i]->stats));
503 memset(&vsi->tx_rings[i]->tx_stats, 0,
504 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 505 }
8e9dca53 506 }
41c445ff
JB		 507 vsi->stat_offsets_loaded = false;
508}
509
510/**
b40c82e6 511 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 512 * @pf: the PF to be reset
513 **/
514void i40e_pf_reset_stats(struct i40e_pf *pf)
515{
e91fdf76
SN		 516 int i;
517
41c445ff
JB		 518 memset(&pf->stats, 0, sizeof(pf->stats));
519 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
520 pf->stat_offsets_loaded = false;
e91fdf76
SN		 521
522 for (i = 0; i < I40E_MAX_VEB; i++) {
523 if (pf->veb[i]) {
524 memset(&pf->veb[i]->stats, 0,
525 sizeof(pf->veb[i]->stats));
526 memset(&pf->veb[i]->stats_offsets, 0,
527 sizeof(pf->veb[i]->stats_offsets));
528 pf->veb[i]->stat_offsets_loaded = false;
529 }
530 }
41c445ff
JB		 531}
532
533/**
534 * i40e_stat_update48 - read and update a 48 bit stat from the chip
535 * @hw: ptr to the hardware info
536 * @hireg: the high 32 bit reg to read
537 * @loreg: the low 32 bit reg to read
538 * @offset_loaded: has the initial offset been loaded yet
539 * @offset: ptr to current offset value
540 * @stat: ptr to the stat
541 *
542 * Since the device stats are not reset at PFReset, they likely will not
543 * be zeroed when the driver starts. We'll save the first values read
544 * and use them as offsets to be subtracted from the raw values in order
545 * to report stats that count from zero. In the process, we also manage
546 * the potential roll-over.
547 **/
548static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
549 bool offset_loaded, u64 *offset, u64 *stat)
550{
551 u64 new_data;
552
ab60085e 553 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 554 new_data = rd32(hw, loreg);
555 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
556 } else {
557 new_data = rd64(hw, loreg);
558 }
559 if (!offset_loaded)
560 *offset = new_data;
561 if (likely(new_data >= *offset))
562 *stat = new_data - *offset;
563 else
41a1d04b 564 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 565 *stat &= 0xFFFFFFFFFFFFULL;
566}
567
568/**
569 * i40e_stat_update32 - read and update a 32 bit stat from the chip
570 * @hw: ptr to the hardware info
571 * @reg: the hw reg to read
572 * @offset_loaded: has the initial offset been loaded yet
573 * @offset: ptr to current offset value
574 * @stat: ptr to the stat
575 **/
576static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
577 bool offset_loaded, u64 *offset, u64 *stat)
578{
579 u32 new_data;
580
581 new_data = rd32(hw, reg);
582 if (!offset_loaded)
583 *offset = new_data;
584 if (likely(new_data >= *offset))
585 *stat = (u32)(new_data - *offset);
586 else
41a1d04b 587 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 588}
589
590/**
591 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
592 * @vsi: the VSI to be updated
593 **/
594void i40e_update_eth_stats(struct i40e_vsi *vsi)
595{
596 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
597 struct i40e_pf *pf = vsi->back;
598 struct i40e_hw *hw = &pf->hw;
599 struct i40e_eth_stats *oes;
600 struct i40e_eth_stats *es; /* device's eth stats */
601
602 es = &vsi->eth_stats;
603 oes = &vsi->eth_stats_offsets;
604
605 /* Gather up the stats that the hw collects */
606 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
607 vsi->stat_offsets_loaded,
608 &oes->tx_errors, &es->tx_errors);
609 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
610 vsi->stat_offsets_loaded,
611 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 612 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
613 vsi->stat_offsets_loaded,
614 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
615 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
616 vsi->stat_offsets_loaded,
617 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 618
619 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
620 I40E_GLV_GORCL(stat_idx),
621 vsi->stat_offsets_loaded,
622 &oes->rx_bytes, &es->rx_bytes);
623 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
624 I40E_GLV_UPRCL(stat_idx),
625 vsi->stat_offsets_loaded,
626 &oes->rx_unicast, &es->rx_unicast);
627 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
628 I40E_GLV_MPRCL(stat_idx),
629 vsi->stat_offsets_loaded,
630 &oes->rx_multicast, &es->rx_multicast);
631 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
632 I40E_GLV_BPRCL(stat_idx),
633 vsi->stat_offsets_loaded,
634 &oes->rx_broadcast, &es->rx_broadcast);
635
636 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
637 I40E_GLV_GOTCL(stat_idx),
638 vsi->stat_offsets_loaded,
639 &oes->tx_bytes, &es->tx_bytes);
640 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
641 I40E_GLV_UPTCL(stat_idx),
642 vsi->stat_offsets_loaded,
643 &oes->tx_unicast, &es->tx_unicast);
644 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
645 I40E_GLV_MPTCL(stat_idx),
646 vsi->stat_offsets_loaded,
647 &oes->tx_multicast, &es->tx_multicast);
648 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
649 I40E_GLV_BPTCL(stat_idx),
650 vsi->stat_offsets_loaded,
651 &oes->tx_broadcast, &es->tx_broadcast);
652 vsi->stat_offsets_loaded = true;
653}
654
655/**
656 * i40e_update_veb_stats - Update Switch component statistics
657 * @veb: the VEB being updated
658 **/
659static void i40e_update_veb_stats(struct i40e_veb *veb)
660{
661 struct i40e_pf *pf = veb->pf;
662 struct i40e_hw *hw = &pf->hw;
663 struct i40e_eth_stats *oes;
664 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 665 struct i40e_veb_tc_stats *veb_oes;
666 struct i40e_veb_tc_stats *veb_es;
667 int i, idx = 0;
41c445ff
JB		 668
669 idx = veb->stats_idx;
670 es = &veb->stats;
671 oes = &veb->stats_offsets;
fe860afb
NP		 672 veb_es = &veb->tc_stats;
673 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 674
675 /* Gather up the stats that the hw collects */
676 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
677 veb->stat_offsets_loaded,
678 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 679 if (hw->revision_id > 0)
680 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
681 veb->stat_offsets_loaded,
682 &oes->rx_unknown_protocol,
683 &es->rx_unknown_protocol);
41c445ff
JB		 684 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
685 veb->stat_offsets_loaded,
686 &oes->rx_bytes, &es->rx_bytes);
687 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
688 veb->stat_offsets_loaded,
689 &oes->rx_unicast, &es->rx_unicast);
690 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
691 veb->stat_offsets_loaded,
692 &oes->rx_multicast, &es->rx_multicast);
693 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
694 veb->stat_offsets_loaded,
695 &oes->rx_broadcast, &es->rx_broadcast);
696
697 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
698 veb->stat_offsets_loaded,
699 &oes->tx_bytes, &es->tx_bytes);
700 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
701 veb->stat_offsets_loaded,
702 &oes->tx_unicast, &es->tx_unicast);
703 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
704 veb->stat_offsets_loaded,
705 &oes->tx_multicast, &es->tx_multicast);
706 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
707 veb->stat_offsets_loaded,
708 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 709 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
710 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
711 I40E_GLVEBTC_RPCL(i, idx),
712 veb->stat_offsets_loaded,
713 &veb_oes->tc_rx_packets[i],
714 &veb_es->tc_rx_packets[i]);
715 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
716 I40E_GLVEBTC_RBCL(i, idx),
717 veb->stat_offsets_loaded,
718 &veb_oes->tc_rx_bytes[i],
719 &veb_es->tc_rx_bytes[i]);
720 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
721 I40E_GLVEBTC_TPCL(i, idx),
722 veb->stat_offsets_loaded,
723 &veb_oes->tc_tx_packets[i],
724 &veb_es->tc_tx_packets[i]);
725 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
726 I40E_GLVEBTC_TBCL(i, idx),
727 veb->stat_offsets_loaded,
728 &veb_oes->tc_tx_bytes[i],
729 &veb_es->tc_tx_bytes[i]);
730 }
41c445ff
JB		 731 veb->stat_offsets_loaded = true;
732}
733
38e00438
VD		 734#ifdef I40E_FCOE
735/**
736 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
737 * @vsi: the VSI that is capable of doing FCoE
738 **/
739static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
740{
741 struct i40e_pf *pf = vsi->back;
742 struct i40e_hw *hw = &pf->hw;
743 struct i40e_fcoe_stats *ofs;
744 struct i40e_fcoe_stats *fs; /* device's eth stats */
745 int idx;
746
747 if (vsi->type != I40E_VSI_FCOE)
748 return;
749
4147e2c5 750 idx = hw->pf_id + I40E_FCOE_PF_STAT_OFFSET;
38e00438
VD		 751 fs = &vsi->fcoe_stats;
752 ofs = &vsi->fcoe_stats_offsets;
753
754 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
755 vsi->fcoe_stat_offsets_loaded,
756 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
757 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
758 vsi->fcoe_stat_offsets_loaded,
759 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
760 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
761 vsi->fcoe_stat_offsets_loaded,
762 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
763 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
764 vsi->fcoe_stat_offsets_loaded,
765 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
766 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
767 vsi->fcoe_stat_offsets_loaded,
768 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
769 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
770 vsi->fcoe_stat_offsets_loaded,
771 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
772 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
773 vsi->fcoe_stat_offsets_loaded,
774 &ofs->fcoe_last_error, &fs->fcoe_last_error);
775 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
776 vsi->fcoe_stat_offsets_loaded,
777 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
778
779 vsi->fcoe_stat_offsets_loaded = true;
780}
781
782#endif
41c445ff 783/**
7812fddc 784 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 785 * @vsi: the VSI to be updated
786 *
787 * There are a few instances where we store the same stat in a
788 * couple of different structs. This is partly because we have
789 * the netdev stats that need to be filled out, which is slightly
790 * different from the "eth_stats" defined by the chip and used in
7812fddc 791 * VF communications. We sort it out here.
41c445ff 792 **/
7812fddc 793static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 794{
795 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 796 struct rtnl_link_stats64 *ons;
797 struct rtnl_link_stats64 *ns; /* netdev stats */
798 struct i40e_eth_stats *oes;
799 struct i40e_eth_stats *es; /* device's eth stats */
800 u32 tx_restart, tx_busy;
dd353109 801 u64 tx_lost_interrupt;
bf00b376 802 struct i40e_ring *p;
41c445ff 803 u32 rx_page, rx_buf;
bf00b376
AA		 804 u64 bytes, packets;
805 unsigned int start;
2fc3d715 806 u64 tx_linearize;
164c9f54 807 u64 tx_force_wb;
41c445ff
JB		 808 u64 rx_p, rx_b;
809 u64 tx_p, tx_b;
41c445ff
JB		 810 u16 q;
811
812 if (test_bit(__I40E_DOWN, &vsi->state) ||
813 test_bit(__I40E_CONFIG_BUSY, &pf->state))
814 return;
815
816 ns = i40e_get_vsi_stats_struct(vsi);
817 ons = &vsi->net_stats_offsets;
818 es = &vsi->eth_stats;
819 oes = &vsi->eth_stats_offsets;
820
821 /* Gather up the netdev and vsi stats that the driver collects
822 * on the fly during packet processing
823 */
824 rx_b = rx_p = 0;
825 tx_b = tx_p = 0;
164c9f54 826 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
dd353109 827 tx_lost_interrupt = 0;
41c445ff
JB		 828 rx_page = 0;
829 rx_buf = 0;
980e9b11 830 rcu_read_lock();
41c445ff 831 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 832 /* locate Tx ring */
833 p = ACCESS_ONCE(vsi->tx_rings[q]);
834
835 do {
57a7744e 836 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 837 packets = p->stats.packets;
838 bytes = p->stats.bytes;
57a7744e 839 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 840 tx_b += bytes;
841 tx_p += packets;
842 tx_restart += p->tx_stats.restart_queue;
843 tx_busy += p->tx_stats.tx_busy;
2fc3d715 844 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 845 tx_force_wb += p->tx_stats.tx_force_wb;
dd353109 846 tx_lost_interrupt += p->tx_stats.tx_lost_interrupt;
41c445ff 847
980e9b11
AD		 848 /* Rx queue is part of the same block as Tx queue */
849 p = &p[1];
850 do {
57a7744e 851 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 852 packets = p->stats.packets;
853 bytes = p->stats.bytes;
57a7744e 854 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 855 rx_b += bytes;
856 rx_p += packets;
420136cc
MW		 857 rx_buf += p->rx_stats.alloc_buff_failed;
858 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 859 }
980e9b11 860 rcu_read_unlock();
41c445ff
JB		 861 vsi->tx_restart = tx_restart;
862 vsi->tx_busy = tx_busy;
2fc3d715 863 vsi->tx_linearize = tx_linearize;
164c9f54 864 vsi->tx_force_wb = tx_force_wb;
dd353109 865 vsi->tx_lost_interrupt = tx_lost_interrupt;
41c445ff
JB		 866 vsi->rx_page_failed = rx_page;
867 vsi->rx_buf_failed = rx_buf;
868
869 ns->rx_packets = rx_p;
870 ns->rx_bytes = rx_b;
871 ns->tx_packets = tx_p;
872 ns->tx_bytes = tx_b;
873
41c445ff 874 /* update netdev stats from eth stats */
7812fddc 875 i40e_update_eth_stats(vsi);
41c445ff
JB		 876 ons->tx_errors = oes->tx_errors;
877 ns->tx_errors = es->tx_errors;
878 ons->multicast = oes->rx_multicast;
879 ns->multicast = es->rx_multicast;
41a9e55c
SN		 880 ons->rx_dropped = oes->rx_discards;
881 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 882 ons->tx_dropped = oes->tx_discards;
883 ns->tx_dropped = es->tx_discards;
884
7812fddc 885 /* pull in a couple PF stats if this is the main vsi */
41c445ff 886 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 887 ns->rx_crc_errors = pf->stats.crc_errors;
888 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
889 ns->rx_length_errors = pf->stats.rx_length_errors;
890 }
891}
41c445ff 892
7812fddc 893/**
b40c82e6 894 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 895 * @pf: the PF to be updated
896 **/
897static void i40e_update_pf_stats(struct i40e_pf *pf)
898{
899 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
900 struct i40e_hw_port_stats *nsd = &pf->stats;
901 struct i40e_hw *hw = &pf->hw;
902 u32 val;
903 int i;
41c445ff 904
7812fddc
SN		 905 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
906 I40E_GLPRT_GORCL(hw->port),
907 pf->stat_offsets_loaded,
908 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
909 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
910 I40E_GLPRT_GOTCL(hw->port),
911 pf->stat_offsets_loaded,
912 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
913 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
914 pf->stat_offsets_loaded,
915 &osd->eth.rx_discards,
916 &nsd->eth.rx_discards);
532d283d
SN		 917 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
918 I40E_GLPRT_UPRCL(hw->port),
919 pf->stat_offsets_loaded,
920 &osd->eth.rx_unicast,
921 &nsd->eth.rx_unicast);
7812fddc
SN		 922 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
923 I40E_GLPRT_MPRCL(hw->port),
924 pf->stat_offsets_loaded,
925 &osd->eth.rx_multicast,
926 &nsd->eth.rx_multicast);
532d283d
SN		 927 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
928 I40E_GLPRT_BPRCL(hw->port),
929 pf->stat_offsets_loaded,
930 &osd->eth.rx_broadcast,
931 &nsd->eth.rx_broadcast);
932 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
933 I40E_GLPRT_UPTCL(hw->port),
934 pf->stat_offsets_loaded,
935 &osd->eth.tx_unicast,
936 &nsd->eth.tx_unicast);
937 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
938 I40E_GLPRT_MPTCL(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->eth.tx_multicast,
941 &nsd->eth.tx_multicast);
942 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
943 I40E_GLPRT_BPTCL(hw->port),
944 pf->stat_offsets_loaded,
945 &osd->eth.tx_broadcast,
946 &nsd->eth.tx_broadcast);
41c445ff 947
7812fddc
SN		 948 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
949 pf->stat_offsets_loaded,
950 &osd->tx_dropped_link_down,
951 &nsd->tx_dropped_link_down);
41c445ff 952
7812fddc
SN		 953 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
954 pf->stat_offsets_loaded,
955 &osd->crc_errors, &nsd->crc_errors);
41c445ff 956
7812fddc
SN		 957 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
958 pf->stat_offsets_loaded,
959 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 960
7812fddc
SN		 961 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->mac_local_faults,
964 &nsd->mac_local_faults);
965 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
966 pf->stat_offsets_loaded,
967 &osd->mac_remote_faults,
968 &nsd->mac_remote_faults);
41c445ff 969
7812fddc
SN		 970 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
971 pf->stat_offsets_loaded,
972 &osd->rx_length_errors,
973 &nsd->rx_length_errors);
41c445ff 974
7812fddc
SN		 975 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
976 pf->stat_offsets_loaded,
977 &osd->link_xon_rx, &nsd->link_xon_rx);
978 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
979 pf->stat_offsets_loaded,
980 &osd->link_xon_tx, &nsd->link_xon_tx);
95db239f
NP		 981 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
982 pf->stat_offsets_loaded,
983 &osd->link_xoff_rx, &nsd->link_xoff_rx);
7812fddc
SN		 984 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
985 pf->stat_offsets_loaded,
986 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 987
7812fddc 988 for (i = 0; i < 8; i++) {
95db239f
NP		 989 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
990 pf->stat_offsets_loaded,
991 &osd->priority_xoff_rx[i],
992 &nsd->priority_xoff_rx[i]);
7812fddc 993 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 994 pf->stat_offsets_loaded,
7812fddc
SN		 995 &osd->priority_xon_rx[i],
996 &nsd->priority_xon_rx[i]);
997 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 998 pf->stat_offsets_loaded,
7812fddc
SN		 999 &osd->priority_xon_tx[i],
1000 &nsd->priority_xon_tx[i]);
1001 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1002 pf->stat_offsets_loaded,
7812fddc
SN		 1003 &osd->priority_xoff_tx[i],
1004 &nsd->priority_xoff_tx[i]);
1005 i40e_stat_update32(hw,
1006 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1007 pf->stat_offsets_loaded,
7812fddc
SN		 1008 &osd->priority_xon_2_xoff[i],
1009 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1010 }
1011
7812fddc
SN		 1012 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1013 I40E_GLPRT_PRC64L(hw->port),
1014 pf->stat_offsets_loaded,
1015 &osd->rx_size_64, &nsd->rx_size_64);
1016 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1017 I40E_GLPRT_PRC127L(hw->port),
1018 pf->stat_offsets_loaded,
1019 &osd->rx_size_127, &nsd->rx_size_127);
1020 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1021 I40E_GLPRT_PRC255L(hw->port),
1022 pf->stat_offsets_loaded,
1023 &osd->rx_size_255, &nsd->rx_size_255);
1024 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1025 I40E_GLPRT_PRC511L(hw->port),
1026 pf->stat_offsets_loaded,
1027 &osd->rx_size_511, &nsd->rx_size_511);
1028 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1029 I40E_GLPRT_PRC1023L(hw->port),
1030 pf->stat_offsets_loaded,
1031 &osd->rx_size_1023, &nsd->rx_size_1023);
1032 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1033 I40E_GLPRT_PRC1522L(hw->port),
1034 pf->stat_offsets_loaded,
1035 &osd->rx_size_1522, &nsd->rx_size_1522);
1036 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1037 I40E_GLPRT_PRC9522L(hw->port),
1038 pf->stat_offsets_loaded,
1039 &osd->rx_size_big, &nsd->rx_size_big);
1040
1041 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1042 I40E_GLPRT_PTC64L(hw->port),
1043 pf->stat_offsets_loaded,
1044 &osd->tx_size_64, &nsd->tx_size_64);
1045 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1046 I40E_GLPRT_PTC127L(hw->port),
1047 pf->stat_offsets_loaded,
1048 &osd->tx_size_127, &nsd->tx_size_127);
1049 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1050 I40E_GLPRT_PTC255L(hw->port),
1051 pf->stat_offsets_loaded,
1052 &osd->tx_size_255, &nsd->tx_size_255);
1053 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1054 I40E_GLPRT_PTC511L(hw->port),
1055 pf->stat_offsets_loaded,
1056 &osd->tx_size_511, &nsd->tx_size_511);
1057 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1058 I40E_GLPRT_PTC1023L(hw->port),
1059 pf->stat_offsets_loaded,
1060 &osd->tx_size_1023, &nsd->tx_size_1023);
1061 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1062 I40E_GLPRT_PTC1522L(hw->port),
1063 pf->stat_offsets_loaded,
1064 &osd->tx_size_1522, &nsd->tx_size_1522);
1065 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1066 I40E_GLPRT_PTC9522L(hw->port),
1067 pf->stat_offsets_loaded,
1068 &osd->tx_size_big, &nsd->tx_size_big);
1069
1070 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1071 pf->stat_offsets_loaded,
1072 &osd->rx_undersize, &nsd->rx_undersize);
1073 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1074 pf->stat_offsets_loaded,
1075 &osd->rx_fragments, &nsd->rx_fragments);
1076 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1077 pf->stat_offsets_loaded,
1078 &osd->rx_oversize, &nsd->rx_oversize);
1079 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1080 pf->stat_offsets_loaded,
1081 &osd->rx_jabber, &nsd->rx_jabber);
1082
433c47de 1083 /* FDIR stats */
0bf4b1b0
ASJ		 1084 i40e_stat_update32(hw,
1085 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1086 pf->stat_offsets_loaded,
1087 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1088 i40e_stat_update32(hw,
1089 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1090 pf->stat_offsets_loaded,
1091 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1092 i40e_stat_update32(hw,
1093 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1094 pf->stat_offsets_loaded,
1095 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1096
7812fddc
SN		 1097 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1098 nsd->tx_lpi_status =
1099 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1100 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1101 nsd->rx_lpi_status =
1102 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1103 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1104 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1105 pf->stat_offsets_loaded,
1106 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1107 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1108 pf->stat_offsets_loaded,
1109 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1110
d0389e51
ASJ		 1111 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1112 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1113 nsd->fd_sb_status = true;
1114 else
1115 nsd->fd_sb_status = false;
1116
1117 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1118 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1119 nsd->fd_atr_status = true;
1120 else
1121 nsd->fd_atr_status = false;
1122
41c445ff
JB		 1123 pf->stat_offsets_loaded = true;
1124}
1125
7812fddc
SN		 1126/**
1127 * i40e_update_stats - Update the various statistics counters.
1128 * @vsi: the VSI to be updated
1129 *
1130 * Update the various stats for this VSI and its related entities.
1131 **/
1132void i40e_update_stats(struct i40e_vsi *vsi)
1133{
1134 struct i40e_pf *pf = vsi->back;
1135
1136 if (vsi == pf->vsi[pf->lan_vsi])
1137 i40e_update_pf_stats(pf);
1138
1139 i40e_update_vsi_stats(vsi);
38e00438
VD		 1140#ifdef I40E_FCOE
1141 i40e_update_fcoe_stats(vsi);
1142#endif
7812fddc
SN		 1143}
1144
41c445ff
JB		 1145/**
1146 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1147 * @vsi: the VSI to be searched
1148 * @macaddr: the MAC address
1149 * @vlan: the vlan
b40c82e6 1150 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1151 * @is_netdev: make sure its a netdev filter, else doesn't matter
1152 *
1153 * Returns ptr to the filter object or NULL
1154 **/
1155static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1156 u8 *macaddr, s16 vlan,
1157 bool is_vf, bool is_netdev)
1158{
1159 struct i40e_mac_filter *f;
1160
1161 if (!vsi || !macaddr)
1162 return NULL;
1163
1164 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1165 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1166 (vlan == f->vlan) &&
1167 (!is_vf || f->is_vf) &&
1168 (!is_netdev || f->is_netdev))
1169 return f;
1170 }
1171 return NULL;
1172}
1173
1174/**
1175 * i40e_find_mac - Find a mac addr in the macvlan filters list
1176 * @vsi: the VSI to be searched
1177 * @macaddr: the MAC address we are searching for
b40c82e6 1178 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1179 * @is_netdev: make sure its a netdev filter, else doesn't matter
1180 *
1181 * Returns the first filter with the provided MAC address or NULL if
1182 * MAC address was not found
1183 **/
1184struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1185 bool is_vf, bool is_netdev)
1186{
1187 struct i40e_mac_filter *f;
1188
1189 if (!vsi || !macaddr)
1190 return NULL;
1191
1192 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1193 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1194 (!is_vf || f->is_vf) &&
1195 (!is_netdev || f->is_netdev))
1196 return f;
1197 }
1198 return NULL;
1199}
1200
1201/**
1202 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1203 * @vsi: the VSI to be searched
1204 *
1205 * Returns true if VSI is in vlan mode or false otherwise
1206 **/
1207bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1208{
1209 struct i40e_mac_filter *f;
1210
1211 /* Only -1 for all the filters denotes not in vlan mode
1212 * so we have to go through all the list in order to make sure
1213 */
1214 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1215 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1216 return true;
1217 }
1218
1219 return false;
1220}
1221
1222/**
1223 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1224 * @vsi: the VSI to be searched
1225 * @macaddr: the mac address to be filtered
b40c82e6 1226 * @is_vf: true if it is a VF
41c445ff
JB		 1227 * @is_netdev: true if it is a netdev
1228 *
1229 * Goes through all the macvlan filters and adds a
1230 * macvlan filter for each unique vlan that already exists
1231 *
1232 * Returns first filter found on success, else NULL
1233 **/
1234struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1235 bool is_vf, bool is_netdev)
1236{
1237 struct i40e_mac_filter *f;
1238
1239 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1240 if (vsi->info.pvid)
1241 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1242 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1243 is_vf, is_netdev)) {
1244 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1245 is_vf, is_netdev))
41c445ff
JB		 1246 return NULL;
1247 }
1248 }
1249
1250 return list_first_entry_or_null(&vsi->mac_filter_list,
1251 struct i40e_mac_filter, list);
1252}
1253
b36e9ab5
MW		 1254/**
1255 * i40e_del_mac_all_vlan - Remove a MAC filter from all VLANS
1256 * @vsi: the VSI to be searched
1257 * @macaddr: the mac address to be removed
1258 * @is_vf: true if it is a VF
1259 * @is_netdev: true if it is a netdev
1260 *
1261 * Removes a given MAC address from a VSI, regardless of VLAN
1262 *
1263 * Returns 0 for success, or error
1264 **/
1265int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1266 bool is_vf, bool is_netdev)
1267{
1268 struct i40e_mac_filter *f = NULL;
1269 int changed = 0;
1270
1271 WARN(!spin_is_locked(&vsi->mac_filter_list_lock),
1272 "Missing mac_filter_list_lock\n");
1273 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1274 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1275 (is_vf == f->is_vf) &&
1276 (is_netdev == f->is_netdev)) {
1277 f->counter--;
1278 f->changed = true;
1279 changed = 1;
1280 }
1281 }
1282 if (changed) {
1283 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1284 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1285 return 0;
1286 }
1287 return -ENOENT;
1288}
1289
8c27d42e
GR		 1290/**
1291 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1292 * @vsi: the PF Main VSI - inappropriate for any other VSI
1293 * @macaddr: the MAC address
30650cc5
SN		 1294 *
1295 * Some older firmware configurations set up a default promiscuous VLAN
1296 * filter that needs to be removed.
8c27d42e 1297 **/
30650cc5 1298static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1299{
1300 struct i40e_aqc_remove_macvlan_element_data element;
1301 struct i40e_pf *pf = vsi->back;
f1c7e72e 1302 i40e_status ret;
8c27d42e
GR		 1303
1304 /* Only appropriate for the PF main VSI */
1305 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1306 return -EINVAL;
8c27d42e 1307
30650cc5 1308 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1309 ether_addr_copy(element.mac_addr, macaddr);
1310 element.vlan_tag = 0;
1311 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1312 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1313 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1314 if (ret)
30650cc5
SN		 1315 return -ENOENT;
1316
1317 return 0;
8c27d42e
GR		 1318}
1319
41c445ff
JB		 1320/**
1321 * i40e_add_filter - Add a mac/vlan filter to the VSI
1322 * @vsi: the VSI to be searched
1323 * @macaddr: the MAC address
1324 * @vlan: the vlan
b40c82e6 1325 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1326 * @is_netdev: make sure its a netdev filter, else doesn't matter
1327 *
1328 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1329 *
1330 * NOTE: This function is expected to be called with mac_filter_list_lock
1331 * being held.
41c445ff
JB		 1332 **/
1333struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1334 u8 *macaddr, s16 vlan,
1335 bool is_vf, bool is_netdev)
1336{
1337 struct i40e_mac_filter *f;
1338
1339 if (!vsi || !macaddr)
1340 return NULL;
1341
1342 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1343 if (!f) {
1344 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1345 if (!f)
1346 goto add_filter_out;
1347
9a173901 1348 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1349 f->vlan = vlan;
1350 f->changed = true;
1351
1352 INIT_LIST_HEAD(&f->list);
04d5a21d 1353 list_add_tail(&f->list, &vsi->mac_filter_list);
41c445ff
JB		 1354 }
1355
1356 /* increment counter and add a new flag if needed */
1357 if (is_vf) {
1358 if (!f->is_vf) {
1359 f->is_vf = true;
1360 f->counter++;
1361 }
1362 } else if (is_netdev) {
1363 if (!f->is_netdev) {
1364 f->is_netdev = true;
1365 f->counter++;
1366 }
1367 } else {
1368 f->counter++;
1369 }
1370
1371 /* changed tells sync_filters_subtask to
1372 * push the filter down to the firmware
1373 */
1374 if (f->changed) {
1375 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1376 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1377 }
1378
1379add_filter_out:
1380 return f;
1381}
1382
1383/**
1384 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1385 * @vsi: the VSI to be searched
1386 * @macaddr: the MAC address
1387 * @vlan: the vlan
b40c82e6 1388 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1389 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1390 *
1391 * NOTE: This function is expected to be called with mac_filter_list_lock
1392 * being held.
41c445ff
JB		 1393 **/
1394void i40e_del_filter(struct i40e_vsi *vsi,
1395 u8 *macaddr, s16 vlan,
1396 bool is_vf, bool is_netdev)
1397{
1398 struct i40e_mac_filter *f;
1399
1400 if (!vsi || !macaddr)
1401 return;
1402
1403 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1404 if (!f || f->counter == 0)
1405 return;
1406
1407 if (is_vf) {
1408 if (f->is_vf) {
1409 f->is_vf = false;
1410 f->counter--;
1411 }
1412 } else if (is_netdev) {
1413 if (f->is_netdev) {
1414 f->is_netdev = false;
1415 f->counter--;
1416 }
1417 } else {
b40c82e6 1418 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1419 int min_f = 0;
6995b36c 1420
41c445ff
JB		 1421 min_f += (f->is_vf ? 1 : 0);
1422 min_f += (f->is_netdev ? 1 : 0);
1423
1424 if (f->counter > min_f)
1425 f->counter--;
1426 }
1427
1428 /* counter == 0 tells sync_filters_subtask to
1429 * remove the filter from the firmware's list
1430 */
1431 if (f->counter == 0) {
1432 f->changed = true;
1433 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1434 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1435 }
1436}
1437
1438/**
1439 * i40e_set_mac - NDO callback to set mac address
1440 * @netdev: network interface device structure
1441 * @p: pointer to an address structure
1442 *
1443 * Returns 0 on success, negative on failure
1444 **/
38e00438
VD		 1445#ifdef I40E_FCOE
1446int i40e_set_mac(struct net_device *netdev, void *p)
1447#else
41c445ff 1448static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1449#endif
41c445ff
JB		 1450{
1451 struct i40e_netdev_priv *np = netdev_priv(netdev);
1452 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1453 struct i40e_pf *pf = vsi->back;
1454 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1455 struct sockaddr *addr = p;
1456 struct i40e_mac_filter *f;
1457
1458 if (!is_valid_ether_addr(addr->sa_data))
1459 return -EADDRNOTAVAIL;
1460
30650cc5
SN		 1461 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1462 netdev_info(netdev, "already using mac address %pM\n",
1463 addr->sa_data);
1464 return 0;
1465 }
41c445ff 1466
80f6428f
ASJ		 1467 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1468 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1469 return -EADDRNOTAVAIL;
1470
30650cc5
SN		 1471 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1472 netdev_info(netdev, "returning to hw mac address %pM\n",
1473 hw->mac.addr);
1474 else
1475 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1476
41c445ff
JB		 1477 if (vsi->type == I40E_VSI_MAIN) {
1478 i40e_status ret;
6995b36c 1479
41c445ff 1480 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1481 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1482 addr->sa_data, NULL);
1483 if (ret) {
1484 netdev_info(netdev,
1485 "Addr change for Main VSI failed: %d\n",
1486 ret);
1487 return -EADDRNOTAVAIL;
1488 }
41c445ff
JB		 1489 }
1490
30650cc5
SN		 1491 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1492 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1493
30650cc5
SN		 1494 memset(&element, 0, sizeof(element));
1495 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1496 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1497 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1498 } else {
21659035 1499 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1500 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1501 false, false);
21659035 1502 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1503 }
41c445ff 1504
30650cc5
SN		 1505 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1506 struct i40e_aqc_add_macvlan_element_data element;
1507
1508 memset(&element, 0, sizeof(element));
1509 ether_addr_copy(element.mac_addr, hw->mac.addr);
1510 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1511 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1512 } else {
21659035 1513 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1514 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1515 false, false);
1516 if (f)
1517 f->is_laa = true;
21659035 1518 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1519 }
1520
30650cc5 1521 ether_addr_copy(netdev->dev_addr, addr->sa_data);
ea02e90b 1522
c53934c6
JB		 1523 /* schedule our worker thread which will take care of
1524 * applying the new filter changes
1525 */
1526 i40e_service_event_schedule(vsi->back);
1527 return 0;
41c445ff
JB		 1528}
1529
1530/**
1531 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1532 * @vsi: the VSI being setup
1533 * @ctxt: VSI context structure
1534 * @enabled_tc: Enabled TCs bitmap
1535 * @is_add: True if called before Add VSI
1536 *
1537 * Setup VSI queue mapping for enabled traffic classes.
1538 **/
38e00438
VD		 1539#ifdef I40E_FCOE
1540void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1541 struct i40e_vsi_context *ctxt,
1542 u8 enabled_tc,
1543 bool is_add)
1544#else
41c445ff
JB		 1545static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1546 struct i40e_vsi_context *ctxt,
1547 u8 enabled_tc,
1548 bool is_add)
38e00438 1549#endif
41c445ff
JB		 1550{
1551 struct i40e_pf *pf = vsi->back;
1552 u16 sections = 0;
1553 u8 netdev_tc = 0;
1554 u16 numtc = 0;
1555 u16 qcount;
1556 u8 offset;
1557 u16 qmap;
1558 int i;
4e3b35b0 1559 u16 num_tc_qps = 0;
41c445ff
JB		 1560
1561 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1562 offset = 0;
1563
1564 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1565 /* Find numtc from enabled TC bitmap */
1566 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 1567 if (enabled_tc & BIT(i)) /* TC is enabled */
41c445ff
JB		 1568 numtc++;
1569 }
1570 if (!numtc) {
1571 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1572 numtc = 1;
1573 }
1574 } else {
1575 /* At least TC0 is enabled in case of non-DCB case */
1576 numtc = 1;
1577 }
1578
1579 vsi->tc_config.numtc = numtc;
1580 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1581 /* Number of queues per enabled TC */
7d64402f
CS		 1582 qcount = vsi->alloc_queue_pairs;
1583
7f9ff476 1584 num_tc_qps = qcount / numtc;
e25d00b8 1585 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1586
1587 /* Setup queue offset/count for all TCs for given VSI */
1588 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1589 /* See if the given TC is enabled for the given VSI */
75f5cea9 1590 if (vsi->tc_config.enabled_tc & BIT(i)) {
41a1d04b 1591 /* TC is enabled */
41c445ff
JB		 1592 int pow, num_qps;
1593
41c445ff
JB		 1594 switch (vsi->type) {
1595 case I40E_VSI_MAIN:
acd65448
HZ		 1596 qcount = min_t(int, pf->alloc_rss_size,
1597 num_tc_qps);
41c445ff 1598 break;
38e00438
VD		 1599#ifdef I40E_FCOE
1600 case I40E_VSI_FCOE:
1601 qcount = num_tc_qps;
1602 break;
1603#endif
41c445ff
JB		 1604 case I40E_VSI_FDIR:
1605 case I40E_VSI_SRIOV:
1606 case I40E_VSI_VMDQ2:
1607 default:
4e3b35b0 1608 qcount = num_tc_qps;
41c445ff
JB		 1609 WARN_ON(i != 0);
1610 break;
1611 }
4e3b35b0
NP		 1612 vsi->tc_config.tc_info[i].qoffset = offset;
1613 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1614
1e200e4a 1615 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1616 num_qps = qcount;
41c445ff 1617 pow = 0;
41a1d04b 1618 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1619 pow++;
1620 num_qps >>= 1;
1621 }
1622
1623 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1624 qmap =
1625 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1626 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1627
4e3b35b0 1628 offset += qcount;
41c445ff
JB		 1629 } else {
1630 /* TC is not enabled so set the offset to
1631 * default queue and allocate one queue
1632 * for the given TC.
1633 */
1634 vsi->tc_config.tc_info[i].qoffset = 0;
1635 vsi->tc_config.tc_info[i].qcount = 1;
1636 vsi->tc_config.tc_info[i].netdev_tc = 0;
1637
1638 qmap = 0;
1639 }
1640 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1641 }
1642
1643 /* Set actual Tx/Rx queue pairs */
1644 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1645 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1646 if (vsi->req_queue_pairs > 0)
1647 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1648 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1649 vsi->num_queue_pairs = pf->num_lan_msix;
1650 }
41c445ff
JB		 1651
1652 /* Scheduler section valid can only be set for ADD VSI */
1653 if (is_add) {
1654 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1655
1656 ctxt->info.up_enable_bits = enabled_tc;
1657 }
1658 if (vsi->type == I40E_VSI_SRIOV) {
1659 ctxt->info.mapping_flags |=
1660 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1661 for (i = 0; i < vsi->num_queue_pairs; i++)
1662 ctxt->info.queue_mapping[i] =
1663 cpu_to_le16(vsi->base_queue + i);
1664 } else {
1665 ctxt->info.mapping_flags |=
1666 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1667 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1668 }
1669 ctxt->info.valid_sections |= cpu_to_le16(sections);
1670}
1671
1672/**
1673 * i40e_set_rx_mode - NDO callback to set the netdev filters
1674 * @netdev: network interface device structure
1675 **/
38e00438
VD		 1676#ifdef I40E_FCOE
1677void i40e_set_rx_mode(struct net_device *netdev)
1678#else
41c445ff 1679static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1680#endif
41c445ff
JB		 1681{
1682 struct i40e_netdev_priv *np = netdev_priv(netdev);
1683 struct i40e_mac_filter *f, *ftmp;
1684 struct i40e_vsi *vsi = np->vsi;
1685 struct netdev_hw_addr *uca;
1686 struct netdev_hw_addr *mca;
1687 struct netdev_hw_addr *ha;
1688
21659035
KP		 1689 spin_lock_bh(&vsi->mac_filter_list_lock);
1690
41c445ff
JB		 1691 /* add addr if not already in the filter list */
1692 netdev_for_each_uc_addr(uca, netdev) {
1693 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1694 if (i40e_is_vsi_in_vlan(vsi))
1695 i40e_put_mac_in_vlan(vsi, uca->addr,
1696 false, true);
1697 else
1698 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1699 false, true);
1700 }
1701 }
1702
1703 netdev_for_each_mc_addr(mca, netdev) {
1704 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1705 if (i40e_is_vsi_in_vlan(vsi))
1706 i40e_put_mac_in_vlan(vsi, mca->addr,
1707 false, true);
1708 else
1709 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1710 false, true);
1711 }
1712 }
1713
1714 /* remove filter if not in netdev list */
1715 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1716
1717 if (!f->is_netdev)
1718 continue;
1719
2f41f335
SN		 1720 netdev_for_each_mc_addr(mca, netdev)
1721 if (ether_addr_equal(mca->addr, f->macaddr))
1722 goto bottom_of_search_loop;
41c445ff 1723
2f41f335
SN		 1724 netdev_for_each_uc_addr(uca, netdev)
1725 if (ether_addr_equal(uca->addr, f->macaddr))
1726 goto bottom_of_search_loop;
1727
1728 for_each_dev_addr(netdev, ha)
1729 if (ether_addr_equal(ha->addr, f->macaddr))
1730 goto bottom_of_search_loop;
1731
1732 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1733 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1734
1735bottom_of_search_loop:
1736 continue;
41c445ff 1737 }
21659035 1738 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1739
1740 /* check for other flag changes */
1741 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1742 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1743 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1744 }
c53934c6
JB		 1745
1746 /* schedule our worker thread which will take care of
1747 * applying the new filter changes
1748 */
1749 i40e_service_event_schedule(vsi->back);
41c445ff
JB		 1750}
1751
21659035
KP		 1752/**
1753 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1754 * @src: source MAC filter entry to be clones
1755 *
1756 * Returns the pointer to newly cloned MAC filter entry or NULL
1757 * in case of error
1758 **/
1759static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1760 struct i40e_mac_filter *src)
1761{
1762 struct i40e_mac_filter *f;
1763
1764 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1765 if (!f)
1766 return NULL;
1767 *f = *src;
1768
1769 INIT_LIST_HEAD(&f->list);
1770
1771 return f;
1772}
1773
1774/**
1775 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1776 * @vsi: pointer to vsi struct
1777 * @from: Pointer to list which contains MAC filter entries - changes to
1778 * those entries needs to be undone.
1779 *
1780 * MAC filter entries from list were slated to be removed from device.
1781 **/
1782static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1783 struct list_head *from)
1784{
1785 struct i40e_mac_filter *f, *ftmp;
1786
1787 list_for_each_entry_safe(f, ftmp, from, list) {
1788 f->changed = true;
1789 /* Move the element back into MAC filter list*/
1790 list_move_tail(&f->list, &vsi->mac_filter_list);
1791 }
1792}
1793
1794/**
1795 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1796 * @vsi: pointer to vsi struct
1797 *
1798 * MAC filter entries from list were slated to be added from device.
1799 **/
1800static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1801{
1802 struct i40e_mac_filter *f, *ftmp;
1803
1804 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1805 if (!f->changed && f->counter)
1806 f->changed = true;
1807 }
1808}
1809
1810/**
1811 * i40e_cleanup_add_list - Deletes the element from add list and release
1812 * memory
1813 * @add_list: Pointer to list which contains MAC filter entries
1814 **/
1815static void i40e_cleanup_add_list(struct list_head *add_list)
1816{
1817 struct i40e_mac_filter *f, *ftmp;
1818
1819 list_for_each_entry_safe(f, ftmp, add_list, list) {
1820 list_del(&f->list);
1821 kfree(f);
1822 }
1823}
1824
41c445ff
JB		 1825/**
1826 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1827 * @vsi: ptr to the VSI
1828 *
1829 * Push any outstanding VSI filter changes through the AdminQ.
1830 *
1831 * Returns 0 or error value
1832 **/
17652c63 1833int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1834{
21659035
KP		 1835 struct list_head tmp_del_list, tmp_add_list;
1836 struct i40e_mac_filter *f, *ftmp, *fclone;
3e25a8f3 1837 struct i40e_hw *hw = &vsi->back->hw;
41c445ff
JB		 1838 bool promisc_forced_on = false;
1839 bool add_happened = false;
2d1de828 1840 char vsi_name[16] = "PF";
41c445ff
JB		 1841 int filter_list_len = 0;
1842 u32 changed_flags = 0;
ea02e90b 1843 i40e_status aq_ret = 0;
21659035 1844 bool err_cond = false;
ea02e90b 1845 int retval = 0;
41c445ff
JB		 1846 struct i40e_pf *pf;
1847 int num_add = 0;
1848 int num_del = 0;
f1c7e72e 1849 int aq_err = 0;
41c445ff
JB		 1850 u16 cmd_flags;
1851
1852 /* empty array typed pointers, kcalloc later */
1853 struct i40e_aqc_add_macvlan_element_data *add_list;
1854 struct i40e_aqc_remove_macvlan_element_data *del_list;
1855
1856 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1857 usleep_range(1000, 2000);
1858 pf = vsi->back;
1859
1860 if (vsi->netdev) {
1861 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1862 vsi->current_netdev_flags = vsi->netdev->flags;
1863 }
1864
21659035
KP		 1865 INIT_LIST_HEAD(&tmp_del_list);
1866 INIT_LIST_HEAD(&tmp_add_list);
1867
2d1de828
SN		 1868 if (vsi->type == I40E_VSI_SRIOV)
1869 snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id);
1870 else if (vsi->type != I40E_VSI_MAIN)
1871 snprintf(vsi_name, sizeof(vsi_name) - 1, "vsi %d", vsi->seid);
1872
41c445ff
JB		 1873 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1874 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1875
21659035 1876 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1877 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1878 if (!f->changed)
1879 continue;
1880
1881 if (f->counter != 0)
1882 continue;
1883 f->changed = false;
21659035
KP		 1884
1885 /* Move the element into temporary del_list */
1886 list_move_tail(&f->list, &tmp_del_list);
1887 }
1888
1889 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1890 if (!f->changed)
1891 continue;
1892
1893 if (f->counter == 0)
1894 continue;
1895 f->changed = false;
1896
1897 /* Clone MAC filter entry and add into temporary list */
1898 fclone = i40e_mac_filter_entry_clone(f);
1899 if (!fclone) {
1900 err_cond = true;
1901 break;
1902 }
1903 list_add_tail(&fclone->list, &tmp_add_list);
1904 }
1905
1906 /* if failed to clone MAC filter entry - undo */
1907 if (err_cond) {
1908 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1909 i40e_undo_add_filter_entries(vsi);
1910 }
1911 spin_unlock_bh(&vsi->mac_filter_list_lock);
1912
ea02e90b 1913 if (err_cond) {
21659035 1914 i40e_cleanup_add_list(&tmp_add_list);
ea02e90b
MW		 1915 retval = -ENOMEM;
1916 goto out;
1917 }
21659035
KP		 1918 }
1919
1920 /* Now process 'del_list' outside the lock */
1921 if (!list_empty(&tmp_del_list)) {
f1199998
SN		 1922 int del_list_size;
1923
3e25a8f3 1924 filter_list_len = hw->aq.asq_buf_size /
21659035 1925 sizeof(struct i40e_aqc_remove_macvlan_element_data);
f1199998
SN		 1926 del_list_size = filter_list_len *
1927 sizeof(struct i40e_aqc_remove_macvlan_element_data);
38c3cec7 1928 del_list = kzalloc(del_list_size, GFP_ATOMIC);
21659035
KP		 1929 if (!del_list) {
1930 i40e_cleanup_add_list(&tmp_add_list);
1931
1932 /* Undo VSI's MAC filter entry element updates */
1933 spin_lock_bh(&vsi->mac_filter_list_lock);
1934 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1935 i40e_undo_add_filter_entries(vsi);
1936 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1937 retval = -ENOMEM;
1938 goto out;
21659035
KP		 1939 }
1940
1941 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1942 cmd_flags = 0;
1943
1944 /* add to delete list */
9a173901 1945 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1946 del_list[num_del].vlan_tag =
1947 cpu_to_le16((u16)(f->vlan ==
1948 I40E_VLAN_ANY ? 0 : f->vlan));
1949
41c445ff
JB		 1950 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1951 del_list[num_del].flags = cmd_flags;
1952 num_del++;
1953
41c445ff
JB		 1954 /* flush a full buffer */
1955 if (num_del == filter_list_len) {
3e25a8f3
MW		 1956 aq_ret =
1957 i40e_aq_remove_macvlan(hw, vsi->seid,
1958 del_list,
1959 num_del, NULL);
1960 aq_err = hw->aq.asq_last_status;
41c445ff 1961 num_del = 0;
f1199998 1962 memset(del_list, 0, del_list_size);
41c445ff 1963
ea02e90b
MW		 1964 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT) {
1965 retval = -EIO;
21659035 1966 dev_err(&pf->pdev->dev,
2d1de828
SN		 1967 "ignoring delete macvlan error on %s, err %s, aq_err %s while flushing a full buffer\n",
1968 vsi_name,
3e25a8f3
MW		 1969 i40e_stat_str(hw, aq_ret),
1970 i40e_aq_str(hw, aq_err));
ea02e90b 1971 }
41c445ff 1972 }
21659035
KP		 1973 /* Release memory for MAC filter entries which were
1974 * synced up with HW.
1975 */
1976 list_del(&f->list);
1977 kfree(f);
41c445ff 1978 }
21659035 1979
41c445ff 1980 if (num_del) {
3e25a8f3
MW		 1981 aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, del_list,
1982 num_del, NULL);
1983 aq_err = hw->aq.asq_last_status;
41c445ff
JB		 1984 num_del = 0;
1985
ea02e90b 1986 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1987 dev_info(&pf->pdev->dev,
2d1de828
SN		 1988 "ignoring delete macvlan error on %s, err %s aq_err %s\n",
1989 vsi_name,
3e25a8f3
MW		 1990 i40e_stat_str(hw, aq_ret),
1991 i40e_aq_str(hw, aq_err));
41c445ff
JB		 1992 }
1993
1994 kfree(del_list);
1995 del_list = NULL;
21659035
KP		 1996 }
1997
1998 if (!list_empty(&tmp_add_list)) {
f1199998 1999 int add_list_size;
41c445ff
JB		 2000
2001 /* do all the adds now */
3e25a8f3 2002 filter_list_len = hw->aq.asq_buf_size /
41c445ff 2003 sizeof(struct i40e_aqc_add_macvlan_element_data),
f1199998
SN		 2004 add_list_size = filter_list_len *
2005 sizeof(struct i40e_aqc_add_macvlan_element_data);
38c3cec7 2006 add_list = kzalloc(add_list_size, GFP_ATOMIC);
21659035
KP		 2007 if (!add_list) {
2008 /* Purge element from temporary lists */
2009 i40e_cleanup_add_list(&tmp_add_list);
2010
2011 /* Undo add filter entries from VSI MAC filter list */
2012 spin_lock_bh(&vsi->mac_filter_list_lock);
2013 i40e_undo_add_filter_entries(vsi);
2014 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 2015 retval = -ENOMEM;
2016 goto out;
21659035 2017 }
41c445ff 2018
21659035 2019 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 2020
41c445ff
JB		 2021 add_happened = true;
2022 cmd_flags = 0;
2023
2024 /* add to add array */
9a173901 2025 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 2026 add_list[num_add].vlan_tag =
2027 cpu_to_le16(
2028 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
2029 add_list[num_add].queue_number = 0;
2030
2031 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 2032 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2033 num_add++;
2034
2035 /* flush a full buffer */
2036 if (num_add == filter_list_len) {
3e25a8f3 2037 aq_ret = i40e_aq_add_macvlan(hw, vsi->seid,
ea02e90b
MW		 2038 add_list, num_add,
2039 NULL);
3e25a8f3 2040 aq_err = hw->aq.asq_last_status;
41c445ff
JB		 2041 num_add = 0;
2042
ea02e90b 2043 if (aq_ret)
41c445ff 2044 break;
f1199998 2045 memset(add_list, 0, add_list_size);
41c445ff 2046 }
21659035
KP		 2047 /* Entries from tmp_add_list were cloned from MAC
2048 * filter list, hence clean those cloned entries
2049 */
2050 list_del(&f->list);
2051 kfree(f);
41c445ff 2052 }
21659035 2053
41c445ff 2054 if (num_add) {
3e25a8f3 2055 aq_ret = i40e_aq_add_macvlan(hw, vsi->seid,
ea02e90b 2056 add_list, num_add, NULL);
3e25a8f3 2057 aq_err = hw->aq.asq_last_status;
41c445ff
JB		 2058 num_add = 0;
2059 }
2060 kfree(add_list);
2061 add_list = NULL;
2062
ea02e90b
MW		 2063 if (add_happened && aq_ret && aq_err != I40E_AQ_RC_EINVAL) {
2064 retval = i40e_aq_rc_to_posix(aq_ret, aq_err);
41c445ff 2065 dev_info(&pf->pdev->dev,
2d1de828
SN		 2066 "add filter failed on %s, err %s aq_err %s\n",
2067 vsi_name,
3e25a8f3
MW		 2068 i40e_stat_str(hw, aq_ret),
2069 i40e_aq_str(hw, aq_err));
2070 if ((hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
41c445ff
JB		 2071 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2072 &vsi->state)) {
2073 promisc_forced_on = true;
2074 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2075 &vsi->state);
2d1de828
SN		 2076 dev_info(&pf->pdev->dev, "promiscuous mode forced on %s\n",
2077 vsi_name);
41c445ff
JB		 2078 }
2079 }
2080 }
2081
a856b5cb
ASJ		 2082 /* if the VF is not trusted do not do promisc */
2083 if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) {
2084 clear_bit(__I40E_FILTER_OVERFLOW_PROMISC, &vsi->state);
2085 goto out;
2086 }
2087
41c445ff
JB		 2088 /* check for changes in promiscuous modes */
2089 if (changed_flags & IFF_ALLMULTI) {
2090 bool cur_multipromisc;
6995b36c 2091
41c445ff 2092 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
ea02e90b
MW		 2093 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2094 vsi->seid,
2095 cur_multipromisc,
2096 NULL);
2097 if (aq_ret) {
2098 retval = i40e_aq_rc_to_posix(aq_ret,
3e25a8f3 2099 hw->aq.asq_last_status);
41c445ff 2100 dev_info(&pf->pdev->dev,
2d1de828
SN		 2101 "set multi promisc failed on %s, err %s aq_err %s\n",
2102 vsi_name,
3e25a8f3
MW		 2103 i40e_stat_str(hw, aq_ret),
2104 i40e_aq_str(hw, hw->aq.asq_last_status));
ea02e90b 2105 }
41c445ff
JB		 2106 }
2107 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2108 bool cur_promisc;
6995b36c 2109
41c445ff
JB		 2110 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2111 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2112 &vsi->state));
6784ed5a
ASJ		 2113 if ((vsi->type == I40E_VSI_MAIN) &&
2114 (pf->lan_veb != I40E_NO_VEB) &&
2115 !(pf->flags & I40E_FLAG_MFP_ENABLED)) {
92faef85
ASJ		 2116 /* set defport ON for Main VSI instead of true promisc
2117 * this way we will get all unicast/multicast and VLAN
2118 * promisc behavior but will not get VF or VMDq traffic
2119 * replicated on the Main VSI.
2120 */
2121 if (pf->cur_promisc != cur_promisc) {
2122 pf->cur_promisc = cur_promisc;
5bc16031
MW		 2123 if (cur_promisc)
2124 aq_ret =
2125 i40e_aq_set_default_vsi(hw,
2126 vsi->seid,
2127 NULL);
2128 else
2129 aq_ret =
2130 i40e_aq_clear_default_vsi(hw,
2131 vsi->seid,
2132 NULL);
2133 if (aq_ret) {
2134 retval = i40e_aq_rc_to_posix(aq_ret,
2135 hw->aq.asq_last_status);
2136 dev_info(&pf->pdev->dev,
2d1de828
SN		 2137 "Set default VSI failed on %s, err %s, aq_err %s\n",
2138 vsi_name,
5bc16031
MW		 2139 i40e_stat_str(hw, aq_ret),
2140 i40e_aq_str(hw,
2141 hw->aq.asq_last_status));
2142 }
92faef85
ASJ		 2143 }
2144 } else {
ea02e90b 2145 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
3e25a8f3 2146 hw,
f1c7e72e 2147 vsi->seid,
b5569892
ASJ		 2148 cur_promisc, NULL,
2149 true);
ea02e90b
MW		 2150 if (aq_ret) {
2151 retval =
2152 i40e_aq_rc_to_posix(aq_ret,
3e25a8f3 2153 hw->aq.asq_last_status);
92faef85 2154 dev_info(&pf->pdev->dev,
2d1de828
SN		 2155 "set unicast promisc failed on %s, err %s, aq_err %s\n",
2156 vsi_name,
3e25a8f3
MW		 2157 i40e_stat_str(hw, aq_ret),
2158 i40e_aq_str(hw,
2159 hw->aq.asq_last_status));
ea02e90b
MW		 2160 }
2161 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
3e25a8f3 2162 hw,
92faef85
ASJ		 2163 vsi->seid,
2164 cur_promisc, NULL);
ea02e90b
MW		 2165 if (aq_ret) {
2166 retval =
2167 i40e_aq_rc_to_posix(aq_ret,
3e25a8f3 2168 hw->aq.asq_last_status);
92faef85 2169 dev_info(&pf->pdev->dev,
2d1de828
SN		 2170 "set multicast promisc failed on %s, err %s, aq_err %s\n",
2171 vsi_name,
3e25a8f3
MW		 2172 i40e_stat_str(hw, aq_ret),
2173 i40e_aq_str(hw,
2174 hw->aq.asq_last_status));
ea02e90b 2175 }
92faef85 2176 }
ea02e90b
MW		 2177 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2178 vsi->seid,
2179 cur_promisc, NULL);
2180 if (aq_ret) {
2181 retval = i40e_aq_rc_to_posix(aq_ret,
2182 pf->hw.aq.asq_last_status);
1a10370a 2183 dev_info(&pf->pdev->dev,
f1c7e72e 2184 "set brdcast promisc failed, err %s, aq_err %s\n",
3e25a8f3
MW		 2185 i40e_stat_str(hw, aq_ret),
2186 i40e_aq_str(hw,
2187 hw->aq.asq_last_status));
ea02e90b 2188 }
41c445ff 2189 }
ea02e90b 2190out:
2818ccd9
JB		 2191 /* if something went wrong then set the changed flag so we try again */
2192 if (retval)
2193 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
2194
41c445ff 2195 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
ea02e90b 2196 return retval;
41c445ff
JB		 2197}
2198
2199/**
2200 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2201 * @pf: board private structure
2202 **/
2203static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2204{
2205 int v;
2206
2207 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2208 return;
2209 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2210
505682cd 2211 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2212 if (pf->vsi[v] &&
17652c63
JB		 2213 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2214 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2215
2216 if (ret) {
2217 /* come back and try again later */
2218 pf->flags |= I40E_FLAG_FILTER_SYNC;
2219 break;
2220 }
2221 }
41c445ff
JB		 2222 }
2223}
2224
2225/**
2226 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2227 * @netdev: network interface device structure
2228 * @new_mtu: new value for maximum frame size
2229 *
2230 * Returns 0 on success, negative on failure
2231 **/
2232static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2233{
2234 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2235 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2236 struct i40e_vsi *vsi = np->vsi;
2237
2238 /* MTU < 68 is an error and causes problems on some kernels */
2239 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2240 return -EINVAL;
2241
2242 netdev_info(netdev, "changing MTU from %d to %d\n",
2243 netdev->mtu, new_mtu);
2244 netdev->mtu = new_mtu;
2245 if (netif_running(netdev))
2246 i40e_vsi_reinit_locked(vsi);
e3219ce6 2247 i40e_notify_client_of_l2_param_changes(vsi);
41c445ff
JB		 2248 return 0;
2249}
2250
beb0dff1
JK		 2251/**
2252 * i40e_ioctl - Access the hwtstamp interface
2253 * @netdev: network interface device structure
2254 * @ifr: interface request data
2255 * @cmd: ioctl command
2256 **/
2257int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2258{
2259 struct i40e_netdev_priv *np = netdev_priv(netdev);
2260 struct i40e_pf *pf = np->vsi->back;
2261
2262 switch (cmd) {
2263 case SIOCGHWTSTAMP:
2264 return i40e_ptp_get_ts_config(pf, ifr);
2265 case SIOCSHWTSTAMP:
2266 return i40e_ptp_set_ts_config(pf, ifr);
2267 default:
2268 return -EOPNOTSUPP;
2269 }
2270}
2271
41c445ff
JB		 2272/**
2273 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2274 * @vsi: the vsi being adjusted
2275 **/
2276void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2277{
2278 struct i40e_vsi_context ctxt;
2279 i40e_status ret;
2280
2281 if ((vsi->info.valid_sections &
2282 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2283 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2284 return; /* already enabled */
2285
2286 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2287 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2288 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2289
2290 ctxt.seid = vsi->seid;
1a2f6248 2291 ctxt.info = vsi->info;
41c445ff
JB		 2292 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2293 if (ret) {
2294 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2295 "update vlan stripping failed, err %s aq_err %s\n",
2296 i40e_stat_str(&vsi->back->hw, ret),
2297 i40e_aq_str(&vsi->back->hw,
2298 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2299 }
2300}
2301
2302/**
2303 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2304 * @vsi: the vsi being adjusted
2305 **/
2306void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2307{
2308 struct i40e_vsi_context ctxt;
2309 i40e_status ret;
2310
2311 if ((vsi->info.valid_sections &
2312 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2313 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2314 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2315 return; /* already disabled */
2316
2317 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2318 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2319 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2320
2321 ctxt.seid = vsi->seid;
1a2f6248 2322 ctxt.info = vsi->info;
41c445ff
JB		 2323 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2324 if (ret) {
2325 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2326 "update vlan stripping failed, err %s aq_err %s\n",
2327 i40e_stat_str(&vsi->back->hw, ret),
2328 i40e_aq_str(&vsi->back->hw,
2329 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2330 }
2331}
2332
2333/**
2334 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2335 * @netdev: network interface to be adjusted
2336 * @features: netdev features to test if VLAN offload is enabled or not
2337 **/
2338static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2339{
2340 struct i40e_netdev_priv *np = netdev_priv(netdev);
2341 struct i40e_vsi *vsi = np->vsi;
2342
2343 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2344 i40e_vlan_stripping_enable(vsi);
2345 else
2346 i40e_vlan_stripping_disable(vsi);
2347}
2348
2349/**
2350 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2351 * @vsi: the vsi being configured
2352 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2353 **/
2354int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2355{
2356 struct i40e_mac_filter *f, *add_f;
2357 bool is_netdev, is_vf;
41c445ff
JB		 2358
2359 is_vf = (vsi->type == I40E_VSI_SRIOV);
2360 is_netdev = !!(vsi->netdev);
2361
21659035
KP		 2362 /* Locked once because all functions invoked below iterates list*/
2363 spin_lock_bh(&vsi->mac_filter_list_lock);
2364
41c445ff
JB		 2365 if (is_netdev) {
2366 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2367 is_vf, is_netdev);
2368 if (!add_f) {
2369 dev_info(&vsi->back->pdev->dev,
2370 "Could not add vlan filter %d for %pM\n",
2371 vid, vsi->netdev->dev_addr);
21659035 2372 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2373 return -ENOMEM;
2374 }
2375 }
2376
2377 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2378 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2379 if (!add_f) {
2380 dev_info(&vsi->back->pdev->dev,
2381 "Could not add vlan filter %d for %pM\n",
2382 vid, f->macaddr);
21659035 2383 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2384 return -ENOMEM;
2385 }
2386 }
2387
41c445ff
JB		 2388 /* Now if we add a vlan tag, make sure to check if it is the first
2389 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2390 * with 0, so we now accept untagged and specified tagged traffic
2391 * (and not any taged and untagged)
2392 */
2393 if (vid > 0) {
2394 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2395 I40E_VLAN_ANY,
2396 is_vf, is_netdev)) {
2397 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2398 I40E_VLAN_ANY, is_vf, is_netdev);
2399 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2400 is_vf, is_netdev);
2401 if (!add_f) {
2402 dev_info(&vsi->back->pdev->dev,
2403 "Could not add filter 0 for %pM\n",
2404 vsi->netdev->dev_addr);
21659035 2405 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2406 return -ENOMEM;
2407 }
2408 }
8d82a7c5 2409 }
41c445ff 2410
8d82a7c5
GR		 2411 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2412 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2413 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2414 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2415 is_vf, is_netdev))
2416 continue;
2417 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2418 is_vf, is_netdev);
2419 add_f = i40e_add_filter(vsi, f->macaddr,
2420 0, is_vf, is_netdev);
2421 if (!add_f) {
2422 dev_info(&vsi->back->pdev->dev,
2423 "Could not add filter 0 for %pM\n",
2424 f->macaddr);
2425 spin_unlock_bh(&vsi->mac_filter_list_lock);
2426 return -ENOMEM;
41c445ff
JB		 2427 }
2428 }
41c445ff
JB		 2429 }
2430
21659035
KP		 2431 spin_unlock_bh(&vsi->mac_filter_list_lock);
2432
0e4425ed
JB		 2433 /* schedule our worker thread which will take care of
2434 * applying the new filter changes
2435 */
2436 i40e_service_event_schedule(vsi->back);
2437 return 0;
41c445ff
JB		 2438}
2439
2440/**
2441 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2442 * @vsi: the vsi being configured
2443 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2444 *
2445 * Return: 0 on success or negative otherwise
41c445ff
JB		 2446 **/
2447int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2448{
2449 struct net_device *netdev = vsi->netdev;
2450 struct i40e_mac_filter *f, *add_f;
2451 bool is_vf, is_netdev;
2452 int filter_count = 0;
41c445ff
JB		 2453
2454 is_vf = (vsi->type == I40E_VSI_SRIOV);
2455 is_netdev = !!(netdev);
2456
21659035
KP		 2457 /* Locked once because all functions invoked below iterates list */
2458 spin_lock_bh(&vsi->mac_filter_list_lock);
2459
41c445ff
JB		 2460 if (is_netdev)
2461 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2462
2463 list_for_each_entry(f, &vsi->mac_filter_list, list)
2464 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2465
41c445ff
JB		 2466 /* go through all the filters for this VSI and if there is only
2467 * vid == 0 it means there are no other filters, so vid 0 must
2468 * be replaced with -1. This signifies that we should from now
2469 * on accept any traffic (with any tag present, or untagged)
2470 */
2471 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2472 if (is_netdev) {
2473 if (f->vlan &&
2474 ether_addr_equal(netdev->dev_addr, f->macaddr))
2475 filter_count++;
2476 }
2477
2478 if (f->vlan)
2479 filter_count++;
2480 }
2481
2482 if (!filter_count && is_netdev) {
2483 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2484 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2485 is_vf, is_netdev);
2486 if (!f) {
2487 dev_info(&vsi->back->pdev->dev,
2488 "Could not add filter %d for %pM\n",
2489 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2490 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2491 return -ENOMEM;
2492 }
2493 }
2494
2495 if (!filter_count) {
2496 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2497 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2498 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2499 is_vf, is_netdev);
41c445ff
JB		 2500 if (!add_f) {
2501 dev_info(&vsi->back->pdev->dev,
2502 "Could not add filter %d for %pM\n",
2503 I40E_VLAN_ANY, f->macaddr);
21659035 2504 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2505 return -ENOMEM;
2506 }
2507 }
2508 }
2509
21659035
KP		 2510 spin_unlock_bh(&vsi->mac_filter_list_lock);
2511
0e4425ed
JB		 2512 /* schedule our worker thread which will take care of
2513 * applying the new filter changes
2514 */
2515 i40e_service_event_schedule(vsi->back);
2516 return 0;
41c445ff
JB		 2517}
2518
2519/**
2520 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2521 * @netdev: network interface to be adjusted
2522 * @vid: vlan id to be added
078b5876
JB		 2523 *
2524 * net_device_ops implementation for adding vlan ids
41c445ff 2525 **/
38e00438
VD		 2526#ifdef I40E_FCOE
2527int i40e_vlan_rx_add_vid(struct net_device *netdev,
2528 __always_unused __be16 proto, u16 vid)
2529#else
41c445ff
JB		 2530static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2531 __always_unused __be16 proto, u16 vid)
38e00438 2532#endif
41c445ff
JB		 2533{
2534 struct i40e_netdev_priv *np = netdev_priv(netdev);
2535 struct i40e_vsi *vsi = np->vsi;
078b5876 2536 int ret = 0;
41c445ff
JB		 2537
2538 if (vid > 4095)
078b5876
JB		 2539 return -EINVAL;
2540
2541 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2542
6982d429
ASJ		 2543 /* If the network stack called us with vid = 0 then
2544 * it is asking to receive priority tagged packets with
2545 * vlan id 0. Our HW receives them by default when configured
2546 * to receive untagged packets so there is no need to add an
2547 * extra filter for vlan 0 tagged packets.
41c445ff 2548 */
6982d429
ASJ		 2549 if (vid)
2550 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2551
078b5876
JB		 2552 if (!ret && (vid < VLAN_N_VID))
2553 set_bit(vid, vsi->active_vlans);
41c445ff 2554
078b5876 2555 return ret;
41c445ff
JB		 2556}
2557
2558/**
2559 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2560 * @netdev: network interface to be adjusted
2561 * @vid: vlan id to be removed
078b5876 2562 *
fdfd943e 2563 * net_device_ops implementation for removing vlan ids
41c445ff 2564 **/
38e00438
VD		 2565#ifdef I40E_FCOE
2566int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2567 __always_unused __be16 proto, u16 vid)
2568#else
41c445ff
JB		 2569static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2570 __always_unused __be16 proto, u16 vid)
38e00438 2571#endif
41c445ff
JB		 2572{
2573 struct i40e_netdev_priv *np = netdev_priv(netdev);
2574 struct i40e_vsi *vsi = np->vsi;
2575
078b5876
JB		 2576 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2577
41c445ff
JB		 2578 /* return code is ignored as there is nothing a user
2579 * can do about failure to remove and a log message was
078b5876 2580 * already printed from the other function
41c445ff
JB		 2581 */
2582 i40e_vsi_kill_vlan(vsi, vid);
2583
2584 clear_bit(vid, vsi->active_vlans);
078b5876 2585
41c445ff
JB		 2586 return 0;
2587}
2588
2589/**
2590 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2591 * @vsi: the vsi being brought back up
2592 **/
2593static void i40e_restore_vlan(struct i40e_vsi *vsi)
2594{
2595 u16 vid;
2596
2597 if (!vsi->netdev)
2598 return;
2599
2600 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2601
2602 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2603 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2604 vid);
2605}
2606
2607/**
2608 * i40e_vsi_add_pvid - Add pvid for the VSI
2609 * @vsi: the vsi being adjusted
2610 * @vid: the vlan id to set as a PVID
2611 **/
dcae29be 2612int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2613{
2614 struct i40e_vsi_context ctxt;
f1c7e72e 2615 i40e_status ret;
41c445ff
JB		 2616
2617 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2618 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2619 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2620 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2621 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2622
2623 ctxt.seid = vsi->seid;
1a2f6248 2624 ctxt.info = vsi->info;
f1c7e72e
SN		 2625 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2626 if (ret) {
41c445ff 2627 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2628 "add pvid failed, err %s aq_err %s\n",
2629 i40e_stat_str(&vsi->back->hw, ret),
2630 i40e_aq_str(&vsi->back->hw,
2631 vsi->back->hw.aq.asq_last_status));
dcae29be 2632 return -ENOENT;
41c445ff
JB		 2633 }
2634
dcae29be 2635 return 0;
41c445ff
JB		 2636}
2637
2638/**
2639 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2640 * @vsi: the vsi being adjusted
2641 *
2642 * Just use the vlan_rx_register() service to put it back to normal
2643 **/
2644void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2645{
6c12fcbf
GR		 2646 i40e_vlan_stripping_disable(vsi);
2647
41c445ff 2648 vsi->info.pvid = 0;
41c445ff
JB		 2649}
2650
2651/**
2652 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2653 * @vsi: ptr to the VSI
2654 *
2655 * If this function returns with an error, then it's possible one or
2656 * more of the rings is populated (while the rest are not). It is the
2657 * callers duty to clean those orphaned rings.
2658 *
2659 * Return 0 on success, negative on failure
2660 **/
2661static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2662{
2663 int i, err = 0;
2664
2665 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2666 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2667
2668 return err;
2669}
2670
2671/**
2672 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2673 * @vsi: ptr to the VSI
2674 *
2675 * Free VSI's transmit software resources
2676 **/
2677static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2678{
2679 int i;
2680
8e9dca53
GR		 2681 if (!vsi->tx_rings)
2682 return;
2683
41c445ff 2684 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2685 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2686 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2687}
2688
2689/**
2690 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2691 * @vsi: ptr to the VSI
2692 *
2693 * If this function returns with an error, then it's possible one or
2694 * more of the rings is populated (while the rest are not). It is the
2695 * callers duty to clean those orphaned rings.
2696 *
2697 * Return 0 on success, negative on failure
2698 **/
2699static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2700{
2701 int i, err = 0;
2702
2703 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2704 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2705#ifdef I40E_FCOE
2706 i40e_fcoe_setup_ddp_resources(vsi);
2707#endif
41c445ff
JB		 2708 return err;
2709}
2710
2711/**
2712 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2713 * @vsi: ptr to the VSI
2714 *
2715 * Free all receive software resources
2716 **/
2717static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2718{
2719 int i;
2720
8e9dca53
GR		 2721 if (!vsi->rx_rings)
2722 return;
2723
41c445ff 2724 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2725 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2726 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2727#ifdef I40E_FCOE
2728 i40e_fcoe_free_ddp_resources(vsi);
2729#endif
41c445ff
JB		 2730}
2731
3ffa037d
NP		 2732/**
2733 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2734 * @ring: The Tx ring to configure
2735 *
2736 * This enables/disables XPS for a given Tx descriptor ring
2737 * based on the TCs enabled for the VSI that ring belongs to.
2738 **/
2739static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2740{
2741 struct i40e_vsi *vsi = ring->vsi;
2742 cpumask_var_t mask;
2743
9a660eea
JB		 2744 if (!ring->q_vector || !ring->netdev)
2745 return;
2746
2747 /* Single TC mode enable XPS */
2748 if (vsi->tc_config.numtc <= 1) {
2749 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2750 netif_set_xps_queue(ring->netdev,
2751 &ring->q_vector->affinity_mask,
2752 ring->queue_index);
9a660eea
JB		 2753 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2754 /* Disable XPS to allow selection based on TC */
2755 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2756 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2757 free_cpumask_var(mask);
3ffa037d 2758 }
0e4425ed
JB		 2759
2760 /* schedule our worker thread which will take care of
2761 * applying the new filter changes
2762 */
2763 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2764}
2765
41c445ff
JB		 2766/**
2767 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2768 * @ring: The Tx ring to configure
2769 *
2770 * Configure the Tx descriptor ring in the HMC context.
2771 **/
2772static int i40e_configure_tx_ring(struct i40e_ring *ring)
2773{
2774 struct i40e_vsi *vsi = ring->vsi;
2775 u16 pf_q = vsi->base_queue + ring->queue_index;
2776 struct i40e_hw *hw = &vsi->back->hw;
2777 struct i40e_hmc_obj_txq tx_ctx;
2778 i40e_status err = 0;
2779 u32 qtx_ctl = 0;
2780
2781 /* some ATR related tx ring init */
60ea5f83 2782 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2783 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2784 ring->atr_count = 0;
2785 } else {
2786 ring->atr_sample_rate = 0;
2787 }
2788
3ffa037d
NP		 2789 /* configure XPS */
2790 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2791
2792 /* clear the context structure first */
2793 memset(&tx_ctx, 0, sizeof(tx_ctx));
2794
2795 tx_ctx.new_context = 1;
2796 tx_ctx.base = (ring->dma / 128);
2797 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2798 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2799 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2800#ifdef I40E_FCOE
2801 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2802#endif
beb0dff1 2803 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2804 /* FDIR VSI tx ring can still use RS bit and writebacks */
2805 if (vsi->type != I40E_VSI_FDIR)
2806 tx_ctx.head_wb_ena = 1;
2807 tx_ctx.head_wb_addr = ring->dma +
2808 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2809
2810 /* As part of VSI creation/update, FW allocates certain
2811 * Tx arbitration queue sets for each TC enabled for
2812 * the VSI. The FW returns the handles to these queue
2813 * sets as part of the response buffer to Add VSI,
2814 * Update VSI, etc. AQ commands. It is expected that
2815 * these queue set handles be associated with the Tx
2816 * queues by the driver as part of the TX queue context
2817 * initialization. This has to be done regardless of
2818 * DCB as by default everything is mapped to TC0.
2819 */
2820 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2821 tx_ctx.rdylist_act = 0;
2822
2823 /* clear the context in the HMC */
2824 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2825 if (err) {
2826 dev_info(&vsi->back->pdev->dev,
2827 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2828 ring->queue_index, pf_q, err);
2829 return -ENOMEM;
2830 }
2831
2832 /* set the context in the HMC */
2833 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2834 if (err) {
2835 dev_info(&vsi->back->pdev->dev,
2836 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2837 ring->queue_index, pf_q, err);
2838 return -ENOMEM;
2839 }
2840
2841 /* Now associate this queue with this PCI function */
7a28d885 2842 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2843 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2844 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2845 I40E_QTX_CTL_VFVM_INDX_MASK;
2846 } else {
9d8bf547 2847 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2848 }
2849
13fd9774
SN		 2850 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2851 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2852 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2853 i40e_flush(hw);
2854
41c445ff
JB		 2855 /* cache tail off for easier writes later */
2856 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2857
2858 return 0;
2859}
2860
2861/**
2862 * i40e_configure_rx_ring - Configure a receive ring context
2863 * @ring: The Rx ring to configure
2864 *
2865 * Configure the Rx descriptor ring in the HMC context.
2866 **/
2867static int i40e_configure_rx_ring(struct i40e_ring *ring)
2868{
2869 struct i40e_vsi *vsi = ring->vsi;
2870 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2871 u16 pf_q = vsi->base_queue + ring->queue_index;
2872 struct i40e_hw *hw = &vsi->back->hw;
2873 struct i40e_hmc_obj_rxq rx_ctx;
2874 i40e_status err = 0;
2875
2876 ring->state = 0;
2877
2878 /* clear the context structure first */
2879 memset(&rx_ctx, 0, sizeof(rx_ctx));
2880
2881 ring->rx_buf_len = vsi->rx_buf_len;
41c445ff
JB		 2882
2883 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
41c445ff
JB		 2884
2885 rx_ctx.base = (ring->dma / 128);
2886 rx_ctx.qlen = ring->count;
2887
bec60fc4
JB		 2888 /* use 32 byte descriptors */
2889 rx_ctx.dsize = 1;
41c445ff 2890
bec60fc4
JB		 2891 /* descriptor type is always zero
2892 * rx_ctx.dtype = 0;
2893 */
b32bfa17 2894 rx_ctx.hsplit_0 = 0;
41c445ff 2895
b32bfa17 2896 rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len);
7134f9ce
JB		 2897 if (hw->revision_id == 0)
2898 rx_ctx.lrxqthresh = 0;
2899 else
2900 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2901 rx_ctx.crcstrip = 1;
2902 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2903 /* this controls whether VLAN is stripped from inner headers */
2904 rx_ctx.showiv = 0;
38e00438
VD		 2905#ifdef I40E_FCOE
2906 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2907#endif
acb3676b
CS		 2908 /* set the prefena field to 1 because the manual says to */
2909 rx_ctx.prefena = 1;
41c445ff
JB		 2910
2911 /* clear the context in the HMC */
2912 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2913 if (err) {
2914 dev_info(&vsi->back->pdev->dev,
2915 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2916 ring->queue_index, pf_q, err);
2917 return -ENOMEM;
2918 }
2919
2920 /* set the context in the HMC */
2921 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2922 if (err) {
2923 dev_info(&vsi->back->pdev->dev,
2924 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2925 ring->queue_index, pf_q, err);
2926 return -ENOMEM;
2927 }
2928
2929 /* cache tail for quicker writes, and clear the reg before use */
2930 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2931 writel(0, ring->tail);
2932
1a557afc 2933 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
41c445ff
JB		 2934
2935 return 0;
2936}
2937
2938/**
2939 * i40e_vsi_configure_tx - Configure the VSI for Tx
2940 * @vsi: VSI structure describing this set of rings and resources
2941 *
2942 * Configure the Tx VSI for operation.
2943 **/
2944static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2945{
2946 int err = 0;
2947 u16 i;
2948
9f65e15b
AD		 2949 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2950 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2951
2952 return err;
2953}
2954
2955/**
2956 * i40e_vsi_configure_rx - Configure the VSI for Rx
2957 * @vsi: the VSI being configured
2958 *
2959 * Configure the Rx VSI for operation.
2960 **/
2961static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2962{
2963 int err = 0;
2964 u16 i;
2965
2966 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2967 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2968 + ETH_FCS_LEN + VLAN_HLEN;
2969 else
2970 vsi->max_frame = I40E_RXBUFFER_2048;
2971
1a557afc 2972 vsi->rx_buf_len = I40E_RXBUFFER_2048;
41c445ff 2973
38e00438
VD		 2974#ifdef I40E_FCOE
2975 /* setup rx buffer for FCoE */
2976 if ((vsi->type == I40E_VSI_FCOE) &&
2977 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
38e00438
VD		 2978 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2979 vsi->max_frame = I40E_RXBUFFER_3072;
38e00438
VD		 2980 }
2981
2982#endif /* I40E_FCOE */
41c445ff 2983 /* round up for the chip's needs */
41c445ff 2984 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2985 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2986
2987 /* set up individual rings */
2988 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2989 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2990
2991 return err;
2992}
2993
2994/**
2995 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2996 * @vsi: ptr to the VSI
2997 **/
2998static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2999{
e7046ee1 3000 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 3001 u16 qoffset, qcount;
3002 int i, n;
3003
cd238a3e
PN		 3004 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
3005 /* Reset the TC information */
3006 for (i = 0; i < vsi->num_queue_pairs; i++) {
3007 rx_ring = vsi->rx_rings[i];
3008 tx_ring = vsi->tx_rings[i];
3009 rx_ring->dcb_tc = 0;
3010 tx_ring->dcb_tc = 0;
3011 }
3012 }
41c445ff
JB		 3013
3014 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 3015 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 3016 continue;
3017
3018 qoffset = vsi->tc_config.tc_info[n].qoffset;
3019 qcount = vsi->tc_config.tc_info[n].qcount;
3020 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 3021 rx_ring = vsi->rx_rings[i];
3022 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 3023 rx_ring->dcb_tc = n;
3024 tx_ring->dcb_tc = n;
3025 }
3026 }
3027}
3028
3029/**
3030 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
3031 * @vsi: ptr to the VSI
3032 **/
3033static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3034{
3035 if (vsi->netdev)
3036 i40e_set_rx_mode(vsi->netdev);
3037}
3038
17a73f6b
JG		 3039/**
3040 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
3041 * @vsi: Pointer to the targeted VSI
3042 *
3043 * This function replays the hlist on the hw where all the SB Flow Director
3044 * filters were saved.
3045 **/
3046static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3047{
3048 struct i40e_fdir_filter *filter;
3049 struct i40e_pf *pf = vsi->back;
3050 struct hlist_node *node;
3051
55a5e60b
ASJ		 3052 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3053 return;
3054
17a73f6b
JG		 3055 hlist_for_each_entry_safe(filter, node,
3056 &pf->fdir_filter_list, fdir_node) {
3057 i40e_add_del_fdir(vsi, filter, true);
3058 }
3059}
3060
41c445ff
JB		 3061/**
3062 * i40e_vsi_configure - Set up the VSI for action
3063 * @vsi: the VSI being configured
3064 **/
3065static int i40e_vsi_configure(struct i40e_vsi *vsi)
3066{
3067 int err;
3068
3069 i40e_set_vsi_rx_mode(vsi);
3070 i40e_restore_vlan(vsi);
3071 i40e_vsi_config_dcb_rings(vsi);
3072 err = i40e_vsi_configure_tx(vsi);
3073 if (!err)
3074 err = i40e_vsi_configure_rx(vsi);
3075
3076 return err;
3077}
3078
3079/**
3080 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3081 * @vsi: the VSI being configured
3082 **/
3083static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3084{
3085 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3086 struct i40e_hw *hw = &pf->hw;
3087 u16 vector;
3088 int i, q;
41c445ff
JB		 3089 u32 qp;
3090
3091 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3092 * and PFINT_LNKLSTn registers, e.g.:
3093 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3094 */
3095 qp = vsi->base_queue;
3096 vector = vsi->base_vector;
493fb300 3097 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3098 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3099
ee2319cf 3100 q_vector->itr_countdown = ITR_COUNTDOWN_START;
a75e8005 3101 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[i]->rx_itr_setting);
41c445ff
JB		 3102 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3103 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3104 q_vector->rx.itr);
a75e8005 3105 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[i]->tx_itr_setting);
41c445ff
JB		 3106 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3107 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3108 q_vector->tx.itr);
ac26fc13
JB		 3109 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3110 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3111
3112 /* Linked list for the queuepairs assigned to this vector */
3113 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3114 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3115 u32 val;
3116
41c445ff
JB		 3117 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3118 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3119 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3120 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3121 (I40E_QUEUE_TYPE_TX
3122 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3123
3124 wr32(hw, I40E_QINT_RQCTL(qp), val);
3125
3126 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3127 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3128 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3129 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3130 (I40E_QUEUE_TYPE_RX
3131 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3132
3133 /* Terminate the linked list */
3134 if (q == (q_vector->num_ringpairs - 1))
3135 val |= (I40E_QUEUE_END_OF_LIST
3136 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3137
3138 wr32(hw, I40E_QINT_TQCTL(qp), val);
3139 qp++;
3140 }
3141 }
3142
3143 i40e_flush(hw);
3144}
3145
3146/**
3147 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3148 * @hw: ptr to the hardware info
3149 **/
ab437b5a 3150static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3151{
ab437b5a 3152 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3153 u32 val;
3154
3155 /* clear things first */
3156 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3157 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3158
3159 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3160 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3161 I40E_PFINT_ICR0_ENA_GRST_MASK |
3162 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3163 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3164 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3165 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3166 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3167
0d8e1439
ASJ		 3168 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3169 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3170
ab437b5a
JK		 3171 if (pf->flags & I40E_FLAG_PTP)
3172 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3173
41c445ff
JB		 3174 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3175
3176 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3177 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3178 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3179
3180 /* OTHER_ITR_IDX = 0 */
3181 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3182}
3183
3184/**
3185 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3186 * @vsi: the VSI being configured
3187 **/
3188static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3189{
493fb300 3190 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3191 struct i40e_pf *pf = vsi->back;
3192 struct i40e_hw *hw = &pf->hw;
3193 u32 val;
3194
3195 /* set the ITR configuration */
ee2319cf 3196 q_vector->itr_countdown = ITR_COUNTDOWN_START;
a75e8005 3197 q_vector->rx.itr = ITR_TO_REG(vsi->rx_rings[0]->rx_itr_setting);
41c445ff
JB		 3198 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3199 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
a75e8005 3200 q_vector->tx.itr = ITR_TO_REG(vsi->tx_rings[0]->tx_itr_setting);
41c445ff
JB		 3201 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3202 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3203
ab437b5a 3204 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3205
3206 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3207 wr32(hw, I40E_PFINT_LNKLST0, 0);
3208
f29eaa3d 3209 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3210 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3211 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3212 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3213
3214 wr32(hw, I40E_QINT_RQCTL(0), val);
3215
3216 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3217 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3218 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3219
3220 wr32(hw, I40E_QINT_TQCTL(0), val);
3221 i40e_flush(hw);
3222}
3223
2ef28cfb
MW		 3224/**
3225 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3226 * @pf: board private structure
3227 **/
3228void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3229{
3230 struct i40e_hw *hw = &pf->hw;
3231
3232 wr32(hw, I40E_PFINT_DYN_CTL0,
3233 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3234 i40e_flush(hw);
3235}
3236
41c445ff
JB		 3237/**
3238 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3239 * @pf: board private structure
40d72a50 3240 * @clearpba: true when all pending interrupt events should be cleared
41c445ff 3241 **/
40d72a50 3242void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba)
41c445ff
JB		 3243{
3244 struct i40e_hw *hw = &pf->hw;
3245 u32 val;
3246
3247 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
40d72a50 3248 (clearpba ? I40E_PFINT_DYN_CTL0_CLEARPBA_MASK : 0) |
41c445ff
JB		 3249 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3250
3251 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3252 i40e_flush(hw);
3253}
3254
41c445ff
JB		 3255/**
3256 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3257 * @irq: interrupt number
3258 * @data: pointer to a q_vector
3259 **/
3260static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3261{
3262 struct i40e_q_vector *q_vector = data;
3263
cd0b6fa6 3264 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3265 return IRQ_HANDLED;
3266
5d3465a1 3267 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3268
3269 return IRQ_HANDLED;
3270}
3271
41c445ff
JB		 3272/**
3273 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3274 * @vsi: the VSI being configured
3275 * @basename: name for the vector
3276 *
3277 * Allocates MSI-X vectors and requests interrupts from the kernel.
3278 **/
3279static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3280{
3281 int q_vectors = vsi->num_q_vectors;
3282 struct i40e_pf *pf = vsi->back;
3283 int base = vsi->base_vector;
3284 int rx_int_idx = 0;
3285 int tx_int_idx = 0;
3286 int vector, err;
3287
3288 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3289 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3290
cd0b6fa6 3291 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3292 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3293 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3294 tx_int_idx++;
cd0b6fa6 3295 } else if (q_vector->rx.ring) {
41c445ff
JB		 3296 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3297 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3298 } else if (q_vector->tx.ring) {
41c445ff
JB		 3299 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3300 "%s-%s-%d", basename, "tx", tx_int_idx++);
3301 } else {
3302 /* skip this unused q_vector */
3303 continue;
3304 }
3305 err = request_irq(pf->msix_entries[base + vector].vector,
3306 vsi->irq_handler,
3307 0,
3308 q_vector->name,
3309 q_vector);
3310 if (err) {
3311 dev_info(&pf->pdev->dev,
fb43201f 3312 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3313 goto free_queue_irqs;
3314 }
3315 /* assign the mask for this irq */
3316 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3317 &q_vector->affinity_mask);
3318 }
3319
63741846 3320 vsi->irqs_ready = true;
41c445ff
JB		 3321 return 0;
3322
3323free_queue_irqs:
3324 while (vector) {
3325 vector--;
3326 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3327 NULL);
3328 free_irq(pf->msix_entries[base + vector].vector,
3329 &(vsi->q_vectors[vector]));
3330 }
3331 return err;
3332}
3333
3334/**
3335 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3336 * @vsi: the VSI being un-configured
3337 **/
3338static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3339{
3340 struct i40e_pf *pf = vsi->back;
3341 struct i40e_hw *hw = &pf->hw;
3342 int base = vsi->base_vector;
3343 int i;
3344
3345 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3346 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3347 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3348 }
3349
3350 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3351 for (i = vsi->base_vector;
3352 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3353 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3354
3355 i40e_flush(hw);
3356 for (i = 0; i < vsi->num_q_vectors; i++)
3357 synchronize_irq(pf->msix_entries[i + base].vector);
3358 } else {
3359 /* Legacy and MSI mode - this stops all interrupt handling */
3360 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3361 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3362 i40e_flush(hw);
3363 synchronize_irq(pf->pdev->irq);
3364 }
3365}
3366
3367/**
3368 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3369 * @vsi: the VSI being configured
3370 **/
3371static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3372{
3373 struct i40e_pf *pf = vsi->back;
3374 int i;
3375
3376 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3377 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3378 i40e_irq_dynamic_enable(vsi, i);
3379 } else {
40d72a50 3380 i40e_irq_dynamic_enable_icr0(pf, true);
41c445ff
JB		 3381 }
3382
1022cb6c 3383 i40e_flush(&pf->hw);
41c445ff
JB		 3384 return 0;
3385}
3386
3387/**
3388 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3389 * @pf: board private structure
3390 **/
3391static void i40e_stop_misc_vector(struct i40e_pf *pf)
3392{
3393 /* Disable ICR 0 */
3394 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3395 i40e_flush(&pf->hw);
3396}
3397
3398/**
3399 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3400 * @irq: interrupt number
3401 * @data: pointer to a q_vector
3402 *
3403 * This is the handler used for all MSI/Legacy interrupts, and deals
3404 * with both queue and non-queue interrupts. This is also used in
3405 * MSIX mode to handle the non-queue interrupts.
3406 **/
3407static irqreturn_t i40e_intr(int irq, void *data)
3408{
3409 struct i40e_pf *pf = (struct i40e_pf *)data;
3410 struct i40e_hw *hw = &pf->hw;
5e823066 3411 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3412 u32 icr0, icr0_remaining;
3413 u32 val, ena_mask;
3414
3415 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3416 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3417
116a57d4
SN		 3418 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3419 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3420 goto enable_intr;
41c445ff 3421
cd92e72f
SN		 3422 /* if interrupt but no bits showing, must be SWINT */
3423 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3424 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3425 pf->sw_int_count++;
3426
0d8e1439
ASJ		 3427 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3428 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3429 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3430 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3431 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3432 }
3433
41c445ff
JB		 3434 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3435 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3436 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3437 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff 3438
a16ae2d5
ASJ		 3439 /* We do not have a way to disarm Queue causes while leaving
3440 * interrupt enabled for all other causes, ideally
3441 * interrupt should be disabled while we are in NAPI but
3442 * this is not a performance path and napi_schedule()
3443 * can deal with rescheduling.
3444 */
41c445ff 3445 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3446 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3447 }
3448
3449 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3450 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3451 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6e93d0c9 3452 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n");
41c445ff
JB		 3453 }
3454
3455 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3456 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3457 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3458 }
3459
3460 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3461 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3462 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3463 }
3464
3465 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3466 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3467 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3468 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3469 val = rd32(hw, I40E_GLGEN_RSTAT);
3470 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3471 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3472 if (val == I40E_RESET_CORER) {
41c445ff 3473 pf->corer_count++;
4eb3f768 3474 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3475 pf->globr_count++;
4eb3f768 3476 } else if (val == I40E_RESET_EMPR) {
41c445ff 3477 pf->empr_count++;
9df42d1a 3478 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3479 }
41c445ff
JB		 3480 }
3481
9c010ee0
ASJ		 3482 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3483 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3484 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3485 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3486 rd32(hw, I40E_PFHMC_ERRORINFO),
3487 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3488 }
3489
beb0dff1
JK		 3490 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3491 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3492
3493 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3494 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3495 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3496 }
beb0dff1
JK		 3497 }
3498
41c445ff
JB		 3499 /* If a critical error is pending we have no choice but to reset the
3500 * device.
3501 * Report and mask out any remaining unexpected interrupts.
3502 */
3503 icr0_remaining = icr0 & ena_mask;
3504 if (icr0_remaining) {
3505 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3506 icr0_remaining);
9c010ee0 3507 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3508 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3509 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3510 dev_info(&pf->pdev->dev, "device will be reset\n");
3511 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3512 i40e_service_event_schedule(pf);
41c445ff
JB		 3513 }
3514 ena_mask &= ~icr0_remaining;
3515 }
5e823066 3516 ret = IRQ_HANDLED;
41c445ff 3517
5e823066 3518enable_intr:
41c445ff
JB		 3519 /* re-enable interrupt causes */
3520 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3521 if (!test_bit(__I40E_DOWN, &pf->state)) {
3522 i40e_service_event_schedule(pf);
40d72a50 3523 i40e_irq_dynamic_enable_icr0(pf, false);
41c445ff
JB		 3524 }
3525
5e823066 3526 return ret;
41c445ff
JB		 3527}
3528
cbf61325
ASJ		 3529/**
3530 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3531 * @tx_ring: tx ring to clean
3532 * @budget: how many cleans we're allowed
3533 *
3534 * Returns true if there's any budget left (e.g. the clean is finished)
3535 **/
3536static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3537{
3538 struct i40e_vsi *vsi = tx_ring->vsi;
3539 u16 i = tx_ring->next_to_clean;
3540 struct i40e_tx_buffer *tx_buf;
3541 struct i40e_tx_desc *tx_desc;
3542
3543 tx_buf = &tx_ring->tx_bi[i];
3544 tx_desc = I40E_TX_DESC(tx_ring, i);
3545 i -= tx_ring->count;
3546
3547 do {
3548 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3549
3550 /* if next_to_watch is not set then there is no work pending */
3551 if (!eop_desc)
3552 break;
3553
3554 /* prevent any other reads prior to eop_desc */
3555 read_barrier_depends();
3556
3557 /* if the descriptor isn't done, no work yet to do */
3558 if (!(eop_desc->cmd_type_offset_bsz &
3559 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3560 break;
3561
3562 /* clear next_to_watch to prevent false hangs */
3563 tx_buf->next_to_watch = NULL;
3564
49d7d933
ASJ		 3565 tx_desc->buffer_addr = 0;
3566 tx_desc->cmd_type_offset_bsz = 0;
3567 /* move past filter desc */
3568 tx_buf++;
3569 tx_desc++;
3570 i++;
3571 if (unlikely(!i)) {
3572 i -= tx_ring->count;
3573 tx_buf = tx_ring->tx_bi;
3574 tx_desc = I40E_TX_DESC(tx_ring, 0);
3575 }
cbf61325
ASJ		 3576 /* unmap skb header data */
3577 dma_unmap_single(tx_ring->dev,
3578 dma_unmap_addr(tx_buf, dma),
3579 dma_unmap_len(tx_buf, len),
3580 DMA_TO_DEVICE);
49d7d933
ASJ		 3581 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3582 kfree(tx_buf->raw_buf);
cbf61325 3583
49d7d933
ASJ		 3584 tx_buf->raw_buf = NULL;
3585 tx_buf->tx_flags = 0;
3586 tx_buf->next_to_watch = NULL;
cbf61325 3587 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3588 tx_desc->buffer_addr = 0;
3589 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3590
49d7d933 3591 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3592 tx_buf++;
3593 tx_desc++;
3594 i++;
3595 if (unlikely(!i)) {
3596 i -= tx_ring->count;
3597 tx_buf = tx_ring->tx_bi;
3598 tx_desc = I40E_TX_DESC(tx_ring, 0);
3599 }
3600
3601 /* update budget accounting */
3602 budget--;
3603 } while (likely(budget));
3604
3605 i += tx_ring->count;
3606 tx_ring->next_to_clean = i;
3607
6995b36c 3608 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3609 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3610
cbf61325
ASJ		 3611 return budget > 0;
3612}
3613
3614/**
3615 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3616 * @irq: interrupt number
3617 * @data: pointer to a q_vector
3618 **/
3619static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3620{
3621 struct i40e_q_vector *q_vector = data;
3622 struct i40e_vsi *vsi;
3623
3624 if (!q_vector->tx.ring)
3625 return IRQ_HANDLED;
3626
3627 vsi = q_vector->tx.ring->vsi;
3628 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3629
3630 return IRQ_HANDLED;
3631}
3632
41c445ff 3633/**
cd0b6fa6 3634 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3635 * @vsi: the VSI being configured
3636 * @v_idx: vector index
cd0b6fa6 3637 * @qp_idx: queue pair index
41c445ff 3638 **/
26cdc443 3639static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3640{
493fb300 3641 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3642 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3643 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3644
3645 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3646 tx_ring->next = q_vector->tx.ring;
3647 q_vector->tx.ring = tx_ring;
41c445ff 3648 q_vector->tx.count++;
cd0b6fa6
AD		 3649
3650 rx_ring->q_vector = q_vector;
3651 rx_ring->next = q_vector->rx.ring;
3652 q_vector->rx.ring = rx_ring;
3653 q_vector->rx.count++;
41c445ff
JB		 3654}
3655
3656/**
3657 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3658 * @vsi: the VSI being configured
3659 *
3660 * This function maps descriptor rings to the queue-specific vectors
3661 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3662 * one vector per queue pair, but on a constrained vector budget, we
3663 * group the queue pairs as "efficiently" as possible.
3664 **/
3665static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3666{
3667 int qp_remaining = vsi->num_queue_pairs;
3668 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3669 int num_ringpairs;
41c445ff
JB		 3670 int v_start = 0;
3671 int qp_idx = 0;
3672
3673 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3674 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3675 * It is also important to go through all the vectors available to be
3676 * sure that if we don't use all the vectors, that the remaining vectors
3677 * are cleared. This is especially important when decreasing the
3678 * number of queues in use.
41c445ff 3679 */
70114ec4 3680 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3681 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3682
3683 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3684
3685 q_vector->num_ringpairs = num_ringpairs;
3686
3687 q_vector->rx.count = 0;
3688 q_vector->tx.count = 0;
3689 q_vector->rx.ring = NULL;
3690 q_vector->tx.ring = NULL;
3691
3692 while (num_ringpairs--) {
26cdc443 3693 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3694 qp_idx++;
3695 qp_remaining--;
41c445ff
JB		 3696 }
3697 }
3698}
3699
3700/**
3701 * i40e_vsi_request_irq - Request IRQ from the OS
3702 * @vsi: the VSI being configured
3703 * @basename: name for the vector
3704 **/
3705static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3706{
3707 struct i40e_pf *pf = vsi->back;
3708 int err;
3709
3710 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3711 err = i40e_vsi_request_irq_msix(vsi, basename);
3712 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3713 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3714 pf->int_name, pf);
41c445ff
JB		 3715 else
3716 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3717 pf->int_name, pf);
41c445ff
JB		 3718
3719 if (err)
3720 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3721
3722 return err;
3723}
3724
3725#ifdef CONFIG_NET_POLL_CONTROLLER
3726/**
d89d967f 3727 * i40e_netpoll - A Polling 'interrupt' handler
41c445ff
JB		 3728 * @netdev: network interface device structure
3729 *
3730 * This is used by netconsole to send skbs without having to re-enable
3731 * interrupts. It's not called while the normal interrupt routine is executing.
3732 **/
38e00438
VD		 3733#ifdef I40E_FCOE
3734void i40e_netpoll(struct net_device *netdev)
3735#else
41c445ff 3736static void i40e_netpoll(struct net_device *netdev)
38e00438 3737#endif
41c445ff
JB		 3738{
3739 struct i40e_netdev_priv *np = netdev_priv(netdev);
3740 struct i40e_vsi *vsi = np->vsi;
3741 struct i40e_pf *pf = vsi->back;
3742 int i;
3743
3744 /* if interface is down do nothing */
3745 if (test_bit(__I40E_DOWN, &vsi->state))
3746 return;
3747
41c445ff
JB		 3748 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3749 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3750 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3751 } else {
3752 i40e_intr(pf->pdev->irq, netdev);
3753 }
41c445ff
JB		 3754}
3755#endif
3756
23527308
NP		 3757/**
3758 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3759 * @pf: the PF being configured
3760 * @pf_q: the PF queue
3761 * @enable: enable or disable state of the queue
3762 *
3763 * This routine will wait for the given Tx queue of the PF to reach the
3764 * enabled or disabled state.
3765 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3766 * multiple retries; else will return 0 in case of success.
3767 **/
3768static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3769{
3770 int i;
3771 u32 tx_reg;
3772
3773 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3774 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3775 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3776 break;
3777
f98a2006 3778 usleep_range(10, 20);
23527308
NP		 3779 }
3780 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3781 return -ETIMEDOUT;
3782
3783 return 0;
3784}
3785
41c445ff
JB		 3786/**
3787 * i40e_vsi_control_tx - Start or stop a VSI's rings
3788 * @vsi: the VSI being configured
3789 * @enable: start or stop the rings
3790 **/
3791static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3792{
3793 struct i40e_pf *pf = vsi->back;
3794 struct i40e_hw *hw = &pf->hw;
23527308 3795 int i, j, pf_q, ret = 0;
41c445ff
JB		 3796 u32 tx_reg;
3797
3798 pf_q = vsi->base_queue;
3799 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3800
3801 /* warn the TX unit of coming changes */
3802 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3803 if (!enable)
f98a2006 3804 usleep_range(10, 20);
351499ab 3805
6c5ef620 3806 for (j = 0; j < 50; j++) {
41c445ff 3807 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3808 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3809 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3810 break;
3811 usleep_range(1000, 2000);
3812 }
fda972f6 3813 /* Skip if the queue is already in the requested state */
7c122007 3814 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3815 continue;
41c445ff
JB		 3816
3817 /* turn on/off the queue */
c5c9eb9e
SN		 3818 if (enable) {
3819 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3820 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3821 } else {
41c445ff 3822 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3823 }
41c445ff
JB		 3824
3825 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3826 /* No waiting for the Tx queue to disable */
3827 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3828 continue;
41c445ff
JB		 3829
3830 /* wait for the change to finish */
23527308
NP		 3831 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3832 if (ret) {
3833 dev_info(&pf->pdev->dev,
fb43201f
SN		 3834 "VSI seid %d Tx ring %d %sable timeout\n",
3835 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3836 break;
41c445ff
JB		 3837 }
3838 }
3839
7134f9ce
JB		 3840 if (hw->revision_id == 0)
3841 mdelay(50);
23527308
NP		 3842 return ret;
3843}
3844
3845/**
3846 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3847 * @pf: the PF being configured
3848 * @pf_q: the PF queue
3849 * @enable: enable or disable state of the queue
3850 *
3851 * This routine will wait for the given Rx queue of the PF to reach the
3852 * enabled or disabled state.
3853 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3854 * multiple retries; else will return 0 in case of success.
3855 **/
3856static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3857{
3858 int i;
3859 u32 rx_reg;
3860
3861 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3862 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3863 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3864 break;
3865
f98a2006 3866 usleep_range(10, 20);
23527308
NP		 3867 }
3868 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3869 return -ETIMEDOUT;
7134f9ce 3870
41c445ff
JB		 3871 return 0;
3872}
3873
3874/**
3875 * i40e_vsi_control_rx - Start or stop a VSI's rings
3876 * @vsi: the VSI being configured
3877 * @enable: start or stop the rings
3878 **/
3879static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3880{
3881 struct i40e_pf *pf = vsi->back;
3882 struct i40e_hw *hw = &pf->hw;
23527308 3883 int i, j, pf_q, ret = 0;
41c445ff
JB		 3884 u32 rx_reg;
3885
3886 pf_q = vsi->base_queue;
3887 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3888 for (j = 0; j < 50; j++) {
41c445ff 3889 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3890 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3891 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3892 break;
3893 usleep_range(1000, 2000);
3894 }
41c445ff 3895
7c122007
CS		 3896 /* Skip if the queue is already in the requested state */
3897 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3898 continue;
41c445ff
JB		 3899
3900 /* turn on/off the queue */
3901 if (enable)
6c5ef620 3902 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3903 else
6c5ef620 3904 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3905 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3fe06f41
NP		 3906 /* No waiting for the Tx queue to disable */
3907 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3908 continue;
41c445ff
JB		 3909
3910 /* wait for the change to finish */
23527308
NP		 3911 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3912 if (ret) {
3913 dev_info(&pf->pdev->dev,
fb43201f
SN		 3914 "VSI seid %d Rx ring %d %sable timeout\n",
3915 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3916 break;
41c445ff
JB		 3917 }
3918 }
3919
23527308 3920 return ret;
41c445ff
JB		 3921}
3922
3923/**
3924 * i40e_vsi_control_rings - Start or stop a VSI's rings
3925 * @vsi: the VSI being configured
3926 * @enable: start or stop the rings
3927 **/
fc18eaa0 3928int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3929{
3b867b28 3930 int ret = 0;
41c445ff
JB		 3931
3932 /* do rx first for enable and last for disable */
3933 if (request) {
3934 ret = i40e_vsi_control_rx(vsi, request);
3935 if (ret)
3936 return ret;
3937 ret = i40e_vsi_control_tx(vsi, request);
3938 } else {
3b867b28
ASJ		 3939 /* Ignore return value, we need to shutdown whatever we can */
3940 i40e_vsi_control_tx(vsi, request);
3941 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3942 }
3943
3944 return ret;
3945}
3946
3947/**
3948 * i40e_vsi_free_irq - Free the irq association with the OS
3949 * @vsi: the VSI being configured
3950 **/
3951static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3952{
3953 struct i40e_pf *pf = vsi->back;
3954 struct i40e_hw *hw = &pf->hw;
3955 int base = vsi->base_vector;
3956 u32 val, qp;
3957 int i;
3958
3959 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3960 if (!vsi->q_vectors)
3961 return;
3962
63741846
SN		 3963 if (!vsi->irqs_ready)
3964 return;
3965
3966 vsi->irqs_ready = false;
41c445ff
JB		 3967 for (i = 0; i < vsi->num_q_vectors; i++) {
3968 u16 vector = i + base;
3969
3970 /* free only the irqs that were actually requested */
78681b1f
SN		 3971 if (!vsi->q_vectors[i] ||
3972 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3973 continue;
3974
3975 /* clear the affinity_mask in the IRQ descriptor */
3976 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3977 NULL);
b33d3b73 3978 synchronize_irq(pf->msix_entries[vector].vector);
41c445ff 3979 free_irq(pf->msix_entries[vector].vector,
493fb300 3980 vsi->q_vectors[i]);
41c445ff
JB		 3981
3982 /* Tear down the interrupt queue link list
3983 *
3984 * We know that they come in pairs and always
3985 * the Rx first, then the Tx. To clear the
3986 * link list, stick the EOL value into the
3987 * next_q field of the registers.
3988 */
3989 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3990 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3991 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3992 val |= I40E_QUEUE_END_OF_LIST
3993 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3994 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3995
3996 while (qp != I40E_QUEUE_END_OF_LIST) {
3997 u32 next;
3998
3999 val = rd32(hw, I40E_QINT_RQCTL(qp));
4000
4001 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4002 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4003 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4004 I40E_QINT_RQCTL_INTEVENT_MASK);
4005
4006 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4007 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4008
4009 wr32(hw, I40E_QINT_RQCTL(qp), val);
4010
4011 val = rd32(hw, I40E_QINT_TQCTL(qp));
4012
4013 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4014 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4015
4016 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4017 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4018 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4019 I40E_QINT_TQCTL_INTEVENT_MASK);
4020
4021 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4022 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4023
4024 wr32(hw, I40E_QINT_TQCTL(qp), val);
4025 qp = next;
4026 }
4027 }
4028 } else {
4029 free_irq(pf->pdev->irq, pf);
4030
4031 val = rd32(hw, I40E_PFINT_LNKLST0);
4032 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4033 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4034 val |= I40E_QUEUE_END_OF_LIST
4035 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4036 wr32(hw, I40E_PFINT_LNKLST0, val);
4037
4038 val = rd32(hw, I40E_QINT_RQCTL(qp));
4039 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4040 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4041 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4042 I40E_QINT_RQCTL_INTEVENT_MASK);
4043
4044 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4045 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4046
4047 wr32(hw, I40E_QINT_RQCTL(qp), val);
4048
4049 val = rd32(hw, I40E_QINT_TQCTL(qp));
4050
4051 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4052 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4053 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4054 I40E_QINT_TQCTL_INTEVENT_MASK);
4055
4056 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4057 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4058
4059 wr32(hw, I40E_QINT_TQCTL(qp), val);
4060 }
4061}
4062
493fb300
AD		 4063/**
4064 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4065 * @vsi: the VSI being configured
4066 * @v_idx: Index of vector to be freed
4067 *
4068 * This function frees the memory allocated to the q_vector. In addition if
4069 * NAPI is enabled it will delete any references to the NAPI struct prior
4070 * to freeing the q_vector.
4071 **/
4072static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4073{
4074 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4075 struct i40e_ring *ring;
493fb300
AD		 4076
4077 if (!q_vector)
4078 return;
4079
4080 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4081 i40e_for_each_ring(ring, q_vector->tx)
4082 ring->q_vector = NULL;
4083
4084 i40e_for_each_ring(ring, q_vector->rx)
4085 ring->q_vector = NULL;
493fb300
AD		 4086
4087 /* only VSI w/ an associated netdev is set up w/ NAPI */
4088 if (vsi->netdev)
4089 netif_napi_del(&q_vector->napi);
4090
4091 vsi->q_vectors[v_idx] = NULL;
4092
4093 kfree_rcu(q_vector, rcu);
4094}
4095
41c445ff
JB		 4096/**
4097 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4098 * @vsi: the VSI being un-configured
4099 *
4100 * This frees the memory allocated to the q_vectors and
4101 * deletes references to the NAPI struct.
4102 **/
4103static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4104{
4105 int v_idx;
4106
493fb300
AD		 4107 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4108 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4109}
4110
4111/**
4112 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4113 * @pf: board private structure
4114 **/
4115static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4116{
4117 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4118 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4119 pci_disable_msix(pf->pdev);
4120 kfree(pf->msix_entries);
4121 pf->msix_entries = NULL;
3b444399
SN		 4122 kfree(pf->irq_pile);
4123 pf->irq_pile = NULL;
41c445ff
JB		 4124 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4125 pci_disable_msi(pf->pdev);
4126 }
4127 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4128}
4129
4130/**
4131 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4132 * @pf: board private structure
4133 *
4134 * We go through and clear interrupt specific resources and reset the structure
4135 * to pre-load conditions
4136 **/
4137static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4138{
4139 int i;
4140
e147758d 4141 i40e_stop_misc_vector(pf);
69278398 4142 if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) {
e147758d
SN		 4143 synchronize_irq(pf->msix_entries[0].vector);
4144 free_irq(pf->msix_entries[0].vector, pf);
4145 }
4146
e3219ce6
ASJ		 4147 i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector,
4148 I40E_IWARP_IRQ_PILE_ID);
4149
41c445ff 4150 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4151 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4152 if (pf->vsi[i])
4153 i40e_vsi_free_q_vectors(pf->vsi[i]);
4154 i40e_reset_interrupt_capability(pf);
4155}
4156
4157/**
4158 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4159 * @vsi: the VSI being configured
4160 **/
4161static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4162{
4163 int q_idx;
4164
4165 if (!vsi->netdev)
4166 return;
4167
4168 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4169 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4170}
4171
4172/**
4173 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4174 * @vsi: the VSI being configured
4175 **/
4176static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4177{
4178 int q_idx;
4179
4180 if (!vsi->netdev)
4181 return;
4182
4183 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4184 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4185}
4186
90ef8d47
SN		 4187/**
4188 * i40e_vsi_close - Shut down a VSI
4189 * @vsi: the vsi to be quelled
4190 **/
4191static void i40e_vsi_close(struct i40e_vsi *vsi)
4192{
e3219ce6
ASJ		 4193 bool reset = false;
4194
90ef8d47
SN		 4195 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4196 i40e_down(vsi);
4197 i40e_vsi_free_irq(vsi);
4198 i40e_vsi_free_tx_resources(vsi);
4199 i40e_vsi_free_rx_resources(vsi);
92faef85 4200 vsi->current_netdev_flags = 0;
e3219ce6
ASJ		 4201 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4202 reset = true;
4203 i40e_notify_client_of_netdev_close(vsi, reset);
90ef8d47
SN		 4204}
4205
41c445ff
JB		 4206/**
4207 * i40e_quiesce_vsi - Pause a given VSI
4208 * @vsi: the VSI being paused
4209 **/
4210static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4211{
4212 if (test_bit(__I40E_DOWN, &vsi->state))
4213 return;
4214
d341b7a5
NP		 4215 /* No need to disable FCoE VSI when Tx suspended */
4216 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4217 vsi->type == I40E_VSI_FCOE) {
4218 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4219 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4220 return;
4221 }
4222
41c445ff 4223 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4224 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4225 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4226 else
90ef8d47 4227 i40e_vsi_close(vsi);
41c445ff
JB		 4228}
4229
4230/**
4231 * i40e_unquiesce_vsi - Resume a given VSI
4232 * @vsi: the VSI being resumed
4233 **/
4234static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4235{
4236 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4237 return;
4238
4239 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4240 if (vsi->netdev && netif_running(vsi->netdev))
4241 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4242 else
8276f757 4243 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4244}
4245
4246/**
4247 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4248 * @pf: the PF
4249 **/
4250static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4251{
4252 int v;
4253
505682cd 4254 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4255 if (pf->vsi[v])
4256 i40e_quiesce_vsi(pf->vsi[v]);
4257 }
4258}
4259
4260/**
4261 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4262 * @pf: the PF
4263 **/
4264static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4265{
4266 int v;
4267
505682cd 4268 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4269 if (pf->vsi[v])
4270 i40e_unquiesce_vsi(pf->vsi[v]);
4271 }
4272}
4273
69129dc3
NP		 4274#ifdef CONFIG_I40E_DCB
4275/**
3fe06f41 4276 * i40e_vsi_wait_queues_disabled - Wait for VSI's queues to be disabled
69129dc3
NP		 4277 * @vsi: the VSI being configured
4278 *
3fe06f41 4279 * This function waits for the given VSI's queues to be disabled.
69129dc3 4280 **/
3fe06f41 4281static int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi)
69129dc3
NP		 4282{
4283 struct i40e_pf *pf = vsi->back;
4284 int i, pf_q, ret;
4285
4286 pf_q = vsi->base_queue;
4287 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4288 /* Check and wait for the disable status of the queue */
4289 ret = i40e_pf_txq_wait(pf, pf_q, false);
4290 if (ret) {
4291 dev_info(&pf->pdev->dev,
fb43201f
SN		 4292 "VSI seid %d Tx ring %d disable timeout\n",
4293 vsi->seid, pf_q);
69129dc3
NP		 4294 return ret;
4295 }
4296 }
4297
3fe06f41
NP		 4298 pf_q = vsi->base_queue;
4299 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4300 /* Check and wait for the disable status of the queue */
4301 ret = i40e_pf_rxq_wait(pf, pf_q, false);
4302 if (ret) {
4303 dev_info(&pf->pdev->dev,
4304 "VSI seid %d Rx ring %d disable timeout\n",
4305 vsi->seid, pf_q);
4306 return ret;
4307 }
4308 }
4309
69129dc3
NP		 4310 return 0;
4311}
4312
4313/**
3fe06f41 4314 * i40e_pf_wait_queues_disabled - Wait for all queues of PF VSIs to be disabled
69129dc3
NP		 4315 * @pf: the PF
4316 *
3fe06f41 4317 * This function waits for the queues to be in disabled state for all the
69129dc3
NP		 4318 * VSIs that are managed by this PF.
4319 **/
3fe06f41 4320static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf)
69129dc3
NP		 4321{
4322 int v, ret = 0;
4323
4324 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4325 /* No need to wait for FCoE VSI queues */
4326 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
3fe06f41 4327 ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]);
69129dc3
NP		 4328 if (ret)
4329 break;
4330 }
4331 }
4332
4333 return ret;
4334}
4335
4336#endif
b03a8c1f
KP		 4337
4338/**
4339 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4340 * @q_idx: TX queue number
4341 * @vsi: Pointer to VSI struct
4342 *
4343 * This function checks specified queue for given VSI. Detects hung condition.
4344 * Sets hung bit since it is two step process. Before next run of service task
4345 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4346 * hung condition remain unchanged and during subsequent run, this function
4347 * issues SW interrupt to recover from hung condition.
4348 **/
4349static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4350{
4351 struct i40e_ring *tx_ring = NULL;
4352 struct i40e_pf *pf;
dd353109 4353 u32 head, val, tx_pending_hw;
b03a8c1f
KP		 4354 int i;
4355
4356 pf = vsi->back;
4357
4358 /* now that we have an index, find the tx_ring struct */
4359 for (i = 0; i < vsi->num_queue_pairs; i++) {
4360 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4361 if (q_idx == vsi->tx_rings[i]->queue_index) {
4362 tx_ring = vsi->tx_rings[i];
4363 break;
4364 }
4365 }
4366 }
4367
4368 if (!tx_ring)
4369 return;
4370
4371 /* Read interrupt register */
4372 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4373 val = rd32(&pf->hw,
4374 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4375 tx_ring->vsi->base_vector - 1));
4376 else
4377 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4378
4379 head = i40e_get_head(tx_ring);
4380
dd353109 4381 tx_pending_hw = i40e_get_tx_pending(tx_ring, false);
b03a8c1f 4382
9c6c1259
KP		 4383 /* HW is done executing descriptors, updated HEAD write back,
4384 * but SW hasn't processed those descriptors. If interrupt is
4385 * not generated from this point ON, it could result into
4386 * dev_watchdog detecting timeout on those netdev_queue,
4387 * hence proactively trigger SW interrupt.
b03a8c1f 4388 */
dd353109 4389 if (tx_pending_hw && (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) {
9c6c1259
KP		 4390 /* NAPI Poll didn't run and clear since it was set */
4391 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT,
4392 &tx_ring->q_vector->hung_detected)) {
dd353109
ASJ		 4393 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending_hw: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n",
4394 vsi->seid, q_idx, tx_pending_hw,
9c6c1259
KP		 4395 tx_ring->next_to_clean, head,
4396 tx_ring->next_to_use,
4397 readl(tx_ring->tail));
4398 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n",
4399 vsi->seid, q_idx, val);
4400 i40e_force_wb(vsi, tx_ring->q_vector);
4401 } else {
4402 /* First Chance - detected possible hung */
4403 set_bit(I40E_Q_VECTOR_HUNG_DETECT,
4404 &tx_ring->q_vector->hung_detected);
4405 }
4406 }
dd353109
ASJ		 4407
4408 /* This is the case where we have interrupts missing,
4409 * so the tx_pending in HW will most likely be 0, but we
4410 * will have tx_pending in SW since the WB happened but the
4411 * interrupt got lost.
4412 */
4413 if ((!tx_pending_hw) && i40e_get_tx_pending(tx_ring, true) &&
4414 (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))) {
4415 if (napi_reschedule(&tx_ring->q_vector->napi))
4416 tx_ring->tx_stats.tx_lost_interrupt++;
4417 }
b03a8c1f
KP		 4418}
4419
4420/**
4421 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4422 * @pf: pointer to PF struct
4423 *
4424 * LAN VSI has netdev and netdev has TX queues. This function is to check
4425 * each of those TX queues if they are hung, trigger recovery by issuing
4426 * SW interrupt.
4427 **/
4428static void i40e_detect_recover_hung(struct i40e_pf *pf)
4429{
4430 struct net_device *netdev;
4431 struct i40e_vsi *vsi;
4432 int i;
4433
4434 /* Only for LAN VSI */
4435 vsi = pf->vsi[pf->lan_vsi];
4436
4437 if (!vsi)
4438 return;
4439
4440 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4441 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4442 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4443 return;
4444
4445 /* Make sure type is MAIN VSI */
4446 if (vsi->type != I40E_VSI_MAIN)
4447 return;
4448
4449 netdev = vsi->netdev;
4450 if (!netdev)
4451 return;
4452
4453 /* Bail out if netif_carrier is not OK */
4454 if (!netif_carrier_ok(netdev))
4455 return;
4456
4457 /* Go thru' TX queues for netdev */
4458 for (i = 0; i < netdev->num_tx_queues; i++) {
4459 struct netdev_queue *q;
4460
4461 q = netdev_get_tx_queue(netdev, i);
4462 if (q)
4463 i40e_detect_recover_hung_queue(i, vsi);
4464 }
4465}
4466
63d7e5a4
NP		 4467/**
4468 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4469 * @pf: pointer to PF
63d7e5a4
NP		 4470 *
4471 * Get TC map for ISCSI PF type that will include iSCSI TC
4472 * and LAN TC.
4473 **/
4474static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4475{
4476 struct i40e_dcb_app_priority_table app;
4477 struct i40e_hw *hw = &pf->hw;
4478 u8 enabled_tc = 1; /* TC0 is always enabled */
4479 u8 tc, i;
4480 /* Get the iSCSI APP TLV */
4481 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4482
4483 for (i = 0; i < dcbcfg->numapps; i++) {
4484 app = dcbcfg->app[i];
4485 if (app.selector == I40E_APP_SEL_TCPIP &&
4486 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4487 tc = dcbcfg->etscfg.prioritytable[app.priority];
75f5cea9 4488 enabled_tc |= BIT(tc);
63d7e5a4
NP		 4489 break;
4490 }
4491 }
4492
4493 return enabled_tc;
4494}
4495
41c445ff
JB		 4496/**
4497 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4498 * @dcbcfg: the corresponding DCBx configuration structure
4499 *
4500 * Return the number of TCs from given DCBx configuration
4501 **/
4502static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4503{
078b5876
JB		 4504 u8 num_tc = 0;
4505 int i;
41c445ff
JB		 4506
4507 /* Scan the ETS Config Priority Table to find
4508 * traffic class enabled for a given priority
4509 * and use the traffic class index to get the
4510 * number of traffic classes enabled
4511 */
4512 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4513 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4514 num_tc = dcbcfg->etscfg.prioritytable[i];
4515 }
4516
4517 /* Traffic class index starts from zero so
4518 * increment to return the actual count
4519 */
078b5876 4520 return num_tc + 1;
41c445ff
JB		 4521}
4522
4523/**
4524 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4525 * @dcbcfg: the corresponding DCBx configuration structure
4526 *
4527 * Query the current DCB configuration and return the number of
4528 * traffic classes enabled from the given DCBX config
4529 **/
4530static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4531{
4532 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4533 u8 enabled_tc = 1;
4534 u8 i;
4535
4536 for (i = 0; i < num_tc; i++)
41a1d04b 4537 enabled_tc |= BIT(i);
41c445ff
JB		 4538
4539 return enabled_tc;
4540}
4541
4542/**
4543 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4544 * @pf: PF being queried
4545 *
4546 * Return number of traffic classes enabled for the given PF
4547 **/
4548static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4549{
4550 struct i40e_hw *hw = &pf->hw;
4551 u8 i, enabled_tc;
4552 u8 num_tc = 0;
4553 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4554
4555 /* If DCB is not enabled then always in single TC */
4556 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4557 return 1;
4558
63d7e5a4
NP		 4559 /* SFP mode will be enabled for all TCs on port */
4560 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4561 return i40e_dcb_get_num_tc(dcbcfg);
4562
41c445ff 4563 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4564 if (pf->hw.func_caps.iscsi)
4565 enabled_tc = i40e_get_iscsi_tc_map(pf);
4566 else
fc51de96 4567 return 1; /* Only TC0 */
41c445ff 4568
63d7e5a4
NP		 4569 /* At least have TC0 */
4570 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4571 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4572 if (enabled_tc & BIT(i))
63d7e5a4
NP		 4573 num_tc++;
4574 }
4575 return num_tc;
41c445ff
JB		 4576}
4577
4578/**
4579 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4580 * @pf: PF being queried
4581 *
4582 * Return a bitmap for first enabled traffic class for this PF.
4583 **/
4584static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4585{
4586 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4587 u8 i = 0;
4588
4589 if (!enabled_tc)
4590 return 0x1; /* TC0 */
4591
4592 /* Find the first enabled TC */
4593 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4594 if (enabled_tc & BIT(i))
41c445ff
JB		 4595 break;
4596 }
4597
41a1d04b 4598 return BIT(i);
41c445ff
JB		 4599}
4600
4601/**
4602 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4603 * @pf: PF being queried
4604 *
4605 * Return a bitmap for enabled traffic classes for this PF.
4606 **/
4607static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4608{
4609 /* If DCB is not enabled for this PF then just return default TC */
4610 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4611 return i40e_pf_get_default_tc(pf);
4612
41c445ff 4613 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4614 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4615 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4616
fc51de96 4617 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4618 if (pf->hw.func_caps.iscsi)
4619 return i40e_get_iscsi_tc_map(pf);
4620 else
fc51de96 4621 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4622}
4623
4624/**
4625 * i40e_vsi_get_bw_info - Query VSI BW Information
4626 * @vsi: the VSI being queried
4627 *
4628 * Returns 0 on success, negative value on failure
4629 **/
4630static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4631{
4632 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4633 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4634 struct i40e_pf *pf = vsi->back;
4635 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4636 i40e_status ret;
41c445ff 4637 u32 tc_bw_max;
41c445ff
JB		 4638 int i;
4639
4640 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4641 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4642 if (ret) {
41c445ff 4643 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4644 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4645 i40e_stat_str(&pf->hw, ret),
4646 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4647 return -EINVAL;
41c445ff
JB		 4648 }
4649
4650 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4651 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4652 NULL);
4653 if (ret) {
41c445ff 4654 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4655 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4656 i40e_stat_str(&pf->hw, ret),
4657 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4658 return -EINVAL;
41c445ff
JB		 4659 }
4660
4661 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4662 dev_info(&pf->pdev->dev,
4663 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4664 bw_config.tc_valid_bits,
4665 bw_ets_config.tc_valid_bits);
4666 /* Still continuing */
4667 }
4668
4669 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4670 vsi->bw_max_quanta = bw_config.max_bw;
4671 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4672 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4673 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4674 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4675 vsi->bw_ets_limit_credits[i] =
4676 le16_to_cpu(bw_ets_config.credits[i]);
4677 /* 3 bits out of 4 for each TC */
4678 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4679 }
078b5876 4680
dcae29be 4681 return 0;
41c445ff
JB		 4682}
4683
4684/**
4685 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4686 * @vsi: the VSI being configured
4687 * @enabled_tc: TC bitmap
4688 * @bw_credits: BW shared credits per TC
4689 *
4690 * Returns 0 on success, negative value on failure
4691 **/
dcae29be 4692static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4693 u8 *bw_share)
4694{
4695 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4696 i40e_status ret;
dcae29be 4697 int i;
41c445ff
JB		 4698
4699 bw_data.tc_valid_bits = enabled_tc;
4700 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4701 bw_data.tc_bw_credits[i] = bw_share[i];
4702
f1c7e72e
SN		 4703 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4704 NULL);
4705 if (ret) {
41c445ff 4706 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4707 "AQ command Config VSI BW allocation per TC failed = %d\n",
4708 vsi->back->hw.aq.asq_last_status);
dcae29be 4709 return -EINVAL;
41c445ff
JB		 4710 }
4711
4712 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4713 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4714
dcae29be 4715 return 0;
41c445ff
JB		 4716}
4717
4718/**
4719 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4720 * @vsi: the VSI being configured
4721 * @enabled_tc: TC map to be enabled
4722 *
4723 **/
4724static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4725{
4726 struct net_device *netdev = vsi->netdev;
4727 struct i40e_pf *pf = vsi->back;
4728 struct i40e_hw *hw = &pf->hw;
4729 u8 netdev_tc = 0;
4730 int i;
4731 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4732
4733 if (!netdev)
4734 return;
4735
4736 if (!enabled_tc) {
4737 netdev_reset_tc(netdev);
4738 return;
4739 }
4740
4741 /* Set up actual enabled TCs on the VSI */
4742 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4743 return;
4744
4745 /* set per TC queues for the VSI */
4746 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4747 /* Only set TC queues for enabled tcs
4748 *
4749 * e.g. For a VSI that has TC0 and TC3 enabled the
4750 * enabled_tc bitmap would be 0x00001001; the driver
4751 * will set the numtc for netdev as 2 that will be
4752 * referenced by the netdev layer as TC 0 and 1.
4753 */
75f5cea9 4754 if (vsi->tc_config.enabled_tc & BIT(i))
41c445ff
JB		 4755 netdev_set_tc_queue(netdev,
4756 vsi->tc_config.tc_info[i].netdev_tc,
4757 vsi->tc_config.tc_info[i].qcount,
4758 vsi->tc_config.tc_info[i].qoffset);
4759 }
4760
4761 /* Assign UP2TC map for the VSI */
4762 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4763 /* Get the actual TC# for the UP */
4764 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4765 /* Get the mapped netdev TC# for the UP */
4766 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4767 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4768 }
4769}
4770
4771/**
4772 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4773 * @vsi: the VSI being configured
4774 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4775 **/
4776static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4777 struct i40e_vsi_context *ctxt)
4778{
4779 /* copy just the sections touched not the entire info
4780 * since not all sections are valid as returned by
4781 * update vsi params
4782 */
4783 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4784 memcpy(&vsi->info.queue_mapping,
4785 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4786 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4787 sizeof(vsi->info.tc_mapping));
4788}
4789
4790/**
4791 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4792 * @vsi: VSI to be configured
4793 * @enabled_tc: TC bitmap
4794 *
4795 * This configures a particular VSI for TCs that are mapped to the
4796 * given TC bitmap. It uses default bandwidth share for TCs across
4797 * VSIs to configure TC for a particular VSI.
4798 *
4799 * NOTE:
4800 * It is expected that the VSI queues have been quisced before calling
4801 * this function.
4802 **/
4803static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4804{
4805 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4806 struct i40e_vsi_context ctxt;
4807 int ret = 0;
4808 int i;
4809
4810 /* Check if enabled_tc is same as existing or new TCs */
4811 if (vsi->tc_config.enabled_tc == enabled_tc)
4812 return ret;
4813
4814 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4815 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4816 if (enabled_tc & BIT(i))
41c445ff
JB		 4817 bw_share[i] = 1;
4818 }
4819
4820 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4821 if (ret) {
4822 dev_info(&vsi->back->pdev->dev,
4823 "Failed configuring TC map %d for VSI %d\n",
4824 enabled_tc, vsi->seid);
4825 goto out;
4826 }
4827
4828 /* Update Queue Pairs Mapping for currently enabled UPs */
4829 ctxt.seid = vsi->seid;
4830 ctxt.pf_num = vsi->back->hw.pf_id;
4831 ctxt.vf_num = 0;
4832 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4833 ctxt.info = vsi->info;
41c445ff
JB		 4834 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4835
e3219ce6
ASJ		 4836 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
4837 ctxt.info.valid_sections |=
4838 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
4839 ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA;
4840 }
4841
41c445ff
JB		 4842 /* Update the VSI after updating the VSI queue-mapping information */
4843 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4844 if (ret) {
4845 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4846 "Update vsi tc config failed, err %s aq_err %s\n",
4847 i40e_stat_str(&vsi->back->hw, ret),
4848 i40e_aq_str(&vsi->back->hw,
4849 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4850 goto out;
4851 }
4852 /* update the local VSI info with updated queue map */
4853 i40e_vsi_update_queue_map(vsi, &ctxt);
4854 vsi->info.valid_sections = 0;
4855
4856 /* Update current VSI BW information */
4857 ret = i40e_vsi_get_bw_info(vsi);
4858 if (ret) {
4859 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4860 "Failed updating vsi bw info, err %s aq_err %s\n",
4861 i40e_stat_str(&vsi->back->hw, ret),
4862 i40e_aq_str(&vsi->back->hw,
4863 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4864 goto out;
4865 }
4866
4867 /* Update the netdev TC setup */
4868 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4869out:
4870 return ret;
4871}
4872
4e3b35b0
NP		 4873/**
4874 * i40e_veb_config_tc - Configure TCs for given VEB
4875 * @veb: given VEB
4876 * @enabled_tc: TC bitmap
4877 *
4878 * Configures given TC bitmap for VEB (switching) element
4879 **/
4880int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4881{
4882 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4883 struct i40e_pf *pf = veb->pf;
4884 int ret = 0;
4885 int i;
4886
4887 /* No TCs or already enabled TCs just return */
4888 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4889 return ret;
4890
4891 bw_data.tc_valid_bits = enabled_tc;
4892 /* bw_data.absolute_credits is not set (relative) */
4893
4894 /* Enable ETS TCs with equal BW Share for now */
4895 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
75f5cea9 4896 if (enabled_tc & BIT(i))
4e3b35b0
NP		 4897 bw_data.tc_bw_share_credits[i] = 1;
4898 }
4899
4900 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4901 &bw_data, NULL);
4902 if (ret) {
4903 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4904 "VEB bw config failed, err %s aq_err %s\n",
4905 i40e_stat_str(&pf->hw, ret),
4906 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4907 goto out;
4908 }
4909
4910 /* Update the BW information */
4911 ret = i40e_veb_get_bw_info(veb);
4912 if (ret) {
4913 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4914 "Failed getting veb bw config, err %s aq_err %s\n",
4915 i40e_stat_str(&pf->hw, ret),
4916 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4917 }
4918
4919out:
4920 return ret;
4921}
4922
4923#ifdef CONFIG_I40E_DCB
4924/**
4925 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4926 * @pf: PF struct
4927 *
4928 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4929 * the caller would've quiesce all the VSIs before calling
4930 * this function
4931 **/
4932static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4933{
4934 u8 tc_map = 0;
4935 int ret;
4936 u8 v;
4937
4938 /* Enable the TCs available on PF to all VEBs */
4939 tc_map = i40e_pf_get_tc_map(pf);
4940 for (v = 0; v < I40E_MAX_VEB; v++) {
4941 if (!pf->veb[v])
4942 continue;
4943 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4944 if (ret) {
4945 dev_info(&pf->pdev->dev,
4946 "Failed configuring TC for VEB seid=%d\n",
4947 pf->veb[v]->seid);
4948 /* Will try to configure as many components */
4949 }
4950 }
4951
4952 /* Update each VSI */
505682cd 4953 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4954 if (!pf->vsi[v])
4955 continue;
4956
4957 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4958#ifdef I40E_FCOE
4959 * - For FCoE VSI only enable the TC configured
4960 * as per the APP TLV
4961#endif
4e3b35b0
NP		 4962 * - For all others keep them at TC0 for now
4963 */
4964 if (v == pf->lan_vsi)
4965 tc_map = i40e_pf_get_tc_map(pf);
4966 else
4967 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4968#ifdef I40E_FCOE
4969 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4970 tc_map = i40e_get_fcoe_tc_map(pf);
4971#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4972
4973 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4974 if (ret) {
4975 dev_info(&pf->pdev->dev,
4976 "Failed configuring TC for VSI seid=%d\n",
4977 pf->vsi[v]->seid);
4978 /* Will try to configure as many components */
4979 } else {
0672a091
NP		 4980 /* Re-configure VSI vectors based on updated TC map */
4981 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4982 if (pf->vsi[v]->netdev)
4983 i40e_dcbnl_set_all(pf->vsi[v]);
4984 }
4985 }
4986}
4987
2fd75f31
NP		 4988/**
4989 * i40e_resume_port_tx - Resume port Tx
4990 * @pf: PF struct
4991 *
4992 * Resume a port's Tx and issue a PF reset in case of failure to
4993 * resume.
4994 **/
4995static int i40e_resume_port_tx(struct i40e_pf *pf)
4996{
4997 struct i40e_hw *hw = &pf->hw;
4998 int ret;
4999
5000 ret = i40e_aq_resume_port_tx(hw, NULL);
5001 if (ret) {
5002 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5003 "Resume Port Tx failed, err %s aq_err %s\n",
5004 i40e_stat_str(&pf->hw, ret),
5005 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 5006 /* Schedule PF reset to recover */
5007 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5008 i40e_service_event_schedule(pf);
5009 }
5010
5011 return ret;
5012}
5013
4e3b35b0
NP		 5014/**
5015 * i40e_init_pf_dcb - Initialize DCB configuration
5016 * @pf: PF being configured
5017 *
5018 * Query the current DCB configuration and cache it
5019 * in the hardware structure
5020 **/
5021static int i40e_init_pf_dcb(struct i40e_pf *pf)
5022{
5023 struct i40e_hw *hw = &pf->hw;
5024 int err = 0;
5025
025b4a54 5026 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
f1bbad33 5027 if (pf->flags & I40E_FLAG_NO_DCB_SUPPORT)
025b4a54
ASJ		 5028 goto out;
5029
4e3b35b0
NP		 5030 /* Get the initial DCB configuration */
5031 err = i40e_init_dcb(hw);
5032 if (!err) {
5033 /* Device/Function is not DCBX capable */
5034 if ((!hw->func_caps.dcb) ||
5035 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
5036 dev_info(&pf->pdev->dev,
5037 "DCBX offload is not supported or is disabled for this PF.\n");
5038
5039 if (pf->flags & I40E_FLAG_MFP_ENABLED)
5040 goto out;
5041
5042 } else {
5043 /* When status is not DISABLED then DCBX in FW */
5044 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
5045 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 5046
5047 pf->flags |= I40E_FLAG_DCB_CAPABLE;
5048 /* Enable DCB tagging only when more than one TC */
5049 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
5050 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 5051 dev_dbg(&pf->pdev->dev,
5052 "DCBX offload is supported for this PF.\n");
4e3b35b0 5053 }
014269ff 5054 } else {
aebfc816 5055 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 5056 "Query for DCB configuration failed, err %s aq_err %s\n",
5057 i40e_stat_str(&pf->hw, err),
5058 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5059 }
5060
5061out:
5062 return err;
5063}
5064#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5065#define SPEED_SIZE 14
5066#define FC_SIZE 8
5067/**
5068 * i40e_print_link_message - print link up or down
5069 * @vsi: the VSI for which link needs a message
5070 */
c156f856 5071void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5072{
a9165490
SN		 5073 char *speed = "Unknown";
5074 char *fc = "Unknown";
cf05ed08 5075
c156f856
MJ		 5076 if (vsi->current_isup == isup)
5077 return;
5078 vsi->current_isup = isup;
cf05ed08
JB		 5079 if (!isup) {
5080 netdev_info(vsi->netdev, "NIC Link is Down\n");
5081 return;
5082 }
5083
148c2d80
GR		 5084 /* Warn user if link speed on NPAR enabled partition is not at
5085 * least 10GB
5086 */
5087 if (vsi->back->hw.func_caps.npar_enable &&
5088 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5089 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5090 netdev_warn(vsi->netdev,
5091 "The partition detected link speed that is less than 10Gbps\n");
5092
cf05ed08
JB		 5093 switch (vsi->back->hw.phy.link_info.link_speed) {
5094 case I40E_LINK_SPEED_40GB:
a9165490 5095 speed = "40 G";
cf05ed08 5096 break;
ae24b409 5097 case I40E_LINK_SPEED_20GB:
a9165490 5098 speed = "20 G";
ae24b409 5099 break;
cf05ed08 5100 case I40E_LINK_SPEED_10GB:
a9165490 5101 speed = "10 G";
cf05ed08
JB		 5102 break;
5103 case I40E_LINK_SPEED_1GB:
a9165490 5104 speed = "1000 M";
cf05ed08 5105 break;
5960d33f 5106 case I40E_LINK_SPEED_100MB:
a9165490 5107 speed = "100 M";
5960d33f 5108 break;
cf05ed08
JB		 5109 default:
5110 break;
5111 }
5112
5113 switch (vsi->back->hw.fc.current_mode) {
5114 case I40E_FC_FULL:
a9165490 5115 fc = "RX/TX";
cf05ed08
JB		 5116 break;
5117 case I40E_FC_TX_PAUSE:
a9165490 5118 fc = "TX";
cf05ed08
JB		 5119 break;
5120 case I40E_FC_RX_PAUSE:
a9165490 5121 fc = "RX";
cf05ed08
JB		 5122 break;
5123 default:
a9165490 5124 fc = "None";
cf05ed08
JB		 5125 break;
5126 }
5127
a9165490 5128 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5129 speed, fc);
5130}
4e3b35b0 5131
41c445ff
JB		 5132/**
5133 * i40e_up_complete - Finish the last steps of bringing up a connection
5134 * @vsi: the VSI being configured
5135 **/
5136static int i40e_up_complete(struct i40e_vsi *vsi)
5137{
5138 struct i40e_pf *pf = vsi->back;
5139 int err;
5140
5141 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5142 i40e_vsi_configure_msix(vsi);
5143 else
5144 i40e_configure_msi_and_legacy(vsi);
5145
5146 /* start rings */
5147 err = i40e_vsi_control_rings(vsi, true);
5148 if (err)
5149 return err;
5150
5151 clear_bit(__I40E_DOWN, &vsi->state);
5152 i40e_napi_enable_all(vsi);
5153 i40e_vsi_enable_irq(vsi);
5154
5155 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5156 (vsi->netdev)) {
cf05ed08 5157 i40e_print_link_message(vsi, true);
41c445ff
JB		 5158 netif_tx_start_all_queues(vsi->netdev);
5159 netif_carrier_on(vsi->netdev);
6d779b41 5160 } else if (vsi->netdev) {
cf05ed08 5161 i40e_print_link_message(vsi, false);
7b592f61
CW		 5162 /* need to check for qualified module here*/
5163 if ((pf->hw.phy.link_info.link_info &
5164 I40E_AQ_MEDIA_AVAILABLE) &&
5165 (!(pf->hw.phy.link_info.an_info &
5166 I40E_AQ_QUALIFIED_MODULE)))
5167 netdev_err(vsi->netdev,
5168 "the driver failed to link because an unqualified module was detected.");
41c445ff 5169 }
ca64fa4e
ASJ		 5170
5171 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5172 if (vsi->type == I40E_VSI_FDIR) {
5173 /* reset fd counters */
5174 pf->fd_add_err = pf->fd_atr_cnt = 0;
5175 if (pf->fd_tcp_rule > 0) {
5176 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5177 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5178 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5179 pf->fd_tcp_rule = 0;
5180 }
ca64fa4e 5181 i40e_fdir_filter_restore(vsi);
1e1be8f6 5182 }
e3219ce6
ASJ		 5183
5184 /* On the next run of the service_task, notify any clients of the new
5185 * opened netdev
5186 */
5187 pf->flags |= I40E_FLAG_SERVICE_CLIENT_REQUESTED;
41c445ff
JB		 5188 i40e_service_event_schedule(pf);
5189
5190 return 0;
5191}
5192
5193/**
5194 * i40e_vsi_reinit_locked - Reset the VSI
5195 * @vsi: the VSI being configured
5196 *
5197 * Rebuild the ring structs after some configuration
5198 * has changed, e.g. MTU size.
5199 **/
5200static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5201{
5202 struct i40e_pf *pf = vsi->back;
5203
5204 WARN_ON(in_interrupt());
5205 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5206 usleep_range(1000, 2000);
5207 i40e_down(vsi);
5208
41c445ff
JB		 5209 i40e_up(vsi);
5210 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5211}
5212
5213/**
5214 * i40e_up - Bring the connection back up after being down
5215 * @vsi: the VSI being configured
5216 **/
5217int i40e_up(struct i40e_vsi *vsi)
5218{
5219 int err;
5220
5221 err = i40e_vsi_configure(vsi);
5222 if (!err)
5223 err = i40e_up_complete(vsi);
5224
5225 return err;
5226}
5227
5228/**
5229 * i40e_down - Shutdown the connection processing
5230 * @vsi: the VSI being stopped
5231 **/
5232void i40e_down(struct i40e_vsi *vsi)
5233{
5234 int i;
5235
5236 /* It is assumed that the caller of this function
5237 * sets the vsi->state __I40E_DOWN bit.
5238 */
5239 if (vsi->netdev) {
5240 netif_carrier_off(vsi->netdev);
5241 netif_tx_disable(vsi->netdev);
5242 }
5243 i40e_vsi_disable_irq(vsi);
5244 i40e_vsi_control_rings(vsi, false);
5245 i40e_napi_disable_all(vsi);
5246
5247 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5248 i40e_clean_tx_ring(vsi->tx_rings[i]);
5249 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff 5250 }
f980d445
CS		 5251
5252 i40e_notify_client_of_netdev_close(vsi, false);
5253
41c445ff
JB		 5254}
5255
5256/**
5257 * i40e_setup_tc - configure multiple traffic classes
5258 * @netdev: net device to configure
5259 * @tc: number of traffic classes to enable
5260 **/
5261static int i40e_setup_tc(struct net_device *netdev, u8 tc)
5262{
5263 struct i40e_netdev_priv *np = netdev_priv(netdev);
5264 struct i40e_vsi *vsi = np->vsi;
5265 struct i40e_pf *pf = vsi->back;
5266 u8 enabled_tc = 0;
5267 int ret = -EINVAL;
5268 int i;
5269
5270 /* Check if DCB enabled to continue */
5271 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5272 netdev_info(netdev, "DCB is not enabled for adapter\n");
5273 goto exit;
5274 }
5275
5276 /* Check if MFP enabled */
5277 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5278 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5279 goto exit;
5280 }
5281
5282 /* Check whether tc count is within enabled limit */
5283 if (tc > i40e_pf_get_num_tc(pf)) {
5284 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5285 goto exit;
5286 }
5287
5288 /* Generate TC map for number of tc requested */
5289 for (i = 0; i < tc; i++)
75f5cea9 5290 enabled_tc |= BIT(i);
41c445ff
JB		 5291
5292 /* Requesting same TC configuration as already enabled */
5293 if (enabled_tc == vsi->tc_config.enabled_tc)
5294 return 0;
5295
5296 /* Quiesce VSI queues */
5297 i40e_quiesce_vsi(vsi);
5298
5299 /* Configure VSI for enabled TCs */
5300 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5301 if (ret) {
5302 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5303 vsi->seid);
5304 goto exit;
5305 }
5306
5307 /* Unquiesce VSI */
5308 i40e_unquiesce_vsi(vsi);
5309
5310exit:
5311 return ret;
5312}
5313
e4c6734e 5314#ifdef I40E_FCOE
16e5cc64
JF		 5315int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5316 struct tc_to_netdev *tc)
e4c6734e 5317#else
16e5cc64
JF		 5318static int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
5319 struct tc_to_netdev *tc)
e4c6734e
JF		 5320#endif
5321{
16e5cc64 5322 if (handle != TC_H_ROOT || tc->type != TC_SETUP_MQPRIO)
e4c6734e 5323 return -EINVAL;
16e5cc64 5324 return i40e_setup_tc(netdev, tc->tc);
e4c6734e
JF		 5325}
5326
41c445ff
JB		 5327/**
5328 * i40e_open - Called when a network interface is made active
5329 * @netdev: network interface device structure
5330 *
5331 * The open entry point is called when a network interface is made
5332 * active by the system (IFF_UP). At this point all resources needed
5333 * for transmit and receive operations are allocated, the interrupt
5334 * handler is registered with the OS, the netdev watchdog subtask is
5335 * enabled, and the stack is notified that the interface is ready.
5336 *
5337 * Returns 0 on success, negative value on failure
5338 **/
38e00438 5339int i40e_open(struct net_device *netdev)
41c445ff
JB		 5340{
5341 struct i40e_netdev_priv *np = netdev_priv(netdev);
5342 struct i40e_vsi *vsi = np->vsi;
5343 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5344 int err;
5345
4eb3f768
SN		 5346 /* disallow open during test or if eeprom is broken */
5347 if (test_bit(__I40E_TESTING, &pf->state) ||
5348 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5349 return -EBUSY;
5350
5351 netif_carrier_off(netdev);
5352
6c167f58
EK		 5353 err = i40e_vsi_open(vsi);
5354 if (err)
5355 return err;
5356
059dab69
JB		 5357 /* configure global TSO hardware offload settings */
5358 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5359 TCP_FLAG_FIN) >> 16);
5360 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5361 TCP_FLAG_FIN |
5362 TCP_FLAG_CWR) >> 16);
5363 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5364
06a5f7f1 5365 udp_tunnel_get_rx_info(netdev);
e3219ce6
ASJ		 5366 i40e_notify_client_of_netdev_open(vsi);
5367
6c167f58
EK		 5368 return 0;
5369}
5370
5371/**
5372 * i40e_vsi_open -
5373 * @vsi: the VSI to open
5374 *
5375 * Finish initialization of the VSI.
5376 *
5377 * Returns 0 on success, negative value on failure
5378 **/
5379int i40e_vsi_open(struct i40e_vsi *vsi)
5380{
5381 struct i40e_pf *pf = vsi->back;
b294ac70 5382 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5383 int err;
5384
41c445ff
JB		 5385 /* allocate descriptors */
5386 err = i40e_vsi_setup_tx_resources(vsi);
5387 if (err)
5388 goto err_setup_tx;
5389 err = i40e_vsi_setup_rx_resources(vsi);
5390 if (err)
5391 goto err_setup_rx;
5392
5393 err = i40e_vsi_configure(vsi);
5394 if (err)
5395 goto err_setup_rx;
5396
c22e3c6c
SN		 5397 if (vsi->netdev) {
5398 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5399 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5400 err = i40e_vsi_request_irq(vsi, int_name);
5401 if (err)
5402 goto err_setup_rx;
41c445ff 5403
c22e3c6c
SN		 5404 /* Notify the stack of the actual queue counts. */
5405 err = netif_set_real_num_tx_queues(vsi->netdev,
5406 vsi->num_queue_pairs);
5407 if (err)
5408 goto err_set_queues;
25946ddb 5409
c22e3c6c
SN		 5410 err = netif_set_real_num_rx_queues(vsi->netdev,
5411 vsi->num_queue_pairs);
5412 if (err)
5413 goto err_set_queues;
8a9eb7d3
SN		 5414
5415 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5416 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5417 dev_driver_string(&pf->pdev->dev),
5418 dev_name(&pf->pdev->dev));
8a9eb7d3 5419 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5420
c22e3c6c 5421 } else {
ce9ccb17 5422 err = -EINVAL;
6c167f58
EK		 5423 goto err_setup_rx;
5424 }
25946ddb 5425
41c445ff
JB		 5426 err = i40e_up_complete(vsi);
5427 if (err)
5428 goto err_up_complete;
5429
41c445ff
JB		 5430 return 0;
5431
5432err_up_complete:
5433 i40e_down(vsi);
25946ddb 5434err_set_queues:
41c445ff
JB		 5435 i40e_vsi_free_irq(vsi);
5436err_setup_rx:
5437 i40e_vsi_free_rx_resources(vsi);
5438err_setup_tx:
5439 i40e_vsi_free_tx_resources(vsi);
5440 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5441 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5442
5443 return err;
5444}
5445
17a73f6b
JG		 5446/**
5447 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5448 * @pf: Pointer to PF
17a73f6b
JG		 5449 *
5450 * This function destroys the hlist where all the Flow Director
5451 * filters were saved.
5452 **/
5453static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5454{
5455 struct i40e_fdir_filter *filter;
5456 struct hlist_node *node2;
5457
5458 hlist_for_each_entry_safe(filter, node2,
5459 &pf->fdir_filter_list, fdir_node) {
5460 hlist_del(&filter->fdir_node);
5461 kfree(filter);
5462 }
5463 pf->fdir_pf_active_filters = 0;
5464}
5465
41c445ff
JB		 5466/**
5467 * i40e_close - Disables a network interface
5468 * @netdev: network interface device structure
5469 *
5470 * The close entry point is called when an interface is de-activated
5471 * by the OS. The hardware is still under the driver's control, but
5472 * this netdev interface is disabled.
5473 *
5474 * Returns 0, this is not allowed to fail
5475 **/
38e00438 5476int i40e_close(struct net_device *netdev)
41c445ff
JB		 5477{
5478 struct i40e_netdev_priv *np = netdev_priv(netdev);
5479 struct i40e_vsi *vsi = np->vsi;
5480
90ef8d47 5481 i40e_vsi_close(vsi);
41c445ff
JB		 5482
5483 return 0;
5484}
5485
5486/**
5487 * i40e_do_reset - Start a PF or Core Reset sequence
5488 * @pf: board private structure
5489 * @reset_flags: which reset is requested
5490 *
5491 * The essential difference in resets is that the PF Reset
5492 * doesn't clear the packet buffers, doesn't reset the PE
5493 * firmware, and doesn't bother the other PFs on the chip.
5494 **/
5495void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5496{
5497 u32 val;
5498
5499 WARN_ON(in_interrupt());
5500
263fc48f 5501
41c445ff 5502 /* do the biggest reset indicated */
41a1d04b 5503 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5504
5505 /* Request a Global Reset
5506 *
5507 * This will start the chip's countdown to the actual full
5508 * chip reset event, and a warning interrupt to be sent
5509 * to all PFs, including the requestor. Our handler
5510 * for the warning interrupt will deal with the shutdown
5511 * and recovery of the switch setup.
5512 */
69bfb110 5513 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5514 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5515 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5516 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5517
41a1d04b 5518 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5519
5520 /* Request a Core Reset
5521 *
5522 * Same as Global Reset, except does *not* include the MAC/PHY
5523 */
69bfb110 5524 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5525 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5526 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5527 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5528 i40e_flush(&pf->hw);
5529
41a1d04b 5530 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5531
5532 /* Request a PF Reset
5533 *
5534 * Resets only the PF-specific registers
5535 *
5536 * This goes directly to the tear-down and rebuild of
5537 * the switch, since we need to do all the recovery as
5538 * for the Core Reset.
5539 */
69bfb110 5540 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5541 i40e_handle_reset_warning(pf);
5542
41a1d04b 5543 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5544 int v;
5545
5546 /* Find the VSI(s) that requested a re-init */
5547 dev_info(&pf->pdev->dev,
5548 "VSI reinit requested\n");
505682cd 5549 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5550 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5551
41c445ff
JB		 5552 if (vsi != NULL &&
5553 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5554 i40e_vsi_reinit_locked(pf->vsi[v]);
5555 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5556 }
5557 }
41a1d04b 5558 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5559 int v;
5560
5561 /* Find the VSI(s) that needs to be brought down */
5562 dev_info(&pf->pdev->dev, "VSI down requested\n");
5563 for (v = 0; v < pf->num_alloc_vsi; v++) {
5564 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5565
b5d06f05
NP		 5566 if (vsi != NULL &&
5567 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5568 set_bit(__I40E_DOWN, &vsi->state);
5569 i40e_down(vsi);
5570 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5571 }
5572 }
41c445ff
JB		 5573 } else {
5574 dev_info(&pf->pdev->dev,
5575 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5576 }
5577}
5578
4e3b35b0
NP		 5579#ifdef CONFIG_I40E_DCB
5580/**
5581 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5582 * @pf: board private structure
5583 * @old_cfg: current DCB config
5584 * @new_cfg: new DCB config
5585 **/
5586bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5587 struct i40e_dcbx_config *old_cfg,
5588 struct i40e_dcbx_config *new_cfg)
5589{
5590 bool need_reconfig = false;
5591
5592 /* Check if ETS configuration has changed */
5593 if (memcmp(&new_cfg->etscfg,
5594 &old_cfg->etscfg,
5595 sizeof(new_cfg->etscfg))) {
5596 /* If Priority Table has changed reconfig is needed */
5597 if (memcmp(&new_cfg->etscfg.prioritytable,
5598 &old_cfg->etscfg.prioritytable,
5599 sizeof(new_cfg->etscfg.prioritytable))) {
5600 need_reconfig = true;
69bfb110 5601 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5602 }
5603
5604 if (memcmp(&new_cfg->etscfg.tcbwtable,
5605 &old_cfg->etscfg.tcbwtable,
5606 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5607 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5608
5609 if (memcmp(&new_cfg->etscfg.tsatable,
5610 &old_cfg->etscfg.tsatable,
5611 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5612 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5613 }
5614
5615 /* Check if PFC configuration has changed */
5616 if (memcmp(&new_cfg->pfc,
5617 &old_cfg->pfc,
5618 sizeof(new_cfg->pfc))) {
5619 need_reconfig = true;
69bfb110 5620 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5621 }
5622
5623 /* Check if APP Table has changed */
5624 if (memcmp(&new_cfg->app,
5625 &old_cfg->app,
3d9667a9 5626 sizeof(new_cfg->app))) {
4e3b35b0 5627 need_reconfig = true;
69bfb110 5628 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5629 }
4e3b35b0 5630
fb43201f 5631 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5632 return need_reconfig;
5633}
5634
5635/**
5636 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5637 * @pf: board private structure
5638 * @e: event info posted on ARQ
5639 **/
5640static int i40e_handle_lldp_event(struct i40e_pf *pf,
5641 struct i40e_arq_event_info *e)
5642{
5643 struct i40e_aqc_lldp_get_mib *mib =
5644 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5645 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5646 struct i40e_dcbx_config tmp_dcbx_cfg;
5647 bool need_reconfig = false;
5648 int ret = 0;
5649 u8 type;
5650
4d9b6043
NP		 5651 /* Not DCB capable or capability disabled */
5652 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5653 return ret;
5654
4e3b35b0
NP		 5655 /* Ignore if event is not for Nearest Bridge */
5656 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5657 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5658 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5659 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5660 return ret;
5661
5662 /* Check MIB Type and return if event for Remote MIB update */
5663 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5664 dev_dbg(&pf->pdev->dev,
fb43201f 5665 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5666 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5667 /* Update the remote cached instance and return */
5668 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5669 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5670 &hw->remote_dcbx_config);
5671 goto exit;
5672 }
5673
9fa61dd2 5674 /* Store the old configuration */
1a2f6248 5675 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5676
750fcbcf
NP		 5677 /* Reset the old DCBx configuration data */
5678 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5679 /* Get updated DCBX data from firmware */
5680 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5681 if (ret) {
f1c7e72e
SN		 5682 dev_info(&pf->pdev->dev,
5683 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5684 i40e_stat_str(&pf->hw, ret),
5685 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5686 goto exit;
5687 }
5688
5689 /* No change detected in DCBX configs */
750fcbcf
NP		 5690 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5691 sizeof(tmp_dcbx_cfg))) {
69bfb110 5692 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5693 goto exit;
5694 }
5695
750fcbcf
NP		 5696 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5697 &hw->local_dcbx_config);
4e3b35b0 5698
750fcbcf 5699 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5700
5701 if (!need_reconfig)
5702 goto exit;
5703
4d9b6043 5704 /* Enable DCB tagging only when more than one TC */
750fcbcf 5705 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5706 pf->flags |= I40E_FLAG_DCB_ENABLED;
5707 else
5708 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5709
69129dc3 5710 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5711 /* Reconfiguration needed quiesce all VSIs */
5712 i40e_pf_quiesce_all_vsi(pf);
5713
5714 /* Changes in configuration update VEB/VSI */
5715 i40e_dcb_reconfigure(pf);
5716
2fd75f31
NP		 5717 ret = i40e_resume_port_tx(pf);
5718
69129dc3 5719 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5720 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5721 if (ret)
5722 goto exit;
5723
3fe06f41
NP		 5724 /* Wait for the PF's queues to be disabled */
5725 ret = i40e_pf_wait_queues_disabled(pf);
11e47708
PN		 5726 if (ret) {
5727 /* Schedule PF reset to recover */
5728 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5729 i40e_service_event_schedule(pf);
5730 } else {
2fd75f31 5731 i40e_pf_unquiesce_all_vsi(pf);
85a1aab7
NP		 5732 /* Notify the client for the DCB changes */
5733 i40e_notify_client_of_l2_param_changes(pf->vsi[pf->lan_vsi]);
11e47708
PN		 5734 }
5735
4e3b35b0
NP		 5736exit:
5737 return ret;
5738}
5739#endif /* CONFIG_I40E_DCB */
5740
23326186
ASJ		 5741/**
5742 * i40e_do_reset_safe - Protected reset path for userland calls.
5743 * @pf: board private structure
5744 * @reset_flags: which reset is requested
5745 *
5746 **/
5747void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5748{
5749 rtnl_lock();
5750 i40e_do_reset(pf, reset_flags);
5751 rtnl_unlock();
5752}
5753
41c445ff
JB		 5754/**
5755 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5756 * @pf: board private structure
5757 * @e: event info posted on ARQ
5758 *
5759 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5760 * and VF queues
5761 **/
5762static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5763 struct i40e_arq_event_info *e)
5764{
5765 struct i40e_aqc_lan_overflow *data =
5766 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5767 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5768 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5769 struct i40e_hw *hw = &pf->hw;
5770 struct i40e_vf *vf;
5771 u16 vf_id;
5772
69bfb110
JB		 5773 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5774 queue, qtx_ctl);
41c445ff
JB		 5775
5776 /* Queue belongs to VF, find the VF and issue VF reset */
5777 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5778 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5779 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5780 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5781 vf_id -= hw->func_caps.vf_base_id;
5782 vf = &pf->vf[vf_id];
5783 i40e_vc_notify_vf_reset(vf);
5784 /* Allow VF to process pending reset notification */
5785 msleep(20);
5786 i40e_reset_vf(vf, false);
5787 }
5788}
5789
5790/**
5791 * i40e_service_event_complete - Finish up the service event
5792 * @pf: board private structure
5793 **/
5794static void i40e_service_event_complete(struct i40e_pf *pf)
5795{
b875f99b 5796 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5797
5798 /* flush memory to make sure state is correct before next watchog */
4e857c58 5799 smp_mb__before_atomic();
41c445ff
JB		 5800 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5801}
5802
55a5e60b 5803/**
12957388
ASJ		 5804 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5805 * @pf: board private structure
5806 **/
04294e38 5807u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5808{
04294e38 5809 u32 val, fcnt_prog;
12957388
ASJ		 5810
5811 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5812 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5813 return fcnt_prog;
5814}
5815
5816/**
04294e38 5817 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5818 * @pf: board private structure
5819 **/
04294e38 5820u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5821{
04294e38
ASJ		 5822 u32 val, fcnt_prog;
5823
55a5e60b
ASJ		 5824 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5825 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5826 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5827 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5828 return fcnt_prog;
5829}
1e1be8f6 5830
04294e38
ASJ		 5831/**
5832 * i40e_get_global_fd_count - Get total FD filters programmed on device
5833 * @pf: board private structure
5834 **/
5835u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5836{
5837 u32 val, fcnt_prog;
5838
5839 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5840 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5841 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5842 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5843 return fcnt_prog;
5844}
5845
55a5e60b
ASJ		 5846/**
5847 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5848 * @pf: board private structure
5849 **/
5850void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5851{
3487b6c3 5852 struct i40e_fdir_filter *filter;
55a5e60b 5853 u32 fcnt_prog, fcnt_avail;
3487b6c3 5854 struct hlist_node *node;
55a5e60b 5855
1e1be8f6
ASJ		 5856 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5857 return;
5858
55a5e60b
ASJ		 5859 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5860 * to re-enable
5861 */
04294e38 5862 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5863 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5864 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5865 (pf->fd_add_err == 0) ||
5866 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5867 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5868 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5869 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5870 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5871 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5872 }
5873 }
5874 /* Wait for some more space to be available to turn on ATR */
5875 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5876 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5877 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5878 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5879 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5880 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5881 }
5882 }
3487b6c3
CW		 5883
5884 /* if hw had a problem adding a filter, delete it */
5885 if (pf->fd_inv > 0) {
5886 hlist_for_each_entry_safe(filter, node,
5887 &pf->fdir_filter_list, fdir_node) {
5888 if (filter->fd_id == pf->fd_inv) {
5889 hlist_del(&filter->fdir_node);
5890 kfree(filter);
5891 pf->fdir_pf_active_filters--;
5892 }
5893 }
5894 }
55a5e60b
ASJ		 5895}
5896
1e1be8f6 5897#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5898#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5899/**
5900 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5901 * @pf: board private structure
5902 **/
5903static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5904{
04294e38 5905 unsigned long min_flush_time;
1e1be8f6 5906 int flush_wait_retry = 50;
04294e38
ASJ		 5907 bool disable_atr = false;
5908 int fd_room;
1e1be8f6
ASJ		 5909 int reg;
5910
1790ed0c
AA		 5911 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5912 return;
5913
a5fdaf34
JB		 5914 if (!time_after(jiffies, pf->fd_flush_timestamp +
5915 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5916 return;
04294e38 5917
a5fdaf34
JB		 5918 /* If the flush is happening too quick and we have mostly SB rules we
5919 * should not re-enable ATR for some time.
5920 */
5921 min_flush_time = pf->fd_flush_timestamp +
5922 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5923 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5924
5925 if (!(time_after(jiffies, min_flush_time)) &&
5926 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5927 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5928 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5929 disable_atr = true;
5930 }
5931
5932 pf->fd_flush_timestamp = jiffies;
5933 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5934 /* flush all filters */
5935 wr32(&pf->hw, I40E_PFQF_CTL_1,
5936 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5937 i40e_flush(&pf->hw);
5938 pf->fd_flush_cnt++;
5939 pf->fd_add_err = 0;
5940 do {
5941 /* Check FD flush status every 5-6msec */
5942 usleep_range(5000, 6000);
5943 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5944 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5945 break;
5946 } while (flush_wait_retry--);
5947 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5948 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5949 } else {
5950 /* replay sideband filters */
5951 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5952 if (!disable_atr)
5953 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5954 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5955 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5956 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6
ASJ		 5957 }
5958}
5959
5960/**
5961 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5962 * @pf: board private structure
5963 **/
04294e38 5964u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5965{
5966 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5967}
5968
5969/* We can see up to 256 filter programming desc in transit if the filters are
5970 * being applied really fast; before we see the first
5971 * filter miss error on Rx queue 0. Accumulating enough error messages before
5972 * reacting will make sure we don't cause flush too often.
5973 */
5974#define I40E_MAX_FD_PROGRAM_ERROR 256
5975
41c445ff
JB		 5976/**
5977 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5978 * @pf: board private structure
5979 **/
5980static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5981{
41c445ff 5982
41c445ff
JB		 5983 /* if interface is down do nothing */
5984 if (test_bit(__I40E_DOWN, &pf->state))
5985 return;
1e1be8f6 5986
1790ed0c
AA		 5987 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5988 return;
5989
04294e38 5990 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5991 i40e_fdir_flush_and_replay(pf);
5992
55a5e60b
ASJ		 5993 i40e_fdir_check_and_reenable(pf);
5994
41c445ff
JB		 5995}
5996
5997/**
5998 * i40e_vsi_link_event - notify VSI of a link event
5999 * @vsi: vsi to be notified
6000 * @link_up: link up or down
6001 **/
6002static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
6003{
32b5b811 6004 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 6005 return;
6006
6007 switch (vsi->type) {
6008 case I40E_VSI_MAIN:
38e00438
VD		 6009#ifdef I40E_FCOE
6010 case I40E_VSI_FCOE:
6011#endif
41c445ff
JB		 6012 if (!vsi->netdev || !vsi->netdev_registered)
6013 break;
6014
6015 if (link_up) {
6016 netif_carrier_on(vsi->netdev);
6017 netif_tx_wake_all_queues(vsi->netdev);
6018 } else {
6019 netif_carrier_off(vsi->netdev);
6020 netif_tx_stop_all_queues(vsi->netdev);
6021 }
6022 break;
6023
6024 case I40E_VSI_SRIOV:
41c445ff
JB		 6025 case I40E_VSI_VMDQ2:
6026 case I40E_VSI_CTRL:
e3219ce6 6027 case I40E_VSI_IWARP:
41c445ff
JB		 6028 case I40E_VSI_MIRROR:
6029 default:
6030 /* there is no notification for other VSIs */
6031 break;
6032 }
6033}
6034
6035/**
6036 * i40e_veb_link_event - notify elements on the veb of a link event
6037 * @veb: veb to be notified
6038 * @link_up: link up or down
6039 **/
6040static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
6041{
6042 struct i40e_pf *pf;
6043 int i;
6044
6045 if (!veb || !veb->pf)
6046 return;
6047 pf = veb->pf;
6048
6049 /* depth first... */
6050 for (i = 0; i < I40E_MAX_VEB; i++)
6051 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
6052 i40e_veb_link_event(pf->veb[i], link_up);
6053
6054 /* ... now the local VSIs */
505682cd 6055 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6056 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
6057 i40e_vsi_link_event(pf->vsi[i], link_up);
6058}
6059
6060/**
6061 * i40e_link_event - Update netif_carrier status
6062 * @pf: board private structure
6063 **/
6064static void i40e_link_event(struct i40e_pf *pf)
6065{
320684cd 6066 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6067 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6068 i40e_status status;
6069 bool new_link, old_link;
41c445ff 6070
1f9610e4
CS		 6071 /* save off old link status information */
6072 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6073
1e701e09
JB		 6074 /* set this to force the get_link_status call to refresh state */
6075 pf->hw.phy.get_link_info = true;
6076
41c445ff 6077 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6078
6079 status = i40e_get_link_status(&pf->hw, &new_link);
6080 if (status) {
6081 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6082 status);
6083 return;
6084 }
6085
fef59ddf
CS		 6086 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6087 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6088
1e701e09 6089 if (new_link == old_link &&
fef59ddf 6090 new_link_speed == old_link_speed &&
320684cd
MW		 6091 (test_bit(__I40E_DOWN, &vsi->state) ||
6092 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6093 return;
320684cd
MW		 6094
6095 if (!test_bit(__I40E_DOWN, &vsi->state))
6096 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6097
6098 /* Notify the base of the switch tree connected to
6099 * the link. Floating VEBs are not notified.
6100 */
6101 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6102 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6103 else
320684cd 6104 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6105
6106 if (pf->vf)
6107 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6108
6109 if (pf->flags & I40E_FLAG_PTP)
6110 i40e_ptp_set_increment(pf);
41c445ff
JB		 6111}
6112
41c445ff 6113/**
21536717 6114 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6115 * @pf: board private structure
6116 **/
6117static void i40e_watchdog_subtask(struct i40e_pf *pf)
6118{
6119 int i;
6120
6121 /* if interface is down do nothing */
6122 if (test_bit(__I40E_DOWN, &pf->state) ||
6123 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6124 return;
6125
21536717
SN		 6126 /* make sure we don't do these things too often */
6127 if (time_before(jiffies, (pf->service_timer_previous +
6128 pf->service_timer_period)))
6129 return;
6130 pf->service_timer_previous = jiffies;
6131
9ac77266
SN		 6132 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6133 i40e_link_event(pf);
21536717 6134
41c445ff
JB		 6135 /* Update the stats for active netdevs so the network stack
6136 * can look at updated numbers whenever it cares to
6137 */
505682cd 6138 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6139 if (pf->vsi[i] && pf->vsi[i]->netdev)
6140 i40e_update_stats(pf->vsi[i]);
6141
d1a8d275
ASJ		 6142 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6143 /* Update the stats for the active switching components */
6144 for (i = 0; i < I40E_MAX_VEB; i++)
6145 if (pf->veb[i])
6146 i40e_update_veb_stats(pf->veb[i]);
6147 }
beb0dff1
JK		 6148
6149 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6150}
6151
6152/**
6153 * i40e_reset_subtask - Set up for resetting the device and driver
6154 * @pf: board private structure
6155 **/
6156static void i40e_reset_subtask(struct i40e_pf *pf)
6157{
6158 u32 reset_flags = 0;
6159
23326186 6160 rtnl_lock();
41c445ff 6161 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
75f5cea9 6162 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6163 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6164 }
6165 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
75f5cea9 6166 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6167 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6168 }
6169 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
75f5cea9 6170 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6171 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6172 }
6173 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
75f5cea9 6174 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6175 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6176 }
b5d06f05 6177 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
75f5cea9 6178 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6179 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6180 }
41c445ff
JB		 6181
6182 /* If there's a recovery already waiting, it takes
6183 * precedence before starting a new reset sequence.
6184 */
6185 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6186 i40e_handle_reset_warning(pf);
23326186 6187 goto unlock;
41c445ff
JB		 6188 }
6189
6190 /* If we're already down or resetting, just bail */
6191 if (reset_flags &&
6192 !test_bit(__I40E_DOWN, &pf->state) &&
6193 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6194 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6195
6196unlock:
6197 rtnl_unlock();
41c445ff
JB		 6198}
6199
6200/**
6201 * i40e_handle_link_event - Handle link event
6202 * @pf: board private structure
6203 * @e: event info posted on ARQ
6204 **/
6205static void i40e_handle_link_event(struct i40e_pf *pf,
6206 struct i40e_arq_event_info *e)
6207{
41c445ff
JB		 6208 struct i40e_aqc_get_link_status *status =
6209 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6210
1e701e09
JB		 6211 /* Do a new status request to re-enable LSE reporting
6212 * and load new status information into the hw struct
6213 * This completely ignores any state information
6214 * in the ARQ event info, instead choosing to always
6215 * issue the AQ update link status command.
6216 */
6217 i40e_link_event(pf);
6218
7b592f61
CW		 6219 /* check for unqualified module, if link is down */
6220 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6221 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6222 (!(status->link_info & I40E_AQ_LINK_UP)))
6223 dev_err(&pf->pdev->dev,
6224 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6225}
6226
6227/**
6228 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6229 * @pf: board private structure
6230 **/
6231static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6232{
6233 struct i40e_arq_event_info event;
6234 struct i40e_hw *hw = &pf->hw;
6235 u16 pending, i = 0;
6236 i40e_status ret;
6237 u16 opcode;
86df242b 6238 u32 oldval;
41c445ff
JB		 6239 u32 val;
6240
a316f651
ASJ		 6241 /* Do not run clean AQ when PF reset fails */
6242 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6243 return;
6244
86df242b
SN		 6245 /* check for error indications */
6246 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6247 oldval = val;
6248 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
75eb73c1
MW		 6249 if (hw->debug_mask & I40E_DEBUG_AQ)
6250 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
86df242b
SN		 6251 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6252 }
6253 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
75eb73c1
MW		 6254 if (hw->debug_mask & I40E_DEBUG_AQ)
6255 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
86df242b 6256 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
1d0a4ada 6257 pf->arq_overflows++;
86df242b
SN		 6258 }
6259 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
75eb73c1
MW		 6260 if (hw->debug_mask & I40E_DEBUG_AQ)
6261 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
86df242b
SN		 6262 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6263 }
6264 if (oldval != val)
6265 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6266
6267 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6268 oldval = val;
6269 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
75eb73c1
MW		 6270 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6271 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
86df242b
SN		 6272 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6273 }
6274 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
75eb73c1
MW		 6275 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6276 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
86df242b
SN		 6277 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6278 }
6279 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
75eb73c1
MW		 6280 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
6281 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
86df242b
SN		 6282 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6283 }
6284 if (oldval != val)
6285 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6286
1001dc37
MW		 6287 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6288 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6289 if (!event.msg_buf)
6290 return;
6291
6292 do {
6293 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6294 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6295 break;
56497978 6296 else if (ret) {
41c445ff
JB		 6297 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6298 break;
6299 }
6300
6301 opcode = le16_to_cpu(event.desc.opcode);
6302 switch (opcode) {
6303
6304 case i40e_aqc_opc_get_link_status:
6305 i40e_handle_link_event(pf, &event);
6306 break;
6307 case i40e_aqc_opc_send_msg_to_pf:
6308 ret = i40e_vc_process_vf_msg(pf,
6309 le16_to_cpu(event.desc.retval),
6310 le32_to_cpu(event.desc.cookie_high),
6311 le32_to_cpu(event.desc.cookie_low),
6312 event.msg_buf,
1001dc37 6313 event.msg_len);
41c445ff
JB		 6314 break;
6315 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6316 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6317#ifdef CONFIG_I40E_DCB
6318 rtnl_lock();
6319 ret = i40e_handle_lldp_event(pf, &event);
6320 rtnl_unlock();
6321#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6322 break;
6323 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6324 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6325 i40e_handle_lan_overflow_event(pf, &event);
6326 break;
0467bc91
SN		 6327 case i40e_aqc_opc_send_msg_to_peer:
6328 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6329 break;
91a0f930
SN		 6330 case i40e_aqc_opc_nvm_erase:
6331 case i40e_aqc_opc_nvm_update:
00ada50d 6332 case i40e_aqc_opc_oem_post_update:
6e93d0c9
SN		 6333 i40e_debug(&pf->hw, I40E_DEBUG_NVM,
6334 "ARQ NVM operation 0x%04x completed\n",
6335 opcode);
91a0f930 6336 break;
41c445ff
JB		 6337 default:
6338 dev_info(&pf->pdev->dev,
56e5ca68 6339 "ARQ: Unknown event 0x%04x ignored\n",
0467bc91 6340 opcode);
41c445ff
JB		 6341 break;
6342 }
6343 } while (pending && (i++ < pf->adminq_work_limit));
6344
6345 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6346 /* re-enable Admin queue interrupt cause */
6347 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6348 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6349 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6350 i40e_flush(hw);
6351
6352 kfree(event.msg_buf);
6353}
6354
4eb3f768
SN		 6355/**
6356 * i40e_verify_eeprom - make sure eeprom is good to use
6357 * @pf: board private structure
6358 **/
6359static void i40e_verify_eeprom(struct i40e_pf *pf)
6360{
6361 int err;
6362
6363 err = i40e_diag_eeprom_test(&pf->hw);
6364 if (err) {
6365 /* retry in case of garbage read */
6366 err = i40e_diag_eeprom_test(&pf->hw);
6367 if (err) {
6368 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6369 err);
6370 set_bit(__I40E_BAD_EEPROM, &pf->state);
6371 }
6372 }
6373
6374 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6375 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6376 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6377 }
6378}
6379
386a0afa
AA		 6380/**
6381 * i40e_enable_pf_switch_lb
b40c82e6 6382 * @pf: pointer to the PF structure
386a0afa
AA		 6383 *
6384 * enable switch loop back or die - no point in a return value
6385 **/
6386static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6387{
6388 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6389 struct i40e_vsi_context ctxt;
f1c7e72e 6390 int ret;
386a0afa
AA		 6391
6392 ctxt.seid = pf->main_vsi_seid;
6393 ctxt.pf_num = pf->hw.pf_id;
6394 ctxt.vf_num = 0;
f1c7e72e
SN		 6395 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6396 if (ret) {
386a0afa 6397 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6398 "couldn't get PF vsi config, err %s aq_err %s\n",
6399 i40e_stat_str(&pf->hw, ret),
6400 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6401 return;
6402 }
6403 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6404 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6405 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6406
f1c7e72e
SN		 6407 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6408 if (ret) {
386a0afa 6409 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6410 "update vsi switch failed, err %s aq_err %s\n",
6411 i40e_stat_str(&pf->hw, ret),
6412 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6413 }
6414}
6415
6416/**
6417 * i40e_disable_pf_switch_lb
b40c82e6 6418 * @pf: pointer to the PF structure
386a0afa
AA		 6419 *
6420 * disable switch loop back or die - no point in a return value
6421 **/
6422static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6423{
6424 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6425 struct i40e_vsi_context ctxt;
f1c7e72e 6426 int ret;
386a0afa
AA		 6427
6428 ctxt.seid = pf->main_vsi_seid;
6429 ctxt.pf_num = pf->hw.pf_id;
6430 ctxt.vf_num = 0;
f1c7e72e
SN		 6431 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6432 if (ret) {
386a0afa 6433 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6434 "couldn't get PF vsi config, err %s aq_err %s\n",
6435 i40e_stat_str(&pf->hw, ret),
6436 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6437 return;
6438 }
6439 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6440 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6441 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6442
f1c7e72e
SN		 6443 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6444 if (ret) {
386a0afa 6445 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6446 "update vsi switch failed, err %s aq_err %s\n",
6447 i40e_stat_str(&pf->hw, ret),
6448 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6449 }
6450}
6451
51616018
NP		 6452/**
6453 * i40e_config_bridge_mode - Configure the HW bridge mode
6454 * @veb: pointer to the bridge instance
6455 *
6456 * Configure the loop back mode for the LAN VSI that is downlink to the
6457 * specified HW bridge instance. It is expected this function is called
6458 * when a new HW bridge is instantiated.
6459 **/
6460static void i40e_config_bridge_mode(struct i40e_veb *veb)
6461{
6462 struct i40e_pf *pf = veb->pf;
6463
6dec1017
SN		 6464 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6465 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6466 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6467 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6468 i40e_disable_pf_switch_lb(pf);
6469 else
6470 i40e_enable_pf_switch_lb(pf);
6471}
6472
41c445ff
JB		 6473/**
6474 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6475 * @veb: pointer to the VEB instance
6476 *
6477 * This is a recursive function that first builds the attached VSIs then
6478 * recurses in to build the next layer of VEB. We track the connections
6479 * through our own index numbers because the seid's from the HW could
6480 * change across the reset.
6481 **/
6482static int i40e_reconstitute_veb(struct i40e_veb *veb)
6483{
6484 struct i40e_vsi *ctl_vsi = NULL;
6485 struct i40e_pf *pf = veb->pf;
6486 int v, veb_idx;
6487 int ret;
6488
6489 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6490 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6491 if (pf->vsi[v] &&
6492 pf->vsi[v]->veb_idx == veb->idx &&
6493 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6494 ctl_vsi = pf->vsi[v];
6495 break;
6496 }
6497 }
6498 if (!ctl_vsi) {
6499 dev_info(&pf->pdev->dev,
6500 "missing owner VSI for veb_idx %d\n", veb->idx);
6501 ret = -ENOENT;
6502 goto end_reconstitute;
6503 }
6504 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6505 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6506 ret = i40e_add_vsi(ctl_vsi);
6507 if (ret) {
6508 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6509 "rebuild of veb_idx %d owner VSI failed: %d\n",
6510 veb->idx, ret);
41c445ff
JB		 6511 goto end_reconstitute;
6512 }
6513 i40e_vsi_reset_stats(ctl_vsi);
6514
6515 /* create the VEB in the switch and move the VSI onto the VEB */
6516 ret = i40e_add_veb(veb, ctl_vsi);
6517 if (ret)
6518 goto end_reconstitute;
6519
fc60861e
ASJ		 6520 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6521 veb->bridge_mode = BRIDGE_MODE_VEB;
6522 else
6523 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6524 i40e_config_bridge_mode(veb);
b64ba084 6525
41c445ff 6526 /* create the remaining VSIs attached to this VEB */
505682cd 6527 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6528 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6529 continue;
6530
6531 if (pf->vsi[v]->veb_idx == veb->idx) {
6532 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6533
41c445ff
JB		 6534 vsi->uplink_seid = veb->seid;
6535 ret = i40e_add_vsi(vsi);
6536 if (ret) {
6537 dev_info(&pf->pdev->dev,
6538 "rebuild of vsi_idx %d failed: %d\n",
6539 v, ret);
6540 goto end_reconstitute;
6541 }
6542 i40e_vsi_reset_stats(vsi);
6543 }
6544 }
6545
6546 /* create any VEBs attached to this VEB - RECURSION */
6547 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6548 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6549 pf->veb[veb_idx]->uplink_seid = veb->seid;
6550 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6551 if (ret)
6552 break;
6553 }
6554 }
6555
6556end_reconstitute:
6557 return ret;
6558}
6559
6560/**
6561 * i40e_get_capabilities - get info about the HW
6562 * @pf: the PF struct
6563 **/
6564static int i40e_get_capabilities(struct i40e_pf *pf)
6565{
6566 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6567 u16 data_size;
6568 int buf_len;
6569 int err;
6570
6571 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6572 do {
6573 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6574 if (!cap_buf)
6575 return -ENOMEM;
6576
6577 /* this loads the data into the hw struct for us */
6578 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6579 &data_size,
6580 i40e_aqc_opc_list_func_capabilities,
6581 NULL);
6582 /* data loaded, buffer no longer needed */
6583 kfree(cap_buf);
6584
6585 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6586 /* retry with a larger buffer */
6587 buf_len = data_size;
6588 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6589 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6590 "capability discovery failed, err %s aq_err %s\n",
6591 i40e_stat_str(&pf->hw, err),
6592 i40e_aq_str(&pf->hw,
6593 pf->hw.aq.asq_last_status));
41c445ff
JB		 6594 return -ENODEV;
6595 }
6596 } while (err);
6597
6598 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6599 dev_info(&pf->pdev->dev,
6600 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6601 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6602 pf->hw.func_caps.num_msix_vectors,
6603 pf->hw.func_caps.num_msix_vectors_vf,
6604 pf->hw.func_caps.fd_filters_guaranteed,
6605 pf->hw.func_caps.fd_filters_best_effort,
6606 pf->hw.func_caps.num_tx_qp,
6607 pf->hw.func_caps.num_vsis);
6608
7134f9ce
JB		 6609#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6610 + pf->hw.func_caps.num_vfs)
6611 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6612 dev_info(&pf->pdev->dev,
6613 "got num_vsis %d, setting num_vsis to %d\n",
6614 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6615 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6616 }
6617
41c445ff
JB		 6618 return 0;
6619}
6620
cbf61325
ASJ		 6621static int i40e_vsi_clear(struct i40e_vsi *vsi);
6622
41c445ff 6623/**
cbf61325 6624 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6625 * @pf: board private structure
6626 **/
cbf61325 6627static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6628{
6629 struct i40e_vsi *vsi;
8a9eb7d3 6630 int i;
41c445ff 6631
407e063c
JB		 6632 /* quick workaround for an NVM issue that leaves a critical register
6633 * uninitialized
6634 */
6635 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6636 static const u32 hkey[] = {
6637 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6638 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6639 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6640 0x95b3a76d};
6641
6642 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6643 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6644 }
6645
cbf61325 6646 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6647 return;
6648
cbf61325 6649 /* find existing VSI and see if it needs configuring */
41c445ff 6650 vsi = NULL;
505682cd 6651 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6652 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6653 vsi = pf->vsi[i];
cbf61325
ASJ		 6654 break;
6655 }
6656 }
6657
6658 /* create a new VSI if none exists */
41c445ff 6659 if (!vsi) {
cbf61325
ASJ		 6660 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6661 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6662 if (!vsi) {
6663 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6664 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6665 return;
41c445ff 6666 }
cbf61325 6667 }
41c445ff 6668
8a9eb7d3 6669 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6670}
6671
6672/**
6673 * i40e_fdir_teardown - release the Flow Director resources
6674 * @pf: board private structure
6675 **/
6676static void i40e_fdir_teardown(struct i40e_pf *pf)
6677{
6678 int i;
6679
17a73f6b 6680 i40e_fdir_filter_exit(pf);
505682cd 6681 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6682 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6683 i40e_vsi_release(pf->vsi[i]);
6684 break;
6685 }
6686 }
6687}
6688
6689/**
f650a38b 6690 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6691 * @pf: board private structure
6692 *
b40c82e6 6693 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6694 **/
23cfbe07 6695static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6696{
41c445ff 6697 struct i40e_hw *hw = &pf->hw;
60442dea 6698 i40e_status ret = 0;
41c445ff
JB		 6699 u32 v;
6700
6701 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6702 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6703 return;
d3ce5734
MW		 6704 if (i40e_check_asq_alive(&pf->hw))
6705 i40e_vc_notify_reset(pf);
41c445ff 6706
69bfb110 6707 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6708
41c445ff
JB		 6709 /* quiesce the VSIs and their queues that are not already DOWN */
6710 i40e_pf_quiesce_all_vsi(pf);
6711
505682cd 6712 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6713 if (pf->vsi[v])
6714 pf->vsi[v]->seid = 0;
6715 }
6716
6717 i40e_shutdown_adminq(&pf->hw);
6718
f650a38b 6719 /* call shutdown HMC */
60442dea
SN		 6720 if (hw->hmc.hmc_obj) {
6721 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6722 if (ret)
60442dea
SN		 6723 dev_warn(&pf->pdev->dev,
6724 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6725 }
f650a38b
ASJ		 6726}
6727
44033fac
JB		 6728/**
6729 * i40e_send_version - update firmware with driver version
6730 * @pf: PF struct
6731 */
6732static void i40e_send_version(struct i40e_pf *pf)
6733{
6734 struct i40e_driver_version dv;
6735
6736 dv.major_version = DRV_VERSION_MAJOR;
6737 dv.minor_version = DRV_VERSION_MINOR;
6738 dv.build_version = DRV_VERSION_BUILD;
6739 dv.subbuild_version = 0;
35a7d804 6740 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6741 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6742}
6743
f650a38b 6744/**
4dda12e6 6745 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6746 * @pf: board private structure
bc7d338f 6747 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6748 **/
bc7d338f 6749static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6750{
f650a38b 6751 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6752 u8 set_fc_aq_fail = 0;
f650a38b 6753 i40e_status ret;
4f2f017c 6754 u32 val;
f650a38b
ASJ		 6755 u32 v;
6756
41c445ff
JB		 6757 /* Now we wait for GRST to settle out.
6758 * We don't have to delete the VEBs or VSIs from the hw switch
6759 * because the reset will make them disappear.
6760 */
6761 ret = i40e_pf_reset(hw);
b5565400 6762 if (ret) {
41c445ff 6763 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6764 set_bit(__I40E_RESET_FAILED, &pf->state);
6765 goto clear_recovery;
b5565400 6766 }
41c445ff
JB		 6767 pf->pfr_count++;
6768
6769 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6770 goto clear_recovery;
69bfb110 6771 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6772
6773 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6774 ret = i40e_init_adminq(&pf->hw);
6775 if (ret) {
f1c7e72e
SN		 6776 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6777 i40e_stat_str(&pf->hw, ret),
6778 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6779 goto clear_recovery;
41c445ff
JB		 6780 }
6781
4eb3f768 6782 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6783 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6784 i40e_verify_eeprom(pf);
4eb3f768 6785
e78ac4bf 6786 i40e_clear_pxe_mode(hw);
41c445ff 6787 ret = i40e_get_capabilities(pf);
f1c7e72e 6788 if (ret)
41c445ff 6789 goto end_core_reset;
41c445ff 6790
41c445ff
JB		 6791 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6792 hw->func_caps.num_rx_qp,
6793 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6794 if (ret) {
6795 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6796 goto end_core_reset;
6797 }
6798 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6799 if (ret) {
6800 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6801 goto end_core_reset;
6802 }
6803
4e3b35b0
NP		 6804#ifdef CONFIG_I40E_DCB
6805 ret = i40e_init_pf_dcb(pf);
6806 if (ret) {
aebfc816
SN		 6807 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6808 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6809 /* Continue without DCB enabled */
4e3b35b0
NP		 6810 }
6811#endif /* CONFIG_I40E_DCB */
38e00438 6812#ifdef I40E_FCOE
21364bcf 6813 i40e_init_pf_fcoe(pf);
4e3b35b0 6814
38e00438 6815#endif
41c445ff 6816 /* do basic switch setup */
bc7d338f 6817 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6818 if (ret)
6819 goto end_core_reset;
6820
2f0aff41
SN		 6821 /* The driver only wants link up/down and module qualification
6822 * reports from firmware. Note the negative logic.
7e2453fe
JB		 6823 */
6824 ret = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41 6825 ~(I40E_AQ_EVENT_LINK_UPDOWN |
867a79e3 6826 I40E_AQ_EVENT_MEDIA_NA |
2f0aff41 6827 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 6828 if (ret)
f1c7e72e
SN		 6829 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6830 i40e_stat_str(&pf->hw, ret),
6831 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6832
cafa2ee6
ASJ		 6833 /* make sure our flow control settings are restored */
6834 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6835 if (ret)
8279e495
NP		 6836 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6837 i40e_stat_str(&pf->hw, ret),
6838 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6839
41c445ff
JB		 6840 /* Rebuild the VSIs and VEBs that existed before reset.
6841 * They are still in our local switch element arrays, so only
6842 * need to rebuild the switch model in the HW.
6843 *
6844 * If there were VEBs but the reconstitution failed, we'll try
6845 * try to recover minimal use by getting the basic PF VSI working.
6846 */
6847 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6848 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6849 /* find the one VEB connected to the MAC, and find orphans */
6850 for (v = 0; v < I40E_MAX_VEB; v++) {
6851 if (!pf->veb[v])
6852 continue;
6853
6854 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6855 pf->veb[v]->uplink_seid == 0) {
6856 ret = i40e_reconstitute_veb(pf->veb[v]);
6857
6858 if (!ret)
6859 continue;
6860
6861 /* If Main VEB failed, we're in deep doodoo,
6862 * so give up rebuilding the switch and set up
6863 * for minimal rebuild of PF VSI.
6864 * If orphan failed, we'll report the error
6865 * but try to keep going.
6866 */
6867 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6868 dev_info(&pf->pdev->dev,
6869 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6870 ret);
6871 pf->vsi[pf->lan_vsi]->uplink_seid
6872 = pf->mac_seid;
6873 break;
6874 } else if (pf->veb[v]->uplink_seid == 0) {
6875 dev_info(&pf->pdev->dev,
6876 "rebuild of orphan VEB failed: %d\n",
6877 ret);
6878 }
6879 }
6880 }
6881 }
6882
6883 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6884 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6885 /* no VEB, so rebuild only the Main VSI */
6886 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6887 if (ret) {
6888 dev_info(&pf->pdev->dev,
6889 "rebuild of Main VSI failed: %d\n", ret);
6890 goto end_core_reset;
6891 }
6892 }
6893
4f2f017c
ASJ		 6894 /* Reconfigure hardware for allowing smaller MSS in the case
6895 * of TSO, so that we avoid the MDD being fired and causing
6896 * a reset in the case of small MSS+TSO.
6897 */
6898#define I40E_REG_MSS 0x000E64DC
6899#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6900#define I40E_64BYTE_MSS 0x400000
6901 val = rd32(hw, I40E_REG_MSS);
6902 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6903 val &= ~I40E_REG_MSS_MIN_MASK;
6904 val |= I40E_64BYTE_MSS;
6905 wr32(hw, I40E_REG_MSS, val);
6906 }
6907
8eed76fa 6908 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 6909 msleep(75);
6910 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6911 if (ret)
f1c7e72e
SN		 6912 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6913 i40e_stat_str(&pf->hw, ret),
6914 i40e_aq_str(&pf->hw,
6915 pf->hw.aq.asq_last_status));
cafa2ee6 6916 }
41c445ff
JB		 6917 /* reinit the misc interrupt */
6918 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6919 ret = i40e_setup_misc_vector(pf);
6920
e7358f54
ASJ		 6921 /* Add a filter to drop all Flow control frames from any VSI from being
6922 * transmitted. By doing so we stop a malicious VF from sending out
6923 * PAUSE or PFC frames and potentially controlling traffic for other
6924 * PF/VF VSIs.
6925 * The FW can still send Flow control frames if enabled.
6926 */
6927 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6928 pf->main_vsi_seid);
6929
41c445ff
JB		 6930 /* restart the VSIs that were rebuilt and running before the reset */
6931 i40e_pf_unquiesce_all_vsi(pf);
6932
69f64b2b
MW		 6933 if (pf->num_alloc_vfs) {
6934 for (v = 0; v < pf->num_alloc_vfs; v++)
6935 i40e_reset_vf(&pf->vf[v], true);
6936 }
6937
41c445ff 6938 /* tell the firmware that we're starting */
44033fac 6939 i40e_send_version(pf);
41c445ff
JB		 6940
6941end_core_reset:
a316f651
ASJ		 6942 clear_bit(__I40E_RESET_FAILED, &pf->state);
6943clear_recovery:
41c445ff
JB		 6944 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6945}
6946
f650a38b 6947/**
b40c82e6 6948 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6949 * @pf: board private structure
6950 *
6951 * Close up the VFs and other things in prep for a Core Reset,
6952 * then get ready to rebuild the world.
6953 **/
6954static void i40e_handle_reset_warning(struct i40e_pf *pf)
6955{
23cfbe07
SN		 6956 i40e_prep_for_reset(pf);
6957 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6958}
6959
41c445ff
JB		 6960/**
6961 * i40e_handle_mdd_event
b40c82e6 6962 * @pf: pointer to the PF structure
41c445ff
JB		 6963 *
6964 * Called from the MDD irq handler to identify possibly malicious vfs
6965 **/
6966static void i40e_handle_mdd_event(struct i40e_pf *pf)
6967{
6968 struct i40e_hw *hw = &pf->hw;
6969 bool mdd_detected = false;
df430b12 6970 bool pf_mdd_detected = false;
41c445ff
JB		 6971 struct i40e_vf *vf;
6972 u32 reg;
6973 int i;
6974
6975 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6976 return;
6977
6978 /* find what triggered the MDD event */
6979 reg = rd32(hw, I40E_GL_MDET_TX);
6980 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6981 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6982 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6983 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6984 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6985 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6986 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6987 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6988 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6989 pf->hw.func_caps.base_queue;
faf32978 6990 if (netif_msg_tx_err(pf))
b40c82e6 6991 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6992 event, queue, pf_num, vf_num);
41c445ff
JB		 6993 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6994 mdd_detected = true;
6995 }
6996 reg = rd32(hw, I40E_GL_MDET_RX);
6997 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6998 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6999 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 7000 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 7001 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 7002 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
7003 I40E_GL_MDET_RX_QUEUE_SHIFT) -
7004 pf->hw.func_caps.base_queue;
faf32978
JB		 7005 if (netif_msg_rx_err(pf))
7006 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
7007 event, queue, func);
41c445ff
JB		 7008 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
7009 mdd_detected = true;
7010 }
7011
df430b12
NP		 7012 if (mdd_detected) {
7013 reg = rd32(hw, I40E_PF_MDET_TX);
7014 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
7015 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 7016 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 7017 pf_mdd_detected = true;
7018 }
7019 reg = rd32(hw, I40E_PF_MDET_RX);
7020 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
7021 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 7022 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 7023 pf_mdd_detected = true;
7024 }
7025 /* Queue belongs to the PF, initiate a reset */
7026 if (pf_mdd_detected) {
7027 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
7028 i40e_service_event_schedule(pf);
7029 }
7030 }
7031
41c445ff
JB		 7032 /* see if one of the VFs needs its hand slapped */
7033 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
7034 vf = &(pf->vf[i]);
7035 reg = rd32(hw, I40E_VP_MDET_TX(i));
7036 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
7037 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
7038 vf->num_mdd_events++;
faf32978
JB		 7039 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
7040 i);
41c445ff
JB		 7041 }
7042
7043 reg = rd32(hw, I40E_VP_MDET_RX(i));
7044 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
7045 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
7046 vf->num_mdd_events++;
faf32978
JB		 7047 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
7048 i);
41c445ff
JB		 7049 }
7050
7051 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
7052 dev_info(&pf->pdev->dev,
7053 "Too many MDD events on VF %d, disabled\n", i);
7054 dev_info(&pf->pdev->dev,
7055 "Use PF Control I/F to re-enable the VF\n");
7056 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
7057 }
7058 }
7059
7060 /* re-enable mdd interrupt cause */
7061 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
7062 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
7063 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
7064 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
7065 i40e_flush(hw);
7066}
7067
a1c9a9d9 7068/**
6a899024 7069 * i40e_sync_udp_filters_subtask - Sync the VSI filter list with HW
a1c9a9d9
JK		 7070 * @pf: board private structure
7071 **/
6a899024 7072static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf)
a1c9a9d9 7073{
a1c9a9d9
JK		 7074 struct i40e_hw *hw = &pf->hw;
7075 i40e_status ret;
a1c9a9d9
JK		 7076 __be16 port;
7077 int i;
7078
6a899024 7079 if (!(pf->flags & I40E_FLAG_UDP_FILTER_SYNC))
a1c9a9d9
JK		 7080 return;
7081
6a899024 7082 pf->flags &= ~I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 7083
7084 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024
SA		 7085 if (pf->pending_udp_bitmap & BIT_ULL(i)) {
7086 pf->pending_udp_bitmap &= ~BIT_ULL(i);
7087 port = pf->udp_ports[i].index;
c22c06c8
SN		 7088 if (port)
7089 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
6a899024 7090 pf->udp_ports[i].type,
c22c06c8
SN		 7091 NULL, NULL);
7092 else
7093 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7094
7095 if (ret) {
730a8f87
CW		 7096 dev_dbg(&pf->pdev->dev,
7097 "%s %s port %d, index %d failed, err %s aq_err %s\n",
7098 pf->udp_ports[i].type ? "vxlan" : "geneve",
7099 port ? "add" : "delete",
7100 ntohs(port), i,
7101 i40e_stat_str(&pf->hw, ret),
7102 i40e_aq_str(&pf->hw,
f1c7e72e 7103 pf->hw.aq.asq_last_status));
6a899024 7104 pf->udp_ports[i].index = 0;
a1c9a9d9
JK		 7105 }
7106 }
7107 }
7108}
7109
41c445ff
JB		 7110/**
7111 * i40e_service_task - Run the driver's async subtasks
7112 * @work: pointer to work_struct containing our data
7113 **/
7114static void i40e_service_task(struct work_struct *work)
7115{
7116 struct i40e_pf *pf = container_of(work,
7117 struct i40e_pf,
7118 service_task);
7119 unsigned long start_time = jiffies;
7120
e57a2fea
SN		 7121 /* don't bother with service tasks if a reset is in progress */
7122 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7123 i40e_service_event_complete(pf);
7124 return;
7125 }
7126
b03a8c1f 7127 i40e_detect_recover_hung(pf);
2818ccd9 7128 i40e_sync_filters_subtask(pf);
41c445ff
JB		 7129 i40e_reset_subtask(pf);
7130 i40e_handle_mdd_event(pf);
7131 i40e_vc_process_vflr_event(pf);
7132 i40e_watchdog_subtask(pf);
7133 i40e_fdir_reinit_subtask(pf);
e3219ce6 7134 i40e_client_subtask(pf);
41c445ff 7135 i40e_sync_filters_subtask(pf);
6a899024 7136 i40e_sync_udp_filters_subtask(pf);
41c445ff
JB		 7137 i40e_clean_adminq_subtask(pf);
7138
7139 i40e_service_event_complete(pf);
7140
7141 /* If the tasks have taken longer than one timer cycle or there
7142 * is more work to be done, reschedule the service task now
7143 * rather than wait for the timer to tick again.
7144 */
7145 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7146 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7147 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7148 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7149 i40e_service_event_schedule(pf);
7150}
7151
7152/**
7153 * i40e_service_timer - timer callback
7154 * @data: pointer to PF struct
7155 **/
7156static void i40e_service_timer(unsigned long data)
7157{
7158 struct i40e_pf *pf = (struct i40e_pf *)data;
7159
7160 mod_timer(&pf->service_timer,
7161 round_jiffies(jiffies + pf->service_timer_period));
7162 i40e_service_event_schedule(pf);
7163}
7164
7165/**
7166 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7167 * @vsi: the VSI being configured
7168 **/
7169static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7170{
7171 struct i40e_pf *pf = vsi->back;
7172
7173 switch (vsi->type) {
7174 case I40E_VSI_MAIN:
7175 vsi->alloc_queue_pairs = pf->num_lan_qps;
7176 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7177 I40E_REQ_DESCRIPTOR_MULTIPLE);
7178 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7179 vsi->num_q_vectors = pf->num_lan_msix;
7180 else
7181 vsi->num_q_vectors = 1;
7182
7183 break;
7184
7185 case I40E_VSI_FDIR:
7186 vsi->alloc_queue_pairs = 1;
7187 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7188 I40E_REQ_DESCRIPTOR_MULTIPLE);
a70e407f 7189 vsi->num_q_vectors = pf->num_fdsb_msix;
41c445ff
JB		 7190 break;
7191
7192 case I40E_VSI_VMDQ2:
7193 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7194 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7195 I40E_REQ_DESCRIPTOR_MULTIPLE);
7196 vsi->num_q_vectors = pf->num_vmdq_msix;
7197 break;
7198
7199 case I40E_VSI_SRIOV:
7200 vsi->alloc_queue_pairs = pf->num_vf_qps;
7201 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7202 I40E_REQ_DESCRIPTOR_MULTIPLE);
7203 break;
7204
38e00438
VD		 7205#ifdef I40E_FCOE
7206 case I40E_VSI_FCOE:
7207 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7208 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7209 I40E_REQ_DESCRIPTOR_MULTIPLE);
7210 vsi->num_q_vectors = pf->num_fcoe_msix;
7211 break;
7212
7213#endif /* I40E_FCOE */
41c445ff
JB		 7214 default:
7215 WARN_ON(1);
7216 return -ENODATA;
7217 }
7218
7219 return 0;
7220}
7221
f650a38b
ASJ		 7222/**
7223 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7224 * @type: VSI pointer
bc7d338f 7225 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7226 *
7227 * On error: returns error code (negative)
7228 * On success: returns 0
7229 **/
bc7d338f 7230static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7231{
7232 int size;
7233 int ret = 0;
7234
ac6c5e3d 7235 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7236 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7237 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7238 if (!vsi->tx_rings)
7239 return -ENOMEM;
f650a38b
ASJ		 7240 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7241
bc7d338f
ASJ		 7242 if (alloc_qvectors) {
7243 /* allocate memory for q_vector pointers */
f57e4fbd 7244 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7245 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7246 if (!vsi->q_vectors) {
7247 ret = -ENOMEM;
7248 goto err_vectors;
7249 }
f650a38b
ASJ		 7250 }
7251 return ret;
7252
7253err_vectors:
7254 kfree(vsi->tx_rings);
7255 return ret;
7256}
7257
41c445ff
JB		 7258/**
7259 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7260 * @pf: board private structure
7261 * @type: type of VSI
7262 *
7263 * On error: returns error code (negative)
7264 * On success: returns vsi index in PF (positive)
7265 **/
7266static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7267{
7268 int ret = -ENODEV;
7269 struct i40e_vsi *vsi;
7270 int vsi_idx;
7271 int i;
7272
7273 /* Need to protect the allocation of the VSIs at the PF level */
7274 mutex_lock(&pf->switch_mutex);
7275
7276 /* VSI list may be fragmented if VSI creation/destruction has
7277 * been happening. We can afford to do a quick scan to look
7278 * for any free VSIs in the list.
7279 *
7280 * find next empty vsi slot, looping back around if necessary
7281 */
7282 i = pf->next_vsi;
505682cd 7283 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7284 i++;
505682cd 7285 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7286 i = 0;
7287 while (i < pf->next_vsi && pf->vsi[i])
7288 i++;
7289 }
7290
505682cd 7291 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7292 vsi_idx = i; /* Found one! */
7293 } else {
7294 ret = -ENODEV;
493fb300 7295 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7296 }
7297 pf->next_vsi = ++i;
7298
7299 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7300 if (!vsi) {
7301 ret = -ENOMEM;
493fb300 7302 goto unlock_pf;
41c445ff
JB		 7303 }
7304 vsi->type = type;
7305 vsi->back = pf;
7306 set_bit(__I40E_DOWN, &vsi->state);
7307 vsi->flags = 0;
7308 vsi->idx = vsi_idx;
ac26fc13 7309 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7310 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7311 pf->rss_table_size : 64;
41c445ff
JB		 7312 vsi->netdev_registered = false;
7313 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7314 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7315 vsi->irqs_ready = false;
41c445ff 7316
9f65e15b
AD		 7317 ret = i40e_set_num_rings_in_vsi(vsi);
7318 if (ret)
7319 goto err_rings;
7320
bc7d338f 7321 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7322 if (ret)
9f65e15b 7323 goto err_rings;
493fb300 7324
41c445ff
JB		 7325 /* Setup default MSIX irq handler for VSI */
7326 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7327
21659035
KP		 7328 /* Initialize VSI lock */
7329 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7330 pf->vsi[vsi_idx] = vsi;
7331 ret = vsi_idx;
493fb300
AD		 7332 goto unlock_pf;
7333
9f65e15b 7334err_rings:
493fb300
AD		 7335 pf->next_vsi = i - 1;
7336 kfree(vsi);
7337unlock_pf:
41c445ff
JB		 7338 mutex_unlock(&pf->switch_mutex);
7339 return ret;
7340}
7341
f650a38b
ASJ		 7342/**
7343 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7344 * @type: VSI pointer
bc7d338f 7345 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7346 *
7347 * On error: returns error code (negative)
7348 * On success: returns 0
7349 **/
bc7d338f 7350static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7351{
7352 /* free the ring and vector containers */
bc7d338f
ASJ		 7353 if (free_qvectors) {
7354 kfree(vsi->q_vectors);
7355 vsi->q_vectors = NULL;
7356 }
f650a38b
ASJ		 7357 kfree(vsi->tx_rings);
7358 vsi->tx_rings = NULL;
7359 vsi->rx_rings = NULL;
7360}
7361
28c5869f
HZ		 7362/**
7363 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7364 * and lookup table
7365 * @vsi: Pointer to VSI structure
7366 */
7367static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7368{
7369 if (!vsi)
7370 return;
7371
7372 kfree(vsi->rss_hkey_user);
7373 vsi->rss_hkey_user = NULL;
7374
7375 kfree(vsi->rss_lut_user);
7376 vsi->rss_lut_user = NULL;
7377}
7378
41c445ff
JB		 7379/**
7380 * i40e_vsi_clear - Deallocate the VSI provided
7381 * @vsi: the VSI being un-configured
7382 **/
7383static int i40e_vsi_clear(struct i40e_vsi *vsi)
7384{
7385 struct i40e_pf *pf;
7386
7387 if (!vsi)
7388 return 0;
7389
7390 if (!vsi->back)
7391 goto free_vsi;
7392 pf = vsi->back;
7393
7394 mutex_lock(&pf->switch_mutex);
7395 if (!pf->vsi[vsi->idx]) {
7396 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7397 vsi->idx, vsi->idx, vsi, vsi->type);
7398 goto unlock_vsi;
7399 }
7400
7401 if (pf->vsi[vsi->idx] != vsi) {
7402 dev_err(&pf->pdev->dev,
7403 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7404 pf->vsi[vsi->idx]->idx,
7405 pf->vsi[vsi->idx],
7406 pf->vsi[vsi->idx]->type,
7407 vsi->idx, vsi, vsi->type);
7408 goto unlock_vsi;
7409 }
7410
b40c82e6 7411 /* updates the PF for this cleared vsi */
41c445ff
JB		 7412 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7413 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7414
bc7d338f 7415 i40e_vsi_free_arrays(vsi, true);
28c5869f 7416 i40e_clear_rss_config_user(vsi);
493fb300 7417
41c445ff
JB		 7418 pf->vsi[vsi->idx] = NULL;
7419 if (vsi->idx < pf->next_vsi)
7420 pf->next_vsi = vsi->idx;
7421
7422unlock_vsi:
7423 mutex_unlock(&pf->switch_mutex);
7424free_vsi:
7425 kfree(vsi);
7426
7427 return 0;
7428}
7429
9f65e15b
AD		 7430/**
7431 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7432 * @vsi: the VSI being cleaned
7433 **/
be1d5eea 7434static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7435{
7436 int i;
7437
8e9dca53 7438 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7439 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7440 kfree_rcu(vsi->tx_rings[i], rcu);
7441 vsi->tx_rings[i] = NULL;
7442 vsi->rx_rings[i] = NULL;
7443 }
be1d5eea 7444 }
9f65e15b
AD		 7445}
7446
41c445ff
JB		 7447/**
7448 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7449 * @vsi: the VSI being configured
7450 **/
7451static int i40e_alloc_rings(struct i40e_vsi *vsi)
7452{
e7046ee1 7453 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7454 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7455 int i;
7456
41c445ff 7457 /* Set basic values in the rings to be used later during open() */
d7397644 7458 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7459 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7460 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7461 if (!tx_ring)
7462 goto err_out;
41c445ff
JB		 7463
7464 tx_ring->queue_index = i;
7465 tx_ring->reg_idx = vsi->base_queue + i;
7466 tx_ring->ring_active = false;
7467 tx_ring->vsi = vsi;
7468 tx_ring->netdev = vsi->netdev;
7469 tx_ring->dev = &pf->pdev->dev;
7470 tx_ring->count = vsi->num_desc;
7471 tx_ring->size = 0;
7472 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7473 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7474 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
a75e8005 7475 tx_ring->tx_itr_setting = pf->tx_itr_default;
9f65e15b 7476 vsi->tx_rings[i] = tx_ring;
41c445ff 7477
9f65e15b 7478 rx_ring = &tx_ring[1];
41c445ff
JB		 7479 rx_ring->queue_index = i;
7480 rx_ring->reg_idx = vsi->base_queue + i;
7481 rx_ring->ring_active = false;
7482 rx_ring->vsi = vsi;
7483 rx_ring->netdev = vsi->netdev;
7484 rx_ring->dev = &pf->pdev->dev;
7485 rx_ring->count = vsi->num_desc;
7486 rx_ring->size = 0;
7487 rx_ring->dcb_tc = 0;
a75e8005 7488 rx_ring->rx_itr_setting = pf->rx_itr_default;
9f65e15b 7489 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7490 }
7491
7492 return 0;
9f65e15b
AD		 7493
7494err_out:
7495 i40e_vsi_clear_rings(vsi);
7496 return -ENOMEM;
41c445ff
JB		 7497}
7498
7499/**
7500 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7501 * @pf: board private structure
7502 * @vectors: the number of MSI-X vectors to request
7503 *
7504 * Returns the number of vectors reserved, or error
7505 **/
7506static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7507{
7b37f376
AG		 7508 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7509 I40E_MIN_MSIX, vectors);
7510 if (vectors < 0) {
41c445ff 7511 dev_info(&pf->pdev->dev,
7b37f376 7512 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7513 vectors = 0;
7514 }
7515
7516 return vectors;
7517}
7518
7519/**
7520 * i40e_init_msix - Setup the MSIX capability
7521 * @pf: board private structure
7522 *
7523 * Work with the OS to set up the MSIX vectors needed.
7524 *
3b444399 7525 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7526 **/
7527static int i40e_init_msix(struct i40e_pf *pf)
7528{
41c445ff 7529 struct i40e_hw *hw = &pf->hw;
1e200e4a 7530 int vectors_left;
41c445ff 7531 int v_budget, i;
3b444399 7532 int v_actual;
e3219ce6 7533 int iwarp_requested = 0;
41c445ff
JB		 7534
7535 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7536 return -ENODEV;
7537
7538 /* The number of vectors we'll request will be comprised of:
7539 * - Add 1 for "other" cause for Admin Queue events, etc.
7540 * - The number of LAN queue pairs
f8ff1464
ASJ		 7541 * - Queues being used for RSS.
7542 * We don't need as many as max_rss_size vectors.
7543 * use rss_size instead in the calculation since that
7544 * is governed by number of cpus in the system.
7545 * - assumes symmetric Tx/Rx pairing
41c445ff 7546 * - The number of VMDq pairs
e3219ce6 7547 * - The CPU count within the NUMA node if iWARP is enabled
38e00438
VD		 7548#ifdef I40E_FCOE
7549 * - The number of FCOE qps.
7550#endif
41c445ff
JB		 7551 * Once we count this up, try the request.
7552 *
7553 * If we can't get what we want, we'll simplify to nearly nothing
7554 * and try again. If that still fails, we punt.
7555 */
1e200e4a
SN		 7556 vectors_left = hw->func_caps.num_msix_vectors;
7557 v_budget = 0;
7558
7559 /* reserve one vector for miscellaneous handler */
7560 if (vectors_left) {
7561 v_budget++;
7562 vectors_left--;
7563 }
7564
7565 /* reserve vectors for the main PF traffic queues */
7566 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7567 vectors_left -= pf->num_lan_msix;
7568 v_budget += pf->num_lan_msix;
7569
7570 /* reserve one vector for sideband flow director */
7571 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7572 if (vectors_left) {
a70e407f 7573 pf->num_fdsb_msix = 1;
1e200e4a
SN		 7574 v_budget++;
7575 vectors_left--;
7576 } else {
a70e407f 7577 pf->num_fdsb_msix = 0;
1e200e4a
SN		 7578 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7579 }
7580 }
83840e4b 7581
38e00438 7582#ifdef I40E_FCOE
1e200e4a 7583 /* can we reserve enough for FCoE? */
38e00438 7584 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7585 if (!vectors_left)
7586 pf->num_fcoe_msix = 0;
7587 else if (vectors_left >= pf->num_fcoe_qps)
7588 pf->num_fcoe_msix = pf->num_fcoe_qps;
7589 else
7590 pf->num_fcoe_msix = 1;
38e00438 7591 v_budget += pf->num_fcoe_msix;
1e200e4a 7592 vectors_left -= pf->num_fcoe_msix;
38e00438 7593 }
1e200e4a 7594
38e00438 7595#endif
e3219ce6
ASJ		 7596 /* can we reserve enough for iWARP? */
7597 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7598 if (!vectors_left)
7599 pf->num_iwarp_msix = 0;
7600 else if (vectors_left < pf->num_iwarp_msix)
7601 pf->num_iwarp_msix = 1;
7602 v_budget += pf->num_iwarp_msix;
7603 vectors_left -= pf->num_iwarp_msix;
7604 }
7605
1e200e4a
SN		 7606 /* any vectors left over go for VMDq support */
7607 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7608 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7609 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7610
7611 /* if we're short on vectors for what's desired, we limit
7612 * the queues per vmdq. If this is still more than are
7613 * available, the user will need to change the number of
7614 * queues/vectors used by the PF later with the ethtool
7615 * channels command
7616 */
7617 if (vmdq_vecs < vmdq_vecs_wanted)
7618 pf->num_vmdq_qps = 1;
7619 pf->num_vmdq_msix = pf->num_vmdq_qps;
7620
7621 v_budget += vmdq_vecs;
7622 vectors_left -= vmdq_vecs;
7623 }
41c445ff
JB		 7624
7625 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7626 GFP_KERNEL);
7627 if (!pf->msix_entries)
7628 return -ENOMEM;
7629
7630 for (i = 0; i < v_budget; i++)
7631 pf->msix_entries[i].entry = i;
3b444399 7632 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7633
3b444399 7634 if (v_actual != v_budget) {
a34977ba
ASJ		 7635 /* If we have limited resources, we will start with no vectors
7636 * for the special features and then allocate vectors to some
7637 * of these features based on the policy and at the end disable
7638 * the features that did not get any vectors.
7639 */
e3219ce6
ASJ		 7640 iwarp_requested = pf->num_iwarp_msix;
7641 pf->num_iwarp_msix = 0;
38e00438
VD		 7642#ifdef I40E_FCOE
7643 pf->num_fcoe_qps = 0;
7644 pf->num_fcoe_msix = 0;
7645#endif
a34977ba
ASJ		 7646 pf->num_vmdq_msix = 0;
7647 }
7648
3b444399 7649 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7650 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7651 kfree(pf->msix_entries);
7652 pf->msix_entries = NULL;
7653 return -ENODEV;
7654
3b444399 7655 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7656 /* Adjust for minimal MSIX use */
41c445ff
JB		 7657 pf->num_vmdq_vsis = 0;
7658 pf->num_vmdq_qps = 0;
41c445ff
JB		 7659 pf->num_lan_qps = 1;
7660 pf->num_lan_msix = 1;
7661
3b444399
SN		 7662 } else if (v_actual != v_budget) {
7663 int vec;
7664
a34977ba 7665 /* reserve the misc vector */
3b444399 7666 vec = v_actual - 1;
a34977ba 7667
41c445ff
JB		 7668 /* Scale vector usage down */
7669 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7670 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7671 pf->num_vmdq_qps = 1;
7672 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7673
7674 /* partition out the remaining vectors */
7675 switch (vec) {
7676 case 2:
41c445ff
JB		 7677 pf->num_lan_msix = 1;
7678 break;
7679 case 3:
e3219ce6
ASJ		 7680 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7681 pf->num_lan_msix = 1;
7682 pf->num_iwarp_msix = 1;
7683 } else {
7684 pf->num_lan_msix = 2;
7685 }
38e00438
VD		 7686#ifdef I40E_FCOE
7687 /* give one vector to FCoE */
7688 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7689 pf->num_lan_msix = 1;
7690 pf->num_fcoe_msix = 1;
7691 }
38e00438 7692#endif
41c445ff
JB		 7693 break;
7694 default:
e3219ce6
ASJ		 7695 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
7696 pf->num_iwarp_msix = min_t(int, (vec / 3),
7697 iwarp_requested);
7698 pf->num_vmdq_vsis = min_t(int, (vec / 3),
7699 I40E_DEFAULT_NUM_VMDQ_VSI);
7700 } else {
7701 pf->num_vmdq_vsis = min_t(int, (vec / 2),
7702 I40E_DEFAULT_NUM_VMDQ_VSI);
7703 }
7704 pf->num_lan_msix = min_t(int,
7705 (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)),
7706 pf->num_lan_msix);
38e00438
VD		 7707#ifdef I40E_FCOE
7708 /* give one vector to FCoE */
7709 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7710 pf->num_fcoe_msix = 1;
7711 vec--;
7712 }
7713#endif
41c445ff
JB		 7714 break;
7715 }
7716 }
7717
a34977ba
ASJ		 7718 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7719 (pf->num_vmdq_msix == 0)) {
7720 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7721 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7722 }
e3219ce6
ASJ		 7723
7724 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
7725 (pf->num_iwarp_msix == 0)) {
7726 dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n");
7727 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
7728 }
38e00438
VD		 7729#ifdef I40E_FCOE
7730
7731 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7732 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7733 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7734 }
7735#endif
3b444399 7736 return v_actual;
41c445ff
JB		 7737}
7738
493fb300 7739/**
90e04070 7740 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7741 * @vsi: the VSI being configured
7742 * @v_idx: index of the vector in the vsi struct
7743 *
7744 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7745 **/
90e04070 7746static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7747{
7748 struct i40e_q_vector *q_vector;
7749
7750 /* allocate q_vector */
7751 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7752 if (!q_vector)
7753 return -ENOMEM;
7754
7755 q_vector->vsi = vsi;
7756 q_vector->v_idx = v_idx;
7757 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7758 if (vsi->netdev)
7759 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7760 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7761
cd0b6fa6
AD		 7762 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7763 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7764
493fb300
AD		 7765 /* tie q_vector and vsi together */
7766 vsi->q_vectors[v_idx] = q_vector;
7767
7768 return 0;
7769}
7770
41c445ff 7771/**
90e04070 7772 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7773 * @vsi: the VSI being configured
7774 *
7775 * We allocate one q_vector per queue interrupt. If allocation fails we
7776 * return -ENOMEM.
7777 **/
90e04070 7778static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7779{
7780 struct i40e_pf *pf = vsi->back;
7781 int v_idx, num_q_vectors;
493fb300 7782 int err;
41c445ff
JB		 7783
7784 /* if not MSIX, give the one vector only to the LAN VSI */
7785 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7786 num_q_vectors = vsi->num_q_vectors;
7787 else if (vsi == pf->vsi[pf->lan_vsi])
7788 num_q_vectors = 1;
7789 else
7790 return -EINVAL;
7791
41c445ff 7792 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7793 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7794 if (err)
7795 goto err_out;
41c445ff
JB		 7796 }
7797
7798 return 0;
493fb300
AD		 7799
7800err_out:
7801 while (v_idx--)
7802 i40e_free_q_vector(vsi, v_idx);
7803
7804 return err;
41c445ff
JB		 7805}
7806
7807/**
7808 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7809 * @pf: board private structure to initialize
7810 **/
c1147280 7811static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7812{
3b444399
SN		 7813 int vectors = 0;
7814 ssize_t size;
41c445ff
JB		 7815
7816 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7817 vectors = i40e_init_msix(pf);
7818 if (vectors < 0) {
60ea5f83 7819 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
e3219ce6 7820 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 7821#ifdef I40E_FCOE
7822 I40E_FLAG_FCOE_ENABLED |
7823#endif
60ea5f83 7824 I40E_FLAG_RSS_ENABLED |
4d9b6043 7825 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7826 I40E_FLAG_SRIOV_ENABLED |
7827 I40E_FLAG_FD_SB_ENABLED |
7828 I40E_FLAG_FD_ATR_ENABLED |
7829 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7830
7831 /* rework the queue expectations without MSIX */
7832 i40e_determine_queue_usage(pf);
7833 }
7834 }
7835
7836 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7837 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7838 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7839 vectors = pci_enable_msi(pf->pdev);
7840 if (vectors < 0) {
7841 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7842 vectors);
41c445ff
JB		 7843 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7844 }
3b444399 7845 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7846 }
7847
958a3e3b 7848 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7849 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7850
3b444399
SN		 7851 /* set up vector assignment tracking */
7852 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7853 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7854 if (!pf->irq_pile) {
7855 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7856 return -ENOMEM;
7857 }
3b444399
SN		 7858 pf->irq_pile->num_entries = vectors;
7859 pf->irq_pile->search_hint = 0;
7860
c1147280 7861 /* track first vector for misc interrupts, ignore return */
3b444399 7862 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7863
7864 return 0;
41c445ff
JB		 7865}
7866
7867/**
7868 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7869 * @pf: board private structure
7870 *
7871 * This sets up the handler for MSIX 0, which is used to manage the
7872 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7873 * when in MSI or Legacy interrupt mode.
7874 **/
7875static int i40e_setup_misc_vector(struct i40e_pf *pf)
7876{
7877 struct i40e_hw *hw = &pf->hw;
7878 int err = 0;
7879
7880 /* Only request the irq if this is the first time through, and
7881 * not when we're rebuilding after a Reset
7882 */
7883 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7884 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7885 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7886 if (err) {
7887 dev_info(&pf->pdev->dev,
77fa28be 7888 "request_irq for %s failed: %d\n",
b294ac70 7889 pf->int_name, err);
41c445ff
JB		 7890 return -EFAULT;
7891 }
7892 }
7893
ab437b5a 7894 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7895
7896 /* associate no queues to the misc vector */
7897 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7898 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7899
7900 i40e_flush(hw);
7901
40d72a50 7902 i40e_irq_dynamic_enable_icr0(pf, true);
41c445ff
JB		 7903
7904 return err;
7905}
7906
7907/**
e25d00b8
ASJ		 7908 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7909 * @vsi: vsi structure
7910 * @seed: RSS hash seed
7911 **/
e69ff813
HZ		 7912static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7913 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7914{
7915 struct i40e_aqc_get_set_rss_key_data rss_key;
7916 struct i40e_pf *pf = vsi->back;
7917 struct i40e_hw *hw = &pf->hw;
7918 bool pf_lut = false;
7919 u8 *rss_lut;
7920 int ret, i;
7921
7922 memset(&rss_key, 0, sizeof(rss_key));
7923 memcpy(&rss_key, seed, sizeof(rss_key));
7924
7925 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7926 if (!rss_lut)
7927 return -ENOMEM;
7928
7929 /* Populate the LUT with max no. of queues in round robin fashion */
7930 for (i = 0; i < vsi->rss_table_size; i++)
7931 rss_lut[i] = i % vsi->rss_size;
7932
7933 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7934 if (ret) {
7935 dev_info(&pf->pdev->dev,
7936 "Cannot set RSS key, err %s aq_err %s\n",
7937 i40e_stat_str(&pf->hw, ret),
7938 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7939 goto config_rss_aq_out;
e25d00b8
ASJ		 7940 }
7941
7942 if (vsi->type == I40E_VSI_MAIN)
7943 pf_lut = true;
7944
7945 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7946 vsi->rss_table_size);
7947 if (ret)
7948 dev_info(&pf->pdev->dev,
7949 "Cannot set RSS lut, err %s aq_err %s\n",
7950 i40e_stat_str(&pf->hw, ret),
7951 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7952
126b63d9
AS		 7953config_rss_aq_out:
7954 kfree(rss_lut);
e25d00b8
ASJ		 7955 return ret;
7956}
7957
7958/**
7959 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7960 * @vsi: VSI structure
7961 **/
7962static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7963{
7964 u8 seed[I40E_HKEY_ARRAY_SIZE];
7965 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 7966 u8 *lut;
7967 int ret;
7968
7969 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
7970 return 0;
7971
7972 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
7973 if (!lut)
7974 return -ENOMEM;
e25d00b8 7975
e69ff813 7976 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 7977 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 7978 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 7979 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
7980 kfree(lut);
e25d00b8 7981
e69ff813 7982 return ret;
e25d00b8
ASJ		 7983}
7984
95a73780
ASJ		 7985/**
7986 * i40e_get_rss_aq - Get RSS keys and lut by using AQ commands
7987 * @vsi: Pointer to vsi structure
7988 * @seed: Buffter to store the hash keys
7989 * @lut: Buffer to store the lookup table entries
7990 * @lut_size: Size of buffer to store the lookup table entries
7991 *
7992 * Return 0 on success, negative on failure
7993 */
7994static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7995 u8 *lut, u16 lut_size)
7996{
7997 struct i40e_pf *pf = vsi->back;
7998 struct i40e_hw *hw = &pf->hw;
7999 int ret = 0;
8000
8001 if (seed) {
8002 ret = i40e_aq_get_rss_key(hw, vsi->id,
8003 (struct i40e_aqc_get_set_rss_key_data *)seed);
8004 if (ret) {
8005 dev_info(&pf->pdev->dev,
8006 "Cannot get RSS key, err %s aq_err %s\n",
8007 i40e_stat_str(&pf->hw, ret),
8008 i40e_aq_str(&pf->hw,
8009 pf->hw.aq.asq_last_status));
8010 return ret;
8011 }
8012 }
8013
8014 if (lut) {
8015 bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false;
8016
8017 ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
8018 if (ret) {
8019 dev_info(&pf->pdev->dev,
8020 "Cannot get RSS lut, err %s aq_err %s\n",
8021 i40e_stat_str(&pf->hw, ret),
8022 i40e_aq_str(&pf->hw,
8023 pf->hw.aq.asq_last_status));
8024 return ret;
8025 }
8026 }
8027
8028 return ret;
8029}
8030
e25d00b8 8031/**
043dd650 8032 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 8033 * @vsi: Pointer to vsi structure
e25d00b8 8034 * @seed: RSS hash seed
e69ff813
HZ		 8035 * @lut: Lookup table
8036 * @lut_size: Lookup table size
8037 *
8038 * Returns 0 on success, negative on failure
41c445ff 8039 **/
e69ff813
HZ		 8040static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
8041 const u8 *lut, u16 lut_size)
41c445ff 8042{
e69ff813 8043 struct i40e_pf *pf = vsi->back;
4617e8c0 8044 struct i40e_hw *hw = &pf->hw;
c4e1868c 8045 u16 vf_id = vsi->vf_id;
e69ff813 8046 u8 i;
41c445ff 8047
e25d00b8 8048 /* Fill out hash function seed */
e69ff813
HZ		 8049 if (seed) {
8050 u32 *seed_dw = (u32 *)seed;
8051
c4e1868c
MW		 8052 if (vsi->type == I40E_VSI_MAIN) {
8053 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
8054 i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i),
8055 seed_dw[i]);
8056 } else if (vsi->type == I40E_VSI_SRIOV) {
8057 for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++)
8058 i40e_write_rx_ctl(hw,
8059 I40E_VFQF_HKEY1(i, vf_id),
8060 seed_dw[i]);
8061 } else {
8062 dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n");
8063 }
e69ff813
HZ		 8064 }
8065
8066 if (lut) {
8067 u32 *lut_dw = (u32 *)lut;
8068
c4e1868c
MW		 8069 if (vsi->type == I40E_VSI_MAIN) {
8070 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8071 return -EINVAL;
8072 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8073 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
8074 } else if (vsi->type == I40E_VSI_SRIOV) {
8075 if (lut_size != I40E_VF_HLUT_ARRAY_SIZE)
8076 return -EINVAL;
8077 for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++)
8078 i40e_write_rx_ctl(hw,
8079 I40E_VFQF_HLUT1(i, vf_id),
8080 lut_dw[i]);
8081 } else {
8082 dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n");
8083 }
e25d00b8
ASJ		 8084 }
8085 i40e_flush(hw);
8086
8087 return 0;
8088}
8089
043dd650
HZ		 8090/**
8091 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
8092 * @vsi: Pointer to VSI structure
8093 * @seed: Buffer to store the keys
8094 * @lut: Buffer to store the lookup table entries
8095 * @lut_size: Size of buffer to store the lookup table entries
8096 *
8097 * Returns 0 on success, negative on failure
8098 */
8099static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
8100 u8 *lut, u16 lut_size)
8101{
8102 struct i40e_pf *pf = vsi->back;
8103 struct i40e_hw *hw = &pf->hw;
8104 u16 i;
8105
8106 if (seed) {
8107 u32 *seed_dw = (u32 *)seed;
8108
8109 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
272cdaf2 8110 seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
043dd650
HZ		 8111 }
8112 if (lut) {
8113 u32 *lut_dw = (u32 *)lut;
8114
8115 if (lut_size != I40E_HLUT_ARRAY_SIZE)
8116 return -EINVAL;
8117 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
8118 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
8119 }
8120
8121 return 0;
8122}
8123
8124/**
8125 * i40e_config_rss - Configure RSS keys and lut
8126 * @vsi: Pointer to VSI structure
8127 * @seed: RSS hash seed
8128 * @lut: Lookup table
8129 * @lut_size: Lookup table size
8130 *
8131 * Returns 0 on success, negative on failure
8132 */
8133int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8134{
8135 struct i40e_pf *pf = vsi->back;
8136
8137 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8138 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
8139 else
8140 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
8141}
8142
8143/**
8144 * i40e_get_rss - Get RSS keys and lut
8145 * @vsi: Pointer to VSI structure
8146 * @seed: Buffer to store the keys
8147 * @lut: Buffer to store the lookup table entries
8148 * lut_size: Size of buffer to store the lookup table entries
8149 *
8150 * Returns 0 on success, negative on failure
8151 */
8152int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
8153{
95a73780
ASJ		 8154 struct i40e_pf *pf = vsi->back;
8155
8156 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
8157 return i40e_get_rss_aq(vsi, seed, lut, lut_size);
8158 else
8159 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
043dd650
HZ		 8160}
8161
e69ff813
HZ		 8162/**
8163 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
8164 * @pf: Pointer to board private structure
8165 * @lut: Lookup table
8166 * @rss_table_size: Lookup table size
8167 * @rss_size: Range of queue number for hashing
8168 */
8169static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
8170 u16 rss_table_size, u16 rss_size)
8171{
8172 u16 i;
8173
8174 for (i = 0; i < rss_table_size; i++)
8175 lut[i] = i % rss_size;
8176}
8177
e25d00b8 8178/**
043dd650 8179 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8180 * @pf: board private structure
8181 **/
043dd650 8182static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8183{
8184 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8185 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8186 u8 *lut;
e25d00b8
ASJ		 8187 struct i40e_hw *hw = &pf->hw;
8188 u32 reg_val;
8189 u64 hena;
e69ff813 8190 int ret;
e25d00b8 8191
41c445ff 8192 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
272cdaf2
SN		 8193 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
8194 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8195 hena |= i40e_pf_get_default_rss_hena(pf);
8196
272cdaf2
SN		 8197 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
8198 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
41c445ff 8199
e25d00b8 8200 /* Determine the RSS table size based on the hardware capabilities */
272cdaf2 8201 reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8202 reg_val = (pf->rss_table_size == 512) ?
8203 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8204 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
272cdaf2 8205 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);
e157ea30 8206
28c5869f
HZ		 8207 /* Determine the RSS size of the VSI */
8208 if (!vsi->rss_size)
acd65448
HZ		 8209 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8210 vsi->num_queue_pairs);
28c5869f 8211
e69ff813
HZ		 8212 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8213 if (!lut)
8214 return -ENOMEM;
8215
28c5869f
HZ		 8216 /* Use user configured lut if there is one, otherwise use default */
8217 if (vsi->rss_lut_user)
8218 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8219 else
8220 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8221
28c5869f
HZ		 8222 /* Use user configured hash key if there is one, otherwise
8223 * use default.
8224 */
8225 if (vsi->rss_hkey_user)
8226 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8227 else
8228 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8229 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8230 kfree(lut);
8231
8232 return ret;
41c445ff
JB		 8233}
8234
f8ff1464
ASJ		 8235/**
8236 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8237 * @pf: board private structure
8238 * @queue_count: the requested queue count for rss.
8239 *
8240 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8241 * count which may be different from the requested queue count.
8242 **/
8243int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8244{
9a3bd2f1
ASJ		 8245 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8246 int new_rss_size;
8247
f8ff1464
ASJ		 8248 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8249 return 0;
8250
9a3bd2f1 8251 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8252
9a3bd2f1
ASJ		 8253 if (queue_count != vsi->num_queue_pairs) {
8254 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8255 i40e_prep_for_reset(pf);
8256
acd65448 8257 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8258
8259 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8260
8261 /* Discard the user configured hash keys and lut, if less
8262 * queues are enabled.
8263 */
8264 if (queue_count < vsi->rss_size) {
8265 i40e_clear_rss_config_user(vsi);
8266 dev_dbg(&pf->pdev->dev,
8267 "discard user configured hash keys and lut\n");
8268 }
8269
8270 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8271 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8272 vsi->num_queue_pairs);
28c5869f 8273
043dd650 8274 i40e_pf_config_rss(pf);
f8ff1464 8275 }
e36b0b11
HZ		 8276 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8277 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8278 return pf->alloc_rss_size;
f8ff1464
ASJ		 8279}
8280
f4492db1
GR		 8281/**
8282 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8283 * @pf: board private structure
8284 **/
8285i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8286{
8287 i40e_status status;
8288 bool min_valid, max_valid;
8289 u32 max_bw, min_bw;
8290
8291 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8292 &min_valid, &max_valid);
8293
8294 if (!status) {
8295 if (min_valid)
8296 pf->npar_min_bw = min_bw;
8297 if (max_valid)
8298 pf->npar_max_bw = max_bw;
8299 }
8300
8301 return status;
8302}
8303
8304/**
8305 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8306 * @pf: board private structure
8307 **/
8308i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8309{
8310 struct i40e_aqc_configure_partition_bw_data bw_data;
8311 i40e_status status;
8312
b40c82e6 8313 /* Set the valid bit for this PF */
41a1d04b 8314 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8315 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8316 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8317
8318 /* Set the new bandwidths */
8319 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8320
8321 return status;
8322}
8323
8324/**
8325 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8326 * @pf: board private structure
8327 **/
8328i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8329{
8330 /* Commit temporary BW setting to permanent NVM image */
8331 enum i40e_admin_queue_err last_aq_status;
8332 i40e_status ret;
8333 u16 nvm_word;
8334
8335 if (pf->hw.partition_id != 1) {
8336 dev_info(&pf->pdev->dev,
8337 "Commit BW only works on partition 1! This is partition %d",
8338 pf->hw.partition_id);
8339 ret = I40E_NOT_SUPPORTED;
8340 goto bw_commit_out;
8341 }
8342
8343 /* Acquire NVM for read access */
8344 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8345 last_aq_status = pf->hw.aq.asq_last_status;
8346 if (ret) {
8347 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8348 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8349 i40e_stat_str(&pf->hw, ret),
8350 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8351 goto bw_commit_out;
8352 }
8353
8354 /* Read word 0x10 of NVM - SW compatibility word 1 */
8355 ret = i40e_aq_read_nvm(&pf->hw,
8356 I40E_SR_NVM_CONTROL_WORD,
8357 0x10, sizeof(nvm_word), &nvm_word,
8358 false, NULL);
8359 /* Save off last admin queue command status before releasing
8360 * the NVM
8361 */
8362 last_aq_status = pf->hw.aq.asq_last_status;
8363 i40e_release_nvm(&pf->hw);
8364 if (ret) {
f1c7e72e
SN		 8365 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8366 i40e_stat_str(&pf->hw, ret),
8367 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8368 goto bw_commit_out;
8369 }
8370
8371 /* Wait a bit for NVM release to complete */
8372 msleep(50);
8373
8374 /* Acquire NVM for write access */
8375 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8376 last_aq_status = pf->hw.aq.asq_last_status;
8377 if (ret) {
8378 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8379 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8380 i40e_stat_str(&pf->hw, ret),
8381 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8382 goto bw_commit_out;
8383 }
8384 /* Write it back out unchanged to initiate update NVM,
8385 * which will force a write of the shadow (alt) RAM to
8386 * the NVM - thus storing the bandwidth values permanently.
8387 */
8388 ret = i40e_aq_update_nvm(&pf->hw,
8389 I40E_SR_NVM_CONTROL_WORD,
8390 0x10, sizeof(nvm_word),
8391 &nvm_word, true, NULL);
8392 /* Save off last admin queue command status before releasing
8393 * the NVM
8394 */
8395 last_aq_status = pf->hw.aq.asq_last_status;
8396 i40e_release_nvm(&pf->hw);
8397 if (ret)
8398 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8399 "BW settings NOT SAVED, err %s aq_err %s\n",
8400 i40e_stat_str(&pf->hw, ret),
8401 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8402bw_commit_out:
8403
8404 return ret;
8405}
8406
41c445ff
JB		 8407/**
8408 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8409 * @pf: board private structure to initialize
8410 *
8411 * i40e_sw_init initializes the Adapter private data structure.
8412 * Fields are initialized based on PCI device information and
8413 * OS network device settings (MTU size).
8414 **/
8415static int i40e_sw_init(struct i40e_pf *pf)
8416{
8417 int err = 0;
8418 int size;
8419
8420 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8421 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
8422 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8423 if (I40E_DEBUG_USER & debug)
8424 pf->hw.debug_mask = debug;
8425 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8426 I40E_DEFAULT_MSG_ENABLE);
8427 }
8428
8429 /* Set default capability flags */
8430 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8431 I40E_FLAG_MSI_ENABLED |
2bc7ee8a
MW		 8432 I40E_FLAG_MSIX_ENABLED;
8433
ca99eb99
MW		 8434 /* Set default ITR */
8435 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8436 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8437
7134f9ce
JB		 8438 /* Depending on PF configurations, it is possible that the RSS
8439 * maximum might end up larger than the available queues
8440 */
41a1d04b 8441 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8442 pf->alloc_rss_size = 1;
5db4cb59 8443 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8444 pf->rss_size_max = min_t(int, pf->rss_size_max,
8445 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8446 if (pf->hw.func_caps.rss) {
8447 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8448 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8449 num_online_cpus());
41c445ff
JB		 8450 }
8451
2050bc65 8452 /* MFP mode enabled */
c78b953e 8453 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8454 pf->flags |= I40E_FLAG_MFP_ENABLED;
8455 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8456 if (i40e_get_npar_bw_setting(pf))
8457 dev_warn(&pf->pdev->dev,
8458 "Could not get NPAR bw settings\n");
8459 else
8460 dev_info(&pf->pdev->dev,
8461 "Min BW = %8.8x, Max BW = %8.8x\n",
8462 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8463 }
8464
cbf61325
ASJ		 8465 /* FW/NVM is not yet fixed in this regard */
8466 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8467 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8468 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8469 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8470 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8471 pf->hw.num_partitions > 1)
cbf61325 8472 dev_info(&pf->pdev->dev,
0b67584f 8473 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8474 else
8475 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8476 pf->fdir_pf_filter_count =
8477 pf->hw.func_caps.fd_filters_guaranteed;
8478 pf->hw.fdir_shared_filter_count =
8479 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8480 }
8481
f1bbad33 8482 if (i40e_is_mac_710(&pf->hw) &&
8eed76fa 8483 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
f1bbad33 8484 (pf->hw.aq.fw_maj_ver < 4))) {
8eed76fa 8485 pf->flags |= I40E_FLAG_RESTART_AUTONEG;
f1bbad33
NP		 8486 /* No DCB support for FW < v4.33 */
8487 pf->flags |= I40E_FLAG_NO_DCB_SUPPORT;
8488 }
8489
8490 /* Disable FW LLDP if FW < v4.3 */
8491 if (i40e_is_mac_710(&pf->hw) &&
8492 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
8493 (pf->hw.aq.fw_maj_ver < 4)))
8494 pf->flags |= I40E_FLAG_STOP_FW_LLDP;
8495
8496 /* Use the FW Set LLDP MIB API if FW > v4.40 */
8497 if (i40e_is_mac_710(&pf->hw) &&
8498 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) ||
8499 (pf->hw.aq.fw_maj_ver >= 5)))
8500 pf->flags |= I40E_FLAG_USE_SET_LLDP_MIB;
8eed76fa 8501
41c445ff 8502 if (pf->hw.func_caps.vmdq) {
41c445ff 8503 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8504 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8505 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8506 }
8507
e3219ce6
ASJ		 8508 if (pf->hw.func_caps.iwarp) {
8509 pf->flags |= I40E_FLAG_IWARP_ENABLED;
8510 /* IWARP needs one extra vector for CQP just like MISC.*/
8511 pf->num_iwarp_msix = (int)num_online_cpus() + 1;
8512 }
8513
38e00438 8514#ifdef I40E_FCOE
21364bcf 8515 i40e_init_pf_fcoe(pf);
38e00438
VD		 8516
8517#endif /* I40E_FCOE */
41c445ff 8518#ifdef CONFIG_PCI_IOV
ba252f13 8519 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8520 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8521 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8522 pf->num_req_vfs = min_t(int,
8523 pf->hw.func_caps.num_vfs,
8524 I40E_MAX_VF_COUNT);
8525 }
8526#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8527 if (pf->hw.mac.type == I40E_MAC_X722) {
8528 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8529 I40E_FLAG_128_QP_RSS_CAPABLE |
8530 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8531 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8532 I40E_FLAG_WB_ON_ITR_CAPABLE |
6a899024 8533 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE |
8e2cc0e6 8534 I40E_FLAG_NO_PCI_LINK_CHECK |
f8db54cc 8535 I40E_FLAG_100M_SGMII_CAPABLE |
f1bbad33 8536 I40E_FLAG_USE_SET_LLDP_MIB |
6a899024 8537 I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
a340c789
AS		 8538 } else if ((pf->hw.aq.api_maj_ver > 1) ||
8539 ((pf->hw.aq.api_maj_ver == 1) &&
8540 (pf->hw.aq.api_min_ver > 4))) {
8541 /* Supported in FW API version higher than 1.4 */
8542 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
72b74869
ASJ		 8543 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
8544 } else {
8545 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
d502ce01 8546 }
a340c789 8547
41c445ff
JB		 8548 pf->eeprom_version = 0xDEAD;
8549 pf->lan_veb = I40E_NO_VEB;
8550 pf->lan_vsi = I40E_NO_VSI;
8551
d1a8d275
ASJ		 8552 /* By default FW has this off for performance reasons */
8553 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8554
41c445ff
JB		 8555 /* set up queue assignment tracking */
8556 size = sizeof(struct i40e_lump_tracking)
8557 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8558 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8559 if (!pf->qp_pile) {
8560 err = -ENOMEM;
8561 goto sw_init_done;
8562 }
8563 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8564 pf->qp_pile->search_hint = 0;
8565
327fe04b
ASJ		 8566 pf->tx_timeout_recovery_level = 1;
8567
41c445ff
JB		 8568 mutex_init(&pf->switch_mutex);
8569
c668a12c
GR		 8570 /* If NPAR is enabled nudge the Tx scheduler */
8571 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8572 i40e_set_npar_bw_setting(pf);
8573
41c445ff
JB		 8574sw_init_done:
8575 return err;
8576}
8577
7c3c288b
ASJ		 8578/**
8579 * i40e_set_ntuple - set the ntuple feature flag and take action
8580 * @pf: board private structure to initialize
8581 * @features: the feature set that the stack is suggesting
8582 *
8583 * returns a bool to indicate if reset needs to happen
8584 **/
8585bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8586{
8587 bool need_reset = false;
8588
8589 /* Check if Flow Director n-tuple support was enabled or disabled. If
8590 * the state changed, we need to reset.
8591 */
8592 if (features & NETIF_F_NTUPLE) {
8593 /* Enable filters and mark for reset */
8594 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8595 need_reset = true;
a70e407f
TD		 8596 /* enable FD_SB only if there is MSI-X vector */
8597 if (pf->num_fdsb_msix > 0)
8598 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7c3c288b
ASJ		 8599 } else {
8600 /* turn off filters, mark for reset and clear SW filter list */
8601 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8602 need_reset = true;
8603 i40e_fdir_filter_exit(pf);
8604 }
8605 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8606 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8607 /* reset fd counters */
8608 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8609 pf->fdir_pf_active_filters = 0;
8610 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8611 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8612 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8613 /* if ATR was auto disabled it can be re-enabled. */
8614 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8615 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8616 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8617 }
8618 return need_reset;
8619}
8620
41c445ff
JB		 8621/**
8622 * i40e_set_features - set the netdev feature flags
8623 * @netdev: ptr to the netdev being adjusted
8624 * @features: the feature set that the stack is suggesting
8625 **/
8626static int i40e_set_features(struct net_device *netdev,
8627 netdev_features_t features)
8628{
8629 struct i40e_netdev_priv *np = netdev_priv(netdev);
8630 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8631 struct i40e_pf *pf = vsi->back;
8632 bool need_reset;
41c445ff
JB		 8633
8634 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8635 i40e_vlan_stripping_enable(vsi);
8636 else
8637 i40e_vlan_stripping_disable(vsi);
8638
7c3c288b
ASJ		 8639 need_reset = i40e_set_ntuple(pf, features);
8640
8641 if (need_reset)
41a1d04b 8642 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8643
41c445ff
JB		 8644 return 0;
8645}
8646
a1c9a9d9 8647/**
6a899024 8648 * i40e_get_udp_port_idx - Lookup a possibly offloaded for Rx UDP port
a1c9a9d9
JK		 8649 * @pf: board private structure
8650 * @port: The UDP port to look up
8651 *
8652 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8653 **/
6a899024 8654static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, __be16 port)
a1c9a9d9
JK		 8655{
8656 u8 i;
8657
8658 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
6a899024 8659 if (pf->udp_ports[i].index == port)
a1c9a9d9
JK		 8660 return i;
8661 }
8662
8663 return i;
8664}
8665
8666/**
06a5f7f1 8667 * i40e_udp_tunnel_add - Get notifications about UDP tunnel ports that come up
a1c9a9d9 8668 * @netdev: This physical port's netdev
06a5f7f1 8669 * @ti: Tunnel endpoint information
a1c9a9d9 8670 **/
06a5f7f1
AD		 8671static void i40e_udp_tunnel_add(struct net_device *netdev,
8672 struct udp_tunnel_info *ti)
a1c9a9d9
JK		 8673{
8674 struct i40e_netdev_priv *np = netdev_priv(netdev);
8675 struct i40e_vsi *vsi = np->vsi;
8676 struct i40e_pf *pf = vsi->back;
06a5f7f1 8677 __be16 port = ti->port;
a1c9a9d9
JK		 8678 u8 next_idx;
8679 u8 idx;
8680
6a899024 8681 idx = i40e_get_udp_port_idx(pf, port);
a1c9a9d9
JK		 8682
8683 /* Check if port already exists */
8684 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
06a5f7f1 8685 netdev_info(netdev, "port %d already offloaded\n",
c22c06c8 8686 ntohs(port));
a1c9a9d9
JK		 8687 return;
8688 }
8689
8690 /* Now check if there is space to add the new port */
6a899024 8691 next_idx = i40e_get_udp_port_idx(pf, 0);
a1c9a9d9
JK		 8692
8693 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
06a5f7f1 8694 netdev_info(netdev, "maximum number of offloaded UDP ports reached, not adding port %d\n",
6a899024
SA		 8695 ntohs(port));
8696 return;
8697 }
8698
06a5f7f1
AD		 8699 switch (ti->type) {
8700 case UDP_TUNNEL_TYPE_VXLAN:
8701 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN;
8702 break;
8703 case UDP_TUNNEL_TYPE_GENEVE:
8704 if (!(pf->flags & I40E_FLAG_GENEVE_OFFLOAD_CAPABLE))
8705 return;
8706 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE;
8707 break;
8708 default:
6a899024
SA		 8709 return;
8710 }
8711
8712 /* New port: add it and mark its index in the bitmap */
8713 pf->udp_ports[next_idx].index = port;
6a899024
SA		 8714 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
8715 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
a1c9a9d9
JK		 8716}
8717
6a899024 8718/**
06a5f7f1 8719 * i40e_udp_tunnel_del - Get notifications about UDP tunnel ports that go away
6a899024 8720 * @netdev: This physical port's netdev
06a5f7f1 8721 * @ti: Tunnel endpoint information
6a899024 8722 **/
06a5f7f1
AD		 8723static void i40e_udp_tunnel_del(struct net_device *netdev,
8724 struct udp_tunnel_info *ti)
6a899024 8725{
6a899024
SA		 8726 struct i40e_netdev_priv *np = netdev_priv(netdev);
8727 struct i40e_vsi *vsi = np->vsi;
8728 struct i40e_pf *pf = vsi->back;
06a5f7f1 8729 __be16 port = ti->port;
6a899024
SA		 8730 u8 idx;
8731
6a899024
SA		 8732 idx = i40e_get_udp_port_idx(pf, port);
8733
8734 /* Check if port already exists */
06a5f7f1
AD		 8735 if (idx >= I40E_MAX_PF_UDP_OFFLOAD_PORTS)
8736 goto not_found;
6a899024 8737
06a5f7f1
AD		 8738 switch (ti->type) {
8739 case UDP_TUNNEL_TYPE_VXLAN:
8740 if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_VXLAN)
8741 goto not_found;
8742 break;
8743 case UDP_TUNNEL_TYPE_GENEVE:
8744 if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_NGE)
8745 goto not_found;
8746 break;
8747 default:
8748 goto not_found;
6a899024 8749 }
06a5f7f1
AD		 8750
8751 /* if port exists, set it to 0 (mark for deletion)
8752 * and make it pending
8753 */
8754 pf->udp_ports[idx].index = 0;
8755 pf->pending_udp_bitmap |= BIT_ULL(idx);
8756 pf->flags |= I40E_FLAG_UDP_FILTER_SYNC;
8757
8758 return;
8759not_found:
8760 netdev_warn(netdev, "UDP port %d was not found, not deleting\n",
8761 ntohs(port));
6a899024
SA		 8762}
8763
1f224ad2 8764static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8765 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8766{
8767 struct i40e_netdev_priv *np = netdev_priv(netdev);
8768 struct i40e_pf *pf = np->vsi->back;
8769 struct i40e_hw *hw = &pf->hw;
8770
8771 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8772 return -EOPNOTSUPP;
8773
8774 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8775 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8776
8777 return 0;
8778}
8779
2f90ade6
JB		 8780/**
8781 * i40e_ndo_fdb_add - add an entry to the hardware database
8782 * @ndm: the input from the stack
8783 * @tb: pointer to array of nladdr (unused)
8784 * @dev: the net device pointer
8785 * @addr: the MAC address entry being added
8786 * @flags: instructions from stack about fdb operation
8787 */
4ba0dea5
GR		 8788static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8789 struct net_device *dev,
f6f6424b 8790 const unsigned char *addr, u16 vid,
4ba0dea5 8791 u16 flags)
4ba0dea5
GR		 8792{
8793 struct i40e_netdev_priv *np = netdev_priv(dev);
8794 struct i40e_pf *pf = np->vsi->back;
8795 int err = 0;
8796
8797 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8798 return -EOPNOTSUPP;
8799
65891fea
OG		 8800 if (vid) {
8801 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8802 return -EINVAL;
8803 }
8804
4ba0dea5
GR		 8805 /* Hardware does not support aging addresses so if a
8806 * ndm_state is given only allow permanent addresses
8807 */
8808 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8809 netdev_info(dev, "FDB only supports static addresses\n");
8810 return -EINVAL;
8811 }
8812
8813 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8814 err = dev_uc_add_excl(dev, addr);
8815 else if (is_multicast_ether_addr(addr))
8816 err = dev_mc_add_excl(dev, addr);
8817 else
8818 err = -EINVAL;
8819
8820 /* Only return duplicate errors if NLM_F_EXCL is set */
8821 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8822 err = 0;
8823
8824 return err;
8825}
8826
51616018
NP		 8827/**
8828 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8829 * @dev: the netdev being configured
8830 * @nlh: RTNL message
8831 *
8832 * Inserts a new hardware bridge if not already created and
8833 * enables the bridging mode requested (VEB or VEPA). If the
8834 * hardware bridge has already been inserted and the request
8835 * is to change the mode then that requires a PF reset to
8836 * allow rebuild of the components with required hardware
8837 * bridge mode enabled.
8838 **/
8839static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8840 struct nlmsghdr *nlh,
8841 u16 flags)
51616018
NP		 8842{
8843 struct i40e_netdev_priv *np = netdev_priv(dev);
8844 struct i40e_vsi *vsi = np->vsi;
8845 struct i40e_pf *pf = vsi->back;
8846 struct i40e_veb *veb = NULL;
8847 struct nlattr *attr, *br_spec;
8848 int i, rem;
8849
8850 /* Only for PF VSI for now */
8851 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8852 return -EOPNOTSUPP;
8853
8854 /* Find the HW bridge for PF VSI */
8855 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8856 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8857 veb = pf->veb[i];
8858 }
8859
8860 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8861
8862 nla_for_each_nested(attr, br_spec, rem) {
8863 __u16 mode;
8864
8865 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8866 continue;
8867
8868 mode = nla_get_u16(attr);
8869 if ((mode != BRIDGE_MODE_VEPA) &&
8870 (mode != BRIDGE_MODE_VEB))
8871 return -EINVAL;
8872
8873 /* Insert a new HW bridge */
8874 if (!veb) {
8875 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8876 vsi->tc_config.enabled_tc);
8877 if (veb) {
8878 veb->bridge_mode = mode;
8879 i40e_config_bridge_mode(veb);
8880 } else {
8881 /* No Bridge HW offload available */
8882 return -ENOENT;
8883 }
8884 break;
8885 } else if (mode != veb->bridge_mode) {
8886 /* Existing HW bridge but different mode needs reset */
8887 veb->bridge_mode = mode;
fc60861e
ASJ		 8888 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8889 if (mode == BRIDGE_MODE_VEB)
8890 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8891 else
8892 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8893 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8894 break;
8895 }
8896 }
8897
8898 return 0;
8899}
8900
8901/**
8902 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8903 * @skb: skb buff
8904 * @pid: process id
8905 * @seq: RTNL message seq #
8906 * @dev: the netdev being configured
8907 * @filter_mask: unused
d4b2f9fe 8908 * @nlflags: netlink flags passed in
51616018
NP		 8909 *
8910 * Return the mode in which the hardware bridge is operating in
8911 * i.e VEB or VEPA.
8912 **/
51616018
NP		 8913static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8914 struct net_device *dev,
9f4ffc44
CW		 8915 u32 __always_unused filter_mask,
8916 int nlflags)
51616018
NP		 8917{
8918 struct i40e_netdev_priv *np = netdev_priv(dev);
8919 struct i40e_vsi *vsi = np->vsi;
8920 struct i40e_pf *pf = vsi->back;
8921 struct i40e_veb *veb = NULL;
8922 int i;
8923
8924 /* Only for PF VSI for now */
8925 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8926 return -EOPNOTSUPP;
8927
8928 /* Find the HW bridge for the PF VSI */
8929 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8930 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8931 veb = pf->veb[i];
8932 }
8933
8934 if (!veb)
8935 return 0;
8936
46c264da 8937 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8938 nlflags, 0, 0, filter_mask, NULL);
51616018 8939}
51616018 8940
6a899024
SA		 8941/* Hardware supports L4 tunnel length of 128B (=2^7) which includes
8942 * inner mac plus all inner ethertypes.
8943 */
8944#define I40E_MAX_TUNNEL_HDR_LEN 128
f44a75e2
JS		 8945/**
8946 * i40e_features_check - Validate encapsulated packet conforms to limits
8947 * @skb: skb buff
2bc11c63 8948 * @dev: This physical port's netdev
f44a75e2
JS		 8949 * @features: Offload features that the stack believes apply
8950 **/
8951static netdev_features_t i40e_features_check(struct sk_buff *skb,
8952 struct net_device *dev,
8953 netdev_features_t features)
8954{
8955 if (skb->encapsulation &&
6a899024 8956 ((skb_inner_network_header(skb) - skb_transport_header(skb)) >
f44a75e2 8957 I40E_MAX_TUNNEL_HDR_LEN))
a188222b 8958 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
f44a75e2
JS		 8959
8960 return features;
8961}
8962
37a2973a 8963static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8964 .ndo_open = i40e_open,
8965 .ndo_stop = i40e_close,
8966 .ndo_start_xmit = i40e_lan_xmit_frame,
8967 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8968 .ndo_set_rx_mode = i40e_set_rx_mode,
8969 .ndo_validate_addr = eth_validate_addr,
8970 .ndo_set_mac_address = i40e_set_mac,
8971 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8972 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8973 .ndo_tx_timeout = i40e_tx_timeout,
8974 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8975 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8976#ifdef CONFIG_NET_POLL_CONTROLLER
8977 .ndo_poll_controller = i40e_netpoll,
8978#endif
e4c6734e 8979 .ndo_setup_tc = __i40e_setup_tc,
38e00438
VD		 8980#ifdef I40E_FCOE
8981 .ndo_fcoe_enable = i40e_fcoe_enable,
8982 .ndo_fcoe_disable = i40e_fcoe_disable,
8983#endif
41c445ff
JB		 8984 .ndo_set_features = i40e_set_features,
8985 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8986 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8987 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8988 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8989 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8990 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
c3bbbd20 8991 .ndo_set_vf_trust = i40e_ndo_set_vf_trust,
06a5f7f1
AD		 8992 .ndo_udp_tunnel_add = i40e_udp_tunnel_add,
8993 .ndo_udp_tunnel_del = i40e_udp_tunnel_del,
1f224ad2 8994 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8995 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8996 .ndo_features_check = i40e_features_check,
51616018
NP		 8997 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8998 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8999};
9000
9001/**
9002 * i40e_config_netdev - Setup the netdev flags
9003 * @vsi: the VSI being configured
9004 *
9005 * Returns 0 on success, negative value on failure
9006 **/
9007static int i40e_config_netdev(struct i40e_vsi *vsi)
9008{
1a10370a 9009 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 9010 struct i40e_pf *pf = vsi->back;
9011 struct i40e_hw *hw = &pf->hw;
9012 struct i40e_netdev_priv *np;
9013 struct net_device *netdev;
9014 u8 mac_addr[ETH_ALEN];
9015 int etherdev_size;
9016
9017 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 9018 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 9019 if (!netdev)
9020 return -ENOMEM;
9021
9022 vsi->netdev = netdev;
9023 np = netdev_priv(netdev);
9024 np->vsi = vsi;
9025
b0fe3306
AD		 9026 netdev->hw_enc_features |= NETIF_F_SG |
9027 NETIF_F_IP_CSUM |
9028 NETIF_F_IPV6_CSUM |
9029 NETIF_F_HIGHDMA |
9030 NETIF_F_SOFT_FEATURES |
9031 NETIF_F_TSO |
9032 NETIF_F_TSO_ECN |
9033 NETIF_F_TSO6 |
9034 NETIF_F_GSO_GRE |
1c7b4a23 9035 NETIF_F_GSO_GRE_CSUM |
7e13318d 9036 NETIF_F_GSO_IPXIP4 |
bf2d1df3 9037 NETIF_F_GSO_IPXIP6 |
b0fe3306
AD		 9038 NETIF_F_GSO_UDP_TUNNEL |
9039 NETIF_F_GSO_UDP_TUNNEL_CSUM |
1c7b4a23 9040 NETIF_F_GSO_PARTIAL |
b0fe3306
AD		 9041 NETIF_F_SCTP_CRC |
9042 NETIF_F_RXHASH |
9043 NETIF_F_RXCSUM |
5afdaaa0 9044 0;
41c445ff 9045
b0fe3306 9046 if (!(pf->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE))
1c7b4a23
AD		 9047 netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
9048
9049 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
b0fe3306
AD		 9050
9051 /* record features VLANs can make use of */
1c7b4a23
AD		 9052 netdev->vlan_features |= netdev->hw_enc_features |
9053 NETIF_F_TSO_MANGLEID;
41c445ff 9054
2e86a0b6 9055 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
b0fe3306
AD		 9056 netdev->hw_features |= NETIF_F_NTUPLE;
9057
9058 netdev->hw_features |= netdev->hw_enc_features |
9059 NETIF_F_HW_VLAN_CTAG_TX |
9060 NETIF_F_HW_VLAN_CTAG_RX;
2e86a0b6 9061
b0fe3306 9062 netdev->features |= netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
1c7b4a23 9063 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
41c445ff
JB		 9064
9065 if (vsi->type == I40E_VSI_MAIN) {
9066 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 9067 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 9068 /* The following steps are necessary to prevent reception
9069 * of tagged packets - some older NVM configurations load a
9070 * default a MAC-VLAN filter that accepts any tagged packet
9071 * which must be replaced by a normal filter.
8c27d42e 9072 */
21659035
KP		 9073 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
9074 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 9075 i40e_add_filter(vsi, mac_addr,
9076 I40E_VLAN_ANY, false, true);
21659035
KP		 9077 spin_unlock_bh(&vsi->mac_filter_list_lock);
9078 }
3845ccea
ASJ		 9079 } else if ((pf->hw.aq.api_maj_ver > 1) ||
9080 ((pf->hw.aq.api_maj_ver == 1) &&
9081 (pf->hw.aq.api_min_ver > 4))) {
9082 /* Supported in FW API version higher than 1.4 */
9083 pf->flags |= I40E_FLAG_GENEVE_OFFLOAD_CAPABLE;
9084 pf->auto_disable_flags = I40E_FLAG_HW_ATR_EVICT_CAPABLE;
41c445ff
JB		 9085 } else {
9086 /* relate the VSI_VMDQ name to the VSI_MAIN name */
9087 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
9088 pf->vsi[pf->lan_vsi]->netdev->name);
9089 random_ether_addr(mac_addr);
21659035
KP		 9090
9091 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 9092 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 9093 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9094 }
21659035
KP		 9095
9096 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 9097 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 9098 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 9099
9a173901
GR		 9100 ether_addr_copy(netdev->dev_addr, mac_addr);
9101 ether_addr_copy(netdev->perm_addr, mac_addr);
b0fe3306 9102
41c445ff
JB		 9103 netdev->priv_flags |= IFF_UNICAST_FLT;
9104 netdev->priv_flags |= IFF_SUPP_NOFCS;
9105 /* Setup netdev TC information */
9106 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
9107
9108 netdev->netdev_ops = &i40e_netdev_ops;
9109 netdev->watchdog_timeo = 5 * HZ;
9110 i40e_set_ethtool_ops(netdev);
38e00438
VD		 9111#ifdef I40E_FCOE
9112 i40e_fcoe_config_netdev(netdev, vsi);
9113#endif
41c445ff
JB		 9114
9115 return 0;
9116}
9117
9118/**
9119 * i40e_vsi_delete - Delete a VSI from the switch
9120 * @vsi: the VSI being removed
9121 *
9122 * Returns 0 on success, negative value on failure
9123 **/
9124static void i40e_vsi_delete(struct i40e_vsi *vsi)
9125{
9126 /* remove default VSI is not allowed */
9127 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
9128 return;
9129
41c445ff 9130 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 9131}
9132
51616018
NP		 9133/**
9134 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
9135 * @vsi: the VSI being queried
9136 *
9137 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
9138 **/
9139int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
9140{
9141 struct i40e_veb *veb;
9142 struct i40e_pf *pf = vsi->back;
9143
9144 /* Uplink is not a bridge so default to VEB */
9145 if (vsi->veb_idx == I40E_NO_VEB)
9146 return 1;
9147
9148 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 9149 if (!veb) {
9150 dev_info(&pf->pdev->dev,
9151 "There is no veb associated with the bridge\n");
9152 return -ENOENT;
9153 }
9154
51616018 9155 /* Uplink is a bridge in VEPA mode */
09603eaa 9156 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 9157 return 0;
09603eaa
AA		 9158 } else {
9159 /* Uplink is a bridge in VEB mode */
9160 return 1;
9161 }
51616018 9162
09603eaa
AA		 9163 /* VEPA is now default bridge, so return 0 */
9164 return 0;
51616018
NP		 9165}
9166
41c445ff
JB		 9167/**
9168 * i40e_add_vsi - Add a VSI to the switch
9169 * @vsi: the VSI being configured
9170 *
9171 * This initializes a VSI context depending on the VSI type to be added and
9172 * passes it down to the add_vsi aq command.
9173 **/
9174static int i40e_add_vsi(struct i40e_vsi *vsi)
9175{
9176 int ret = -ENODEV;
21659035
KP		 9177 u8 laa_macaddr[ETH_ALEN];
9178 bool found_laa_mac_filter = false;
41c445ff
JB		 9179 struct i40e_pf *pf = vsi->back;
9180 struct i40e_hw *hw = &pf->hw;
9181 struct i40e_vsi_context ctxt;
21659035
KP		 9182 struct i40e_mac_filter *f, *ftmp;
9183
41c445ff
JB		 9184 u8 enabled_tc = 0x1; /* TC0 enabled */
9185 int f_count = 0;
9186
9187 memset(&ctxt, 0, sizeof(ctxt));
9188 switch (vsi->type) {
9189 case I40E_VSI_MAIN:
9190 /* The PF's main VSI is already setup as part of the
9191 * device initialization, so we'll not bother with
9192 * the add_vsi call, but we will retrieve the current
9193 * VSI context.
9194 */
9195 ctxt.seid = pf->main_vsi_seid;
9196 ctxt.pf_num = pf->hw.pf_id;
9197 ctxt.vf_num = 0;
9198 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
9199 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
9200 if (ret) {
9201 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9202 "couldn't get PF vsi config, err %s aq_err %s\n",
9203 i40e_stat_str(&pf->hw, ret),
9204 i40e_aq_str(&pf->hw,
9205 pf->hw.aq.asq_last_status));
41c445ff
JB		 9206 return -ENOENT;
9207 }
1a2f6248 9208 vsi->info = ctxt.info;
41c445ff
JB		 9209 vsi->info.valid_sections = 0;
9210
9211 vsi->seid = ctxt.seid;
9212 vsi->id = ctxt.vsi_number;
9213
9214 enabled_tc = i40e_pf_get_tc_map(pf);
9215
9216 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 9217 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
9218 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 9219 memset(&ctxt, 0, sizeof(ctxt));
9220 ctxt.seid = pf->main_vsi_seid;
9221 ctxt.pf_num = pf->hw.pf_id;
9222 ctxt.vf_num = 0;
9223 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
9224 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
9225 if (ret) {
9226 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9227 "update vsi failed, err %s aq_err %s\n",
9228 i40e_stat_str(&pf->hw, ret),
9229 i40e_aq_str(&pf->hw,
9230 pf->hw.aq.asq_last_status));
41c445ff
JB		 9231 ret = -ENOENT;
9232 goto err;
9233 }
9234 /* update the local VSI info queue map */
9235 i40e_vsi_update_queue_map(vsi, &ctxt);
9236 vsi->info.valid_sections = 0;
9237 } else {
9238 /* Default/Main VSI is only enabled for TC0
9239 * reconfigure it to enable all TCs that are
9240 * available on the port in SFP mode.
63d7e5a4
NP		 9241 * For MFP case the iSCSI PF would use this
9242 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 9243 */
9244 ret = i40e_vsi_config_tc(vsi, enabled_tc);
9245 if (ret) {
9246 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9247 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9248 enabled_tc,
9249 i40e_stat_str(&pf->hw, ret),
9250 i40e_aq_str(&pf->hw,
9251 pf->hw.aq.asq_last_status));
41c445ff
JB		 9252 ret = -ENOENT;
9253 }
9254 }
9255 break;
9256
9257 case I40E_VSI_FDIR:
cbf61325
ASJ		 9258 ctxt.pf_num = hw->pf_id;
9259 ctxt.vf_num = 0;
9260 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9261 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9262 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9263 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9264 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9265 ctxt.info.valid_sections |=
fc60861e 9266 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9267 ctxt.info.switch_id =
fc60861e 9268 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9269 }
41c445ff 9270 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9271 break;
9272
9273 case I40E_VSI_VMDQ2:
9274 ctxt.pf_num = hw->pf_id;
9275 ctxt.vf_num = 0;
9276 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9277 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9278 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9279
41c445ff
JB		 9280 /* This VSI is connected to VEB so the switch_id
9281 * should be set to zero by default.
9282 */
51616018
NP		 9283 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9284 ctxt.info.valid_sections |=
9285 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9286 ctxt.info.switch_id =
9287 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9288 }
41c445ff
JB		 9289
9290 /* Setup the VSI tx/rx queue map for TC0 only for now */
9291 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9292 break;
9293
9294 case I40E_VSI_SRIOV:
9295 ctxt.pf_num = hw->pf_id;
9296 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9297 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9298 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9299 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9300
41c445ff
JB		 9301 /* This VSI is connected to VEB so the switch_id
9302 * should be set to zero by default.
9303 */
51616018
NP		 9304 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9305 ctxt.info.valid_sections |=
9306 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9307 ctxt.info.switch_id =
9308 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9309 }
41c445ff 9310
e3219ce6
ASJ		 9311 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
9312 ctxt.info.valid_sections |=
9313 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
9314 ctxt.info.queueing_opt_flags |=
4b28cdba
AS		 9315 (I40E_AQ_VSI_QUE_OPT_TCP_ENA |
9316 I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI);
e3219ce6
ASJ		 9317 }
9318
41c445ff
JB		 9319 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9320 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9321 if (pf->vf[vsi->vf_id].spoofchk) {
9322 ctxt.info.valid_sections |=
9323 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9324 ctxt.info.sec_flags |=
9325 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9326 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9327 }
41c445ff
JB		 9328 /* Setup the VSI tx/rx queue map for TC0 only for now */
9329 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9330 break;
9331
38e00438
VD		 9332#ifdef I40E_FCOE
9333 case I40E_VSI_FCOE:
9334 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9335 if (ret) {
9336 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9337 return ret;
9338 }
9339 break;
9340
9341#endif /* I40E_FCOE */
e3219ce6
ASJ		 9342 case I40E_VSI_IWARP:
9343 /* send down message to iWARP */
9344 break;
9345
41c445ff
JB		 9346 default:
9347 return -ENODEV;
9348 }
9349
9350 if (vsi->type != I40E_VSI_MAIN) {
9351 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9352 if (ret) {
9353 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9354 "add vsi failed, err %s aq_err %s\n",
9355 i40e_stat_str(&pf->hw, ret),
9356 i40e_aq_str(&pf->hw,
9357 pf->hw.aq.asq_last_status));
41c445ff
JB		 9358 ret = -ENOENT;
9359 goto err;
9360 }
1a2f6248 9361 vsi->info = ctxt.info;
41c445ff
JB		 9362 vsi->info.valid_sections = 0;
9363 vsi->seid = ctxt.seid;
9364 vsi->id = ctxt.vsi_number;
9365 }
9366
21659035 9367 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9368 /* If macvlan filters already exist, force them to get loaded */
9369 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9370 f->changed = true;
9371 f_count++;
6252c7e4 9372
21659035 9373 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9374 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9375 ether_addr_copy(laa_macaddr, f->macaddr);
9376 found_laa_mac_filter = true;
9377 }
9378 }
9379 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9380
21659035
KP		 9381 if (found_laa_mac_filter) {
9382 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9383
21659035
KP		 9384 memset(&element, 0, sizeof(element));
9385 ether_addr_copy(element.mac_addr, laa_macaddr);
9386 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9387 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9388 &element, 1, NULL);
9389 if (ret) {
9390 /* some older FW has a different default */
9391 element.flags |=
9392 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9393 i40e_aq_remove_macvlan(hw, vsi->seid,
9394 &element, 1, NULL);
6252c7e4 9395 }
21659035
KP		 9396
9397 i40e_aq_mac_address_write(hw,
9398 I40E_AQC_WRITE_TYPE_LAA_WOL,
9399 laa_macaddr, NULL);
41c445ff 9400 }
21659035 9401
41c445ff
JB		 9402 if (f_count) {
9403 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9404 pf->flags |= I40E_FLAG_FILTER_SYNC;
9405 }
9406
9407 /* Update VSI BW information */
9408 ret = i40e_vsi_get_bw_info(vsi);
9409 if (ret) {
9410 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9411 "couldn't get vsi bw info, err %s aq_err %s\n",
9412 i40e_stat_str(&pf->hw, ret),
9413 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9414 /* VSI is already added so not tearing that up */
9415 ret = 0;
9416 }
9417
9418err:
9419 return ret;
9420}
9421
9422/**
9423 * i40e_vsi_release - Delete a VSI and free its resources
9424 * @vsi: the VSI being removed
9425 *
9426 * Returns 0 on success or < 0 on error
9427 **/
9428int i40e_vsi_release(struct i40e_vsi *vsi)
9429{
9430 struct i40e_mac_filter *f, *ftmp;
9431 struct i40e_veb *veb = NULL;
9432 struct i40e_pf *pf;
9433 u16 uplink_seid;
9434 int i, n;
9435
9436 pf = vsi->back;
9437
9438 /* release of a VEB-owner or last VSI is not allowed */
9439 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9440 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9441 vsi->seid, vsi->uplink_seid);
9442 return -ENODEV;
9443 }
9444 if (vsi == pf->vsi[pf->lan_vsi] &&
9445 !test_bit(__I40E_DOWN, &pf->state)) {
9446 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9447 return -ENODEV;
9448 }
9449
9450 uplink_seid = vsi->uplink_seid;
9451 if (vsi->type != I40E_VSI_SRIOV) {
9452 if (vsi->netdev_registered) {
9453 vsi->netdev_registered = false;
9454 if (vsi->netdev) {
9455 /* results in a call to i40e_close() */
9456 unregister_netdev(vsi->netdev);
41c445ff
JB		 9457 }
9458 } else {
90ef8d47 9459 i40e_vsi_close(vsi);
41c445ff
JB		 9460 }
9461 i40e_vsi_disable_irq(vsi);
9462 }
9463
21659035 9464 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9465 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9466 i40e_del_filter(vsi, f->macaddr, f->vlan,
9467 f->is_vf, f->is_netdev);
21659035
KP		 9468 spin_unlock_bh(&vsi->mac_filter_list_lock);
9469
17652c63 9470 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9471
9472 i40e_vsi_delete(vsi);
9473 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9474 if (vsi->netdev) {
9475 free_netdev(vsi->netdev);
9476 vsi->netdev = NULL;
9477 }
41c445ff
JB		 9478 i40e_vsi_clear_rings(vsi);
9479 i40e_vsi_clear(vsi);
9480
9481 /* If this was the last thing on the VEB, except for the
9482 * controlling VSI, remove the VEB, which puts the controlling
9483 * VSI onto the next level down in the switch.
9484 *
9485 * Well, okay, there's one more exception here: don't remove
9486 * the orphan VEBs yet. We'll wait for an explicit remove request
9487 * from up the network stack.
9488 */
505682cd 9489 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9490 if (pf->vsi[i] &&
9491 pf->vsi[i]->uplink_seid == uplink_seid &&
9492 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9493 n++; /* count the VSIs */
9494 }
9495 }
9496 for (i = 0; i < I40E_MAX_VEB; i++) {
9497 if (!pf->veb[i])
9498 continue;
9499 if (pf->veb[i]->uplink_seid == uplink_seid)
9500 n++; /* count the VEBs */
9501 if (pf->veb[i]->seid == uplink_seid)
9502 veb = pf->veb[i];
9503 }
9504 if (n == 0 && veb && veb->uplink_seid != 0)
9505 i40e_veb_release(veb);
9506
9507 return 0;
9508}
9509
9510/**
9511 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9512 * @vsi: ptr to the VSI
9513 *
9514 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9515 * corresponding SW VSI structure and initializes num_queue_pairs for the
9516 * newly allocated VSI.
9517 *
9518 * Returns 0 on success or negative on failure
9519 **/
9520static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9521{
9522 int ret = -ENOENT;
9523 struct i40e_pf *pf = vsi->back;
9524
493fb300 9525 if (vsi->q_vectors[0]) {
41c445ff
JB		 9526 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9527 vsi->seid);
9528 return -EEXIST;
9529 }
9530
9531 if (vsi->base_vector) {
f29eaa3d 9532 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9533 vsi->seid, vsi->base_vector);
9534 return -EEXIST;
9535 }
9536
90e04070 9537 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9538 if (ret) {
9539 dev_info(&pf->pdev->dev,
9540 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9541 vsi->num_q_vectors, vsi->seid, ret);
9542 vsi->num_q_vectors = 0;
9543 goto vector_setup_out;
9544 }
9545
26cdc443
ASJ		 9546 /* In Legacy mode, we do not have to get any other vector since we
9547 * piggyback on the misc/ICR0 for queue interrupts.
9548 */
9549 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9550 return ret;
958a3e3b
SN		 9551 if (vsi->num_q_vectors)
9552 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9553 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9554 if (vsi->base_vector < 0) {
9555 dev_info(&pf->pdev->dev,
049a2be8
SN		 9556 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9557 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9558 i40e_vsi_free_q_vectors(vsi);
9559 ret = -ENOENT;
9560 goto vector_setup_out;
9561 }
9562
9563vector_setup_out:
9564 return ret;
9565}
9566
bc7d338f
ASJ		 9567/**
9568 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9569 * @vsi: pointer to the vsi.
9570 *
9571 * This re-allocates a vsi's queue resources.
9572 *
9573 * Returns pointer to the successfully allocated and configured VSI sw struct
9574 * on success, otherwise returns NULL on failure.
9575 **/
9576static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9577{
f534039d 9578 struct i40e_pf *pf;
bc7d338f
ASJ		 9579 u8 enabled_tc;
9580 int ret;
9581
f534039d
JU		 9582 if (!vsi)
9583 return NULL;
9584
9585 pf = vsi->back;
9586
bc7d338f
ASJ		 9587 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9588 i40e_vsi_clear_rings(vsi);
9589
9590 i40e_vsi_free_arrays(vsi, false);
9591 i40e_set_num_rings_in_vsi(vsi);
9592 ret = i40e_vsi_alloc_arrays(vsi, false);
9593 if (ret)
9594 goto err_vsi;
9595
9596 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9597 if (ret < 0) {
049a2be8 9598 dev_info(&pf->pdev->dev,
f1c7e72e 9599 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9600 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9601 goto err_vsi;
9602 }
9603 vsi->base_queue = ret;
9604
9605 /* Update the FW view of the VSI. Force a reset of TC and queue
9606 * layout configurations.
9607 */
9608 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9609 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9610 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9611 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9612
9613 /* assign it some queues */
9614 ret = i40e_alloc_rings(vsi);
9615 if (ret)
9616 goto err_rings;
9617
9618 /* map all of the rings to the q_vectors */
9619 i40e_vsi_map_rings_to_vectors(vsi);
9620 return vsi;
9621
9622err_rings:
9623 i40e_vsi_free_q_vectors(vsi);
9624 if (vsi->netdev_registered) {
9625 vsi->netdev_registered = false;
9626 unregister_netdev(vsi->netdev);
9627 free_netdev(vsi->netdev);
9628 vsi->netdev = NULL;
9629 }
9630 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9631err_vsi:
9632 i40e_vsi_clear(vsi);
9633 return NULL;
9634}
9635
b499ffb0
SV		 9636/**
9637 * i40e_macaddr_init - explicitly write the mac address filters.
9638 *
9639 * @vsi: pointer to the vsi.
9640 * @macaddr: the MAC address
9641 *
9642 * This is needed when the macaddr has been obtained by other
9643 * means than the default, e.g., from Open Firmware or IDPROM.
9644 * Returns 0 on success, negative on failure
9645 **/
9646static int i40e_macaddr_init(struct i40e_vsi *vsi, u8 *macaddr)
9647{
9648 int ret;
9649 struct i40e_aqc_add_macvlan_element_data element;
9650
9651 ret = i40e_aq_mac_address_write(&vsi->back->hw,
9652 I40E_AQC_WRITE_TYPE_LAA_WOL,
9653 macaddr, NULL);
9654 if (ret) {
9655 dev_info(&vsi->back->pdev->dev,
9656 "Addr change for VSI failed: %d\n", ret);
9657 return -EADDRNOTAVAIL;
9658 }
9659
9660 memset(&element, 0, sizeof(element));
9661 ether_addr_copy(element.mac_addr, macaddr);
9662 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
9663 ret = i40e_aq_add_macvlan(&vsi->back->hw, vsi->seid, &element, 1, NULL);
9664 if (ret) {
9665 dev_info(&vsi->back->pdev->dev,
9666 "add filter failed err %s aq_err %s\n",
9667 i40e_stat_str(&vsi->back->hw, ret),
9668 i40e_aq_str(&vsi->back->hw,
9669 vsi->back->hw.aq.asq_last_status));
9670 }
9671 return ret;
9672}
9673
41c445ff
JB		 9674/**
9675 * i40e_vsi_setup - Set up a VSI by a given type
9676 * @pf: board private structure
9677 * @type: VSI type
9678 * @uplink_seid: the switch element to link to
9679 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9680 *
9681 * This allocates the sw VSI structure and its queue resources, then add a VSI
9682 * to the identified VEB.
9683 *
9684 * Returns pointer to the successfully allocated and configure VSI sw struct on
9685 * success, otherwise returns NULL on failure.
9686 **/
9687struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9688 u16 uplink_seid, u32 param1)
9689{
9690 struct i40e_vsi *vsi = NULL;
9691 struct i40e_veb *veb = NULL;
9692 int ret, i;
9693 int v_idx;
9694
9695 /* The requested uplink_seid must be either
9696 * - the PF's port seid
9697 * no VEB is needed because this is the PF
9698 * or this is a Flow Director special case VSI
9699 * - seid of an existing VEB
9700 * - seid of a VSI that owns an existing VEB
9701 * - seid of a VSI that doesn't own a VEB
9702 * a new VEB is created and the VSI becomes the owner
9703 * - seid of the PF VSI, which is what creates the first VEB
9704 * this is a special case of the previous
9705 *
9706 * Find which uplink_seid we were given and create a new VEB if needed
9707 */
9708 for (i = 0; i < I40E_MAX_VEB; i++) {
9709 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9710 veb = pf->veb[i];
9711 break;
9712 }
9713 }
9714
9715 if (!veb && uplink_seid != pf->mac_seid) {
9716
505682cd 9717 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9718 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9719 vsi = pf->vsi[i];
9720 break;
9721 }
9722 }
9723 if (!vsi) {
9724 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9725 uplink_seid);
9726 return NULL;
9727 }
9728
9729 if (vsi->uplink_seid == pf->mac_seid)
9730 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9731 vsi->tc_config.enabled_tc);
9732 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9733 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9734 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9735 if (veb) {
9736 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9737 dev_info(&vsi->back->pdev->dev,
fb43201f 9738 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9739 return NULL;
9740 }
fa11cb3d
ASJ		 9741 /* We come up by default in VEPA mode if SRIOV is not
9742 * already enabled, in which case we can't force VEPA
9743 * mode.
9744 */
9745 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9746 veb->bridge_mode = BRIDGE_MODE_VEPA;
9747 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9748 }
51616018 9749 i40e_config_bridge_mode(veb);
79c21a82 9750 }
41c445ff
JB		 9751 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9752 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9753 veb = pf->veb[i];
9754 }
9755 if (!veb) {
9756 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9757 return NULL;
9758 }
9759
9760 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9761 uplink_seid = veb->seid;
9762 }
9763
9764 /* get vsi sw struct */
9765 v_idx = i40e_vsi_mem_alloc(pf, type);
9766 if (v_idx < 0)
9767 goto err_alloc;
9768 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9769 if (!vsi)
9770 goto err_alloc;
41c445ff
JB		 9771 vsi->type = type;
9772 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9773
9774 if (type == I40E_VSI_MAIN)
9775 pf->lan_vsi = v_idx;
9776 else if (type == I40E_VSI_SRIOV)
9777 vsi->vf_id = param1;
9778 /* assign it some queues */
cbf61325
ASJ		 9779 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9780 vsi->idx);
41c445ff 9781 if (ret < 0) {
049a2be8
SN		 9782 dev_info(&pf->pdev->dev,
9783 "failed to get tracking for %d queues for VSI %d err=%d\n",
9784 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9785 goto err_vsi;
9786 }
9787 vsi->base_queue = ret;
9788
9789 /* get a VSI from the hardware */
9790 vsi->uplink_seid = uplink_seid;
9791 ret = i40e_add_vsi(vsi);
9792 if (ret)
9793 goto err_vsi;
9794
9795 switch (vsi->type) {
9796 /* setup the netdev if needed */
9797 case I40E_VSI_MAIN:
b499ffb0
SV		 9798 /* Apply relevant filters if a platform-specific mac
9799 * address was selected.
9800 */
9801 if (!!(pf->flags & I40E_FLAG_PF_MAC)) {
9802 ret = i40e_macaddr_init(vsi, pf->hw.mac.addr);
9803 if (ret) {
9804 dev_warn(&pf->pdev->dev,
9805 "could not set up macaddr; err %d\n",
9806 ret);
9807 }
9808 }
41c445ff 9809 case I40E_VSI_VMDQ2:
38e00438 9810 case I40E_VSI_FCOE:
41c445ff
JB		 9811 ret = i40e_config_netdev(vsi);
9812 if (ret)
9813 goto err_netdev;
9814 ret = register_netdev(vsi->netdev);
9815 if (ret)
9816 goto err_netdev;
9817 vsi->netdev_registered = true;
9818 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9819#ifdef CONFIG_I40E_DCB
9820 /* Setup DCB netlink interface */
9821 i40e_dcbnl_setup(vsi);
9822#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9823 /* fall through */
9824
9825 case I40E_VSI_FDIR:
9826 /* set up vectors and rings if needed */
9827 ret = i40e_vsi_setup_vectors(vsi);
9828 if (ret)
9829 goto err_msix;
9830
9831 ret = i40e_alloc_rings(vsi);
9832 if (ret)
9833 goto err_rings;
9834
9835 /* map all of the rings to the q_vectors */
9836 i40e_vsi_map_rings_to_vectors(vsi);
9837
9838 i40e_vsi_reset_stats(vsi);
9839 break;
9840
9841 default:
9842 /* no netdev or rings for the other VSI types */
9843 break;
9844 }
9845
e25d00b8
ASJ		 9846 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9847 (vsi->type == I40E_VSI_VMDQ2)) {
9848 ret = i40e_vsi_config_rss(vsi);
9849 }
41c445ff
JB		 9850 return vsi;
9851
9852err_rings:
9853 i40e_vsi_free_q_vectors(vsi);
9854err_msix:
9855 if (vsi->netdev_registered) {
9856 vsi->netdev_registered = false;
9857 unregister_netdev(vsi->netdev);
9858 free_netdev(vsi->netdev);
9859 vsi->netdev = NULL;
9860 }
9861err_netdev:
9862 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9863err_vsi:
9864 i40e_vsi_clear(vsi);
9865err_alloc:
9866 return NULL;
9867}
9868
9869/**
9870 * i40e_veb_get_bw_info - Query VEB BW information
9871 * @veb: the veb to query
9872 *
9873 * Query the Tx scheduler BW configuration data for given VEB
9874 **/
9875static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9876{
9877 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9878 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9879 struct i40e_pf *pf = veb->pf;
9880 struct i40e_hw *hw = &pf->hw;
9881 u32 tc_bw_max;
9882 int ret = 0;
9883 int i;
9884
9885 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9886 &bw_data, NULL);
9887 if (ret) {
9888 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9889 "query veb bw config failed, err %s aq_err %s\n",
9890 i40e_stat_str(&pf->hw, ret),
9891 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9892 goto out;
9893 }
9894
9895 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9896 &ets_data, NULL);
9897 if (ret) {
9898 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9899 "query veb bw ets config failed, err %s aq_err %s\n",
9900 i40e_stat_str(&pf->hw, ret),
9901 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9902 goto out;
9903 }
9904
9905 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9906 veb->bw_max_quanta = ets_data.tc_bw_max;
9907 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9908 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9909 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9910 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9911 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9912 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9913 veb->bw_tc_limit_credits[i] =
9914 le16_to_cpu(bw_data.tc_bw_limits[i]);
9915 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9916 }
9917
9918out:
9919 return ret;
9920}
9921
9922/**
9923 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9924 * @pf: board private structure
9925 *
9926 * On error: returns error code (negative)
9927 * On success: returns vsi index in PF (positive)
9928 **/
9929static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9930{
9931 int ret = -ENOENT;
9932 struct i40e_veb *veb;
9933 int i;
9934
9935 /* Need to protect the allocation of switch elements at the PF level */
9936 mutex_lock(&pf->switch_mutex);
9937
9938 /* VEB list may be fragmented if VEB creation/destruction has
9939 * been happening. We can afford to do a quick scan to look
9940 * for any free slots in the list.
9941 *
9942 * find next empty veb slot, looping back around if necessary
9943 */
9944 i = 0;
9945 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9946 i++;
9947 if (i >= I40E_MAX_VEB) {
9948 ret = -ENOMEM;
9949 goto err_alloc_veb; /* out of VEB slots! */
9950 }
9951
9952 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9953 if (!veb) {
9954 ret = -ENOMEM;
9955 goto err_alloc_veb;
9956 }
9957 veb->pf = pf;
9958 veb->idx = i;
9959 veb->enabled_tc = 1;
9960
9961 pf->veb[i] = veb;
9962 ret = i;
9963err_alloc_veb:
9964 mutex_unlock(&pf->switch_mutex);
9965 return ret;
9966}
9967
9968/**
9969 * i40e_switch_branch_release - Delete a branch of the switch tree
9970 * @branch: where to start deleting
9971 *
9972 * This uses recursion to find the tips of the branch to be
9973 * removed, deleting until we get back to and can delete this VEB.
9974 **/
9975static void i40e_switch_branch_release(struct i40e_veb *branch)
9976{
9977 struct i40e_pf *pf = branch->pf;
9978 u16 branch_seid = branch->seid;
9979 u16 veb_idx = branch->idx;
9980 int i;
9981
9982 /* release any VEBs on this VEB - RECURSION */
9983 for (i = 0; i < I40E_MAX_VEB; i++) {
9984 if (!pf->veb[i])
9985 continue;
9986 if (pf->veb[i]->uplink_seid == branch->seid)
9987 i40e_switch_branch_release(pf->veb[i]);
9988 }
9989
9990 /* Release the VSIs on this VEB, but not the owner VSI.
9991 *
9992 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9993 * the VEB itself, so don't use (*branch) after this loop.
9994 */
505682cd 9995 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9996 if (!pf->vsi[i])
9997 continue;
9998 if (pf->vsi[i]->uplink_seid == branch_seid &&
9999 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
10000 i40e_vsi_release(pf->vsi[i]);
10001 }
10002 }
10003
10004 /* There's one corner case where the VEB might not have been
10005 * removed, so double check it here and remove it if needed.
10006 * This case happens if the veb was created from the debugfs
10007 * commands and no VSIs were added to it.
10008 */
10009 if (pf->veb[veb_idx])
10010 i40e_veb_release(pf->veb[veb_idx]);
10011}
10012
10013/**
10014 * i40e_veb_clear - remove veb struct
10015 * @veb: the veb to remove
10016 **/
10017static void i40e_veb_clear(struct i40e_veb *veb)
10018{
10019 if (!veb)
10020 return;
10021
10022 if (veb->pf) {
10023 struct i40e_pf *pf = veb->pf;
10024
10025 mutex_lock(&pf->switch_mutex);
10026 if (pf->veb[veb->idx] == veb)
10027 pf->veb[veb->idx] = NULL;
10028 mutex_unlock(&pf->switch_mutex);
10029 }
10030
10031 kfree(veb);
10032}
10033
10034/**
10035 * i40e_veb_release - Delete a VEB and free its resources
10036 * @veb: the VEB being removed
10037 **/
10038void i40e_veb_release(struct i40e_veb *veb)
10039{
10040 struct i40e_vsi *vsi = NULL;
10041 struct i40e_pf *pf;
10042 int i, n = 0;
10043
10044 pf = veb->pf;
10045
10046 /* find the remaining VSI and check for extras */
505682cd 10047 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10048 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
10049 n++;
10050 vsi = pf->vsi[i];
10051 }
10052 }
10053 if (n != 1) {
10054 dev_info(&pf->pdev->dev,
10055 "can't remove VEB %d with %d VSIs left\n",
10056 veb->seid, n);
10057 return;
10058 }
10059
10060 /* move the remaining VSI to uplink veb */
10061 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
10062 if (veb->uplink_seid) {
10063 vsi->uplink_seid = veb->uplink_seid;
10064 if (veb->uplink_seid == pf->mac_seid)
10065 vsi->veb_idx = I40E_NO_VEB;
10066 else
10067 vsi->veb_idx = veb->veb_idx;
10068 } else {
10069 /* floating VEB */
10070 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
10071 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
10072 }
10073
10074 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
10075 i40e_veb_clear(veb);
41c445ff
JB		 10076}
10077
10078/**
10079 * i40e_add_veb - create the VEB in the switch
10080 * @veb: the VEB to be instantiated
10081 * @vsi: the controlling VSI
10082 **/
10083static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
10084{
f1c7e72e 10085 struct i40e_pf *pf = veb->pf;
66fc360a 10086 bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED);
41c445ff
JB		 10087 int ret;
10088
f1c7e72e 10089 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
5bc16031 10090 veb->enabled_tc, false,
66fc360a 10091 &veb->seid, enable_stats, NULL);
5bc16031
MW		 10092
10093 /* get a VEB from the hardware */
41c445ff 10094 if (ret) {
f1c7e72e
SN		 10095 dev_info(&pf->pdev->dev,
10096 "couldn't add VEB, err %s aq_err %s\n",
10097 i40e_stat_str(&pf->hw, ret),
10098 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10099 return -EPERM;
10100 }
10101
10102 /* get statistics counter */
f1c7e72e 10103 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 10104 &veb->stats_idx, NULL, NULL, NULL);
10105 if (ret) {
f1c7e72e
SN		 10106 dev_info(&pf->pdev->dev,
10107 "couldn't get VEB statistics idx, err %s aq_err %s\n",
10108 i40e_stat_str(&pf->hw, ret),
10109 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10110 return -EPERM;
10111 }
10112 ret = i40e_veb_get_bw_info(veb);
10113 if (ret) {
f1c7e72e
SN		 10114 dev_info(&pf->pdev->dev,
10115 "couldn't get VEB bw info, err %s aq_err %s\n",
10116 i40e_stat_str(&pf->hw, ret),
10117 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10118 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 10119 return -ENOENT;
10120 }
10121
10122 vsi->uplink_seid = veb->seid;
10123 vsi->veb_idx = veb->idx;
10124 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
10125
10126 return 0;
10127}
10128
10129/**
10130 * i40e_veb_setup - Set up a VEB
10131 * @pf: board private structure
10132 * @flags: VEB setup flags
10133 * @uplink_seid: the switch element to link to
10134 * @vsi_seid: the initial VSI seid
10135 * @enabled_tc: Enabled TC bit-map
10136 *
10137 * This allocates the sw VEB structure and links it into the switch
10138 * It is possible and legal for this to be a duplicate of an already
10139 * existing VEB. It is also possible for both uplink and vsi seids
10140 * to be zero, in order to create a floating VEB.
10141 *
10142 * Returns pointer to the successfully allocated VEB sw struct on
10143 * success, otherwise returns NULL on failure.
10144 **/
10145struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
10146 u16 uplink_seid, u16 vsi_seid,
10147 u8 enabled_tc)
10148{
10149 struct i40e_veb *veb, *uplink_veb = NULL;
10150 int vsi_idx, veb_idx;
10151 int ret;
10152
10153 /* if one seid is 0, the other must be 0 to create a floating relay */
10154 if ((uplink_seid == 0 || vsi_seid == 0) &&
10155 (uplink_seid + vsi_seid != 0)) {
10156 dev_info(&pf->pdev->dev,
10157 "one, not both seid's are 0: uplink=%d vsi=%d\n",
10158 uplink_seid, vsi_seid);
10159 return NULL;
10160 }
10161
10162 /* make sure there is such a vsi and uplink */
505682cd 10163 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 10164 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
10165 break;
505682cd 10166 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 10167 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
10168 vsi_seid);
10169 return NULL;
10170 }
10171
10172 if (uplink_seid && uplink_seid != pf->mac_seid) {
10173 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
10174 if (pf->veb[veb_idx] &&
10175 pf->veb[veb_idx]->seid == uplink_seid) {
10176 uplink_veb = pf->veb[veb_idx];
10177 break;
10178 }
10179 }
10180 if (!uplink_veb) {
10181 dev_info(&pf->pdev->dev,
10182 "uplink seid %d not found\n", uplink_seid);
10183 return NULL;
10184 }
10185 }
10186
10187 /* get veb sw struct */
10188 veb_idx = i40e_veb_mem_alloc(pf);
10189 if (veb_idx < 0)
10190 goto err_alloc;
10191 veb = pf->veb[veb_idx];
10192 veb->flags = flags;
10193 veb->uplink_seid = uplink_seid;
10194 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
10195 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
10196
10197 /* create the VEB in the switch */
10198 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
10199 if (ret)
10200 goto err_veb;
1bb8b935
SN		 10201 if (vsi_idx == pf->lan_vsi)
10202 pf->lan_veb = veb->idx;
41c445ff
JB		 10203
10204 return veb;
10205
10206err_veb:
10207 i40e_veb_clear(veb);
10208err_alloc:
10209 return NULL;
10210}
10211
10212/**
b40c82e6 10213 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 10214 * @pf: board private structure
10215 * @ele: element we are building info from
10216 * @num_reported: total number of elements
10217 * @printconfig: should we print the contents
10218 *
10219 * helper function to assist in extracting a few useful SEID values.
10220 **/
10221static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
10222 struct i40e_aqc_switch_config_element_resp *ele,
10223 u16 num_reported, bool printconfig)
10224{
10225 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
10226 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
10227 u8 element_type = ele->element_type;
10228 u16 seid = le16_to_cpu(ele->seid);
10229
10230 if (printconfig)
10231 dev_info(&pf->pdev->dev,
10232 "type=%d seid=%d uplink=%d downlink=%d\n",
10233 element_type, seid, uplink_seid, downlink_seid);
10234
10235 switch (element_type) {
10236 case I40E_SWITCH_ELEMENT_TYPE_MAC:
10237 pf->mac_seid = seid;
10238 break;
10239 case I40E_SWITCH_ELEMENT_TYPE_VEB:
10240 /* Main VEB? */
10241 if (uplink_seid != pf->mac_seid)
10242 break;
10243 if (pf->lan_veb == I40E_NO_VEB) {
10244 int v;
10245
10246 /* find existing or else empty VEB */
10247 for (v = 0; v < I40E_MAX_VEB; v++) {
10248 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
10249 pf->lan_veb = v;
10250 break;
10251 }
10252 }
10253 if (pf->lan_veb == I40E_NO_VEB) {
10254 v = i40e_veb_mem_alloc(pf);
10255 if (v < 0)
10256 break;
10257 pf->lan_veb = v;
10258 }
10259 }
10260
10261 pf->veb[pf->lan_veb]->seid = seid;
10262 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
10263 pf->veb[pf->lan_veb]->pf = pf;
10264 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
10265 break;
10266 case I40E_SWITCH_ELEMENT_TYPE_VSI:
10267 if (num_reported != 1)
10268 break;
10269 /* This is immediately after a reset so we can assume this is
10270 * the PF's VSI
10271 */
10272 pf->mac_seid = uplink_seid;
10273 pf->pf_seid = downlink_seid;
10274 pf->main_vsi_seid = seid;
10275 if (printconfig)
10276 dev_info(&pf->pdev->dev,
10277 "pf_seid=%d main_vsi_seid=%d\n",
10278 pf->pf_seid, pf->main_vsi_seid);
10279 break;
10280 case I40E_SWITCH_ELEMENT_TYPE_PF:
10281 case I40E_SWITCH_ELEMENT_TYPE_VF:
10282 case I40E_SWITCH_ELEMENT_TYPE_EMP:
10283 case I40E_SWITCH_ELEMENT_TYPE_BMC:
10284 case I40E_SWITCH_ELEMENT_TYPE_PE:
10285 case I40E_SWITCH_ELEMENT_TYPE_PA:
10286 /* ignore these for now */
10287 break;
10288 default:
10289 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
10290 element_type, seid);
10291 break;
10292 }
10293}
10294
10295/**
10296 * i40e_fetch_switch_configuration - Get switch config from firmware
10297 * @pf: board private structure
10298 * @printconfig: should we print the contents
10299 *
10300 * Get the current switch configuration from the device and
10301 * extract a few useful SEID values.
10302 **/
10303int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
10304{
10305 struct i40e_aqc_get_switch_config_resp *sw_config;
10306 u16 next_seid = 0;
10307 int ret = 0;
10308 u8 *aq_buf;
10309 int i;
10310
10311 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10312 if (!aq_buf)
10313 return -ENOMEM;
10314
10315 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10316 do {
10317 u16 num_reported, num_total;
10318
10319 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10320 I40E_AQ_LARGE_BUF,
10321 &next_seid, NULL);
10322 if (ret) {
10323 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10324 "get switch config failed err %s aq_err %s\n",
10325 i40e_stat_str(&pf->hw, ret),
10326 i40e_aq_str(&pf->hw,
10327 pf->hw.aq.asq_last_status));
41c445ff
JB		 10328 kfree(aq_buf);
10329 return -ENOENT;
10330 }
10331
10332 num_reported = le16_to_cpu(sw_config->header.num_reported);
10333 num_total = le16_to_cpu(sw_config->header.num_total);
10334
10335 if (printconfig)
10336 dev_info(&pf->pdev->dev,
10337 "header: %d reported %d total\n",
10338 num_reported, num_total);
10339
41c445ff
JB		 10340 for (i = 0; i < num_reported; i++) {
10341 struct i40e_aqc_switch_config_element_resp *ele =
10342 &sw_config->element[i];
10343
10344 i40e_setup_pf_switch_element(pf, ele, num_reported,
10345 printconfig);
10346 }
10347 } while (next_seid != 0);
10348
10349 kfree(aq_buf);
10350 return ret;
10351}
10352
10353/**
10354 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10355 * @pf: board private structure
bc7d338f 10356 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10357 *
10358 * Returns 0 on success, negative value on failure
10359 **/
bc7d338f 10360static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff 10361{
b5569892 10362 u16 flags = 0;
41c445ff
JB		 10363 int ret;
10364
10365 /* find out what's out there already */
10366 ret = i40e_fetch_switch_configuration(pf, false);
10367 if (ret) {
10368 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10369 "couldn't fetch switch config, err %s aq_err %s\n",
10370 i40e_stat_str(&pf->hw, ret),
10371 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10372 return ret;
10373 }
10374 i40e_pf_reset_stats(pf);
10375
b5569892
ASJ		 10376 /* set the switch config bit for the whole device to
10377 * support limited promisc or true promisc
10378 * when user requests promisc. The default is limited
10379 * promisc.
10380 */
10381
10382 if ((pf->hw.pf_id == 0) &&
10383 !(pf->flags & I40E_FLAG_TRUE_PROMISC_SUPPORT))
10384 flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
10385
10386 if (pf->hw.pf_id == 0) {
10387 u16 valid_flags;
10388
10389 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
10390 ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags,
10391 NULL);
10392 if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
10393 dev_info(&pf->pdev->dev,
10394 "couldn't set switch config bits, err %s aq_err %s\n",
10395 i40e_stat_str(&pf->hw, ret),
10396 i40e_aq_str(&pf->hw,
10397 pf->hw.aq.asq_last_status));
10398 /* not a fatal problem, just keep going */
10399 }
10400 }
10401
41c445ff 10402 /* first time setup */
bc7d338f 10403 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10404 struct i40e_vsi *vsi = NULL;
10405 u16 uplink_seid;
10406
10407 /* Set up the PF VSI associated with the PF's main VSI
10408 * that is already in the HW switch
10409 */
10410 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10411 uplink_seid = pf->veb[pf->lan_veb]->seid;
10412 else
10413 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10414 if (pf->lan_vsi == I40E_NO_VSI)
10415 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10416 else if (reinit)
10417 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10418 if (!vsi) {
10419 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10420 i40e_fdir_teardown(pf);
10421 return -EAGAIN;
10422 }
41c445ff
JB		 10423 } else {
10424 /* force a reset of TC and queue layout configurations */
10425 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10426
41c445ff
JB		 10427 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10428 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10429 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10430 }
10431 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10432
cbf61325
ASJ		 10433 i40e_fdir_sb_setup(pf);
10434
41c445ff
JB		 10435 /* Setup static PF queue filter control settings */
10436 ret = i40e_setup_pf_filter_control(pf);
10437 if (ret) {
10438 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10439 ret);
10440 /* Failure here should not stop continuing other steps */
10441 }
10442
10443 /* enable RSS in the HW, even for only one queue, as the stack can use
10444 * the hash
10445 */
10446 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10447 i40e_pf_config_rss(pf);
41c445ff
JB		 10448
10449 /* fill in link information and enable LSE reporting */
0a862b43 10450 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10451 i40e_link_event(pf);
10452
d52c20b7 10453 /* Initialize user-specific link properties */
41c445ff
JB		 10454 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10455 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10456
beb0dff1
JK		 10457 i40e_ptp_init(pf);
10458
41c445ff
JB		 10459 return ret;
10460}
10461
41c445ff
JB		 10462/**
10463 * i40e_determine_queue_usage - Work out queue distribution
10464 * @pf: board private structure
10465 **/
10466static void i40e_determine_queue_usage(struct i40e_pf *pf)
10467{
41c445ff
JB		 10468 int queues_left;
10469
10470 pf->num_lan_qps = 0;
38e00438
VD		 10471#ifdef I40E_FCOE
10472 pf->num_fcoe_qps = 0;
10473#endif
41c445ff
JB		 10474
10475 /* Find the max queues to be put into basic use. We'll always be
10476 * using TC0, whether or not DCB is running, and TC0 will get the
10477 * big RSS set.
10478 */
10479 queues_left = pf->hw.func_caps.num_tx_qp;
10480
cbf61325 10481 if ((queues_left == 1) ||
9aa7e935 10482 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10483 /* one qp for PF, no queues for anything else */
10484 queues_left = 0;
acd65448 10485 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10486
10487 /* make sure all the fancies are disabled */
60ea5f83 10488 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
e3219ce6 10489 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 10490#ifdef I40E_FCOE
10491 I40E_FLAG_FCOE_ENABLED |
10492#endif
60ea5f83
JB		 10493 I40E_FLAG_FD_SB_ENABLED |
10494 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10495 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10496 I40E_FLAG_SRIOV_ENABLED |
10497 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10498 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10499 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10500 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10501 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10502 /* one qp for PF */
acd65448 10503 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10504 queues_left -= pf->num_lan_qps;
10505
10506 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
e3219ce6 10507 I40E_FLAG_IWARP_ENABLED |
38e00438
VD		 10508#ifdef I40E_FCOE
10509 I40E_FLAG_FCOE_ENABLED |
10510#endif
9aa7e935
FZ		 10511 I40E_FLAG_FD_SB_ENABLED |
10512 I40E_FLAG_FD_ATR_ENABLED |
10513 I40E_FLAG_DCB_ENABLED |
10514 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10515 } else {
cbf61325 10516 /* Not enough queues for all TCs */
4d9b6043 10517 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10518 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10519 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10520 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10521 }
9a3bd2f1
ASJ		 10522 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10523 num_online_cpus());
10524 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10525 pf->hw.func_caps.num_tx_qp);
10526
cbf61325
ASJ		 10527 queues_left -= pf->num_lan_qps;
10528 }
10529
38e00438
VD		 10530#ifdef I40E_FCOE
10531 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10532 if (I40E_DEFAULT_FCOE <= queues_left) {
10533 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10534 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10535 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10536 } else {
10537 pf->num_fcoe_qps = 0;
10538 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10539 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10540 }
10541
10542 queues_left -= pf->num_fcoe_qps;
10543 }
10544
10545#endif
cbf61325
ASJ		 10546 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10547 if (queues_left > 1) {
10548 queues_left -= 1; /* save 1 queue for FD */
10549 } else {
10550 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10551 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10552 }
41c445ff
JB		 10553 }
10554
10555 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10556 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10557 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10558 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10559 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10560 }
10561
10562 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10563 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10564 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10565 (queues_left / pf->num_vmdq_qps));
10566 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10567 }
10568
f8ff1464 10569 pf->queues_left = queues_left;
8279e495
NP		 10570 dev_dbg(&pf->pdev->dev,
10571 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10572 pf->hw.func_caps.num_tx_qp,
10573 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10574 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10575 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10576 queues_left);
38e00438 10577#ifdef I40E_FCOE
8279e495 10578 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10579#endif
41c445ff
JB		 10580}
10581
10582/**
10583 * i40e_setup_pf_filter_control - Setup PF static filter control
10584 * @pf: PF to be setup
10585 *
b40c82e6 10586 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10587 * settings. If PE/FCoE are enabled then it will also set the per PF
10588 * based filter sizes required for them. It also enables Flow director,
10589 * ethertype and macvlan type filter settings for the pf.
10590 *
10591 * Returns 0 on success, negative on failure
10592 **/
10593static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10594{
10595 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10596
10597 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10598
10599 /* Flow Director is enabled */
60ea5f83 10600 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10601 settings->enable_fdir = true;
10602
10603 /* Ethtype and MACVLAN filters enabled for PF */
10604 settings->enable_ethtype = true;
10605 settings->enable_macvlan = true;
10606
10607 if (i40e_set_filter_control(&pf->hw, settings))
10608 return -ENOENT;
10609
10610 return 0;
10611}
10612
0c22b3dd 10613#define INFO_STRING_LEN 255
7fd89545 10614#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10615static void i40e_print_features(struct i40e_pf *pf)
10616{
10617 struct i40e_hw *hw = &pf->hw;
3b195843
JP		 10618 char *buf;
10619 int i;
0c22b3dd 10620
3b195843
JP		 10621 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
10622 if (!buf)
0c22b3dd 10623 return;
0c22b3dd 10624
3b195843 10625 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
0c22b3dd 10626#ifdef CONFIG_PCI_IOV
3b195843 10627 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
0c22b3dd 10628#endif
1a557afc 10629 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d",
7fd89545 10630 pf->hw.func_caps.num_vsis,
1a557afc 10631 pf->vsi[pf->lan_vsi]->num_queue_pairs);
0c22b3dd 10632 if (pf->flags & I40E_FLAG_RSS_ENABLED)
3b195843 10633 i += snprintf(&buf[i], REMAIN(i), " RSS");
0c22b3dd 10634 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
3b195843 10635 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
c6423ff1 10636 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
3b195843
JP		 10637 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
10638 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
c6423ff1 10639 }
4d9b6043 10640 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
3b195843 10641 i += snprintf(&buf[i], REMAIN(i), " DCB");
3b195843 10642 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
6a899024 10643 i += snprintf(&buf[i], REMAIN(i), " Geneve");
0c22b3dd 10644 if (pf->flags & I40E_FLAG_PTP)
3b195843 10645 i += snprintf(&buf[i], REMAIN(i), " PTP");
38e00438
VD		 10646#ifdef I40E_FCOE
10647 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
3b195843 10648 i += snprintf(&buf[i], REMAIN(i), " FCOE");
38e00438 10649#endif
6dec1017 10650 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
3b195843 10651 i += snprintf(&buf[i], REMAIN(i), " VEB");
6dec1017 10652 else
3b195843 10653 i += snprintf(&buf[i], REMAIN(i), " VEPA");
0c22b3dd 10654
3b195843
JP		 10655 dev_info(&pf->pdev->dev, "%s\n", buf);
10656 kfree(buf);
7fd89545 10657 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10658}
10659
b499ffb0
SV		 10660/**
10661 * i40e_get_platform_mac_addr - get platform-specific MAC address
10662 *
10663 * @pdev: PCI device information struct
10664 * @pf: board private structure
10665 *
10666 * Look up the MAC address in Open Firmware on systems that support it,
10667 * and use IDPROM on SPARC if no OF address is found. On return, the
10668 * I40E_FLAG_PF_MAC will be wset in pf->flags if a platform-specific value
10669 * has been selected.
10670 **/
10671static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf)
10672{
b499ffb0 10673 pf->flags &= ~I40E_FLAG_PF_MAC;
ba94272d 10674 if (!eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr))
b499ffb0 10675 pf->flags |= I40E_FLAG_PF_MAC;
b499ffb0
SV		 10676}
10677
41c445ff
JB		 10678/**
10679 * i40e_probe - Device initialization routine
10680 * @pdev: PCI device information struct
10681 * @ent: entry in i40e_pci_tbl
10682 *
b40c82e6
JK		 10683 * i40e_probe initializes a PF identified by a pci_dev structure.
10684 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10685 * and a hardware reset occur.
10686 *
10687 * Returns 0 on success, negative on failure
10688 **/
10689static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10690{
e827845c 10691 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10692 struct i40e_pf *pf;
10693 struct i40e_hw *hw;
93cd765b 10694 static u16 pfs_found;
1d5109d1 10695 u16 wol_nvm_bits;
d4dfb81a 10696 u16 link_status;
6f66a484 10697 int err;
4f2f017c 10698 u32 val;
8a9eb7d3 10699 u32 i;
58fc3267 10700 u8 set_fc_aq_fail;
41c445ff
JB		 10701
10702 err = pci_enable_device_mem(pdev);
10703 if (err)
10704 return err;
10705
10706 /* set up for high or low dma */
6494294f 10707 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10708 if (err) {
e3e3bfdd
JS		 10709 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10710 if (err) {
10711 dev_err(&pdev->dev,
10712 "DMA configuration failed: 0x%x\n", err);
10713 goto err_dma;
10714 }
41c445ff
JB		 10715 }
10716
10717 /* set up pci connections */
10718 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10719 IORESOURCE_MEM), i40e_driver_name);
10720 if (err) {
10721 dev_info(&pdev->dev,
10722 "pci_request_selected_regions failed %d\n", err);
10723 goto err_pci_reg;
10724 }
10725
10726 pci_enable_pcie_error_reporting(pdev);
10727 pci_set_master(pdev);
10728
10729 /* Now that we have a PCI connection, we need to do the
10730 * low level device setup. This is primarily setting up
10731 * the Admin Queue structures and then querying for the
10732 * device's current profile information.
10733 */
10734 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10735 if (!pf) {
10736 err = -ENOMEM;
10737 goto err_pf_alloc;
10738 }
10739 pf->next_vsi = 0;
10740 pf->pdev = pdev;
10741 set_bit(__I40E_DOWN, &pf->state);
10742
10743 hw = &pf->hw;
10744 hw->back = pf;
232f4706 10745
2ac8b675
SN		 10746 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10747 I40E_MAX_CSR_SPACE);
232f4706 10748
2ac8b675 10749 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10750 if (!hw->hw_addr) {
10751 err = -EIO;
10752 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10753 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10754 pf->ioremap_len, err);
41c445ff
JB		 10755 goto err_ioremap;
10756 }
10757 hw->vendor_id = pdev->vendor;
10758 hw->device_id = pdev->device;
10759 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10760 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10761 hw->subsystem_device_id = pdev->subsystem_device;
10762 hw->bus.device = PCI_SLOT(pdev->devfn);
10763 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10764 pf->instance = pfs_found;
41c445ff 10765
de03d2b0
SN		 10766 /* set up the locks for the AQ, do this only once in probe
10767 * and destroy them only once in remove
10768 */
10769 mutex_init(&hw->aq.asq_mutex);
10770 mutex_init(&hw->aq.arq_mutex);
10771
5b5faa43
SN		 10772 if (debug != -1) {
10773 pf->msg_enable = pf->hw.debug_mask;
10774 pf->msg_enable = debug;
10775 }
10776
7134f9ce
JB		 10777 /* do a special CORER for clearing PXE mode once at init */
10778 if (hw->revision_id == 0 &&
10779 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10780 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10781 i40e_flush(hw);
10782 msleep(200);
10783 pf->corer_count++;
10784
10785 i40e_clear_pxe_mode(hw);
10786 }
10787
41c445ff 10788 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10789 i40e_clear_hw(hw);
41c445ff
JB		 10790 err = i40e_pf_reset(hw);
10791 if (err) {
10792 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10793 goto err_pf_reset;
10794 }
10795 pf->pfr_count++;
10796
10797 hw->aq.num_arq_entries = I40E_AQ_LEN;
10798 hw->aq.num_asq_entries = I40E_AQ_LEN;
10799 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10800 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10801 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10802
b294ac70 10803 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10804 "%s-%s:misc",
10805 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10806
10807 err = i40e_init_shared_code(hw);
10808 if (err) {
b2a75c58
ASJ		 10809 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10810 err);
41c445ff
JB		 10811 goto err_pf_reset;
10812 }
10813
d52c20b7
JB		 10814 /* set up a default setting for link flow control */
10815 pf->hw.fc.requested_mode = I40E_FC_NONE;
10816
41c445ff 10817 err = i40e_init_adminq(hw);
2b2426a7
CW		 10818 if (err) {
10819 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10820 dev_info(&pdev->dev,
10821 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10822 else
10823 dev_info(&pdev->dev,
10824 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10825
10826 goto err_pf_reset;
10827 }
f0b44440 10828
6dec1017
SN		 10829 /* provide nvm, fw, api versions */
10830 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10831 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10832 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10833 i40e_nvm_version_str(hw));
f0b44440 10834
7aa67613
CS		 10835 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10836 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10837 dev_info(&pdev->dev,
7aa67613
CS		 10838 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10839 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10840 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10841 dev_info(&pdev->dev,
7aa67613 10842 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10843
4eb3f768
SN		 10844 i40e_verify_eeprom(pf);
10845
2c5fe33b
JB		 10846 /* Rev 0 hardware was never productized */
10847 if (hw->revision_id < 1)
10848 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10849
6ff4ef86 10850 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10851 err = i40e_get_capabilities(pf);
10852 if (err)
10853 goto err_adminq_setup;
10854
10855 err = i40e_sw_init(pf);
10856 if (err) {
10857 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10858 goto err_sw_init;
10859 }
10860
10861 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10862 hw->func_caps.num_rx_qp,
10863 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10864 if (err) {
10865 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10866 goto err_init_lan_hmc;
10867 }
10868
10869 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10870 if (err) {
10871 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10872 err = -ENOENT;
10873 goto err_configure_lan_hmc;
10874 }
10875
b686ece5
NP		 10876 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10877 * Ignore error return codes because if it was already disabled via
10878 * hardware settings this will fail
10879 */
f1bbad33 10880 if (pf->flags & I40E_FLAG_STOP_FW_LLDP) {
b686ece5
NP		 10881 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10882 i40e_aq_stop_lldp(hw, true, NULL);
10883 }
10884
41c445ff 10885 i40e_get_mac_addr(hw, hw->mac.addr);
b499ffb0
SV		 10886 /* allow a platform config to override the HW addr */
10887 i40e_get_platform_mac_addr(pdev, pf);
f62b5060 10888 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10889 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10890 err = -EIO;
10891 goto err_mac_addr;
10892 }
10893 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10894 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10895 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10896 if (is_valid_ether_addr(hw->mac.port_addr))
10897 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10898#ifdef I40E_FCOE
10899 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10900 if (err)
10901 dev_info(&pdev->dev,
10902 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10903 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10904 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10905 hw->mac.san_addr);
10906 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10907 }
10908 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10909#endif /* I40E_FCOE */
41c445ff
JB		 10910
10911 pci_set_drvdata(pdev, pf);
10912 pci_save_state(pdev);
4e3b35b0
NP		 10913#ifdef CONFIG_I40E_DCB
10914 err = i40e_init_pf_dcb(pf);
10915 if (err) {
aebfc816 10916 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10917 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10918 /* Continue without DCB enabled */
4e3b35b0
NP		 10919 }
10920#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10921
10922 /* set up periodic task facility */
10923 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10924 pf->service_timer_period = HZ;
10925
10926 INIT_WORK(&pf->service_task, i40e_service_task);
10927 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10928 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10929
1d5109d1
SN		 10930 /* NVM bit on means WoL disabled for the port */
10931 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
75f5cea9 10932 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
1d5109d1
SN		 10933 pf->wol_en = false;
10934 else
10935 pf->wol_en = true;
8e2773ae
SN		 10936 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10937
41c445ff
JB		 10938 /* set up the main switch operations */
10939 i40e_determine_queue_usage(pf);
c1147280
JB		 10940 err = i40e_init_interrupt_scheme(pf);
10941 if (err)
10942 goto err_switch_setup;
41c445ff 10943
505682cd
MW		 10944 /* The number of VSIs reported by the FW is the minimum guaranteed
10945 * to us; HW supports far more and we share the remaining pool with
10946 * the other PFs. We allocate space for more than the guarantee with
10947 * the understanding that we might not get them all later.
41c445ff 10948 */
505682cd
MW		 10949 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10950 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10951 else
10952 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10953
10954 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
d17038d6
JB		 10955 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *),
10956 GFP_KERNEL);
ed87ac09
WY		 10957 if (!pf->vsi) {
10958 err = -ENOMEM;
41c445ff 10959 goto err_switch_setup;
ed87ac09 10960 }
41c445ff 10961
fa11cb3d
ASJ		 10962#ifdef CONFIG_PCI_IOV
10963 /* prep for VF support */
10964 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10965 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10966 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10967 if (pci_num_vf(pdev))
10968 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10969 }
10970#endif
bc7d338f 10971 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10972 if (err) {
10973 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10974 goto err_vsis;
10975 }
58fc3267
HZ		 10976
10977 /* Make sure flow control is set according to current settings */
10978 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10979 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10980 dev_dbg(&pf->pdev->dev,
10981 "Set fc with err %s aq_err %s on get_phy_cap\n",
10982 i40e_stat_str(hw, err),
10983 i40e_aq_str(hw, hw->aq.asq_last_status));
10984 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10985 dev_dbg(&pf->pdev->dev,
10986 "Set fc with err %s aq_err %s on set_phy_config\n",
10987 i40e_stat_str(hw, err),
10988 i40e_aq_str(hw, hw->aq.asq_last_status));
10989 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10990 dev_dbg(&pf->pdev->dev,
10991 "Set fc with err %s aq_err %s on get_link_info\n",
10992 i40e_stat_str(hw, err),
10993 i40e_aq_str(hw, hw->aq.asq_last_status));
10994
8a9eb7d3 10995 /* if FDIR VSI was set up, start it now */
505682cd 10996 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10997 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10998 i40e_vsi_open(pf->vsi[i]);
10999 break;
11000 }
11001 }
41c445ff 11002
2f0aff41
SN		 11003 /* The driver only wants link up/down and module qualification
11004 * reports from firmware. Note the negative logic.
7e2453fe
JB		 11005 */
11006 err = i40e_aq_set_phy_int_mask(&pf->hw,
2f0aff41 11007 ~(I40E_AQ_EVENT_LINK_UPDOWN |
867a79e3 11008 I40E_AQ_EVENT_MEDIA_NA |
2f0aff41 11009 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
7e2453fe 11010 if (err)
f1c7e72e
SN		 11011 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
11012 i40e_stat_str(&pf->hw, err),
11013 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 11014
4f2f017c
ASJ		 11015 /* Reconfigure hardware for allowing smaller MSS in the case
11016 * of TSO, so that we avoid the MDD being fired and causing
11017 * a reset in the case of small MSS+TSO.
11018 */
11019 val = rd32(hw, I40E_REG_MSS);
11020 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
11021 val &= ~I40E_REG_MSS_MIN_MASK;
11022 val |= I40E_64BYTE_MSS;
11023 wr32(hw, I40E_REG_MSS, val);
11024 }
11025
8eed76fa 11026 if (pf->flags & I40E_FLAG_RESTART_AUTONEG) {
025b4a54
ASJ		 11027 msleep(75);
11028 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
11029 if (err)
f1c7e72e
SN		 11030 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
11031 i40e_stat_str(&pf->hw, err),
11032 i40e_aq_str(&pf->hw,
11033 pf->hw.aq.asq_last_status));
cafa2ee6 11034 }
41c445ff
JB		 11035 /* The main driver is (mostly) up and happy. We need to set this state
11036 * before setting up the misc vector or we get a race and the vector
11037 * ends up disabled forever.
11038 */
11039 clear_bit(__I40E_DOWN, &pf->state);
11040
11041 /* In case of MSIX we are going to setup the misc vector right here
11042 * to handle admin queue events etc. In case of legacy and MSI
11043 * the misc functionality and queue processing is combined in
11044 * the same vector and that gets setup at open.
11045 */
11046 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
11047 err = i40e_setup_misc_vector(pf);
11048 if (err) {
11049 dev_info(&pdev->dev,
11050 "setup of misc vector failed: %d\n", err);
11051 goto err_vsis;
11052 }
11053 }
11054
df805f62 11055#ifdef CONFIG_PCI_IOV
41c445ff
JB		 11056 /* prep for VF support */
11057 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 11058 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
11059 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 11060 /* disable link interrupts for VFs */
11061 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
11062 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
11063 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
11064 i40e_flush(hw);
4aeec010
MW		 11065
11066 if (pci_num_vf(pdev)) {
11067 dev_info(&pdev->dev,
11068 "Active VFs found, allocating resources.\n");
11069 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
11070 if (err)
11071 dev_info(&pdev->dev,
11072 "Error %d allocating resources for existing VFs\n",
11073 err);
11074 }
41c445ff 11075 }
df805f62 11076#endif /* CONFIG_PCI_IOV */
41c445ff 11077
e3219ce6
ASJ		 11078 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
11079 pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile,
11080 pf->num_iwarp_msix,
11081 I40E_IWARP_IRQ_PILE_ID);
11082 if (pf->iwarp_base_vector < 0) {
11083 dev_info(&pdev->dev,
11084 "failed to get tracking for %d vectors for IWARP err=%d\n",
11085 pf->num_iwarp_msix, pf->iwarp_base_vector);
11086 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
11087 }
11088 }
93cd765b 11089
41c445ff
JB		 11090 i40e_dbg_pf_init(pf);
11091
11092 /* tell the firmware that we're starting */
44033fac 11093 i40e_send_version(pf);
41c445ff
JB		 11094
11095 /* since everything's happy, start the service_task timer */
11096 mod_timer(&pf->service_timer,
11097 round_jiffies(jiffies + pf->service_timer_period));
11098
e3219ce6
ASJ		 11099 /* add this PF to client device list and launch a client service task */
11100 err = i40e_lan_add_device(pf);
11101 if (err)
11102 dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n",
11103 err);
11104
38e00438
VD		 11105#ifdef I40E_FCOE
11106 /* create FCoE interface */
11107 i40e_fcoe_vsi_setup(pf);
11108
11109#endif
3fced535
ASJ		 11110#define PCI_SPEED_SIZE 8
11111#define PCI_WIDTH_SIZE 8
11112 /* Devices on the IOSF bus do not have this information
11113 * and will report PCI Gen 1 x 1 by default so don't bother
11114 * checking them.
11115 */
11116 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
11117 char speed[PCI_SPEED_SIZE] = "Unknown";
11118 char width[PCI_WIDTH_SIZE] = "Unknown";
11119
11120 /* Get the negotiated link width and speed from PCI config
11121 * space
11122 */
11123 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
11124 &link_status);
11125
11126 i40e_set_pci_config_data(hw, link_status);
11127
11128 switch (hw->bus.speed) {
11129 case i40e_bus_speed_8000:
11130 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
11131 case i40e_bus_speed_5000:
11132 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
11133 case i40e_bus_speed_2500:
11134 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
11135 default:
11136 break;
11137 }
11138 switch (hw->bus.width) {
11139 case i40e_bus_width_pcie_x8:
11140 strncpy(width, "8", PCI_WIDTH_SIZE); break;
11141 case i40e_bus_width_pcie_x4:
11142 strncpy(width, "4", PCI_WIDTH_SIZE); break;
11143 case i40e_bus_width_pcie_x2:
11144 strncpy(width, "2", PCI_WIDTH_SIZE); break;
11145 case i40e_bus_width_pcie_x1:
11146 strncpy(width, "1", PCI_WIDTH_SIZE); break;
11147 default:
11148 break;
11149 }
11150
11151 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
11152 speed, width);
11153
11154 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
11155 hw->bus.speed < i40e_bus_speed_8000) {
11156 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
11157 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
11158 }
d4dfb81a
CS		 11159 }
11160
e827845c
CS		 11161 /* get the requested speeds from the fw */
11162 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
11163 if (err)
8279e495
NP		 11164 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
11165 i40e_stat_str(&pf->hw, err),
11166 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 11167 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
11168
fc72dbce
CS		 11169 /* get the supported phy types from the fw */
11170 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
11171 if (err)
11172 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
11173 i40e_stat_str(&pf->hw, err),
11174 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
11175 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
11176
e7358f54
ASJ		 11177 /* Add a filter to drop all Flow control frames from any VSI from being
11178 * transmitted. By doing so we stop a malicious VF from sending out
11179 * PAUSE or PFC frames and potentially controlling traffic for other
11180 * PF/VF VSIs.
11181 * The FW can still send Flow control frames if enabled.
11182 */
11183 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
11184 pf->main_vsi_seid);
11185
31b606d0
CW		 11186 if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) ||
11187 (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4))
11188 pf->flags |= I40E_FLAG_HAVE_10GBASET_PHY;
11189
0c22b3dd
JB		 11190 /* print a string summarizing features */
11191 i40e_print_features(pf);
11192
41c445ff
JB		 11193 return 0;
11194
11195 /* Unwind what we've done if something failed in the setup */
11196err_vsis:
11197 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 11198 i40e_clear_interrupt_scheme(pf);
11199 kfree(pf->vsi);
04b03013
SN		 11200err_switch_setup:
11201 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 11202 del_timer_sync(&pf->service_timer);
11203err_mac_addr:
11204err_configure_lan_hmc:
11205 (void)i40e_shutdown_lan_hmc(hw);
11206err_init_lan_hmc:
11207 kfree(pf->qp_pile);
41c445ff
JB		 11208err_sw_init:
11209err_adminq_setup:
41c445ff
JB		 11210err_pf_reset:
11211 iounmap(hw->hw_addr);
11212err_ioremap:
11213 kfree(pf);
11214err_pf_alloc:
11215 pci_disable_pcie_error_reporting(pdev);
11216 pci_release_selected_regions(pdev,
11217 pci_select_bars(pdev, IORESOURCE_MEM));
11218err_pci_reg:
11219err_dma:
11220 pci_disable_device(pdev);
11221 return err;
11222}
11223
11224/**
11225 * i40e_remove - Device removal routine
11226 * @pdev: PCI device information struct
11227 *
11228 * i40e_remove is called by the PCI subsystem to alert the driver
11229 * that is should release a PCI device. This could be caused by a
11230 * Hot-Plug event, or because the driver is going to be removed from
11231 * memory.
11232 **/
11233static void i40e_remove(struct pci_dev *pdev)
11234{
11235 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 11236 struct i40e_hw *hw = &pf->hw;
41c445ff 11237 i40e_status ret_code;
41c445ff
JB		 11238 int i;
11239
11240 i40e_dbg_pf_exit(pf);
11241
beb0dff1
JK		 11242 i40e_ptp_stop(pf);
11243
bcab2db9 11244 /* Disable RSS in hw */
272cdaf2
SN		 11245 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
11246 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
bcab2db9 11247
41c445ff 11248 /* no more scheduling of any task */
a4618ec8 11249 set_bit(__I40E_SUSPENDED, &pf->state);
41c445ff 11250 set_bit(__I40E_DOWN, &pf->state);
c99abb4c
SN		 11251 if (pf->service_timer.data)
11252 del_timer_sync(&pf->service_timer);
11253 if (pf->service_task.func)
11254 cancel_work_sync(&pf->service_task);
41c445ff 11255
eb2d80bc
MW		 11256 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
11257 i40e_free_vfs(pf);
11258 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
11259 }
11260
41c445ff
JB		 11261 i40e_fdir_teardown(pf);
11262
11263 /* If there is a switch structure or any orphans, remove them.
11264 * This will leave only the PF's VSI remaining.
11265 */
11266 for (i = 0; i < I40E_MAX_VEB; i++) {
11267 if (!pf->veb[i])
11268 continue;
11269
11270 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
11271 pf->veb[i]->uplink_seid == 0)
11272 i40e_switch_branch_release(pf->veb[i]);
11273 }
11274
11275 /* Now we can shutdown the PF's VSI, just before we kill
11276 * adminq and hmc.
11277 */
11278 if (pf->vsi[pf->lan_vsi])
11279 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
11280
e3219ce6
ASJ		 11281 /* remove attached clients */
11282 ret_code = i40e_lan_del_device(pf);
11283 if (ret_code) {
11284 dev_warn(&pdev->dev, "Failed to delete client device: %d\n",
11285 ret_code);
11286 }
11287
41c445ff 11288 /* shutdown and destroy the HMC */
f734dfff
JB		 11289 if (hw->hmc.hmc_obj) {
11290 ret_code = i40e_shutdown_lan_hmc(hw);
60442dea
SN		 11291 if (ret_code)
11292 dev_warn(&pdev->dev,
11293 "Failed to destroy the HMC resources: %d\n",
11294 ret_code);
11295 }
41c445ff
JB		 11296
11297 /* shutdown the adminq */
f734dfff 11298 ret_code = i40e_shutdown_adminq(hw);
41c445ff
JB		 11299 if (ret_code)
11300 dev_warn(&pdev->dev,
11301 "Failed to destroy the Admin Queue resources: %d\n",
11302 ret_code);
11303
8ddb3326
JB		 11304 /* destroy the locks only once, here */
11305 mutex_destroy(&hw->aq.arq_mutex);
11306 mutex_destroy(&hw->aq.asq_mutex);
11307
41c445ff
JB		 11308 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
11309 i40e_clear_interrupt_scheme(pf);
505682cd 11310 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 11311 if (pf->vsi[i]) {
11312 i40e_vsi_clear_rings(pf->vsi[i]);
11313 i40e_vsi_clear(pf->vsi[i]);
11314 pf->vsi[i] = NULL;
11315 }
11316 }
11317
11318 for (i = 0; i < I40E_MAX_VEB; i++) {
11319 kfree(pf->veb[i]);
11320 pf->veb[i] = NULL;
11321 }
11322
11323 kfree(pf->qp_pile);
41c445ff
JB		 11324 kfree(pf->vsi);
11325
f734dfff 11326 iounmap(hw->hw_addr);
41c445ff
JB		 11327 kfree(pf);
11328 pci_release_selected_regions(pdev,
11329 pci_select_bars(pdev, IORESOURCE_MEM));
11330
11331 pci_disable_pcie_error_reporting(pdev);
11332 pci_disable_device(pdev);
11333}
11334
11335/**
11336 * i40e_pci_error_detected - warning that something funky happened in PCI land
11337 * @pdev: PCI device information struct
11338 *
11339 * Called to warn that something happened and the error handling steps
11340 * are in progress. Allows the driver to quiesce things, be ready for
11341 * remediation.
11342 **/
11343static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
11344 enum pci_channel_state error)
11345{
11346 struct i40e_pf *pf = pci_get_drvdata(pdev);
11347
11348 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
11349
11350 /* shutdown all operations */
9007bccd
SN		 11351 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
11352 rtnl_lock();
11353 i40e_prep_for_reset(pf);
11354 rtnl_unlock();
11355 }
41c445ff
JB		 11356
11357 /* Request a slot reset */
11358 return PCI_ERS_RESULT_NEED_RESET;
11359}
11360
11361/**
11362 * i40e_pci_error_slot_reset - a PCI slot reset just happened
11363 * @pdev: PCI device information struct
11364 *
11365 * Called to find if the driver can work with the device now that
11366 * the pci slot has been reset. If a basic connection seems good
11367 * (registers are readable and have sane content) then return a
11368 * happy little PCI_ERS_RESULT_xxx.
11369 **/
11370static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
11371{
11372 struct i40e_pf *pf = pci_get_drvdata(pdev);
11373 pci_ers_result_t result;
11374 int err;
11375 u32 reg;
11376
fb43201f 11377 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 11378 if (pci_enable_device_mem(pdev)) {
11379 dev_info(&pdev->dev,
11380 "Cannot re-enable PCI device after reset.\n");
11381 result = PCI_ERS_RESULT_DISCONNECT;
11382 } else {
11383 pci_set_master(pdev);
11384 pci_restore_state(pdev);
11385 pci_save_state(pdev);
11386 pci_wake_from_d3(pdev, false);
11387
11388 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
11389 if (reg == 0)
11390 result = PCI_ERS_RESULT_RECOVERED;
11391 else
11392 result = PCI_ERS_RESULT_DISCONNECT;
11393 }
11394
11395 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11396 if (err) {
11397 dev_info(&pdev->dev,
11398 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11399 err);
11400 /* non-fatal, continue */
11401 }
11402
11403 return result;
11404}
11405
11406/**
11407 * i40e_pci_error_resume - restart operations after PCI error recovery
11408 * @pdev: PCI device information struct
11409 *
11410 * Called to allow the driver to bring things back up after PCI error
11411 * and/or reset recovery has finished.
11412 **/
11413static void i40e_pci_error_resume(struct pci_dev *pdev)
11414{
11415 struct i40e_pf *pf = pci_get_drvdata(pdev);
11416
fb43201f 11417 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11418 if (test_bit(__I40E_SUSPENDED, &pf->state))
11419 return;
11420
11421 rtnl_lock();
41c445ff 11422 i40e_handle_reset_warning(pf);
4c4935a9 11423 rtnl_unlock();
9007bccd
SN		 11424}
11425
11426/**
11427 * i40e_shutdown - PCI callback for shutting down
11428 * @pdev: PCI device information struct
11429 **/
11430static void i40e_shutdown(struct pci_dev *pdev)
11431{
11432 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11433 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11434
11435 set_bit(__I40E_SUSPENDED, &pf->state);
11436 set_bit(__I40E_DOWN, &pf->state);
11437 rtnl_lock();
11438 i40e_prep_for_reset(pf);
11439 rtnl_unlock();
11440
8e2773ae
SN		 11441 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11442 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11443
02b42498
CS		 11444 del_timer_sync(&pf->service_timer);
11445 cancel_work_sync(&pf->service_task);
11446 i40e_fdir_teardown(pf);
11447
11448 rtnl_lock();
11449 i40e_prep_for_reset(pf);
11450 rtnl_unlock();
11451
11452 wr32(hw, I40E_PFPM_APM,
11453 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11454 wr32(hw, I40E_PFPM_WUFC,
11455 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11456
e147758d
SN		 11457 i40e_clear_interrupt_scheme(pf);
11458
9007bccd 11459 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11460 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11461 pci_set_power_state(pdev, PCI_D3hot);
11462 }
11463}
11464
11465#ifdef CONFIG_PM
11466/**
11467 * i40e_suspend - PCI callback for moving to D3
11468 * @pdev: PCI device information struct
11469 **/
11470static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11471{
11472 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11473 struct i40e_hw *hw = &pf->hw;
059ff69b 11474 int retval = 0;
9007bccd
SN		 11475
11476 set_bit(__I40E_SUSPENDED, &pf->state);
11477 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11478
9007bccd
SN		 11479 rtnl_lock();
11480 i40e_prep_for_reset(pf);
11481 rtnl_unlock();
11482
8e2773ae
SN		 11483 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11484 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11485
b33d3b73
GR		 11486 i40e_stop_misc_vector(pf);
11487
059ff69b
GR		 11488 retval = pci_save_state(pdev);
11489 if (retval)
11490 return retval;
11491
8e2773ae 11492 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11493 pci_set_power_state(pdev, PCI_D3hot);
11494
059ff69b 11495 return retval;
41c445ff
JB		 11496}
11497
9007bccd
SN		 11498/**
11499 * i40e_resume - PCI callback for waking up from D3
11500 * @pdev: PCI device information struct
11501 **/
11502static int i40e_resume(struct pci_dev *pdev)
11503{
11504 struct i40e_pf *pf = pci_get_drvdata(pdev);
11505 u32 err;
11506
11507 pci_set_power_state(pdev, PCI_D0);
11508 pci_restore_state(pdev);
11509 /* pci_restore_state() clears dev->state_saves, so
11510 * call pci_save_state() again to restore it.
11511 */
11512 pci_save_state(pdev);
11513
11514 err = pci_enable_device_mem(pdev);
11515 if (err) {
fb43201f 11516 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11517 return err;
11518 }
11519 pci_set_master(pdev);
11520
11521 /* no wakeup events while running */
11522 pci_wake_from_d3(pdev, false);
11523
11524 /* handling the reset will rebuild the device state */
11525 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11526 clear_bit(__I40E_DOWN, &pf->state);
11527 rtnl_lock();
11528 i40e_reset_and_rebuild(pf, false);
11529 rtnl_unlock();
11530 }
11531
11532 return 0;
11533}
11534
11535#endif
41c445ff
JB		 11536static const struct pci_error_handlers i40e_err_handler = {
11537 .error_detected = i40e_pci_error_detected,
11538 .slot_reset = i40e_pci_error_slot_reset,
11539 .resume = i40e_pci_error_resume,
11540};
11541
11542static struct pci_driver i40e_driver = {
11543 .name = i40e_driver_name,
11544 .id_table = i40e_pci_tbl,
11545 .probe = i40e_probe,
11546 .remove = i40e_remove,
9007bccd
SN		 11547#ifdef CONFIG_PM
11548 .suspend = i40e_suspend,
11549 .resume = i40e_resume,
11550#endif
11551 .shutdown = i40e_shutdown,
41c445ff
JB		 11552 .err_handler = &i40e_err_handler,
11553 .sriov_configure = i40e_pci_sriov_configure,
11554};
11555
11556/**
11557 * i40e_init_module - Driver registration routine
11558 *
11559 * i40e_init_module is the first routine called when the driver is
11560 * loaded. All it does is register with the PCI subsystem.
11561 **/
11562static int __init i40e_init_module(void)
11563{
11564 pr_info("%s: %s - version %s\n", i40e_driver_name,
11565 i40e_driver_string, i40e_driver_version_str);
11566 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11567
2803b16c
JB		 11568 /* we will see if single thread per module is enough for now,
11569 * it can't be any worse than using the system workqueue which
11570 * was already single threaded
11571 */
11572 i40e_wq = create_singlethread_workqueue(i40e_driver_name);
11573 if (!i40e_wq) {
11574 pr_err("%s: Failed to create workqueue\n", i40e_driver_name);
11575 return -ENOMEM;
11576 }
11577
41c445ff
JB		 11578 i40e_dbg_init();
11579 return pci_register_driver(&i40e_driver);
11580}
11581module_init(i40e_init_module);
11582
11583/**
11584 * i40e_exit_module - Driver exit cleanup routine
11585 *
11586 * i40e_exit_module is called just before the driver is removed
11587 * from memory.
11588 **/
11589static void __exit i40e_exit_module(void)
11590{
11591 pci_unregister_driver(&i40e_driver);
2803b16c 11592 destroy_workqueue(i40e_wq);
41c445ff
JB		 11593 i40e_dbg_exit();
11594}
11595module_exit(i40e_exit_module);
Linux 6.x block layer and io_uring tree(s)