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Merge branch '10GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/next...
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_main.c
CommitLineData
41c445ff
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
e827845c 4 * Copyright(c) 2013 - 2015 Intel Corporation.
41c445ff
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
41c445ff
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27/* Local includes */
28#include "i40e.h"
4eb3f768 29#include "i40e_diag.h"
6633d381 30#ifdef CONFIG_I40E_VXLAN
a1c9a9d9
JK		 31#include <net/vxlan.h>
32#endif
41c445ff
JB		 33
34const char i40e_driver_name[] = "i40e";
35static const char i40e_driver_string[] =
36 "Intel(R) Ethernet Connection XL710 Network Driver";
37
38#define DRV_KERN "-k"
39
e8e724db 40#define DRV_VERSION_MAJOR 1
1c2df9e5 41#define DRV_VERSION_MINOR 4
1e590660 42#define DRV_VERSION_BUILD 7
41c445ff
JB		 43#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
44 __stringify(DRV_VERSION_MINOR) "." \
45 __stringify(DRV_VERSION_BUILD) DRV_KERN
46const char i40e_driver_version_str[] = DRV_VERSION;
8fb905b3 47static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
41c445ff
JB		 48
49/* a bit of forward declarations */
50static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
51static void i40e_handle_reset_warning(struct i40e_pf *pf);
52static int i40e_add_vsi(struct i40e_vsi *vsi);
53static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
bc7d338f 54static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
41c445ff
JB		 55static int i40e_setup_misc_vector(struct i40e_pf *pf);
56static void i40e_determine_queue_usage(struct i40e_pf *pf);
57static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
e69ff813
HZ		 58static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
59 u16 rss_table_size, u16 rss_size);
cbf61325 60static void i40e_fdir_sb_setup(struct i40e_pf *pf);
4e3b35b0 61static int i40e_veb_get_bw_info(struct i40e_veb *veb);
41c445ff
JB		 62
63/* i40e_pci_tbl - PCI Device ID Table
64 *
65 * Last entry must be all 0s
66 *
67 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
68 * Class, Class Mask, private data (not used) }
69 */
9baa3c34 70static const struct pci_device_id i40e_pci_tbl[] = {
ab60085e 71 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
ab60085e
SN		 72 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
73 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_A), 0},
74 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
75 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
ab60085e
SN		 76 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
77 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
78 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
5960d33f 79 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
bc5166b9 80 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
ae24b409 81 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
87e6c1d7
ASJ		 82 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
83 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
84 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
48a3b512
SN		 85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
41c445ff
JB		 87 /* required last entry */
88 {0, }
89};
90MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
91
92#define I40E_MAX_VF_COUNT 128
93static int debug = -1;
94module_param(debug, int, 0);
95MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
96
97MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
98MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
99MODULE_LICENSE("GPL");
100MODULE_VERSION(DRV_VERSION);
101
102/**
103 * i40e_allocate_dma_mem_d - OS specific memory alloc for shared code
104 * @hw: pointer to the HW structure
105 * @mem: ptr to mem struct to fill out
106 * @size: size of memory requested
107 * @alignment: what to align the allocation to
108 **/
109int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
110 u64 size, u32 alignment)
111{
112 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
113
114 mem->size = ALIGN(size, alignment);
115 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
116 &mem->pa, GFP_KERNEL);
93bc73b8
JB		 117 if (!mem->va)
118 return -ENOMEM;
41c445ff 119
93bc73b8 120 return 0;
41c445ff
JB		 121}
122
123/**
124 * i40e_free_dma_mem_d - OS specific memory free for shared code
125 * @hw: pointer to the HW structure
126 * @mem: ptr to mem struct to free
127 **/
128int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
129{
130 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
131
132 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
133 mem->va = NULL;
134 mem->pa = 0;
135 mem->size = 0;
136
137 return 0;
138}
139
140/**
141 * i40e_allocate_virt_mem_d - OS specific memory alloc for shared code
142 * @hw: pointer to the HW structure
143 * @mem: ptr to mem struct to fill out
144 * @size: size of memory requested
145 **/
146int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
147 u32 size)
148{
149 mem->size = size;
150 mem->va = kzalloc(size, GFP_KERNEL);
151
93bc73b8
JB		 152 if (!mem->va)
153 return -ENOMEM;
41c445ff 154
93bc73b8 155 return 0;
41c445ff
JB		 156}
157
158/**
159 * i40e_free_virt_mem_d - OS specific memory free for shared code
160 * @hw: pointer to the HW structure
161 * @mem: ptr to mem struct to free
162 **/
163int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
164{
165 /* it's ok to kfree a NULL pointer */
166 kfree(mem->va);
167 mem->va = NULL;
168 mem->size = 0;
169
170 return 0;
171}
172
173/**
174 * i40e_get_lump - find a lump of free generic resource
175 * @pf: board private structure
176 * @pile: the pile of resource to search
177 * @needed: the number of items needed
178 * @id: an owner id to stick on the items assigned
179 *
180 * Returns the base item index of the lump, or negative for error
181 *
182 * The search_hint trick and lack of advanced fit-finding only work
183 * because we're highly likely to have all the same size lump requests.
184 * Linear search time and any fragmentation should be minimal.
185 **/
186static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
187 u16 needed, u16 id)
188{
189 int ret = -ENOMEM;
ddf434ac 190 int i, j;
41c445ff
JB		 191
192 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
193 dev_info(&pf->pdev->dev,
194 "param err: pile=%p needed=%d id=0x%04x\n",
195 pile, needed, id);
196 return -EINVAL;
197 }
198
199 /* start the linear search with an imperfect hint */
200 i = pile->search_hint;
ddf434ac 201 while (i < pile->num_entries) {
41c445ff
JB		 202 /* skip already allocated entries */
203 if (pile->list[i] & I40E_PILE_VALID_BIT) {
204 i++;
205 continue;
206 }
207
208 /* do we have enough in this lump? */
209 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
210 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
211 break;
212 }
213
214 if (j == needed) {
215 /* there was enough, so assign it to the requestor */
216 for (j = 0; j < needed; j++)
217 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
218 ret = i;
219 pile->search_hint = i + j;
ddf434ac 220 break;
41c445ff 221 }
6995b36c
JB		 222
223 /* not enough, so skip over it and continue looking */
224 i += j;
41c445ff
JB		 225 }
226
227 return ret;
228}
229
230/**
231 * i40e_put_lump - return a lump of generic resource
232 * @pile: the pile of resource to search
233 * @index: the base item index
234 * @id: the owner id of the items assigned
235 *
236 * Returns the count of items in the lump
237 **/
238static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
239{
240 int valid_id = (id | I40E_PILE_VALID_BIT);
241 int count = 0;
242 int i;
243
244 if (!pile || index >= pile->num_entries)
245 return -EINVAL;
246
247 for (i = index;
248 i < pile->num_entries && pile->list[i] == valid_id;
249 i++) {
250 pile->list[i] = 0;
251 count++;
252 }
253
254 if (count && index < pile->search_hint)
255 pile->search_hint = index;
256
257 return count;
258}
259
fdf0e0bf
ASJ		 260/**
261 * i40e_find_vsi_from_id - searches for the vsi with the given id
262 * @pf - the pf structure to search for the vsi
263 * @id - id of the vsi it is searching for
264 **/
265struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
266{
267 int i;
268
269 for (i = 0; i < pf->num_alloc_vsi; i++)
270 if (pf->vsi[i] && (pf->vsi[i]->id == id))
271 return pf->vsi[i];
272
273 return NULL;
274}
275
41c445ff
JB		 276/**
277 * i40e_service_event_schedule - Schedule the service task to wake up
278 * @pf: board private structure
279 *
280 * If not already scheduled, this puts the task into the work queue
281 **/
282static void i40e_service_event_schedule(struct i40e_pf *pf)
283{
284 if (!test_bit(__I40E_DOWN, &pf->state) &&
285 !test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) &&
286 !test_and_set_bit(__I40E_SERVICE_SCHED, &pf->state))
287 schedule_work(&pf->service_task);
288}
289
290/**
291 * i40e_tx_timeout - Respond to a Tx Hang
292 * @netdev: network interface device structure
293 *
294 * If any port has noticed a Tx timeout, it is likely that the whole
295 * device is munged, not just the one netdev port, so go for the full
296 * reset.
297 **/
38e00438
VD		 298#ifdef I40E_FCOE
299void i40e_tx_timeout(struct net_device *netdev)
300#else
41c445ff 301static void i40e_tx_timeout(struct net_device *netdev)
38e00438 302#endif
41c445ff
JB		 303{
304 struct i40e_netdev_priv *np = netdev_priv(netdev);
305 struct i40e_vsi *vsi = np->vsi;
306 struct i40e_pf *pf = vsi->back;
b03a8c1f
KP		 307 struct i40e_ring *tx_ring = NULL;
308 unsigned int i, hung_queue = 0;
309 u32 head, val;
41c445ff
JB		 310
311 pf->tx_timeout_count++;
312
b03a8c1f
KP		 313 /* find the stopped queue the same way the stack does */
314 for (i = 0; i < netdev->num_tx_queues; i++) {
315 struct netdev_queue *q;
316 unsigned long trans_start;
317
318 q = netdev_get_tx_queue(netdev, i);
319 trans_start = q->trans_start ? : netdev->trans_start;
320 if (netif_xmit_stopped(q) &&
321 time_after(jiffies,
322 (trans_start + netdev->watchdog_timeo))) {
323 hung_queue = i;
324 break;
325 }
326 }
327
328 if (i == netdev->num_tx_queues) {
329 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
330 } else {
331 /* now that we have an index, find the tx_ring struct */
332 for (i = 0; i < vsi->num_queue_pairs; i++) {
333 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
334 if (hung_queue ==
335 vsi->tx_rings[i]->queue_index) {
336 tx_ring = vsi->tx_rings[i];
337 break;
338 }
339 }
340 }
341 }
342
41c445ff 343 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
b03a8c1f
KP		 344 pf->tx_timeout_recovery_level = 1; /* reset after some time */
345 else if (time_before(jiffies,
346 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
347 return; /* don't do any new action before the next timeout */
348
349 if (tx_ring) {
350 head = i40e_get_head(tx_ring);
351 /* Read interrupt register */
352 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
353 val = rd32(&pf->hw,
354 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
355 tx_ring->vsi->base_vector - 1));
356 else
357 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
358
359 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
360 vsi->seid, hung_queue, tx_ring->next_to_clean,
361 head, tx_ring->next_to_use,
362 readl(tx_ring->tail), val);
363 }
364
41c445ff 365 pf->tx_timeout_last_recovery = jiffies;
b03a8c1f
KP		 366 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
367 pf->tx_timeout_recovery_level, hung_queue);
41c445ff
JB		 368
369 switch (pf->tx_timeout_recovery_level) {
41c445ff
JB		 370 case 1:
371 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
372 break;
373 case 2:
374 set_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
375 break;
376 case 3:
377 set_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
378 break;
379 default:
380 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
41c445ff
JB		 381 break;
382 }
b03a8c1f 383
41c445ff
JB		 384 i40e_service_event_schedule(pf);
385 pf->tx_timeout_recovery_level++;
386}
387
388/**
389 * i40e_release_rx_desc - Store the new tail and head values
390 * @rx_ring: ring to bump
391 * @val: new head index
392 **/
393static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
394{
395 rx_ring->next_to_use = val;
396
397 /* Force memory writes to complete before letting h/w
398 * know there are new descriptors to fetch. (Only
399 * applicable for weak-ordered memory model archs,
400 * such as IA-64).
401 */
402 wmb();
403 writel(val, rx_ring->tail);
404}
405
406/**
407 * i40e_get_vsi_stats_struct - Get System Network Statistics
408 * @vsi: the VSI we care about
409 *
410 * Returns the address of the device statistics structure.
411 * The statistics are actually updated from the service task.
412 **/
413struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
414{
415 return &vsi->net_stats;
416}
417
418/**
419 * i40e_get_netdev_stats_struct - Get statistics for netdev interface
420 * @netdev: network interface device structure
421 *
422 * Returns the address of the device statistics structure.
423 * The statistics are actually updated from the service task.
424 **/
38e00438
VD		 425#ifdef I40E_FCOE
426struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
427 struct net_device *netdev,
428 struct rtnl_link_stats64 *stats)
429#else
41c445ff
JB		 430static struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
431 struct net_device *netdev,
980e9b11 432 struct rtnl_link_stats64 *stats)
38e00438 433#endif
41c445ff
JB		 434{
435 struct i40e_netdev_priv *np = netdev_priv(netdev);
e7046ee1 436 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 437 struct i40e_vsi *vsi = np->vsi;
980e9b11
AD		 438 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
439 int i;
440
bc7d338f
ASJ		 441 if (test_bit(__I40E_DOWN, &vsi->state))
442 return stats;
443
3c325ced
JB		 444 if (!vsi->tx_rings)
445 return stats;
446
980e9b11
AD		 447 rcu_read_lock();
448 for (i = 0; i < vsi->num_queue_pairs; i++) {
980e9b11
AD		 449 u64 bytes, packets;
450 unsigned int start;
451
452 tx_ring = ACCESS_ONCE(vsi->tx_rings[i]);
453 if (!tx_ring)
454 continue;
455
456 do {
57a7744e 457 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
980e9b11
AD		 458 packets = tx_ring->stats.packets;
459 bytes = tx_ring->stats.bytes;
57a7744e 460 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
980e9b11
AD		 461
462 stats->tx_packets += packets;
463 stats->tx_bytes += bytes;
464 rx_ring = &tx_ring[1];
465
466 do {
57a7744e 467 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
980e9b11
AD		 468 packets = rx_ring->stats.packets;
469 bytes = rx_ring->stats.bytes;
57a7744e 470 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
41c445ff 471
980e9b11
AD		 472 stats->rx_packets += packets;
473 stats->rx_bytes += bytes;
474 }
475 rcu_read_unlock();
476
a5282f44 477 /* following stats updated by i40e_watchdog_subtask() */
980e9b11
AD		 478 stats->multicast = vsi_stats->multicast;
479 stats->tx_errors = vsi_stats->tx_errors;
480 stats->tx_dropped = vsi_stats->tx_dropped;
481 stats->rx_errors = vsi_stats->rx_errors;
d8201e20 482 stats->rx_dropped = vsi_stats->rx_dropped;
980e9b11
AD		 483 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
484 stats->rx_length_errors = vsi_stats->rx_length_errors;
41c445ff 485
980e9b11 486 return stats;
41c445ff
JB		 487}
488
489/**
490 * i40e_vsi_reset_stats - Resets all stats of the given vsi
491 * @vsi: the VSI to have its stats reset
492 **/
493void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
494{
495 struct rtnl_link_stats64 *ns;
496 int i;
497
498 if (!vsi)
499 return;
500
501 ns = i40e_get_vsi_stats_struct(vsi);
502 memset(ns, 0, sizeof(*ns));
503 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
504 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
505 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
8e9dca53 506 if (vsi->rx_rings && vsi->rx_rings[0]) {
41c445ff 507 for (i = 0; i < vsi->num_queue_pairs; i++) {
6995b36c 508 memset(&vsi->rx_rings[i]->stats, 0,
9f65e15b 509 sizeof(vsi->rx_rings[i]->stats));
6995b36c 510 memset(&vsi->rx_rings[i]->rx_stats, 0,
9f65e15b 511 sizeof(vsi->rx_rings[i]->rx_stats));
6995b36c 512 memset(&vsi->tx_rings[i]->stats, 0,
9f65e15b
AD		 513 sizeof(vsi->tx_rings[i]->stats));
514 memset(&vsi->tx_rings[i]->tx_stats, 0,
515 sizeof(vsi->tx_rings[i]->tx_stats));
41c445ff 516 }
8e9dca53 517 }
41c445ff
JB		 518 vsi->stat_offsets_loaded = false;
519}
520
521/**
b40c82e6 522 * i40e_pf_reset_stats - Reset all of the stats for the given PF
41c445ff
JB		 523 * @pf: the PF to be reset
524 **/
525void i40e_pf_reset_stats(struct i40e_pf *pf)
526{
e91fdf76
SN		 527 int i;
528
41c445ff
JB		 529 memset(&pf->stats, 0, sizeof(pf->stats));
530 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
531 pf->stat_offsets_loaded = false;
e91fdf76
SN		 532
533 for (i = 0; i < I40E_MAX_VEB; i++) {
534 if (pf->veb[i]) {
535 memset(&pf->veb[i]->stats, 0,
536 sizeof(pf->veb[i]->stats));
537 memset(&pf->veb[i]->stats_offsets, 0,
538 sizeof(pf->veb[i]->stats_offsets));
539 pf->veb[i]->stat_offsets_loaded = false;
540 }
541 }
41c445ff
JB		 542}
543
544/**
545 * i40e_stat_update48 - read and update a 48 bit stat from the chip
546 * @hw: ptr to the hardware info
547 * @hireg: the high 32 bit reg to read
548 * @loreg: the low 32 bit reg to read
549 * @offset_loaded: has the initial offset been loaded yet
550 * @offset: ptr to current offset value
551 * @stat: ptr to the stat
552 *
553 * Since the device stats are not reset at PFReset, they likely will not
554 * be zeroed when the driver starts. We'll save the first values read
555 * and use them as offsets to be subtracted from the raw values in order
556 * to report stats that count from zero. In the process, we also manage
557 * the potential roll-over.
558 **/
559static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
560 bool offset_loaded, u64 *offset, u64 *stat)
561{
562 u64 new_data;
563
ab60085e 564 if (hw->device_id == I40E_DEV_ID_QEMU) {
41c445ff
JB		 565 new_data = rd32(hw, loreg);
566 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
567 } else {
568 new_data = rd64(hw, loreg);
569 }
570 if (!offset_loaded)
571 *offset = new_data;
572 if (likely(new_data >= *offset))
573 *stat = new_data - *offset;
574 else
41a1d04b 575 *stat = (new_data + BIT_ULL(48)) - *offset;
41c445ff
JB		 576 *stat &= 0xFFFFFFFFFFFFULL;
577}
578
579/**
580 * i40e_stat_update32 - read and update a 32 bit stat from the chip
581 * @hw: ptr to the hardware info
582 * @reg: the hw reg to read
583 * @offset_loaded: has the initial offset been loaded yet
584 * @offset: ptr to current offset value
585 * @stat: ptr to the stat
586 **/
587static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
588 bool offset_loaded, u64 *offset, u64 *stat)
589{
590 u32 new_data;
591
592 new_data = rd32(hw, reg);
593 if (!offset_loaded)
594 *offset = new_data;
595 if (likely(new_data >= *offset))
596 *stat = (u32)(new_data - *offset);
597 else
41a1d04b 598 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
41c445ff
JB		 599}
600
601/**
602 * i40e_update_eth_stats - Update VSI-specific ethernet statistics counters.
603 * @vsi: the VSI to be updated
604 **/
605void i40e_update_eth_stats(struct i40e_vsi *vsi)
606{
607 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
608 struct i40e_pf *pf = vsi->back;
609 struct i40e_hw *hw = &pf->hw;
610 struct i40e_eth_stats *oes;
611 struct i40e_eth_stats *es; /* device's eth stats */
612
613 es = &vsi->eth_stats;
614 oes = &vsi->eth_stats_offsets;
615
616 /* Gather up the stats that the hw collects */
617 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
618 vsi->stat_offsets_loaded,
619 &oes->tx_errors, &es->tx_errors);
620 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
621 vsi->stat_offsets_loaded,
622 &oes->rx_discards, &es->rx_discards);
41a9e55c
SN		 623 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
624 vsi->stat_offsets_loaded,
625 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
626 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
627 vsi->stat_offsets_loaded,
628 &oes->tx_errors, &es->tx_errors);
41c445ff
JB		 629
630 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
631 I40E_GLV_GORCL(stat_idx),
632 vsi->stat_offsets_loaded,
633 &oes->rx_bytes, &es->rx_bytes);
634 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
635 I40E_GLV_UPRCL(stat_idx),
636 vsi->stat_offsets_loaded,
637 &oes->rx_unicast, &es->rx_unicast);
638 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
639 I40E_GLV_MPRCL(stat_idx),
640 vsi->stat_offsets_loaded,
641 &oes->rx_multicast, &es->rx_multicast);
642 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
643 I40E_GLV_BPRCL(stat_idx),
644 vsi->stat_offsets_loaded,
645 &oes->rx_broadcast, &es->rx_broadcast);
646
647 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
648 I40E_GLV_GOTCL(stat_idx),
649 vsi->stat_offsets_loaded,
650 &oes->tx_bytes, &es->tx_bytes);
651 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
652 I40E_GLV_UPTCL(stat_idx),
653 vsi->stat_offsets_loaded,
654 &oes->tx_unicast, &es->tx_unicast);
655 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
656 I40E_GLV_MPTCL(stat_idx),
657 vsi->stat_offsets_loaded,
658 &oes->tx_multicast, &es->tx_multicast);
659 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
660 I40E_GLV_BPTCL(stat_idx),
661 vsi->stat_offsets_loaded,
662 &oes->tx_broadcast, &es->tx_broadcast);
663 vsi->stat_offsets_loaded = true;
664}
665
666/**
667 * i40e_update_veb_stats - Update Switch component statistics
668 * @veb: the VEB being updated
669 **/
670static void i40e_update_veb_stats(struct i40e_veb *veb)
671{
672 struct i40e_pf *pf = veb->pf;
673 struct i40e_hw *hw = &pf->hw;
674 struct i40e_eth_stats *oes;
675 struct i40e_eth_stats *es; /* device's eth stats */
fe860afb
NP		 676 struct i40e_veb_tc_stats *veb_oes;
677 struct i40e_veb_tc_stats *veb_es;
678 int i, idx = 0;
41c445ff
JB		 679
680 idx = veb->stats_idx;
681 es = &veb->stats;
682 oes = &veb->stats_offsets;
fe860afb
NP		 683 veb_es = &veb->tc_stats;
684 veb_oes = &veb->tc_stats_offsets;
41c445ff
JB		 685
686 /* Gather up the stats that the hw collects */
687 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
688 veb->stat_offsets_loaded,
689 &oes->tx_discards, &es->tx_discards);
7134f9ce
JB		 690 if (hw->revision_id > 0)
691 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
692 veb->stat_offsets_loaded,
693 &oes->rx_unknown_protocol,
694 &es->rx_unknown_protocol);
41c445ff
JB		 695 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
696 veb->stat_offsets_loaded,
697 &oes->rx_bytes, &es->rx_bytes);
698 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
699 veb->stat_offsets_loaded,
700 &oes->rx_unicast, &es->rx_unicast);
701 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
702 veb->stat_offsets_loaded,
703 &oes->rx_multicast, &es->rx_multicast);
704 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
705 veb->stat_offsets_loaded,
706 &oes->rx_broadcast, &es->rx_broadcast);
707
708 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
709 veb->stat_offsets_loaded,
710 &oes->tx_bytes, &es->tx_bytes);
711 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
712 veb->stat_offsets_loaded,
713 &oes->tx_unicast, &es->tx_unicast);
714 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
715 veb->stat_offsets_loaded,
716 &oes->tx_multicast, &es->tx_multicast);
717 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
718 veb->stat_offsets_loaded,
719 &oes->tx_broadcast, &es->tx_broadcast);
fe860afb
NP		 720 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
721 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
722 I40E_GLVEBTC_RPCL(i, idx),
723 veb->stat_offsets_loaded,
724 &veb_oes->tc_rx_packets[i],
725 &veb_es->tc_rx_packets[i]);
726 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
727 I40E_GLVEBTC_RBCL(i, idx),
728 veb->stat_offsets_loaded,
729 &veb_oes->tc_rx_bytes[i],
730 &veb_es->tc_rx_bytes[i]);
731 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
732 I40E_GLVEBTC_TPCL(i, idx),
733 veb->stat_offsets_loaded,
734 &veb_oes->tc_tx_packets[i],
735 &veb_es->tc_tx_packets[i]);
736 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
737 I40E_GLVEBTC_TBCL(i, idx),
738 veb->stat_offsets_loaded,
739 &veb_oes->tc_tx_bytes[i],
740 &veb_es->tc_tx_bytes[i]);
741 }
41c445ff
JB		 742 veb->stat_offsets_loaded = true;
743}
744
38e00438
VD		 745#ifdef I40E_FCOE
746/**
747 * i40e_update_fcoe_stats - Update FCoE-specific ethernet statistics counters.
748 * @vsi: the VSI that is capable of doing FCoE
749 **/
750static void i40e_update_fcoe_stats(struct i40e_vsi *vsi)
751{
752 struct i40e_pf *pf = vsi->back;
753 struct i40e_hw *hw = &pf->hw;
754 struct i40e_fcoe_stats *ofs;
755 struct i40e_fcoe_stats *fs; /* device's eth stats */
756 int idx;
757
758 if (vsi->type != I40E_VSI_FCOE)
759 return;
760
761 idx = (pf->pf_seid - I40E_BASE_PF_SEID) + I40E_FCOE_PF_STAT_OFFSET;
762 fs = &vsi->fcoe_stats;
763 ofs = &vsi->fcoe_stats_offsets;
764
765 i40e_stat_update32(hw, I40E_GL_FCOEPRC(idx),
766 vsi->fcoe_stat_offsets_loaded,
767 &ofs->rx_fcoe_packets, &fs->rx_fcoe_packets);
768 i40e_stat_update48(hw, I40E_GL_FCOEDWRCH(idx), I40E_GL_FCOEDWRCL(idx),
769 vsi->fcoe_stat_offsets_loaded,
770 &ofs->rx_fcoe_dwords, &fs->rx_fcoe_dwords);
771 i40e_stat_update32(hw, I40E_GL_FCOERPDC(idx),
772 vsi->fcoe_stat_offsets_loaded,
773 &ofs->rx_fcoe_dropped, &fs->rx_fcoe_dropped);
774 i40e_stat_update32(hw, I40E_GL_FCOEPTC(idx),
775 vsi->fcoe_stat_offsets_loaded,
776 &ofs->tx_fcoe_packets, &fs->tx_fcoe_packets);
777 i40e_stat_update48(hw, I40E_GL_FCOEDWTCH(idx), I40E_GL_FCOEDWTCL(idx),
778 vsi->fcoe_stat_offsets_loaded,
779 &ofs->tx_fcoe_dwords, &fs->tx_fcoe_dwords);
780 i40e_stat_update32(hw, I40E_GL_FCOECRC(idx),
781 vsi->fcoe_stat_offsets_loaded,
782 &ofs->fcoe_bad_fccrc, &fs->fcoe_bad_fccrc);
783 i40e_stat_update32(hw, I40E_GL_FCOELAST(idx),
784 vsi->fcoe_stat_offsets_loaded,
785 &ofs->fcoe_last_error, &fs->fcoe_last_error);
786 i40e_stat_update32(hw, I40E_GL_FCOEDDPC(idx),
787 vsi->fcoe_stat_offsets_loaded,
788 &ofs->fcoe_ddp_count, &fs->fcoe_ddp_count);
789
790 vsi->fcoe_stat_offsets_loaded = true;
791}
792
793#endif
41c445ff 794/**
7812fddc 795 * i40e_update_vsi_stats - Update the vsi statistics counters.
41c445ff
JB		 796 * @vsi: the VSI to be updated
797 *
798 * There are a few instances where we store the same stat in a
799 * couple of different structs. This is partly because we have
800 * the netdev stats that need to be filled out, which is slightly
801 * different from the "eth_stats" defined by the chip and used in
7812fddc 802 * VF communications. We sort it out here.
41c445ff 803 **/
7812fddc 804static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
41c445ff
JB		 805{
806 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 807 struct rtnl_link_stats64 *ons;
808 struct rtnl_link_stats64 *ns; /* netdev stats */
809 struct i40e_eth_stats *oes;
810 struct i40e_eth_stats *es; /* device's eth stats */
811 u32 tx_restart, tx_busy;
bf00b376 812 struct i40e_ring *p;
41c445ff 813 u32 rx_page, rx_buf;
bf00b376
AA		 814 u64 bytes, packets;
815 unsigned int start;
2fc3d715 816 u64 tx_linearize;
164c9f54 817 u64 tx_force_wb;
41c445ff
JB		 818 u64 rx_p, rx_b;
819 u64 tx_p, tx_b;
41c445ff
JB		 820 u16 q;
821
822 if (test_bit(__I40E_DOWN, &vsi->state) ||
823 test_bit(__I40E_CONFIG_BUSY, &pf->state))
824 return;
825
826 ns = i40e_get_vsi_stats_struct(vsi);
827 ons = &vsi->net_stats_offsets;
828 es = &vsi->eth_stats;
829 oes = &vsi->eth_stats_offsets;
830
831 /* Gather up the netdev and vsi stats that the driver collects
832 * on the fly during packet processing
833 */
834 rx_b = rx_p = 0;
835 tx_b = tx_p = 0;
164c9f54 836 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
41c445ff
JB		 837 rx_page = 0;
838 rx_buf = 0;
980e9b11 839 rcu_read_lock();
41c445ff 840 for (q = 0; q < vsi->num_queue_pairs; q++) {
980e9b11
AD		 841 /* locate Tx ring */
842 p = ACCESS_ONCE(vsi->tx_rings[q]);
843
844 do {
57a7744e 845 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 846 packets = p->stats.packets;
847 bytes = p->stats.bytes;
57a7744e 848 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 849 tx_b += bytes;
850 tx_p += packets;
851 tx_restart += p->tx_stats.restart_queue;
852 tx_busy += p->tx_stats.tx_busy;
2fc3d715 853 tx_linearize += p->tx_stats.tx_linearize;
164c9f54 854 tx_force_wb += p->tx_stats.tx_force_wb;
41c445ff 855
980e9b11
AD		 856 /* Rx queue is part of the same block as Tx queue */
857 p = &p[1];
858 do {
57a7744e 859 start = u64_stats_fetch_begin_irq(&p->syncp);
980e9b11
AD		 860 packets = p->stats.packets;
861 bytes = p->stats.bytes;
57a7744e 862 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
980e9b11
AD		 863 rx_b += bytes;
864 rx_p += packets;
420136cc
MW		 865 rx_buf += p->rx_stats.alloc_buff_failed;
866 rx_page += p->rx_stats.alloc_page_failed;
41c445ff 867 }
980e9b11 868 rcu_read_unlock();
41c445ff
JB		 869 vsi->tx_restart = tx_restart;
870 vsi->tx_busy = tx_busy;
2fc3d715 871 vsi->tx_linearize = tx_linearize;
164c9f54 872 vsi->tx_force_wb = tx_force_wb;
41c445ff
JB		 873 vsi->rx_page_failed = rx_page;
874 vsi->rx_buf_failed = rx_buf;
875
876 ns->rx_packets = rx_p;
877 ns->rx_bytes = rx_b;
878 ns->tx_packets = tx_p;
879 ns->tx_bytes = tx_b;
880
41c445ff 881 /* update netdev stats from eth stats */
7812fddc 882 i40e_update_eth_stats(vsi);
41c445ff
JB		 883 ons->tx_errors = oes->tx_errors;
884 ns->tx_errors = es->tx_errors;
885 ons->multicast = oes->rx_multicast;
886 ns->multicast = es->rx_multicast;
41a9e55c
SN		 887 ons->rx_dropped = oes->rx_discards;
888 ns->rx_dropped = es->rx_discards;
41c445ff
JB		 889 ons->tx_dropped = oes->tx_discards;
890 ns->tx_dropped = es->tx_discards;
891
7812fddc 892 /* pull in a couple PF stats if this is the main vsi */
41c445ff 893 if (vsi == pf->vsi[pf->lan_vsi]) {
7812fddc
SN		 894 ns->rx_crc_errors = pf->stats.crc_errors;
895 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
896 ns->rx_length_errors = pf->stats.rx_length_errors;
897 }
898}
41c445ff 899
7812fddc 900/**
b40c82e6 901 * i40e_update_pf_stats - Update the PF statistics counters.
7812fddc
SN		 902 * @pf: the PF to be updated
903 **/
904static void i40e_update_pf_stats(struct i40e_pf *pf)
905{
906 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
907 struct i40e_hw_port_stats *nsd = &pf->stats;
908 struct i40e_hw *hw = &pf->hw;
909 u32 val;
910 int i;
41c445ff 911
7812fddc
SN		 912 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
913 I40E_GLPRT_GORCL(hw->port),
914 pf->stat_offsets_loaded,
915 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
916 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
917 I40E_GLPRT_GOTCL(hw->port),
918 pf->stat_offsets_loaded,
919 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
920 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->eth.rx_discards,
923 &nsd->eth.rx_discards);
532d283d
SN		 924 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
925 I40E_GLPRT_UPRCL(hw->port),
926 pf->stat_offsets_loaded,
927 &osd->eth.rx_unicast,
928 &nsd->eth.rx_unicast);
7812fddc
SN		 929 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
930 I40E_GLPRT_MPRCL(hw->port),
931 pf->stat_offsets_loaded,
932 &osd->eth.rx_multicast,
933 &nsd->eth.rx_multicast);
532d283d
SN		 934 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
935 I40E_GLPRT_BPRCL(hw->port),
936 pf->stat_offsets_loaded,
937 &osd->eth.rx_broadcast,
938 &nsd->eth.rx_broadcast);
939 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
940 I40E_GLPRT_UPTCL(hw->port),
941 pf->stat_offsets_loaded,
942 &osd->eth.tx_unicast,
943 &nsd->eth.tx_unicast);
944 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
945 I40E_GLPRT_MPTCL(hw->port),
946 pf->stat_offsets_loaded,
947 &osd->eth.tx_multicast,
948 &nsd->eth.tx_multicast);
949 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
950 I40E_GLPRT_BPTCL(hw->port),
951 pf->stat_offsets_loaded,
952 &osd->eth.tx_broadcast,
953 &nsd->eth.tx_broadcast);
41c445ff 954
7812fddc
SN		 955 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
956 pf->stat_offsets_loaded,
957 &osd->tx_dropped_link_down,
958 &nsd->tx_dropped_link_down);
41c445ff 959
7812fddc
SN		 960 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
961 pf->stat_offsets_loaded,
962 &osd->crc_errors, &nsd->crc_errors);
41c445ff 963
7812fddc
SN		 964 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
965 pf->stat_offsets_loaded,
966 &osd->illegal_bytes, &nsd->illegal_bytes);
41c445ff 967
7812fddc
SN		 968 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
969 pf->stat_offsets_loaded,
970 &osd->mac_local_faults,
971 &nsd->mac_local_faults);
972 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
973 pf->stat_offsets_loaded,
974 &osd->mac_remote_faults,
975 &nsd->mac_remote_faults);
41c445ff 976
7812fddc
SN		 977 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
978 pf->stat_offsets_loaded,
979 &osd->rx_length_errors,
980 &nsd->rx_length_errors);
41c445ff 981
7812fddc
SN		 982 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
983 pf->stat_offsets_loaded,
984 &osd->link_xon_rx, &nsd->link_xon_rx);
985 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
986 pf->stat_offsets_loaded,
987 &osd->link_xon_tx, &nsd->link_xon_tx);
95db239f
NP		 988 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
989 pf->stat_offsets_loaded,
990 &osd->link_xoff_rx, &nsd->link_xoff_rx);
7812fddc
SN		 991 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
992 pf->stat_offsets_loaded,
993 &osd->link_xoff_tx, &nsd->link_xoff_tx);
41c445ff 994
7812fddc 995 for (i = 0; i < 8; i++) {
95db239f
NP		 996 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
997 pf->stat_offsets_loaded,
998 &osd->priority_xoff_rx[i],
999 &nsd->priority_xoff_rx[i]);
7812fddc 1000 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
41c445ff 1001 pf->stat_offsets_loaded,
7812fddc
SN		 1002 &osd->priority_xon_rx[i],
1003 &nsd->priority_xon_rx[i]);
1004 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
41c445ff 1005 pf->stat_offsets_loaded,
7812fddc
SN		 1006 &osd->priority_xon_tx[i],
1007 &nsd->priority_xon_tx[i]);
1008 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
41c445ff 1009 pf->stat_offsets_loaded,
7812fddc
SN		 1010 &osd->priority_xoff_tx[i],
1011 &nsd->priority_xoff_tx[i]);
1012 i40e_stat_update32(hw,
1013 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
bee5af7e 1014 pf->stat_offsets_loaded,
7812fddc
SN		 1015 &osd->priority_xon_2_xoff[i],
1016 &nsd->priority_xon_2_xoff[i]);
41c445ff
JB		 1017 }
1018
7812fddc
SN		 1019 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
1020 I40E_GLPRT_PRC64L(hw->port),
1021 pf->stat_offsets_loaded,
1022 &osd->rx_size_64, &nsd->rx_size_64);
1023 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
1024 I40E_GLPRT_PRC127L(hw->port),
1025 pf->stat_offsets_loaded,
1026 &osd->rx_size_127, &nsd->rx_size_127);
1027 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
1028 I40E_GLPRT_PRC255L(hw->port),
1029 pf->stat_offsets_loaded,
1030 &osd->rx_size_255, &nsd->rx_size_255);
1031 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1032 I40E_GLPRT_PRC511L(hw->port),
1033 pf->stat_offsets_loaded,
1034 &osd->rx_size_511, &nsd->rx_size_511);
1035 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1036 I40E_GLPRT_PRC1023L(hw->port),
1037 pf->stat_offsets_loaded,
1038 &osd->rx_size_1023, &nsd->rx_size_1023);
1039 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1040 I40E_GLPRT_PRC1522L(hw->port),
1041 pf->stat_offsets_loaded,
1042 &osd->rx_size_1522, &nsd->rx_size_1522);
1043 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1044 I40E_GLPRT_PRC9522L(hw->port),
1045 pf->stat_offsets_loaded,
1046 &osd->rx_size_big, &nsd->rx_size_big);
1047
1048 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1049 I40E_GLPRT_PTC64L(hw->port),
1050 pf->stat_offsets_loaded,
1051 &osd->tx_size_64, &nsd->tx_size_64);
1052 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1053 I40E_GLPRT_PTC127L(hw->port),
1054 pf->stat_offsets_loaded,
1055 &osd->tx_size_127, &nsd->tx_size_127);
1056 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1057 I40E_GLPRT_PTC255L(hw->port),
1058 pf->stat_offsets_loaded,
1059 &osd->tx_size_255, &nsd->tx_size_255);
1060 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1061 I40E_GLPRT_PTC511L(hw->port),
1062 pf->stat_offsets_loaded,
1063 &osd->tx_size_511, &nsd->tx_size_511);
1064 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1065 I40E_GLPRT_PTC1023L(hw->port),
1066 pf->stat_offsets_loaded,
1067 &osd->tx_size_1023, &nsd->tx_size_1023);
1068 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1069 I40E_GLPRT_PTC1522L(hw->port),
1070 pf->stat_offsets_loaded,
1071 &osd->tx_size_1522, &nsd->tx_size_1522);
1072 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1073 I40E_GLPRT_PTC9522L(hw->port),
1074 pf->stat_offsets_loaded,
1075 &osd->tx_size_big, &nsd->tx_size_big);
1076
1077 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1078 pf->stat_offsets_loaded,
1079 &osd->rx_undersize, &nsd->rx_undersize);
1080 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1081 pf->stat_offsets_loaded,
1082 &osd->rx_fragments, &nsd->rx_fragments);
1083 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1084 pf->stat_offsets_loaded,
1085 &osd->rx_oversize, &nsd->rx_oversize);
1086 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1087 pf->stat_offsets_loaded,
1088 &osd->rx_jabber, &nsd->rx_jabber);
1089
433c47de 1090 /* FDIR stats */
0bf4b1b0
ASJ		 1091 i40e_stat_update32(hw,
1092 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1093 pf->stat_offsets_loaded,
1094 &osd->fd_atr_match, &nsd->fd_atr_match);
0bf4b1b0
ASJ		 1095 i40e_stat_update32(hw,
1096 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(pf->hw.pf_id)),
433c47de
ASJ		 1097 pf->stat_offsets_loaded,
1098 &osd->fd_sb_match, &nsd->fd_sb_match);
60ccd45c
ASJ		 1099 i40e_stat_update32(hw,
1100 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id)),
1101 pf->stat_offsets_loaded,
1102 &osd->fd_atr_tunnel_match, &nsd->fd_atr_tunnel_match);
433c47de 1103
7812fddc
SN		 1104 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1105 nsd->tx_lpi_status =
1106 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1107 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1108 nsd->rx_lpi_status =
1109 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1110 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1111 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1112 pf->stat_offsets_loaded,
1113 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1114 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1115 pf->stat_offsets_loaded,
1116 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1117
d0389e51
ASJ		 1118 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1119 !(pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED))
1120 nsd->fd_sb_status = true;
1121 else
1122 nsd->fd_sb_status = false;
1123
1124 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1125 !(pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
1126 nsd->fd_atr_status = true;
1127 else
1128 nsd->fd_atr_status = false;
1129
41c445ff
JB		 1130 pf->stat_offsets_loaded = true;
1131}
1132
7812fddc
SN		 1133/**
1134 * i40e_update_stats - Update the various statistics counters.
1135 * @vsi: the VSI to be updated
1136 *
1137 * Update the various stats for this VSI and its related entities.
1138 **/
1139void i40e_update_stats(struct i40e_vsi *vsi)
1140{
1141 struct i40e_pf *pf = vsi->back;
1142
1143 if (vsi == pf->vsi[pf->lan_vsi])
1144 i40e_update_pf_stats(pf);
1145
1146 i40e_update_vsi_stats(vsi);
38e00438
VD		 1147#ifdef I40E_FCOE
1148 i40e_update_fcoe_stats(vsi);
1149#endif
7812fddc
SN		 1150}
1151
41c445ff
JB		 1152/**
1153 * i40e_find_filter - Search VSI filter list for specific mac/vlan filter
1154 * @vsi: the VSI to be searched
1155 * @macaddr: the MAC address
1156 * @vlan: the vlan
b40c82e6 1157 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1158 * @is_netdev: make sure its a netdev filter, else doesn't matter
1159 *
1160 * Returns ptr to the filter object or NULL
1161 **/
1162static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1163 u8 *macaddr, s16 vlan,
1164 bool is_vf, bool is_netdev)
1165{
1166 struct i40e_mac_filter *f;
1167
1168 if (!vsi || !macaddr)
1169 return NULL;
1170
1171 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1172 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1173 (vlan == f->vlan) &&
1174 (!is_vf || f->is_vf) &&
1175 (!is_netdev || f->is_netdev))
1176 return f;
1177 }
1178 return NULL;
1179}
1180
1181/**
1182 * i40e_find_mac - Find a mac addr in the macvlan filters list
1183 * @vsi: the VSI to be searched
1184 * @macaddr: the MAC address we are searching for
b40c82e6 1185 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1186 * @is_netdev: make sure its a netdev filter, else doesn't matter
1187 *
1188 * Returns the first filter with the provided MAC address or NULL if
1189 * MAC address was not found
1190 **/
1191struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
1192 bool is_vf, bool is_netdev)
1193{
1194 struct i40e_mac_filter *f;
1195
1196 if (!vsi || !macaddr)
1197 return NULL;
1198
1199 list_for_each_entry(f, &vsi->mac_filter_list, list) {
1200 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1201 (!is_vf || f->is_vf) &&
1202 (!is_netdev || f->is_netdev))
1203 return f;
1204 }
1205 return NULL;
1206}
1207
1208/**
1209 * i40e_is_vsi_in_vlan - Check if VSI is in vlan mode
1210 * @vsi: the VSI to be searched
1211 *
1212 * Returns true if VSI is in vlan mode or false otherwise
1213 **/
1214bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1215{
1216 struct i40e_mac_filter *f;
1217
1218 /* Only -1 for all the filters denotes not in vlan mode
1219 * so we have to go through all the list in order to make sure
1220 */
1221 list_for_each_entry(f, &vsi->mac_filter_list, list) {
d9b68f8a 1222 if (f->vlan >= 0 || vsi->info.pvid)
41c445ff
JB		 1223 return true;
1224 }
1225
1226 return false;
1227}
1228
1229/**
1230 * i40e_put_mac_in_vlan - Make macvlan filters from macaddrs and vlans
1231 * @vsi: the VSI to be searched
1232 * @macaddr: the mac address to be filtered
b40c82e6 1233 * @is_vf: true if it is a VF
41c445ff
JB		 1234 * @is_netdev: true if it is a netdev
1235 *
1236 * Goes through all the macvlan filters and adds a
1237 * macvlan filter for each unique vlan that already exists
1238 *
1239 * Returns first filter found on success, else NULL
1240 **/
1241struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
1242 bool is_vf, bool is_netdev)
1243{
1244 struct i40e_mac_filter *f;
1245
1246 list_for_each_entry(f, &vsi->mac_filter_list, list) {
ecbb44e8
MW		 1247 if (vsi->info.pvid)
1248 f->vlan = le16_to_cpu(vsi->info.pvid);
41c445ff
JB		 1249 if (!i40e_find_filter(vsi, macaddr, f->vlan,
1250 is_vf, is_netdev)) {
1251 if (!i40e_add_filter(vsi, macaddr, f->vlan,
8fb905b3 1252 is_vf, is_netdev))
41c445ff
JB		 1253 return NULL;
1254 }
1255 }
1256
1257 return list_first_entry_or_null(&vsi->mac_filter_list,
1258 struct i40e_mac_filter, list);
1259}
1260
8c27d42e
GR		 1261/**
1262 * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
1263 * @vsi: the PF Main VSI - inappropriate for any other VSI
1264 * @macaddr: the MAC address
30650cc5
SN		 1265 *
1266 * Some older firmware configurations set up a default promiscuous VLAN
1267 * filter that needs to be removed.
8c27d42e 1268 **/
30650cc5 1269static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
8c27d42e
GR		 1270{
1271 struct i40e_aqc_remove_macvlan_element_data element;
1272 struct i40e_pf *pf = vsi->back;
f1c7e72e 1273 i40e_status ret;
8c27d42e
GR		 1274
1275 /* Only appropriate for the PF main VSI */
1276 if (vsi->type != I40E_VSI_MAIN)
30650cc5 1277 return -EINVAL;
8c27d42e 1278
30650cc5 1279 memset(&element, 0, sizeof(element));
8c27d42e
GR		 1280 ether_addr_copy(element.mac_addr, macaddr);
1281 element.vlan_tag = 0;
1282 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1283 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
f1c7e72e
SN		 1284 ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1285 if (ret)
30650cc5
SN		 1286 return -ENOENT;
1287
1288 return 0;
8c27d42e
GR		 1289}
1290
41c445ff
JB		 1291/**
1292 * i40e_add_filter - Add a mac/vlan filter to the VSI
1293 * @vsi: the VSI to be searched
1294 * @macaddr: the MAC address
1295 * @vlan: the vlan
b40c82e6 1296 * @is_vf: make sure its a VF filter, else doesn't matter
41c445ff
JB		 1297 * @is_netdev: make sure its a netdev filter, else doesn't matter
1298 *
1299 * Returns ptr to the filter object or NULL when no memory available.
21659035
KP		 1300 *
1301 * NOTE: This function is expected to be called with mac_filter_list_lock
1302 * being held.
41c445ff
JB		 1303 **/
1304struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1305 u8 *macaddr, s16 vlan,
1306 bool is_vf, bool is_netdev)
1307{
1308 struct i40e_mac_filter *f;
1309
1310 if (!vsi || !macaddr)
1311 return NULL;
1312
1313 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1314 if (!f) {
1315 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1316 if (!f)
1317 goto add_filter_out;
1318
9a173901 1319 ether_addr_copy(f->macaddr, macaddr);
41c445ff
JB		 1320 f->vlan = vlan;
1321 f->changed = true;
1322
1323 INIT_LIST_HEAD(&f->list);
1324 list_add(&f->list, &vsi->mac_filter_list);
1325 }
1326
1327 /* increment counter and add a new flag if needed */
1328 if (is_vf) {
1329 if (!f->is_vf) {
1330 f->is_vf = true;
1331 f->counter++;
1332 }
1333 } else if (is_netdev) {
1334 if (!f->is_netdev) {
1335 f->is_netdev = true;
1336 f->counter++;
1337 }
1338 } else {
1339 f->counter++;
1340 }
1341
1342 /* changed tells sync_filters_subtask to
1343 * push the filter down to the firmware
1344 */
1345 if (f->changed) {
1346 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1347 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1348 }
1349
1350add_filter_out:
1351 return f;
1352}
1353
1354/**
1355 * i40e_del_filter - Remove a mac/vlan filter from the VSI
1356 * @vsi: the VSI to be searched
1357 * @macaddr: the MAC address
1358 * @vlan: the vlan
b40c82e6 1359 * @is_vf: make sure it's a VF filter, else doesn't matter
41c445ff 1360 * @is_netdev: make sure it's a netdev filter, else doesn't matter
21659035
KP		 1361 *
1362 * NOTE: This function is expected to be called with mac_filter_list_lock
1363 * being held.
41c445ff
JB		 1364 **/
1365void i40e_del_filter(struct i40e_vsi *vsi,
1366 u8 *macaddr, s16 vlan,
1367 bool is_vf, bool is_netdev)
1368{
1369 struct i40e_mac_filter *f;
1370
1371 if (!vsi || !macaddr)
1372 return;
1373
1374 f = i40e_find_filter(vsi, macaddr, vlan, is_vf, is_netdev);
1375 if (!f || f->counter == 0)
1376 return;
1377
1378 if (is_vf) {
1379 if (f->is_vf) {
1380 f->is_vf = false;
1381 f->counter--;
1382 }
1383 } else if (is_netdev) {
1384 if (f->is_netdev) {
1385 f->is_netdev = false;
1386 f->counter--;
1387 }
1388 } else {
b40c82e6 1389 /* make sure we don't remove a filter in use by VF or netdev */
41c445ff 1390 int min_f = 0;
6995b36c 1391
41c445ff
JB		 1392 min_f += (f->is_vf ? 1 : 0);
1393 min_f += (f->is_netdev ? 1 : 0);
1394
1395 if (f->counter > min_f)
1396 f->counter--;
1397 }
1398
1399 /* counter == 0 tells sync_filters_subtask to
1400 * remove the filter from the firmware's list
1401 */
1402 if (f->counter == 0) {
1403 f->changed = true;
1404 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1405 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1406 }
1407}
1408
1409/**
1410 * i40e_set_mac - NDO callback to set mac address
1411 * @netdev: network interface device structure
1412 * @p: pointer to an address structure
1413 *
1414 * Returns 0 on success, negative on failure
1415 **/
38e00438
VD		 1416#ifdef I40E_FCOE
1417int i40e_set_mac(struct net_device *netdev, void *p)
1418#else
41c445ff 1419static int i40e_set_mac(struct net_device *netdev, void *p)
38e00438 1420#endif
41c445ff
JB		 1421{
1422 struct i40e_netdev_priv *np = netdev_priv(netdev);
1423 struct i40e_vsi *vsi = np->vsi;
30650cc5
SN		 1424 struct i40e_pf *pf = vsi->back;
1425 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 1426 struct sockaddr *addr = p;
1427 struct i40e_mac_filter *f;
1428
1429 if (!is_valid_ether_addr(addr->sa_data))
1430 return -EADDRNOTAVAIL;
1431
30650cc5
SN		 1432 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1433 netdev_info(netdev, "already using mac address %pM\n",
1434 addr->sa_data);
1435 return 0;
1436 }
41c445ff 1437
80f6428f
ASJ		 1438 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
1439 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
1440 return -EADDRNOTAVAIL;
1441
30650cc5
SN		 1442 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1443 netdev_info(netdev, "returning to hw mac address %pM\n",
1444 hw->mac.addr);
1445 else
1446 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1447
41c445ff
JB		 1448 if (vsi->type == I40E_VSI_MAIN) {
1449 i40e_status ret;
6995b36c 1450
41c445ff 1451 ret = i40e_aq_mac_address_write(&vsi->back->hw,
cc41222c 1452 I40E_AQC_WRITE_TYPE_LAA_WOL,
41c445ff
JB		 1453 addr->sa_data, NULL);
1454 if (ret) {
1455 netdev_info(netdev,
1456 "Addr change for Main VSI failed: %d\n",
1457 ret);
1458 return -EADDRNOTAVAIL;
1459 }
41c445ff
JB		 1460 }
1461
30650cc5
SN		 1462 if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
1463 struct i40e_aqc_remove_macvlan_element_data element;
6c8ad1ba 1464
30650cc5
SN		 1465 memset(&element, 0, sizeof(element));
1466 ether_addr_copy(element.mac_addr, netdev->dev_addr);
1467 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1468 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1469 } else {
21659035 1470 spin_lock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba
SN		 1471 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
1472 false, false);
21659035 1473 spin_unlock_bh(&vsi->mac_filter_list_lock);
6c8ad1ba 1474 }
41c445ff 1475
30650cc5
SN		 1476 if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
1477 struct i40e_aqc_add_macvlan_element_data element;
1478
1479 memset(&element, 0, sizeof(element));
1480 ether_addr_copy(element.mac_addr, hw->mac.addr);
1481 element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
1482 i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1483 } else {
21659035 1484 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1485 f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
1486 false, false);
1487 if (f)
1488 f->is_laa = true;
21659035 1489 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 1490 }
1491
30650cc5 1492 ether_addr_copy(netdev->dev_addr, addr->sa_data);
ea02e90b
MW		 1493
1494 return i40e_sync_vsi_filters(vsi);
41c445ff
JB		 1495}
1496
1497/**
1498 * i40e_vsi_setup_queue_map - Setup a VSI queue map based on enabled_tc
1499 * @vsi: the VSI being setup
1500 * @ctxt: VSI context structure
1501 * @enabled_tc: Enabled TCs bitmap
1502 * @is_add: True if called before Add VSI
1503 *
1504 * Setup VSI queue mapping for enabled traffic classes.
1505 **/
38e00438
VD		 1506#ifdef I40E_FCOE
1507void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1508 struct i40e_vsi_context *ctxt,
1509 u8 enabled_tc,
1510 bool is_add)
1511#else
41c445ff
JB		 1512static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1513 struct i40e_vsi_context *ctxt,
1514 u8 enabled_tc,
1515 bool is_add)
38e00438 1516#endif
41c445ff
JB		 1517{
1518 struct i40e_pf *pf = vsi->back;
1519 u16 sections = 0;
1520 u8 netdev_tc = 0;
1521 u16 numtc = 0;
1522 u16 qcount;
1523 u8 offset;
1524 u16 qmap;
1525 int i;
4e3b35b0 1526 u16 num_tc_qps = 0;
41c445ff
JB		 1527
1528 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1529 offset = 0;
1530
1531 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1532 /* Find numtc from enabled TC bitmap */
1533 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 1534 if (enabled_tc & BIT_ULL(i)) /* TC is enabled */
41c445ff
JB		 1535 numtc++;
1536 }
1537 if (!numtc) {
1538 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1539 numtc = 1;
1540 }
1541 } else {
1542 /* At least TC0 is enabled in case of non-DCB case */
1543 numtc = 1;
1544 }
1545
1546 vsi->tc_config.numtc = numtc;
1547 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
4e3b35b0 1548 /* Number of queues per enabled TC */
7f9ff476
AS		 1549 /* In MFP case we can have a much lower count of MSIx
1550 * vectors available and so we need to lower the used
1551 * q count.
1552 */
26cdc443
ASJ		 1553 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1554 qcount = min_t(int, vsi->alloc_queue_pairs, pf->num_lan_msix);
1555 else
1556 qcount = vsi->alloc_queue_pairs;
7f9ff476 1557 num_tc_qps = qcount / numtc;
e25d00b8 1558 num_tc_qps = min_t(int, num_tc_qps, i40e_pf_get_max_q_per_tc(pf));
41c445ff
JB		 1559
1560 /* Setup queue offset/count for all TCs for given VSI */
1561 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1562 /* See if the given TC is enabled for the given VSI */
41a1d04b
JB		 1563 if (vsi->tc_config.enabled_tc & BIT_ULL(i)) {
1564 /* TC is enabled */
41c445ff
JB		 1565 int pow, num_qps;
1566
41c445ff
JB		 1567 switch (vsi->type) {
1568 case I40E_VSI_MAIN:
acd65448
HZ		 1569 qcount = min_t(int, pf->alloc_rss_size,
1570 num_tc_qps);
41c445ff 1571 break;
38e00438
VD		 1572#ifdef I40E_FCOE
1573 case I40E_VSI_FCOE:
1574 qcount = num_tc_qps;
1575 break;
1576#endif
41c445ff
JB		 1577 case I40E_VSI_FDIR:
1578 case I40E_VSI_SRIOV:
1579 case I40E_VSI_VMDQ2:
1580 default:
4e3b35b0 1581 qcount = num_tc_qps;
41c445ff
JB		 1582 WARN_ON(i != 0);
1583 break;
1584 }
4e3b35b0
NP		 1585 vsi->tc_config.tc_info[i].qoffset = offset;
1586 vsi->tc_config.tc_info[i].qcount = qcount;
41c445ff 1587
1e200e4a 1588 /* find the next higher power-of-2 of num queue pairs */
4e3b35b0 1589 num_qps = qcount;
41c445ff 1590 pow = 0;
41a1d04b 1591 while (num_qps && (BIT_ULL(pow) < qcount)) {
41c445ff
JB		 1592 pow++;
1593 num_qps >>= 1;
1594 }
1595
1596 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1597 qmap =
1598 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1599 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1600
4e3b35b0 1601 offset += qcount;
41c445ff
JB		 1602 } else {
1603 /* TC is not enabled so set the offset to
1604 * default queue and allocate one queue
1605 * for the given TC.
1606 */
1607 vsi->tc_config.tc_info[i].qoffset = 0;
1608 vsi->tc_config.tc_info[i].qcount = 1;
1609 vsi->tc_config.tc_info[i].netdev_tc = 0;
1610
1611 qmap = 0;
1612 }
1613 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1614 }
1615
1616 /* Set actual Tx/Rx queue pairs */
1617 vsi->num_queue_pairs = offset;
9a3bd2f1
ASJ		 1618 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1619 if (vsi->req_queue_pairs > 0)
1620 vsi->num_queue_pairs = vsi->req_queue_pairs;
26cdc443 1621 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9a3bd2f1
ASJ		 1622 vsi->num_queue_pairs = pf->num_lan_msix;
1623 }
41c445ff
JB		 1624
1625 /* Scheduler section valid can only be set for ADD VSI */
1626 if (is_add) {
1627 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1628
1629 ctxt->info.up_enable_bits = enabled_tc;
1630 }
1631 if (vsi->type == I40E_VSI_SRIOV) {
1632 ctxt->info.mapping_flags |=
1633 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1634 for (i = 0; i < vsi->num_queue_pairs; i++)
1635 ctxt->info.queue_mapping[i] =
1636 cpu_to_le16(vsi->base_queue + i);
1637 } else {
1638 ctxt->info.mapping_flags |=
1639 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1640 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1641 }
1642 ctxt->info.valid_sections |= cpu_to_le16(sections);
1643}
1644
1645/**
1646 * i40e_set_rx_mode - NDO callback to set the netdev filters
1647 * @netdev: network interface device structure
1648 **/
38e00438
VD		 1649#ifdef I40E_FCOE
1650void i40e_set_rx_mode(struct net_device *netdev)
1651#else
41c445ff 1652static void i40e_set_rx_mode(struct net_device *netdev)
38e00438 1653#endif
41c445ff
JB		 1654{
1655 struct i40e_netdev_priv *np = netdev_priv(netdev);
1656 struct i40e_mac_filter *f, *ftmp;
1657 struct i40e_vsi *vsi = np->vsi;
1658 struct netdev_hw_addr *uca;
1659 struct netdev_hw_addr *mca;
1660 struct netdev_hw_addr *ha;
1661
21659035
KP		 1662 spin_lock_bh(&vsi->mac_filter_list_lock);
1663
41c445ff
JB		 1664 /* add addr if not already in the filter list */
1665 netdev_for_each_uc_addr(uca, netdev) {
1666 if (!i40e_find_mac(vsi, uca->addr, false, true)) {
1667 if (i40e_is_vsi_in_vlan(vsi))
1668 i40e_put_mac_in_vlan(vsi, uca->addr,
1669 false, true);
1670 else
1671 i40e_add_filter(vsi, uca->addr, I40E_VLAN_ANY,
1672 false, true);
1673 }
1674 }
1675
1676 netdev_for_each_mc_addr(mca, netdev) {
1677 if (!i40e_find_mac(vsi, mca->addr, false, true)) {
1678 if (i40e_is_vsi_in_vlan(vsi))
1679 i40e_put_mac_in_vlan(vsi, mca->addr,
1680 false, true);
1681 else
1682 i40e_add_filter(vsi, mca->addr, I40E_VLAN_ANY,
1683 false, true);
1684 }
1685 }
1686
1687 /* remove filter if not in netdev list */
1688 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
41c445ff
JB		 1689
1690 if (!f->is_netdev)
1691 continue;
1692
2f41f335
SN		 1693 netdev_for_each_mc_addr(mca, netdev)
1694 if (ether_addr_equal(mca->addr, f->macaddr))
1695 goto bottom_of_search_loop;
41c445ff 1696
2f41f335
SN		 1697 netdev_for_each_uc_addr(uca, netdev)
1698 if (ether_addr_equal(uca->addr, f->macaddr))
1699 goto bottom_of_search_loop;
1700
1701 for_each_dev_addr(netdev, ha)
1702 if (ether_addr_equal(ha->addr, f->macaddr))
1703 goto bottom_of_search_loop;
1704
1705 /* f->macaddr wasn't found in uc, mc, or ha list so delete it */
1706 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY, false, true);
1707
1708bottom_of_search_loop:
1709 continue;
41c445ff 1710 }
21659035 1711 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1712
1713 /* check for other flag changes */
1714 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1715 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1716 vsi->back->flags |= I40E_FLAG_FILTER_SYNC;
1717 }
1718}
1719
21659035
KP		 1720/**
1721 * i40e_mac_filter_entry_clone - Clones a MAC filter entry
1722 * @src: source MAC filter entry to be clones
1723 *
1724 * Returns the pointer to newly cloned MAC filter entry or NULL
1725 * in case of error
1726 **/
1727static struct i40e_mac_filter *i40e_mac_filter_entry_clone(
1728 struct i40e_mac_filter *src)
1729{
1730 struct i40e_mac_filter *f;
1731
1732 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1733 if (!f)
1734 return NULL;
1735 *f = *src;
1736
1737 INIT_LIST_HEAD(&f->list);
1738
1739 return f;
1740}
1741
1742/**
1743 * i40e_undo_del_filter_entries - Undo the changes made to MAC filter entries
1744 * @vsi: pointer to vsi struct
1745 * @from: Pointer to list which contains MAC filter entries - changes to
1746 * those entries needs to be undone.
1747 *
1748 * MAC filter entries from list were slated to be removed from device.
1749 **/
1750static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1751 struct list_head *from)
1752{
1753 struct i40e_mac_filter *f, *ftmp;
1754
1755 list_for_each_entry_safe(f, ftmp, from, list) {
1756 f->changed = true;
1757 /* Move the element back into MAC filter list*/
1758 list_move_tail(&f->list, &vsi->mac_filter_list);
1759 }
1760}
1761
1762/**
1763 * i40e_undo_add_filter_entries - Undo the changes made to MAC filter entries
1764 * @vsi: pointer to vsi struct
1765 *
1766 * MAC filter entries from list were slated to be added from device.
1767 **/
1768static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi)
1769{
1770 struct i40e_mac_filter *f, *ftmp;
1771
1772 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1773 if (!f->changed && f->counter)
1774 f->changed = true;
1775 }
1776}
1777
1778/**
1779 * i40e_cleanup_add_list - Deletes the element from add list and release
1780 * memory
1781 * @add_list: Pointer to list which contains MAC filter entries
1782 **/
1783static void i40e_cleanup_add_list(struct list_head *add_list)
1784{
1785 struct i40e_mac_filter *f, *ftmp;
1786
1787 list_for_each_entry_safe(f, ftmp, add_list, list) {
1788 list_del(&f->list);
1789 kfree(f);
1790 }
1791}
1792
41c445ff
JB		 1793/**
1794 * i40e_sync_vsi_filters - Update the VSI filter list to the HW
1795 * @vsi: ptr to the VSI
1796 *
1797 * Push any outstanding VSI filter changes through the AdminQ.
1798 *
1799 * Returns 0 or error value
1800 **/
17652c63 1801int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
41c445ff 1802{
21659035
KP		 1803 struct list_head tmp_del_list, tmp_add_list;
1804 struct i40e_mac_filter *f, *ftmp, *fclone;
41c445ff
JB		 1805 bool promisc_forced_on = false;
1806 bool add_happened = false;
1807 int filter_list_len = 0;
1808 u32 changed_flags = 0;
ea02e90b 1809 i40e_status aq_ret = 0;
21659035 1810 bool err_cond = false;
ea02e90b 1811 int retval = 0;
41c445ff
JB		 1812 struct i40e_pf *pf;
1813 int num_add = 0;
1814 int num_del = 0;
f1c7e72e 1815 int aq_err = 0;
41c445ff
JB		 1816 u16 cmd_flags;
1817
1818 /* empty array typed pointers, kcalloc later */
1819 struct i40e_aqc_add_macvlan_element_data *add_list;
1820 struct i40e_aqc_remove_macvlan_element_data *del_list;
1821
1822 while (test_and_set_bit(__I40E_CONFIG_BUSY, &vsi->state))
1823 usleep_range(1000, 2000);
1824 pf = vsi->back;
1825
1826 if (vsi->netdev) {
1827 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
1828 vsi->current_netdev_flags = vsi->netdev->flags;
1829 }
1830
21659035
KP		 1831 INIT_LIST_HEAD(&tmp_del_list);
1832 INIT_LIST_HEAD(&tmp_add_list);
1833
41c445ff
JB		 1834 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
1835 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
1836
21659035 1837 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 1838 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1839 if (!f->changed)
1840 continue;
1841
1842 if (f->counter != 0)
1843 continue;
1844 f->changed = false;
21659035
KP		 1845
1846 /* Move the element into temporary del_list */
1847 list_move_tail(&f->list, &tmp_del_list);
1848 }
1849
1850 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
1851 if (!f->changed)
1852 continue;
1853
1854 if (f->counter == 0)
1855 continue;
1856 f->changed = false;
1857
1858 /* Clone MAC filter entry and add into temporary list */
1859 fclone = i40e_mac_filter_entry_clone(f);
1860 if (!fclone) {
1861 err_cond = true;
1862 break;
1863 }
1864 list_add_tail(&fclone->list, &tmp_add_list);
1865 }
1866
1867 /* if failed to clone MAC filter entry - undo */
1868 if (err_cond) {
1869 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1870 i40e_undo_add_filter_entries(vsi);
1871 }
1872 spin_unlock_bh(&vsi->mac_filter_list_lock);
1873
ea02e90b 1874 if (err_cond) {
21659035 1875 i40e_cleanup_add_list(&tmp_add_list);
ea02e90b
MW		 1876 retval = -ENOMEM;
1877 goto out;
1878 }
21659035
KP		 1879 }
1880
1881 /* Now process 'del_list' outside the lock */
1882 if (!list_empty(&tmp_del_list)) {
1883 filter_list_len = pf->hw.aq.asq_buf_size /
1884 sizeof(struct i40e_aqc_remove_macvlan_element_data);
1885 del_list = kcalloc(filter_list_len,
1886 sizeof(struct i40e_aqc_remove_macvlan_element_data),
1887 GFP_KERNEL);
1888 if (!del_list) {
1889 i40e_cleanup_add_list(&tmp_add_list);
1890
1891 /* Undo VSI's MAC filter entry element updates */
1892 spin_lock_bh(&vsi->mac_filter_list_lock);
1893 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
1894 i40e_undo_add_filter_entries(vsi);
1895 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1896 retval = -ENOMEM;
1897 goto out;
21659035
KP		 1898 }
1899
1900 list_for_each_entry_safe(f, ftmp, &tmp_del_list, list) {
41c445ff
JB		 1901 cmd_flags = 0;
1902
1903 /* add to delete list */
9a173901 1904 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
41c445ff
JB		 1905 del_list[num_del].vlan_tag =
1906 cpu_to_le16((u16)(f->vlan ==
1907 I40E_VLAN_ANY ? 0 : f->vlan));
1908
41c445ff
JB		 1909 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1910 del_list[num_del].flags = cmd_flags;
1911 num_del++;
1912
41c445ff
JB		 1913 /* flush a full buffer */
1914 if (num_del == filter_list_len) {
ea02e90b
MW		 1915 aq_ret = i40e_aq_remove_macvlan(&pf->hw,
1916 vsi->seid,
1917 del_list,
1918 num_del,
1919 NULL);
f1c7e72e 1920 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1921 num_del = 0;
1922 memset(del_list, 0, sizeof(*del_list));
1923
ea02e90b
MW		 1924 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT) {
1925 retval = -EIO;
21659035
KP		 1926 dev_err(&pf->pdev->dev,
1927 "ignoring delete macvlan error, err %s, aq_err %s while flushing a full buffer\n",
ea02e90b 1928 i40e_stat_str(&pf->hw, aq_ret),
21659035 1929 i40e_aq_str(&pf->hw, aq_err));
ea02e90b 1930 }
41c445ff 1931 }
21659035
KP		 1932 /* Release memory for MAC filter entries which were
1933 * synced up with HW.
1934 */
1935 list_del(&f->list);
1936 kfree(f);
41c445ff 1937 }
21659035 1938
41c445ff 1939 if (num_del) {
ea02e90b
MW		 1940 aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid,
1941 del_list, num_del,
1942 NULL);
f1c7e72e 1943 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1944 num_del = 0;
1945
ea02e90b 1946 if (aq_ret && aq_err != I40E_AQ_RC_ENOENT)
41c445ff 1947 dev_info(&pf->pdev->dev,
f1c7e72e 1948 "ignoring delete macvlan error, err %s aq_err %s\n",
ea02e90b 1949 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 1950 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 1951 }
1952
1953 kfree(del_list);
1954 del_list = NULL;
21659035
KP		 1955 }
1956
1957 if (!list_empty(&tmp_add_list)) {
41c445ff
JB		 1958
1959 /* do all the adds now */
1960 filter_list_len = pf->hw.aq.asq_buf_size /
1961 sizeof(struct i40e_aqc_add_macvlan_element_data),
1962 add_list = kcalloc(filter_list_len,
1963 sizeof(struct i40e_aqc_add_macvlan_element_data),
1964 GFP_KERNEL);
21659035
KP		 1965 if (!add_list) {
1966 /* Purge element from temporary lists */
1967 i40e_cleanup_add_list(&tmp_add_list);
1968
1969 /* Undo add filter entries from VSI MAC filter list */
1970 spin_lock_bh(&vsi->mac_filter_list_lock);
1971 i40e_undo_add_filter_entries(vsi);
1972 spin_unlock_bh(&vsi->mac_filter_list_lock);
ea02e90b
MW		 1973 retval = -ENOMEM;
1974 goto out;
21659035 1975 }
41c445ff 1976
21659035 1977 list_for_each_entry_safe(f, ftmp, &tmp_add_list, list) {
41c445ff 1978
41c445ff
JB		 1979 add_happened = true;
1980 cmd_flags = 0;
1981
1982 /* add to add array */
9a173901 1983 ether_addr_copy(add_list[num_add].mac_addr, f->macaddr);
41c445ff
JB		 1984 add_list[num_add].vlan_tag =
1985 cpu_to_le16(
1986 (u16)(f->vlan == I40E_VLAN_ANY ? 0 : f->vlan));
1987 add_list[num_add].queue_number = 0;
1988
1989 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
41c445ff
JB		 1990 add_list[num_add].flags = cpu_to_le16(cmd_flags);
1991 num_add++;
1992
1993 /* flush a full buffer */
1994 if (num_add == filter_list_len) {
ea02e90b
MW		 1995 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
1996 add_list, num_add,
1997 NULL);
f1c7e72e 1998 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 1999 num_add = 0;
2000
ea02e90b 2001 if (aq_ret)
41c445ff
JB		 2002 break;
2003 memset(add_list, 0, sizeof(*add_list));
2004 }
21659035
KP		 2005 /* Entries from tmp_add_list were cloned from MAC
2006 * filter list, hence clean those cloned entries
2007 */
2008 list_del(&f->list);
2009 kfree(f);
41c445ff 2010 }
21659035 2011
41c445ff 2012 if (num_add) {
ea02e90b
MW		 2013 aq_ret = i40e_aq_add_macvlan(&pf->hw, vsi->seid,
2014 add_list, num_add, NULL);
f1c7e72e 2015 aq_err = pf->hw.aq.asq_last_status;
41c445ff
JB		 2016 num_add = 0;
2017 }
2018 kfree(add_list);
2019 add_list = NULL;
2020
ea02e90b
MW		 2021 if (add_happened && aq_ret && aq_err != I40E_AQ_RC_EINVAL) {
2022 retval = i40e_aq_rc_to_posix(aq_ret, aq_err);
41c445ff 2023 dev_info(&pf->pdev->dev,
f1c7e72e 2024 "add filter failed, err %s aq_err %s\n",
ea02e90b 2025 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e 2026 i40e_aq_str(&pf->hw, aq_err));
41c445ff
JB		 2027 if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOSPC) &&
2028 !test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2029 &vsi->state)) {
2030 promisc_forced_on = true;
2031 set_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2032 &vsi->state);
2033 dev_info(&pf->pdev->dev, "promiscuous mode forced on\n");
2034 }
2035 }
2036 }
2037
2038 /* check for changes in promiscuous modes */
2039 if (changed_flags & IFF_ALLMULTI) {
2040 bool cur_multipromisc;
6995b36c 2041
41c445ff 2042 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
ea02e90b
MW		 2043 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2044 vsi->seid,
2045 cur_multipromisc,
2046 NULL);
2047 if (aq_ret) {
2048 retval = i40e_aq_rc_to_posix(aq_ret,
2049 pf->hw.aq.asq_last_status);
41c445ff 2050 dev_info(&pf->pdev->dev,
f1c7e72e 2051 "set multi promisc failed, err %s aq_err %s\n",
ea02e90b 2052 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2053 i40e_aq_str(&pf->hw,
2054 pf->hw.aq.asq_last_status));
ea02e90b 2055 }
41c445ff
JB		 2056 }
2057 if ((changed_flags & IFF_PROMISC) || promisc_forced_on) {
2058 bool cur_promisc;
6995b36c 2059
41c445ff
JB		 2060 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2061 test_bit(__I40E_FILTER_OVERFLOW_PROMISC,
2062 &vsi->state));
92faef85
ASJ		 2063 if (vsi->type == I40E_VSI_MAIN && pf->lan_veb != I40E_NO_VEB) {
2064 /* set defport ON for Main VSI instead of true promisc
2065 * this way we will get all unicast/multicast and VLAN
2066 * promisc behavior but will not get VF or VMDq traffic
2067 * replicated on the Main VSI.
2068 */
2069 if (pf->cur_promisc != cur_promisc) {
2070 pf->cur_promisc = cur_promisc;
0e4425ed 2071 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
92faef85
ASJ		 2072 }
2073 } else {
ea02e90b 2074 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
92faef85 2075 &vsi->back->hw,
f1c7e72e
SN		 2076 vsi->seid,
2077 cur_promisc, NULL);
ea02e90b
MW		 2078 if (aq_ret) {
2079 retval =
2080 i40e_aq_rc_to_posix(aq_ret,
2081 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2082 dev_info(&pf->pdev->dev,
2083 "set unicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2084 aq_ret, pf->hw.aq.asq_last_status);
2085 }
2086 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
92faef85
ASJ		 2087 &vsi->back->hw,
2088 vsi->seid,
2089 cur_promisc, NULL);
ea02e90b
MW		 2090 if (aq_ret) {
2091 retval =
2092 i40e_aq_rc_to_posix(aq_ret,
2093 pf->hw.aq.asq_last_status);
92faef85
ASJ		 2094 dev_info(&pf->pdev->dev,
2095 "set multicast promisc failed, err %d, aq_err %d\n",
ea02e90b
MW		 2096 aq_ret, pf->hw.aq.asq_last_status);
2097 }
92faef85 2098 }
ea02e90b
MW		 2099 aq_ret = i40e_aq_set_vsi_broadcast(&vsi->back->hw,
2100 vsi->seid,
2101 cur_promisc, NULL);
2102 if (aq_ret) {
2103 retval = i40e_aq_rc_to_posix(aq_ret,
2104 pf->hw.aq.asq_last_status);
1a10370a 2105 dev_info(&pf->pdev->dev,
f1c7e72e 2106 "set brdcast promisc failed, err %s, aq_err %s\n",
ea02e90b 2107 i40e_stat_str(&pf->hw, aq_ret),
f1c7e72e
SN		 2108 i40e_aq_str(&pf->hw,
2109 pf->hw.aq.asq_last_status));
ea02e90b 2110 }
41c445ff 2111 }
ea02e90b 2112out:
41c445ff 2113 clear_bit(__I40E_CONFIG_BUSY, &vsi->state);
ea02e90b 2114 return retval;
41c445ff
JB		 2115}
2116
2117/**
2118 * i40e_sync_filters_subtask - Sync the VSI filter list with HW
2119 * @pf: board private structure
2120 **/
2121static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2122{
2123 int v;
2124
2125 if (!pf || !(pf->flags & I40E_FLAG_FILTER_SYNC))
2126 return;
2127 pf->flags &= ~I40E_FLAG_FILTER_SYNC;
2128
505682cd 2129 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 2130 if (pf->vsi[v] &&
17652c63
JB		 2131 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2132 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2133
2134 if (ret) {
2135 /* come back and try again later */
2136 pf->flags |= I40E_FLAG_FILTER_SYNC;
2137 break;
2138 }
2139 }
41c445ff
JB		 2140 }
2141}
2142
2143/**
2144 * i40e_change_mtu - NDO callback to change the Maximum Transfer Unit
2145 * @netdev: network interface device structure
2146 * @new_mtu: new value for maximum frame size
2147 *
2148 * Returns 0 on success, negative on failure
2149 **/
2150static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2151{
2152 struct i40e_netdev_priv *np = netdev_priv(netdev);
61a46a4c 2153 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
41c445ff
JB		 2154 struct i40e_vsi *vsi = np->vsi;
2155
2156 /* MTU < 68 is an error and causes problems on some kernels */
2157 if ((new_mtu < 68) || (max_frame > I40E_MAX_RXBUFFER))
2158 return -EINVAL;
2159
2160 netdev_info(netdev, "changing MTU from %d to %d\n",
2161 netdev->mtu, new_mtu);
2162 netdev->mtu = new_mtu;
2163 if (netif_running(netdev))
2164 i40e_vsi_reinit_locked(vsi);
2165
2166 return 0;
2167}
2168
beb0dff1
JK		 2169/**
2170 * i40e_ioctl - Access the hwtstamp interface
2171 * @netdev: network interface device structure
2172 * @ifr: interface request data
2173 * @cmd: ioctl command
2174 **/
2175int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2176{
2177 struct i40e_netdev_priv *np = netdev_priv(netdev);
2178 struct i40e_pf *pf = np->vsi->back;
2179
2180 switch (cmd) {
2181 case SIOCGHWTSTAMP:
2182 return i40e_ptp_get_ts_config(pf, ifr);
2183 case SIOCSHWTSTAMP:
2184 return i40e_ptp_set_ts_config(pf, ifr);
2185 default:
2186 return -EOPNOTSUPP;
2187 }
2188}
2189
41c445ff
JB		 2190/**
2191 * i40e_vlan_stripping_enable - Turn on vlan stripping for the VSI
2192 * @vsi: the vsi being adjusted
2193 **/
2194void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2195{
2196 struct i40e_vsi_context ctxt;
2197 i40e_status ret;
2198
2199 if ((vsi->info.valid_sections &
2200 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2201 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2202 return; /* already enabled */
2203
2204 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2205 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2206 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2207
2208 ctxt.seid = vsi->seid;
1a2f6248 2209 ctxt.info = vsi->info;
41c445ff
JB		 2210 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2211 if (ret) {
2212 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2213 "update vlan stripping failed, err %s aq_err %s\n",
2214 i40e_stat_str(&vsi->back->hw, ret),
2215 i40e_aq_str(&vsi->back->hw,
2216 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2217 }
2218}
2219
2220/**
2221 * i40e_vlan_stripping_disable - Turn off vlan stripping for the VSI
2222 * @vsi: the vsi being adjusted
2223 **/
2224void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2225{
2226 struct i40e_vsi_context ctxt;
2227 i40e_status ret;
2228
2229 if ((vsi->info.valid_sections &
2230 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2231 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2232 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2233 return; /* already disabled */
2234
2235 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2236 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2237 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2238
2239 ctxt.seid = vsi->seid;
1a2f6248 2240 ctxt.info = vsi->info;
41c445ff
JB		 2241 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2242 if (ret) {
2243 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2244 "update vlan stripping failed, err %s aq_err %s\n",
2245 i40e_stat_str(&vsi->back->hw, ret),
2246 i40e_aq_str(&vsi->back->hw,
2247 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 2248 }
2249}
2250
2251/**
2252 * i40e_vlan_rx_register - Setup or shutdown vlan offload
2253 * @netdev: network interface to be adjusted
2254 * @features: netdev features to test if VLAN offload is enabled or not
2255 **/
2256static void i40e_vlan_rx_register(struct net_device *netdev, u32 features)
2257{
2258 struct i40e_netdev_priv *np = netdev_priv(netdev);
2259 struct i40e_vsi *vsi = np->vsi;
2260
2261 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2262 i40e_vlan_stripping_enable(vsi);
2263 else
2264 i40e_vlan_stripping_disable(vsi);
2265}
2266
2267/**
2268 * i40e_vsi_add_vlan - Add vsi membership for given vlan
2269 * @vsi: the vsi being configured
2270 * @vid: vlan id to be added (0 = untagged only , -1 = any)
2271 **/
2272int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid)
2273{
2274 struct i40e_mac_filter *f, *add_f;
2275 bool is_netdev, is_vf;
41c445ff
JB		 2276
2277 is_vf = (vsi->type == I40E_VSI_SRIOV);
2278 is_netdev = !!(vsi->netdev);
2279
21659035
KP		 2280 /* Locked once because all functions invoked below iterates list*/
2281 spin_lock_bh(&vsi->mac_filter_list_lock);
2282
41c445ff
JB		 2283 if (is_netdev) {
2284 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, vid,
2285 is_vf, is_netdev);
2286 if (!add_f) {
2287 dev_info(&vsi->back->pdev->dev,
2288 "Could not add vlan filter %d for %pM\n",
2289 vid, vsi->netdev->dev_addr);
21659035 2290 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2291 return -ENOMEM;
2292 }
2293 }
2294
2295 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2296 add_f = i40e_add_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2297 if (!add_f) {
2298 dev_info(&vsi->back->pdev->dev,
2299 "Could not add vlan filter %d for %pM\n",
2300 vid, f->macaddr);
21659035 2301 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2302 return -ENOMEM;
2303 }
2304 }
2305
41c445ff
JB		 2306 /* Now if we add a vlan tag, make sure to check if it is the first
2307 * tag (i.e. a "tag" -1 does exist) and if so replace the -1 "tag"
2308 * with 0, so we now accept untagged and specified tagged traffic
2309 * (and not any taged and untagged)
2310 */
2311 if (vid > 0) {
2312 if (is_netdev && i40e_find_filter(vsi, vsi->netdev->dev_addr,
2313 I40E_VLAN_ANY,
2314 is_vf, is_netdev)) {
2315 i40e_del_filter(vsi, vsi->netdev->dev_addr,
2316 I40E_VLAN_ANY, is_vf, is_netdev);
2317 add_f = i40e_add_filter(vsi, vsi->netdev->dev_addr, 0,
2318 is_vf, is_netdev);
2319 if (!add_f) {
2320 dev_info(&vsi->back->pdev->dev,
2321 "Could not add filter 0 for %pM\n",
2322 vsi->netdev->dev_addr);
21659035 2323 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2324 return -ENOMEM;
2325 }
2326 }
8d82a7c5 2327 }
41c445ff 2328
8d82a7c5
GR		 2329 /* Do not assume that I40E_VLAN_ANY should be reset to VLAN 0 */
2330 if (vid > 0 && !vsi->info.pvid) {
41c445ff 2331 list_for_each_entry(f, &vsi->mac_filter_list, list) {
21659035
KP		 2332 if (!i40e_find_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2333 is_vf, is_netdev))
2334 continue;
2335 i40e_del_filter(vsi, f->macaddr, I40E_VLAN_ANY,
2336 is_vf, is_netdev);
2337 add_f = i40e_add_filter(vsi, f->macaddr,
2338 0, is_vf, is_netdev);
2339 if (!add_f) {
2340 dev_info(&vsi->back->pdev->dev,
2341 "Could not add filter 0 for %pM\n",
2342 f->macaddr);
2343 spin_unlock_bh(&vsi->mac_filter_list_lock);
2344 return -ENOMEM;
41c445ff
JB		 2345 }
2346 }
41c445ff
JB		 2347 }
2348
21659035
KP		 2349 spin_unlock_bh(&vsi->mac_filter_list_lock);
2350
0e4425ed
JB		 2351 /* schedule our worker thread which will take care of
2352 * applying the new filter changes
2353 */
2354 i40e_service_event_schedule(vsi->back);
2355 return 0;
41c445ff
JB		 2356}
2357
2358/**
2359 * i40e_vsi_kill_vlan - Remove vsi membership for given vlan
2360 * @vsi: the vsi being configured
2361 * @vid: vlan id to be removed (0 = untagged only , -1 = any)
078b5876
JB		 2362 *
2363 * Return: 0 on success or negative otherwise
41c445ff
JB		 2364 **/
2365int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid)
2366{
2367 struct net_device *netdev = vsi->netdev;
2368 struct i40e_mac_filter *f, *add_f;
2369 bool is_vf, is_netdev;
2370 int filter_count = 0;
41c445ff
JB		 2371
2372 is_vf = (vsi->type == I40E_VSI_SRIOV);
2373 is_netdev = !!(netdev);
2374
21659035
KP		 2375 /* Locked once because all functions invoked below iterates list */
2376 spin_lock_bh(&vsi->mac_filter_list_lock);
2377
41c445ff
JB		 2378 if (is_netdev)
2379 i40e_del_filter(vsi, netdev->dev_addr, vid, is_vf, is_netdev);
2380
2381 list_for_each_entry(f, &vsi->mac_filter_list, list)
2382 i40e_del_filter(vsi, f->macaddr, vid, is_vf, is_netdev);
2383
41c445ff
JB		 2384 /* go through all the filters for this VSI and if there is only
2385 * vid == 0 it means there are no other filters, so vid 0 must
2386 * be replaced with -1. This signifies that we should from now
2387 * on accept any traffic (with any tag present, or untagged)
2388 */
2389 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2390 if (is_netdev) {
2391 if (f->vlan &&
2392 ether_addr_equal(netdev->dev_addr, f->macaddr))
2393 filter_count++;
2394 }
2395
2396 if (f->vlan)
2397 filter_count++;
2398 }
2399
2400 if (!filter_count && is_netdev) {
2401 i40e_del_filter(vsi, netdev->dev_addr, 0, is_vf, is_netdev);
2402 f = i40e_add_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
2403 is_vf, is_netdev);
2404 if (!f) {
2405 dev_info(&vsi->back->pdev->dev,
2406 "Could not add filter %d for %pM\n",
2407 I40E_VLAN_ANY, netdev->dev_addr);
21659035 2408 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2409 return -ENOMEM;
2410 }
2411 }
2412
2413 if (!filter_count) {
2414 list_for_each_entry(f, &vsi->mac_filter_list, list) {
2415 i40e_del_filter(vsi, f->macaddr, 0, is_vf, is_netdev);
2416 add_f = i40e_add_filter(vsi, f->macaddr, I40E_VLAN_ANY,
21659035 2417 is_vf, is_netdev);
41c445ff
JB		 2418 if (!add_f) {
2419 dev_info(&vsi->back->pdev->dev,
2420 "Could not add filter %d for %pM\n",
2421 I40E_VLAN_ANY, f->macaddr);
21659035 2422 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 2423 return -ENOMEM;
2424 }
2425 }
2426 }
2427
21659035
KP		 2428 spin_unlock_bh(&vsi->mac_filter_list_lock);
2429
0e4425ed
JB		 2430 /* schedule our worker thread which will take care of
2431 * applying the new filter changes
2432 */
2433 i40e_service_event_schedule(vsi->back);
2434 return 0;
41c445ff
JB		 2435}
2436
2437/**
2438 * i40e_vlan_rx_add_vid - Add a vlan id filter to HW offload
2439 * @netdev: network interface to be adjusted
2440 * @vid: vlan id to be added
078b5876
JB		 2441 *
2442 * net_device_ops implementation for adding vlan ids
41c445ff 2443 **/
38e00438
VD		 2444#ifdef I40E_FCOE
2445int i40e_vlan_rx_add_vid(struct net_device *netdev,
2446 __always_unused __be16 proto, u16 vid)
2447#else
41c445ff
JB		 2448static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2449 __always_unused __be16 proto, u16 vid)
38e00438 2450#endif
41c445ff
JB		 2451{
2452 struct i40e_netdev_priv *np = netdev_priv(netdev);
2453 struct i40e_vsi *vsi = np->vsi;
078b5876 2454 int ret = 0;
41c445ff
JB		 2455
2456 if (vid > 4095)
078b5876
JB		 2457 return -EINVAL;
2458
2459 netdev_info(netdev, "adding %pM vid=%d\n", netdev->dev_addr, vid);
41c445ff 2460
6982d429
ASJ		 2461 /* If the network stack called us with vid = 0 then
2462 * it is asking to receive priority tagged packets with
2463 * vlan id 0. Our HW receives them by default when configured
2464 * to receive untagged packets so there is no need to add an
2465 * extra filter for vlan 0 tagged packets.
41c445ff 2466 */
6982d429
ASJ		 2467 if (vid)
2468 ret = i40e_vsi_add_vlan(vsi, vid);
41c445ff 2469
078b5876
JB		 2470 if (!ret && (vid < VLAN_N_VID))
2471 set_bit(vid, vsi->active_vlans);
41c445ff 2472
078b5876 2473 return ret;
41c445ff
JB		 2474}
2475
2476/**
2477 * i40e_vlan_rx_kill_vid - Remove a vlan id filter from HW offload
2478 * @netdev: network interface to be adjusted
2479 * @vid: vlan id to be removed
078b5876 2480 *
fdfd943e 2481 * net_device_ops implementation for removing vlan ids
41c445ff 2482 **/
38e00438
VD		 2483#ifdef I40E_FCOE
2484int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2485 __always_unused __be16 proto, u16 vid)
2486#else
41c445ff
JB		 2487static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2488 __always_unused __be16 proto, u16 vid)
38e00438 2489#endif
41c445ff
JB		 2490{
2491 struct i40e_netdev_priv *np = netdev_priv(netdev);
2492 struct i40e_vsi *vsi = np->vsi;
2493
078b5876
JB		 2494 netdev_info(netdev, "removing %pM vid=%d\n", netdev->dev_addr, vid);
2495
41c445ff
JB		 2496 /* return code is ignored as there is nothing a user
2497 * can do about failure to remove and a log message was
078b5876 2498 * already printed from the other function
41c445ff
JB		 2499 */
2500 i40e_vsi_kill_vlan(vsi, vid);
2501
2502 clear_bit(vid, vsi->active_vlans);
078b5876 2503
41c445ff
JB		 2504 return 0;
2505}
2506
2507/**
2508 * i40e_restore_vlan - Reinstate vlans when vsi/netdev comes back up
2509 * @vsi: the vsi being brought back up
2510 **/
2511static void i40e_restore_vlan(struct i40e_vsi *vsi)
2512{
2513 u16 vid;
2514
2515 if (!vsi->netdev)
2516 return;
2517
2518 i40e_vlan_rx_register(vsi->netdev, vsi->netdev->features);
2519
2520 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2521 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2522 vid);
2523}
2524
2525/**
2526 * i40e_vsi_add_pvid - Add pvid for the VSI
2527 * @vsi: the vsi being adjusted
2528 * @vid: the vlan id to set as a PVID
2529 **/
dcae29be 2530int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
41c445ff
JB		 2531{
2532 struct i40e_vsi_context ctxt;
f1c7e72e 2533 i40e_status ret;
41c445ff
JB		 2534
2535 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2536 vsi->info.pvid = cpu_to_le16(vid);
6c12fcbf
GR		 2537 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2538 I40E_AQ_VSI_PVLAN_INSERT_PVID |
b774c7dd 2539 I40E_AQ_VSI_PVLAN_EMOD_STR;
41c445ff
JB		 2540
2541 ctxt.seid = vsi->seid;
1a2f6248 2542 ctxt.info = vsi->info;
f1c7e72e
SN		 2543 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2544 if (ret) {
41c445ff 2545 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 2546 "add pvid failed, err %s aq_err %s\n",
2547 i40e_stat_str(&vsi->back->hw, ret),
2548 i40e_aq_str(&vsi->back->hw,
2549 vsi->back->hw.aq.asq_last_status));
dcae29be 2550 return -ENOENT;
41c445ff
JB		 2551 }
2552
dcae29be 2553 return 0;
41c445ff
JB		 2554}
2555
2556/**
2557 * i40e_vsi_remove_pvid - Remove the pvid from the VSI
2558 * @vsi: the vsi being adjusted
2559 *
2560 * Just use the vlan_rx_register() service to put it back to normal
2561 **/
2562void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2563{
6c12fcbf
GR		 2564 i40e_vlan_stripping_disable(vsi);
2565
41c445ff 2566 vsi->info.pvid = 0;
41c445ff
JB		 2567}
2568
2569/**
2570 * i40e_vsi_setup_tx_resources - Allocate VSI Tx queue resources
2571 * @vsi: ptr to the VSI
2572 *
2573 * If this function returns with an error, then it's possible one or
2574 * more of the rings is populated (while the rest are not). It is the
2575 * callers duty to clean those orphaned rings.
2576 *
2577 * Return 0 on success, negative on failure
2578 **/
2579static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2580{
2581 int i, err = 0;
2582
2583 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2584 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
41c445ff
JB		 2585
2586 return err;
2587}
2588
2589/**
2590 * i40e_vsi_free_tx_resources - Free Tx resources for VSI queues
2591 * @vsi: ptr to the VSI
2592 *
2593 * Free VSI's transmit software resources
2594 **/
2595static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2596{
2597 int i;
2598
8e9dca53
GR		 2599 if (!vsi->tx_rings)
2600 return;
2601
41c445ff 2602 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2603 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
9f65e15b 2604 i40e_free_tx_resources(vsi->tx_rings[i]);
41c445ff
JB		 2605}
2606
2607/**
2608 * i40e_vsi_setup_rx_resources - Allocate VSI queues Rx resources
2609 * @vsi: ptr to the VSI
2610 *
2611 * If this function returns with an error, then it's possible one or
2612 * more of the rings is populated (while the rest are not). It is the
2613 * callers duty to clean those orphaned rings.
2614 *
2615 * Return 0 on success, negative on failure
2616 **/
2617static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
2618{
2619 int i, err = 0;
2620
2621 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2622 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
38e00438
VD		 2623#ifdef I40E_FCOE
2624 i40e_fcoe_setup_ddp_resources(vsi);
2625#endif
41c445ff
JB		 2626 return err;
2627}
2628
2629/**
2630 * i40e_vsi_free_rx_resources - Free Rx Resources for VSI queues
2631 * @vsi: ptr to the VSI
2632 *
2633 * Free all receive software resources
2634 **/
2635static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
2636{
2637 int i;
2638
8e9dca53
GR		 2639 if (!vsi->rx_rings)
2640 return;
2641
41c445ff 2642 for (i = 0; i < vsi->num_queue_pairs; i++)
8e9dca53 2643 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
9f65e15b 2644 i40e_free_rx_resources(vsi->rx_rings[i]);
38e00438
VD		 2645#ifdef I40E_FCOE
2646 i40e_fcoe_free_ddp_resources(vsi);
2647#endif
41c445ff
JB		 2648}
2649
3ffa037d
NP		 2650/**
2651 * i40e_config_xps_tx_ring - Configure XPS for a Tx ring
2652 * @ring: The Tx ring to configure
2653 *
2654 * This enables/disables XPS for a given Tx descriptor ring
2655 * based on the TCs enabled for the VSI that ring belongs to.
2656 **/
2657static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
2658{
2659 struct i40e_vsi *vsi = ring->vsi;
2660 cpumask_var_t mask;
2661
9a660eea
JB		 2662 if (!ring->q_vector || !ring->netdev)
2663 return;
2664
2665 /* Single TC mode enable XPS */
2666 if (vsi->tc_config.numtc <= 1) {
2667 if (!test_and_set_bit(__I40E_TX_XPS_INIT_DONE, &ring->state))
3ffa037d
NP		 2668 netif_set_xps_queue(ring->netdev,
2669 &ring->q_vector->affinity_mask,
2670 ring->queue_index);
9a660eea
JB		 2671 } else if (alloc_cpumask_var(&mask, GFP_KERNEL)) {
2672 /* Disable XPS to allow selection based on TC */
2673 bitmap_zero(cpumask_bits(mask), nr_cpumask_bits);
2674 netif_set_xps_queue(ring->netdev, mask, ring->queue_index);
2675 free_cpumask_var(mask);
3ffa037d 2676 }
0e4425ed
JB		 2677
2678 /* schedule our worker thread which will take care of
2679 * applying the new filter changes
2680 */
2681 i40e_service_event_schedule(vsi->back);
3ffa037d
NP		 2682}
2683
41c445ff
JB		 2684/**
2685 * i40e_configure_tx_ring - Configure a transmit ring context and rest
2686 * @ring: The Tx ring to configure
2687 *
2688 * Configure the Tx descriptor ring in the HMC context.
2689 **/
2690static int i40e_configure_tx_ring(struct i40e_ring *ring)
2691{
2692 struct i40e_vsi *vsi = ring->vsi;
2693 u16 pf_q = vsi->base_queue + ring->queue_index;
2694 struct i40e_hw *hw = &vsi->back->hw;
2695 struct i40e_hmc_obj_txq tx_ctx;
2696 i40e_status err = 0;
2697 u32 qtx_ctl = 0;
2698
2699 /* some ATR related tx ring init */
60ea5f83 2700 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
41c445ff
JB		 2701 ring->atr_sample_rate = vsi->back->atr_sample_rate;
2702 ring->atr_count = 0;
2703 } else {
2704 ring->atr_sample_rate = 0;
2705 }
2706
3ffa037d
NP		 2707 /* configure XPS */
2708 i40e_config_xps_tx_ring(ring);
41c445ff
JB		 2709
2710 /* clear the context structure first */
2711 memset(&tx_ctx, 0, sizeof(tx_ctx));
2712
2713 tx_ctx.new_context = 1;
2714 tx_ctx.base = (ring->dma / 128);
2715 tx_ctx.qlen = ring->count;
60ea5f83
JB		 2716 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
2717 I40E_FLAG_FD_ATR_ENABLED));
38e00438
VD		 2718#ifdef I40E_FCOE
2719 tx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2720#endif
beb0dff1 2721 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
1943d8ba
JB		 2722 /* FDIR VSI tx ring can still use RS bit and writebacks */
2723 if (vsi->type != I40E_VSI_FDIR)
2724 tx_ctx.head_wb_ena = 1;
2725 tx_ctx.head_wb_addr = ring->dma +
2726 (ring->count * sizeof(struct i40e_tx_desc));
41c445ff
JB		 2727
2728 /* As part of VSI creation/update, FW allocates certain
2729 * Tx arbitration queue sets for each TC enabled for
2730 * the VSI. The FW returns the handles to these queue
2731 * sets as part of the response buffer to Add VSI,
2732 * Update VSI, etc. AQ commands. It is expected that
2733 * these queue set handles be associated with the Tx
2734 * queues by the driver as part of the TX queue context
2735 * initialization. This has to be done regardless of
2736 * DCB as by default everything is mapped to TC0.
2737 */
2738 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
2739 tx_ctx.rdylist_act = 0;
2740
2741 /* clear the context in the HMC */
2742 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2743 if (err) {
2744 dev_info(&vsi->back->pdev->dev,
2745 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
2746 ring->queue_index, pf_q, err);
2747 return -ENOMEM;
2748 }
2749
2750 /* set the context in the HMC */
2751 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2752 if (err) {
2753 dev_info(&vsi->back->pdev->dev,
2754 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
2755 ring->queue_index, pf_q, err);
2756 return -ENOMEM;
2757 }
2758
2759 /* Now associate this queue with this PCI function */
7a28d885 2760 if (vsi->type == I40E_VSI_VMDQ2) {
9d8bf547 2761 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
7a28d885
MW		 2762 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
2763 I40E_QTX_CTL_VFVM_INDX_MASK;
2764 } else {
9d8bf547 2765 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
7a28d885
MW		 2766 }
2767
13fd9774
SN		 2768 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2769 I40E_QTX_CTL_PF_INDX_MASK);
41c445ff
JB		 2770 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2771 i40e_flush(hw);
2772
41c445ff
JB		 2773 /* cache tail off for easier writes later */
2774 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2775
2776 return 0;
2777}
2778
2779/**
2780 * i40e_configure_rx_ring - Configure a receive ring context
2781 * @ring: The Rx ring to configure
2782 *
2783 * Configure the Rx descriptor ring in the HMC context.
2784 **/
2785static int i40e_configure_rx_ring(struct i40e_ring *ring)
2786{
2787 struct i40e_vsi *vsi = ring->vsi;
2788 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
2789 u16 pf_q = vsi->base_queue + ring->queue_index;
2790 struct i40e_hw *hw = &vsi->back->hw;
2791 struct i40e_hmc_obj_rxq rx_ctx;
2792 i40e_status err = 0;
2793
2794 ring->state = 0;
2795
2796 /* clear the context structure first */
2797 memset(&rx_ctx, 0, sizeof(rx_ctx));
2798
2799 ring->rx_buf_len = vsi->rx_buf_len;
2800 ring->rx_hdr_len = vsi->rx_hdr_len;
2801
2802 rx_ctx.dbuff = ring->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2803 rx_ctx.hbuff = ring->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2804
2805 rx_ctx.base = (ring->dma / 128);
2806 rx_ctx.qlen = ring->count;
2807
2808 if (vsi->back->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED) {
2809 set_ring_16byte_desc_enabled(ring);
2810 rx_ctx.dsize = 0;
2811 } else {
2812 rx_ctx.dsize = 1;
2813 }
2814
2815 rx_ctx.dtype = vsi->dtype;
2816 if (vsi->dtype) {
2817 set_ring_ps_enabled(ring);
2818 rx_ctx.hsplit_0 = I40E_RX_SPLIT_L2 |
2819 I40E_RX_SPLIT_IP |
2820 I40E_RX_SPLIT_TCP_UDP |
2821 I40E_RX_SPLIT_SCTP;
2822 } else {
2823 rx_ctx.hsplit_0 = 0;
2824 }
2825
2826 rx_ctx.rxmax = min_t(u16, vsi->max_frame,
2827 (chain_len * ring->rx_buf_len));
7134f9ce
JB		 2828 if (hw->revision_id == 0)
2829 rx_ctx.lrxqthresh = 0;
2830 else
2831 rx_ctx.lrxqthresh = 2;
41c445ff
JB		 2832 rx_ctx.crcstrip = 1;
2833 rx_ctx.l2tsel = 1;
c4bbac39
JB		 2834 /* this controls whether VLAN is stripped from inner headers */
2835 rx_ctx.showiv = 0;
38e00438
VD		 2836#ifdef I40E_FCOE
2837 rx_ctx.fc_ena = (vsi->type == I40E_VSI_FCOE);
2838#endif
acb3676b
CS		 2839 /* set the prefena field to 1 because the manual says to */
2840 rx_ctx.prefena = 1;
41c445ff
JB		 2841
2842 /* clear the context in the HMC */
2843 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2844 if (err) {
2845 dev_info(&vsi->back->pdev->dev,
2846 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2847 ring->queue_index, pf_q, err);
2848 return -ENOMEM;
2849 }
2850
2851 /* set the context in the HMC */
2852 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2853 if (err) {
2854 dev_info(&vsi->back->pdev->dev,
2855 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
2856 ring->queue_index, pf_q, err);
2857 return -ENOMEM;
2858 }
2859
2860 /* cache tail for quicker writes, and clear the reg before use */
2861 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2862 writel(0, ring->tail);
2863
a132af24
MW		 2864 if (ring_is_ps_enabled(ring)) {
2865 i40e_alloc_rx_headers(ring);
2866 i40e_alloc_rx_buffers_ps(ring, I40E_DESC_UNUSED(ring));
2867 } else {
2868 i40e_alloc_rx_buffers_1buf(ring, I40E_DESC_UNUSED(ring));
2869 }
41c445ff
JB		 2870
2871 return 0;
2872}
2873
2874/**
2875 * i40e_vsi_configure_tx - Configure the VSI for Tx
2876 * @vsi: VSI structure describing this set of rings and resources
2877 *
2878 * Configure the Tx VSI for operation.
2879 **/
2880static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
2881{
2882 int err = 0;
2883 u16 i;
2884
9f65e15b
AD		 2885 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
2886 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
41c445ff
JB		 2887
2888 return err;
2889}
2890
2891/**
2892 * i40e_vsi_configure_rx - Configure the VSI for Rx
2893 * @vsi: the VSI being configured
2894 *
2895 * Configure the Rx VSI for operation.
2896 **/
2897static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
2898{
2899 int err = 0;
2900 u16 i;
2901
2902 if (vsi->netdev && (vsi->netdev->mtu > ETH_DATA_LEN))
2903 vsi->max_frame = vsi->netdev->mtu + ETH_HLEN
2904 + ETH_FCS_LEN + VLAN_HLEN;
2905 else
2906 vsi->max_frame = I40E_RXBUFFER_2048;
2907
2908 /* figure out correct receive buffer length */
2909 switch (vsi->back->flags & (I40E_FLAG_RX_1BUF_ENABLED |
2910 I40E_FLAG_RX_PS_ENABLED)) {
2911 case I40E_FLAG_RX_1BUF_ENABLED:
2912 vsi->rx_hdr_len = 0;
2913 vsi->rx_buf_len = vsi->max_frame;
2914 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2915 break;
2916 case I40E_FLAG_RX_PS_ENABLED:
2917 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2918 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2919 vsi->dtype = I40E_RX_DTYPE_HEADER_SPLIT;
2920 break;
2921 default:
2922 vsi->rx_hdr_len = I40E_RX_HDR_SIZE;
2923 vsi->rx_buf_len = I40E_RXBUFFER_2048;
2924 vsi->dtype = I40E_RX_DTYPE_SPLIT_ALWAYS;
2925 break;
2926 }
2927
38e00438
VD		 2928#ifdef I40E_FCOE
2929 /* setup rx buffer for FCoE */
2930 if ((vsi->type == I40E_VSI_FCOE) &&
2931 (vsi->back->flags & I40E_FLAG_FCOE_ENABLED)) {
2932 vsi->rx_hdr_len = 0;
2933 vsi->rx_buf_len = I40E_RXBUFFER_3072;
2934 vsi->max_frame = I40E_RXBUFFER_3072;
2935 vsi->dtype = I40E_RX_DTYPE_NO_SPLIT;
2936 }
2937
2938#endif /* I40E_FCOE */
41c445ff
JB		 2939 /* round up for the chip's needs */
2940 vsi->rx_hdr_len = ALIGN(vsi->rx_hdr_len,
41a1d04b 2941 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT));
41c445ff 2942 vsi->rx_buf_len = ALIGN(vsi->rx_buf_len,
41a1d04b 2943 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
41c445ff
JB		 2944
2945 /* set up individual rings */
2946 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
9f65e15b 2947 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 2948
2949 return err;
2950}
2951
2952/**
2953 * i40e_vsi_config_dcb_rings - Update rings to reflect DCB TC
2954 * @vsi: ptr to the VSI
2955 **/
2956static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
2957{
e7046ee1 2958 struct i40e_ring *tx_ring, *rx_ring;
41c445ff
JB		 2959 u16 qoffset, qcount;
2960 int i, n;
2961
cd238a3e
PN		 2962 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
2963 /* Reset the TC information */
2964 for (i = 0; i < vsi->num_queue_pairs; i++) {
2965 rx_ring = vsi->rx_rings[i];
2966 tx_ring = vsi->tx_rings[i];
2967 rx_ring->dcb_tc = 0;
2968 tx_ring->dcb_tc = 0;
2969 }
2970 }
41c445ff
JB		 2971
2972 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
41a1d04b 2973 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
41c445ff
JB		 2974 continue;
2975
2976 qoffset = vsi->tc_config.tc_info[n].qoffset;
2977 qcount = vsi->tc_config.tc_info[n].qcount;
2978 for (i = qoffset; i < (qoffset + qcount); i++) {
e7046ee1
AA		 2979 rx_ring = vsi->rx_rings[i];
2980 tx_ring = vsi->tx_rings[i];
41c445ff
JB		 2981 rx_ring->dcb_tc = n;
2982 tx_ring->dcb_tc = n;
2983 }
2984 }
2985}
2986
2987/**
2988 * i40e_set_vsi_rx_mode - Call set_rx_mode on a VSI
2989 * @vsi: ptr to the VSI
2990 **/
2991static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
2992{
2993 if (vsi->netdev)
2994 i40e_set_rx_mode(vsi->netdev);
2995}
2996
17a73f6b
JG		 2997/**
2998 * i40e_fdir_filter_restore - Restore the Sideband Flow Director filters
2999 * @vsi: Pointer to the targeted VSI
3000 *
3001 * This function replays the hlist on the hw where all the SB Flow Director
3002 * filters were saved.
3003 **/
3004static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3005{
3006 struct i40e_fdir_filter *filter;
3007 struct i40e_pf *pf = vsi->back;
3008 struct hlist_node *node;
3009
55a5e60b
ASJ		 3010 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3011 return;
3012
17a73f6b
JG		 3013 hlist_for_each_entry_safe(filter, node,
3014 &pf->fdir_filter_list, fdir_node) {
3015 i40e_add_del_fdir(vsi, filter, true);
3016 }
3017}
3018
41c445ff
JB		 3019/**
3020 * i40e_vsi_configure - Set up the VSI for action
3021 * @vsi: the VSI being configured
3022 **/
3023static int i40e_vsi_configure(struct i40e_vsi *vsi)
3024{
3025 int err;
3026
3027 i40e_set_vsi_rx_mode(vsi);
3028 i40e_restore_vlan(vsi);
3029 i40e_vsi_config_dcb_rings(vsi);
3030 err = i40e_vsi_configure_tx(vsi);
3031 if (!err)
3032 err = i40e_vsi_configure_rx(vsi);
3033
3034 return err;
3035}
3036
3037/**
3038 * i40e_vsi_configure_msix - MSIX mode Interrupt Config in the HW
3039 * @vsi: the VSI being configured
3040 **/
3041static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3042{
3043 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 3044 struct i40e_hw *hw = &pf->hw;
3045 u16 vector;
3046 int i, q;
41c445ff
JB		 3047 u32 qp;
3048
3049 /* The interrupt indexing is offset by 1 in the PFINT_ITRn
3050 * and PFINT_LNKLSTn registers, e.g.:
3051 * PFINT_ITRn[0..n-1] gets msix-1..msix-n (qpair interrupts)
3052 */
3053 qp = vsi->base_queue;
3054 vector = vsi->base_vector;
493fb300 3055 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
ac26fc13
JB		 3056 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3057
ee2319cf 3058 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3059 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3060 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3061 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3062 q_vector->rx.itr);
3063 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3064 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3065 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3066 q_vector->tx.itr);
ac26fc13
JB		 3067 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3068 INTRL_USEC_TO_REG(vsi->int_rate_limit));
41c445ff
JB		 3069
3070 /* Linked list for the queuepairs assigned to this vector */
3071 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3072 for (q = 0; q < q_vector->num_ringpairs; q++) {
ac26fc13
JB		 3073 u32 val;
3074
41c445ff
JB		 3075 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3076 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3077 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3078 (qp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3079 (I40E_QUEUE_TYPE_TX
3080 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3081
3082 wr32(hw, I40E_QINT_RQCTL(qp), val);
3083
3084 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3085 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3086 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3087 ((qp+1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)|
3088 (I40E_QUEUE_TYPE_RX
3089 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3090
3091 /* Terminate the linked list */
3092 if (q == (q_vector->num_ringpairs - 1))
3093 val |= (I40E_QUEUE_END_OF_LIST
3094 << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3095
3096 wr32(hw, I40E_QINT_TQCTL(qp), val);
3097 qp++;
3098 }
3099 }
3100
3101 i40e_flush(hw);
3102}
3103
3104/**
3105 * i40e_enable_misc_int_causes - enable the non-queue interrupts
3106 * @hw: ptr to the hardware info
3107 **/
ab437b5a 3108static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
41c445ff 3109{
ab437b5a 3110 struct i40e_hw *hw = &pf->hw;
41c445ff
JB		 3111 u32 val;
3112
3113 /* clear things first */
3114 wr32(hw, I40E_PFINT_ICR0_ENA, 0); /* disable all */
3115 rd32(hw, I40E_PFINT_ICR0); /* read to clear */
3116
3117 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3118 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3119 I40E_PFINT_ICR0_ENA_GRST_MASK |
3120 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3121 I40E_PFINT_ICR0_ENA_GPIO_MASK |
41c445ff
JB		 3122 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3123 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3124 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3125
0d8e1439
ASJ		 3126 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3127 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3128
ab437b5a
JK		 3129 if (pf->flags & I40E_FLAG_PTP)
3130 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3131
41c445ff
JB		 3132 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3133
3134 /* SW_ITR_IDX = 0, but don't change INTENA */
84ed40e7
ASJ		 3135 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3136 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
41c445ff
JB		 3137
3138 /* OTHER_ITR_IDX = 0 */
3139 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3140}
3141
3142/**
3143 * i40e_configure_msi_and_legacy - Legacy mode interrupt config in the HW
3144 * @vsi: the VSI being configured
3145 **/
3146static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3147{
493fb300 3148 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3149 struct i40e_pf *pf = vsi->back;
3150 struct i40e_hw *hw = &pf->hw;
3151 u32 val;
3152
3153 /* set the ITR configuration */
ee2319cf 3154 q_vector->itr_countdown = ITR_COUNTDOWN_START;
41c445ff
JB		 3155 q_vector->rx.itr = ITR_TO_REG(vsi->rx_itr_setting);
3156 q_vector->rx.latency_range = I40E_LOW_LATENCY;
3157 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.itr);
3158 q_vector->tx.itr = ITR_TO_REG(vsi->tx_itr_setting);
3159 q_vector->tx.latency_range = I40E_LOW_LATENCY;
3160 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.itr);
3161
ab437b5a 3162 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 3163
3164 /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
3165 wr32(hw, I40E_PFINT_LNKLST0, 0);
3166
f29eaa3d 3167 /* Associate the queue pair to the vector and enable the queue int */
41c445ff
JB		 3168 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3169 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3170 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3171
3172 wr32(hw, I40E_QINT_RQCTL(0), val);
3173
3174 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3175 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3176 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3177
3178 wr32(hw, I40E_QINT_TQCTL(0), val);
3179 i40e_flush(hw);
3180}
3181
2ef28cfb
MW		 3182/**
3183 * i40e_irq_dynamic_disable_icr0 - Disable default interrupt generation for icr0
3184 * @pf: board private structure
3185 **/
3186void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3187{
3188 struct i40e_hw *hw = &pf->hw;
3189
3190 wr32(hw, I40E_PFINT_DYN_CTL0,
3191 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3192 i40e_flush(hw);
3193}
3194
41c445ff
JB		 3195/**
3196 * i40e_irq_dynamic_enable_icr0 - Enable default interrupt generation for icr0
3197 * @pf: board private structure
3198 **/
116a57d4 3199void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
41c445ff
JB		 3200{
3201 struct i40e_hw *hw = &pf->hw;
3202 u32 val;
3203
3204 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3205 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3206 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3207
3208 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3209 i40e_flush(hw);
3210}
3211
5c2cebda
CW		 3212/**
3213 * i40e_irq_dynamic_disable - Disable default interrupt generation settings
3214 * @vsi: pointer to a vsi
03147773 3215 * @vector: disable a particular Hw Interrupt vector
5c2cebda
CW		 3216 **/
3217void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector)
3218{
3219 struct i40e_pf *pf = vsi->back;
3220 struct i40e_hw *hw = &pf->hw;
3221 u32 val;
3222
3223 val = I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
3224 wr32(hw, I40E_PFINT_DYN_CTLN(vector - 1), val);
3225 i40e_flush(hw);
3226}
3227
41c445ff
JB		 3228/**
3229 * i40e_msix_clean_rings - MSIX mode Interrupt Handler
3230 * @irq: interrupt number
3231 * @data: pointer to a q_vector
3232 **/
3233static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3234{
3235 struct i40e_q_vector *q_vector = data;
3236
cd0b6fa6 3237 if (!q_vector->tx.ring && !q_vector->rx.ring)
41c445ff
JB		 3238 return IRQ_HANDLED;
3239
5d3465a1 3240 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3241
3242 return IRQ_HANDLED;
3243}
3244
41c445ff
JB		 3245/**
3246 * i40e_vsi_request_irq_msix - Initialize MSI-X interrupts
3247 * @vsi: the VSI being configured
3248 * @basename: name for the vector
3249 *
3250 * Allocates MSI-X vectors and requests interrupts from the kernel.
3251 **/
3252static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3253{
3254 int q_vectors = vsi->num_q_vectors;
3255 struct i40e_pf *pf = vsi->back;
3256 int base = vsi->base_vector;
3257 int rx_int_idx = 0;
3258 int tx_int_idx = 0;
3259 int vector, err;
3260
3261 for (vector = 0; vector < q_vectors; vector++) {
493fb300 3262 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
41c445ff 3263
cd0b6fa6 3264 if (q_vector->tx.ring && q_vector->rx.ring) {
41c445ff
JB		 3265 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3266 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3267 tx_int_idx++;
cd0b6fa6 3268 } else if (q_vector->rx.ring) {
41c445ff
JB		 3269 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3270 "%s-%s-%d", basename, "rx", rx_int_idx++);
cd0b6fa6 3271 } else if (q_vector->tx.ring) {
41c445ff
JB		 3272 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3273 "%s-%s-%d", basename, "tx", tx_int_idx++);
3274 } else {
3275 /* skip this unused q_vector */
3276 continue;
3277 }
3278 err = request_irq(pf->msix_entries[base + vector].vector,
3279 vsi->irq_handler,
3280 0,
3281 q_vector->name,
3282 q_vector);
3283 if (err) {
3284 dev_info(&pf->pdev->dev,
fb43201f 3285 "MSIX request_irq failed, error: %d\n", err);
41c445ff
JB		 3286 goto free_queue_irqs;
3287 }
3288 /* assign the mask for this irq */
3289 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3290 &q_vector->affinity_mask);
3291 }
3292
63741846 3293 vsi->irqs_ready = true;
41c445ff
JB		 3294 return 0;
3295
3296free_queue_irqs:
3297 while (vector) {
3298 vector--;
3299 irq_set_affinity_hint(pf->msix_entries[base + vector].vector,
3300 NULL);
3301 free_irq(pf->msix_entries[base + vector].vector,
3302 &(vsi->q_vectors[vector]));
3303 }
3304 return err;
3305}
3306
3307/**
3308 * i40e_vsi_disable_irq - Mask off queue interrupt generation on the VSI
3309 * @vsi: the VSI being un-configured
3310 **/
3311static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3312{
3313 struct i40e_pf *pf = vsi->back;
3314 struct i40e_hw *hw = &pf->hw;
3315 int base = vsi->base_vector;
3316 int i;
3317
3318 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 3319 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), 0);
3320 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), 0);
41c445ff
JB		 3321 }
3322
3323 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3324 for (i = vsi->base_vector;
3325 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3326 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3327
3328 i40e_flush(hw);
3329 for (i = 0; i < vsi->num_q_vectors; i++)
3330 synchronize_irq(pf->msix_entries[i + base].vector);
3331 } else {
3332 /* Legacy and MSI mode - this stops all interrupt handling */
3333 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3334 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3335 i40e_flush(hw);
3336 synchronize_irq(pf->pdev->irq);
3337 }
3338}
3339
3340/**
3341 * i40e_vsi_enable_irq - Enable IRQ for the given VSI
3342 * @vsi: the VSI being configured
3343 **/
3344static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3345{
3346 struct i40e_pf *pf = vsi->back;
3347 int i;
3348
3349 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
7845548d 3350 for (i = 0; i < vsi->num_q_vectors; i++)
41c445ff
JB		 3351 i40e_irq_dynamic_enable(vsi, i);
3352 } else {
3353 i40e_irq_dynamic_enable_icr0(pf);
3354 }
3355
1022cb6c 3356 i40e_flush(&pf->hw);
41c445ff
JB		 3357 return 0;
3358}
3359
3360/**
3361 * i40e_stop_misc_vector - Stop the vector that handles non-queue events
3362 * @pf: board private structure
3363 **/
3364static void i40e_stop_misc_vector(struct i40e_pf *pf)
3365{
3366 /* Disable ICR 0 */
3367 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3368 i40e_flush(&pf->hw);
3369}
3370
3371/**
3372 * i40e_intr - MSI/Legacy and non-queue interrupt handler
3373 * @irq: interrupt number
3374 * @data: pointer to a q_vector
3375 *
3376 * This is the handler used for all MSI/Legacy interrupts, and deals
3377 * with both queue and non-queue interrupts. This is also used in
3378 * MSIX mode to handle the non-queue interrupts.
3379 **/
3380static irqreturn_t i40e_intr(int irq, void *data)
3381{
3382 struct i40e_pf *pf = (struct i40e_pf *)data;
3383 struct i40e_hw *hw = &pf->hw;
5e823066 3384 irqreturn_t ret = IRQ_NONE;
41c445ff
JB		 3385 u32 icr0, icr0_remaining;
3386 u32 val, ena_mask;
3387
3388 icr0 = rd32(hw, I40E_PFINT_ICR0);
5e823066 3389 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
41c445ff 3390
116a57d4
SN		 3391 /* if sharing a legacy IRQ, we might get called w/o an intr pending */
3392 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
5e823066 3393 goto enable_intr;
41c445ff 3394
cd92e72f
SN		 3395 /* if interrupt but no bits showing, must be SWINT */
3396 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3397 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3398 pf->sw_int_count++;
3399
0d8e1439
ASJ		 3400 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3401 (ena_mask & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3402 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3403 icr0 &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3404 dev_info(&pf->pdev->dev, "cleared PE_CRITERR\n");
3405 }
3406
41c445ff
JB		 3407 /* only q0 is used in MSI/Legacy mode, and none are used in MSIX */
3408 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
5d3465a1
AD		 3409 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3410 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
41c445ff
JB		 3411
3412 /* temporarily disable queue cause for NAPI processing */
3413 u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
6995b36c 3414
41c445ff
JB		 3415 qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3416 wr32(hw, I40E_QINT_RQCTL(0), qval);
3417
3418 qval = rd32(hw, I40E_QINT_TQCTL(0));
3419 qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3420 wr32(hw, I40E_QINT_TQCTL(0), qval);
41c445ff
JB		 3421
3422 if (!test_bit(__I40E_DOWN, &pf->state))
5d3465a1 3423 napi_schedule_irqoff(&q_vector->napi);
41c445ff
JB		 3424 }
3425
3426 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3427 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3428 set_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
3429 }
3430
3431 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3432 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3433 set_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
3434 }
3435
3436 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3437 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3438 set_bit(__I40E_VFLR_EVENT_PENDING, &pf->state);
3439 }
3440
3441 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3442 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
3443 set_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
3444 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3445 val = rd32(hw, I40E_GLGEN_RSTAT);
3446 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3447 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
4eb3f768 3448 if (val == I40E_RESET_CORER) {
41c445ff 3449 pf->corer_count++;
4eb3f768 3450 } else if (val == I40E_RESET_GLOBR) {
41c445ff 3451 pf->globr_count++;
4eb3f768 3452 } else if (val == I40E_RESET_EMPR) {
41c445ff 3453 pf->empr_count++;
9df42d1a 3454 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state);
4eb3f768 3455 }
41c445ff
JB		 3456 }
3457
9c010ee0
ASJ		 3458 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3459 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3460 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
25fc0e65
ASJ		 3461 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3462 rd32(hw, I40E_PFHMC_ERRORINFO),
3463 rd32(hw, I40E_PFHMC_ERRORDATA));
9c010ee0
ASJ		 3464 }
3465
beb0dff1
JK		 3466 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3467 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3468
3469 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
cafa1fca 3470 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
beb0dff1 3471 i40e_ptp_tx_hwtstamp(pf);
beb0dff1 3472 }
beb0dff1
JK		 3473 }
3474
41c445ff
JB		 3475 /* If a critical error is pending we have no choice but to reset the
3476 * device.
3477 * Report and mask out any remaining unexpected interrupts.
3478 */
3479 icr0_remaining = icr0 & ena_mask;
3480 if (icr0_remaining) {
3481 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3482 icr0_remaining);
9c010ee0 3483 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
41c445ff 3484 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
c0c28975 3485 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
9c010ee0
ASJ		 3486 dev_info(&pf->pdev->dev, "device will be reset\n");
3487 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
3488 i40e_service_event_schedule(pf);
41c445ff
JB		 3489 }
3490 ena_mask &= ~icr0_remaining;
3491 }
5e823066 3492 ret = IRQ_HANDLED;
41c445ff 3493
5e823066 3494enable_intr:
41c445ff
JB		 3495 /* re-enable interrupt causes */
3496 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
41c445ff
JB		 3497 if (!test_bit(__I40E_DOWN, &pf->state)) {
3498 i40e_service_event_schedule(pf);
3499 i40e_irq_dynamic_enable_icr0(pf);
3500 }
3501
5e823066 3502 return ret;
41c445ff
JB		 3503}
3504
cbf61325
ASJ		 3505/**
3506 * i40e_clean_fdir_tx_irq - Reclaim resources after transmit completes
3507 * @tx_ring: tx ring to clean
3508 * @budget: how many cleans we're allowed
3509 *
3510 * Returns true if there's any budget left (e.g. the clean is finished)
3511 **/
3512static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3513{
3514 struct i40e_vsi *vsi = tx_ring->vsi;
3515 u16 i = tx_ring->next_to_clean;
3516 struct i40e_tx_buffer *tx_buf;
3517 struct i40e_tx_desc *tx_desc;
3518
3519 tx_buf = &tx_ring->tx_bi[i];
3520 tx_desc = I40E_TX_DESC(tx_ring, i);
3521 i -= tx_ring->count;
3522
3523 do {
3524 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3525
3526 /* if next_to_watch is not set then there is no work pending */
3527 if (!eop_desc)
3528 break;
3529
3530 /* prevent any other reads prior to eop_desc */
3531 read_barrier_depends();
3532
3533 /* if the descriptor isn't done, no work yet to do */
3534 if (!(eop_desc->cmd_type_offset_bsz &
3535 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3536 break;
3537
3538 /* clear next_to_watch to prevent false hangs */
3539 tx_buf->next_to_watch = NULL;
3540
49d7d933
ASJ		 3541 tx_desc->buffer_addr = 0;
3542 tx_desc->cmd_type_offset_bsz = 0;
3543 /* move past filter desc */
3544 tx_buf++;
3545 tx_desc++;
3546 i++;
3547 if (unlikely(!i)) {
3548 i -= tx_ring->count;
3549 tx_buf = tx_ring->tx_bi;
3550 tx_desc = I40E_TX_DESC(tx_ring, 0);
3551 }
cbf61325
ASJ		 3552 /* unmap skb header data */
3553 dma_unmap_single(tx_ring->dev,
3554 dma_unmap_addr(tx_buf, dma),
3555 dma_unmap_len(tx_buf, len),
3556 DMA_TO_DEVICE);
49d7d933
ASJ		 3557 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3558 kfree(tx_buf->raw_buf);
cbf61325 3559
49d7d933
ASJ		 3560 tx_buf->raw_buf = NULL;
3561 tx_buf->tx_flags = 0;
3562 tx_buf->next_to_watch = NULL;
cbf61325 3563 dma_unmap_len_set(tx_buf, len, 0);
49d7d933
ASJ		 3564 tx_desc->buffer_addr = 0;
3565 tx_desc->cmd_type_offset_bsz = 0;
cbf61325 3566
49d7d933 3567 /* move us past the eop_desc for start of next FD desc */
cbf61325
ASJ		 3568 tx_buf++;
3569 tx_desc++;
3570 i++;
3571 if (unlikely(!i)) {
3572 i -= tx_ring->count;
3573 tx_buf = tx_ring->tx_bi;
3574 tx_desc = I40E_TX_DESC(tx_ring, 0);
3575 }
3576
3577 /* update budget accounting */
3578 budget--;
3579 } while (likely(budget));
3580
3581 i += tx_ring->count;
3582 tx_ring->next_to_clean = i;
3583
6995b36c 3584 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
7845548d 3585 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
6995b36c 3586
cbf61325
ASJ		 3587 return budget > 0;
3588}
3589
3590/**
3591 * i40e_fdir_clean_ring - Interrupt Handler for FDIR SB ring
3592 * @irq: interrupt number
3593 * @data: pointer to a q_vector
3594 **/
3595static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
3596{
3597 struct i40e_q_vector *q_vector = data;
3598 struct i40e_vsi *vsi;
3599
3600 if (!q_vector->tx.ring)
3601 return IRQ_HANDLED;
3602
3603 vsi = q_vector->tx.ring->vsi;
3604 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
3605
3606 return IRQ_HANDLED;
3607}
3608
41c445ff 3609/**
cd0b6fa6 3610 * i40e_map_vector_to_qp - Assigns the queue pair to the vector
41c445ff
JB		 3611 * @vsi: the VSI being configured
3612 * @v_idx: vector index
cd0b6fa6 3613 * @qp_idx: queue pair index
41c445ff 3614 **/
26cdc443 3615static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
41c445ff 3616{
493fb300 3617 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
9f65e15b
AD		 3618 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
3619 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
41c445ff
JB		 3620
3621 tx_ring->q_vector = q_vector;
cd0b6fa6
AD		 3622 tx_ring->next = q_vector->tx.ring;
3623 q_vector->tx.ring = tx_ring;
41c445ff 3624 q_vector->tx.count++;
cd0b6fa6
AD		 3625
3626 rx_ring->q_vector = q_vector;
3627 rx_ring->next = q_vector->rx.ring;
3628 q_vector->rx.ring = rx_ring;
3629 q_vector->rx.count++;
41c445ff
JB		 3630}
3631
3632/**
3633 * i40e_vsi_map_rings_to_vectors - Maps descriptor rings to vectors
3634 * @vsi: the VSI being configured
3635 *
3636 * This function maps descriptor rings to the queue-specific vectors
3637 * we were allotted through the MSI-X enabling code. Ideally, we'd have
3638 * one vector per queue pair, but on a constrained vector budget, we
3639 * group the queue pairs as "efficiently" as possible.
3640 **/
3641static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
3642{
3643 int qp_remaining = vsi->num_queue_pairs;
3644 int q_vectors = vsi->num_q_vectors;
cd0b6fa6 3645 int num_ringpairs;
41c445ff
JB		 3646 int v_start = 0;
3647 int qp_idx = 0;
3648
3649 /* If we don't have enough vectors for a 1-to-1 mapping, we'll have to
3650 * group them so there are multiple queues per vector.
70114ec4
ASJ		 3651 * It is also important to go through all the vectors available to be
3652 * sure that if we don't use all the vectors, that the remaining vectors
3653 * are cleared. This is especially important when decreasing the
3654 * number of queues in use.
41c445ff 3655 */
70114ec4 3656 for (; v_start < q_vectors; v_start++) {
cd0b6fa6
AD		 3657 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
3658
3659 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
3660
3661 q_vector->num_ringpairs = num_ringpairs;
3662
3663 q_vector->rx.count = 0;
3664 q_vector->tx.count = 0;
3665 q_vector->rx.ring = NULL;
3666 q_vector->tx.ring = NULL;
3667
3668 while (num_ringpairs--) {
26cdc443 3669 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
cd0b6fa6
AD		 3670 qp_idx++;
3671 qp_remaining--;
41c445ff
JB		 3672 }
3673 }
3674}
3675
3676/**
3677 * i40e_vsi_request_irq - Request IRQ from the OS
3678 * @vsi: the VSI being configured
3679 * @basename: name for the vector
3680 **/
3681static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
3682{
3683 struct i40e_pf *pf = vsi->back;
3684 int err;
3685
3686 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
3687 err = i40e_vsi_request_irq_msix(vsi, basename);
3688 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
3689 err = request_irq(pf->pdev->irq, i40e_intr, 0,
b294ac70 3690 pf->int_name, pf);
41c445ff
JB		 3691 else
3692 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
b294ac70 3693 pf->int_name, pf);
41c445ff
JB		 3694
3695 if (err)
3696 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
3697
3698 return err;
3699}
3700
3701#ifdef CONFIG_NET_POLL_CONTROLLER
3702/**
3703 * i40e_netpoll - A Polling 'interrupt'handler
3704 * @netdev: network interface device structure
3705 *
3706 * This is used by netconsole to send skbs without having to re-enable
3707 * interrupts. It's not called while the normal interrupt routine is executing.
3708 **/
38e00438
VD		 3709#ifdef I40E_FCOE
3710void i40e_netpoll(struct net_device *netdev)
3711#else
41c445ff 3712static void i40e_netpoll(struct net_device *netdev)
38e00438 3713#endif
41c445ff
JB		 3714{
3715 struct i40e_netdev_priv *np = netdev_priv(netdev);
3716 struct i40e_vsi *vsi = np->vsi;
3717 struct i40e_pf *pf = vsi->back;
3718 int i;
3719
3720 /* if interface is down do nothing */
3721 if (test_bit(__I40E_DOWN, &vsi->state))
3722 return;
3723
41c445ff
JB		 3724 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3725 for (i = 0; i < vsi->num_q_vectors; i++)
493fb300 3726 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
41c445ff
JB		 3727 } else {
3728 i40e_intr(pf->pdev->irq, netdev);
3729 }
41c445ff
JB		 3730}
3731#endif
3732
23527308
NP		 3733/**
3734 * i40e_pf_txq_wait - Wait for a PF's Tx queue to be enabled or disabled
3735 * @pf: the PF being configured
3736 * @pf_q: the PF queue
3737 * @enable: enable or disable state of the queue
3738 *
3739 * This routine will wait for the given Tx queue of the PF to reach the
3740 * enabled or disabled state.
3741 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3742 * multiple retries; else will return 0 in case of success.
3743 **/
3744static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3745{
3746 int i;
3747 u32 tx_reg;
3748
3749 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3750 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
3751 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
3752 break;
3753
f98a2006 3754 usleep_range(10, 20);
23527308
NP		 3755 }
3756 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3757 return -ETIMEDOUT;
3758
3759 return 0;
3760}
3761
41c445ff
JB		 3762/**
3763 * i40e_vsi_control_tx - Start or stop a VSI's rings
3764 * @vsi: the VSI being configured
3765 * @enable: start or stop the rings
3766 **/
3767static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
3768{
3769 struct i40e_pf *pf = vsi->back;
3770 struct i40e_hw *hw = &pf->hw;
23527308 3771 int i, j, pf_q, ret = 0;
41c445ff
JB		 3772 u32 tx_reg;
3773
3774 pf_q = vsi->base_queue;
3775 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
351499ab
MJ		 3776
3777 /* warn the TX unit of coming changes */
3778 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
3779 if (!enable)
f98a2006 3780 usleep_range(10, 20);
351499ab 3781
6c5ef620 3782 for (j = 0; j < 50; j++) {
41c445ff 3783 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
6c5ef620
MW		 3784 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
3785 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
3786 break;
3787 usleep_range(1000, 2000);
3788 }
fda972f6 3789 /* Skip if the queue is already in the requested state */
7c122007 3790 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
fda972f6 3791 continue;
41c445ff
JB		 3792
3793 /* turn on/off the queue */
c5c9eb9e
SN		 3794 if (enable) {
3795 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
6c5ef620 3796 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3797 } else {
41c445ff 3798 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
c5c9eb9e 3799 }
41c445ff
JB		 3800
3801 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
69129dc3
NP		 3802 /* No waiting for the Tx queue to disable */
3803 if (!enable && test_bit(__I40E_PORT_TX_SUSPENDED, &pf->state))
3804 continue;
41c445ff
JB		 3805
3806 /* wait for the change to finish */
23527308
NP		 3807 ret = i40e_pf_txq_wait(pf, pf_q, enable);
3808 if (ret) {
3809 dev_info(&pf->pdev->dev,
fb43201f
SN		 3810 "VSI seid %d Tx ring %d %sable timeout\n",
3811 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3812 break;
41c445ff
JB		 3813 }
3814 }
3815
7134f9ce
JB		 3816 if (hw->revision_id == 0)
3817 mdelay(50);
23527308
NP		 3818 return ret;
3819}
3820
3821/**
3822 * i40e_pf_rxq_wait - Wait for a PF's Rx queue to be enabled or disabled
3823 * @pf: the PF being configured
3824 * @pf_q: the PF queue
3825 * @enable: enable or disable state of the queue
3826 *
3827 * This routine will wait for the given Rx queue of the PF to reach the
3828 * enabled or disabled state.
3829 * Returns -ETIMEDOUT in case of failing to reach the requested state after
3830 * multiple retries; else will return 0 in case of success.
3831 **/
3832static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
3833{
3834 int i;
3835 u32 rx_reg;
3836
3837 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
3838 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
3839 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3840 break;
3841
f98a2006 3842 usleep_range(10, 20);
23527308
NP		 3843 }
3844 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
3845 return -ETIMEDOUT;
7134f9ce 3846
41c445ff
JB		 3847 return 0;
3848}
3849
3850/**
3851 * i40e_vsi_control_rx - Start or stop a VSI's rings
3852 * @vsi: the VSI being configured
3853 * @enable: start or stop the rings
3854 **/
3855static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
3856{
3857 struct i40e_pf *pf = vsi->back;
3858 struct i40e_hw *hw = &pf->hw;
23527308 3859 int i, j, pf_q, ret = 0;
41c445ff
JB		 3860 u32 rx_reg;
3861
3862 pf_q = vsi->base_queue;
3863 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
6c5ef620 3864 for (j = 0; j < 50; j++) {
41c445ff 3865 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
6c5ef620
MW		 3866 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
3867 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
3868 break;
3869 usleep_range(1000, 2000);
3870 }
41c445ff 3871
7c122007
CS		 3872 /* Skip if the queue is already in the requested state */
3873 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
3874 continue;
41c445ff
JB		 3875
3876 /* turn on/off the queue */
3877 if (enable)
6c5ef620 3878 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff 3879 else
6c5ef620 3880 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
41c445ff
JB		 3881 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
3882
3883 /* wait for the change to finish */
23527308
NP		 3884 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
3885 if (ret) {
3886 dev_info(&pf->pdev->dev,
fb43201f
SN		 3887 "VSI seid %d Rx ring %d %sable timeout\n",
3888 vsi->seid, pf_q, (enable ? "en" : "dis"));
23527308 3889 break;
41c445ff
JB		 3890 }
3891 }
3892
23527308 3893 return ret;
41c445ff
JB		 3894}
3895
3896/**
3897 * i40e_vsi_control_rings - Start or stop a VSI's rings
3898 * @vsi: the VSI being configured
3899 * @enable: start or stop the rings
3900 **/
fc18eaa0 3901int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool request)
41c445ff 3902{
3b867b28 3903 int ret = 0;
41c445ff
JB		 3904
3905 /* do rx first for enable and last for disable */
3906 if (request) {
3907 ret = i40e_vsi_control_rx(vsi, request);
3908 if (ret)
3909 return ret;
3910 ret = i40e_vsi_control_tx(vsi, request);
3911 } else {
3b867b28
ASJ		 3912 /* Ignore return value, we need to shutdown whatever we can */
3913 i40e_vsi_control_tx(vsi, request);
3914 i40e_vsi_control_rx(vsi, request);
41c445ff
JB		 3915 }
3916
3917 return ret;
3918}
3919
3920/**
3921 * i40e_vsi_free_irq - Free the irq association with the OS
3922 * @vsi: the VSI being configured
3923 **/
3924static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
3925{
3926 struct i40e_pf *pf = vsi->back;
3927 struct i40e_hw *hw = &pf->hw;
3928 int base = vsi->base_vector;
3929 u32 val, qp;
3930 int i;
3931
3932 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3933 if (!vsi->q_vectors)
3934 return;
3935
63741846
SN		 3936 if (!vsi->irqs_ready)
3937 return;
3938
3939 vsi->irqs_ready = false;
41c445ff
JB		 3940 for (i = 0; i < vsi->num_q_vectors; i++) {
3941 u16 vector = i + base;
3942
3943 /* free only the irqs that were actually requested */
78681b1f
SN		 3944 if (!vsi->q_vectors[i] ||
3945 !vsi->q_vectors[i]->num_ringpairs)
41c445ff
JB		 3946 continue;
3947
3948 /* clear the affinity_mask in the IRQ descriptor */
3949 irq_set_affinity_hint(pf->msix_entries[vector].vector,
3950 NULL);
3951 free_irq(pf->msix_entries[vector].vector,
493fb300 3952 vsi->q_vectors[i]);
41c445ff
JB		 3953
3954 /* Tear down the interrupt queue link list
3955 *
3956 * We know that they come in pairs and always
3957 * the Rx first, then the Tx. To clear the
3958 * link list, stick the EOL value into the
3959 * next_q field of the registers.
3960 */
3961 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
3962 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
3963 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3964 val |= I40E_QUEUE_END_OF_LIST
3965 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
3966 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
3967
3968 while (qp != I40E_QUEUE_END_OF_LIST) {
3969 u32 next;
3970
3971 val = rd32(hw, I40E_QINT_RQCTL(qp));
3972
3973 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
3974 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
3975 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3976 I40E_QINT_RQCTL_INTEVENT_MASK);
3977
3978 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
3979 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
3980
3981 wr32(hw, I40E_QINT_RQCTL(qp), val);
3982
3983 val = rd32(hw, I40E_QINT_TQCTL(qp));
3984
3985 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
3986 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
3987
3988 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
3989 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
3990 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3991 I40E_QINT_TQCTL_INTEVENT_MASK);
3992
3993 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
3994 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
3995
3996 wr32(hw, I40E_QINT_TQCTL(qp), val);
3997 qp = next;
3998 }
3999 }
4000 } else {
4001 free_irq(pf->pdev->irq, pf);
4002
4003 val = rd32(hw, I40E_PFINT_LNKLST0);
4004 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4005 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4006 val |= I40E_QUEUE_END_OF_LIST
4007 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4008 wr32(hw, I40E_PFINT_LNKLST0, val);
4009
4010 val = rd32(hw, I40E_QINT_RQCTL(qp));
4011 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4012 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4013 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4014 I40E_QINT_RQCTL_INTEVENT_MASK);
4015
4016 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4017 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4018
4019 wr32(hw, I40E_QINT_RQCTL(qp), val);
4020
4021 val = rd32(hw, I40E_QINT_TQCTL(qp));
4022
4023 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4024 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4025 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4026 I40E_QINT_TQCTL_INTEVENT_MASK);
4027
4028 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4029 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4030
4031 wr32(hw, I40E_QINT_TQCTL(qp), val);
4032 }
4033}
4034
493fb300
AD		 4035/**
4036 * i40e_free_q_vector - Free memory allocated for specific interrupt vector
4037 * @vsi: the VSI being configured
4038 * @v_idx: Index of vector to be freed
4039 *
4040 * This function frees the memory allocated to the q_vector. In addition if
4041 * NAPI is enabled it will delete any references to the NAPI struct prior
4042 * to freeing the q_vector.
4043 **/
4044static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4045{
4046 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
cd0b6fa6 4047 struct i40e_ring *ring;
493fb300
AD		 4048
4049 if (!q_vector)
4050 return;
4051
4052 /* disassociate q_vector from rings */
cd0b6fa6
AD		 4053 i40e_for_each_ring(ring, q_vector->tx)
4054 ring->q_vector = NULL;
4055
4056 i40e_for_each_ring(ring, q_vector->rx)
4057 ring->q_vector = NULL;
493fb300
AD		 4058
4059 /* only VSI w/ an associated netdev is set up w/ NAPI */
4060 if (vsi->netdev)
4061 netif_napi_del(&q_vector->napi);
4062
4063 vsi->q_vectors[v_idx] = NULL;
4064
4065 kfree_rcu(q_vector, rcu);
4066}
4067
41c445ff
JB		 4068/**
4069 * i40e_vsi_free_q_vectors - Free memory allocated for interrupt vectors
4070 * @vsi: the VSI being un-configured
4071 *
4072 * This frees the memory allocated to the q_vectors and
4073 * deletes references to the NAPI struct.
4074 **/
4075static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4076{
4077 int v_idx;
4078
493fb300
AD		 4079 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4080 i40e_free_q_vector(vsi, v_idx);
41c445ff
JB		 4081}
4082
4083/**
4084 * i40e_reset_interrupt_capability - Disable interrupt setup in OS
4085 * @pf: board private structure
4086 **/
4087static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4088{
4089 /* If we're in Legacy mode, the interrupt was cleaned in vsi_close */
4090 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4091 pci_disable_msix(pf->pdev);
4092 kfree(pf->msix_entries);
4093 pf->msix_entries = NULL;
3b444399
SN		 4094 kfree(pf->irq_pile);
4095 pf->irq_pile = NULL;
41c445ff
JB		 4096 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4097 pci_disable_msi(pf->pdev);
4098 }
4099 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4100}
4101
4102/**
4103 * i40e_clear_interrupt_scheme - Clear the current interrupt scheme settings
4104 * @pf: board private structure
4105 *
4106 * We go through and clear interrupt specific resources and reset the structure
4107 * to pre-load conditions
4108 **/
4109static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4110{
4111 int i;
4112
e147758d
SN		 4113 i40e_stop_misc_vector(pf);
4114 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4115 synchronize_irq(pf->msix_entries[0].vector);
4116 free_irq(pf->msix_entries[0].vector, pf);
4117 }
4118
41c445ff 4119 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
505682cd 4120 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 4121 if (pf->vsi[i])
4122 i40e_vsi_free_q_vectors(pf->vsi[i]);
4123 i40e_reset_interrupt_capability(pf);
4124}
4125
4126/**
4127 * i40e_napi_enable_all - Enable NAPI for all q_vectors in the VSI
4128 * @vsi: the VSI being configured
4129 **/
4130static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4131{
4132 int q_idx;
4133
4134 if (!vsi->netdev)
4135 return;
4136
4137 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4138 napi_enable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4139}
4140
4141/**
4142 * i40e_napi_disable_all - Disable NAPI for all q_vectors in the VSI
4143 * @vsi: the VSI being configured
4144 **/
4145static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4146{
4147 int q_idx;
4148
4149 if (!vsi->netdev)
4150 return;
4151
4152 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++)
493fb300 4153 napi_disable(&vsi->q_vectors[q_idx]->napi);
41c445ff
JB		 4154}
4155
90ef8d47
SN		 4156/**
4157 * i40e_vsi_close - Shut down a VSI
4158 * @vsi: the vsi to be quelled
4159 **/
4160static void i40e_vsi_close(struct i40e_vsi *vsi)
4161{
4162 if (!test_and_set_bit(__I40E_DOWN, &vsi->state))
4163 i40e_down(vsi);
4164 i40e_vsi_free_irq(vsi);
4165 i40e_vsi_free_tx_resources(vsi);
4166 i40e_vsi_free_rx_resources(vsi);
92faef85 4167 vsi->current_netdev_flags = 0;
90ef8d47
SN		 4168}
4169
41c445ff
JB		 4170/**
4171 * i40e_quiesce_vsi - Pause a given VSI
4172 * @vsi: the VSI being paused
4173 **/
4174static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4175{
4176 if (test_bit(__I40E_DOWN, &vsi->state))
4177 return;
4178
d341b7a5
NP		 4179 /* No need to disable FCoE VSI when Tx suspended */
4180 if ((test_bit(__I40E_PORT_TX_SUSPENDED, &vsi->back->state)) &&
4181 vsi->type == I40E_VSI_FCOE) {
4182 dev_dbg(&vsi->back->pdev->dev,
fb43201f 4183 "VSI seid %d skipping FCoE VSI disable\n", vsi->seid);
d341b7a5
NP		 4184 return;
4185 }
4186
41c445ff 4187 set_bit(__I40E_NEEDS_RESTART, &vsi->state);
6995b36c 4188 if (vsi->netdev && netif_running(vsi->netdev))
41c445ff 4189 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
6995b36c 4190 else
90ef8d47 4191 i40e_vsi_close(vsi);
41c445ff
JB		 4192}
4193
4194/**
4195 * i40e_unquiesce_vsi - Resume a given VSI
4196 * @vsi: the VSI being resumed
4197 **/
4198static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4199{
4200 if (!test_bit(__I40E_NEEDS_RESTART, &vsi->state))
4201 return;
4202
4203 clear_bit(__I40E_NEEDS_RESTART, &vsi->state);
4204 if (vsi->netdev && netif_running(vsi->netdev))
4205 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4206 else
8276f757 4207 i40e_vsi_open(vsi); /* this clears the DOWN bit */
41c445ff
JB		 4208}
4209
4210/**
4211 * i40e_pf_quiesce_all_vsi - Pause all VSIs on a PF
4212 * @pf: the PF
4213 **/
4214static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4215{
4216 int v;
4217
505682cd 4218 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4219 if (pf->vsi[v])
4220 i40e_quiesce_vsi(pf->vsi[v]);
4221 }
4222}
4223
4224/**
4225 * i40e_pf_unquiesce_all_vsi - Resume all VSIs on a PF
4226 * @pf: the PF
4227 **/
4228static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4229{
4230 int v;
4231
505682cd 4232 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 4233 if (pf->vsi[v])
4234 i40e_unquiesce_vsi(pf->vsi[v]);
4235 }
4236}
4237
69129dc3
NP		 4238#ifdef CONFIG_I40E_DCB
4239/**
4240 * i40e_vsi_wait_txq_disabled - Wait for VSI's queues to be disabled
4241 * @vsi: the VSI being configured
4242 *
4243 * This function waits for the given VSI's Tx queues to be disabled.
4244 **/
4245static int i40e_vsi_wait_txq_disabled(struct i40e_vsi *vsi)
4246{
4247 struct i40e_pf *pf = vsi->back;
4248 int i, pf_q, ret;
4249
4250 pf_q = vsi->base_queue;
4251 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4252 /* Check and wait for the disable status of the queue */
4253 ret = i40e_pf_txq_wait(pf, pf_q, false);
4254 if (ret) {
4255 dev_info(&pf->pdev->dev,
fb43201f
SN		 4256 "VSI seid %d Tx ring %d disable timeout\n",
4257 vsi->seid, pf_q);
69129dc3
NP		 4258 return ret;
4259 }
4260 }
4261
4262 return 0;
4263}
4264
4265/**
4266 * i40e_pf_wait_txq_disabled - Wait for all queues of PF VSIs to be disabled
4267 * @pf: the PF
4268 *
4269 * This function waits for the Tx queues to be in disabled state for all the
4270 * VSIs that are managed by this PF.
4271 **/
4272static int i40e_pf_wait_txq_disabled(struct i40e_pf *pf)
4273{
4274 int v, ret = 0;
4275
4276 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
d341b7a5
NP		 4277 /* No need to wait for FCoE VSI queues */
4278 if (pf->vsi[v] && pf->vsi[v]->type != I40E_VSI_FCOE) {
69129dc3
NP		 4279 ret = i40e_vsi_wait_txq_disabled(pf->vsi[v]);
4280 if (ret)
4281 break;
4282 }
4283 }
4284
4285 return ret;
4286}
4287
4288#endif
b03a8c1f
KP		 4289
4290/**
4291 * i40e_detect_recover_hung_queue - Function to detect and recover hung_queue
4292 * @q_idx: TX queue number
4293 * @vsi: Pointer to VSI struct
4294 *
4295 * This function checks specified queue for given VSI. Detects hung condition.
4296 * Sets hung bit since it is two step process. Before next run of service task
4297 * if napi_poll runs, it reset 'hung' bit for respective q_vector. If not,
4298 * hung condition remain unchanged and during subsequent run, this function
4299 * issues SW interrupt to recover from hung condition.
4300 **/
4301static void i40e_detect_recover_hung_queue(int q_idx, struct i40e_vsi *vsi)
4302{
4303 struct i40e_ring *tx_ring = NULL;
4304 struct i40e_pf *pf;
4305 u32 head, val, tx_pending;
4306 int i;
4307
4308 pf = vsi->back;
4309
4310 /* now that we have an index, find the tx_ring struct */
4311 for (i = 0; i < vsi->num_queue_pairs; i++) {
4312 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
4313 if (q_idx == vsi->tx_rings[i]->queue_index) {
4314 tx_ring = vsi->tx_rings[i];
4315 break;
4316 }
4317 }
4318 }
4319
4320 if (!tx_ring)
4321 return;
4322
4323 /* Read interrupt register */
4324 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4325 val = rd32(&pf->hw,
4326 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
4327 tx_ring->vsi->base_vector - 1));
4328 else
4329 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
4330
9c6c1259
KP		 4331 /* Bail out if interrupts are disabled because napi_poll
4332 * execution in-progress or will get scheduled soon.
4333 * napi_poll cleans TX and RX queues and updates 'next_to_clean'.
4334 */
4335 if (!(val & I40E_PFINT_DYN_CTLN_INTENA_MASK))
4336 return;
4337
b03a8c1f
KP		 4338 head = i40e_get_head(tx_ring);
4339
4340 tx_pending = i40e_get_tx_pending(tx_ring);
4341
9c6c1259
KP		 4342 /* HW is done executing descriptors, updated HEAD write back,
4343 * but SW hasn't processed those descriptors. If interrupt is
4344 * not generated from this point ON, it could result into
4345 * dev_watchdog detecting timeout on those netdev_queue,
4346 * hence proactively trigger SW interrupt.
b03a8c1f 4347 */
9c6c1259
KP		 4348 if (tx_pending) {
4349 /* NAPI Poll didn't run and clear since it was set */
4350 if (test_and_clear_bit(I40E_Q_VECTOR_HUNG_DETECT,
4351 &tx_ring->q_vector->hung_detected)) {
4352 netdev_info(vsi->netdev, "VSI_seid %d, Hung TX queue %d, tx_pending: %d, NTC:0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x\n",
4353 vsi->seid, q_idx, tx_pending,
4354 tx_ring->next_to_clean, head,
4355 tx_ring->next_to_use,
4356 readl(tx_ring->tail));
4357 netdev_info(vsi->netdev, "VSI_seid %d, Issuing force_wb for TX queue %d, Interrupt Reg: 0x%x\n",
4358 vsi->seid, q_idx, val);
4359 i40e_force_wb(vsi, tx_ring->q_vector);
4360 } else {
4361 /* First Chance - detected possible hung */
4362 set_bit(I40E_Q_VECTOR_HUNG_DETECT,
4363 &tx_ring->q_vector->hung_detected);
4364 }
4365 }
b03a8c1f
KP		 4366}
4367
4368/**
4369 * i40e_detect_recover_hung - Function to detect and recover hung_queues
4370 * @pf: pointer to PF struct
4371 *
4372 * LAN VSI has netdev and netdev has TX queues. This function is to check
4373 * each of those TX queues if they are hung, trigger recovery by issuing
4374 * SW interrupt.
4375 **/
4376static void i40e_detect_recover_hung(struct i40e_pf *pf)
4377{
4378 struct net_device *netdev;
4379 struct i40e_vsi *vsi;
4380 int i;
4381
4382 /* Only for LAN VSI */
4383 vsi = pf->vsi[pf->lan_vsi];
4384
4385 if (!vsi)
4386 return;
4387
4388 /* Make sure, VSI state is not DOWN/RECOVERY_PENDING */
4389 if (test_bit(__I40E_DOWN, &vsi->back->state) ||
4390 test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
4391 return;
4392
4393 /* Make sure type is MAIN VSI */
4394 if (vsi->type != I40E_VSI_MAIN)
4395 return;
4396
4397 netdev = vsi->netdev;
4398 if (!netdev)
4399 return;
4400
4401 /* Bail out if netif_carrier is not OK */
4402 if (!netif_carrier_ok(netdev))
4403 return;
4404
4405 /* Go thru' TX queues for netdev */
4406 for (i = 0; i < netdev->num_tx_queues; i++) {
4407 struct netdev_queue *q;
4408
4409 q = netdev_get_tx_queue(netdev, i);
4410 if (q)
4411 i40e_detect_recover_hung_queue(i, vsi);
4412 }
4413}
4414
63d7e5a4
NP		 4415/**
4416 * i40e_get_iscsi_tc_map - Return TC map for iSCSI APP
b40c82e6 4417 * @pf: pointer to PF
63d7e5a4
NP		 4418 *
4419 * Get TC map for ISCSI PF type that will include iSCSI TC
4420 * and LAN TC.
4421 **/
4422static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4423{
4424 struct i40e_dcb_app_priority_table app;
4425 struct i40e_hw *hw = &pf->hw;
4426 u8 enabled_tc = 1; /* TC0 is always enabled */
4427 u8 tc, i;
4428 /* Get the iSCSI APP TLV */
4429 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4430
4431 for (i = 0; i < dcbcfg->numapps; i++) {
4432 app = dcbcfg->app[i];
4433 if (app.selector == I40E_APP_SEL_TCPIP &&
4434 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4435 tc = dcbcfg->etscfg.prioritytable[app.priority];
41a1d04b 4436 enabled_tc |= BIT_ULL(tc);
63d7e5a4
NP		 4437 break;
4438 }
4439 }
4440
4441 return enabled_tc;
4442}
4443
41c445ff
JB		 4444/**
4445 * i40e_dcb_get_num_tc - Get the number of TCs from DCBx config
4446 * @dcbcfg: the corresponding DCBx configuration structure
4447 *
4448 * Return the number of TCs from given DCBx configuration
4449 **/
4450static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4451{
078b5876
JB		 4452 u8 num_tc = 0;
4453 int i;
41c445ff
JB		 4454
4455 /* Scan the ETS Config Priority Table to find
4456 * traffic class enabled for a given priority
4457 * and use the traffic class index to get the
4458 * number of traffic classes enabled
4459 */
4460 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4461 if (dcbcfg->etscfg.prioritytable[i] > num_tc)
4462 num_tc = dcbcfg->etscfg.prioritytable[i];
4463 }
4464
4465 /* Traffic class index starts from zero so
4466 * increment to return the actual count
4467 */
078b5876 4468 return num_tc + 1;
41c445ff
JB		 4469}
4470
4471/**
4472 * i40e_dcb_get_enabled_tc - Get enabled traffic classes
4473 * @dcbcfg: the corresponding DCBx configuration structure
4474 *
4475 * Query the current DCB configuration and return the number of
4476 * traffic classes enabled from the given DCBX config
4477 **/
4478static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4479{
4480 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4481 u8 enabled_tc = 1;
4482 u8 i;
4483
4484 for (i = 0; i < num_tc; i++)
41a1d04b 4485 enabled_tc |= BIT(i);
41c445ff
JB		 4486
4487 return enabled_tc;
4488}
4489
4490/**
4491 * i40e_pf_get_num_tc - Get enabled traffic classes for PF
4492 * @pf: PF being queried
4493 *
4494 * Return number of traffic classes enabled for the given PF
4495 **/
4496static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4497{
4498 struct i40e_hw *hw = &pf->hw;
4499 u8 i, enabled_tc;
4500 u8 num_tc = 0;
4501 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4502
4503 /* If DCB is not enabled then always in single TC */
4504 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4505 return 1;
4506
63d7e5a4
NP		 4507 /* SFP mode will be enabled for all TCs on port */
4508 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4509 return i40e_dcb_get_num_tc(dcbcfg);
4510
41c445ff 4511 /* MFP mode return count of enabled TCs for this PF */
63d7e5a4
NP		 4512 if (pf->hw.func_caps.iscsi)
4513 enabled_tc = i40e_get_iscsi_tc_map(pf);
4514 else
fc51de96 4515 return 1; /* Only TC0 */
41c445ff 4516
63d7e5a4
NP		 4517 /* At least have TC0 */
4518 enabled_tc = (enabled_tc ? enabled_tc : 0x1);
4519 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4520 if (enabled_tc & BIT_ULL(i))
63d7e5a4
NP		 4521 num_tc++;
4522 }
4523 return num_tc;
41c445ff
JB		 4524}
4525
4526/**
4527 * i40e_pf_get_default_tc - Get bitmap for first enabled TC
4528 * @pf: PF being queried
4529 *
4530 * Return a bitmap for first enabled traffic class for this PF.
4531 **/
4532static u8 i40e_pf_get_default_tc(struct i40e_pf *pf)
4533{
4534 u8 enabled_tc = pf->hw.func_caps.enabled_tcmap;
4535 u8 i = 0;
4536
4537 if (!enabled_tc)
4538 return 0x1; /* TC0 */
4539
4540 /* Find the first enabled TC */
4541 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4542 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4543 break;
4544 }
4545
41a1d04b 4546 return BIT(i);
41c445ff
JB		 4547}
4548
4549/**
4550 * i40e_pf_get_pf_tc_map - Get bitmap for enabled traffic classes
4551 * @pf: PF being queried
4552 *
4553 * Return a bitmap for enabled traffic classes for this PF.
4554 **/
4555static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
4556{
4557 /* If DCB is not enabled for this PF then just return default TC */
4558 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4559 return i40e_pf_get_default_tc(pf);
4560
41c445ff 4561 /* SFP mode we want PF to be enabled for all TCs */
63d7e5a4
NP		 4562 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4563 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
4564
fc51de96 4565 /* MFP enabled and iSCSI PF type */
63d7e5a4
NP		 4566 if (pf->hw.func_caps.iscsi)
4567 return i40e_get_iscsi_tc_map(pf);
4568 else
fc51de96 4569 return i40e_pf_get_default_tc(pf);
41c445ff
JB		 4570}
4571
4572/**
4573 * i40e_vsi_get_bw_info - Query VSI BW Information
4574 * @vsi: the VSI being queried
4575 *
4576 * Returns 0 on success, negative value on failure
4577 **/
4578static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
4579{
4580 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
4581 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
4582 struct i40e_pf *pf = vsi->back;
4583 struct i40e_hw *hw = &pf->hw;
f1c7e72e 4584 i40e_status ret;
41c445ff 4585 u32 tc_bw_max;
41c445ff
JB		 4586 int i;
4587
4588 /* Get the VSI level BW configuration */
f1c7e72e
SN		 4589 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
4590 if (ret) {
41c445ff 4591 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4592 "couldn't get PF vsi bw config, err %s aq_err %s\n",
4593 i40e_stat_str(&pf->hw, ret),
4594 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4595 return -EINVAL;
41c445ff
JB		 4596 }
4597
4598 /* Get the VSI level BW configuration per TC */
f1c7e72e
SN		 4599 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
4600 NULL);
4601 if (ret) {
41c445ff 4602 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4603 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
4604 i40e_stat_str(&pf->hw, ret),
4605 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
dcae29be 4606 return -EINVAL;
41c445ff
JB		 4607 }
4608
4609 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
4610 dev_info(&pf->pdev->dev,
4611 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
4612 bw_config.tc_valid_bits,
4613 bw_ets_config.tc_valid_bits);
4614 /* Still continuing */
4615 }
4616
4617 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
4618 vsi->bw_max_quanta = bw_config.max_bw;
4619 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
4620 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
4621 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4622 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
4623 vsi->bw_ets_limit_credits[i] =
4624 le16_to_cpu(bw_ets_config.credits[i]);
4625 /* 3 bits out of 4 for each TC */
4626 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
4627 }
078b5876 4628
dcae29be 4629 return 0;
41c445ff
JB		 4630}
4631
4632/**
4633 * i40e_vsi_configure_bw_alloc - Configure VSI BW allocation per TC
4634 * @vsi: the VSI being configured
4635 * @enabled_tc: TC bitmap
4636 * @bw_credits: BW shared credits per TC
4637 *
4638 * Returns 0 on success, negative value on failure
4639 **/
dcae29be 4640static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
41c445ff
JB		 4641 u8 *bw_share)
4642{
4643 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
f1c7e72e 4644 i40e_status ret;
dcae29be 4645 int i;
41c445ff
JB		 4646
4647 bw_data.tc_valid_bits = enabled_tc;
4648 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4649 bw_data.tc_bw_credits[i] = bw_share[i];
4650
f1c7e72e
SN		 4651 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
4652 NULL);
4653 if (ret) {
41c445ff 4654 dev_info(&vsi->back->pdev->dev,
69bfb110
JB		 4655 "AQ command Config VSI BW allocation per TC failed = %d\n",
4656 vsi->back->hw.aq.asq_last_status);
dcae29be 4657 return -EINVAL;
41c445ff
JB		 4658 }
4659
4660 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4661 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
4662
dcae29be 4663 return 0;
41c445ff
JB		 4664}
4665
4666/**
4667 * i40e_vsi_config_netdev_tc - Setup the netdev TC configuration
4668 * @vsi: the VSI being configured
4669 * @enabled_tc: TC map to be enabled
4670 *
4671 **/
4672static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4673{
4674 struct net_device *netdev = vsi->netdev;
4675 struct i40e_pf *pf = vsi->back;
4676 struct i40e_hw *hw = &pf->hw;
4677 u8 netdev_tc = 0;
4678 int i;
4679 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4680
4681 if (!netdev)
4682 return;
4683
4684 if (!enabled_tc) {
4685 netdev_reset_tc(netdev);
4686 return;
4687 }
4688
4689 /* Set up actual enabled TCs on the VSI */
4690 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
4691 return;
4692
4693 /* set per TC queues for the VSI */
4694 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4695 /* Only set TC queues for enabled tcs
4696 *
4697 * e.g. For a VSI that has TC0 and TC3 enabled the
4698 * enabled_tc bitmap would be 0x00001001; the driver
4699 * will set the numtc for netdev as 2 that will be
4700 * referenced by the netdev layer as TC 0 and 1.
4701 */
41a1d04b 4702 if (vsi->tc_config.enabled_tc & BIT_ULL(i))
41c445ff
JB		 4703 netdev_set_tc_queue(netdev,
4704 vsi->tc_config.tc_info[i].netdev_tc,
4705 vsi->tc_config.tc_info[i].qcount,
4706 vsi->tc_config.tc_info[i].qoffset);
4707 }
4708
4709 /* Assign UP2TC map for the VSI */
4710 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
4711 /* Get the actual TC# for the UP */
4712 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
4713 /* Get the mapped netdev TC# for the UP */
4714 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
4715 netdev_set_prio_tc_map(netdev, i, netdev_tc);
4716 }
4717}
4718
4719/**
4720 * i40e_vsi_update_queue_map - Update our copy of VSi info with new queue map
4721 * @vsi: the VSI being configured
4722 * @ctxt: the ctxt buffer returned from AQ VSI update param command
4723 **/
4724static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
4725 struct i40e_vsi_context *ctxt)
4726{
4727 /* copy just the sections touched not the entire info
4728 * since not all sections are valid as returned by
4729 * update vsi params
4730 */
4731 vsi->info.mapping_flags = ctxt->info.mapping_flags;
4732 memcpy(&vsi->info.queue_mapping,
4733 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
4734 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
4735 sizeof(vsi->info.tc_mapping));
4736}
4737
4738/**
4739 * i40e_vsi_config_tc - Configure VSI Tx Scheduler for given TC map
4740 * @vsi: VSI to be configured
4741 * @enabled_tc: TC bitmap
4742 *
4743 * This configures a particular VSI for TCs that are mapped to the
4744 * given TC bitmap. It uses default bandwidth share for TCs across
4745 * VSIs to configure TC for a particular VSI.
4746 *
4747 * NOTE:
4748 * It is expected that the VSI queues have been quisced before calling
4749 * this function.
4750 **/
4751static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
4752{
4753 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
4754 struct i40e_vsi_context ctxt;
4755 int ret = 0;
4756 int i;
4757
4758 /* Check if enabled_tc is same as existing or new TCs */
4759 if (vsi->tc_config.enabled_tc == enabled_tc)
4760 return ret;
4761
4762 /* Enable ETS TCs with equal BW Share for now across all VSIs */
4763 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4764 if (enabled_tc & BIT_ULL(i))
41c445ff
JB		 4765 bw_share[i] = 1;
4766 }
4767
4768 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
4769 if (ret) {
4770 dev_info(&vsi->back->pdev->dev,
4771 "Failed configuring TC map %d for VSI %d\n",
4772 enabled_tc, vsi->seid);
4773 goto out;
4774 }
4775
4776 /* Update Queue Pairs Mapping for currently enabled UPs */
4777 ctxt.seid = vsi->seid;
4778 ctxt.pf_num = vsi->back->hw.pf_id;
4779 ctxt.vf_num = 0;
4780 ctxt.uplink_seid = vsi->uplink_seid;
1a2f6248 4781 ctxt.info = vsi->info;
41c445ff
JB		 4782 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
4783
4784 /* Update the VSI after updating the VSI queue-mapping information */
4785 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
4786 if (ret) {
4787 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4788 "Update vsi tc config failed, err %s aq_err %s\n",
4789 i40e_stat_str(&vsi->back->hw, ret),
4790 i40e_aq_str(&vsi->back->hw,
4791 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4792 goto out;
4793 }
4794 /* update the local VSI info with updated queue map */
4795 i40e_vsi_update_queue_map(vsi, &ctxt);
4796 vsi->info.valid_sections = 0;
4797
4798 /* Update current VSI BW information */
4799 ret = i40e_vsi_get_bw_info(vsi);
4800 if (ret) {
4801 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 4802 "Failed updating vsi bw info, err %s aq_err %s\n",
4803 i40e_stat_str(&vsi->back->hw, ret),
4804 i40e_aq_str(&vsi->back->hw,
4805 vsi->back->hw.aq.asq_last_status));
41c445ff
JB		 4806 goto out;
4807 }
4808
4809 /* Update the netdev TC setup */
4810 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
4811out:
4812 return ret;
4813}
4814
4e3b35b0
NP		 4815/**
4816 * i40e_veb_config_tc - Configure TCs for given VEB
4817 * @veb: given VEB
4818 * @enabled_tc: TC bitmap
4819 *
4820 * Configures given TC bitmap for VEB (switching) element
4821 **/
4822int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
4823{
4824 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
4825 struct i40e_pf *pf = veb->pf;
4826 int ret = 0;
4827 int i;
4828
4829 /* No TCs or already enabled TCs just return */
4830 if (!enabled_tc || veb->enabled_tc == enabled_tc)
4831 return ret;
4832
4833 bw_data.tc_valid_bits = enabled_tc;
4834 /* bw_data.absolute_credits is not set (relative) */
4835
4836 /* Enable ETS TCs with equal BW Share for now */
4837 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
41a1d04b 4838 if (enabled_tc & BIT_ULL(i))
4e3b35b0
NP		 4839 bw_data.tc_bw_share_credits[i] = 1;
4840 }
4841
4842 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
4843 &bw_data, NULL);
4844 if (ret) {
4845 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4846 "VEB bw config failed, err %s aq_err %s\n",
4847 i40e_stat_str(&pf->hw, ret),
4848 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4849 goto out;
4850 }
4851
4852 /* Update the BW information */
4853 ret = i40e_veb_get_bw_info(veb);
4854 if (ret) {
4855 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4856 "Failed getting veb bw config, err %s aq_err %s\n",
4857 i40e_stat_str(&pf->hw, ret),
4858 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 4859 }
4860
4861out:
4862 return ret;
4863}
4864
4865#ifdef CONFIG_I40E_DCB
4866/**
4867 * i40e_dcb_reconfigure - Reconfigure all VEBs and VSIs
4868 * @pf: PF struct
4869 *
4870 * Reconfigure VEB/VSIs on a given PF; it is assumed that
4871 * the caller would've quiesce all the VSIs before calling
4872 * this function
4873 **/
4874static void i40e_dcb_reconfigure(struct i40e_pf *pf)
4875{
4876 u8 tc_map = 0;
4877 int ret;
4878 u8 v;
4879
4880 /* Enable the TCs available on PF to all VEBs */
4881 tc_map = i40e_pf_get_tc_map(pf);
4882 for (v = 0; v < I40E_MAX_VEB; v++) {
4883 if (!pf->veb[v])
4884 continue;
4885 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
4886 if (ret) {
4887 dev_info(&pf->pdev->dev,
4888 "Failed configuring TC for VEB seid=%d\n",
4889 pf->veb[v]->seid);
4890 /* Will try to configure as many components */
4891 }
4892 }
4893
4894 /* Update each VSI */
505682cd 4895 for (v = 0; v < pf->num_alloc_vsi; v++) {
4e3b35b0
NP		 4896 if (!pf->vsi[v])
4897 continue;
4898
4899 /* - Enable all TCs for the LAN VSI
38e00438
VD		 4900#ifdef I40E_FCOE
4901 * - For FCoE VSI only enable the TC configured
4902 * as per the APP TLV
4903#endif
4e3b35b0
NP		 4904 * - For all others keep them at TC0 for now
4905 */
4906 if (v == pf->lan_vsi)
4907 tc_map = i40e_pf_get_tc_map(pf);
4908 else
4909 tc_map = i40e_pf_get_default_tc(pf);
38e00438
VD		 4910#ifdef I40E_FCOE
4911 if (pf->vsi[v]->type == I40E_VSI_FCOE)
4912 tc_map = i40e_get_fcoe_tc_map(pf);
4913#endif /* #ifdef I40E_FCOE */
4e3b35b0
NP		 4914
4915 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
4916 if (ret) {
4917 dev_info(&pf->pdev->dev,
4918 "Failed configuring TC for VSI seid=%d\n",
4919 pf->vsi[v]->seid);
4920 /* Will try to configure as many components */
4921 } else {
0672a091
NP		 4922 /* Re-configure VSI vectors based on updated TC map */
4923 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
4e3b35b0
NP		 4924 if (pf->vsi[v]->netdev)
4925 i40e_dcbnl_set_all(pf->vsi[v]);
4926 }
4927 }
4928}
4929
2fd75f31
NP		 4930/**
4931 * i40e_resume_port_tx - Resume port Tx
4932 * @pf: PF struct
4933 *
4934 * Resume a port's Tx and issue a PF reset in case of failure to
4935 * resume.
4936 **/
4937static int i40e_resume_port_tx(struct i40e_pf *pf)
4938{
4939 struct i40e_hw *hw = &pf->hw;
4940 int ret;
4941
4942 ret = i40e_aq_resume_port_tx(hw, NULL);
4943 if (ret) {
4944 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4945 "Resume Port Tx failed, err %s aq_err %s\n",
4946 i40e_stat_str(&pf->hw, ret),
4947 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
2fd75f31
NP		 4948 /* Schedule PF reset to recover */
4949 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
4950 i40e_service_event_schedule(pf);
4951 }
4952
4953 return ret;
4954}
4955
4e3b35b0
NP		 4956/**
4957 * i40e_init_pf_dcb - Initialize DCB configuration
4958 * @pf: PF being configured
4959 *
4960 * Query the current DCB configuration and cache it
4961 * in the hardware structure
4962 **/
4963static int i40e_init_pf_dcb(struct i40e_pf *pf)
4964{
4965 struct i40e_hw *hw = &pf->hw;
4966 int err = 0;
4967
025b4a54
ASJ		 4968 /* Do not enable DCB for SW1 and SW2 images even if the FW is capable */
4969 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
4970 (pf->hw.aq.fw_maj_ver < 4))
4971 goto out;
4972
4e3b35b0
NP		 4973 /* Get the initial DCB configuration */
4974 err = i40e_init_dcb(hw);
4975 if (!err) {
4976 /* Device/Function is not DCBX capable */
4977 if ((!hw->func_caps.dcb) ||
4978 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
4979 dev_info(&pf->pdev->dev,
4980 "DCBX offload is not supported or is disabled for this PF.\n");
4981
4982 if (pf->flags & I40E_FLAG_MFP_ENABLED)
4983 goto out;
4984
4985 } else {
4986 /* When status is not DISABLED then DCBX in FW */
4987 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
4988 DCB_CAP_DCBX_VER_IEEE;
4d9b6043
NP		 4989
4990 pf->flags |= I40E_FLAG_DCB_CAPABLE;
4991 /* Enable DCB tagging only when more than one TC */
4992 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4993 pf->flags |= I40E_FLAG_DCB_ENABLED;
9fa61dd2
NP		 4994 dev_dbg(&pf->pdev->dev,
4995 "DCBX offload is supported for this PF.\n");
4e3b35b0 4996 }
014269ff 4997 } else {
aebfc816 4998 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 4999 "Query for DCB configuration failed, err %s aq_err %s\n",
5000 i40e_stat_str(&pf->hw, err),
5001 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5002 }
5003
5004out:
5005 return err;
5006}
5007#endif /* CONFIG_I40E_DCB */
cf05ed08
JB		 5008#define SPEED_SIZE 14
5009#define FC_SIZE 8
5010/**
5011 * i40e_print_link_message - print link up or down
5012 * @vsi: the VSI for which link needs a message
5013 */
c156f856 5014void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
cf05ed08 5015{
a9165490
SN		 5016 char *speed = "Unknown";
5017 char *fc = "Unknown";
cf05ed08 5018
c156f856
MJ		 5019 if (vsi->current_isup == isup)
5020 return;
5021 vsi->current_isup = isup;
cf05ed08
JB		 5022 if (!isup) {
5023 netdev_info(vsi->netdev, "NIC Link is Down\n");
5024 return;
5025 }
5026
148c2d80
GR		 5027 /* Warn user if link speed on NPAR enabled partition is not at
5028 * least 10GB
5029 */
5030 if (vsi->back->hw.func_caps.npar_enable &&
5031 (vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
5032 vsi->back->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
5033 netdev_warn(vsi->netdev,
5034 "The partition detected link speed that is less than 10Gbps\n");
5035
cf05ed08
JB		 5036 switch (vsi->back->hw.phy.link_info.link_speed) {
5037 case I40E_LINK_SPEED_40GB:
a9165490 5038 speed = "40 G";
cf05ed08 5039 break;
ae24b409 5040 case I40E_LINK_SPEED_20GB:
a9165490 5041 speed = "20 G";
ae24b409 5042 break;
cf05ed08 5043 case I40E_LINK_SPEED_10GB:
a9165490 5044 speed = "10 G";
cf05ed08
JB		 5045 break;
5046 case I40E_LINK_SPEED_1GB:
a9165490 5047 speed = "1000 M";
cf05ed08 5048 break;
5960d33f 5049 case I40E_LINK_SPEED_100MB:
a9165490 5050 speed = "100 M";
5960d33f 5051 break;
cf05ed08
JB		 5052 default:
5053 break;
5054 }
5055
5056 switch (vsi->back->hw.fc.current_mode) {
5057 case I40E_FC_FULL:
a9165490 5058 fc = "RX/TX";
cf05ed08
JB		 5059 break;
5060 case I40E_FC_TX_PAUSE:
a9165490 5061 fc = "TX";
cf05ed08
JB		 5062 break;
5063 case I40E_FC_RX_PAUSE:
a9165490 5064 fc = "RX";
cf05ed08
JB		 5065 break;
5066 default:
a9165490 5067 fc = "None";
cf05ed08
JB		 5068 break;
5069 }
5070
a9165490 5071 netdev_info(vsi->netdev, "NIC Link is Up %sbps Full Duplex, Flow Control: %s\n",
cf05ed08
JB		 5072 speed, fc);
5073}
4e3b35b0 5074
41c445ff
JB		 5075/**
5076 * i40e_up_complete - Finish the last steps of bringing up a connection
5077 * @vsi: the VSI being configured
5078 **/
5079static int i40e_up_complete(struct i40e_vsi *vsi)
5080{
5081 struct i40e_pf *pf = vsi->back;
5082 int err;
5083
5084 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
5085 i40e_vsi_configure_msix(vsi);
5086 else
5087 i40e_configure_msi_and_legacy(vsi);
5088
5089 /* start rings */
5090 err = i40e_vsi_control_rings(vsi, true);
5091 if (err)
5092 return err;
5093
5094 clear_bit(__I40E_DOWN, &vsi->state);
5095 i40e_napi_enable_all(vsi);
5096 i40e_vsi_enable_irq(vsi);
5097
5098 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
5099 (vsi->netdev)) {
cf05ed08 5100 i40e_print_link_message(vsi, true);
41c445ff
JB		 5101 netif_tx_start_all_queues(vsi->netdev);
5102 netif_carrier_on(vsi->netdev);
6d779b41 5103 } else if (vsi->netdev) {
cf05ed08 5104 i40e_print_link_message(vsi, false);
7b592f61
CW		 5105 /* need to check for qualified module here*/
5106 if ((pf->hw.phy.link_info.link_info &
5107 I40E_AQ_MEDIA_AVAILABLE) &&
5108 (!(pf->hw.phy.link_info.an_info &
5109 I40E_AQ_QUALIFIED_MODULE)))
5110 netdev_err(vsi->netdev,
5111 "the driver failed to link because an unqualified module was detected.");
41c445ff 5112 }
ca64fa4e
ASJ		 5113
5114 /* replay FDIR SB filters */
1e1be8f6
ASJ		 5115 if (vsi->type == I40E_VSI_FDIR) {
5116 /* reset fd counters */
5117 pf->fd_add_err = pf->fd_atr_cnt = 0;
5118 if (pf->fd_tcp_rule > 0) {
5119 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5120 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5121 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
1e1be8f6
ASJ		 5122 pf->fd_tcp_rule = 0;
5123 }
ca64fa4e 5124 i40e_fdir_filter_restore(vsi);
1e1be8f6 5125 }
41c445ff
JB		 5126 i40e_service_event_schedule(pf);
5127
5128 return 0;
5129}
5130
5131/**
5132 * i40e_vsi_reinit_locked - Reset the VSI
5133 * @vsi: the VSI being configured
5134 *
5135 * Rebuild the ring structs after some configuration
5136 * has changed, e.g. MTU size.
5137 **/
5138static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
5139{
5140 struct i40e_pf *pf = vsi->back;
5141
5142 WARN_ON(in_interrupt());
5143 while (test_and_set_bit(__I40E_CONFIG_BUSY, &pf->state))
5144 usleep_range(1000, 2000);
5145 i40e_down(vsi);
5146
5147 /* Give a VF some time to respond to the reset. The
5148 * two second wait is based upon the watchdog cycle in
5149 * the VF driver.
5150 */
5151 if (vsi->type == I40E_VSI_SRIOV)
5152 msleep(2000);
5153 i40e_up(vsi);
5154 clear_bit(__I40E_CONFIG_BUSY, &pf->state);
5155}
5156
5157/**
5158 * i40e_up - Bring the connection back up after being down
5159 * @vsi: the VSI being configured
5160 **/
5161int i40e_up(struct i40e_vsi *vsi)
5162{
5163 int err;
5164
5165 err = i40e_vsi_configure(vsi);
5166 if (!err)
5167 err = i40e_up_complete(vsi);
5168
5169 return err;
5170}
5171
5172/**
5173 * i40e_down - Shutdown the connection processing
5174 * @vsi: the VSI being stopped
5175 **/
5176void i40e_down(struct i40e_vsi *vsi)
5177{
5178 int i;
5179
5180 /* It is assumed that the caller of this function
5181 * sets the vsi->state __I40E_DOWN bit.
5182 */
5183 if (vsi->netdev) {
5184 netif_carrier_off(vsi->netdev);
5185 netif_tx_disable(vsi->netdev);
5186 }
5187 i40e_vsi_disable_irq(vsi);
5188 i40e_vsi_control_rings(vsi, false);
5189 i40e_napi_disable_all(vsi);
5190
5191 for (i = 0; i < vsi->num_queue_pairs; i++) {
9f65e15b
AD		 5192 i40e_clean_tx_ring(vsi->tx_rings[i]);
5193 i40e_clean_rx_ring(vsi->rx_rings[i]);
41c445ff
JB		 5194 }
5195}
5196
5197/**
5198 * i40e_setup_tc - configure multiple traffic classes
5199 * @netdev: net device to configure
5200 * @tc: number of traffic classes to enable
5201 **/
38e00438
VD		 5202#ifdef I40E_FCOE
5203int i40e_setup_tc(struct net_device *netdev, u8 tc)
5204#else
41c445ff 5205static int i40e_setup_tc(struct net_device *netdev, u8 tc)
38e00438 5206#endif
41c445ff
JB		 5207{
5208 struct i40e_netdev_priv *np = netdev_priv(netdev);
5209 struct i40e_vsi *vsi = np->vsi;
5210 struct i40e_pf *pf = vsi->back;
5211 u8 enabled_tc = 0;
5212 int ret = -EINVAL;
5213 int i;
5214
5215 /* Check if DCB enabled to continue */
5216 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
5217 netdev_info(netdev, "DCB is not enabled for adapter\n");
5218 goto exit;
5219 }
5220
5221 /* Check if MFP enabled */
5222 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
5223 netdev_info(netdev, "Configuring TC not supported in MFP mode\n");
5224 goto exit;
5225 }
5226
5227 /* Check whether tc count is within enabled limit */
5228 if (tc > i40e_pf_get_num_tc(pf)) {
5229 netdev_info(netdev, "TC count greater than enabled on link for adapter\n");
5230 goto exit;
5231 }
5232
5233 /* Generate TC map for number of tc requested */
5234 for (i = 0; i < tc; i++)
41a1d04b 5235 enabled_tc |= BIT_ULL(i);
41c445ff
JB		 5236
5237 /* Requesting same TC configuration as already enabled */
5238 if (enabled_tc == vsi->tc_config.enabled_tc)
5239 return 0;
5240
5241 /* Quiesce VSI queues */
5242 i40e_quiesce_vsi(vsi);
5243
5244 /* Configure VSI for enabled TCs */
5245 ret = i40e_vsi_config_tc(vsi, enabled_tc);
5246 if (ret) {
5247 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
5248 vsi->seid);
5249 goto exit;
5250 }
5251
5252 /* Unquiesce VSI */
5253 i40e_unquiesce_vsi(vsi);
5254
5255exit:
5256 return ret;
5257}
5258
5259/**
5260 * i40e_open - Called when a network interface is made active
5261 * @netdev: network interface device structure
5262 *
5263 * The open entry point is called when a network interface is made
5264 * active by the system (IFF_UP). At this point all resources needed
5265 * for transmit and receive operations are allocated, the interrupt
5266 * handler is registered with the OS, the netdev watchdog subtask is
5267 * enabled, and the stack is notified that the interface is ready.
5268 *
5269 * Returns 0 on success, negative value on failure
5270 **/
38e00438 5271int i40e_open(struct net_device *netdev)
41c445ff
JB		 5272{
5273 struct i40e_netdev_priv *np = netdev_priv(netdev);
5274 struct i40e_vsi *vsi = np->vsi;
5275 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 5276 int err;
5277
4eb3f768
SN		 5278 /* disallow open during test or if eeprom is broken */
5279 if (test_bit(__I40E_TESTING, &pf->state) ||
5280 test_bit(__I40E_BAD_EEPROM, &pf->state))
41c445ff
JB		 5281 return -EBUSY;
5282
5283 netif_carrier_off(netdev);
5284
6c167f58
EK		 5285 err = i40e_vsi_open(vsi);
5286 if (err)
5287 return err;
5288
059dab69
JB		 5289 /* configure global TSO hardware offload settings */
5290 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
5291 TCP_FLAG_FIN) >> 16);
5292 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
5293 TCP_FLAG_FIN |
5294 TCP_FLAG_CWR) >> 16);
5295 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
5296
6633d381 5297#ifdef CONFIG_I40E_VXLAN
6c167f58
EK		 5298 vxlan_get_rx_port(netdev);
5299#endif
5300
5301 return 0;
5302}
5303
5304/**
5305 * i40e_vsi_open -
5306 * @vsi: the VSI to open
5307 *
5308 * Finish initialization of the VSI.
5309 *
5310 * Returns 0 on success, negative value on failure
5311 **/
5312int i40e_vsi_open(struct i40e_vsi *vsi)
5313{
5314 struct i40e_pf *pf = vsi->back;
b294ac70 5315 char int_name[I40E_INT_NAME_STR_LEN];
6c167f58
EK		 5316 int err;
5317
41c445ff
JB		 5318 /* allocate descriptors */
5319 err = i40e_vsi_setup_tx_resources(vsi);
5320 if (err)
5321 goto err_setup_tx;
5322 err = i40e_vsi_setup_rx_resources(vsi);
5323 if (err)
5324 goto err_setup_rx;
5325
5326 err = i40e_vsi_configure(vsi);
5327 if (err)
5328 goto err_setup_rx;
5329
c22e3c6c
SN		 5330 if (vsi->netdev) {
5331 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
5332 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
5333 err = i40e_vsi_request_irq(vsi, int_name);
5334 if (err)
5335 goto err_setup_rx;
41c445ff 5336
c22e3c6c
SN		 5337 /* Notify the stack of the actual queue counts. */
5338 err = netif_set_real_num_tx_queues(vsi->netdev,
5339 vsi->num_queue_pairs);
5340 if (err)
5341 goto err_set_queues;
25946ddb 5342
c22e3c6c
SN		 5343 err = netif_set_real_num_rx_queues(vsi->netdev,
5344 vsi->num_queue_pairs);
5345 if (err)
5346 goto err_set_queues;
8a9eb7d3
SN		 5347
5348 } else if (vsi->type == I40E_VSI_FDIR) {
e240f674 5349 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
b2008cbf
CW		 5350 dev_driver_string(&pf->pdev->dev),
5351 dev_name(&pf->pdev->dev));
8a9eb7d3 5352 err = i40e_vsi_request_irq(vsi, int_name);
b2008cbf 5353
c22e3c6c 5354 } else {
ce9ccb17 5355 err = -EINVAL;
6c167f58
EK		 5356 goto err_setup_rx;
5357 }
25946ddb 5358
41c445ff
JB		 5359 err = i40e_up_complete(vsi);
5360 if (err)
5361 goto err_up_complete;
5362
41c445ff
JB		 5363 return 0;
5364
5365err_up_complete:
5366 i40e_down(vsi);
25946ddb 5367err_set_queues:
41c445ff
JB		 5368 i40e_vsi_free_irq(vsi);
5369err_setup_rx:
5370 i40e_vsi_free_rx_resources(vsi);
5371err_setup_tx:
5372 i40e_vsi_free_tx_resources(vsi);
5373 if (vsi == pf->vsi[pf->lan_vsi])
41a1d04b 5374 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
41c445ff
JB		 5375
5376 return err;
5377}
5378
17a73f6b
JG		 5379/**
5380 * i40e_fdir_filter_exit - Cleans up the Flow Director accounting
b40c82e6 5381 * @pf: Pointer to PF
17a73f6b
JG		 5382 *
5383 * This function destroys the hlist where all the Flow Director
5384 * filters were saved.
5385 **/
5386static void i40e_fdir_filter_exit(struct i40e_pf *pf)
5387{
5388 struct i40e_fdir_filter *filter;
5389 struct hlist_node *node2;
5390
5391 hlist_for_each_entry_safe(filter, node2,
5392 &pf->fdir_filter_list, fdir_node) {
5393 hlist_del(&filter->fdir_node);
5394 kfree(filter);
5395 }
5396 pf->fdir_pf_active_filters = 0;
5397}
5398
41c445ff
JB		 5399/**
5400 * i40e_close - Disables a network interface
5401 * @netdev: network interface device structure
5402 *
5403 * The close entry point is called when an interface is de-activated
5404 * by the OS. The hardware is still under the driver's control, but
5405 * this netdev interface is disabled.
5406 *
5407 * Returns 0, this is not allowed to fail
5408 **/
38e00438
VD		 5409#ifdef I40E_FCOE
5410int i40e_close(struct net_device *netdev)
5411#else
41c445ff 5412static int i40e_close(struct net_device *netdev)
38e00438 5413#endif
41c445ff
JB		 5414{
5415 struct i40e_netdev_priv *np = netdev_priv(netdev);
5416 struct i40e_vsi *vsi = np->vsi;
5417
90ef8d47 5418 i40e_vsi_close(vsi);
41c445ff
JB		 5419
5420 return 0;
5421}
5422
5423/**
5424 * i40e_do_reset - Start a PF or Core Reset sequence
5425 * @pf: board private structure
5426 * @reset_flags: which reset is requested
5427 *
5428 * The essential difference in resets is that the PF Reset
5429 * doesn't clear the packet buffers, doesn't reset the PE
5430 * firmware, and doesn't bother the other PFs on the chip.
5431 **/
5432void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags)
5433{
5434 u32 val;
5435
5436 WARN_ON(in_interrupt());
5437
263fc48f
MW		 5438 if (i40e_check_asq_alive(&pf->hw))
5439 i40e_vc_notify_reset(pf);
5440
41c445ff 5441 /* do the biggest reset indicated */
41a1d04b 5442 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
41c445ff
JB		 5443
5444 /* Request a Global Reset
5445 *
5446 * This will start the chip's countdown to the actual full
5447 * chip reset event, and a warning interrupt to be sent
5448 * to all PFs, including the requestor. Our handler
5449 * for the warning interrupt will deal with the shutdown
5450 * and recovery of the switch setup.
5451 */
69bfb110 5452 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
41c445ff
JB		 5453 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5454 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
5455 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5456
41a1d04b 5457 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
41c445ff
JB		 5458
5459 /* Request a Core Reset
5460 *
5461 * Same as Global Reset, except does *not* include the MAC/PHY
5462 */
69bfb110 5463 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
41c445ff
JB		 5464 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
5465 val |= I40E_GLGEN_RTRIG_CORER_MASK;
5466 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
5467 i40e_flush(&pf->hw);
5468
41a1d04b 5469 } else if (reset_flags & BIT_ULL(__I40E_PF_RESET_REQUESTED)) {
41c445ff
JB		 5470
5471 /* Request a PF Reset
5472 *
5473 * Resets only the PF-specific registers
5474 *
5475 * This goes directly to the tear-down and rebuild of
5476 * the switch, since we need to do all the recovery as
5477 * for the Core Reset.
5478 */
69bfb110 5479 dev_dbg(&pf->pdev->dev, "PFR requested\n");
41c445ff
JB		 5480 i40e_handle_reset_warning(pf);
5481
41a1d04b 5482 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
41c445ff
JB		 5483 int v;
5484
5485 /* Find the VSI(s) that requested a re-init */
5486 dev_info(&pf->pdev->dev,
5487 "VSI reinit requested\n");
505682cd 5488 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff 5489 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5490
41c445ff
JB		 5491 if (vsi != NULL &&
5492 test_bit(__I40E_REINIT_REQUESTED, &vsi->state)) {
5493 i40e_vsi_reinit_locked(pf->vsi[v]);
5494 clear_bit(__I40E_REINIT_REQUESTED, &vsi->state);
5495 }
5496 }
41a1d04b 5497 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
b5d06f05
NP		 5498 int v;
5499
5500 /* Find the VSI(s) that needs to be brought down */
5501 dev_info(&pf->pdev->dev, "VSI down requested\n");
5502 for (v = 0; v < pf->num_alloc_vsi; v++) {
5503 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 5504
b5d06f05
NP		 5505 if (vsi != NULL &&
5506 test_bit(__I40E_DOWN_REQUESTED, &vsi->state)) {
5507 set_bit(__I40E_DOWN, &vsi->state);
5508 i40e_down(vsi);
5509 clear_bit(__I40E_DOWN_REQUESTED, &vsi->state);
5510 }
5511 }
41c445ff
JB		 5512 } else {
5513 dev_info(&pf->pdev->dev,
5514 "bad reset request 0x%08x\n", reset_flags);
41c445ff
JB		 5515 }
5516}
5517
4e3b35b0
NP		 5518#ifdef CONFIG_I40E_DCB
5519/**
5520 * i40e_dcb_need_reconfig - Check if DCB needs reconfig
5521 * @pf: board private structure
5522 * @old_cfg: current DCB config
5523 * @new_cfg: new DCB config
5524 **/
5525bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
5526 struct i40e_dcbx_config *old_cfg,
5527 struct i40e_dcbx_config *new_cfg)
5528{
5529 bool need_reconfig = false;
5530
5531 /* Check if ETS configuration has changed */
5532 if (memcmp(&new_cfg->etscfg,
5533 &old_cfg->etscfg,
5534 sizeof(new_cfg->etscfg))) {
5535 /* If Priority Table has changed reconfig is needed */
5536 if (memcmp(&new_cfg->etscfg.prioritytable,
5537 &old_cfg->etscfg.prioritytable,
5538 sizeof(new_cfg->etscfg.prioritytable))) {
5539 need_reconfig = true;
69bfb110 5540 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
4e3b35b0
NP		 5541 }
5542
5543 if (memcmp(&new_cfg->etscfg.tcbwtable,
5544 &old_cfg->etscfg.tcbwtable,
5545 sizeof(new_cfg->etscfg.tcbwtable)))
69bfb110 5546 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
4e3b35b0
NP		 5547
5548 if (memcmp(&new_cfg->etscfg.tsatable,
5549 &old_cfg->etscfg.tsatable,
5550 sizeof(new_cfg->etscfg.tsatable)))
69bfb110 5551 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
4e3b35b0
NP		 5552 }
5553
5554 /* Check if PFC configuration has changed */
5555 if (memcmp(&new_cfg->pfc,
5556 &old_cfg->pfc,
5557 sizeof(new_cfg->pfc))) {
5558 need_reconfig = true;
69bfb110 5559 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
4e3b35b0
NP		 5560 }
5561
5562 /* Check if APP Table has changed */
5563 if (memcmp(&new_cfg->app,
5564 &old_cfg->app,
3d9667a9 5565 sizeof(new_cfg->app))) {
4e3b35b0 5566 need_reconfig = true;
69bfb110 5567 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
3d9667a9 5568 }
4e3b35b0 5569
fb43201f 5570 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
4e3b35b0
NP		 5571 return need_reconfig;
5572}
5573
5574/**
5575 * i40e_handle_lldp_event - Handle LLDP Change MIB event
5576 * @pf: board private structure
5577 * @e: event info posted on ARQ
5578 **/
5579static int i40e_handle_lldp_event(struct i40e_pf *pf,
5580 struct i40e_arq_event_info *e)
5581{
5582 struct i40e_aqc_lldp_get_mib *mib =
5583 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
5584 struct i40e_hw *hw = &pf->hw;
4e3b35b0
NP		 5585 struct i40e_dcbx_config tmp_dcbx_cfg;
5586 bool need_reconfig = false;
5587 int ret = 0;
5588 u8 type;
5589
4d9b6043
NP		 5590 /* Not DCB capable or capability disabled */
5591 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
5592 return ret;
5593
4e3b35b0
NP		 5594 /* Ignore if event is not for Nearest Bridge */
5595 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
5596 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
fb43201f 5597 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
4e3b35b0
NP		 5598 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
5599 return ret;
5600
5601 /* Check MIB Type and return if event for Remote MIB update */
5602 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
9fa61dd2 5603 dev_dbg(&pf->pdev->dev,
fb43201f 5604 "LLDP event mib type %s\n", type ? "remote" : "local");
4e3b35b0
NP		 5605 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
5606 /* Update the remote cached instance and return */
5607 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
5608 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
5609 &hw->remote_dcbx_config);
5610 goto exit;
5611 }
5612
9fa61dd2 5613 /* Store the old configuration */
1a2f6248 5614 tmp_dcbx_cfg = hw->local_dcbx_config;
9fa61dd2 5615
750fcbcf
NP		 5616 /* Reset the old DCBx configuration data */
5617 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
9fa61dd2
NP		 5618 /* Get updated DCBX data from firmware */
5619 ret = i40e_get_dcb_config(&pf->hw);
4e3b35b0 5620 if (ret) {
f1c7e72e
SN		 5621 dev_info(&pf->pdev->dev,
5622 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
5623 i40e_stat_str(&pf->hw, ret),
5624 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
4e3b35b0
NP		 5625 goto exit;
5626 }
5627
5628 /* No change detected in DCBX configs */
750fcbcf
NP		 5629 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
5630 sizeof(tmp_dcbx_cfg))) {
69bfb110 5631 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
4e3b35b0
NP		 5632 goto exit;
5633 }
5634
750fcbcf
NP		 5635 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
5636 &hw->local_dcbx_config);
4e3b35b0 5637
750fcbcf 5638 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
4e3b35b0
NP		 5639
5640 if (!need_reconfig)
5641 goto exit;
5642
4d9b6043 5643 /* Enable DCB tagging only when more than one TC */
750fcbcf 5644 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
4d9b6043
NP		 5645 pf->flags |= I40E_FLAG_DCB_ENABLED;
5646 else
5647 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
5648
69129dc3 5649 set_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
4e3b35b0
NP		 5650 /* Reconfiguration needed quiesce all VSIs */
5651 i40e_pf_quiesce_all_vsi(pf);
5652
5653 /* Changes in configuration update VEB/VSI */
5654 i40e_dcb_reconfigure(pf);
5655
2fd75f31
NP		 5656 ret = i40e_resume_port_tx(pf);
5657
69129dc3 5658 clear_bit(__I40E_PORT_TX_SUSPENDED, &pf->state);
2fd75f31 5659 /* In case of error no point in resuming VSIs */
69129dc3
NP		 5660 if (ret)
5661 goto exit;
5662
5663 /* Wait for the PF's Tx queues to be disabled */
5664 ret = i40e_pf_wait_txq_disabled(pf);
11e47708
PN		 5665 if (ret) {
5666 /* Schedule PF reset to recover */
5667 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
5668 i40e_service_event_schedule(pf);
5669 } else {
2fd75f31 5670 i40e_pf_unquiesce_all_vsi(pf);
11e47708
PN		 5671 }
5672
4e3b35b0
NP		 5673exit:
5674 return ret;
5675}
5676#endif /* CONFIG_I40E_DCB */
5677
23326186
ASJ		 5678/**
5679 * i40e_do_reset_safe - Protected reset path for userland calls.
5680 * @pf: board private structure
5681 * @reset_flags: which reset is requested
5682 *
5683 **/
5684void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
5685{
5686 rtnl_lock();
5687 i40e_do_reset(pf, reset_flags);
5688 rtnl_unlock();
5689}
5690
41c445ff
JB		 5691/**
5692 * i40e_handle_lan_overflow_event - Handler for LAN queue overflow event
5693 * @pf: board private structure
5694 * @e: event info posted on ARQ
5695 *
5696 * Handler for LAN Queue Overflow Event generated by the firmware for PF
5697 * and VF queues
5698 **/
5699static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
5700 struct i40e_arq_event_info *e)
5701{
5702 struct i40e_aqc_lan_overflow *data =
5703 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
5704 u32 queue = le32_to_cpu(data->prtdcb_rupto);
5705 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
5706 struct i40e_hw *hw = &pf->hw;
5707 struct i40e_vf *vf;
5708 u16 vf_id;
5709
69bfb110
JB		 5710 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
5711 queue, qtx_ctl);
41c445ff
JB		 5712
5713 /* Queue belongs to VF, find the VF and issue VF reset */
5714 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
5715 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
5716 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
5717 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
5718 vf_id -= hw->func_caps.vf_base_id;
5719 vf = &pf->vf[vf_id];
5720 i40e_vc_notify_vf_reset(vf);
5721 /* Allow VF to process pending reset notification */
5722 msleep(20);
5723 i40e_reset_vf(vf, false);
5724 }
5725}
5726
5727/**
5728 * i40e_service_event_complete - Finish up the service event
5729 * @pf: board private structure
5730 **/
5731static void i40e_service_event_complete(struct i40e_pf *pf)
5732{
b875f99b 5733 WARN_ON(!test_bit(__I40E_SERVICE_SCHED, &pf->state));
41c445ff
JB		 5734
5735 /* flush memory to make sure state is correct before next watchog */
4e857c58 5736 smp_mb__before_atomic();
41c445ff
JB		 5737 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
5738}
5739
55a5e60b 5740/**
12957388
ASJ		 5741 * i40e_get_cur_guaranteed_fd_count - Get the consumed guaranteed FD filters
5742 * @pf: board private structure
5743 **/
04294e38 5744u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
12957388 5745{
04294e38 5746 u32 val, fcnt_prog;
12957388
ASJ		 5747
5748 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5749 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
5750 return fcnt_prog;
5751}
5752
5753/**
04294e38 5754 * i40e_get_current_fd_count - Get total FD filters programmed for this PF
55a5e60b
ASJ		 5755 * @pf: board private structure
5756 **/
04294e38 5757u32 i40e_get_current_fd_count(struct i40e_pf *pf)
55a5e60b 5758{
04294e38
ASJ		 5759 u32 val, fcnt_prog;
5760
55a5e60b
ASJ		 5761 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
5762 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
5763 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
5764 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
5765 return fcnt_prog;
5766}
1e1be8f6 5767
04294e38
ASJ		 5768/**
5769 * i40e_get_global_fd_count - Get total FD filters programmed on device
5770 * @pf: board private structure
5771 **/
5772u32 i40e_get_global_fd_count(struct i40e_pf *pf)
5773{
5774 u32 val, fcnt_prog;
5775
5776 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
5777 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
5778 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
5779 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
5780 return fcnt_prog;
5781}
5782
55a5e60b
ASJ		 5783/**
5784 * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
5785 * @pf: board private structure
5786 **/
5787void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
5788{
3487b6c3 5789 struct i40e_fdir_filter *filter;
55a5e60b 5790 u32 fcnt_prog, fcnt_avail;
3487b6c3 5791 struct hlist_node *node;
55a5e60b 5792
1e1be8f6
ASJ		 5793 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
5794 return;
5795
55a5e60b
ASJ		 5796 /* Check if, FD SB or ATR was auto disabled and if there is enough room
5797 * to re-enable
5798 */
04294e38 5799 fcnt_prog = i40e_get_global_fd_count(pf);
12957388 5800 fcnt_avail = pf->fdir_pf_filter_count;
1e1be8f6
ASJ		 5801 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
5802 (pf->fd_add_err == 0) ||
5803 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
55a5e60b
ASJ		 5804 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
5805 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
5806 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
2e4875e3
ASJ		 5807 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5808 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5809 }
5810 }
5811 /* Wait for some more space to be available to turn on ATR */
5812 if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM * 2)) {
5813 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
5814 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED)) {
5815 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 5816 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5817 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table now\n");
55a5e60b
ASJ		 5818 }
5819 }
3487b6c3
CW		 5820
5821 /* if hw had a problem adding a filter, delete it */
5822 if (pf->fd_inv > 0) {
5823 hlist_for_each_entry_safe(filter, node,
5824 &pf->fdir_filter_list, fdir_node) {
5825 if (filter->fd_id == pf->fd_inv) {
5826 hlist_del(&filter->fdir_node);
5827 kfree(filter);
5828 pf->fdir_pf_active_filters--;
5829 }
5830 }
5831 }
55a5e60b
ASJ		 5832}
5833
1e1be8f6 5834#define I40E_MIN_FD_FLUSH_INTERVAL 10
04294e38 5835#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
1e1be8f6
ASJ		 5836/**
5837 * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
5838 * @pf: board private structure
5839 **/
5840static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
5841{
04294e38 5842 unsigned long min_flush_time;
1e1be8f6 5843 int flush_wait_retry = 50;
04294e38
ASJ		 5844 bool disable_atr = false;
5845 int fd_room;
1e1be8f6
ASJ		 5846 int reg;
5847
1790ed0c
AA		 5848 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5849 return;
5850
a5fdaf34
JB		 5851 if (!time_after(jiffies, pf->fd_flush_timestamp +
5852 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
5853 return;
04294e38 5854
a5fdaf34
JB		 5855 /* If the flush is happening too quick and we have mostly SB rules we
5856 * should not re-enable ATR for some time.
5857 */
5858 min_flush_time = pf->fd_flush_timestamp +
5859 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
5860 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
5861
5862 if (!(time_after(jiffies, min_flush_time)) &&
5863 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
5864 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5865 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
5866 disable_atr = true;
5867 }
5868
5869 pf->fd_flush_timestamp = jiffies;
5870 pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
5871 /* flush all filters */
5872 wr32(&pf->hw, I40E_PFQF_CTL_1,
5873 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
5874 i40e_flush(&pf->hw);
5875 pf->fd_flush_cnt++;
5876 pf->fd_add_err = 0;
5877 do {
5878 /* Check FD flush status every 5-6msec */
5879 usleep_range(5000, 6000);
5880 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
5881 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
5882 break;
5883 } while (flush_wait_retry--);
5884 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
5885 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
5886 } else {
5887 /* replay sideband filters */
5888 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
5889 if (!disable_atr)
5890 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
5891 clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
5892 if (I40E_DEBUG_FD & pf->hw.debug_mask)
5893 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
1e1be8f6 5894 }
a5fdaf34 5895
1e1be8f6
ASJ		 5896}
5897
5898/**
5899 * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
5900 * @pf: board private structure
5901 **/
04294e38 5902u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
1e1be8f6
ASJ		 5903{
5904 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
5905}
5906
5907/* We can see up to 256 filter programming desc in transit if the filters are
5908 * being applied really fast; before we see the first
5909 * filter miss error on Rx queue 0. Accumulating enough error messages before
5910 * reacting will make sure we don't cause flush too often.
5911 */
5912#define I40E_MAX_FD_PROGRAM_ERROR 256
5913
41c445ff
JB		 5914/**
5915 * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
5916 * @pf: board private structure
5917 **/
5918static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
5919{
41c445ff 5920
41c445ff
JB		 5921 /* if interface is down do nothing */
5922 if (test_bit(__I40E_DOWN, &pf->state))
5923 return;
1e1be8f6 5924
1790ed0c
AA		 5925 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED)))
5926 return;
5927
04294e38 5928 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
1e1be8f6
ASJ		 5929 i40e_fdir_flush_and_replay(pf);
5930
55a5e60b
ASJ		 5931 i40e_fdir_check_and_reenable(pf);
5932
41c445ff
JB		 5933}
5934
5935/**
5936 * i40e_vsi_link_event - notify VSI of a link event
5937 * @vsi: vsi to be notified
5938 * @link_up: link up or down
5939 **/
5940static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
5941{
32b5b811 5942 if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
41c445ff
JB		 5943 return;
5944
5945 switch (vsi->type) {
5946 case I40E_VSI_MAIN:
38e00438
VD		 5947#ifdef I40E_FCOE
5948 case I40E_VSI_FCOE:
5949#endif
41c445ff
JB		 5950 if (!vsi->netdev || !vsi->netdev_registered)
5951 break;
5952
5953 if (link_up) {
5954 netif_carrier_on(vsi->netdev);
5955 netif_tx_wake_all_queues(vsi->netdev);
5956 } else {
5957 netif_carrier_off(vsi->netdev);
5958 netif_tx_stop_all_queues(vsi->netdev);
5959 }
5960 break;
5961
5962 case I40E_VSI_SRIOV:
41c445ff
JB		 5963 case I40E_VSI_VMDQ2:
5964 case I40E_VSI_CTRL:
5965 case I40E_VSI_MIRROR:
5966 default:
5967 /* there is no notification for other VSIs */
5968 break;
5969 }
5970}
5971
5972/**
5973 * i40e_veb_link_event - notify elements on the veb of a link event
5974 * @veb: veb to be notified
5975 * @link_up: link up or down
5976 **/
5977static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
5978{
5979 struct i40e_pf *pf;
5980 int i;
5981
5982 if (!veb || !veb->pf)
5983 return;
5984 pf = veb->pf;
5985
5986 /* depth first... */
5987 for (i = 0; i < I40E_MAX_VEB; i++)
5988 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
5989 i40e_veb_link_event(pf->veb[i], link_up);
5990
5991 /* ... now the local VSIs */
505682cd 5992 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 5993 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
5994 i40e_vsi_link_event(pf->vsi[i], link_up);
5995}
5996
5997/**
5998 * i40e_link_event - Update netif_carrier status
5999 * @pf: board private structure
6000 **/
6001static void i40e_link_event(struct i40e_pf *pf)
6002{
320684cd 6003 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
fef59ddf 6004 u8 new_link_speed, old_link_speed;
a72a5abc
JB		 6005 i40e_status status;
6006 bool new_link, old_link;
41c445ff 6007
1f9610e4
CS		 6008 /* save off old link status information */
6009 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
6010
1e701e09
JB		 6011 /* set this to force the get_link_status call to refresh state */
6012 pf->hw.phy.get_link_info = true;
6013
41c445ff 6014 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
a72a5abc
JB		 6015
6016 status = i40e_get_link_status(&pf->hw, &new_link);
6017 if (status) {
6018 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
6019 status);
6020 return;
6021 }
6022
fef59ddf
CS		 6023 old_link_speed = pf->hw.phy.link_info_old.link_speed;
6024 new_link_speed = pf->hw.phy.link_info.link_speed;
41c445ff 6025
1e701e09 6026 if (new_link == old_link &&
fef59ddf 6027 new_link_speed == old_link_speed &&
320684cd
MW		 6028 (test_bit(__I40E_DOWN, &vsi->state) ||
6029 new_link == netif_carrier_ok(vsi->netdev)))
41c445ff 6030 return;
320684cd
MW		 6031
6032 if (!test_bit(__I40E_DOWN, &vsi->state))
6033 i40e_print_link_message(vsi, new_link);
41c445ff
JB		 6034
6035 /* Notify the base of the switch tree connected to
6036 * the link. Floating VEBs are not notified.
6037 */
6038 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
6039 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
6040 else
320684cd 6041 i40e_vsi_link_event(vsi, new_link);
41c445ff
JB		 6042
6043 if (pf->vf)
6044 i40e_vc_notify_link_state(pf);
beb0dff1
JK		 6045
6046 if (pf->flags & I40E_FLAG_PTP)
6047 i40e_ptp_set_increment(pf);
41c445ff
JB		 6048}
6049
41c445ff 6050/**
21536717 6051 * i40e_watchdog_subtask - periodic checks not using event driven response
41c445ff
JB		 6052 * @pf: board private structure
6053 **/
6054static void i40e_watchdog_subtask(struct i40e_pf *pf)
6055{
6056 int i;
6057
6058 /* if interface is down do nothing */
6059 if (test_bit(__I40E_DOWN, &pf->state) ||
6060 test_bit(__I40E_CONFIG_BUSY, &pf->state))
6061 return;
6062
21536717
SN		 6063 /* make sure we don't do these things too often */
6064 if (time_before(jiffies, (pf->service_timer_previous +
6065 pf->service_timer_period)))
6066 return;
6067 pf->service_timer_previous = jiffies;
6068
9ac77266
SN		 6069 if (pf->flags & I40E_FLAG_LINK_POLLING_ENABLED)
6070 i40e_link_event(pf);
21536717 6071
41c445ff
JB		 6072 /* Update the stats for active netdevs so the network stack
6073 * can look at updated numbers whenever it cares to
6074 */
505682cd 6075 for (i = 0; i < pf->num_alloc_vsi; i++)
41c445ff
JB		 6076 if (pf->vsi[i] && pf->vsi[i]->netdev)
6077 i40e_update_stats(pf->vsi[i]);
6078
d1a8d275
ASJ		 6079 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
6080 /* Update the stats for the active switching components */
6081 for (i = 0; i < I40E_MAX_VEB; i++)
6082 if (pf->veb[i])
6083 i40e_update_veb_stats(pf->veb[i]);
6084 }
beb0dff1
JK		 6085
6086 i40e_ptp_rx_hang(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 6087}
6088
6089/**
6090 * i40e_reset_subtask - Set up for resetting the device and driver
6091 * @pf: board private structure
6092 **/
6093static void i40e_reset_subtask(struct i40e_pf *pf)
6094{
6095 u32 reset_flags = 0;
6096
23326186 6097 rtnl_lock();
41c445ff 6098 if (test_bit(__I40E_REINIT_REQUESTED, &pf->state)) {
41a1d04b 6099 reset_flags |= BIT_ULL(__I40E_REINIT_REQUESTED);
41c445ff
JB		 6100 clear_bit(__I40E_REINIT_REQUESTED, &pf->state);
6101 }
6102 if (test_bit(__I40E_PF_RESET_REQUESTED, &pf->state)) {
41a1d04b 6103 reset_flags |= BIT_ULL(__I40E_PF_RESET_REQUESTED);
41c445ff
JB		 6104 clear_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6105 }
6106 if (test_bit(__I40E_CORE_RESET_REQUESTED, &pf->state)) {
41a1d04b 6107 reset_flags |= BIT_ULL(__I40E_CORE_RESET_REQUESTED);
41c445ff
JB		 6108 clear_bit(__I40E_CORE_RESET_REQUESTED, &pf->state);
6109 }
6110 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state)) {
41a1d04b 6111 reset_flags |= BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED);
41c445ff
JB		 6112 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, &pf->state);
6113 }
b5d06f05 6114 if (test_bit(__I40E_DOWN_REQUESTED, &pf->state)) {
41a1d04b 6115 reset_flags |= BIT_ULL(__I40E_DOWN_REQUESTED);
b5d06f05
NP		 6116 clear_bit(__I40E_DOWN_REQUESTED, &pf->state);
6117 }
41c445ff
JB		 6118
6119 /* If there's a recovery already waiting, it takes
6120 * precedence before starting a new reset sequence.
6121 */
6122 if (test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state)) {
6123 i40e_handle_reset_warning(pf);
23326186 6124 goto unlock;
41c445ff
JB		 6125 }
6126
6127 /* If we're already down or resetting, just bail */
6128 if (reset_flags &&
6129 !test_bit(__I40E_DOWN, &pf->state) &&
6130 !test_bit(__I40E_CONFIG_BUSY, &pf->state))
6131 i40e_do_reset(pf, reset_flags);
23326186
ASJ		 6132
6133unlock:
6134 rtnl_unlock();
41c445ff
JB		 6135}
6136
6137/**
6138 * i40e_handle_link_event - Handle link event
6139 * @pf: board private structure
6140 * @e: event info posted on ARQ
6141 **/
6142static void i40e_handle_link_event(struct i40e_pf *pf,
6143 struct i40e_arq_event_info *e)
6144{
41c445ff
JB		 6145 struct i40e_aqc_get_link_status *status =
6146 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
41c445ff 6147
1e701e09
JB		 6148 /* Do a new status request to re-enable LSE reporting
6149 * and load new status information into the hw struct
6150 * This completely ignores any state information
6151 * in the ARQ event info, instead choosing to always
6152 * issue the AQ update link status command.
6153 */
6154 i40e_link_event(pf);
6155
7b592f61
CW		 6156 /* check for unqualified module, if link is down */
6157 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
6158 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
6159 (!(status->link_info & I40E_AQ_LINK_UP)))
6160 dev_err(&pf->pdev->dev,
6161 "The driver failed to link because an unqualified module was detected.\n");
41c445ff
JB		 6162}
6163
6164/**
6165 * i40e_clean_adminq_subtask - Clean the AdminQ rings
6166 * @pf: board private structure
6167 **/
6168static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
6169{
6170 struct i40e_arq_event_info event;
6171 struct i40e_hw *hw = &pf->hw;
6172 u16 pending, i = 0;
6173 i40e_status ret;
6174 u16 opcode;
86df242b 6175 u32 oldval;
41c445ff
JB		 6176 u32 val;
6177
a316f651
ASJ		 6178 /* Do not run clean AQ when PF reset fails */
6179 if (test_bit(__I40E_RESET_FAILED, &pf->state))
6180 return;
6181
86df242b
SN		 6182 /* check for error indications */
6183 val = rd32(&pf->hw, pf->hw.aq.arq.len);
6184 oldval = val;
6185 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
6186 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
6187 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
6188 }
6189 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
6190 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
6191 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
6192 }
6193 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
6194 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
6195 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
6196 }
6197 if (oldval != val)
6198 wr32(&pf->hw, pf->hw.aq.arq.len, val);
6199
6200 val = rd32(&pf->hw, pf->hw.aq.asq.len);
6201 oldval = val;
6202 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
6203 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
6204 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
6205 }
6206 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
6207 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
6208 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
6209 }
6210 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
6211 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
6212 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
6213 }
6214 if (oldval != val)
6215 wr32(&pf->hw, pf->hw.aq.asq.len, val);
6216
1001dc37
MW		 6217 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
6218 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
41c445ff
JB		 6219 if (!event.msg_buf)
6220 return;
6221
6222 do {
6223 ret = i40e_clean_arq_element(hw, &event, &pending);
56497978 6224 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
41c445ff 6225 break;
56497978 6226 else if (ret) {
41c445ff
JB		 6227 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
6228 break;
6229 }
6230
6231 opcode = le16_to_cpu(event.desc.opcode);
6232 switch (opcode) {
6233
6234 case i40e_aqc_opc_get_link_status:
6235 i40e_handle_link_event(pf, &event);
6236 break;
6237 case i40e_aqc_opc_send_msg_to_pf:
6238 ret = i40e_vc_process_vf_msg(pf,
6239 le16_to_cpu(event.desc.retval),
6240 le32_to_cpu(event.desc.cookie_high),
6241 le32_to_cpu(event.desc.cookie_low),
6242 event.msg_buf,
1001dc37 6243 event.msg_len);
41c445ff
JB		 6244 break;
6245 case i40e_aqc_opc_lldp_update_mib:
69bfb110 6246 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
4e3b35b0
NP		 6247#ifdef CONFIG_I40E_DCB
6248 rtnl_lock();
6249 ret = i40e_handle_lldp_event(pf, &event);
6250 rtnl_unlock();
6251#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 6252 break;
6253 case i40e_aqc_opc_event_lan_overflow:
69bfb110 6254 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
41c445ff
JB		 6255 i40e_handle_lan_overflow_event(pf, &event);
6256 break;
0467bc91
SN		 6257 case i40e_aqc_opc_send_msg_to_peer:
6258 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
6259 break;
91a0f930
SN		 6260 case i40e_aqc_opc_nvm_erase:
6261 case i40e_aqc_opc_nvm_update:
6262 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "ARQ NVM operation completed\n");
6263 break;
41c445ff
JB		 6264 default:
6265 dev_info(&pf->pdev->dev,
0467bc91
SN		 6266 "ARQ Error: Unknown event 0x%04x received\n",
6267 opcode);
41c445ff
JB		 6268 break;
6269 }
6270 } while (pending && (i++ < pf->adminq_work_limit));
6271
6272 clear_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state);
6273 /* re-enable Admin queue interrupt cause */
6274 val = rd32(hw, I40E_PFINT_ICR0_ENA);
6275 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
6276 wr32(hw, I40E_PFINT_ICR0_ENA, val);
6277 i40e_flush(hw);
6278
6279 kfree(event.msg_buf);
6280}
6281
4eb3f768
SN		 6282/**
6283 * i40e_verify_eeprom - make sure eeprom is good to use
6284 * @pf: board private structure
6285 **/
6286static void i40e_verify_eeprom(struct i40e_pf *pf)
6287{
6288 int err;
6289
6290 err = i40e_diag_eeprom_test(&pf->hw);
6291 if (err) {
6292 /* retry in case of garbage read */
6293 err = i40e_diag_eeprom_test(&pf->hw);
6294 if (err) {
6295 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
6296 err);
6297 set_bit(__I40E_BAD_EEPROM, &pf->state);
6298 }
6299 }
6300
6301 if (!err && test_bit(__I40E_BAD_EEPROM, &pf->state)) {
6302 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
6303 clear_bit(__I40E_BAD_EEPROM, &pf->state);
6304 }
6305}
6306
386a0afa
AA		 6307/**
6308 * i40e_enable_pf_switch_lb
b40c82e6 6309 * @pf: pointer to the PF structure
386a0afa
AA		 6310 *
6311 * enable switch loop back or die - no point in a return value
6312 **/
6313static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
6314{
6315 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6316 struct i40e_vsi_context ctxt;
f1c7e72e 6317 int ret;
386a0afa
AA		 6318
6319 ctxt.seid = pf->main_vsi_seid;
6320 ctxt.pf_num = pf->hw.pf_id;
6321 ctxt.vf_num = 0;
f1c7e72e
SN		 6322 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6323 if (ret) {
386a0afa 6324 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6325 "couldn't get PF vsi config, err %s aq_err %s\n",
6326 i40e_stat_str(&pf->hw, ret),
6327 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6328 return;
6329 }
6330 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6331 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6332 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6333
f1c7e72e
SN		 6334 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6335 if (ret) {
386a0afa 6336 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6337 "update vsi switch failed, err %s aq_err %s\n",
6338 i40e_stat_str(&pf->hw, ret),
6339 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6340 }
6341}
6342
6343/**
6344 * i40e_disable_pf_switch_lb
b40c82e6 6345 * @pf: pointer to the PF structure
386a0afa
AA		 6346 *
6347 * disable switch loop back or die - no point in a return value
6348 **/
6349static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
6350{
6351 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
6352 struct i40e_vsi_context ctxt;
f1c7e72e 6353 int ret;
386a0afa
AA		 6354
6355 ctxt.seid = pf->main_vsi_seid;
6356 ctxt.pf_num = pf->hw.pf_id;
6357 ctxt.vf_num = 0;
f1c7e72e
SN		 6358 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
6359 if (ret) {
386a0afa 6360 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6361 "couldn't get PF vsi config, err %s aq_err %s\n",
6362 i40e_stat_str(&pf->hw, ret),
6363 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6364 return;
6365 }
6366 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
6367 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
6368 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
6369
f1c7e72e
SN		 6370 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
6371 if (ret) {
386a0afa 6372 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6373 "update vsi switch failed, err %s aq_err %s\n",
6374 i40e_stat_str(&pf->hw, ret),
6375 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
386a0afa
AA		 6376 }
6377}
6378
51616018
NP		 6379/**
6380 * i40e_config_bridge_mode - Configure the HW bridge mode
6381 * @veb: pointer to the bridge instance
6382 *
6383 * Configure the loop back mode for the LAN VSI that is downlink to the
6384 * specified HW bridge instance. It is expected this function is called
6385 * when a new HW bridge is instantiated.
6386 **/
6387static void i40e_config_bridge_mode(struct i40e_veb *veb)
6388{
6389 struct i40e_pf *pf = veb->pf;
6390
6dec1017
SN		 6391 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
6392 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
6393 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
51616018
NP		 6394 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
6395 i40e_disable_pf_switch_lb(pf);
6396 else
6397 i40e_enable_pf_switch_lb(pf);
6398}
6399
41c445ff
JB		 6400/**
6401 * i40e_reconstitute_veb - rebuild the VEB and anything connected to it
6402 * @veb: pointer to the VEB instance
6403 *
6404 * This is a recursive function that first builds the attached VSIs then
6405 * recurses in to build the next layer of VEB. We track the connections
6406 * through our own index numbers because the seid's from the HW could
6407 * change across the reset.
6408 **/
6409static int i40e_reconstitute_veb(struct i40e_veb *veb)
6410{
6411 struct i40e_vsi *ctl_vsi = NULL;
6412 struct i40e_pf *pf = veb->pf;
6413 int v, veb_idx;
6414 int ret;
6415
6416 /* build VSI that owns this VEB, temporarily attached to base VEB */
505682cd 6417 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
41c445ff
JB		 6418 if (pf->vsi[v] &&
6419 pf->vsi[v]->veb_idx == veb->idx &&
6420 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
6421 ctl_vsi = pf->vsi[v];
6422 break;
6423 }
6424 }
6425 if (!ctl_vsi) {
6426 dev_info(&pf->pdev->dev,
6427 "missing owner VSI for veb_idx %d\n", veb->idx);
6428 ret = -ENOENT;
6429 goto end_reconstitute;
6430 }
6431 if (ctl_vsi != pf->vsi[pf->lan_vsi])
6432 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
6433 ret = i40e_add_vsi(ctl_vsi);
6434 if (ret) {
6435 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6436 "rebuild of veb_idx %d owner VSI failed: %d\n",
6437 veb->idx, ret);
41c445ff
JB		 6438 goto end_reconstitute;
6439 }
6440 i40e_vsi_reset_stats(ctl_vsi);
6441
6442 /* create the VEB in the switch and move the VSI onto the VEB */
6443 ret = i40e_add_veb(veb, ctl_vsi);
6444 if (ret)
6445 goto end_reconstitute;
6446
fc60861e
ASJ		 6447 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
6448 veb->bridge_mode = BRIDGE_MODE_VEB;
6449 else
6450 veb->bridge_mode = BRIDGE_MODE_VEPA;
51616018 6451 i40e_config_bridge_mode(veb);
b64ba084 6452
41c445ff 6453 /* create the remaining VSIs attached to this VEB */
505682cd 6454 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6455 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
6456 continue;
6457
6458 if (pf->vsi[v]->veb_idx == veb->idx) {
6459 struct i40e_vsi *vsi = pf->vsi[v];
6995b36c 6460
41c445ff
JB		 6461 vsi->uplink_seid = veb->seid;
6462 ret = i40e_add_vsi(vsi);
6463 if (ret) {
6464 dev_info(&pf->pdev->dev,
6465 "rebuild of vsi_idx %d failed: %d\n",
6466 v, ret);
6467 goto end_reconstitute;
6468 }
6469 i40e_vsi_reset_stats(vsi);
6470 }
6471 }
6472
6473 /* create any VEBs attached to this VEB - RECURSION */
6474 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
6475 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
6476 pf->veb[veb_idx]->uplink_seid = veb->seid;
6477 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
6478 if (ret)
6479 break;
6480 }
6481 }
6482
6483end_reconstitute:
6484 return ret;
6485}
6486
6487/**
6488 * i40e_get_capabilities - get info about the HW
6489 * @pf: the PF struct
6490 **/
6491static int i40e_get_capabilities(struct i40e_pf *pf)
6492{
6493 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
6494 u16 data_size;
6495 int buf_len;
6496 int err;
6497
6498 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
6499 do {
6500 cap_buf = kzalloc(buf_len, GFP_KERNEL);
6501 if (!cap_buf)
6502 return -ENOMEM;
6503
6504 /* this loads the data into the hw struct for us */
6505 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
6506 &data_size,
6507 i40e_aqc_opc_list_func_capabilities,
6508 NULL);
6509 /* data loaded, buffer no longer needed */
6510 kfree(cap_buf);
6511
6512 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
6513 /* retry with a larger buffer */
6514 buf_len = data_size;
6515 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
6516 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 6517 "capability discovery failed, err %s aq_err %s\n",
6518 i40e_stat_str(&pf->hw, err),
6519 i40e_aq_str(&pf->hw,
6520 pf->hw.aq.asq_last_status));
41c445ff
JB		 6521 return -ENODEV;
6522 }
6523 } while (err);
6524
6525 if (pf->hw.debug_mask & I40E_DEBUG_USER)
6526 dev_info(&pf->pdev->dev,
6527 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
6528 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
6529 pf->hw.func_caps.num_msix_vectors,
6530 pf->hw.func_caps.num_msix_vectors_vf,
6531 pf->hw.func_caps.fd_filters_guaranteed,
6532 pf->hw.func_caps.fd_filters_best_effort,
6533 pf->hw.func_caps.num_tx_qp,
6534 pf->hw.func_caps.num_vsis);
6535
7134f9ce
JB		 6536#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
6537 + pf->hw.func_caps.num_vfs)
6538 if (pf->hw.revision_id == 0 && (DEF_NUM_VSI > pf->hw.func_caps.num_vsis)) {
6539 dev_info(&pf->pdev->dev,
6540 "got num_vsis %d, setting num_vsis to %d\n",
6541 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
6542 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
6543 }
6544
41c445ff
JB		 6545 return 0;
6546}
6547
cbf61325
ASJ		 6548static int i40e_vsi_clear(struct i40e_vsi *vsi);
6549
41c445ff 6550/**
cbf61325 6551 * i40e_fdir_sb_setup - initialize the Flow Director resources for Sideband
41c445ff
JB		 6552 * @pf: board private structure
6553 **/
cbf61325 6554static void i40e_fdir_sb_setup(struct i40e_pf *pf)
41c445ff
JB		 6555{
6556 struct i40e_vsi *vsi;
8a9eb7d3 6557 int i;
41c445ff 6558
407e063c
JB		 6559 /* quick workaround for an NVM issue that leaves a critical register
6560 * uninitialized
6561 */
6562 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
6563 static const u32 hkey[] = {
6564 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
6565 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
6566 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
6567 0x95b3a76d};
6568
6569 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
6570 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
6571 }
6572
cbf61325 6573 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
41c445ff
JB		 6574 return;
6575
cbf61325 6576 /* find existing VSI and see if it needs configuring */
41c445ff 6577 vsi = NULL;
505682cd 6578 for (i = 0; i < pf->num_alloc_vsi; i++) {
cbf61325 6579 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
41c445ff 6580 vsi = pf->vsi[i];
cbf61325
ASJ		 6581 break;
6582 }
6583 }
6584
6585 /* create a new VSI if none exists */
41c445ff 6586 if (!vsi) {
cbf61325
ASJ		 6587 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
6588 pf->vsi[pf->lan_vsi]->seid, 0);
41c445ff
JB		 6589 if (!vsi) {
6590 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
8a9eb7d3
SN		 6591 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
6592 return;
41c445ff 6593 }
cbf61325 6594 }
41c445ff 6595
8a9eb7d3 6596 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
41c445ff
JB		 6597}
6598
6599/**
6600 * i40e_fdir_teardown - release the Flow Director resources
6601 * @pf: board private structure
6602 **/
6603static void i40e_fdir_teardown(struct i40e_pf *pf)
6604{
6605 int i;
6606
17a73f6b 6607 i40e_fdir_filter_exit(pf);
505682cd 6608 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 6609 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
6610 i40e_vsi_release(pf->vsi[i]);
6611 break;
6612 }
6613 }
6614}
6615
6616/**
f650a38b 6617 * i40e_prep_for_reset - prep for the core to reset
41c445ff
JB		 6618 * @pf: board private structure
6619 *
b40c82e6 6620 * Close up the VFs and other things in prep for PF Reset.
f650a38b 6621 **/
23cfbe07 6622static void i40e_prep_for_reset(struct i40e_pf *pf)
41c445ff 6623{
41c445ff 6624 struct i40e_hw *hw = &pf->hw;
60442dea 6625 i40e_status ret = 0;
41c445ff
JB		 6626 u32 v;
6627
6628 clear_bit(__I40E_RESET_INTR_RECEIVED, &pf->state);
6629 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state))
23cfbe07 6630 return;
41c445ff 6631
69bfb110 6632 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
41c445ff 6633
41c445ff
JB		 6634 /* quiesce the VSIs and their queues that are not already DOWN */
6635 i40e_pf_quiesce_all_vsi(pf);
6636
505682cd 6637 for (v = 0; v < pf->num_alloc_vsi; v++) {
41c445ff
JB		 6638 if (pf->vsi[v])
6639 pf->vsi[v]->seid = 0;
6640 }
6641
6642 i40e_shutdown_adminq(&pf->hw);
6643
f650a38b 6644 /* call shutdown HMC */
60442dea
SN		 6645 if (hw->hmc.hmc_obj) {
6646 ret = i40e_shutdown_lan_hmc(hw);
23cfbe07 6647 if (ret)
60442dea
SN		 6648 dev_warn(&pf->pdev->dev,
6649 "shutdown_lan_hmc failed: %d\n", ret);
f650a38b 6650 }
f650a38b
ASJ		 6651}
6652
44033fac
JB		 6653/**
6654 * i40e_send_version - update firmware with driver version
6655 * @pf: PF struct
6656 */
6657static void i40e_send_version(struct i40e_pf *pf)
6658{
6659 struct i40e_driver_version dv;
6660
6661 dv.major_version = DRV_VERSION_MAJOR;
6662 dv.minor_version = DRV_VERSION_MINOR;
6663 dv.build_version = DRV_VERSION_BUILD;
6664 dv.subbuild_version = 0;
35a7d804 6665 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
44033fac
JB		 6666 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
6667}
6668
f650a38b 6669/**
4dda12e6 6670 * i40e_reset_and_rebuild - reset and rebuild using a saved config
f650a38b 6671 * @pf: board private structure
bc7d338f 6672 * @reinit: if the Main VSI needs to re-initialized.
f650a38b 6673 **/
bc7d338f 6674static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
f650a38b 6675{
f650a38b 6676 struct i40e_hw *hw = &pf->hw;
cafa2ee6 6677 u8 set_fc_aq_fail = 0;
f650a38b 6678 i40e_status ret;
4f2f017c 6679 u32 val;
f650a38b
ASJ		 6680 u32 v;
6681
41c445ff
JB		 6682 /* Now we wait for GRST to settle out.
6683 * We don't have to delete the VEBs or VSIs from the hw switch
6684 * because the reset will make them disappear.
6685 */
6686 ret = i40e_pf_reset(hw);
b5565400 6687 if (ret) {
41c445ff 6688 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
a316f651
ASJ		 6689 set_bit(__I40E_RESET_FAILED, &pf->state);
6690 goto clear_recovery;
b5565400 6691 }
41c445ff
JB		 6692 pf->pfr_count++;
6693
6694 if (test_bit(__I40E_DOWN, &pf->state))
a316f651 6695 goto clear_recovery;
69bfb110 6696 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
41c445ff
JB		 6697
6698 /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
6699 ret = i40e_init_adminq(&pf->hw);
6700 if (ret) {
f1c7e72e
SN		 6701 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
6702 i40e_stat_str(&pf->hw, ret),
6703 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
a316f651 6704 goto clear_recovery;
41c445ff
JB		 6705 }
6706
4eb3f768 6707 /* re-verify the eeprom if we just had an EMP reset */
9df42d1a 6708 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, &pf->state))
4eb3f768 6709 i40e_verify_eeprom(pf);
4eb3f768 6710
e78ac4bf 6711 i40e_clear_pxe_mode(hw);
41c445ff 6712 ret = i40e_get_capabilities(pf);
f1c7e72e 6713 if (ret)
41c445ff 6714 goto end_core_reset;
41c445ff 6715
41c445ff
JB		 6716 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
6717 hw->func_caps.num_rx_qp,
6718 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
6719 if (ret) {
6720 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
6721 goto end_core_reset;
6722 }
6723 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
6724 if (ret) {
6725 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
6726 goto end_core_reset;
6727 }
6728
4e3b35b0
NP		 6729#ifdef CONFIG_I40E_DCB
6730 ret = i40e_init_pf_dcb(pf);
6731 if (ret) {
aebfc816
SN		 6732 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
6733 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
6734 /* Continue without DCB enabled */
4e3b35b0
NP		 6735 }
6736#endif /* CONFIG_I40E_DCB */
38e00438 6737#ifdef I40E_FCOE
21364bcf 6738 i40e_init_pf_fcoe(pf);
4e3b35b0 6739
38e00438 6740#endif
41c445ff 6741 /* do basic switch setup */
bc7d338f 6742 ret = i40e_setup_pf_switch(pf, reinit);
41c445ff
JB		 6743 if (ret)
6744 goto end_core_reset;
6745
7e2453fe
JB		 6746 /* driver is only interested in link up/down and module qualification
6747 * reports from firmware
6748 */
6749 ret = i40e_aq_set_phy_int_mask(&pf->hw,
6750 I40E_AQ_EVENT_LINK_UPDOWN |
6751 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
6752 if (ret)
f1c7e72e
SN		 6753 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
6754 i40e_stat_str(&pf->hw, ret),
6755 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 6756
cafa2ee6
ASJ		 6757 /* make sure our flow control settings are restored */
6758 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
6759 if (ret)
8279e495
NP		 6760 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
6761 i40e_stat_str(&pf->hw, ret),
6762 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
cafa2ee6 6763
41c445ff
JB		 6764 /* Rebuild the VSIs and VEBs that existed before reset.
6765 * They are still in our local switch element arrays, so only
6766 * need to rebuild the switch model in the HW.
6767 *
6768 * If there were VEBs but the reconstitution failed, we'll try
6769 * try to recover minimal use by getting the basic PF VSI working.
6770 */
6771 if (pf->vsi[pf->lan_vsi]->uplink_seid != pf->mac_seid) {
69bfb110 6772 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
41c445ff
JB		 6773 /* find the one VEB connected to the MAC, and find orphans */
6774 for (v = 0; v < I40E_MAX_VEB; v++) {
6775 if (!pf->veb[v])
6776 continue;
6777
6778 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
6779 pf->veb[v]->uplink_seid == 0) {
6780 ret = i40e_reconstitute_veb(pf->veb[v]);
6781
6782 if (!ret)
6783 continue;
6784
6785 /* If Main VEB failed, we're in deep doodoo,
6786 * so give up rebuilding the switch and set up
6787 * for minimal rebuild of PF VSI.
6788 * If orphan failed, we'll report the error
6789 * but try to keep going.
6790 */
6791 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
6792 dev_info(&pf->pdev->dev,
6793 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
6794 ret);
6795 pf->vsi[pf->lan_vsi]->uplink_seid
6796 = pf->mac_seid;
6797 break;
6798 } else if (pf->veb[v]->uplink_seid == 0) {
6799 dev_info(&pf->pdev->dev,
6800 "rebuild of orphan VEB failed: %d\n",
6801 ret);
6802 }
6803 }
6804 }
6805 }
6806
6807 if (pf->vsi[pf->lan_vsi]->uplink_seid == pf->mac_seid) {
cde4cbc7 6808 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
41c445ff
JB		 6809 /* no VEB, so rebuild only the Main VSI */
6810 ret = i40e_add_vsi(pf->vsi[pf->lan_vsi]);
6811 if (ret) {
6812 dev_info(&pf->pdev->dev,
6813 "rebuild of Main VSI failed: %d\n", ret);
6814 goto end_core_reset;
6815 }
6816 }
6817
4f2f017c
ASJ		 6818 /* Reconfigure hardware for allowing smaller MSS in the case
6819 * of TSO, so that we avoid the MDD being fired and causing
6820 * a reset in the case of small MSS+TSO.
6821 */
6822#define I40E_REG_MSS 0x000E64DC
6823#define I40E_REG_MSS_MIN_MASK 0x3FF0000
6824#define I40E_64BYTE_MSS 0x400000
6825 val = rd32(hw, I40E_REG_MSS);
6826 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
6827 val &= ~I40E_REG_MSS_MIN_MASK;
6828 val |= I40E_64BYTE_MSS;
6829 wr32(hw, I40E_REG_MSS, val);
6830 }
6831
025b4a54
ASJ		 6832 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
6833 (pf->hw.aq.fw_maj_ver < 4)) {
6834 msleep(75);
6835 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
6836 if (ret)
f1c7e72e
SN		 6837 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
6838 i40e_stat_str(&pf->hw, ret),
6839 i40e_aq_str(&pf->hw,
6840 pf->hw.aq.asq_last_status));
cafa2ee6 6841 }
41c445ff
JB		 6842 /* reinit the misc interrupt */
6843 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6844 ret = i40e_setup_misc_vector(pf);
6845
e7358f54
ASJ		 6846 /* Add a filter to drop all Flow control frames from any VSI from being
6847 * transmitted. By doing so we stop a malicious VF from sending out
6848 * PAUSE or PFC frames and potentially controlling traffic for other
6849 * PF/VF VSIs.
6850 * The FW can still send Flow control frames if enabled.
6851 */
6852 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
6853 pf->main_vsi_seid);
6854
41c445ff
JB		 6855 /* restart the VSIs that were rebuilt and running before the reset */
6856 i40e_pf_unquiesce_all_vsi(pf);
6857
69f64b2b
MW		 6858 if (pf->num_alloc_vfs) {
6859 for (v = 0; v < pf->num_alloc_vfs; v++)
6860 i40e_reset_vf(&pf->vf[v], true);
6861 }
6862
41c445ff 6863 /* tell the firmware that we're starting */
44033fac 6864 i40e_send_version(pf);
41c445ff
JB		 6865
6866end_core_reset:
a316f651
ASJ		 6867 clear_bit(__I40E_RESET_FAILED, &pf->state);
6868clear_recovery:
41c445ff
JB		 6869 clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
6870}
6871
f650a38b 6872/**
b40c82e6 6873 * i40e_handle_reset_warning - prep for the PF to reset, reset and rebuild
f650a38b
ASJ		 6874 * @pf: board private structure
6875 *
6876 * Close up the VFs and other things in prep for a Core Reset,
6877 * then get ready to rebuild the world.
6878 **/
6879static void i40e_handle_reset_warning(struct i40e_pf *pf)
6880{
23cfbe07
SN		 6881 i40e_prep_for_reset(pf);
6882 i40e_reset_and_rebuild(pf, false);
f650a38b
ASJ		 6883}
6884
41c445ff
JB		 6885/**
6886 * i40e_handle_mdd_event
b40c82e6 6887 * @pf: pointer to the PF structure
41c445ff
JB		 6888 *
6889 * Called from the MDD irq handler to identify possibly malicious vfs
6890 **/
6891static void i40e_handle_mdd_event(struct i40e_pf *pf)
6892{
6893 struct i40e_hw *hw = &pf->hw;
6894 bool mdd_detected = false;
df430b12 6895 bool pf_mdd_detected = false;
41c445ff
JB		 6896 struct i40e_vf *vf;
6897 u32 reg;
6898 int i;
6899
6900 if (!test_bit(__I40E_MDD_EVENT_PENDING, &pf->state))
6901 return;
6902
6903 /* find what triggered the MDD event */
6904 reg = rd32(hw, I40E_GL_MDET_TX);
6905 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
4c33f83a
ASJ		 6906 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6907 I40E_GL_MDET_TX_PF_NUM_SHIFT;
2089ad03 6908 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
4c33f83a 6909 I40E_GL_MDET_TX_VF_NUM_SHIFT;
013f6579 6910 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
4c33f83a 6911 I40E_GL_MDET_TX_EVENT_SHIFT;
2089ad03
MW		 6912 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6913 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6914 pf->hw.func_caps.base_queue;
faf32978 6915 if (netif_msg_tx_err(pf))
b40c82e6 6916 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
faf32978 6917 event, queue, pf_num, vf_num);
41c445ff
JB		 6918 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
6919 mdd_detected = true;
6920 }
6921 reg = rd32(hw, I40E_GL_MDET_RX);
6922 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
4c33f83a
ASJ		 6923 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6924 I40E_GL_MDET_RX_FUNCTION_SHIFT;
013f6579 6925 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
4c33f83a 6926 I40E_GL_MDET_RX_EVENT_SHIFT;
2089ad03
MW		 6927 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6928 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6929 pf->hw.func_caps.base_queue;
faf32978
JB		 6930 if (netif_msg_rx_err(pf))
6931 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
6932 event, queue, func);
41c445ff
JB		 6933 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
6934 mdd_detected = true;
6935 }
6936
df430b12
NP		 6937 if (mdd_detected) {
6938 reg = rd32(hw, I40E_PF_MDET_TX);
6939 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6940 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
faf32978 6941 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
df430b12
NP		 6942 pf_mdd_detected = true;
6943 }
6944 reg = rd32(hw, I40E_PF_MDET_RX);
6945 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6946 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
faf32978 6947 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
df430b12
NP		 6948 pf_mdd_detected = true;
6949 }
6950 /* Queue belongs to the PF, initiate a reset */
6951 if (pf_mdd_detected) {
6952 set_bit(__I40E_PF_RESET_REQUESTED, &pf->state);
6953 i40e_service_event_schedule(pf);
6954 }
6955 }
6956
41c445ff
JB		 6957 /* see if one of the VFs needs its hand slapped */
6958 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
6959 vf = &(pf->vf[i]);
6960 reg = rd32(hw, I40E_VP_MDET_TX(i));
6961 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6962 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
6963 vf->num_mdd_events++;
faf32978
JB		 6964 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
6965 i);
41c445ff
JB		 6966 }
6967
6968 reg = rd32(hw, I40E_VP_MDET_RX(i));
6969 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6970 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
6971 vf->num_mdd_events++;
faf32978
JB		 6972 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
6973 i);
41c445ff
JB		 6974 }
6975
6976 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
6977 dev_info(&pf->pdev->dev,
6978 "Too many MDD events on VF %d, disabled\n", i);
6979 dev_info(&pf->pdev->dev,
6980 "Use PF Control I/F to re-enable the VF\n");
6981 set_bit(I40E_VF_STAT_DISABLED, &vf->vf_states);
6982 }
6983 }
6984
6985 /* re-enable mdd interrupt cause */
6986 clear_bit(__I40E_MDD_EVENT_PENDING, &pf->state);
6987 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
6988 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
6989 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
6990 i40e_flush(hw);
6991}
6992
6633d381 6993#ifdef CONFIG_I40E_VXLAN
a1c9a9d9
JK		 6994/**
6995 * i40e_sync_vxlan_filters_subtask - Sync the VSI filter list with HW
6996 * @pf: board private structure
6997 **/
6998static void i40e_sync_vxlan_filters_subtask(struct i40e_pf *pf)
6999{
a1c9a9d9
JK		 7000 struct i40e_hw *hw = &pf->hw;
7001 i40e_status ret;
a1c9a9d9
JK		 7002 __be16 port;
7003 int i;
7004
7005 if (!(pf->flags & I40E_FLAG_VXLAN_FILTER_SYNC))
7006 return;
7007
7008 pf->flags &= ~I40E_FLAG_VXLAN_FILTER_SYNC;
7009
7010 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
41a1d04b
JB		 7011 if (pf->pending_vxlan_bitmap & BIT_ULL(i)) {
7012 pf->pending_vxlan_bitmap &= ~BIT_ULL(i);
a1c9a9d9 7013 port = pf->vxlan_ports[i];
c22c06c8
SN		 7014 if (port)
7015 ret = i40e_aq_add_udp_tunnel(hw, ntohs(port),
a1c9a9d9 7016 I40E_AQC_TUNNEL_TYPE_VXLAN,
c22c06c8
SN		 7017 NULL, NULL);
7018 else
7019 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
a1c9a9d9
JK		 7020
7021 if (ret) {
c22c06c8 7022 dev_info(&pf->pdev->dev,
f1c7e72e 7023 "%s vxlan port %d, index %d failed, err %s aq_err %s\n",
c22c06c8 7024 port ? "add" : "delete",
f1c7e72e
SN		 7025 ntohs(port), i,
7026 i40e_stat_str(&pf->hw, ret),
7027 i40e_aq_str(&pf->hw,
7028 pf->hw.aq.asq_last_status));
a1c9a9d9 7029 pf->vxlan_ports[i] = 0;
a1c9a9d9
JK		 7030 }
7031 }
7032 }
7033}
7034
7035#endif
41c445ff
JB		 7036/**
7037 * i40e_service_task - Run the driver's async subtasks
7038 * @work: pointer to work_struct containing our data
7039 **/
7040static void i40e_service_task(struct work_struct *work)
7041{
7042 struct i40e_pf *pf = container_of(work,
7043 struct i40e_pf,
7044 service_task);
7045 unsigned long start_time = jiffies;
7046
e57a2fea
SN		 7047 /* don't bother with service tasks if a reset is in progress */
7048 if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7049 i40e_service_event_complete(pf);
7050 return;
7051 }
7052
b03a8c1f 7053 i40e_detect_recover_hung(pf);
41c445ff
JB		 7054 i40e_reset_subtask(pf);
7055 i40e_handle_mdd_event(pf);
7056 i40e_vc_process_vflr_event(pf);
7057 i40e_watchdog_subtask(pf);
7058 i40e_fdir_reinit_subtask(pf);
41c445ff 7059 i40e_sync_filters_subtask(pf);
6633d381 7060#ifdef CONFIG_I40E_VXLAN
a1c9a9d9
JK		 7061 i40e_sync_vxlan_filters_subtask(pf);
7062#endif
41c445ff
JB		 7063 i40e_clean_adminq_subtask(pf);
7064
7065 i40e_service_event_complete(pf);
7066
7067 /* If the tasks have taken longer than one timer cycle or there
7068 * is more work to be done, reschedule the service task now
7069 * rather than wait for the timer to tick again.
7070 */
7071 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
7072 test_bit(__I40E_ADMINQ_EVENT_PENDING, &pf->state) ||
7073 test_bit(__I40E_MDD_EVENT_PENDING, &pf->state) ||
7074 test_bit(__I40E_VFLR_EVENT_PENDING, &pf->state))
7075 i40e_service_event_schedule(pf);
7076}
7077
7078/**
7079 * i40e_service_timer - timer callback
7080 * @data: pointer to PF struct
7081 **/
7082static void i40e_service_timer(unsigned long data)
7083{
7084 struct i40e_pf *pf = (struct i40e_pf *)data;
7085
7086 mod_timer(&pf->service_timer,
7087 round_jiffies(jiffies + pf->service_timer_period));
7088 i40e_service_event_schedule(pf);
7089}
7090
7091/**
7092 * i40e_set_num_rings_in_vsi - Determine number of rings in the VSI
7093 * @vsi: the VSI being configured
7094 **/
7095static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
7096{
7097 struct i40e_pf *pf = vsi->back;
7098
7099 switch (vsi->type) {
7100 case I40E_VSI_MAIN:
7101 vsi->alloc_queue_pairs = pf->num_lan_qps;
7102 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7103 I40E_REQ_DESCRIPTOR_MULTIPLE);
7104 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7105 vsi->num_q_vectors = pf->num_lan_msix;
7106 else
7107 vsi->num_q_vectors = 1;
7108
7109 break;
7110
7111 case I40E_VSI_FDIR:
7112 vsi->alloc_queue_pairs = 1;
7113 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
7114 I40E_REQ_DESCRIPTOR_MULTIPLE);
7115 vsi->num_q_vectors = 1;
7116 break;
7117
7118 case I40E_VSI_VMDQ2:
7119 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
7120 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7121 I40E_REQ_DESCRIPTOR_MULTIPLE);
7122 vsi->num_q_vectors = pf->num_vmdq_msix;
7123 break;
7124
7125 case I40E_VSI_SRIOV:
7126 vsi->alloc_queue_pairs = pf->num_vf_qps;
7127 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7128 I40E_REQ_DESCRIPTOR_MULTIPLE);
7129 break;
7130
38e00438
VD		 7131#ifdef I40E_FCOE
7132 case I40E_VSI_FCOE:
7133 vsi->alloc_queue_pairs = pf->num_fcoe_qps;
7134 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
7135 I40E_REQ_DESCRIPTOR_MULTIPLE);
7136 vsi->num_q_vectors = pf->num_fcoe_msix;
7137 break;
7138
7139#endif /* I40E_FCOE */
41c445ff
JB		 7140 default:
7141 WARN_ON(1);
7142 return -ENODATA;
7143 }
7144
7145 return 0;
7146}
7147
f650a38b
ASJ		 7148/**
7149 * i40e_vsi_alloc_arrays - Allocate queue and vector pointer arrays for the vsi
7150 * @type: VSI pointer
bc7d338f 7151 * @alloc_qvectors: a bool to specify if q_vectors need to be allocated.
f650a38b
ASJ		 7152 *
7153 * On error: returns error code (negative)
7154 * On success: returns 0
7155 **/
bc7d338f 7156static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
f650a38b
ASJ		 7157{
7158 int size;
7159 int ret = 0;
7160
ac6c5e3d 7161 /* allocate memory for both Tx and Rx ring pointers */
f650a38b
ASJ		 7162 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs * 2;
7163 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
7164 if (!vsi->tx_rings)
7165 return -ENOMEM;
f650a38b
ASJ		 7166 vsi->rx_rings = &vsi->tx_rings[vsi->alloc_queue_pairs];
7167
bc7d338f
ASJ		 7168 if (alloc_qvectors) {
7169 /* allocate memory for q_vector pointers */
f57e4fbd 7170 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
bc7d338f
ASJ		 7171 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
7172 if (!vsi->q_vectors) {
7173 ret = -ENOMEM;
7174 goto err_vectors;
7175 }
f650a38b
ASJ		 7176 }
7177 return ret;
7178
7179err_vectors:
7180 kfree(vsi->tx_rings);
7181 return ret;
7182}
7183
41c445ff
JB		 7184/**
7185 * i40e_vsi_mem_alloc - Allocates the next available struct vsi in the PF
7186 * @pf: board private structure
7187 * @type: type of VSI
7188 *
7189 * On error: returns error code (negative)
7190 * On success: returns vsi index in PF (positive)
7191 **/
7192static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
7193{
7194 int ret = -ENODEV;
7195 struct i40e_vsi *vsi;
7196 int vsi_idx;
7197 int i;
7198
7199 /* Need to protect the allocation of the VSIs at the PF level */
7200 mutex_lock(&pf->switch_mutex);
7201
7202 /* VSI list may be fragmented if VSI creation/destruction has
7203 * been happening. We can afford to do a quick scan to look
7204 * for any free VSIs in the list.
7205 *
7206 * find next empty vsi slot, looping back around if necessary
7207 */
7208 i = pf->next_vsi;
505682cd 7209 while (i < pf->num_alloc_vsi && pf->vsi[i])
41c445ff 7210 i++;
505682cd 7211 if (i >= pf->num_alloc_vsi) {
41c445ff
JB		 7212 i = 0;
7213 while (i < pf->next_vsi && pf->vsi[i])
7214 i++;
7215 }
7216
505682cd 7217 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
41c445ff
JB		 7218 vsi_idx = i; /* Found one! */
7219 } else {
7220 ret = -ENODEV;
493fb300 7221 goto unlock_pf; /* out of VSI slots! */
41c445ff
JB		 7222 }
7223 pf->next_vsi = ++i;
7224
7225 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
7226 if (!vsi) {
7227 ret = -ENOMEM;
493fb300 7228 goto unlock_pf;
41c445ff
JB		 7229 }
7230 vsi->type = type;
7231 vsi->back = pf;
7232 set_bit(__I40E_DOWN, &vsi->state);
7233 vsi->flags = 0;
7234 vsi->idx = vsi_idx;
7235 vsi->rx_itr_setting = pf->rx_itr_default;
7236 vsi->tx_itr_setting = pf->tx_itr_default;
ac26fc13 7237 vsi->int_rate_limit = 0;
5db4cb59
ASJ		 7238 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
7239 pf->rss_table_size : 64;
41c445ff
JB		 7240 vsi->netdev_registered = false;
7241 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
7242 INIT_LIST_HEAD(&vsi->mac_filter_list);
63741846 7243 vsi->irqs_ready = false;
41c445ff 7244
9f65e15b
AD		 7245 ret = i40e_set_num_rings_in_vsi(vsi);
7246 if (ret)
7247 goto err_rings;
7248
bc7d338f 7249 ret = i40e_vsi_alloc_arrays(vsi, true);
f650a38b 7250 if (ret)
9f65e15b 7251 goto err_rings;
493fb300 7252
41c445ff
JB		 7253 /* Setup default MSIX irq handler for VSI */
7254 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
7255
21659035
KP		 7256 /* Initialize VSI lock */
7257 spin_lock_init(&vsi->mac_filter_list_lock);
41c445ff
JB		 7258 pf->vsi[vsi_idx] = vsi;
7259 ret = vsi_idx;
493fb300
AD		 7260 goto unlock_pf;
7261
9f65e15b 7262err_rings:
493fb300
AD		 7263 pf->next_vsi = i - 1;
7264 kfree(vsi);
7265unlock_pf:
41c445ff
JB		 7266 mutex_unlock(&pf->switch_mutex);
7267 return ret;
7268}
7269
f650a38b
ASJ		 7270/**
7271 * i40e_vsi_free_arrays - Free queue and vector pointer arrays for the VSI
7272 * @type: VSI pointer
bc7d338f 7273 * @free_qvectors: a bool to specify if q_vectors need to be freed.
f650a38b
ASJ		 7274 *
7275 * On error: returns error code (negative)
7276 * On success: returns 0
7277 **/
bc7d338f 7278static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
f650a38b
ASJ		 7279{
7280 /* free the ring and vector containers */
bc7d338f
ASJ		 7281 if (free_qvectors) {
7282 kfree(vsi->q_vectors);
7283 vsi->q_vectors = NULL;
7284 }
f650a38b
ASJ		 7285 kfree(vsi->tx_rings);
7286 vsi->tx_rings = NULL;
7287 vsi->rx_rings = NULL;
7288}
7289
28c5869f
HZ		 7290/**
7291 * i40e_clear_rss_config_user - clear the user configured RSS hash keys
7292 * and lookup table
7293 * @vsi: Pointer to VSI structure
7294 */
7295static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
7296{
7297 if (!vsi)
7298 return;
7299
7300 kfree(vsi->rss_hkey_user);
7301 vsi->rss_hkey_user = NULL;
7302
7303 kfree(vsi->rss_lut_user);
7304 vsi->rss_lut_user = NULL;
7305}
7306
41c445ff
JB		 7307/**
7308 * i40e_vsi_clear - Deallocate the VSI provided
7309 * @vsi: the VSI being un-configured
7310 **/
7311static int i40e_vsi_clear(struct i40e_vsi *vsi)
7312{
7313 struct i40e_pf *pf;
7314
7315 if (!vsi)
7316 return 0;
7317
7318 if (!vsi->back)
7319 goto free_vsi;
7320 pf = vsi->back;
7321
7322 mutex_lock(&pf->switch_mutex);
7323 if (!pf->vsi[vsi->idx]) {
7324 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](%p,type %d)\n",
7325 vsi->idx, vsi->idx, vsi, vsi->type);
7326 goto unlock_vsi;
7327 }
7328
7329 if (pf->vsi[vsi->idx] != vsi) {
7330 dev_err(&pf->pdev->dev,
7331 "pf->vsi[%d](%p, type %d) != vsi[%d](%p,type %d): no free!\n",
7332 pf->vsi[vsi->idx]->idx,
7333 pf->vsi[vsi->idx],
7334 pf->vsi[vsi->idx]->type,
7335 vsi->idx, vsi, vsi->type);
7336 goto unlock_vsi;
7337 }
7338
b40c82e6 7339 /* updates the PF for this cleared vsi */
41c445ff
JB		 7340 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
7341 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
7342
bc7d338f 7343 i40e_vsi_free_arrays(vsi, true);
28c5869f 7344 i40e_clear_rss_config_user(vsi);
493fb300 7345
41c445ff
JB		 7346 pf->vsi[vsi->idx] = NULL;
7347 if (vsi->idx < pf->next_vsi)
7348 pf->next_vsi = vsi->idx;
7349
7350unlock_vsi:
7351 mutex_unlock(&pf->switch_mutex);
7352free_vsi:
7353 kfree(vsi);
7354
7355 return 0;
7356}
7357
9f65e15b
AD		 7358/**
7359 * i40e_vsi_clear_rings - Deallocates the Rx and Tx rings for the provided VSI
7360 * @vsi: the VSI being cleaned
7361 **/
be1d5eea 7362static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
9f65e15b
AD		 7363{
7364 int i;
7365
8e9dca53 7366 if (vsi->tx_rings && vsi->tx_rings[0]) {
d7397644 7367 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
00403f04
MW		 7368 kfree_rcu(vsi->tx_rings[i], rcu);
7369 vsi->tx_rings[i] = NULL;
7370 vsi->rx_rings[i] = NULL;
7371 }
be1d5eea 7372 }
9f65e15b
AD		 7373}
7374
41c445ff
JB		 7375/**
7376 * i40e_alloc_rings - Allocates the Rx and Tx rings for the provided VSI
7377 * @vsi: the VSI being configured
7378 **/
7379static int i40e_alloc_rings(struct i40e_vsi *vsi)
7380{
e7046ee1 7381 struct i40e_ring *tx_ring, *rx_ring;
41c445ff 7382 struct i40e_pf *pf = vsi->back;
41c445ff
JB		 7383 int i;
7384
41c445ff 7385 /* Set basic values in the rings to be used later during open() */
d7397644 7386 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
ac6c5e3d 7387 /* allocate space for both Tx and Rx in one shot */
9f65e15b
AD		 7388 tx_ring = kzalloc(sizeof(struct i40e_ring) * 2, GFP_KERNEL);
7389 if (!tx_ring)
7390 goto err_out;
41c445ff
JB		 7391
7392 tx_ring->queue_index = i;
7393 tx_ring->reg_idx = vsi->base_queue + i;
7394 tx_ring->ring_active = false;
7395 tx_ring->vsi = vsi;
7396 tx_ring->netdev = vsi->netdev;
7397 tx_ring->dev = &pf->pdev->dev;
7398 tx_ring->count = vsi->num_desc;
7399 tx_ring->size = 0;
7400 tx_ring->dcb_tc = 0;
8e0764b4
ASJ		 7401 if (vsi->back->flags & I40E_FLAG_WB_ON_ITR_CAPABLE)
7402 tx_ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
527274c7
ASJ		 7403 if (vsi->back->flags & I40E_FLAG_OUTER_UDP_CSUM_CAPABLE)
7404 tx_ring->flags |= I40E_TXR_FLAGS_OUTER_UDP_CSUM;
9f65e15b 7405 vsi->tx_rings[i] = tx_ring;
41c445ff 7406
9f65e15b 7407 rx_ring = &tx_ring[1];
41c445ff
JB		 7408 rx_ring->queue_index = i;
7409 rx_ring->reg_idx = vsi->base_queue + i;
7410 rx_ring->ring_active = false;
7411 rx_ring->vsi = vsi;
7412 rx_ring->netdev = vsi->netdev;
7413 rx_ring->dev = &pf->pdev->dev;
7414 rx_ring->count = vsi->num_desc;
7415 rx_ring->size = 0;
7416 rx_ring->dcb_tc = 0;
7417 if (pf->flags & I40E_FLAG_16BYTE_RX_DESC_ENABLED)
7418 set_ring_16byte_desc_enabled(rx_ring);
7419 else
7420 clear_ring_16byte_desc_enabled(rx_ring);
9f65e15b 7421 vsi->rx_rings[i] = rx_ring;
41c445ff
JB		 7422 }
7423
7424 return 0;
9f65e15b
AD		 7425
7426err_out:
7427 i40e_vsi_clear_rings(vsi);
7428 return -ENOMEM;
41c445ff
JB		 7429}
7430
7431/**
7432 * i40e_reserve_msix_vectors - Reserve MSI-X vectors in the kernel
7433 * @pf: board private structure
7434 * @vectors: the number of MSI-X vectors to request
7435 *
7436 * Returns the number of vectors reserved, or error
7437 **/
7438static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
7439{
7b37f376
AG		 7440 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
7441 I40E_MIN_MSIX, vectors);
7442 if (vectors < 0) {
41c445ff 7443 dev_info(&pf->pdev->dev,
7b37f376 7444 "MSI-X vector reservation failed: %d\n", vectors);
41c445ff
JB		 7445 vectors = 0;
7446 }
7447
7448 return vectors;
7449}
7450
7451/**
7452 * i40e_init_msix - Setup the MSIX capability
7453 * @pf: board private structure
7454 *
7455 * Work with the OS to set up the MSIX vectors needed.
7456 *
3b444399 7457 * Returns the number of vectors reserved or negative on failure
41c445ff
JB		 7458 **/
7459static int i40e_init_msix(struct i40e_pf *pf)
7460{
41c445ff 7461 struct i40e_hw *hw = &pf->hw;
1e200e4a 7462 int vectors_left;
41c445ff 7463 int v_budget, i;
3b444399 7464 int v_actual;
41c445ff
JB		 7465
7466 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
7467 return -ENODEV;
7468
7469 /* The number of vectors we'll request will be comprised of:
7470 * - Add 1 for "other" cause for Admin Queue events, etc.
7471 * - The number of LAN queue pairs
f8ff1464
ASJ		 7472 * - Queues being used for RSS.
7473 * We don't need as many as max_rss_size vectors.
7474 * use rss_size instead in the calculation since that
7475 * is governed by number of cpus in the system.
7476 * - assumes symmetric Tx/Rx pairing
41c445ff 7477 * - The number of VMDq pairs
38e00438
VD		 7478#ifdef I40E_FCOE
7479 * - The number of FCOE qps.
7480#endif
41c445ff
JB		 7481 * Once we count this up, try the request.
7482 *
7483 * If we can't get what we want, we'll simplify to nearly nothing
7484 * and try again. If that still fails, we punt.
7485 */
1e200e4a
SN		 7486 vectors_left = hw->func_caps.num_msix_vectors;
7487 v_budget = 0;
7488
7489 /* reserve one vector for miscellaneous handler */
7490 if (vectors_left) {
7491 v_budget++;
7492 vectors_left--;
7493 }
7494
7495 /* reserve vectors for the main PF traffic queues */
7496 pf->num_lan_msix = min_t(int, num_online_cpus(), vectors_left);
7497 vectors_left -= pf->num_lan_msix;
7498 v_budget += pf->num_lan_msix;
7499
7500 /* reserve one vector for sideband flow director */
7501 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
7502 if (vectors_left) {
7503 v_budget++;
7504 vectors_left--;
7505 } else {
7506 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7507 }
7508 }
83840e4b 7509
38e00438 7510#ifdef I40E_FCOE
1e200e4a 7511 /* can we reserve enough for FCoE? */
38e00438 7512 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
1e200e4a
SN		 7513 if (!vectors_left)
7514 pf->num_fcoe_msix = 0;
7515 else if (vectors_left >= pf->num_fcoe_qps)
7516 pf->num_fcoe_msix = pf->num_fcoe_qps;
7517 else
7518 pf->num_fcoe_msix = 1;
38e00438 7519 v_budget += pf->num_fcoe_msix;
1e200e4a 7520 vectors_left -= pf->num_fcoe_msix;
38e00438 7521 }
1e200e4a 7522
38e00438 7523#endif
1e200e4a
SN		 7524 /* any vectors left over go for VMDq support */
7525 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
7526 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
7527 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
7528
7529 /* if we're short on vectors for what's desired, we limit
7530 * the queues per vmdq. If this is still more than are
7531 * available, the user will need to change the number of
7532 * queues/vectors used by the PF later with the ethtool
7533 * channels command
7534 */
7535 if (vmdq_vecs < vmdq_vecs_wanted)
7536 pf->num_vmdq_qps = 1;
7537 pf->num_vmdq_msix = pf->num_vmdq_qps;
7538
7539 v_budget += vmdq_vecs;
7540 vectors_left -= vmdq_vecs;
7541 }
41c445ff
JB		 7542
7543 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
7544 GFP_KERNEL);
7545 if (!pf->msix_entries)
7546 return -ENOMEM;
7547
7548 for (i = 0; i < v_budget; i++)
7549 pf->msix_entries[i].entry = i;
3b444399 7550 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
a34977ba 7551
3b444399 7552 if (v_actual != v_budget) {
a34977ba
ASJ		 7553 /* If we have limited resources, we will start with no vectors
7554 * for the special features and then allocate vectors to some
7555 * of these features based on the policy and at the end disable
7556 * the features that did not get any vectors.
7557 */
38e00438
VD		 7558#ifdef I40E_FCOE
7559 pf->num_fcoe_qps = 0;
7560 pf->num_fcoe_msix = 0;
7561#endif
a34977ba
ASJ		 7562 pf->num_vmdq_msix = 0;
7563 }
7564
3b444399 7565 if (v_actual < I40E_MIN_MSIX) {
41c445ff
JB		 7566 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
7567 kfree(pf->msix_entries);
7568 pf->msix_entries = NULL;
7569 return -ENODEV;
7570
3b444399 7571 } else if (v_actual == I40E_MIN_MSIX) {
41c445ff 7572 /* Adjust for minimal MSIX use */
41c445ff
JB		 7573 pf->num_vmdq_vsis = 0;
7574 pf->num_vmdq_qps = 0;
41c445ff
JB		 7575 pf->num_lan_qps = 1;
7576 pf->num_lan_msix = 1;
7577
3b444399
SN		 7578 } else if (v_actual != v_budget) {
7579 int vec;
7580
a34977ba 7581 /* reserve the misc vector */
3b444399 7582 vec = v_actual - 1;
a34977ba 7583
41c445ff
JB		 7584 /* Scale vector usage down */
7585 pf->num_vmdq_msix = 1; /* force VMDqs to only one vector */
a34977ba 7586 pf->num_vmdq_vsis = 1;
1e200e4a
SN		 7587 pf->num_vmdq_qps = 1;
7588 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
41c445ff
JB		 7589
7590 /* partition out the remaining vectors */
7591 switch (vec) {
7592 case 2:
41c445ff
JB		 7593 pf->num_lan_msix = 1;
7594 break;
7595 case 3:
38e00438
VD		 7596#ifdef I40E_FCOE
7597 /* give one vector to FCoE */
7598 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7599 pf->num_lan_msix = 1;
7600 pf->num_fcoe_msix = 1;
7601 }
7602#else
41c445ff 7603 pf->num_lan_msix = 2;
38e00438 7604#endif
41c445ff
JB		 7605 break;
7606 default:
38e00438
VD		 7607#ifdef I40E_FCOE
7608 /* give one vector to FCoE */
7609 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
7610 pf->num_fcoe_msix = 1;
7611 vec--;
7612 }
7613#endif
1e200e4a
SN		 7614 /* give the rest to the PF */
7615 pf->num_lan_msix = min_t(int, vec, pf->num_lan_qps);
41c445ff
JB		 7616 break;
7617 }
7618 }
7619
a34977ba
ASJ		 7620 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
7621 (pf->num_vmdq_msix == 0)) {
7622 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
7623 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
7624 }
38e00438
VD		 7625#ifdef I40E_FCOE
7626
7627 if ((pf->flags & I40E_FLAG_FCOE_ENABLED) && (pf->num_fcoe_msix == 0)) {
7628 dev_info(&pf->pdev->dev, "FCOE disabled, not enough MSI-X vectors\n");
7629 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
7630 }
7631#endif
3b444399 7632 return v_actual;
41c445ff
JB		 7633}
7634
493fb300 7635/**
90e04070 7636 * i40e_vsi_alloc_q_vector - Allocate memory for a single interrupt vector
493fb300
AD		 7637 * @vsi: the VSI being configured
7638 * @v_idx: index of the vector in the vsi struct
7639 *
7640 * We allocate one q_vector. If allocation fails we return -ENOMEM.
7641 **/
90e04070 7642static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx)
493fb300
AD		 7643{
7644 struct i40e_q_vector *q_vector;
7645
7646 /* allocate q_vector */
7647 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
7648 if (!q_vector)
7649 return -ENOMEM;
7650
7651 q_vector->vsi = vsi;
7652 q_vector->v_idx = v_idx;
7653 cpumask_set_cpu(v_idx, &q_vector->affinity_mask);
7654 if (vsi->netdev)
7655 netif_napi_add(vsi->netdev, &q_vector->napi,
eefeacee 7656 i40e_napi_poll, NAPI_POLL_WEIGHT);
493fb300 7657
cd0b6fa6
AD		 7658 q_vector->rx.latency_range = I40E_LOW_LATENCY;
7659 q_vector->tx.latency_range = I40E_LOW_LATENCY;
7660
493fb300
AD		 7661 /* tie q_vector and vsi together */
7662 vsi->q_vectors[v_idx] = q_vector;
7663
7664 return 0;
7665}
7666
41c445ff 7667/**
90e04070 7668 * i40e_vsi_alloc_q_vectors - Allocate memory for interrupt vectors
41c445ff
JB		 7669 * @vsi: the VSI being configured
7670 *
7671 * We allocate one q_vector per queue interrupt. If allocation fails we
7672 * return -ENOMEM.
7673 **/
90e04070 7674static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
41c445ff
JB		 7675{
7676 struct i40e_pf *pf = vsi->back;
7677 int v_idx, num_q_vectors;
493fb300 7678 int err;
41c445ff
JB		 7679
7680 /* if not MSIX, give the one vector only to the LAN VSI */
7681 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
7682 num_q_vectors = vsi->num_q_vectors;
7683 else if (vsi == pf->vsi[pf->lan_vsi])
7684 num_q_vectors = 1;
7685 else
7686 return -EINVAL;
7687
41c445ff 7688 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
90e04070 7689 err = i40e_vsi_alloc_q_vector(vsi, v_idx);
493fb300
AD		 7690 if (err)
7691 goto err_out;
41c445ff
JB		 7692 }
7693
7694 return 0;
493fb300
AD		 7695
7696err_out:
7697 while (v_idx--)
7698 i40e_free_q_vector(vsi, v_idx);
7699
7700 return err;
41c445ff
JB		 7701}
7702
7703/**
7704 * i40e_init_interrupt_scheme - Determine proper interrupt scheme
7705 * @pf: board private structure to initialize
7706 **/
c1147280 7707static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
41c445ff 7708{
3b444399
SN		 7709 int vectors = 0;
7710 ssize_t size;
41c445ff
JB		 7711
7712 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3b444399
SN		 7713 vectors = i40e_init_msix(pf);
7714 if (vectors < 0) {
60ea5f83 7715 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
38e00438
VD		 7716#ifdef I40E_FCOE
7717 I40E_FLAG_FCOE_ENABLED |
7718#endif
60ea5f83 7719 I40E_FLAG_RSS_ENABLED |
4d9b6043 7720 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 7721 I40E_FLAG_SRIOV_ENABLED |
7722 I40E_FLAG_FD_SB_ENABLED |
7723 I40E_FLAG_FD_ATR_ENABLED |
7724 I40E_FLAG_VMDQ_ENABLED);
41c445ff
JB		 7725
7726 /* rework the queue expectations without MSIX */
7727 i40e_determine_queue_usage(pf);
7728 }
7729 }
7730
7731 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
7732 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
77fa28be 7733 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
3b444399
SN		 7734 vectors = pci_enable_msi(pf->pdev);
7735 if (vectors < 0) {
7736 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
7737 vectors);
41c445ff
JB		 7738 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
7739 }
3b444399 7740 vectors = 1; /* one MSI or Legacy vector */
41c445ff
JB		 7741 }
7742
958a3e3b 7743 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
77fa28be 7744 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
958a3e3b 7745
3b444399
SN		 7746 /* set up vector assignment tracking */
7747 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
7748 pf->irq_pile = kzalloc(size, GFP_KERNEL);
c1147280
JB		 7749 if (!pf->irq_pile) {
7750 dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
7751 return -ENOMEM;
7752 }
3b444399
SN		 7753 pf->irq_pile->num_entries = vectors;
7754 pf->irq_pile->search_hint = 0;
7755
c1147280 7756 /* track first vector for misc interrupts, ignore return */
3b444399 7757 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
c1147280
JB		 7758
7759 return 0;
41c445ff
JB		 7760}
7761
7762/**
7763 * i40e_setup_misc_vector - Setup the misc vector to handle non queue events
7764 * @pf: board private structure
7765 *
7766 * This sets up the handler for MSIX 0, which is used to manage the
7767 * non-queue interrupts, e.g. AdminQ and errors. This is not used
7768 * when in MSI or Legacy interrupt mode.
7769 **/
7770static int i40e_setup_misc_vector(struct i40e_pf *pf)
7771{
7772 struct i40e_hw *hw = &pf->hw;
7773 int err = 0;
7774
7775 /* Only request the irq if this is the first time through, and
7776 * not when we're rebuilding after a Reset
7777 */
7778 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state)) {
7779 err = request_irq(pf->msix_entries[0].vector,
b294ac70 7780 i40e_intr, 0, pf->int_name, pf);
41c445ff
JB		 7781 if (err) {
7782 dev_info(&pf->pdev->dev,
77fa28be 7783 "request_irq for %s failed: %d\n",
b294ac70 7784 pf->int_name, err);
41c445ff
JB		 7785 return -EFAULT;
7786 }
7787 }
7788
ab437b5a 7789 i40e_enable_misc_int_causes(pf);
41c445ff
JB		 7790
7791 /* associate no queues to the misc vector */
7792 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
7793 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
7794
7795 i40e_flush(hw);
7796
7797 i40e_irq_dynamic_enable_icr0(pf);
7798
7799 return err;
7800}
7801
7802/**
e25d00b8
ASJ		 7803 * i40e_config_rss_aq - Prepare for RSS using AQ commands
7804 * @vsi: vsi structure
7805 * @seed: RSS hash seed
7806 **/
e69ff813
HZ		 7807static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
7808 u8 *lut, u16 lut_size)
e25d00b8
ASJ		 7809{
7810 struct i40e_aqc_get_set_rss_key_data rss_key;
7811 struct i40e_pf *pf = vsi->back;
7812 struct i40e_hw *hw = &pf->hw;
7813 bool pf_lut = false;
7814 u8 *rss_lut;
7815 int ret, i;
7816
7817 memset(&rss_key, 0, sizeof(rss_key));
7818 memcpy(&rss_key, seed, sizeof(rss_key));
7819
7820 rss_lut = kzalloc(pf->rss_table_size, GFP_KERNEL);
7821 if (!rss_lut)
7822 return -ENOMEM;
7823
7824 /* Populate the LUT with max no. of queues in round robin fashion */
7825 for (i = 0; i < vsi->rss_table_size; i++)
7826 rss_lut[i] = i % vsi->rss_size;
7827
7828 ret = i40e_aq_set_rss_key(hw, vsi->id, &rss_key);
7829 if (ret) {
7830 dev_info(&pf->pdev->dev,
7831 "Cannot set RSS key, err %s aq_err %s\n",
7832 i40e_stat_str(&pf->hw, ret),
7833 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
126b63d9 7834 goto config_rss_aq_out;
e25d00b8
ASJ		 7835 }
7836
7837 if (vsi->type == I40E_VSI_MAIN)
7838 pf_lut = true;
7839
7840 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, rss_lut,
7841 vsi->rss_table_size);
7842 if (ret)
7843 dev_info(&pf->pdev->dev,
7844 "Cannot set RSS lut, err %s aq_err %s\n",
7845 i40e_stat_str(&pf->hw, ret),
7846 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7847
126b63d9
AS		 7848config_rss_aq_out:
7849 kfree(rss_lut);
e25d00b8
ASJ		 7850 return ret;
7851}
7852
7853/**
7854 * i40e_vsi_config_rss - Prepare for VSI(VMDq) RSS if used
7855 * @vsi: VSI structure
7856 **/
7857static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
7858{
7859 u8 seed[I40E_HKEY_ARRAY_SIZE];
7860 struct i40e_pf *pf = vsi->back;
e69ff813
HZ		 7861 u8 *lut;
7862 int ret;
7863
7864 if (!(pf->flags & I40E_FLAG_RSS_AQ_CAPABLE))
7865 return 0;
7866
7867 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
7868 if (!lut)
7869 return -ENOMEM;
e25d00b8 7870
e69ff813 7871 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e25d00b8 7872 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
acd65448 7873 vsi->rss_size = min_t(int, pf->alloc_rss_size, vsi->num_queue_pairs);
e69ff813
HZ		 7874 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
7875 kfree(lut);
e25d00b8 7876
e69ff813 7877 return ret;
e25d00b8
ASJ		 7878}
7879
7880/**
043dd650 7881 * i40e_config_rss_reg - Configure RSS keys and lut by writing registers
e69ff813 7882 * @vsi: Pointer to vsi structure
e25d00b8 7883 * @seed: RSS hash seed
e69ff813
HZ		 7884 * @lut: Lookup table
7885 * @lut_size: Lookup table size
7886 *
7887 * Returns 0 on success, negative on failure
41c445ff 7888 **/
e69ff813
HZ		 7889static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
7890 const u8 *lut, u16 lut_size)
41c445ff 7891{
e69ff813 7892 struct i40e_pf *pf = vsi->back;
4617e8c0 7893 struct i40e_hw *hw = &pf->hw;
e69ff813 7894 u8 i;
41c445ff 7895
e25d00b8 7896 /* Fill out hash function seed */
e69ff813
HZ		 7897 if (seed) {
7898 u32 *seed_dw = (u32 *)seed;
7899
7900 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7901 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
7902 }
7903
7904 if (lut) {
7905 u32 *lut_dw = (u32 *)lut;
7906
7907 if (lut_size != I40E_HLUT_ARRAY_SIZE)
7908 return -EINVAL;
7909
7910 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
7911 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
e25d00b8
ASJ		 7912 }
7913 i40e_flush(hw);
7914
7915 return 0;
7916}
7917
043dd650
HZ		 7918/**
7919 * i40e_get_rss_reg - Get the RSS keys and lut by reading registers
7920 * @vsi: Pointer to VSI structure
7921 * @seed: Buffer to store the keys
7922 * @lut: Buffer to store the lookup table entries
7923 * @lut_size: Size of buffer to store the lookup table entries
7924 *
7925 * Returns 0 on success, negative on failure
7926 */
7927static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
7928 u8 *lut, u16 lut_size)
7929{
7930 struct i40e_pf *pf = vsi->back;
7931 struct i40e_hw *hw = &pf->hw;
7932 u16 i;
7933
7934 if (seed) {
7935 u32 *seed_dw = (u32 *)seed;
7936
7937 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7938 seed_dw[i] = rd32(hw, I40E_PFQF_HKEY(i));
7939 }
7940 if (lut) {
7941 u32 *lut_dw = (u32 *)lut;
7942
7943 if (lut_size != I40E_HLUT_ARRAY_SIZE)
7944 return -EINVAL;
7945 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
7946 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
7947 }
7948
7949 return 0;
7950}
7951
7952/**
7953 * i40e_config_rss - Configure RSS keys and lut
7954 * @vsi: Pointer to VSI structure
7955 * @seed: RSS hash seed
7956 * @lut: Lookup table
7957 * @lut_size: Lookup table size
7958 *
7959 * Returns 0 on success, negative on failure
7960 */
7961int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
7962{
7963 struct i40e_pf *pf = vsi->back;
7964
7965 if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE)
7966 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
7967 else
7968 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
7969}
7970
7971/**
7972 * i40e_get_rss - Get RSS keys and lut
7973 * @vsi: Pointer to VSI structure
7974 * @seed: Buffer to store the keys
7975 * @lut: Buffer to store the lookup table entries
7976 * lut_size: Size of buffer to store the lookup table entries
7977 *
7978 * Returns 0 on success, negative on failure
7979 */
7980int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
7981{
7982 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
7983}
7984
e69ff813
HZ		 7985/**
7986 * i40e_fill_rss_lut - Fill the RSS lookup table with default values
7987 * @pf: Pointer to board private structure
7988 * @lut: Lookup table
7989 * @rss_table_size: Lookup table size
7990 * @rss_size: Range of queue number for hashing
7991 */
7992static void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
7993 u16 rss_table_size, u16 rss_size)
7994{
7995 u16 i;
7996
7997 for (i = 0; i < rss_table_size; i++)
7998 lut[i] = i % rss_size;
7999}
8000
e25d00b8 8001/**
043dd650 8002 * i40e_pf_config_rss - Prepare for RSS if used
e25d00b8
ASJ		 8003 * @pf: board private structure
8004 **/
043dd650 8005static int i40e_pf_config_rss(struct i40e_pf *pf)
e25d00b8
ASJ		 8006{
8007 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8008 u8 seed[I40E_HKEY_ARRAY_SIZE];
e69ff813 8009 u8 *lut;
e25d00b8
ASJ		 8010 struct i40e_hw *hw = &pf->hw;
8011 u32 reg_val;
8012 u64 hena;
e69ff813 8013 int ret;
e25d00b8 8014
41c445ff
JB		 8015 /* By default we enable TCP/UDP with IPv4/IPv6 ptypes */
8016 hena = (u64)rd32(hw, I40E_PFQF_HENA(0)) |
8017 ((u64)rd32(hw, I40E_PFQF_HENA(1)) << 32);
e25d00b8
ASJ		 8018 hena |= i40e_pf_get_default_rss_hena(pf);
8019
41c445ff
JB		 8020 wr32(hw, I40E_PFQF_HENA(0), (u32)hena);
8021 wr32(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
8022
e25d00b8 8023 /* Determine the RSS table size based on the hardware capabilities */
e157ea30 8024 reg_val = rd32(hw, I40E_PFQF_CTL_0);
e25d00b8
ASJ		 8025 reg_val = (pf->rss_table_size == 512) ?
8026 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
8027 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
e157ea30
CW		 8028 wr32(hw, I40E_PFQF_CTL_0, reg_val);
8029
28c5869f
HZ		 8030 /* Determine the RSS size of the VSI */
8031 if (!vsi->rss_size)
acd65448
HZ		 8032 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8033 vsi->num_queue_pairs);
28c5869f 8034
e69ff813
HZ		 8035 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
8036 if (!lut)
8037 return -ENOMEM;
8038
28c5869f
HZ		 8039 /* Use user configured lut if there is one, otherwise use default */
8040 if (vsi->rss_lut_user)
8041 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
8042 else
8043 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
e69ff813 8044
28c5869f
HZ		 8045 /* Use user configured hash key if there is one, otherwise
8046 * use default.
8047 */
8048 if (vsi->rss_hkey_user)
8049 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
8050 else
8051 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
043dd650 8052 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
e69ff813
HZ		 8053 kfree(lut);
8054
8055 return ret;
41c445ff
JB		 8056}
8057
f8ff1464
ASJ		 8058/**
8059 * i40e_reconfig_rss_queues - change number of queues for rss and rebuild
8060 * @pf: board private structure
8061 * @queue_count: the requested queue count for rss.
8062 *
8063 * returns 0 if rss is not enabled, if enabled returns the final rss queue
8064 * count which may be different from the requested queue count.
8065 **/
8066int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
8067{
9a3bd2f1
ASJ		 8068 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8069 int new_rss_size;
8070
f8ff1464
ASJ		 8071 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
8072 return 0;
8073
9a3bd2f1 8074 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
f8ff1464 8075
9a3bd2f1
ASJ		 8076 if (queue_count != vsi->num_queue_pairs) {
8077 vsi->req_queue_pairs = queue_count;
f8ff1464
ASJ		 8078 i40e_prep_for_reset(pf);
8079
acd65448 8080 pf->alloc_rss_size = new_rss_size;
f8ff1464
ASJ		 8081
8082 i40e_reset_and_rebuild(pf, true);
28c5869f
HZ		 8083
8084 /* Discard the user configured hash keys and lut, if less
8085 * queues are enabled.
8086 */
8087 if (queue_count < vsi->rss_size) {
8088 i40e_clear_rss_config_user(vsi);
8089 dev_dbg(&pf->pdev->dev,
8090 "discard user configured hash keys and lut\n");
8091 }
8092
8093 /* Reset vsi->rss_size, as number of enabled queues changed */
acd65448
HZ		 8094 vsi->rss_size = min_t(int, pf->alloc_rss_size,
8095 vsi->num_queue_pairs);
28c5869f 8096
043dd650 8097 i40e_pf_config_rss(pf);
f8ff1464 8098 }
e36b0b11
HZ		 8099 dev_info(&pf->pdev->dev, "RSS count/HW max RSS count: %d/%d\n",
8100 pf->alloc_rss_size, pf->rss_size_max);
acd65448 8101 return pf->alloc_rss_size;
f8ff1464
ASJ		 8102}
8103
f4492db1
GR		 8104/**
8105 * i40e_get_npar_bw_setting - Retrieve BW settings for this PF partition
8106 * @pf: board private structure
8107 **/
8108i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf)
8109{
8110 i40e_status status;
8111 bool min_valid, max_valid;
8112 u32 max_bw, min_bw;
8113
8114 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
8115 &min_valid, &max_valid);
8116
8117 if (!status) {
8118 if (min_valid)
8119 pf->npar_min_bw = min_bw;
8120 if (max_valid)
8121 pf->npar_max_bw = max_bw;
8122 }
8123
8124 return status;
8125}
8126
8127/**
8128 * i40e_set_npar_bw_setting - Set BW settings for this PF partition
8129 * @pf: board private structure
8130 **/
8131i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf)
8132{
8133 struct i40e_aqc_configure_partition_bw_data bw_data;
8134 i40e_status status;
8135
b40c82e6 8136 /* Set the valid bit for this PF */
41a1d04b 8137 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
f4492db1
GR		 8138 bw_data.max_bw[pf->hw.pf_id] = pf->npar_max_bw & I40E_ALT_BW_VALUE_MASK;
8139 bw_data.min_bw[pf->hw.pf_id] = pf->npar_min_bw & I40E_ALT_BW_VALUE_MASK;
8140
8141 /* Set the new bandwidths */
8142 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
8143
8144 return status;
8145}
8146
8147/**
8148 * i40e_commit_npar_bw_setting - Commit BW settings for this PF partition
8149 * @pf: board private structure
8150 **/
8151i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf)
8152{
8153 /* Commit temporary BW setting to permanent NVM image */
8154 enum i40e_admin_queue_err last_aq_status;
8155 i40e_status ret;
8156 u16 nvm_word;
8157
8158 if (pf->hw.partition_id != 1) {
8159 dev_info(&pf->pdev->dev,
8160 "Commit BW only works on partition 1! This is partition %d",
8161 pf->hw.partition_id);
8162 ret = I40E_NOT_SUPPORTED;
8163 goto bw_commit_out;
8164 }
8165
8166 /* Acquire NVM for read access */
8167 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
8168 last_aq_status = pf->hw.aq.asq_last_status;
8169 if (ret) {
8170 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8171 "Cannot acquire NVM for read access, err %s aq_err %s\n",
8172 i40e_stat_str(&pf->hw, ret),
8173 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8174 goto bw_commit_out;
8175 }
8176
8177 /* Read word 0x10 of NVM - SW compatibility word 1 */
8178 ret = i40e_aq_read_nvm(&pf->hw,
8179 I40E_SR_NVM_CONTROL_WORD,
8180 0x10, sizeof(nvm_word), &nvm_word,
8181 false, NULL);
8182 /* Save off last admin queue command status before releasing
8183 * the NVM
8184 */
8185 last_aq_status = pf->hw.aq.asq_last_status;
8186 i40e_release_nvm(&pf->hw);
8187 if (ret) {
f1c7e72e
SN		 8188 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
8189 i40e_stat_str(&pf->hw, ret),
8190 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8191 goto bw_commit_out;
8192 }
8193
8194 /* Wait a bit for NVM release to complete */
8195 msleep(50);
8196
8197 /* Acquire NVM for write access */
8198 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
8199 last_aq_status = pf->hw.aq.asq_last_status;
8200 if (ret) {
8201 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8202 "Cannot acquire NVM for write access, err %s aq_err %s\n",
8203 i40e_stat_str(&pf->hw, ret),
8204 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8205 goto bw_commit_out;
8206 }
8207 /* Write it back out unchanged to initiate update NVM,
8208 * which will force a write of the shadow (alt) RAM to
8209 * the NVM - thus storing the bandwidth values permanently.
8210 */
8211 ret = i40e_aq_update_nvm(&pf->hw,
8212 I40E_SR_NVM_CONTROL_WORD,
8213 0x10, sizeof(nvm_word),
8214 &nvm_word, true, NULL);
8215 /* Save off last admin queue command status before releasing
8216 * the NVM
8217 */
8218 last_aq_status = pf->hw.aq.asq_last_status;
8219 i40e_release_nvm(&pf->hw);
8220 if (ret)
8221 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8222 "BW settings NOT SAVED, err %s aq_err %s\n",
8223 i40e_stat_str(&pf->hw, ret),
8224 i40e_aq_str(&pf->hw, last_aq_status));
f4492db1
GR		 8225bw_commit_out:
8226
8227 return ret;
8228}
8229
41c445ff
JB		 8230/**
8231 * i40e_sw_init - Initialize general software structures (struct i40e_pf)
8232 * @pf: board private structure to initialize
8233 *
8234 * i40e_sw_init initializes the Adapter private data structure.
8235 * Fields are initialized based on PCI device information and
8236 * OS network device settings (MTU size).
8237 **/
8238static int i40e_sw_init(struct i40e_pf *pf)
8239{
8240 int err = 0;
8241 int size;
8242
8243 pf->msg_enable = netif_msg_init(I40E_DEFAULT_MSG_ENABLE,
8244 (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK));
2759997b 8245 pf->hw.debug_mask = pf->msg_enable | I40E_DEBUG_DIAG;
41c445ff
JB		 8246 if (debug != -1 && debug != I40E_DEFAULT_MSG_ENABLE) {
8247 if (I40E_DEBUG_USER & debug)
8248 pf->hw.debug_mask = debug;
8249 pf->msg_enable = netif_msg_init((debug & ~I40E_DEBUG_USER),
8250 I40E_DEFAULT_MSG_ENABLE);
8251 }
8252
8253 /* Set default capability flags */
8254 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
8255 I40E_FLAG_MSI_ENABLED |
9ac77266 8256 I40E_FLAG_LINK_POLLING_ENABLED |
2bc7ee8a
MW		 8257 I40E_FLAG_MSIX_ENABLED;
8258
8259 if (iommu_present(&pci_bus_type))
8260 pf->flags |= I40E_FLAG_RX_PS_ENABLED;
8261 else
8262 pf->flags |= I40E_FLAG_RX_1BUF_ENABLED;
41c445ff 8263
ca99eb99
MW		 8264 /* Set default ITR */
8265 pf->rx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_RX_DEF;
8266 pf->tx_itr_default = I40E_ITR_DYNAMIC | I40E_ITR_TX_DEF;
8267
7134f9ce
JB		 8268 /* Depending on PF configurations, it is possible that the RSS
8269 * maximum might end up larger than the available queues
8270 */
41a1d04b 8271 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
acd65448 8272 pf->alloc_rss_size = 1;
5db4cb59 8273 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
7134f9ce
JB		 8274 pf->rss_size_max = min_t(int, pf->rss_size_max,
8275 pf->hw.func_caps.num_tx_qp);
41c445ff
JB		 8276 if (pf->hw.func_caps.rss) {
8277 pf->flags |= I40E_FLAG_RSS_ENABLED;
acd65448
HZ		 8278 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
8279 num_online_cpus());
41c445ff
JB		 8280 }
8281
2050bc65 8282 /* MFP mode enabled */
c78b953e 8283 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
2050bc65
CS		 8284 pf->flags |= I40E_FLAG_MFP_ENABLED;
8285 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
f4492db1
GR		 8286 if (i40e_get_npar_bw_setting(pf))
8287 dev_warn(&pf->pdev->dev,
8288 "Could not get NPAR bw settings\n");
8289 else
8290 dev_info(&pf->pdev->dev,
8291 "Min BW = %8.8x, Max BW = %8.8x\n",
8292 pf->npar_min_bw, pf->npar_max_bw);
2050bc65
CS		 8293 }
8294
cbf61325
ASJ		 8295 /* FW/NVM is not yet fixed in this regard */
8296 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
8297 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
8298 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
8299 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
6eae9c6a
SN		 8300 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
8301 pf->hw.num_partitions > 1)
cbf61325 8302 dev_info(&pf->pdev->dev,
0b67584f 8303 "Flow Director Sideband mode Disabled in MFP mode\n");
6eae9c6a
SN		 8304 else
8305 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
cbf61325
ASJ		 8306 pf->fdir_pf_filter_count =
8307 pf->hw.func_caps.fd_filters_guaranteed;
8308 pf->hw.fdir_shared_filter_count =
8309 pf->hw.func_caps.fd_filters_best_effort;
41c445ff
JB		 8310 }
8311
8312 if (pf->hw.func_caps.vmdq) {
41c445ff 8313 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
e25d00b8 8314 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
e9e53662 8315 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
41c445ff
JB		 8316 }
8317
38e00438 8318#ifdef I40E_FCOE
21364bcf 8319 i40e_init_pf_fcoe(pf);
38e00438
VD		 8320
8321#endif /* I40E_FCOE */
41c445ff 8322#ifdef CONFIG_PCI_IOV
ba252f13 8323 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
41c445ff
JB		 8324 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
8325 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
8326 pf->num_req_vfs = min_t(int,
8327 pf->hw.func_caps.num_vfs,
8328 I40E_MAX_VF_COUNT);
8329 }
8330#endif /* CONFIG_PCI_IOV */
d502ce01
ASJ		 8331 if (pf->hw.mac.type == I40E_MAC_X722) {
8332 pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE |
8333 I40E_FLAG_128_QP_RSS_CAPABLE |
8334 I40E_FLAG_HW_ATR_EVICT_CAPABLE |
8335 I40E_FLAG_OUTER_UDP_CSUM_CAPABLE |
8336 I40E_FLAG_WB_ON_ITR_CAPABLE |
8337 I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE;
8338 }
41c445ff
JB		 8339 pf->eeprom_version = 0xDEAD;
8340 pf->lan_veb = I40E_NO_VEB;
8341 pf->lan_vsi = I40E_NO_VSI;
8342
d1a8d275
ASJ		 8343 /* By default FW has this off for performance reasons */
8344 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
8345
41c445ff
JB		 8346 /* set up queue assignment tracking */
8347 size = sizeof(struct i40e_lump_tracking)
8348 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
8349 pf->qp_pile = kzalloc(size, GFP_KERNEL);
8350 if (!pf->qp_pile) {
8351 err = -ENOMEM;
8352 goto sw_init_done;
8353 }
8354 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
8355 pf->qp_pile->search_hint = 0;
8356
327fe04b
ASJ		 8357 pf->tx_timeout_recovery_level = 1;
8358
41c445ff
JB		 8359 mutex_init(&pf->switch_mutex);
8360
c668a12c
GR		 8361 /* If NPAR is enabled nudge the Tx scheduler */
8362 if (pf->hw.func_caps.npar_enable && (!i40e_get_npar_bw_setting(pf)))
8363 i40e_set_npar_bw_setting(pf);
8364
41c445ff
JB		 8365sw_init_done:
8366 return err;
8367}
8368
7c3c288b
ASJ		 8369/**
8370 * i40e_set_ntuple - set the ntuple feature flag and take action
8371 * @pf: board private structure to initialize
8372 * @features: the feature set that the stack is suggesting
8373 *
8374 * returns a bool to indicate if reset needs to happen
8375 **/
8376bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
8377{
8378 bool need_reset = false;
8379
8380 /* Check if Flow Director n-tuple support was enabled or disabled. If
8381 * the state changed, we need to reset.
8382 */
8383 if (features & NETIF_F_NTUPLE) {
8384 /* Enable filters and mark for reset */
8385 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
8386 need_reset = true;
8387 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
8388 } else {
8389 /* turn off filters, mark for reset and clear SW filter list */
8390 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
8391 need_reset = true;
8392 i40e_fdir_filter_exit(pf);
8393 }
8394 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
8a4f34fb 8395 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
1e1be8f6
ASJ		 8396 /* reset fd counters */
8397 pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
8398 pf->fdir_pf_active_filters = 0;
8399 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
2e4875e3
ASJ		 8400 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8401 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
8a4f34fb
ASJ		 8402 /* if ATR was auto disabled it can be re-enabled. */
8403 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8404 (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
8405 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
7c3c288b
ASJ		 8406 }
8407 return need_reset;
8408}
8409
41c445ff
JB		 8410/**
8411 * i40e_set_features - set the netdev feature flags
8412 * @netdev: ptr to the netdev being adjusted
8413 * @features: the feature set that the stack is suggesting
8414 **/
8415static int i40e_set_features(struct net_device *netdev,
8416 netdev_features_t features)
8417{
8418 struct i40e_netdev_priv *np = netdev_priv(netdev);
8419 struct i40e_vsi *vsi = np->vsi;
7c3c288b
ASJ		 8420 struct i40e_pf *pf = vsi->back;
8421 bool need_reset;
41c445ff
JB		 8422
8423 if (features & NETIF_F_HW_VLAN_CTAG_RX)
8424 i40e_vlan_stripping_enable(vsi);
8425 else
8426 i40e_vlan_stripping_disable(vsi);
8427
7c3c288b
ASJ		 8428 need_reset = i40e_set_ntuple(pf, features);
8429
8430 if (need_reset)
41a1d04b 8431 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
7c3c288b 8432
41c445ff
JB		 8433 return 0;
8434}
8435
6633d381 8436#ifdef CONFIG_I40E_VXLAN
a1c9a9d9
JK		 8437/**
8438 * i40e_get_vxlan_port_idx - Lookup a possibly offloaded for Rx UDP port
8439 * @pf: board private structure
8440 * @port: The UDP port to look up
8441 *
8442 * Returns the index number or I40E_MAX_PF_UDP_OFFLOAD_PORTS if port not found
8443 **/
8444static u8 i40e_get_vxlan_port_idx(struct i40e_pf *pf, __be16 port)
8445{
8446 u8 i;
8447
8448 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8449 if (pf->vxlan_ports[i] == port)
8450 return i;
8451 }
8452
8453 return i;
8454}
8455
8456/**
8457 * i40e_add_vxlan_port - Get notifications about VXLAN ports that come up
8458 * @netdev: This physical port's netdev
8459 * @sa_family: Socket Family that VXLAN is notifying us about
8460 * @port: New UDP port number that VXLAN started listening to
8461 **/
8462static void i40e_add_vxlan_port(struct net_device *netdev,
8463 sa_family_t sa_family, __be16 port)
8464{
8465 struct i40e_netdev_priv *np = netdev_priv(netdev);
8466 struct i40e_vsi *vsi = np->vsi;
8467 struct i40e_pf *pf = vsi->back;
8468 u8 next_idx;
8469 u8 idx;
8470
8471 if (sa_family == AF_INET6)
8472 return;
8473
8474 idx = i40e_get_vxlan_port_idx(pf, port);
8475
8476 /* Check if port already exists */
8477 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8
SN		 8478 netdev_info(netdev, "vxlan port %d already offloaded\n",
8479 ntohs(port));
a1c9a9d9
JK		 8480 return;
8481 }
8482
8483 /* Now check if there is space to add the new port */
8484 next_idx = i40e_get_vxlan_port_idx(pf, 0);
8485
8486 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
c22c06c8 8487 netdev_info(netdev, "maximum number of vxlan UDP ports reached, not adding port %d\n",
a1c9a9d9
JK		 8488 ntohs(port));
8489 return;
8490 }
8491
8492 /* New port: add it and mark its index in the bitmap */
8493 pf->vxlan_ports[next_idx] = port;
41a1d04b 8494 pf->pending_vxlan_bitmap |= BIT_ULL(next_idx);
a1c9a9d9
JK		 8495 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8496}
8497
8498/**
8499 * i40e_del_vxlan_port - Get notifications about VXLAN ports that go away
8500 * @netdev: This physical port's netdev
8501 * @sa_family: Socket Family that VXLAN is notifying us about
8502 * @port: UDP port number that VXLAN stopped listening to
8503 **/
8504static void i40e_del_vxlan_port(struct net_device *netdev,
8505 sa_family_t sa_family, __be16 port)
8506{
8507 struct i40e_netdev_priv *np = netdev_priv(netdev);
8508 struct i40e_vsi *vsi = np->vsi;
8509 struct i40e_pf *pf = vsi->back;
8510 u8 idx;
8511
8512 if (sa_family == AF_INET6)
8513 return;
8514
8515 idx = i40e_get_vxlan_port_idx(pf, port);
8516
8517 /* Check if port already exists */
8518 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
8519 /* if port exists, set it to 0 (mark for deletion)
8520 * and make it pending
8521 */
8522 pf->vxlan_ports[idx] = 0;
41a1d04b 8523 pf->pending_vxlan_bitmap |= BIT_ULL(idx);
a1c9a9d9
JK		 8524 pf->flags |= I40E_FLAG_VXLAN_FILTER_SYNC;
8525 } else {
c22c06c8 8526 netdev_warn(netdev, "vxlan port %d was not found, not deleting\n",
a1c9a9d9
JK		 8527 ntohs(port));
8528 }
8529}
8530
8531#endif
1f224ad2 8532static int i40e_get_phys_port_id(struct net_device *netdev,
02637fce 8533 struct netdev_phys_item_id *ppid)
1f224ad2
NP		 8534{
8535 struct i40e_netdev_priv *np = netdev_priv(netdev);
8536 struct i40e_pf *pf = np->vsi->back;
8537 struct i40e_hw *hw = &pf->hw;
8538
8539 if (!(pf->flags & I40E_FLAG_PORT_ID_VALID))
8540 return -EOPNOTSUPP;
8541
8542 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
8543 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
8544
8545 return 0;
8546}
8547
2f90ade6
JB		 8548/**
8549 * i40e_ndo_fdb_add - add an entry to the hardware database
8550 * @ndm: the input from the stack
8551 * @tb: pointer to array of nladdr (unused)
8552 * @dev: the net device pointer
8553 * @addr: the MAC address entry being added
8554 * @flags: instructions from stack about fdb operation
8555 */
4ba0dea5
GR		 8556static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
8557 struct net_device *dev,
f6f6424b 8558 const unsigned char *addr, u16 vid,
4ba0dea5 8559 u16 flags)
4ba0dea5
GR		 8560{
8561 struct i40e_netdev_priv *np = netdev_priv(dev);
8562 struct i40e_pf *pf = np->vsi->back;
8563 int err = 0;
8564
8565 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
8566 return -EOPNOTSUPP;
8567
65891fea
OG		 8568 if (vid) {
8569 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
8570 return -EINVAL;
8571 }
8572
4ba0dea5
GR		 8573 /* Hardware does not support aging addresses so if a
8574 * ndm_state is given only allow permanent addresses
8575 */
8576 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
8577 netdev_info(dev, "FDB only supports static addresses\n");
8578 return -EINVAL;
8579 }
8580
8581 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
8582 err = dev_uc_add_excl(dev, addr);
8583 else if (is_multicast_ether_addr(addr))
8584 err = dev_mc_add_excl(dev, addr);
8585 else
8586 err = -EINVAL;
8587
8588 /* Only return duplicate errors if NLM_F_EXCL is set */
8589 if (err == -EEXIST && !(flags & NLM_F_EXCL))
8590 err = 0;
8591
8592 return err;
8593}
8594
51616018
NP		 8595/**
8596 * i40e_ndo_bridge_setlink - Set the hardware bridge mode
8597 * @dev: the netdev being configured
8598 * @nlh: RTNL message
8599 *
8600 * Inserts a new hardware bridge if not already created and
8601 * enables the bridging mode requested (VEB or VEPA). If the
8602 * hardware bridge has already been inserted and the request
8603 * is to change the mode then that requires a PF reset to
8604 * allow rebuild of the components with required hardware
8605 * bridge mode enabled.
8606 **/
8607static int i40e_ndo_bridge_setlink(struct net_device *dev,
9df70b66
CW		 8608 struct nlmsghdr *nlh,
8609 u16 flags)
51616018
NP		 8610{
8611 struct i40e_netdev_priv *np = netdev_priv(dev);
8612 struct i40e_vsi *vsi = np->vsi;
8613 struct i40e_pf *pf = vsi->back;
8614 struct i40e_veb *veb = NULL;
8615 struct nlattr *attr, *br_spec;
8616 int i, rem;
8617
8618 /* Only for PF VSI for now */
8619 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8620 return -EOPNOTSUPP;
8621
8622 /* Find the HW bridge for PF VSI */
8623 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8624 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8625 veb = pf->veb[i];
8626 }
8627
8628 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
8629
8630 nla_for_each_nested(attr, br_spec, rem) {
8631 __u16 mode;
8632
8633 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8634 continue;
8635
8636 mode = nla_get_u16(attr);
8637 if ((mode != BRIDGE_MODE_VEPA) &&
8638 (mode != BRIDGE_MODE_VEB))
8639 return -EINVAL;
8640
8641 /* Insert a new HW bridge */
8642 if (!veb) {
8643 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
8644 vsi->tc_config.enabled_tc);
8645 if (veb) {
8646 veb->bridge_mode = mode;
8647 i40e_config_bridge_mode(veb);
8648 } else {
8649 /* No Bridge HW offload available */
8650 return -ENOENT;
8651 }
8652 break;
8653 } else if (mode != veb->bridge_mode) {
8654 /* Existing HW bridge but different mode needs reset */
8655 veb->bridge_mode = mode;
fc60861e
ASJ		 8656 /* TODO: If no VFs or VMDq VSIs, disallow VEB mode */
8657 if (mode == BRIDGE_MODE_VEB)
8658 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
8659 else
8660 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
8661 i40e_do_reset(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED));
51616018
NP		 8662 break;
8663 }
8664 }
8665
8666 return 0;
8667}
8668
8669/**
8670 * i40e_ndo_bridge_getlink - Get the hardware bridge mode
8671 * @skb: skb buff
8672 * @pid: process id
8673 * @seq: RTNL message seq #
8674 * @dev: the netdev being configured
8675 * @filter_mask: unused
d4b2f9fe 8676 * @nlflags: netlink flags passed in
51616018
NP		 8677 *
8678 * Return the mode in which the hardware bridge is operating in
8679 * i.e VEB or VEPA.
8680 **/
51616018
NP		 8681static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
8682 struct net_device *dev,
9f4ffc44
CW		 8683 u32 __always_unused filter_mask,
8684 int nlflags)
51616018
NP		 8685{
8686 struct i40e_netdev_priv *np = netdev_priv(dev);
8687 struct i40e_vsi *vsi = np->vsi;
8688 struct i40e_pf *pf = vsi->back;
8689 struct i40e_veb *veb = NULL;
8690 int i;
8691
8692 /* Only for PF VSI for now */
8693 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
8694 return -EOPNOTSUPP;
8695
8696 /* Find the HW bridge for the PF VSI */
8697 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
8698 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
8699 veb = pf->veb[i];
8700 }
8701
8702 if (!veb)
8703 return 0;
8704
46c264da 8705 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
7d4f8d87 8706 nlflags, 0, 0, filter_mask, NULL);
51616018 8707}
51616018 8708
f44a75e2
JS		 8709#define I40E_MAX_TUNNEL_HDR_LEN 80
8710/**
8711 * i40e_features_check - Validate encapsulated packet conforms to limits
8712 * @skb: skb buff
2bc11c63 8713 * @dev: This physical port's netdev
f44a75e2
JS		 8714 * @features: Offload features that the stack believes apply
8715 **/
8716static netdev_features_t i40e_features_check(struct sk_buff *skb,
8717 struct net_device *dev,
8718 netdev_features_t features)
8719{
8720 if (skb->encapsulation &&
8721 (skb_inner_mac_header(skb) - skb_transport_header(skb) >
8722 I40E_MAX_TUNNEL_HDR_LEN))
8723 return features & ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
8724
8725 return features;
8726}
8727
37a2973a 8728static const struct net_device_ops i40e_netdev_ops = {
41c445ff
JB		 8729 .ndo_open = i40e_open,
8730 .ndo_stop = i40e_close,
8731 .ndo_start_xmit = i40e_lan_xmit_frame,
8732 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
8733 .ndo_set_rx_mode = i40e_set_rx_mode,
8734 .ndo_validate_addr = eth_validate_addr,
8735 .ndo_set_mac_address = i40e_set_mac,
8736 .ndo_change_mtu = i40e_change_mtu,
beb0dff1 8737 .ndo_do_ioctl = i40e_ioctl,
41c445ff
JB		 8738 .ndo_tx_timeout = i40e_tx_timeout,
8739 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
8740 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
8741#ifdef CONFIG_NET_POLL_CONTROLLER
8742 .ndo_poll_controller = i40e_netpoll,
8743#endif
8744 .ndo_setup_tc = i40e_setup_tc,
38e00438
VD		 8745#ifdef I40E_FCOE
8746 .ndo_fcoe_enable = i40e_fcoe_enable,
8747 .ndo_fcoe_disable = i40e_fcoe_disable,
8748#endif
41c445ff
JB		 8749 .ndo_set_features = i40e_set_features,
8750 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
8751 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
ed616689 8752 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
41c445ff 8753 .ndo_get_vf_config = i40e_ndo_get_vf_config,
588aefa0 8754 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
e6d9004d 8755 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
6633d381 8756#ifdef CONFIG_I40E_VXLAN
a1c9a9d9
JK		 8757 .ndo_add_vxlan_port = i40e_add_vxlan_port,
8758 .ndo_del_vxlan_port = i40e_del_vxlan_port,
8759#endif
1f224ad2 8760 .ndo_get_phys_port_id = i40e_get_phys_port_id,
4ba0dea5 8761 .ndo_fdb_add = i40e_ndo_fdb_add,
f44a75e2 8762 .ndo_features_check = i40e_features_check,
51616018
NP		 8763 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
8764 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
41c445ff
JB		 8765};
8766
8767/**
8768 * i40e_config_netdev - Setup the netdev flags
8769 * @vsi: the VSI being configured
8770 *
8771 * Returns 0 on success, negative value on failure
8772 **/
8773static int i40e_config_netdev(struct i40e_vsi *vsi)
8774{
1a10370a 8775 u8 brdcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
41c445ff
JB		 8776 struct i40e_pf *pf = vsi->back;
8777 struct i40e_hw *hw = &pf->hw;
8778 struct i40e_netdev_priv *np;
8779 struct net_device *netdev;
8780 u8 mac_addr[ETH_ALEN];
8781 int etherdev_size;
8782
8783 etherdev_size = sizeof(struct i40e_netdev_priv);
f8ff1464 8784 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
41c445ff
JB		 8785 if (!netdev)
8786 return -ENOMEM;
8787
8788 vsi->netdev = netdev;
8789 np = netdev_priv(netdev);
8790 np->vsi = vsi;
8791
d70e941b 8792 netdev->hw_enc_features |= NETIF_F_IP_CSUM |
41c445ff 8793 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 8794 NETIF_F_GSO_GRE |
d70e941b 8795 NETIF_F_TSO;
41c445ff
JB		 8796
8797 netdev->features = NETIF_F_SG |
8798 NETIF_F_IP_CSUM |
8799 NETIF_F_SCTP_CSUM |
8800 NETIF_F_HIGHDMA |
8801 NETIF_F_GSO_UDP_TUNNEL |
fec31fff 8802 NETIF_F_GSO_GRE |
41c445ff
JB		 8803 NETIF_F_HW_VLAN_CTAG_TX |
8804 NETIF_F_HW_VLAN_CTAG_RX |
8805 NETIF_F_HW_VLAN_CTAG_FILTER |
8806 NETIF_F_IPV6_CSUM |
8807 NETIF_F_TSO |
059dab69 8808 NETIF_F_TSO_ECN |
41c445ff
JB		 8809 NETIF_F_TSO6 |
8810 NETIF_F_RXCSUM |
8811 NETIF_F_RXHASH |
8812 0;
8813
2e86a0b6
ASJ		 8814 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
8815 netdev->features |= NETIF_F_NTUPLE;
8816
41c445ff
JB		 8817 /* copy netdev features into list of user selectable features */
8818 netdev->hw_features |= netdev->features;
8819
8820 if (vsi->type == I40E_VSI_MAIN) {
8821 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
9a173901 8822 ether_addr_copy(mac_addr, hw->mac.perm_addr);
30650cc5
SN		 8823 /* The following steps are necessary to prevent reception
8824 * of tagged packets - some older NVM configurations load a
8825 * default a MAC-VLAN filter that accepts any tagged packet
8826 * which must be replaced by a normal filter.
8c27d42e 8827 */
21659035
KP		 8828 if (!i40e_rm_default_mac_filter(vsi, mac_addr)) {
8829 spin_lock_bh(&vsi->mac_filter_list_lock);
30650cc5
SN		 8830 i40e_add_filter(vsi, mac_addr,
8831 I40E_VLAN_ANY, false, true);
21659035
KP		 8832 spin_unlock_bh(&vsi->mac_filter_list_lock);
8833 }
41c445ff
JB		 8834 } else {
8835 /* relate the VSI_VMDQ name to the VSI_MAIN name */
8836 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
8837 pf->vsi[pf->lan_vsi]->netdev->name);
8838 random_ether_addr(mac_addr);
21659035
KP		 8839
8840 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff 8841 i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, false);
21659035 8842 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 8843 }
21659035
KP		 8844
8845 spin_lock_bh(&vsi->mac_filter_list_lock);
1a10370a 8846 i40e_add_filter(vsi, brdcast, I40E_VLAN_ANY, false, false);
21659035 8847 spin_unlock_bh(&vsi->mac_filter_list_lock);
41c445ff 8848
9a173901
GR		 8849 ether_addr_copy(netdev->dev_addr, mac_addr);
8850 ether_addr_copy(netdev->perm_addr, mac_addr);
41c445ff
JB		 8851 /* vlan gets same features (except vlan offload)
8852 * after any tweaks for specific VSI types
8853 */
8854 netdev->vlan_features = netdev->features & ~(NETIF_F_HW_VLAN_CTAG_TX |
8855 NETIF_F_HW_VLAN_CTAG_RX |
8856 NETIF_F_HW_VLAN_CTAG_FILTER);
8857 netdev->priv_flags |= IFF_UNICAST_FLT;
8858 netdev->priv_flags |= IFF_SUPP_NOFCS;
8859 /* Setup netdev TC information */
8860 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
8861
8862 netdev->netdev_ops = &i40e_netdev_ops;
8863 netdev->watchdog_timeo = 5 * HZ;
8864 i40e_set_ethtool_ops(netdev);
38e00438
VD		 8865#ifdef I40E_FCOE
8866 i40e_fcoe_config_netdev(netdev, vsi);
8867#endif
41c445ff
JB		 8868
8869 return 0;
8870}
8871
8872/**
8873 * i40e_vsi_delete - Delete a VSI from the switch
8874 * @vsi: the VSI being removed
8875 *
8876 * Returns 0 on success, negative value on failure
8877 **/
8878static void i40e_vsi_delete(struct i40e_vsi *vsi)
8879{
8880 /* remove default VSI is not allowed */
8881 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
8882 return;
8883
41c445ff 8884 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
41c445ff
JB		 8885}
8886
51616018
NP		 8887/**
8888 * i40e_is_vsi_uplink_mode_veb - Check if the VSI's uplink bridge mode is VEB
8889 * @vsi: the VSI being queried
8890 *
8891 * Returns 1 if HW bridge mode is VEB and return 0 in case of VEPA mode
8892 **/
8893int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
8894{
8895 struct i40e_veb *veb;
8896 struct i40e_pf *pf = vsi->back;
8897
8898 /* Uplink is not a bridge so default to VEB */
8899 if (vsi->veb_idx == I40E_NO_VEB)
8900 return 1;
8901
8902 veb = pf->veb[vsi->veb_idx];
09603eaa
AA		 8903 if (!veb) {
8904 dev_info(&pf->pdev->dev,
8905 "There is no veb associated with the bridge\n");
8906 return -ENOENT;
8907 }
8908
51616018 8909 /* Uplink is a bridge in VEPA mode */
09603eaa 8910 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
51616018 8911 return 0;
09603eaa
AA		 8912 } else {
8913 /* Uplink is a bridge in VEB mode */
8914 return 1;
8915 }
51616018 8916
09603eaa
AA		 8917 /* VEPA is now default bridge, so return 0 */
8918 return 0;
51616018
NP		 8919}
8920
41c445ff
JB		 8921/**
8922 * i40e_add_vsi - Add a VSI to the switch
8923 * @vsi: the VSI being configured
8924 *
8925 * This initializes a VSI context depending on the VSI type to be added and
8926 * passes it down to the add_vsi aq command.
8927 **/
8928static int i40e_add_vsi(struct i40e_vsi *vsi)
8929{
8930 int ret = -ENODEV;
21659035
KP		 8931 u8 laa_macaddr[ETH_ALEN];
8932 bool found_laa_mac_filter = false;
41c445ff
JB		 8933 struct i40e_pf *pf = vsi->back;
8934 struct i40e_hw *hw = &pf->hw;
8935 struct i40e_vsi_context ctxt;
21659035
KP		 8936 struct i40e_mac_filter *f, *ftmp;
8937
41c445ff
JB		 8938 u8 enabled_tc = 0x1; /* TC0 enabled */
8939 int f_count = 0;
8940
8941 memset(&ctxt, 0, sizeof(ctxt));
8942 switch (vsi->type) {
8943 case I40E_VSI_MAIN:
8944 /* The PF's main VSI is already setup as part of the
8945 * device initialization, so we'll not bother with
8946 * the add_vsi call, but we will retrieve the current
8947 * VSI context.
8948 */
8949 ctxt.seid = pf->main_vsi_seid;
8950 ctxt.pf_num = pf->hw.pf_id;
8951 ctxt.vf_num = 0;
8952 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8953 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8954 if (ret) {
8955 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8956 "couldn't get PF vsi config, err %s aq_err %s\n",
8957 i40e_stat_str(&pf->hw, ret),
8958 i40e_aq_str(&pf->hw,
8959 pf->hw.aq.asq_last_status));
41c445ff
JB		 8960 return -ENOENT;
8961 }
1a2f6248 8962 vsi->info = ctxt.info;
41c445ff
JB		 8963 vsi->info.valid_sections = 0;
8964
8965 vsi->seid = ctxt.seid;
8966 vsi->id = ctxt.vsi_number;
8967
8968 enabled_tc = i40e_pf_get_tc_map(pf);
8969
8970 /* MFP mode setup queue map and update VSI */
63d7e5a4
NP		 8971 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
8972 !(pf->hw.func_caps.iscsi)) { /* NIC type PF */
41c445ff
JB		 8973 memset(&ctxt, 0, sizeof(ctxt));
8974 ctxt.seid = pf->main_vsi_seid;
8975 ctxt.pf_num = pf->hw.pf_id;
8976 ctxt.vf_num = 0;
8977 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
8978 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
8979 if (ret) {
8980 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 8981 "update vsi failed, err %s aq_err %s\n",
8982 i40e_stat_str(&pf->hw, ret),
8983 i40e_aq_str(&pf->hw,
8984 pf->hw.aq.asq_last_status));
41c445ff
JB		 8985 ret = -ENOENT;
8986 goto err;
8987 }
8988 /* update the local VSI info queue map */
8989 i40e_vsi_update_queue_map(vsi, &ctxt);
8990 vsi->info.valid_sections = 0;
8991 } else {
8992 /* Default/Main VSI is only enabled for TC0
8993 * reconfigure it to enable all TCs that are
8994 * available on the port in SFP mode.
63d7e5a4
NP		 8995 * For MFP case the iSCSI PF would use this
8996 * flow to enable LAN+iSCSI TC.
41c445ff
JB		 8997 */
8998 ret = i40e_vsi_config_tc(vsi, enabled_tc);
8999 if (ret) {
9000 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9001 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
9002 enabled_tc,
9003 i40e_stat_str(&pf->hw, ret),
9004 i40e_aq_str(&pf->hw,
9005 pf->hw.aq.asq_last_status));
41c445ff
JB		 9006 ret = -ENOENT;
9007 }
9008 }
9009 break;
9010
9011 case I40E_VSI_FDIR:
cbf61325
ASJ		 9012 ctxt.pf_num = hw->pf_id;
9013 ctxt.vf_num = 0;
9014 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9015 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
cbf61325 9016 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
fc60861e
ASJ		 9017 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
9018 (i40e_is_vsi_uplink_mode_veb(vsi))) {
51616018 9019 ctxt.info.valid_sections |=
fc60861e 9020 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
51616018 9021 ctxt.info.switch_id =
fc60861e 9022 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
51616018 9023 }
41c445ff 9024 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
41c445ff
JB		 9025 break;
9026
9027 case I40E_VSI_VMDQ2:
9028 ctxt.pf_num = hw->pf_id;
9029 ctxt.vf_num = 0;
9030 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9031 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9032 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
9033
41c445ff
JB		 9034 /* This VSI is connected to VEB so the switch_id
9035 * should be set to zero by default.
9036 */
51616018
NP		 9037 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9038 ctxt.info.valid_sections |=
9039 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9040 ctxt.info.switch_id =
9041 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9042 }
41c445ff
JB		 9043
9044 /* Setup the VSI tx/rx queue map for TC0 only for now */
9045 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9046 break;
9047
9048 case I40E_VSI_SRIOV:
9049 ctxt.pf_num = hw->pf_id;
9050 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
9051 ctxt.uplink_seid = vsi->uplink_seid;
2b18e591 9052 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
41c445ff
JB		 9053 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
9054
41c445ff
JB		 9055 /* This VSI is connected to VEB so the switch_id
9056 * should be set to zero by default.
9057 */
51616018
NP		 9058 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
9059 ctxt.info.valid_sections |=
9060 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
9061 ctxt.info.switch_id =
9062 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
9063 }
41c445ff
JB		 9064
9065 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
9066 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
c674d125
MW		 9067 if (pf->vf[vsi->vf_id].spoofchk) {
9068 ctxt.info.valid_sections |=
9069 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
9070 ctxt.info.sec_flags |=
9071 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
9072 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
9073 }
41c445ff
JB		 9074 /* Setup the VSI tx/rx queue map for TC0 only for now */
9075 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
9076 break;
9077
38e00438
VD		 9078#ifdef I40E_FCOE
9079 case I40E_VSI_FCOE:
9080 ret = i40e_fcoe_vsi_init(vsi, &ctxt);
9081 if (ret) {
9082 dev_info(&pf->pdev->dev, "failed to initialize FCoE VSI\n");
9083 return ret;
9084 }
9085 break;
9086
9087#endif /* I40E_FCOE */
41c445ff
JB		 9088 default:
9089 return -ENODEV;
9090 }
9091
9092 if (vsi->type != I40E_VSI_MAIN) {
9093 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
9094 if (ret) {
9095 dev_info(&vsi->back->pdev->dev,
f1c7e72e
SN		 9096 "add vsi failed, err %s aq_err %s\n",
9097 i40e_stat_str(&pf->hw, ret),
9098 i40e_aq_str(&pf->hw,
9099 pf->hw.aq.asq_last_status));
41c445ff
JB		 9100 ret = -ENOENT;
9101 goto err;
9102 }
1a2f6248 9103 vsi->info = ctxt.info;
41c445ff
JB		 9104 vsi->info.valid_sections = 0;
9105 vsi->seid = ctxt.seid;
9106 vsi->id = ctxt.vsi_number;
9107 }
9108
21659035 9109 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9110 /* If macvlan filters already exist, force them to get loaded */
9111 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list) {
9112 f->changed = true;
9113 f_count++;
6252c7e4 9114
21659035 9115 /* Expected to have only one MAC filter entry for LAA in list */
6252c7e4 9116 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
21659035
KP		 9117 ether_addr_copy(laa_macaddr, f->macaddr);
9118 found_laa_mac_filter = true;
9119 }
9120 }
9121 spin_unlock_bh(&vsi->mac_filter_list_lock);
30650cc5 9122
21659035
KP		 9123 if (found_laa_mac_filter) {
9124 struct i40e_aqc_remove_macvlan_element_data element;
30650cc5 9125
21659035
KP		 9126 memset(&element, 0, sizeof(element));
9127 ether_addr_copy(element.mac_addr, laa_macaddr);
9128 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
9129 ret = i40e_aq_remove_macvlan(hw, vsi->seid,
9130 &element, 1, NULL);
9131 if (ret) {
9132 /* some older FW has a different default */
9133 element.flags |=
9134 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
9135 i40e_aq_remove_macvlan(hw, vsi->seid,
9136 &element, 1, NULL);
6252c7e4 9137 }
21659035
KP		 9138
9139 i40e_aq_mac_address_write(hw,
9140 I40E_AQC_WRITE_TYPE_LAA_WOL,
9141 laa_macaddr, NULL);
41c445ff 9142 }
21659035 9143
41c445ff
JB		 9144 if (f_count) {
9145 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
9146 pf->flags |= I40E_FLAG_FILTER_SYNC;
9147 }
9148
9149 /* Update VSI BW information */
9150 ret = i40e_vsi_get_bw_info(vsi);
9151 if (ret) {
9152 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9153 "couldn't get vsi bw info, err %s aq_err %s\n",
9154 i40e_stat_str(&pf->hw, ret),
9155 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9156 /* VSI is already added so not tearing that up */
9157 ret = 0;
9158 }
9159
9160err:
9161 return ret;
9162}
9163
9164/**
9165 * i40e_vsi_release - Delete a VSI and free its resources
9166 * @vsi: the VSI being removed
9167 *
9168 * Returns 0 on success or < 0 on error
9169 **/
9170int i40e_vsi_release(struct i40e_vsi *vsi)
9171{
9172 struct i40e_mac_filter *f, *ftmp;
9173 struct i40e_veb *veb = NULL;
9174 struct i40e_pf *pf;
9175 u16 uplink_seid;
9176 int i, n;
9177
9178 pf = vsi->back;
9179
9180 /* release of a VEB-owner or last VSI is not allowed */
9181 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
9182 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
9183 vsi->seid, vsi->uplink_seid);
9184 return -ENODEV;
9185 }
9186 if (vsi == pf->vsi[pf->lan_vsi] &&
9187 !test_bit(__I40E_DOWN, &pf->state)) {
9188 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
9189 return -ENODEV;
9190 }
9191
9192 uplink_seid = vsi->uplink_seid;
9193 if (vsi->type != I40E_VSI_SRIOV) {
9194 if (vsi->netdev_registered) {
9195 vsi->netdev_registered = false;
9196 if (vsi->netdev) {
9197 /* results in a call to i40e_close() */
9198 unregister_netdev(vsi->netdev);
41c445ff
JB		 9199 }
9200 } else {
90ef8d47 9201 i40e_vsi_close(vsi);
41c445ff
JB		 9202 }
9203 i40e_vsi_disable_irq(vsi);
9204 }
9205
21659035 9206 spin_lock_bh(&vsi->mac_filter_list_lock);
41c445ff
JB		 9207 list_for_each_entry_safe(f, ftmp, &vsi->mac_filter_list, list)
9208 i40e_del_filter(vsi, f->macaddr, f->vlan,
9209 f->is_vf, f->is_netdev);
21659035
KP		 9210 spin_unlock_bh(&vsi->mac_filter_list_lock);
9211
17652c63 9212 i40e_sync_vsi_filters(vsi);
41c445ff
JB		 9213
9214 i40e_vsi_delete(vsi);
9215 i40e_vsi_free_q_vectors(vsi);
a4866597
SN		 9216 if (vsi->netdev) {
9217 free_netdev(vsi->netdev);
9218 vsi->netdev = NULL;
9219 }
41c445ff
JB		 9220 i40e_vsi_clear_rings(vsi);
9221 i40e_vsi_clear(vsi);
9222
9223 /* If this was the last thing on the VEB, except for the
9224 * controlling VSI, remove the VEB, which puts the controlling
9225 * VSI onto the next level down in the switch.
9226 *
9227 * Well, okay, there's one more exception here: don't remove
9228 * the orphan VEBs yet. We'll wait for an explicit remove request
9229 * from up the network stack.
9230 */
505682cd 9231 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9232 if (pf->vsi[i] &&
9233 pf->vsi[i]->uplink_seid == uplink_seid &&
9234 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9235 n++; /* count the VSIs */
9236 }
9237 }
9238 for (i = 0; i < I40E_MAX_VEB; i++) {
9239 if (!pf->veb[i])
9240 continue;
9241 if (pf->veb[i]->uplink_seid == uplink_seid)
9242 n++; /* count the VEBs */
9243 if (pf->veb[i]->seid == uplink_seid)
9244 veb = pf->veb[i];
9245 }
9246 if (n == 0 && veb && veb->uplink_seid != 0)
9247 i40e_veb_release(veb);
9248
9249 return 0;
9250}
9251
9252/**
9253 * i40e_vsi_setup_vectors - Set up the q_vectors for the given VSI
9254 * @vsi: ptr to the VSI
9255 *
9256 * This should only be called after i40e_vsi_mem_alloc() which allocates the
9257 * corresponding SW VSI structure and initializes num_queue_pairs for the
9258 * newly allocated VSI.
9259 *
9260 * Returns 0 on success or negative on failure
9261 **/
9262static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
9263{
9264 int ret = -ENOENT;
9265 struct i40e_pf *pf = vsi->back;
9266
493fb300 9267 if (vsi->q_vectors[0]) {
41c445ff
JB		 9268 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
9269 vsi->seid);
9270 return -EEXIST;
9271 }
9272
9273 if (vsi->base_vector) {
f29eaa3d 9274 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
41c445ff
JB		 9275 vsi->seid, vsi->base_vector);
9276 return -EEXIST;
9277 }
9278
90e04070 9279 ret = i40e_vsi_alloc_q_vectors(vsi);
41c445ff
JB		 9280 if (ret) {
9281 dev_info(&pf->pdev->dev,
9282 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
9283 vsi->num_q_vectors, vsi->seid, ret);
9284 vsi->num_q_vectors = 0;
9285 goto vector_setup_out;
9286 }
9287
26cdc443
ASJ		 9288 /* In Legacy mode, we do not have to get any other vector since we
9289 * piggyback on the misc/ICR0 for queue interrupts.
9290 */
9291 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
9292 return ret;
958a3e3b
SN		 9293 if (vsi->num_q_vectors)
9294 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
9295 vsi->num_q_vectors, vsi->idx);
41c445ff
JB		 9296 if (vsi->base_vector < 0) {
9297 dev_info(&pf->pdev->dev,
049a2be8
SN		 9298 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
9299 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
41c445ff
JB		 9300 i40e_vsi_free_q_vectors(vsi);
9301 ret = -ENOENT;
9302 goto vector_setup_out;
9303 }
9304
9305vector_setup_out:
9306 return ret;
9307}
9308
bc7d338f
ASJ		 9309/**
9310 * i40e_vsi_reinit_setup - return and reallocate resources for a VSI
9311 * @vsi: pointer to the vsi.
9312 *
9313 * This re-allocates a vsi's queue resources.
9314 *
9315 * Returns pointer to the successfully allocated and configured VSI sw struct
9316 * on success, otherwise returns NULL on failure.
9317 **/
9318static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
9319{
9320 struct i40e_pf *pf = vsi->back;
9321 u8 enabled_tc;
9322 int ret;
9323
9324 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
9325 i40e_vsi_clear_rings(vsi);
9326
9327 i40e_vsi_free_arrays(vsi, false);
9328 i40e_set_num_rings_in_vsi(vsi);
9329 ret = i40e_vsi_alloc_arrays(vsi, false);
9330 if (ret)
9331 goto err_vsi;
9332
9333 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs, vsi->idx);
9334 if (ret < 0) {
049a2be8 9335 dev_info(&pf->pdev->dev,
f1c7e72e 9336 "failed to get tracking for %d queues for VSI %d err %d\n",
049a2be8 9337 vsi->alloc_queue_pairs, vsi->seid, ret);
bc7d338f
ASJ		 9338 goto err_vsi;
9339 }
9340 vsi->base_queue = ret;
9341
9342 /* Update the FW view of the VSI. Force a reset of TC and queue
9343 * layout configurations.
9344 */
9345 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
9346 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
9347 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
9348 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
9349
9350 /* assign it some queues */
9351 ret = i40e_alloc_rings(vsi);
9352 if (ret)
9353 goto err_rings;
9354
9355 /* map all of the rings to the q_vectors */
9356 i40e_vsi_map_rings_to_vectors(vsi);
9357 return vsi;
9358
9359err_rings:
9360 i40e_vsi_free_q_vectors(vsi);
9361 if (vsi->netdev_registered) {
9362 vsi->netdev_registered = false;
9363 unregister_netdev(vsi->netdev);
9364 free_netdev(vsi->netdev);
9365 vsi->netdev = NULL;
9366 }
9367 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9368err_vsi:
9369 i40e_vsi_clear(vsi);
9370 return NULL;
9371}
9372
41c445ff
JB		 9373/**
9374 * i40e_vsi_setup - Set up a VSI by a given type
9375 * @pf: board private structure
9376 * @type: VSI type
9377 * @uplink_seid: the switch element to link to
9378 * @param1: usage depends upon VSI type. For VF types, indicates VF id
9379 *
9380 * This allocates the sw VSI structure and its queue resources, then add a VSI
9381 * to the identified VEB.
9382 *
9383 * Returns pointer to the successfully allocated and configure VSI sw struct on
9384 * success, otherwise returns NULL on failure.
9385 **/
9386struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
9387 u16 uplink_seid, u32 param1)
9388{
9389 struct i40e_vsi *vsi = NULL;
9390 struct i40e_veb *veb = NULL;
9391 int ret, i;
9392 int v_idx;
9393
9394 /* The requested uplink_seid must be either
9395 * - the PF's port seid
9396 * no VEB is needed because this is the PF
9397 * or this is a Flow Director special case VSI
9398 * - seid of an existing VEB
9399 * - seid of a VSI that owns an existing VEB
9400 * - seid of a VSI that doesn't own a VEB
9401 * a new VEB is created and the VSI becomes the owner
9402 * - seid of the PF VSI, which is what creates the first VEB
9403 * this is a special case of the previous
9404 *
9405 * Find which uplink_seid we were given and create a new VEB if needed
9406 */
9407 for (i = 0; i < I40E_MAX_VEB; i++) {
9408 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
9409 veb = pf->veb[i];
9410 break;
9411 }
9412 }
9413
9414 if (!veb && uplink_seid != pf->mac_seid) {
9415
505682cd 9416 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9417 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
9418 vsi = pf->vsi[i];
9419 break;
9420 }
9421 }
9422 if (!vsi) {
9423 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
9424 uplink_seid);
9425 return NULL;
9426 }
9427
9428 if (vsi->uplink_seid == pf->mac_seid)
9429 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
9430 vsi->tc_config.enabled_tc);
9431 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
9432 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
9433 vsi->tc_config.enabled_tc);
79c21a82
ASJ		 9434 if (veb) {
9435 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
9436 dev_info(&vsi->back->pdev->dev,
fb43201f 9437 "New VSI creation error, uplink seid of LAN VSI expected.\n");
79c21a82
ASJ		 9438 return NULL;
9439 }
fa11cb3d
ASJ		 9440 /* We come up by default in VEPA mode if SRIOV is not
9441 * already enabled, in which case we can't force VEPA
9442 * mode.
9443 */
9444 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
9445 veb->bridge_mode = BRIDGE_MODE_VEPA;
9446 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
9447 }
51616018 9448 i40e_config_bridge_mode(veb);
79c21a82 9449 }
41c445ff
JB		 9450 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
9451 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
9452 veb = pf->veb[i];
9453 }
9454 if (!veb) {
9455 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
9456 return NULL;
9457 }
9458
9459 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9460 uplink_seid = veb->seid;
9461 }
9462
9463 /* get vsi sw struct */
9464 v_idx = i40e_vsi_mem_alloc(pf, type);
9465 if (v_idx < 0)
9466 goto err_alloc;
9467 vsi = pf->vsi[v_idx];
cbf61325
ASJ		 9468 if (!vsi)
9469 goto err_alloc;
41c445ff
JB		 9470 vsi->type = type;
9471 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
9472
9473 if (type == I40E_VSI_MAIN)
9474 pf->lan_vsi = v_idx;
9475 else if (type == I40E_VSI_SRIOV)
9476 vsi->vf_id = param1;
9477 /* assign it some queues */
cbf61325
ASJ		 9478 ret = i40e_get_lump(pf, pf->qp_pile, vsi->alloc_queue_pairs,
9479 vsi->idx);
41c445ff 9480 if (ret < 0) {
049a2be8
SN		 9481 dev_info(&pf->pdev->dev,
9482 "failed to get tracking for %d queues for VSI %d err=%d\n",
9483 vsi->alloc_queue_pairs, vsi->seid, ret);
41c445ff
JB		 9484 goto err_vsi;
9485 }
9486 vsi->base_queue = ret;
9487
9488 /* get a VSI from the hardware */
9489 vsi->uplink_seid = uplink_seid;
9490 ret = i40e_add_vsi(vsi);
9491 if (ret)
9492 goto err_vsi;
9493
9494 switch (vsi->type) {
9495 /* setup the netdev if needed */
9496 case I40E_VSI_MAIN:
9497 case I40E_VSI_VMDQ2:
38e00438 9498 case I40E_VSI_FCOE:
41c445ff
JB		 9499 ret = i40e_config_netdev(vsi);
9500 if (ret)
9501 goto err_netdev;
9502 ret = register_netdev(vsi->netdev);
9503 if (ret)
9504 goto err_netdev;
9505 vsi->netdev_registered = true;
9506 netif_carrier_off(vsi->netdev);
4e3b35b0
NP		 9507#ifdef CONFIG_I40E_DCB
9508 /* Setup DCB netlink interface */
9509 i40e_dcbnl_setup(vsi);
9510#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 9511 /* fall through */
9512
9513 case I40E_VSI_FDIR:
9514 /* set up vectors and rings if needed */
9515 ret = i40e_vsi_setup_vectors(vsi);
9516 if (ret)
9517 goto err_msix;
9518
9519 ret = i40e_alloc_rings(vsi);
9520 if (ret)
9521 goto err_rings;
9522
9523 /* map all of the rings to the q_vectors */
9524 i40e_vsi_map_rings_to_vectors(vsi);
9525
9526 i40e_vsi_reset_stats(vsi);
9527 break;
9528
9529 default:
9530 /* no netdev or rings for the other VSI types */
9531 break;
9532 }
9533
e25d00b8
ASJ		 9534 if ((pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) &&
9535 (vsi->type == I40E_VSI_VMDQ2)) {
9536 ret = i40e_vsi_config_rss(vsi);
9537 }
41c445ff
JB		 9538 return vsi;
9539
9540err_rings:
9541 i40e_vsi_free_q_vectors(vsi);
9542err_msix:
9543 if (vsi->netdev_registered) {
9544 vsi->netdev_registered = false;
9545 unregister_netdev(vsi->netdev);
9546 free_netdev(vsi->netdev);
9547 vsi->netdev = NULL;
9548 }
9549err_netdev:
9550 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
9551err_vsi:
9552 i40e_vsi_clear(vsi);
9553err_alloc:
9554 return NULL;
9555}
9556
9557/**
9558 * i40e_veb_get_bw_info - Query VEB BW information
9559 * @veb: the veb to query
9560 *
9561 * Query the Tx scheduler BW configuration data for given VEB
9562 **/
9563static int i40e_veb_get_bw_info(struct i40e_veb *veb)
9564{
9565 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
9566 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
9567 struct i40e_pf *pf = veb->pf;
9568 struct i40e_hw *hw = &pf->hw;
9569 u32 tc_bw_max;
9570 int ret = 0;
9571 int i;
9572
9573 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
9574 &bw_data, NULL);
9575 if (ret) {
9576 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9577 "query veb bw config failed, err %s aq_err %s\n",
9578 i40e_stat_str(&pf->hw, ret),
9579 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9580 goto out;
9581 }
9582
9583 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
9584 &ets_data, NULL);
9585 if (ret) {
9586 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 9587 "query veb bw ets config failed, err %s aq_err %s\n",
9588 i40e_stat_str(&pf->hw, ret),
9589 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
41c445ff
JB		 9590 goto out;
9591 }
9592
9593 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
9594 veb->bw_max_quanta = ets_data.tc_bw_max;
9595 veb->is_abs_credits = bw_data.absolute_credits_enable;
23cd1f09 9596 veb->enabled_tc = ets_data.tc_valid_bits;
41c445ff
JB		 9597 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
9598 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
9599 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
9600 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
9601 veb->bw_tc_limit_credits[i] =
9602 le16_to_cpu(bw_data.tc_bw_limits[i]);
9603 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
9604 }
9605
9606out:
9607 return ret;
9608}
9609
9610/**
9611 * i40e_veb_mem_alloc - Allocates the next available struct veb in the PF
9612 * @pf: board private structure
9613 *
9614 * On error: returns error code (negative)
9615 * On success: returns vsi index in PF (positive)
9616 **/
9617static int i40e_veb_mem_alloc(struct i40e_pf *pf)
9618{
9619 int ret = -ENOENT;
9620 struct i40e_veb *veb;
9621 int i;
9622
9623 /* Need to protect the allocation of switch elements at the PF level */
9624 mutex_lock(&pf->switch_mutex);
9625
9626 /* VEB list may be fragmented if VEB creation/destruction has
9627 * been happening. We can afford to do a quick scan to look
9628 * for any free slots in the list.
9629 *
9630 * find next empty veb slot, looping back around if necessary
9631 */
9632 i = 0;
9633 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
9634 i++;
9635 if (i >= I40E_MAX_VEB) {
9636 ret = -ENOMEM;
9637 goto err_alloc_veb; /* out of VEB slots! */
9638 }
9639
9640 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
9641 if (!veb) {
9642 ret = -ENOMEM;
9643 goto err_alloc_veb;
9644 }
9645 veb->pf = pf;
9646 veb->idx = i;
9647 veb->enabled_tc = 1;
9648
9649 pf->veb[i] = veb;
9650 ret = i;
9651err_alloc_veb:
9652 mutex_unlock(&pf->switch_mutex);
9653 return ret;
9654}
9655
9656/**
9657 * i40e_switch_branch_release - Delete a branch of the switch tree
9658 * @branch: where to start deleting
9659 *
9660 * This uses recursion to find the tips of the branch to be
9661 * removed, deleting until we get back to and can delete this VEB.
9662 **/
9663static void i40e_switch_branch_release(struct i40e_veb *branch)
9664{
9665 struct i40e_pf *pf = branch->pf;
9666 u16 branch_seid = branch->seid;
9667 u16 veb_idx = branch->idx;
9668 int i;
9669
9670 /* release any VEBs on this VEB - RECURSION */
9671 for (i = 0; i < I40E_MAX_VEB; i++) {
9672 if (!pf->veb[i])
9673 continue;
9674 if (pf->veb[i]->uplink_seid == branch->seid)
9675 i40e_switch_branch_release(pf->veb[i]);
9676 }
9677
9678 /* Release the VSIs on this VEB, but not the owner VSI.
9679 *
9680 * NOTE: Removing the last VSI on a VEB has the SIDE EFFECT of removing
9681 * the VEB itself, so don't use (*branch) after this loop.
9682 */
505682cd 9683 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9684 if (!pf->vsi[i])
9685 continue;
9686 if (pf->vsi[i]->uplink_seid == branch_seid &&
9687 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
9688 i40e_vsi_release(pf->vsi[i]);
9689 }
9690 }
9691
9692 /* There's one corner case where the VEB might not have been
9693 * removed, so double check it here and remove it if needed.
9694 * This case happens if the veb was created from the debugfs
9695 * commands and no VSIs were added to it.
9696 */
9697 if (pf->veb[veb_idx])
9698 i40e_veb_release(pf->veb[veb_idx]);
9699}
9700
9701/**
9702 * i40e_veb_clear - remove veb struct
9703 * @veb: the veb to remove
9704 **/
9705static void i40e_veb_clear(struct i40e_veb *veb)
9706{
9707 if (!veb)
9708 return;
9709
9710 if (veb->pf) {
9711 struct i40e_pf *pf = veb->pf;
9712
9713 mutex_lock(&pf->switch_mutex);
9714 if (pf->veb[veb->idx] == veb)
9715 pf->veb[veb->idx] = NULL;
9716 mutex_unlock(&pf->switch_mutex);
9717 }
9718
9719 kfree(veb);
9720}
9721
9722/**
9723 * i40e_veb_release - Delete a VEB and free its resources
9724 * @veb: the VEB being removed
9725 **/
9726void i40e_veb_release(struct i40e_veb *veb)
9727{
9728 struct i40e_vsi *vsi = NULL;
9729 struct i40e_pf *pf;
9730 int i, n = 0;
9731
9732 pf = veb->pf;
9733
9734 /* find the remaining VSI and check for extras */
505682cd 9735 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 9736 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
9737 n++;
9738 vsi = pf->vsi[i];
9739 }
9740 }
9741 if (n != 1) {
9742 dev_info(&pf->pdev->dev,
9743 "can't remove VEB %d with %d VSIs left\n",
9744 veb->seid, n);
9745 return;
9746 }
9747
9748 /* move the remaining VSI to uplink veb */
9749 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
9750 if (veb->uplink_seid) {
9751 vsi->uplink_seid = veb->uplink_seid;
9752 if (veb->uplink_seid == pf->mac_seid)
9753 vsi->veb_idx = I40E_NO_VEB;
9754 else
9755 vsi->veb_idx = veb->veb_idx;
9756 } else {
9757 /* floating VEB */
9758 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
9759 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
9760 }
9761
9762 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
9763 i40e_veb_clear(veb);
41c445ff
JB		 9764}
9765
9766/**
9767 * i40e_add_veb - create the VEB in the switch
9768 * @veb: the VEB to be instantiated
9769 * @vsi: the controlling VSI
9770 **/
9771static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
9772{
f1c7e72e 9773 struct i40e_pf *pf = veb->pf;
92faef85 9774 bool is_default = veb->pf->cur_promisc;
e1c51b95 9775 bool is_cloud = false;
41c445ff
JB		 9776 int ret;
9777
9778 /* get a VEB from the hardware */
f1c7e72e 9779 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
e1c51b95
KS		 9780 veb->enabled_tc, is_default,
9781 is_cloud, &veb->seid, NULL);
41c445ff 9782 if (ret) {
f1c7e72e
SN		 9783 dev_info(&pf->pdev->dev,
9784 "couldn't add VEB, err %s aq_err %s\n",
9785 i40e_stat_str(&pf->hw, ret),
9786 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9787 return -EPERM;
9788 }
9789
9790 /* get statistics counter */
f1c7e72e 9791 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
41c445ff
JB		 9792 &veb->stats_idx, NULL, NULL, NULL);
9793 if (ret) {
f1c7e72e
SN		 9794 dev_info(&pf->pdev->dev,
9795 "couldn't get VEB statistics idx, err %s aq_err %s\n",
9796 i40e_stat_str(&pf->hw, ret),
9797 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 9798 return -EPERM;
9799 }
9800 ret = i40e_veb_get_bw_info(veb);
9801 if (ret) {
f1c7e72e
SN		 9802 dev_info(&pf->pdev->dev,
9803 "couldn't get VEB bw info, err %s aq_err %s\n",
9804 i40e_stat_str(&pf->hw, ret),
9805 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9806 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
41c445ff
JB		 9807 return -ENOENT;
9808 }
9809
9810 vsi->uplink_seid = veb->seid;
9811 vsi->veb_idx = veb->idx;
9812 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
9813
9814 return 0;
9815}
9816
9817/**
9818 * i40e_veb_setup - Set up a VEB
9819 * @pf: board private structure
9820 * @flags: VEB setup flags
9821 * @uplink_seid: the switch element to link to
9822 * @vsi_seid: the initial VSI seid
9823 * @enabled_tc: Enabled TC bit-map
9824 *
9825 * This allocates the sw VEB structure and links it into the switch
9826 * It is possible and legal for this to be a duplicate of an already
9827 * existing VEB. It is also possible for both uplink and vsi seids
9828 * to be zero, in order to create a floating VEB.
9829 *
9830 * Returns pointer to the successfully allocated VEB sw struct on
9831 * success, otherwise returns NULL on failure.
9832 **/
9833struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
9834 u16 uplink_seid, u16 vsi_seid,
9835 u8 enabled_tc)
9836{
9837 struct i40e_veb *veb, *uplink_veb = NULL;
9838 int vsi_idx, veb_idx;
9839 int ret;
9840
9841 /* if one seid is 0, the other must be 0 to create a floating relay */
9842 if ((uplink_seid == 0 || vsi_seid == 0) &&
9843 (uplink_seid + vsi_seid != 0)) {
9844 dev_info(&pf->pdev->dev,
9845 "one, not both seid's are 0: uplink=%d vsi=%d\n",
9846 uplink_seid, vsi_seid);
9847 return NULL;
9848 }
9849
9850 /* make sure there is such a vsi and uplink */
505682cd 9851 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
41c445ff
JB		 9852 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
9853 break;
505682cd 9854 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
41c445ff
JB		 9855 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
9856 vsi_seid);
9857 return NULL;
9858 }
9859
9860 if (uplink_seid && uplink_seid != pf->mac_seid) {
9861 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
9862 if (pf->veb[veb_idx] &&
9863 pf->veb[veb_idx]->seid == uplink_seid) {
9864 uplink_veb = pf->veb[veb_idx];
9865 break;
9866 }
9867 }
9868 if (!uplink_veb) {
9869 dev_info(&pf->pdev->dev,
9870 "uplink seid %d not found\n", uplink_seid);
9871 return NULL;
9872 }
9873 }
9874
9875 /* get veb sw struct */
9876 veb_idx = i40e_veb_mem_alloc(pf);
9877 if (veb_idx < 0)
9878 goto err_alloc;
9879 veb = pf->veb[veb_idx];
9880 veb->flags = flags;
9881 veb->uplink_seid = uplink_seid;
9882 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
9883 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
9884
9885 /* create the VEB in the switch */
9886 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
9887 if (ret)
9888 goto err_veb;
1bb8b935
SN		 9889 if (vsi_idx == pf->lan_vsi)
9890 pf->lan_veb = veb->idx;
41c445ff
JB		 9891
9892 return veb;
9893
9894err_veb:
9895 i40e_veb_clear(veb);
9896err_alloc:
9897 return NULL;
9898}
9899
9900/**
b40c82e6 9901 * i40e_setup_pf_switch_element - set PF vars based on switch type
41c445ff
JB		 9902 * @pf: board private structure
9903 * @ele: element we are building info from
9904 * @num_reported: total number of elements
9905 * @printconfig: should we print the contents
9906 *
9907 * helper function to assist in extracting a few useful SEID values.
9908 **/
9909static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
9910 struct i40e_aqc_switch_config_element_resp *ele,
9911 u16 num_reported, bool printconfig)
9912{
9913 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
9914 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
9915 u8 element_type = ele->element_type;
9916 u16 seid = le16_to_cpu(ele->seid);
9917
9918 if (printconfig)
9919 dev_info(&pf->pdev->dev,
9920 "type=%d seid=%d uplink=%d downlink=%d\n",
9921 element_type, seid, uplink_seid, downlink_seid);
9922
9923 switch (element_type) {
9924 case I40E_SWITCH_ELEMENT_TYPE_MAC:
9925 pf->mac_seid = seid;
9926 break;
9927 case I40E_SWITCH_ELEMENT_TYPE_VEB:
9928 /* Main VEB? */
9929 if (uplink_seid != pf->mac_seid)
9930 break;
9931 if (pf->lan_veb == I40E_NO_VEB) {
9932 int v;
9933
9934 /* find existing or else empty VEB */
9935 for (v = 0; v < I40E_MAX_VEB; v++) {
9936 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
9937 pf->lan_veb = v;
9938 break;
9939 }
9940 }
9941 if (pf->lan_veb == I40E_NO_VEB) {
9942 v = i40e_veb_mem_alloc(pf);
9943 if (v < 0)
9944 break;
9945 pf->lan_veb = v;
9946 }
9947 }
9948
9949 pf->veb[pf->lan_veb]->seid = seid;
9950 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
9951 pf->veb[pf->lan_veb]->pf = pf;
9952 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
9953 break;
9954 case I40E_SWITCH_ELEMENT_TYPE_VSI:
9955 if (num_reported != 1)
9956 break;
9957 /* This is immediately after a reset so we can assume this is
9958 * the PF's VSI
9959 */
9960 pf->mac_seid = uplink_seid;
9961 pf->pf_seid = downlink_seid;
9962 pf->main_vsi_seid = seid;
9963 if (printconfig)
9964 dev_info(&pf->pdev->dev,
9965 "pf_seid=%d main_vsi_seid=%d\n",
9966 pf->pf_seid, pf->main_vsi_seid);
9967 break;
9968 case I40E_SWITCH_ELEMENT_TYPE_PF:
9969 case I40E_SWITCH_ELEMENT_TYPE_VF:
9970 case I40E_SWITCH_ELEMENT_TYPE_EMP:
9971 case I40E_SWITCH_ELEMENT_TYPE_BMC:
9972 case I40E_SWITCH_ELEMENT_TYPE_PE:
9973 case I40E_SWITCH_ELEMENT_TYPE_PA:
9974 /* ignore these for now */
9975 break;
9976 default:
9977 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
9978 element_type, seid);
9979 break;
9980 }
9981}
9982
9983/**
9984 * i40e_fetch_switch_configuration - Get switch config from firmware
9985 * @pf: board private structure
9986 * @printconfig: should we print the contents
9987 *
9988 * Get the current switch configuration from the device and
9989 * extract a few useful SEID values.
9990 **/
9991int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
9992{
9993 struct i40e_aqc_get_switch_config_resp *sw_config;
9994 u16 next_seid = 0;
9995 int ret = 0;
9996 u8 *aq_buf;
9997 int i;
9998
9999 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
10000 if (!aq_buf)
10001 return -ENOMEM;
10002
10003 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
10004 do {
10005 u16 num_reported, num_total;
10006
10007 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
10008 I40E_AQ_LARGE_BUF,
10009 &next_seid, NULL);
10010 if (ret) {
10011 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10012 "get switch config failed err %s aq_err %s\n",
10013 i40e_stat_str(&pf->hw, ret),
10014 i40e_aq_str(&pf->hw,
10015 pf->hw.aq.asq_last_status));
41c445ff
JB		 10016 kfree(aq_buf);
10017 return -ENOENT;
10018 }
10019
10020 num_reported = le16_to_cpu(sw_config->header.num_reported);
10021 num_total = le16_to_cpu(sw_config->header.num_total);
10022
10023 if (printconfig)
10024 dev_info(&pf->pdev->dev,
10025 "header: %d reported %d total\n",
10026 num_reported, num_total);
10027
41c445ff
JB		 10028 for (i = 0; i < num_reported; i++) {
10029 struct i40e_aqc_switch_config_element_resp *ele =
10030 &sw_config->element[i];
10031
10032 i40e_setup_pf_switch_element(pf, ele, num_reported,
10033 printconfig);
10034 }
10035 } while (next_seid != 0);
10036
10037 kfree(aq_buf);
10038 return ret;
10039}
10040
10041/**
10042 * i40e_setup_pf_switch - Setup the HW switch on startup or after reset
10043 * @pf: board private structure
bc7d338f 10044 * @reinit: if the Main VSI needs to re-initialized.
41c445ff
JB		 10045 *
10046 * Returns 0 on success, negative value on failure
10047 **/
bc7d338f 10048static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
41c445ff
JB		 10049{
10050 int ret;
10051
10052 /* find out what's out there already */
10053 ret = i40e_fetch_switch_configuration(pf, false);
10054 if (ret) {
10055 dev_info(&pf->pdev->dev,
f1c7e72e
SN		 10056 "couldn't fetch switch config, err %s aq_err %s\n",
10057 i40e_stat_str(&pf->hw, ret),
10058 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
41c445ff
JB		 10059 return ret;
10060 }
10061 i40e_pf_reset_stats(pf);
10062
41c445ff 10063 /* first time setup */
bc7d338f 10064 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
41c445ff
JB		 10065 struct i40e_vsi *vsi = NULL;
10066 u16 uplink_seid;
10067
10068 /* Set up the PF VSI associated with the PF's main VSI
10069 * that is already in the HW switch
10070 */
10071 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
10072 uplink_seid = pf->veb[pf->lan_veb]->seid;
10073 else
10074 uplink_seid = pf->mac_seid;
bc7d338f
ASJ		 10075 if (pf->lan_vsi == I40E_NO_VSI)
10076 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
10077 else if (reinit)
10078 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
41c445ff
JB		 10079 if (!vsi) {
10080 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
10081 i40e_fdir_teardown(pf);
10082 return -EAGAIN;
10083 }
41c445ff
JB		 10084 } else {
10085 /* force a reset of TC and queue layout configurations */
10086 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
6995b36c 10087
41c445ff
JB		 10088 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
10089 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
10090 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
10091 }
10092 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
10093
cbf61325
ASJ		 10094 i40e_fdir_sb_setup(pf);
10095
41c445ff
JB		 10096 /* Setup static PF queue filter control settings */
10097 ret = i40e_setup_pf_filter_control(pf);
10098 if (ret) {
10099 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
10100 ret);
10101 /* Failure here should not stop continuing other steps */
10102 }
10103
10104 /* enable RSS in the HW, even for only one queue, as the stack can use
10105 * the hash
10106 */
10107 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
043dd650 10108 i40e_pf_config_rss(pf);
41c445ff
JB		 10109
10110 /* fill in link information and enable LSE reporting */
0a862b43 10111 i40e_update_link_info(&pf->hw);
a34a6711
MW		 10112 i40e_link_event(pf);
10113
d52c20b7 10114 /* Initialize user-specific link properties */
41c445ff
JB		 10115 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
10116 I40E_AQ_AN_COMPLETED) ? true : false);
d52c20b7 10117
beb0dff1
JK		 10118 i40e_ptp_init(pf);
10119
41c445ff
JB		 10120 return ret;
10121}
10122
41c445ff
JB		 10123/**
10124 * i40e_determine_queue_usage - Work out queue distribution
10125 * @pf: board private structure
10126 **/
10127static void i40e_determine_queue_usage(struct i40e_pf *pf)
10128{
41c445ff
JB		 10129 int queues_left;
10130
10131 pf->num_lan_qps = 0;
38e00438
VD		 10132#ifdef I40E_FCOE
10133 pf->num_fcoe_qps = 0;
10134#endif
41c445ff
JB		 10135
10136 /* Find the max queues to be put into basic use. We'll always be
10137 * using TC0, whether or not DCB is running, and TC0 will get the
10138 * big RSS set.
10139 */
10140 queues_left = pf->hw.func_caps.num_tx_qp;
10141
cbf61325 10142 if ((queues_left == 1) ||
9aa7e935 10143 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
41c445ff
JB		 10144 /* one qp for PF, no queues for anything else */
10145 queues_left = 0;
acd65448 10146 pf->alloc_rss_size = pf->num_lan_qps = 1;
41c445ff
JB		 10147
10148 /* make sure all the fancies are disabled */
60ea5f83 10149 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10150#ifdef I40E_FCOE
10151 I40E_FLAG_FCOE_ENABLED |
10152#endif
60ea5f83
JB		 10153 I40E_FLAG_FD_SB_ENABLED |
10154 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10155 I40E_FLAG_DCB_CAPABLE |
60ea5f83
JB		 10156 I40E_FLAG_SRIOV_ENABLED |
10157 I40E_FLAG_VMDQ_ENABLED);
9aa7e935
FZ		 10158 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
10159 I40E_FLAG_FD_SB_ENABLED |
bbe7d0e0 10160 I40E_FLAG_FD_ATR_ENABLED |
4d9b6043 10161 I40E_FLAG_DCB_CAPABLE))) {
9aa7e935 10162 /* one qp for PF */
acd65448 10163 pf->alloc_rss_size = pf->num_lan_qps = 1;
9aa7e935
FZ		 10164 queues_left -= pf->num_lan_qps;
10165
10166 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
38e00438
VD		 10167#ifdef I40E_FCOE
10168 I40E_FLAG_FCOE_ENABLED |
10169#endif
9aa7e935
FZ		 10170 I40E_FLAG_FD_SB_ENABLED |
10171 I40E_FLAG_FD_ATR_ENABLED |
10172 I40E_FLAG_DCB_ENABLED |
10173 I40E_FLAG_VMDQ_ENABLED);
41c445ff 10174 } else {
cbf61325 10175 /* Not enough queues for all TCs */
4d9b6043 10176 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
cbf61325 10177 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
4d9b6043 10178 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
cbf61325
ASJ		 10179 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
10180 }
9a3bd2f1
ASJ		 10181 pf->num_lan_qps = max_t(int, pf->rss_size_max,
10182 num_online_cpus());
10183 pf->num_lan_qps = min_t(int, pf->num_lan_qps,
10184 pf->hw.func_caps.num_tx_qp);
10185
cbf61325
ASJ		 10186 queues_left -= pf->num_lan_qps;
10187 }
10188
38e00438
VD		 10189#ifdef I40E_FCOE
10190 if (pf->flags & I40E_FLAG_FCOE_ENABLED) {
10191 if (I40E_DEFAULT_FCOE <= queues_left) {
10192 pf->num_fcoe_qps = I40E_DEFAULT_FCOE;
10193 } else if (I40E_MINIMUM_FCOE <= queues_left) {
10194 pf->num_fcoe_qps = I40E_MINIMUM_FCOE;
10195 } else {
10196 pf->num_fcoe_qps = 0;
10197 pf->flags &= ~I40E_FLAG_FCOE_ENABLED;
10198 dev_info(&pf->pdev->dev, "not enough queues for FCoE. FCoE feature will be disabled\n");
10199 }
10200
10201 queues_left -= pf->num_fcoe_qps;
10202 }
10203
10204#endif
cbf61325
ASJ		 10205 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10206 if (queues_left > 1) {
10207 queues_left -= 1; /* save 1 queue for FD */
10208 } else {
10209 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10210 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
10211 }
41c445ff
JB		 10212 }
10213
10214 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10215 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
cbf61325
ASJ		 10216 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
10217 (queues_left / pf->num_vf_qps));
41c445ff
JB		 10218 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
10219 }
10220
10221 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10222 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
10223 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
10224 (queues_left / pf->num_vmdq_qps));
10225 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
10226 }
10227
f8ff1464 10228 pf->queues_left = queues_left;
8279e495
NP		 10229 dev_dbg(&pf->pdev->dev,
10230 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
10231 pf->hw.func_caps.num_tx_qp,
10232 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
acd65448
HZ		 10233 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
10234 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
10235 queues_left);
38e00438 10236#ifdef I40E_FCOE
8279e495 10237 dev_dbg(&pf->pdev->dev, "fcoe queues = %d\n", pf->num_fcoe_qps);
38e00438 10238#endif
41c445ff
JB		 10239}
10240
10241/**
10242 * i40e_setup_pf_filter_control - Setup PF static filter control
10243 * @pf: PF to be setup
10244 *
b40c82e6 10245 * i40e_setup_pf_filter_control sets up a PF's initial filter control
41c445ff
JB		 10246 * settings. If PE/FCoE are enabled then it will also set the per PF
10247 * based filter sizes required for them. It also enables Flow director,
10248 * ethertype and macvlan type filter settings for the pf.
10249 *
10250 * Returns 0 on success, negative on failure
10251 **/
10252static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
10253{
10254 struct i40e_filter_control_settings *settings = &pf->filter_settings;
10255
10256 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
10257
10258 /* Flow Director is enabled */
60ea5f83 10259 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
41c445ff
JB		 10260 settings->enable_fdir = true;
10261
10262 /* Ethtype and MACVLAN filters enabled for PF */
10263 settings->enable_ethtype = true;
10264 settings->enable_macvlan = true;
10265
10266 if (i40e_set_filter_control(&pf->hw, settings))
10267 return -ENOENT;
10268
10269 return 0;
10270}
10271
0c22b3dd 10272#define INFO_STRING_LEN 255
7fd89545 10273#define REMAIN(__x) (INFO_STRING_LEN - (__x))
0c22b3dd
JB		 10274static void i40e_print_features(struct i40e_pf *pf)
10275{
10276 struct i40e_hw *hw = &pf->hw;
3b195843
JP		 10277 char *buf;
10278 int i;
0c22b3dd 10279
3b195843
JP		 10280 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
10281 if (!buf)
0c22b3dd 10282 return;
0c22b3dd 10283
3b195843 10284 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
0c22b3dd 10285#ifdef CONFIG_PCI_IOV
3b195843 10286 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
0c22b3dd 10287#endif
3b195843 10288 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d RX: %s",
7fd89545
SN		 10289 pf->hw.func_caps.num_vsis,
10290 pf->vsi[pf->lan_vsi]->num_queue_pairs,
10291 pf->flags & I40E_FLAG_RX_PS_ENABLED ? "PS" : "1BUF");
0c22b3dd
JB		 10292
10293 if (pf->flags & I40E_FLAG_RSS_ENABLED)
3b195843 10294 i += snprintf(&buf[i], REMAIN(i), " RSS");
0c22b3dd 10295 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
3b195843 10296 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
c6423ff1 10297 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
3b195843
JP		 10298 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
10299 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
c6423ff1 10300 }
4d9b6043 10301 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
3b195843 10302 i += snprintf(&buf[i], REMAIN(i), " DCB");
ce6fcb3f 10303#if IS_ENABLED(CONFIG_VXLAN)
3b195843 10304 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
ce6fcb3f 10305#endif
0c22b3dd 10306 if (pf->flags & I40E_FLAG_PTP)
3b195843 10307 i += snprintf(&buf[i], REMAIN(i), " PTP");
38e00438
VD		 10308#ifdef I40E_FCOE
10309 if (pf->flags & I40E_FLAG_FCOE_ENABLED)
3b195843 10310 i += snprintf(&buf[i], REMAIN(i), " FCOE");
38e00438 10311#endif
6dec1017 10312 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
3b195843 10313 i += snprintf(&buf[i], REMAIN(i), " VEB");
6dec1017 10314 else
3b195843 10315 i += snprintf(&buf[i], REMAIN(i), " VEPA");
0c22b3dd 10316
3b195843
JP		 10317 dev_info(&pf->pdev->dev, "%s\n", buf);
10318 kfree(buf);
7fd89545 10319 WARN_ON(i > INFO_STRING_LEN);
0c22b3dd
JB		 10320}
10321
41c445ff
JB		 10322/**
10323 * i40e_probe - Device initialization routine
10324 * @pdev: PCI device information struct
10325 * @ent: entry in i40e_pci_tbl
10326 *
b40c82e6
JK		 10327 * i40e_probe initializes a PF identified by a pci_dev structure.
10328 * The OS initialization, configuring of the PF private structure,
41c445ff
JB		 10329 * and a hardware reset occur.
10330 *
10331 * Returns 0 on success, negative on failure
10332 **/
10333static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10334{
e827845c 10335 struct i40e_aq_get_phy_abilities_resp abilities;
41c445ff
JB		 10336 struct i40e_pf *pf;
10337 struct i40e_hw *hw;
93cd765b 10338 static u16 pfs_found;
1d5109d1 10339 u16 wol_nvm_bits;
d4dfb81a 10340 u16 link_status;
6f66a484 10341 int err;
41c445ff 10342 u32 len;
4f2f017c 10343 u32 val;
8a9eb7d3 10344 u32 i;
58fc3267 10345 u8 set_fc_aq_fail;
41c445ff
JB		 10346
10347 err = pci_enable_device_mem(pdev);
10348 if (err)
10349 return err;
10350
10351 /* set up for high or low dma */
6494294f 10352 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6494294f 10353 if (err) {
e3e3bfdd
JS		 10354 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10355 if (err) {
10356 dev_err(&pdev->dev,
10357 "DMA configuration failed: 0x%x\n", err);
10358 goto err_dma;
10359 }
41c445ff
JB		 10360 }
10361
10362 /* set up pci connections */
10363 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
10364 IORESOURCE_MEM), i40e_driver_name);
10365 if (err) {
10366 dev_info(&pdev->dev,
10367 "pci_request_selected_regions failed %d\n", err);
10368 goto err_pci_reg;
10369 }
10370
10371 pci_enable_pcie_error_reporting(pdev);
10372 pci_set_master(pdev);
10373
10374 /* Now that we have a PCI connection, we need to do the
10375 * low level device setup. This is primarily setting up
10376 * the Admin Queue structures and then querying for the
10377 * device's current profile information.
10378 */
10379 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
10380 if (!pf) {
10381 err = -ENOMEM;
10382 goto err_pf_alloc;
10383 }
10384 pf->next_vsi = 0;
10385 pf->pdev = pdev;
10386 set_bit(__I40E_DOWN, &pf->state);
10387
10388 hw = &pf->hw;
10389 hw->back = pf;
232f4706 10390
2ac8b675
SN		 10391 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
10392 I40E_MAX_CSR_SPACE);
232f4706 10393
2ac8b675 10394 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
41c445ff
JB		 10395 if (!hw->hw_addr) {
10396 err = -EIO;
10397 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
10398 (unsigned int)pci_resource_start(pdev, 0),
2ac8b675 10399 pf->ioremap_len, err);
41c445ff
JB		 10400 goto err_ioremap;
10401 }
10402 hw->vendor_id = pdev->vendor;
10403 hw->device_id = pdev->device;
10404 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
10405 hw->subsystem_vendor_id = pdev->subsystem_vendor;
10406 hw->subsystem_device_id = pdev->subsystem_device;
10407 hw->bus.device = PCI_SLOT(pdev->devfn);
10408 hw->bus.func = PCI_FUNC(pdev->devfn);
93cd765b 10409 pf->instance = pfs_found;
41c445ff 10410
5b5faa43
SN		 10411 if (debug != -1) {
10412 pf->msg_enable = pf->hw.debug_mask;
10413 pf->msg_enable = debug;
10414 }
10415
7134f9ce
JB		 10416 /* do a special CORER for clearing PXE mode once at init */
10417 if (hw->revision_id == 0 &&
10418 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
10419 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
10420 i40e_flush(hw);
10421 msleep(200);
10422 pf->corer_count++;
10423
10424 i40e_clear_pxe_mode(hw);
10425 }
10426
41c445ff 10427 /* Reset here to make sure all is clean and to define PF 'n' */
838d41d9 10428 i40e_clear_hw(hw);
41c445ff
JB		 10429 err = i40e_pf_reset(hw);
10430 if (err) {
10431 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
10432 goto err_pf_reset;
10433 }
10434 pf->pfr_count++;
10435
10436 hw->aq.num_arq_entries = I40E_AQ_LEN;
10437 hw->aq.num_asq_entries = I40E_AQ_LEN;
10438 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10439 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
10440 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
b2008cbf 10441
b294ac70 10442 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
b2008cbf
CW		 10443 "%s-%s:misc",
10444 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
41c445ff
JB		 10445
10446 err = i40e_init_shared_code(hw);
10447 if (err) {
b2a75c58
ASJ		 10448 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
10449 err);
41c445ff
JB		 10450 goto err_pf_reset;
10451 }
10452
d52c20b7
JB		 10453 /* set up a default setting for link flow control */
10454 pf->hw.fc.requested_mode = I40E_FC_NONE;
10455
41c445ff 10456 err = i40e_init_adminq(hw);
2b2426a7
CW		 10457 if (err) {
10458 if (err == I40E_ERR_FIRMWARE_API_VERSION)
10459 dev_info(&pdev->dev,
10460 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
10461 else
10462 dev_info(&pdev->dev,
10463 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
10464
10465 goto err_pf_reset;
10466 }
f0b44440 10467
6dec1017
SN		 10468 /* provide nvm, fw, api versions */
10469 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
10470 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
10471 hw->aq.api_maj_ver, hw->aq.api_min_ver,
10472 i40e_nvm_version_str(hw));
f0b44440 10473
7aa67613
CS		 10474 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
10475 hw->aq.api_min_ver > I40E_FW_API_VERSION_MINOR)
278b6f62 10476 dev_info(&pdev->dev,
7aa67613
CS		 10477 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
10478 else if (hw->aq.api_maj_ver < I40E_FW_API_VERSION_MAJOR ||
10479 hw->aq.api_min_ver < (I40E_FW_API_VERSION_MINOR - 1))
278b6f62 10480 dev_info(&pdev->dev,
7aa67613 10481 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
278b6f62 10482
4eb3f768
SN		 10483 i40e_verify_eeprom(pf);
10484
2c5fe33b
JB		 10485 /* Rev 0 hardware was never productized */
10486 if (hw->revision_id < 1)
10487 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
10488
6ff4ef86 10489 i40e_clear_pxe_mode(hw);
41c445ff
JB		 10490 err = i40e_get_capabilities(pf);
10491 if (err)
10492 goto err_adminq_setup;
10493
10494 err = i40e_sw_init(pf);
10495 if (err) {
10496 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
10497 goto err_sw_init;
10498 }
10499
10500 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
10501 hw->func_caps.num_rx_qp,
10502 pf->fcoe_hmc_cntx_num, pf->fcoe_hmc_filt_num);
10503 if (err) {
10504 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
10505 goto err_init_lan_hmc;
10506 }
10507
10508 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
10509 if (err) {
10510 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
10511 err = -ENOENT;
10512 goto err_configure_lan_hmc;
10513 }
10514
b686ece5
NP		 10515 /* Disable LLDP for NICs that have firmware versions lower than v4.3.
10516 * Ignore error return codes because if it was already disabled via
10517 * hardware settings this will fail
10518 */
10519 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
10520 (pf->hw.aq.fw_maj_ver < 4)) {
10521 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
10522 i40e_aq_stop_lldp(hw, true, NULL);
10523 }
10524
41c445ff 10525 i40e_get_mac_addr(hw, hw->mac.addr);
f62b5060 10526 if (!is_valid_ether_addr(hw->mac.addr)) {
41c445ff
JB		 10527 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
10528 err = -EIO;
10529 goto err_mac_addr;
10530 }
10531 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
9a173901 10532 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
1f224ad2
NP		 10533 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
10534 if (is_valid_ether_addr(hw->mac.port_addr))
10535 pf->flags |= I40E_FLAG_PORT_ID_VALID;
38e00438
VD		 10536#ifdef I40E_FCOE
10537 err = i40e_get_san_mac_addr(hw, hw->mac.san_addr);
10538 if (err)
10539 dev_info(&pdev->dev,
10540 "(non-fatal) SAN MAC retrieval failed: %d\n", err);
10541 if (!is_valid_ether_addr(hw->mac.san_addr)) {
10542 dev_warn(&pdev->dev, "invalid SAN MAC address %pM, falling back to LAN MAC\n",
10543 hw->mac.san_addr);
10544 ether_addr_copy(hw->mac.san_addr, hw->mac.addr);
10545 }
10546 dev_info(&pf->pdev->dev, "SAN MAC: %pM\n", hw->mac.san_addr);
10547#endif /* I40E_FCOE */
41c445ff
JB		 10548
10549 pci_set_drvdata(pdev, pf);
10550 pci_save_state(pdev);
4e3b35b0
NP		 10551#ifdef CONFIG_I40E_DCB
10552 err = i40e_init_pf_dcb(pf);
10553 if (err) {
aebfc816 10554 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
4d9b6043 10555 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
014269ff 10556 /* Continue without DCB enabled */
4e3b35b0
NP		 10557 }
10558#endif /* CONFIG_I40E_DCB */
41c445ff
JB		 10559
10560 /* set up periodic task facility */
10561 setup_timer(&pf->service_timer, i40e_service_timer, (unsigned long)pf);
10562 pf->service_timer_period = HZ;
10563
10564 INIT_WORK(&pf->service_task, i40e_service_task);
10565 clear_bit(__I40E_SERVICE_SCHED, &pf->state);
10566 pf->flags |= I40E_FLAG_NEED_LINK_UPDATE;
41c445ff 10567
1d5109d1
SN		 10568 /* NVM bit on means WoL disabled for the port */
10569 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
10570 if ((1 << hw->port) & wol_nvm_bits || hw->partition_id != 1)
10571 pf->wol_en = false;
10572 else
10573 pf->wol_en = true;
8e2773ae
SN		 10574 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
10575
41c445ff
JB		 10576 /* set up the main switch operations */
10577 i40e_determine_queue_usage(pf);
c1147280
JB		 10578 err = i40e_init_interrupt_scheme(pf);
10579 if (err)
10580 goto err_switch_setup;
41c445ff 10581
505682cd
MW		 10582 /* The number of VSIs reported by the FW is the minimum guaranteed
10583 * to us; HW supports far more and we share the remaining pool with
10584 * the other PFs. We allocate space for more than the guarantee with
10585 * the understanding that we might not get them all later.
41c445ff 10586 */
505682cd
MW		 10587 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
10588 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
10589 else
10590 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
10591
10592 /* Set up the *vsi struct and our local tracking of the MAIN PF vsi. */
10593 len = sizeof(struct i40e_vsi *) * pf->num_alloc_vsi;
41c445ff 10594 pf->vsi = kzalloc(len, GFP_KERNEL);
ed87ac09
WY		 10595 if (!pf->vsi) {
10596 err = -ENOMEM;
41c445ff 10597 goto err_switch_setup;
ed87ac09 10598 }
41c445ff 10599
fa11cb3d
ASJ		 10600#ifdef CONFIG_PCI_IOV
10601 /* prep for VF support */
10602 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
10603 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10604 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
10605 if (pci_num_vf(pdev))
10606 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
10607 }
10608#endif
bc7d338f 10609 err = i40e_setup_pf_switch(pf, false);
41c445ff
JB		 10610 if (err) {
10611 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
10612 goto err_vsis;
10613 }
58fc3267
HZ		 10614
10615 /* Make sure flow control is set according to current settings */
10616 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
10617 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
10618 dev_dbg(&pf->pdev->dev,
10619 "Set fc with err %s aq_err %s on get_phy_cap\n",
10620 i40e_stat_str(hw, err),
10621 i40e_aq_str(hw, hw->aq.asq_last_status));
10622 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
10623 dev_dbg(&pf->pdev->dev,
10624 "Set fc with err %s aq_err %s on set_phy_config\n",
10625 i40e_stat_str(hw, err),
10626 i40e_aq_str(hw, hw->aq.asq_last_status));
10627 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
10628 dev_dbg(&pf->pdev->dev,
10629 "Set fc with err %s aq_err %s on get_link_info\n",
10630 i40e_stat_str(hw, err),
10631 i40e_aq_str(hw, hw->aq.asq_last_status));
10632
8a9eb7d3 10633 /* if FDIR VSI was set up, start it now */
505682cd 10634 for (i = 0; i < pf->num_alloc_vsi; i++) {
8a9eb7d3
SN		 10635 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
10636 i40e_vsi_open(pf->vsi[i]);
10637 break;
10638 }
10639 }
41c445ff 10640
7e2453fe
JB		 10641 /* driver is only interested in link up/down and module qualification
10642 * reports from firmware
10643 */
10644 err = i40e_aq_set_phy_int_mask(&pf->hw,
10645 I40E_AQ_EVENT_LINK_UPDOWN |
10646 I40E_AQ_EVENT_MODULE_QUAL_FAIL, NULL);
10647 if (err)
f1c7e72e
SN		 10648 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
10649 i40e_stat_str(&pf->hw, err),
10650 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7e2453fe 10651
4f2f017c
ASJ		 10652 /* Reconfigure hardware for allowing smaller MSS in the case
10653 * of TSO, so that we avoid the MDD being fired and causing
10654 * a reset in the case of small MSS+TSO.
10655 */
10656 val = rd32(hw, I40E_REG_MSS);
10657 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
10658 val &= ~I40E_REG_MSS_MIN_MASK;
10659 val |= I40E_64BYTE_MSS;
10660 wr32(hw, I40E_REG_MSS, val);
10661 }
10662
025b4a54
ASJ		 10663 if (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
10664 (pf->hw.aq.fw_maj_ver < 4)) {
10665 msleep(75);
10666 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
10667 if (err)
f1c7e72e
SN		 10668 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
10669 i40e_stat_str(&pf->hw, err),
10670 i40e_aq_str(&pf->hw,
10671 pf->hw.aq.asq_last_status));
cafa2ee6 10672 }
41c445ff
JB		 10673 /* The main driver is (mostly) up and happy. We need to set this state
10674 * before setting up the misc vector or we get a race and the vector
10675 * ends up disabled forever.
10676 */
10677 clear_bit(__I40E_DOWN, &pf->state);
10678
10679 /* In case of MSIX we are going to setup the misc vector right here
10680 * to handle admin queue events etc. In case of legacy and MSI
10681 * the misc functionality and queue processing is combined in
10682 * the same vector and that gets setup at open.
10683 */
10684 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10685 err = i40e_setup_misc_vector(pf);
10686 if (err) {
10687 dev_info(&pdev->dev,
10688 "setup of misc vector failed: %d\n", err);
10689 goto err_vsis;
10690 }
10691 }
10692
df805f62 10693#ifdef CONFIG_PCI_IOV
41c445ff
JB		 10694 /* prep for VF support */
10695 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
4eb3f768
SN		 10696 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10697 !test_bit(__I40E_BAD_EEPROM, &pf->state)) {
41c445ff
JB		 10698 u32 val;
10699
10700 /* disable link interrupts for VFs */
10701 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
10702 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
10703 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
10704 i40e_flush(hw);
4aeec010
MW		 10705
10706 if (pci_num_vf(pdev)) {
10707 dev_info(&pdev->dev,
10708 "Active VFs found, allocating resources.\n");
10709 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
10710 if (err)
10711 dev_info(&pdev->dev,
10712 "Error %d allocating resources for existing VFs\n",
10713 err);
10714 }
41c445ff 10715 }
df805f62 10716#endif /* CONFIG_PCI_IOV */
41c445ff 10717
93cd765b
ASJ		 10718 pfs_found++;
10719
41c445ff
JB		 10720 i40e_dbg_pf_init(pf);
10721
10722 /* tell the firmware that we're starting */
44033fac 10723 i40e_send_version(pf);
41c445ff
JB		 10724
10725 /* since everything's happy, start the service_task timer */
10726 mod_timer(&pf->service_timer,
10727 round_jiffies(jiffies + pf->service_timer_period));
10728
38e00438
VD		 10729#ifdef I40E_FCOE
10730 /* create FCoE interface */
10731 i40e_fcoe_vsi_setup(pf);
10732
10733#endif
3fced535
ASJ		 10734#define PCI_SPEED_SIZE 8
10735#define PCI_WIDTH_SIZE 8
10736 /* Devices on the IOSF bus do not have this information
10737 * and will report PCI Gen 1 x 1 by default so don't bother
10738 * checking them.
10739 */
10740 if (!(pf->flags & I40E_FLAG_NO_PCI_LINK_CHECK)) {
10741 char speed[PCI_SPEED_SIZE] = "Unknown";
10742 char width[PCI_WIDTH_SIZE] = "Unknown";
10743
10744 /* Get the negotiated link width and speed from PCI config
10745 * space
10746 */
10747 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
10748 &link_status);
10749
10750 i40e_set_pci_config_data(hw, link_status);
10751
10752 switch (hw->bus.speed) {
10753 case i40e_bus_speed_8000:
10754 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
10755 case i40e_bus_speed_5000:
10756 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
10757 case i40e_bus_speed_2500:
10758 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
10759 default:
10760 break;
10761 }
10762 switch (hw->bus.width) {
10763 case i40e_bus_width_pcie_x8:
10764 strncpy(width, "8", PCI_WIDTH_SIZE); break;
10765 case i40e_bus_width_pcie_x4:
10766 strncpy(width, "4", PCI_WIDTH_SIZE); break;
10767 case i40e_bus_width_pcie_x2:
10768 strncpy(width, "2", PCI_WIDTH_SIZE); break;
10769 case i40e_bus_width_pcie_x1:
10770 strncpy(width, "1", PCI_WIDTH_SIZE); break;
10771 default:
10772 break;
10773 }
10774
10775 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
10776 speed, width);
10777
10778 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
10779 hw->bus.speed < i40e_bus_speed_8000) {
10780 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
10781 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
10782 }
d4dfb81a
CS		 10783 }
10784
e827845c
CS		 10785 /* get the requested speeds from the fw */
10786 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
10787 if (err)
8279e495
NP		 10788 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
10789 i40e_stat_str(&pf->hw, err),
10790 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
e827845c
CS		 10791 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
10792
fc72dbce
CS		 10793 /* get the supported phy types from the fw */
10794 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
10795 if (err)
10796 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
10797 i40e_stat_str(&pf->hw, err),
10798 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
10799 pf->hw.phy.phy_types = le32_to_cpu(abilities.phy_type);
10800
e7358f54
ASJ		 10801 /* Add a filter to drop all Flow control frames from any VSI from being
10802 * transmitted. By doing so we stop a malicious VF from sending out
10803 * PAUSE or PFC frames and potentially controlling traffic for other
10804 * PF/VF VSIs.
10805 * The FW can still send Flow control frames if enabled.
10806 */
10807 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
10808 pf->main_vsi_seid);
10809
0c22b3dd
JB		 10810 /* print a string summarizing features */
10811 i40e_print_features(pf);
10812
41c445ff
JB		 10813 return 0;
10814
10815 /* Unwind what we've done if something failed in the setup */
10816err_vsis:
10817 set_bit(__I40E_DOWN, &pf->state);
41c445ff
JB		 10818 i40e_clear_interrupt_scheme(pf);
10819 kfree(pf->vsi);
04b03013
SN		 10820err_switch_setup:
10821 i40e_reset_interrupt_capability(pf);
41c445ff
JB		 10822 del_timer_sync(&pf->service_timer);
10823err_mac_addr:
10824err_configure_lan_hmc:
10825 (void)i40e_shutdown_lan_hmc(hw);
10826err_init_lan_hmc:
10827 kfree(pf->qp_pile);
41c445ff
JB		 10828err_sw_init:
10829err_adminq_setup:
10830 (void)i40e_shutdown_adminq(hw);
10831err_pf_reset:
10832 iounmap(hw->hw_addr);
10833err_ioremap:
10834 kfree(pf);
10835err_pf_alloc:
10836 pci_disable_pcie_error_reporting(pdev);
10837 pci_release_selected_regions(pdev,
10838 pci_select_bars(pdev, IORESOURCE_MEM));
10839err_pci_reg:
10840err_dma:
10841 pci_disable_device(pdev);
10842 return err;
10843}
10844
10845/**
10846 * i40e_remove - Device removal routine
10847 * @pdev: PCI device information struct
10848 *
10849 * i40e_remove is called by the PCI subsystem to alert the driver
10850 * that is should release a PCI device. This could be caused by a
10851 * Hot-Plug event, or because the driver is going to be removed from
10852 * memory.
10853 **/
10854static void i40e_remove(struct pci_dev *pdev)
10855{
10856 struct i40e_pf *pf = pci_get_drvdata(pdev);
bcab2db9 10857 struct i40e_hw *hw = &pf->hw;
41c445ff 10858 i40e_status ret_code;
41c445ff
JB		 10859 int i;
10860
10861 i40e_dbg_pf_exit(pf);
10862
beb0dff1
JK		 10863 i40e_ptp_stop(pf);
10864
bcab2db9
CW		 10865 /* Disable RSS in hw */
10866 wr32(hw, I40E_PFQF_HENA(0), 0);
10867 wr32(hw, I40E_PFQF_HENA(1), 0);
10868
41c445ff
JB		 10869 /* no more scheduling of any task */
10870 set_bit(__I40E_DOWN, &pf->state);
10871 del_timer_sync(&pf->service_timer);
10872 cancel_work_sync(&pf->service_task);
33c62b34 10873 i40e_fdir_teardown(pf);
41c445ff 10874
eb2d80bc
MW		 10875 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
10876 i40e_free_vfs(pf);
10877 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
10878 }
10879
41c445ff
JB		 10880 i40e_fdir_teardown(pf);
10881
10882 /* If there is a switch structure or any orphans, remove them.
10883 * This will leave only the PF's VSI remaining.
10884 */
10885 for (i = 0; i < I40E_MAX_VEB; i++) {
10886 if (!pf->veb[i])
10887 continue;
10888
10889 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
10890 pf->veb[i]->uplink_seid == 0)
10891 i40e_switch_branch_release(pf->veb[i]);
10892 }
10893
10894 /* Now we can shutdown the PF's VSI, just before we kill
10895 * adminq and hmc.
10896 */
10897 if (pf->vsi[pf->lan_vsi])
10898 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
10899
41c445ff 10900 /* shutdown and destroy the HMC */
60442dea
SN		 10901 if (pf->hw.hmc.hmc_obj) {
10902 ret_code = i40e_shutdown_lan_hmc(&pf->hw);
10903 if (ret_code)
10904 dev_warn(&pdev->dev,
10905 "Failed to destroy the HMC resources: %d\n",
10906 ret_code);
10907 }
41c445ff
JB		 10908
10909 /* shutdown the adminq */
41c445ff
JB		 10910 ret_code = i40e_shutdown_adminq(&pf->hw);
10911 if (ret_code)
10912 dev_warn(&pdev->dev,
10913 "Failed to destroy the Admin Queue resources: %d\n",
10914 ret_code);
10915
10916 /* Clear all dynamic memory lists of rings, q_vectors, and VSIs */
10917 i40e_clear_interrupt_scheme(pf);
505682cd 10918 for (i = 0; i < pf->num_alloc_vsi; i++) {
41c445ff
JB		 10919 if (pf->vsi[i]) {
10920 i40e_vsi_clear_rings(pf->vsi[i]);
10921 i40e_vsi_clear(pf->vsi[i]);
10922 pf->vsi[i] = NULL;
10923 }
10924 }
10925
10926 for (i = 0; i < I40E_MAX_VEB; i++) {
10927 kfree(pf->veb[i]);
10928 pf->veb[i] = NULL;
10929 }
10930
10931 kfree(pf->qp_pile);
41c445ff
JB		 10932 kfree(pf->vsi);
10933
41c445ff
JB		 10934 iounmap(pf->hw.hw_addr);
10935 kfree(pf);
10936 pci_release_selected_regions(pdev,
10937 pci_select_bars(pdev, IORESOURCE_MEM));
10938
10939 pci_disable_pcie_error_reporting(pdev);
10940 pci_disable_device(pdev);
10941}
10942
10943/**
10944 * i40e_pci_error_detected - warning that something funky happened in PCI land
10945 * @pdev: PCI device information struct
10946 *
10947 * Called to warn that something happened and the error handling steps
10948 * are in progress. Allows the driver to quiesce things, be ready for
10949 * remediation.
10950 **/
10951static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
10952 enum pci_channel_state error)
10953{
10954 struct i40e_pf *pf = pci_get_drvdata(pdev);
10955
10956 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
10957
10958 /* shutdown all operations */
9007bccd
SN		 10959 if (!test_bit(__I40E_SUSPENDED, &pf->state)) {
10960 rtnl_lock();
10961 i40e_prep_for_reset(pf);
10962 rtnl_unlock();
10963 }
41c445ff
JB		 10964
10965 /* Request a slot reset */
10966 return PCI_ERS_RESULT_NEED_RESET;
10967}
10968
10969/**
10970 * i40e_pci_error_slot_reset - a PCI slot reset just happened
10971 * @pdev: PCI device information struct
10972 *
10973 * Called to find if the driver can work with the device now that
10974 * the pci slot has been reset. If a basic connection seems good
10975 * (registers are readable and have sane content) then return a
10976 * happy little PCI_ERS_RESULT_xxx.
10977 **/
10978static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
10979{
10980 struct i40e_pf *pf = pci_get_drvdata(pdev);
10981 pci_ers_result_t result;
10982 int err;
10983 u32 reg;
10984
fb43201f 10985 dev_dbg(&pdev->dev, "%s\n", __func__);
41c445ff
JB		 10986 if (pci_enable_device_mem(pdev)) {
10987 dev_info(&pdev->dev,
10988 "Cannot re-enable PCI device after reset.\n");
10989 result = PCI_ERS_RESULT_DISCONNECT;
10990 } else {
10991 pci_set_master(pdev);
10992 pci_restore_state(pdev);
10993 pci_save_state(pdev);
10994 pci_wake_from_d3(pdev, false);
10995
10996 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
10997 if (reg == 0)
10998 result = PCI_ERS_RESULT_RECOVERED;
10999 else
11000 result = PCI_ERS_RESULT_DISCONNECT;
11001 }
11002
11003 err = pci_cleanup_aer_uncorrect_error_status(pdev);
11004 if (err) {
11005 dev_info(&pdev->dev,
11006 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
11007 err);
11008 /* non-fatal, continue */
11009 }
11010
11011 return result;
11012}
11013
11014/**
11015 * i40e_pci_error_resume - restart operations after PCI error recovery
11016 * @pdev: PCI device information struct
11017 *
11018 * Called to allow the driver to bring things back up after PCI error
11019 * and/or reset recovery has finished.
11020 **/
11021static void i40e_pci_error_resume(struct pci_dev *pdev)
11022{
11023 struct i40e_pf *pf = pci_get_drvdata(pdev);
11024
fb43201f 11025 dev_dbg(&pdev->dev, "%s\n", __func__);
9007bccd
SN		 11026 if (test_bit(__I40E_SUSPENDED, &pf->state))
11027 return;
11028
11029 rtnl_lock();
41c445ff 11030 i40e_handle_reset_warning(pf);
4c4935a9 11031 rtnl_unlock();
9007bccd
SN		 11032}
11033
11034/**
11035 * i40e_shutdown - PCI callback for shutting down
11036 * @pdev: PCI device information struct
11037 **/
11038static void i40e_shutdown(struct pci_dev *pdev)
11039{
11040 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11041 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11042
11043 set_bit(__I40E_SUSPENDED, &pf->state);
11044 set_bit(__I40E_DOWN, &pf->state);
11045 rtnl_lock();
11046 i40e_prep_for_reset(pf);
11047 rtnl_unlock();
11048
8e2773ae
SN		 11049 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11050 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11051
02b42498
CS		 11052 del_timer_sync(&pf->service_timer);
11053 cancel_work_sync(&pf->service_task);
11054 i40e_fdir_teardown(pf);
11055
11056 rtnl_lock();
11057 i40e_prep_for_reset(pf);
11058 rtnl_unlock();
11059
11060 wr32(hw, I40E_PFPM_APM,
11061 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11062 wr32(hw, I40E_PFPM_WUFC,
11063 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11064
e147758d
SN		 11065 i40e_clear_interrupt_scheme(pf);
11066
9007bccd 11067 if (system_state == SYSTEM_POWER_OFF) {
8e2773ae 11068 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11069 pci_set_power_state(pdev, PCI_D3hot);
11070 }
11071}
11072
11073#ifdef CONFIG_PM
11074/**
11075 * i40e_suspend - PCI callback for moving to D3
11076 * @pdev: PCI device information struct
11077 **/
11078static int i40e_suspend(struct pci_dev *pdev, pm_message_t state)
11079{
11080 struct i40e_pf *pf = pci_get_drvdata(pdev);
8e2773ae 11081 struct i40e_hw *hw = &pf->hw;
9007bccd
SN		 11082
11083 set_bit(__I40E_SUSPENDED, &pf->state);
11084 set_bit(__I40E_DOWN, &pf->state);
3932dbfe 11085
9007bccd
SN		 11086 rtnl_lock();
11087 i40e_prep_for_reset(pf);
11088 rtnl_unlock();
11089
8e2773ae
SN		 11090 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
11091 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
11092
11093 pci_wake_from_d3(pdev, pf->wol_en);
9007bccd
SN		 11094 pci_set_power_state(pdev, PCI_D3hot);
11095
11096 return 0;
41c445ff
JB		 11097}
11098
9007bccd
SN		 11099/**
11100 * i40e_resume - PCI callback for waking up from D3
11101 * @pdev: PCI device information struct
11102 **/
11103static int i40e_resume(struct pci_dev *pdev)
11104{
11105 struct i40e_pf *pf = pci_get_drvdata(pdev);
11106 u32 err;
11107
11108 pci_set_power_state(pdev, PCI_D0);
11109 pci_restore_state(pdev);
11110 /* pci_restore_state() clears dev->state_saves, so
11111 * call pci_save_state() again to restore it.
11112 */
11113 pci_save_state(pdev);
11114
11115 err = pci_enable_device_mem(pdev);
11116 if (err) {
fb43201f 11117 dev_err(&pdev->dev, "Cannot enable PCI device from suspend\n");
9007bccd
SN		 11118 return err;
11119 }
11120 pci_set_master(pdev);
11121
11122 /* no wakeup events while running */
11123 pci_wake_from_d3(pdev, false);
11124
11125 /* handling the reset will rebuild the device state */
11126 if (test_and_clear_bit(__I40E_SUSPENDED, &pf->state)) {
11127 clear_bit(__I40E_DOWN, &pf->state);
11128 rtnl_lock();
11129 i40e_reset_and_rebuild(pf, false);
11130 rtnl_unlock();
11131 }
11132
11133 return 0;
11134}
11135
11136#endif
41c445ff
JB		 11137static const struct pci_error_handlers i40e_err_handler = {
11138 .error_detected = i40e_pci_error_detected,
11139 .slot_reset = i40e_pci_error_slot_reset,
11140 .resume = i40e_pci_error_resume,
11141};
11142
11143static struct pci_driver i40e_driver = {
11144 .name = i40e_driver_name,
11145 .id_table = i40e_pci_tbl,
11146 .probe = i40e_probe,
11147 .remove = i40e_remove,
9007bccd
SN		 11148#ifdef CONFIG_PM
11149 .suspend = i40e_suspend,
11150 .resume = i40e_resume,
11151#endif
11152 .shutdown = i40e_shutdown,
41c445ff
JB		 11153 .err_handler = &i40e_err_handler,
11154 .sriov_configure = i40e_pci_sriov_configure,
11155};
11156
11157/**
11158 * i40e_init_module - Driver registration routine
11159 *
11160 * i40e_init_module is the first routine called when the driver is
11161 * loaded. All it does is register with the PCI subsystem.
11162 **/
11163static int __init i40e_init_module(void)
11164{
11165 pr_info("%s: %s - version %s\n", i40e_driver_name,
11166 i40e_driver_string, i40e_driver_version_str);
11167 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
96664483 11168
41c445ff
JB		 11169 i40e_dbg_init();
11170 return pci_register_driver(&i40e_driver);
11171}
11172module_init(i40e_init_module);
11173
11174/**
11175 * i40e_exit_module - Driver exit cleanup routine
11176 *
11177 * i40e_exit_module is called just before the driver is removed
11178 * from memory.
11179 **/
11180static void __exit i40e_exit_module(void)
11181{
11182 pci_unregister_driver(&i40e_driver);
11183 i40e_dbg_exit();
11184}
11185module_exit(i40e_exit_module);
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