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i40e: Fix VF driver MAC address configuration
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#include "i40e_type.h"
29#include "i40e_adminq.h"
30#include "i40e_prototype.h"
31#include "i40e_virtchnl.h"
32
33/**
34 * i40e_set_mac_type - Sets MAC type
35 * @hw: pointer to the HW structure
36 *
37 * This function sets the mac type of the adapter based on the
38 * vendor ID and device ID stored in the hw structure.
39 **/
40static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
41{
42 i40e_status status = 0;
43
44 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
45 switch (hw->device_id) {
46 case I40E_SFP_XL710_DEVICE_ID:
47 case I40E_SFP_X710_DEVICE_ID:
48 case I40E_QEMU_DEVICE_ID:
49 case I40E_KX_A_DEVICE_ID:
50 case I40E_KX_B_DEVICE_ID:
51 case I40E_KX_C_DEVICE_ID:
52 case I40E_KX_D_DEVICE_ID:
53 case I40E_QSFP_A_DEVICE_ID:
54 case I40E_QSFP_B_DEVICE_ID:
55 case I40E_QSFP_C_DEVICE_ID:
56 hw->mac.type = I40E_MAC_XL710;
57 break;
58 case I40E_VF_DEVICE_ID:
59 case I40E_VF_HV_DEVICE_ID:
60 hw->mac.type = I40E_MAC_VF;
61 break;
62 default:
63 hw->mac.type = I40E_MAC_GENERIC;
64 break;
65 }
66 } else {
67 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
68 }
69
70 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
71 hw->mac.type, status);
72 return status;
73}
74
75/**
76 * i40e_debug_aq
77 * @hw: debug mask related to admin queue
78 * @cap: pointer to adminq command descriptor
79 * @buffer: pointer to command buffer
80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
84 void *buffer)
85{
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
87 u8 *aq_buffer = (u8 *)buffer;
88 u32 data[4];
89 u32 i = 0;
90
91 if ((!(mask & hw->debug_mask)) || (desc == NULL))
92 return;
93
94 i40e_debug(hw, mask,
95 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
96 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
97 aq_desc->retval);
98 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
99 aq_desc->cookie_high, aq_desc->cookie_low);
100 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
101 aq_desc->params.internal.param0,
102 aq_desc->params.internal.param1);
103 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
104 aq_desc->params.external.addr_high,
105 aq_desc->params.external.addr_low);
106
107 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
108 memset(data, 0, sizeof(data));
109 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
110 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
111 data[((i % 16) / 4)] |=
112 ((u32)aq_buffer[i]) << (8 * (i % 4));
113 if ((i % 16) == 15) {
114 i40e_debug(hw, mask,
115 "\t0x%04X %08X %08X %08X %08X\n",
116 i - 15, data[0], data[1], data[2],
117 data[3]);
118 memset(data, 0, sizeof(data));
119 }
120 }
121 if ((i % 16) != 0)
122 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
123 i - (i % 16), data[0], data[1], data[2],
124 data[3]);
125 }
126}
127
128/**
129 * i40e_init_shared_code - Initialize the shared code
130 * @hw: pointer to hardware structure
131 *
132 * This assigns the MAC type and PHY code and inits the NVM.
133 * Does not touch the hardware. This function must be called prior to any
134 * other function in the shared code. The i40e_hw structure should be
135 * memset to 0 prior to calling this function. The following fields in
136 * hw structure should be filled in prior to calling this function:
137 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
138 * subsystem_vendor_id, and revision_id
139 **/
140i40e_status i40e_init_shared_code(struct i40e_hw *hw)
141{
142 i40e_status status = 0;
143 u32 reg;
144
145 hw->phy.get_link_info = true;
146
147 /* Determine port number */
148 reg = rd32(hw, I40E_PFGEN_PORTNUM);
149 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
150 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
151 hw->port = (u8)reg;
152
153 i40e_set_mac_type(hw);
154
155 switch (hw->mac.type) {
156 case I40E_MAC_XL710:
157 break;
158 default:
159 return I40E_ERR_DEVICE_NOT_SUPPORTED;
160 break;
161 }
162
163 status = i40e_init_nvm(hw);
164 return status;
165}
166
167/**
168 * i40e_aq_mac_address_read - Retrieve the MAC addresses
169 * @hw: pointer to the hw struct
170 * @flags: a return indicator of what addresses were added to the addr store
171 * @addrs: the requestor's mac addr store
172 * @cmd_details: pointer to command details structure or NULL
173 **/
174static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
175 u16 *flags,
176 struct i40e_aqc_mac_address_read_data *addrs,
177 struct i40e_asq_cmd_details *cmd_details)
178{
179 struct i40e_aq_desc desc;
180 struct i40e_aqc_mac_address_read *cmd_data =
181 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
182 i40e_status status;
183
184 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
185 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
186
187 status = i40e_asq_send_command(hw, &desc, addrs,
188 sizeof(*addrs), cmd_details);
189 *flags = le16_to_cpu(cmd_data->command_flags);
190
191 return status;
192}
193
194/**
195 * i40e_aq_mac_address_write - Change the MAC addresses
196 * @hw: pointer to the hw struct
197 * @flags: indicates which MAC to be written
198 * @mac_addr: address to write
199 * @cmd_details: pointer to command details structure or NULL
200 **/
201i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
202 u16 flags, u8 *mac_addr,
203 struct i40e_asq_cmd_details *cmd_details)
204{
205 struct i40e_aq_desc desc;
206 struct i40e_aqc_mac_address_write *cmd_data =
207 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
208 i40e_status status;
209
210 i40e_fill_default_direct_cmd_desc(&desc,
211 i40e_aqc_opc_mac_address_write);
212 cmd_data->command_flags = cpu_to_le16(flags);
213 memcpy(&cmd_data->mac_sal, &mac_addr[0], 4);
214 memcpy(&cmd_data->mac_sah, &mac_addr[4], 2);
215
216 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
217
218 return status;
219}
220
221/**
222 * i40e_get_mac_addr - get MAC address
223 * @hw: pointer to the HW structure
224 * @mac_addr: pointer to MAC address
225 *
226 * Reads the adapter's MAC address from register
227 **/
228i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
229{
230 struct i40e_aqc_mac_address_read_data addrs;
231 i40e_status status;
232 u16 flags = 0;
233
234 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
235
236 if (flags & I40E_AQC_LAN_ADDR_VALID)
237 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
238
239 return status;
240}
241
be405eb0
JB		 242/**
243 * i40e_get_media_type - Gets media type
244 * @hw: pointer to the hardware structure
245 **/
246static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
247{
248 enum i40e_media_type media;
249
250 switch (hw->phy.link_info.phy_type) {
251 case I40E_PHY_TYPE_10GBASE_SR:
252 case I40E_PHY_TYPE_10GBASE_LR:
253 case I40E_PHY_TYPE_40GBASE_SR4:
254 case I40E_PHY_TYPE_40GBASE_LR4:
255 media = I40E_MEDIA_TYPE_FIBER;
256 break;
257 case I40E_PHY_TYPE_100BASE_TX:
258 case I40E_PHY_TYPE_1000BASE_T:
259 case I40E_PHY_TYPE_10GBASE_T:
260 media = I40E_MEDIA_TYPE_BASET;
261 break;
262 case I40E_PHY_TYPE_10GBASE_CR1_CU:
263 case I40E_PHY_TYPE_40GBASE_CR4_CU:
264 case I40E_PHY_TYPE_10GBASE_CR1:
265 case I40E_PHY_TYPE_40GBASE_CR4:
266 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
267 media = I40E_MEDIA_TYPE_DA;
268 break;
269 case I40E_PHY_TYPE_1000BASE_KX:
270 case I40E_PHY_TYPE_10GBASE_KX4:
271 case I40E_PHY_TYPE_10GBASE_KR:
272 case I40E_PHY_TYPE_40GBASE_KR4:
273 media = I40E_MEDIA_TYPE_BACKPLANE;
274 break;
275 case I40E_PHY_TYPE_SGMII:
276 case I40E_PHY_TYPE_XAUI:
277 case I40E_PHY_TYPE_XFI:
278 case I40E_PHY_TYPE_XLAUI:
279 case I40E_PHY_TYPE_XLPPI:
280 default:
281 media = I40E_MEDIA_TYPE_UNKNOWN;
282 break;
283 }
284
285 return media;
286}
287
7134f9ce
JB		 288#define I40E_PF_RESET_WAIT_COUNT_A0 200
289#define I40E_PF_RESET_WAIT_COUNT 10
56a62fc8
JB		 290/**
291 * i40e_pf_reset - Reset the PF
292 * @hw: pointer to the hardware structure
293 *
294 * Assuming someone else has triggered a global reset,
295 * assure the global reset is complete and then reset the PF
296 **/
297i40e_status i40e_pf_reset(struct i40e_hw *hw)
298{
7134f9ce 299 u32 cnt = 0;
56a62fc8
JB		 300 u32 reg = 0;
301 u32 grst_del;
302
303 /* Poll for Global Reset steady state in case of recent GRST.
304 * The grst delay value is in 100ms units, and we'll wait a
305 * couple counts longer to be sure we don't just miss the end.
306 */
307 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
308 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
7134f9ce 309 for (cnt = 0; cnt < grst_del + 2; cnt++) {
56a62fc8
JB		 310 reg = rd32(hw, I40E_GLGEN_RSTAT);
311 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
312 break;
313 msleep(100);
314 }
315 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
316 hw_dbg(hw, "Global reset polling failed to complete.\n");
317 return I40E_ERR_RESET_FAILED;
318 }
319
320 /* Determine the PF number based on the PCI fn */
71bd4b8e
CP		 321 reg = rd32(hw, I40E_GLPCI_CAPSUP);
322 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
323 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
324 else
325 hw->pf_id = (u8)hw->bus.func;
56a62fc8
JB		 326
327 /* If there was a Global Reset in progress when we got here,
328 * we don't need to do the PF Reset
329 */
7134f9ce
JB		 330 if (!cnt) {
331 if (hw->revision_id == 0)
332 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
333 else
334 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 335 reg = rd32(hw, I40E_PFGEN_CTRL);
336 wr32(hw, I40E_PFGEN_CTRL,
337 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 338 for (; cnt; cnt--) {
56a62fc8
JB		 339 reg = rd32(hw, I40E_PFGEN_CTRL);
340 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
341 break;
342 usleep_range(1000, 2000);
343 }
344 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
345 hw_dbg(hw, "PF reset polling failed to complete.\n");
346 return I40E_ERR_RESET_FAILED;
347 }
348 }
349
350 i40e_clear_pxe_mode(hw);
351 return 0;
352}
353
354/**
355 * i40e_clear_pxe_mode - clear pxe operations mode
356 * @hw: pointer to the hw struct
357 *
358 * Make sure all PXE mode settings are cleared, including things
359 * like descriptor fetch/write-back mode.
360 **/
361void i40e_clear_pxe_mode(struct i40e_hw *hw)
362{
363 u32 reg;
364
365 /* Clear single descriptor fetch/write-back mode */
366 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 367
368 if (hw->revision_id == 0) {
369 /* As a work around clear PXE_MODE instead of setting it */
370 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
371 } else {
372 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
373 }
56a62fc8
JB		 374}
375
0556a9e3
JB		 376/**
377 * i40e_led_is_mine - helper to find matching led
378 * @hw: pointer to the hw struct
379 * @idx: index into GPIO registers
380 *
381 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
382 */
383static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
384{
385 u32 gpio_val = 0;
386 u32 port;
387
388 if (!hw->func_caps.led[idx])
389 return 0;
390
391 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
392 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
393 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
394
395 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
396 * if it is not our port then ignore
397 */
398 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
399 (port != hw->port))
400 return 0;
401
402 return gpio_val;
403}
404
405#define I40E_LED0 22
406#define I40E_LINK_ACTIVITY 0xC
407
56a62fc8
JB		 408/**
409 * i40e_led_get - return current on/off mode
410 * @hw: pointer to the hw struct
411 *
412 * The value returned is the 'mode' field as defined in the
413 * GPIO register definitions: 0x0 = off, 0xf = on, and other
414 * values are variations of possible behaviors relating to
415 * blink, link, and wire.
416 **/
417u32 i40e_led_get(struct i40e_hw *hw)
418{
56a62fc8 419 u32 mode = 0;
56a62fc8
JB		 420 int i;
421
0556a9e3
JB		 422 /* as per the documentation GPIO 22-29 are the LED
423 * GPIO pins named LED0..LED7
424 */
425 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
426 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 427
0556a9e3 428 if (!gpio_val)
56a62fc8
JB		 429 continue;
430
0556a9e3
JB		 431 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
432 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 433 break;
434 }
435
436 return mode;
437}
438
439/**
440 * i40e_led_set - set new on/off mode
441 * @hw: pointer to the hw struct
0556a9e3
JB		 442 * @mode: 0=off, 0xf=on (else see manual for mode details)
443 * @blink: true if the LED should blink when on, false if steady
444 *
445 * if this function is used to turn on the blink it should
446 * be used to disable the blink when restoring the original state.
56a62fc8 447 **/
0556a9e3 448void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 449{
56a62fc8
JB		 450 int i;
451
0556a9e3
JB		 452 if (mode & 0xfffffff0)
453 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 454
0556a9e3
JB		 455 /* as per the documentation GPIO 22-29 are the LED
456 * GPIO pins named LED0..LED7
457 */
458 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
459 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 460
0556a9e3 461 if (!gpio_val)
56a62fc8
JB		 462 continue;
463
56a62fc8 464 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 465 /* this & is a bit of paranoia, but serves as a range check */
466 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
467 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
468
469 if (mode == I40E_LINK_ACTIVITY)
470 blink = false;
471
472 gpio_val |= (blink ? 1 : 0) <<
473 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
474
56a62fc8 475 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 476 break;
56a62fc8
JB		 477 }
478}
479
480/* Admin command wrappers */
481/**
482 * i40e_aq_queue_shutdown
483 * @hw: pointer to the hw struct
484 * @unloading: is the driver unloading itself
485 *
486 * Tell the Firmware that we're shutting down the AdminQ and whether
487 * or not the driver is unloading as well.
488 **/
489i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
490 bool unloading)
491{
492 struct i40e_aq_desc desc;
493 struct i40e_aqc_queue_shutdown *cmd =
494 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
495 i40e_status status;
496
497 i40e_fill_default_direct_cmd_desc(&desc,
498 i40e_aqc_opc_queue_shutdown);
499
500 if (unloading)
501 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
502 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
503
504 return status;
505}
506
507/**
508 * i40e_aq_set_link_restart_an
509 * @hw: pointer to the hw struct
510 * @cmd_details: pointer to command details structure or NULL
511 *
512 * Sets up the link and restarts the Auto-Negotiation over the link.
513 **/
514i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
515 struct i40e_asq_cmd_details *cmd_details)
516{
517 struct i40e_aq_desc desc;
518 struct i40e_aqc_set_link_restart_an *cmd =
519 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
520 i40e_status status;
521
522 i40e_fill_default_direct_cmd_desc(&desc,
523 i40e_aqc_opc_set_link_restart_an);
524
525 cmd->command = I40E_AQ_PHY_RESTART_AN;
526
527 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
528
529 return status;
530}
531
532/**
533 * i40e_aq_get_link_info
534 * @hw: pointer to the hw struct
535 * @enable_lse: enable/disable LinkStatusEvent reporting
536 * @link: pointer to link status structure - optional
537 * @cmd_details: pointer to command details structure or NULL
538 *
539 * Returns the link status of the adapter.
540 **/
541i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
542 bool enable_lse, struct i40e_link_status *link,
543 struct i40e_asq_cmd_details *cmd_details)
544{
545 struct i40e_aq_desc desc;
546 struct i40e_aqc_get_link_status *resp =
547 (struct i40e_aqc_get_link_status *)&desc.params.raw;
548 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
549 i40e_status status;
550 u16 command_flags;
551
552 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
553
554 if (enable_lse)
555 command_flags = I40E_AQ_LSE_ENABLE;
556 else
557 command_flags = I40E_AQ_LSE_DISABLE;
558 resp->command_flags = cpu_to_le16(command_flags);
559
560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
561
562 if (status)
563 goto aq_get_link_info_exit;
564
565 /* save off old link status information */
566 memcpy(&hw->phy.link_info_old, hw_link_info,
567 sizeof(struct i40e_link_status));
568
569 /* update link status */
570 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 571 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 572 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
573 hw_link_info->link_info = resp->link_info;
574 hw_link_info->an_info = resp->an_info;
575 hw_link_info->ext_info = resp->ext_info;
639dc377 576 hw_link_info->loopback = resp->loopback;
56a62fc8
JB		 577
578 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
579 hw_link_info->lse_enable = true;
580 else
581 hw_link_info->lse_enable = false;
582
583 /* save link status information */
584 if (link)
d7595a22 585 *link = *hw_link_info;
56a62fc8
JB		 586
587 /* flag cleared so helper functions don't call AQ again */
588 hw->phy.get_link_info = false;
589
590aq_get_link_info_exit:
591 return status;
592}
593
594/**
595 * i40e_aq_add_vsi
596 * @hw: pointer to the hw struct
597 * @vsi: pointer to a vsi context struct
598 * @cmd_details: pointer to command details structure or NULL
599 *
600 * Add a VSI context to the hardware.
601**/
602i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
603 struct i40e_vsi_context *vsi_ctx,
604 struct i40e_asq_cmd_details *cmd_details)
605{
606 struct i40e_aq_desc desc;
607 struct i40e_aqc_add_get_update_vsi *cmd =
608 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
609 struct i40e_aqc_add_get_update_vsi_completion *resp =
610 (struct i40e_aqc_add_get_update_vsi_completion *)
611 &desc.params.raw;
612 i40e_status status;
613
614 i40e_fill_default_direct_cmd_desc(&desc,
615 i40e_aqc_opc_add_vsi);
616
617 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
618 cmd->connection_type = vsi_ctx->connection_type;
619 cmd->vf_id = vsi_ctx->vf_num;
620 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
621
622 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
623 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
624 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
625
626 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
627 sizeof(vsi_ctx->info), cmd_details);
628
629 if (status)
630 goto aq_add_vsi_exit;
631
632 vsi_ctx->seid = le16_to_cpu(resp->seid);
633 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
634 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
635 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
636
637aq_add_vsi_exit:
638 return status;
639}
640
641/**
642 * i40e_aq_set_vsi_unicast_promiscuous
643 * @hw: pointer to the hw struct
644 * @seid: vsi number
645 * @set: set unicast promiscuous enable/disable
646 * @cmd_details: pointer to command details structure or NULL
647 **/
648i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
649 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
650{
651 struct i40e_aq_desc desc;
652 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
653 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
654 i40e_status status;
655 u16 flags = 0;
656
657 i40e_fill_default_direct_cmd_desc(&desc,
658 i40e_aqc_opc_set_vsi_promiscuous_modes);
659
660 if (set)
661 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
662
663 cmd->promiscuous_flags = cpu_to_le16(flags);
664
665 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
666
667 cmd->seid = cpu_to_le16(seid);
668 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
669
670 return status;
671}
672
673/**
674 * i40e_aq_set_vsi_multicast_promiscuous
675 * @hw: pointer to the hw struct
676 * @seid: vsi number
677 * @set: set multicast promiscuous enable/disable
678 * @cmd_details: pointer to command details structure or NULL
679 **/
680i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
681 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
682{
683 struct i40e_aq_desc desc;
684 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
685 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
686 i40e_status status;
687 u16 flags = 0;
688
689 i40e_fill_default_direct_cmd_desc(&desc,
690 i40e_aqc_opc_set_vsi_promiscuous_modes);
691
692 if (set)
693 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
694
695 cmd->promiscuous_flags = cpu_to_le16(flags);
696
697 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
698
699 cmd->seid = cpu_to_le16(seid);
700 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
701
702 return status;
703}
704
705/**
706 * i40e_aq_set_vsi_broadcast
707 * @hw: pointer to the hw struct
708 * @seid: vsi number
709 * @set_filter: true to set filter, false to clear filter
710 * @cmd_details: pointer to command details structure or NULL
711 *
712 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
713 **/
714i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
715 u16 seid, bool set_filter,
716 struct i40e_asq_cmd_details *cmd_details)
717{
718 struct i40e_aq_desc desc;
719 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
720 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
721 i40e_status status;
722
723 i40e_fill_default_direct_cmd_desc(&desc,
724 i40e_aqc_opc_set_vsi_promiscuous_modes);
725
726 if (set_filter)
727 cmd->promiscuous_flags
728 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
729 else
730 cmd->promiscuous_flags
731 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
732
733 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
734 cmd->seid = cpu_to_le16(seid);
735 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
736
737 return status;
738}
739
740/**
741 * i40e_get_vsi_params - get VSI configuration info
742 * @hw: pointer to the hw struct
743 * @vsi: pointer to a vsi context struct
744 * @cmd_details: pointer to command details structure or NULL
745 **/
746i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
747 struct i40e_vsi_context *vsi_ctx,
748 struct i40e_asq_cmd_details *cmd_details)
749{
750 struct i40e_aq_desc desc;
751 struct i40e_aqc_switch_seid *cmd =
752 (struct i40e_aqc_switch_seid *)&desc.params.raw;
753 struct i40e_aqc_add_get_update_vsi_completion *resp =
754 (struct i40e_aqc_add_get_update_vsi_completion *)
755 &desc.params.raw;
756 i40e_status status;
757
758 i40e_fill_default_direct_cmd_desc(&desc,
759 i40e_aqc_opc_get_vsi_parameters);
760
761 cmd->seid = cpu_to_le16(vsi_ctx->seid);
762
763 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
764 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
765 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
766
767 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
768 sizeof(vsi_ctx->info), NULL);
769
770 if (status)
771 goto aq_get_vsi_params_exit;
772
773 vsi_ctx->seid = le16_to_cpu(resp->seid);
774 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
775 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
776 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
777
778aq_get_vsi_params_exit:
779 return status;
780}
781
782/**
783 * i40e_aq_update_vsi_params
784 * @hw: pointer to the hw struct
785 * @vsi: pointer to a vsi context struct
786 * @cmd_details: pointer to command details structure or NULL
787 *
788 * Update a VSI context.
789 **/
790i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
791 struct i40e_vsi_context *vsi_ctx,
792 struct i40e_asq_cmd_details *cmd_details)
793{
794 struct i40e_aq_desc desc;
795 struct i40e_aqc_switch_seid *cmd =
796 (struct i40e_aqc_switch_seid *)&desc.params.raw;
797 i40e_status status;
798
799 i40e_fill_default_direct_cmd_desc(&desc,
800 i40e_aqc_opc_update_vsi_parameters);
801 cmd->seid = cpu_to_le16(vsi_ctx->seid);
802
803 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
804 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
805 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
806
807 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
808 sizeof(vsi_ctx->info), cmd_details);
809
810 return status;
811}
812
813/**
814 * i40e_aq_get_switch_config
815 * @hw: pointer to the hardware structure
816 * @buf: pointer to the result buffer
817 * @buf_size: length of input buffer
818 * @start_seid: seid to start for the report, 0 == beginning
819 * @cmd_details: pointer to command details structure or NULL
820 *
821 * Fill the buf with switch configuration returned from AdminQ command
822 **/
823i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
824 struct i40e_aqc_get_switch_config_resp *buf,
825 u16 buf_size, u16 *start_seid,
826 struct i40e_asq_cmd_details *cmd_details)
827{
828 struct i40e_aq_desc desc;
829 struct i40e_aqc_switch_seid *scfg =
830 (struct i40e_aqc_switch_seid *)&desc.params.raw;
831 i40e_status status;
832
833 i40e_fill_default_direct_cmd_desc(&desc,
834 i40e_aqc_opc_get_switch_config);
835 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
836 if (buf_size > I40E_AQ_LARGE_BUF)
837 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
838 scfg->seid = cpu_to_le16(*start_seid);
839
840 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
841 *start_seid = le16_to_cpu(scfg->seid);
842
843 return status;
844}
845
846/**
847 * i40e_aq_get_firmware_version
848 * @hw: pointer to the hw struct
849 * @fw_major_version: firmware major version
850 * @fw_minor_version: firmware minor version
851 * @api_major_version: major queue version
852 * @api_minor_version: minor queue version
853 * @cmd_details: pointer to command details structure or NULL
854 *
855 * Get the firmware version from the admin queue commands
856 **/
857i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
858 u16 *fw_major_version, u16 *fw_minor_version,
859 u16 *api_major_version, u16 *api_minor_version,
860 struct i40e_asq_cmd_details *cmd_details)
861{
862 struct i40e_aq_desc desc;
863 struct i40e_aqc_get_version *resp =
864 (struct i40e_aqc_get_version *)&desc.params.raw;
865 i40e_status status;
866
867 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
868
869 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
870
871 if (!status) {
872 if (fw_major_version != NULL)
873 *fw_major_version = le16_to_cpu(resp->fw_major);
874 if (fw_minor_version != NULL)
875 *fw_minor_version = le16_to_cpu(resp->fw_minor);
876 if (api_major_version != NULL)
877 *api_major_version = le16_to_cpu(resp->api_major);
878 if (api_minor_version != NULL)
879 *api_minor_version = le16_to_cpu(resp->api_minor);
880 }
881
882 return status;
883}
884
885/**
886 * i40e_aq_send_driver_version
887 * @hw: pointer to the hw struct
888 * @event: driver event: driver ok, start or stop
889 * @dv: driver's major, minor version
890 * @cmd_details: pointer to command details structure or NULL
891 *
892 * Send the driver version to the firmware
893 **/
894i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
895 struct i40e_driver_version *dv,
896 struct i40e_asq_cmd_details *cmd_details)
897{
898 struct i40e_aq_desc desc;
899 struct i40e_aqc_driver_version *cmd =
900 (struct i40e_aqc_driver_version *)&desc.params.raw;
901 i40e_status status;
902
903 if (dv == NULL)
904 return I40E_ERR_PARAM;
905
906 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
907
908 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
909 cmd->driver_major_ver = dv->major_version;
910 cmd->driver_minor_ver = dv->minor_version;
911 cmd->driver_build_ver = dv->build_version;
912 cmd->driver_subbuild_ver = dv->subbuild_version;
913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
914
915 return status;
916}
917
918/**
919 * i40e_get_link_status - get status of the HW network link
920 * @hw: pointer to the hw struct
921 *
922 * Returns true if link is up, false if link is down.
923 *
924 * Side effect: LinkStatusEvent reporting becomes enabled
925 **/
926bool i40e_get_link_status(struct i40e_hw *hw)
927{
928 i40e_status status = 0;
929 bool link_status = false;
930
931 if (hw->phy.get_link_info) {
932 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
933
934 if (status)
935 goto i40e_get_link_status_exit;
936 }
937
938 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
939
940i40e_get_link_status_exit:
941 return link_status;
942}
943
944/**
945 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
946 * @hw: pointer to the hw struct
947 * @uplink_seid: the MAC or other gizmo SEID
948 * @downlink_seid: the VSI SEID
949 * @enabled_tc: bitmap of TCs to be enabled
950 * @default_port: true for default port VSI, false for control port
e1c51b95 951 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 952 * @veb_seid: pointer to where to put the resulting VEB SEID
953 * @cmd_details: pointer to command details structure or NULL
954 *
955 * This asks the FW to add a VEB between the uplink and downlink
956 * elements. If the uplink SEID is 0, this will be a floating VEB.
957 **/
958i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
959 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 960 bool default_port, bool enable_l2_filtering,
961 u16 *veb_seid,
56a62fc8
JB		 962 struct i40e_asq_cmd_details *cmd_details)
963{
964 struct i40e_aq_desc desc;
965 struct i40e_aqc_add_veb *cmd =
966 (struct i40e_aqc_add_veb *)&desc.params.raw;
967 struct i40e_aqc_add_veb_completion *resp =
968 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
969 i40e_status status;
970 u16 veb_flags = 0;
971
972 /* SEIDs need to either both be set or both be 0 for floating VEB */
973 if (!!uplink_seid != !!downlink_seid)
974 return I40E_ERR_PARAM;
975
976 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
977
978 cmd->uplink_seid = cpu_to_le16(uplink_seid);
979 cmd->downlink_seid = cpu_to_le16(downlink_seid);
980 cmd->enable_tcs = enabled_tc;
981 if (!uplink_seid)
982 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
983 if (default_port)
984 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
985 else
986 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 987
988 if (enable_l2_filtering)
989 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
990
56a62fc8
JB		 991 cmd->veb_flags = cpu_to_le16(veb_flags);
992
993 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
994
995 if (!status && veb_seid)
996 *veb_seid = le16_to_cpu(resp->veb_seid);
997
998 return status;
999}
1000
1001/**
1002 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1003 * @hw: pointer to the hw struct
1004 * @veb_seid: the SEID of the VEB to query
1005 * @switch_id: the uplink switch id
1006 * @floating_veb: set to true if the VEB is floating
1007 * @statistic_index: index of the stats counter block for this VEB
1008 * @vebs_used: number of VEB's used by function
1009 * @vebs_unallocated: total VEB's not reserved by any function
1010 * @cmd_details: pointer to command details structure or NULL
1011 *
1012 * This retrieves the parameters for a particular VEB, specified by
1013 * uplink_seid, and returns them to the caller.
1014 **/
1015i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1016 u16 veb_seid, u16 *switch_id,
1017 bool *floating, u16 *statistic_index,
1018 u16 *vebs_used, u16 *vebs_free,
1019 struct i40e_asq_cmd_details *cmd_details)
1020{
1021 struct i40e_aq_desc desc;
1022 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1023 (struct i40e_aqc_get_veb_parameters_completion *)
1024 &desc.params.raw;
1025 i40e_status status;
1026
1027 if (veb_seid == 0)
1028 return I40E_ERR_PARAM;
1029
1030 i40e_fill_default_direct_cmd_desc(&desc,
1031 i40e_aqc_opc_get_veb_parameters);
1032 cmd_resp->seid = cpu_to_le16(veb_seid);
1033
1034 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1035 if (status)
1036 goto get_veb_exit;
1037
1038 if (switch_id)
1039 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1040 if (statistic_index)
1041 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1042 if (vebs_used)
1043 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1044 if (vebs_free)
1045 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1046 if (floating) {
1047 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1048 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1049 *floating = true;
1050 else
1051 *floating = false;
1052 }
1053
1054get_veb_exit:
1055 return status;
1056}
1057
1058/**
1059 * i40e_aq_add_macvlan
1060 * @hw: pointer to the hw struct
1061 * @seid: VSI for the mac address
1062 * @mv_list: list of macvlans to be added
1063 * @count: length of the list
1064 * @cmd_details: pointer to command details structure or NULL
1065 *
1066 * Add MAC/VLAN addresses to the HW filtering
1067 **/
1068i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1069 struct i40e_aqc_add_macvlan_element_data *mv_list,
1070 u16 count, struct i40e_asq_cmd_details *cmd_details)
1071{
1072 struct i40e_aq_desc desc;
1073 struct i40e_aqc_macvlan *cmd =
1074 (struct i40e_aqc_macvlan *)&desc.params.raw;
1075 i40e_status status;
1076 u16 buf_size;
1077
1078 if (count == 0 || !mv_list || !hw)
1079 return I40E_ERR_PARAM;
1080
1081 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1082
1083 /* prep the rest of the request */
1084 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1085 cmd->num_addresses = cpu_to_le16(count);
1086 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1087 cmd->seid[1] = 0;
1088 cmd->seid[2] = 0;
1089
1090 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1091 if (buf_size > I40E_AQ_LARGE_BUF)
1092 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1093
1094 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1095 cmd_details);
1096
1097 return status;
1098}
1099
1100/**
1101 * i40e_aq_remove_macvlan
1102 * @hw: pointer to the hw struct
1103 * @seid: VSI for the mac address
1104 * @mv_list: list of macvlans to be removed
1105 * @count: length of the list
1106 * @cmd_details: pointer to command details structure or NULL
1107 *
1108 * Remove MAC/VLAN addresses from the HW filtering
1109 **/
1110i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1111 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1112 u16 count, struct i40e_asq_cmd_details *cmd_details)
1113{
1114 struct i40e_aq_desc desc;
1115 struct i40e_aqc_macvlan *cmd =
1116 (struct i40e_aqc_macvlan *)&desc.params.raw;
1117 i40e_status status;
1118 u16 buf_size;
1119
1120 if (count == 0 || !mv_list || !hw)
1121 return I40E_ERR_PARAM;
1122
1123 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1124
1125 /* prep the rest of the request */
1126 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1127 cmd->num_addresses = cpu_to_le16(count);
1128 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1129 cmd->seid[1] = 0;
1130 cmd->seid[2] = 0;
1131
1132 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1133 if (buf_size > I40E_AQ_LARGE_BUF)
1134 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1135
1136 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1137 cmd_details);
1138
1139 return status;
1140}
1141
56a62fc8
JB		 1142/**
1143 * i40e_aq_send_msg_to_vf
1144 * @hw: pointer to the hardware structure
1145 * @vfid: vf id to send msg
1146 * @msg: pointer to the msg buffer
1147 * @msglen: msg length
1148 * @cmd_details: pointer to command details
1149 *
1150 * send msg to vf
1151 **/
1152i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1153 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1154 struct i40e_asq_cmd_details *cmd_details)
1155{
1156 struct i40e_aq_desc desc;
1157 struct i40e_aqc_pf_vf_message *cmd =
1158 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1159 i40e_status status;
1160
1161 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1162 cmd->id = cpu_to_le32(vfid);
1163 desc.cookie_high = cpu_to_le32(v_opcode);
1164 desc.cookie_low = cpu_to_le32(v_retval);
1165 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1166 if (msglen) {
1167 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1168 I40E_AQ_FLAG_RD));
1169 if (msglen > I40E_AQ_LARGE_BUF)
1170 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1171 desc.datalen = cpu_to_le16(msglen);
1172 }
1173 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1174
1175 return status;
1176}
1177
1178/**
1179 * i40e_aq_set_hmc_resource_profile
1180 * @hw: pointer to the hw struct
1181 * @profile: type of profile the HMC is to be set as
1182 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1183 * @cmd_details: pointer to command details structure or NULL
1184 *
1185 * set the HMC profile of the device.
1186 **/
1187i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1188 enum i40e_aq_hmc_profile profile,
1189 u8 pe_vf_enabled_count,
1190 struct i40e_asq_cmd_details *cmd_details)
1191{
1192 struct i40e_aq_desc desc;
1193 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1194 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1195 i40e_status status;
1196
1197 i40e_fill_default_direct_cmd_desc(&desc,
1198 i40e_aqc_opc_set_hmc_resource_profile);
1199
1200 cmd->pm_profile = (u8)profile;
1201 cmd->pe_vf_enabled = pe_vf_enabled_count;
1202
1203 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1204
1205 return status;
1206}
1207
1208/**
1209 * i40e_aq_request_resource
1210 * @hw: pointer to the hw struct
1211 * @resource: resource id
1212 * @access: access type
1213 * @sdp_number: resource number
1214 * @timeout: the maximum time in ms that the driver may hold the resource
1215 * @cmd_details: pointer to command details structure or NULL
1216 *
1217 * requests common resource using the admin queue commands
1218 **/
1219i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1220 enum i40e_aq_resources_ids resource,
1221 enum i40e_aq_resource_access_type access,
1222 u8 sdp_number, u64 *timeout,
1223 struct i40e_asq_cmd_details *cmd_details)
1224{
1225 struct i40e_aq_desc desc;
1226 struct i40e_aqc_request_resource *cmd_resp =
1227 (struct i40e_aqc_request_resource *)&desc.params.raw;
1228 i40e_status status;
1229
1230 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
1231
1232 cmd_resp->resource_id = cpu_to_le16(resource);
1233 cmd_resp->access_type = cpu_to_le16(access);
1234 cmd_resp->resource_number = cpu_to_le32(sdp_number);
1235
1236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1237 /* The completion specifies the maximum time in ms that the driver
1238 * may hold the resource in the Timeout field.
1239 * If the resource is held by someone else, the command completes with
1240 * busy return value and the timeout field indicates the maximum time
1241 * the current owner of the resource has to free it.
1242 */
1243 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
1244 *timeout = le32_to_cpu(cmd_resp->timeout);
1245
1246 return status;
1247}
1248
1249/**
1250 * i40e_aq_release_resource
1251 * @hw: pointer to the hw struct
1252 * @resource: resource id
1253 * @sdp_number: resource number
1254 * @cmd_details: pointer to command details structure or NULL
1255 *
1256 * release common resource using the admin queue commands
1257 **/
1258i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
1259 enum i40e_aq_resources_ids resource,
1260 u8 sdp_number,
1261 struct i40e_asq_cmd_details *cmd_details)
1262{
1263 struct i40e_aq_desc desc;
1264 struct i40e_aqc_request_resource *cmd =
1265 (struct i40e_aqc_request_resource *)&desc.params.raw;
1266 i40e_status status;
1267
1268 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
1269
1270 cmd->resource_id = cpu_to_le16(resource);
1271 cmd->resource_number = cpu_to_le32(sdp_number);
1272
1273 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1274
1275 return status;
1276}
1277
1278/**
1279 * i40e_aq_read_nvm
1280 * @hw: pointer to the hw struct
1281 * @module_pointer: module pointer location in words from the NVM beginning
1282 * @offset: byte offset from the module beginning
1283 * @length: length of the section to be read (in bytes from the offset)
1284 * @data: command buffer (size [bytes] = length)
1285 * @last_command: tells if this is the last command in a series
1286 * @cmd_details: pointer to command details structure or NULL
1287 *
1288 * Read the NVM using the admin queue commands
1289 **/
1290i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
1291 u32 offset, u16 length, void *data,
1292 bool last_command,
1293 struct i40e_asq_cmd_details *cmd_details)
1294{
1295 struct i40e_aq_desc desc;
1296 struct i40e_aqc_nvm_update *cmd =
1297 (struct i40e_aqc_nvm_update *)&desc.params.raw;
1298 i40e_status status;
1299
1300 /* In offset the highest byte must be zeroed. */
1301 if (offset & 0xFF000000) {
1302 status = I40E_ERR_PARAM;
1303 goto i40e_aq_read_nvm_exit;
1304 }
1305
1306 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
1307
1308 /* If this is the last command in a series, set the proper flag. */
1309 if (last_command)
1310 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
1311 cmd->module_pointer = module_pointer;
1312 cmd->offset = cpu_to_le32(offset);
1313 cmd->length = cpu_to_le16(length);
1314
1315 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1316 if (length > I40E_AQ_LARGE_BUF)
1317 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1318
1319 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
1320
1321i40e_aq_read_nvm_exit:
1322 return status;
1323}
1324
1325#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1326#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1327#define I40E_DEV_FUNC_CAP_NPAR 0x03
1328#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1329#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1330#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1331#define I40E_DEV_FUNC_CAP_VF 0x13
1332#define I40E_DEV_FUNC_CAP_VMDQ 0x14
1333#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1334#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1335#define I40E_DEV_FUNC_CAP_VSI 0x17
1336#define I40E_DEV_FUNC_CAP_DCB 0x18
1337#define I40E_DEV_FUNC_CAP_FCOE 0x21
1338#define I40E_DEV_FUNC_CAP_RSS 0x40
1339#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1340#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1341#define I40E_DEV_FUNC_CAP_MSIX 0x43
1342#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1343#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1344#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1345#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1346#define I40E_DEV_FUNC_CAP_CEM 0xF2
1347#define I40E_DEV_FUNC_CAP_IWARP 0x51
1348#define I40E_DEV_FUNC_CAP_LED 0x61
1349#define I40E_DEV_FUNC_CAP_SDP 0x62
1350#define I40E_DEV_FUNC_CAP_MDIO 0x63
1351
1352/**
1353 * i40e_parse_discover_capabilities
1354 * @hw: pointer to the hw struct
1355 * @buff: pointer to a buffer containing device/function capability records
1356 * @cap_count: number of capability records in the list
1357 * @list_type_opc: type of capabilities list to parse
1358 *
1359 * Parse the device/function capabilities list.
1360 **/
1361static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1362 u32 cap_count,
1363 enum i40e_admin_queue_opc list_type_opc)
1364{
1365 struct i40e_aqc_list_capabilities_element_resp *cap;
1366 u32 number, logical_id, phys_id;
1367 struct i40e_hw_capabilities *p;
1368 u32 reg_val;
1369 u32 i = 0;
1370 u16 id;
1371
1372 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
1373
1374 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
1375 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
1376 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
1377 p = (struct i40e_hw_capabilities *)&hw->func_caps;
1378 else
1379 return;
1380
1381 for (i = 0; i < cap_count; i++, cap++) {
1382 id = le16_to_cpu(cap->id);
1383 number = le32_to_cpu(cap->number);
1384 logical_id = le32_to_cpu(cap->logical_id);
1385 phys_id = le32_to_cpu(cap->phys_id);
1386
1387 switch (id) {
1388 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
1389 p->switch_mode = number;
1390 break;
1391 case I40E_DEV_FUNC_CAP_MGMT_MODE:
1392 p->management_mode = number;
1393 break;
1394 case I40E_DEV_FUNC_CAP_NPAR:
1395 p->npar_enable = number;
1396 break;
1397 case I40E_DEV_FUNC_CAP_OS2BMC:
1398 p->os2bmc = number;
1399 break;
1400 case I40E_DEV_FUNC_CAP_VALID_FUNC:
1401 p->valid_functions = number;
1402 break;
1403 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
1404 if (number == 1)
1405 p->sr_iov_1_1 = true;
1406 break;
1407 case I40E_DEV_FUNC_CAP_VF:
1408 p->num_vfs = number;
1409 p->vf_base_id = logical_id;
1410 break;
1411 case I40E_DEV_FUNC_CAP_VMDQ:
1412 if (number == 1)
1413 p->vmdq = true;
1414 break;
1415 case I40E_DEV_FUNC_CAP_802_1_QBG:
1416 if (number == 1)
1417 p->evb_802_1_qbg = true;
1418 break;
1419 case I40E_DEV_FUNC_CAP_802_1_QBH:
1420 if (number == 1)
1421 p->evb_802_1_qbh = true;
1422 break;
1423 case I40E_DEV_FUNC_CAP_VSI:
1424 p->num_vsis = number;
1425 break;
1426 case I40E_DEV_FUNC_CAP_DCB:
1427 if (number == 1) {
1428 p->dcb = true;
1429 p->enabled_tcmap = logical_id;
1430 p->maxtc = phys_id;
1431 }
1432 break;
1433 case I40E_DEV_FUNC_CAP_FCOE:
1434 if (number == 1)
1435 p->fcoe = true;
1436 break;
1437 case I40E_DEV_FUNC_CAP_RSS:
1438 p->rss = true;
1439 reg_val = rd32(hw, I40E_PFQF_CTL_0);
1440 if (reg_val & I40E_PFQF_CTL_0_HASHLUTSIZE_MASK)
1441 p->rss_table_size = number;
1442 else
1443 p->rss_table_size = 128;
1444 p->rss_table_entry_width = logical_id;
1445 break;
1446 case I40E_DEV_FUNC_CAP_RX_QUEUES:
1447 p->num_rx_qp = number;
1448 p->base_queue = phys_id;
1449 break;
1450 case I40E_DEV_FUNC_CAP_TX_QUEUES:
1451 p->num_tx_qp = number;
1452 p->base_queue = phys_id;
1453 break;
1454 case I40E_DEV_FUNC_CAP_MSIX:
1455 p->num_msix_vectors = number;
1456 break;
1457 case I40E_DEV_FUNC_CAP_MSIX_VF:
1458 p->num_msix_vectors_vf = number;
1459 break;
1460 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
1461 if (number == 1)
1462 p->mfp_mode_1 = true;
1463 break;
1464 case I40E_DEV_FUNC_CAP_CEM:
1465 if (number == 1)
1466 p->mgmt_cem = true;
1467 break;
1468 case I40E_DEV_FUNC_CAP_IWARP:
1469 if (number == 1)
1470 p->iwarp = true;
1471 break;
1472 case I40E_DEV_FUNC_CAP_LED:
1473 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1474 p->led[phys_id] = true;
1475 break;
1476 case I40E_DEV_FUNC_CAP_SDP:
1477 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1478 p->sdp[phys_id] = true;
1479 break;
1480 case I40E_DEV_FUNC_CAP_MDIO:
1481 if (number == 1) {
1482 p->mdio_port_num = phys_id;
1483 p->mdio_port_mode = logical_id;
1484 }
1485 break;
1486 case I40E_DEV_FUNC_CAP_IEEE_1588:
1487 if (number == 1)
1488 p->ieee_1588 = true;
1489 break;
1490 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
1491 p->fd = true;
1492 p->fd_filters_guaranteed = number;
1493 p->fd_filters_best_effort = logical_id;
1494 break;
1495 default:
1496 break;
1497 }
1498 }
1499
1500 /* additional HW specific goodies that might
1501 * someday be HW version specific
1502 */
1503 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
1504}
1505
1506/**
1507 * i40e_aq_discover_capabilities
1508 * @hw: pointer to the hw struct
1509 * @buff: a virtual buffer to hold the capabilities
1510 * @buff_size: Size of the virtual buffer
1511 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
1512 * @list_type_opc: capabilities type to discover - pass in the command opcode
1513 * @cmd_details: pointer to command details structure or NULL
1514 *
1515 * Get the device capabilities descriptions from the firmware
1516 **/
1517i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
1518 void *buff, u16 buff_size, u16 *data_size,
1519 enum i40e_admin_queue_opc list_type_opc,
1520 struct i40e_asq_cmd_details *cmd_details)
1521{
1522 struct i40e_aqc_list_capabilites *cmd;
1523 i40e_status status = 0;
1524 struct i40e_aq_desc desc;
1525
1526 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
1527
1528 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
1529 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
1530 status = I40E_ERR_PARAM;
1531 goto exit;
1532 }
1533
1534 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
1535
1536 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1537 if (buff_size > I40E_AQ_LARGE_BUF)
1538 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1539
1540 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1541 *data_size = le16_to_cpu(desc.datalen);
1542
1543 if (status)
1544 goto exit;
1545
1546 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
1547 list_type_opc);
1548
1549exit:
1550 return status;
1551}
1552
1553/**
1554 * i40e_aq_get_lldp_mib
1555 * @hw: pointer to the hw struct
1556 * @bridge_type: type of bridge requested
1557 * @mib_type: Local, Remote or both Local and Remote MIBs
1558 * @buff: pointer to a user supplied buffer to store the MIB block
1559 * @buff_size: size of the buffer (in bytes)
1560 * @local_len : length of the returned Local LLDP MIB
1561 * @remote_len: length of the returned Remote LLDP MIB
1562 * @cmd_details: pointer to command details structure or NULL
1563 *
1564 * Requests the complete LLDP MIB (entire packet).
1565 **/
1566i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
1567 u8 mib_type, void *buff, u16 buff_size,
1568 u16 *local_len, u16 *remote_len,
1569 struct i40e_asq_cmd_details *cmd_details)
1570{
1571 struct i40e_aq_desc desc;
1572 struct i40e_aqc_lldp_get_mib *cmd =
1573 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1574 struct i40e_aqc_lldp_get_mib *resp =
1575 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1576 i40e_status status;
1577
1578 if (buff_size == 0 || !buff)
1579 return I40E_ERR_PARAM;
1580
1581 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
1582 /* Indirect Command */
1583 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1584
1585 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
1586 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
1587 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
1588
1589 desc.datalen = cpu_to_le16(buff_size);
1590
1591 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1592 if (buff_size > I40E_AQ_LARGE_BUF)
1593 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1594
1595 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1596 if (!status) {
1597 if (local_len != NULL)
1598 *local_len = le16_to_cpu(resp->local_len);
1599 if (remote_len != NULL)
1600 *remote_len = le16_to_cpu(resp->remote_len);
1601 }
1602
1603 return status;
1604}
1605
1606/**
1607 * i40e_aq_cfg_lldp_mib_change_event
1608 * @hw: pointer to the hw struct
1609 * @enable_update: Enable or Disable event posting
1610 * @cmd_details: pointer to command details structure or NULL
1611 *
1612 * Enable or Disable posting of an event on ARQ when LLDP MIB
1613 * associated with the interface changes
1614 **/
1615i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
1616 bool enable_update,
1617 struct i40e_asq_cmd_details *cmd_details)
1618{
1619 struct i40e_aq_desc desc;
1620 struct i40e_aqc_lldp_update_mib *cmd =
1621 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
1622 i40e_status status;
1623
1624 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
1625
1626 if (!enable_update)
1627 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
1628
1629 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1630
1631 return status;
1632}
1633
1634/**
1635 * i40e_aq_stop_lldp
1636 * @hw: pointer to the hw struct
1637 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
1638 * @cmd_details: pointer to command details structure or NULL
1639 *
1640 * Stop or Shutdown the embedded LLDP Agent
1641 **/
1642i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
1643 struct i40e_asq_cmd_details *cmd_details)
1644{
1645 struct i40e_aq_desc desc;
1646 struct i40e_aqc_lldp_stop *cmd =
1647 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
1648 i40e_status status;
1649
1650 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
1651
1652 if (shutdown_agent)
1653 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
1654
1655 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1656
1657 return status;
1658}
1659
1660/**
1661 * i40e_aq_start_lldp
1662 * @hw: pointer to the hw struct
1663 * @cmd_details: pointer to command details structure or NULL
1664 *
1665 * Start the embedded LLDP Agent on all ports.
1666 **/
1667i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
1668 struct i40e_asq_cmd_details *cmd_details)
1669{
1670 struct i40e_aq_desc desc;
1671 struct i40e_aqc_lldp_start *cmd =
1672 (struct i40e_aqc_lldp_start *)&desc.params.raw;
1673 i40e_status status;
1674
1675 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
1676
1677 cmd->command = I40E_AQ_LLDP_AGENT_START;
1678
1679 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1680
1681 return status;
1682}
1683
a1c9a9d9
JK		 1684/**
1685 * i40e_aq_add_udp_tunnel
1686 * @hw: pointer to the hw struct
1687 * @udp_port: the UDP port to add
1688 * @header_len: length of the tunneling header length in DWords
1689 * @protocol_index: protocol index type
1690 * @cmd_details: pointer to command details structure or NULL
1691 **/
1692i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
1693 u16 udp_port, u8 header_len,
1694 u8 protocol_index, u8 *filter_index,
1695 struct i40e_asq_cmd_details *cmd_details)
1696{
1697 struct i40e_aq_desc desc;
1698 struct i40e_aqc_add_udp_tunnel *cmd =
1699 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
1700 struct i40e_aqc_del_udp_tunnel_completion *resp =
1701 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
1702 i40e_status status;
1703
1704 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
1705
1706 cmd->udp_port = cpu_to_le16(udp_port);
1707 cmd->header_len = header_len;
1708 cmd->protocol_index = protocol_index;
1709
1710 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1711
1712 if (!status)
1713 *filter_index = resp->index;
1714
1715 return status;
1716}
1717
1718/**
1719 * i40e_aq_del_udp_tunnel
1720 * @hw: pointer to the hw struct
1721 * @index: filter index
1722 * @cmd_details: pointer to command details structure or NULL
1723 **/
1724i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
1725 struct i40e_asq_cmd_details *cmd_details)
1726{
1727 struct i40e_aq_desc desc;
1728 struct i40e_aqc_remove_udp_tunnel *cmd =
1729 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
1730 i40e_status status;
1731
1732 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
1733
1734 cmd->index = index;
1735
1736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1737
1738 return status;
1739}
1740
56a62fc8
JB		 1741/**
1742 * i40e_aq_delete_element - Delete switch element
1743 * @hw: pointer to the hw struct
1744 * @seid: the SEID to delete from the switch
1745 * @cmd_details: pointer to command details structure or NULL
1746 *
1747 * This deletes a switch element from the switch.
1748 **/
1749i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
1750 struct i40e_asq_cmd_details *cmd_details)
1751{
1752 struct i40e_aq_desc desc;
1753 struct i40e_aqc_switch_seid *cmd =
1754 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1755 i40e_status status;
1756
1757 if (seid == 0)
1758 return I40E_ERR_PARAM;
1759
1760 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
1761
1762 cmd->seid = cpu_to_le16(seid);
1763
1764 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1765
1766 return status;
1767}
1768
1769/**
1770 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
1771 * @hw: pointer to the hw struct
1772 * @seid: seid for the physical port/switching component/vsi
1773 * @buff: Indirect buffer to hold data parameters and response
1774 * @buff_size: Indirect buffer size
1775 * @opcode: Tx scheduler AQ command opcode
1776 * @cmd_details: pointer to command details structure or NULL
1777 *
1778 * Generic command handler for Tx scheduler AQ commands
1779 **/
1780static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
1781 void *buff, u16 buff_size,
1782 enum i40e_admin_queue_opc opcode,
1783 struct i40e_asq_cmd_details *cmd_details)
1784{
1785 struct i40e_aq_desc desc;
1786 struct i40e_aqc_tx_sched_ind *cmd =
1787 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
1788 i40e_status status;
1789 bool cmd_param_flag = false;
1790
1791 switch (opcode) {
1792 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
1793 case i40e_aqc_opc_configure_vsi_tc_bw:
1794 case i40e_aqc_opc_enable_switching_comp_ets:
1795 case i40e_aqc_opc_modify_switching_comp_ets:
1796 case i40e_aqc_opc_disable_switching_comp_ets:
1797 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
1798 case i40e_aqc_opc_configure_switching_comp_bw_config:
1799 cmd_param_flag = true;
1800 break;
1801 case i40e_aqc_opc_query_vsi_bw_config:
1802 case i40e_aqc_opc_query_vsi_ets_sla_config:
1803 case i40e_aqc_opc_query_switching_comp_ets_config:
1804 case i40e_aqc_opc_query_port_ets_config:
1805 case i40e_aqc_opc_query_switching_comp_bw_config:
1806 cmd_param_flag = false;
1807 break;
1808 default:
1809 return I40E_ERR_PARAM;
1810 }
1811
1812 i40e_fill_default_direct_cmd_desc(&desc, opcode);
1813
1814 /* Indirect command */
1815 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1816 if (cmd_param_flag)
1817 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
1818 if (buff_size > I40E_AQ_LARGE_BUF)
1819 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1820
1821 desc.datalen = cpu_to_le16(buff_size);
1822
1823 cmd->vsi_seid = cpu_to_le16(seid);
1824
1825 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1826
1827 return status;
1828}
1829
1830/**
1831 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
1832 * @hw: pointer to the hw struct
1833 * @seid: VSI seid
1834 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
1835 * @cmd_details: pointer to command details structure or NULL
1836 **/
1837i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
1838 u16 seid,
1839 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
1840 struct i40e_asq_cmd_details *cmd_details)
1841{
1842 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1843 i40e_aqc_opc_configure_vsi_tc_bw,
1844 cmd_details);
1845}
1846
1847/**
1848 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
1849 * @hw: pointer to the hw struct
1850 * @seid: seid of the VSI
1851 * @bw_data: Buffer to hold VSI BW configuration
1852 * @cmd_details: pointer to command details structure or NULL
1853 **/
1854i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
1855 u16 seid,
1856 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
1857 struct i40e_asq_cmd_details *cmd_details)
1858{
1859 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1860 i40e_aqc_opc_query_vsi_bw_config,
1861 cmd_details);
1862}
1863
1864/**
1865 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
1866 * @hw: pointer to the hw struct
1867 * @seid: seid of the VSI
1868 * @bw_data: Buffer to hold VSI BW configuration per TC
1869 * @cmd_details: pointer to command details structure or NULL
1870 **/
1871i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
1872 u16 seid,
1873 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
1874 struct i40e_asq_cmd_details *cmd_details)
1875{
1876 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1877 i40e_aqc_opc_query_vsi_ets_sla_config,
1878 cmd_details);
1879}
1880
1881/**
1882 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
1883 * @hw: pointer to the hw struct
1884 * @seid: seid of the switching component
1885 * @bw_data: Buffer to hold switching component's per TC BW config
1886 * @cmd_details: pointer to command details structure or NULL
1887 **/
1888i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
1889 u16 seid,
1890 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
1891 struct i40e_asq_cmd_details *cmd_details)
1892{
1893 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1894 i40e_aqc_opc_query_switching_comp_ets_config,
1895 cmd_details);
1896}
1897
1898/**
1899 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
1900 * @hw: pointer to the hw struct
1901 * @seid: seid of the VSI or switching component connected to Physical Port
1902 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
1903 * @cmd_details: pointer to command details structure or NULL
1904 **/
1905i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
1906 u16 seid,
1907 struct i40e_aqc_query_port_ets_config_resp *bw_data,
1908 struct i40e_asq_cmd_details *cmd_details)
1909{
1910 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1911 i40e_aqc_opc_query_port_ets_config,
1912 cmd_details);
1913}
1914
1915/**
1916 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
1917 * @hw: pointer to the hw struct
1918 * @seid: seid of the switching component
1919 * @bw_data: Buffer to hold switching component's BW configuration
1920 * @cmd_details: pointer to command details structure or NULL
1921 **/
1922i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
1923 u16 seid,
1924 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
1925 struct i40e_asq_cmd_details *cmd_details)
1926{
1927 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1928 i40e_aqc_opc_query_switching_comp_bw_config,
1929 cmd_details);
1930}
1931
1932/**
1933 * i40e_validate_filter_settings
1934 * @hw: pointer to the hardware structure
1935 * @settings: Filter control settings
1936 *
1937 * Check and validate the filter control settings passed.
1938 * The function checks for the valid filter/context sizes being
1939 * passed for FCoE and PE.
1940 *
1941 * Returns 0 if the values passed are valid and within
1942 * range else returns an error.
1943 **/
1944static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
1945 struct i40e_filter_control_settings *settings)
1946{
1947 u32 fcoe_cntx_size, fcoe_filt_size;
1948 u32 pe_cntx_size, pe_filt_size;
1949 u32 fcoe_fmax, pe_fmax;
1950 u32 val;
1951
1952 /* Validate FCoE settings passed */
1953 switch (settings->fcoe_filt_num) {
1954 case I40E_HASH_FILTER_SIZE_1K:
1955 case I40E_HASH_FILTER_SIZE_2K:
1956 case I40E_HASH_FILTER_SIZE_4K:
1957 case I40E_HASH_FILTER_SIZE_8K:
1958 case I40E_HASH_FILTER_SIZE_16K:
1959 case I40E_HASH_FILTER_SIZE_32K:
1960 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
1961 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
1962 break;
1963 default:
1964 return I40E_ERR_PARAM;
1965 }
1966
1967 switch (settings->fcoe_cntx_num) {
1968 case I40E_DMA_CNTX_SIZE_512:
1969 case I40E_DMA_CNTX_SIZE_1K:
1970 case I40E_DMA_CNTX_SIZE_2K:
1971 case I40E_DMA_CNTX_SIZE_4K:
1972 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
1973 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
1974 break;
1975 default:
1976 return I40E_ERR_PARAM;
1977 }
1978
1979 /* Validate PE settings passed */
1980 switch (settings->pe_filt_num) {
1981 case I40E_HASH_FILTER_SIZE_1K:
1982 case I40E_HASH_FILTER_SIZE_2K:
1983 case I40E_HASH_FILTER_SIZE_4K:
1984 case I40E_HASH_FILTER_SIZE_8K:
1985 case I40E_HASH_FILTER_SIZE_16K:
1986 case I40E_HASH_FILTER_SIZE_32K:
1987 case I40E_HASH_FILTER_SIZE_64K:
1988 case I40E_HASH_FILTER_SIZE_128K:
1989 case I40E_HASH_FILTER_SIZE_256K:
1990 case I40E_HASH_FILTER_SIZE_512K:
1991 case I40E_HASH_FILTER_SIZE_1M:
1992 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
1993 pe_filt_size <<= (u32)settings->pe_filt_num;
1994 break;
1995 default:
1996 return I40E_ERR_PARAM;
1997 }
1998
1999 switch (settings->pe_cntx_num) {
2000 case I40E_DMA_CNTX_SIZE_512:
2001 case I40E_DMA_CNTX_SIZE_1K:
2002 case I40E_DMA_CNTX_SIZE_2K:
2003 case I40E_DMA_CNTX_SIZE_4K:
2004 case I40E_DMA_CNTX_SIZE_8K:
2005 case I40E_DMA_CNTX_SIZE_16K:
2006 case I40E_DMA_CNTX_SIZE_32K:
2007 case I40E_DMA_CNTX_SIZE_64K:
2008 case I40E_DMA_CNTX_SIZE_128K:
2009 case I40E_DMA_CNTX_SIZE_256K:
2010 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2011 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2012 break;
2013 default:
2014 return I40E_ERR_PARAM;
2015 }
2016
2017 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2018 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2019 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2020 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2021 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2022 return I40E_ERR_INVALID_SIZE;
2023
2024 /* PEHSIZE + PEDSIZE should not be greater than PMPEXFMAX */
2025 val = rd32(hw, I40E_GLHMC_PEXFMAX);
2026 pe_fmax = (val & I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK)
2027 >> I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT;
2028 if (pe_filt_size + pe_cntx_size > pe_fmax)
2029 return I40E_ERR_INVALID_SIZE;
2030
2031 return 0;
2032}
2033
2034/**
2035 * i40e_set_filter_control
2036 * @hw: pointer to the hardware structure
2037 * @settings: Filter control settings
2038 *
2039 * Set the Queue Filters for PE/FCoE and enable filters required
2040 * for a single PF. It is expected that these settings are programmed
2041 * at the driver initialization time.
2042 **/
2043i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2044 struct i40e_filter_control_settings *settings)
2045{
2046 i40e_status ret = 0;
2047 u32 hash_lut_size = 0;
2048 u32 val;
2049
2050 if (!settings)
2051 return I40E_ERR_PARAM;
2052
2053 /* Validate the input settings */
2054 ret = i40e_validate_filter_settings(hw, settings);
2055 if (ret)
2056 return ret;
2057
2058 /* Read the PF Queue Filter control register */
2059 val = rd32(hw, I40E_PFQF_CTL_0);
2060
2061 /* Program required PE hash buckets for the PF */
2062 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2063 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2064 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2065 /* Program required PE contexts for the PF */
2066 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2067 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2068 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2069
2070 /* Program required FCoE hash buckets for the PF */
2071 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2072 val |= ((u32)settings->fcoe_filt_num <<
2073 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2074 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2075 /* Program required FCoE DDP contexts for the PF */
2076 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2077 val |= ((u32)settings->fcoe_cntx_num <<
2078 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2079 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2080
2081 /* Program Hash LUT size for the PF */
2082 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2083 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2084 hash_lut_size = 1;
2085 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2086 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2087
2088 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2089 if (settings->enable_fdir)
2090 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2091 if (settings->enable_ethtype)
2092 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2093 if (settings->enable_macvlan)
2094 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2095
2096 wr32(hw, I40E_PFQF_CTL_0, val);
2097
2098 return 0;
2099}
d4dfb81a
CS		 2100/**
2101 * i40e_set_pci_config_data - store PCI bus info
2102 * @hw: pointer to hardware structure
2103 * @link_status: the link status word from PCI config space
2104 *
2105 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
2106 **/
2107void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
2108{
2109 hw->bus.type = i40e_bus_type_pci_express;
2110
2111 switch (link_status & PCI_EXP_LNKSTA_NLW) {
2112 case PCI_EXP_LNKSTA_NLW_X1:
2113 hw->bus.width = i40e_bus_width_pcie_x1;
2114 break;
2115 case PCI_EXP_LNKSTA_NLW_X2:
2116 hw->bus.width = i40e_bus_width_pcie_x2;
2117 break;
2118 case PCI_EXP_LNKSTA_NLW_X4:
2119 hw->bus.width = i40e_bus_width_pcie_x4;
2120 break;
2121 case PCI_EXP_LNKSTA_NLW_X8:
2122 hw->bus.width = i40e_bus_width_pcie_x8;
2123 break;
2124 default:
2125 hw->bus.width = i40e_bus_width_unknown;
2126 break;
2127 }
2128
2129 switch (link_status & PCI_EXP_LNKSTA_CLS) {
2130 case PCI_EXP_LNKSTA_CLS_2_5GB:
2131 hw->bus.speed = i40e_bus_speed_2500;
2132 break;
2133 case PCI_EXP_LNKSTA_CLS_5_0GB:
2134 hw->bus.speed = i40e_bus_speed_5000;
2135 break;
2136 case PCI_EXP_LNKSTA_CLS_8_0GB:
2137 hw->bus.speed = i40e_bus_speed_8000;
2138 break;
2139 default:
2140 hw->bus.speed = i40e_bus_speed_unknown;
2141 break;
2142 }
2143}
Linux 6.x block layer and io_uring tree(s)