projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i40e: check MAC type before any REG access
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#include "i40e_type.h"
29#include "i40e_adminq.h"
30#include "i40e_prototype.h"
31#include "i40e_virtchnl.h"
32
33/**
34 * i40e_set_mac_type - Sets MAC type
35 * @hw: pointer to the HW structure
36 *
37 * This function sets the mac type of the adapter based on the
38 * vendor ID and device ID stored in the hw structure.
39 **/
40static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
41{
42 i40e_status status = 0;
43
44 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
45 switch (hw->device_id) {
46 case I40E_SFP_XL710_DEVICE_ID:
47 case I40E_SFP_X710_DEVICE_ID:
48 case I40E_QEMU_DEVICE_ID:
49 case I40E_KX_A_DEVICE_ID:
50 case I40E_KX_B_DEVICE_ID:
51 case I40E_KX_C_DEVICE_ID:
52 case I40E_KX_D_DEVICE_ID:
53 case I40E_QSFP_A_DEVICE_ID:
54 case I40E_QSFP_B_DEVICE_ID:
55 case I40E_QSFP_C_DEVICE_ID:
56 hw->mac.type = I40E_MAC_XL710;
57 break;
58 case I40E_VF_DEVICE_ID:
59 case I40E_VF_HV_DEVICE_ID:
60 hw->mac.type = I40E_MAC_VF;
61 break;
62 default:
63 hw->mac.type = I40E_MAC_GENERIC;
64 break;
65 }
66 } else {
67 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
68 }
69
70 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
71 hw->mac.type, status);
72 return status;
73}
74
75/**
76 * i40e_debug_aq
77 * @hw: debug mask related to admin queue
78 * @cap: pointer to adminq command descriptor
79 * @buffer: pointer to command buffer
80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
84 void *buffer)
85{
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
87 u8 *aq_buffer = (u8 *)buffer;
88 u32 data[4];
89 u32 i = 0;
90
91 if ((!(mask & hw->debug_mask)) || (desc == NULL))
92 return;
93
94 i40e_debug(hw, mask,
95 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
96 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
97 aq_desc->retval);
98 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
99 aq_desc->cookie_high, aq_desc->cookie_low);
100 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
101 aq_desc->params.internal.param0,
102 aq_desc->params.internal.param1);
103 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
104 aq_desc->params.external.addr_high,
105 aq_desc->params.external.addr_low);
106
107 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
108 memset(data, 0, sizeof(data));
109 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
110 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
111 data[((i % 16) / 4)] |=
112 ((u32)aq_buffer[i]) << (8 * (i % 4));
113 if ((i % 16) == 15) {
114 i40e_debug(hw, mask,
115 "\t0x%04X %08X %08X %08X %08X\n",
116 i - 15, data[0], data[1], data[2],
117 data[3]);
118 memset(data, 0, sizeof(data));
119 }
120 }
121 if ((i % 16) != 0)
122 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
123 i - (i % 16), data[0], data[1], data[2],
124 data[3]);
125 }
126}
127
e1860d8f
ASJ		 128/**
129 * i40e_check_asq_alive
130 * @hw: pointer to the hw struct
131 *
132 * Returns true if Queue is enabled else false.
133 **/
134bool i40e_check_asq_alive(struct i40e_hw *hw)
135{
136 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
137}
138
139/**
140 * i40e_aq_queue_shutdown
141 * @hw: pointer to the hw struct
142 * @unloading: is the driver unloading itself
143 *
144 * Tell the Firmware that we're shutting down the AdminQ and whether
145 * or not the driver is unloading as well.
146 **/
147i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
148 bool unloading)
149{
150 struct i40e_aq_desc desc;
151 struct i40e_aqc_queue_shutdown *cmd =
152 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
153 i40e_status status;
154
155 i40e_fill_default_direct_cmd_desc(&desc,
156 i40e_aqc_opc_queue_shutdown);
157
158 if (unloading)
159 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
160 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
161
162 return status;
163}
164
165
56a62fc8
JB		 166/**
167 * i40e_init_shared_code - Initialize the shared code
168 * @hw: pointer to hardware structure
169 *
170 * This assigns the MAC type and PHY code and inits the NVM.
171 * Does not touch the hardware. This function must be called prior to any
172 * other function in the shared code. The i40e_hw structure should be
173 * memset to 0 prior to calling this function. The following fields in
174 * hw structure should be filled in prior to calling this function:
175 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
176 * subsystem_vendor_id, and revision_id
177 **/
178i40e_status i40e_init_shared_code(struct i40e_hw *hw)
179{
180 i40e_status status = 0;
181 u32 reg;
182
56a62fc8
JB		 183 i40e_set_mac_type(hw);
184
185 switch (hw->mac.type) {
186 case I40E_MAC_XL710:
187 break;
188 default:
189 return I40E_ERR_DEVICE_NOT_SUPPORTED;
190 break;
191 }
192
af89d26c
SN		 193 hw->phy.get_link_info = true;
194
195 /* Determine port number */
196 reg = rd32(hw, I40E_PFGEN_PORTNUM);
197 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
198 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
199 hw->port = (u8)reg;
200
5f9116ac
SN		 201 /* Determine the PF number based on the PCI fn */
202 reg = rd32(hw, I40E_GLPCI_CAPSUP);
203 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
204 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
205 else
206 hw->pf_id = (u8)hw->bus.func;
207
56a62fc8
JB		 208 status = i40e_init_nvm(hw);
209 return status;
210}
211
212/**
213 * i40e_aq_mac_address_read - Retrieve the MAC addresses
214 * @hw: pointer to the hw struct
215 * @flags: a return indicator of what addresses were added to the addr store
216 * @addrs: the requestor's mac addr store
217 * @cmd_details: pointer to command details structure or NULL
218 **/
219static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
220 u16 *flags,
221 struct i40e_aqc_mac_address_read_data *addrs,
222 struct i40e_asq_cmd_details *cmd_details)
223{
224 struct i40e_aq_desc desc;
225 struct i40e_aqc_mac_address_read *cmd_data =
226 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
227 i40e_status status;
228
229 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
230 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
231
232 status = i40e_asq_send_command(hw, &desc, addrs,
233 sizeof(*addrs), cmd_details);
234 *flags = le16_to_cpu(cmd_data->command_flags);
235
236 return status;
237}
238
239/**
240 * i40e_aq_mac_address_write - Change the MAC addresses
241 * @hw: pointer to the hw struct
242 * @flags: indicates which MAC to be written
243 * @mac_addr: address to write
244 * @cmd_details: pointer to command details structure or NULL
245 **/
246i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
247 u16 flags, u8 *mac_addr,
248 struct i40e_asq_cmd_details *cmd_details)
249{
250 struct i40e_aq_desc desc;
251 struct i40e_aqc_mac_address_write *cmd_data =
252 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
253 i40e_status status;
254
255 i40e_fill_default_direct_cmd_desc(&desc,
256 i40e_aqc_opc_mac_address_write);
257 cmd_data->command_flags = cpu_to_le16(flags);
258 memcpy(&cmd_data->mac_sal, &mac_addr[0], 4);
259 memcpy(&cmd_data->mac_sah, &mac_addr[4], 2);
260
261 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
262
263 return status;
264}
265
266/**
267 * i40e_get_mac_addr - get MAC address
268 * @hw: pointer to the HW structure
269 * @mac_addr: pointer to MAC address
270 *
271 * Reads the adapter's MAC address from register
272 **/
273i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
274{
275 struct i40e_aqc_mac_address_read_data addrs;
276 i40e_status status;
277 u16 flags = 0;
278
279 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
280
281 if (flags & I40E_AQC_LAN_ADDR_VALID)
282 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
283
284 return status;
285}
286
be405eb0
JB		 287/**
288 * i40e_get_media_type - Gets media type
289 * @hw: pointer to the hardware structure
290 **/
291static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
292{
293 enum i40e_media_type media;
294
295 switch (hw->phy.link_info.phy_type) {
296 case I40E_PHY_TYPE_10GBASE_SR:
297 case I40E_PHY_TYPE_10GBASE_LR:
298 case I40E_PHY_TYPE_40GBASE_SR4:
299 case I40E_PHY_TYPE_40GBASE_LR4:
300 media = I40E_MEDIA_TYPE_FIBER;
301 break;
302 case I40E_PHY_TYPE_100BASE_TX:
303 case I40E_PHY_TYPE_1000BASE_T:
304 case I40E_PHY_TYPE_10GBASE_T:
305 media = I40E_MEDIA_TYPE_BASET;
306 break;
307 case I40E_PHY_TYPE_10GBASE_CR1_CU:
308 case I40E_PHY_TYPE_40GBASE_CR4_CU:
309 case I40E_PHY_TYPE_10GBASE_CR1:
310 case I40E_PHY_TYPE_40GBASE_CR4:
311 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
312 media = I40E_MEDIA_TYPE_DA;
313 break;
314 case I40E_PHY_TYPE_1000BASE_KX:
315 case I40E_PHY_TYPE_10GBASE_KX4:
316 case I40E_PHY_TYPE_10GBASE_KR:
317 case I40E_PHY_TYPE_40GBASE_KR4:
318 media = I40E_MEDIA_TYPE_BACKPLANE;
319 break;
320 case I40E_PHY_TYPE_SGMII:
321 case I40E_PHY_TYPE_XAUI:
322 case I40E_PHY_TYPE_XFI:
323 case I40E_PHY_TYPE_XLAUI:
324 case I40E_PHY_TYPE_XLPPI:
325 default:
326 media = I40E_MEDIA_TYPE_UNKNOWN;
327 break;
328 }
329
330 return media;
331}
332
7134f9ce
JB		 333#define I40E_PF_RESET_WAIT_COUNT_A0 200
334#define I40E_PF_RESET_WAIT_COUNT 10
56a62fc8
JB		 335/**
336 * i40e_pf_reset - Reset the PF
337 * @hw: pointer to the hardware structure
338 *
339 * Assuming someone else has triggered a global reset,
340 * assure the global reset is complete and then reset the PF
341 **/
342i40e_status i40e_pf_reset(struct i40e_hw *hw)
343{
7134f9ce 344 u32 cnt = 0;
42794bd8 345 u32 cnt1 = 0;
56a62fc8
JB		 346 u32 reg = 0;
347 u32 grst_del;
348
349 /* Poll for Global Reset steady state in case of recent GRST.
350 * The grst delay value is in 100ms units, and we'll wait a
351 * couple counts longer to be sure we don't just miss the end.
352 */
353 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
354 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
7134f9ce 355 for (cnt = 0; cnt < grst_del + 2; cnt++) {
56a62fc8
JB		 356 reg = rd32(hw, I40E_GLGEN_RSTAT);
357 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
358 break;
359 msleep(100);
360 }
361 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
362 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 363 return I40E_ERR_RESET_FAILED;
364 }
365
366 /* Now Wait for the FW to be ready */
367 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
368 reg = rd32(hw, I40E_GLNVM_ULD);
369 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
370 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
371 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
372 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
373 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
374 break;
375 }
376 usleep_range(10000, 20000);
377 }
378 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
379 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
380 hw_dbg(hw, "wait for FW Reset complete timedout\n");
381 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 382 return I40E_ERR_RESET_FAILED;
383 }
384
56a62fc8
JB		 385 /* If there was a Global Reset in progress when we got here,
386 * we don't need to do the PF Reset
387 */
7134f9ce
JB		 388 if (!cnt) {
389 if (hw->revision_id == 0)
390 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
391 else
392 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 393 reg = rd32(hw, I40E_PFGEN_CTRL);
394 wr32(hw, I40E_PFGEN_CTRL,
395 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 396 for (; cnt; cnt--) {
56a62fc8
JB		 397 reg = rd32(hw, I40E_PFGEN_CTRL);
398 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
399 break;
400 usleep_range(1000, 2000);
401 }
402 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
403 hw_dbg(hw, "PF reset polling failed to complete.\n");
404 return I40E_ERR_RESET_FAILED;
405 }
406 }
407
408 i40e_clear_pxe_mode(hw);
409 return 0;
410}
411
412/**
413 * i40e_clear_pxe_mode - clear pxe operations mode
414 * @hw: pointer to the hw struct
415 *
416 * Make sure all PXE mode settings are cleared, including things
417 * like descriptor fetch/write-back mode.
418 **/
419void i40e_clear_pxe_mode(struct i40e_hw *hw)
420{
421 u32 reg;
422
423 /* Clear single descriptor fetch/write-back mode */
424 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 425
426 if (hw->revision_id == 0) {
427 /* As a work around clear PXE_MODE instead of setting it */
428 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
429 } else {
430 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
431 }
56a62fc8
JB		 432}
433
0556a9e3
JB		 434/**
435 * i40e_led_is_mine - helper to find matching led
436 * @hw: pointer to the hw struct
437 * @idx: index into GPIO registers
438 *
439 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
440 */
441static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
442{
443 u32 gpio_val = 0;
444 u32 port;
445
446 if (!hw->func_caps.led[idx])
447 return 0;
448
449 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
450 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
451 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
452
453 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
454 * if it is not our port then ignore
455 */
456 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
457 (port != hw->port))
458 return 0;
459
460 return gpio_val;
461}
462
463#define I40E_LED0 22
464#define I40E_LINK_ACTIVITY 0xC
465
56a62fc8
JB		 466/**
467 * i40e_led_get - return current on/off mode
468 * @hw: pointer to the hw struct
469 *
470 * The value returned is the 'mode' field as defined in the
471 * GPIO register definitions: 0x0 = off, 0xf = on, and other
472 * values are variations of possible behaviors relating to
473 * blink, link, and wire.
474 **/
475u32 i40e_led_get(struct i40e_hw *hw)
476{
56a62fc8 477 u32 mode = 0;
56a62fc8
JB		 478 int i;
479
0556a9e3
JB		 480 /* as per the documentation GPIO 22-29 are the LED
481 * GPIO pins named LED0..LED7
482 */
483 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
484 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 485
0556a9e3 486 if (!gpio_val)
56a62fc8
JB		 487 continue;
488
0556a9e3
JB		 489 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
490 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 491 break;
492 }
493
494 return mode;
495}
496
497/**
498 * i40e_led_set - set new on/off mode
499 * @hw: pointer to the hw struct
0556a9e3
JB		 500 * @mode: 0=off, 0xf=on (else see manual for mode details)
501 * @blink: true if the LED should blink when on, false if steady
502 *
503 * if this function is used to turn on the blink it should
504 * be used to disable the blink when restoring the original state.
56a62fc8 505 **/
0556a9e3 506void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 507{
56a62fc8
JB		 508 int i;
509
0556a9e3
JB		 510 if (mode & 0xfffffff0)
511 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 512
0556a9e3
JB		 513 /* as per the documentation GPIO 22-29 are the LED
514 * GPIO pins named LED0..LED7
515 */
516 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
517 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 518
0556a9e3 519 if (!gpio_val)
56a62fc8
JB		 520 continue;
521
56a62fc8 522 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 523 /* this & is a bit of paranoia, but serves as a range check */
524 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
525 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
526
527 if (mode == I40E_LINK_ACTIVITY)
528 blink = false;
529
530 gpio_val |= (blink ? 1 : 0) <<
531 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
532
56a62fc8 533 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 534 break;
56a62fc8
JB		 535 }
536}
537
538/* Admin command wrappers */
56a62fc8
JB		 539
540/**
541 * i40e_aq_set_link_restart_an
542 * @hw: pointer to the hw struct
543 * @cmd_details: pointer to command details structure or NULL
544 *
545 * Sets up the link and restarts the Auto-Negotiation over the link.
546 **/
547i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
548 struct i40e_asq_cmd_details *cmd_details)
549{
550 struct i40e_aq_desc desc;
551 struct i40e_aqc_set_link_restart_an *cmd =
552 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
553 i40e_status status;
554
555 i40e_fill_default_direct_cmd_desc(&desc,
556 i40e_aqc_opc_set_link_restart_an);
557
558 cmd->command = I40E_AQ_PHY_RESTART_AN;
559
560 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
561
562 return status;
563}
564
565/**
566 * i40e_aq_get_link_info
567 * @hw: pointer to the hw struct
568 * @enable_lse: enable/disable LinkStatusEvent reporting
569 * @link: pointer to link status structure - optional
570 * @cmd_details: pointer to command details structure or NULL
571 *
572 * Returns the link status of the adapter.
573 **/
574i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
575 bool enable_lse, struct i40e_link_status *link,
576 struct i40e_asq_cmd_details *cmd_details)
577{
578 struct i40e_aq_desc desc;
579 struct i40e_aqc_get_link_status *resp =
580 (struct i40e_aqc_get_link_status *)&desc.params.raw;
581 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
582 i40e_status status;
583 u16 command_flags;
584
585 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
586
587 if (enable_lse)
588 command_flags = I40E_AQ_LSE_ENABLE;
589 else
590 command_flags = I40E_AQ_LSE_DISABLE;
591 resp->command_flags = cpu_to_le16(command_flags);
592
593 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
594
595 if (status)
596 goto aq_get_link_info_exit;
597
598 /* save off old link status information */
599 memcpy(&hw->phy.link_info_old, hw_link_info,
600 sizeof(struct i40e_link_status));
601
602 /* update link status */
603 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 604 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 605 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
606 hw_link_info->link_info = resp->link_info;
607 hw_link_info->an_info = resp->an_info;
608 hw_link_info->ext_info = resp->ext_info;
639dc377 609 hw_link_info->loopback = resp->loopback;
56a62fc8
JB		 610
611 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
612 hw_link_info->lse_enable = true;
613 else
614 hw_link_info->lse_enable = false;
615
616 /* save link status information */
617 if (link)
d7595a22 618 *link = *hw_link_info;
56a62fc8
JB		 619
620 /* flag cleared so helper functions don't call AQ again */
621 hw->phy.get_link_info = false;
622
623aq_get_link_info_exit:
624 return status;
625}
626
627/**
628 * i40e_aq_add_vsi
629 * @hw: pointer to the hw struct
630 * @vsi: pointer to a vsi context struct
631 * @cmd_details: pointer to command details structure or NULL
632 *
633 * Add a VSI context to the hardware.
634**/
635i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
636 struct i40e_vsi_context *vsi_ctx,
637 struct i40e_asq_cmd_details *cmd_details)
638{
639 struct i40e_aq_desc desc;
640 struct i40e_aqc_add_get_update_vsi *cmd =
641 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
642 struct i40e_aqc_add_get_update_vsi_completion *resp =
643 (struct i40e_aqc_add_get_update_vsi_completion *)
644 &desc.params.raw;
645 i40e_status status;
646
647 i40e_fill_default_direct_cmd_desc(&desc,
648 i40e_aqc_opc_add_vsi);
649
650 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
651 cmd->connection_type = vsi_ctx->connection_type;
652 cmd->vf_id = vsi_ctx->vf_num;
653 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
654
655 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
656 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
657 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
658
659 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
660 sizeof(vsi_ctx->info), cmd_details);
661
662 if (status)
663 goto aq_add_vsi_exit;
664
665 vsi_ctx->seid = le16_to_cpu(resp->seid);
666 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
667 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
668 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
669
670aq_add_vsi_exit:
671 return status;
672}
673
674/**
675 * i40e_aq_set_vsi_unicast_promiscuous
676 * @hw: pointer to the hw struct
677 * @seid: vsi number
678 * @set: set unicast promiscuous enable/disable
679 * @cmd_details: pointer to command details structure or NULL
680 **/
681i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
682 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
683{
684 struct i40e_aq_desc desc;
685 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
686 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
687 i40e_status status;
688 u16 flags = 0;
689
690 i40e_fill_default_direct_cmd_desc(&desc,
691 i40e_aqc_opc_set_vsi_promiscuous_modes);
692
693 if (set)
694 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
695
696 cmd->promiscuous_flags = cpu_to_le16(flags);
697
698 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
699
700 cmd->seid = cpu_to_le16(seid);
701 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
702
703 return status;
704}
705
706/**
707 * i40e_aq_set_vsi_multicast_promiscuous
708 * @hw: pointer to the hw struct
709 * @seid: vsi number
710 * @set: set multicast promiscuous enable/disable
711 * @cmd_details: pointer to command details structure or NULL
712 **/
713i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
714 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
715{
716 struct i40e_aq_desc desc;
717 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
718 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
719 i40e_status status;
720 u16 flags = 0;
721
722 i40e_fill_default_direct_cmd_desc(&desc,
723 i40e_aqc_opc_set_vsi_promiscuous_modes);
724
725 if (set)
726 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
727
728 cmd->promiscuous_flags = cpu_to_le16(flags);
729
730 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
731
732 cmd->seid = cpu_to_le16(seid);
733 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
734
735 return status;
736}
737
738/**
739 * i40e_aq_set_vsi_broadcast
740 * @hw: pointer to the hw struct
741 * @seid: vsi number
742 * @set_filter: true to set filter, false to clear filter
743 * @cmd_details: pointer to command details structure or NULL
744 *
745 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
746 **/
747i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
748 u16 seid, bool set_filter,
749 struct i40e_asq_cmd_details *cmd_details)
750{
751 struct i40e_aq_desc desc;
752 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
753 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
754 i40e_status status;
755
756 i40e_fill_default_direct_cmd_desc(&desc,
757 i40e_aqc_opc_set_vsi_promiscuous_modes);
758
759 if (set_filter)
760 cmd->promiscuous_flags
761 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
762 else
763 cmd->promiscuous_flags
764 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
765
766 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
767 cmd->seid = cpu_to_le16(seid);
768 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
769
770 return status;
771}
772
773/**
774 * i40e_get_vsi_params - get VSI configuration info
775 * @hw: pointer to the hw struct
776 * @vsi: pointer to a vsi context struct
777 * @cmd_details: pointer to command details structure or NULL
778 **/
779i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
780 struct i40e_vsi_context *vsi_ctx,
781 struct i40e_asq_cmd_details *cmd_details)
782{
783 struct i40e_aq_desc desc;
f5ac8579
SN		 784 struct i40e_aqc_add_get_update_vsi *cmd =
785 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 786 struct i40e_aqc_add_get_update_vsi_completion *resp =
787 (struct i40e_aqc_add_get_update_vsi_completion *)
788 &desc.params.raw;
789 i40e_status status;
790
791 i40e_fill_default_direct_cmd_desc(&desc,
792 i40e_aqc_opc_get_vsi_parameters);
793
f5ac8579 794 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 795
796 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
797 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
798 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
799
800 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
801 sizeof(vsi_ctx->info), NULL);
802
803 if (status)
804 goto aq_get_vsi_params_exit;
805
806 vsi_ctx->seid = le16_to_cpu(resp->seid);
807 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
808 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
809 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
810
811aq_get_vsi_params_exit:
812 return status;
813}
814
815/**
816 * i40e_aq_update_vsi_params
817 * @hw: pointer to the hw struct
818 * @vsi: pointer to a vsi context struct
819 * @cmd_details: pointer to command details structure or NULL
820 *
821 * Update a VSI context.
822 **/
823i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
824 struct i40e_vsi_context *vsi_ctx,
825 struct i40e_asq_cmd_details *cmd_details)
826{
827 struct i40e_aq_desc desc;
f5ac8579
SN		 828 struct i40e_aqc_add_get_update_vsi *cmd =
829 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 830 i40e_status status;
831
832 i40e_fill_default_direct_cmd_desc(&desc,
833 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 834 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 835
836 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
837 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
838 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
839
840 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
841 sizeof(vsi_ctx->info), cmd_details);
842
843 return status;
844}
845
846/**
847 * i40e_aq_get_switch_config
848 * @hw: pointer to the hardware structure
849 * @buf: pointer to the result buffer
850 * @buf_size: length of input buffer
851 * @start_seid: seid to start for the report, 0 == beginning
852 * @cmd_details: pointer to command details structure or NULL
853 *
854 * Fill the buf with switch configuration returned from AdminQ command
855 **/
856i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
857 struct i40e_aqc_get_switch_config_resp *buf,
858 u16 buf_size, u16 *start_seid,
859 struct i40e_asq_cmd_details *cmd_details)
860{
861 struct i40e_aq_desc desc;
862 struct i40e_aqc_switch_seid *scfg =
863 (struct i40e_aqc_switch_seid *)&desc.params.raw;
864 i40e_status status;
865
866 i40e_fill_default_direct_cmd_desc(&desc,
867 i40e_aqc_opc_get_switch_config);
868 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
869 if (buf_size > I40E_AQ_LARGE_BUF)
870 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
871 scfg->seid = cpu_to_le16(*start_seid);
872
873 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
874 *start_seid = le16_to_cpu(scfg->seid);
875
876 return status;
877}
878
879/**
880 * i40e_aq_get_firmware_version
881 * @hw: pointer to the hw struct
882 * @fw_major_version: firmware major version
883 * @fw_minor_version: firmware minor version
884 * @api_major_version: major queue version
885 * @api_minor_version: minor queue version
886 * @cmd_details: pointer to command details structure or NULL
887 *
888 * Get the firmware version from the admin queue commands
889 **/
890i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
891 u16 *fw_major_version, u16 *fw_minor_version,
892 u16 *api_major_version, u16 *api_minor_version,
893 struct i40e_asq_cmd_details *cmd_details)
894{
895 struct i40e_aq_desc desc;
896 struct i40e_aqc_get_version *resp =
897 (struct i40e_aqc_get_version *)&desc.params.raw;
898 i40e_status status;
899
900 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
901
902 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
903
904 if (!status) {
905 if (fw_major_version != NULL)
906 *fw_major_version = le16_to_cpu(resp->fw_major);
907 if (fw_minor_version != NULL)
908 *fw_minor_version = le16_to_cpu(resp->fw_minor);
909 if (api_major_version != NULL)
910 *api_major_version = le16_to_cpu(resp->api_major);
911 if (api_minor_version != NULL)
912 *api_minor_version = le16_to_cpu(resp->api_minor);
913 }
914
915 return status;
916}
917
918/**
919 * i40e_aq_send_driver_version
920 * @hw: pointer to the hw struct
921 * @event: driver event: driver ok, start or stop
922 * @dv: driver's major, minor version
923 * @cmd_details: pointer to command details structure or NULL
924 *
925 * Send the driver version to the firmware
926 **/
927i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
928 struct i40e_driver_version *dv,
929 struct i40e_asq_cmd_details *cmd_details)
930{
931 struct i40e_aq_desc desc;
932 struct i40e_aqc_driver_version *cmd =
933 (struct i40e_aqc_driver_version *)&desc.params.raw;
934 i40e_status status;
935
936 if (dv == NULL)
937 return I40E_ERR_PARAM;
938
939 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
940
941 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
942 cmd->driver_major_ver = dv->major_version;
943 cmd->driver_minor_ver = dv->minor_version;
944 cmd->driver_build_ver = dv->build_version;
945 cmd->driver_subbuild_ver = dv->subbuild_version;
946 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
947
948 return status;
949}
950
951/**
952 * i40e_get_link_status - get status of the HW network link
953 * @hw: pointer to the hw struct
954 *
955 * Returns true if link is up, false if link is down.
956 *
957 * Side effect: LinkStatusEvent reporting becomes enabled
958 **/
959bool i40e_get_link_status(struct i40e_hw *hw)
960{
961 i40e_status status = 0;
962 bool link_status = false;
963
964 if (hw->phy.get_link_info) {
965 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
966
967 if (status)
968 goto i40e_get_link_status_exit;
969 }
970
971 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
972
973i40e_get_link_status_exit:
974 return link_status;
975}
976
977/**
978 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
979 * @hw: pointer to the hw struct
980 * @uplink_seid: the MAC or other gizmo SEID
981 * @downlink_seid: the VSI SEID
982 * @enabled_tc: bitmap of TCs to be enabled
983 * @default_port: true for default port VSI, false for control port
e1c51b95 984 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 985 * @veb_seid: pointer to where to put the resulting VEB SEID
986 * @cmd_details: pointer to command details structure or NULL
987 *
988 * This asks the FW to add a VEB between the uplink and downlink
989 * elements. If the uplink SEID is 0, this will be a floating VEB.
990 **/
991i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
992 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 993 bool default_port, bool enable_l2_filtering,
994 u16 *veb_seid,
56a62fc8
JB		 995 struct i40e_asq_cmd_details *cmd_details)
996{
997 struct i40e_aq_desc desc;
998 struct i40e_aqc_add_veb *cmd =
999 (struct i40e_aqc_add_veb *)&desc.params.raw;
1000 struct i40e_aqc_add_veb_completion *resp =
1001 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1002 i40e_status status;
1003 u16 veb_flags = 0;
1004
1005 /* SEIDs need to either both be set or both be 0 for floating VEB */
1006 if (!!uplink_seid != !!downlink_seid)
1007 return I40E_ERR_PARAM;
1008
1009 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1010
1011 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1012 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1013 cmd->enable_tcs = enabled_tc;
1014 if (!uplink_seid)
1015 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1016 if (default_port)
1017 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1018 else
1019 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 1020
1021 if (enable_l2_filtering)
1022 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1023
56a62fc8
JB		 1024 cmd->veb_flags = cpu_to_le16(veb_flags);
1025
1026 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1027
1028 if (!status && veb_seid)
1029 *veb_seid = le16_to_cpu(resp->veb_seid);
1030
1031 return status;
1032}
1033
1034/**
1035 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1036 * @hw: pointer to the hw struct
1037 * @veb_seid: the SEID of the VEB to query
1038 * @switch_id: the uplink switch id
1039 * @floating_veb: set to true if the VEB is floating
1040 * @statistic_index: index of the stats counter block for this VEB
1041 * @vebs_used: number of VEB's used by function
1042 * @vebs_unallocated: total VEB's not reserved by any function
1043 * @cmd_details: pointer to command details structure or NULL
1044 *
1045 * This retrieves the parameters for a particular VEB, specified by
1046 * uplink_seid, and returns them to the caller.
1047 **/
1048i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1049 u16 veb_seid, u16 *switch_id,
1050 bool *floating, u16 *statistic_index,
1051 u16 *vebs_used, u16 *vebs_free,
1052 struct i40e_asq_cmd_details *cmd_details)
1053{
1054 struct i40e_aq_desc desc;
1055 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1056 (struct i40e_aqc_get_veb_parameters_completion *)
1057 &desc.params.raw;
1058 i40e_status status;
1059
1060 if (veb_seid == 0)
1061 return I40E_ERR_PARAM;
1062
1063 i40e_fill_default_direct_cmd_desc(&desc,
1064 i40e_aqc_opc_get_veb_parameters);
1065 cmd_resp->seid = cpu_to_le16(veb_seid);
1066
1067 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1068 if (status)
1069 goto get_veb_exit;
1070
1071 if (switch_id)
1072 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1073 if (statistic_index)
1074 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1075 if (vebs_used)
1076 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1077 if (vebs_free)
1078 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1079 if (floating) {
1080 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1081 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1082 *floating = true;
1083 else
1084 *floating = false;
1085 }
1086
1087get_veb_exit:
1088 return status;
1089}
1090
1091/**
1092 * i40e_aq_add_macvlan
1093 * @hw: pointer to the hw struct
1094 * @seid: VSI for the mac address
1095 * @mv_list: list of macvlans to be added
1096 * @count: length of the list
1097 * @cmd_details: pointer to command details structure or NULL
1098 *
1099 * Add MAC/VLAN addresses to the HW filtering
1100 **/
1101i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1102 struct i40e_aqc_add_macvlan_element_data *mv_list,
1103 u16 count, struct i40e_asq_cmd_details *cmd_details)
1104{
1105 struct i40e_aq_desc desc;
1106 struct i40e_aqc_macvlan *cmd =
1107 (struct i40e_aqc_macvlan *)&desc.params.raw;
1108 i40e_status status;
1109 u16 buf_size;
1110
1111 if (count == 0 || !mv_list || !hw)
1112 return I40E_ERR_PARAM;
1113
1114 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1115
1116 /* prep the rest of the request */
1117 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1118 cmd->num_addresses = cpu_to_le16(count);
1119 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1120 cmd->seid[1] = 0;
1121 cmd->seid[2] = 0;
1122
1123 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1124 if (buf_size > I40E_AQ_LARGE_BUF)
1125 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1126
1127 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1128 cmd_details);
1129
1130 return status;
1131}
1132
1133/**
1134 * i40e_aq_remove_macvlan
1135 * @hw: pointer to the hw struct
1136 * @seid: VSI for the mac address
1137 * @mv_list: list of macvlans to be removed
1138 * @count: length of the list
1139 * @cmd_details: pointer to command details structure or NULL
1140 *
1141 * Remove MAC/VLAN addresses from the HW filtering
1142 **/
1143i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1144 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1145 u16 count, struct i40e_asq_cmd_details *cmd_details)
1146{
1147 struct i40e_aq_desc desc;
1148 struct i40e_aqc_macvlan *cmd =
1149 (struct i40e_aqc_macvlan *)&desc.params.raw;
1150 i40e_status status;
1151 u16 buf_size;
1152
1153 if (count == 0 || !mv_list || !hw)
1154 return I40E_ERR_PARAM;
1155
1156 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1157
1158 /* prep the rest of the request */
1159 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1160 cmd->num_addresses = cpu_to_le16(count);
1161 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1162 cmd->seid[1] = 0;
1163 cmd->seid[2] = 0;
1164
1165 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1166 if (buf_size > I40E_AQ_LARGE_BUF)
1167 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1168
1169 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1170 cmd_details);
1171
1172 return status;
1173}
1174
56a62fc8
JB		 1175/**
1176 * i40e_aq_send_msg_to_vf
1177 * @hw: pointer to the hardware structure
1178 * @vfid: vf id to send msg
1179 * @msg: pointer to the msg buffer
1180 * @msglen: msg length
1181 * @cmd_details: pointer to command details
1182 *
1183 * send msg to vf
1184 **/
1185i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1186 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1187 struct i40e_asq_cmd_details *cmd_details)
1188{
1189 struct i40e_aq_desc desc;
1190 struct i40e_aqc_pf_vf_message *cmd =
1191 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1192 i40e_status status;
1193
1194 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1195 cmd->id = cpu_to_le32(vfid);
1196 desc.cookie_high = cpu_to_le32(v_opcode);
1197 desc.cookie_low = cpu_to_le32(v_retval);
1198 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1199 if (msglen) {
1200 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1201 I40E_AQ_FLAG_RD));
1202 if (msglen > I40E_AQ_LARGE_BUF)
1203 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1204 desc.datalen = cpu_to_le16(msglen);
1205 }
1206 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1207
1208 return status;
1209}
1210
1211/**
1212 * i40e_aq_set_hmc_resource_profile
1213 * @hw: pointer to the hw struct
1214 * @profile: type of profile the HMC is to be set as
1215 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1216 * @cmd_details: pointer to command details structure or NULL
1217 *
1218 * set the HMC profile of the device.
1219 **/
1220i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1221 enum i40e_aq_hmc_profile profile,
1222 u8 pe_vf_enabled_count,
1223 struct i40e_asq_cmd_details *cmd_details)
1224{
1225 struct i40e_aq_desc desc;
1226 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1227 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1228 i40e_status status;
1229
1230 i40e_fill_default_direct_cmd_desc(&desc,
1231 i40e_aqc_opc_set_hmc_resource_profile);
1232
1233 cmd->pm_profile = (u8)profile;
1234 cmd->pe_vf_enabled = pe_vf_enabled_count;
1235
1236 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1237
1238 return status;
1239}
1240
1241/**
1242 * i40e_aq_request_resource
1243 * @hw: pointer to the hw struct
1244 * @resource: resource id
1245 * @access: access type
1246 * @sdp_number: resource number
1247 * @timeout: the maximum time in ms that the driver may hold the resource
1248 * @cmd_details: pointer to command details structure or NULL
1249 *
1250 * requests common resource using the admin queue commands
1251 **/
1252i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1253 enum i40e_aq_resources_ids resource,
1254 enum i40e_aq_resource_access_type access,
1255 u8 sdp_number, u64 *timeout,
1256 struct i40e_asq_cmd_details *cmd_details)
1257{
1258 struct i40e_aq_desc desc;
1259 struct i40e_aqc_request_resource *cmd_resp =
1260 (struct i40e_aqc_request_resource *)&desc.params.raw;
1261 i40e_status status;
1262
1263 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
1264
1265 cmd_resp->resource_id = cpu_to_le16(resource);
1266 cmd_resp->access_type = cpu_to_le16(access);
1267 cmd_resp->resource_number = cpu_to_le32(sdp_number);
1268
1269 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1270 /* The completion specifies the maximum time in ms that the driver
1271 * may hold the resource in the Timeout field.
1272 * If the resource is held by someone else, the command completes with
1273 * busy return value and the timeout field indicates the maximum time
1274 * the current owner of the resource has to free it.
1275 */
1276 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
1277 *timeout = le32_to_cpu(cmd_resp->timeout);
1278
1279 return status;
1280}
1281
1282/**
1283 * i40e_aq_release_resource
1284 * @hw: pointer to the hw struct
1285 * @resource: resource id
1286 * @sdp_number: resource number
1287 * @cmd_details: pointer to command details structure or NULL
1288 *
1289 * release common resource using the admin queue commands
1290 **/
1291i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
1292 enum i40e_aq_resources_ids resource,
1293 u8 sdp_number,
1294 struct i40e_asq_cmd_details *cmd_details)
1295{
1296 struct i40e_aq_desc desc;
1297 struct i40e_aqc_request_resource *cmd =
1298 (struct i40e_aqc_request_resource *)&desc.params.raw;
1299 i40e_status status;
1300
1301 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
1302
1303 cmd->resource_id = cpu_to_le16(resource);
1304 cmd->resource_number = cpu_to_le32(sdp_number);
1305
1306 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1307
1308 return status;
1309}
1310
1311/**
1312 * i40e_aq_read_nvm
1313 * @hw: pointer to the hw struct
1314 * @module_pointer: module pointer location in words from the NVM beginning
1315 * @offset: byte offset from the module beginning
1316 * @length: length of the section to be read (in bytes from the offset)
1317 * @data: command buffer (size [bytes] = length)
1318 * @last_command: tells if this is the last command in a series
1319 * @cmd_details: pointer to command details structure or NULL
1320 *
1321 * Read the NVM using the admin queue commands
1322 **/
1323i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
1324 u32 offset, u16 length, void *data,
1325 bool last_command,
1326 struct i40e_asq_cmd_details *cmd_details)
1327{
1328 struct i40e_aq_desc desc;
1329 struct i40e_aqc_nvm_update *cmd =
1330 (struct i40e_aqc_nvm_update *)&desc.params.raw;
1331 i40e_status status;
1332
1333 /* In offset the highest byte must be zeroed. */
1334 if (offset & 0xFF000000) {
1335 status = I40E_ERR_PARAM;
1336 goto i40e_aq_read_nvm_exit;
1337 }
1338
1339 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
1340
1341 /* If this is the last command in a series, set the proper flag. */
1342 if (last_command)
1343 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
1344 cmd->module_pointer = module_pointer;
1345 cmd->offset = cpu_to_le32(offset);
1346 cmd->length = cpu_to_le16(length);
1347
1348 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1349 if (length > I40E_AQ_LARGE_BUF)
1350 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1351
1352 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
1353
1354i40e_aq_read_nvm_exit:
1355 return status;
1356}
1357
1358#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1359#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1360#define I40E_DEV_FUNC_CAP_NPAR 0x03
1361#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1362#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1363#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1364#define I40E_DEV_FUNC_CAP_VF 0x13
1365#define I40E_DEV_FUNC_CAP_VMDQ 0x14
1366#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1367#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1368#define I40E_DEV_FUNC_CAP_VSI 0x17
1369#define I40E_DEV_FUNC_CAP_DCB 0x18
1370#define I40E_DEV_FUNC_CAP_FCOE 0x21
1371#define I40E_DEV_FUNC_CAP_RSS 0x40
1372#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1373#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1374#define I40E_DEV_FUNC_CAP_MSIX 0x43
1375#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1376#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1377#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1378#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1379#define I40E_DEV_FUNC_CAP_CEM 0xF2
1380#define I40E_DEV_FUNC_CAP_IWARP 0x51
1381#define I40E_DEV_FUNC_CAP_LED 0x61
1382#define I40E_DEV_FUNC_CAP_SDP 0x62
1383#define I40E_DEV_FUNC_CAP_MDIO 0x63
1384
1385/**
1386 * i40e_parse_discover_capabilities
1387 * @hw: pointer to the hw struct
1388 * @buff: pointer to a buffer containing device/function capability records
1389 * @cap_count: number of capability records in the list
1390 * @list_type_opc: type of capabilities list to parse
1391 *
1392 * Parse the device/function capabilities list.
1393 **/
1394static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1395 u32 cap_count,
1396 enum i40e_admin_queue_opc list_type_opc)
1397{
1398 struct i40e_aqc_list_capabilities_element_resp *cap;
1399 u32 number, logical_id, phys_id;
1400 struct i40e_hw_capabilities *p;
1401 u32 reg_val;
1402 u32 i = 0;
1403 u16 id;
1404
1405 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
1406
1407 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
1408 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
1409 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
1410 p = (struct i40e_hw_capabilities *)&hw->func_caps;
1411 else
1412 return;
1413
1414 for (i = 0; i < cap_count; i++, cap++) {
1415 id = le16_to_cpu(cap->id);
1416 number = le32_to_cpu(cap->number);
1417 logical_id = le32_to_cpu(cap->logical_id);
1418 phys_id = le32_to_cpu(cap->phys_id);
1419
1420 switch (id) {
1421 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
1422 p->switch_mode = number;
1423 break;
1424 case I40E_DEV_FUNC_CAP_MGMT_MODE:
1425 p->management_mode = number;
1426 break;
1427 case I40E_DEV_FUNC_CAP_NPAR:
1428 p->npar_enable = number;
1429 break;
1430 case I40E_DEV_FUNC_CAP_OS2BMC:
1431 p->os2bmc = number;
1432 break;
1433 case I40E_DEV_FUNC_CAP_VALID_FUNC:
1434 p->valid_functions = number;
1435 break;
1436 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
1437 if (number == 1)
1438 p->sr_iov_1_1 = true;
1439 break;
1440 case I40E_DEV_FUNC_CAP_VF:
1441 p->num_vfs = number;
1442 p->vf_base_id = logical_id;
1443 break;
1444 case I40E_DEV_FUNC_CAP_VMDQ:
1445 if (number == 1)
1446 p->vmdq = true;
1447 break;
1448 case I40E_DEV_FUNC_CAP_802_1_QBG:
1449 if (number == 1)
1450 p->evb_802_1_qbg = true;
1451 break;
1452 case I40E_DEV_FUNC_CAP_802_1_QBH:
1453 if (number == 1)
1454 p->evb_802_1_qbh = true;
1455 break;
1456 case I40E_DEV_FUNC_CAP_VSI:
1457 p->num_vsis = number;
1458 break;
1459 case I40E_DEV_FUNC_CAP_DCB:
1460 if (number == 1) {
1461 p->dcb = true;
1462 p->enabled_tcmap = logical_id;
1463 p->maxtc = phys_id;
1464 }
1465 break;
1466 case I40E_DEV_FUNC_CAP_FCOE:
1467 if (number == 1)
1468 p->fcoe = true;
1469 break;
1470 case I40E_DEV_FUNC_CAP_RSS:
1471 p->rss = true;
1472 reg_val = rd32(hw, I40E_PFQF_CTL_0);
1473 if (reg_val & I40E_PFQF_CTL_0_HASHLUTSIZE_MASK)
1474 p->rss_table_size = number;
1475 else
1476 p->rss_table_size = 128;
1477 p->rss_table_entry_width = logical_id;
1478 break;
1479 case I40E_DEV_FUNC_CAP_RX_QUEUES:
1480 p->num_rx_qp = number;
1481 p->base_queue = phys_id;
1482 break;
1483 case I40E_DEV_FUNC_CAP_TX_QUEUES:
1484 p->num_tx_qp = number;
1485 p->base_queue = phys_id;
1486 break;
1487 case I40E_DEV_FUNC_CAP_MSIX:
1488 p->num_msix_vectors = number;
1489 break;
1490 case I40E_DEV_FUNC_CAP_MSIX_VF:
1491 p->num_msix_vectors_vf = number;
1492 break;
1493 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
1494 if (number == 1)
1495 p->mfp_mode_1 = true;
1496 break;
1497 case I40E_DEV_FUNC_CAP_CEM:
1498 if (number == 1)
1499 p->mgmt_cem = true;
1500 break;
1501 case I40E_DEV_FUNC_CAP_IWARP:
1502 if (number == 1)
1503 p->iwarp = true;
1504 break;
1505 case I40E_DEV_FUNC_CAP_LED:
1506 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1507 p->led[phys_id] = true;
1508 break;
1509 case I40E_DEV_FUNC_CAP_SDP:
1510 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1511 p->sdp[phys_id] = true;
1512 break;
1513 case I40E_DEV_FUNC_CAP_MDIO:
1514 if (number == 1) {
1515 p->mdio_port_num = phys_id;
1516 p->mdio_port_mode = logical_id;
1517 }
1518 break;
1519 case I40E_DEV_FUNC_CAP_IEEE_1588:
1520 if (number == 1)
1521 p->ieee_1588 = true;
1522 break;
1523 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
1524 p->fd = true;
1525 p->fd_filters_guaranteed = number;
1526 p->fd_filters_best_effort = logical_id;
1527 break;
1528 default:
1529 break;
1530 }
1531 }
1532
1533 /* additional HW specific goodies that might
1534 * someday be HW version specific
1535 */
1536 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
1537}
1538
1539/**
1540 * i40e_aq_discover_capabilities
1541 * @hw: pointer to the hw struct
1542 * @buff: a virtual buffer to hold the capabilities
1543 * @buff_size: Size of the virtual buffer
1544 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
1545 * @list_type_opc: capabilities type to discover - pass in the command opcode
1546 * @cmd_details: pointer to command details structure or NULL
1547 *
1548 * Get the device capabilities descriptions from the firmware
1549 **/
1550i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
1551 void *buff, u16 buff_size, u16 *data_size,
1552 enum i40e_admin_queue_opc list_type_opc,
1553 struct i40e_asq_cmd_details *cmd_details)
1554{
1555 struct i40e_aqc_list_capabilites *cmd;
1556 i40e_status status = 0;
1557 struct i40e_aq_desc desc;
1558
1559 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
1560
1561 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
1562 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
1563 status = I40E_ERR_PARAM;
1564 goto exit;
1565 }
1566
1567 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
1568
1569 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1570 if (buff_size > I40E_AQ_LARGE_BUF)
1571 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1572
1573 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1574 *data_size = le16_to_cpu(desc.datalen);
1575
1576 if (status)
1577 goto exit;
1578
1579 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
1580 list_type_opc);
1581
1582exit:
1583 return status;
1584}
1585
1586/**
1587 * i40e_aq_get_lldp_mib
1588 * @hw: pointer to the hw struct
1589 * @bridge_type: type of bridge requested
1590 * @mib_type: Local, Remote or both Local and Remote MIBs
1591 * @buff: pointer to a user supplied buffer to store the MIB block
1592 * @buff_size: size of the buffer (in bytes)
1593 * @local_len : length of the returned Local LLDP MIB
1594 * @remote_len: length of the returned Remote LLDP MIB
1595 * @cmd_details: pointer to command details structure or NULL
1596 *
1597 * Requests the complete LLDP MIB (entire packet).
1598 **/
1599i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
1600 u8 mib_type, void *buff, u16 buff_size,
1601 u16 *local_len, u16 *remote_len,
1602 struct i40e_asq_cmd_details *cmd_details)
1603{
1604 struct i40e_aq_desc desc;
1605 struct i40e_aqc_lldp_get_mib *cmd =
1606 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1607 struct i40e_aqc_lldp_get_mib *resp =
1608 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1609 i40e_status status;
1610
1611 if (buff_size == 0 || !buff)
1612 return I40E_ERR_PARAM;
1613
1614 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
1615 /* Indirect Command */
1616 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1617
1618 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
1619 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
1620 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
1621
1622 desc.datalen = cpu_to_le16(buff_size);
1623
1624 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1625 if (buff_size > I40E_AQ_LARGE_BUF)
1626 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1627
1628 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1629 if (!status) {
1630 if (local_len != NULL)
1631 *local_len = le16_to_cpu(resp->local_len);
1632 if (remote_len != NULL)
1633 *remote_len = le16_to_cpu(resp->remote_len);
1634 }
1635
1636 return status;
1637}
1638
1639/**
1640 * i40e_aq_cfg_lldp_mib_change_event
1641 * @hw: pointer to the hw struct
1642 * @enable_update: Enable or Disable event posting
1643 * @cmd_details: pointer to command details structure or NULL
1644 *
1645 * Enable or Disable posting of an event on ARQ when LLDP MIB
1646 * associated with the interface changes
1647 **/
1648i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
1649 bool enable_update,
1650 struct i40e_asq_cmd_details *cmd_details)
1651{
1652 struct i40e_aq_desc desc;
1653 struct i40e_aqc_lldp_update_mib *cmd =
1654 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
1655 i40e_status status;
1656
1657 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
1658
1659 if (!enable_update)
1660 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
1661
1662 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1663
1664 return status;
1665}
1666
1667/**
1668 * i40e_aq_stop_lldp
1669 * @hw: pointer to the hw struct
1670 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
1671 * @cmd_details: pointer to command details structure or NULL
1672 *
1673 * Stop or Shutdown the embedded LLDP Agent
1674 **/
1675i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
1676 struct i40e_asq_cmd_details *cmd_details)
1677{
1678 struct i40e_aq_desc desc;
1679 struct i40e_aqc_lldp_stop *cmd =
1680 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
1681 i40e_status status;
1682
1683 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
1684
1685 if (shutdown_agent)
1686 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
1687
1688 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1689
1690 return status;
1691}
1692
1693/**
1694 * i40e_aq_start_lldp
1695 * @hw: pointer to the hw struct
1696 * @cmd_details: pointer to command details structure or NULL
1697 *
1698 * Start the embedded LLDP Agent on all ports.
1699 **/
1700i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
1701 struct i40e_asq_cmd_details *cmd_details)
1702{
1703 struct i40e_aq_desc desc;
1704 struct i40e_aqc_lldp_start *cmd =
1705 (struct i40e_aqc_lldp_start *)&desc.params.raw;
1706 i40e_status status;
1707
1708 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
1709
1710 cmd->command = I40E_AQ_LLDP_AGENT_START;
1711
1712 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1713
1714 return status;
1715}
1716
a1c9a9d9
JK		 1717/**
1718 * i40e_aq_add_udp_tunnel
1719 * @hw: pointer to the hw struct
1720 * @udp_port: the UDP port to add
1721 * @header_len: length of the tunneling header length in DWords
1722 * @protocol_index: protocol index type
1723 * @cmd_details: pointer to command details structure or NULL
1724 **/
1725i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
1726 u16 udp_port, u8 header_len,
1727 u8 protocol_index, u8 *filter_index,
1728 struct i40e_asq_cmd_details *cmd_details)
1729{
1730 struct i40e_aq_desc desc;
1731 struct i40e_aqc_add_udp_tunnel *cmd =
1732 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
1733 struct i40e_aqc_del_udp_tunnel_completion *resp =
1734 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
1735 i40e_status status;
1736
1737 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
1738
1739 cmd->udp_port = cpu_to_le16(udp_port);
1740 cmd->header_len = header_len;
981b7545 1741 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 1742
1743 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1744
1745 if (!status)
1746 *filter_index = resp->index;
1747
1748 return status;
1749}
1750
1751/**
1752 * i40e_aq_del_udp_tunnel
1753 * @hw: pointer to the hw struct
1754 * @index: filter index
1755 * @cmd_details: pointer to command details structure or NULL
1756 **/
1757i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
1758 struct i40e_asq_cmd_details *cmd_details)
1759{
1760 struct i40e_aq_desc desc;
1761 struct i40e_aqc_remove_udp_tunnel *cmd =
1762 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
1763 i40e_status status;
1764
1765 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
1766
1767 cmd->index = index;
1768
1769 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1770
1771 return status;
1772}
1773
56a62fc8
JB		 1774/**
1775 * i40e_aq_delete_element - Delete switch element
1776 * @hw: pointer to the hw struct
1777 * @seid: the SEID to delete from the switch
1778 * @cmd_details: pointer to command details structure or NULL
1779 *
1780 * This deletes a switch element from the switch.
1781 **/
1782i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
1783 struct i40e_asq_cmd_details *cmd_details)
1784{
1785 struct i40e_aq_desc desc;
1786 struct i40e_aqc_switch_seid *cmd =
1787 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1788 i40e_status status;
1789
1790 if (seid == 0)
1791 return I40E_ERR_PARAM;
1792
1793 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
1794
1795 cmd->seid = cpu_to_le16(seid);
1796
1797 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1798
1799 return status;
1800}
1801
1802/**
1803 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
1804 * @hw: pointer to the hw struct
1805 * @seid: seid for the physical port/switching component/vsi
1806 * @buff: Indirect buffer to hold data parameters and response
1807 * @buff_size: Indirect buffer size
1808 * @opcode: Tx scheduler AQ command opcode
1809 * @cmd_details: pointer to command details structure or NULL
1810 *
1811 * Generic command handler for Tx scheduler AQ commands
1812 **/
1813static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
1814 void *buff, u16 buff_size,
1815 enum i40e_admin_queue_opc opcode,
1816 struct i40e_asq_cmd_details *cmd_details)
1817{
1818 struct i40e_aq_desc desc;
1819 struct i40e_aqc_tx_sched_ind *cmd =
1820 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
1821 i40e_status status;
1822 bool cmd_param_flag = false;
1823
1824 switch (opcode) {
1825 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
1826 case i40e_aqc_opc_configure_vsi_tc_bw:
1827 case i40e_aqc_opc_enable_switching_comp_ets:
1828 case i40e_aqc_opc_modify_switching_comp_ets:
1829 case i40e_aqc_opc_disable_switching_comp_ets:
1830 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
1831 case i40e_aqc_opc_configure_switching_comp_bw_config:
1832 cmd_param_flag = true;
1833 break;
1834 case i40e_aqc_opc_query_vsi_bw_config:
1835 case i40e_aqc_opc_query_vsi_ets_sla_config:
1836 case i40e_aqc_opc_query_switching_comp_ets_config:
1837 case i40e_aqc_opc_query_port_ets_config:
1838 case i40e_aqc_opc_query_switching_comp_bw_config:
1839 cmd_param_flag = false;
1840 break;
1841 default:
1842 return I40E_ERR_PARAM;
1843 }
1844
1845 i40e_fill_default_direct_cmd_desc(&desc, opcode);
1846
1847 /* Indirect command */
1848 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1849 if (cmd_param_flag)
1850 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
1851 if (buff_size > I40E_AQ_LARGE_BUF)
1852 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1853
1854 desc.datalen = cpu_to_le16(buff_size);
1855
1856 cmd->vsi_seid = cpu_to_le16(seid);
1857
1858 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1859
1860 return status;
1861}
1862
1863/**
1864 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
1865 * @hw: pointer to the hw struct
1866 * @seid: VSI seid
1867 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
1868 * @cmd_details: pointer to command details structure or NULL
1869 **/
1870i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
1871 u16 seid,
1872 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
1873 struct i40e_asq_cmd_details *cmd_details)
1874{
1875 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1876 i40e_aqc_opc_configure_vsi_tc_bw,
1877 cmd_details);
1878}
1879
1880/**
1881 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
1882 * @hw: pointer to the hw struct
1883 * @seid: seid of the VSI
1884 * @bw_data: Buffer to hold VSI BW configuration
1885 * @cmd_details: pointer to command details structure or NULL
1886 **/
1887i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
1888 u16 seid,
1889 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
1890 struct i40e_asq_cmd_details *cmd_details)
1891{
1892 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1893 i40e_aqc_opc_query_vsi_bw_config,
1894 cmd_details);
1895}
1896
1897/**
1898 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
1899 * @hw: pointer to the hw struct
1900 * @seid: seid of the VSI
1901 * @bw_data: Buffer to hold VSI BW configuration per TC
1902 * @cmd_details: pointer to command details structure or NULL
1903 **/
1904i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
1905 u16 seid,
1906 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
1907 struct i40e_asq_cmd_details *cmd_details)
1908{
1909 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1910 i40e_aqc_opc_query_vsi_ets_sla_config,
1911 cmd_details);
1912}
1913
1914/**
1915 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
1916 * @hw: pointer to the hw struct
1917 * @seid: seid of the switching component
1918 * @bw_data: Buffer to hold switching component's per TC BW config
1919 * @cmd_details: pointer to command details structure or NULL
1920 **/
1921i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
1922 u16 seid,
1923 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
1924 struct i40e_asq_cmd_details *cmd_details)
1925{
1926 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1927 i40e_aqc_opc_query_switching_comp_ets_config,
1928 cmd_details);
1929}
1930
1931/**
1932 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
1933 * @hw: pointer to the hw struct
1934 * @seid: seid of the VSI or switching component connected to Physical Port
1935 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
1936 * @cmd_details: pointer to command details structure or NULL
1937 **/
1938i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
1939 u16 seid,
1940 struct i40e_aqc_query_port_ets_config_resp *bw_data,
1941 struct i40e_asq_cmd_details *cmd_details)
1942{
1943 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1944 i40e_aqc_opc_query_port_ets_config,
1945 cmd_details);
1946}
1947
1948/**
1949 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
1950 * @hw: pointer to the hw struct
1951 * @seid: seid of the switching component
1952 * @bw_data: Buffer to hold switching component's BW configuration
1953 * @cmd_details: pointer to command details structure or NULL
1954 **/
1955i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
1956 u16 seid,
1957 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
1958 struct i40e_asq_cmd_details *cmd_details)
1959{
1960 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1961 i40e_aqc_opc_query_switching_comp_bw_config,
1962 cmd_details);
1963}
1964
1965/**
1966 * i40e_validate_filter_settings
1967 * @hw: pointer to the hardware structure
1968 * @settings: Filter control settings
1969 *
1970 * Check and validate the filter control settings passed.
1971 * The function checks for the valid filter/context sizes being
1972 * passed for FCoE and PE.
1973 *
1974 * Returns 0 if the values passed are valid and within
1975 * range else returns an error.
1976 **/
1977static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
1978 struct i40e_filter_control_settings *settings)
1979{
1980 u32 fcoe_cntx_size, fcoe_filt_size;
1981 u32 pe_cntx_size, pe_filt_size;
1982 u32 fcoe_fmax, pe_fmax;
1983 u32 val;
1984
1985 /* Validate FCoE settings passed */
1986 switch (settings->fcoe_filt_num) {
1987 case I40E_HASH_FILTER_SIZE_1K:
1988 case I40E_HASH_FILTER_SIZE_2K:
1989 case I40E_HASH_FILTER_SIZE_4K:
1990 case I40E_HASH_FILTER_SIZE_8K:
1991 case I40E_HASH_FILTER_SIZE_16K:
1992 case I40E_HASH_FILTER_SIZE_32K:
1993 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
1994 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
1995 break;
1996 default:
1997 return I40E_ERR_PARAM;
1998 }
1999
2000 switch (settings->fcoe_cntx_num) {
2001 case I40E_DMA_CNTX_SIZE_512:
2002 case I40E_DMA_CNTX_SIZE_1K:
2003 case I40E_DMA_CNTX_SIZE_2K:
2004 case I40E_DMA_CNTX_SIZE_4K:
2005 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2006 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
2007 break;
2008 default:
2009 return I40E_ERR_PARAM;
2010 }
2011
2012 /* Validate PE settings passed */
2013 switch (settings->pe_filt_num) {
2014 case I40E_HASH_FILTER_SIZE_1K:
2015 case I40E_HASH_FILTER_SIZE_2K:
2016 case I40E_HASH_FILTER_SIZE_4K:
2017 case I40E_HASH_FILTER_SIZE_8K:
2018 case I40E_HASH_FILTER_SIZE_16K:
2019 case I40E_HASH_FILTER_SIZE_32K:
2020 case I40E_HASH_FILTER_SIZE_64K:
2021 case I40E_HASH_FILTER_SIZE_128K:
2022 case I40E_HASH_FILTER_SIZE_256K:
2023 case I40E_HASH_FILTER_SIZE_512K:
2024 case I40E_HASH_FILTER_SIZE_1M:
2025 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2026 pe_filt_size <<= (u32)settings->pe_filt_num;
2027 break;
2028 default:
2029 return I40E_ERR_PARAM;
2030 }
2031
2032 switch (settings->pe_cntx_num) {
2033 case I40E_DMA_CNTX_SIZE_512:
2034 case I40E_DMA_CNTX_SIZE_1K:
2035 case I40E_DMA_CNTX_SIZE_2K:
2036 case I40E_DMA_CNTX_SIZE_4K:
2037 case I40E_DMA_CNTX_SIZE_8K:
2038 case I40E_DMA_CNTX_SIZE_16K:
2039 case I40E_DMA_CNTX_SIZE_32K:
2040 case I40E_DMA_CNTX_SIZE_64K:
2041 case I40E_DMA_CNTX_SIZE_128K:
2042 case I40E_DMA_CNTX_SIZE_256K:
2043 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2044 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2045 break;
2046 default:
2047 return I40E_ERR_PARAM;
2048 }
2049
2050 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2051 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2052 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2053 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2054 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2055 return I40E_ERR_INVALID_SIZE;
2056
2057 /* PEHSIZE + PEDSIZE should not be greater than PMPEXFMAX */
2058 val = rd32(hw, I40E_GLHMC_PEXFMAX);
2059 pe_fmax = (val & I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK)
2060 >> I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT;
2061 if (pe_filt_size + pe_cntx_size > pe_fmax)
2062 return I40E_ERR_INVALID_SIZE;
2063
2064 return 0;
2065}
2066
2067/**
2068 * i40e_set_filter_control
2069 * @hw: pointer to the hardware structure
2070 * @settings: Filter control settings
2071 *
2072 * Set the Queue Filters for PE/FCoE and enable filters required
2073 * for a single PF. It is expected that these settings are programmed
2074 * at the driver initialization time.
2075 **/
2076i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2077 struct i40e_filter_control_settings *settings)
2078{
2079 i40e_status ret = 0;
2080 u32 hash_lut_size = 0;
2081 u32 val;
2082
2083 if (!settings)
2084 return I40E_ERR_PARAM;
2085
2086 /* Validate the input settings */
2087 ret = i40e_validate_filter_settings(hw, settings);
2088 if (ret)
2089 return ret;
2090
2091 /* Read the PF Queue Filter control register */
2092 val = rd32(hw, I40E_PFQF_CTL_0);
2093
2094 /* Program required PE hash buckets for the PF */
2095 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2096 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2097 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2098 /* Program required PE contexts for the PF */
2099 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2100 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2101 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2102
2103 /* Program required FCoE hash buckets for the PF */
2104 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2105 val |= ((u32)settings->fcoe_filt_num <<
2106 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2107 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2108 /* Program required FCoE DDP contexts for the PF */
2109 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2110 val |= ((u32)settings->fcoe_cntx_num <<
2111 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2112 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2113
2114 /* Program Hash LUT size for the PF */
2115 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2116 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2117 hash_lut_size = 1;
2118 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2119 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2120
2121 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2122 if (settings->enable_fdir)
2123 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2124 if (settings->enable_ethtype)
2125 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2126 if (settings->enable_macvlan)
2127 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2128
2129 wr32(hw, I40E_PFQF_CTL_0, val);
2130
2131 return 0;
2132}
d4dfb81a
CS		 2133/**
2134 * i40e_set_pci_config_data - store PCI bus info
2135 * @hw: pointer to hardware structure
2136 * @link_status: the link status word from PCI config space
2137 *
2138 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
2139 **/
2140void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
2141{
2142 hw->bus.type = i40e_bus_type_pci_express;
2143
2144 switch (link_status & PCI_EXP_LNKSTA_NLW) {
2145 case PCI_EXP_LNKSTA_NLW_X1:
2146 hw->bus.width = i40e_bus_width_pcie_x1;
2147 break;
2148 case PCI_EXP_LNKSTA_NLW_X2:
2149 hw->bus.width = i40e_bus_width_pcie_x2;
2150 break;
2151 case PCI_EXP_LNKSTA_NLW_X4:
2152 hw->bus.width = i40e_bus_width_pcie_x4;
2153 break;
2154 case PCI_EXP_LNKSTA_NLW_X8:
2155 hw->bus.width = i40e_bus_width_pcie_x8;
2156 break;
2157 default:
2158 hw->bus.width = i40e_bus_width_unknown;
2159 break;
2160 }
2161
2162 switch (link_status & PCI_EXP_LNKSTA_CLS) {
2163 case PCI_EXP_LNKSTA_CLS_2_5GB:
2164 hw->bus.speed = i40e_bus_speed_2500;
2165 break;
2166 case PCI_EXP_LNKSTA_CLS_5_0GB:
2167 hw->bus.speed = i40e_bus_speed_5000;
2168 break;
2169 case PCI_EXP_LNKSTA_CLS_8_0GB:
2170 hw->bus.speed = i40e_bus_speed_8000;
2171 break;
2172 default:
2173 hw->bus.speed = i40e_bus_speed_unknown;
2174 break;
2175 }
2176}
Linux 6.x block layer and io_uring tree(s)