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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec...
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e_common.c
CommitLineData
56a62fc8
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
56a62fc8
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
56a62fc8
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32/**
33 * i40e_set_mac_type - Sets MAC type
34 * @hw: pointer to the HW structure
35 *
36 * This function sets the mac type of the adapter based on the
37 * vendor ID and device ID stored in the hw structure.
38 **/
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
ab60085e
SN		 45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_SFP_X710:
47 case I40E_DEV_ID_QEMU:
48 case I40E_DEV_ID_KX_A:
49 case I40E_DEV_ID_KX_B:
50 case I40E_DEV_ID_KX_C:
51 case I40E_DEV_ID_KX_D:
52 case I40E_DEV_ID_QSFP_A:
53 case I40E_DEV_ID_QSFP_B:
54 case I40E_DEV_ID_QSFP_C:
56a62fc8
JB		 55 hw->mac.type = I40E_MAC_XL710;
56 break;
ab60085e
SN		 57 case I40E_DEV_ID_VF:
58 case I40E_DEV_ID_VF_HV:
56a62fc8
JB		 59 hw->mac.type = I40E_MAC_VF;
60 break;
61 default:
62 hw->mac.type = I40E_MAC_GENERIC;
63 break;
64 }
65 } else {
66 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
67 }
68
69 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
70 hw->mac.type, status);
71 return status;
72}
73
74/**
75 * i40e_debug_aq
76 * @hw: debug mask related to admin queue
98d44381
JK		 77 * @mask: debug mask
78 * @desc: pointer to admin queue descriptor
56a62fc8
JB		 79 * @buffer: pointer to command buffer
80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
84 void *buffer)
85{
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
87 u8 *aq_buffer = (u8 *)buffer;
88 u32 data[4];
89 u32 i = 0;
90
91 if ((!(mask & hw->debug_mask)) || (desc == NULL))
92 return;
93
94 i40e_debug(hw, mask,
95 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
96 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
97 aq_desc->retval);
98 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
99 aq_desc->cookie_high, aq_desc->cookie_low);
100 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
101 aq_desc->params.internal.param0,
102 aq_desc->params.internal.param1);
103 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
104 aq_desc->params.external.addr_high,
105 aq_desc->params.external.addr_low);
106
107 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
108 memset(data, 0, sizeof(data));
109 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
110 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
111 data[((i % 16) / 4)] |=
112 ((u32)aq_buffer[i]) << (8 * (i % 4));
113 if ((i % 16) == 15) {
114 i40e_debug(hw, mask,
115 "\t0x%04X %08X %08X %08X %08X\n",
116 i - 15, data[0], data[1], data[2],
117 data[3]);
118 memset(data, 0, sizeof(data));
119 }
120 }
121 if ((i % 16) != 0)
122 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
123 i - (i % 16), data[0], data[1], data[2],
124 data[3]);
125 }
126}
127
e1860d8f
ASJ		 128/**
129 * i40e_check_asq_alive
130 * @hw: pointer to the hw struct
131 *
132 * Returns true if Queue is enabled else false.
133 **/
134bool i40e_check_asq_alive(struct i40e_hw *hw)
135{
136 return !!(rd32(hw, hw->aq.asq.len) & I40E_PF_ATQLEN_ATQENABLE_MASK);
137}
138
139/**
140 * i40e_aq_queue_shutdown
141 * @hw: pointer to the hw struct
142 * @unloading: is the driver unloading itself
143 *
144 * Tell the Firmware that we're shutting down the AdminQ and whether
145 * or not the driver is unloading as well.
146 **/
147i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
148 bool unloading)
149{
150 struct i40e_aq_desc desc;
151 struct i40e_aqc_queue_shutdown *cmd =
152 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
153 i40e_status status;
154
155 i40e_fill_default_direct_cmd_desc(&desc,
156 i40e_aqc_opc_queue_shutdown);
157
158 if (unloading)
159 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
160 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
161
162 return status;
163}
164
206812b5
JB		 165/* The i40e_ptype_lookup table is used to convert from the 8-bit ptype in the
166 * hardware to a bit-field that can be used by SW to more easily determine the
167 * packet type.
168 *
169 * Macros are used to shorten the table lines and make this table human
170 * readable.
171 *
172 * We store the PTYPE in the top byte of the bit field - this is just so that
173 * we can check that the table doesn't have a row missing, as the index into
174 * the table should be the PTYPE.
175 *
176 * Typical work flow:
177 *
178 * IF NOT i40e_ptype_lookup[ptype].known
179 * THEN
180 * Packet is unknown
181 * ELSE IF i40e_ptype_lookup[ptype].outer_ip == I40E_RX_PTYPE_OUTER_IP
182 * Use the rest of the fields to look at the tunnels, inner protocols, etc
183 * ELSE
184 * Use the enum i40e_rx_l2_ptype to decode the packet type
185 * ENDIF
186 */
187
188/* macro to make the table lines short */
189#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
190 { PTYPE, \
191 1, \
192 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
193 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
194 I40E_RX_PTYPE_##OUTER_FRAG, \
195 I40E_RX_PTYPE_TUNNEL_##T, \
196 I40E_RX_PTYPE_TUNNEL_END_##TE, \
197 I40E_RX_PTYPE_##TEF, \
198 I40E_RX_PTYPE_INNER_PROT_##I, \
199 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
200
201#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
202 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
203
204/* shorter macros makes the table fit but are terse */
205#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
206#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
207#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
208
209/* Lookup table mapping the HW PTYPE to the bit field for decoding */
210struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
211 /* L2 Packet types */
212 I40E_PTT_UNUSED_ENTRY(0),
213 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
214 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
215 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
216 I40E_PTT_UNUSED_ENTRY(4),
217 I40E_PTT_UNUSED_ENTRY(5),
218 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
219 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
220 I40E_PTT_UNUSED_ENTRY(8),
221 I40E_PTT_UNUSED_ENTRY(9),
222 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
223 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
224 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
225 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
226 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
227 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
228 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
229 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
230 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
231 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
232 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
233 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
234
235 /* Non Tunneled IPv4 */
236 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
237 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
238 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
239 I40E_PTT_UNUSED_ENTRY(25),
240 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
241 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
242 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
243
244 /* IPv4 --> IPv4 */
245 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
246 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
247 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
248 I40E_PTT_UNUSED_ENTRY(32),
249 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
250 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
251 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
252
253 /* IPv4 --> IPv6 */
254 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
255 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
256 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
257 I40E_PTT_UNUSED_ENTRY(39),
258 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
259 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
260 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
261
262 /* IPv4 --> GRE/NAT */
263 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
264
265 /* IPv4 --> GRE/NAT --> IPv4 */
266 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
267 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
268 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
269 I40E_PTT_UNUSED_ENTRY(47),
270 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
271 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
272 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
273
274 /* IPv4 --> GRE/NAT --> IPv6 */
275 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
276 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
277 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
278 I40E_PTT_UNUSED_ENTRY(54),
279 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
280 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
281 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
282
283 /* IPv4 --> GRE/NAT --> MAC */
284 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
285
286 /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
287 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
288 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
289 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
290 I40E_PTT_UNUSED_ENTRY(62),
291 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
292 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
293 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
294
295 /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
296 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
297 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
298 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
299 I40E_PTT_UNUSED_ENTRY(69),
300 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
301 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
302 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
303
304 /* IPv4 --> GRE/NAT --> MAC/VLAN */
305 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
306
307 /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
308 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
309 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
310 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
311 I40E_PTT_UNUSED_ENTRY(77),
312 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
313 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
314 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
315
316 /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
317 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
318 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
319 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
320 I40E_PTT_UNUSED_ENTRY(84),
321 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
322 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
323 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
324
325 /* Non Tunneled IPv6 */
326 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
327 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
328 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
329 I40E_PTT_UNUSED_ENTRY(91),
330 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
331 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
332 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
333
334 /* IPv6 --> IPv4 */
335 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
336 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
337 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
338 I40E_PTT_UNUSED_ENTRY(98),
339 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
340 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
341 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
342
343 /* IPv6 --> IPv6 */
344 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
345 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
346 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
347 I40E_PTT_UNUSED_ENTRY(105),
348 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
349 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
350 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
351
352 /* IPv6 --> GRE/NAT */
353 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
354
355 /* IPv6 --> GRE/NAT -> IPv4 */
356 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
357 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
358 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
359 I40E_PTT_UNUSED_ENTRY(113),
360 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
361 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
362 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
363
364 /* IPv6 --> GRE/NAT -> IPv6 */
365 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
366 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
367 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
368 I40E_PTT_UNUSED_ENTRY(120),
369 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
370 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
371 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
372
373 /* IPv6 --> GRE/NAT -> MAC */
374 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
375
376 /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
377 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
378 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
379 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
380 I40E_PTT_UNUSED_ENTRY(128),
381 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
382 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
383 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
384
385 /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
386 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
387 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
388 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
389 I40E_PTT_UNUSED_ENTRY(135),
390 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
391 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
392 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
393
394 /* IPv6 --> GRE/NAT -> MAC/VLAN */
395 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
396
397 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
398 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
399 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
400 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
401 I40E_PTT_UNUSED_ENTRY(143),
402 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
403 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
404 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
405
406 /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
407 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
408 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
409 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
410 I40E_PTT_UNUSED_ENTRY(150),
411 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
412 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
413 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
414
415 /* unused entries */
416 I40E_PTT_UNUSED_ENTRY(154),
417 I40E_PTT_UNUSED_ENTRY(155),
418 I40E_PTT_UNUSED_ENTRY(156),
419 I40E_PTT_UNUSED_ENTRY(157),
420 I40E_PTT_UNUSED_ENTRY(158),
421 I40E_PTT_UNUSED_ENTRY(159),
422
423 I40E_PTT_UNUSED_ENTRY(160),
424 I40E_PTT_UNUSED_ENTRY(161),
425 I40E_PTT_UNUSED_ENTRY(162),
426 I40E_PTT_UNUSED_ENTRY(163),
427 I40E_PTT_UNUSED_ENTRY(164),
428 I40E_PTT_UNUSED_ENTRY(165),
429 I40E_PTT_UNUSED_ENTRY(166),
430 I40E_PTT_UNUSED_ENTRY(167),
431 I40E_PTT_UNUSED_ENTRY(168),
432 I40E_PTT_UNUSED_ENTRY(169),
433
434 I40E_PTT_UNUSED_ENTRY(170),
435 I40E_PTT_UNUSED_ENTRY(171),
436 I40E_PTT_UNUSED_ENTRY(172),
437 I40E_PTT_UNUSED_ENTRY(173),
438 I40E_PTT_UNUSED_ENTRY(174),
439 I40E_PTT_UNUSED_ENTRY(175),
440 I40E_PTT_UNUSED_ENTRY(176),
441 I40E_PTT_UNUSED_ENTRY(177),
442 I40E_PTT_UNUSED_ENTRY(178),
443 I40E_PTT_UNUSED_ENTRY(179),
444
445 I40E_PTT_UNUSED_ENTRY(180),
446 I40E_PTT_UNUSED_ENTRY(181),
447 I40E_PTT_UNUSED_ENTRY(182),
448 I40E_PTT_UNUSED_ENTRY(183),
449 I40E_PTT_UNUSED_ENTRY(184),
450 I40E_PTT_UNUSED_ENTRY(185),
451 I40E_PTT_UNUSED_ENTRY(186),
452 I40E_PTT_UNUSED_ENTRY(187),
453 I40E_PTT_UNUSED_ENTRY(188),
454 I40E_PTT_UNUSED_ENTRY(189),
455
456 I40E_PTT_UNUSED_ENTRY(190),
457 I40E_PTT_UNUSED_ENTRY(191),
458 I40E_PTT_UNUSED_ENTRY(192),
459 I40E_PTT_UNUSED_ENTRY(193),
460 I40E_PTT_UNUSED_ENTRY(194),
461 I40E_PTT_UNUSED_ENTRY(195),
462 I40E_PTT_UNUSED_ENTRY(196),
463 I40E_PTT_UNUSED_ENTRY(197),
464 I40E_PTT_UNUSED_ENTRY(198),
465 I40E_PTT_UNUSED_ENTRY(199),
466
467 I40E_PTT_UNUSED_ENTRY(200),
468 I40E_PTT_UNUSED_ENTRY(201),
469 I40E_PTT_UNUSED_ENTRY(202),
470 I40E_PTT_UNUSED_ENTRY(203),
471 I40E_PTT_UNUSED_ENTRY(204),
472 I40E_PTT_UNUSED_ENTRY(205),
473 I40E_PTT_UNUSED_ENTRY(206),
474 I40E_PTT_UNUSED_ENTRY(207),
475 I40E_PTT_UNUSED_ENTRY(208),
476 I40E_PTT_UNUSED_ENTRY(209),
477
478 I40E_PTT_UNUSED_ENTRY(210),
479 I40E_PTT_UNUSED_ENTRY(211),
480 I40E_PTT_UNUSED_ENTRY(212),
481 I40E_PTT_UNUSED_ENTRY(213),
482 I40E_PTT_UNUSED_ENTRY(214),
483 I40E_PTT_UNUSED_ENTRY(215),
484 I40E_PTT_UNUSED_ENTRY(216),
485 I40E_PTT_UNUSED_ENTRY(217),
486 I40E_PTT_UNUSED_ENTRY(218),
487 I40E_PTT_UNUSED_ENTRY(219),
488
489 I40E_PTT_UNUSED_ENTRY(220),
490 I40E_PTT_UNUSED_ENTRY(221),
491 I40E_PTT_UNUSED_ENTRY(222),
492 I40E_PTT_UNUSED_ENTRY(223),
493 I40E_PTT_UNUSED_ENTRY(224),
494 I40E_PTT_UNUSED_ENTRY(225),
495 I40E_PTT_UNUSED_ENTRY(226),
496 I40E_PTT_UNUSED_ENTRY(227),
497 I40E_PTT_UNUSED_ENTRY(228),
498 I40E_PTT_UNUSED_ENTRY(229),
499
500 I40E_PTT_UNUSED_ENTRY(230),
501 I40E_PTT_UNUSED_ENTRY(231),
502 I40E_PTT_UNUSED_ENTRY(232),
503 I40E_PTT_UNUSED_ENTRY(233),
504 I40E_PTT_UNUSED_ENTRY(234),
505 I40E_PTT_UNUSED_ENTRY(235),
506 I40E_PTT_UNUSED_ENTRY(236),
507 I40E_PTT_UNUSED_ENTRY(237),
508 I40E_PTT_UNUSED_ENTRY(238),
509 I40E_PTT_UNUSED_ENTRY(239),
510
511 I40E_PTT_UNUSED_ENTRY(240),
512 I40E_PTT_UNUSED_ENTRY(241),
513 I40E_PTT_UNUSED_ENTRY(242),
514 I40E_PTT_UNUSED_ENTRY(243),
515 I40E_PTT_UNUSED_ENTRY(244),
516 I40E_PTT_UNUSED_ENTRY(245),
517 I40E_PTT_UNUSED_ENTRY(246),
518 I40E_PTT_UNUSED_ENTRY(247),
519 I40E_PTT_UNUSED_ENTRY(248),
520 I40E_PTT_UNUSED_ENTRY(249),
521
522 I40E_PTT_UNUSED_ENTRY(250),
523 I40E_PTT_UNUSED_ENTRY(251),
524 I40E_PTT_UNUSED_ENTRY(252),
525 I40E_PTT_UNUSED_ENTRY(253),
526 I40E_PTT_UNUSED_ENTRY(254),
527 I40E_PTT_UNUSED_ENTRY(255)
528};
529
530
56a62fc8
JB		 531/**
532 * i40e_init_shared_code - Initialize the shared code
533 * @hw: pointer to hardware structure
534 *
535 * This assigns the MAC type and PHY code and inits the NVM.
536 * Does not touch the hardware. This function must be called prior to any
537 * other function in the shared code. The i40e_hw structure should be
538 * memset to 0 prior to calling this function. The following fields in
539 * hw structure should be filled in prior to calling this function:
540 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
541 * subsystem_vendor_id, and revision_id
542 **/
543i40e_status i40e_init_shared_code(struct i40e_hw *hw)
544{
545 i40e_status status = 0;
546 u32 reg;
547
56a62fc8
JB		 548 i40e_set_mac_type(hw);
549
550 switch (hw->mac.type) {
551 case I40E_MAC_XL710:
552 break;
553 default:
554 return I40E_ERR_DEVICE_NOT_SUPPORTED;
555 break;
556 }
557
af89d26c
SN		 558 hw->phy.get_link_info = true;
559
560 /* Determine port number */
561 reg = rd32(hw, I40E_PFGEN_PORTNUM);
562 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
563 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
564 hw->port = (u8)reg;
565
5f9116ac
SN		 566 /* Determine the PF number based on the PCI fn */
567 reg = rd32(hw, I40E_GLPCI_CAPSUP);
568 if (reg & I40E_GLPCI_CAPSUP_ARI_EN_MASK)
569 hw->pf_id = (u8)((hw->bus.device << 3) | hw->bus.func);
570 else
571 hw->pf_id = (u8)hw->bus.func;
572
56a62fc8
JB		 573 status = i40e_init_nvm(hw);
574 return status;
575}
576
577/**
578 * i40e_aq_mac_address_read - Retrieve the MAC addresses
579 * @hw: pointer to the hw struct
580 * @flags: a return indicator of what addresses were added to the addr store
581 * @addrs: the requestor's mac addr store
582 * @cmd_details: pointer to command details structure or NULL
583 **/
584static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
585 u16 *flags,
586 struct i40e_aqc_mac_address_read_data *addrs,
587 struct i40e_asq_cmd_details *cmd_details)
588{
589 struct i40e_aq_desc desc;
590 struct i40e_aqc_mac_address_read *cmd_data =
591 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
592 i40e_status status;
593
594 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
595 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
596
597 status = i40e_asq_send_command(hw, &desc, addrs,
598 sizeof(*addrs), cmd_details);
599 *flags = le16_to_cpu(cmd_data->command_flags);
600
601 return status;
602}
603
604/**
605 * i40e_aq_mac_address_write - Change the MAC addresses
606 * @hw: pointer to the hw struct
607 * @flags: indicates which MAC to be written
608 * @mac_addr: address to write
609 * @cmd_details: pointer to command details structure or NULL
610 **/
611i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
612 u16 flags, u8 *mac_addr,
613 struct i40e_asq_cmd_details *cmd_details)
614{
615 struct i40e_aq_desc desc;
616 struct i40e_aqc_mac_address_write *cmd_data =
617 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
618 i40e_status status;
619
620 i40e_fill_default_direct_cmd_desc(&desc,
621 i40e_aqc_opc_mac_address_write);
622 cmd_data->command_flags = cpu_to_le16(flags);
55c29c31
KK		 623 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
624 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
625 ((u32)mac_addr[3] << 16) |
626 ((u32)mac_addr[4] << 8) |
627 mac_addr[5]);
56a62fc8
JB		 628
629 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
630
631 return status;
632}
633
634/**
635 * i40e_get_mac_addr - get MAC address
636 * @hw: pointer to the HW structure
637 * @mac_addr: pointer to MAC address
638 *
639 * Reads the adapter's MAC address from register
640 **/
641i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
642{
643 struct i40e_aqc_mac_address_read_data addrs;
644 i40e_status status;
645 u16 flags = 0;
646
647 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
648
649 if (flags & I40E_AQC_LAN_ADDR_VALID)
650 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
651
652 return status;
653}
654
be405eb0
JB		 655/**
656 * i40e_get_media_type - Gets media type
657 * @hw: pointer to the hardware structure
658 **/
659static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
660{
661 enum i40e_media_type media;
662
663 switch (hw->phy.link_info.phy_type) {
664 case I40E_PHY_TYPE_10GBASE_SR:
665 case I40E_PHY_TYPE_10GBASE_LR:
666 case I40E_PHY_TYPE_40GBASE_SR4:
667 case I40E_PHY_TYPE_40GBASE_LR4:
668 media = I40E_MEDIA_TYPE_FIBER;
669 break;
670 case I40E_PHY_TYPE_100BASE_TX:
671 case I40E_PHY_TYPE_1000BASE_T:
672 case I40E_PHY_TYPE_10GBASE_T:
673 media = I40E_MEDIA_TYPE_BASET;
674 break;
675 case I40E_PHY_TYPE_10GBASE_CR1_CU:
676 case I40E_PHY_TYPE_40GBASE_CR4_CU:
677 case I40E_PHY_TYPE_10GBASE_CR1:
678 case I40E_PHY_TYPE_40GBASE_CR4:
679 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
680 media = I40E_MEDIA_TYPE_DA;
681 break;
682 case I40E_PHY_TYPE_1000BASE_KX:
683 case I40E_PHY_TYPE_10GBASE_KX4:
684 case I40E_PHY_TYPE_10GBASE_KR:
685 case I40E_PHY_TYPE_40GBASE_KR4:
686 media = I40E_MEDIA_TYPE_BACKPLANE;
687 break;
688 case I40E_PHY_TYPE_SGMII:
689 case I40E_PHY_TYPE_XAUI:
690 case I40E_PHY_TYPE_XFI:
691 case I40E_PHY_TYPE_XLAUI:
692 case I40E_PHY_TYPE_XLPPI:
693 default:
694 media = I40E_MEDIA_TYPE_UNKNOWN;
695 break;
696 }
697
698 return media;
699}
700
7134f9ce
JB		 701#define I40E_PF_RESET_WAIT_COUNT_A0 200
702#define I40E_PF_RESET_WAIT_COUNT 10
56a62fc8
JB		 703/**
704 * i40e_pf_reset - Reset the PF
705 * @hw: pointer to the hardware structure
706 *
707 * Assuming someone else has triggered a global reset,
708 * assure the global reset is complete and then reset the PF
709 **/
710i40e_status i40e_pf_reset(struct i40e_hw *hw)
711{
7134f9ce 712 u32 cnt = 0;
42794bd8 713 u32 cnt1 = 0;
56a62fc8
JB		 714 u32 reg = 0;
715 u32 grst_del;
716
717 /* Poll for Global Reset steady state in case of recent GRST.
718 * The grst delay value is in 100ms units, and we'll wait a
719 * couple counts longer to be sure we don't just miss the end.
720 */
721 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
722 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
7134f9ce 723 for (cnt = 0; cnt < grst_del + 2; cnt++) {
56a62fc8
JB		 724 reg = rd32(hw, I40E_GLGEN_RSTAT);
725 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
726 break;
727 msleep(100);
728 }
729 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
730 hw_dbg(hw, "Global reset polling failed to complete.\n");
42794bd8
SN		 731 return I40E_ERR_RESET_FAILED;
732 }
733
734 /* Now Wait for the FW to be ready */
735 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
736 reg = rd32(hw, I40E_GLNVM_ULD);
737 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
738 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
739 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
740 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
741 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
742 break;
743 }
744 usleep_range(10000, 20000);
745 }
746 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
747 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
748 hw_dbg(hw, "wait for FW Reset complete timedout\n");
749 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
56a62fc8
JB		 750 return I40E_ERR_RESET_FAILED;
751 }
752
56a62fc8
JB		 753 /* If there was a Global Reset in progress when we got here,
754 * we don't need to do the PF Reset
755 */
7134f9ce
JB		 756 if (!cnt) {
757 if (hw->revision_id == 0)
758 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
759 else
760 cnt = I40E_PF_RESET_WAIT_COUNT;
56a62fc8
JB		 761 reg = rd32(hw, I40E_PFGEN_CTRL);
762 wr32(hw, I40E_PFGEN_CTRL,
763 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
7134f9ce 764 for (; cnt; cnt--) {
56a62fc8
JB		 765 reg = rd32(hw, I40E_PFGEN_CTRL);
766 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
767 break;
768 usleep_range(1000, 2000);
769 }
770 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
771 hw_dbg(hw, "PF reset polling failed to complete.\n");
772 return I40E_ERR_RESET_FAILED;
773 }
774 }
775
776 i40e_clear_pxe_mode(hw);
922680b9 777
56a62fc8
JB		 778 return 0;
779}
780
781/**
782 * i40e_clear_pxe_mode - clear pxe operations mode
783 * @hw: pointer to the hw struct
784 *
785 * Make sure all PXE mode settings are cleared, including things
786 * like descriptor fetch/write-back mode.
787 **/
788void i40e_clear_pxe_mode(struct i40e_hw *hw)
789{
790 u32 reg;
791
792 /* Clear single descriptor fetch/write-back mode */
793 reg = rd32(hw, I40E_GLLAN_RCTL_0);
7134f9ce
JB		 794
795 if (hw->revision_id == 0) {
796 /* As a work around clear PXE_MODE instead of setting it */
797 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
798 } else {
799 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
800 }
56a62fc8
JB		 801}
802
0556a9e3
JB		 803/**
804 * i40e_led_is_mine - helper to find matching led
805 * @hw: pointer to the hw struct
806 * @idx: index into GPIO registers
807 *
808 * returns: 0 if no match, otherwise the value of the GPIO_CTL register
809 */
810static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
811{
812 u32 gpio_val = 0;
813 u32 port;
814
815 if (!hw->func_caps.led[idx])
816 return 0;
817
818 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
819 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
820 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
821
822 /* if PRT_NUM_NA is 1 then this LED is not port specific, OR
823 * if it is not our port then ignore
824 */
825 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
826 (port != hw->port))
827 return 0;
828
829 return gpio_val;
830}
831
832#define I40E_LED0 22
833#define I40E_LINK_ACTIVITY 0xC
834
56a62fc8
JB		 835/**
836 * i40e_led_get - return current on/off mode
837 * @hw: pointer to the hw struct
838 *
839 * The value returned is the 'mode' field as defined in the
840 * GPIO register definitions: 0x0 = off, 0xf = on, and other
841 * values are variations of possible behaviors relating to
842 * blink, link, and wire.
843 **/
844u32 i40e_led_get(struct i40e_hw *hw)
845{
56a62fc8 846 u32 mode = 0;
56a62fc8
JB		 847 int i;
848
0556a9e3
JB		 849 /* as per the documentation GPIO 22-29 are the LED
850 * GPIO pins named LED0..LED7
851 */
852 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
853 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 854
0556a9e3 855 if (!gpio_val)
56a62fc8
JB		 856 continue;
857
0556a9e3
JB		 858 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
859 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
56a62fc8
JB		 860 break;
861 }
862
863 return mode;
864}
865
866/**
867 * i40e_led_set - set new on/off mode
868 * @hw: pointer to the hw struct
0556a9e3
JB		 869 * @mode: 0=off, 0xf=on (else see manual for mode details)
870 * @blink: true if the LED should blink when on, false if steady
871 *
872 * if this function is used to turn on the blink it should
873 * be used to disable the blink when restoring the original state.
56a62fc8 874 **/
0556a9e3 875void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
56a62fc8 876{
56a62fc8
JB		 877 int i;
878
0556a9e3
JB		 879 if (mode & 0xfffffff0)
880 hw_dbg(hw, "invalid mode passed in %X\n", mode);
56a62fc8 881
0556a9e3
JB		 882 /* as per the documentation GPIO 22-29 are the LED
883 * GPIO pins named LED0..LED7
884 */
885 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
886 u32 gpio_val = i40e_led_is_mine(hw, i);
56a62fc8 887
0556a9e3 888 if (!gpio_val)
56a62fc8
JB		 889 continue;
890
56a62fc8 891 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
0556a9e3
JB		 892 /* this & is a bit of paranoia, but serves as a range check */
893 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
894 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
895
896 if (mode == I40E_LINK_ACTIVITY)
897 blink = false;
898
899 gpio_val |= (blink ? 1 : 0) <<
900 I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT;
901
56a62fc8 902 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
0556a9e3 903 break;
56a62fc8
JB		 904 }
905}
906
907/* Admin command wrappers */
56a62fc8
JB		 908
909/**
910 * i40e_aq_set_link_restart_an
911 * @hw: pointer to the hw struct
912 * @cmd_details: pointer to command details structure or NULL
913 *
914 * Sets up the link and restarts the Auto-Negotiation over the link.
915 **/
916i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
917 struct i40e_asq_cmd_details *cmd_details)
918{
919 struct i40e_aq_desc desc;
920 struct i40e_aqc_set_link_restart_an *cmd =
921 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
922 i40e_status status;
923
924 i40e_fill_default_direct_cmd_desc(&desc,
925 i40e_aqc_opc_set_link_restart_an);
926
927 cmd->command = I40E_AQ_PHY_RESTART_AN;
928
929 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
930
931 return status;
932}
933
934/**
935 * i40e_aq_get_link_info
936 * @hw: pointer to the hw struct
937 * @enable_lse: enable/disable LinkStatusEvent reporting
938 * @link: pointer to link status structure - optional
939 * @cmd_details: pointer to command details structure or NULL
940 *
941 * Returns the link status of the adapter.
942 **/
943i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
944 bool enable_lse, struct i40e_link_status *link,
945 struct i40e_asq_cmd_details *cmd_details)
946{
947 struct i40e_aq_desc desc;
948 struct i40e_aqc_get_link_status *resp =
949 (struct i40e_aqc_get_link_status *)&desc.params.raw;
950 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
951 i40e_status status;
952 u16 command_flags;
953
954 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
955
956 if (enable_lse)
957 command_flags = I40E_AQ_LSE_ENABLE;
958 else
959 command_flags = I40E_AQ_LSE_DISABLE;
960 resp->command_flags = cpu_to_le16(command_flags);
961
962 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
963
964 if (status)
965 goto aq_get_link_info_exit;
966
967 /* save off old link status information */
c36bd4a7 968 hw->phy.link_info_old = *hw_link_info;
56a62fc8
JB		 969
970 /* update link status */
971 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
be405eb0 972 hw->phy.media_type = i40e_get_media_type(hw);
56a62fc8
JB		 973 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
974 hw_link_info->link_info = resp->link_info;
975 hw_link_info->an_info = resp->an_info;
976 hw_link_info->ext_info = resp->ext_info;
639dc377 977 hw_link_info->loopback = resp->loopback;
56a62fc8
JB		 978
979 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
980 hw_link_info->lse_enable = true;
981 else
982 hw_link_info->lse_enable = false;
983
984 /* save link status information */
985 if (link)
d7595a22 986 *link = *hw_link_info;
56a62fc8
JB		 987
988 /* flag cleared so helper functions don't call AQ again */
989 hw->phy.get_link_info = false;
990
991aq_get_link_info_exit:
992 return status;
993}
994
995/**
996 * i40e_aq_add_vsi
997 * @hw: pointer to the hw struct
98d44381 998 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 999 * @cmd_details: pointer to command details structure or NULL
1000 *
1001 * Add a VSI context to the hardware.
1002**/
1003i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1004 struct i40e_vsi_context *vsi_ctx,
1005 struct i40e_asq_cmd_details *cmd_details)
1006{
1007 struct i40e_aq_desc desc;
1008 struct i40e_aqc_add_get_update_vsi *cmd =
1009 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1010 struct i40e_aqc_add_get_update_vsi_completion *resp =
1011 (struct i40e_aqc_add_get_update_vsi_completion *)
1012 &desc.params.raw;
1013 i40e_status status;
1014
1015 i40e_fill_default_direct_cmd_desc(&desc,
1016 i40e_aqc_opc_add_vsi);
1017
1018 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1019 cmd->connection_type = vsi_ctx->connection_type;
1020 cmd->vf_id = vsi_ctx->vf_num;
1021 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1022
1023 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1024 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
1025 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1026
1027 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1028 sizeof(vsi_ctx->info), cmd_details);
1029
1030 if (status)
1031 goto aq_add_vsi_exit;
1032
1033 vsi_ctx->seid = le16_to_cpu(resp->seid);
1034 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1035 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1036 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1037
1038aq_add_vsi_exit:
1039 return status;
1040}
1041
1042/**
1043 * i40e_aq_set_vsi_unicast_promiscuous
1044 * @hw: pointer to the hw struct
1045 * @seid: vsi number
1046 * @set: set unicast promiscuous enable/disable
1047 * @cmd_details: pointer to command details structure or NULL
1048 **/
1049i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
885552a2
MW		 1050 u16 seid, bool set,
1051 struct i40e_asq_cmd_details *cmd_details)
56a62fc8
JB		 1052{
1053 struct i40e_aq_desc desc;
1054 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1055 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1056 i40e_status status;
1057 u16 flags = 0;
1058
1059 i40e_fill_default_direct_cmd_desc(&desc,
1060 i40e_aqc_opc_set_vsi_promiscuous_modes);
1061
1062 if (set)
1063 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1064
1065 cmd->promiscuous_flags = cpu_to_le16(flags);
1066
1067 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1068
1069 cmd->seid = cpu_to_le16(seid);
1070 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1071
1072 return status;
1073}
1074
1075/**
1076 * i40e_aq_set_vsi_multicast_promiscuous
1077 * @hw: pointer to the hw struct
1078 * @seid: vsi number
1079 * @set: set multicast promiscuous enable/disable
1080 * @cmd_details: pointer to command details structure or NULL
1081 **/
1082i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
1083 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
1084{
1085 struct i40e_aq_desc desc;
1086 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1087 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1088 i40e_status status;
1089 u16 flags = 0;
1090
1091 i40e_fill_default_direct_cmd_desc(&desc,
1092 i40e_aqc_opc_set_vsi_promiscuous_modes);
1093
1094 if (set)
1095 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
1096
1097 cmd->promiscuous_flags = cpu_to_le16(flags);
1098
1099 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
1100
1101 cmd->seid = cpu_to_le16(seid);
1102 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1103
1104 return status;
1105}
1106
1107/**
1108 * i40e_aq_set_vsi_broadcast
1109 * @hw: pointer to the hw struct
1110 * @seid: vsi number
1111 * @set_filter: true to set filter, false to clear filter
1112 * @cmd_details: pointer to command details structure or NULL
1113 *
1114 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
1115 **/
1116i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
1117 u16 seid, bool set_filter,
1118 struct i40e_asq_cmd_details *cmd_details)
1119{
1120 struct i40e_aq_desc desc;
1121 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1122 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1123 i40e_status status;
1124
1125 i40e_fill_default_direct_cmd_desc(&desc,
1126 i40e_aqc_opc_set_vsi_promiscuous_modes);
1127
1128 if (set_filter)
1129 cmd->promiscuous_flags
1130 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1131 else
1132 cmd->promiscuous_flags
1133 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1134
1135 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
1136 cmd->seid = cpu_to_le16(seid);
1137 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1138
1139 return status;
1140}
1141
1142/**
1143 * i40e_get_vsi_params - get VSI configuration info
1144 * @hw: pointer to the hw struct
98d44381 1145 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1146 * @cmd_details: pointer to command details structure or NULL
1147 **/
1148i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
1149 struct i40e_vsi_context *vsi_ctx,
1150 struct i40e_asq_cmd_details *cmd_details)
1151{
1152 struct i40e_aq_desc desc;
f5ac8579
SN		 1153 struct i40e_aqc_add_get_update_vsi *cmd =
1154 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1155 struct i40e_aqc_add_get_update_vsi_completion *resp =
1156 (struct i40e_aqc_add_get_update_vsi_completion *)
1157 &desc.params.raw;
1158 i40e_status status;
1159
1160 i40e_fill_default_direct_cmd_desc(&desc,
1161 i40e_aqc_opc_get_vsi_parameters);
1162
f5ac8579 1163 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1164
1165 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1166 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
1167 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1168
1169 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1170 sizeof(vsi_ctx->info), NULL);
1171
1172 if (status)
1173 goto aq_get_vsi_params_exit;
1174
1175 vsi_ctx->seid = le16_to_cpu(resp->seid);
1176 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1177 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1178 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1179
1180aq_get_vsi_params_exit:
1181 return status;
1182}
1183
1184/**
1185 * i40e_aq_update_vsi_params
1186 * @hw: pointer to the hw struct
98d44381 1187 * @vsi_ctx: pointer to a vsi context struct
56a62fc8
JB		 1188 * @cmd_details: pointer to command details structure or NULL
1189 *
1190 * Update a VSI context.
1191 **/
1192i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
1193 struct i40e_vsi_context *vsi_ctx,
1194 struct i40e_asq_cmd_details *cmd_details)
1195{
1196 struct i40e_aq_desc desc;
f5ac8579
SN		 1197 struct i40e_aqc_add_get_update_vsi *cmd =
1198 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
56a62fc8
JB		 1199 i40e_status status;
1200
1201 i40e_fill_default_direct_cmd_desc(&desc,
1202 i40e_aqc_opc_update_vsi_parameters);
f5ac8579 1203 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
56a62fc8
JB		 1204
1205 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1206 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
1207 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1208
1209 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1210 sizeof(vsi_ctx->info), cmd_details);
1211
1212 return status;
1213}
1214
1215/**
1216 * i40e_aq_get_switch_config
1217 * @hw: pointer to the hardware structure
1218 * @buf: pointer to the result buffer
1219 * @buf_size: length of input buffer
1220 * @start_seid: seid to start for the report, 0 == beginning
1221 * @cmd_details: pointer to command details structure or NULL
1222 *
1223 * Fill the buf with switch configuration returned from AdminQ command
1224 **/
1225i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
1226 struct i40e_aqc_get_switch_config_resp *buf,
1227 u16 buf_size, u16 *start_seid,
1228 struct i40e_asq_cmd_details *cmd_details)
1229{
1230 struct i40e_aq_desc desc;
1231 struct i40e_aqc_switch_seid *scfg =
1232 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1233 i40e_status status;
1234
1235 i40e_fill_default_direct_cmd_desc(&desc,
1236 i40e_aqc_opc_get_switch_config);
1237 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1238 if (buf_size > I40E_AQ_LARGE_BUF)
1239 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1240 scfg->seid = cpu_to_le16(*start_seid);
1241
1242 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
1243 *start_seid = le16_to_cpu(scfg->seid);
1244
1245 return status;
1246}
1247
1248/**
1249 * i40e_aq_get_firmware_version
1250 * @hw: pointer to the hw struct
1251 * @fw_major_version: firmware major version
1252 * @fw_minor_version: firmware minor version
1253 * @api_major_version: major queue version
1254 * @api_minor_version: minor queue version
1255 * @cmd_details: pointer to command details structure or NULL
1256 *
1257 * Get the firmware version from the admin queue commands
1258 **/
1259i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
1260 u16 *fw_major_version, u16 *fw_minor_version,
1261 u16 *api_major_version, u16 *api_minor_version,
1262 struct i40e_asq_cmd_details *cmd_details)
1263{
1264 struct i40e_aq_desc desc;
1265 struct i40e_aqc_get_version *resp =
1266 (struct i40e_aqc_get_version *)&desc.params.raw;
1267 i40e_status status;
1268
1269 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
1270
1271 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1272
1273 if (!status) {
1274 if (fw_major_version != NULL)
1275 *fw_major_version = le16_to_cpu(resp->fw_major);
1276 if (fw_minor_version != NULL)
1277 *fw_minor_version = le16_to_cpu(resp->fw_minor);
1278 if (api_major_version != NULL)
1279 *api_major_version = le16_to_cpu(resp->api_major);
1280 if (api_minor_version != NULL)
1281 *api_minor_version = le16_to_cpu(resp->api_minor);
1282 }
1283
1284 return status;
1285}
1286
1287/**
1288 * i40e_aq_send_driver_version
1289 * @hw: pointer to the hw struct
56a62fc8
JB		 1290 * @dv: driver's major, minor version
1291 * @cmd_details: pointer to command details structure or NULL
1292 *
1293 * Send the driver version to the firmware
1294 **/
1295i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
1296 struct i40e_driver_version *dv,
1297 struct i40e_asq_cmd_details *cmd_details)
1298{
1299 struct i40e_aq_desc desc;
1300 struct i40e_aqc_driver_version *cmd =
1301 (struct i40e_aqc_driver_version *)&desc.params.raw;
1302 i40e_status status;
1303
1304 if (dv == NULL)
1305 return I40E_ERR_PARAM;
1306
1307 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
1308
1309 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
1310 cmd->driver_major_ver = dv->major_version;
1311 cmd->driver_minor_ver = dv->minor_version;
1312 cmd->driver_build_ver = dv->build_version;
1313 cmd->driver_subbuild_ver = dv->subbuild_version;
1314 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1315
1316 return status;
1317}
1318
1319/**
1320 * i40e_get_link_status - get status of the HW network link
1321 * @hw: pointer to the hw struct
1322 *
1323 * Returns true if link is up, false if link is down.
1324 *
1325 * Side effect: LinkStatusEvent reporting becomes enabled
1326 **/
1327bool i40e_get_link_status(struct i40e_hw *hw)
1328{
1329 i40e_status status = 0;
1330 bool link_status = false;
1331
1332 if (hw->phy.get_link_info) {
1333 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1334
1335 if (status)
1336 goto i40e_get_link_status_exit;
1337 }
1338
1339 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
1340
1341i40e_get_link_status_exit:
1342 return link_status;
1343}
1344
1345/**
1346 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
1347 * @hw: pointer to the hw struct
1348 * @uplink_seid: the MAC or other gizmo SEID
1349 * @downlink_seid: the VSI SEID
1350 * @enabled_tc: bitmap of TCs to be enabled
1351 * @default_port: true for default port VSI, false for control port
e1c51b95 1352 * @enable_l2_filtering: true to add L2 filter table rules to regular forwarding rules for cloud support
56a62fc8
JB		 1353 * @veb_seid: pointer to where to put the resulting VEB SEID
1354 * @cmd_details: pointer to command details structure or NULL
1355 *
1356 * This asks the FW to add a VEB between the uplink and downlink
1357 * elements. If the uplink SEID is 0, this will be a floating VEB.
1358 **/
1359i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
1360 u16 downlink_seid, u8 enabled_tc,
e1c51b95
KS		 1361 bool default_port, bool enable_l2_filtering,
1362 u16 *veb_seid,
56a62fc8
JB		 1363 struct i40e_asq_cmd_details *cmd_details)
1364{
1365 struct i40e_aq_desc desc;
1366 struct i40e_aqc_add_veb *cmd =
1367 (struct i40e_aqc_add_veb *)&desc.params.raw;
1368 struct i40e_aqc_add_veb_completion *resp =
1369 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
1370 i40e_status status;
1371 u16 veb_flags = 0;
1372
1373 /* SEIDs need to either both be set or both be 0 for floating VEB */
1374 if (!!uplink_seid != !!downlink_seid)
1375 return I40E_ERR_PARAM;
1376
1377 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
1378
1379 cmd->uplink_seid = cpu_to_le16(uplink_seid);
1380 cmd->downlink_seid = cpu_to_le16(downlink_seid);
1381 cmd->enable_tcs = enabled_tc;
1382 if (!uplink_seid)
1383 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
1384 if (default_port)
1385 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
1386 else
1387 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
e1c51b95
KS		 1388
1389 if (enable_l2_filtering)
1390 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_L2_FILTER;
1391
56a62fc8
JB		 1392 cmd->veb_flags = cpu_to_le16(veb_flags);
1393
1394 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1395
1396 if (!status && veb_seid)
1397 *veb_seid = le16_to_cpu(resp->veb_seid);
1398
1399 return status;
1400}
1401
1402/**
1403 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
1404 * @hw: pointer to the hw struct
1405 * @veb_seid: the SEID of the VEB to query
1406 * @switch_id: the uplink switch id
98d44381 1407 * @floating: set to true if the VEB is floating
56a62fc8
JB		 1408 * @statistic_index: index of the stats counter block for this VEB
1409 * @vebs_used: number of VEB's used by function
98d44381 1410 * @vebs_free: total VEB's not reserved by any function
56a62fc8
JB		 1411 * @cmd_details: pointer to command details structure or NULL
1412 *
1413 * This retrieves the parameters for a particular VEB, specified by
1414 * uplink_seid, and returns them to the caller.
1415 **/
1416i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
1417 u16 veb_seid, u16 *switch_id,
1418 bool *floating, u16 *statistic_index,
1419 u16 *vebs_used, u16 *vebs_free,
1420 struct i40e_asq_cmd_details *cmd_details)
1421{
1422 struct i40e_aq_desc desc;
1423 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
1424 (struct i40e_aqc_get_veb_parameters_completion *)
1425 &desc.params.raw;
1426 i40e_status status;
1427
1428 if (veb_seid == 0)
1429 return I40E_ERR_PARAM;
1430
1431 i40e_fill_default_direct_cmd_desc(&desc,
1432 i40e_aqc_opc_get_veb_parameters);
1433 cmd_resp->seid = cpu_to_le16(veb_seid);
1434
1435 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1436 if (status)
1437 goto get_veb_exit;
1438
1439 if (switch_id)
1440 *switch_id = le16_to_cpu(cmd_resp->switch_id);
1441 if (statistic_index)
1442 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
1443 if (vebs_used)
1444 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
1445 if (vebs_free)
1446 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
1447 if (floating) {
1448 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
1449 if (flags & I40E_AQC_ADD_VEB_FLOATING)
1450 *floating = true;
1451 else
1452 *floating = false;
1453 }
1454
1455get_veb_exit:
1456 return status;
1457}
1458
1459/**
1460 * i40e_aq_add_macvlan
1461 * @hw: pointer to the hw struct
1462 * @seid: VSI for the mac address
1463 * @mv_list: list of macvlans to be added
1464 * @count: length of the list
1465 * @cmd_details: pointer to command details structure or NULL
1466 *
1467 * Add MAC/VLAN addresses to the HW filtering
1468 **/
1469i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
1470 struct i40e_aqc_add_macvlan_element_data *mv_list,
1471 u16 count, struct i40e_asq_cmd_details *cmd_details)
1472{
1473 struct i40e_aq_desc desc;
1474 struct i40e_aqc_macvlan *cmd =
1475 (struct i40e_aqc_macvlan *)&desc.params.raw;
1476 i40e_status status;
1477 u16 buf_size;
1478
1479 if (count == 0 || !mv_list || !hw)
1480 return I40E_ERR_PARAM;
1481
1482 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1483
1484 /* prep the rest of the request */
1485 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1486 cmd->num_addresses = cpu_to_le16(count);
1487 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1488 cmd->seid[1] = 0;
1489 cmd->seid[2] = 0;
1490
1491 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1492 if (buf_size > I40E_AQ_LARGE_BUF)
1493 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1494
1495 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1496 cmd_details);
1497
1498 return status;
1499}
1500
1501/**
1502 * i40e_aq_remove_macvlan
1503 * @hw: pointer to the hw struct
1504 * @seid: VSI for the mac address
1505 * @mv_list: list of macvlans to be removed
1506 * @count: length of the list
1507 * @cmd_details: pointer to command details structure or NULL
1508 *
1509 * Remove MAC/VLAN addresses from the HW filtering
1510 **/
1511i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1512 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1513 u16 count, struct i40e_asq_cmd_details *cmd_details)
1514{
1515 struct i40e_aq_desc desc;
1516 struct i40e_aqc_macvlan *cmd =
1517 (struct i40e_aqc_macvlan *)&desc.params.raw;
1518 i40e_status status;
1519 u16 buf_size;
1520
1521 if (count == 0 || !mv_list || !hw)
1522 return I40E_ERR_PARAM;
1523
1524 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1525
1526 /* prep the rest of the request */
1527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1528 cmd->num_addresses = cpu_to_le16(count);
1529 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1530 cmd->seid[1] = 0;
1531 cmd->seid[2] = 0;
1532
1533 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1534 if (buf_size > I40E_AQ_LARGE_BUF)
1535 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1536
1537 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1538 cmd_details);
1539
1540 return status;
1541}
1542
56a62fc8
JB		 1543/**
1544 * i40e_aq_send_msg_to_vf
1545 * @hw: pointer to the hardware structure
1546 * @vfid: vf id to send msg
98d44381
JK		 1547 * @v_opcode: opcodes for VF-PF communication
1548 * @v_retval: return error code
56a62fc8
JB		 1549 * @msg: pointer to the msg buffer
1550 * @msglen: msg length
1551 * @cmd_details: pointer to command details
1552 *
1553 * send msg to vf
1554 **/
1555i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1556 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1557 struct i40e_asq_cmd_details *cmd_details)
1558{
1559 struct i40e_aq_desc desc;
1560 struct i40e_aqc_pf_vf_message *cmd =
1561 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1562 i40e_status status;
1563
1564 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1565 cmd->id = cpu_to_le32(vfid);
1566 desc.cookie_high = cpu_to_le32(v_opcode);
1567 desc.cookie_low = cpu_to_le32(v_retval);
1568 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1569 if (msglen) {
1570 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1571 I40E_AQ_FLAG_RD));
1572 if (msglen > I40E_AQ_LARGE_BUF)
1573 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1574 desc.datalen = cpu_to_le16(msglen);
1575 }
1576 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1577
1578 return status;
1579}
1580
1581/**
1582 * i40e_aq_set_hmc_resource_profile
1583 * @hw: pointer to the hw struct
1584 * @profile: type of profile the HMC is to be set as
1585 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1586 * @cmd_details: pointer to command details structure or NULL
1587 *
1588 * set the HMC profile of the device.
1589 **/
1590i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1591 enum i40e_aq_hmc_profile profile,
1592 u8 pe_vf_enabled_count,
1593 struct i40e_asq_cmd_details *cmd_details)
1594{
1595 struct i40e_aq_desc desc;
1596 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1597 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1598 i40e_status status;
1599
1600 i40e_fill_default_direct_cmd_desc(&desc,
1601 i40e_aqc_opc_set_hmc_resource_profile);
1602
1603 cmd->pm_profile = (u8)profile;
1604 cmd->pe_vf_enabled = pe_vf_enabled_count;
1605
1606 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1607
1608 return status;
1609}
1610
1611/**
1612 * i40e_aq_request_resource
1613 * @hw: pointer to the hw struct
1614 * @resource: resource id
1615 * @access: access type
1616 * @sdp_number: resource number
1617 * @timeout: the maximum time in ms that the driver may hold the resource
1618 * @cmd_details: pointer to command details structure or NULL
1619 *
1620 * requests common resource using the admin queue commands
1621 **/
1622i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1623 enum i40e_aq_resources_ids resource,
1624 enum i40e_aq_resource_access_type access,
1625 u8 sdp_number, u64 *timeout,
1626 struct i40e_asq_cmd_details *cmd_details)
1627{
1628 struct i40e_aq_desc desc;
1629 struct i40e_aqc_request_resource *cmd_resp =
1630 (struct i40e_aqc_request_resource *)&desc.params.raw;
1631 i40e_status status;
1632
1633 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
1634
1635 cmd_resp->resource_id = cpu_to_le16(resource);
1636 cmd_resp->access_type = cpu_to_le16(access);
1637 cmd_resp->resource_number = cpu_to_le32(sdp_number);
1638
1639 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1640 /* The completion specifies the maximum time in ms that the driver
1641 * may hold the resource in the Timeout field.
1642 * If the resource is held by someone else, the command completes with
1643 * busy return value and the timeout field indicates the maximum time
1644 * the current owner of the resource has to free it.
1645 */
1646 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
1647 *timeout = le32_to_cpu(cmd_resp->timeout);
1648
1649 return status;
1650}
1651
1652/**
1653 * i40e_aq_release_resource
1654 * @hw: pointer to the hw struct
1655 * @resource: resource id
1656 * @sdp_number: resource number
1657 * @cmd_details: pointer to command details structure or NULL
1658 *
1659 * release common resource using the admin queue commands
1660 **/
1661i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
1662 enum i40e_aq_resources_ids resource,
1663 u8 sdp_number,
1664 struct i40e_asq_cmd_details *cmd_details)
1665{
1666 struct i40e_aq_desc desc;
1667 struct i40e_aqc_request_resource *cmd =
1668 (struct i40e_aqc_request_resource *)&desc.params.raw;
1669 i40e_status status;
1670
1671 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
1672
1673 cmd->resource_id = cpu_to_le16(resource);
1674 cmd->resource_number = cpu_to_le32(sdp_number);
1675
1676 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1677
1678 return status;
1679}
1680
1681/**
1682 * i40e_aq_read_nvm
1683 * @hw: pointer to the hw struct
1684 * @module_pointer: module pointer location in words from the NVM beginning
1685 * @offset: byte offset from the module beginning
1686 * @length: length of the section to be read (in bytes from the offset)
1687 * @data: command buffer (size [bytes] = length)
1688 * @last_command: tells if this is the last command in a series
1689 * @cmd_details: pointer to command details structure or NULL
1690 *
1691 * Read the NVM using the admin queue commands
1692 **/
1693i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
1694 u32 offset, u16 length, void *data,
1695 bool last_command,
1696 struct i40e_asq_cmd_details *cmd_details)
1697{
1698 struct i40e_aq_desc desc;
1699 struct i40e_aqc_nvm_update *cmd =
1700 (struct i40e_aqc_nvm_update *)&desc.params.raw;
1701 i40e_status status;
1702
1703 /* In offset the highest byte must be zeroed. */
1704 if (offset & 0xFF000000) {
1705 status = I40E_ERR_PARAM;
1706 goto i40e_aq_read_nvm_exit;
1707 }
1708
1709 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
1710
1711 /* If this is the last command in a series, set the proper flag. */
1712 if (last_command)
1713 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
1714 cmd->module_pointer = module_pointer;
1715 cmd->offset = cpu_to_le32(offset);
1716 cmd->length = cpu_to_le16(length);
1717
1718 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1719 if (length > I40E_AQ_LARGE_BUF)
1720 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1721
1722 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
1723
1724i40e_aq_read_nvm_exit:
1725 return status;
1726}
1727
1728#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1729#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1730#define I40E_DEV_FUNC_CAP_NPAR 0x03
1731#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1732#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1733#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1734#define I40E_DEV_FUNC_CAP_VF 0x13
1735#define I40E_DEV_FUNC_CAP_VMDQ 0x14
1736#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1737#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1738#define I40E_DEV_FUNC_CAP_VSI 0x17
1739#define I40E_DEV_FUNC_CAP_DCB 0x18
1740#define I40E_DEV_FUNC_CAP_FCOE 0x21
1741#define I40E_DEV_FUNC_CAP_RSS 0x40
1742#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1743#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1744#define I40E_DEV_FUNC_CAP_MSIX 0x43
1745#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1746#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1747#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1748#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1749#define I40E_DEV_FUNC_CAP_CEM 0xF2
1750#define I40E_DEV_FUNC_CAP_IWARP 0x51
1751#define I40E_DEV_FUNC_CAP_LED 0x61
1752#define I40E_DEV_FUNC_CAP_SDP 0x62
1753#define I40E_DEV_FUNC_CAP_MDIO 0x63
1754
1755/**
1756 * i40e_parse_discover_capabilities
1757 * @hw: pointer to the hw struct
1758 * @buff: pointer to a buffer containing device/function capability records
1759 * @cap_count: number of capability records in the list
1760 * @list_type_opc: type of capabilities list to parse
1761 *
1762 * Parse the device/function capabilities list.
1763 **/
1764static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1765 u32 cap_count,
1766 enum i40e_admin_queue_opc list_type_opc)
1767{
1768 struct i40e_aqc_list_capabilities_element_resp *cap;
1769 u32 number, logical_id, phys_id;
1770 struct i40e_hw_capabilities *p;
1771 u32 reg_val;
1772 u32 i = 0;
1773 u16 id;
1774
1775 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
1776
1777 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
1778 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
1779 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
1780 p = (struct i40e_hw_capabilities *)&hw->func_caps;
1781 else
1782 return;
1783
1784 for (i = 0; i < cap_count; i++, cap++) {
1785 id = le16_to_cpu(cap->id);
1786 number = le32_to_cpu(cap->number);
1787 logical_id = le32_to_cpu(cap->logical_id);
1788 phys_id = le32_to_cpu(cap->phys_id);
1789
1790 switch (id) {
1791 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
1792 p->switch_mode = number;
1793 break;
1794 case I40E_DEV_FUNC_CAP_MGMT_MODE:
1795 p->management_mode = number;
1796 break;
1797 case I40E_DEV_FUNC_CAP_NPAR:
1798 p->npar_enable = number;
1799 break;
1800 case I40E_DEV_FUNC_CAP_OS2BMC:
1801 p->os2bmc = number;
1802 break;
1803 case I40E_DEV_FUNC_CAP_VALID_FUNC:
1804 p->valid_functions = number;
1805 break;
1806 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
1807 if (number == 1)
1808 p->sr_iov_1_1 = true;
1809 break;
1810 case I40E_DEV_FUNC_CAP_VF:
1811 p->num_vfs = number;
1812 p->vf_base_id = logical_id;
1813 break;
1814 case I40E_DEV_FUNC_CAP_VMDQ:
1815 if (number == 1)
1816 p->vmdq = true;
1817 break;
1818 case I40E_DEV_FUNC_CAP_802_1_QBG:
1819 if (number == 1)
1820 p->evb_802_1_qbg = true;
1821 break;
1822 case I40E_DEV_FUNC_CAP_802_1_QBH:
1823 if (number == 1)
1824 p->evb_802_1_qbh = true;
1825 break;
1826 case I40E_DEV_FUNC_CAP_VSI:
1827 p->num_vsis = number;
1828 break;
1829 case I40E_DEV_FUNC_CAP_DCB:
1830 if (number == 1) {
1831 p->dcb = true;
1832 p->enabled_tcmap = logical_id;
1833 p->maxtc = phys_id;
1834 }
1835 break;
1836 case I40E_DEV_FUNC_CAP_FCOE:
1837 if (number == 1)
1838 p->fcoe = true;
1839 break;
1840 case I40E_DEV_FUNC_CAP_RSS:
1841 p->rss = true;
1842 reg_val = rd32(hw, I40E_PFQF_CTL_0);
1843 if (reg_val & I40E_PFQF_CTL_0_HASHLUTSIZE_MASK)
1844 p->rss_table_size = number;
1845 else
1846 p->rss_table_size = 128;
1847 p->rss_table_entry_width = logical_id;
1848 break;
1849 case I40E_DEV_FUNC_CAP_RX_QUEUES:
1850 p->num_rx_qp = number;
1851 p->base_queue = phys_id;
1852 break;
1853 case I40E_DEV_FUNC_CAP_TX_QUEUES:
1854 p->num_tx_qp = number;
1855 p->base_queue = phys_id;
1856 break;
1857 case I40E_DEV_FUNC_CAP_MSIX:
1858 p->num_msix_vectors = number;
1859 break;
1860 case I40E_DEV_FUNC_CAP_MSIX_VF:
1861 p->num_msix_vectors_vf = number;
1862 break;
1863 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
1864 if (number == 1)
1865 p->mfp_mode_1 = true;
1866 break;
1867 case I40E_DEV_FUNC_CAP_CEM:
1868 if (number == 1)
1869 p->mgmt_cem = true;
1870 break;
1871 case I40E_DEV_FUNC_CAP_IWARP:
1872 if (number == 1)
1873 p->iwarp = true;
1874 break;
1875 case I40E_DEV_FUNC_CAP_LED:
1876 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1877 p->led[phys_id] = true;
1878 break;
1879 case I40E_DEV_FUNC_CAP_SDP:
1880 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1881 p->sdp[phys_id] = true;
1882 break;
1883 case I40E_DEV_FUNC_CAP_MDIO:
1884 if (number == 1) {
1885 p->mdio_port_num = phys_id;
1886 p->mdio_port_mode = logical_id;
1887 }
1888 break;
1889 case I40E_DEV_FUNC_CAP_IEEE_1588:
1890 if (number == 1)
1891 p->ieee_1588 = true;
1892 break;
1893 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
1894 p->fd = true;
1895 p->fd_filters_guaranteed = number;
1896 p->fd_filters_best_effort = logical_id;
1897 break;
1898 default:
1899 break;
1900 }
1901 }
1902
1903 /* additional HW specific goodies that might
1904 * someday be HW version specific
1905 */
1906 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
1907}
1908
1909/**
1910 * i40e_aq_discover_capabilities
1911 * @hw: pointer to the hw struct
1912 * @buff: a virtual buffer to hold the capabilities
1913 * @buff_size: Size of the virtual buffer
1914 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
1915 * @list_type_opc: capabilities type to discover - pass in the command opcode
1916 * @cmd_details: pointer to command details structure or NULL
1917 *
1918 * Get the device capabilities descriptions from the firmware
1919 **/
1920i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
1921 void *buff, u16 buff_size, u16 *data_size,
1922 enum i40e_admin_queue_opc list_type_opc,
1923 struct i40e_asq_cmd_details *cmd_details)
1924{
1925 struct i40e_aqc_list_capabilites *cmd;
56a62fc8 1926 struct i40e_aq_desc desc;
8fb905b3 1927 i40e_status status = 0;
56a62fc8
JB		 1928
1929 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
1930
1931 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
1932 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
1933 status = I40E_ERR_PARAM;
1934 goto exit;
1935 }
1936
1937 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
1938
1939 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1940 if (buff_size > I40E_AQ_LARGE_BUF)
1941 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1942
1943 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1944 *data_size = le16_to_cpu(desc.datalen);
1945
1946 if (status)
1947 goto exit;
1948
1949 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
1950 list_type_opc);
1951
1952exit:
1953 return status;
1954}
1955
1956/**
1957 * i40e_aq_get_lldp_mib
1958 * @hw: pointer to the hw struct
1959 * @bridge_type: type of bridge requested
1960 * @mib_type: Local, Remote or both Local and Remote MIBs
1961 * @buff: pointer to a user supplied buffer to store the MIB block
1962 * @buff_size: size of the buffer (in bytes)
1963 * @local_len : length of the returned Local LLDP MIB
1964 * @remote_len: length of the returned Remote LLDP MIB
1965 * @cmd_details: pointer to command details structure or NULL
1966 *
1967 * Requests the complete LLDP MIB (entire packet).
1968 **/
1969i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
1970 u8 mib_type, void *buff, u16 buff_size,
1971 u16 *local_len, u16 *remote_len,
1972 struct i40e_asq_cmd_details *cmd_details)
1973{
1974 struct i40e_aq_desc desc;
1975 struct i40e_aqc_lldp_get_mib *cmd =
1976 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1977 struct i40e_aqc_lldp_get_mib *resp =
1978 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1979 i40e_status status;
1980
1981 if (buff_size == 0 || !buff)
1982 return I40E_ERR_PARAM;
1983
1984 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
1985 /* Indirect Command */
1986 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1987
1988 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
1989 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
1990 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
1991
1992 desc.datalen = cpu_to_le16(buff_size);
1993
1994 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1995 if (buff_size > I40E_AQ_LARGE_BUF)
1996 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1997
1998 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1999 if (!status) {
2000 if (local_len != NULL)
2001 *local_len = le16_to_cpu(resp->local_len);
2002 if (remote_len != NULL)
2003 *remote_len = le16_to_cpu(resp->remote_len);
2004 }
2005
2006 return status;
2007}
2008
2009/**
2010 * i40e_aq_cfg_lldp_mib_change_event
2011 * @hw: pointer to the hw struct
2012 * @enable_update: Enable or Disable event posting
2013 * @cmd_details: pointer to command details structure or NULL
2014 *
2015 * Enable or Disable posting of an event on ARQ when LLDP MIB
2016 * associated with the interface changes
2017 **/
2018i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
2019 bool enable_update,
2020 struct i40e_asq_cmd_details *cmd_details)
2021{
2022 struct i40e_aq_desc desc;
2023 struct i40e_aqc_lldp_update_mib *cmd =
2024 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
2025 i40e_status status;
2026
2027 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
2028
2029 if (!enable_update)
2030 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
2031
2032 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2033
2034 return status;
2035}
2036
2037/**
2038 * i40e_aq_stop_lldp
2039 * @hw: pointer to the hw struct
2040 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
2041 * @cmd_details: pointer to command details structure or NULL
2042 *
2043 * Stop or Shutdown the embedded LLDP Agent
2044 **/
2045i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
2046 struct i40e_asq_cmd_details *cmd_details)
2047{
2048 struct i40e_aq_desc desc;
2049 struct i40e_aqc_lldp_stop *cmd =
2050 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
2051 i40e_status status;
2052
2053 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
2054
2055 if (shutdown_agent)
2056 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
2057
2058 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2059
2060 return status;
2061}
2062
2063/**
2064 * i40e_aq_start_lldp
2065 * @hw: pointer to the hw struct
2066 * @cmd_details: pointer to command details structure or NULL
2067 *
2068 * Start the embedded LLDP Agent on all ports.
2069 **/
2070i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
2071 struct i40e_asq_cmd_details *cmd_details)
2072{
2073 struct i40e_aq_desc desc;
2074 struct i40e_aqc_lldp_start *cmd =
2075 (struct i40e_aqc_lldp_start *)&desc.params.raw;
2076 i40e_status status;
2077
2078 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
2079
2080 cmd->command = I40E_AQ_LLDP_AGENT_START;
2081
2082 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2083
2084 return status;
2085}
2086
a1c9a9d9
JK		 2087/**
2088 * i40e_aq_add_udp_tunnel
2089 * @hw: pointer to the hw struct
2090 * @udp_port: the UDP port to add
2091 * @header_len: length of the tunneling header length in DWords
2092 * @protocol_index: protocol index type
98d44381 2093 * @filter_index: pointer to filter index
a1c9a9d9
JK		 2094 * @cmd_details: pointer to command details structure or NULL
2095 **/
2096i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
2097 u16 udp_port, u8 header_len,
2098 u8 protocol_index, u8 *filter_index,
2099 struct i40e_asq_cmd_details *cmd_details)
2100{
2101 struct i40e_aq_desc desc;
2102 struct i40e_aqc_add_udp_tunnel *cmd =
2103 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
2104 struct i40e_aqc_del_udp_tunnel_completion *resp =
2105 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
2106 i40e_status status;
2107
2108 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
2109
2110 cmd->udp_port = cpu_to_le16(udp_port);
981b7545 2111 cmd->protocol_type = protocol_index;
a1c9a9d9
JK		 2112
2113 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2114
2115 if (!status)
2116 *filter_index = resp->index;
2117
2118 return status;
2119}
2120
2121/**
2122 * i40e_aq_del_udp_tunnel
2123 * @hw: pointer to the hw struct
2124 * @index: filter index
2125 * @cmd_details: pointer to command details structure or NULL
2126 **/
2127i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
2128 struct i40e_asq_cmd_details *cmd_details)
2129{
2130 struct i40e_aq_desc desc;
2131 struct i40e_aqc_remove_udp_tunnel *cmd =
2132 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
2133 i40e_status status;
2134
2135 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
2136
2137 cmd->index = index;
2138
2139 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2140
2141 return status;
2142}
2143
56a62fc8
JB		 2144/**
2145 * i40e_aq_delete_element - Delete switch element
2146 * @hw: pointer to the hw struct
2147 * @seid: the SEID to delete from the switch
2148 * @cmd_details: pointer to command details structure or NULL
2149 *
2150 * This deletes a switch element from the switch.
2151 **/
2152i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
2153 struct i40e_asq_cmd_details *cmd_details)
2154{
2155 struct i40e_aq_desc desc;
2156 struct i40e_aqc_switch_seid *cmd =
2157 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2158 i40e_status status;
2159
2160 if (seid == 0)
2161 return I40E_ERR_PARAM;
2162
2163 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
2164
2165 cmd->seid = cpu_to_le16(seid);
2166
2167 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2168
2169 return status;
2170}
2171
afb3ff0d
NP		 2172/**
2173 * i40e_aq_dcb_updated - DCB Updated Command
2174 * @hw: pointer to the hw struct
2175 * @cmd_details: pointer to command details structure or NULL
2176 *
2177 * EMP will return when the shared RPB settings have been
2178 * recomputed and modified. The retval field in the descriptor
2179 * will be set to 0 when RPB is modified.
2180 **/
2181i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
2182 struct i40e_asq_cmd_details *cmd_details)
2183{
2184 struct i40e_aq_desc desc;
2185 i40e_status status;
2186
2187 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
2188
2189 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2190
2191 return status;
2192}
2193
56a62fc8
JB		 2194/**
2195 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
2196 * @hw: pointer to the hw struct
2197 * @seid: seid for the physical port/switching component/vsi
2198 * @buff: Indirect buffer to hold data parameters and response
2199 * @buff_size: Indirect buffer size
2200 * @opcode: Tx scheduler AQ command opcode
2201 * @cmd_details: pointer to command details structure or NULL
2202 *
2203 * Generic command handler for Tx scheduler AQ commands
2204 **/
2205static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
2206 void *buff, u16 buff_size,
2207 enum i40e_admin_queue_opc opcode,
2208 struct i40e_asq_cmd_details *cmd_details)
2209{
2210 struct i40e_aq_desc desc;
2211 struct i40e_aqc_tx_sched_ind *cmd =
2212 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
2213 i40e_status status;
2214 bool cmd_param_flag = false;
2215
2216 switch (opcode) {
2217 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
2218 case i40e_aqc_opc_configure_vsi_tc_bw:
2219 case i40e_aqc_opc_enable_switching_comp_ets:
2220 case i40e_aqc_opc_modify_switching_comp_ets:
2221 case i40e_aqc_opc_disable_switching_comp_ets:
2222 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
2223 case i40e_aqc_opc_configure_switching_comp_bw_config:
2224 cmd_param_flag = true;
2225 break;
2226 case i40e_aqc_opc_query_vsi_bw_config:
2227 case i40e_aqc_opc_query_vsi_ets_sla_config:
2228 case i40e_aqc_opc_query_switching_comp_ets_config:
2229 case i40e_aqc_opc_query_port_ets_config:
2230 case i40e_aqc_opc_query_switching_comp_bw_config:
2231 cmd_param_flag = false;
2232 break;
2233 default:
2234 return I40E_ERR_PARAM;
2235 }
2236
2237 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2238
2239 /* Indirect command */
2240 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2241 if (cmd_param_flag)
2242 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
2243 if (buff_size > I40E_AQ_LARGE_BUF)
2244 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2245
2246 desc.datalen = cpu_to_le16(buff_size);
2247
2248 cmd->vsi_seid = cpu_to_le16(seid);
2249
2250 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
2251
2252 return status;
2253}
2254
2255/**
2256 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
2257 * @hw: pointer to the hw struct
2258 * @seid: VSI seid
2259 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
2260 * @cmd_details: pointer to command details structure or NULL
2261 **/
2262i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
2263 u16 seid,
2264 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
2265 struct i40e_asq_cmd_details *cmd_details)
2266{
2267 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2268 i40e_aqc_opc_configure_vsi_tc_bw,
2269 cmd_details);
2270}
2271
afb3ff0d
NP		 2272/**
2273 * i40e_aq_config_switch_comp_ets - Enable/Disable/Modify ETS on the port
2274 * @hw: pointer to the hw struct
2275 * @seid: seid of the switching component connected to Physical Port
2276 * @ets_data: Buffer holding ETS parameters
2277 * @cmd_details: pointer to command details structure or NULL
2278 **/
2279i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
2280 u16 seid,
2281 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
2282 enum i40e_admin_queue_opc opcode,
2283 struct i40e_asq_cmd_details *cmd_details)
2284{
2285 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
2286 sizeof(*ets_data), opcode, cmd_details);
2287}
2288
2289/**
2290 * i40e_aq_config_switch_comp_bw_config - Config Switch comp BW Alloc per TC
2291 * @hw: pointer to the hw struct
2292 * @seid: seid of the switching component
2293 * @bw_data: Buffer holding enabled TCs, relative/absolute TC BW limit/credits
2294 * @cmd_details: pointer to command details structure or NULL
2295 **/
2296i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
2297 u16 seid,
2298 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
2299 struct i40e_asq_cmd_details *cmd_details)
2300{
2301 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2302 i40e_aqc_opc_configure_switching_comp_bw_config,
2303 cmd_details);
2304}
2305
56a62fc8
JB		 2306/**
2307 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
2308 * @hw: pointer to the hw struct
2309 * @seid: seid of the VSI
2310 * @bw_data: Buffer to hold VSI BW configuration
2311 * @cmd_details: pointer to command details structure or NULL
2312 **/
2313i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
2314 u16 seid,
2315 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
2316 struct i40e_asq_cmd_details *cmd_details)
2317{
2318 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2319 i40e_aqc_opc_query_vsi_bw_config,
2320 cmd_details);
2321}
2322
2323/**
2324 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
2325 * @hw: pointer to the hw struct
2326 * @seid: seid of the VSI
2327 * @bw_data: Buffer to hold VSI BW configuration per TC
2328 * @cmd_details: pointer to command details structure or NULL
2329 **/
2330i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
2331 u16 seid,
2332 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
2333 struct i40e_asq_cmd_details *cmd_details)
2334{
2335 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2336 i40e_aqc_opc_query_vsi_ets_sla_config,
2337 cmd_details);
2338}
2339
2340/**
2341 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
2342 * @hw: pointer to the hw struct
2343 * @seid: seid of the switching component
2344 * @bw_data: Buffer to hold switching component's per TC BW config
2345 * @cmd_details: pointer to command details structure or NULL
2346 **/
2347i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
2348 u16 seid,
2349 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
2350 struct i40e_asq_cmd_details *cmd_details)
2351{
2352 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2353 i40e_aqc_opc_query_switching_comp_ets_config,
2354 cmd_details);
2355}
2356
2357/**
2358 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
2359 * @hw: pointer to the hw struct
2360 * @seid: seid of the VSI or switching component connected to Physical Port
2361 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
2362 * @cmd_details: pointer to command details structure or NULL
2363 **/
2364i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
2365 u16 seid,
2366 struct i40e_aqc_query_port_ets_config_resp *bw_data,
2367 struct i40e_asq_cmd_details *cmd_details)
2368{
2369 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2370 i40e_aqc_opc_query_port_ets_config,
2371 cmd_details);
2372}
2373
2374/**
2375 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
2376 * @hw: pointer to the hw struct
2377 * @seid: seid of the switching component
2378 * @bw_data: Buffer to hold switching component's BW configuration
2379 * @cmd_details: pointer to command details structure or NULL
2380 **/
2381i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
2382 u16 seid,
2383 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
2384 struct i40e_asq_cmd_details *cmd_details)
2385{
2386 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
2387 i40e_aqc_opc_query_switching_comp_bw_config,
2388 cmd_details);
2389}
2390
2391/**
2392 * i40e_validate_filter_settings
2393 * @hw: pointer to the hardware structure
2394 * @settings: Filter control settings
2395 *
2396 * Check and validate the filter control settings passed.
2397 * The function checks for the valid filter/context sizes being
2398 * passed for FCoE and PE.
2399 *
2400 * Returns 0 if the values passed are valid and within
2401 * range else returns an error.
2402 **/
2403static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
2404 struct i40e_filter_control_settings *settings)
2405{
2406 u32 fcoe_cntx_size, fcoe_filt_size;
2407 u32 pe_cntx_size, pe_filt_size;
2408 u32 fcoe_fmax, pe_fmax;
2409 u32 val;
2410
2411 /* Validate FCoE settings passed */
2412 switch (settings->fcoe_filt_num) {
2413 case I40E_HASH_FILTER_SIZE_1K:
2414 case I40E_HASH_FILTER_SIZE_2K:
2415 case I40E_HASH_FILTER_SIZE_4K:
2416 case I40E_HASH_FILTER_SIZE_8K:
2417 case I40E_HASH_FILTER_SIZE_16K:
2418 case I40E_HASH_FILTER_SIZE_32K:
2419 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2420 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
2421 break;
2422 default:
2423 return I40E_ERR_PARAM;
2424 }
2425
2426 switch (settings->fcoe_cntx_num) {
2427 case I40E_DMA_CNTX_SIZE_512:
2428 case I40E_DMA_CNTX_SIZE_1K:
2429 case I40E_DMA_CNTX_SIZE_2K:
2430 case I40E_DMA_CNTX_SIZE_4K:
2431 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2432 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
2433 break;
2434 default:
2435 return I40E_ERR_PARAM;
2436 }
2437
2438 /* Validate PE settings passed */
2439 switch (settings->pe_filt_num) {
2440 case I40E_HASH_FILTER_SIZE_1K:
2441 case I40E_HASH_FILTER_SIZE_2K:
2442 case I40E_HASH_FILTER_SIZE_4K:
2443 case I40E_HASH_FILTER_SIZE_8K:
2444 case I40E_HASH_FILTER_SIZE_16K:
2445 case I40E_HASH_FILTER_SIZE_32K:
2446 case I40E_HASH_FILTER_SIZE_64K:
2447 case I40E_HASH_FILTER_SIZE_128K:
2448 case I40E_HASH_FILTER_SIZE_256K:
2449 case I40E_HASH_FILTER_SIZE_512K:
2450 case I40E_HASH_FILTER_SIZE_1M:
2451 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
2452 pe_filt_size <<= (u32)settings->pe_filt_num;
2453 break;
2454 default:
2455 return I40E_ERR_PARAM;
2456 }
2457
2458 switch (settings->pe_cntx_num) {
2459 case I40E_DMA_CNTX_SIZE_512:
2460 case I40E_DMA_CNTX_SIZE_1K:
2461 case I40E_DMA_CNTX_SIZE_2K:
2462 case I40E_DMA_CNTX_SIZE_4K:
2463 case I40E_DMA_CNTX_SIZE_8K:
2464 case I40E_DMA_CNTX_SIZE_16K:
2465 case I40E_DMA_CNTX_SIZE_32K:
2466 case I40E_DMA_CNTX_SIZE_64K:
2467 case I40E_DMA_CNTX_SIZE_128K:
2468 case I40E_DMA_CNTX_SIZE_256K:
2469 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
2470 pe_cntx_size <<= (u32)settings->pe_cntx_num;
2471 break;
2472 default:
2473 return I40E_ERR_PARAM;
2474 }
2475
2476 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
2477 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
2478 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
2479 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
2480 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
2481 return I40E_ERR_INVALID_SIZE;
2482
2483 /* PEHSIZE + PEDSIZE should not be greater than PMPEXFMAX */
2484 val = rd32(hw, I40E_GLHMC_PEXFMAX);
2485 pe_fmax = (val & I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK)
2486 >> I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT;
2487 if (pe_filt_size + pe_cntx_size > pe_fmax)
2488 return I40E_ERR_INVALID_SIZE;
2489
2490 return 0;
2491}
2492
2493/**
2494 * i40e_set_filter_control
2495 * @hw: pointer to the hardware structure
2496 * @settings: Filter control settings
2497 *
2498 * Set the Queue Filters for PE/FCoE and enable filters required
2499 * for a single PF. It is expected that these settings are programmed
2500 * at the driver initialization time.
2501 **/
2502i40e_status i40e_set_filter_control(struct i40e_hw *hw,
2503 struct i40e_filter_control_settings *settings)
2504{
2505 i40e_status ret = 0;
2506 u32 hash_lut_size = 0;
2507 u32 val;
2508
2509 if (!settings)
2510 return I40E_ERR_PARAM;
2511
2512 /* Validate the input settings */
2513 ret = i40e_validate_filter_settings(hw, settings);
2514 if (ret)
2515 return ret;
2516
2517 /* Read the PF Queue Filter control register */
2518 val = rd32(hw, I40E_PFQF_CTL_0);
2519
2520 /* Program required PE hash buckets for the PF */
2521 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2522 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2523 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2524 /* Program required PE contexts for the PF */
2525 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2526 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2527 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2528
2529 /* Program required FCoE hash buckets for the PF */
2530 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2531 val |= ((u32)settings->fcoe_filt_num <<
2532 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2533 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2534 /* Program required FCoE DDP contexts for the PF */
2535 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2536 val |= ((u32)settings->fcoe_cntx_num <<
2537 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2538 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2539
2540 /* Program Hash LUT size for the PF */
2541 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2542 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2543 hash_lut_size = 1;
2544 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2545 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2546
2547 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2548 if (settings->enable_fdir)
2549 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2550 if (settings->enable_ethtype)
2551 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2552 if (settings->enable_macvlan)
2553 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2554
2555 wr32(hw, I40E_PFQF_CTL_0, val);
2556
2557 return 0;
2558}
afb3ff0d
NP		 2559
2560/**
2561 * i40e_aq_add_rem_control_packet_filter - Add or Remove Control Packet Filter
2562 * @hw: pointer to the hw struct
2563 * @mac_addr: MAC address to use in the filter
2564 * @ethtype: Ethertype to use in the filter
2565 * @flags: Flags that needs to be applied to the filter
2566 * @vsi_seid: seid of the control VSI
2567 * @queue: VSI queue number to send the packet to
2568 * @is_add: Add control packet filter if True else remove
2569 * @stats: Structure to hold information on control filter counts
2570 * @cmd_details: pointer to command details structure or NULL
2571 *
2572 * This command will Add or Remove control packet filter for a control VSI.
2573 * In return it will update the total number of perfect filter count in
2574 * the stats member.
2575 **/
2576i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
2577 u8 *mac_addr, u16 ethtype, u16 flags,
2578 u16 vsi_seid, u16 queue, bool is_add,
2579 struct i40e_control_filter_stats *stats,
2580 struct i40e_asq_cmd_details *cmd_details)
2581{
2582 struct i40e_aq_desc desc;
2583 struct i40e_aqc_add_remove_control_packet_filter *cmd =
2584 (struct i40e_aqc_add_remove_control_packet_filter *)
2585 &desc.params.raw;
2586 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
2587 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
2588 &desc.params.raw;
2589 i40e_status status;
2590
2591 if (vsi_seid == 0)
2592 return I40E_ERR_PARAM;
2593
2594 if (is_add) {
2595 i40e_fill_default_direct_cmd_desc(&desc,
2596 i40e_aqc_opc_add_control_packet_filter);
2597 cmd->queue = cpu_to_le16(queue);
2598 } else {
2599 i40e_fill_default_direct_cmd_desc(&desc,
2600 i40e_aqc_opc_remove_control_packet_filter);
2601 }
2602
2603 if (mac_addr)
2604 memcpy(cmd->mac, mac_addr, ETH_ALEN);
2605
2606 cmd->etype = cpu_to_le16(ethtype);
2607 cmd->flags = cpu_to_le16(flags);
2608 cmd->seid = cpu_to_le16(vsi_seid);
2609
2610 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2611
2612 if (!status && stats) {
2613 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
2614 stats->etype_used = le16_to_cpu(resp->etype_used);
2615 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
2616 stats->etype_free = le16_to_cpu(resp->etype_free);
2617 }
2618
2619 return status;
2620}
2621
d4dfb81a
CS		 2622/**
2623 * i40e_set_pci_config_data - store PCI bus info
2624 * @hw: pointer to hardware structure
2625 * @link_status: the link status word from PCI config space
2626 *
2627 * Stores the PCI bus info (speed, width, type) within the i40e_hw structure
2628 **/
2629void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
2630{
2631 hw->bus.type = i40e_bus_type_pci_express;
2632
2633 switch (link_status & PCI_EXP_LNKSTA_NLW) {
2634 case PCI_EXP_LNKSTA_NLW_X1:
2635 hw->bus.width = i40e_bus_width_pcie_x1;
2636 break;
2637 case PCI_EXP_LNKSTA_NLW_X2:
2638 hw->bus.width = i40e_bus_width_pcie_x2;
2639 break;
2640 case PCI_EXP_LNKSTA_NLW_X4:
2641 hw->bus.width = i40e_bus_width_pcie_x4;
2642 break;
2643 case PCI_EXP_LNKSTA_NLW_X8:
2644 hw->bus.width = i40e_bus_width_pcie_x8;
2645 break;
2646 default:
2647 hw->bus.width = i40e_bus_width_unknown;
2648 break;
2649 }
2650
2651 switch (link_status & PCI_EXP_LNKSTA_CLS) {
2652 case PCI_EXP_LNKSTA_CLS_2_5GB:
2653 hw->bus.speed = i40e_bus_speed_2500;
2654 break;
2655 case PCI_EXP_LNKSTA_CLS_5_0GB:
2656 hw->bus.speed = i40e_bus_speed_5000;
2657 break;
2658 case PCI_EXP_LNKSTA_CLS_8_0GB:
2659 hw->bus.speed = i40e_bus_speed_8000;
2660 break;
2661 default:
2662 hw->bus.speed = i40e_bus_speed_unknown;
2663 break;
2664 }
2665}
Linux 6.x block layer and io_uring tree(s)