projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
i40e: don't give up on DCB error after reset
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e.h
CommitLineData
7daa6bf3
JB		 1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
dc641b73 4 * Copyright(c) 2013 - 2014 Intel Corporation.
7daa6bf3
JB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
GR		 15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
7daa6bf3
JB		 17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_H_
28#define _I40E_H_
29
30#include <net/tcp.h>
8144f0f7 31#include <net/udp.h>
7daa6bf3
JB		 32#include <linux/types.h>
33#include <linux/errno.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/aer.h>
37#include <linux/netdevice.h>
38#include <linux/ioport.h>
39#include <linux/slab.h>
40#include <linux/list.h>
41#include <linux/string.h>
42#include <linux/in.h>
43#include <linux/ip.h>
44#include <linux/tcp.h>
45#include <linux/sctp.h>
46#include <linux/pkt_sched.h>
47#include <linux/ipv6.h>
7daa6bf3
JB		 48#include <net/checksum.h>
49#include <net/ip6_checksum.h>
50#include <linux/ethtool.h>
51#include <linux/if_vlan.h>
beb0dff1
JK		 52#include <linux/clocksource.h>
53#include <linux/net_tstamp.h>
54#include <linux/ptp_clock_kernel.h>
7daa6bf3
JB		 55#include "i40e_type.h"
56#include "i40e_prototype.h"
38e00438
VD		 57#ifdef I40E_FCOE
58#include "i40e_fcoe.h"
59#endif
7daa6bf3
JB		 60#include "i40e_virtchnl.h"
61#include "i40e_virtchnl_pf.h"
62#include "i40e_txrx.h"
4e3b35b0 63#include "i40e_dcb.h"
7daa6bf3
JB		 64
65/* Useful i40e defaults */
66#define I40E_BASE_PF_SEID 16
67#define I40E_BASE_VSI_SEID 512
68#define I40E_BASE_VEB_SEID 288
69#define I40E_MAX_VEB 16
70
71#define I40E_MAX_NUM_DESCRIPTORS 4096
a45e88c9 72#define I40E_MAX_REGISTER 0x800000
7daa6bf3
JB		 73#define I40E_DEFAULT_NUM_DESCRIPTORS 512
74#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
75#define I40E_MIN_NUM_DESCRIPTORS 64
76#define I40E_MIN_MSIX 2
77#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
505682cd 78#define I40E_MIN_VSI_ALLOC 51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */
7daa6bf3
JB		 79#define I40E_DEFAULT_QUEUES_PER_VMDQ 2 /* max 16 qps */
80#define I40E_DEFAULT_QUEUES_PER_VF 4
81#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
4e3b35b0 82#define I40E_MAX_QUEUES_PER_TC 64 /* should be a power of 2 */
7daa6bf3
JB		 83#define I40E_FDIR_RING 0
84#define I40E_FDIR_RING_COUNT 32
38e00438
VD		 85#ifdef I40E_FCOE
86#define I40E_DEFAULT_FCOE 8 /* default number of QPs for FCoE */
87#define I40E_MINIMUM_FCOE 1 /* minimum number of QPs for FCoE */
88#endif /* I40E_FCOE */
7daa6bf3 89#define I40E_MAX_AQ_BUF_SIZE 4096
baf73277 90#define I40E_AQ_LEN 128
7daa6bf3
JB		 91#define I40E_AQ_WORK_LIMIT 16
92#define I40E_MAX_USER_PRIORITY 8
93#define I40E_DEFAULT_MSG_ENABLE 4
23527308 94#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
7daa6bf3
JB		 95
96#define I40E_NVM_VERSION_LO_SHIFT 0
fe310704 97#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
ff80301e
JB		 98#define I40E_NVM_VERSION_HI_SHIFT 12
99#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
fe310704
AS		 100
101/* The values in here are decimal coded as hex as is the case in the NVM map*/
102#define I40E_CURRENT_NVM_VERSION_HI 0x2
ff80301e 103#define I40E_CURRENT_NVM_VERSION_LO 0x40
fe310704 104
7daa6bf3
JB		 105/* magic for getting defines into strings */
106#define STRINGIFY(foo) #foo
107#define XSTRINGIFY(bar) STRINGIFY(bar)
108
7daa6bf3
JB		 109#define I40E_RX_DESC(R, i) \
110 ((ring_is_16byte_desc_enabled(R)) \
111 ? (union i40e_32byte_rx_desc *) \
112 (&(((union i40e_16byte_rx_desc *)((R)->desc))[i])) \
113 : (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])))
114#define I40E_TX_DESC(R, i) \
115 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
116#define I40E_TX_CTXTDESC(R, i) \
117 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
118#define I40E_TX_FDIRDESC(R, i) \
119 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
120
121/* default to trying for four seconds */
122#define I40E_TRY_LINK_TIMEOUT (4 * HZ)
123
124/* driver state flags */
125enum i40e_state_t {
126 __I40E_TESTING,
127 __I40E_CONFIG_BUSY,
128 __I40E_CONFIG_DONE,
129 __I40E_DOWN,
130 __I40E_NEEDS_RESTART,
131 __I40E_SERVICE_SCHED,
132 __I40E_ADMINQ_EVENT_PENDING,
133 __I40E_MDD_EVENT_PENDING,
134 __I40E_VFLR_EVENT_PENDING,
135 __I40E_RESET_RECOVERY_PENDING,
136 __I40E_RESET_INTR_RECEIVED,
137 __I40E_REINIT_REQUESTED,
138 __I40E_PF_RESET_REQUESTED,
139 __I40E_CORE_RESET_REQUESTED,
140 __I40E_GLOBAL_RESET_REQUESTED,
7823fe34 141 __I40E_EMP_RESET_REQUESTED,
7daa6bf3 142 __I40E_FILTER_OVERFLOW_PROMISC,
9007bccd 143 __I40E_SUSPENDED,
9ce34f02 144 __I40E_PTP_TX_IN_PROGRESS,
4eb3f768 145 __I40E_BAD_EEPROM,
b5d06f05 146 __I40E_DOWN_REQUESTED,
1e1be8f6 147 __I40E_FD_FLUSH_REQUESTED,
a316f651 148 __I40E_RESET_FAILED,
69129dc3 149 __I40E_PORT_TX_SUSPENDED,
7daa6bf3
JB		 150};
151
152enum i40e_interrupt_policy {
153 I40E_INTERRUPT_BEST_CASE,
154 I40E_INTERRUPT_MEDIUM,
155 I40E_INTERRUPT_LOWEST
156};
157
158struct i40e_lump_tracking {
159 u16 num_entries;
160 u16 search_hint;
161 u16 list[0];
162#define I40E_PILE_VALID_BIT 0x8000
163};
164
165#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
55a5e60b
ASJ		 166#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
167#define I40E_FDIR_BUFFER_FULL_MARGIN 10
12957388 168#define I40E_FDIR_BUFFER_HEAD_ROOM 32
55a5e60b 169
433c47de
ASJ		 170enum i40e_fd_stat_idx {
171 I40E_FD_STAT_ATR,
172 I40E_FD_STAT_SB,
173 I40E_FD_STAT_PF_COUNT
174};
175#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
176#define I40E_FD_ATR_STAT_IDX(pf_id) \
177 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
178#define I40E_FD_SB_STAT_IDX(pf_id) \
179 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
180
17a73f6b
JG		 181struct i40e_fdir_filter {
182 struct hlist_node fdir_node;
183 /* filter ipnut set */
184 u8 flow_type;
185 u8 ip4_proto;
04b73bd7 186 /* TX packet view of src and dst */
17a73f6b
JG		 187 __be32 dst_ip[4];
188 __be32 src_ip[4];
189 __be16 src_port;
190 __be16 dst_port;
191 __be32 sctp_v_tag;
192 /* filter control */
7daa6bf3
JB		 193 u16 q_index;
194 u8 flex_off;
195 u8 pctype;
196 u16 dest_vsi;
197 u8 dest_ctl;
198 u8 fd_status;
199 u16 cnt_index;
200 u32 fd_id;
7daa6bf3
JB		 201};
202
4e3b35b0
NP		 203#define I40E_ETH_P_LLDP 0x88cc
204
7daa6bf3
JB		 205#define I40E_DCB_PRIO_TYPE_STRICT 0
206#define I40E_DCB_PRIO_TYPE_ETS 1
207#define I40E_DCB_STRICT_PRIO_CREDITS 127
208#define I40E_MAX_USER_PRIORITY 8
209/* DCB per TC information data structure */
210struct i40e_tc_info {
211 u16 qoffset; /* Queue offset from base queue */
212 u16 qcount; /* Total Queues */
213 u8 netdev_tc; /* Netdev TC index if netdev associated */
214};
215
216/* TC configuration data structure */
217struct i40e_tc_configuration {
218 u8 numtc; /* Total number of enabled TCs */
219 u8 enabled_tc; /* TC map */
220 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
221};
222
223/* struct that defines the Ethernet device */
224struct i40e_pf {
225 struct pci_dev *pdev;
226 struct i40e_hw hw;
227 unsigned long state;
228 unsigned long link_check_timeout;
229 struct msix_entry *msix_entries;
7daa6bf3
JB		 230 bool fc_autoneg_status;
231
232 u16 eeprom_version;
6c167f58 233 u16 num_vmdq_vsis; /* num vmdq vsis this pf has set up */
7daa6bf3
JB		 234 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
235 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
236 u16 num_req_vfs; /* num vfs requested for this vf */
237 u16 num_vf_qps; /* num queue pairs per vf */
38e00438
VD		 238#ifdef I40E_FCOE
239 u16 num_fcoe_qps; /* num fcoe queues this pf has set up */
240 u16 num_fcoe_msix; /* num queue vectors per fcoe pool */
241#endif /* I40E_FCOE */
7daa6bf3
JB		 242 u16 num_lan_qps; /* num lan queues this pf has set up */
243 u16 num_lan_msix; /* num queue vectors for the base pf vsi */
f8ff1464 244 int queues_left; /* queues left unclaimed */
7daa6bf3
JB		 245 u16 rss_size; /* num queues in the RSS array */
246 u16 rss_size_max; /* HW defined max RSS queues */
247 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
505682cd 248 u16 num_alloc_vsi; /* num VSIs this driver supports */
7daa6bf3 249 u8 atr_sample_rate;
8e2773ae 250 bool wol_en;
7daa6bf3 251
17a73f6b
JG		 252 struct hlist_head fdir_filter_list;
253 u16 fdir_pf_active_filters;
433c47de
ASJ		 254 u16 fd_sb_cnt_idx;
255 u16 fd_atr_cnt_idx;
1e1be8f6 256 unsigned long fd_flush_timestamp;
60793f4a 257 u32 fd_flush_cnt;
1e1be8f6
ASJ		 258 u32 fd_add_err;
259 u32 fd_atr_cnt;
260 u32 fd_tcp_rule;
17a73f6b 261
a1c9a9d9
JK		 262#ifdef CONFIG_I40E_VXLAN
263 __be16 vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
264 u16 pending_vxlan_bitmap;
265
266#endif
7daa6bf3
JB		 267 enum i40e_interrupt_policy int_policy;
268 u16 rx_itr_default;
269 u16 tx_itr_default;
270 u16 msg_enable;
271 char misc_int_name[IFNAMSIZ + 9];
272 u16 adminq_work_limit; /* num of admin receive queue desc to process */
21536717
SN		 273 unsigned long service_timer_period;
274 unsigned long service_timer_previous;
7daa6bf3
JB		 275 struct timer_list service_timer;
276 struct work_struct service_task;
277
278 u64 flags;
279#define I40E_FLAG_RX_CSUM_ENABLED (u64)(1 << 1)
280#define I40E_FLAG_MSI_ENABLED (u64)(1 << 2)
281#define I40E_FLAG_MSIX_ENABLED (u64)(1 << 3)
282#define I40E_FLAG_RX_1BUF_ENABLED (u64)(1 << 4)
283#define I40E_FLAG_RX_PS_ENABLED (u64)(1 << 5)
284#define I40E_FLAG_RSS_ENABLED (u64)(1 << 6)
9f52987b
NP		 285#define I40E_FLAG_VMDQ_ENABLED (u64)(1 << 7)
286#define I40E_FLAG_FDIR_REQUIRES_REINIT (u64)(1 << 8)
287#define I40E_FLAG_NEED_LINK_UPDATE (u64)(1 << 9)
38e00438
VD		 288#ifdef I40E_FCOE
289#define I40E_FLAG_FCOE_ENABLED (u64)(1 << 11)
290#endif /* I40E_FCOE */
9f52987b
NP		 291#define I40E_FLAG_IN_NETPOLL (u64)(1 << 12)
292#define I40E_FLAG_16BYTE_RX_DESC_ENABLED (u64)(1 << 13)
293#define I40E_FLAG_CLEAN_ADMINQ (u64)(1 << 14)
294#define I40E_FLAG_FILTER_SYNC (u64)(1 << 15)
295#define I40E_FLAG_PROCESS_MDD_EVENT (u64)(1 << 17)
296#define I40E_FLAG_PROCESS_VFLR_EVENT (u64)(1 << 18)
297#define I40E_FLAG_SRIOV_ENABLED (u64)(1 << 19)
298#define I40E_FLAG_DCB_ENABLED (u64)(1 << 20)
60ea5f83
JB		 299#define I40E_FLAG_FD_SB_ENABLED (u64)(1 << 21)
300#define I40E_FLAG_FD_ATR_ENABLED (u64)(1 << 22)
beb0dff1 301#define I40E_FLAG_PTP (u64)(1 << 25)
a1c9a9d9
JK		 302#define I40E_FLAG_MFP_ENABLED (u64)(1 << 26)
303#ifdef CONFIG_I40E_VXLAN
304#define I40E_FLAG_VXLAN_FILTER_SYNC (u64)(1 << 27)
305#endif
1f224ad2 306#define I40E_FLAG_PORT_ID_VALID (u64)(1 << 28)
4d9b6043 307#define I40E_FLAG_DCB_CAPABLE (u64)(1 << 29)
7daa6bf3 308
61dade7e
ASJ		 309 /* tracks features that get auto disabled by errors */
310 u64 auto_disable_flags;
311
38e00438
VD		 312#ifdef I40E_FCOE
313 struct i40e_fcoe fcoe;
314
315#endif /* I40E_FCOE */
7daa6bf3
JB		 316 bool stat_offsets_loaded;
317 struct i40e_hw_port_stats stats;
318 struct i40e_hw_port_stats stats_offsets;
319 u32 tx_timeout_count;
320 u32 tx_timeout_recovery_level;
321 unsigned long tx_timeout_last_recovery;
810b3ae4 322 u32 tx_sluggish_count;
7daa6bf3
JB		 323 u32 hw_csum_rx_error;
324 u32 led_status;
325 u16 corer_count; /* Core reset count */
326 u16 globr_count; /* Global reset count */
327 u16 empr_count; /* EMP reset count */
328 u16 pfr_count; /* PF reset count */
cd92e72f 329 u16 sw_int_count; /* SW interrupt count */
7daa6bf3
JB		 330
331 struct mutex switch_mutex;
332 u16 lan_vsi; /* our default LAN VSI */
333 u16 lan_veb; /* initial relay, if exists */
334#define I40E_NO_VEB 0xffff
335#define I40E_NO_VSI 0xffff
336 u16 next_vsi; /* Next unallocated VSI - 0-based! */
337 struct i40e_vsi **vsi;
338 struct i40e_veb *veb[I40E_MAX_VEB];
339
340 struct i40e_lump_tracking *qp_pile;
341 struct i40e_lump_tracking *irq_pile;
342
343 /* switch config info */
344 u16 pf_seid;
345 u16 main_vsi_seid;
346 u16 mac_seid;
7daa6bf3
JB		 347 struct kobject *switch_kobj;
348#ifdef CONFIG_DEBUG_FS
349 struct dentry *i40e_dbg_pf;
350#endif /* CONFIG_DEBUG_FS */
351
93cd765b
ASJ		 352 u16 instance; /* A unique number per i40e_pf instance in the system */
353
7daa6bf3
JB		 354 /* sr-iov config info */
355 struct i40e_vf *vf;
356 int num_alloc_vfs; /* actual number of VFs allocated */
357 u32 vf_aq_requests;
358
359 /* DCBx/DCBNL capability for PF that indicates
360 * whether DCBx is managed by firmware or host
361 * based agent (LLDPAD). Also, indicates what
362 * flavor of DCBx protocol (IEEE/CEE) is supported
363 * by the device. For now we're supporting IEEE
364 * mode only.
365 */
366 u16 dcbx_cap;
367
368 u32 fcoe_hmc_filt_num;
369 u32 fcoe_hmc_cntx_num;
370 struct i40e_filter_control_settings filter_settings;
beb0dff1
JK		 371
372 struct ptp_clock *ptp_clock;
373 struct ptp_clock_info ptp_caps;
374 struct sk_buff *ptp_tx_skb;
beb0dff1 375 struct hwtstamp_config tstamp_config;
beb0dff1
JK		 376 unsigned long last_rx_ptp_check;
377 spinlock_t tmreg_lock; /* Used to protect the device time registers. */
378 u64 ptp_base_adj;
379 u32 tx_hwtstamp_timeouts;
380 u32 rx_hwtstamp_cleared;
381 bool ptp_tx;
382 bool ptp_rx;
e157ea30 383 u16 rss_table_size;
7daa6bf3
JB		 384};
385
386struct i40e_mac_filter {
387 struct list_head list;
388 u8 macaddr[ETH_ALEN];
389#define I40E_VLAN_ANY -1
390 s16 vlan;
391 u8 counter; /* number of instances of this filter */
392 bool is_vf; /* filter belongs to a VF */
393 bool is_netdev; /* filter belongs to a netdev */
394 bool changed; /* filter needs to be sync'd to the HW */
6252c7e4 395 bool is_laa; /* filter is a Locally Administered Address */
7daa6bf3
JB		 396};
397
398struct i40e_veb {
399 struct i40e_pf *pf;
400 u16 idx;
401 u16 veb_idx; /* index of VEB parent */
402 u16 seid;
403 u16 uplink_seid;
404 u16 stats_idx; /* index of VEB parent */
405 u8 enabled_tc;
406 u16 flags;
407 u16 bw_limit;
408 u8 bw_max_quanta;
409 bool is_abs_credits;
410 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
411 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
412 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
413 struct kobject *kobj;
414 bool stat_offsets_loaded;
415 struct i40e_eth_stats stats;
416 struct i40e_eth_stats stats_offsets;
417};
418
419/* struct that defines a VSI, associated with a dev */
420struct i40e_vsi {
421 struct net_device *netdev;
422 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
423 bool netdev_registered;
424 bool stat_offsets_loaded;
425
426 u32 current_netdev_flags;
427 unsigned long state;
428#define I40E_VSI_FLAG_FILTER_CHANGED (1<<0)
429#define I40E_VSI_FLAG_VEB_OWNER (1<<1)
430 unsigned long flags;
431
432 struct list_head mac_filter_list;
433
434 /* VSI stats */
435 struct rtnl_link_stats64 net_stats;
436 struct rtnl_link_stats64 net_stats_offsets;
437 struct i40e_eth_stats eth_stats;
438 struct i40e_eth_stats eth_stats_offsets;
38e00438
VD		 439#ifdef I40E_FCOE
440 struct i40e_fcoe_stats fcoe_stats;
441 struct i40e_fcoe_stats fcoe_stats_offsets;
442 bool fcoe_stat_offsets_loaded;
443#endif
7daa6bf3
JB		 444 u32 tx_restart;
445 u32 tx_busy;
446 u32 rx_buf_failed;
447 u32 rx_page_failed;
448
9f65e15b
AD		 449 /* These are containers of ring pointers, allocated at run-time */
450 struct i40e_ring **rx_rings;
451 struct i40e_ring **tx_rings;
7daa6bf3
JB		 452
453 u16 work_limit;
454 /* high bit set means dynamic, use accessor routines to read/write.
455 * hardware only supports 2us resolution for the ITR registers.
456 * these values always store the USER setting, and must be converted
457 * before programming to a register.
458 */
459 u16 rx_itr_setting;
460 u16 tx_itr_setting;
461
462 u16 max_frame;
463 u16 rx_hdr_len;
464 u16 rx_buf_len;
465 u8 dtype;
466
467 /* List of q_vectors allocated to this VSI */
493fb300 468 struct i40e_q_vector **q_vectors;
7daa6bf3
JB		 469 int num_q_vectors;
470 int base_vector;
63741846 471 bool irqs_ready;
7daa6bf3
JB		 472
473 u16 seid; /* HW index of this VSI (absolute index) */
474 u16 id; /* VSI number */
475 u16 uplink_seid;
476
477 u16 base_queue; /* vsi's first queue in hw array */
478 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
479 u16 num_queue_pairs; /* Used tx and rx pairs */
480 u16 num_desc;
481 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
482 u16 vf_id; /* Virtual function ID for SRIOV VSIs */
483
484 struct i40e_tc_configuration tc_config;
485 struct i40e_aqc_vsi_properties_data info;
486
487 /* VSI BW limit (absolute across all TCs) */
488 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
489 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
490
491 /* Relative TC credits across VSIs */
492 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
493 /* TC BW limit credits within VSI */
494 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
495 /* TC BW limit max quanta within VSI */
496 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
497
498 struct i40e_pf *back; /* Backreference to associated PF */
499 u16 idx; /* index in pf->vsi[] */
500 u16 veb_idx; /* index of VEB parent */
501 struct kobject *kobj; /* sysfs object */
502
503 /* VSI specific handlers */
504 irqreturn_t (*irq_handler)(int irq, void *data);
505} ____cacheline_internodealigned_in_smp;
506
507struct i40e_netdev_priv {
508 struct i40e_vsi *vsi;
509};
510
511/* struct that defines an interrupt vector */
512struct i40e_q_vector {
513 struct i40e_vsi *vsi;
514
515 u16 v_idx; /* index in the vsi->q_vector array. */
516 u16 reg_idx; /* register index of the interrupt */
517
518 struct napi_struct napi;
519
520 struct i40e_ring_container rx;
521 struct i40e_ring_container tx;
522
523 u8 num_ringpairs; /* total number of ring pairs in vector */
524
7daa6bf3 525 cpumask_t affinity_mask;
493fb300
AD		 526 struct rcu_head rcu; /* to avoid race with update stats on free */
527 char name[IFNAMSIZ + 9];
7daa6bf3
JB		 528} ____cacheline_internodealigned_in_smp;
529
530/* lan device */
531struct i40e_device {
532 struct list_head list;
533 struct i40e_pf *pf;
534};
535
536/**
537 * i40e_fw_version_str - format the FW and NVM version strings
538 * @hw: ptr to the hardware info
539 **/
540static inline char *i40e_fw_version_str(struct i40e_hw *hw)
541{
542 static char buf[32];
543
544 snprintf(buf, sizeof(buf),
fe310704 545 "f%d.%d a%d.%d n%02x.%02x e%08x",
7daa6bf3
JB		 546 hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
547 hw->aq.api_maj_ver, hw->aq.api_min_ver,
ff80301e
JB		 548 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
549 I40E_NVM_VERSION_HI_SHIFT,
550 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
551 I40E_NVM_VERSION_LO_SHIFT,
7daa6bf3
JB		 552 hw->nvm.eetrack);
553
554 return buf;
555}
556
557/**
558 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
559 * @netdev: the corresponding netdev
560 *
561 * Return the PF struct for the given netdev
562 **/
563static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
564{
565 struct i40e_netdev_priv *np = netdev_priv(netdev);
566 struct i40e_vsi *vsi = np->vsi;
567
568 return vsi->back;
569}
570
571static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
572 irqreturn_t (*irq_handler)(int, void *))
573{
574 vsi->irq_handler = irq_handler;
575}
576
577/**
578 * i40e_rx_is_programming_status - check for programming status descriptor
579 * @qw: the first quad word of the program status descriptor
580 *
581 * The value of in the descriptor length field indicate if this
582 * is a programming status descriptor for flow director or FCoE
583 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
584 * it is a packet descriptor.
585 **/
586static inline bool i40e_rx_is_programming_status(u64 qw)
587{
588 return I40E_RX_PROG_STATUS_DESC_LENGTH ==
589 (qw >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT);
590}
591
082def10
ASJ		 592/**
593 * i40e_get_fd_cnt_all - get the total FD filter space available
594 * @pf: pointer to the pf struct
595 **/
596static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
597{
598 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
599}
600
7daa6bf3
JB		 601/* needed by i40e_ethtool.c */
602int i40e_up(struct i40e_vsi *vsi);
603void i40e_down(struct i40e_vsi *vsi);
604extern const char i40e_driver_name[];
605extern const char i40e_driver_version_str[];
23326186 606void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
7daa6bf3
JB		 607void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags);
608void i40e_update_stats(struct i40e_vsi *vsi);
609void i40e_update_eth_stats(struct i40e_vsi *vsi);
610struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
611int i40e_fetch_switch_configuration(struct i40e_pf *pf,
612 bool printconfig);
613
17a73f6b 614int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
7daa6bf3 615 struct i40e_pf *pf, bool add);
17a73f6b
JG		 616int i40e_add_del_fdir(struct i40e_vsi *vsi,
617 struct i40e_fdir_filter *input, bool add);
55a5e60b
ASJ		 618void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
619int i40e_get_current_fd_count(struct i40e_pf *pf);
12957388 620int i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
1e1be8f6 621int i40e_get_current_atr_cnt(struct i40e_pf *pf);
7c3c288b 622bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
7daa6bf3
JB		 623void i40e_set_ethtool_ops(struct net_device *netdev);
624struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
625 u8 *macaddr, s16 vlan,
626 bool is_vf, bool is_netdev);
627void i40e_del_filter(struct i40e_vsi *vsi, u8 *macaddr, s16 vlan,
628 bool is_vf, bool is_netdev);
629int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
630struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
631 u16 uplink, u32 param1);
632int i40e_vsi_release(struct i40e_vsi *vsi);
633struct i40e_vsi *i40e_vsi_lookup(struct i40e_pf *pf, enum i40e_vsi_type type,
634 struct i40e_vsi *start_vsi);
38e00438
VD		 635#ifdef I40E_FCOE
636void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
637 struct i40e_vsi_context *ctxt,
638 u8 enabled_tc, bool is_add);
639#endif
fc18eaa0 640int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool enable);
f8ff1464 641int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
7daa6bf3
JB		 642struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
643 u16 downlink_seid, u8 enabled_tc);
644void i40e_veb_release(struct i40e_veb *veb);
645
4e3b35b0 646int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
7daa6bf3
JB		 647i40e_status i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
648void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
649void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
650void i40e_pf_reset_stats(struct i40e_pf *pf);
651#ifdef CONFIG_DEBUG_FS
652void i40e_dbg_pf_init(struct i40e_pf *pf);
653void i40e_dbg_pf_exit(struct i40e_pf *pf);
654void i40e_dbg_init(void);
655void i40e_dbg_exit(void);
656#else
657static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
658static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
659static inline void i40e_dbg_init(void) {}
660static inline void i40e_dbg_exit(void) {}
661#endif /* CONFIG_DEBUG_FS*/
662void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector);
5c2cebda 663void i40e_irq_dynamic_disable(struct i40e_vsi *vsi, int vector);
2ef28cfb 664void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
116a57d4 665void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
38e00438
VD		 666#ifdef I40E_FCOE
667struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
668 struct net_device *netdev,
669 struct rtnl_link_stats64 *storage);
670int i40e_set_mac(struct net_device *netdev, void *p);
671void i40e_set_rx_mode(struct net_device *netdev);
672#endif
7daa6bf3 673int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
38e00438
VD		 674#ifdef I40E_FCOE
675void i40e_tx_timeout(struct net_device *netdev);
676int i40e_vlan_rx_add_vid(struct net_device *netdev,
677 __always_unused __be16 proto, u16 vid);
678int i40e_vlan_rx_kill_vid(struct net_device *netdev,
679 __always_unused __be16 proto, u16 vid);
680#endif
6c167f58 681int i40e_vsi_open(struct i40e_vsi *vsi);
7daa6bf3
JB		 682void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
683int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid);
684int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid);
685struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
686 bool is_vf, bool is_netdev);
687bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
688struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
689 bool is_vf, bool is_netdev);
38e00438
VD		 690#ifdef I40E_FCOE
691int i40e_open(struct net_device *netdev);
692int i40e_close(struct net_device *netdev);
693int i40e_setup_tc(struct net_device *netdev, u8 tc);
694void i40e_netpoll(struct net_device *netdev);
695int i40e_fcoe_enable(struct net_device *netdev);
696int i40e_fcoe_disable(struct net_device *netdev);
697int i40e_fcoe_vsi_init(struct i40e_vsi *vsi, struct i40e_vsi_context *ctxt);
698u8 i40e_get_fcoe_tc_map(struct i40e_pf *pf);
699void i40e_fcoe_config_netdev(struct net_device *netdev, struct i40e_vsi *vsi);
700void i40e_fcoe_vsi_setup(struct i40e_pf *pf);
701int i40e_init_pf_fcoe(struct i40e_pf *pf);
702int i40e_fcoe_setup_ddp_resources(struct i40e_vsi *vsi);
703void i40e_fcoe_free_ddp_resources(struct i40e_vsi *vsi);
704int i40e_fcoe_handle_offload(struct i40e_ring *rx_ring,
705 union i40e_rx_desc *rx_desc,
706 struct sk_buff *skb);
707void i40e_fcoe_handle_status(struct i40e_ring *rx_ring,
708 union i40e_rx_desc *rx_desc, u8 prog_id);
709#endif /* I40E_FCOE */
7daa6bf3 710void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
4e3b35b0
NP		 711#ifdef CONFIG_I40E_DCB
712void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
713 struct i40e_dcbx_config *new_cfg);
714void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
715void i40e_dcbnl_setup(struct i40e_vsi *vsi);
716bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
717 struct i40e_dcbx_config *old_cfg,
718 struct i40e_dcbx_config *new_cfg);
719#endif /* CONFIG_I40E_DCB */
beb0dff1
JK		 720void i40e_ptp_rx_hang(struct i40e_vsi *vsi);
721void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
722void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
723void i40e_ptp_set_increment(struct i40e_pf *pf);
724int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
725int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
726void i40e_ptp_init(struct i40e_pf *pf);
727void i40e_ptp_stop(struct i40e_pf *pf);
7daa6bf3 728#endif /* _I40E_H_ */
Linux 6.x block layer and io_uring tree(s)