i40e: Limiting RSS queues to CPUs
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e.h
CommitLineData
ae06c70b 1/* SPDX-License-Identifier: GPL-2.0 */
51dce24b 2/* Copyright(c) 2013 - 2018 Intel Corporation. */
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3
4#ifndef _I40E_H_
5#define _I40E_H_
6
7#include <net/tcp.h>
8144f0f7 8#include <net/udp.h>
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9#include <linux/types.h>
10#include <linux/errno.h>
11#include <linux/module.h>
12#include <linux/pci.h>
13#include <linux/aer.h>
14#include <linux/netdevice.h>
15#include <linux/ioport.h>
2bc7ee8a 16#include <linux/iommu.h>
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17#include <linux/slab.h>
18#include <linux/list.h>
278e7d0b 19#include <linux/hashtable.h>
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20#include <linux/string.h>
21#include <linux/in.h>
22#include <linux/ip.h>
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23#include <linux/sctp.h>
24#include <linux/pkt_sched.h>
25#include <linux/ipv6.h>
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26#include <net/checksum.h>
27#include <net/ip6_checksum.h>
28#include <linux/ethtool.h>
29#include <linux/if_vlan.h>
51616018 30#include <linux/if_bridge.h>
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31#include <linux/clocksource.h>
32#include <linux/net_tstamp.h>
33#include <linux/ptp_clock_kernel.h>
a9ce82f7 34#include <net/pkt_cls.h>
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35#include <net/tc_act/tc_gact.h>
36#include <net/tc_act/tc_mirred.h>
f3fef2b6 37#include <net/xdp_sock.h>
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38#include "i40e_type.h"
39#include "i40e_prototype.h"
e3219ce6 40#include "i40e_client.h"
55cdfd48 41#include <linux/avf/virtchnl.h>
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42#include "i40e_virtchnl_pf.h"
43#include "i40e_txrx.h"
4e3b35b0 44#include "i40e_dcb.h"
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45
46/* Useful i40e defaults */
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47#define I40E_MAX_VEB 16
48
49#define I40E_MAX_NUM_DESCRIPTORS 4096
50#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
51#define I40E_DEFAULT_NUM_DESCRIPTORS 512
52#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
53#define I40E_MIN_NUM_DESCRIPTORS 64
54#define I40E_MIN_MSIX 2
55#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
7ac4b5c6 56#define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
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57/* max 16 qps */
58#define i40e_default_queues_per_vmdq(pf) \
d36e41dc 59 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
c57c9959 60#define I40E_DEFAULT_QUEUES_PER_VF 4
a3f5aa90 61#define I40E_MAX_VF_QUEUES 16
c57c9959 62#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
e25d00b8 63#define i40e_pf_get_max_q_per_tc(pf) \
d36e41dc 64 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
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65#define I40E_FDIR_RING 0
66#define I40E_FDIR_RING_COUNT 32
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67#define I40E_MAX_AQ_BUF_SIZE 4096
68#define I40E_AQ_LEN 256
69#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
70#define I40E_MAX_USER_PRIORITY 8
ea6acb7e 71#define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
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72#define I40E_DEFAULT_MSG_ENABLE 4
73#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
74#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
7daa6bf3 75
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76#define I40E_NVM_VERSION_LO_SHIFT 0
77#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
78#define I40E_NVM_VERSION_HI_SHIFT 12
79#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
80#define I40E_OEM_VER_BUILD_MASK 0xffff
81#define I40E_OEM_VER_PATCH_MASK 0xff
82#define I40E_OEM_VER_BUILD_SHIFT 8
83#define I40E_OEM_VER_SHIFT 24
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84#define I40E_PHY_DEBUG_ALL \
85 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
86 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
fe310704 87
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88#define I40E_OEM_EETRACK_ID 0xffffffff
89#define I40E_OEM_GEN_SHIFT 24
90#define I40E_OEM_SNAP_MASK 0x00ff0000
91#define I40E_OEM_SNAP_SHIFT 16
92#define I40E_OEM_RELEASE_MASK 0x0000ffff
93
fe310704 94/* The values in here are decimal coded as hex as is the case in the NVM map*/
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95#define I40E_CURRENT_NVM_VERSION_HI 0x2
96#define I40E_CURRENT_NVM_VERSION_LO 0x40
fe310704 97
c57c9959 98#define I40E_RX_DESC(R, i) \
bec60fc4 99 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))
c57c9959 100#define I40E_TX_DESC(R, i) \
7daa6bf3 101 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
c57c9959 102#define I40E_TX_CTXTDESC(R, i) \
7daa6bf3 103 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
c57c9959 104#define I40E_TX_FDIRDESC(R, i) \
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105 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
106
107/* default to trying for four seconds */
c57c9959 108#define I40E_TRY_LINK_TIMEOUT (4 * HZ)
7daa6bf3 109
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110/* BW rate limiting */
111#define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
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112#define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
113#define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
5ecae412 114
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115/* driver state flags */
116enum i40e_state_t {
117 __I40E_TESTING,
118 __I40E_CONFIG_BUSY,
119 __I40E_CONFIG_DONE,
120 __I40E_DOWN,
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121 __I40E_SERVICE_SCHED,
122 __I40E_ADMINQ_EVENT_PENDING,
123 __I40E_MDD_EVENT_PENDING,
124 __I40E_VFLR_EVENT_PENDING,
125 __I40E_RESET_RECOVERY_PENDING,
d5585b7b 126 __I40E_TIMEOUT_RECOVERY_PENDING,
c17401a1 127 __I40E_MISC_IRQ_REQUESTED,
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128 __I40E_RESET_INTR_RECEIVED,
129 __I40E_REINIT_REQUESTED,
130 __I40E_PF_RESET_REQUESTED,
131 __I40E_CORE_RESET_REQUESTED,
132 __I40E_GLOBAL_RESET_REQUESTED,
7823fe34 133 __I40E_EMP_RESET_REQUESTED,
9df42d1a 134 __I40E_EMP_RESET_INTR_RECEIVED,
9007bccd 135 __I40E_SUSPENDED,
9ce34f02 136 __I40E_PTP_TX_IN_PROGRESS,
4eb3f768 137 __I40E_BAD_EEPROM,
b5d06f05 138 __I40E_DOWN_REQUESTED,
1e1be8f6 139 __I40E_FD_FLUSH_REQUESTED,
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140 __I40E_FD_ATR_AUTO_DISABLED,
141 __I40E_FD_SB_AUTO_DISABLED,
a316f651 142 __I40E_RESET_FAILED,
3480756f 143 __I40E_PORT_SUSPENDED,
3ba9bcb4 144 __I40E_VF_DISABLE,
bfe040c3 145 __I40E_MACVLAN_SYNC_PENDING,
41898c66 146 __I40E_UDP_FILTER_SYNC_PENDING,
0605c45c 147 __I40E_TEMP_LINK_POLLING,
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148 __I40E_CLIENT_SERVICE_REQUESTED,
149 __I40E_CLIENT_L2_CHANGE,
150 __I40E_CLIENT_RESET,
f5a7b21b 151 __I40E_VIRTCHNL_OP_PENDING,
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152 /* This must be last as it determines the size of the BITMAP */
153 __I40E_STATE_SIZE__,
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154};
155
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156#define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
157
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158/* VSI state flags */
159enum i40e_vsi_state_t {
160 __I40E_VSI_DOWN,
161 __I40E_VSI_NEEDS_RESTART,
162 __I40E_VSI_SYNCING_FILTERS,
163 __I40E_VSI_OVERFLOW_PROMISC,
164 __I40E_VSI_REINIT_REQUESTED,
165 __I40E_VSI_DOWN_REQUESTED,
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166 /* This must be last as it determines the size of the BITMAP */
167 __I40E_VSI_STATE_SIZE__,
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168};
169
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170enum i40e_interrupt_policy {
171 I40E_INTERRUPT_BEST_CASE,
172 I40E_INTERRUPT_MEDIUM,
173 I40E_INTERRUPT_LOWEST
174};
175
176struct i40e_lump_tracking {
177 u16 num_entries;
178 u16 search_hint;
179 u16 list[0];
180#define I40E_PILE_VALID_BIT 0x8000
e3219ce6 181#define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
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182};
183
184#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
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185#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
186#define I40E_FDIR_BUFFER_FULL_MARGIN 10
12957388 187#define I40E_FDIR_BUFFER_HEAD_ROOM 32
04294e38 188#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
55a5e60b 189
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190#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
191#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
192#define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
b29e13bb 193
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194enum i40e_fd_stat_idx {
195 I40E_FD_STAT_ATR,
196 I40E_FD_STAT_SB,
60ccd45c 197 I40E_FD_STAT_ATR_TUNNEL,
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198 I40E_FD_STAT_PF_COUNT
199};
200#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
201#define I40E_FD_ATR_STAT_IDX(pf_id) \
202 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
203#define I40E_FD_SB_STAT_IDX(pf_id) \
204 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
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205#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
206 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
433c47de 207
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208/* The following structure contains the data parsed from the user-defined
209 * field of the ethtool_rx_flow_spec structure.
210 */
211struct i40e_rx_flow_userdef {
212 bool flex_filter;
213 u16 flex_word;
214 u16 flex_offset;
215};
216
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217struct i40e_fdir_filter {
218 struct hlist_node fdir_node;
219 /* filter ipnut set */
220 u8 flow_type;
221 u8 ip4_proto;
04b73bd7 222 /* TX packet view of src and dst */
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223 __be32 dst_ip;
224 __be32 src_ip;
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225 __be16 src_port;
226 __be16 dst_port;
227 __be32 sctp_v_tag;
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228
229 /* Flexible data to match within the packet payload */
230 __be16 flex_word;
231 u16 flex_offset;
232 bool flex_filter;
233
17a73f6b 234 /* filter control */
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235 u16 q_index;
236 u8 flex_off;
237 u8 pctype;
238 u16 dest_vsi;
239 u8 dest_ctl;
240 u8 fd_status;
241 u16 cnt_index;
242 u32 fd_id;
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243};
244
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245#define I40E_CLOUD_FIELD_OMAC 0x01
246#define I40E_CLOUD_FIELD_IMAC 0x02
247#define I40E_CLOUD_FIELD_IVLAN 0x04
248#define I40E_CLOUD_FIELD_TEN_ID 0x08
249#define I40E_CLOUD_FIELD_IIP 0x10
250
251#define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
252#define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
253#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
254 I40E_CLOUD_FIELD_IVLAN)
255#define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
256 I40E_CLOUD_FIELD_TEN_ID)
257#define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
258 I40E_CLOUD_FIELD_IMAC | \
259 I40E_CLOUD_FIELD_TEN_ID)
260#define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
261 I40E_CLOUD_FIELD_IVLAN | \
262 I40E_CLOUD_FIELD_TEN_ID)
263#define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
264
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AN
265struct i40e_cloud_filter {
266 struct hlist_node cloud_node;
267 unsigned long cookie;
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AN
268 /* cloud filter input set follows */
269 u8 dst_mac[ETH_ALEN];
270 u8 src_mac[ETH_ALEN];
271 __be16 vlan_id;
272 u16 seid; /* filter control */
273 __be16 dst_port;
274 __be16 src_port;
275 u32 tenant_id;
276 union {
277 struct {
278 struct in_addr dst_ip;
279 struct in_addr src_ip;
280 } v4;
281 struct {
282 struct in6_addr dst_ip6;
283 struct in6_addr src_ip6;
284 } v6;
285 } ip;
286#define dst_ipv6 ip.v6.dst_ip6.s6_addr32
287#define src_ipv6 ip.v6.src_ip6.s6_addr32
288#define dst_ipv4 ip.v4.dst_ip.s_addr
289#define src_ipv4 ip.v4.src_ip.s_addr
290 u16 n_proto; /* Ethernet Protocol */
291 u8 ip_proto; /* IPPROTO value */
292 u8 flags;
293#define I40E_CLOUD_TNL_TYPE_NONE 0xff
294 u8 tunnel_type;
aaf66502
AN
295};
296
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NP
297#define I40E_ETH_P_LLDP 0x88cc
298
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299#define I40E_DCB_PRIO_TYPE_STRICT 0
300#define I40E_DCB_PRIO_TYPE_ETS 1
301#define I40E_DCB_STRICT_PRIO_CREDITS 127
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302/* DCB per TC information data structure */
303struct i40e_tc_info {
304 u16 qoffset; /* Queue offset from base queue */
305 u16 qcount; /* Total Queues */
306 u8 netdev_tc; /* Netdev TC index if netdev associated */
307};
308
309/* TC configuration data structure */
310struct i40e_tc_configuration {
311 u8 numtc; /* Total number of enabled TCs */
312 u8 enabled_tc; /* TC map */
313 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
314};
315
5305d0fe 316#define I40E_UDP_PORT_INDEX_UNUSED 255
6a899024 317struct i40e_udp_port_config {
fe0b0cd9 318 /* AdminQ command interface expects port number in Host byte order */
27826fd5 319 u16 port;
6a899024 320 u8 type;
5305d0fe 321 u8 filter_index;
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SA
322};
323
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324/* macros related to FLX_PIT */
325#define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
326 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
327 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
328#define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
329 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
330 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
331#define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
332 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
333 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
334#define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
335 I40E_FLEX_SET_FSIZE(fsize) | \
336 I40E_FLEX_SET_SRC_WORD(src))
337
338#define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \
339 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \
340 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
341#define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \
342 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \
343 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
344#define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \
345 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \
346 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
347
348#define I40E_MAX_FLEX_SRC_OFFSET 0x1F
349
350/* macros related to GLQF_ORT */
351#define I40E_ORT_SET_IDX(idx) (((idx) << \
352 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
353 I40E_GLQF_ORT_PIT_INDX_MASK)
354
355#define I40E_ORT_SET_COUNT(count) (((count) << \
356 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
357 I40E_GLQF_ORT_FIELD_CNT_MASK)
358
359#define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
360 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
361 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
362
363#define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
364 I40E_ORT_SET_COUNT(count) | \
365 I40E_ORT_SET_PAYLOAD(payload))
366
367#define I40E_L3_GLQF_ORT_IDX 34
368#define I40E_L4_GLQF_ORT_IDX 35
369
370/* Flex PIT register index */
371#define I40E_FLEX_PIT_IDX_START_L2 0
372#define I40E_FLEX_PIT_IDX_START_L3 3
373#define I40E_FLEX_PIT_IDX_START_L4 6
374
375#define I40E_FLEX_PIT_TABLE_SIZE 3
376
377#define I40E_FLEX_DEST_UNUSED 63
378
379#define I40E_FLEX_INDEX_ENTRIES 8
380
381/* Flex MASK to disable all flexible entries */
382#define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
383 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
384 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
385 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
386
387struct i40e_flex_pit {
388 struct list_head list;
389 u16 src_offset;
390 u8 pit_index;
391};
392
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AN
393struct i40e_channel {
394 struct list_head list;
395 bool initialized;
396 u8 type;
397 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
398 u16 stat_counter_idx;
399 u16 base_queue;
400 u16 num_queue_pairs; /* Requested by user */
401 u16 seid;
402
403 u8 enabled_tc;
404 struct i40e_aqc_vsi_properties_data info;
405
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AN
406 u64 max_tx_rate;
407
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AN
408 /* track this channel belongs to which VSI */
409 struct i40e_vsi *parent_vsi;
410};
411
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412/* struct that defines the Ethernet device */
413struct i40e_pf {
414 struct pci_dev *pdev;
415 struct i40e_hw hw;
0da36b97 416 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
7daa6bf3 417 struct msix_entry *msix_entries;
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JB
418 bool fc_autoneg_status;
419
420 u16 eeprom_version;
b40c82e6 421 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
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JB
422 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
423 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
ec2f25d2 424 u16 num_req_vfs; /* num VFs requested for this PF */
b40c82e6 425 u16 num_vf_qps; /* num queue pairs per VF */
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JK
426 u16 num_lan_qps; /* num lan queues this PF has set up */
427 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
a70e407f 428 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
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ASJ
429 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
430 int iwarp_base_vector;
f8ff1464 431 int queues_left; /* queues left unclaimed */
acd65448 432 u16 alloc_rss_size; /* allocated RSS queues */
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JB
433 u16 rss_size_max; /* HW defined max RSS queues */
434 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
505682cd 435 u16 num_alloc_vsi; /* num VSIs this driver supports */
7daa6bf3 436 u8 atr_sample_rate;
8e2773ae 437 bool wol_en;
7daa6bf3 438
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JG
439 struct hlist_head fdir_filter_list;
440 u16 fdir_pf_active_filters;
1e1be8f6 441 unsigned long fd_flush_timestamp;
60793f4a 442 u32 fd_flush_cnt;
1e1be8f6
ASJ
443 u32 fd_add_err;
444 u32 fd_atr_cnt;
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JK
445
446 /* Book-keeping of side-band filter count per flow-type.
447 * This is used to detect and handle input set changes for
448 * respective flow-type.
449 */
450 u16 fd_tcp4_filter_cnt;
451 u16 fd_udp4_filter_cnt;
f223c875 452 u16 fd_sctp4_filter_cnt;
097dbf52 453 u16 fd_ip4_filter_cnt;
17a73f6b 454
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JK
455 /* Flexible filter table values that need to be programmed into
456 * hardware, which expects L3 and L4 to be programmed separately. We
457 * need to ensure that the values are in ascended order and don't have
458 * duplicates, so we track each L3 and L4 values in separate lists.
459 */
460 struct list_head l3_flex_pit_list;
461 struct list_head l4_flex_pit_list;
462
6a899024
SA
463 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
464 u16 pending_udp_bitmap;
a1c9a9d9 465
aaf66502
AN
466 struct hlist_head cloud_filter_list;
467 u16 num_cloud_filters;
468
7daa6bf3
JB
469 enum i40e_interrupt_policy int_policy;
470 u16 rx_itr_default;
471 u16 tx_itr_default;
71e6163a 472 u32 msg_enable;
b294ac70 473 char int_name[I40E_INT_NAME_STR_LEN];
7daa6bf3 474 u16 adminq_work_limit; /* num of admin receive queue desc to process */
21536717
SN
475 unsigned long service_timer_period;
476 unsigned long service_timer_previous;
7daa6bf3
JB
477 struct timer_list service_timer;
478 struct work_struct service_task;
479
b74f571f
JK
480 u32 hw_features;
481#define I40E_HW_RSS_AQ_CAPABLE BIT(0)
482#define I40E_HW_128_QP_RSS_CAPABLE BIT(1)
483#define I40E_HW_ATR_EVICT_CAPABLE BIT(2)
484#define I40E_HW_WB_ON_ITR_CAPABLE BIT(3)
485#define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4)
486#define I40E_HW_NO_PCI_LINK_CHECK BIT(5)
487#define I40E_HW_100M_SGMII_CAPABLE BIT(6)
488#define I40E_HW_NO_DCB_SUPPORT BIT(7)
489#define I40E_HW_USE_SET_LLDP_MIB BIT(8)
490#define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9)
491#define I40E_HW_PTP_L4_CAPABLE BIT(10)
492#define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11)
493#define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12)
494#define I40E_HW_HAVE_CRT_RETIMER BIT(13)
495#define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14)
496#define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
497#define I40E_HW_STOP_FW_LLDP BIT(16)
498#define I40E_HW_PORT_ID_VALID BIT(17)
499#define I40E_HW_RESTART_AUTONEG BIT(18)
d36e41dc 500
8f769dd1
JK
501 u32 flags;
502#define I40E_FLAG_RX_CSUM_ENABLED BIT(0)
503#define I40E_FLAG_MSI_ENABLED BIT(1)
504#define I40E_FLAG_MSIX_ENABLED BIT(2)
505#define I40E_FLAG_RSS_ENABLED BIT(3)
506#define I40E_FLAG_VMDQ_ENABLED BIT(4)
507#define I40E_FLAG_SRIOV_ENABLED BIT(5)
508#define I40E_FLAG_DCB_CAPABLE BIT(6)
509#define I40E_FLAG_DCB_ENABLED BIT(7)
510#define I40E_FLAG_FD_SB_ENABLED BIT(8)
511#define I40E_FLAG_FD_ATR_ENABLED BIT(9)
512#define I40E_FLAG_MFP_ENABLED BIT(10)
513#define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11)
514#define I40E_FLAG_VEB_MODE_ENABLED BIT(12)
515#define I40E_FLAG_VEB_STATS_ENABLED BIT(13)
516#define I40E_FLAG_LINK_POLLING_ENABLED BIT(14)
517#define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15)
518#define I40E_FLAG_LEGACY_RX BIT(16)
519#define I40E_FLAG_PTP BIT(17)
520#define I40E_FLAG_IWARP_ENABLED BIT(18)
521#define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19)
522#define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20)
523#define I40E_FLAG_TC_MQPRIO BIT(21)
524#define I40E_FLAG_FD_SB_INACTIVE BIT(22)
525#define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23)
526#define I40E_FLAG_DISABLE_FW_LLDP BIT(24)
7daa6bf3 527
0ef2d5af 528 struct i40e_client_instance *cinst;
7daa6bf3
JB
529 bool stat_offsets_loaded;
530 struct i40e_hw_port_stats stats;
531 struct i40e_hw_port_stats stats_offsets;
532 u32 tx_timeout_count;
533 u32 tx_timeout_recovery_level;
534 unsigned long tx_timeout_last_recovery;
810b3ae4 535 u32 tx_sluggish_count;
7daa6bf3
JB
536 u32 hw_csum_rx_error;
537 u32 led_status;
538 u16 corer_count; /* Core reset count */
539 u16 globr_count; /* Global reset count */
540 u16 empr_count; /* EMP reset count */
541 u16 pfr_count; /* PF reset count */
cd92e72f 542 u16 sw_int_count; /* SW interrupt count */
7daa6bf3
JB
543
544 struct mutex switch_mutex;
545 u16 lan_vsi; /* our default LAN VSI */
546 u16 lan_veb; /* initial relay, if exists */
c57c9959
JK
547#define I40E_NO_VEB 0xffff
548#define I40E_NO_VSI 0xffff
7daa6bf3
JB
549 u16 next_vsi; /* Next unallocated VSI - 0-based! */
550 struct i40e_vsi **vsi;
551 struct i40e_veb *veb[I40E_MAX_VEB];
552
553 struct i40e_lump_tracking *qp_pile;
554 struct i40e_lump_tracking *irq_pile;
555
556 /* switch config info */
557 u16 pf_seid;
558 u16 main_vsi_seid;
559 u16 mac_seid;
7daa6bf3
JB
560 struct kobject *switch_kobj;
561#ifdef CONFIG_DEBUG_FS
562 struct dentry *i40e_dbg_pf;
563#endif /* CONFIG_DEBUG_FS */
92faef85 564 bool cur_promisc;
7daa6bf3 565
93cd765b
ASJ
566 u16 instance; /* A unique number per i40e_pf instance in the system */
567
7daa6bf3
JB
568 /* sr-iov config info */
569 struct i40e_vf *vf;
570 int num_alloc_vfs; /* actual number of VFs allocated */
571 u32 vf_aq_requests;
1d0a4ada 572 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
7daa6bf3
JB
573
574 /* DCBx/DCBNL capability for PF that indicates
575 * whether DCBx is managed by firmware or host
576 * based agent (LLDPAD). Also, indicates what
577 * flavor of DCBx protocol (IEEE/CEE) is supported
578 * by the device. For now we're supporting IEEE
579 * mode only.
580 */
581 u16 dcbx_cap;
582
7daa6bf3 583 struct i40e_filter_control_settings filter_settings;
beb0dff1
JK
584
585 struct ptp_clock *ptp_clock;
586 struct ptp_clock_info ptp_caps;
587 struct sk_buff *ptp_tx_skb;
0bc0706b 588 unsigned long ptp_tx_start;
beb0dff1 589 struct hwtstamp_config tstamp_config;
19551262 590 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
830e0dd9 591 u32 ptp_adj_mult;
beb0dff1 592 u32 tx_hwtstamp_timeouts;
2955faca 593 u32 tx_hwtstamp_skipped;
beb0dff1 594 u32 rx_hwtstamp_cleared;
12490501
JK
595 u32 latch_event_flags;
596 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
597 unsigned long latch_events[4];
beb0dff1
JK
598 bool ptp_tx;
599 bool ptp_rx;
acd65448 600 u16 rss_table_size; /* HW RSS table size */
4fc8c676
SN
601 u32 max_bw;
602 u32 min_bw;
2ac8b675
SN
603
604 u32 ioremap_len;
3487b6c3 605 u32 fd_inv;
31b606d0 606 u16 phy_led_val;
8f88b303
AN
607
608 u16 override_q_count;
2f4b411a
AN
609 u16 last_sw_conf_flags;
610 u16 last_sw_conf_valid_flags;
7daa6bf3
JB
611};
612
278e7d0b
JK
613/**
614 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
615 * @macaddr: the MAC Address as the base key
616 *
617 * Simply copies the address and returns it as a u64 for hashing
618 **/
619static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
620{
621 u64 key = 0;
622
623 ether_addr_copy((u8 *)&key, macaddr);
624 return key;
625}
626
c3c7ea27
MW
627enum i40e_filter_state {
628 I40E_FILTER_INVALID = 0, /* Invalid state */
629 I40E_FILTER_NEW, /* New, not sent to FW yet */
630 I40E_FILTER_ACTIVE, /* Added to switch by FW */
631 I40E_FILTER_FAILED, /* Rejected by FW */
632 I40E_FILTER_REMOVE, /* To be removed */
633/* There is no 'removed' state; the filter struct is freed */
634};
7daa6bf3 635struct i40e_mac_filter {
278e7d0b 636 struct hlist_node hlist;
7daa6bf3
JB
637 u8 macaddr[ETH_ALEN];
638#define I40E_VLAN_ANY -1
639 s16 vlan;
c3c7ea27 640 enum i40e_filter_state state;
7daa6bf3
JB
641};
642
671889e6
JK
643/* Wrapper structure to keep track of filters while we are preparing to send
644 * firmware commands. We cannot send firmware commands while holding a
645 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
646 * a separate structure, which will track the state change and update the real
647 * filter while under lock. We can't simply hold the filters in a separate
648 * list, as this opens a window for a race condition when adding new MAC
649 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
650 */
651struct i40e_new_mac_filter {
652 struct hlist_node hlist;
653 struct i40e_mac_filter *f;
654
655 /* Track future changes to state separately */
656 enum i40e_filter_state state;
657};
658
7daa6bf3
JB
659struct i40e_veb {
660 struct i40e_pf *pf;
661 u16 idx;
c57c9959 662 u16 veb_idx; /* index of VEB parent */
7daa6bf3
JB
663 u16 seid;
664 u16 uplink_seid;
c57c9959 665 u16 stats_idx; /* index of VEB parent */
7daa6bf3 666 u8 enabled_tc;
51616018 667 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
7daa6bf3
JB
668 u16 flags;
669 u16 bw_limit;
670 u8 bw_max_quanta;
671 bool is_abs_credits;
672 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
673 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
674 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
675 struct kobject *kobj;
676 bool stat_offsets_loaded;
677 struct i40e_eth_stats stats;
678 struct i40e_eth_stats stats_offsets;
fe860afb
NP
679 struct i40e_veb_tc_stats tc_stats;
680 struct i40e_veb_tc_stats tc_stats_offsets;
7daa6bf3
JB
681};
682
683/* struct that defines a VSI, associated with a dev */
684struct i40e_vsi {
685 struct net_device *netdev;
686 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
687 bool netdev_registered;
688 bool stat_offsets_loaded;
689
690 u32 current_netdev_flags;
0da36b97 691 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
41a1d04b
JB
692#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
693#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
7daa6bf3
JB
694 unsigned long flags;
695
278e7d0b
JK
696 /* Per VSI lock to protect elements/hash (MAC filter) */
697 spinlock_t mac_filter_hash_lock;
698 /* Fixed size hash table with 2^8 buckets for MAC filters */
699 DECLARE_HASHTABLE(mac_filter_hash, 8);
cbebb85f 700 bool has_vlan_filter;
7daa6bf3
JB
701
702 /* VSI stats */
703 struct rtnl_link_stats64 net_stats;
704 struct rtnl_link_stats64 net_stats_offsets;
705 struct i40e_eth_stats eth_stats;
706 struct i40e_eth_stats eth_stats_offsets;
707 u32 tx_restart;
708 u32 tx_busy;
2fc3d715 709 u64 tx_linearize;
164c9f54 710 u64 tx_force_wb;
7daa6bf3
JB
711 u32 rx_buf_failed;
712 u32 rx_page_failed;
713
9f65e15b
AD
714 /* These are containers of ring pointers, allocated at run-time */
715 struct i40e_ring **rx_rings;
716 struct i40e_ring **tx_rings;
74608d17 717 struct i40e_ring **xdp_rings; /* XDP Tx rings */
7daa6bf3 718
c3c7ea27
MW
719 u32 active_filters;
720 u32 promisc_threshold;
721
7daa6bf3 722 u16 work_limit;
c57c9959
JK
723 u16 int_rate_limit; /* value in usecs */
724
725 u16 rss_table_size; /* HW RSS table size */
726 u16 rss_size; /* Allocated RSS queues */
727 u8 *rss_hkey_user; /* User configured hash keys */
728 u8 *rss_lut_user; /* User configured lookup table entries */
7daa6bf3 729
5db4cb59 730
7daa6bf3 731 u16 max_frame;
7daa6bf3 732 u16 rx_buf_len;
7daa6bf3 733
0c8493d9
BT
734 struct bpf_prog *xdp_prog;
735
7daa6bf3 736 /* List of q_vectors allocated to this VSI */
493fb300 737 struct i40e_q_vector **q_vectors;
7daa6bf3
JB
738 int num_q_vectors;
739 int base_vector;
63741846 740 bool irqs_ready;
7daa6bf3 741
c57c9959
JK
742 u16 seid; /* HW index of this VSI (absolute index) */
743 u16 id; /* VSI number */
7daa6bf3
JB
744 u16 uplink_seid;
745
c57c9959
JK
746 u16 base_queue; /* vsi's first queue in hw array */
747 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
748 u16 req_queue_pairs; /* User requested queue pairs */
749 u16 num_queue_pairs; /* Used tx and rx pairs */
7daa6bf3
JB
750 u16 num_desc;
751 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
a1b5a24f 752 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
7daa6bf3 753
a9ce82f7 754 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
7daa6bf3
JB
755 struct i40e_tc_configuration tc_config;
756 struct i40e_aqc_vsi_properties_data info;
757
758 /* VSI BW limit (absolute across all TCs) */
759 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
760 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
761
762 /* Relative TC credits across VSIs */
763 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
764 /* TC BW limit credits within VSI */
765 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
766 /* TC BW limit max quanta within VSI */
767 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
768
c57c9959
JK
769 struct i40e_pf *back; /* Backreference to associated PF */
770 u16 idx; /* index in pf->vsi[] */
771 u16 veb_idx; /* index of VEB parent */
772 struct kobject *kobj; /* sysfs object */
773 bool current_isup; /* Sync 'link up' logging */
7ec9ba11 774 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
7daa6bf3 775
8f88b303
AN
776 /* channel specific fields */
777 u16 cnt_q_avail; /* num of queues available for channel usage */
778 u16 orig_rss_size;
779 u16 current_rss_size;
a9ce82f7 780 bool reconfig_rss;
8f88b303
AN
781
782 u16 next_base_queue; /* next queue to be used for channel setup */
783
784 struct list_head ch_list;
aa5cb02a 785 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
8f88b303 786
e3219ce6
ASJ
787 void *priv; /* client driver data reference. */
788
7daa6bf3
JB
789 /* VSI specific handlers */
790 irqreturn_t (*irq_handler)(int irq, void *data);
791} ____cacheline_internodealigned_in_smp;
792
793struct i40e_netdev_priv {
794 struct i40e_vsi *vsi;
795};
796
797/* struct that defines an interrupt vector */
798struct i40e_q_vector {
799 struct i40e_vsi *vsi;
800
801 u16 v_idx; /* index in the vsi->q_vector array. */
802 u16 reg_idx; /* register index of the interrupt */
803
804 struct napi_struct napi;
805
806 struct i40e_ring_container rx;
807 struct i40e_ring_container tx;
808
a0073a4b 809 u8 itr_countdown; /* when 0 should adjust adaptive ITR */
7daa6bf3
JB
810 u8 num_ringpairs; /* total number of ring pairs in vector */
811
7daa6bf3 812 cpumask_t affinity_mask;
96db776a
AB
813 struct irq_affinity_notify affinity_notify;
814
493fb300 815 struct rcu_head rcu; /* to avoid race with update stats on free */
b294ac70 816 char name[I40E_INT_NAME_STR_LEN];
8e0764b4 817 bool arm_wb_state;
7daa6bf3
JB
818} ____cacheline_internodealigned_in_smp;
819
820/* lan device */
821struct i40e_device {
822 struct list_head list;
823 struct i40e_pf *pf;
824};
825
826/**
6dec1017 827 * i40e_nvm_version_str - format the NVM version strings
7daa6bf3
JB
828 * @hw: ptr to the hardware info
829 **/
6dec1017 830static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
7daa6bf3
JB
831{
832 static char buf[32];
2efaad86 833 u32 full_ver;
2efaad86
CW
834
835 full_ver = hw->nvm.oem_ver;
5bbb2e20
FS
836
837 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
838 u8 gen, snap;
839 u16 release;
840
841 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
842 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
843 I40E_OEM_SNAP_SHIFT);
844 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
845
846 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
847 } else {
848 u8 ver, patch;
849 u16 build;
850
851 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
852 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
853 I40E_OEM_VER_BUILD_MASK);
854 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
855
856 snprintf(buf, sizeof(buf),
857 "%x.%02x 0x%x %d.%d.%d",
858 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
859 I40E_NVM_VERSION_HI_SHIFT,
860 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
861 I40E_NVM_VERSION_LO_SHIFT,
862 hw->nvm.eetrack, ver, build, patch);
863 }
7daa6bf3
JB
864
865 return buf;
866}
867
868/**
869 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
870 * @netdev: the corresponding netdev
871 *
872 * Return the PF struct for the given netdev
873 **/
874static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
875{
876 struct i40e_netdev_priv *np = netdev_priv(netdev);
877 struct i40e_vsi *vsi = np->vsi;
878
879 return vsi->back;
880}
881
882static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
883 irqreturn_t (*irq_handler)(int, void *))
884{
885 vsi->irq_handler = irq_handler;
886}
887
082def10
ASJ
888/**
889 * i40e_get_fd_cnt_all - get the total FD filter space available
b40c82e6 890 * @pf: pointer to the PF struct
082def10
ASJ
891 **/
892static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
893{
894 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
895}
896
36777d9f
JK
897/**
898 * i40e_read_fd_input_set - reads value of flow director input set register
899 * @pf: pointer to the PF struct
900 * @addr: register addr
901 *
902 * This function reads value of flow director input set register
903 * specified by 'addr' (which is specific to flow-type)
904 **/
905static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
906{
907 u64 val;
908
909 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
910 val <<= 32;
911 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
912
913 return val;
914}
915
3bcee1e6
JK
916/**
917 * i40e_write_fd_input_set - writes value into flow director input set register
918 * @pf: pointer to the PF struct
919 * @addr: register addr
920 * @val: value to be written
921 *
922 * This function writes specified value to the register specified by 'addr'.
923 * This register is input set register based on flow-type.
924 **/
925static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
926 u16 addr, u64 val)
927{
928 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
929 (u32)(val >> 32));
930 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
931 (u32)(val & 0xFFFFFFFFULL));
932}
933
7daa6bf3
JB
934/* needed by i40e_ethtool.c */
935int i40e_up(struct i40e_vsi *vsi);
936void i40e_down(struct i40e_vsi *vsi);
937extern const char i40e_driver_name[];
938extern const char i40e_driver_version_str[];
23326186 939void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
373149fc 940void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
043dd650
HZ
941int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
942int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
f1582351
AB
943void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
944 u16 rss_table_size, u16 rss_size);
fdf0e0bf 945struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
4b816446
AD
946/**
947 * i40e_find_vsi_by_type - Find and return Flow Director VSI
948 * @pf: PF to search for VSI
949 * @type: Value indicating type of VSI we are looking for
950 **/
951static inline struct i40e_vsi *
952i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
953{
954 int i;
955
956 for (i = 0; i < pf->num_alloc_vsi; i++) {
957 struct i40e_vsi *vsi = pf->vsi[i];
958
959 if (vsi && vsi->type == type)
960 return vsi;
961 }
962
963 return NULL;
964}
7daa6bf3
JB
965void i40e_update_stats(struct i40e_vsi *vsi);
966void i40e_update_eth_stats(struct i40e_vsi *vsi);
967struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
968int i40e_fetch_switch_configuration(struct i40e_pf *pf,
969 bool printconfig);
970
17a73f6b
JG
971int i40e_add_del_fdir(struct i40e_vsi *vsi,
972 struct i40e_fdir_filter *input, bool add);
55a5e60b 973void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
04294e38
ASJ
974u32 i40e_get_current_fd_count(struct i40e_pf *pf);
975u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
976u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
977u32 i40e_get_global_fd_count(struct i40e_pf *pf);
7c3c288b 978bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
7daa6bf3
JB
979void i40e_set_ethtool_ops(struct net_device *netdev);
980struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
6622f5cd 981 const u8 *macaddr, s16 vlan);
148141bb 982void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
6622f5cd 983void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
17652c63 984int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
7daa6bf3
JB
985struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
986 u16 uplink, u32 param1);
987int i40e_vsi_release(struct i40e_vsi *vsi);
e3219ce6
ASJ
988void i40e_service_event_schedule(struct i40e_pf *pf);
989void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
990 u8 *msg, u16 len);
991
d0fda04d
HR
992int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
993 bool enable);
994int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
3aa7b74d
FS
995int i40e_vsi_start_rings(struct i40e_vsi *vsi);
996void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
e4b433f4
JK
997void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
998int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
f8ff1464 999int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
7daa6bf3
JB
1000struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1001 u16 downlink_seid, u8 enabled_tc);
1002void i40e_veb_release(struct i40e_veb *veb);
1003
4e3b35b0 1004int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
4eeb1fff 1005int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
7daa6bf3
JB
1006void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1007void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1008void i40e_pf_reset_stats(struct i40e_pf *pf);
1009#ifdef CONFIG_DEBUG_FS
1010void i40e_dbg_pf_init(struct i40e_pf *pf);
1011void i40e_dbg_pf_exit(struct i40e_pf *pf);
1012void i40e_dbg_init(void);
1013void i40e_dbg_exit(void);
1014#else
1015static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
1016static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
1017static inline void i40e_dbg_init(void) {}
1018static inline void i40e_dbg_exit(void) {}
1019#endif /* CONFIG_DEBUG_FS*/
e3219ce6
ASJ
1020/* needed by client drivers */
1021int i40e_lan_add_device(struct i40e_pf *pf);
1022int i40e_lan_del_device(struct i40e_pf *pf);
1023void i40e_client_subtask(struct i40e_pf *pf);
1024void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
e3219ce6
ASJ
1025void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1026void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1027void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
ddbb8d5d 1028void i40e_client_update_msix_info(struct i40e_pf *pf);
0ef2d5af 1029int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
02d109be
JB
1030/**
1031 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1032 * @vsi: pointer to a vsi
1033 * @vector: enable a particular Hw Interrupt vector, without base_vector
1034 **/
1035static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1036{
1037 struct i40e_pf *pf = vsi->back;
1038 struct i40e_hw *hw = &pf->hw;
1039 u32 val;
1040
1041 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1042 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1043 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1044 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1045 /* skip the flush */
1046}
1047
2ef28cfb 1048void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
dbadbbe2 1049void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
7daa6bf3 1050int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
96664483 1051int i40e_open(struct net_device *netdev);
08ca3874 1052int i40e_close(struct net_device *netdev);
6c167f58 1053int i40e_vsi_open(struct i40e_vsi *vsi);
7daa6bf3 1054void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
9af52f60 1055int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
f94484b7 1056int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
9af52f60 1057void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
f94484b7 1058void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
feffdbe4
JK
1059struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1060 const u8 *macaddr);
1061int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
7daa6bf3 1062bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
6622f5cd 1063struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
7daa6bf3 1064void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
4e3b35b0
NP
1065#ifdef CONFIG_I40E_DCB
1066void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
750fcbcf 1067 struct i40e_dcbx_config *old_cfg,
4e3b35b0
NP
1068 struct i40e_dcbx_config *new_cfg);
1069void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1070void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1071bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1072 struct i40e_dcbx_config *old_cfg,
1073 struct i40e_dcbx_config *new_cfg);
1074#endif /* CONFIG_I40E_DCB */
61189556 1075void i40e_ptp_rx_hang(struct i40e_pf *pf);
0bc0706b 1076void i40e_ptp_tx_hang(struct i40e_pf *pf);
beb0dff1
JK
1077void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1078void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1079void i40e_ptp_set_increment(struct i40e_pf *pf);
1080int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1081int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1082void i40e_ptp_init(struct i40e_pf *pf);
1083void i40e_ptp_stop(struct i40e_pf *pf);
51616018 1084int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
4fc8c676
SN
1085i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1086i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1087i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
c156f856 1088void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
0c8493d9
BT
1089
1090static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1091{
1092 return !!vsi->xdp_prog;
1093}
8f88b303 1094
0a714186
BT
1095static inline struct xdp_umem *i40e_xsk_umem(struct i40e_ring *ring)
1096{
1097 bool xdp_on = i40e_enabled_xdp_vsi(ring->vsi);
1098 int qid = ring->queue_index;
1099
1100 if (ring_is_xdp(ring))
1101 qid -= ring->vsi->alloc_queue_pairs;
1102
f3fef2b6 1103 if (!xdp_on)
0a714186
BT
1104 return NULL;
1105
f3fef2b6 1106 return xdp_get_umem_from_qid(ring->vsi->netdev, qid);
0a714186
BT
1107}
1108
8f88b303 1109int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
5ecae412 1110int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
e284fc28
AD
1111int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1112 struct i40e_cloud_filter *filter,
1113 bool add);
1114int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1115 struct i40e_cloud_filter *filter,
1116 bool add);
7daa6bf3 1117#endif /* _I40E_H_ */