Merge branch 'tcp-udp-misc'
[linux-2.6-block.git] / drivers / net / ethernet / intel / i40e / i40e.h
CommitLineData
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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
40d72a50 4 * Copyright(c) 2013 - 2016 Intel Corporation.
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5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
dc641b73
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15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
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17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_H_
28#define _I40E_H_
29
30#include <net/tcp.h>
8144f0f7 31#include <net/udp.h>
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32#include <linux/types.h>
33#include <linux/errno.h>
34#include <linux/module.h>
35#include <linux/pci.h>
36#include <linux/aer.h>
37#include <linux/netdevice.h>
38#include <linux/ioport.h>
2bc7ee8a 39#include <linux/iommu.h>
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40#include <linux/slab.h>
41#include <linux/list.h>
42#include <linux/string.h>
43#include <linux/in.h>
44#include <linux/ip.h>
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45#include <linux/sctp.h>
46#include <linux/pkt_sched.h>
47#include <linux/ipv6.h>
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48#include <net/checksum.h>
49#include <net/ip6_checksum.h>
50#include <linux/ethtool.h>
51#include <linux/if_vlan.h>
51616018 52#include <linux/if_bridge.h>
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53#include <linux/clocksource.h>
54#include <linux/net_tstamp.h>
55#include <linux/ptp_clock_kernel.h>
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56#include "i40e_type.h"
57#include "i40e_prototype.h"
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58#ifdef I40E_FCOE
59#include "i40e_fcoe.h"
60#endif
e3219ce6 61#include "i40e_client.h"
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62#include "i40e_virtchnl.h"
63#include "i40e_virtchnl_pf.h"
64#include "i40e_txrx.h"
4e3b35b0 65#include "i40e_dcb.h"
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66
67/* Useful i40e defaults */
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68#define I40E_MAX_VEB 16
69
70#define I40E_MAX_NUM_DESCRIPTORS 4096
232f4706 71#define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
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72#define I40E_DEFAULT_NUM_DESCRIPTORS 512
73#define I40E_REQ_DESCRIPTOR_MULTIPLE 32
74#define I40E_MIN_NUM_DESCRIPTORS 64
75#define I40E_MIN_MSIX 2
76#define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
505682cd 77#define I40E_MIN_VSI_ALLOC 51 /* LAN, ATR, FCOE, 32 VF, 16 VMDQ */
e25d00b8
ASJ
78/* max 16 qps */
79#define i40e_default_queues_per_vmdq(pf) \
80 (((pf)->flags & I40E_FLAG_RSS_AQ_CAPABLE) ? 4 : 1)
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81#define I40E_DEFAULT_QUEUES_PER_VF 4
82#define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
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83#define i40e_pf_get_max_q_per_tc(pf) \
84 (((pf)->flags & I40E_FLAG_128_QP_RSS_CAPABLE) ? 128 : 64)
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85#define I40E_FDIR_RING 0
86#define I40E_FDIR_RING_COUNT 32
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87#ifdef I40E_FCOE
88#define I40E_DEFAULT_FCOE 8 /* default number of QPs for FCoE */
89#define I40E_MINIMUM_FCOE 1 /* minimum number of QPs for FCoE */
90#endif /* I40E_FCOE */
7daa6bf3 91#define I40E_MAX_AQ_BUF_SIZE 4096
07574897 92#define I40E_AQ_LEN 256
628f096d 93#define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
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94#define I40E_MAX_USER_PRIORITY 8
95#define I40E_DEFAULT_MSG_ENABLE 4
23527308 96#define I40E_QUEUE_WAIT_RETRY_LIMIT 10
fba52e21 97#define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
7daa6bf3 98
7e45ab44 99/* Ethtool Private Flags */
41a1d04b 100#define I40E_PRIV_FLAGS_NPAR_FLAG BIT(0)
9ac77266 101#define I40E_PRIV_FLAGS_LINKPOLL_FLAG BIT(1)
ef17178c 102#define I40E_PRIV_FLAGS_FD_ATR BIT(2)
1cdfd88f 103#define I40E_PRIV_FLAGS_VEB_STATS BIT(3)
827de392 104#define I40E_PRIV_FLAGS_PS BIT(4)
72b74869 105#define I40E_PRIV_FLAGS_HW_ATR_EVICT BIT(5)
7e45ab44 106
7daa6bf3 107#define I40E_NVM_VERSION_LO_SHIFT 0
fe310704 108#define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
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109#define I40E_NVM_VERSION_HI_SHIFT 12
110#define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
2efaad86 111#define I40E_OEM_VER_BUILD_MASK 0xffff
f0b44440 112#define I40E_OEM_VER_PATCH_MASK 0xff
2efaad86
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113#define I40E_OEM_VER_BUILD_SHIFT 8
114#define I40E_OEM_VER_SHIFT 24
31b606d0 115#define I40E_PHY_DEBUG_PORT BIT(4)
fe310704
AS
116
117/* The values in here are decimal coded as hex as is the case in the NVM map*/
118#define I40E_CURRENT_NVM_VERSION_HI 0x2
ff80301e 119#define I40E_CURRENT_NVM_VERSION_LO 0x40
fe310704 120
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121/* magic for getting defines into strings */
122#define STRINGIFY(foo) #foo
123#define XSTRINGIFY(bar) STRINGIFY(bar)
124
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125#define I40E_RX_DESC(R, i) \
126 ((ring_is_16byte_desc_enabled(R)) \
127 ? (union i40e_32byte_rx_desc *) \
128 (&(((union i40e_16byte_rx_desc *)((R)->desc))[i])) \
129 : (&(((union i40e_32byte_rx_desc *)((R)->desc))[i])))
130#define I40E_TX_DESC(R, i) \
131 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
132#define I40E_TX_CTXTDESC(R, i) \
133 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
134#define I40E_TX_FDIRDESC(R, i) \
135 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
136
137/* default to trying for four seconds */
138#define I40E_TRY_LINK_TIMEOUT (4 * HZ)
139
f1bbad33
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140/**
141 * i40e_is_mac_710 - Return true if MAC is X710/XL710
142 * @hw: ptr to the hardware info
143 **/
144static inline bool i40e_is_mac_710(struct i40e_hw *hw)
145{
146 if ((hw->mac.type == I40E_MAC_X710) ||
147 (hw->mac.type == I40E_MAC_XL710))
148 return true;
149
150 return false;
151}
152
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153/* driver state flags */
154enum i40e_state_t {
155 __I40E_TESTING,
156 __I40E_CONFIG_BUSY,
157 __I40E_CONFIG_DONE,
158 __I40E_DOWN,
159 __I40E_NEEDS_RESTART,
160 __I40E_SERVICE_SCHED,
161 __I40E_ADMINQ_EVENT_PENDING,
162 __I40E_MDD_EVENT_PENDING,
163 __I40E_VFLR_EVENT_PENDING,
164 __I40E_RESET_RECOVERY_PENDING,
165 __I40E_RESET_INTR_RECEIVED,
166 __I40E_REINIT_REQUESTED,
167 __I40E_PF_RESET_REQUESTED,
168 __I40E_CORE_RESET_REQUESTED,
169 __I40E_GLOBAL_RESET_REQUESTED,
7823fe34 170 __I40E_EMP_RESET_REQUESTED,
9df42d1a 171 __I40E_EMP_RESET_INTR_RECEIVED,
7daa6bf3 172 __I40E_FILTER_OVERFLOW_PROMISC,
9007bccd 173 __I40E_SUSPENDED,
9ce34f02 174 __I40E_PTP_TX_IN_PROGRESS,
4eb3f768 175 __I40E_BAD_EEPROM,
b5d06f05 176 __I40E_DOWN_REQUESTED,
1e1be8f6 177 __I40E_FD_FLUSH_REQUESTED,
a316f651 178 __I40E_RESET_FAILED,
69129dc3 179 __I40E_PORT_TX_SUSPENDED,
3ba9bcb4 180 __I40E_VF_DISABLE,
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181};
182
183enum i40e_interrupt_policy {
184 I40E_INTERRUPT_BEST_CASE,
185 I40E_INTERRUPT_MEDIUM,
186 I40E_INTERRUPT_LOWEST
187};
188
189struct i40e_lump_tracking {
190 u16 num_entries;
191 u16 search_hint;
192 u16 list[0];
193#define I40E_PILE_VALID_BIT 0x8000
e3219ce6 194#define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
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195};
196
197#define I40E_DEFAULT_ATR_SAMPLE_RATE 20
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198#define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
199#define I40E_FDIR_BUFFER_FULL_MARGIN 10
12957388 200#define I40E_FDIR_BUFFER_HEAD_ROOM 32
04294e38 201#define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
55a5e60b 202
b29e13bb 203#define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
e69ff813 204#define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
b29e13bb 205
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206enum i40e_fd_stat_idx {
207 I40E_FD_STAT_ATR,
208 I40E_FD_STAT_SB,
60ccd45c 209 I40E_FD_STAT_ATR_TUNNEL,
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210 I40E_FD_STAT_PF_COUNT
211};
212#define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
213#define I40E_FD_ATR_STAT_IDX(pf_id) \
214 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
215#define I40E_FD_SB_STAT_IDX(pf_id) \
216 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
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217#define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
218 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
433c47de 219
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JG
220struct i40e_fdir_filter {
221 struct hlist_node fdir_node;
222 /* filter ipnut set */
223 u8 flow_type;
224 u8 ip4_proto;
04b73bd7 225 /* TX packet view of src and dst */
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JG
226 __be32 dst_ip[4];
227 __be32 src_ip[4];
228 __be16 src_port;
229 __be16 dst_port;
230 __be32 sctp_v_tag;
231 /* filter control */
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232 u16 q_index;
233 u8 flex_off;
234 u8 pctype;
235 u16 dest_vsi;
236 u8 dest_ctl;
237 u8 fd_status;
238 u16 cnt_index;
239 u32 fd_id;
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240};
241
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242#define I40E_ETH_P_LLDP 0x88cc
243
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244#define I40E_DCB_PRIO_TYPE_STRICT 0
245#define I40E_DCB_PRIO_TYPE_ETS 1
246#define I40E_DCB_STRICT_PRIO_CREDITS 127
247#define I40E_MAX_USER_PRIORITY 8
248/* DCB per TC information data structure */
249struct i40e_tc_info {
250 u16 qoffset; /* Queue offset from base queue */
251 u16 qcount; /* Total Queues */
252 u8 netdev_tc; /* Netdev TC index if netdev associated */
253};
254
255/* TC configuration data structure */
256struct i40e_tc_configuration {
257 u8 numtc; /* Total number of enabled TCs */
258 u8 enabled_tc; /* TC map */
259 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
260};
261
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262struct i40e_udp_port_config {
263 __be16 index;
264 u8 type;
265};
266
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267/* struct that defines the Ethernet device */
268struct i40e_pf {
269 struct pci_dev *pdev;
270 struct i40e_hw hw;
271 unsigned long state;
7daa6bf3 272 struct msix_entry *msix_entries;
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273 bool fc_autoneg_status;
274
275 u16 eeprom_version;
b40c82e6 276 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
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277 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
278 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
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279 u16 num_req_vfs; /* num VFs requested for this VF */
280 u16 num_vf_qps; /* num queue pairs per VF */
38e00438 281#ifdef I40E_FCOE
b40c82e6 282 u16 num_fcoe_qps; /* num fcoe queues this PF has set up */
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283 u16 num_fcoe_msix; /* num queue vectors per fcoe pool */
284#endif /* I40E_FCOE */
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285 u16 num_lan_qps; /* num lan queues this PF has set up */
286 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
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287 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
288 int iwarp_base_vector;
f8ff1464 289 int queues_left; /* queues left unclaimed */
acd65448 290 u16 alloc_rss_size; /* allocated RSS queues */
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291 u16 rss_size_max; /* HW defined max RSS queues */
292 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
505682cd 293 u16 num_alloc_vsi; /* num VSIs this driver supports */
7daa6bf3 294 u8 atr_sample_rate;
8e2773ae 295 bool wol_en;
7daa6bf3 296
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297 struct hlist_head fdir_filter_list;
298 u16 fdir_pf_active_filters;
1e1be8f6 299 unsigned long fd_flush_timestamp;
60793f4a 300 u32 fd_flush_cnt;
1e1be8f6
ASJ
301 u32 fd_add_err;
302 u32 fd_atr_cnt;
303 u32 fd_tcp_rule;
17a73f6b 304
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305 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
306 u16 pending_udp_bitmap;
a1c9a9d9 307
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308 enum i40e_interrupt_policy int_policy;
309 u16 rx_itr_default;
310 u16 tx_itr_default;
71e6163a 311 u32 msg_enable;
b294ac70 312 char int_name[I40E_INT_NAME_STR_LEN];
7daa6bf3 313 u16 adminq_work_limit; /* num of admin receive queue desc to process */
21536717
SN
314 unsigned long service_timer_period;
315 unsigned long service_timer_previous;
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316 struct timer_list service_timer;
317 struct work_struct service_task;
318
319 u64 flags;
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JB
320#define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)
321#define I40E_FLAG_MSI_ENABLED BIT_ULL(2)
322#define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)
323#define I40E_FLAG_RX_1BUF_ENABLED BIT_ULL(4)
324#define I40E_FLAG_RX_PS_ENABLED BIT_ULL(5)
325#define I40E_FLAG_RSS_ENABLED BIT_ULL(6)
326#define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
327#define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)
328#define I40E_FLAG_NEED_LINK_UPDATE BIT_ULL(9)
d502ce01 329#define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)
38e00438 330#ifdef I40E_FCOE
41a1d04b 331#define I40E_FLAG_FCOE_ENABLED BIT_ULL(11)
38e00438 332#endif /* I40E_FCOE */
41a1d04b
JB
333#define I40E_FLAG_16BYTE_RX_DESC_ENABLED BIT_ULL(13)
334#define I40E_FLAG_CLEAN_ADMINQ BIT_ULL(14)
335#define I40E_FLAG_FILTER_SYNC BIT_ULL(15)
e3219ce6 336#define I40E_FLAG_SERVICE_CLIENT_REQUESTED BIT_ULL(16)
41a1d04b
JB
337#define I40E_FLAG_PROCESS_MDD_EVENT BIT_ULL(17)
338#define I40E_FLAG_PROCESS_VFLR_EVENT BIT_ULL(18)
339#define I40E_FLAG_SRIOV_ENABLED BIT_ULL(19)
340#define I40E_FLAG_DCB_ENABLED BIT_ULL(20)
341#define I40E_FLAG_FD_SB_ENABLED BIT_ULL(21)
342#define I40E_FLAG_FD_ATR_ENABLED BIT_ULL(22)
343#define I40E_FLAG_PTP BIT_ULL(25)
344#define I40E_FLAG_MFP_ENABLED BIT_ULL(26)
6a899024 345#define I40E_FLAG_UDP_FILTER_SYNC BIT_ULL(27)
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346#define I40E_FLAG_PORT_ID_VALID BIT_ULL(28)
347#define I40E_FLAG_DCB_CAPABLE BIT_ULL(29)
d502ce01
ASJ
348#define I40E_FLAG_RSS_AQ_CAPABLE BIT_ULL(31)
349#define I40E_FLAG_HW_ATR_EVICT_CAPABLE BIT_ULL(32)
350#define I40E_FLAG_OUTER_UDP_CSUM_CAPABLE BIT_ULL(33)
351#define I40E_FLAG_128_QP_RSS_CAPABLE BIT_ULL(34)
352#define I40E_FLAG_WB_ON_ITR_CAPABLE BIT_ULL(35)
d1a8d275 353#define I40E_FLAG_VEB_STATS_ENABLED BIT_ULL(37)
d502ce01 354#define I40E_FLAG_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT_ULL(38)
9ac77266 355#define I40E_FLAG_LINK_POLLING_ENABLED BIT_ULL(39)
fc60861e 356#define I40E_FLAG_VEB_MODE_ENABLED BIT_ULL(40)
6a899024 357#define I40E_FLAG_GENEVE_OFFLOAD_CAPABLE BIT_ULL(41)
3fced535 358#define I40E_FLAG_NO_PCI_LINK_CHECK BIT_ULL(42)
48b1804e 359#define I40E_FLAG_100M_SGMII_CAPABLE BIT_ULL(43)
8eed76fa 360#define I40E_FLAG_RESTART_AUTONEG BIT_ULL(44)
f1bbad33
NP
361#define I40E_FLAG_NO_DCB_SUPPORT BIT_ULL(45)
362#define I40E_FLAG_USE_SET_LLDP_MIB BIT_ULL(46)
363#define I40E_FLAG_STOP_FW_LLDP BIT_ULL(47)
31b606d0 364#define I40E_FLAG_HAVE_10GBASET_PHY BIT_ULL(48)
b499ffb0 365#define I40E_FLAG_PF_MAC BIT_ULL(50)
7daa6bf3 366
61dade7e
ASJ
367 /* tracks features that get auto disabled by errors */
368 u64 auto_disable_flags;
369
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VD
370#ifdef I40E_FCOE
371 struct i40e_fcoe fcoe;
372
373#endif /* I40E_FCOE */
7daa6bf3
JB
374 bool stat_offsets_loaded;
375 struct i40e_hw_port_stats stats;
376 struct i40e_hw_port_stats stats_offsets;
377 u32 tx_timeout_count;
378 u32 tx_timeout_recovery_level;
379 unsigned long tx_timeout_last_recovery;
810b3ae4 380 u32 tx_sluggish_count;
7daa6bf3
JB
381 u32 hw_csum_rx_error;
382 u32 led_status;
383 u16 corer_count; /* Core reset count */
384 u16 globr_count; /* Global reset count */
385 u16 empr_count; /* EMP reset count */
386 u16 pfr_count; /* PF reset count */
cd92e72f 387 u16 sw_int_count; /* SW interrupt count */
7daa6bf3
JB
388
389 struct mutex switch_mutex;
390 u16 lan_vsi; /* our default LAN VSI */
391 u16 lan_veb; /* initial relay, if exists */
392#define I40E_NO_VEB 0xffff
393#define I40E_NO_VSI 0xffff
394 u16 next_vsi; /* Next unallocated VSI - 0-based! */
395 struct i40e_vsi **vsi;
396 struct i40e_veb *veb[I40E_MAX_VEB];
397
398 struct i40e_lump_tracking *qp_pile;
399 struct i40e_lump_tracking *irq_pile;
400
401 /* switch config info */
402 u16 pf_seid;
403 u16 main_vsi_seid;
404 u16 mac_seid;
7daa6bf3
JB
405 struct kobject *switch_kobj;
406#ifdef CONFIG_DEBUG_FS
407 struct dentry *i40e_dbg_pf;
408#endif /* CONFIG_DEBUG_FS */
92faef85 409 bool cur_promisc;
7daa6bf3 410
93cd765b
ASJ
411 u16 instance; /* A unique number per i40e_pf instance in the system */
412
7daa6bf3
JB
413 /* sr-iov config info */
414 struct i40e_vf *vf;
415 int num_alloc_vfs; /* actual number of VFs allocated */
416 u32 vf_aq_requests;
1d0a4ada 417 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
7daa6bf3
JB
418
419 /* DCBx/DCBNL capability for PF that indicates
420 * whether DCBx is managed by firmware or host
421 * based agent (LLDPAD). Also, indicates what
422 * flavor of DCBx protocol (IEEE/CEE) is supported
423 * by the device. For now we're supporting IEEE
424 * mode only.
425 */
426 u16 dcbx_cap;
427
428 u32 fcoe_hmc_filt_num;
429 u32 fcoe_hmc_cntx_num;
430 struct i40e_filter_control_settings filter_settings;
beb0dff1
JK
431
432 struct ptp_clock *ptp_clock;
433 struct ptp_clock_info ptp_caps;
434 struct sk_buff *ptp_tx_skb;
beb0dff1 435 struct hwtstamp_config tstamp_config;
beb0dff1
JK
436 unsigned long last_rx_ptp_check;
437 spinlock_t tmreg_lock; /* Used to protect the device time registers. */
438 u64 ptp_base_adj;
439 u32 tx_hwtstamp_timeouts;
440 u32 rx_hwtstamp_cleared;
441 bool ptp_tx;
442 bool ptp_rx;
acd65448 443 u16 rss_table_size; /* HW RSS table size */
f4492db1
GR
444 /* These are only valid in NPAR modes */
445 u32 npar_max_bw;
446 u32 npar_min_bw;
2ac8b675
SN
447
448 u32 ioremap_len;
3487b6c3 449 u32 fd_inv;
31b606d0 450 u16 phy_led_val;
7daa6bf3
JB
451};
452
453struct i40e_mac_filter {
454 struct list_head list;
455 u8 macaddr[ETH_ALEN];
456#define I40E_VLAN_ANY -1
457 s16 vlan;
458 u8 counter; /* number of instances of this filter */
459 bool is_vf; /* filter belongs to a VF */
460 bool is_netdev; /* filter belongs to a netdev */
461 bool changed; /* filter needs to be sync'd to the HW */
6252c7e4 462 bool is_laa; /* filter is a Locally Administered Address */
7daa6bf3
JB
463};
464
465struct i40e_veb {
466 struct i40e_pf *pf;
467 u16 idx;
468 u16 veb_idx; /* index of VEB parent */
469 u16 seid;
470 u16 uplink_seid;
471 u16 stats_idx; /* index of VEB parent */
472 u8 enabled_tc;
51616018 473 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
7daa6bf3
JB
474 u16 flags;
475 u16 bw_limit;
476 u8 bw_max_quanta;
477 bool is_abs_credits;
478 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
479 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
480 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
481 struct kobject *kobj;
482 bool stat_offsets_loaded;
483 struct i40e_eth_stats stats;
484 struct i40e_eth_stats stats_offsets;
fe860afb
NP
485 struct i40e_veb_tc_stats tc_stats;
486 struct i40e_veb_tc_stats tc_stats_offsets;
7daa6bf3
JB
487};
488
489/* struct that defines a VSI, associated with a dev */
490struct i40e_vsi {
491 struct net_device *netdev;
492 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
493 bool netdev_registered;
494 bool stat_offsets_loaded;
495
496 u32 current_netdev_flags;
497 unsigned long state;
41a1d04b
JB
498#define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
499#define I40E_VSI_FLAG_VEB_OWNER BIT(1)
7daa6bf3
JB
500 unsigned long flags;
501
21659035
KP
502 /* Per VSI lock to protect elements/list (MAC filter) */
503 spinlock_t mac_filter_list_lock;
7daa6bf3
JB
504 struct list_head mac_filter_list;
505
506 /* VSI stats */
507 struct rtnl_link_stats64 net_stats;
508 struct rtnl_link_stats64 net_stats_offsets;
509 struct i40e_eth_stats eth_stats;
510 struct i40e_eth_stats eth_stats_offsets;
38e00438
VD
511#ifdef I40E_FCOE
512 struct i40e_fcoe_stats fcoe_stats;
513 struct i40e_fcoe_stats fcoe_stats_offsets;
514 bool fcoe_stat_offsets_loaded;
515#endif
7daa6bf3
JB
516 u32 tx_restart;
517 u32 tx_busy;
2fc3d715 518 u64 tx_linearize;
164c9f54 519 u64 tx_force_wb;
dd353109 520 u64 tx_lost_interrupt;
7daa6bf3
JB
521 u32 rx_buf_failed;
522 u32 rx_page_failed;
523
9f65e15b
AD
524 /* These are containers of ring pointers, allocated at run-time */
525 struct i40e_ring **rx_rings;
526 struct i40e_ring **tx_rings;
7daa6bf3
JB
527
528 u16 work_limit;
ac26fc13 529 u16 int_rate_limit; /* value in usecs */
7daa6bf3 530
acd65448
HZ
531 u16 rss_table_size; /* HW RSS table size */
532 u16 rss_size; /* Allocated RSS queues */
28c5869f
HZ
533 u8 *rss_hkey_user; /* User configured hash keys */
534 u8 *rss_lut_user; /* User configured lookup table entries */
5db4cb59 535
7daa6bf3
JB
536 u16 max_frame;
537 u16 rx_hdr_len;
538 u16 rx_buf_len;
539 u8 dtype;
540
541 /* List of q_vectors allocated to this VSI */
493fb300 542 struct i40e_q_vector **q_vectors;
7daa6bf3
JB
543 int num_q_vectors;
544 int base_vector;
63741846 545 bool irqs_ready;
7daa6bf3
JB
546
547 u16 seid; /* HW index of this VSI (absolute index) */
548 u16 id; /* VSI number */
549 u16 uplink_seid;
550
551 u16 base_queue; /* vsi's first queue in hw array */
552 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
9a3bd2f1 553 u16 req_queue_pairs; /* User requested queue pairs */
7daa6bf3
JB
554 u16 num_queue_pairs; /* Used tx and rx pairs */
555 u16 num_desc;
556 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
557 u16 vf_id; /* Virtual function ID for SRIOV VSIs */
558
559 struct i40e_tc_configuration tc_config;
560 struct i40e_aqc_vsi_properties_data info;
561
562 /* VSI BW limit (absolute across all TCs) */
563 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
564 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
565
566 /* Relative TC credits across VSIs */
567 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
568 /* TC BW limit credits within VSI */
569 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
570 /* TC BW limit max quanta within VSI */
571 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
572
573 struct i40e_pf *back; /* Backreference to associated PF */
574 u16 idx; /* index in pf->vsi[] */
575 u16 veb_idx; /* index of VEB parent */
576 struct kobject *kobj; /* sysfs object */
c156f856 577 bool current_isup; /* Sync 'link up' logging */
7daa6bf3 578
e3219ce6
ASJ
579 void *priv; /* client driver data reference. */
580
7daa6bf3
JB
581 /* VSI specific handlers */
582 irqreturn_t (*irq_handler)(int irq, void *data);
88eee9bc
CW
583
584 /* current rxnfc data */
585 struct ethtool_rxnfc rxnfc; /* current rss hash opts */
7daa6bf3
JB
586} ____cacheline_internodealigned_in_smp;
587
588struct i40e_netdev_priv {
589 struct i40e_vsi *vsi;
590};
591
592/* struct that defines an interrupt vector */
593struct i40e_q_vector {
594 struct i40e_vsi *vsi;
595
596 u16 v_idx; /* index in the vsi->q_vector array. */
597 u16 reg_idx; /* register index of the interrupt */
598
599 struct napi_struct napi;
600
601 struct i40e_ring_container rx;
602 struct i40e_ring_container tx;
603
604 u8 num_ringpairs; /* total number of ring pairs in vector */
605
9c6c1259
KP
606#define I40E_Q_VECTOR_HUNG_DETECT 0 /* Bit Index for hung detection logic */
607 unsigned long hung_detected; /* Set/Reset for hung_detection logic */
608
7daa6bf3 609 cpumask_t affinity_mask;
493fb300 610 struct rcu_head rcu; /* to avoid race with update stats on free */
b294ac70 611 char name[I40E_INT_NAME_STR_LEN];
8e0764b4 612 bool arm_wb_state;
ee2319cf
JB
613#define ITR_COUNTDOWN_START 100
614 u8 itr_countdown; /* when 0 should adjust ITR */
7daa6bf3
JB
615} ____cacheline_internodealigned_in_smp;
616
617/* lan device */
618struct i40e_device {
619 struct list_head list;
620 struct i40e_pf *pf;
621};
622
623/**
6dec1017 624 * i40e_nvm_version_str - format the NVM version strings
7daa6bf3
JB
625 * @hw: ptr to the hardware info
626 **/
6dec1017 627static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
7daa6bf3
JB
628{
629 static char buf[32];
2efaad86
CW
630 u32 full_ver;
631 u8 ver, patch;
632 u16 build;
633
634 full_ver = hw->nvm.oem_ver;
635 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
4eeb1fff
JB
636 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
637 I40E_OEM_VER_BUILD_MASK);
2efaad86 638 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
7daa6bf3
JB
639
640 snprintf(buf, sizeof(buf),
f0b44440 641 "%x.%02x 0x%x %d.%d.%d",
ff80301e
JB
642 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
643 I40E_NVM_VERSION_HI_SHIFT,
644 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
645 I40E_NVM_VERSION_LO_SHIFT,
2efaad86 646 hw->nvm.eetrack, ver, build, patch);
7daa6bf3
JB
647
648 return buf;
649}
650
651/**
652 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
653 * @netdev: the corresponding netdev
654 *
655 * Return the PF struct for the given netdev
656 **/
657static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
658{
659 struct i40e_netdev_priv *np = netdev_priv(netdev);
660 struct i40e_vsi *vsi = np->vsi;
661
662 return vsi->back;
663}
664
665static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
666 irqreturn_t (*irq_handler)(int, void *))
667{
668 vsi->irq_handler = irq_handler;
669}
670
671/**
672 * i40e_rx_is_programming_status - check for programming status descriptor
673 * @qw: the first quad word of the program status descriptor
674 *
675 * The value of in the descriptor length field indicate if this
676 * is a programming status descriptor for flow director or FCoE
677 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
678 * it is a packet descriptor.
679 **/
680static inline bool i40e_rx_is_programming_status(u64 qw)
681{
682 return I40E_RX_PROG_STATUS_DESC_LENGTH ==
683 (qw >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT);
684}
685
082def10
ASJ
686/**
687 * i40e_get_fd_cnt_all - get the total FD filter space available
b40c82e6 688 * @pf: pointer to the PF struct
082def10
ASJ
689 **/
690static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
691{
692 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
693}
694
7daa6bf3
JB
695/* needed by i40e_ethtool.c */
696int i40e_up(struct i40e_vsi *vsi);
697void i40e_down(struct i40e_vsi *vsi);
698extern const char i40e_driver_name[];
699extern const char i40e_driver_version_str[];
23326186 700void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
7daa6bf3 701void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags);
043dd650
HZ
702int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
703int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
fdf0e0bf 704struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
7daa6bf3
JB
705void i40e_update_stats(struct i40e_vsi *vsi);
706void i40e_update_eth_stats(struct i40e_vsi *vsi);
707struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
708int i40e_fetch_switch_configuration(struct i40e_pf *pf,
709 bool printconfig);
710
17a73f6b 711int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data, u8 *raw_packet,
7daa6bf3 712 struct i40e_pf *pf, bool add);
17a73f6b
JG
713int i40e_add_del_fdir(struct i40e_vsi *vsi,
714 struct i40e_fdir_filter *input, bool add);
55a5e60b 715void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
04294e38
ASJ
716u32 i40e_get_current_fd_count(struct i40e_pf *pf);
717u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
718u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
719u32 i40e_get_global_fd_count(struct i40e_pf *pf);
7c3c288b 720bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
7daa6bf3
JB
721void i40e_set_ethtool_ops(struct net_device *netdev);
722struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
723 u8 *macaddr, s16 vlan,
724 bool is_vf, bool is_netdev);
725void i40e_del_filter(struct i40e_vsi *vsi, u8 *macaddr, s16 vlan,
726 bool is_vf, bool is_netdev);
17652c63 727int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
7daa6bf3
JB
728struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
729 u16 uplink, u32 param1);
730int i40e_vsi_release(struct i40e_vsi *vsi);
731struct i40e_vsi *i40e_vsi_lookup(struct i40e_pf *pf, enum i40e_vsi_type type,
732 struct i40e_vsi *start_vsi);
38e00438
VD
733#ifdef I40E_FCOE
734void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
735 struct i40e_vsi_context *ctxt,
736 u8 enabled_tc, bool is_add);
737#endif
e3219ce6
ASJ
738void i40e_service_event_schedule(struct i40e_pf *pf);
739void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
740 u8 *msg, u16 len);
741
fc18eaa0 742int i40e_vsi_control_rings(struct i40e_vsi *vsi, bool enable);
f8ff1464 743int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
7daa6bf3
JB
744struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
745 u16 downlink_seid, u8 enabled_tc);
746void i40e_veb_release(struct i40e_veb *veb);
747
4e3b35b0 748int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
4eeb1fff 749int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
7daa6bf3
JB
750void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
751void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
752void i40e_pf_reset_stats(struct i40e_pf *pf);
753#ifdef CONFIG_DEBUG_FS
754void i40e_dbg_pf_init(struct i40e_pf *pf);
755void i40e_dbg_pf_exit(struct i40e_pf *pf);
756void i40e_dbg_init(void);
757void i40e_dbg_exit(void);
758#else
759static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
760static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
761static inline void i40e_dbg_init(void) {}
762static inline void i40e_dbg_exit(void) {}
763#endif /* CONFIG_DEBUG_FS*/
e3219ce6
ASJ
764/* needed by client drivers */
765int i40e_lan_add_device(struct i40e_pf *pf);
766int i40e_lan_del_device(struct i40e_pf *pf);
767void i40e_client_subtask(struct i40e_pf *pf);
768void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
769void i40e_notify_client_of_netdev_open(struct i40e_vsi *vsi);
770void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
771void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
772void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
773int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id,
774 enum i40e_client_type type);
02d109be
JB
775/**
776 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
777 * @vsi: pointer to a vsi
778 * @vector: enable a particular Hw Interrupt vector, without base_vector
779 **/
780static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
781{
782 struct i40e_pf *pf = vsi->back;
783 struct i40e_hw *hw = &pf->hw;
784 u32 val;
785
40d72a50
JB
786 /* definitely clear the PBA here, as this function is meant to
787 * clean out all previous interrupts AND enable the interrupt
788 */
02d109be
JB
789 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
790 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
791 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
792 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
793 /* skip the flush */
794}
795
2ef28cfb 796void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
40d72a50 797void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf, bool clearpba);
38e00438
VD
798#ifdef I40E_FCOE
799struct rtnl_link_stats64 *i40e_get_netdev_stats_struct(
800 struct net_device *netdev,
801 struct rtnl_link_stats64 *storage);
802int i40e_set_mac(struct net_device *netdev, void *p);
803void i40e_set_rx_mode(struct net_device *netdev);
804#endif
7daa6bf3 805int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
38e00438
VD
806#ifdef I40E_FCOE
807void i40e_tx_timeout(struct net_device *netdev);
808int i40e_vlan_rx_add_vid(struct net_device *netdev,
809 __always_unused __be16 proto, u16 vid);
810int i40e_vlan_rx_kill_vid(struct net_device *netdev,
811 __always_unused __be16 proto, u16 vid);
812#endif
96664483 813int i40e_open(struct net_device *netdev);
6c167f58 814int i40e_vsi_open(struct i40e_vsi *vsi);
7daa6bf3
JB
815void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
816int i40e_vsi_add_vlan(struct i40e_vsi *vsi, s16 vid);
817int i40e_vsi_kill_vlan(struct i40e_vsi *vsi, s16 vid);
818struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
819 bool is_vf, bool is_netdev);
b36e9ab5
MW
820int i40e_del_mac_all_vlan(struct i40e_vsi *vsi, u8 *macaddr,
821 bool is_vf, bool is_netdev);
7daa6bf3
JB
822bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
823struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, u8 *macaddr,
824 bool is_vf, bool is_netdev);
38e00438 825#ifdef I40E_FCOE
38e00438 826int i40e_close(struct net_device *netdev);
16e5cc64
JF
827int __i40e_setup_tc(struct net_device *netdev, u32 handle, __be16 proto,
828 struct tc_to_netdev *tc);
38e00438
VD
829void i40e_netpoll(struct net_device *netdev);
830int i40e_fcoe_enable(struct net_device *netdev);
831int i40e_fcoe_disable(struct net_device *netdev);
832int i40e_fcoe_vsi_init(struct i40e_vsi *vsi, struct i40e_vsi_context *ctxt);
833u8 i40e_get_fcoe_tc_map(struct i40e_pf *pf);
834void i40e_fcoe_config_netdev(struct net_device *netdev, struct i40e_vsi *vsi);
835void i40e_fcoe_vsi_setup(struct i40e_pf *pf);
21364bcf 836void i40e_init_pf_fcoe(struct i40e_pf *pf);
38e00438
VD
837int i40e_fcoe_setup_ddp_resources(struct i40e_vsi *vsi);
838void i40e_fcoe_free_ddp_resources(struct i40e_vsi *vsi);
839int i40e_fcoe_handle_offload(struct i40e_ring *rx_ring,
840 union i40e_rx_desc *rx_desc,
841 struct sk_buff *skb);
842void i40e_fcoe_handle_status(struct i40e_ring *rx_ring,
843 union i40e_rx_desc *rx_desc, u8 prog_id);
844#endif /* I40E_FCOE */
7daa6bf3 845void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
4e3b35b0
NP
846#ifdef CONFIG_I40E_DCB
847void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
750fcbcf 848 struct i40e_dcbx_config *old_cfg,
4e3b35b0
NP
849 struct i40e_dcbx_config *new_cfg);
850void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
851void i40e_dcbnl_setup(struct i40e_vsi *vsi);
852bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
853 struct i40e_dcbx_config *old_cfg,
854 struct i40e_dcbx_config *new_cfg);
855#endif /* CONFIG_I40E_DCB */
beb0dff1
JK
856void i40e_ptp_rx_hang(struct i40e_vsi *vsi);
857void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
858void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
859void i40e_ptp_set_increment(struct i40e_pf *pf);
860int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
861int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
862void i40e_ptp_init(struct i40e_pf *pf);
863void i40e_ptp_stop(struct i40e_pf *pf);
51616018 864int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
f4492db1
GR
865i40e_status i40e_get_npar_bw_setting(struct i40e_pf *pf);
866i40e_status i40e_set_npar_bw_setting(struct i40e_pf *pf);
867i40e_status i40e_commit_npar_bw_setting(struct i40e_pf *pf);
c156f856 868void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
7daa6bf3 869#endif /* _I40E_H_ */