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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
bf67044b | 4 | Copyright(c) 1999 - 2013 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
bc7f75fa AK |
29 | #include "e1000.h" |
30 | ||
bc7f75fa | 31 | static s32 e1000_wait_autoneg(struct e1000_hw *hw); |
97ac8cae | 32 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, |
2b6b168d | 33 | u16 *data, bool read, bool page_set); |
a4f58f54 BA |
34 | static u32 e1000_get_phy_addr_for_hv_page(u32 page); |
35 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |
1f96012d | 36 | u16 *data, bool read); |
bc7f75fa AK |
37 | |
38 | /* Cable length tables */ | |
6480641e BA |
39 | static const u16 e1000_m88_cable_length_table[] = { |
40 | 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; | |
eb656d45 BA |
41 | #define M88E1000_CABLE_LENGTH_TABLE_SIZE \ |
42 | ARRAY_SIZE(e1000_m88_cable_length_table) | |
bc7f75fa | 43 | |
6480641e BA |
44 | static const u16 e1000_igp_2_cable_length_table[] = { |
45 | 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, | |
46 | 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, | |
47 | 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, | |
48 | 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, | |
49 | 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, | |
50 | 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, | |
51 | 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, | |
52 | 124}; | |
bc7f75fa | 53 | #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ |
c00acf46 | 54 | ARRAY_SIZE(e1000_igp_2_cable_length_table) |
bc7f75fa AK |
55 | |
56 | /** | |
57 | * e1000e_check_reset_block_generic - Check if PHY reset is blocked | |
58 | * @hw: pointer to the HW structure | |
59 | * | |
60 | * Read the PHY management control register and check whether a PHY reset | |
61 | * is blocked. If a reset is not blocked return 0, otherwise | |
62 | * return E1000_BLK_PHY_RESET (12). | |
63 | **/ | |
64 | s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) | |
65 | { | |
66 | u32 manc; | |
67 | ||
68 | manc = er32(MANC); | |
69 | ||
70 | return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? | |
71 | E1000_BLK_PHY_RESET : 0; | |
72 | } | |
73 | ||
74 | /** | |
75 | * e1000e_get_phy_id - Retrieve the PHY ID and revision | |
76 | * @hw: pointer to the HW structure | |
77 | * | |
78 | * Reads the PHY registers and stores the PHY ID and possibly the PHY | |
79 | * revision in the hardware structure. | |
80 | **/ | |
81 | s32 e1000e_get_phy_id(struct e1000_hw *hw) | |
82 | { | |
83 | struct e1000_phy_info *phy = &hw->phy; | |
a4f58f54 | 84 | s32 ret_val = 0; |
bc7f75fa | 85 | u16 phy_id; |
a4f58f54 | 86 | u16 retry_count = 0; |
bc7f75fa | 87 | |
668018d7 | 88 | if (!phy->ops.read_reg) |
5015e53a | 89 | return 0; |
bc7f75fa | 90 | |
a4f58f54 | 91 | while (retry_count < 2) { |
c2ade1a4 | 92 | ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id); |
a4f58f54 | 93 | if (ret_val) |
5015e53a | 94 | return ret_val; |
bc7f75fa | 95 | |
a4f58f54 BA |
96 | phy->id = (u32)(phy_id << 16); |
97 | udelay(20); | |
c2ade1a4 | 98 | ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id); |
a4f58f54 | 99 | if (ret_val) |
5015e53a | 100 | return ret_val; |
bc7f75fa | 101 | |
a4f58f54 BA |
102 | phy->id |= (u32)(phy_id & PHY_REVISION_MASK); |
103 | phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); | |
104 | ||
105 | if (phy->id != 0 && phy->id != PHY_REVISION_MASK) | |
5015e53a | 106 | return 0; |
a4f58f54 | 107 | |
a4f58f54 BA |
108 | retry_count++; |
109 | } | |
5015e53a BA |
110 | |
111 | return 0; | |
bc7f75fa AK |
112 | } |
113 | ||
114 | /** | |
115 | * e1000e_phy_reset_dsp - Reset PHY DSP | |
116 | * @hw: pointer to the HW structure | |
117 | * | |
118 | * Reset the digital signal processor. | |
119 | **/ | |
120 | s32 e1000e_phy_reset_dsp(struct e1000_hw *hw) | |
121 | { | |
122 | s32 ret_val; | |
123 | ||
124 | ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); | |
125 | if (ret_val) | |
126 | return ret_val; | |
127 | ||
128 | return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0); | |
129 | } | |
130 | ||
131 | /** | |
2d9498f3 | 132 | * e1000e_read_phy_reg_mdic - Read MDI control register |
bc7f75fa AK |
133 | * @hw: pointer to the HW structure |
134 | * @offset: register offset to be read | |
135 | * @data: pointer to the read data | |
136 | * | |
489815ce | 137 | * Reads the MDI control register in the PHY at offset and stores the |
bc7f75fa AK |
138 | * information read to data. |
139 | **/ | |
2d9498f3 | 140 | s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) |
bc7f75fa AK |
141 | { |
142 | struct e1000_phy_info *phy = &hw->phy; | |
143 | u32 i, mdic = 0; | |
144 | ||
145 | if (offset > MAX_PHY_REG_ADDRESS) { | |
3bb99fe2 | 146 | e_dbg("PHY Address %d is out of range\n", offset); |
bc7f75fa AK |
147 | return -E1000_ERR_PARAM; |
148 | } | |
149 | ||
e921eb1a | 150 | /* Set up Op-code, Phy Address, and register offset in the MDI |
bc7f75fa AK |
151 | * Control register. The MAC will take care of interfacing with the |
152 | * PHY to retrieve the desired data. | |
153 | */ | |
154 | mdic = ((offset << E1000_MDIC_REG_SHIFT) | | |
155 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
156 | (E1000_MDIC_OP_READ)); | |
157 | ||
158 | ew32(MDIC, mdic); | |
159 | ||
e921eb1a | 160 | /* Poll the ready bit to see if the MDI read completed |
ad68076e BA |
161 | * Increasing the time out as testing showed failures with |
162 | * the lower time out | |
163 | */ | |
2d9498f3 | 164 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { |
bc7f75fa AK |
165 | udelay(50); |
166 | mdic = er32(MDIC); | |
167 | if (mdic & E1000_MDIC_READY) | |
168 | break; | |
169 | } | |
170 | if (!(mdic & E1000_MDIC_READY)) { | |
3bb99fe2 | 171 | e_dbg("MDI Read did not complete\n"); |
bc7f75fa AK |
172 | return -E1000_ERR_PHY; |
173 | } | |
174 | if (mdic & E1000_MDIC_ERROR) { | |
3bb99fe2 | 175 | e_dbg("MDI Error\n"); |
bc7f75fa AK |
176 | return -E1000_ERR_PHY; |
177 | } | |
178 | *data = (u16) mdic; | |
179 | ||
e921eb1a | 180 | /* Allow some time after each MDIC transaction to avoid |
664dc878 BA |
181 | * reading duplicate data in the next MDIC transaction. |
182 | */ | |
183 | if (hw->mac.type == e1000_pch2lan) | |
184 | udelay(100); | |
185 | ||
bc7f75fa AK |
186 | return 0; |
187 | } | |
188 | ||
189 | /** | |
2d9498f3 | 190 | * e1000e_write_phy_reg_mdic - Write MDI control register |
bc7f75fa AK |
191 | * @hw: pointer to the HW structure |
192 | * @offset: register offset to write to | |
193 | * @data: data to write to register at offset | |
194 | * | |
195 | * Writes data to MDI control register in the PHY at offset. | |
196 | **/ | |
2d9498f3 | 197 | s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) |
bc7f75fa AK |
198 | { |
199 | struct e1000_phy_info *phy = &hw->phy; | |
200 | u32 i, mdic = 0; | |
201 | ||
202 | if (offset > MAX_PHY_REG_ADDRESS) { | |
3bb99fe2 | 203 | e_dbg("PHY Address %d is out of range\n", offset); |
bc7f75fa AK |
204 | return -E1000_ERR_PARAM; |
205 | } | |
206 | ||
e921eb1a | 207 | /* Set up Op-code, Phy Address, and register offset in the MDI |
bc7f75fa AK |
208 | * Control register. The MAC will take care of interfacing with the |
209 | * PHY to retrieve the desired data. | |
210 | */ | |
211 | mdic = (((u32)data) | | |
212 | (offset << E1000_MDIC_REG_SHIFT) | | |
213 | (phy->addr << E1000_MDIC_PHY_SHIFT) | | |
214 | (E1000_MDIC_OP_WRITE)); | |
215 | ||
216 | ew32(MDIC, mdic); | |
217 | ||
e921eb1a | 218 | /* Poll the ready bit to see if the MDI read completed |
2d9498f3 DG |
219 | * Increasing the time out as testing showed failures with |
220 | * the lower time out | |
221 | */ | |
222 | for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { | |
223 | udelay(50); | |
bc7f75fa AK |
224 | mdic = er32(MDIC); |
225 | if (mdic & E1000_MDIC_READY) | |
226 | break; | |
227 | } | |
228 | if (!(mdic & E1000_MDIC_READY)) { | |
3bb99fe2 | 229 | e_dbg("MDI Write did not complete\n"); |
bc7f75fa AK |
230 | return -E1000_ERR_PHY; |
231 | } | |
2d9498f3 | 232 | if (mdic & E1000_MDIC_ERROR) { |
3bb99fe2 | 233 | e_dbg("MDI Error\n"); |
2d9498f3 DG |
234 | return -E1000_ERR_PHY; |
235 | } | |
bc7f75fa | 236 | |
e921eb1a | 237 | /* Allow some time after each MDIC transaction to avoid |
664dc878 BA |
238 | * reading duplicate data in the next MDIC transaction. |
239 | */ | |
240 | if (hw->mac.type == e1000_pch2lan) | |
241 | udelay(100); | |
242 | ||
bc7f75fa AK |
243 | return 0; |
244 | } | |
245 | ||
246 | /** | |
247 | * e1000e_read_phy_reg_m88 - Read m88 PHY register | |
248 | * @hw: pointer to the HW structure | |
249 | * @offset: register offset to be read | |
250 | * @data: pointer to the read data | |
251 | * | |
252 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
253 | * and storing the retrieved information in data. Release any acquired | |
254 | * semaphores before exiting. | |
255 | **/ | |
256 | s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) | |
257 | { | |
258 | s32 ret_val; | |
259 | ||
94d8186a | 260 | ret_val = hw->phy.ops.acquire(hw); |
bc7f75fa AK |
261 | if (ret_val) |
262 | return ret_val; | |
263 | ||
2d9498f3 DG |
264 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
265 | data); | |
bc7f75fa | 266 | |
94d8186a | 267 | hw->phy.ops.release(hw); |
bc7f75fa AK |
268 | |
269 | return ret_val; | |
270 | } | |
271 | ||
272 | /** | |
273 | * e1000e_write_phy_reg_m88 - Write m88 PHY register | |
274 | * @hw: pointer to the HW structure | |
275 | * @offset: register offset to write to | |
276 | * @data: data to write at register offset | |
277 | * | |
278 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
279 | * at the offset. Release any acquired semaphores before exiting. | |
280 | **/ | |
281 | s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) | |
282 | { | |
283 | s32 ret_val; | |
284 | ||
94d8186a | 285 | ret_val = hw->phy.ops.acquire(hw); |
bc7f75fa AK |
286 | if (ret_val) |
287 | return ret_val; | |
288 | ||
2d9498f3 DG |
289 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, |
290 | data); | |
bc7f75fa | 291 | |
94d8186a | 292 | hw->phy.ops.release(hw); |
bc7f75fa AK |
293 | |
294 | return ret_val; | |
295 | } | |
296 | ||
2b6b168d BA |
297 | /** |
298 | * e1000_set_page_igp - Set page as on IGP-like PHY(s) | |
299 | * @hw: pointer to the HW structure | |
300 | * @page: page to set (shifted left when necessary) | |
301 | * | |
302 | * Sets PHY page required for PHY register access. Assumes semaphore is | |
303 | * already acquired. Note, this function sets phy.addr to 1 so the caller | |
304 | * must set it appropriately (if necessary) after this function returns. | |
305 | **/ | |
306 | s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) | |
307 | { | |
308 | e_dbg("Setting page 0x%x\n", page); | |
309 | ||
310 | hw->phy.addr = 1; | |
311 | ||
312 | return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); | |
313 | } | |
314 | ||
bc7f75fa | 315 | /** |
5ccdcecb | 316 | * __e1000e_read_phy_reg_igp - Read igp PHY register |
bc7f75fa AK |
317 | * @hw: pointer to the HW structure |
318 | * @offset: register offset to be read | |
319 | * @data: pointer to the read data | |
5ccdcecb | 320 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
321 | * |
322 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
5ccdcecb | 323 | * and stores the retrieved information in data. Release any acquired |
bc7f75fa AK |
324 | * semaphores before exiting. |
325 | **/ | |
5ccdcecb BA |
326 | static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, |
327 | bool locked) | |
bc7f75fa | 328 | { |
5ccdcecb | 329 | s32 ret_val = 0; |
bc7f75fa | 330 | |
5ccdcecb | 331 | if (!locked) { |
668018d7 | 332 | if (!hw->phy.ops.acquire) |
5015e53a | 333 | return 0; |
5ccdcecb | 334 | |
94d8186a | 335 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb | 336 | if (ret_val) |
5015e53a | 337 | return ret_val; |
5ccdcecb | 338 | } |
bc7f75fa | 339 | |
5015e53a | 340 | if (offset > MAX_PHY_MULTI_PAGE_REG) |
2d9498f3 DG |
341 | ret_val = e1000e_write_phy_reg_mdic(hw, |
342 | IGP01E1000_PHY_PAGE_SELECT, | |
343 | (u16)offset); | |
5015e53a BA |
344 | if (!ret_val) |
345 | ret_val = e1000e_read_phy_reg_mdic(hw, | |
346 | MAX_PHY_REG_ADDRESS & offset, | |
347 | data); | |
5ccdcecb | 348 | if (!locked) |
94d8186a | 349 | hw->phy.ops.release(hw); |
5015e53a | 350 | |
bc7f75fa AK |
351 | return ret_val; |
352 | } | |
353 | ||
5ccdcecb BA |
354 | /** |
355 | * e1000e_read_phy_reg_igp - Read igp PHY register | |
356 | * @hw: pointer to the HW structure | |
357 | * @offset: register offset to be read | |
358 | * @data: pointer to the read data | |
359 | * | |
360 | * Acquires semaphore then reads the PHY register at offset and stores the | |
361 | * retrieved information in data. | |
362 | * Release the acquired semaphore before exiting. | |
363 | **/ | |
364 | s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) | |
365 | { | |
366 | return __e1000e_read_phy_reg_igp(hw, offset, data, false); | |
367 | } | |
368 | ||
369 | /** | |
370 | * e1000e_read_phy_reg_igp_locked - Read igp PHY register | |
371 | * @hw: pointer to the HW structure | |
372 | * @offset: register offset to be read | |
373 | * @data: pointer to the read data | |
374 | * | |
375 | * Reads the PHY register at offset and stores the retrieved information | |
376 | * in data. Assumes semaphore already acquired. | |
377 | **/ | |
378 | s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) | |
379 | { | |
380 | return __e1000e_read_phy_reg_igp(hw, offset, data, true); | |
381 | } | |
382 | ||
bc7f75fa AK |
383 | /** |
384 | * e1000e_write_phy_reg_igp - Write igp PHY register | |
385 | * @hw: pointer to the HW structure | |
386 | * @offset: register offset to write to | |
387 | * @data: data to write at register offset | |
5ccdcecb | 388 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
389 | * |
390 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
391 | * at the offset. Release any acquired semaphores before exiting. | |
392 | **/ | |
5ccdcecb BA |
393 | static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, |
394 | bool locked) | |
bc7f75fa | 395 | { |
5ccdcecb | 396 | s32 ret_val = 0; |
bc7f75fa | 397 | |
5ccdcecb | 398 | if (!locked) { |
668018d7 | 399 | if (!hw->phy.ops.acquire) |
5015e53a | 400 | return 0; |
5ccdcecb | 401 | |
94d8186a | 402 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb | 403 | if (ret_val) |
5015e53a | 404 | return ret_val; |
5ccdcecb | 405 | } |
bc7f75fa | 406 | |
5015e53a | 407 | if (offset > MAX_PHY_MULTI_PAGE_REG) |
2d9498f3 DG |
408 | ret_val = e1000e_write_phy_reg_mdic(hw, |
409 | IGP01E1000_PHY_PAGE_SELECT, | |
410 | (u16)offset); | |
5015e53a BA |
411 | if (!ret_val) |
412 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & | |
413 | offset, | |
414 | data); | |
5ccdcecb | 415 | if (!locked) |
94d8186a | 416 | hw->phy.ops.release(hw); |
bc7f75fa AK |
417 | |
418 | return ret_val; | |
419 | } | |
420 | ||
421 | /** | |
5ccdcecb BA |
422 | * e1000e_write_phy_reg_igp - Write igp PHY register |
423 | * @hw: pointer to the HW structure | |
424 | * @offset: register offset to write to | |
425 | * @data: data to write at register offset | |
426 | * | |
427 | * Acquires semaphore then writes the data to PHY register | |
428 | * at the offset. Release any acquired semaphores before exiting. | |
429 | **/ | |
430 | s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) | |
431 | { | |
432 | return __e1000e_write_phy_reg_igp(hw, offset, data, false); | |
433 | } | |
434 | ||
435 | /** | |
436 | * e1000e_write_phy_reg_igp_locked - Write igp PHY register | |
437 | * @hw: pointer to the HW structure | |
438 | * @offset: register offset to write to | |
439 | * @data: data to write at register offset | |
440 | * | |
441 | * Writes the data to PHY register at the offset. | |
442 | * Assumes semaphore already acquired. | |
443 | **/ | |
444 | s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) | |
445 | { | |
446 | return __e1000e_write_phy_reg_igp(hw, offset, data, true); | |
447 | } | |
448 | ||
449 | /** | |
450 | * __e1000_read_kmrn_reg - Read kumeran register | |
bc7f75fa AK |
451 | * @hw: pointer to the HW structure |
452 | * @offset: register offset to be read | |
453 | * @data: pointer to the read data | |
5ccdcecb | 454 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
455 | * |
456 | * Acquires semaphore, if necessary. Then reads the PHY register at offset | |
457 | * using the kumeran interface. The information retrieved is stored in data. | |
458 | * Release any acquired semaphores before exiting. | |
459 | **/ | |
5ccdcecb BA |
460 | static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, |
461 | bool locked) | |
bc7f75fa AK |
462 | { |
463 | u32 kmrnctrlsta; | |
bc7f75fa | 464 | |
5ccdcecb | 465 | if (!locked) { |
5015e53a BA |
466 | s32 ret_val = 0; |
467 | ||
668018d7 | 468 | if (!hw->phy.ops.acquire) |
5015e53a | 469 | return 0; |
5ccdcecb | 470 | |
94d8186a | 471 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb | 472 | if (ret_val) |
5015e53a | 473 | return ret_val; |
5ccdcecb | 474 | } |
bc7f75fa AK |
475 | |
476 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
477 | E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; | |
478 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
945a5151 | 479 | e1e_flush(); |
bc7f75fa AK |
480 | |
481 | udelay(2); | |
482 | ||
483 | kmrnctrlsta = er32(KMRNCTRLSTA); | |
484 | *data = (u16)kmrnctrlsta; | |
485 | ||
5ccdcecb | 486 | if (!locked) |
94d8186a | 487 | hw->phy.ops.release(hw); |
bc7f75fa | 488 | |
5015e53a | 489 | return 0; |
bc7f75fa AK |
490 | } |
491 | ||
492 | /** | |
5ccdcecb BA |
493 | * e1000e_read_kmrn_reg - Read kumeran register |
494 | * @hw: pointer to the HW structure | |
495 | * @offset: register offset to be read | |
496 | * @data: pointer to the read data | |
497 | * | |
498 | * Acquires semaphore then reads the PHY register at offset using the | |
499 | * kumeran interface. The information retrieved is stored in data. | |
500 | * Release the acquired semaphore before exiting. | |
501 | **/ | |
502 | s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data) | |
503 | { | |
504 | return __e1000_read_kmrn_reg(hw, offset, data, false); | |
505 | } | |
506 | ||
507 | /** | |
1d5846b9 | 508 | * e1000e_read_kmrn_reg_locked - Read kumeran register |
5ccdcecb BA |
509 | * @hw: pointer to the HW structure |
510 | * @offset: register offset to be read | |
511 | * @data: pointer to the read data | |
512 | * | |
513 | * Reads the PHY register at offset using the kumeran interface. The | |
514 | * information retrieved is stored in data. | |
515 | * Assumes semaphore already acquired. | |
516 | **/ | |
1d5846b9 | 517 | s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) |
5ccdcecb BA |
518 | { |
519 | return __e1000_read_kmrn_reg(hw, offset, data, true); | |
520 | } | |
521 | ||
522 | /** | |
523 | * __e1000_write_kmrn_reg - Write kumeran register | |
bc7f75fa AK |
524 | * @hw: pointer to the HW structure |
525 | * @offset: register offset to write to | |
526 | * @data: data to write at register offset | |
5ccdcecb | 527 | * @locked: semaphore has already been acquired or not |
bc7f75fa AK |
528 | * |
529 | * Acquires semaphore, if necessary. Then write the data to PHY register | |
530 | * at the offset using the kumeran interface. Release any acquired semaphores | |
531 | * before exiting. | |
532 | **/ | |
5ccdcecb BA |
533 | static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, |
534 | bool locked) | |
bc7f75fa AK |
535 | { |
536 | u32 kmrnctrlsta; | |
bc7f75fa | 537 | |
5ccdcecb | 538 | if (!locked) { |
5015e53a BA |
539 | s32 ret_val = 0; |
540 | ||
668018d7 | 541 | if (!hw->phy.ops.acquire) |
5015e53a | 542 | return 0; |
5ccdcecb | 543 | |
94d8186a | 544 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb | 545 | if (ret_val) |
5015e53a | 546 | return ret_val; |
5ccdcecb | 547 | } |
bc7f75fa AK |
548 | |
549 | kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & | |
550 | E1000_KMRNCTRLSTA_OFFSET) | data; | |
551 | ew32(KMRNCTRLSTA, kmrnctrlsta); | |
945a5151 | 552 | e1e_flush(); |
bc7f75fa AK |
553 | |
554 | udelay(2); | |
bc7f75fa | 555 | |
5ccdcecb | 556 | if (!locked) |
94d8186a | 557 | hw->phy.ops.release(hw); |
5ccdcecb | 558 | |
5015e53a | 559 | return 0; |
bc7f75fa AK |
560 | } |
561 | ||
5ccdcecb BA |
562 | /** |
563 | * e1000e_write_kmrn_reg - Write kumeran register | |
564 | * @hw: pointer to the HW structure | |
565 | * @offset: register offset to write to | |
566 | * @data: data to write at register offset | |
567 | * | |
568 | * Acquires semaphore then writes the data to the PHY register at the offset | |
569 | * using the kumeran interface. Release the acquired semaphore before exiting. | |
570 | **/ | |
571 | s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data) | |
572 | { | |
573 | return __e1000_write_kmrn_reg(hw, offset, data, false); | |
574 | } | |
575 | ||
576 | /** | |
1d5846b9 | 577 | * e1000e_write_kmrn_reg_locked - Write kumeran register |
5ccdcecb BA |
578 | * @hw: pointer to the HW structure |
579 | * @offset: register offset to write to | |
580 | * @data: data to write at register offset | |
581 | * | |
582 | * Write the data to PHY register at the offset using the kumeran interface. | |
583 | * Assumes semaphore already acquired. | |
584 | **/ | |
1d5846b9 | 585 | s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) |
5ccdcecb BA |
586 | { |
587 | return __e1000_write_kmrn_reg(hw, offset, data, true); | |
588 | } | |
589 | ||
7b9f7e35 BA |
590 | /** |
591 | * e1000_set_master_slave_mode - Setup PHY for Master/slave mode | |
592 | * @hw: pointer to the HW structure | |
593 | * | |
594 | * Sets up Master/slave mode | |
595 | **/ | |
596 | static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) | |
597 | { | |
598 | s32 ret_val; | |
599 | u16 phy_data; | |
600 | ||
601 | /* Resolve Master/Slave mode */ | |
c2ade1a4 | 602 | ret_val = e1e_rphy(hw, MII_CTRL1000, &phy_data); |
7b9f7e35 BA |
603 | if (ret_val) |
604 | return ret_val; | |
605 | ||
606 | /* load defaults for future use */ | |
c2ade1a4 BA |
607 | hw->phy.original_ms_type = (phy_data & CTL1000_ENABLE_MASTER) ? |
608 | ((phy_data & CTL1000_AS_MASTER) ? | |
7b9f7e35 BA |
609 | e1000_ms_force_master : e1000_ms_force_slave) : e1000_ms_auto; |
610 | ||
611 | switch (hw->phy.ms_type) { | |
612 | case e1000_ms_force_master: | |
c2ade1a4 | 613 | phy_data |= (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER); |
7b9f7e35 BA |
614 | break; |
615 | case e1000_ms_force_slave: | |
c2ade1a4 BA |
616 | phy_data |= CTL1000_ENABLE_MASTER; |
617 | phy_data &= ~(CTL1000_AS_MASTER); | |
7b9f7e35 BA |
618 | break; |
619 | case e1000_ms_auto: | |
c2ade1a4 | 620 | phy_data &= ~CTL1000_ENABLE_MASTER; |
7b9f7e35 BA |
621 | /* fall-through */ |
622 | default: | |
623 | break; | |
624 | } | |
625 | ||
c2ade1a4 | 626 | return e1e_wphy(hw, MII_CTRL1000, phy_data); |
7b9f7e35 BA |
627 | } |
628 | ||
a4f58f54 BA |
629 | /** |
630 | * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link | |
631 | * @hw: pointer to the HW structure | |
632 | * | |
633 | * Sets up Carrier-sense on Transmit and downshift values. | |
634 | **/ | |
635 | s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) | |
636 | { | |
a4f58f54 BA |
637 | s32 ret_val; |
638 | u16 phy_data; | |
639 | ||
af667a29 | 640 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
482fed85 | 641 | ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data); |
a4f58f54 | 642 | if (ret_val) |
5015e53a | 643 | return ret_val; |
a4f58f54 BA |
644 | |
645 | phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; | |
646 | ||
647 | /* Enable downshift */ | |
648 | phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; | |
649 | ||
7b9f7e35 BA |
650 | ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data); |
651 | if (ret_val) | |
652 | return ret_val; | |
653 | ||
e86fd891 BA |
654 | /* Set MDI/MDIX mode */ |
655 | ret_val = e1e_rphy(hw, I82577_PHY_CTRL_2, &phy_data); | |
656 | if (ret_val) | |
657 | return ret_val; | |
658 | phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; | |
e921eb1a | 659 | /* Options: |
e86fd891 BA |
660 | * 0 - Auto (default) |
661 | * 1 - MDI mode | |
662 | * 2 - MDI-X mode | |
663 | */ | |
664 | switch (hw->phy.mdix) { | |
665 | case 1: | |
666 | break; | |
667 | case 2: | |
668 | phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; | |
669 | break; | |
670 | case 0: | |
671 | default: | |
672 | phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; | |
673 | break; | |
674 | } | |
675 | ret_val = e1e_wphy(hw, I82577_PHY_CTRL_2, phy_data); | |
676 | if (ret_val) | |
677 | return ret_val; | |
678 | ||
7b9f7e35 | 679 | return e1000_set_master_slave_mode(hw); |
a4f58f54 BA |
680 | } |
681 | ||
bc7f75fa AK |
682 | /** |
683 | * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link | |
684 | * @hw: pointer to the HW structure | |
685 | * | |
686 | * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock | |
687 | * and downshift values are set also. | |
688 | **/ | |
689 | s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw) | |
690 | { | |
691 | struct e1000_phy_info *phy = &hw->phy; | |
692 | s32 ret_val; | |
693 | u16 phy_data; | |
694 | ||
ad68076e | 695 | /* Enable CRS on Tx. This must be set for half-duplex operation. */ |
bc7f75fa AK |
696 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); |
697 | if (ret_val) | |
698 | return ret_val; | |
699 | ||
a4f58f54 BA |
700 | /* For BM PHY this bit is downshift enable */ |
701 | if (phy->type != e1000_phy_bm) | |
2d9498f3 | 702 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; |
bc7f75fa | 703 | |
e921eb1a | 704 | /* Options: |
bc7f75fa AK |
705 | * MDI/MDI-X = 0 (default) |
706 | * 0 - Auto for all speeds | |
707 | * 1 - MDI mode | |
708 | * 2 - MDI-X mode | |
709 | * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) | |
710 | */ | |
711 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
712 | ||
713 | switch (phy->mdix) { | |
714 | case 1: | |
715 | phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; | |
716 | break; | |
717 | case 2: | |
718 | phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; | |
719 | break; | |
720 | case 3: | |
721 | phy_data |= M88E1000_PSCR_AUTO_X_1000T; | |
722 | break; | |
723 | case 0: | |
724 | default: | |
725 | phy_data |= M88E1000_PSCR_AUTO_X_MODE; | |
726 | break; | |
727 | } | |
728 | ||
e921eb1a | 729 | /* Options: |
bc7f75fa AK |
730 | * disable_polarity_correction = 0 (default) |
731 | * Automatic Correction for Reversed Cable Polarity | |
732 | * 0 - Disabled | |
733 | * 1 - Enabled | |
734 | */ | |
735 | phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; | |
04499ec4 | 736 | if (phy->disable_polarity_correction) |
bc7f75fa AK |
737 | phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; |
738 | ||
97ac8cae | 739 | /* Enable downshift on BM (disabled by default) */ |
885fe7be MV |
740 | if (phy->type == e1000_phy_bm) { |
741 | /* For 82574/82583, first disable then enable downshift */ | |
742 | if (phy->id == BME1000_E_PHY_ID_R2) { | |
743 | phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; | |
744 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, | |
745 | phy_data); | |
746 | if (ret_val) | |
747 | return ret_val; | |
748 | /* Commit the changes. */ | |
6b598e1e | 749 | ret_val = phy->ops.commit(hw); |
885fe7be MV |
750 | if (ret_val) { |
751 | e_dbg("Error committing the PHY changes\n"); | |
752 | return ret_val; | |
753 | } | |
754 | } | |
755 | ||
97ac8cae | 756 | phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; |
885fe7be | 757 | } |
97ac8cae | 758 | |
bc7f75fa AK |
759 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); |
760 | if (ret_val) | |
761 | return ret_val; | |
762 | ||
4662e82b BA |
763 | if ((phy->type == e1000_phy_m88) && |
764 | (phy->revision < E1000_REVISION_4) && | |
765 | (phy->id != BME1000_E_PHY_ID_R2)) { | |
e921eb1a | 766 | /* Force TX_CLK in the Extended PHY Specific Control Register |
bc7f75fa AK |
767 | * to 25MHz clock. |
768 | */ | |
769 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); | |
770 | if (ret_val) | |
771 | return ret_val; | |
772 | ||
773 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
774 | ||
775 | if ((phy->revision == 2) && | |
776 | (phy->id == M88E1111_I_PHY_ID)) { | |
777 | /* 82573L PHY - set the downshift counter to 5x. */ | |
778 | phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
779 | phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; | |
780 | } else { | |
781 | /* Configure Master and Slave downshift values */ | |
782 | phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | | |
783 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); | |
784 | phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | | |
785 | M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); | |
786 | } | |
787 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
788 | if (ret_val) | |
789 | return ret_val; | |
790 | } | |
791 | ||
4662e82b BA |
792 | if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { |
793 | /* Set PHY page 0, register 29 to 0x0003 */ | |
794 | ret_val = e1e_wphy(hw, 29, 0x0003); | |
795 | if (ret_val) | |
796 | return ret_val; | |
797 | ||
798 | /* Set PHY page 0, register 30 to 0x0000 */ | |
799 | ret_val = e1e_wphy(hw, 30, 0x0000); | |
800 | if (ret_val) | |
801 | return ret_val; | |
802 | } | |
803 | ||
bc7f75fa | 804 | /* Commit the changes. */ |
6b598e1e BA |
805 | if (phy->ops.commit) { |
806 | ret_val = phy->ops.commit(hw); | |
807 | if (ret_val) { | |
808 | e_dbg("Error committing the PHY changes\n"); | |
809 | return ret_val; | |
810 | } | |
a4f58f54 | 811 | } |
bc7f75fa | 812 | |
a4f58f54 | 813 | if (phy->type == e1000_phy_82578) { |
482fed85 | 814 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
a4f58f54 BA |
815 | if (ret_val) |
816 | return ret_val; | |
817 | ||
818 | /* 82578 PHY - set the downshift count to 1x. */ | |
819 | phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; | |
820 | phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; | |
482fed85 | 821 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); |
a4f58f54 BA |
822 | if (ret_val) |
823 | return ret_val; | |
824 | } | |
825 | ||
826 | return 0; | |
bc7f75fa AK |
827 | } |
828 | ||
829 | /** | |
830 | * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link | |
831 | * @hw: pointer to the HW structure | |
832 | * | |
833 | * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for | |
834 | * igp PHY's. | |
835 | **/ | |
836 | s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw) | |
837 | { | |
838 | struct e1000_phy_info *phy = &hw->phy; | |
839 | s32 ret_val; | |
840 | u16 data; | |
841 | ||
842 | ret_val = e1000_phy_hw_reset(hw); | |
843 | if (ret_val) { | |
3bb99fe2 | 844 | e_dbg("Error resetting the PHY.\n"); |
bc7f75fa AK |
845 | return ret_val; |
846 | } | |
847 | ||
e921eb1a | 848 | /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid |
2d9498f3 DG |
849 | * timeout issues when LFS is enabled. |
850 | */ | |
851 | msleep(100); | |
bc7f75fa AK |
852 | |
853 | /* disable lplu d0 during driver init */ | |
7de89f05 BA |
854 | if (hw->phy.ops.set_d0_lplu_state) { |
855 | ret_val = hw->phy.ops.set_d0_lplu_state(hw, false); | |
856 | if (ret_val) { | |
857 | e_dbg("Error Disabling LPLU D0\n"); | |
858 | return ret_val; | |
859 | } | |
bc7f75fa AK |
860 | } |
861 | /* Configure mdi-mdix settings */ | |
862 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data); | |
863 | if (ret_val) | |
864 | return ret_val; | |
865 | ||
866 | data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
867 | ||
868 | switch (phy->mdix) { | |
869 | case 1: | |
870 | data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
871 | break; | |
872 | case 2: | |
873 | data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
874 | break; | |
875 | case 0: | |
876 | default: | |
877 | data |= IGP01E1000_PSCR_AUTO_MDIX; | |
878 | break; | |
879 | } | |
880 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data); | |
881 | if (ret_val) | |
882 | return ret_val; | |
883 | ||
884 | /* set auto-master slave resolution settings */ | |
885 | if (hw->mac.autoneg) { | |
e921eb1a | 886 | /* when autonegotiation advertisement is only 1000Mbps then we |
bc7f75fa | 887 | * should disable SmartSpeed and enable Auto MasterSlave |
ad68076e BA |
888 | * resolution as hardware default. |
889 | */ | |
bc7f75fa AK |
890 | if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { |
891 | /* Disable SmartSpeed */ | |
892 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 893 | &data); |
bc7f75fa AK |
894 | if (ret_val) |
895 | return ret_val; | |
896 | ||
897 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
898 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 899 | data); |
bc7f75fa AK |
900 | if (ret_val) |
901 | return ret_val; | |
902 | ||
903 | /* Set auto Master/Slave resolution process */ | |
c2ade1a4 | 904 | ret_val = e1e_rphy(hw, MII_CTRL1000, &data); |
bc7f75fa AK |
905 | if (ret_val) |
906 | return ret_val; | |
907 | ||
c2ade1a4 BA |
908 | data &= ~CTL1000_ENABLE_MASTER; |
909 | ret_val = e1e_wphy(hw, MII_CTRL1000, data); | |
bc7f75fa AK |
910 | if (ret_val) |
911 | return ret_val; | |
912 | } | |
913 | ||
7b9f7e35 | 914 | ret_val = e1000_set_master_slave_mode(hw); |
bc7f75fa AK |
915 | } |
916 | ||
917 | return ret_val; | |
918 | } | |
919 | ||
920 | /** | |
921 | * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation | |
922 | * @hw: pointer to the HW structure | |
923 | * | |
924 | * Reads the MII auto-neg advertisement register and/or the 1000T control | |
925 | * register and if the PHY is already setup for auto-negotiation, then | |
926 | * return successful. Otherwise, setup advertisement and flow control to | |
927 | * the appropriate values for the wanted auto-negotiation. | |
928 | **/ | |
929 | static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) | |
930 | { | |
931 | struct e1000_phy_info *phy = &hw->phy; | |
932 | s32 ret_val; | |
933 | u16 mii_autoneg_adv_reg; | |
934 | u16 mii_1000t_ctrl_reg = 0; | |
935 | ||
936 | phy->autoneg_advertised &= phy->autoneg_mask; | |
937 | ||
938 | /* Read the MII Auto-Neg Advertisement Register (Address 4). */ | |
c2ade1a4 | 939 | ret_val = e1e_rphy(hw, MII_ADVERTISE, &mii_autoneg_adv_reg); |
bc7f75fa AK |
940 | if (ret_val) |
941 | return ret_val; | |
942 | ||
943 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) { | |
944 | /* Read the MII 1000Base-T Control Register (Address 9). */ | |
c2ade1a4 | 945 | ret_val = e1e_rphy(hw, MII_CTRL1000, &mii_1000t_ctrl_reg); |
bc7f75fa AK |
946 | if (ret_val) |
947 | return ret_val; | |
948 | } | |
949 | ||
e921eb1a | 950 | /* Need to parse both autoneg_advertised and fc and set up |
bc7f75fa AK |
951 | * the appropriate PHY registers. First we will parse for |
952 | * autoneg_advertised software override. Since we can advertise | |
953 | * a plethora of combinations, we need to check each bit | |
954 | * individually. | |
955 | */ | |
956 | ||
e921eb1a | 957 | /* First we clear all the 10/100 mb speed bits in the Auto-Neg |
bc7f75fa AK |
958 | * Advertisement Register (Address 4) and the 1000 mb speed bits in |
959 | * the 1000Base-T Control Register (Address 9). | |
960 | */ | |
c2ade1a4 BA |
961 | mii_autoneg_adv_reg &= ~(ADVERTISE_100FULL | |
962 | ADVERTISE_100HALF | | |
963 | ADVERTISE_10FULL | ADVERTISE_10HALF); | |
964 | mii_1000t_ctrl_reg &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); | |
bc7f75fa | 965 | |
3bb99fe2 | 966 | e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised); |
bc7f75fa AK |
967 | |
968 | /* Do we want to advertise 10 Mb Half Duplex? */ | |
969 | if (phy->autoneg_advertised & ADVERTISE_10_HALF) { | |
3bb99fe2 | 970 | e_dbg("Advertise 10mb Half duplex\n"); |
c2ade1a4 | 971 | mii_autoneg_adv_reg |= ADVERTISE_10HALF; |
bc7f75fa AK |
972 | } |
973 | ||
974 | /* Do we want to advertise 10 Mb Full Duplex? */ | |
975 | if (phy->autoneg_advertised & ADVERTISE_10_FULL) { | |
3bb99fe2 | 976 | e_dbg("Advertise 10mb Full duplex\n"); |
c2ade1a4 | 977 | mii_autoneg_adv_reg |= ADVERTISE_10FULL; |
bc7f75fa AK |
978 | } |
979 | ||
980 | /* Do we want to advertise 100 Mb Half Duplex? */ | |
981 | if (phy->autoneg_advertised & ADVERTISE_100_HALF) { | |
3bb99fe2 | 982 | e_dbg("Advertise 100mb Half duplex\n"); |
c2ade1a4 | 983 | mii_autoneg_adv_reg |= ADVERTISE_100HALF; |
bc7f75fa AK |
984 | } |
985 | ||
986 | /* Do we want to advertise 100 Mb Full Duplex? */ | |
987 | if (phy->autoneg_advertised & ADVERTISE_100_FULL) { | |
3bb99fe2 | 988 | e_dbg("Advertise 100mb Full duplex\n"); |
c2ade1a4 | 989 | mii_autoneg_adv_reg |= ADVERTISE_100FULL; |
bc7f75fa AK |
990 | } |
991 | ||
992 | /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ | |
993 | if (phy->autoneg_advertised & ADVERTISE_1000_HALF) | |
3bb99fe2 | 994 | e_dbg("Advertise 1000mb Half duplex request denied!\n"); |
bc7f75fa AK |
995 | |
996 | /* Do we want to advertise 1000 Mb Full Duplex? */ | |
997 | if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { | |
3bb99fe2 | 998 | e_dbg("Advertise 1000mb Full duplex\n"); |
c2ade1a4 | 999 | mii_1000t_ctrl_reg |= ADVERTISE_1000FULL; |
bc7f75fa AK |
1000 | } |
1001 | ||
e921eb1a | 1002 | /* Check for a software override of the flow control settings, and |
bc7f75fa AK |
1003 | * setup the PHY advertisement registers accordingly. If |
1004 | * auto-negotiation is enabled, then software will have to set the | |
1005 | * "PAUSE" bits to the correct value in the Auto-Negotiation | |
c2ade1a4 | 1006 | * Advertisement Register (MII_ADVERTISE) and re-start auto- |
bc7f75fa AK |
1007 | * negotiation. |
1008 | * | |
1009 | * The possible values of the "fc" parameter are: | |
1010 | * 0: Flow control is completely disabled | |
1011 | * 1: Rx flow control is enabled (we can receive pause frames | |
3d3a1676 | 1012 | * but not send pause frames). |
bc7f75fa | 1013 | * 2: Tx flow control is enabled (we can send pause frames |
3d3a1676 | 1014 | * but we do not support receiving pause frames). |
ad68076e | 1015 | * 3: Both Rx and Tx flow control (symmetric) are enabled. |
bc7f75fa | 1016 | * other: No software override. The flow control configuration |
3d3a1676 | 1017 | * in the EEPROM is used. |
bc7f75fa | 1018 | */ |
5c48ef3e | 1019 | switch (hw->fc.current_mode) { |
bc7f75fa | 1020 | case e1000_fc_none: |
e921eb1a | 1021 | /* Flow control (Rx & Tx) is completely disabled by a |
bc7f75fa AK |
1022 | * software over-ride. |
1023 | */ | |
c2ade1a4 BA |
1024 | mii_autoneg_adv_reg &= |
1025 | ~(ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); | |
bc7f75fa AK |
1026 | break; |
1027 | case e1000_fc_rx_pause: | |
e921eb1a | 1028 | /* Rx Flow control is enabled, and Tx Flow control is |
bc7f75fa | 1029 | * disabled, by a software over-ride. |
ad68076e BA |
1030 | * |
1031 | * Since there really isn't a way to advertise that we are | |
1032 | * capable of Rx Pause ONLY, we will advertise that we | |
1033 | * support both symmetric and asymmetric Rx PAUSE. Later | |
bc7f75fa AK |
1034 | * (in e1000e_config_fc_after_link_up) we will disable the |
1035 | * hw's ability to send PAUSE frames. | |
1036 | */ | |
c2ade1a4 BA |
1037 | mii_autoneg_adv_reg |= |
1038 | (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); | |
bc7f75fa AK |
1039 | break; |
1040 | case e1000_fc_tx_pause: | |
e921eb1a | 1041 | /* Tx Flow control is enabled, and Rx Flow control is |
bc7f75fa AK |
1042 | * disabled, by a software over-ride. |
1043 | */ | |
c2ade1a4 BA |
1044 | mii_autoneg_adv_reg |= ADVERTISE_PAUSE_ASYM; |
1045 | mii_autoneg_adv_reg &= ~ADVERTISE_PAUSE_CAP; | |
bc7f75fa AK |
1046 | break; |
1047 | case e1000_fc_full: | |
e921eb1a | 1048 | /* Flow control (both Rx and Tx) is enabled by a software |
bc7f75fa AK |
1049 | * over-ride. |
1050 | */ | |
c2ade1a4 BA |
1051 | mii_autoneg_adv_reg |= |
1052 | (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP); | |
bc7f75fa AK |
1053 | break; |
1054 | default: | |
3bb99fe2 | 1055 | e_dbg("Flow control param set incorrectly\n"); |
7eb61d81 | 1056 | return -E1000_ERR_CONFIG; |
bc7f75fa AK |
1057 | } |
1058 | ||
c2ade1a4 | 1059 | ret_val = e1e_wphy(hw, MII_ADVERTISE, mii_autoneg_adv_reg); |
bc7f75fa AK |
1060 | if (ret_val) |
1061 | return ret_val; | |
1062 | ||
3bb99fe2 | 1063 | e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); |
bc7f75fa | 1064 | |
b1cdfead | 1065 | if (phy->autoneg_mask & ADVERTISE_1000_FULL) |
c2ade1a4 | 1066 | ret_val = e1e_wphy(hw, MII_CTRL1000, mii_1000t_ctrl_reg); |
bc7f75fa AK |
1067 | |
1068 | return ret_val; | |
1069 | } | |
1070 | ||
1071 | /** | |
1072 | * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link | |
1073 | * @hw: pointer to the HW structure | |
1074 | * | |
1075 | * Performs initial bounds checking on autoneg advertisement parameter, then | |
1076 | * configure to advertise the full capability. Setup the PHY to autoneg | |
1077 | * and restart the negotiation process between the link partner. If | |
ad68076e | 1078 | * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. |
bc7f75fa AK |
1079 | **/ |
1080 | static s32 e1000_copper_link_autoneg(struct e1000_hw *hw) | |
1081 | { | |
1082 | struct e1000_phy_info *phy = &hw->phy; | |
1083 | s32 ret_val; | |
1084 | u16 phy_ctrl; | |
1085 | ||
e921eb1a | 1086 | /* Perform some bounds checking on the autoneg advertisement |
bc7f75fa AK |
1087 | * parameter. |
1088 | */ | |
1089 | phy->autoneg_advertised &= phy->autoneg_mask; | |
1090 | ||
e921eb1a | 1091 | /* If autoneg_advertised is zero, we assume it was not defaulted |
bc7f75fa AK |
1092 | * by the calling code so we set to advertise full capability. |
1093 | */ | |
04499ec4 | 1094 | if (!phy->autoneg_advertised) |
bc7f75fa AK |
1095 | phy->autoneg_advertised = phy->autoneg_mask; |
1096 | ||
3bb99fe2 | 1097 | e_dbg("Reconfiguring auto-neg advertisement params\n"); |
bc7f75fa AK |
1098 | ret_val = e1000_phy_setup_autoneg(hw); |
1099 | if (ret_val) { | |
3bb99fe2 | 1100 | e_dbg("Error Setting up Auto-Negotiation\n"); |
bc7f75fa AK |
1101 | return ret_val; |
1102 | } | |
3bb99fe2 | 1103 | e_dbg("Restarting Auto-Neg\n"); |
bc7f75fa | 1104 | |
e921eb1a | 1105 | /* Restart auto-negotiation by setting the Auto Neg Enable bit and |
bc7f75fa AK |
1106 | * the Auto Neg Restart bit in the PHY control register. |
1107 | */ | |
c2ade1a4 | 1108 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); |
bc7f75fa AK |
1109 | if (ret_val) |
1110 | return ret_val; | |
1111 | ||
c2ade1a4 BA |
1112 | phy_ctrl |= (BMCR_ANENABLE | BMCR_ANRESTART); |
1113 | ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); | |
bc7f75fa AK |
1114 | if (ret_val) |
1115 | return ret_val; | |
1116 | ||
e921eb1a | 1117 | /* Does the user want to wait for Auto-Neg to complete here, or |
bc7f75fa AK |
1118 | * check at a later time (for example, callback routine). |
1119 | */ | |
318a94d6 | 1120 | if (phy->autoneg_wait_to_complete) { |
bc7f75fa AK |
1121 | ret_val = e1000_wait_autoneg(hw); |
1122 | if (ret_val) { | |
434f1392 | 1123 | e_dbg("Error while waiting for autoneg to complete\n"); |
bc7f75fa AK |
1124 | return ret_val; |
1125 | } | |
1126 | } | |
1127 | ||
f92518dd | 1128 | hw->mac.get_link_status = true; |
bc7f75fa AK |
1129 | |
1130 | return ret_val; | |
1131 | } | |
1132 | ||
1133 | /** | |
1134 | * e1000e_setup_copper_link - Configure copper link settings | |
1135 | * @hw: pointer to the HW structure | |
1136 | * | |
1137 | * Calls the appropriate function to configure the link for auto-neg or forced | |
1138 | * speed and duplex. Then we check for link, once link is established calls | |
1139 | * to configure collision distance and flow control are called. If link is | |
1140 | * not established, we return -E1000_ERR_PHY (-2). | |
1141 | **/ | |
1142 | s32 e1000e_setup_copper_link(struct e1000_hw *hw) | |
1143 | { | |
1144 | s32 ret_val; | |
1145 | bool link; | |
1146 | ||
1147 | if (hw->mac.autoneg) { | |
e921eb1a | 1148 | /* Setup autoneg and flow control advertisement and perform |
ad68076e BA |
1149 | * autonegotiation. |
1150 | */ | |
bc7f75fa AK |
1151 | ret_val = e1000_copper_link_autoneg(hw); |
1152 | if (ret_val) | |
1153 | return ret_val; | |
1154 | } else { | |
e921eb1a | 1155 | /* PHY will be set to 10H, 10F, 100H or 100F |
ad68076e BA |
1156 | * depending on user settings. |
1157 | */ | |
3bb99fe2 | 1158 | e_dbg("Forcing Speed and Duplex\n"); |
c2c6629b | 1159 | ret_val = hw->phy.ops.force_speed_duplex(hw); |
bc7f75fa | 1160 | if (ret_val) { |
3bb99fe2 | 1161 | e_dbg("Error Forcing Speed and Duplex\n"); |
bc7f75fa AK |
1162 | return ret_val; |
1163 | } | |
1164 | } | |
1165 | ||
e921eb1a | 1166 | /* Check link status. Wait up to 100 microseconds for link to become |
bc7f75fa AK |
1167 | * valid. |
1168 | */ | |
3d3a1676 BA |
1169 | ret_val = e1000e_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, |
1170 | &link); | |
bc7f75fa AK |
1171 | if (ret_val) |
1172 | return ret_val; | |
1173 | ||
1174 | if (link) { | |
3bb99fe2 | 1175 | e_dbg("Valid link established!!!\n"); |
57cde763 | 1176 | hw->mac.ops.config_collision_dist(hw); |
bc7f75fa AK |
1177 | ret_val = e1000e_config_fc_after_link_up(hw); |
1178 | } else { | |
3bb99fe2 | 1179 | e_dbg("Unable to establish link!!!\n"); |
bc7f75fa AK |
1180 | } |
1181 | ||
1182 | return ret_val; | |
1183 | } | |
1184 | ||
1185 | /** | |
1186 | * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY | |
1187 | * @hw: pointer to the HW structure | |
1188 | * | |
1189 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1190 | * auto-crossover to force MDI manually. Waits for link and returns | |
1191 | * successful if link up is successful, else -E1000_ERR_PHY (-2). | |
1192 | **/ | |
1193 | s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw) | |
1194 | { | |
1195 | struct e1000_phy_info *phy = &hw->phy; | |
1196 | s32 ret_val; | |
1197 | u16 phy_data; | |
1198 | bool link; | |
1199 | ||
c2ade1a4 | 1200 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
bc7f75fa AK |
1201 | if (ret_val) |
1202 | return ret_val; | |
1203 | ||
1204 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
1205 | ||
c2ade1a4 | 1206 | ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
bc7f75fa AK |
1207 | if (ret_val) |
1208 | return ret_val; | |
1209 | ||
e921eb1a | 1210 | /* Clear Auto-Crossover to force MDI manually. IGP requires MDI |
bc7f75fa AK |
1211 | * forced whenever speed and duplex are forced. |
1212 | */ | |
1213 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); | |
1214 | if (ret_val) | |
1215 | return ret_val; | |
1216 | ||
1217 | phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; | |
1218 | phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; | |
1219 | ||
1220 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); | |
1221 | if (ret_val) | |
1222 | return ret_val; | |
1223 | ||
3bb99fe2 | 1224 | e_dbg("IGP PSCR: %X\n", phy_data); |
bc7f75fa AK |
1225 | |
1226 | udelay(1); | |
1227 | ||
318a94d6 | 1228 | if (phy->autoneg_wait_to_complete) { |
3bb99fe2 | 1229 | e_dbg("Waiting for forced speed/duplex link on IGP phy.\n"); |
bc7f75fa | 1230 | |
3d3a1676 BA |
1231 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
1232 | 100000, &link); | |
bc7f75fa AK |
1233 | if (ret_val) |
1234 | return ret_val; | |
1235 | ||
1236 | if (!link) | |
3bb99fe2 | 1237 | e_dbg("Link taking longer than expected.\n"); |
bc7f75fa AK |
1238 | |
1239 | /* Try once more */ | |
3d3a1676 BA |
1240 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
1241 | 100000, &link); | |
bc7f75fa AK |
1242 | } |
1243 | ||
1244 | return ret_val; | |
1245 | } | |
1246 | ||
1247 | /** | |
1248 | * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY | |
1249 | * @hw: pointer to the HW structure | |
1250 | * | |
1251 | * Calls the PHY setup function to force speed and duplex. Clears the | |
1252 | * auto-crossover to force MDI manually. Resets the PHY to commit the | |
1253 | * changes. If time expires while waiting for link up, we reset the DSP. | |
ad68076e | 1254 | * After reset, TX_CLK and CRS on Tx must be set. Return successful upon |
bc7f75fa AK |
1255 | * successful completion, else return corresponding error code. |
1256 | **/ | |
1257 | s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw) | |
1258 | { | |
1259 | struct e1000_phy_info *phy = &hw->phy; | |
1260 | s32 ret_val; | |
1261 | u16 phy_data; | |
1262 | bool link; | |
1263 | ||
e921eb1a | 1264 | /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI |
bc7f75fa AK |
1265 | * forced whenever speed and duplex are forced. |
1266 | */ | |
1267 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1268 | if (ret_val) | |
1269 | return ret_val; | |
1270 | ||
1271 | phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; | |
1272 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1273 | if (ret_val) | |
1274 | return ret_val; | |
1275 | ||
3bb99fe2 | 1276 | e_dbg("M88E1000 PSCR: %X\n", phy_data); |
bc7f75fa | 1277 | |
c2ade1a4 | 1278 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
bc7f75fa AK |
1279 | if (ret_val) |
1280 | return ret_val; | |
1281 | ||
1282 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
1283 | ||
c2ade1a4 | 1284 | ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
bc7f75fa AK |
1285 | if (ret_val) |
1286 | return ret_val; | |
1287 | ||
5aa49c82 | 1288 | /* Reset the phy to commit changes. */ |
6b598e1e BA |
1289 | if (hw->phy.ops.commit) { |
1290 | ret_val = hw->phy.ops.commit(hw); | |
1291 | if (ret_val) | |
1292 | return ret_val; | |
1293 | } | |
bc7f75fa | 1294 | |
318a94d6 | 1295 | if (phy->autoneg_wait_to_complete) { |
3bb99fe2 | 1296 | e_dbg("Waiting for forced speed/duplex link on M88 phy.\n"); |
bc7f75fa AK |
1297 | |
1298 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
1299 | 100000, &link); | |
1300 | if (ret_val) | |
1301 | return ret_val; | |
1302 | ||
1303 | if (!link) { | |
0be84010 BA |
1304 | if (hw->phy.type != e1000_phy_m88) { |
1305 | e_dbg("Link taking longer than expected.\n"); | |
1306 | } else { | |
e921eb1a | 1307 | /* We didn't get link. |
0be84010 BA |
1308 | * Reset the DSP and cross our fingers. |
1309 | */ | |
482fed85 BA |
1310 | ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, |
1311 | 0x001d); | |
0be84010 BA |
1312 | if (ret_val) |
1313 | return ret_val; | |
1314 | ret_val = e1000e_phy_reset_dsp(hw); | |
1315 | if (ret_val) | |
1316 | return ret_val; | |
1317 | } | |
bc7f75fa AK |
1318 | } |
1319 | ||
1320 | /* Try once more */ | |
1321 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, | |
1322 | 100000, &link); | |
1323 | if (ret_val) | |
1324 | return ret_val; | |
1325 | } | |
1326 | ||
0be84010 BA |
1327 | if (hw->phy.type != e1000_phy_m88) |
1328 | return 0; | |
1329 | ||
bc7f75fa AK |
1330 | ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); |
1331 | if (ret_val) | |
1332 | return ret_val; | |
1333 | ||
e921eb1a | 1334 | /* Resetting the phy means we need to re-force TX_CLK in the |
bc7f75fa AK |
1335 | * Extended PHY Specific Control Register to 25MHz clock from |
1336 | * the reset value of 2.5MHz. | |
1337 | */ | |
1338 | phy_data |= M88E1000_EPSCR_TX_CLK_25; | |
1339 | ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); | |
1340 | if (ret_val) | |
1341 | return ret_val; | |
1342 | ||
e921eb1a | 1343 | /* In addition, we must re-enable CRS on Tx for both half and full |
bc7f75fa AK |
1344 | * duplex. |
1345 | */ | |
1346 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1347 | if (ret_val) | |
1348 | return ret_val; | |
1349 | ||
1350 | phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; | |
1351 | ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data); | |
1352 | ||
1353 | return ret_val; | |
1354 | } | |
1355 | ||
0be84010 BA |
1356 | /** |
1357 | * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex | |
1358 | * @hw: pointer to the HW structure | |
1359 | * | |
1360 | * Forces the speed and duplex settings of the PHY. | |
1361 | * This is a function pointer entry point only called by | |
1362 | * PHY setup routines. | |
1363 | **/ | |
1364 | s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) | |
1365 | { | |
1366 | struct e1000_phy_info *phy = &hw->phy; | |
1367 | s32 ret_val; | |
1368 | u16 data; | |
1369 | bool link; | |
1370 | ||
c2ade1a4 | 1371 | ret_val = e1e_rphy(hw, MII_BMCR, &data); |
0be84010 | 1372 | if (ret_val) |
5015e53a | 1373 | return ret_val; |
0be84010 BA |
1374 | |
1375 | e1000e_phy_force_speed_duplex_setup(hw, &data); | |
1376 | ||
c2ade1a4 | 1377 | ret_val = e1e_wphy(hw, MII_BMCR, data); |
0be84010 | 1378 | if (ret_val) |
5015e53a | 1379 | return ret_val; |
0be84010 BA |
1380 | |
1381 | /* Disable MDI-X support for 10/100 */ | |
1382 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
1383 | if (ret_val) | |
5015e53a | 1384 | return ret_val; |
0be84010 BA |
1385 | |
1386 | data &= ~IFE_PMC_AUTO_MDIX; | |
1387 | data &= ~IFE_PMC_FORCE_MDIX; | |
1388 | ||
1389 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data); | |
1390 | if (ret_val) | |
5015e53a | 1391 | return ret_val; |
0be84010 BA |
1392 | |
1393 | e_dbg("IFE PMC: %X\n", data); | |
1394 | ||
1395 | udelay(1); | |
1396 | ||
1397 | if (phy->autoneg_wait_to_complete) { | |
1398 | e_dbg("Waiting for forced speed/duplex link on IFE phy.\n"); | |
1399 | ||
3d3a1676 BA |
1400 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
1401 | 100000, &link); | |
0be84010 | 1402 | if (ret_val) |
5015e53a | 1403 | return ret_val; |
0be84010 BA |
1404 | |
1405 | if (!link) | |
1406 | e_dbg("Link taking longer than expected.\n"); | |
1407 | ||
1408 | /* Try once more */ | |
3d3a1676 BA |
1409 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
1410 | 100000, &link); | |
0be84010 | 1411 | if (ret_val) |
5015e53a | 1412 | return ret_val; |
0be84010 BA |
1413 | } |
1414 | ||
5015e53a | 1415 | return 0; |
0be84010 BA |
1416 | } |
1417 | ||
bc7f75fa AK |
1418 | /** |
1419 | * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex | |
1420 | * @hw: pointer to the HW structure | |
c2ade1a4 | 1421 | * @phy_ctrl: pointer to current value of MII_BMCR |
bc7f75fa AK |
1422 | * |
1423 | * Forces speed and duplex on the PHY by doing the following: disable flow | |
1424 | * control, force speed/duplex on the MAC, disable auto speed detection, | |
1425 | * disable auto-negotiation, configure duplex, configure speed, configure | |
1426 | * the collision distance, write configuration to CTRL register. The | |
c2ade1a4 | 1427 | * caller must write to the MII_BMCR register for these settings to |
bc7f75fa AK |
1428 | * take affect. |
1429 | **/ | |
1430 | void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) | |
1431 | { | |
1432 | struct e1000_mac_info *mac = &hw->mac; | |
1433 | u32 ctrl; | |
1434 | ||
1435 | /* Turn off flow control when forcing speed/duplex */ | |
5c48ef3e | 1436 | hw->fc.current_mode = e1000_fc_none; |
bc7f75fa AK |
1437 | |
1438 | /* Force speed/duplex on the mac */ | |
1439 | ctrl = er32(CTRL); | |
1440 | ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
1441 | ctrl &= ~E1000_CTRL_SPD_SEL; | |
1442 | ||
1443 | /* Disable Auto Speed Detection */ | |
1444 | ctrl &= ~E1000_CTRL_ASDE; | |
1445 | ||
1446 | /* Disable autoneg on the phy */ | |
c2ade1a4 | 1447 | *phy_ctrl &= ~BMCR_ANENABLE; |
bc7f75fa AK |
1448 | |
1449 | /* Forcing Full or Half Duplex? */ | |
1450 | if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { | |
1451 | ctrl &= ~E1000_CTRL_FD; | |
c2ade1a4 | 1452 | *phy_ctrl &= ~BMCR_FULLDPLX; |
3bb99fe2 | 1453 | e_dbg("Half Duplex\n"); |
bc7f75fa AK |
1454 | } else { |
1455 | ctrl |= E1000_CTRL_FD; | |
c2ade1a4 | 1456 | *phy_ctrl |= BMCR_FULLDPLX; |
3bb99fe2 | 1457 | e_dbg("Full Duplex\n"); |
bc7f75fa AK |
1458 | } |
1459 | ||
1460 | /* Forcing 10mb or 100mb? */ | |
1461 | if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { | |
1462 | ctrl |= E1000_CTRL_SPD_100; | |
c2ade1a4 BA |
1463 | *phy_ctrl |= BMCR_SPEED100; |
1464 | *phy_ctrl &= ~BMCR_SPEED1000; | |
3bb99fe2 | 1465 | e_dbg("Forcing 100mb\n"); |
bc7f75fa AK |
1466 | } else { |
1467 | ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
c2ade1a4 | 1468 | *phy_ctrl &= ~(BMCR_SPEED1000 | BMCR_SPEED100); |
3bb99fe2 | 1469 | e_dbg("Forcing 10mb\n"); |
bc7f75fa AK |
1470 | } |
1471 | ||
57cde763 | 1472 | hw->mac.ops.config_collision_dist(hw); |
bc7f75fa AK |
1473 | |
1474 | ew32(CTRL, ctrl); | |
1475 | } | |
1476 | ||
1477 | /** | |
1478 | * e1000e_set_d3_lplu_state - Sets low power link up state for D3 | |
1479 | * @hw: pointer to the HW structure | |
1480 | * @active: boolean used to enable/disable lplu | |
1481 | * | |
1482 | * Success returns 0, Failure returns 1 | |
1483 | * | |
1484 | * The low power link up (lplu) state is set to the power management level D3 | |
1485 | * and SmartSpeed is disabled when active is true, else clear lplu for D3 | |
1486 | * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU | |
1487 | * is used during Dx states where the power conservation is most important. | |
1488 | * During driver activity, SmartSpeed should be enabled so performance is | |
1489 | * maintained. | |
1490 | **/ | |
1491 | s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active) | |
1492 | { | |
1493 | struct e1000_phy_info *phy = &hw->phy; | |
1494 | s32 ret_val; | |
1495 | u16 data; | |
1496 | ||
1497 | ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data); | |
1498 | if (ret_val) | |
1499 | return ret_val; | |
1500 | ||
1501 | if (!active) { | |
1502 | data &= ~IGP02E1000_PM_D3_LPLU; | |
2d9498f3 | 1503 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); |
bc7f75fa AK |
1504 | if (ret_val) |
1505 | return ret_val; | |
e921eb1a | 1506 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
bc7f75fa AK |
1507 | * during Dx states where the power conservation is most |
1508 | * important. During driver activity we should enable | |
ad68076e BA |
1509 | * SmartSpeed, so performance is maintained. |
1510 | */ | |
bc7f75fa AK |
1511 | if (phy->smart_speed == e1000_smart_speed_on) { |
1512 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1513 | &data); |
bc7f75fa AK |
1514 | if (ret_val) |
1515 | return ret_val; | |
1516 | ||
1517 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
1518 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1519 | data); |
bc7f75fa AK |
1520 | if (ret_val) |
1521 | return ret_val; | |
1522 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
1523 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1524 | &data); |
bc7f75fa AK |
1525 | if (ret_val) |
1526 | return ret_val; | |
1527 | ||
1528 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1529 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 1530 | data); |
bc7f75fa AK |
1531 | if (ret_val) |
1532 | return ret_val; | |
1533 | } | |
1534 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
1535 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
1536 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
1537 | data |= IGP02E1000_PM_D3_LPLU; | |
1538 | ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data); | |
1539 | if (ret_val) | |
1540 | return ret_val; | |
1541 | ||
1542 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
1543 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
1544 | if (ret_val) | |
1545 | return ret_val; | |
1546 | ||
1547 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
1548 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
1549 | } | |
1550 | ||
1551 | return ret_val; | |
1552 | } | |
1553 | ||
1554 | /** | |
489815ce | 1555 | * e1000e_check_downshift - Checks whether a downshift in speed occurred |
bc7f75fa AK |
1556 | * @hw: pointer to the HW structure |
1557 | * | |
1558 | * Success returns 0, Failure returns 1 | |
1559 | * | |
1560 | * A downshift is detected by querying the PHY link health. | |
1561 | **/ | |
1562 | s32 e1000e_check_downshift(struct e1000_hw *hw) | |
1563 | { | |
1564 | struct e1000_phy_info *phy = &hw->phy; | |
1565 | s32 ret_val; | |
1566 | u16 phy_data, offset, mask; | |
1567 | ||
1568 | switch (phy->type) { | |
1569 | case e1000_phy_m88: | |
1570 | case e1000_phy_gg82563: | |
07f025e6 | 1571 | case e1000_phy_bm: |
a4f58f54 | 1572 | case e1000_phy_82578: |
bc7f75fa AK |
1573 | offset = M88E1000_PHY_SPEC_STATUS; |
1574 | mask = M88E1000_PSSR_DOWNSHIFT; | |
1575 | break; | |
1576 | case e1000_phy_igp_2: | |
1577 | case e1000_phy_igp_3: | |
1578 | offset = IGP01E1000_PHY_LINK_HEALTH; | |
1579 | mask = IGP01E1000_PLHR_SS_DOWNGRADE; | |
1580 | break; | |
1581 | default: | |
1582 | /* speed downshift not supported */ | |
564ea9bb | 1583 | phy->speed_downgraded = false; |
bc7f75fa AK |
1584 | return 0; |
1585 | } | |
1586 | ||
1587 | ret_val = e1e_rphy(hw, offset, &phy_data); | |
1588 | ||
1589 | if (!ret_val) | |
04499ec4 | 1590 | phy->speed_downgraded = !!(phy_data & mask); |
bc7f75fa AK |
1591 | |
1592 | return ret_val; | |
1593 | } | |
1594 | ||
1595 | /** | |
1596 | * e1000_check_polarity_m88 - Checks the polarity. | |
1597 | * @hw: pointer to the HW structure | |
1598 | * | |
1599 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1600 | * | |
1601 | * Polarity is determined based on the PHY specific status register. | |
1602 | **/ | |
0be84010 | 1603 | s32 e1000_check_polarity_m88(struct e1000_hw *hw) |
bc7f75fa AK |
1604 | { |
1605 | struct e1000_phy_info *phy = &hw->phy; | |
1606 | s32 ret_val; | |
1607 | u16 data; | |
1608 | ||
1609 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data); | |
1610 | ||
1611 | if (!ret_val) | |
1612 | phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY) | |
1613 | ? e1000_rev_polarity_reversed | |
1614 | : e1000_rev_polarity_normal; | |
1615 | ||
1616 | return ret_val; | |
1617 | } | |
1618 | ||
1619 | /** | |
1620 | * e1000_check_polarity_igp - Checks the polarity. | |
1621 | * @hw: pointer to the HW structure | |
1622 | * | |
1623 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1624 | * | |
1625 | * Polarity is determined based on the PHY port status register, and the | |
1626 | * current speed (since there is no polarity at 100Mbps). | |
1627 | **/ | |
0be84010 | 1628 | s32 e1000_check_polarity_igp(struct e1000_hw *hw) |
bc7f75fa AK |
1629 | { |
1630 | struct e1000_phy_info *phy = &hw->phy; | |
1631 | s32 ret_val; | |
1632 | u16 data, offset, mask; | |
1633 | ||
e921eb1a | 1634 | /* Polarity is determined based on the speed of |
ad68076e BA |
1635 | * our connection. |
1636 | */ | |
bc7f75fa AK |
1637 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); |
1638 | if (ret_val) | |
1639 | return ret_val; | |
1640 | ||
1641 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1642 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
1643 | offset = IGP01E1000_PHY_PCS_INIT_REG; | |
1644 | mask = IGP01E1000_PHY_POLARITY_MASK; | |
1645 | } else { | |
e921eb1a | 1646 | /* This really only applies to 10Mbps since |
bc7f75fa AK |
1647 | * there is no polarity for 100Mbps (always 0). |
1648 | */ | |
1649 | offset = IGP01E1000_PHY_PORT_STATUS; | |
1650 | mask = IGP01E1000_PSSR_POLARITY_REVERSED; | |
1651 | } | |
1652 | ||
1653 | ret_val = e1e_rphy(hw, offset, &data); | |
1654 | ||
1655 | if (!ret_val) | |
1656 | phy->cable_polarity = (data & mask) | |
1657 | ? e1000_rev_polarity_reversed | |
1658 | : e1000_rev_polarity_normal; | |
1659 | ||
1660 | return ret_val; | |
1661 | } | |
1662 | ||
0be84010 BA |
1663 | /** |
1664 | * e1000_check_polarity_ife - Check cable polarity for IFE PHY | |
1665 | * @hw: pointer to the HW structure | |
1666 | * | |
1667 | * Polarity is determined on the polarity reversal feature being enabled. | |
1668 | **/ | |
1669 | s32 e1000_check_polarity_ife(struct e1000_hw *hw) | |
1670 | { | |
1671 | struct e1000_phy_info *phy = &hw->phy; | |
1672 | s32 ret_val; | |
1673 | u16 phy_data, offset, mask; | |
1674 | ||
e921eb1a | 1675 | /* Polarity is determined based on the reversal feature being enabled. |
0be84010 BA |
1676 | */ |
1677 | if (phy->polarity_correction) { | |
1678 | offset = IFE_PHY_EXTENDED_STATUS_CONTROL; | |
1679 | mask = IFE_PESC_POLARITY_REVERSED; | |
1680 | } else { | |
1681 | offset = IFE_PHY_SPECIAL_CONTROL; | |
1682 | mask = IFE_PSC_FORCE_POLARITY; | |
1683 | } | |
1684 | ||
1685 | ret_val = e1e_rphy(hw, offset, &phy_data); | |
1686 | ||
1687 | if (!ret_val) | |
1688 | phy->cable_polarity = (phy_data & mask) | |
1689 | ? e1000_rev_polarity_reversed | |
1690 | : e1000_rev_polarity_normal; | |
1691 | ||
1692 | return ret_val; | |
1693 | } | |
1694 | ||
bc7f75fa | 1695 | /** |
ad68076e | 1696 | * e1000_wait_autoneg - Wait for auto-neg completion |
bc7f75fa AK |
1697 | * @hw: pointer to the HW structure |
1698 | * | |
1699 | * Waits for auto-negotiation to complete or for the auto-negotiation time | |
1700 | * limit to expire, which ever happens first. | |
1701 | **/ | |
1702 | static s32 e1000_wait_autoneg(struct e1000_hw *hw) | |
1703 | { | |
1704 | s32 ret_val = 0; | |
1705 | u16 i, phy_status; | |
1706 | ||
1707 | /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ | |
1708 | for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { | |
c2ade1a4 | 1709 | ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
bc7f75fa AK |
1710 | if (ret_val) |
1711 | break; | |
c2ade1a4 | 1712 | ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
bc7f75fa AK |
1713 | if (ret_val) |
1714 | break; | |
c2ade1a4 | 1715 | if (phy_status & BMSR_ANEGCOMPLETE) |
bc7f75fa AK |
1716 | break; |
1717 | msleep(100); | |
1718 | } | |
1719 | ||
e921eb1a | 1720 | /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation |
bc7f75fa AK |
1721 | * has completed. |
1722 | */ | |
1723 | return ret_val; | |
1724 | } | |
1725 | ||
1726 | /** | |
1727 | * e1000e_phy_has_link_generic - Polls PHY for link | |
1728 | * @hw: pointer to the HW structure | |
1729 | * @iterations: number of times to poll for link | |
1730 | * @usec_interval: delay between polling attempts | |
1731 | * @success: pointer to whether polling was successful or not | |
1732 | * | |
1733 | * Polls the PHY status register for link, 'iterations' number of times. | |
1734 | **/ | |
1735 | s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, | |
1736 | u32 usec_interval, bool *success) | |
1737 | { | |
1738 | s32 ret_val = 0; | |
1739 | u16 i, phy_status; | |
1740 | ||
1741 | for (i = 0; i < iterations; i++) { | |
c2ade1a4 | 1742 | /* Some PHYs require the MII_BMSR register to be read |
bc7f75fa AK |
1743 | * twice due to the link bit being sticky. No harm doing |
1744 | * it across the board. | |
1745 | */ | |
c2ade1a4 | 1746 | ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
bc7f75fa | 1747 | if (ret_val) |
e921eb1a | 1748 | /* If the first read fails, another entity may have |
906e8d97 BA |
1749 | * ownership of the resources, wait and try again to |
1750 | * see if they have relinquished the resources yet. | |
1751 | */ | |
1752 | udelay(usec_interval); | |
c2ade1a4 | 1753 | ret_val = e1e_rphy(hw, MII_BMSR, &phy_status); |
bc7f75fa AK |
1754 | if (ret_val) |
1755 | break; | |
c2ade1a4 | 1756 | if (phy_status & BMSR_LSTATUS) |
bc7f75fa AK |
1757 | break; |
1758 | if (usec_interval >= 1000) | |
1759 | mdelay(usec_interval/1000); | |
1760 | else | |
1761 | udelay(usec_interval); | |
1762 | } | |
1763 | ||
1764 | *success = (i < iterations); | |
1765 | ||
1766 | return ret_val; | |
1767 | } | |
1768 | ||
1769 | /** | |
1770 | * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY | |
1771 | * @hw: pointer to the HW structure | |
1772 | * | |
1773 | * Reads the PHY specific status register to retrieve the cable length | |
1774 | * information. The cable length is determined by averaging the minimum and | |
1775 | * maximum values to get the "average" cable length. The m88 PHY has four | |
1776 | * possible cable length values, which are: | |
1777 | * Register Value Cable Length | |
1778 | * 0 < 50 meters | |
1779 | * 1 50 - 80 meters | |
1780 | * 2 80 - 110 meters | |
1781 | * 3 110 - 140 meters | |
1782 | * 4 > 140 meters | |
1783 | **/ | |
1784 | s32 e1000e_get_cable_length_m88(struct e1000_hw *hw) | |
1785 | { | |
1786 | struct e1000_phy_info *phy = &hw->phy; | |
1787 | s32 ret_val; | |
1788 | u16 phy_data, index; | |
1789 | ||
1790 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
1791 | if (ret_val) | |
5015e53a | 1792 | return ret_val; |
bc7f75fa AK |
1793 | |
1794 | index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> | |
eb656d45 | 1795 | M88E1000_PSSR_CABLE_LENGTH_SHIFT; |
5015e53a BA |
1796 | |
1797 | if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) | |
1798 | return -E1000_ERR_PHY; | |
eb656d45 | 1799 | |
bc7f75fa | 1800 | phy->min_cable_length = e1000_m88_cable_length_table[index]; |
eb656d45 | 1801 | phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; |
bc7f75fa AK |
1802 | |
1803 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1804 | ||
5015e53a | 1805 | return 0; |
bc7f75fa AK |
1806 | } |
1807 | ||
1808 | /** | |
1809 | * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY | |
1810 | * @hw: pointer to the HW structure | |
1811 | * | |
1812 | * The automatic gain control (agc) normalizes the amplitude of the | |
1813 | * received signal, adjusting for the attenuation produced by the | |
489815ce | 1814 | * cable. By reading the AGC registers, which represent the |
5ff5b664 | 1815 | * combination of coarse and fine gain value, the value can be put |
bc7f75fa AK |
1816 | * into a lookup table to obtain the approximate cable length |
1817 | * for each channel. | |
1818 | **/ | |
1819 | s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw) | |
1820 | { | |
1821 | struct e1000_phy_info *phy = &hw->phy; | |
1822 | s32 ret_val; | |
1823 | u16 phy_data, i, agc_value = 0; | |
1824 | u16 cur_agc_index, max_agc_index = 0; | |
1825 | u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; | |
66744500 JK |
1826 | static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { |
1827 | IGP02E1000_PHY_AGC_A, | |
1828 | IGP02E1000_PHY_AGC_B, | |
1829 | IGP02E1000_PHY_AGC_C, | |
1830 | IGP02E1000_PHY_AGC_D | |
1831 | }; | |
bc7f75fa AK |
1832 | |
1833 | /* Read the AGC registers for all channels */ | |
1834 | for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { | |
1835 | ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data); | |
1836 | if (ret_val) | |
1837 | return ret_val; | |
1838 | ||
e921eb1a | 1839 | /* Getting bits 15:9, which represent the combination of |
5ff5b664 | 1840 | * coarse and fine gain values. The result is a number |
bc7f75fa | 1841 | * that can be put into the lookup table to obtain the |
ad68076e BA |
1842 | * approximate cable length. |
1843 | */ | |
bc7f75fa AK |
1844 | cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & |
1845 | IGP02E1000_AGC_LENGTH_MASK; | |
1846 | ||
1847 | /* Array index bound check. */ | |
1848 | if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || | |
1849 | (cur_agc_index == 0)) | |
1850 | return -E1000_ERR_PHY; | |
1851 | ||
1852 | /* Remove min & max AGC values from calculation. */ | |
1853 | if (e1000_igp_2_cable_length_table[min_agc_index] > | |
1854 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1855 | min_agc_index = cur_agc_index; | |
1856 | if (e1000_igp_2_cable_length_table[max_agc_index] < | |
1857 | e1000_igp_2_cable_length_table[cur_agc_index]) | |
1858 | max_agc_index = cur_agc_index; | |
1859 | ||
1860 | agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; | |
1861 | } | |
1862 | ||
1863 | agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + | |
1864 | e1000_igp_2_cable_length_table[max_agc_index]); | |
1865 | agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); | |
1866 | ||
1867 | /* Calculate cable length with the error range of +/- 10 meters. */ | |
1868 | phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ? | |
1869 | (agc_value - IGP02E1000_AGC_RANGE) : 0; | |
1870 | phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; | |
1871 | ||
1872 | phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; | |
1873 | ||
82607255 | 1874 | return 0; |
bc7f75fa AK |
1875 | } |
1876 | ||
1877 | /** | |
1878 | * e1000e_get_phy_info_m88 - Retrieve PHY information | |
1879 | * @hw: pointer to the HW structure | |
1880 | * | |
1881 | * Valid for only copper links. Read the PHY status register (sticky read) | |
1882 | * to verify that link is up. Read the PHY special control register to | |
1883 | * determine the polarity and 10base-T extended distance. Read the PHY | |
1884 | * special status register to determine MDI/MDIx and current speed. If | |
1885 | * speed is 1000, then determine cable length, local and remote receiver. | |
1886 | **/ | |
1887 | s32 e1000e_get_phy_info_m88(struct e1000_hw *hw) | |
1888 | { | |
1889 | struct e1000_phy_info *phy = &hw->phy; | |
1890 | s32 ret_val; | |
1891 | u16 phy_data; | |
1892 | bool link; | |
1893 | ||
0be84010 | 1894 | if (phy->media_type != e1000_media_type_copper) { |
3bb99fe2 | 1895 | e_dbg("Phy info is only valid for copper media\n"); |
bc7f75fa AK |
1896 | return -E1000_ERR_CONFIG; |
1897 | } | |
1898 | ||
1899 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
1900 | if (ret_val) | |
1901 | return ret_val; | |
1902 | ||
1903 | if (!link) { | |
3bb99fe2 | 1904 | e_dbg("Phy info is only valid if link is up\n"); |
bc7f75fa AK |
1905 | return -E1000_ERR_CONFIG; |
1906 | } | |
1907 | ||
1908 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); | |
1909 | if (ret_val) | |
1910 | return ret_val; | |
1911 | ||
04499ec4 BA |
1912 | phy->polarity_correction = !!(phy_data & |
1913 | M88E1000_PSCR_POLARITY_REVERSAL); | |
bc7f75fa AK |
1914 | |
1915 | ret_val = e1000_check_polarity_m88(hw); | |
1916 | if (ret_val) | |
1917 | return ret_val; | |
1918 | ||
1919 | ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); | |
1920 | if (ret_val) | |
1921 | return ret_val; | |
1922 | ||
04499ec4 | 1923 | phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); |
bc7f75fa AK |
1924 | |
1925 | if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { | |
dde3a574 | 1926 | ret_val = hw->phy.ops.get_cable_length(hw); |
bc7f75fa AK |
1927 | if (ret_val) |
1928 | return ret_val; | |
1929 | ||
c2ade1a4 | 1930 | ret_val = e1e_rphy(hw, MII_STAT1000, &phy_data); |
bc7f75fa AK |
1931 | if (ret_val) |
1932 | return ret_val; | |
1933 | ||
c2ade1a4 BA |
1934 | phy->local_rx = (phy_data & LPA_1000LOCALRXOK) |
1935 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
bc7f75fa | 1936 | |
c2ade1a4 BA |
1937 | phy->remote_rx = (phy_data & LPA_1000REMRXOK) |
1938 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
bc7f75fa AK |
1939 | } else { |
1940 | /* Set values to "undefined" */ | |
1941 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
1942 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
1943 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
1944 | } | |
1945 | ||
1946 | return ret_val; | |
1947 | } | |
1948 | ||
1949 | /** | |
1950 | * e1000e_get_phy_info_igp - Retrieve igp PHY information | |
1951 | * @hw: pointer to the HW structure | |
1952 | * | |
1953 | * Read PHY status to determine if link is up. If link is up, then | |
1954 | * set/determine 10base-T extended distance and polarity correction. Read | |
1955 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
1956 | * determine on the cable length, local and remote receiver. | |
1957 | **/ | |
1958 | s32 e1000e_get_phy_info_igp(struct e1000_hw *hw) | |
1959 | { | |
1960 | struct e1000_phy_info *phy = &hw->phy; | |
1961 | s32 ret_val; | |
1962 | u16 data; | |
1963 | bool link; | |
1964 | ||
1965 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
1966 | if (ret_val) | |
1967 | return ret_val; | |
1968 | ||
1969 | if (!link) { | |
3bb99fe2 | 1970 | e_dbg("Phy info is only valid if link is up\n"); |
bc7f75fa AK |
1971 | return -E1000_ERR_CONFIG; |
1972 | } | |
1973 | ||
564ea9bb | 1974 | phy->polarity_correction = true; |
bc7f75fa AK |
1975 | |
1976 | ret_val = e1000_check_polarity_igp(hw); | |
1977 | if (ret_val) | |
1978 | return ret_val; | |
1979 | ||
1980 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data); | |
1981 | if (ret_val) | |
1982 | return ret_val; | |
1983 | ||
04499ec4 | 1984 | phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); |
bc7f75fa AK |
1985 | |
1986 | if ((data & IGP01E1000_PSSR_SPEED_MASK) == | |
1987 | IGP01E1000_PSSR_SPEED_1000MBPS) { | |
dde3a574 | 1988 | ret_val = phy->ops.get_cable_length(hw); |
bc7f75fa AK |
1989 | if (ret_val) |
1990 | return ret_val; | |
1991 | ||
c2ade1a4 | 1992 | ret_val = e1e_rphy(hw, MII_STAT1000, &data); |
bc7f75fa AK |
1993 | if (ret_val) |
1994 | return ret_val; | |
1995 | ||
c2ade1a4 BA |
1996 | phy->local_rx = (data & LPA_1000LOCALRXOK) |
1997 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
bc7f75fa | 1998 | |
c2ade1a4 BA |
1999 | phy->remote_rx = (data & LPA_1000REMRXOK) |
2000 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
bc7f75fa AK |
2001 | } else { |
2002 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
2003 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
2004 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
2005 | } | |
2006 | ||
2007 | return ret_val; | |
2008 | } | |
2009 | ||
0be84010 BA |
2010 | /** |
2011 | * e1000_get_phy_info_ife - Retrieves various IFE PHY states | |
2012 | * @hw: pointer to the HW structure | |
2013 | * | |
2014 | * Populates "phy" structure with various feature states. | |
2015 | **/ | |
2016 | s32 e1000_get_phy_info_ife(struct e1000_hw *hw) | |
2017 | { | |
2018 | struct e1000_phy_info *phy = &hw->phy; | |
2019 | s32 ret_val; | |
2020 | u16 data; | |
2021 | bool link; | |
2022 | ||
2023 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
2024 | if (ret_val) | |
5015e53a | 2025 | return ret_val; |
0be84010 BA |
2026 | |
2027 | if (!link) { | |
2028 | e_dbg("Phy info is only valid if link is up\n"); | |
5015e53a | 2029 | return -E1000_ERR_CONFIG; |
0be84010 BA |
2030 | } |
2031 | ||
2032 | ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data); | |
2033 | if (ret_val) | |
5015e53a | 2034 | return ret_val; |
04499ec4 | 2035 | phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); |
0be84010 BA |
2036 | |
2037 | if (phy->polarity_correction) { | |
2038 | ret_val = e1000_check_polarity_ife(hw); | |
2039 | if (ret_val) | |
5015e53a | 2040 | return ret_val; |
0be84010 BA |
2041 | } else { |
2042 | /* Polarity is forced */ | |
2043 | phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY) | |
2044 | ? e1000_rev_polarity_reversed | |
2045 | : e1000_rev_polarity_normal; | |
2046 | } | |
2047 | ||
2048 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data); | |
2049 | if (ret_val) | |
5015e53a | 2050 | return ret_val; |
0be84010 | 2051 | |
04499ec4 | 2052 | phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); |
0be84010 BA |
2053 | |
2054 | /* The following parameters are undefined for 10/100 operation. */ | |
2055 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
2056 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
2057 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
2058 | ||
5015e53a | 2059 | return 0; |
0be84010 BA |
2060 | } |
2061 | ||
bc7f75fa AK |
2062 | /** |
2063 | * e1000e_phy_sw_reset - PHY software reset | |
2064 | * @hw: pointer to the HW structure | |
2065 | * | |
2066 | * Does a software reset of the PHY by reading the PHY control register and | |
2067 | * setting/write the control register reset bit to the PHY. | |
2068 | **/ | |
2069 | s32 e1000e_phy_sw_reset(struct e1000_hw *hw) | |
2070 | { | |
2071 | s32 ret_val; | |
2072 | u16 phy_ctrl; | |
2073 | ||
c2ade1a4 | 2074 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_ctrl); |
bc7f75fa AK |
2075 | if (ret_val) |
2076 | return ret_val; | |
2077 | ||
c2ade1a4 BA |
2078 | phy_ctrl |= BMCR_RESET; |
2079 | ret_val = e1e_wphy(hw, MII_BMCR, phy_ctrl); | |
bc7f75fa AK |
2080 | if (ret_val) |
2081 | return ret_val; | |
2082 | ||
2083 | udelay(1); | |
2084 | ||
2085 | return ret_val; | |
2086 | } | |
2087 | ||
2088 | /** | |
2089 | * e1000e_phy_hw_reset_generic - PHY hardware reset | |
2090 | * @hw: pointer to the HW structure | |
2091 | * | |
2092 | * Verify the reset block is not blocking us from resetting. Acquire | |
2093 | * semaphore (if necessary) and read/set/write the device control reset | |
2094 | * bit in the PHY. Wait the appropriate delay time for the device to | |
489815ce | 2095 | * reset and release the semaphore (if necessary). |
bc7f75fa AK |
2096 | **/ |
2097 | s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw) | |
2098 | { | |
2099 | struct e1000_phy_info *phy = &hw->phy; | |
2100 | s32 ret_val; | |
2101 | u32 ctrl; | |
2102 | ||
470a5420 BA |
2103 | if (phy->ops.check_reset_block) { |
2104 | ret_val = phy->ops.check_reset_block(hw); | |
2105 | if (ret_val) | |
2106 | return 0; | |
2107 | } | |
bc7f75fa | 2108 | |
94d8186a | 2109 | ret_val = phy->ops.acquire(hw); |
bc7f75fa AK |
2110 | if (ret_val) |
2111 | return ret_val; | |
2112 | ||
2113 | ctrl = er32(CTRL); | |
2114 | ew32(CTRL, ctrl | E1000_CTRL_PHY_RST); | |
2115 | e1e_flush(); | |
2116 | ||
2117 | udelay(phy->reset_delay_us); | |
2118 | ||
2119 | ew32(CTRL, ctrl); | |
2120 | e1e_flush(); | |
2121 | ||
2122 | udelay(150); | |
2123 | ||
94d8186a | 2124 | phy->ops.release(hw); |
bc7f75fa | 2125 | |
84c1befe | 2126 | return phy->ops.get_cfg_done(hw); |
bc7f75fa AK |
2127 | } |
2128 | ||
2129 | /** | |
fe90849f | 2130 | * e1000e_get_cfg_done_generic - Generic configuration done |
bc7f75fa AK |
2131 | * @hw: pointer to the HW structure |
2132 | * | |
2133 | * Generic function to wait 10 milli-seconds for configuration to complete | |
2134 | * and return success. | |
2135 | **/ | |
8bb62869 | 2136 | s32 e1000e_get_cfg_done_generic(struct e1000_hw __always_unused *hw) |
bc7f75fa AK |
2137 | { |
2138 | mdelay(10); | |
3d3a1676 | 2139 | |
bc7f75fa AK |
2140 | return 0; |
2141 | } | |
2142 | ||
f4187b56 BA |
2143 | /** |
2144 | * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY | |
2145 | * @hw: pointer to the HW structure | |
2146 | * | |
2147 | * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. | |
2148 | **/ | |
2149 | s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw) | |
2150 | { | |
3bb99fe2 | 2151 | e_dbg("Running IGP 3 PHY init script\n"); |
f4187b56 BA |
2152 | |
2153 | /* PHY init IGP 3 */ | |
2154 | /* Enable rise/fall, 10-mode work in class-A */ | |
2155 | e1e_wphy(hw, 0x2F5B, 0x9018); | |
2156 | /* Remove all caps from Replica path filter */ | |
2157 | e1e_wphy(hw, 0x2F52, 0x0000); | |
2158 | /* Bias trimming for ADC, AFE and Driver (Default) */ | |
2159 | e1e_wphy(hw, 0x2FB1, 0x8B24); | |
2160 | /* Increase Hybrid poly bias */ | |
2161 | e1e_wphy(hw, 0x2FB2, 0xF8F0); | |
2162 | /* Add 4% to Tx amplitude in Gig mode */ | |
2163 | e1e_wphy(hw, 0x2010, 0x10B0); | |
2164 | /* Disable trimming (TTT) */ | |
2165 | e1e_wphy(hw, 0x2011, 0x0000); | |
2166 | /* Poly DC correction to 94.6% + 2% for all channels */ | |
2167 | e1e_wphy(hw, 0x20DD, 0x249A); | |
2168 | /* ABS DC correction to 95.9% */ | |
2169 | e1e_wphy(hw, 0x20DE, 0x00D3); | |
2170 | /* BG temp curve trim */ | |
2171 | e1e_wphy(hw, 0x28B4, 0x04CE); | |
2172 | /* Increasing ADC OPAMP stage 1 currents to max */ | |
2173 | e1e_wphy(hw, 0x2F70, 0x29E4); | |
2174 | /* Force 1000 ( required for enabling PHY regs configuration) */ | |
2175 | e1e_wphy(hw, 0x0000, 0x0140); | |
2176 | /* Set upd_freq to 6 */ | |
2177 | e1e_wphy(hw, 0x1F30, 0x1606); | |
2178 | /* Disable NPDFE */ | |
2179 | e1e_wphy(hw, 0x1F31, 0xB814); | |
2180 | /* Disable adaptive fixed FFE (Default) */ | |
2181 | e1e_wphy(hw, 0x1F35, 0x002A); | |
2182 | /* Enable FFE hysteresis */ | |
2183 | e1e_wphy(hw, 0x1F3E, 0x0067); | |
2184 | /* Fixed FFE for short cable lengths */ | |
2185 | e1e_wphy(hw, 0x1F54, 0x0065); | |
2186 | /* Fixed FFE for medium cable lengths */ | |
2187 | e1e_wphy(hw, 0x1F55, 0x002A); | |
2188 | /* Fixed FFE for long cable lengths */ | |
2189 | e1e_wphy(hw, 0x1F56, 0x002A); | |
2190 | /* Enable Adaptive Clip Threshold */ | |
2191 | e1e_wphy(hw, 0x1F72, 0x3FB0); | |
2192 | /* AHT reset limit to 1 */ | |
2193 | e1e_wphy(hw, 0x1F76, 0xC0FF); | |
2194 | /* Set AHT master delay to 127 msec */ | |
2195 | e1e_wphy(hw, 0x1F77, 0x1DEC); | |
2196 | /* Set scan bits for AHT */ | |
2197 | e1e_wphy(hw, 0x1F78, 0xF9EF); | |
2198 | /* Set AHT Preset bits */ | |
2199 | e1e_wphy(hw, 0x1F79, 0x0210); | |
2200 | /* Change integ_factor of channel A to 3 */ | |
2201 | e1e_wphy(hw, 0x1895, 0x0003); | |
2202 | /* Change prop_factor of channels BCD to 8 */ | |
2203 | e1e_wphy(hw, 0x1796, 0x0008); | |
2204 | /* Change cg_icount + enable integbp for channels BCD */ | |
2205 | e1e_wphy(hw, 0x1798, 0xD008); | |
e921eb1a | 2206 | /* Change cg_icount + enable integbp + change prop_factor_master |
f4187b56 BA |
2207 | * to 8 for channel A |
2208 | */ | |
2209 | e1e_wphy(hw, 0x1898, 0xD918); | |
2210 | /* Disable AHT in Slave mode on channel A */ | |
2211 | e1e_wphy(hw, 0x187A, 0x0800); | |
e921eb1a | 2212 | /* Enable LPLU and disable AN to 1000 in non-D0a states, |
f4187b56 BA |
2213 | * Enable SPD+B2B |
2214 | */ | |
2215 | e1e_wphy(hw, 0x0019, 0x008D); | |
2216 | /* Enable restart AN on an1000_dis change */ | |
2217 | e1e_wphy(hw, 0x001B, 0x2080); | |
2218 | /* Enable wh_fifo read clock in 10/100 modes */ | |
2219 | e1e_wphy(hw, 0x0014, 0x0045); | |
2220 | /* Restart AN, Speed selection is 1000 */ | |
2221 | e1e_wphy(hw, 0x0000, 0x1340); | |
2222 | ||
2223 | return 0; | |
2224 | } | |
2225 | ||
bc7f75fa AK |
2226 | /** |
2227 | * e1000e_get_phy_type_from_id - Get PHY type from id | |
2228 | * @phy_id: phy_id read from the phy | |
2229 | * | |
2230 | * Returns the phy type from the id. | |
2231 | **/ | |
2232 | enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id) | |
2233 | { | |
2234 | enum e1000_phy_type phy_type = e1000_phy_unknown; | |
2235 | ||
2236 | switch (phy_id) { | |
2237 | case M88E1000_I_PHY_ID: | |
2238 | case M88E1000_E_PHY_ID: | |
2239 | case M88E1111_I_PHY_ID: | |
2240 | case M88E1011_I_PHY_ID: | |
2241 | phy_type = e1000_phy_m88; | |
2242 | break; | |
2243 | case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ | |
2244 | phy_type = e1000_phy_igp_2; | |
2245 | break; | |
2246 | case GG82563_E_PHY_ID: | |
2247 | phy_type = e1000_phy_gg82563; | |
2248 | break; | |
2249 | case IGP03E1000_E_PHY_ID: | |
2250 | phy_type = e1000_phy_igp_3; | |
2251 | break; | |
2252 | case IFE_E_PHY_ID: | |
2253 | case IFE_PLUS_E_PHY_ID: | |
2254 | case IFE_C_E_PHY_ID: | |
2255 | phy_type = e1000_phy_ife; | |
2256 | break; | |
97ac8cae BA |
2257 | case BME1000_E_PHY_ID: |
2258 | case BME1000_E_PHY_ID_R2: | |
2259 | phy_type = e1000_phy_bm; | |
2260 | break; | |
a4f58f54 BA |
2261 | case I82578_E_PHY_ID: |
2262 | phy_type = e1000_phy_82578; | |
2263 | break; | |
2264 | case I82577_E_PHY_ID: | |
2265 | phy_type = e1000_phy_82577; | |
2266 | break; | |
d3738bb8 BA |
2267 | case I82579_E_PHY_ID: |
2268 | phy_type = e1000_phy_82579; | |
2269 | break; | |
2fbe4526 BA |
2270 | case I217_E_PHY_ID: |
2271 | phy_type = e1000_phy_i217; | |
2272 | break; | |
bc7f75fa AK |
2273 | default: |
2274 | phy_type = e1000_phy_unknown; | |
2275 | break; | |
2276 | } | |
2277 | return phy_type; | |
2278 | } | |
2279 | ||
97ac8cae BA |
2280 | /** |
2281 | * e1000e_determine_phy_address - Determines PHY address. | |
2282 | * @hw: pointer to the HW structure | |
2283 | * | |
2284 | * This uses a trial and error method to loop through possible PHY | |
2285 | * addresses. It tests each by reading the PHY ID registers and | |
2286 | * checking for a match. | |
2287 | **/ | |
2288 | s32 e1000e_determine_phy_address(struct e1000_hw *hw) | |
2289 | { | |
5eb6f3c7 BA |
2290 | u32 phy_addr = 0; |
2291 | u32 i; | |
97ac8cae BA |
2292 | enum e1000_phy_type phy_type = e1000_phy_unknown; |
2293 | ||
5eb6f3c7 BA |
2294 | hw->phy.id = phy_type; |
2295 | ||
2296 | for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { | |
2297 | hw->phy.addr = phy_addr; | |
2298 | i = 0; | |
2299 | ||
2300 | do { | |
97ac8cae BA |
2301 | e1000e_get_phy_id(hw); |
2302 | phy_type = e1000e_get_phy_type_from_id(hw->phy.id); | |
2303 | ||
e921eb1a | 2304 | /* If phy_type is valid, break - we found our |
97ac8cae BA |
2305 | * PHY address |
2306 | */ | |
5015e53a BA |
2307 | if (phy_type != e1000_phy_unknown) |
2308 | return 0; | |
2309 | ||
1bba4386 | 2310 | usleep_range(1000, 2000); |
5eb6f3c7 BA |
2311 | i++; |
2312 | } while (i < 10); | |
2313 | } | |
97ac8cae | 2314 | |
5015e53a | 2315 | return -E1000_ERR_PHY_TYPE; |
97ac8cae BA |
2316 | } |
2317 | ||
2318 | /** | |
2319 | * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address | |
2320 | * @page: page to access | |
2321 | * | |
2322 | * Returns the phy address for the page requested. | |
2323 | **/ | |
2324 | static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) | |
2325 | { | |
2326 | u32 phy_addr = 2; | |
2327 | ||
2328 | if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) | |
2329 | phy_addr = 1; | |
2330 | ||
2331 | return phy_addr; | |
2332 | } | |
2333 | ||
2334 | /** | |
2335 | * e1000e_write_phy_reg_bm - Write BM PHY register | |
2336 | * @hw: pointer to the HW structure | |
2337 | * @offset: register offset to write to | |
2338 | * @data: data to write at register offset | |
2339 | * | |
2340 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2341 | * at the offset. Release any acquired semaphores before exiting. | |
2342 | **/ | |
2343 | s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) | |
2344 | { | |
2345 | s32 ret_val; | |
97ac8cae | 2346 | u32 page = offset >> IGP_PAGE_SHIFT; |
97ac8cae | 2347 | |
94d8186a | 2348 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2349 | if (ret_val) |
2350 | return ret_val; | |
2351 | ||
97ac8cae BA |
2352 | /* Page 800 works differently than the rest so it has its own func */ |
2353 | if (page == BM_WUC_PAGE) { | |
2354 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, | |
2b6b168d | 2355 | false, false); |
75ce1532 | 2356 | goto release; |
97ac8cae BA |
2357 | } |
2358 | ||
97ac8cae BA |
2359 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
2360 | ||
2361 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
90da0669 BA |
2362 | u32 page_shift, page_select; |
2363 | ||
e921eb1a | 2364 | /* Page select is register 31 for phy address 1 and 22 for |
97ac8cae BA |
2365 | * phy address 2 and 3. Page select is shifted only for |
2366 | * phy address 1. | |
2367 | */ | |
2368 | if (hw->phy.addr == 1) { | |
2369 | page_shift = IGP_PAGE_SHIFT; | |
2370 | page_select = IGP01E1000_PHY_PAGE_SELECT; | |
2371 | } else { | |
2372 | page_shift = 0; | |
2373 | page_select = BM_PHY_PAGE_SELECT; | |
2374 | } | |
2375 | ||
2376 | /* Page is shifted left, PHY expects (page x 32) */ | |
2377 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, | |
2378 | (page << page_shift)); | |
5ccdcecb | 2379 | if (ret_val) |
75ce1532 | 2380 | goto release; |
97ac8cae BA |
2381 | } |
2382 | ||
2383 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2384 | data); | |
2385 | ||
75ce1532 | 2386 | release: |
94d8186a | 2387 | hw->phy.ops.release(hw); |
97ac8cae BA |
2388 | return ret_val; |
2389 | } | |
2390 | ||
2391 | /** | |
2392 | * e1000e_read_phy_reg_bm - Read BM PHY register | |
2393 | * @hw: pointer to the HW structure | |
2394 | * @offset: register offset to be read | |
2395 | * @data: pointer to the read data | |
2396 | * | |
2397 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2398 | * and storing the retrieved information in data. Release any acquired | |
2399 | * semaphores before exiting. | |
2400 | **/ | |
2401 | s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) | |
2402 | { | |
2403 | s32 ret_val; | |
97ac8cae | 2404 | u32 page = offset >> IGP_PAGE_SHIFT; |
97ac8cae | 2405 | |
94d8186a | 2406 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2407 | if (ret_val) |
2408 | return ret_val; | |
2409 | ||
97ac8cae BA |
2410 | /* Page 800 works differently than the rest so it has its own func */ |
2411 | if (page == BM_WUC_PAGE) { | |
2412 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, | |
2b6b168d | 2413 | true, false); |
75ce1532 | 2414 | goto release; |
97ac8cae BA |
2415 | } |
2416 | ||
97ac8cae BA |
2417 | hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); |
2418 | ||
2419 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
90da0669 BA |
2420 | u32 page_shift, page_select; |
2421 | ||
e921eb1a | 2422 | /* Page select is register 31 for phy address 1 and 22 for |
97ac8cae BA |
2423 | * phy address 2 and 3. Page select is shifted only for |
2424 | * phy address 1. | |
2425 | */ | |
2426 | if (hw->phy.addr == 1) { | |
2427 | page_shift = IGP_PAGE_SHIFT; | |
2428 | page_select = IGP01E1000_PHY_PAGE_SELECT; | |
2429 | } else { | |
2430 | page_shift = 0; | |
2431 | page_select = BM_PHY_PAGE_SELECT; | |
2432 | } | |
2433 | ||
2434 | /* Page is shifted left, PHY expects (page x 32) */ | |
2435 | ret_val = e1000e_write_phy_reg_mdic(hw, page_select, | |
2436 | (page << page_shift)); | |
5ccdcecb | 2437 | if (ret_val) |
75ce1532 | 2438 | goto release; |
97ac8cae BA |
2439 | } |
2440 | ||
2441 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2442 | data); | |
75ce1532 | 2443 | release: |
94d8186a | 2444 | hw->phy.ops.release(hw); |
97ac8cae BA |
2445 | return ret_val; |
2446 | } | |
2447 | ||
4662e82b BA |
2448 | /** |
2449 | * e1000e_read_phy_reg_bm2 - Read BM PHY register | |
2450 | * @hw: pointer to the HW structure | |
2451 | * @offset: register offset to be read | |
2452 | * @data: pointer to the read data | |
2453 | * | |
2454 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
2455 | * and storing the retrieved information in data. Release any acquired | |
2456 | * semaphores before exiting. | |
2457 | **/ | |
2458 | s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) | |
2459 | { | |
2460 | s32 ret_val; | |
2461 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); | |
2462 | ||
94d8186a | 2463 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2464 | if (ret_val) |
2465 | return ret_val; | |
2466 | ||
4662e82b BA |
2467 | /* Page 800 works differently than the rest so it has its own func */ |
2468 | if (page == BM_WUC_PAGE) { | |
2469 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, | |
2b6b168d | 2470 | true, false); |
75ce1532 | 2471 | goto release; |
4662e82b BA |
2472 | } |
2473 | ||
4662e82b BA |
2474 | hw->phy.addr = 1; |
2475 | ||
2476 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
4662e82b BA |
2477 | /* Page is shifted left, PHY expects (page x 32) */ |
2478 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, | |
2479 | page); | |
2480 | ||
5ccdcecb | 2481 | if (ret_val) |
75ce1532 | 2482 | goto release; |
4662e82b BA |
2483 | } |
2484 | ||
2485 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2486 | data); | |
75ce1532 | 2487 | release: |
94d8186a | 2488 | hw->phy.ops.release(hw); |
4662e82b BA |
2489 | return ret_val; |
2490 | } | |
2491 | ||
2492 | /** | |
2493 | * e1000e_write_phy_reg_bm2 - Write BM PHY register | |
2494 | * @hw: pointer to the HW structure | |
2495 | * @offset: register offset to write to | |
2496 | * @data: data to write at register offset | |
2497 | * | |
2498 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2499 | * at the offset. Release any acquired semaphores before exiting. | |
2500 | **/ | |
2501 | s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) | |
2502 | { | |
2503 | s32 ret_val; | |
2504 | u16 page = (u16)(offset >> IGP_PAGE_SHIFT); | |
2505 | ||
94d8186a | 2506 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2507 | if (ret_val) |
2508 | return ret_val; | |
2509 | ||
4662e82b BA |
2510 | /* Page 800 works differently than the rest so it has its own func */ |
2511 | if (page == BM_WUC_PAGE) { | |
2512 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, | |
2b6b168d | 2513 | false, false); |
75ce1532 | 2514 | goto release; |
4662e82b BA |
2515 | } |
2516 | ||
4662e82b BA |
2517 | hw->phy.addr = 1; |
2518 | ||
2519 | if (offset > MAX_PHY_MULTI_PAGE_REG) { | |
2520 | /* Page is shifted left, PHY expects (page x 32) */ | |
2521 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, | |
2522 | page); | |
2523 | ||
5ccdcecb | 2524 | if (ret_val) |
75ce1532 | 2525 | goto release; |
4662e82b BA |
2526 | } |
2527 | ||
2528 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, | |
2529 | data); | |
2530 | ||
75ce1532 | 2531 | release: |
94d8186a | 2532 | hw->phy.ops.release(hw); |
4662e82b BA |
2533 | return ret_val; |
2534 | } | |
2535 | ||
97ac8cae | 2536 | /** |
2b6b168d | 2537 | * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers |
97ac8cae | 2538 | * @hw: pointer to the HW structure |
2b6b168d | 2539 | * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG |
97ac8cae | 2540 | * |
2b6b168d BA |
2541 | * Assumes semaphore already acquired and phy_reg points to a valid memory |
2542 | * address to store contents of the BM_WUC_ENABLE_REG register. | |
97ac8cae | 2543 | **/ |
2b6b168d | 2544 | s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) |
97ac8cae BA |
2545 | { |
2546 | s32 ret_val; | |
2b6b168d | 2547 | u16 temp; |
97ac8cae | 2548 | |
2b6b168d | 2549 | /* All page select, port ctrl and wakeup registers use phy address 1 */ |
97ac8cae BA |
2550 | hw->phy.addr = 1; |
2551 | ||
2b6b168d BA |
2552 | /* Select Port Control Registers page */ |
2553 | ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); | |
2554 | if (ret_val) { | |
2555 | e_dbg("Could not set Port Control page\n"); | |
5015e53a | 2556 | return ret_val; |
2b6b168d | 2557 | } |
97ac8cae | 2558 | |
2b6b168d | 2559 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); |
9b71b419 | 2560 | if (ret_val) { |
2b6b168d BA |
2561 | e_dbg("Could not read PHY register %d.%d\n", |
2562 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); | |
5015e53a | 2563 | return ret_val; |
9b71b419 | 2564 | } |
97ac8cae | 2565 | |
e921eb1a | 2566 | /* Enable both PHY wakeup mode and Wakeup register page writes. |
2b6b168d BA |
2567 | * Prevent a power state change by disabling ME and Host PHY wakeup. |
2568 | */ | |
2569 | temp = *phy_reg; | |
2570 | temp |= BM_WUC_ENABLE_BIT; | |
2571 | temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); | |
2572 | ||
2573 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); | |
9b71b419 | 2574 | if (ret_val) { |
2b6b168d BA |
2575 | e_dbg("Could not write PHY register %d.%d\n", |
2576 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); | |
5015e53a | 2577 | return ret_val; |
9b71b419 | 2578 | } |
97ac8cae | 2579 | |
e921eb1a | 2580 | /* Select Host Wakeup Registers page - caller now able to write |
5015e53a BA |
2581 | * registers on the Wakeup registers page |
2582 | */ | |
2583 | return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); | |
2b6b168d BA |
2584 | } |
2585 | ||
2586 | /** | |
2587 | * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs | |
2588 | * @hw: pointer to the HW structure | |
2589 | * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG | |
2590 | * | |
2591 | * Restore BM_WUC_ENABLE_REG to its original value. | |
2592 | * | |
2593 | * Assumes semaphore already acquired and *phy_reg is the contents of the | |
2594 | * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by | |
2595 | * caller. | |
2596 | **/ | |
2597 | s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) | |
2598 | { | |
70806a7f | 2599 | s32 ret_val; |
2b6b168d BA |
2600 | |
2601 | /* Select Port Control Registers page */ | |
2602 | ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); | |
9b71b419 | 2603 | if (ret_val) { |
2b6b168d | 2604 | e_dbg("Could not set Port Control page\n"); |
5015e53a | 2605 | return ret_val; |
9b71b419 | 2606 | } |
97ac8cae | 2607 | |
2b6b168d BA |
2608 | /* Restore 769.17 to its original value */ |
2609 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); | |
2610 | if (ret_val) | |
2611 | e_dbg("Could not restore PHY register %d.%d\n", | |
2612 | BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); | |
5015e53a | 2613 | |
2b6b168d BA |
2614 | return ret_val; |
2615 | } | |
97ac8cae | 2616 | |
2b6b168d BA |
2617 | /** |
2618 | * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register | |
2619 | * @hw: pointer to the HW structure | |
2620 | * @offset: register offset to be read or written | |
2621 | * @data: pointer to the data to read or write | |
2622 | * @read: determines if operation is read or write | |
2623 | * @page_set: BM_WUC_PAGE already set and access enabled | |
2624 | * | |
2625 | * Read the PHY register at offset and store the retrieved information in | |
2626 | * data, or write data to PHY register at offset. Note the procedure to | |
2627 | * access the PHY wakeup registers is different than reading the other PHY | |
2628 | * registers. It works as such: | |
2629 | * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 | |
2630 | * 2) Set page to 800 for host (801 if we were manageability) | |
2631 | * 3) Write the address using the address opcode (0x11) | |
2632 | * 4) Read or write the data using the data opcode (0x12) | |
2633 | * 5) Restore 769.17.2 to its original value | |
2634 | * | |
2635 | * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and | |
2636 | * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). | |
2637 | * | |
2638 | * Assumes semaphore is already acquired. When page_set==true, assumes | |
2639 | * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack | |
2640 | * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). | |
2641 | **/ | |
2642 | static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, | |
2643 | u16 *data, bool read, bool page_set) | |
2644 | { | |
2645 | s32 ret_val; | |
2646 | u16 reg = BM_PHY_REG_NUM(offset); | |
2647 | u16 page = BM_PHY_REG_PAGE(offset); | |
2648 | u16 phy_reg = 0; | |
2649 | ||
2650 | /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ | |
2651 | if ((hw->mac.type == e1000_pchlan) && | |
2652 | (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) | |
2653 | e_dbg("Attempting to access page %d while gig enabled.\n", | |
2654 | page); | |
2655 | ||
2656 | if (!page_set) { | |
2657 | /* Enable access to PHY wakeup registers */ | |
2658 | ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); | |
2659 | if (ret_val) { | |
2660 | e_dbg("Could not enable PHY wakeup reg access\n"); | |
5015e53a | 2661 | return ret_val; |
2b6b168d BA |
2662 | } |
2663 | } | |
2664 | ||
2665 | e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg); | |
2666 | ||
2667 | /* Write the Wakeup register page offset value using opcode 0x11 */ | |
97ac8cae | 2668 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); |
9b71b419 | 2669 | if (ret_val) { |
2b6b168d | 2670 | e_dbg("Could not write address opcode to page %d\n", page); |
5015e53a | 2671 | return ret_val; |
9b71b419 | 2672 | } |
97ac8cae BA |
2673 | |
2674 | if (read) { | |
2b6b168d | 2675 | /* Read the Wakeup register page value using opcode 0x12 */ |
97ac8cae BA |
2676 | ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
2677 | data); | |
2678 | } else { | |
2b6b168d | 2679 | /* Write the Wakeup register page value using opcode 0x12 */ |
97ac8cae BA |
2680 | ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, |
2681 | *data); | |
2682 | } | |
2683 | ||
9b71b419 | 2684 | if (ret_val) { |
2b6b168d | 2685 | e_dbg("Could not access PHY reg %d.%d\n", page, reg); |
5015e53a | 2686 | return ret_val; |
9b71b419 | 2687 | } |
97ac8cae | 2688 | |
2b6b168d BA |
2689 | if (!page_set) |
2690 | ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); | |
97ac8cae | 2691 | |
97ac8cae BA |
2692 | return ret_val; |
2693 | } | |
2694 | ||
17f208de BA |
2695 | /** |
2696 | * e1000_power_up_phy_copper - Restore copper link in case of PHY power down | |
2697 | * @hw: pointer to the HW structure | |
2698 | * | |
2699 | * In the case of a PHY power down to save power, or to turn off link during a | |
2700 | * driver unload, or wake on lan is not enabled, restore the link to previous | |
2701 | * settings. | |
2702 | **/ | |
2703 | void e1000_power_up_phy_copper(struct e1000_hw *hw) | |
2704 | { | |
2705 | u16 mii_reg = 0; | |
2706 | ||
2707 | /* The PHY will retain its settings across a power down/up cycle */ | |
c2ade1a4 BA |
2708 | e1e_rphy(hw, MII_BMCR, &mii_reg); |
2709 | mii_reg &= ~BMCR_PDOWN; | |
2710 | e1e_wphy(hw, MII_BMCR, mii_reg); | |
17f208de BA |
2711 | } |
2712 | ||
2713 | /** | |
2714 | * e1000_power_down_phy_copper - Restore copper link in case of PHY power down | |
2715 | * @hw: pointer to the HW structure | |
2716 | * | |
2717 | * In the case of a PHY power down to save power, or to turn off link during a | |
2718 | * driver unload, or wake on lan is not enabled, restore the link to previous | |
2719 | * settings. | |
2720 | **/ | |
2721 | void e1000_power_down_phy_copper(struct e1000_hw *hw) | |
2722 | { | |
2723 | u16 mii_reg = 0; | |
2724 | ||
2725 | /* The PHY will retain its settings across a power down/up cycle */ | |
c2ade1a4 BA |
2726 | e1e_rphy(hw, MII_BMCR, &mii_reg); |
2727 | mii_reg |= BMCR_PDOWN; | |
2728 | e1e_wphy(hw, MII_BMCR, mii_reg); | |
1bba4386 | 2729 | usleep_range(1000, 2000); |
17f208de BA |
2730 | } |
2731 | ||
a4f58f54 | 2732 | /** |
5ccdcecb | 2733 | * __e1000_read_phy_reg_hv - Read HV PHY register |
a4f58f54 BA |
2734 | * @hw: pointer to the HW structure |
2735 | * @offset: register offset to be read | |
2736 | * @data: pointer to the read data | |
5ccdcecb | 2737 | * @locked: semaphore has already been acquired or not |
a4f58f54 BA |
2738 | * |
2739 | * Acquires semaphore, if necessary, then reads the PHY register at offset | |
5ccdcecb | 2740 | * and stores the retrieved information in data. Release any acquired |
a4f58f54 BA |
2741 | * semaphore before exiting. |
2742 | **/ | |
5ccdcecb | 2743 | static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, |
2b6b168d | 2744 | bool locked, bool page_set) |
a4f58f54 BA |
2745 | { |
2746 | s32 ret_val; | |
2747 | u16 page = BM_PHY_REG_PAGE(offset); | |
2748 | u16 reg = BM_PHY_REG_NUM(offset); | |
2b6b168d | 2749 | u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
a4f58f54 | 2750 | |
5ccdcecb | 2751 | if (!locked) { |
94d8186a | 2752 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2753 | if (ret_val) |
2754 | return ret_val; | |
2755 | } | |
2756 | ||
a4f58f54 BA |
2757 | /* Page 800 works differently than the rest so it has its own func */ |
2758 | if (page == BM_WUC_PAGE) { | |
2b6b168d BA |
2759 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, |
2760 | true, page_set); | |
a4f58f54 BA |
2761 | goto out; |
2762 | } | |
2763 | ||
2764 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { | |
2765 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, | |
2766 | data, true); | |
2767 | goto out; | |
2768 | } | |
2769 | ||
2b6b168d BA |
2770 | if (!page_set) { |
2771 | if (page == HV_INTC_FC_PAGE_START) | |
2772 | page = 0; | |
a4f58f54 | 2773 | |
2b6b168d BA |
2774 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
2775 | /* Page is shifted left, PHY expects (page x 32) */ | |
2776 | ret_val = e1000_set_page_igp(hw, | |
2777 | (page << IGP_PAGE_SHIFT)); | |
a4f58f54 | 2778 | |
2b6b168d | 2779 | hw->phy.addr = phy_addr; |
842ec8b6 | 2780 | |
2b6b168d BA |
2781 | if (ret_val) |
2782 | goto out; | |
2783 | } | |
a4f58f54 BA |
2784 | } |
2785 | ||
2b6b168d BA |
2786 | e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, |
2787 | page << IGP_PAGE_SHIFT, reg); | |
2788 | ||
a4f58f54 BA |
2789 | ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
2790 | data); | |
a4f58f54 | 2791 | out: |
5ccdcecb | 2792 | if (!locked) |
94d8186a | 2793 | hw->phy.ops.release(hw); |
5ccdcecb | 2794 | |
a4f58f54 BA |
2795 | return ret_val; |
2796 | } | |
2797 | ||
2798 | /** | |
5ccdcecb BA |
2799 | * e1000_read_phy_reg_hv - Read HV PHY register |
2800 | * @hw: pointer to the HW structure | |
2801 | * @offset: register offset to be read | |
2802 | * @data: pointer to the read data | |
2803 | * | |
2804 | * Acquires semaphore then reads the PHY register at offset and stores | |
2805 | * the retrieved information in data. Release the acquired semaphore | |
2806 | * before exiting. | |
2807 | **/ | |
2808 | s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) | |
2809 | { | |
2b6b168d | 2810 | return __e1000_read_phy_reg_hv(hw, offset, data, false, false); |
5ccdcecb BA |
2811 | } |
2812 | ||
2813 | /** | |
2814 | * e1000_read_phy_reg_hv_locked - Read HV PHY register | |
2815 | * @hw: pointer to the HW structure | |
2816 | * @offset: register offset to be read | |
2817 | * @data: pointer to the read data | |
2818 | * | |
2819 | * Reads the PHY register at offset and stores the retrieved information | |
2820 | * in data. Assumes semaphore already acquired. | |
2821 | **/ | |
2822 | s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) | |
2823 | { | |
2b6b168d BA |
2824 | return __e1000_read_phy_reg_hv(hw, offset, data, true, false); |
2825 | } | |
2826 | ||
2827 | /** | |
2828 | * e1000_read_phy_reg_page_hv - Read HV PHY register | |
2829 | * @hw: pointer to the HW structure | |
2830 | * @offset: register offset to write to | |
2831 | * @data: data to write at register offset | |
2832 | * | |
2833 | * Reads the PHY register at offset and stores the retrieved information | |
2834 | * in data. Assumes semaphore already acquired and page already set. | |
2835 | **/ | |
2836 | s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) | |
2837 | { | |
2838 | return __e1000_read_phy_reg_hv(hw, offset, data, true, true); | |
5ccdcecb BA |
2839 | } |
2840 | ||
2841 | /** | |
2842 | * __e1000_write_phy_reg_hv - Write HV PHY register | |
a4f58f54 BA |
2843 | * @hw: pointer to the HW structure |
2844 | * @offset: register offset to write to | |
2845 | * @data: data to write at register offset | |
5ccdcecb | 2846 | * @locked: semaphore has already been acquired or not |
a4f58f54 BA |
2847 | * |
2848 | * Acquires semaphore, if necessary, then writes the data to PHY register | |
2849 | * at the offset. Release any acquired semaphores before exiting. | |
2850 | **/ | |
5ccdcecb | 2851 | static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, |
2b6b168d | 2852 | bool locked, bool page_set) |
a4f58f54 BA |
2853 | { |
2854 | s32 ret_val; | |
2855 | u16 page = BM_PHY_REG_PAGE(offset); | |
2856 | u16 reg = BM_PHY_REG_NUM(offset); | |
2b6b168d | 2857 | u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); |
a4f58f54 | 2858 | |
5ccdcecb | 2859 | if (!locked) { |
94d8186a | 2860 | ret_val = hw->phy.ops.acquire(hw); |
5ccdcecb BA |
2861 | if (ret_val) |
2862 | return ret_val; | |
2863 | } | |
2864 | ||
a4f58f54 BA |
2865 | /* Page 800 works differently than the rest so it has its own func */ |
2866 | if (page == BM_WUC_PAGE) { | |
2b6b168d BA |
2867 | ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, |
2868 | false, page_set); | |
a4f58f54 BA |
2869 | goto out; |
2870 | } | |
2871 | ||
2872 | if (page > 0 && page < HV_INTC_FC_PAGE_START) { | |
2873 | ret_val = e1000_access_phy_debug_regs_hv(hw, offset, | |
2874 | &data, false); | |
2875 | goto out; | |
2876 | } | |
2877 | ||
2b6b168d BA |
2878 | if (!page_set) { |
2879 | if (page == HV_INTC_FC_PAGE_START) | |
2880 | page = 0; | |
a4f58f54 | 2881 | |
e921eb1a | 2882 | /* Workaround MDIO accesses being disabled after entering IEEE |
2b6b168d BA |
2883 | * Power Down (when bit 11 of the PHY Control register is set) |
2884 | */ | |
2885 | if ((hw->phy.type == e1000_phy_82578) && | |
2886 | (hw->phy.revision >= 1) && | |
2887 | (hw->phy.addr == 2) && | |
04499ec4 | 2888 | !(MAX_PHY_REG_ADDRESS & reg) && (data & (1 << 11))) { |
2b6b168d BA |
2889 | u16 data2 = 0x7EFF; |
2890 | ret_val = e1000_access_phy_debug_regs_hv(hw, | |
2891 | (1 << 6) | 0x3, | |
2892 | &data2, false); | |
2893 | if (ret_val) | |
2894 | goto out; | |
2895 | } | |
a4f58f54 | 2896 | |
2b6b168d BA |
2897 | if (reg > MAX_PHY_MULTI_PAGE_REG) { |
2898 | /* Page is shifted left, PHY expects (page x 32) */ | |
2899 | ret_val = e1000_set_page_igp(hw, | |
2900 | (page << IGP_PAGE_SHIFT)); | |
a4f58f54 | 2901 | |
2b6b168d | 2902 | hw->phy.addr = phy_addr; |
842ec8b6 | 2903 | |
2b6b168d BA |
2904 | if (ret_val) |
2905 | goto out; | |
2906 | } | |
a4f58f54 BA |
2907 | } |
2908 | ||
2b6b168d BA |
2909 | e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, |
2910 | page << IGP_PAGE_SHIFT, reg); | |
2911 | ||
a4f58f54 BA |
2912 | ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, |
2913 | data); | |
a4f58f54 BA |
2914 | |
2915 | out: | |
5ccdcecb | 2916 | if (!locked) |
94d8186a | 2917 | hw->phy.ops.release(hw); |
5ccdcecb | 2918 | |
a4f58f54 BA |
2919 | return ret_val; |
2920 | } | |
2921 | ||
5ccdcecb BA |
2922 | /** |
2923 | * e1000_write_phy_reg_hv - Write HV PHY register | |
2924 | * @hw: pointer to the HW structure | |
2925 | * @offset: register offset to write to | |
2926 | * @data: data to write at register offset | |
2927 | * | |
2928 | * Acquires semaphore then writes the data to PHY register at the offset. | |
2929 | * Release the acquired semaphores before exiting. | |
2930 | **/ | |
2931 | s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) | |
2932 | { | |
2b6b168d | 2933 | return __e1000_write_phy_reg_hv(hw, offset, data, false, false); |
5ccdcecb BA |
2934 | } |
2935 | ||
2936 | /** | |
2937 | * e1000_write_phy_reg_hv_locked - Write HV PHY register | |
2938 | * @hw: pointer to the HW structure | |
2939 | * @offset: register offset to write to | |
2940 | * @data: data to write at register offset | |
2941 | * | |
2942 | * Writes the data to PHY register at the offset. Assumes semaphore | |
2943 | * already acquired. | |
2944 | **/ | |
2945 | s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) | |
2946 | { | |
2b6b168d BA |
2947 | return __e1000_write_phy_reg_hv(hw, offset, data, true, false); |
2948 | } | |
2949 | ||
2950 | /** | |
2951 | * e1000_write_phy_reg_page_hv - Write HV PHY register | |
2952 | * @hw: pointer to the HW structure | |
2953 | * @offset: register offset to write to | |
2954 | * @data: data to write at register offset | |
2955 | * | |
2956 | * Writes the data to PHY register at the offset. Assumes semaphore | |
2957 | * already acquired and page already set. | |
2958 | **/ | |
2959 | s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) | |
2960 | { | |
2961 | return __e1000_write_phy_reg_hv(hw, offset, data, true, true); | |
5ccdcecb BA |
2962 | } |
2963 | ||
a4f58f54 | 2964 | /** |
b595076a | 2965 | * e1000_get_phy_addr_for_hv_page - Get PHY address based on page |
a4f58f54 BA |
2966 | * @page: page to be accessed |
2967 | **/ | |
2968 | static u32 e1000_get_phy_addr_for_hv_page(u32 page) | |
2969 | { | |
2970 | u32 phy_addr = 2; | |
2971 | ||
2972 | if (page >= HV_INTC_FC_PAGE_START) | |
2973 | phy_addr = 1; | |
2974 | ||
2975 | return phy_addr; | |
2976 | } | |
2977 | ||
2978 | /** | |
2979 | * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers | |
2980 | * @hw: pointer to the HW structure | |
2981 | * @offset: register offset to be read or written | |
2982 | * @data: pointer to the data to be read or written | |
2b6b168d | 2983 | * @read: determines if operation is read or write |
a4f58f54 | 2984 | * |
5ccdcecb BA |
2985 | * Reads the PHY register at offset and stores the retreived information |
2986 | * in data. Assumes semaphore already acquired. Note that the procedure | |
2b6b168d BA |
2987 | * to access these regs uses the address port and data port to read/write. |
2988 | * These accesses done with PHY address 2 and without using pages. | |
a4f58f54 BA |
2989 | **/ |
2990 | static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, | |
2991 | u16 *data, bool read) | |
2992 | { | |
2993 | s32 ret_val; | |
70806a7f BA |
2994 | u32 addr_reg; |
2995 | u32 data_reg; | |
a4f58f54 BA |
2996 | |
2997 | /* This takes care of the difference with desktop vs mobile phy */ | |
2998 | addr_reg = (hw->phy.type == e1000_phy_82578) ? | |
2999 | I82578_ADDR_REG : I82577_ADDR_REG; | |
3000 | data_reg = addr_reg + 1; | |
3001 | ||
a4f58f54 BA |
3002 | /* All operations in this function are phy address 2 */ |
3003 | hw->phy.addr = 2; | |
3004 | ||
3005 | /* masking with 0x3F to remove the page from offset */ | |
3006 | ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); | |
3007 | if (ret_val) { | |
2b6b168d | 3008 | e_dbg("Could not write the Address Offset port register\n"); |
5015e53a | 3009 | return ret_val; |
a4f58f54 BA |
3010 | } |
3011 | ||
3012 | /* Read or write the data value next */ | |
3013 | if (read) | |
3014 | ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data); | |
3015 | else | |
3016 | ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data); | |
3017 | ||
5015e53a | 3018 | if (ret_val) |
2b6b168d | 3019 | e_dbg("Could not access the Data port register\n"); |
a4f58f54 | 3020 | |
a4f58f54 BA |
3021 | return ret_val; |
3022 | } | |
3023 | ||
3024 | /** | |
3025 | * e1000_link_stall_workaround_hv - Si workaround | |
3026 | * @hw: pointer to the HW structure | |
3027 | * | |
3028 | * This function works around a Si bug where the link partner can get | |
3029 | * a link up indication before the PHY does. If small packets are sent | |
3030 | * by the link partner they can be placed in the packet buffer without | |
3031 | * being properly accounted for by the PHY and will stall preventing | |
3032 | * further packets from being received. The workaround is to clear the | |
3033 | * packet buffer after the PHY detects link up. | |
3034 | **/ | |
3035 | s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) | |
3036 | { | |
3037 | s32 ret_val = 0; | |
3038 | u16 data; | |
3039 | ||
3040 | if (hw->phy.type != e1000_phy_82578) | |
5015e53a | 3041 | return 0; |
a4f58f54 | 3042 | |
e65fa87c | 3043 | /* Do not apply workaround if in PHY loopback bit 14 set */ |
c2ade1a4 BA |
3044 | e1e_rphy(hw, MII_BMCR, &data); |
3045 | if (data & BMCR_LOOPBACK) | |
5015e53a | 3046 | return 0; |
e65fa87c | 3047 | |
a4f58f54 | 3048 | /* check if link is up and at 1Gbps */ |
482fed85 | 3049 | ret_val = e1e_rphy(hw, BM_CS_STATUS, &data); |
a4f58f54 | 3050 | if (ret_val) |
5015e53a | 3051 | return ret_val; |
a4f58f54 | 3052 | |
3d3a1676 BA |
3053 | data &= BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | |
3054 | BM_CS_STATUS_SPEED_MASK; | |
a4f58f54 | 3055 | |
3d3a1676 BA |
3056 | if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | |
3057 | BM_CS_STATUS_SPEED_1000)) | |
5015e53a | 3058 | return 0; |
a4f58f54 | 3059 | |
bb9c5ee1 | 3060 | msleep(200); |
a4f58f54 BA |
3061 | |
3062 | /* flush the packets in the fifo buffer */ | |
c063f606 BA |
3063 | ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, |
3064 | (HV_MUX_DATA_CTRL_GEN_TO_MAC | | |
3065 | HV_MUX_DATA_CTRL_FORCE_SPEED)); | |
a4f58f54 | 3066 | if (ret_val) |
5015e53a | 3067 | return ret_val; |
a4f58f54 | 3068 | |
5015e53a | 3069 | return e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC); |
a4f58f54 BA |
3070 | } |
3071 | ||
3072 | /** | |
3073 | * e1000_check_polarity_82577 - Checks the polarity. | |
3074 | * @hw: pointer to the HW structure | |
3075 | * | |
3076 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
3077 | * | |
3078 | * Polarity is determined based on the PHY specific status register. | |
3079 | **/ | |
3080 | s32 e1000_check_polarity_82577(struct e1000_hw *hw) | |
3081 | { | |
3082 | struct e1000_phy_info *phy = &hw->phy; | |
3083 | s32 ret_val; | |
3084 | u16 data; | |
3085 | ||
482fed85 | 3086 | ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
a4f58f54 BA |
3087 | |
3088 | if (!ret_val) | |
3089 | phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY) | |
3090 | ? e1000_rev_polarity_reversed | |
3091 | : e1000_rev_polarity_normal; | |
3092 | ||
3093 | return ret_val; | |
3094 | } | |
3095 | ||
3096 | /** | |
3097 | * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY | |
3098 | * @hw: pointer to the HW structure | |
3099 | * | |
eab50ffb | 3100 | * Calls the PHY setup function to force speed and duplex. |
a4f58f54 BA |
3101 | **/ |
3102 | s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) | |
3103 | { | |
3104 | struct e1000_phy_info *phy = &hw->phy; | |
3105 | s32 ret_val; | |
3106 | u16 phy_data; | |
3107 | bool link; | |
3108 | ||
c2ade1a4 | 3109 | ret_val = e1e_rphy(hw, MII_BMCR, &phy_data); |
a4f58f54 | 3110 | if (ret_val) |
5015e53a | 3111 | return ret_val; |
a4f58f54 BA |
3112 | |
3113 | e1000e_phy_force_speed_duplex_setup(hw, &phy_data); | |
3114 | ||
c2ade1a4 | 3115 | ret_val = e1e_wphy(hw, MII_BMCR, phy_data); |
a4f58f54 | 3116 | if (ret_val) |
5015e53a | 3117 | return ret_val; |
a4f58f54 | 3118 | |
a4f58f54 BA |
3119 | udelay(1); |
3120 | ||
3121 | if (phy->autoneg_wait_to_complete) { | |
3bb99fe2 | 3122 | e_dbg("Waiting for forced speed/duplex link on 82577 phy\n"); |
a4f58f54 | 3123 | |
3d3a1676 BA |
3124 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
3125 | 100000, &link); | |
a4f58f54 | 3126 | if (ret_val) |
5015e53a | 3127 | return ret_val; |
a4f58f54 BA |
3128 | |
3129 | if (!link) | |
3bb99fe2 | 3130 | e_dbg("Link taking longer than expected.\n"); |
a4f58f54 BA |
3131 | |
3132 | /* Try once more */ | |
3d3a1676 BA |
3133 | ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT, |
3134 | 100000, &link); | |
a4f58f54 BA |
3135 | } |
3136 | ||
a4f58f54 BA |
3137 | return ret_val; |
3138 | } | |
3139 | ||
3140 | /** | |
3141 | * e1000_get_phy_info_82577 - Retrieve I82577 PHY information | |
3142 | * @hw: pointer to the HW structure | |
3143 | * | |
3144 | * Read PHY status to determine if link is up. If link is up, then | |
3145 | * set/determine 10base-T extended distance and polarity correction. Read | |
3146 | * PHY port status to determine MDI/MDIx and speed. Based on the speed, | |
3147 | * determine on the cable length, local and remote receiver. | |
3148 | **/ | |
3149 | s32 e1000_get_phy_info_82577(struct e1000_hw *hw) | |
3150 | { | |
3151 | struct e1000_phy_info *phy = &hw->phy; | |
3152 | s32 ret_val; | |
3153 | u16 data; | |
3154 | bool link; | |
3155 | ||
3156 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
3157 | if (ret_val) | |
5015e53a | 3158 | return ret_val; |
a4f58f54 BA |
3159 | |
3160 | if (!link) { | |
3bb99fe2 | 3161 | e_dbg("Phy info is only valid if link is up\n"); |
5015e53a | 3162 | return -E1000_ERR_CONFIG; |
a4f58f54 BA |
3163 | } |
3164 | ||
3165 | phy->polarity_correction = true; | |
3166 | ||
3167 | ret_val = e1000_check_polarity_82577(hw); | |
3168 | if (ret_val) | |
5015e53a | 3169 | return ret_val; |
a4f58f54 | 3170 | |
482fed85 | 3171 | ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data); |
a4f58f54 | 3172 | if (ret_val) |
5015e53a | 3173 | return ret_val; |
a4f58f54 | 3174 | |
04499ec4 | 3175 | phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); |
a4f58f54 BA |
3176 | |
3177 | if ((data & I82577_PHY_STATUS2_SPEED_MASK) == | |
3178 | I82577_PHY_STATUS2_SPEED_1000MBPS) { | |
3179 | ret_val = hw->phy.ops.get_cable_length(hw); | |
3180 | if (ret_val) | |
5015e53a | 3181 | return ret_val; |
a4f58f54 | 3182 | |
c2ade1a4 | 3183 | ret_val = e1e_rphy(hw, MII_STAT1000, &data); |
a4f58f54 | 3184 | if (ret_val) |
5015e53a | 3185 | return ret_val; |
a4f58f54 | 3186 | |
c2ade1a4 BA |
3187 | phy->local_rx = (data & LPA_1000LOCALRXOK) |
3188 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
a4f58f54 | 3189 | |
c2ade1a4 BA |
3190 | phy->remote_rx = (data & LPA_1000REMRXOK) |
3191 | ? e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok; | |
a4f58f54 BA |
3192 | } else { |
3193 | phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; | |
3194 | phy->local_rx = e1000_1000t_rx_status_undefined; | |
3195 | phy->remote_rx = e1000_1000t_rx_status_undefined; | |
3196 | } | |
3197 | ||
5015e53a | 3198 | return 0; |
a4f58f54 BA |
3199 | } |
3200 | ||
3201 | /** | |
3202 | * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY | |
3203 | * @hw: pointer to the HW structure | |
3204 | * | |
3205 | * Reads the diagnostic status register and verifies result is valid before | |
3206 | * placing it in the phy_cable_length field. | |
3207 | **/ | |
3208 | s32 e1000_get_cable_length_82577(struct e1000_hw *hw) | |
3209 | { | |
3210 | struct e1000_phy_info *phy = &hw->phy; | |
3211 | s32 ret_val; | |
3212 | u16 phy_data, length; | |
3213 | ||
482fed85 | 3214 | ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data); |
a4f58f54 | 3215 | if (ret_val) |
5015e53a | 3216 | return ret_val; |
a4f58f54 BA |
3217 | |
3218 | length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >> | |
3219 | I82577_DSTATUS_CABLE_LENGTH_SHIFT; | |
3220 | ||
3221 | if (length == E1000_CABLE_LENGTH_UNDEFINED) | |
7dbbe5d5 | 3222 | return -E1000_ERR_PHY; |
a4f58f54 BA |
3223 | |
3224 | phy->cable_length = length; | |
3225 | ||
5015e53a | 3226 | return 0; |
a4f58f54 | 3227 | } |