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Merge tag 'pci-v6.16-fixes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
[linux-block.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
ae06c70b 1// SPDX-License-Identifier: GPL-2.0
51dce24b 2/* Copyright(c) 1999 - 2018 Intel Corporation. */
bc7f75fa 3
8544b9f7
BA		 4#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
5
bc7f75fa
AK		 6#include <linux/module.h>
7#include <linux/types.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/vmalloc.h>
11#include <linux/pagemap.h>
12#include <linux/delay.h>
13#include <linux/netdevice.h>
9fb7a5f7 14#include <linux/interrupt.h>
bc7f75fa
AK		 15#include <linux/tcp.h>
16#include <linux/ipv6.h>
5a0e3ad6 17#include <linux/slab.h>
bc7f75fa
AK		 18#include <net/checksum.h>
19#include <net/ip6_checksum.h>
bc7f75fa
AK		 20#include <linux/ethtool.h>
21#include <linux/if_vlan.h>
22#include <linux/cpu.h>
23#include <linux/smp.h>
e8db0be1 24#include <linux/pm_qos.h>
23606cf5 25#include <linux/pm_runtime.h>
70c71606 26#include <linux/prefetch.h>
ccf8b940 27#include <linux/suspend.h>
bc7f75fa
AK		 28
29#include "e1000.h"
7bab8828
SN		 30#define CREATE_TRACE_POINTS
31#include "e1000e_trace.h"
bc7f75fa 32
bc7f75fa 33char e1000e_driver_name[] = "e1000e";
bc7f75fa 34
b3f4d599 35#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
36static int debug = -1;
37module_param(debug, int, 0);
38MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
39
bc7f75fa
AK		 40static const struct e1000_info *e1000_info_tbl[] = {
41 [board_82571] = &e1000_82571_info,
42 [board_82572] = &e1000_82572_info,
43 [board_82573] = &e1000_82573_info,
4662e82b 44 [board_82574] = &e1000_82574_info,
8c81c9c3 45 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 46 [board_80003es2lan] = &e1000_es2_info,
47 [board_ich8lan] = &e1000_ich8_info,
48 [board_ich9lan] = &e1000_ich9_info,
f4187b56 49 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 50 [board_pchlan] = &e1000_pch_info,
d3738bb8 51 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 52 [board_pch_lpt] = &e1000_pch_lpt_info,
79849ebc 53 [board_pch_spt] = &e1000_pch_spt_info,
3a3173b9 54 [board_pch_cnp] = &e1000_pch_cnp_info,
280db5d4 55 [board_pch_tgp] = &e1000_pch_tgp_info,
68defd52 56 [board_pch_adp] = &e1000_pch_adp_info,
db2d737d 57 [board_pch_mtp] = &e1000_pch_mtp_info,
bc7f75fa
AK		 58};
59
84f4ee90
TI		 60struct e1000_reg_info {
61 u32 ofs;
62 char *name;
63};
64
84f4ee90 65static const struct e1000_reg_info e1000_reg_info_tbl[] = {
84f4ee90
TI		 66 /* General Registers */
67 {E1000_CTRL, "CTRL"},
68 {E1000_STATUS, "STATUS"},
69 {E1000_CTRL_EXT, "CTRL_EXT"},
70
71 /* Interrupt Registers */
72 {E1000_ICR, "ICR"},
73
af667a29 74 /* Rx Registers */
84f4ee90 75 {E1000_RCTL, "RCTL"},
1e36052e
BA		 76 {E1000_RDLEN(0), "RDLEN"},
77 {E1000_RDH(0), "RDH"},
78 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 79 {E1000_RDTR, "RDTR"},
80 {E1000_RXDCTL(0), "RXDCTL"},
81 {E1000_ERT, "ERT"},
1e36052e
BA		 82 {E1000_RDBAL(0), "RDBAL"},
83 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 84 {E1000_RDFH, "RDFH"},
85 {E1000_RDFT, "RDFT"},
86 {E1000_RDFHS, "RDFHS"},
87 {E1000_RDFTS, "RDFTS"},
88 {E1000_RDFPC, "RDFPC"},
89
af667a29 90 /* Tx Registers */
84f4ee90 91 {E1000_TCTL, "TCTL"},
1e36052e
BA		 92 {E1000_TDBAL(0), "TDBAL"},
93 {E1000_TDBAH(0), "TDBAH"},
94 {E1000_TDLEN(0), "TDLEN"},
95 {E1000_TDH(0), "TDH"},
96 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 97 {E1000_TIDV, "TIDV"},
98 {E1000_TXDCTL(0), "TXDCTL"},
99 {E1000_TADV, "TADV"},
100 {E1000_TARC(0), "TARC"},
101 {E1000_TDFH, "TDFH"},
102 {E1000_TDFT, "TDFT"},
103 {E1000_TDFHS, "TDFHS"},
104 {E1000_TDFTS, "TDFTS"},
105 {E1000_TDFPC, "TDFPC"},
106
107 /* List Terminator */
f36bb6ca 108 {0, NULL}
84f4ee90
TI		 109};
110
c6f3148c
AK		 111/**
112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
113 * @hw: pointer to the HW structure
114 *
115 * When updating the MAC CSR registers, the Manageability Engine (ME) could
116 * be accessing the registers at the same time. Normally, this is handled in
117 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
118 * accesses later than it should which could result in the register to have
119 * an incorrect value. Workaround this by checking the FWSM register which
120 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
121 * and try again a number of times.
122 **/
d601afca 123static void __ew32_prepare(struct e1000_hw *hw)
c6f3148c
AK		 124{
125 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
126
127 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
128 udelay(50);
c6f3148c
AK		 129}
130
131void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
132{
133 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
134 __ew32_prepare(hw);
135
136 writel(val, hw->hw_addr + reg);
137}
138
e921eb1a 139/**
84f4ee90 140 * e1000_regdump - register printout routine
e921eb1a
BA		 141 * @hw: pointer to the HW structure
142 * @reginfo: pointer to the register info table
143 **/
84f4ee90
TI		 144static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
145{
146 int n = 0;
147 char rname[16];
148 u32 regs[8];
149
150 switch (reginfo->ofs) {
151 case E1000_RXDCTL(0):
152 for (n = 0; n < 2; n++)
153 regs[n] = __er32(hw, E1000_RXDCTL(n));
154 break;
155 case E1000_TXDCTL(0):
156 for (n = 0; n < 2; n++)
157 regs[n] = __er32(hw, E1000_TXDCTL(n));
158 break;
159 case E1000_TARC(0):
160 for (n = 0; n < 2; n++)
161 regs[n] = __er32(hw, E1000_TARC(n));
162 break;
163 default:
ef456f85
JK		 164 pr_info("%-15s %08x\n",
165 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 166 return;
167 }
168
169 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 170 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 171}
172
f0c5dadf
ET		 173static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
174 struct e1000_buffer *bi)
175{
176 int i;
177 struct e1000_ps_page *ps_page;
178
179 for (i = 0; i < adapter->rx_ps_pages; i++) {
180 ps_page = &bi->ps_pages[i];
181
182 if (ps_page->page) {
183 pr_info("packet dump for ps_page %d:\n", i);
184 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
185 16, 1, page_address(ps_page->page),
186 PAGE_SIZE, true);
187 }
188 }
189}
190
e921eb1a 191/**
af667a29 192 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 193 * @adapter: board private structure
194 **/
84f4ee90
TI		 195static void e1000e_dump(struct e1000_adapter *adapter)
196{
197 struct net_device *netdev = adapter->netdev;
198 struct e1000_hw *hw = &adapter->hw;
199 struct e1000_reg_info *reginfo;
200 struct e1000_ring *tx_ring = adapter->tx_ring;
201 struct e1000_tx_desc *tx_desc;
af667a29 202 struct my_u0 {
e885d762
BA		 203 __le64 a;
204 __le64 b;
af667a29 205 } *u0;
84f4ee90
TI		 206 struct e1000_buffer *buffer_info;
207 struct e1000_ring *rx_ring = adapter->rx_ring;
208 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 209 union e1000_rx_desc_extended *rx_desc;
af667a29 210 struct my_u1 {
e885d762
BA		 211 __le64 a;
212 __le64 b;
213 __le64 c;
214 __le64 d;
af667a29 215 } *u1;
84f4ee90
TI		 216 u32 staterr;
217 int i = 0;
218
219 if (!netif_msg_hw(adapter))
220 return;
221
222 /* Print netdevice Info */
223 if (netdev) {
224 dev_info(&adapter->pdev->dev, "Net device Info\n");
4a7c9726
TK		 225 pr_info("Device Name state trans_start\n");
226 pr_info("%-15s %016lX %016lX\n", netdev->name,
227 netdev->state, dev_trans_start(netdev));
84f4ee90
TI		 228 }
229
230 /* Print Registers */
231 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 232 pr_info(" Register Name Value\n");
84f4ee90
TI		 233 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
234 reginfo->name; reginfo++) {
235 e1000_regdump(hw, reginfo);
236 }
237
af667a29 238 /* Print Tx Ring Summary */
84f4ee90 239 if (!netdev || !netif_running(netdev))
fe1e980f 240 return;
84f4ee90 241
af667a29 242 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 243 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 244 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 245 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
246 0, tx_ring->next_to_use, tx_ring->next_to_clean,
247 (unsigned long long)buffer_info->dma,
248 buffer_info->length,
249 buffer_info->next_to_watch,
250 (unsigned long long)buffer_info->time_stamp);
84f4ee90 251
af667a29 252 /* Print Tx Ring */
84f4ee90
TI		 253 if (!netif_msg_tx_done(adapter))
254 goto rx_ring_summary;
255
af667a29 256 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 257
258 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
259 *
260 * Legacy Transmit Descriptor
261 * +--------------------------------------------------------------+
262 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
263 * +--------------------------------------------------------------+
264 * 8 | Special | CSS | Status | CMD | CSO | Length |
265 * +--------------------------------------------------------------+
266 * 63 48 47 36 35 32 31 24 23 16 15 0
267 *
268 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
269 * 63 48 47 40 39 32 31 16 15 8 7 0
270 * +----------------------------------------------------------------+
271 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
272 * +----------------------------------------------------------------+
273 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
274 * +----------------------------------------------------------------+
275 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
276 *
277 * Extended Data Descriptor (DTYP=0x1)
278 * +----------------------------------------------------------------+
279 * 0 | Buffer Address [63:0] |
280 * +----------------------------------------------------------------+
281 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
282 * +----------------------------------------------------------------+
283 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
284 */
ef456f85
JK		 285 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
286 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
287 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 288 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 289 const char *next_desc;
84f4ee90
TI		 290 tx_desc = E1000_TX_DESC(*tx_ring, i);
291 buffer_info = &tx_ring->buffer_info[i];
292 u0 = (struct my_u0 *)tx_desc;
84f4ee90 293 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 294 next_desc = " NTC/U";
84f4ee90 295 else if (i == tx_ring->next_to_use)
ef456f85 296 next_desc = " NTU";
84f4ee90 297 else if (i == tx_ring->next_to_clean)
ef456f85 298 next_desc = " NTC";
84f4ee90 299 else
ef456f85
JK		 300 next_desc = "";
301 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
18dd2392
JK		 302 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
303 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
ef456f85
JK		 304 i,
305 (unsigned long long)le64_to_cpu(u0->a),
306 (unsigned long long)le64_to_cpu(u0->b),
307 (unsigned long long)buffer_info->dma,
308 buffer_info->length, buffer_info->next_to_watch,
309 (unsigned long long)buffer_info->time_stamp,
310 buffer_info->skb, next_desc);
84f4ee90 311
f0c5dadf 312 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 313 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 314 16, 1, buffer_info->skb->data,
315 buffer_info->skb->len, true);
84f4ee90
TI		 316 }
317
af667a29 318 /* Print Rx Ring Summary */
84f4ee90 319rx_ring_summary:
af667a29 320 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 321 pr_info("Queue [NTU] [NTC]\n");
322 pr_info(" %5d %5X %5X\n",
323 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 324
af667a29 325 /* Print Rx Ring */
84f4ee90 326 if (!netif_msg_rx_status(adapter))
fe1e980f 327 return;
84f4ee90 328
af667a29 329 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 330 switch (adapter->rx_ps_pages) {
331 case 1:
332 case 2:
333 case 3:
334 /* [Extended] Packet Split Receive Descriptor Format
335 *
336 * +-----------------------------------------------------+
337 * 0 | Buffer Address 0 [63:0] |
338 * +-----------------------------------------------------+
339 * 8 | Buffer Address 1 [63:0] |
340 * +-----------------------------------------------------+
341 * 16 | Buffer Address 2 [63:0] |
342 * +-----------------------------------------------------+
343 * 24 | Buffer Address 3 [63:0] |
344 * +-----------------------------------------------------+
345 */
ef456f85 346 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 347 /* [Extended] Receive Descriptor (Write-Back) Format
348 *
349 * 63 48 47 32 31 13 12 8 7 4 3 0
350 * +------------------------------------------------------+
351 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
352 * | Checksum | Ident | | Queue | | Type |
353 * +------------------------------------------------------+
354 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
355 * +------------------------------------------------------+
356 * 63 48 47 32 31 20 19 0
357 */
ef456f85 358 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 359 for (i = 0; i < rx_ring->count; i++) {
ef456f85 360 const char *next_desc;
84f4ee90
TI		 361 buffer_info = &rx_ring->buffer_info[i];
362 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
363 u1 = (struct my_u1 *)rx_desc_ps;
364 staterr =
af667a29 365 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 366
367 if (i == rx_ring->next_to_use)
368 next_desc = " NTU";
369 else if (i == rx_ring->next_to_clean)
370 next_desc = " NTC";
371 else
372 next_desc = "";
373
84f4ee90
TI		 374 if (staterr & E1000_RXD_STAT_DD) {
375 /* Descriptor Done */
ef456f85
JK		 376 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
377 "RWB", i,
378 (unsigned long long)le64_to_cpu(u1->a),
379 (unsigned long long)le64_to_cpu(u1->b),
380 (unsigned long long)le64_to_cpu(u1->c),
381 (unsigned long long)le64_to_cpu(u1->d),
382 buffer_info->skb, next_desc);
84f4ee90 383 } else {
ef456f85
JK		 384 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
385 "R ", i,
386 (unsigned long long)le64_to_cpu(u1->a),
387 (unsigned long long)le64_to_cpu(u1->b),
388 (unsigned long long)le64_to_cpu(u1->c),
389 (unsigned long long)le64_to_cpu(u1->d),
390 (unsigned long long)buffer_info->dma,
391 buffer_info->skb, next_desc);
84f4ee90
TI		 392
393 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 394 e1000e_dump_ps_pages(adapter,
395 buffer_info);
84f4ee90 396 }
84f4ee90
TI		 397 }
398 break;
399 default:
400 case 0:
5f450212 401 /* Extended Receive Descriptor (Read) Format
84f4ee90 402 *
5f450212
BA		 403 * +-----------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +-----------------------------------------------------+
406 * 8 | Reserved |
407 * +-----------------------------------------------------+
84f4ee90 408 */
ef456f85 409 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 410 /* Extended Receive Descriptor (Write-Back) Format
411 *
412 * 63 48 47 32 31 24 23 4 3 0
413 * +------------------------------------------------------+
414 * | RSS Hash | | | |
415 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
416 * | Packet | IP | | | Type |
417 * | Checksum | Ident | | | |
418 * +------------------------------------------------------+
419 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
420 * +------------------------------------------------------+
421 * 63 48 47 32 31 20 19 0
422 */
ef456f85 423 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 424
425 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 426 const char *next_desc;
427
84f4ee90 428 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 429 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
430 u1 = (struct my_u1 *)rx_desc;
431 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 432
433 if (i == rx_ring->next_to_use)
434 next_desc = " NTU";
435 else if (i == rx_ring->next_to_clean)
436 next_desc = " NTC";
437 else
438 next_desc = "";
439
5f450212
BA		 440 if (staterr & E1000_RXD_STAT_DD) {
441 /* Descriptor Done */
ef456f85
JK		 442 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
443 "RWB", i,
444 (unsigned long long)le64_to_cpu(u1->a),
445 (unsigned long long)le64_to_cpu(u1->b),
446 buffer_info->skb, next_desc);
5f450212 447 } else {
ef456f85
JK		 448 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
449 "R ", i,
450 (unsigned long long)le64_to_cpu(u1->a),
451 (unsigned long long)le64_to_cpu(u1->b),
452 (unsigned long long)buffer_info->dma,
453 buffer_info->skb, next_desc);
5f450212 454
f0c5dadf
ET		 455 if (netif_msg_pktdata(adapter) &&
456 buffer_info->skb)
5f450212
BA		 457 print_hex_dump(KERN_INFO, "",
458 DUMP_PREFIX_ADDRESS, 16,
459 1,
f0c5dadf 460 buffer_info->skb->data,
5f450212
BA		 461 adapter->rx_buffer_len,
462 true);
463 }
84f4ee90
TI		 464 }
465 }
84f4ee90
TI		 466}
467
bc7f75fa
AK		 468/**
469 * e1000_desc_unused - calculate if we have unused descriptors
b50f7bca 470 * @ring: pointer to ring struct to perform calculation on
bc7f75fa
AK		 471 **/
472static int e1000_desc_unused(struct e1000_ring *ring)
473{
474 if (ring->next_to_clean > ring->next_to_use)
475 return ring->next_to_clean - ring->next_to_use - 1;
476
477 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
478}
479
b67e1913
BA		 480/**
481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
482 * @adapter: board private structure
483 * @hwtstamps: time stamp structure to update
484 * @systim: unsigned 64bit system time value.
485 *
486 * Convert the system time value stored in the RX/TXSTMP registers into a
487 * hwtstamp which can be used by the upper level time stamping functions.
488 *
489 * The 'systim_lock' spinlock is used to protect the consistency of the
490 * system time value. This is needed because reading the 64 bit time
491 * value involves reading two 32 bit registers. The first read latches the
492 * value.
493 **/
494static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
495 struct skb_shared_hwtstamps *hwtstamps,
496 u64 systim)
497{
498 u64 ns;
499 unsigned long flags;
500
501 spin_lock_irqsave(&adapter->systim_lock, flags);
502 ns = timecounter_cyc2time(&adapter->tc, systim);
503 spin_unlock_irqrestore(&adapter->systim_lock, flags);
504
505 memset(hwtstamps, 0, sizeof(*hwtstamps));
506 hwtstamps->hwtstamp = ns_to_ktime(ns);
507}
508
509/**
510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
511 * @adapter: board private structure
512 * @status: descriptor extended error and status field
513 * @skb: particular skb to include time stamp
514 *
515 * If the time stamp is valid, convert it into the timecounter ns value
516 * and store that result into the shhwtstamps structure which is passed
517 * up the network stack.
518 **/
519static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
520 struct sk_buff *skb)
521{
522 struct e1000_hw *hw = &adapter->hw;
523 u64 rxstmp;
524
525 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
526 !(status & E1000_RXDEXT_STATERR_TST) ||
527 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
528 return;
529
530 /* The Rx time stamp registers contain the time stamp. No other
531 * received packet will be time stamped until the Rx time stamp
532 * registers are read. Because only one packet can be time stamped
533 * at a time, the register values must belong to this packet and
534 * therefore none of the other additional attributes need to be
535 * compared.
536 */
537 rxstmp = (u64)er32(RXSTMPL);
538 rxstmp |= (u64)er32(RXSTMPH) << 32;
539 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
540
541 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
542}
543
bc7f75fa 544/**
ad68076e 545 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 546 * @adapter: board private structure
b50f7bca 547 * @netdev: pointer to netdev struct
b67e1913 548 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 549 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
550 * @skb: pointer to sk_buff to be indicated to stack
551 **/
552static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 553 struct net_device *netdev, struct sk_buff *skb,
b67e1913 554 u32 staterr, __le16 vlan)
bc7f75fa 555{
86d70e53 556 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 557
558 e1000e_rx_hwtstamp(adapter, staterr, skb);
559
bc7f75fa
AK		 560 skb->protocol = eth_type_trans(skb, netdev);
561
b67e1913 562 if (staterr & E1000_RXD_STAT_VP)
86a9bad3 563 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
86d70e53
JK		 564
565 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 566}
567
568/**
af667a29 569 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 570 * @adapter: board private structure
571 * @status_err: receive descriptor status and error fields
b50f7bca 572 * @skb: socket buffer with received data
bc7f75fa
AK		 573 **/
574static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 575 struct sk_buff *skb)
bc7f75fa
AK		 576{
577 u16 status = (u16)status_err;
578 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 579
580 skb_checksum_none_assert(skb);
bc7f75fa 581
afd12939
BA		 582 /* Rx checksum disabled */
583 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
584 return;
585
bc7f75fa
AK		 586 /* Ignore Checksum bit is set */
587 if (status & E1000_RXD_STAT_IXSM)
588 return;
afd12939 589
2e1706f2
BA		 590 /* TCP/UDP checksum error bit or IP checksum error bit is set */
591 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 592 /* let the stack verify checksum errors */
593 adapter->hw_csum_err++;
594 return;
595 }
596
597 /* TCP/UDP Checksum has not been calculated */
598 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
599 return;
600
601 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 602 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 603 adapter->hw_csum_good++;
604}
605
55aa6985 606static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 607{
55aa6985 608 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 609 struct e1000_hw *hw = &adapter->hw;
bdc125f7 610
d601afca 611 __ew32_prepare(hw);
bdc125f7 612 writel(i, rx_ring->tail);
c6e7f51e 613
d601afca 614 if (unlikely(i != readl(rx_ring->tail))) {
c6e7f51e 615 u32 rctl = er32(RCTL);
6cf08d1c 616
c6e7f51e
BA		 617 ew32(RCTL, rctl & ~E1000_RCTL_EN);
618 e_err("ME firmware caused invalid RDT - resetting\n");
619 schedule_work(&adapter->reset_task);
620 }
621}
622
55aa6985 623static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 624{
55aa6985 625 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e
BA		 626 struct e1000_hw *hw = &adapter->hw;
627
d601afca 628 __ew32_prepare(hw);
bdc125f7
BA		 629 writel(i, tx_ring->tail);
630
d601afca 631 if (unlikely(i != readl(tx_ring->tail))) {
c6e7f51e 632 u32 tctl = er32(TCTL);
6cf08d1c 633
c6e7f51e
BA		 634 ew32(TCTL, tctl & ~E1000_TCTL_EN);
635 e_err("ME firmware caused invalid TDT - resetting\n");
636 schedule_work(&adapter->reset_task);
637 }
638}
639
bc7f75fa 640/**
5f450212 641 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 642 * @rx_ring: Rx descriptor ring
b50f7bca
JB		 643 * @cleaned_count: number to reallocate
644 * @gfp: flags for allocation
bc7f75fa 645 **/
55aa6985 646static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 647 int cleaned_count, gfp_t gfp)
bc7f75fa 648{
55aa6985 649 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 650 struct net_device *netdev = adapter->netdev;
651 struct pci_dev *pdev = adapter->pdev;
5f450212 652 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 653 struct e1000_buffer *buffer_info;
654 struct sk_buff *skb;
655 unsigned int i;
89d71a66 656 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 657
658 i = rx_ring->next_to_use;
659 buffer_info = &rx_ring->buffer_info[i];
660
661 while (cleaned_count--) {
662 skb = buffer_info->skb;
663 if (skb) {
664 skb_trim(skb, 0);
665 goto map_skb;
666 }
667
c2fed996 668 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 669 if (!skb) {
670 /* Better luck next round */
671 adapter->alloc_rx_buff_failed++;
672 break;
673 }
674
bc7f75fa
AK		 675 buffer_info->skb = skb;
676map_skb:
0be3f55f 677 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 678 adapter->rx_buffer_len,
0be3f55f
NN		 679 DMA_FROM_DEVICE);
680 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 681 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 682 adapter->rx_dma_failed++;
683 break;
684 }
685
5f450212
BA		 686 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
687 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 688
50849d79 689 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 690 /* Force memory writes to complete before letting h/w
50849d79
TH		 691 * know there are new descriptors to fetch. (Only
692 * applicable for weak-ordered memory model archs,
693 * such as IA-64).
694 */
695 wmb();
c6e7f51e 696 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 697 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 698 else
c5083cf6 699 writel(i, rx_ring->tail);
50849d79 700 }
bc7f75fa
AK		 701 i++;
702 if (i == rx_ring->count)
703 i = 0;
704 buffer_info = &rx_ring->buffer_info[i];
705 }
706
50849d79 707 rx_ring->next_to_use = i;
bc7f75fa
AK		 708}
709
710/**
711 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 712 * @rx_ring: Rx descriptor ring
b50f7bca
JB		 713 * @cleaned_count: number to reallocate
714 * @gfp: flags for allocation
bc7f75fa 715 **/
55aa6985 716static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 717 int cleaned_count, gfp_t gfp)
bc7f75fa 718{
55aa6985 719 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 720 struct net_device *netdev = adapter->netdev;
721 struct pci_dev *pdev = adapter->pdev;
722 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 723 struct e1000_buffer *buffer_info;
724 struct e1000_ps_page *ps_page;
725 struct sk_buff *skb;
726 unsigned int i, j;
727
728 i = rx_ring->next_to_use;
729 buffer_info = &rx_ring->buffer_info[i];
730
731 while (cleaned_count--) {
732 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
733
734 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 735 ps_page = &buffer_info->ps_pages[j];
736 if (j >= adapter->rx_ps_pages) {
737 /* all unused desc entries get hw null ptr */
af667a29
BA		 738 rx_desc->read.buffer_addr[j + 1] =
739 ~cpu_to_le64(0);
47f44e40
AK		 740 continue;
741 }
742 if (!ps_page->page) {
c2fed996 743 ps_page->page = alloc_page(gfp);
bc7f75fa 744 if (!ps_page->page) {
47f44e40
AK		 745 adapter->alloc_rx_buff_failed++;
746 goto no_buffers;
747 }
0be3f55f
NN		 748 ps_page->dma = dma_map_page(&pdev->dev,
749 ps_page->page,
750 0, PAGE_SIZE,
751 DMA_FROM_DEVICE);
752 if (dma_mapping_error(&pdev->dev,
753 ps_page->dma)) {
47f44e40 754 dev_err(&adapter->pdev->dev,
af667a29 755 "Rx DMA page map failed\n");
47f44e40
AK		 756 adapter->rx_dma_failed++;
757 goto no_buffers;
bc7f75fa 758 }
bc7f75fa 759 }
e921eb1a 760 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 761 * didn't change because each write-back
762 * erases this info.
763 */
af667a29
BA		 764 rx_desc->read.buffer_addr[j + 1] =
765 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 766 }
767
e5fe2541 768 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
c2fed996 769 gfp);
bc7f75fa
AK		 770
771 if (!skb) {
772 adapter->alloc_rx_buff_failed++;
773 break;
774 }
775
bc7f75fa 776 buffer_info->skb = skb;
0be3f55f 777 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 778 adapter->rx_ps_bsize0,
0be3f55f
NN		 779 DMA_FROM_DEVICE);
780 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 781 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 782 adapter->rx_dma_failed++;
783 /* cleanup skb */
784 dev_kfree_skb_any(skb);
785 buffer_info->skb = NULL;
786 break;
787 }
788
789 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
790
50849d79 791 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 792 /* Force memory writes to complete before letting h/w
50849d79
TH		 793 * know there are new descriptors to fetch. (Only
794 * applicable for weak-ordered memory model archs,
795 * such as IA-64).
796 */
797 wmb();
c6e7f51e 798 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 799 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 800 else
c5083cf6 801 writel(i << 1, rx_ring->tail);
50849d79
TH		 802 }
803
bc7f75fa
AK		 804 i++;
805 if (i == rx_ring->count)
806 i = 0;
807 buffer_info = &rx_ring->buffer_info[i];
808 }
809
810no_buffers:
50849d79 811 rx_ring->next_to_use = i;
bc7f75fa
AK		 812}
813
97ac8cae
BA		 814/**
815 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 816 * @rx_ring: Rx descriptor ring
97ac8cae 817 * @cleaned_count: number of buffers to allocate this pass
b50f7bca 818 * @gfp: flags for allocation
97ac8cae
BA		 819 **/
820
55aa6985 821static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 822 int cleaned_count, gfp_t gfp)
97ac8cae 823{
55aa6985 824 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 825 struct net_device *netdev = adapter->netdev;
826 struct pci_dev *pdev = adapter->pdev;
5f450212 827 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 828 struct e1000_buffer *buffer_info;
829 struct sk_buff *skb;
830 unsigned int i;
2a2293b9 831 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 832
833 i = rx_ring->next_to_use;
834 buffer_info = &rx_ring->buffer_info[i];
835
836 while (cleaned_count--) {
837 skb = buffer_info->skb;
838 if (skb) {
839 skb_trim(skb, 0);
840 goto check_page;
841 }
842
c2fed996 843 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 844 if (unlikely(!skb)) {
845 /* Better luck next round */
846 adapter->alloc_rx_buff_failed++;
847 break;
848 }
849
97ac8cae
BA		 850 buffer_info->skb = skb;
851check_page:
852 /* allocate a new page if necessary */
853 if (!buffer_info->page) {
c2fed996 854 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 855 if (unlikely(!buffer_info->page)) {
856 adapter->alloc_rx_buff_failed++;
857 break;
858 }
859 }
860
37287fae 861 if (!buffer_info->dma) {
0be3f55f 862 buffer_info->dma = dma_map_page(&pdev->dev,
f0ff4398
BA		 863 buffer_info->page, 0,
864 PAGE_SIZE,
0be3f55f 865 DMA_FROM_DEVICE);
37287fae
CP		 866 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
867 adapter->alloc_rx_buff_failed++;
868 break;
869 }
870 }
97ac8cae 871
5f450212
BA		 872 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
873 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 874
875 if (unlikely(++i == rx_ring->count))
876 i = 0;
877 buffer_info = &rx_ring->buffer_info[i];
878 }
879
880 if (likely(rx_ring->next_to_use != i)) {
881 rx_ring->next_to_use = i;
882 if (unlikely(i-- == 0))
883 i = (rx_ring->count - 1);
884
885 /* Force memory writes to complete before letting h/w
886 * know there are new descriptors to fetch. (Only
887 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 888 * such as IA-64).
889 */
97ac8cae 890 wmb();
c6e7f51e 891 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 892 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 893 else
c5083cf6 894 writel(i, rx_ring->tail);
97ac8cae
BA		 895 }
896}
897
70495a50
BA		 898static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
899 struct sk_buff *skb)
900{
901 if (netdev->features & NETIF_F_RXHASH)
e25909bc 902 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
70495a50
BA		 903}
904
bc7f75fa 905/**
55aa6985
BA		 906 * e1000_clean_rx_irq - Send received data up the network stack
907 * @rx_ring: Rx descriptor ring
b50f7bca
JB		 908 * @work_done: output parameter for indicating completed work
909 * @work_to_do: how many packets we can clean
bc7f75fa
AK		 910 *
911 * the return value indicates whether actual cleaning was done, there
912 * is no guarantee that everything was cleaned
913 **/
55aa6985
BA		 914static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
915 int work_to_do)
bc7f75fa 916{
55aa6985 917 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 918 struct net_device *netdev = adapter->netdev;
919 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 920 struct e1000_hw *hw = &adapter->hw;
5f450212 921 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 922 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 923 u32 length, staterr;
bc7f75fa
AK		 924 unsigned int i;
925 int cleaned_count = 0;
3db1cd5c 926 bool cleaned = false;
bc7f75fa
AK		 927 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
928
929 i = rx_ring->next_to_clean;
5f450212
BA		 930 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
931 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 932 buffer_info = &rx_ring->buffer_info[i];
933
5f450212 934 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 935 struct sk_buff *skb;
bc7f75fa
AK		 936
937 if (*work_done >= work_to_do)
938 break;
939 (*work_done)++;
837a1dba 940 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 941
bc7f75fa
AK		 942 skb = buffer_info->skb;
943 buffer_info->skb = NULL;
944
945 prefetch(skb->data - NET_IP_ALIGN);
946
947 i++;
948 if (i == rx_ring->count)
949 i = 0;
5f450212 950 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 951 prefetch(next_rxd);
952
953 next_buffer = &rx_ring->buffer_info[i];
954
3db1cd5c 955 cleaned = true;
bc7f75fa 956 cleaned_count++;
e5fe2541
BA		 957 dma_unmap_single(&pdev->dev, buffer_info->dma,
958 adapter->rx_buffer_len, DMA_FROM_DEVICE);
bc7f75fa
AK		 959 buffer_info->dma = 0;
960
5f450212 961 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 962
e921eb1a 963 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 964 * packet, if that's the case we need to toss it. In fact, we
965 * need to toss every packet with the EOP bit clear and the
966 * next frame that _does_ have the EOP bit set, as it is by
967 * definition only a frame fragment
968 */
5f450212 969 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 970 adapter->flags2 |= FLAG2_IS_DISCARDING;
971
972 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 973 /* All receives must fit into a single buffer */
3bb99fe2 974 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 975 /* recycle */
976 buffer_info->skb = skb;
5f450212 977 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 978 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 979 goto next_desc;
980 }
981
cf955e6c
BG		 982 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
983 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 984 /* recycle */
985 buffer_info->skb = skb;
986 goto next_desc;
987 }
988
eb7c3adb 989 /* adjust length to remove Ethernet CRC */
0184039a
BG		 990 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
991 /* If configured to store CRC, don't subtract FCS,
992 * but keep the FCS bytes out of the total_rx_bytes
993 * counter
994 */
995 if (netdev->features & NETIF_F_RXFCS)
996 total_rx_bytes -= 4;
997 else
998 length -= 4;
999 }
eb7c3adb 1000
bc7f75fa
AK		 1001 total_rx_bytes += length;
1002 total_rx_packets++;
1003
e921eb1a 1004 /* code added for copybreak, this should improve
bc7f75fa 1005 * performance for small packets with large amounts
ad68076e
BA		 1006 * of reassembly being done in the stack
1007 */
bc7f75fa
AK		 1008 if (length < copybreak) {
1009 struct sk_buff *new_skb =
67fd893e 1010 napi_alloc_skb(&adapter->napi, length);
bc7f75fa 1011 if (new_skb) {
808ff676
BA		 1012 skb_copy_to_linear_data_offset(new_skb,
1013 -NET_IP_ALIGN,
1014 (skb->data -
1015 NET_IP_ALIGN),
1016 (length +
1017 NET_IP_ALIGN));
bc7f75fa
AK		 1018 /* save the skb in buffer_info as good */
1019 buffer_info->skb = skb;
1020 skb = new_skb;
1021 }
1022 /* else just continue with the old one */
1023 }
1024 /* end copybreak code */
1025 skb_put(skb, length);
1026
1027 /* Receive Checksum Offload */
2e1706f2 1028 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1029
70495a50
BA		 1030 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1031
5f450212
BA		 1032 e1000_receive_skb(adapter, netdev, skb, staterr,
1033 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1034
1035next_desc:
5f450212 1036 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1037
1038 /* return some buffers to hardware, one at a time is too slow */
1039 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1040 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1041 GFP_ATOMIC);
bc7f75fa
AK		 1042 cleaned_count = 0;
1043 }
1044
1045 /* use prefetched values */
1046 rx_desc = next_rxd;
1047 buffer_info = next_buffer;
5f450212
BA		 1048
1049 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1050 }
1051 rx_ring->next_to_clean = i;
1052
1053 cleaned_count = e1000_desc_unused(rx_ring);
1054 if (cleaned_count)
55aa6985 1055 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1056
bc7f75fa 1057 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1058 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1059 return cleaned;
1060}
1061
55aa6985 1062static void e1000_put_txbuf(struct e1000_ring *tx_ring,
377b6273
FF		 1063 struct e1000_buffer *buffer_info,
1064 bool drop)
bc7f75fa 1065{
55aa6985
BA		 1066 struct e1000_adapter *adapter = tx_ring->adapter;
1067
03b1320d
AD		 1068 if (buffer_info->dma) {
1069 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1070 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1071 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1072 else
0be3f55f
NN		 1073 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1074 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1075 buffer_info->dma = 0;
1076 }
bc7f75fa 1077 if (buffer_info->skb) {
377b6273
FF		 1078 if (drop)
1079 dev_kfree_skb_any(buffer_info->skb);
1080 else
1081 dev_consume_skb_any(buffer_info->skb);
bc7f75fa
AK		 1082 buffer_info->skb = NULL;
1083 }
1b7719c4 1084 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1085}
1086
41cec6f1 1087static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1088{
41cec6f1 1089 struct e1000_adapter *adapter = container_of(work,
f0ff4398
BA		 1090 struct e1000_adapter,
1091 print_hang_task);
09357b00 1092 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1093 struct e1000_ring *tx_ring = adapter->tx_ring;
1094 unsigned int i = tx_ring->next_to_clean;
1095 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1096 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1097 struct e1000_hw *hw = &adapter->hw;
1098 u16 phy_status, phy_1000t_status, phy_ext_status;
1099 u16 pci_status;
1100
615b32af
JB		 1101 if (test_bit(__E1000_DOWN, &adapter->state))
1102 return;
1103
e5fe2541 1104 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1105 /* May be block on write-back, flush and detect again
09357b00
JK		 1106 * flush pending descriptor writebacks to memory
1107 */
1108 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1109 /* execute the writes immediately */
1110 e1e_flush();
e921eb1a 1111 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1112 * the write is successful
1113 */
1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1115 /* execute the writes immediately */
1116 e1e_flush();
09357b00
JK		 1117 adapter->tx_hang_recheck = true;
1118 return;
1119 }
09357b00 1120 adapter->tx_hang_recheck = false;
d9554e96
DE		 1121
1122 if (er32(TDH(0)) == er32(TDT(0))) {
1123 e_dbg("false hang detected, ignoring\n");
1124 return;
1125 }
1126
1127 /* Real hang detected */
09357b00
JK		 1128 netif_stop_queue(netdev);
1129
c2ade1a4
BA		 1130 e1e_rphy(hw, MII_BMSR, &phy_status);
1131 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1132 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
bc7f75fa 1133
41cec6f1
BA		 1134 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1135
1136 /* detected Hardware unit hang */
1137 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1138 " TDH <%x>\n"
1139 " TDT <%x>\n"
1140 " next_to_use <%x>\n"
1141 " next_to_clean <%x>\n"
1142 "buffer_info[next_to_clean]:\n"
1143 " time_stamp <%lx>\n"
1144 " next_to_watch <%x>\n"
1145 " jiffies <%lx>\n"
41cec6f1
BA		 1146 " next_to_watch.status <%x>\n"
1147 "MAC Status <%x>\n"
1148 "PHY Status <%x>\n"
1149 "PHY 1000BASE-T Status <%x>\n"
1150 "PHY Extended Status <%x>\n"
1151 "PCI Status <%x>\n",
e5fe2541
BA		 1152 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1153 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1154 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1155 phy_status, phy_1000t_status, phy_ext_status, pci_status);
7c0427ee 1156
d9554e96
DE		 1157 e1000e_dump(adapter);
1158
7c0427ee
BA		 1159 /* Suggest workaround for known h/w issue */
1160 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1161 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1162}
1163
b67e1913
BA		 1164/**
1165 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1166 * @work: pointer to work struct
1167 *
1168 * This work function polls the TSYNCTXCTL valid bit to determine when a
1169 * timestamp has been taken for the current stored skb. The timestamp must
1170 * be for this skb because only one such packet is allowed in the queue.
1171 */
1172static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1173{
1174 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1175 tx_hwtstamp_work);
1176 struct e1000_hw *hw = &adapter->hw;
1177
b67e1913 1178 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
5012863b 1179 struct sk_buff *skb = adapter->tx_hwtstamp_skb;
b67e1913
BA		 1180 struct skb_shared_hwtstamps shhwtstamps;
1181 u64 txstmp;
1182
1183 txstmp = er32(TXSTMPL);
1184 txstmp |= (u64)er32(TXSTMPH) << 32;
1185
1186 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1187
5012863b
JK		 1188 /* Clear the global tx_hwtstamp_skb pointer and force writes
1189 * prior to notifying the stack of a Tx timestamp.
1190 */
b67e1913 1191 adapter->tx_hwtstamp_skb = NULL;
5012863b
JK		 1192 wmb(); /* force write prior to skb_tstamp_tx */
1193
1194 skb_tstamp_tx(skb, &shhwtstamps);
377b6273 1195 dev_consume_skb_any(skb);
59c871c5
JK		 1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1197 + adapter->tx_timeout_factor * HZ)) {
1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1199 adapter->tx_hwtstamp_skb = NULL;
1200 adapter->tx_hwtstamp_timeouts++;
c5ffe7e1 1201 e_warn("clearing Tx timestamp hang\n");
b67e1913
BA		 1202 } else {
1203 /* reschedule to check later */
1204 schedule_work(&adapter->tx_hwtstamp_work);
1205 }
1206}
1207
bc7f75fa
AK		 1208/**
1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1210 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1211 *
1212 * the return value indicates whether actual cleaning was done, there
1213 * is no guarantee that everything was cleaned
1214 **/
55aa6985 1215static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1216{
55aa6985 1217 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1218 struct net_device *netdev = adapter->netdev;
1219 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1220 struct e1000_tx_desc *tx_desc, *eop_desc;
1221 struct e1000_buffer *buffer_info;
1222 unsigned int i, eop;
1223 unsigned int count = 0;
bc7f75fa 1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1225 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1226
1227 i = tx_ring->next_to_clean;
1228 eop = tx_ring->buffer_info[i].next_to_watch;
1229 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1230
12d04a3c
AD		 1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1232 (count < tx_ring->count)) {
a86043c2 1233 bool cleaned = false;
6cf08d1c 1234
837a1dba 1235 dma_rmb(); /* read buffer_info after eop_desc */
a86043c2 1236 for (; !cleaned; count++) {
bc7f75fa
AK		 1237 tx_desc = E1000_TX_DESC(*tx_ring, i);
1238 buffer_info = &tx_ring->buffer_info[i];
1239 cleaned = (i == eop);
1240
1241 if (cleaned) {
9ed318d5
TH		 1242 total_tx_packets += buffer_info->segs;
1243 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1244 if (buffer_info->skb) {
1245 bytes_compl += buffer_info->skb->len;
1246 pkts_compl++;
1247 }
bc7f75fa
AK		 1248 }
1249
377b6273 1250 e1000_put_txbuf(tx_ring, buffer_info, false);
bc7f75fa
AK		 1251 tx_desc->upper.data = 0;
1252
1253 i++;
1254 if (i == tx_ring->count)
1255 i = 0;
1256 }
1257
dac87619
TL		 1258 if (i == tx_ring->next_to_use)
1259 break;
bc7f75fa
AK		 1260 eop = tx_ring->buffer_info[i].next_to_watch;
1261 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1262 }
1263
1264 tx_ring->next_to_clean = i;
1265
3f0cfa3b
TH		 1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1267
bc7f75fa 1268#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1269 if (count && netif_carrier_ok(netdev) &&
1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1271 /* Make sure that anybody stopping the queue after this
1272 * sees the new next_to_clean.
1273 */
1274 smp_mb();
1275
1276 if (netif_queue_stopped(netdev) &&
1277 !(test_bit(__E1000_DOWN, &adapter->state))) {
1278 netif_wake_queue(netdev);
1279 ++adapter->restart_queue;
1280 }
1281 }
1282
1283 if (adapter->detect_tx_hung) {
e921eb1a 1284 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1285 * check with the clearing of time_stamp and movement of i
1286 */
3db1cd5c 1287 adapter->detect_tx_hung = false;
12d04a3c
AD		 1288 if (tx_ring->buffer_info[i].time_stamp &&
1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1290 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1291 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1292 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1293 else
1294 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1295 }
1296 adapter->total_tx_bytes += total_tx_bytes;
1297 adapter->total_tx_packets += total_tx_packets;
807540ba 1298 return count < tx_ring->count;
bc7f75fa
AK		 1299}
1300
bc7f75fa
AK		 1301/**
1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1303 * @rx_ring: Rx descriptor ring
b50f7bca
JB		 1304 * @work_done: output parameter for indicating completed work
1305 * @work_to_do: how many packets we can clean
bc7f75fa
AK		 1306 *
1307 * the return value indicates whether actual cleaning was done, there
1308 * is no guarantee that everything was cleaned
1309 **/
55aa6985
BA		 1310static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1311 int work_to_do)
bc7f75fa 1312{
55aa6985 1313 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1314 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1315 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1316 struct net_device *netdev = adapter->netdev;
1317 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1318 struct e1000_buffer *buffer_info, *next_buffer;
1319 struct e1000_ps_page *ps_page;
1320 struct sk_buff *skb;
1321 unsigned int i, j;
1322 u32 length, staterr;
1323 int cleaned_count = 0;
3db1cd5c 1324 bool cleaned = false;
bc7f75fa
AK		 1325 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1326
1327 i = rx_ring->next_to_clean;
1328 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1329 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1330 buffer_info = &rx_ring->buffer_info[i];
1331
1332 while (staterr & E1000_RXD_STAT_DD) {
1333 if (*work_done >= work_to_do)
1334 break;
1335 (*work_done)++;
1336 skb = buffer_info->skb;
837a1dba 1337 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1338
1339 /* in the packet split case this is header only */
1340 prefetch(skb->data - NET_IP_ALIGN);
1341
1342 i++;
1343 if (i == rx_ring->count)
1344 i = 0;
1345 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1346 prefetch(next_rxd);
1347
1348 next_buffer = &rx_ring->buffer_info[i];
1349
3db1cd5c 1350 cleaned = true;
bc7f75fa 1351 cleaned_count++;
0be3f55f 1352 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1353 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1354 buffer_info->dma = 0;
1355
af667a29 1356 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1357 if (!(staterr & E1000_RXD_STAT_EOP))
1358 adapter->flags2 |= FLAG2_IS_DISCARDING;
1359
1360 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1361 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1362 dev_kfree_skb_irq(skb);
b94b5028
JB		 1363 if (staterr & E1000_RXD_STAT_EOP)
1364 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1365 goto next_desc;
1366 }
1367
cf955e6c
BG		 1368 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1369 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1370 dev_kfree_skb_irq(skb);
1371 goto next_desc;
1372 }
1373
1374 length = le16_to_cpu(rx_desc->wb.middle.length0);
1375
1376 if (!length) {
ef456f85 1377 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1378 dev_kfree_skb_irq(skb);
1379 goto next_desc;
1380 }
1381
1382 /* Good Receive */
1383 skb_put(skb, length);
1384
1385 {
e921eb1a 1386 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1387 * it more efficient than reusing j
1388 */
1389 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1390
e921eb1a 1391 /* page alloc/put takes too long and effects small
0e15df49 1392 * packet throughput, so unsplit small packets and
ab400b0d 1393 * save the alloc/put
ad68076e 1394 */
0e15df49
BA		 1395 if (l1 && (l1 <= copybreak) &&
1396 ((length + l1) <= adapter->rx_ps_bsize0)) {
0e15df49
BA		 1397 ps_page = &buffer_info->ps_pages[0];
1398
0e15df49
BA		 1399 dma_sync_single_for_cpu(&pdev->dev,
1400 ps_page->dma,
1401 PAGE_SIZE,
1402 DMA_FROM_DEVICE);
ab400b0d
AV		 1403 memcpy(skb_tail_pointer(skb),
1404 page_address(ps_page->page), l1);
0e15df49
BA		 1405 dma_sync_single_for_device(&pdev->dev,
1406 ps_page->dma,
1407 PAGE_SIZE,
1408 DMA_FROM_DEVICE);
1409
1410 /* remove the CRC */
0184039a
BG		 1411 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1412 if (!(netdev->features & NETIF_F_RXFCS))
1413 l1 -= 4;
1414 }
0e15df49
BA		 1415
1416 skb_put(skb, l1);
1417 goto copydone;
e80bd1d1 1418 } /* if */
bc7f75fa
AK		 1419 }
1420
1421 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1422 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1423 if (!length)
1424 break;
1425
47f44e40 1426 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1427 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1428 DMA_FROM_DEVICE);
bc7f75fa
AK		 1429 ps_page->dma = 0;
1430 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1431 ps_page->page = NULL;
1432 skb->len += length;
1433 skb->data_len += length;
98a045d7 1434 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1435 }
1436
eb7c3adb
JK		 1437 /* strip the ethernet crc, problem is we're using pages now so
1438 * this whole operation can get a little cpu intensive
1439 */
0184039a
BG		 1440 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1441 if (!(netdev->features & NETIF_F_RXFCS))
1442 pskb_trim(skb, skb->len - 4);
1443 }
eb7c3adb 1444
bc7f75fa
AK		 1445copydone:
1446 total_rx_bytes += skb->len;
1447 total_rx_packets++;
1448
2e1706f2 1449 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1450
70495a50
BA		 1451 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1452
bc7f75fa 1453 if (rx_desc->wb.upper.header_status &
17e813ec 1454 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
bc7f75fa
AK		 1455 adapter->rx_hdr_split++;
1456
b67e1913
BA		 1457 e1000_receive_skb(adapter, netdev, skb, staterr,
1458 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1459
1460next_desc:
1461 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1462 buffer_info->skb = NULL;
1463
1464 /* return some buffers to hardware, one at a time is too slow */
1465 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1466 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1467 GFP_ATOMIC);
bc7f75fa
AK		 1468 cleaned_count = 0;
1469 }
1470
1471 /* use prefetched values */
1472 rx_desc = next_rxd;
1473 buffer_info = next_buffer;
1474
1475 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1476 }
1477 rx_ring->next_to_clean = i;
1478
1479 cleaned_count = e1000_desc_unused(rx_ring);
1480 if (cleaned_count)
55aa6985 1481 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1482
bc7f75fa 1483 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1484 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1485 return cleaned;
1486}
1487
97ac8cae 1488static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
66501f56 1489 u16 length)
97ac8cae
BA		 1490{
1491 bi->page = NULL;
1492 skb->len += length;
1493 skb->data_len += length;
98a045d7 1494 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1495}
1496
1497/**
1498 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
b50f7bca
JB		 1499 * @rx_ring: Rx descriptor ring
1500 * @work_done: output parameter for indicating completed work
1501 * @work_to_do: how many packets we can clean
97ac8cae
BA		 1502 *
1503 * the return value indicates whether actual cleaning was done, there
1504 * is no guarantee that everything was cleaned
1505 **/
55aa6985
BA		 1506static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1507 int work_to_do)
97ac8cae 1508{
55aa6985 1509 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1510 struct net_device *netdev = adapter->netdev;
1511 struct pci_dev *pdev = adapter->pdev;
5f450212 1512 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1513 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1514 u32 length, staterr;
97ac8cae
BA		 1515 unsigned int i;
1516 int cleaned_count = 0;
1517 bool cleaned = false;
362e20ca 1518 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
17e813ec 1519 struct skb_shared_info *shinfo;
97ac8cae
BA		 1520
1521 i = rx_ring->next_to_clean;
5f450212
BA		 1522 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1524 buffer_info = &rx_ring->buffer_info[i];
1525
5f450212 1526 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1527 struct sk_buff *skb;
97ac8cae
BA		 1528
1529 if (*work_done >= work_to_do)
1530 break;
1531 (*work_done)++;
837a1dba 1532 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1533
97ac8cae
BA		 1534 skb = buffer_info->skb;
1535 buffer_info->skb = NULL;
1536
1537 ++i;
1538 if (i == rx_ring->count)
1539 i = 0;
5f450212 1540 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1541 prefetch(next_rxd);
1542
1543 next_buffer = &rx_ring->buffer_info[i];
1544
1545 cleaned = true;
1546 cleaned_count++;
0be3f55f
NN		 1547 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1548 DMA_FROM_DEVICE);
97ac8cae
BA		 1549 buffer_info->dma = 0;
1550
5f450212 1551 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1552
1553 /* errors is only valid for DD + EOP descriptors */
5f450212 1554 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1555 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1556 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1557 /* recycle both page and skb */
1558 buffer_info->skb = skb;
1559 /* an error means any chain goes out the window too */
1560 if (rx_ring->rx_skb_top)
1561 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1562 rx_ring->rx_skb_top = NULL;
1563 goto next_desc;
97ac8cae 1564 }
f0f1a172 1565#define rxtop (rx_ring->rx_skb_top)
5f450212 1566 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1567 /* this descriptor is only the beginning (or middle) */
1568 if (!rxtop) {
1569 /* this is the beginning of a chain */
1570 rxtop = skb;
1571 skb_fill_page_desc(rxtop, 0, buffer_info->page,
f0ff4398 1572 0, length);
97ac8cae
BA		 1573 } else {
1574 /* this is the middle of a chain */
17e813ec
BA		 1575 shinfo = skb_shinfo(rxtop);
1576 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1577 buffer_info->page, 0,
1578 length);
97ac8cae
BA		 1579 /* re-use the skb, only consumed the page */
1580 buffer_info->skb = skb;
1581 }
1582 e1000_consume_page(buffer_info, rxtop, length);
1583 goto next_desc;
1584 } else {
1585 if (rxtop) {
1586 /* end of the chain */
17e813ec
BA		 1587 shinfo = skb_shinfo(rxtop);
1588 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1589 buffer_info->page, 0,
1590 length);
97ac8cae 1591 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1592 * page
1593 */
97ac8cae
BA		 1594 buffer_info->skb = skb;
1595 skb = rxtop;
1596 rxtop = NULL;
1597 e1000_consume_page(buffer_info, skb, length);
1598 } else {
1599 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1600 * copybreak to save the put_page/alloc_page
1601 */
97ac8cae
BA		 1602 if (length <= copybreak &&
1603 skb_tailroom(skb) >= length) {
ab400b0d
AV		 1604 memcpy(skb_tail_pointer(skb),
1605 page_address(buffer_info->page),
97ac8cae 1606 length);
97ac8cae 1607 /* re-use the page, so don't erase
e921eb1a
BA		 1608 * buffer_info->page
1609 */
97ac8cae
BA		 1610 skb_put(skb, length);
1611 } else {
1612 skb_fill_page_desc(skb, 0,
f0ff4398
BA		 1613 buffer_info->page, 0,
1614 length);
97ac8cae 1615 e1000_consume_page(buffer_info, skb,
f0ff4398 1616 length);
97ac8cae
BA		 1617 }
1618 }
1619 }
1620
2e1706f2
BA		 1621 /* Receive Checksum Offload */
1622 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1623
70495a50
BA		 1624 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1625
97ac8cae
BA		 1626 /* probably a little skewed due to removing CRC */
1627 total_rx_bytes += skb->len;
1628 total_rx_packets++;
1629
1630 /* eth type trans needs skb->data to point to something */
1631 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1632 e_err("pskb_may_pull failed.\n");
ef5ab89c 1633 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1634 goto next_desc;
1635 }
1636
5f450212
BA		 1637 e1000_receive_skb(adapter, netdev, skb, staterr,
1638 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1639
1640next_desc:
5f450212 1641 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1642
1643 /* return some buffers to hardware, one at a time is too slow */
1644 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1645 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1646 GFP_ATOMIC);
97ac8cae
BA		 1647 cleaned_count = 0;
1648 }
1649
1650 /* use prefetched values */
1651 rx_desc = next_rxd;
1652 buffer_info = next_buffer;
5f450212
BA		 1653
1654 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1655 }
1656 rx_ring->next_to_clean = i;
1657
1658 cleaned_count = e1000_desc_unused(rx_ring);
1659 if (cleaned_count)
55aa6985 1660 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1661
1662 adapter->total_rx_bytes += total_rx_bytes;
1663 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1664 return cleaned;
1665}
1666
bc7f75fa
AK		 1667/**
1668 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1669 * @rx_ring: Rx descriptor ring
bc7f75fa 1670 **/
55aa6985 1671static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1672{
55aa6985 1673 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1674 struct e1000_buffer *buffer_info;
1675 struct e1000_ps_page *ps_page;
1676 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1677 unsigned int i, j;
1678
1679 /* Free all the Rx ring sk_buffs */
1680 for (i = 0; i < rx_ring->count; i++) {
1681 buffer_info = &rx_ring->buffer_info[i];
1682 if (buffer_info->dma) {
1683 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1684 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1685 adapter->rx_buffer_len,
0be3f55f 1686 DMA_FROM_DEVICE);
97ac8cae 1687 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1688 dma_unmap_page(&pdev->dev, buffer_info->dma,
f0ff4398 1689 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa 1690 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1691 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1692 adapter->rx_ps_bsize0,
0be3f55f 1693 DMA_FROM_DEVICE);
bc7f75fa
AK		 1694 buffer_info->dma = 0;
1695 }
1696
97ac8cae
BA		 1697 if (buffer_info->page) {
1698 put_page(buffer_info->page);
1699 buffer_info->page = NULL;
1700 }
1701
bc7f75fa
AK		 1702 if (buffer_info->skb) {
1703 dev_kfree_skb(buffer_info->skb);
1704 buffer_info->skb = NULL;
1705 }
1706
1707 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1708 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1709 if (!ps_page->page)
1710 break;
0be3f55f
NN		 1711 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1712 DMA_FROM_DEVICE);
bc7f75fa
AK		 1713 ps_page->dma = 0;
1714 put_page(ps_page->page);
1715 ps_page->page = NULL;
1716 }
1717 }
1718
1719 /* there also may be some cached data from a chained receive */
1720 if (rx_ring->rx_skb_top) {
1721 dev_kfree_skb(rx_ring->rx_skb_top);
1722 rx_ring->rx_skb_top = NULL;
1723 }
1724
bc7f75fa
AK		 1725 /* Zero out the descriptor ring */
1726 memset(rx_ring->desc, 0, rx_ring->size);
1727
1728 rx_ring->next_to_clean = 0;
1729 rx_ring->next_to_use = 0;
b94b5028 1730 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1731}
1732
a8f88ff5
JB		 1733static void e1000e_downshift_workaround(struct work_struct *work)
1734{
1735 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 1736 struct e1000_adapter,
1737 downshift_task);
a8f88ff5 1738
615b32af
JB		 1739 if (test_bit(__E1000_DOWN, &adapter->state))
1740 return;
1741
a8f88ff5
JB		 1742 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1743}
1744
bc7f75fa
AK		 1745/**
1746 * e1000_intr_msi - Interrupt Handler
1747 * @irq: interrupt number
1748 * @data: pointer to a network interface device structure
1749 **/
8bb62869 1750static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
bc7f75fa
AK		 1751{
1752 struct net_device *netdev = data;
1753 struct e1000_adapter *adapter = netdev_priv(netdev);
1754 struct e1000_hw *hw = &adapter->hw;
1755 u32 icr = er32(ICR);
1756
e921eb1a 1757 /* read ICR disables interrupts using IAM */
573cca8c 1758 if (icr & E1000_ICR_LSC) {
f92518dd 1759 hw->mac.get_link_status = true;
e921eb1a 1760 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1761 * disconnect (LSC) before accessing any PHY registers
1762 */
bc7f75fa
AK		 1763 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1764 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1765 schedule_work(&adapter->downshift_task);
bc7f75fa 1766
e921eb1a 1767 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1768 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1769 * adapter in watchdog
1770 */
bc7f75fa
AK		 1771 if (netif_carrier_ok(netdev) &&
1772 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1773 /* disable receives */
1774 u32 rctl = er32(RCTL);
6cf08d1c 1775
bc7f75fa 1776 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1777 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1778 }
1779 /* guard against interrupt when we're going down */
1780 if (!test_bit(__E1000_DOWN, &adapter->state))
d5ad7a6a 1781 mod_timer(&adapter->watchdog_timer, jiffies + 1);
bc7f75fa
AK		 1782 }
1783
94fb848b 1784 /* Reset on uncorrectable ECC error */
c8744f44 1785 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
94fb848b
BA		 1786 u32 pbeccsts = er32(PBECCSTS);
1787
1788 adapter->corr_errors +=
1789 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1790 adapter->uncorr_errors +=
b9a45254 1791 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
94fb848b
BA		 1792
1793 /* Do the reset outside of interrupt context */
1794 schedule_work(&adapter->reset_task);
1795
1796 /* return immediately since reset is imminent */
1797 return IRQ_HANDLED;
1798 }
1799
288379f0 1800 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1801 adapter->total_tx_bytes = 0;
1802 adapter->total_tx_packets = 0;
1803 adapter->total_rx_bytes = 0;
1804 adapter->total_rx_packets = 0;
288379f0 1805 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1806 }
1807
1808 return IRQ_HANDLED;
1809}
1810
1811/**
1812 * e1000_intr - Interrupt Handler
1813 * @irq: interrupt number
1814 * @data: pointer to a network interface device structure
1815 **/
8bb62869 1816static irqreturn_t e1000_intr(int __always_unused irq, void *data)
bc7f75fa
AK		 1817{
1818 struct net_device *netdev = data;
1819 struct e1000_adapter *adapter = netdev_priv(netdev);
1820 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1821 u32 rctl, icr = er32(ICR);
4662e82b 1822
a68ea775 1823 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
e80bd1d1 1824 return IRQ_NONE; /* Not our interrupt */
bc7f75fa 1825
e921eb1a 1826 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1827 * not set, then the adapter didn't send an interrupt
1828 */
bc7f75fa
AK		 1829 if (!(icr & E1000_ICR_INT_ASSERTED))
1830 return IRQ_NONE;
1831
e921eb1a 1832 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1833 * interrupts are masked. No need for the
1834 * IMC write
1835 */
bc7f75fa 1836
573cca8c 1837 if (icr & E1000_ICR_LSC) {
f92518dd 1838 hw->mac.get_link_status = true;
e921eb1a 1839 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1840 * disconnect (LSC) before accessing any PHY registers
1841 */
bc7f75fa
AK		 1842 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1843 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1844 schedule_work(&adapter->downshift_task);
bc7f75fa 1845
e921eb1a 1846 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1847 * For packet buffer work-around on link down event;
1848 * disable receives here in the ISR and
1849 * reset adapter in watchdog
1850 */
1851 if (netif_carrier_ok(netdev) &&
1852 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1853 /* disable receives */
1854 rctl = er32(RCTL);
1855 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1856 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1857 }
1858 /* guard against interrupt when we're going down */
1859 if (!test_bit(__E1000_DOWN, &adapter->state))
d5ad7a6a 1860 mod_timer(&adapter->watchdog_timer, jiffies + 1);
bc7f75fa
AK		 1861 }
1862
94fb848b 1863 /* Reset on uncorrectable ECC error */
c8744f44 1864 if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) {
94fb848b
BA		 1865 u32 pbeccsts = er32(PBECCSTS);
1866
1867 adapter->corr_errors +=
1868 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1869 adapter->uncorr_errors +=
b9a45254 1870 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
94fb848b
BA		 1871
1872 /* Do the reset outside of interrupt context */
1873 schedule_work(&adapter->reset_task);
1874
1875 /* return immediately since reset is imminent */
1876 return IRQ_HANDLED;
1877 }
1878
288379f0 1879 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1880 adapter->total_tx_bytes = 0;
1881 adapter->total_tx_packets = 0;
1882 adapter->total_rx_bytes = 0;
1883 adapter->total_rx_packets = 0;
288379f0 1884 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1885 }
1886
1887 return IRQ_HANDLED;
1888}
1889
8bb62869 1890static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
4662e82b
BA		 1891{
1892 struct net_device *netdev = data;
1893 struct e1000_adapter *adapter = netdev_priv(netdev);
1894 struct e1000_hw *hw = &adapter->hw;
116f4a64 1895 u32 icr = er32(ICR);
745d0bd3 1896
361a954e
BP		 1897 if (icr & adapter->eiac_mask)
1898 ew32(ICS, (icr & adapter->eiac_mask));
1899
4aea7a5c 1900 if (icr & E1000_ICR_LSC) {
4aea7a5c
BP		 1901 hw->mac.get_link_status = true;
1902 /* guard against interrupt when we're going down */
1903 if (!test_bit(__E1000_DOWN, &adapter->state))
d5ad7a6a 1904 mod_timer(&adapter->watchdog_timer, jiffies + 1);
4aea7a5c 1905 }
4662e82b 1906
1f0ea197 1907 if (!test_bit(__E1000_DOWN, &adapter->state))
116f4a64 1908 ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK);
4662e82b 1909
4662e82b
BA		 1910 return IRQ_HANDLED;
1911}
1912
8bb62869 1913static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
4662e82b
BA		 1914{
1915 struct net_device *netdev = data;
1916 struct e1000_adapter *adapter = netdev_priv(netdev);
1917 struct e1000_hw *hw = &adapter->hw;
1918 struct e1000_ring *tx_ring = adapter->tx_ring;
1919
4662e82b
BA		 1920 adapter->total_tx_bytes = 0;
1921 adapter->total_tx_packets = 0;
1922
55aa6985 1923 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1924 /* Ring was not completely cleaned, so fire another interrupt */
1925 ew32(ICS, tx_ring->ims_val);
1926
0a8047ac
BP		 1927 if (!test_bit(__E1000_DOWN, &adapter->state))
1928 ew32(IMS, adapter->tx_ring->ims_val);
1929
4662e82b
BA		 1930 return IRQ_HANDLED;
1931}
1932
8bb62869 1933static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
4662e82b
BA		 1934{
1935 struct net_device *netdev = data;
1936 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1937 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1938
1939 /* Write the ITR value calculated at the end of the
1940 * previous interrupt.
1941 */
55aa6985 1942 if (rx_ring->set_itr) {
b77ac46b
DF		 1943 u32 itr = rx_ring->itr_val ?
1944 1000000000 / (rx_ring->itr_val * 256) : 0;
1945
1946 writel(itr, rx_ring->itr_register);
55aa6985 1947 rx_ring->set_itr = 0;
4662e82b
BA		 1948 }
1949
288379f0 1950 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1951 adapter->total_rx_bytes = 0;
1952 adapter->total_rx_packets = 0;
288379f0 1953 __napi_schedule(&adapter->napi);
4662e82b
BA		 1954 }
1955 return IRQ_HANDLED;
1956}
1957
1958/**
1959 * e1000_configure_msix - Configure MSI-X hardware
b50f7bca 1960 * @adapter: board private structure
4662e82b
BA		 1961 *
1962 * e1000_configure_msix sets up the hardware to properly
1963 * generate MSI-X interrupts.
1964 **/
1965static void e1000_configure_msix(struct e1000_adapter *adapter)
1966{
1967 struct e1000_hw *hw = &adapter->hw;
1968 struct e1000_ring *rx_ring = adapter->rx_ring;
1969 struct e1000_ring *tx_ring = adapter->tx_ring;
1970 int vector = 0;
1971 u32 ctrl_ext, ivar = 0;
1972
1973 adapter->eiac_mask = 0;
1974
1975 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1976 if (hw->mac.type == e1000_82574) {
1977 u32 rfctl = er32(RFCTL);
6cf08d1c 1978
4662e82b
BA		 1979 rfctl |= E1000_RFCTL_ACK_DIS;
1980 ew32(RFCTL, rfctl);
1981 }
1982
4662e82b
BA		 1983 /* Configure Rx vector */
1984 rx_ring->ims_val = E1000_IMS_RXQ0;
1985 adapter->eiac_mask |= rx_ring->ims_val;
1986 if (rx_ring->itr_val)
1987 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1988 rx_ring->itr_register);
4662e82b 1989 else
c5083cf6 1990 writel(1, rx_ring->itr_register);
4662e82b
BA		 1991 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1992
1993 /* Configure Tx vector */
1994 tx_ring->ims_val = E1000_IMS_TXQ0;
1995 vector++;
1996 if (tx_ring->itr_val)
1997 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1998 tx_ring->itr_register);
4662e82b 1999 else
c5083cf6 2000 writel(1, tx_ring->itr_register);
4662e82b
BA		 2001 adapter->eiac_mask |= tx_ring->ims_val;
2002 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2003
2004 /* set vector for Other Causes, e.g. link changes */
2005 vector++;
2006 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2007 if (rx_ring->itr_val)
2008 writel(1000000000 / (rx_ring->itr_val * 256),
2009 hw->hw_addr + E1000_EITR_82574(vector));
2010 else
2011 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2012
2013 /* Cause Tx interrupts on every write back */
18dd2392 2014 ivar |= BIT(31);
4662e82b
BA		 2015
2016 ew32(IVAR, ivar);
2017
2018 /* enable MSI-X PBA support */
0a8047ac
BP		 2019 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2020 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
4662e82b
BA		 2021 ew32(CTRL_EXT, ctrl_ext);
2022 e1e_flush();
2023}
2024
2025void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2026{
2027 if (adapter->msix_entries) {
2028 pci_disable_msix(adapter->pdev);
2029 kfree(adapter->msix_entries);
2030 adapter->msix_entries = NULL;
2031 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2032 pci_disable_msi(adapter->pdev);
2033 adapter->flags &= ~FLAG_MSI_ENABLED;
2034 }
4662e82b
BA		 2035}
2036
2037/**
2038 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
b50f7bca 2039 * @adapter: board private structure
4662e82b
BA		 2040 *
2041 * Attempt to configure interrupts using the best available
2042 * capabilities of the hardware and kernel.
2043 **/
2044void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2045{
2046 int err;
8e86acd7 2047 int i;
4662e82b
BA		 2048
2049 switch (adapter->int_mode) {
2050 case E1000E_INT_MODE_MSIX:
2051 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2052 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2053 adapter->msix_entries = kcalloc(adapter->num_vectors,
17e813ec
BA		 2054 sizeof(struct
2055 msix_entry),
2056 GFP_KERNEL);
4662e82b 2057 if (adapter->msix_entries) {
0cc7c959
AG		 2058 struct e1000_adapter *a = adapter;
2059
8e86acd7 2060 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2061 adapter->msix_entries[i].entry = i;
2062
0cc7c959
AG		 2063 err = pci_enable_msix_range(a->pdev,
2064 a->msix_entries,
2065 a->num_vectors,
2066 a->num_vectors);
2067 if (err > 0)
4662e82b
BA		 2068 return;
2069 }
2070 /* MSI-X failed, so fall through and try MSI */
ef456f85 2071 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2072 e1000e_reset_interrupt_capability(adapter);
2073 }
2074 adapter->int_mode = E1000E_INT_MODE_MSI;
5463fce6 2075 fallthrough;
4662e82b
BA		 2076 case E1000E_INT_MODE_MSI:
2077 if (!pci_enable_msi(adapter->pdev)) {
2078 adapter->flags |= FLAG_MSI_ENABLED;
2079 } else {
2080 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2081 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b 2082 }
5463fce6 2083 fallthrough;
4662e82b
BA		 2084 case E1000E_INT_MODE_LEGACY:
2085 /* Don't do anything; this is the system default */
2086 break;
2087 }
8e86acd7
JK		 2088
2089 /* store the number of vectors being used */
2090 adapter->num_vectors = 1;
4662e82b
BA		 2091}
2092
2093/**
2094 * e1000_request_msix - Initialize MSI-X interrupts
b50f7bca 2095 * @adapter: board private structure
4662e82b
BA		 2096 *
2097 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2098 * kernel.
2099 **/
2100static int e1000_request_msix(struct e1000_adapter *adapter)
2101{
2102 struct net_device *netdev = adapter->netdev;
2103 int err = 0, vector = 0;
2104
2105 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2106 snprintf(adapter->rx_ring->name,
2107 sizeof(adapter->rx_ring->name) - 1,
135e7245 2108 "%.14s-rx-0", netdev->name);
4662e82b
BA		 2109 else
2110 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2111 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2112 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2113 netdev);
2114 if (err)
5015e53a 2115 return err;
c5083cf6
BA		 2116 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2117 E1000_EITR_82574(vector);
4662e82b
BA		 2118 adapter->rx_ring->itr_val = adapter->itr;
2119 vector++;
2120
2121 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2122 snprintf(adapter->tx_ring->name,
2123 sizeof(adapter->tx_ring->name) - 1,
135e7245 2124 "%.14s-tx-0", netdev->name);
4662e82b
BA		 2125 else
2126 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2127 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2128 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2129 netdev);
2130 if (err)
5015e53a 2131 return err;
c5083cf6
BA		 2132 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2133 E1000_EITR_82574(vector);
4662e82b
BA		 2134 adapter->tx_ring->itr_val = adapter->itr;
2135 vector++;
2136
2137 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2138 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2139 if (err)
5015e53a 2140 return err;
4662e82b
BA		 2141
2142 e1000_configure_msix(adapter);
5015e53a 2143
4662e82b 2144 return 0;
4662e82b
BA		 2145}
2146
f8d59f78
BA		 2147/**
2148 * e1000_request_irq - initialize interrupts
b50f7bca 2149 * @adapter: board private structure
f8d59f78
BA		 2150 *
2151 * Attempts to configure interrupts using the best available
2152 * capabilities of the hardware and kernel.
2153 **/
bc7f75fa
AK		 2154static int e1000_request_irq(struct e1000_adapter *adapter)
2155{
2156 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2157 int err;
2158
4662e82b
BA		 2159 if (adapter->msix_entries) {
2160 err = e1000_request_msix(adapter);
2161 if (!err)
2162 return err;
2163 /* fall back to MSI */
2164 e1000e_reset_interrupt_capability(adapter);
2165 adapter->int_mode = E1000E_INT_MODE_MSI;
2166 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2167 }
4662e82b 2168 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2169 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2170 netdev->name, netdev);
2171 if (!err)
2172 return err;
bc7f75fa 2173
4662e82b
BA		 2174 /* fall back to legacy interrupt */
2175 e1000e_reset_interrupt_capability(adapter);
2176 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2177 }
2178
a0607fd3 2179 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2180 netdev->name, netdev);
2181 if (err)
2182 e_err("Unable to allocate interrupt, Error: %d\n", err);
2183
bc7f75fa
AK		 2184 return err;
2185}
2186
2187static void e1000_free_irq(struct e1000_adapter *adapter)
2188{
2189 struct net_device *netdev = adapter->netdev;
2190
4662e82b
BA		 2191 if (adapter->msix_entries) {
2192 int vector = 0;
2193
2194 free_irq(adapter->msix_entries[vector].vector, netdev);
2195 vector++;
2196
2197 free_irq(adapter->msix_entries[vector].vector, netdev);
2198 vector++;
2199
2200 /* Other Causes interrupt vector */
2201 free_irq(adapter->msix_entries[vector].vector, netdev);
2202 return;
bc7f75fa 2203 }
4662e82b
BA		 2204
2205 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2206}
2207
2208/**
2209 * e1000_irq_disable - Mask off interrupt generation on the NIC
b50f7bca 2210 * @adapter: board private structure
bc7f75fa
AK		 2211 **/
2212static void e1000_irq_disable(struct e1000_adapter *adapter)
2213{
2214 struct e1000_hw *hw = &adapter->hw;
2215
bc7f75fa 2216 ew32(IMC, ~0);
4662e82b
BA		 2217 if (adapter->msix_entries)
2218 ew32(EIAC_82574, 0);
bc7f75fa 2219 e1e_flush();
8e86acd7
JK		 2220
2221 if (adapter->msix_entries) {
2222 int i;
6cf08d1c 2223
8e86acd7
JK		 2224 for (i = 0; i < adapter->num_vectors; i++)
2225 synchronize_irq(adapter->msix_entries[i].vector);
2226 } else {
2227 synchronize_irq(adapter->pdev->irq);
2228 }
bc7f75fa
AK		 2229}
2230
2231/**
2232 * e1000_irq_enable - Enable default interrupt generation settings
b50f7bca 2233 * @adapter: board private structure
bc7f75fa
AK		 2234 **/
2235static void e1000_irq_enable(struct e1000_adapter *adapter)
2236{
2237 struct e1000_hw *hw = &adapter->hw;
2238
4662e82b
BA		 2239 if (adapter->msix_entries) {
2240 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
116f4a64
BP		 2241 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER |
2242 IMS_OTHER_MASK);
c8744f44 2243 } else if (hw->mac.type >= e1000_pch_lpt) {
94fb848b 2244 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2245 } else {
2246 ew32(IMS, IMS_ENABLE_MASK);
2247 }
74ef9c39 2248 e1e_flush();
bc7f75fa
AK		 2249}
2250
2251/**
31dbe5b4 2252 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2253 * @adapter: address of board private structure
2254 *
31dbe5b4 2255 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2256 * For ASF and Pass Through versions of f/w this means that
2257 * the driver is loaded. For AMT version (only with 82573)
2258 * of the f/w this means that the network i/f is open.
2259 **/
31dbe5b4 2260void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2261{
2262 struct e1000_hw *hw = &adapter->hw;
2263 u32 ctrl_ext;
2264 u32 swsm;
2265
2266 /* Let firmware know the driver has taken over */
2267 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2268 swsm = er32(SWSM);
2269 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2270 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2271 ctrl_ext = er32(CTRL_EXT);
ad68076e 2272 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2273 }
2274}
2275
2276/**
31dbe5b4 2277 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2278 * @adapter: address of board private structure
2279 *
31dbe5b4 2280 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2281 * For ASF and Pass Through versions of f/w this means that the
2282 * driver is no longer loaded. For AMT version (only with 82573) i
2283 * of the f/w this means that the network i/f is closed.
2284 *
2285 **/
31dbe5b4 2286void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2287{
2288 struct e1000_hw *hw = &adapter->hw;
2289 u32 ctrl_ext;
2290 u32 swsm;
2291
2292 /* Let firmware taken over control of h/w */
2293 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2294 swsm = er32(SWSM);
2295 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2296 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2297 ctrl_ext = er32(CTRL_EXT);
ad68076e 2298 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2299 }
2300}
2301
bc7f75fa 2302/**
49ce9c2c 2303 * e1000_alloc_ring_dma - allocate memory for a ring structure
b50f7bca
JB		 2304 * @adapter: board private structure
2305 * @ring: ring struct for which to allocate dma
bc7f75fa
AK		 2306 **/
2307static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2308 struct e1000_ring *ring)
2309{
2310 struct pci_dev *pdev = adapter->pdev;
2311
750afb08
LC		 2312 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2313 GFP_KERNEL);
bc7f75fa
AK		 2314 if (!ring->desc)
2315 return -ENOMEM;
2316
2317 return 0;
2318}
2319
2320/**
2321 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2322 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2323 *
2324 * Return 0 on success, negative on failure
2325 **/
55aa6985 2326int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2327{
55aa6985 2328 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2329 int err = -ENOMEM, size;
2330
2331 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2332 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2333 if (!tx_ring->buffer_info)
2334 goto err;
bc7f75fa
AK		 2335
2336 /* round up to nearest 4K */
2337 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2338 tx_ring->size = ALIGN(tx_ring->size, 4096);
2339
2340 err = e1000_alloc_ring_dma(adapter, tx_ring);
2341 if (err)
2342 goto err;
2343
2344 tx_ring->next_to_use = 0;
2345 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2346
2347 return 0;
2348err:
2349 vfree(tx_ring->buffer_info);
44defeb3 2350 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2351 return err;
2352}
2353
2354/**
2355 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2356 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2357 *
2358 * Returns 0 on success, negative on failure
2359 **/
55aa6985 2360int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2361{
55aa6985 2362 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2363 struct e1000_buffer *buffer_info;
2364 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2365
2366 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2367 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2368 if (!rx_ring->buffer_info)
2369 goto err;
bc7f75fa 2370
47f44e40
AK		 2371 for (i = 0; i < rx_ring->count; i++) {
2372 buffer_info = &rx_ring->buffer_info[i];
2373 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2374 sizeof(struct e1000_ps_page),
2375 GFP_KERNEL);
2376 if (!buffer_info->ps_pages)
2377 goto err_pages;
2378 }
bc7f75fa
AK		 2379
2380 desc_len = sizeof(union e1000_rx_desc_packet_split);
2381
2382 /* Round up to nearest 4K */
2383 rx_ring->size = rx_ring->count * desc_len;
2384 rx_ring->size = ALIGN(rx_ring->size, 4096);
2385
2386 err = e1000_alloc_ring_dma(adapter, rx_ring);
2387 if (err)
47f44e40 2388 goto err_pages;
bc7f75fa
AK		 2389
2390 rx_ring->next_to_clean = 0;
2391 rx_ring->next_to_use = 0;
2392 rx_ring->rx_skb_top = NULL;
2393
2394 return 0;
47f44e40
AK		 2395
2396err_pages:
2397 for (i = 0; i < rx_ring->count; i++) {
2398 buffer_info = &rx_ring->buffer_info[i];
2399 kfree(buffer_info->ps_pages);
2400 }
bc7f75fa
AK		 2401err:
2402 vfree(rx_ring->buffer_info);
e9262447 2403 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2404 return err;
2405}
2406
2407/**
2408 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2409 * @tx_ring: Tx descriptor ring
bc7f75fa 2410 **/
55aa6985 2411static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2412{
55aa6985 2413 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2414 struct e1000_buffer *buffer_info;
2415 unsigned long size;
2416 unsigned int i;
2417
2418 for (i = 0; i < tx_ring->count; i++) {
2419 buffer_info = &tx_ring->buffer_info[i];
377b6273 2420 e1000_put_txbuf(tx_ring, buffer_info, false);
bc7f75fa
AK		 2421 }
2422
3f0cfa3b 2423 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2424 size = sizeof(struct e1000_buffer) * tx_ring->count;
2425 memset(tx_ring->buffer_info, 0, size);
2426
2427 memset(tx_ring->desc, 0, tx_ring->size);
2428
2429 tx_ring->next_to_use = 0;
2430 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2431}
2432
2433/**
2434 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2435 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2436 *
2437 * Free all transmit software resources
2438 **/
55aa6985 2439void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2440{
55aa6985 2441 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2442 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2443
55aa6985 2444 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2445
2446 vfree(tx_ring->buffer_info);
2447 tx_ring->buffer_info = NULL;
2448
2449 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2450 tx_ring->dma);
2451 tx_ring->desc = NULL;
2452}
2453
2454/**
2455 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2456 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2457 *
2458 * Free all receive software resources
2459 **/
55aa6985 2460void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2461{
55aa6985 2462 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2463 struct pci_dev *pdev = adapter->pdev;
47f44e40 2464 int i;
bc7f75fa 2465
55aa6985 2466 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2467
b1cdfead 2468 for (i = 0; i < rx_ring->count; i++)
47f44e40 2469 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2470
bc7f75fa
AK		 2471 vfree(rx_ring->buffer_info);
2472 rx_ring->buffer_info = NULL;
2473
bc7f75fa
AK		 2474 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2475 rx_ring->dma);
2476 rx_ring->desc = NULL;
2477}
2478
2479/**
2480 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2481 * @itr_setting: current adapter->itr
2482 * @packets: the number of packets during this measurement interval
2483 * @bytes: the number of bytes during this measurement interval
2484 *
bc7f75fa
AK		 2485 * Stores a new ITR value based on packets and byte
2486 * counts during the last interrupt. The advantage of per interrupt
2487 * computation is faster updates and more accurate ITR for the current
2488 * traffic pattern. Constants in this function were computed
2489 * based on theoretical maximum wire speed and thresholds were set based
2490 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2491 * while increasing bulk throughput. This functionality is controlled
2492 * by the InterruptThrottleRate module parameter.
bc7f75fa 2493 **/
8bb62869 2494static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
bc7f75fa
AK		 2495{
2496 unsigned int retval = itr_setting;
2497
2498 if (packets == 0)
5015e53a 2499 return itr_setting;
bc7f75fa
AK		 2500
2501 switch (itr_setting) {
2502 case lowest_latency:
2503 /* handle TSO and jumbo frames */
362e20ca 2504 if (bytes / packets > 8000)
bc7f75fa 2505 retval = bulk_latency;
b1cdfead 2506 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2507 retval = low_latency;
bc7f75fa 2508 break;
e80bd1d1 2509 case low_latency: /* 50 usec aka 20000 ints/s */
bc7f75fa
AK		 2510 if (bytes > 10000) {
2511 /* this if handles the TSO accounting */
362e20ca 2512 if (bytes / packets > 8000)
bc7f75fa 2513 retval = bulk_latency;
362e20ca 2514 else if ((packets < 10) || ((bytes / packets) > 1200))
bc7f75fa 2515 retval = bulk_latency;
b1cdfead 2516 else if ((packets > 35))
bc7f75fa 2517 retval = lowest_latency;
362e20ca 2518 } else if (bytes / packets > 2000) {
bc7f75fa
AK		 2519 retval = bulk_latency;
2520 } else if (packets <= 2 && bytes < 512) {
2521 retval = lowest_latency;
2522 }
2523 break;
e80bd1d1 2524 case bulk_latency: /* 250 usec aka 4000 ints/s */
bc7f75fa 2525 if (bytes > 25000) {
b1cdfead 2526 if (packets > 35)
bc7f75fa 2527 retval = low_latency;
bc7f75fa
AK		 2528 } else if (bytes < 6000) {
2529 retval = low_latency;
2530 }
2531 break;
2532 }
2533
bc7f75fa
AK		 2534 return retval;
2535}
2536
2537static void e1000_set_itr(struct e1000_adapter *adapter)
2538{
bc7f75fa
AK		 2539 u16 current_itr;
2540 u32 new_itr = adapter->itr;
2541
2542 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2543 if (adapter->link_speed != SPEED_1000) {
bc7f75fa
AK		 2544 new_itr = 4000;
2545 goto set_itr_now;
2546 }
2547
828bac87
BA		 2548 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2549 new_itr = 0;
2550 goto set_itr_now;
2551 }
2552
8bb62869
BA		 2553 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2554 adapter->total_tx_packets,
2555 adapter->total_tx_bytes);
bc7f75fa
AK		 2556 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2557 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2558 adapter->tx_itr = low_latency;
2559
8bb62869
BA		 2560 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2561 adapter->total_rx_packets,
2562 adapter->total_rx_bytes);
bc7f75fa
AK		 2563 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2564 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2565 adapter->rx_itr = low_latency;
2566
2567 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2568
bc7f75fa 2569 /* counts and packets in update_itr are dependent on these numbers */
33550cec 2570 switch (current_itr) {
bc7f75fa
AK		 2571 case lowest_latency:
2572 new_itr = 70000;
2573 break;
2574 case low_latency:
e80bd1d1 2575 new_itr = 20000; /* aka hwitr = ~200 */
bc7f75fa
AK		 2576 break;
2577 case bulk_latency:
2578 new_itr = 4000;
2579 break;
2580 default:
2581 break;
2582 }
2583
2584set_itr_now:
2585 if (new_itr != adapter->itr) {
e921eb1a 2586 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2587 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2588 * increasing
2589 */
bc7f75fa 2590 new_itr = new_itr > adapter->itr ?
f0ff4398 2591 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
bc7f75fa 2592 adapter->itr = new_itr;
4662e82b
BA		 2593 adapter->rx_ring->itr_val = new_itr;
2594 if (adapter->msix_entries)
2595 adapter->rx_ring->set_itr = 1;
2596 else
e3d14b08 2597 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2598 }
2599}
2600
22a4cca2
MV		 2601/**
2602 * e1000e_write_itr - write the ITR value to the appropriate registers
2603 * @adapter: address of board private structure
2604 * @itr: new ITR value to program
2605 *
2606 * e1000e_write_itr determines if the adapter is in MSI-X mode
2607 * and, if so, writes the EITR registers with the ITR value.
2608 * Otherwise, it writes the ITR value into the ITR register.
2609 **/
2610void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2611{
2612 struct e1000_hw *hw = &adapter->hw;
2613 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2614
2615 if (adapter->msix_entries) {
2616 int vector;
2617
2618 for (vector = 0; vector < adapter->num_vectors; vector++)
2619 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2620 } else {
2621 ew32(ITR, new_itr);
2622 }
2623}
2624
4662e82b
BA		 2625/**
2626 * e1000_alloc_queues - Allocate memory for all rings
2627 * @adapter: board private structure to initialize
2628 **/
9f9a12f8 2629static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2630{
55aa6985
BA		 2631 int size = sizeof(struct e1000_ring);
2632
2633 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2634 if (!adapter->tx_ring)
2635 goto err;
55aa6985
BA		 2636 adapter->tx_ring->count = adapter->tx_ring_count;
2637 adapter->tx_ring->adapter = adapter;
4662e82b 2638
55aa6985 2639 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2640 if (!adapter->rx_ring)
2641 goto err;
55aa6985
BA		 2642 adapter->rx_ring->count = adapter->rx_ring_count;
2643 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2644
2645 return 0;
2646err:
2647 e_err("Unable to allocate memory for queues\n");
2648 kfree(adapter->rx_ring);
2649 kfree(adapter->tx_ring);
2650 return -ENOMEM;
2651}
2652
bc7f75fa 2653/**
c58c8a78 2654 * e1000e_poll - NAPI Rx polling callback
ad68076e 2655 * @napi: struct associated with this polling callback
0bcd952f 2656 * @budget: number of packets driver is allowed to process this poll
bc7f75fa 2657 **/
0bcd952f 2658static int e1000e_poll(struct napi_struct *napi, int budget)
bc7f75fa 2659{
c58c8a78
BA		 2660 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2661 napi);
4662e82b 2662 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2663 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2664 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2665
4cf1653a 2666 adapter = netdev_priv(poll_dev);
bc7f75fa 2667
c58c8a78
BA		 2668 if (!adapter->msix_entries ||
2669 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2670 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2671
0bcd952f 2672 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
d2c7ddd6 2673
0bcd952f
JB		 2674 if (!tx_cleaned || work_done == budget)
2675 return budget;
bc7f75fa 2676
0bcd952f
JB		 2677 /* Exit the polling mode, but don't re-enable interrupts if stack might
2678 * poll us due to busy-polling
2679 */
2680 if (likely(napi_complete_done(napi, work_done))) {
bc7f75fa
AK		 2681 if (adapter->itr_setting & 3)
2682 e1000_set_itr(adapter);
a3c69fef
JB		 2683 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2684 if (adapter->msix_entries)
1f0ea197 2685 ew32(IMS, adapter->rx_ring->ims_val);
a3c69fef
JB		 2686 else
2687 e1000_irq_enable(adapter);
2688 }
bc7f75fa
AK		 2689 }
2690
2691 return work_done;
2692}
2693
80d5c368 2694static int e1000_vlan_rx_add_vid(struct net_device *netdev,
603cdca9 2695 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2696{
2697 struct e1000_adapter *adapter = netdev_priv(netdev);
2698 struct e1000_hw *hw = &adapter->hw;
2699 u32 vfta, index;
2700
2701 /* don't update vlan cookie if already programmed */
2702 if ((adapter->hw.mng_cookie.status &
2703 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2704 (vid == adapter->mng_vlan_id))
8e586137 2705 return 0;
caaddaf8 2706
bc7f75fa 2707 /* add VID to filter table */
caaddaf8
BA		 2708 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2709 index = (vid >> 5) & 0x7F;
2710 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
18dd2392 2711 vfta |= BIT((vid & 0x1F));
caaddaf8
BA		 2712 hw->mac.ops.write_vfta(hw, index, vfta);
2713 }
86d70e53
JK		 2714
2715 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2716
2717 return 0;
bc7f75fa
AK		 2718}
2719
80d5c368 2720static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
603cdca9 2721 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2722{
2723 struct e1000_adapter *adapter = netdev_priv(netdev);
2724 struct e1000_hw *hw = &adapter->hw;
2725 u32 vfta, index;
2726
bc7f75fa
AK		 2727 if ((adapter->hw.mng_cookie.status &
2728 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2729 (vid == adapter->mng_vlan_id)) {
2730 /* release control to f/w */
31dbe5b4 2731 e1000e_release_hw_control(adapter);
8e586137 2732 return 0;
bc7f75fa
AK		 2733 }
2734
2735 /* remove VID from filter table */
caaddaf8
BA		 2736 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2737 index = (vid >> 5) & 0x7F;
2738 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
18dd2392 2739 vfta &= ~BIT((vid & 0x1F));
caaddaf8
BA		 2740 hw->mac.ops.write_vfta(hw, index, vfta);
2741 }
86d70e53
JK		 2742
2743 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2744
2745 return 0;
bc7f75fa
AK		 2746}
2747
86d70e53
JK		 2748/**
2749 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2750 * @adapter: board private structure to initialize
2751 **/
2752static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2753{
2754 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2755 struct e1000_hw *hw = &adapter->hw;
2756 u32 rctl;
bc7f75fa 2757
86d70e53
JK		 2758 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2759 /* disable VLAN receive filtering */
2760 rctl = er32(RCTL);
2761 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2762 ew32(RCTL, rctl);
2763
2764 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
80d5c368
PM		 2765 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2766 adapter->mng_vlan_id);
86d70e53 2767 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2768 }
bc7f75fa
AK		 2769 }
2770}
2771
86d70e53
JK		 2772/**
2773 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2774 * @adapter: board private structure to initialize
2775 **/
2776static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2777{
2778 struct e1000_hw *hw = &adapter->hw;
2779 u32 rctl;
2780
2781 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2782 /* enable VLAN receive filtering */
2783 rctl = er32(RCTL);
2784 rctl |= E1000_RCTL_VFE;
2785 rctl &= ~E1000_RCTL_CFIEN;
2786 ew32(RCTL, rctl);
2787 }
2788}
bc7f75fa 2789
86d70e53 2790/**
889ad456 2791 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
86d70e53
JK		 2792 * @adapter: board private structure to initialize
2793 **/
2794static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2795{
bc7f75fa 2796 struct e1000_hw *hw = &adapter->hw;
86d70e53 2797 u32 ctrl;
bc7f75fa 2798
86d70e53
JK		 2799 /* disable VLAN tag insert/strip */
2800 ctrl = er32(CTRL);
2801 ctrl &= ~E1000_CTRL_VME;
2802 ew32(CTRL, ctrl);
2803}
bc7f75fa 2804
86d70e53
JK		 2805/**
2806 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2807 * @adapter: board private structure to initialize
2808 **/
2809static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2810{
2811 struct e1000_hw *hw = &adapter->hw;
2812 u32 ctrl;
bc7f75fa 2813
86d70e53
JK		 2814 /* enable VLAN tag insert/strip */
2815 ctrl = er32(CTRL);
2816 ctrl |= E1000_CTRL_VME;
2817 ew32(CTRL, ctrl);
2818}
bc7f75fa 2819
86d70e53
JK		 2820static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2821{
2822 struct net_device *netdev = adapter->netdev;
2823 u16 vid = adapter->hw.mng_cookie.vlan_id;
2824 u16 old_vid = adapter->mng_vlan_id;
2825
e5fe2541 2826 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
80d5c368 2827 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
86d70e53 2828 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2829 }
2830
86d70e53 2831 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
80d5c368 2832 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
bc7f75fa
AK		 2833}
2834
2835static void e1000_restore_vlan(struct e1000_adapter *adapter)
2836{
2837 u16 vid;
2838
80d5c368 2839 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
bc7f75fa 2840
86d70e53 2841 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 2842 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
bc7f75fa
AK		 2843}
2844
cd791618 2845static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2846{
2847 struct e1000_hw *hw = &adapter->hw;
cd791618 2848 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2849
2850 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2851 return;
2852
2853 manc = er32(MANC);
2854
e921eb1a 2855 /* enable receiving management packets to the host. this will probably
bc7f75fa 2856 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2857 * the packets will be handled on SMBUS
2858 */
bc7f75fa
AK		 2859 manc |= E1000_MANC_EN_MNG2HOST;
2860 manc2h = er32(MANC2H);
cd791618
BA		 2861
2862 switch (hw->mac.type) {
2863 default:
2864 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2865 break;
2866 case e1000_82574:
2867 case e1000_82583:
e921eb1a 2868 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2869 * if so, enable it.
2870 */
2871 for (i = 0, j = 0; i < 8; i++) {
2872 mdef = er32(MDEF(i));
2873
2874 /* Ignore filters with anything other than IPMI ports */
3b21b508 2875 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2876 continue;
2877
2878 /* Enable this decision filter in MANC2H */
2879 if (mdef)
18dd2392 2880 manc2h |= BIT(i);
cd791618
BA		 2881
2882 j |= mdef;
2883 }
2884
2885 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2886 break;
2887
2888 /* Create new decision filter in an empty filter */
2889 for (i = 0, j = 0; i < 8; i++)
2890 if (er32(MDEF(i)) == 0) {
2891 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2892 E1000_MDEF_PORT_664));
18dd2392 2893 manc2h |= BIT(1);
cd791618
BA		 2894 j++;
2895 break;
2896 }
2897
2898 if (!j)
2899 e_warn("Unable to create IPMI pass-through filter\n");
2900 break;
2901 }
2902
bc7f75fa
AK		 2903 ew32(MANC2H, manc2h);
2904 ew32(MANC, manc);
2905}
2906
2907/**
af667a29 2908 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2909 * @adapter: board private structure
2910 *
2911 * Configure the Tx unit of the MAC after a reset.
2912 **/
2913static void e1000_configure_tx(struct e1000_adapter *adapter)
2914{
2915 struct e1000_hw *hw = &adapter->hw;
2916 struct e1000_ring *tx_ring = adapter->tx_ring;
2917 u64 tdba;
e7e834aa 2918 u32 tdlen, tctl, tarc;
bc7f75fa
AK		 2919
2920 /* Setup the HW Tx Head and Tail descriptor pointers */
2921 tdba = tx_ring->dma;
2922 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2923 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2924 ew32(TDBAH(0), (tdba >> 32));
2925 ew32(TDLEN(0), tdlen);
2926 ew32(TDH(0), 0);
2927 ew32(TDT(0), 0);
2928 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2929 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2930
0845d45e
JJB		 2931 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2932 e1000e_update_tdt_wa(tx_ring, 0);
0845d45e 2933
bc7f75fa
AK		 2934 /* Set the Tx Interrupt Delay register */
2935 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2936 /* Tx irq moderation */
bc7f75fa
AK		 2937 ew32(TADV, adapter->tx_abs_int_delay);
2938
3a3b7586
JB		 2939 if (adapter->flags2 & FLAG2_DMA_BURST) {
2940 u32 txdctl = er32(TXDCTL(0));
6cf08d1c 2941
3a3b7586
JB		 2942 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2943 E1000_TXDCTL_WTHRESH);
e921eb1a 2944 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2945 * hardware to use the bus more efficiently in bursts, depends
2946 * on the tx_int_delay to be enabled,
8edc0e62 2947 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2948 * hthresh = 1 ==> prefetch when one or more available
2949 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2950 * BEWARE: this seems to work but should be considered first if
af667a29 2951 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2952 */
2953 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2954 ew32(TXDCTL(0), txdctl);
3a3b7586 2955 }
56032be7
BA		 2956 /* erratum work around: set txdctl the same for both queues */
2957 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2958
e7e834aa
DE		 2959 /* Program the Transmit Control Register */
2960 tctl = er32(TCTL);
2961 tctl &= ~E1000_TCTL_CT;
2962 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2963 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2964
bc7f75fa 2965 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2966 tarc = er32(TARC(0));
e921eb1a 2967 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2968 * gigabit link later
2969 */
18dd2392 2970#define SPEED_MODE_BIT BIT(21)
bc7f75fa 2971 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2972 ew32(TARC(0), tarc);
bc7f75fa
AK		 2973 }
2974
2975 /* errata: program both queues to unweighted RR */
2976 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2977 tarc = er32(TARC(0));
bc7f75fa 2978 tarc |= 1;
e9ec2c0f
JK		 2979 ew32(TARC(0), tarc);
2980 tarc = er32(TARC(1));
bc7f75fa 2981 tarc |= 1;
e9ec2c0f 2982 ew32(TARC(1), tarc);
bc7f75fa
AK		 2983 }
2984
bc7f75fa
AK		 2985 /* Setup Transmit Descriptor Settings for eop descriptor */
2986 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2987
2988 /* only set IDE if we are delaying interrupts using the timers */
2989 if (adapter->tx_int_delay)
2990 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2991
2992 /* enable Report Status bit */
2993 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2994
e7e834aa
DE		 2995 ew32(TCTL, tctl);
2996
57cde763 2997 hw->mac.ops.config_collision_dist(hw);
79849ebc 2998
b10effb9
SN		 2999 /* SPT and KBL Si errata workaround to avoid data corruption */
3000 if (hw->mac.type == e1000_pch_spt) {
79849ebc
DE		 3001 u32 reg_val;
3002
3003 reg_val = er32(IOSFPC);
3004 reg_val |= E1000_RCTL_RDMTS_HEX;
3005 ew32(IOSFPC, reg_val);
3006
3007 reg_val = er32(TARC(0));
c0f4b163
SN		 3008 /* SPT and KBL Si errata workaround to avoid Tx hang.
3009 * Dropping the number of outstanding requests from
3010 * 3 to 2 in order to avoid a buffer overrun.
3011 */
3012 reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ;
3013 reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ;
79849ebc
DE		 3014 ew32(TARC(0), reg_val);
3015 }
bc7f75fa
AK		 3016}
3017
b50f7bca
JB		 3018#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3019 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3020
bc7f75fa
AK		 3021/**
3022 * e1000_setup_rctl - configure the receive control registers
3023 * @adapter: Board private structure
3024 **/
bc7f75fa
AK		 3025static void e1000_setup_rctl(struct e1000_adapter *adapter)
3026{
3027 struct e1000_hw *hw = &adapter->hw;
3028 u32 rctl, rfctl;
bc7f75fa
AK		 3029 u32 pages = 0;
3030
b20a7744
DE		 3031 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3032 * If jumbo frames not set, program related MAC/PHY registers
3033 * to h/w defaults
3034 */
3035 if (hw->mac.type >= e1000_pch2lan) {
3036 s32 ret_val;
3037
3038 if (adapter->netdev->mtu > ETH_DATA_LEN)
3039 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3040 else
3041 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3042
3043 if (ret_val)
3044 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3045 }
a1ce6473 3046
bc7f75fa
AK		 3047 /* Program MC offset vector base */
3048 rctl = er32(RCTL);
3049 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3050 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
f0ff4398
BA		 3051 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3052 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
bc7f75fa
AK		 3053
3054 /* Do not Store bad packets */
3055 rctl &= ~E1000_RCTL_SBP;
3056
3057 /* Enable Long Packet receive */
3058 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3059 rctl &= ~E1000_RCTL_LPE;
3060 else
3061 rctl |= E1000_RCTL_LPE;
3062
eb7c3adb
JK		 3063 /* Some systems expect that the CRC is included in SMBUS traffic. The
3064 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3065 * host memory when this is enabled
3066 */
3067 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3068 rctl |= E1000_RCTL_SECRC;
5918bd88 3069
a4f58f54
BA		 3070 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3071 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3072 u16 phy_data;
3073
3074 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3075 phy_data &= 0xfff8;
18dd2392 3076 phy_data |= BIT(2);
a4f58f54
BA		 3077 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3078
3079 e1e_rphy(hw, 22, &phy_data);
3080 phy_data &= 0x0fff;
18dd2392 3081 phy_data |= BIT(14);
a4f58f54
BA		 3082 e1e_wphy(hw, 0x10, 0x2823);
3083 e1e_wphy(hw, 0x11, 0x0003);
3084 e1e_wphy(hw, 22, phy_data);
3085 }
3086
bc7f75fa
AK		 3087 /* Setup buffer sizes */
3088 rctl &= ~E1000_RCTL_SZ_4096;
3089 rctl |= E1000_RCTL_BSEX;
3090 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3091 case 2048:
3092 default:
3093 rctl |= E1000_RCTL_SZ_2048;
3094 rctl &= ~E1000_RCTL_BSEX;
3095 break;
3096 case 4096:
3097 rctl |= E1000_RCTL_SZ_4096;
3098 break;
3099 case 8192:
3100 rctl |= E1000_RCTL_SZ_8192;
3101 break;
3102 case 16384:
3103 rctl |= E1000_RCTL_SZ_16384;
3104 break;
3105 }
3106
5f450212
BA		 3107 /* Enable Extended Status in all Receive Descriptors */
3108 rfctl = er32(RFCTL);
3109 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3110 ew32(RFCTL, rfctl);
5f450212 3111
e921eb1a 3112 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3113 * header is placed in skb->data and the packet data is
3114 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3115 * In the case of a non-split, skb->data is linearly filled,
3116 * followed by the page buffers. Therefore, skb->data is
3117 * sized to hold the largest protocol header.
3118 *
3119 * allocations using alloc_page take too long for regular MTU
3120 * so only enable packet split for jumbo frames
3121 *
3122 * Using pages when the page size is greater than 16k wastes
3123 * a lot of memory, since we allocate 3 pages at all times
3124 * per packet.
3125 */
bc7f75fa 3126 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3127 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3128 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3129 else
3130 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3131
3132 if (adapter->rx_ps_pages) {
90da0669
BA		 3133 u32 psrctl = 0;
3134
140a7480
AK		 3135 /* Enable Packet split descriptors */
3136 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa 3137
e5fe2541 3138 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
bc7f75fa
AK		 3139
3140 switch (adapter->rx_ps_pages) {
3141 case 3:
e5fe2541 3142 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
5463fce6 3143 fallthrough;
bc7f75fa 3144 case 2:
e5fe2541 3145 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
5463fce6 3146 fallthrough;
bc7f75fa 3147 case 1:
e5fe2541 3148 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
bc7f75fa
AK		 3149 break;
3150 }
3151
3152 ew32(PSRCTL, psrctl);
3153 }
3154
cf955e6c
BG		 3155 /* This is useful for sniffing bad packets. */
3156 if (adapter->netdev->features & NETIF_F_RXALL) {
3157 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3158 * in e1000e_set_rx_mode
3159 */
e80bd1d1
BA		 3160 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3161 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3162 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
cf955e6c 3163
e80bd1d1
BA		 3164 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3165 E1000_RCTL_DPF | /* Allow filtered pause */
3166 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
cf955e6c
BG		 3167 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3168 * and that breaks VLANs.
3169 */
3170 }
3171
bc7f75fa 3172 ew32(RCTL, rctl);
318a94d6 3173 /* just started the receive unit, no need to restart */
12d43f7d 3174 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3175}
3176
3177/**
3178 * e1000_configure_rx - Configure Receive Unit after Reset
3179 * @adapter: board private structure
3180 *
3181 * Configure the Rx unit of the MAC after a reset.
3182 **/
3183static void e1000_configure_rx(struct e1000_adapter *adapter)
3184{
3185 struct e1000_hw *hw = &adapter->hw;
3186 struct e1000_ring *rx_ring = adapter->rx_ring;
3187 u64 rdba;
3188 u32 rdlen, rctl, rxcsum, ctrl_ext;
3189
3190 if (adapter->rx_ps_pages) {
3191 /* this is a 32 byte descriptor */
3192 rdlen = rx_ring->count *
af667a29 3193 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3194 adapter->clean_rx = e1000_clean_rx_irq_ps;
3195 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3196 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3197 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3198 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3199 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3200 } else {
5f450212 3201 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3202 adapter->clean_rx = e1000_clean_rx_irq;
3203 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3204 }
3205
3206 /* disable receives while setting up the descriptors */
3207 rctl = er32(RCTL);
7f99ae63
BA		 3208 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3209 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3210 e1e_flush();
ab6973ae 3211 usleep_range(10000, 11000);
bc7f75fa 3212
3a3b7586 3213 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3214 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3215 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3216 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3217 * granularity = 01
3218 * wthresh = 04,
3219 * hthresh = 04,
3220 * pthresh = 0x20
3221 */
3222 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3223 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3a3b7586
JB		 3224 }
3225
bc7f75fa
AK		 3226 /* set the Receive Delay Timer Register */
3227 ew32(RDTR, adapter->rx_int_delay);
3228
3229 /* irq moderation */
3230 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3231 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3232 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3233
3234 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3235 /* Auto-Mask interrupts upon ICR access */
3236 ctrl_ext |= E1000_CTRL_EXT_IAME;
3237 ew32(IAM, 0xffffffff);
3238 ew32(CTRL_EXT, ctrl_ext);
3239 e1e_flush();
3240
e921eb1a 3241 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3242 * the Base and Length of the Rx Descriptor Ring
3243 */
bc7f75fa 3244 rdba = rx_ring->dma;
1e36052e
BA		 3245 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3246 ew32(RDBAH(0), (rdba >> 32));
3247 ew32(RDLEN(0), rdlen);
3248 ew32(RDH(0), 0);
3249 ew32(RDT(0), 0);
3250 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3251 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa 3252
0845d45e
JJB		 3253 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3254 e1000e_update_rdt_wa(rx_ring, 0);
0845d45e 3255
bc7f75fa
AK		 3256 /* Enable Receive Checksum Offload for TCP and UDP */
3257 rxcsum = er32(RXCSUM);
2e1706f2 3258 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3259 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3260 else
bc7f75fa 3261 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3262 ew32(RXCSUM, rxcsum);
3263
3e35d991
BA		 3264 /* With jumbo frames, excessive C-state transition latencies result
3265 * in dropped transactions.
3266 */
3267 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3268 u32 lat =
3269 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3270 adapter->max_frame_size) * 8 / 1000;
3271
3272 if (adapter->flags & FLAG_IS_ICH) {
53ec5498 3273 u32 rxdctl = er32(RXDCTL(0));
6cf08d1c 3274
b701cacd 3275 ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8));
53ec5498 3276 }
3e35d991 3277
8299b006
MT		 3278 dev_info(&adapter->pdev->dev,
3279 "Some CPU C-states have been disabled in order to enable jumbo frames\n");
81e95ad7 3280 cpu_latency_qos_update_request(&adapter->pm_qos_req, lat);
3e35d991 3281 } else {
81e95ad7
RW		 3282 cpu_latency_qos_update_request(&adapter->pm_qos_req,
3283 PM_QOS_DEFAULT_VALUE);
97ac8cae 3284 }
bc7f75fa
AK		 3285
3286 /* Enable Receives */
3287 ew32(RCTL, rctl);
3288}
3289
3290/**
ef9b965a
JB		 3291 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3292 * @netdev: network interface device structure
bc7f75fa 3293 *
ef9b965a
JB		 3294 * Writes multicast address list to the MTA hash table.
3295 * Returns: -ENOMEM on failure
3296 * 0 on no addresses written
3297 * X on writing X addresses to MTA
3298 */
3299static int e1000e_write_mc_addr_list(struct net_device *netdev)
3300{
3301 struct e1000_adapter *adapter = netdev_priv(netdev);
3302 struct e1000_hw *hw = &adapter->hw;
3303 struct netdev_hw_addr *ha;
3304 u8 *mta_list;
3305 int i;
3306
3307 if (netdev_mc_empty(netdev)) {
3308 /* nothing to program, so clear mc list */
3309 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3310 return 0;
3311 }
3312
6396bb22 3313 mta_list = kcalloc(netdev_mc_count(netdev), ETH_ALEN, GFP_ATOMIC);
ef9b965a
JB		 3314 if (!mta_list)
3315 return -ENOMEM;
3316
3317 /* update_mc_addr_list expects a packed array of only addresses. */
3318 i = 0;
3319 netdev_for_each_mc_addr(ha, netdev)
f0ff4398 3320 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
ef9b965a
JB		 3321
3322 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3323 kfree(mta_list);
3324
3325 return netdev_mc_count(netdev);
3326}
3327
3328/**
3329 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3330 * @netdev: network interface device structure
bc7f75fa 3331 *
ef9b965a
JB		 3332 * Writes unicast address list to the RAR table.
3333 * Returns: -ENOMEM on failure/insufficient address space
3334 * 0 on no addresses written
3335 * X on writing X addresses to the RAR table
bc7f75fa 3336 **/
ef9b965a 3337static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3338{
ef9b965a
JB		 3339 struct e1000_adapter *adapter = netdev_priv(netdev);
3340 struct e1000_hw *hw = &adapter->hw;
b3e5bf1f 3341 unsigned int rar_entries;
ef9b965a
JB		 3342 int count = 0;
3343
b3e5bf1f
DE		 3344 rar_entries = hw->mac.ops.rar_get_count(hw);
3345
ef9b965a
JB		 3346 /* save a rar entry for our hardware address */
3347 rar_entries--;
3348
3349 /* save a rar entry for the LAA workaround */
3350 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3351 rar_entries--;
3352
3353 /* return ENOMEM indicating insufficient memory for addresses */
3354 if (netdev_uc_count(netdev) > rar_entries)
3355 return -ENOMEM;
3356
3357 if (!netdev_uc_empty(netdev) && rar_entries) {
3358 struct netdev_hw_addr *ha;
3359
e921eb1a 3360 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3361 * combining
3362 */
3363 netdev_for_each_uc_addr(ha, netdev) {
847042a6 3364 int ret_val;
b3e5bf1f 3365
ef9b965a
JB		 3366 if (!rar_entries)
3367 break;
847042a6
BW		 3368 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3369 if (ret_val < 0)
b3e5bf1f 3370 return -ENOMEM;
ef9b965a
JB		 3371 count++;
3372 }
3373 }
3374
3375 /* zero out the remaining RAR entries not used above */
3376 for (; rar_entries > 0; rar_entries--) {
3377 ew32(RAH(rar_entries), 0);
3378 ew32(RAL(rar_entries), 0);
3379 }
3380 e1e_flush();
3381
3382 return count;
bc7f75fa
AK		 3383}
3384
3385/**
ef9b965a 3386 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3387 * @netdev: network interface device structure
3388 *
ef9b965a
JB		 3389 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3390 * address list or the network interface flags are updated. This routine is
3391 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3392 * promiscuous mode, and all-multi behavior.
3393 **/
ef9b965a 3394static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3395{
3396 struct e1000_adapter *adapter = netdev_priv(netdev);
3397 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3398 u32 rctl;
bc7f75fa 3399
63eb48f1
DE		 3400 if (pm_runtime_suspended(netdev->dev.parent))
3401 return;
3402
bc7f75fa 3403 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3404 rctl = er32(RCTL);
3405
ef9b965a
JB		 3406 /* clear the affected bits */
3407 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3408
bc7f75fa
AK		 3409 if (netdev->flags & IFF_PROMISC) {
3410 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3411 /* Do not hardware filter VLANs in promisc mode */
3412 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3413 } else {
ef9b965a 3414 int count;
3d3a1676 3415
746b9f02
PM		 3416 if (netdev->flags & IFF_ALLMULTI) {
3417 rctl |= E1000_RCTL_MPE;
746b9f02 3418 } else {
e921eb1a 3419 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3420 * then we should just turn on promiscuous mode so
3421 * that we can at least receive multicast traffic
3422 */
3423 count = e1000e_write_mc_addr_list(netdev);
3424 if (count < 0)
3425 rctl |= E1000_RCTL_MPE;
746b9f02 3426 }
86d70e53 3427 e1000e_vlan_filter_enable(adapter);
e921eb1a 3428 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3429 * sufficient space to store all the addresses then enable
3430 * unicast promiscuous mode
bc7f75fa 3431 */
ef9b965a
JB		 3432 count = e1000e_write_uc_addr_list(netdev);
3433 if (count < 0)
3434 rctl |= E1000_RCTL_UPE;
bc7f75fa 3435 }
86d70e53 3436
ef9b965a
JB		 3437 ew32(RCTL, rctl);
3438
83808641 3439 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
86d70e53
JK		 3440 e1000e_vlan_strip_enable(adapter);
3441 else
3442 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3443}
3444
70495a50
BA		 3445static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3446{
3447 struct e1000_hw *hw = &adapter->hw;
3448 u32 mrqc, rxcsum;
5c8d19da 3449 u32 rss_key[10];
70495a50 3450 int i;
70495a50 3451
5c8d19da 3452 netdev_rss_key_fill(rss_key, sizeof(rss_key));
70495a50 3453 for (i = 0; i < 10; i++)
5c8d19da 3454 ew32(RSSRK(i), rss_key[i]);
70495a50
BA		 3455
3456 /* Direct all traffic to queue 0 */
3457 for (i = 0; i < 32; i++)
3458 ew32(RETA(i), 0);
3459
e921eb1a 3460 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3461 * descriptor on writeback.
3462 */
3463 rxcsum = er32(RXCSUM);
3464 rxcsum |= E1000_RXCSUM_PCSD;
3465
3466 ew32(RXCSUM, rxcsum);
3467
3468 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3469 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3470 E1000_MRQC_RSS_FIELD_IPV6 |
3471 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3472 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3473
3474 ew32(MRQC, mrqc);
3475}
3476
b67e1913
BA		 3477/**
3478 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3479 * @adapter: board private structure
3480 * @timinca: pointer to returned time increment attributes
3481 *
3482 * Get attributes for incrementing the System Time Register SYSTIML/H at
3483 * the default base frequency, and set the cyclecounter shift value.
3484 **/
d89777bf 3485s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3486{
3487 struct e1000_hw *hw = &adapter->hw;
3488 u32 incvalue, incperiod, shift;
3489
79849ebc
DE		 3490 /* Make sure clock is enabled on I217/I218/I219 before checking
3491 * the frequency
3492 */
c8744f44 3493 if ((hw->mac.type >= e1000_pch_lpt) &&
b67e1913
BA		 3494 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3495 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3496 u32 fextnvm7 = er32(FEXTNVM7);
3497
18dd2392
JK		 3498 if (!(fextnvm7 & BIT(0))) {
3499 ew32(FEXTNVM7, fextnvm7 | BIT(0));
b67e1913
BA		 3500 e1e_flush();
3501 }
3502 }
3503
3504 switch (hw->mac.type) {
3505 case e1000_pch2lan:
5313eecc 3506 /* Stable 96MHz frequency */
68fe1d5d
SN		 3507 incperiod = INCPERIOD_96MHZ;
3508 incvalue = INCVALUE_96MHZ;
3509 shift = INCVALUE_SHIFT_96MHZ;
3510 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
5313eecc 3511 break;
b67e1913 3512 case e1000_pch_lpt:
83129b37 3513 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
b67e1913 3514 /* Stable 96MHz frequency */
68fe1d5d
SN		 3515 incperiod = INCPERIOD_96MHZ;
3516 incvalue = INCVALUE_96MHZ;
3517 shift = INCVALUE_SHIFT_96MHZ;
3518 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ;
83129b37
YL		 3519 } else {
3520 /* Stable 25MHz frequency */
68fe1d5d
SN		 3521 incperiod = INCPERIOD_25MHZ;
3522 incvalue = INCVALUE_25MHZ;
3523 shift = INCVALUE_SHIFT_25MHZ;
83129b37
YL		 3524 adapter->cc.shift = shift;
3525 }
3526 break;
3527 case e1000_pch_spt:
fff200ca
BP		 3528 /* Stable 24MHz frequency */
3529 incperiod = INCPERIOD_24MHZ;
3530 incvalue = INCVALUE_24MHZ;
3531 shift = INCVALUE_SHIFT_24MHZ;
3532 adapter->cc.shift = shift;
3533 break;
68fe1d5d 3534 case e1000_pch_cnp:
fb776f5d 3535 case e1000_pch_tgp:
59e46688 3536 case e1000_pch_adp:
1fe4f45e 3537 case e1000_pch_nvp:
68fe1d5d
SN		 3538 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3539 /* Stable 24MHz frequency */
3540 incperiod = INCPERIOD_24MHZ;
3541 incvalue = INCVALUE_24MHZ;
3542 shift = INCVALUE_SHIFT_24MHZ;
3543 adapter->cc.shift = shift;
3544 } else {
3545 /* Stable 38400KHz frequency */
3546 incperiod = INCPERIOD_38400KHZ;
3547 incvalue = INCVALUE_38400KHZ;
3548 shift = INCVALUE_SHIFT_38400KHZ;
3549 adapter->cc.shift = shift;
3550 }
3551 break;
688a0d61
VL		 3552 case e1000_pch_mtp:
3553 case e1000_pch_lnp:
3554 case e1000_pch_ptp:
3555 /* System firmware can misreport this value, so set it to a
3556 * stable 38400KHz frequency.
3557 */
3558 incperiod = INCPERIOD_38400KHZ;
3559 incvalue = INCVALUE_38400KHZ;
3560 shift = INCVALUE_SHIFT_38400KHZ;
3561 adapter->cc.shift = shift;
3562 break;
b67e1913
BA		 3563 case e1000_82574:
3564 case e1000_82583:
3565 /* Stable 25MHz frequency */
68fe1d5d
SN		 3566 incperiod = INCPERIOD_25MHZ;
3567 incvalue = INCVALUE_25MHZ;
3568 shift = INCVALUE_SHIFT_25MHZ;
b67e1913
BA		 3569 adapter->cc.shift = shift;
3570 break;
3571 default:
3572 return -EINVAL;
3573 }
3574
3575 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3576 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3577
3578 return 0;
3579}
3580
3581/**
3582 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3583 * @adapter: board private structure
b50f7bca 3584 * @config: timestamp configuration
39aa687a 3585 * @extack: netlink extended ACK for error report
b67e1913
BA		 3586 *
3587 * Outgoing time stamping can be enabled and disabled. Play nice and
3588 * disable it when requested, although it shouldn't cause any overhead
3589 * when no packet needs it. At most one packet in the queue may be
3590 * marked for time stamping, otherwise it would be impossible to tell
3591 * for sure to which packet the hardware time stamp belongs.
3592 *
3593 * Incoming time stamping has to be configured via the hardware filters.
3594 * Not all combinations are supported, in particular event type has to be
3595 * specified. Matching the kind of event packet is not supported, with the
3596 * exception of "all V2 events regardless of level 2 or 4".
3597 **/
62d7e3a2 3598static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
39aa687a
PW		 3599 struct kernel_hwtstamp_config *config,
3600 struct netlink_ext_ack *extack)
b67e1913
BA		 3601{
3602 struct e1000_hw *hw = &adapter->hw;
b67e1913
BA		 3603 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3604 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3605 u32 rxmtrl = 0;
3606 u16 rxudp = 0;
3607 bool is_l4 = false;
3608 bool is_l2 = false;
b67e1913 3609 u32 regval;
b67e1913 3610
39aa687a
PW		 3611 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
3612 NL_SET_ERR_MSG(extack, "No HW timestamp support");
b67e1913 3613 return -EINVAL;
39aa687a 3614 }
b67e1913 3615
b67e1913
BA		 3616 switch (config->tx_type) {
3617 case HWTSTAMP_TX_OFF:
3618 tsync_tx_ctl = 0;
3619 break;
3620 case HWTSTAMP_TX_ON:
3621 break;
3622 default:
39aa687a 3623 NL_SET_ERR_MSG(extack, "Unsupported TX HW timestamp type");
b67e1913
BA		 3624 return -ERANGE;
3625 }
3626
3627 switch (config->rx_filter) {
3628 case HWTSTAMP_FILTER_NONE:
3629 tsync_rx_ctl = 0;
3630 break;
d89777bf
BA		 3631 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3632 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3633 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3634 is_l4 = true;
3635 break;
3636 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3637 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3638 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3639 is_l4 = true;
3640 break;
3641 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3642 /* Also time stamps V2 L2 Path Delay Request/Response */
3643 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3644 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3645 is_l2 = true;
3646 break;
3647 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3648 /* Also time stamps V2 L2 Path Delay Request/Response. */
3649 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3650 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3651 is_l2 = true;
3652 break;
3653 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5463fce6
JK		 3654 /* Hardware cannot filter just V2 L4 Sync messages */
3655 fallthrough;
d89777bf
BA		 3656 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3657 /* Also time stamps V2 Path Delay Request/Response. */
3658 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3659 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3660 is_l2 = true;
3661 is_l4 = true;
3662 break;
3663 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5463fce6
JK		 3664 /* Hardware cannot filter just V2 L4 Delay Request messages */
3665 fallthrough;
d89777bf
BA		 3666 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3667 /* Also time stamps V2 Path Delay Request/Response. */
3668 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3669 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3670 is_l2 = true;
3671 is_l4 = true;
3672 break;
3673 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3674 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
5463fce6
JK		 3675 /* Hardware cannot filter just V2 L4 or L2 Event messages */
3676 fallthrough;
d89777bf
BA		 3677 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3678 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3679 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3680 is_l2 = true;
3681 is_l4 = true;
3682 break;
3683 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3684 /* For V1, the hardware can only filter Sync messages or
3685 * Delay Request messages but not both so fall-through to
3686 * time stamp all packets.
3687 */
5463fce6 3688 fallthrough;
e3412575 3689 case HWTSTAMP_FILTER_NTP_ALL:
b67e1913 3690 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3691 is_l2 = true;
3692 is_l4 = true;
b67e1913
BA		 3693 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3694 config->rx_filter = HWTSTAMP_FILTER_ALL;
3695 break;
3696 default:
39aa687a 3697 NL_SET_ERR_MSG(extack, "Unsupported RX HW timestamp filter");
b67e1913
BA		 3698 return -ERANGE;
3699 }
3700
62d7e3a2
BH		 3701 adapter->hwtstamp_config = *config;
3702
b67e1913
BA		 3703 /* enable/disable Tx h/w time stamping */
3704 regval = er32(TSYNCTXCTL);
3705 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3706 regval |= tsync_tx_ctl;
3707 ew32(TSYNCTXCTL, regval);
3708 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3709 (regval & E1000_TSYNCTXCTL_ENABLED)) {
39aa687a
PW		 3710 NL_SET_ERR_MSG(extack,
3711 "Timesync Tx Control register not set as expected");
b67e1913
BA		 3712 return -EAGAIN;
3713 }
3714
3715 /* enable/disable Rx h/w time stamping */
3716 regval = er32(TSYNCRXCTL);
3717 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3718 regval |= tsync_rx_ctl;
3719 ew32(TSYNCRXCTL, regval);
3720 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3721 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3722 (regval & (E1000_TSYNCRXCTL_ENABLED |
3723 E1000_TSYNCRXCTL_TYPE_MASK))) {
39aa687a
PW		 3724 NL_SET_ERR_MSG(extack,
3725 "Timesync Rx Control register not set as expected");
b67e1913
BA		 3726 return -EAGAIN;
3727 }
3728
d89777bf
BA		 3729 /* L2: define ethertype filter for time stamped packets */
3730 if (is_l2)
3731 rxmtrl |= ETH_P_1588;
3732
3733 /* define which PTP packets get time stamped */
3734 ew32(RXMTRL, rxmtrl);
3735
3736 /* Filter by destination port */
3737 if (is_l4) {
3738 rxudp = PTP_EV_PORT;
3739 cpu_to_be16s(&rxudp);
3740 }
3741 ew32(RXUDP, rxudp);
3742
3743 e1e_flush();
3744
b67e1913 3745 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
70806a7f
BA		 3746 er32(RXSTMPH);
3747 er32(TXSTMPH);
b67e1913 3748
b67e1913
BA		 3749 return 0;
3750}
3751
bc7f75fa 3752/**
ad68076e 3753 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3754 * @adapter: private board structure
3755 **/
3756static void e1000_configure(struct e1000_adapter *adapter)
3757{
55aa6985
BA		 3758 struct e1000_ring *rx_ring = adapter->rx_ring;
3759
ef9b965a 3760 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3761
3762 e1000_restore_vlan(adapter);
cd791618 3763 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3764
3765 e1000_configure_tx(adapter);
70495a50
BA		 3766
3767 if (adapter->netdev->features & NETIF_F_RXHASH)
3768 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3769 e1000_setup_rctl(adapter);
3770 e1000_configure_rx(adapter);
55aa6985 3771 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3772}
3773
3774/**
3775 * e1000e_power_up_phy - restore link in case the phy was powered down
3776 * @adapter: address of board private structure
3777 *
3778 * The phy may be powered down to save power and turn off link when the
3779 * driver is unloaded and wake on lan is not enabled (among others)
3780 * *** this routine MUST be followed by a call to e1000e_reset ***
3781 **/
3782void e1000e_power_up_phy(struct e1000_adapter *adapter)
3783{
17f208de
BA		 3784 if (adapter->hw.phy.ops.power_up)
3785 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3786
3787 adapter->hw.mac.ops.setup_link(&adapter->hw);
3788}
3789
3790/**
3791 * e1000_power_down_phy - Power down the PHY
b50f7bca 3792 * @adapter: board private structure
bc7f75fa 3793 *
17f208de
BA		 3794 * Power down the PHY so no link is implied when interface is down.
3795 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3796 */
3797static void e1000_power_down_phy(struct e1000_adapter *adapter)
3798{
17f208de
BA		 3799 if (adapter->hw.phy.ops.power_down)
3800 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3801}
3802
ad851fbb
YL		 3803/**
3804 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
b50f7bca 3805 * @adapter: board private structure
ad851fbb
YL		 3806 *
3807 * We want to clear all pending descriptors from the TX ring.
3808 * zeroing happens when the HW reads the regs. We assign the ring itself as
3809 * the data of the next descriptor. We don't care about the data we are about
3810 * to reset the HW.
3811 */
3812static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3813{
3814 struct e1000_hw *hw = &adapter->hw;
3815 struct e1000_ring *tx_ring = adapter->tx_ring;
3816 struct e1000_tx_desc *tx_desc = NULL;
3817 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3818 u16 size = 512;
3819
3820 tctl = er32(TCTL);
3821 ew32(TCTL, tctl | E1000_TCTL_EN);
3822 tdt = er32(TDT(0));
3823 BUG_ON(tdt != tx_ring->next_to_use);
3824 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
99fe61b2 3825 tx_desc->buffer_addr = cpu_to_le64(tx_ring->dma);
ad851fbb
YL		 3826
3827 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3828 tx_desc->upper.data = 0;
3829 /* flush descriptors to memory before notifying the HW */
3830 wmb();
3831 tx_ring->next_to_use++;
3832 if (tx_ring->next_to_use == tx_ring->count)
3833 tx_ring->next_to_use = 0;
3834 ew32(TDT(0), tx_ring->next_to_use);
ad851fbb
YL		 3835 usleep_range(200, 250);
3836}
3837
3838/**
3839 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
b50f7bca 3840 * @adapter: board private structure
ad851fbb
YL		 3841 *
3842 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3843 */
3844static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3845{
3846 u32 rctl, rxdctl;
3847 struct e1000_hw *hw = &adapter->hw;
3848
3849 rctl = er32(RCTL);
3850 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3851 e1e_flush();
3852 usleep_range(100, 150);
3853
3854 rxdctl = er32(RXDCTL(0));
3855 /* zero the lower 14 bits (prefetch and host thresholds) */
3856 rxdctl &= 0xffffc000;
3857
3858 /* update thresholds: prefetch threshold to 31, host threshold to 1
3859 * and make sure the granularity is "descriptors" and not "cache lines"
3860 */
18dd2392 3861 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
ad851fbb
YL		 3862
3863 ew32(RXDCTL(0), rxdctl);
3864 /* momentarily enable the RX ring for the changes to take effect */
3865 ew32(RCTL, rctl | E1000_RCTL_EN);
3866 e1e_flush();
3867 usleep_range(100, 150);
3868 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3869}
3870
3871/**
3872 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
b50f7bca 3873 * @adapter: board private structure
ad851fbb
YL		 3874 *
3875 * In i219, the descriptor rings must be emptied before resetting the HW
3876 * or before changing the device state to D3 during runtime (runtime PM).
3877 *
3878 * Failure to do this will cause the HW to enter a unit hang state which can
3879 * only be released by PCI reset on the device
3880 *
3881 */
3882
3883static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3884{
ff917429 3885 u16 hang_state;
ad851fbb
YL		 3886 u32 fext_nvm11, tdlen;
3887 struct e1000_hw *hw = &adapter->hw;
3888
3889 /* First, disable MULR fix in FEXTNVM11 */
3890 fext_nvm11 = er32(FEXTNVM11);
3891 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3892 ew32(FEXTNVM11, fext_nvm11);
3893 /* do nothing if we're not in faulty state, or if the queue is empty */
3894 tdlen = er32(TDLEN(0));
ff917429
YL		 3895 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3896 &hang_state);
3897 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
ad851fbb
YL		 3898 return;
3899 e1000_flush_tx_ring(adapter);
3900 /* recheck, maybe the fault is caused by the rx ring */
ff917429
YL		 3901 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3902 &hang_state);
3903 if (hang_state & FLUSH_DESC_REQUIRED)
ad851fbb
YL		 3904 e1000_flush_rx_ring(adapter);
3905}
3906
aa524b66
JK		 3907/**
3908 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3909 * @adapter: board private structure
3910 *
3911 * When the MAC is reset, all hardware bits for timesync will be reset to the
3912 * default values. This function will restore the settings last in place.
3913 * Since the clock SYSTIME registers are reset, we will simply restore the
3914 * cyclecounter to the kernel real clock time.
3915 **/
3916static void e1000e_systim_reset(struct e1000_adapter *adapter)
3917{
3918 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3919 struct e1000_hw *hw = &adapter->hw;
39aa687a 3920 struct netlink_ext_ack extack = {};
aa524b66
JK		 3921 unsigned long flags;
3922 u32 timinca;
3923 s32 ret_val;
3924
3925 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3926 return;
3927
abab010f 3928 if (info->adjfine) {
aa524b66 3929 /* restore the previous ptp frequency delta */
abab010f 3930 ret_val = info->adjfine(info, adapter->ptp_delta);
aa524b66
JK		 3931 } else {
3932 /* set the default base frequency if no adjustment possible */
3933 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3934 if (!ret_val)
3935 ew32(TIMINCA, timinca);
3936 }
3937
3938 if (ret_val) {
3939 dev_warn(&adapter->pdev->dev,
3940 "Failed to restore TIMINCA clock rate delta: %d\n",
3941 ret_val);
3942 return;
3943 }
3944
3945 /* reset the systim ns time counter */
3946 spin_lock_irqsave(&adapter->systim_lock, flags);
3947 timecounter_init(&adapter->tc, &adapter->cc,
3948 ktime_to_ns(ktime_get_real()));
3949 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3950
3951 /* restore the previous hwtstamp configuration settings */
39aa687a
PW		 3952 ret_val = e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config,
3953 &extack);
3954 if (ret_val) {
3955 if (extack._msg)
3956 e_err("%s\n", extack._msg);
3957 }
aa524b66
JK		 3958}
3959
bc7f75fa
AK		 3960/**
3961 * e1000e_reset - bring the hardware into a known good state
b50f7bca 3962 * @adapter: board private structure
bc7f75fa
AK		 3963 *
3964 * This function boots the hardware and enables some settings that
3965 * require a configuration cycle of the hardware - those cannot be
3966 * set/changed during runtime. After reset the device needs to be
ad68076e 3967 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3968 */
3969void e1000e_reset(struct e1000_adapter *adapter)
3970{
3971 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3972 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3973 struct e1000_hw *hw = &adapter->hw;
3974 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3975 u32 pba = adapter->pba;
bc7f75fa
AK		 3976 u16 hwm;
3977
ad68076e 3978 /* reset Packet Buffer Allocation to default */
318a94d6 3979 ew32(PBA, pba);
df762464 3980
8084b86d 3981 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
e921eb1a 3982 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3983 * large enough to accommodate two full transmit packets,
3984 * rounded up to the next 1KB and expressed in KB. Likewise,
3985 * the Rx FIFO should be large enough to accommodate at least
3986 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3987 * expressed in KB.
3988 */
df762464 3989 pba = er32(PBA);
bc7f75fa 3990 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3991 tx_space = pba >> 16;
bc7f75fa 3992 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3993 pba &= 0xffff;
e921eb1a 3994 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3995 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3996 */
3997 min_tx_space = (adapter->max_frame_size +
e5fe2541 3998 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
bc7f75fa
AK		 3999 min_tx_space = ALIGN(min_tx_space, 1024);
4000 min_tx_space >>= 10;
4001 /* software strips receive CRC, so leave room for it */
318a94d6 4002 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 4003 min_rx_space = ALIGN(min_rx_space, 1024);
4004 min_rx_space >>= 10;
4005
e921eb1a 4006 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 4007 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 4008 * allocation, take space away from current Rx allocation
4009 */
df762464
AK		 4010 if ((tx_space < min_tx_space) &&
4011 ((min_tx_space - tx_space) < pba)) {
4012 pba -= min_tx_space - tx_space;
bc7f75fa 4013
e921eb1a 4014 /* if short on Rx space, Rx wins and must trump Tx
419e551c 4015 * adjustment
ad68076e 4016 */
79d4e908 4017 if (pba < min_rx_space)
df762464 4018 pba = min_rx_space;
bc7f75fa 4019 }
df762464
AK		 4020
4021 ew32(PBA, pba);
bc7f75fa
AK		 4022 }
4023
e921eb1a 4024 /* flow control settings
ad68076e 4025 *
38eb394e 4026 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 4027 * (or the size used for early receive) above it in the Rx FIFO.
4028 * Set it to the lower of:
4029 * - 90% of the Rx FIFO size, and
38eb394e 4030 * - the full Rx FIFO size minus one full frame
ad68076e 4031 */
d3738bb8
BA		 4032 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
4033 fc->pause_time = 0xFFFF;
4034 else
4035 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 4036 fc->send_xon = true;
d3738bb8
BA		 4037 fc->current_mode = fc->requested_mode;
4038
4039 switch (hw->mac.type) {
79d4e908
BA		 4040 case e1000_ich9lan:
4041 case e1000_ich10lan:
4042 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4043 pba = 14;
4044 ew32(PBA, pba);
4045 fc->high_water = 0x2800;
4046 fc->low_water = fc->high_water - 8;
4047 break;
4048 }
5463fce6 4049 fallthrough;
d3738bb8 4050 default:
79d4e908
BA		 4051 hwm = min(((pba << 10) * 9 / 10),
4052 ((pba << 10) - adapter->max_frame_size));
d3738bb8 4053
e80bd1d1 4054 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
d3738bb8
BA		 4055 fc->low_water = fc->high_water - 8;
4056 break;
4057 case e1000_pchlan:
e921eb1a 4058 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 4059 * loads. If hangs persist, try disabling Tx flow control.
4060 */
4061 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4062 fc->high_water = 0x3500;
e80bd1d1 4063 fc->low_water = 0x1500;
38eb394e
BA		 4064 } else {
4065 fc->high_water = 0x5000;
e80bd1d1 4066 fc->low_water = 0x3000;
38eb394e 4067 }
a305595b 4068 fc->refresh_time = 0x1000;
d3738bb8
BA		 4069 break;
4070 case e1000_pch2lan:
2fbe4526 4071 case e1000_pch_lpt:
79849ebc 4072 case e1000_pch_spt:
c8744f44 4073 case e1000_pch_cnp:
fb776f5d 4074 case e1000_pch_tgp:
59e46688 4075 case e1000_pch_adp:
cc23f4f0 4076 case e1000_pch_mtp:
820b8ff6 4077 case e1000_pch_lnp:
0c9183ce 4078 case e1000_pch_ptp:
1fe4f45e 4079 case e1000_pch_nvp:
f74dc880
MBM		 4080 fc->refresh_time = 0xFFFF;
4081 fc->pause_time = 0xFFFF;
347b5201
BA		 4082
4083 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4084 fc->high_water = 0x05C20;
4085 fc->low_water = 0x05048;
347b5201 4086 break;
828bac87 4087 }
347b5201 4088
ce345e08
BA		 4089 pba = 14;
4090 ew32(PBA, pba);
347b5201
BA		 4091 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4092 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 4093 break;
38eb394e 4094 }
bc7f75fa 4095
e921eb1a 4096 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 4097 * maximum size per Tx descriptor limited only to the transmit
4098 * allocation of the packet buffer minus 96 bytes with an upper
4099 * limit of 24KB due to receive synchronization limitations.
4100 */
4101 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4102 24 << 10);
4103
e921eb1a 4104 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 4105 * fit in receive buffer.
828bac87
BA		 4106 */
4107 if (adapter->itr_setting & 0x3) {
79d4e908 4108 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 4109 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4110 dev_info(&adapter->pdev->dev,
17e813ec 4111 "Interrupt Throttle Rate off\n");
828bac87 4112 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 4113 e1000e_write_itr(adapter, 0);
828bac87
BA		 4114 }
4115 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4116 dev_info(&adapter->pdev->dev,
17e813ec 4117 "Interrupt Throttle Rate on\n");
828bac87
BA		 4118 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4119 adapter->itr = 20000;
22a4cca2 4120 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 4121 }
4122 }
4123
c8744f44 4124 if (hw->mac.type >= e1000_pch_spt)
0ffc5646 4125 e1000_flush_desc_rings(adapter);
bc7f75fa
AK		 4126 /* Allow time for pending master requests to run */
4127 mac->ops.reset_hw(hw);
97ac8cae 4128
e921eb1a 4129 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 4130 * that the network interface is in control
4131 */
c43bc57e 4132 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 4133 e1000e_get_hw_control(adapter);
97ac8cae 4134
bc7f75fa
AK		 4135 ew32(WUC, 0);
4136
4137 if (mac->ops.init_hw(hw))
44defeb3 4138 e_err("Hardware Error\n");
bc7f75fa
AK		 4139
4140 e1000_update_mng_vlan(adapter);
4141
4142 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4143 ew32(VET, ETH_P_8021Q);
4144
4145 e1000e_reset_adaptive(hw);
31dbe5b4 4146
aa524b66
JK		 4147 /* restore systim and hwtstamp settings */
4148 e1000e_systim_reset(adapter);
b67e1913 4149
d495bcb8
BA		 4150 /* Set EEE advertisement as appropriate */
4151 if (adapter->flags2 & FLAG2_HAS_EEE) {
4152 s32 ret_val;
4153 u16 adv_addr;
4154
4155 switch (hw->phy.type) {
4156 case e1000_phy_82579:
4157 adv_addr = I82579_EEE_ADVERTISEMENT;
4158 break;
4159 case e1000_phy_i217:
4160 adv_addr = I217_EEE_ADVERTISEMENT;
4161 break;
4162 default:
4163 dev_err(&adapter->pdev->dev,
4164 "Invalid PHY type setting EEE advertisement\n");
4165 return;
4166 }
4167
4168 ret_val = hw->phy.ops.acquire(hw);
4169 if (ret_val) {
4170 dev_err(&adapter->pdev->dev,
4171 "EEE advertisement - unable to acquire PHY\n");
4172 return;
4173 }
4174
4175 e1000_write_emi_reg_locked(hw, adv_addr,
4176 hw->dev_spec.ich8lan.eee_disable ?
4177 0 : adapter->eee_advert);
4178
4179 hw->phy.ops.release(hw);
4180 }
4181
31dbe5b4 4182 if (!netif_running(adapter->netdev) &&
28002099 4183 !test_bit(__E1000_TESTING, &adapter->state))
31dbe5b4 4184 e1000_power_down_phy(adapter);
31dbe5b4 4185
bc7f75fa
AK		 4186 e1000_get_phy_info(hw);
4187
918d7197
BA		 4188 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4189 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 4190 u16 phy_data = 0;
e921eb1a 4191 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 4192 * the return value of this function because there is nothing
ad68076e
BA		 4193 * different we would do if it failed
4194 */
bc7f75fa
AK		 4195 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4196 phy_data &= ~IGP02E1000_PM_SPD;
4197 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4198 }
c8744f44 4199 if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) {
ec945cfb
YL		 4200 u32 reg;
4201
4202 /* Fextnvm7 @ 0xe4[2] = 1 */
4203 reg = er32(FEXTNVM7);
4204 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4205 ew32(FEXTNVM7, reg);
4206 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4207 reg = er32(FEXTNVM9);
4208 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4209 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4210 ew32(FEXTNVM9, reg);
4211 }
4212
bc7f75fa
AK		 4213}
4214
a61cfe4f
BP		 4215/**
4216 * e1000e_trigger_lsc - trigger an LSC interrupt
c4dc8dc3 4217 * @adapter: board private structure
a61cfe4f
BP		 4218 *
4219 * Fire a link status change interrupt to start the watchdog.
4220 **/
4221static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
bc7f75fa
AK		 4222{
4223 struct e1000_hw *hw = &adapter->hw;
4224
a61cfe4f 4225 if (adapter->msix_entries)
4aea7a5c 4226 ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER);
a61cfe4f
BP		 4227 else
4228 ew32(ICS, E1000_ICS_LSC);
4229}
4230
4231void e1000e_up(struct e1000_adapter *adapter)
4232{
bc7f75fa
AK		 4233 /* hardware has been reset, we need to reload some things */
4234 e1000_configure(adapter);
4235
4236 clear_bit(__E1000_DOWN, &adapter->state);
4237
4662e82b
BA		 4238 if (adapter->msix_entries)
4239 e1000_configure_msix(adapter);
bc7f75fa
AK		 4240 e1000_irq_enable(adapter);
4241
d17ba0f6 4242 /* Tx queue started by watchdog timer when link is up */
4cb9be7a 4243
a61cfe4f 4244 e1000e_trigger_lsc(adapter);
bc7f75fa
AK		 4245}
4246
713b3c9e
JB		 4247static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4248{
4249 struct e1000_hw *hw = &adapter->hw;
4250
4251 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4252 return;
4253
4254 /* flush pending descriptor writebacks to memory */
4255 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4256 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4257
4258 /* execute the writes immediately */
4259 e1e_flush();
bf03085f 4260
e921eb1a 4261 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 4262 * write is successful
4263 */
4264 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4265 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 4266
4267 /* execute the writes immediately */
4268 e1e_flush();
4269}
4270
67fd4fcb
JK		 4271static void e1000e_update_stats(struct e1000_adapter *adapter);
4272
28002099
DE		 4273/**
4274 * e1000e_down - quiesce the device and optionally reset the hardware
4275 * @adapter: board private structure
4276 * @reset: boolean flag to reset the hardware or not
4277 */
4278void e1000e_down(struct e1000_adapter *adapter, bool reset)
bc7f75fa
AK		 4279{
4280 struct net_device *netdev = adapter->netdev;
4281 struct e1000_hw *hw = &adapter->hw;
4282 u32 tctl, rctl;
4283
e921eb1a 4284 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 4285 * reschedule our watchdog timer
4286 */
bc7f75fa
AK		 4287 set_bit(__E1000_DOWN, &adapter->state);
4288
a60a132e
ET		 4289 netif_carrier_off(netdev);
4290
bc7f75fa
AK		 4291 /* disable receives in the hardware */
4292 rctl = er32(RCTL);
7f99ae63
BA		 4293 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4294 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 4295 /* flush and sleep below */
4296
4cb9be7a 4297 netif_stop_queue(netdev);
bc7f75fa
AK		 4298
4299 /* disable transmits in the hardware */
4300 tctl = er32(TCTL);
4301 tctl &= ~E1000_TCTL_EN;
4302 ew32(TCTL, tctl);
7f99ae63 4303
bc7f75fa
AK		 4304 /* flush both disables and wait for them to finish */
4305 e1e_flush();
ab6973ae 4306 usleep_range(10000, 11000);
bc7f75fa 4307
bc7f75fa
AK		 4308 e1000_irq_disable(adapter);
4309
a3b87a4c
BA		 4310 napi_synchronize(&adapter->napi);
4311
8fa7292f
TG		 4312 timer_delete_sync(&adapter->watchdog_timer);
4313 timer_delete_sync(&adapter->phy_info_timer);
bc7f75fa 4314
67fd4fcb
JK		 4315 spin_lock(&adapter->stats64_lock);
4316 e1000e_update_stats(adapter);
4317 spin_unlock(&adapter->stats64_lock);
4318
400484fa 4319 e1000e_flush_descriptors(adapter);
400484fa 4320
bc7f75fa
AK		 4321 adapter->link_speed = 0;
4322 adapter->link_duplex = 0;
4323
da1e2046
BA		 4324 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4325 if ((hw->mac.type >= e1000_pch2lan) &&
4326 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4327 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4328 e_dbg("failed to disable jumbo frame workaround mode\n");
4329
0ffc5646
YL		 4330 if (!pci_channel_offline(adapter->pdev)) {
4331 if (reset)
4332 e1000e_reset(adapter);
c8744f44 4333 else if (hw->mac.type >= e1000_pch_spt)
0ffc5646
YL		 4334 e1000_flush_desc_rings(adapter);
4335 }
4336 e1000_clean_tx_ring(adapter->tx_ring);
4337 e1000_clean_rx_ring(adapter->rx_ring);
bc7f75fa
AK		 4338}
4339
4340void e1000e_reinit_locked(struct e1000_adapter *adapter)
4341{
4342 might_sleep();
4343 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
ab6973ae 4344 usleep_range(1000, 1100);
28002099 4345 e1000e_down(adapter, true);
bc7f75fa
AK		 4346 e1000e_up(adapter);
4347 clear_bit(__E1000_RESETTING, &adapter->state);
4348}
4349
0be5b96c
JW		 4350/**
4351 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4352 * @hw: pointer to the HW structure
98942d70
ML		 4353 * @systim: PHC time value read, sanitized and returned
4354 * @sts: structure to hold system time before and after reading SYSTIML,
4355 * may be NULL
0be5b96c
JW		 4356 *
4357 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4358 * check to see that the time is incrementing at a reasonable
4359 * rate and is a multiple of incvalue.
4360 **/
98942d70
ML		 4361static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim,
4362 struct ptp_system_timestamp *sts)
0be5b96c
JW		 4363{
4364 u64 time_delta, rem, temp;
a5a1d1c2 4365 u64 systim_next;
0be5b96c
JW		 4366 u32 incvalue;
4367 int i;
4368
4369 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4370 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4371 /* latch SYSTIMH on read of SYSTIML */
98942d70 4372 ptp_read_system_prets(sts);
a5a1d1c2 4373 systim_next = (u64)er32(SYSTIML);
98942d70 4374 ptp_read_system_postts(sts);
a5a1d1c2 4375 systim_next |= (u64)er32(SYSTIMH) << 32;
0be5b96c
JW		 4376
4377 time_delta = systim_next - systim;
4378 temp = time_delta;
4379 /* VMWare users have seen incvalue of zero, don't div / 0 */
4380 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
4381
4382 systim = systim_next;
4383
4384 if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0))
4385 break;
4386 }
4387
4388 return systim;
4389}
4390
b67e1913 4391/**
98942d70
ML		 4392 * e1000e_read_systim - read SYSTIM register
4393 * @adapter: board private structure
4394 * @sts: structure which will contain system time before and after reading
4395 * SYSTIML, may be NULL
b67e1913 4396 **/
98942d70
ML		 4397u64 e1000e_read_systim(struct e1000_adapter *adapter,
4398 struct ptp_system_timestamp *sts)
b67e1913 4399{
b67e1913 4400 struct e1000_hw *hw = &adapter->hw;
98942d70 4401 u32 systimel, systimel_2, systimeh;
a5a1d1c2 4402 u64 systim;
37b12910
RA		 4403 /* SYSTIMH latching upon SYSTIML read does not work well.
4404 * This means that if SYSTIML overflows after we read it but before
4405 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4406 * will experience a huge non linear increment in the systime value
4407 * to fix that we test for overflow and if true, we re-read systime.
83129b37 4408 */
98942d70 4409 ptp_read_system_prets(sts);
ab507c9a 4410 systimel = er32(SYSTIML);
98942d70 4411 ptp_read_system_postts(sts);
37b12910 4412 systimeh = er32(SYSTIMH);
ab507c9a
DV		 4413 /* Is systimel is so large that overflow is possible? */
4414 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
98942d70
ML		 4415 ptp_read_system_prets(sts);
4416 systimel_2 = er32(SYSTIML);
4417 ptp_read_system_postts(sts);
ab507c9a
DV		 4418 if (systimel > systimel_2) {
4419 /* There was an overflow, read again SYSTIMH, and use
4420 * systimel_2
4421 */
4422 systimeh = er32(SYSTIMH);
4423 systimel = systimel_2;
4424 }
37b12910 4425 }
a5a1d1c2
TG		 4426 systim = (u64)systimel;
4427 systim |= (u64)systimeh << 32;
b67e1913 4428
0be5b96c 4429 if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW)
98942d70 4430 systim = e1000e_sanitize_systim(hw, systim, sts);
5e7ff970 4431
b67e1913
BA		 4432 return systim;
4433}
4434
98942d70
ML		 4435/**
4436 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4437 * @cc: cyclecounter structure
4438 **/
4439static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc)
4440{
4441 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4442 cc);
4443
4444 return e1000e_read_systim(adapter, NULL);
4445}
4446
bc7f75fa
AK		 4447/**
4448 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4449 * @adapter: board private structure to initialize
4450 *
4451 * e1000_sw_init initializes the Adapter private data structure.
4452 * Fields are initialized based on PCI device information and
4453 * OS network device settings (MTU size).
4454 **/
9f9a12f8 4455static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4456{
bc7f75fa
AK		 4457 struct net_device *netdev = adapter->netdev;
4458
8084b86d 4459 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
bc7f75fa 4460 adapter->rx_ps_bsize0 = 128;
8084b86d 4461 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
318a94d6 4462 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4463 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4464 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4465
67fd4fcb
JK		 4466 spin_lock_init(&adapter->stats64_lock);
4467
4662e82b 4468 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4469
4662e82b
BA		 4470 if (e1000_alloc_queues(adapter))
4471 return -ENOMEM;
bc7f75fa 4472
b67e1913
BA		 4473 /* Setup hardware time stamping cyclecounter */
4474 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4475 adapter->cc.read = e1000e_cyclecounter_read;
4d045b4c 4476 adapter->cc.mask = CYCLECOUNTER_MASK(64);
b67e1913
BA		 4477 adapter->cc.mult = 1;
4478 /* cc.shift set in e1000e_get_base_tininca() */
4479
4480 spin_lock_init(&adapter->systim_lock);
4481 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4482 }
4483
bc7f75fa 4484 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4485 e1000_irq_disable(adapter);
4486
bc7f75fa
AK		 4487 set_bit(__E1000_DOWN, &adapter->state);
4488 return 0;
bc7f75fa
AK		 4489}
4490
f8d59f78
BA		 4491/**
4492 * e1000_intr_msi_test - Interrupt Handler
4493 * @irq: interrupt number
4494 * @data: pointer to a network interface device structure
4495 **/
8bb62869 4496static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
f8d59f78
BA		 4497{
4498 struct net_device *netdev = data;
4499 struct e1000_adapter *adapter = netdev_priv(netdev);
4500 struct e1000_hw *hw = &adapter->hw;
4501 u32 icr = er32(ICR);
4502
3bb99fe2 4503 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4504 if (icr & E1000_ICR_RXSEQ) {
4505 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4506 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4507 * interrupt is handled.
4508 */
f8d59f78
BA		 4509 wmb();
4510 }
4511
4512 return IRQ_HANDLED;
4513}
4514
4515/**
4516 * e1000_test_msi_interrupt - Returns 0 for successful test
4517 * @adapter: board private struct
4518 *
4519 * code flow taken from tg3.c
4520 **/
4521static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4522{
4523 struct net_device *netdev = adapter->netdev;
4524 struct e1000_hw *hw = &adapter->hw;
4525 int err;
4526
4527 /* poll_enable hasn't been called yet, so don't need disable */
4528 /* clear any pending events */
4529 er32(ICR);
4530
4531 /* free the real vector and request a test handler */
4532 e1000_free_irq(adapter);
4662e82b 4533 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4534
4535 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4536 * MSI irq handler will unset this flag
4537 */
f8d59f78
BA		 4538 adapter->flags |= FLAG_MSI_TEST_FAILED;
4539
4540 err = pci_enable_msi(adapter->pdev);
4541 if (err)
4542 goto msi_test_failed;
4543
a0607fd3 4544 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4545 netdev->name, netdev);
4546 if (err) {
4547 pci_disable_msi(adapter->pdev);
4548 goto msi_test_failed;
4549 }
4550
e921eb1a 4551 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4552 * interrupt.
4553 */
f8d59f78
BA		 4554 wmb();
4555
4556 e1000_irq_enable(adapter);
4557
4558 /* fire an unusual interrupt on the test handler */
4559 ew32(ICS, E1000_ICS_RXSEQ);
4560 e1e_flush();
569a3aff 4561 msleep(100);
f8d59f78
BA		 4562
4563 e1000_irq_disable(adapter);
4564
bc76329d 4565 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4566
4567 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4568 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4569 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4570 } else {
068e8a30 4571 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4572 }
f8d59f78
BA		 4573
4574 free_irq(adapter->pdev->irq, netdev);
4575 pci_disable_msi(adapter->pdev);
4576
f8d59f78 4577msi_test_failed:
4662e82b 4578 e1000e_set_interrupt_capability(adapter);
068e8a30 4579 return e1000_request_irq(adapter);
f8d59f78
BA		 4580}
4581
4582/**
4583 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4584 * @adapter: board private struct
4585 *
4586 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4587 **/
4588static int e1000_test_msi(struct e1000_adapter *adapter)
4589{
4590 int err;
4591 u16 pci_cmd;
4592
4593 if (!(adapter->flags & FLAG_MSI_ENABLED))
4594 return 0;
4595
4596 /* disable SERR in case the MSI write causes a master abort */
4597 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4598 if (pci_cmd & PCI_COMMAND_SERR)
4599 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4600 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4601
4602 err = e1000_test_msi_interrupt(adapter);
4603
36f2407f
DN		 4604 /* re-enable SERR */
4605 if (pci_cmd & PCI_COMMAND_SERR) {
4606 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4607 pci_cmd |= PCI_COMMAND_SERR;
4608 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4609 }
f8d59f78 4610
f8d59f78
BA		 4611 return err;
4612}
4613
bc7f75fa 4614/**
d5ea45da 4615 * e1000e_open - Called when a network interface is made active
bc7f75fa
AK		 4616 * @netdev: network interface device structure
4617 *
4618 * Returns 0 on success, negative value on failure
4619 *
4620 * The open entry point is called when a network interface is made
4621 * active by the system (IFF_UP). At this point all resources needed
4622 * for transmit and receive operations are allocated, the interrupt
4623 * handler is registered with the OS, the watchdog timer is started,
4624 * and the stack is notified that the interface is ready.
4625 **/
d5ea45da 4626int e1000e_open(struct net_device *netdev)
bc7f75fa
AK		 4627{
4628 struct e1000_adapter *adapter = netdev_priv(netdev);
4629 struct e1000_hw *hw = &adapter->hw;
23606cf5 4630 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4631 int err;
c6b8cd69 4632 int irq;
bc7f75fa
AK		 4633
4634 /* disallow open during test */
4635 if (test_bit(__E1000_TESTING, &adapter->state))
4636 return -EBUSY;
4637
23606cf5
RW		 4638 pm_runtime_get_sync(&pdev->dev);
4639
9c563d20 4640 netif_carrier_off(netdev);
d17ba0f6 4641 netif_stop_queue(netdev);
9c563d20 4642
bc7f75fa 4643 /* allocate transmit descriptors */
55aa6985 4644 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4645 if (err)
4646 goto err_setup_tx;
4647
4648 /* allocate receive descriptors */
55aa6985 4649 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4650 if (err)
4651 goto err_setup_rx;
4652
e921eb1a 4653 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4654 * interface is now open and reset the part to a known state.
4655 */
4656 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4657 e1000e_get_hw_control(adapter);
11b08be8
BA		 4658 e1000e_reset(adapter);
4659 }
4660
bc7f75fa
AK		 4661 e1000e_power_up_phy(adapter);
4662
4663 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
e5fe2541 4664 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
bc7f75fa
AK		 4665 e1000_update_mng_vlan(adapter);
4666
79d4e908 4667 /* DMA latency requirement to workaround jumbo issue */
81e95ad7 4668 cpu_latency_qos_add_request(&adapter->pm_qos_req, PM_QOS_DEFAULT_VALUE);
c128ec29 4669
e921eb1a 4670 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4671 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4672 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4673 * clean_rx handler before we do so.
4674 */
bc7f75fa
AK		 4675 e1000_configure(adapter);
4676
4677 err = e1000_request_irq(adapter);
4678 if (err)
4679 goto err_req_irq;
4680
e921eb1a 4681 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4682 * ignore e1000e MSI messages, which means we need to test our MSI
4683 * interrupt now
4684 */
4662e82b 4685 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4686 err = e1000_test_msi(adapter);
4687 if (err) {
4688 e_err("Interrupt allocation failed\n");
4689 goto err_req_irq;
4690 }
4691 }
4692
bc7f75fa
AK		 4693 /* From here on the code is the same as e1000e_up() */
4694 clear_bit(__E1000_DOWN, &adapter->state);
4695
c6b8cd69
JD		 4696 if (adapter->int_mode == E1000E_INT_MODE_MSIX)
4697 irq = adapter->msix_entries[0].vector;
4698 else
4699 irq = adapter->pdev->irq;
4700
4701 netif_napi_set_irq(&adapter->napi, irq);
bc7f75fa 4702 napi_enable(&adapter->napi);
c6b8cd69
JD		 4703 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, &adapter->napi);
4704 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, &adapter->napi);
bc7f75fa
AK		 4705
4706 e1000_irq_enable(adapter);
4707
09357b00 4708 adapter->tx_hang_recheck = false;
d55b53ff 4709
66148bab 4710 hw->mac.get_link_status = true;
23606cf5
RW		 4711 pm_runtime_put(&pdev->dev);
4712
a61cfe4f 4713 e1000e_trigger_lsc(adapter);
bc7f75fa
AK		 4714
4715 return 0;
4716
4717err_req_irq:
81e95ad7 4718 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
31dbe5b4 4719 e1000e_release_hw_control(adapter);
bc7f75fa 4720 e1000_power_down_phy(adapter);
55aa6985 4721 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4722err_setup_rx:
55aa6985 4723 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4724err_setup_tx:
4725 e1000e_reset(adapter);
23606cf5 4726 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4727
4728 return err;
4729}
4730
4731/**
d5ea45da 4732 * e1000e_close - Disables a network interface
bc7f75fa
AK		 4733 * @netdev: network interface device structure
4734 *
4735 * Returns 0, this is not allowed to fail
4736 *
4737 * The close entry point is called when an interface is de-activated
4738 * by the OS. The hardware is still under the drivers control, but
4739 * needs to be disabled. A global MAC reset is issued to stop the
4740 * hardware, and all transmit and receive resources are freed.
4741 **/
d5ea45da 4742int e1000e_close(struct net_device *netdev)
bc7f75fa
AK		 4743{
4744 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4745 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4746 int count = E1000_CHECK_RESET_COUNT;
4747
4748 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
ab6973ae 4749 usleep_range(10000, 11000);
bc7f75fa
AK		 4750
4751 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4752
4753 pm_runtime_get_sync(&pdev->dev);
4754
a7023819 4755 if (netif_device_present(netdev)) {
28002099 4756 e1000e_down(adapter, true);
23606cf5 4757 e1000_free_irq(adapter);
63eb48f1
DE		 4758
4759 /* Link status message must follow this format */
c557a4b3 4760 netdev_info(netdev, "NIC Link is Down\n");
23606cf5 4761 }
a3b87a4c 4762
c6b8cd69
JD		 4763 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_RX, NULL);
4764 netif_queue_set_napi(netdev, 0, NETDEV_QUEUE_TYPE_TX, NULL);
a3b87a4c
BA		 4765 napi_disable(&adapter->napi);
4766
55aa6985
BA		 4767 e1000e_free_tx_resources(adapter->tx_ring);
4768 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4769
e921eb1a 4770 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4771 * the same ID is registered on the host OS (let 8021q kill it)
4772 */
e5fe2541 4773 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
80d5c368
PM		 4774 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4775 adapter->mng_vlan_id);
bc7f75fa 4776
e921eb1a 4777 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4778 * interface is now closed
4779 */
31dbe5b4
BA		 4780 if ((adapter->flags & FLAG_HAS_AMT) &&
4781 !test_bit(__E1000_TESTING, &adapter->state))
4782 e1000e_release_hw_control(adapter);
bc7f75fa 4783
81e95ad7 4784 cpu_latency_qos_remove_request(&adapter->pm_qos_req);
c128ec29 4785
23606cf5
RW		 4786 pm_runtime_put_sync(&pdev->dev);
4787
bc7f75fa
AK		 4788 return 0;
4789}
fc830b78 4790
bc7f75fa
AK		 4791/**
4792 * e1000_set_mac - Change the Ethernet Address of the NIC
4793 * @netdev: network interface device structure
4794 * @p: pointer to an address structure
4795 *
4796 * Returns 0 on success, negative on failure
4797 **/
4798static int e1000_set_mac(struct net_device *netdev, void *p)
4799{
4800 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4801 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4802 struct sockaddr *addr = p;
4803
4804 if (!is_valid_ether_addr(addr->sa_data))
4805 return -EADDRNOTAVAIL;
4806
a05e4c0a 4807 eth_hw_addr_set(netdev, addr->sa_data);
bc7f75fa
AK		 4808 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4809
69e1e019 4810 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4811
4812 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4813 /* activate the work around */
4814 e1000e_set_laa_state_82571(&adapter->hw, 1);
4815
e921eb1a 4816 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4817 * between the time RAR[0] gets clobbered and the time it
4818 * gets fixed (in e1000_watchdog), the actual LAA is in one
4819 * of the RARs and no incoming packets directed to this port
4820 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4821 * RAR[14]
4822 */
69e1e019
BA		 4823 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4824 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4825 }
4826
4827 return 0;
4828}
4829
a8f88ff5
JB		 4830/**
4831 * e1000e_update_phy_task - work thread to update phy
4832 * @work: pointer to our work struct
4833 *
4834 * this worker thread exists because we must acquire a
4835 * semaphore to read the phy, which we could msleep while
4836 * waiting for it, and we can't msleep in a timer.
4837 **/
4838static void e1000e_update_phy_task(struct work_struct *work)
4839{
4840 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4841 struct e1000_adapter,
4842 update_phy_task);
a03206ed 4843 struct e1000_hw *hw = &adapter->hw;
615b32af
JB		 4844
4845 if (test_bit(__E1000_DOWN, &adapter->state))
4846 return;
4847
a03206ed
DE		 4848 e1000_get_phy_info(hw);
4849
4850 /* Enable EEE on 82579 after link up */
50844bb7 4851 if (hw->phy.type >= e1000_phy_82579)
a03206ed 4852 e1000_set_eee_pchlan(hw);
a8f88ff5
JB		 4853}
4854
e921eb1a
BA		 4855/**
4856 * e1000_update_phy_info - timre call-back to update PHY info
b50f7bca 4857 * @t: pointer to timer_list containing private info adapter
e921eb1a 4858 *
ad68076e
BA		 4859 * Need to wait a few seconds after link up to get diagnostic information from
4860 * the phy
e921eb1a 4861 **/
26566eae 4862static void e1000_update_phy_info(struct timer_list *t)
bc7f75fa 4863{
41cb0855
IM		 4864 struct e1000_adapter *adapter = timer_container_of(adapter, t,
4865 phy_info_timer);
615b32af
JB		 4866
4867 if (test_bit(__E1000_DOWN, &adapter->state))
4868 return;
4869
a8f88ff5 4870 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4871}
4872
8c7bbb92
BA		 4873/**
4874 * e1000e_update_phy_stats - Update the PHY statistics counters
4875 * @adapter: board private structure
2b6b168d
BA		 4876 *
4877 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4878 **/
4879static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4880{
4881 struct e1000_hw *hw = &adapter->hw;
4882 s32 ret_val;
4883 u16 phy_data;
4884
4885 ret_val = hw->phy.ops.acquire(hw);
4886 if (ret_val)
4887 return;
4888
e921eb1a 4889 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4890 * If not, set to the page with the PHY status registers.
4891 */
2b6b168d 4892 hw->phy.addr = 1;
8c7bbb92
BA		 4893 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4894 &phy_data);
4895 if (ret_val)
4896 goto release;
2b6b168d
BA		 4897 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4898 ret_val = hw->phy.ops.set_page(hw,
4899 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4900 if (ret_val)
4901 goto release;
4902 }
4903
8c7bbb92 4904 /* Single Collision Count */
2b6b168d
BA		 4905 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4906 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4907 if (!ret_val)
4908 adapter->stats.scc += phy_data;
4909
4910 /* Excessive Collision Count */
2b6b168d
BA		 4911 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4912 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4913 if (!ret_val)
4914 adapter->stats.ecol += phy_data;
4915
4916 /* Multiple Collision Count */
2b6b168d
BA		 4917 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4918 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4919 if (!ret_val)
4920 adapter->stats.mcc += phy_data;
4921
4922 /* Late Collision Count */
2b6b168d
BA		 4923 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4924 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4925 if (!ret_val)
4926 adapter->stats.latecol += phy_data;
4927
4928 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4929 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4930 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4931 if (!ret_val)
4932 hw->mac.collision_delta = phy_data;
4933
4934 /* Defer Count */
2b6b168d
BA		 4935 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4936 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4937 if (!ret_val)
4938 adapter->stats.dc += phy_data;
4939
4940 /* Transmit with no CRS */
2b6b168d
BA		 4941 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4942 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4943 if (!ret_val)
4944 adapter->stats.tncrs += phy_data;
4945
4946release:
4947 hw->phy.ops.release(hw);
4948}
4949
bc7f75fa
AK		 4950/**
4951 * e1000e_update_stats - Update the board statistics counters
4952 * @adapter: board private structure
4953 **/
67fd4fcb 4954static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4955{
7274c20f 4956 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4957 struct e1000_hw *hw = &adapter->hw;
4958 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4959
e921eb1a 4960 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4961 * connection is down.
4962 */
4963 if (adapter->link_speed == 0)
4964 return;
4965 if (pci_channel_offline(pdev))
4966 return;
4967
bc7f75fa
AK		 4968 adapter->stats.crcerrs += er32(CRCERRS);
4969 adapter->stats.gprc += er32(GPRC);
7c25769f 4970 adapter->stats.gorc += er32(GORCL);
e80bd1d1 4971 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4972 adapter->stats.bprc += er32(BPRC);
4973 adapter->stats.mprc += er32(MPRC);
4974 adapter->stats.roc += er32(ROC);
4975
bc7f75fa 4976 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4977
4978 /* Half-duplex statistics */
4979 if (adapter->link_duplex == HALF_DUPLEX) {
4980 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4981 e1000e_update_phy_stats(adapter);
4982 } else {
4983 adapter->stats.scc += er32(SCC);
4984 adapter->stats.ecol += er32(ECOL);
4985 adapter->stats.mcc += er32(MCC);
4986 adapter->stats.latecol += er32(LATECOL);
4987 adapter->stats.dc += er32(DC);
4988
4989 hw->mac.collision_delta = er32(COLC);
4990
4991 if ((hw->mac.type != e1000_82574) &&
4992 (hw->mac.type != e1000_82583))
4993 adapter->stats.tncrs += er32(TNCRS);
4994 }
4995 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4996 }
8c7bbb92 4997
bc7f75fa
AK		 4998 adapter->stats.xonrxc += er32(XONRXC);
4999 adapter->stats.xontxc += er32(XONTXC);
5000 adapter->stats.xoffrxc += er32(XOFFRXC);
5001 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 5002 adapter->stats.gptc += er32(GPTC);
7c25769f 5003 adapter->stats.gotc += er32(GOTCL);
e80bd1d1 5004 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 5005 adapter->stats.rnbc += er32(RNBC);
5006 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 5007
5008 adapter->stats.mptc += er32(MPTC);
5009 adapter->stats.bptc += er32(BPTC);
5010
5011 /* used for adaptive IFS */
5012
5013 hw->mac.tx_packet_delta = er32(TPT);
5014 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 5015
5016 adapter->stats.algnerrc += er32(ALGNERRC);
5017 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 5018 adapter->stats.cexterr += er32(CEXTERR);
5019 adapter->stats.tsctc += er32(TSCTC);
5020 adapter->stats.tsctfc += er32(TSCTFC);
5021
bc7f75fa 5022 /* Fill out the OS statistics structure */
7274c20f
AK		 5023 netdev->stats.multicast = adapter->stats.mprc;
5024 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 5025
5026 /* Rx Errors */
5027
e921eb1a 5028 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 5029 * our own version based on RUC and ROC
5030 */
7274c20f 5031 netdev->stats.rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 5032 adapter->stats.crcerrs + adapter->stats.algnerrc +
5033 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
7274c20f 5034 netdev->stats.rx_length_errors = adapter->stats.ruc +
f0ff4398 5035 adapter->stats.roc;
7274c20f
AK		 5036 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
5037 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
5038 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 5039
5040 /* Tx Errors */
f0ff4398 5041 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
7274c20f
AK		 5042 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
5043 netdev->stats.tx_window_errors = adapter->stats.latecol;
5044 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 5045
5046 /* Tx Dropped needs to be maintained elsewhere */
5047
bc7f75fa
AK		 5048 /* Management Stats */
5049 adapter->stats.mgptc += er32(MGTPTC);
5050 adapter->stats.mgprc += er32(MGTPRC);
5051 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 5052
5053 /* Correctable ECC Errors */
c8744f44 5054 if (hw->mac.type >= e1000_pch_lpt) {
94fb848b 5055 u32 pbeccsts = er32(PBECCSTS);
6cf08d1c 5056
94fb848b
BA		 5057 adapter->corr_errors +=
5058 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
5059 adapter->uncorr_errors +=
b9a45254 5060 FIELD_GET(E1000_PBECCSTS_UNCORR_ERR_CNT_MASK, pbeccsts);
94fb848b 5061 }
bc7f75fa
AK		 5062}
5063
7c25769f
BA		 5064/**
5065 * e1000_phy_read_status - Update the PHY register status snapshot
5066 * @adapter: board private structure
5067 **/
5068static void e1000_phy_read_status(struct e1000_adapter *adapter)
5069{
5070 struct e1000_hw *hw = &adapter->hw;
5071 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f 5072
97390ab8
BA		 5073 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
5074 (er32(STATUS) & E1000_STATUS_LU) &&
7c25769f 5075 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 5076 int ret_val;
5077
c2ade1a4
BA		 5078 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
5079 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
5080 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
5081 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
5082 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
5083 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
5084 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
5085 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
7c25769f 5086 if (ret_val)
44defeb3 5087 e_warn("Error reading PHY register\n");
7c25769f 5088 } else {
e921eb1a 5089 /* Do not read PHY registers if link is not up
7c25769f
BA		 5090 * Set values to typical power-on defaults
5091 */
5092 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5093 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5094 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5095 BMSR_ERCAP);
5096 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5097 ADVERTISE_ALL | ADVERTISE_CSMA);
5098 phy->lpa = 0;
5099 phy->expansion = EXPANSION_ENABLENPAGE;
5100 phy->ctrl1000 = ADVERTISE_1000FULL;
5101 phy->stat1000 = 0;
5102 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5103 }
7c25769f
BA		 5104}
5105
bc7f75fa
AK		 5106static void e1000_print_link_info(struct e1000_adapter *adapter)
5107{
bc7f75fa
AK		 5108 struct e1000_hw *hw = &adapter->hw;
5109 u32 ctrl = er32(CTRL);
5110
8f12fe86 5111 /* Link status message must follow this format for user tools */
c557a4b3
AD		 5112 netdev_info(adapter->netdev,
5113 "NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5114 adapter->link_speed,
5115 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5116 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5117 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5118 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 5119}
5120
0c6bdb30 5121static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 5122{
5123 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 5124 bool link_active = false;
318a94d6
JK		 5125 s32 ret_val = 0;
5126
e921eb1a 5127 /* get_link_status is set on LSC (link status) interrupt or
318a94d6 5128 * Rx sequence error interrupt. get_link_status will stay
65a29da1 5129 * true until the check_for_link establishes link
318a94d6
JK		 5130 * for copper adapters ONLY
5131 */
5132 switch (hw->phy.media_type) {
5133 case e1000_media_type_copper:
5134 if (hw->mac.get_link_status) {
5135 ret_val = hw->mac.ops.check_for_link(hw);
3016e0a0 5136 link_active = !hw->mac.get_link_status;
318a94d6 5137 } else {
3db1cd5c 5138 link_active = true;
318a94d6
JK		 5139 }
5140 break;
5141 case e1000_media_type_fiber:
5142 ret_val = hw->mac.ops.check_for_link(hw);
5143 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5144 break;
5145 case e1000_media_type_internal_serdes:
5146 ret_val = hw->mac.ops.check_for_link(hw);
65a29da1 5147 link_active = hw->mac.serdes_has_link;
318a94d6
JK		 5148 break;
5149 default:
5150 case e1000_media_type_unknown:
5151 break;
5152 }
5153
d3509f8b 5154 if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
318a94d6
JK		 5155 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5156 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 5157 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 5158 }
5159
5160 return link_active;
5161}
5162
5163static void e1000e_enable_receives(struct e1000_adapter *adapter)
5164{
5165 /* make sure the receive unit is started */
5166 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 5167 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 5168 struct e1000_hw *hw = &adapter->hw;
5169 u32 rctl = er32(RCTL);
6cf08d1c 5170
318a94d6 5171 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 5172 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 5173 }
5174}
5175
ff10e13c
CW		 5176static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5177{
5178 struct e1000_hw *hw = &adapter->hw;
5179
e921eb1a 5180 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 5181 * for hung state and reset, if two calls return true
5182 */
5183 if (e1000_check_phy_82574(hw))
5184 adapter->phy_hang_count++;
5185 else
5186 adapter->phy_hang_count = 0;
5187
5188 if (adapter->phy_hang_count > 1) {
5189 adapter->phy_hang_count = 0;
d9554e96 5190 e_dbg("PHY appears hung - resetting\n");
ff10e13c
CW		 5191 schedule_work(&adapter->reset_task);
5192 }
5193}
5194
d5ad7a6a
JK		 5195/**
5196 * e1000_watchdog - Timer Call-back
b50f7bca 5197 * @t: pointer to timer_list containing private info adapter
d5ad7a6a
JK		 5198 **/
5199static void e1000_watchdog(struct timer_list *t)
5200{
41cb0855
IM		 5201 struct e1000_adapter *adapter = timer_container_of(adapter, t,
5202 watchdog_timer);
d5ad7a6a
JK		 5203
5204 /* Do the rest outside of interrupt context */
5205 schedule_work(&adapter->watchdog_task);
5206
5207 /* TODO: make this use queue_delayed_work() */
5208}
5209
bc7f75fa
AK		 5210static void e1000_watchdog_task(struct work_struct *work)
5211{
5212 struct e1000_adapter *adapter = container_of(work,
17e813ec 5213 struct e1000_adapter,
d5ad7a6a 5214 watchdog_task);
bc7f75fa
AK		 5215 struct net_device *netdev = adapter->netdev;
5216 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 5217 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa 5218 struct e1000_ring *tx_ring = adapter->tx_ring;
def4ec6d 5219 u32 dmoff_exit_timeout = 100, tries = 0;
bc7f75fa 5220 struct e1000_hw *hw = &adapter->hw;
def4ec6d 5221 u32 link, tctl, pcim_state;
bc7f75fa 5222
615b32af
JB		 5223 if (test_bit(__E1000_DOWN, &adapter->state))
5224 return;
5225
b405e8df 5226 link = e1000e_has_link(adapter);
318a94d6 5227 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 5228 /* Cancel scheduled suspend requests. */
5229 pm_runtime_resume(netdev->dev.parent);
5230
318a94d6 5231 e1000e_enable_receives(adapter);
bc7f75fa 5232 goto link_up;
bc7f75fa
AK		 5233 }
5234
5235 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5236 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5237 e1000_update_mng_vlan(adapter);
5238
bc7f75fa
AK		 5239 if (link) {
5240 if (!netif_carrier_ok(netdev)) {
3db1cd5c 5241 bool txb2b = true;
23606cf5
RW		 5242
5243 /* Cancel scheduled suspend requests. */
5244 pm_runtime_resume(netdev->dev.parent);
5245
def4ec6d 5246 /* Checking if MAC is in DMoff state*/
2e7256f1 5247 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID) {
def4ec6d 5248 pcim_state = er32(STATUS);
2e7256f1
SN		 5249 while (pcim_state & E1000_STATUS_PCIM_STATE) {
5250 if (tries++ == dmoff_exit_timeout) {
5251 e_dbg("Error in exiting dmoff\n");
5252 break;
5253 }
5254 usleep_range(10000, 20000);
5255 pcim_state = er32(STATUS);
5256
5257 /* Checking if MAC exited DMoff state */
5258 if (!(pcim_state & E1000_STATUS_PCIM_STATE))
5259 e1000_phy_hw_reset(&adapter->hw);
5260 }
def4ec6d
VL		 5261 }
5262
318a94d6 5263 /* update snapshot of PHY registers on LSC */
7c25769f 5264 e1000_phy_read_status(adapter);
bc7f75fa 5265 mac->ops.get_link_up_info(&adapter->hw,
17e813ec
BA		 5266 &adapter->link_speed,
5267 &adapter->link_duplex);
bc7f75fa 5268 e1000_print_link_info(adapter);
e792cd91
KS		 5269
5270 /* check if SmartSpeed worked */
5271 e1000e_check_downshift(hw);
5272 if (phy->speed_downgraded)
5273 netdev_warn(netdev,
5274 "Link Speed was downgraded by SmartSpeed\n");
5275
e921eb1a 5276 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 5277 * if link has autonegotiated at 10/100 half
5278 */
5279 if ((hw->phy.type == e1000_phy_igp_3 ||
5280 hw->phy.type == e1000_phy_bm) &&
138953bb 5281 hw->mac.autoneg &&
f4187b56
BA		 5282 (adapter->link_speed == SPEED_10 ||
5283 adapter->link_speed == SPEED_100) &&
5284 (adapter->link_duplex == HALF_DUPLEX)) {
5285 u16 autoneg_exp;
5286
c2ade1a4 5287 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
f4187b56 5288
c2ade1a4 5289 if (!(autoneg_exp & EXPANSION_NWAY))
ef456f85 5290 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 5291 }
5292
f49c57e1 5293 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 5294 adapter->tx_timeout_factor = 1;
5295 switch (adapter->link_speed) {
5296 case SPEED_10:
3db1cd5c 5297 txb2b = false;
10f1b492 5298 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 5299 break;
5300 case SPEED_100:
3db1cd5c 5301 txb2b = false;
4c86e0b9 5302 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 5303 break;
5304 }
5305
e921eb1a 5306 /* workaround: re-program speed mode bit after
ad68076e
BA		 5307 * link-up event
5308 */
bc7f75fa
AK		 5309 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5310 !txb2b) {
5311 u32 tarc0;
6cf08d1c 5312
e9ec2c0f 5313 tarc0 = er32(TARC(0));
bc7f75fa 5314 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 5315 ew32(TARC(0), tarc0);
bc7f75fa
AK		 5316 }
5317
e921eb1a 5318 /* enable transmits in the hardware, need to do this
ad68076e
BA		 5319 * after setting TARC(0)
5320 */
bc7f75fa
AK		 5321 tctl = er32(TCTL);
5322 tctl |= E1000_TCTL_EN;
5323 ew32(TCTL, tctl);
5324
e921eb1a 5325 /* Perform any post-link-up configuration before
75eb0fad
BA		 5326 * reporting link up.
5327 */
5328 if (phy->ops.cfg_on_link_up)
5329 phy->ops.cfg_on_link_up(hw);
5330
d17ba0f6 5331 netif_wake_queue(netdev);
bc7f75fa 5332 netif_carrier_on(netdev);
bc7f75fa
AK		 5333
5334 if (!test_bit(__E1000_DOWN, &adapter->state))
5335 mod_timer(&adapter->phy_info_timer,
5336 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 5337 }
5338 } else {
5339 if (netif_carrier_ok(netdev)) {
5340 adapter->link_speed = 0;
5341 adapter->link_duplex = 0;
8f12fe86 5342 /* Link status message must follow this format */
c557a4b3 5343 netdev_info(netdev, "NIC Link is Down\n");
bc7f75fa 5344 netif_carrier_off(netdev);
d17ba0f6 5345 netif_stop_queue(netdev);
bc7f75fa
AK		 5346 if (!test_bit(__E1000_DOWN, &adapter->state))
5347 mod_timer(&adapter->phy_info_timer,
5348 round_jiffies(jiffies + 2 * HZ));
5349
d9554e96
DE		 5350 /* 8000ES2LAN requires a Rx packet buffer work-around
5351 * on link down event; reset the controller to flush
5352 * the Rx packet buffer.
12d43f7d 5353 */
caff422e 5354 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
12d43f7d 5355 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 5356 else
5357 pm_schedule_suspend(netdev->dev.parent,
17e813ec 5358 LINK_TIMEOUT);
bc7f75fa
AK		 5359 }
5360 }
5361
5362link_up:
67fd4fcb 5363 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 5364 e1000e_update_stats(adapter);
5365
5366 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5367 adapter->tpt_old = adapter->stats.tpt;
5368 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5369 adapter->colc_old = adapter->stats.colc;
5370
7c25769f
BA		 5371 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5372 adapter->gorc_old = adapter->stats.gorc;
5373 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5374 adapter->gotc_old = adapter->stats.gotc;
2084b114 5375 spin_unlock(&adapter->stats64_lock);
bc7f75fa 5376
caff422e
KK		 5377 /* If the link is lost the controller stops DMA, but
5378 * if there is queued Tx work it cannot be done. So
5379 * reset the controller to flush the Tx packet buffers.
5380 */
5381 if (!netif_carrier_ok(netdev) &&
5382 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5383 adapter->flags |= FLAG_RESTART_NOW;
5384
d9554e96 5385 /* If reset is necessary, do it outside of interrupt context. */
12d43f7d 5386 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 5387 schedule_work(&adapter->reset_task);
5388 /* return immediately since reset is imminent */
5389 return;
bc7f75fa
AK		 5390 }
5391
12d43f7d
BA		 5392 e1000e_update_adaptive(&adapter->hw);
5393
eab2abf5
JB		 5394 /* Simple mode for Interrupt Throttle Rate (ITR) */
5395 if (adapter->itr_setting == 4) {
e921eb1a 5396 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 5397 * Total asymmetrical Tx or Rx gets ITR=8000;
5398 * everyone else is between 2000-8000.
5399 */
5400 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5401 u32 dif = (adapter->gotc > adapter->gorc ?
17e813ec
BA		 5402 adapter->gotc - adapter->gorc :
5403 adapter->gorc - adapter->gotc) / 10000;
eab2abf5
JB		 5404 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5405
22a4cca2 5406 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 5407 }
5408
ad68076e 5409 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 5410 if (adapter->msix_entries)
5411 ew32(ICS, adapter->rx_ring->ims_val);
5412 else
5413 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 5414
713b3c9e
JB		 5415 /* flush pending descriptors to memory before detecting Tx hang */
5416 e1000e_flush_descriptors(adapter);
5417
bc7f75fa 5418 /* Force detection of hung controller every watchdog period */
3db1cd5c 5419 adapter->detect_tx_hung = true;
bc7f75fa 5420
e921eb1a 5421 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 5422 * reset from the other port. Set the appropriate LAA in RAR[0]
5423 */
bc7f75fa 5424 if (e1000e_get_laa_state_82571(hw))
69e1e019 5425 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 5426
ff10e13c
CW		 5427 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5428 e1000e_check_82574_phy_workaround(adapter);
5429
b67e1913
BA		 5430 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5431 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5432 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5433 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5434 er32(RXSTMPH);
5435 adapter->rx_hwtstamp_cleared++;
5436 } else {
5437 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5438 }
5439 }
5440
bc7f75fa
AK		 5441 /* Reset the timer */
5442 if (!test_bit(__E1000_DOWN, &adapter->state))
d5ad7a6a
JK		 5443 mod_timer(&adapter->watchdog_timer,
5444 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 5445}
5446
5447#define E1000_TX_FLAGS_CSUM 0x00000001
5448#define E1000_TX_FLAGS_VLAN 0x00000002
5449#define E1000_TX_FLAGS_TSO 0x00000004
5450#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5451#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5452#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5453#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5454#define E1000_TX_FLAGS_VLAN_SHIFT 16
5455
47ccd1ed
VY		 5456static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5457 __be16 protocol)
bc7f75fa 5458{
bc7f75fa
AK		 5459 struct e1000_context_desc *context_desc;
5460 struct e1000_buffer *buffer_info;
5461 unsigned int i;
5462 u32 cmd_length = 0;
70443ae9 5463 u16 ipcse = 0, mss;
bc7f75fa 5464 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bcf1f57f 5465 int err;
bc7f75fa 5466
3d5e33c9
BA		 5467 if (!skb_is_gso(skb))
5468 return 0;
bc7f75fa 5469
bcf1f57f
FR		 5470 err = skb_cow_head(skb, 0);
5471 if (err < 0)
5472 return err;
bc7f75fa 5473
504148fe 5474 hdr_len = skb_tcp_all_headers(skb);
3d5e33c9 5475 mss = skb_shinfo(skb)->gso_size;
47ccd1ed 5476 if (protocol == htons(ETH_P_IP)) {
3d5e33c9
BA		 5477 struct iphdr *iph = ip_hdr(skb);
5478 iph->tot_len = 0;
5479 iph->check = 0;
5480 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
f0ff4398 5481 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5482 cmd_length = E1000_TXD_CMD_IP;
5483 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5484 } else if (skb_is_gso_v6(skb)) {
2b316fbc 5485 tcp_v6_gso_csum_prep(skb);
3d5e33c9
BA		 5486 ipcse = 0;
5487 }
5488 ipcss = skb_network_offset(skb);
5489 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5490 tucss = skb_transport_offset(skb);
5491 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5492
5493 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
f0ff4398 5494 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
3d5e33c9
BA		 5495
5496 i = tx_ring->next_to_use;
5497 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5498 buffer_info = &tx_ring->buffer_info[i];
5499
e80bd1d1
BA		 5500 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5501 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5502 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
3d5e33c9
BA		 5503 context_desc->upper_setup.tcp_fields.tucss = tucss;
5504 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5505 context_desc->upper_setup.tcp_fields.tucse = 0;
e80bd1d1 5506 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
3d5e33c9
BA		 5507 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5508 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5509
5510 buffer_info->time_stamp = jiffies;
5511 buffer_info->next_to_watch = i;
5512
5513 i++;
5514 if (i == tx_ring->count)
5515 i = 0;
5516 tx_ring->next_to_use = i;
5517
5518 return 1;
bc7f75fa
AK		 5519}
5520
47ccd1ed
VY		 5521static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5522 __be16 protocol)
bc7f75fa 5523{
55aa6985 5524 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5525 struct e1000_context_desc *context_desc;
5526 struct e1000_buffer *buffer_info;
5527 unsigned int i;
5528 u8 css;
af807c82 5529 u32 cmd_len = E1000_TXD_CMD_DEXT;
bc7f75fa 5530
af807c82 5531 if (skb->ip_summed != CHECKSUM_PARTIAL)
3992c8ed 5532 return false;
bc7f75fa 5533
3f518390 5534 switch (protocol) {
09640e63 5535 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5536 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5537 cmd_len |= E1000_TXD_CMD_TCP;
5538 break;
09640e63 5539 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5540 /* XXX not handling all IPV6 headers */
5541 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5542 cmd_len |= E1000_TXD_CMD_TCP;
5543 break;
5544 default:
5545 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5546 e_warn("checksum_partial proto=%x!\n",
5547 be16_to_cpu(protocol));
af807c82 5548 break;
bc7f75fa
AK		 5549 }
5550
0d0b1672 5551 css = skb_checksum_start_offset(skb);
af807c82
DG		 5552
5553 i = tx_ring->next_to_use;
5554 buffer_info = &tx_ring->buffer_info[i];
5555 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5556
5557 context_desc->lower_setup.ip_config = 0;
5558 context_desc->upper_setup.tcp_fields.tucss = css;
f0ff4398 5559 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
af807c82
DG		 5560 context_desc->upper_setup.tcp_fields.tucse = 0;
5561 context_desc->tcp_seg_setup.data = 0;
5562 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5563
5564 buffer_info->time_stamp = jiffies;
5565 buffer_info->next_to_watch = i;
5566
5567 i++;
5568 if (i == tx_ring->count)
5569 i = 0;
5570 tx_ring->next_to_use = i;
5571
3992c8ed 5572 return true;
bc7f75fa
AK		 5573}
5574
55aa6985
BA		 5575static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5576 unsigned int first, unsigned int max_per_txd,
d821a4c4 5577 unsigned int nr_frags)
bc7f75fa 5578{
55aa6985 5579 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5580 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5581 struct e1000_buffer *buffer_info;
8ddc951c 5582 unsigned int len = skb_headlen(skb);
03b1320d 5583 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5584 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5585
5586 i = tx_ring->next_to_use;
5587
5588 while (len) {
1b7719c4 5589 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5590 size = min(len, max_per_txd);
5591
bc7f75fa 5592 buffer_info->length = size;
bc7f75fa 5593 buffer_info->time_stamp = jiffies;
bc7f75fa 5594 buffer_info->next_to_watch = i;
0be3f55f
NN		 5595 buffer_info->dma = dma_map_single(&pdev->dev,
5596 skb->data + offset,
af667a29 5597 size, DMA_TO_DEVICE);
03b1320d 5598 buffer_info->mapped_as_page = false;
0be3f55f 5599 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5600 goto dma_error;
bc7f75fa
AK		 5601
5602 len -= size;
5603 offset += size;
03b1320d 5604 count++;
1b7719c4
AD		 5605
5606 if (len) {
5607 i++;
5608 if (i == tx_ring->count)
5609 i = 0;
5610 }
bc7f75fa
AK		 5611 }
5612
5613 for (f = 0; f < nr_frags; f++) {
d7840976 5614 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
bc7f75fa 5615
9e903e08 5616 len = skb_frag_size(frag);
877749bf 5617 offset = 0;
bc7f75fa
AK		 5618
5619 while (len) {
1b7719c4
AD		 5620 i++;
5621 if (i == tx_ring->count)
5622 i = 0;
5623
bc7f75fa
AK		 5624 buffer_info = &tx_ring->buffer_info[i];
5625 size = min(len, max_per_txd);
bc7f75fa
AK		 5626
5627 buffer_info->length = size;
5628 buffer_info->time_stamp = jiffies;
bc7f75fa 5629 buffer_info->next_to_watch = i;
877749bf 5630 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
17e813ec
BA		 5631 offset, size,
5632 DMA_TO_DEVICE);
03b1320d 5633 buffer_info->mapped_as_page = true;
0be3f55f 5634 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5635 goto dma_error;
bc7f75fa
AK		 5636
5637 len -= size;
5638 offset += size;
5639 count++;
bc7f75fa
AK		 5640 }
5641 }
5642
af667a29 5643 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5644 /* multiply data chunks by size of headers */
5645 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5646
bc7f75fa 5647 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5648 tx_ring->buffer_info[i].segs = segs;
5649 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5650 tx_ring->buffer_info[first].next_to_watch = i;
5651
5652 return count;
03b1320d
AD		 5653
5654dma_error:
af667a29 5655 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5656 buffer_info->dma = 0;
c1fa347f 5657 if (count)
03b1320d 5658 count--;
c1fa347f
RK		 5659
5660 while (count--) {
af667a29 5661 if (i == 0)
03b1320d 5662 i += tx_ring->count;
c1fa347f 5663 i--;
03b1320d 5664 buffer_info = &tx_ring->buffer_info[i];
377b6273 5665 e1000_put_txbuf(tx_ring, buffer_info, true);
03b1320d
AD		 5666 }
5667
5668 return 0;
bc7f75fa
AK		 5669}
5670
55aa6985 5671static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5672{
55aa6985 5673 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5674 struct e1000_tx_desc *tx_desc = NULL;
5675 struct e1000_buffer *buffer_info;
5676 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5677 unsigned int i;
5678
5679 if (tx_flags & E1000_TX_FLAGS_TSO) {
5680 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
f0ff4398 5681 E1000_TXD_CMD_TSE;
bc7f75fa
AK		 5682 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5683
5684 if (tx_flags & E1000_TX_FLAGS_IPV4)
5685 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5686 }
5687
5688 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5689 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5690 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5691 }
5692
5693 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5694 txd_lower |= E1000_TXD_CMD_VLE;
5695 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5696 }
5697
943146de
BG		 5698 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5699 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5700
b67e1913
BA		 5701 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5702 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5703 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5704 }
5705
bc7f75fa
AK		 5706 i = tx_ring->next_to_use;
5707
36b973df 5708 do {
bc7f75fa
AK		 5709 buffer_info = &tx_ring->buffer_info[i];
5710 tx_desc = E1000_TX_DESC(*tx_ring, i);
5711 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
f0ff4398
BA		 5712 tx_desc->lower.data = cpu_to_le32(txd_lower |
5713 buffer_info->length);
bc7f75fa
AK		 5714 tx_desc->upper.data = cpu_to_le32(txd_upper);
5715
5716 i++;
5717 if (i == tx_ring->count)
5718 i = 0;
36b973df 5719 } while (--count > 0);
bc7f75fa
AK		 5720
5721 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5722
943146de
BG		 5723 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5724 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5725 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5726
e921eb1a 5727 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5728 * know there are new descriptors to fetch. (Only
5729 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5730 * such as IA-64).
5731 */
bc7f75fa
AK		 5732 wmb();
5733
5734 tx_ring->next_to_use = i;
bc7f75fa
AK		 5735}
5736
5737#define MINIMUM_DHCP_PACKET_SIZE 282
5738static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5739 struct sk_buff *skb)
5740{
e80bd1d1 5741 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 5742 u16 length, offset;
5743
df8a39de
JP		 5744 if (skb_vlan_tag_present(skb) &&
5745 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
d60923c4
BA		 5746 (adapter->hw.mng_cookie.status &
5747 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5748 return 0;
bc7f75fa
AK		 5749
5750 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5751 return 0;
5752
53aa82da 5753 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
bc7f75fa
AK		 5754 return 0;
5755
5756 {
362e20ca 5757 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
bc7f75fa
AK		 5758 struct udphdr *udp;
5759
5760 if (ip->protocol != IPPROTO_UDP)
5761 return 0;
5762
5763 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5764 if (ntohs(udp->dest) != 67)
5765 return 0;
5766
5767 offset = (u8 *)udp + 8 - skb->data;
5768 length = skb->len - offset;
5769 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5770 }
5771
5772 return 0;
5773}
5774
55aa6985 5775static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5776{
55aa6985 5777 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5778
55aa6985 5779 netif_stop_queue(adapter->netdev);
e921eb1a 5780 /* Herbert's original patch had:
bc7f75fa 5781 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5782 * but since that doesn't exist yet, just open code it.
5783 */
bc7f75fa
AK		 5784 smp_mb();
5785
e921eb1a 5786 /* We need to check again in a case another CPU has just
ad68076e
BA		 5787 * made room available.
5788 */
55aa6985 5789 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5790 return -EBUSY;
5791
5792 /* A reprieve! */
55aa6985 5793 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5794 ++adapter->restart_queue;
5795 return 0;
5796}
5797
55aa6985 5798static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5799{
d821a4c4
BA		 5800 BUG_ON(size > tx_ring->count);
5801
55aa6985 5802 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5803 return 0;
55aa6985 5804 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5805}
5806
3b29a56d
SH		 5807static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5808 struct net_device *netdev)
bc7f75fa
AK		 5809{
5810 struct e1000_adapter *adapter = netdev_priv(netdev);
5811 struct e1000_ring *tx_ring = adapter->tx_ring;
5812 unsigned int first;
bc7f75fa 5813 unsigned int tx_flags = 0;
e743d313 5814 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5815 unsigned int nr_frags;
5816 unsigned int mss;
bc7f75fa
AK		 5817 int count = 0;
5818 int tso;
5819 unsigned int f;
47ccd1ed 5820 __be16 protocol = vlan_get_protocol(skb);
bc7f75fa
AK		 5821
5822 if (test_bit(__E1000_DOWN, &adapter->state)) {
5823 dev_kfree_skb_any(skb);
5824 return NETDEV_TX_OK;
5825 }
5826
5827 if (skb->len <= 0) {
5828 dev_kfree_skb_any(skb);
5829 return NETDEV_TX_OK;
5830 }
5831
e921eb1a 5832 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5833 * pad skb in order to meet this minimum size requirement
5834 */
a94d9e22
AD		 5835 if (skb_put_padto(skb, 17))
5836 return NETDEV_TX_OK;
6e97c170 5837
bc7f75fa 5838 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5839 if (mss) {
5840 u8 hdr_len;
bc7f75fa 5841
e921eb1a 5842 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5843 * points to just header, pull a few bytes of payload from
5844 * frags into skb->data
5845 */
504148fe 5846 hdr_len = skb_tcp_all_headers(skb);
e921eb1a 5847 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5848 * avoiding it could save a lot of cycles
5849 */
4e6c709c 5850 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5851 unsigned int pull_size;
5852
a2a5b323 5853 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5854 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5855 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5856 dev_kfree_skb_any(skb);
5857 return NETDEV_TX_OK;
5858 }
e743d313 5859 len = skb_headlen(skb);
bc7f75fa
AK		 5860 }
5861 }
5862
5863 /* reserve a descriptor for the offload context */
5864 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5865 count++;
5866 count++;
5867
d821a4c4 5868 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5869
5870 nr_frags = skb_shinfo(skb)->nr_frags;
5871 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5872 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5873 adapter->tx_fifo_limit);
bc7f75fa
AK		 5874
5875 if (adapter->hw.mac.tx_pkt_filtering)
5876 e1000_transfer_dhcp_info(adapter, skb);
5877
e921eb1a 5878 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5879 * head, otherwise try next time
5880 */
55aa6985 5881 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5882 return NETDEV_TX_BUSY;
bc7f75fa 5883
df8a39de 5884 if (skb_vlan_tag_present(skb)) {
bc7f75fa 5885 tx_flags |= E1000_TX_FLAGS_VLAN;
df8a39de
JP		 5886 tx_flags |= (skb_vlan_tag_get(skb) <<
5887 E1000_TX_FLAGS_VLAN_SHIFT);
bc7f75fa
AK		 5888 }
5889
5890 first = tx_ring->next_to_use;
5891
47ccd1ed 5892 tso = e1000_tso(tx_ring, skb, protocol);
bc7f75fa
AK		 5893 if (tso < 0) {
5894 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5895 return NETDEV_TX_OK;
5896 }
5897
5898 if (tso)
5899 tx_flags |= E1000_TX_FLAGS_TSO;
47ccd1ed 5900 else if (e1000_tx_csum(tx_ring, skb, protocol))
bc7f75fa
AK		 5901 tx_flags |= E1000_TX_FLAGS_CSUM;
5902
e921eb1a 5903 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5904 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5905 * no longer assume, we must.
5906 */
47ccd1ed 5907 if (protocol == htons(ETH_P_IP))
bc7f75fa
AK		 5908 tx_flags |= E1000_TX_FLAGS_IPV4;
5909
943146de
BG		 5910 if (unlikely(skb->no_fcs))
5911 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5912
25985edc 5913 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5914 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5915 nr_frags);
1b7719c4 5916 if (count) {
6930895d 5917 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
cff57141
JK		 5918 (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) {
5919 if (!adapter->tx_hwtstamp_skb) {
5920 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5921 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5922 adapter->tx_hwtstamp_skb = skb_get(skb);
5923 adapter->tx_hwtstamp_start = jiffies;
5924 schedule_work(&adapter->tx_hwtstamp_work);
5925 } else {
5926 adapter->tx_hwtstamp_skipped++;
5927 }
b67e1913 5928 }
80be3129 5929
74abc9b1
ML		 5930 skb_tx_timestamp(skb);
5931
3f0cfa3b 5932 netdev_sent_queue(netdev, skb->len);
55aa6985 5933 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5934 /* Make sure there is space in the ring for the next send. */
d821a4c4 5935 e1000_maybe_stop_tx(tx_ring,
eed913f6 5936 ((MAX_SKB_FRAGS + 1) *
d821a4c4 5937 DIV_ROUND_UP(PAGE_SIZE,
eed913f6 5938 adapter->tx_fifo_limit) + 4));
472f31f5 5939
6b16f9ee 5940 if (!netdev_xmit_more() ||
472f31f5
FW		 5941 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5942 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5943 e1000e_update_tdt_wa(tx_ring,
5944 tx_ring->next_to_use);
5945 else
5946 writel(tx_ring->next_to_use, tx_ring->tail);
472f31f5 5947 }
1b7719c4 5948 } else {
bc7f75fa 5949 dev_kfree_skb_any(skb);
1b7719c4
AD		 5950 tx_ring->buffer_info[first].time_stamp = 0;
5951 tx_ring->next_to_use = first;
bc7f75fa
AK		 5952 }
5953
bc7f75fa
AK		 5954 return NETDEV_TX_OK;
5955}
5956
5957/**
5958 * e1000_tx_timeout - Respond to a Tx Hang
5959 * @netdev: network interface device structure
b50f7bca 5960 * @txqueue: index of the hung queue (unused)
bc7f75fa 5961 **/
b50f7bca 5962static void e1000_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
bc7f75fa
AK		 5963{
5964 struct e1000_adapter *adapter = netdev_priv(netdev);
5965
5966 /* Do the reset outside of interrupt context */
5967 adapter->tx_timeout_count++;
5968 schedule_work(&adapter->reset_task);
5969}
5970
5971static void e1000_reset_task(struct work_struct *work)
5972{
5973 struct e1000_adapter *adapter;
5974 adapter = container_of(work, struct e1000_adapter, reset_task);
5975
21f857f0 5976 rtnl_lock();
615b32af 5977 /* don't run the task if already down */
21f857f0
VL		 5978 if (test_bit(__E1000_DOWN, &adapter->state)) {
5979 rtnl_unlock();
615b32af 5980 return;
21f857f0 5981 }
615b32af 5982
12d43f7d 5983 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5984 e1000e_dump(adapter);
12d43f7d 5985 e_err("Reset adapter unexpectedly\n");
affa9dfb 5986 }
bc7f75fa 5987 e1000e_reinit_locked(adapter);
21f857f0 5988 rtnl_unlock();
bc7f75fa
AK		 5989}
5990
5991/**
39da2cac 5992 * e1000e_get_stats64 - Get System Network Statistics
bc7f75fa 5993 * @netdev: network interface device structure
67fd4fcb 5994 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5995 *
5996 * Returns the address of the device statistics structure.
bc7f75fa 5997 **/
bc1f4470 5998void e1000e_get_stats64(struct net_device *netdev,
5999 struct rtnl_link_stats64 *stats)
bc7f75fa 6000{
67fd4fcb
JK		 6001 struct e1000_adapter *adapter = netdev_priv(netdev);
6002
67fd4fcb
JK		 6003 spin_lock(&adapter->stats64_lock);
6004 e1000e_update_stats(adapter);
6005 /* Fill out the OS statistics structure */
6006 stats->rx_bytes = adapter->stats.gorc;
6007 stats->rx_packets = adapter->stats.gprc;
6008 stats->tx_bytes = adapter->stats.gotc;
6009 stats->tx_packets = adapter->stats.gptc;
6010 stats->multicast = adapter->stats.mprc;
6011 stats->collisions = adapter->stats.colc;
6012
6013 /* Rx Errors */
6014
e921eb1a 6015 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 6016 * our own version based on RUC and ROC
6017 */
6018 stats->rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 6019 adapter->stats.crcerrs + adapter->stats.algnerrc +
6020 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
6021 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
67fd4fcb
JK		 6022 stats->rx_crc_errors = adapter->stats.crcerrs;
6023 stats->rx_frame_errors = adapter->stats.algnerrc;
6024 stats->rx_missed_errors = adapter->stats.mpc;
6025
6026 /* Tx Errors */
f0ff4398 6027 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
67fd4fcb
JK		 6028 stats->tx_aborted_errors = adapter->stats.ecol;
6029 stats->tx_window_errors = adapter->stats.latecol;
6030 stats->tx_carrier_errors = adapter->stats.tncrs;
6031
6032 /* Tx Dropped needs to be maintained elsewhere */
6033
6034 spin_unlock(&adapter->stats64_lock);
bc7f75fa
AK		 6035}
6036
6037/**
6038 * e1000_change_mtu - Change the Maximum Transfer Unit
6039 * @netdev: network interface device structure
6040 * @new_mtu: new value for maximum frame size
6041 *
6042 * Returns 0 on success, negative on failure
6043 **/
6044static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
6045{
6046 struct e1000_adapter *adapter = netdev_priv(netdev);
8084b86d 6047 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
bc7f75fa 6048
2adc55c9 6049 /* Jumbo frame support */
91c527a5 6050 if ((new_mtu > ETH_DATA_LEN) &&
2e1706f2
BA		 6051 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
6052 e_err("Jumbo Frames not supported.\n");
6053 return -EINVAL;
bc7f75fa
AK		 6054 }
6055
2fbe4526
BA		 6056 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6057 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 6058 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
6059 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 6060 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 6061 return -EINVAL;
6062 }
6063
bc7f75fa 6064 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
ab6973ae 6065 usleep_range(1000, 1100);
610c9928 6066 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 6067 adapter->max_frame_size = max_frame;
12299132
FF		 6068 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6069 netdev->mtu, new_mtu);
1eb2cded 6070 WRITE_ONCE(netdev->mtu, new_mtu);
63eb48f1
DE		 6071
6072 pm_runtime_get_sync(netdev->dev.parent);
6073
bc7f75fa 6074 if (netif_running(netdev))
28002099 6075 e1000e_down(adapter, true);
bc7f75fa 6076
e921eb1a 6077 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 6078 * means we reserve 2 more, this pushes us to allocate from the next
6079 * larger slab size.
ad68076e 6080 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 6081 * However with the new *_jumbo_rx* routines, jumbo receives will use
6082 * fragmented skbs
ad68076e 6083 */
bc7f75fa 6084
9926146b 6085 if (max_frame <= 2048)
bc7f75fa
AK		 6086 adapter->rx_buffer_len = 2048;
6087 else
6088 adapter->rx_buffer_len = 4096;
6089
6090 /* adjust allocation if LPE protects us, and we aren't using SBP */
8084b86d
AD		 6091 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6092 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
bc7f75fa 6093
bc7f75fa
AK		 6094 if (netif_running(netdev))
6095 e1000e_up(adapter);
6096 else
6097 e1000e_reset(adapter);
6098
63eb48f1
DE		 6099 pm_runtime_put_sync(netdev->dev.parent);
6100
bc7f75fa
AK		 6101 clear_bit(__E1000_RESETTING, &adapter->state);
6102
6103 return 0;
6104}
6105
39aa687a 6106static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
bc7f75fa
AK		 6107{
6108 struct e1000_adapter *adapter = netdev_priv(netdev);
6109 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 6110
318a94d6 6111 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 6112 return -EOPNOTSUPP;
6113
6114 switch (cmd) {
6115 case SIOCGMIIPHY:
6116 data->phy_id = adapter->hw.phy.addr;
6117 break;
6118 case SIOCGMIIREG:
b16a002e
BA		 6119 e1000_phy_read_status(adapter);
6120
7c25769f
BA		 6121 switch (data->reg_num & 0x1F) {
6122 case MII_BMCR:
6123 data->val_out = adapter->phy_regs.bmcr;
6124 break;
6125 case MII_BMSR:
6126 data->val_out = adapter->phy_regs.bmsr;
6127 break;
6128 case MII_PHYSID1:
6129 data->val_out = (adapter->hw.phy.id >> 16);
6130 break;
6131 case MII_PHYSID2:
6132 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6133 break;
6134 case MII_ADVERTISE:
6135 data->val_out = adapter->phy_regs.advertise;
6136 break;
6137 case MII_LPA:
6138 data->val_out = adapter->phy_regs.lpa;
6139 break;
6140 case MII_EXPANSION:
6141 data->val_out = adapter->phy_regs.expansion;
6142 break;
6143 case MII_CTRL1000:
6144 data->val_out = adapter->phy_regs.ctrl1000;
6145 break;
6146 case MII_STAT1000:
6147 data->val_out = adapter->phy_regs.stat1000;
6148 break;
6149 case MII_ESTATUS:
6150 data->val_out = adapter->phy_regs.estatus;
6151 break;
6152 default:
bc7f75fa
AK		 6153 return -EIO;
6154 }
bc7f75fa
AK		 6155 break;
6156 case SIOCSMIIREG:
6157 default:
6158 return -EOPNOTSUPP;
6159 }
6160 return 0;
6161}
6162
b67e1913 6163/**
39da2cac 6164 * e1000e_hwtstamp_set - control hardware time stamping
b67e1913 6165 * @netdev: network interface device structure
39aa687a
PW		 6166 * @config: timestamp configuration
6167 * @extack: netlink extended ACK report
b67e1913
BA		 6168 *
6169 * Outgoing time stamping can be enabled and disabled. Play nice and
6170 * disable it when requested, although it shouldn't cause any overhead
6171 * when no packet needs it. At most one packet in the queue may be
6172 * marked for time stamping, otherwise it would be impossible to tell
6173 * for sure to which packet the hardware time stamp belongs.
6174 *
6175 * Incoming time stamping has to be configured via the hardware filters.
6176 * Not all combinations are supported, in particular event type has to be
6177 * specified. Matching the kind of event packet is not supported, with the
6178 * exception of "all V2 events regardless of level 2 or 4".
6179 **/
39aa687a
PW		 6180static int e1000e_hwtstamp_set(struct net_device *netdev,
6181 struct kernel_hwtstamp_config *config,
6182 struct netlink_ext_ack *extack)
b67e1913
BA		 6183{
6184 struct e1000_adapter *adapter = netdev_priv(netdev);
b67e1913
BA		 6185 int ret_val;
6186
39aa687a 6187 ret_val = e1000e_config_hwtstamp(adapter, config, extack);
b67e1913
BA		 6188 if (ret_val)
6189 return ret_val;
6190
39aa687a 6191 switch (config->rx_filter) {
d89777bf
BA		 6192 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6193 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6194 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6195 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6196 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6197 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6198 /* With V2 type filters which specify a Sync or Delay Request,
6199 * Path Delay Request/Response messages are also time stamped
6200 * by hardware so notify the caller the requested packets plus
6201 * some others are time stamped.
6202 */
39aa687a 6203 config->rx_filter = HWTSTAMP_FILTER_SOME;
d89777bf
BA		 6204 break;
6205 default:
6206 break;
6207 }
6208
39aa687a 6209 return 0;
b67e1913
BA		 6210}
6211
39aa687a
PW		 6212static int e1000e_hwtstamp_get(struct net_device *netdev,
6213 struct kernel_hwtstamp_config *kernel_config)
4e8cff64
BH		 6214{
6215 struct e1000_adapter *adapter = netdev_priv(netdev);
6216
39aa687a 6217 *kernel_config = adapter->hwtstamp_config;
4e8cff64 6218
39aa687a 6219 return 0;
bc7f75fa
AK		 6220}
6221
a4f58f54
BA		 6222static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6223{
6224 struct e1000_hw *hw = &adapter->hw;
74f350ee 6225 u32 i, mac_reg, wuc;
2b6b168d 6226 u16 phy_reg, wuc_enable;
70806a7f 6227 int retval;
a4f58f54
BA		 6228
6229 /* copy MAC RARs to PHY RARs */
d3738bb8 6230 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 6231
2b6b168d
BA		 6232 retval = hw->phy.ops.acquire(hw);
6233 if (retval) {
6234 e_err("Could not acquire PHY\n");
6235 return retval;
6236 }
6237
6238 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6239 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6240 if (retval)
75ce1532 6241 goto release;
2b6b168d
BA		 6242
6243 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 6244 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6245 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 6246 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6247 (u16)(mac_reg & 0xFFFF));
6248 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6249 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 6250 }
6251
6252 /* configure PHY Rx Control register */
2b6b168d 6253 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 6254 mac_reg = er32(RCTL);
6255 if (mac_reg & E1000_RCTL_UPE)
6256 phy_reg |= BM_RCTL_UPE;
6257 if (mac_reg & E1000_RCTL_MPE)
6258 phy_reg |= BM_RCTL_MPE;
6259 phy_reg &= ~(BM_RCTL_MO_MASK);
6260 if (mac_reg & E1000_RCTL_MO_3)
b9a45254 6261 phy_reg |= (FIELD_GET(E1000_RCTL_MO_3, mac_reg)
17e813ec 6262 << BM_RCTL_MO_SHIFT);
a4f58f54
BA		 6263 if (mac_reg & E1000_RCTL_BAM)
6264 phy_reg |= BM_RCTL_BAM;
6265 if (mac_reg & E1000_RCTL_PMCF)
6266 phy_reg |= BM_RCTL_PMCF;
6267 mac_reg = er32(CTRL);
6268 if (mac_reg & E1000_CTRL_RFCE)
6269 phy_reg |= BM_RCTL_RFCE;
2b6b168d 6270 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54 6271
74f350ee
DE		 6272 wuc = E1000_WUC_PME_EN;
6273 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6274 wuc |= E1000_WUC_APME;
6275
a4f58f54
BA		 6276 /* enable PHY wakeup in MAC register */
6277 ew32(WUFC, wufc);
74f350ee
DE		 6278 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6279 E1000_WUC_PME_STATUS | wuc));
a4f58f54
BA		 6280
6281 /* configure and enable PHY wakeup in PHY registers */
2b6b168d 6282 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
74f350ee 6283 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
a4f58f54
BA		 6284
6285 /* activate PHY wakeup */
2b6b168d
BA		 6286 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6287 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 6288 if (retval)
6289 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 6290release:
94d8186a 6291 hw->phy.ops.release(hw);
a4f58f54
BA		 6292
6293 return retval;
6294}
6295
2a7e19af
DE		 6296static void e1000e_flush_lpic(struct pci_dev *pdev)
6297{
6298 struct net_device *netdev = pci_get_drvdata(pdev);
6299 struct e1000_adapter *adapter = netdev_priv(netdev);
6300 struct e1000_hw *hw = &adapter->hw;
6301 u32 ret_val;
6302
6303 pm_runtime_get_sync(netdev->dev.parent);
6304
6305 ret_val = hw->phy.ops.acquire(hw);
6306 if (ret_val)
6307 goto fl_out;
6308
6309 pr_info("EEE TX LPI TIMER: %08X\n",
6310 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6311
6312 hw->phy.ops.release(hw);
6313
6314fl_out:
6315 pm_runtime_put_sync(netdev->dev.parent);
6316}
6317
f15bb6dd
SN		 6318/* S0ix implementation */
6319static void e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)
6320{
6321 struct e1000_hw *hw = &adapter->hw;
6322 u32 mac_data;
6323 u16 phy_data;
6324
cad014b7
SN		 6325 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6326 hw->mac.type >= e1000_pch_adp) {
3e55d231
SN		 6327 /* Request ME configure the device for S0ix */
6328 mac_data = er32(H2ME);
6329 mac_data |= E1000_H2ME_START_DPG;
6330 mac_data &= ~E1000_H2ME_EXIT_DPG;
7bab8828 6331 trace_e1000e_trace_mac_register(mac_data);
3e55d231
SN		 6332 ew32(H2ME, mac_data);
6333 } else {
6334 /* Request driver configure the device to S0ix */
6335 /* Disable the periodic inband message,
6336 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6337 */
6338 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6339 phy_data &= ~HV_PM_CTRL_K1_CLK_REQ;
6340 phy_data |= BIT(10);
6341 e1e_wphy(hw, HV_PM_CTRL, phy_data);
f15bb6dd 6342
3e55d231
SN		 6343 /* Make sure we don't exit K1 every time a new packet arrives
6344 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6345 */
6346 e1e_rphy(hw, I217_CGFREG, &phy_data);
6347 phy_data |= BIT(5);
6348 e1e_wphy(hw, I217_CGFREG, phy_data);
f15bb6dd 6349
3e55d231
SN		 6350 /* Change the MAC/PHY interface to SMBus
6351 * Force the SMBus in PHY page769_23[0] = 1
6352 * Force the SMBus in MAC CTRL_EXT[11] = 1
6353 */
6354 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6355 phy_data |= CV_SMB_CTRL_FORCE_SMBUS;
6356 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6357 mac_data = er32(CTRL_EXT);
6358 mac_data |= E1000_CTRL_EXT_FORCE_SMBUS;
6359 ew32(CTRL_EXT, mac_data);
6360
6361 /* DFT control: PHY bit: page769_20[0] = 1
3ad3e28c
SN		 6362 * page769_20[7] - PHY PLL stop
6363 * page769_20[8] - PHY go to the electrical idle
6364 * page769_20[9] - PHY serdes disable
3e55d231
SN		 6365 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6366 */
6367 e1e_rphy(hw, I82579_DFT_CTRL, &phy_data);
6368 phy_data |= BIT(0);
3ad3e28c
SN		 6369 phy_data |= BIT(7);
6370 phy_data |= BIT(8);
6371 phy_data |= BIT(9);
3e55d231
SN		 6372 e1e_wphy(hw, I82579_DFT_CTRL, phy_data);
6373
6374 mac_data = er32(EXTCNF_CTRL);
6375 mac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
6376 ew32(EXTCNF_CTRL, mac_data);
6377
3e55d231
SN		 6378 /* Disable disconnected cable conditioning for Power Gating */
6379 mac_data = er32(DPGFR);
6380 mac_data |= BIT(2);
6381 ew32(DPGFR, mac_data);
6382
3e55d231
SN		 6383 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6384 mac_data = er32(CTRL_EXT);
6385 mac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;
6386 ew32(CTRL_EXT, mac_data);
3e55d231 6387 }
f15bb6dd 6388
c93a6f62
DR		 6389 /* Enable the Dynamic Power Gating in the MAC */
6390 mac_data = er32(FEXTNVM7);
6391 mac_data |= BIT(22);
6392 ew32(FEXTNVM7, mac_data);
6393
6394 /* Don't wake from dynamic Power Gating with clock request */
6395 mac_data = er32(FEXTNVM12);
6396 mac_data |= BIT(12);
6397 ew32(FEXTNVM12, mac_data);
6398
6399 /* Ungate PGCB clock */
6400 mac_data = er32(FEXTNVM9);
6401 mac_data &= ~BIT(28);
6402 ew32(FEXTNVM9, mac_data);
6403
6404 /* Enable K1 off to enable mPHY Power Gating */
6405 mac_data = er32(FEXTNVM6);
6406 mac_data |= BIT(31);
6407 ew32(FEXTNVM6, mac_data);
6408
6409 /* Enable mPHY power gating for any link and speed */
6410 mac_data = er32(FEXTNVM8);
6411 mac_data |= BIT(9);
6412 ew32(FEXTNVM8, mac_data);
6413
6414 /* No MAC DPG gating SLP_S0 in modern standby
6415 * Switch the logic of the lanphypc to use PMC counter
6416 */
6417 mac_data = er32(FEXTNVM5);
6418 mac_data |= BIT(7);
6419 ew32(FEXTNVM5, mac_data);
6420
3e55d231
SN		 6421 /* Disable the time synchronization clock */
6422 mac_data = er32(FEXTNVM7);
6423 mac_data |= BIT(31);
6424 mac_data &= ~BIT(0);
6425 ew32(FEXTNVM7, mac_data);
f15bb6dd 6426
3e55d231
SN		 6427 /* Dynamic Power Gating Enable */
6428 mac_data = er32(CTRL_EXT);
6429 mac_data |= BIT(3);
6430 ew32(CTRL_EXT, mac_data);
f15bb6dd
SN		 6431
6432 /* Check MAC Tx/Rx packet buffer pointers.
6433 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6434 * pending traffic indication that would prevent power gating.
6435 */
6436 mac_data = er32(TDFH);
6437 if (mac_data)
6438 ew32(TDFH, 0);
6439 mac_data = er32(TDFT);
6440 if (mac_data)
6441 ew32(TDFT, 0);
6442 mac_data = er32(TDFHS);
6443 if (mac_data)
6444 ew32(TDFHS, 0);
6445 mac_data = er32(TDFTS);
6446 if (mac_data)
6447 ew32(TDFTS, 0);
6448 mac_data = er32(TDFPC);
6449 if (mac_data)
6450 ew32(TDFPC, 0);
6451 mac_data = er32(RDFH);
6452 if (mac_data)
6453 ew32(RDFH, 0);
6454 mac_data = er32(RDFT);
6455 if (mac_data)
6456 ew32(RDFT, 0);
6457 mac_data = er32(RDFHS);
6458 if (mac_data)
6459 ew32(RDFHS, 0);
6460 mac_data = er32(RDFTS);
6461 if (mac_data)
6462 ew32(RDFTS, 0);
6463 mac_data = er32(RDFPC);
6464 if (mac_data)
6465 ew32(RDFPC, 0);
f15bb6dd
SN		 6466}
6467
6468static void e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)
6469{
6470 struct e1000_hw *hw = &adapter->hw;
ef407b86 6471 bool firmware_bug = false;
f15bb6dd
SN		 6472 u32 mac_data;
6473 u16 phy_data;
ef407b86 6474 u32 i = 0;
f15bb6dd 6475
cad014b7
SN		 6476 if (er32(FWSM) & E1000_ICH_FWSM_FW_VALID &&
6477 hw->mac.type >= e1000_pch_adp) {
b49feacb
SN		 6478 /* Keep the GPT clock enabled for CSME */
6479 mac_data = er32(FEXTNVM);
6480 mac_data |= BIT(3);
6481 ew32(FEXTNVM, mac_data);
3e55d231
SN		 6482 /* Request ME unconfigure the device from S0ix */
6483 mac_data = er32(H2ME);
6484 mac_data &= ~E1000_H2ME_START_DPG;
6485 mac_data |= E1000_H2ME_EXIT_DPG;
7bab8828 6486 trace_e1000e_trace_mac_register(mac_data);
3e55d231 6487 ew32(H2ME, mac_data);
ef407b86
SN		 6488
6489 /* Poll up to 2.5 seconds for ME to unconfigure DPG.
6490 * If this takes more than 1 second, show a warning indicating a
6491 * firmware bug
6492 */
6493 while (!(er32(EXFWSM) & E1000_EXFWSM_DPG_EXIT_DONE)) {
6494 if (i > 100 && !firmware_bug)
6495 firmware_bug = true;
6496
6497 if (i++ == 250) {
6498 e_dbg("Timeout (firmware bug): %d msec\n",
6499 i * 10);
6500 break;
6501 }
6502
6503 usleep_range(10000, 11000);
6504 }
6505 if (firmware_bug)
6506 e_warn("DPG_EXIT_DONE took %d msec. This is a firmware bug\n",
6507 i * 10);
6508 else
6509 e_dbg("DPG_EXIT_DONE cleared after %d msec\n", i * 10);
3e55d231
SN		 6510 } else {
6511 /* Request driver unconfigure the device from S0ix */
6512
3e55d231
SN		 6513 /* Cancel disable disconnected cable conditioning
6514 * for Power Gating
6515 */
6516 mac_data = er32(DPGFR);
6517 mac_data &= ~BIT(2);
6518 ew32(DPGFR, mac_data);
f15bb6dd 6519
3e55d231
SN		 6520 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6521 mac_data = er32(CTRL_EXT);
6522 mac_data &= 0xFFF7FFFF;
6523 ew32(CTRL_EXT, mac_data);
632fbd5e 6524
3e55d231
SN		 6525 /* Enable the periodic inband message,
6526 * Request PCIe clock in K1 page770_17[10:9] =01b
6527 */
6528 e1e_rphy(hw, HV_PM_CTRL, &phy_data);
6529 phy_data &= 0xFBFF;
6530 phy_data |= HV_PM_CTRL_K1_CLK_REQ;
6531 e1e_wphy(hw, HV_PM_CTRL, phy_data);
632fbd5e 6532
3e55d231
SN		 6533 /* Return back configuration
6534 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6535 */
6536 e1e_rphy(hw, I217_CGFREG, &phy_data);
6537 phy_data &= 0xFFDF;
6538 e1e_wphy(hw, I217_CGFREG, phy_data);
632fbd5e 6539
3e55d231
SN		 6540 /* Change the MAC/PHY interface to Kumeran
6541 * Unforce the SMBus in PHY page769_23[0] = 0
6542 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6543 */
6544 e1e_rphy(hw, CV_SMB_CTRL, &phy_data);
6545 phy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;
6546 e1e_wphy(hw, CV_SMB_CTRL, phy_data);
6547 mac_data = er32(CTRL_EXT);
6548 mac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;
6549 ew32(CTRL_EXT, mac_data);
6550 }
632fbd5e 6551
f15bb6dd
SN		 6552 /* Disable Dynamic Power Gating */
6553 mac_data = er32(CTRL_EXT);
6554 mac_data &= 0xFFFFFFF7;
6555 ew32(CTRL_EXT, mac_data);
6556
3e55d231
SN		 6557 /* Enable the time synchronization clock */
6558 mac_data = er32(FEXTNVM7);
6559 mac_data &= ~BIT(31);
6560 mac_data |= BIT(0);
6561 ew32(FEXTNVM7, mac_data);
c93a6f62
DR		 6562
6563 /* Disable the Dynamic Power Gating in the MAC */
6564 mac_data = er32(FEXTNVM7);
6565 mac_data &= 0xFFBFFFFF;
6566 ew32(FEXTNVM7, mac_data);
6567
6568 /* Disable mPHY power gating for any link and speed */
6569 mac_data = er32(FEXTNVM8);
6570 mac_data &= ~BIT(9);
6571 ew32(FEXTNVM8, mac_data);
6572
6573 /* Disable K1 off */
6574 mac_data = er32(FEXTNVM6);
6575 mac_data &= ~BIT(31);
6576 ew32(FEXTNVM6, mac_data);
6577
6578 /* Disable Ungate PGCB clock */
6579 mac_data = er32(FEXTNVM9);
6580 mac_data |= BIT(28);
6581 ew32(FEXTNVM9, mac_data);
6582
6583 /* Cancel not waking from dynamic
6584 * Power Gating with clock request
6585 */
6586 mac_data = er32(FEXTNVM12);
6587 mac_data &= ~BIT(12);
6588 ew32(FEXTNVM12, mac_data);
6589
6590 /* Revert the lanphypc logic to use the internal Gbe counter
6591 * and not the PMC counter
6592 */
6593 mac_data = er32(FEXTNVM5);
6594 mac_data &= 0xFFFFFF7F;
6595 ew32(FEXTNVM5, mac_data);
f15bb6dd
SN		 6596}
6597
28002099 6598static int e1000e_pm_freeze(struct device *dev)
bc7f75fa 6599{
ee2e80c1 6600 struct net_device *netdev = dev_get_drvdata(dev);
bc7f75fa 6601 struct e1000_adapter *adapter = netdev_priv(netdev);
a7023819 6602 bool present;
bc7f75fa 6603
a7023819
AD		 6604 rtnl_lock();
6605
6606 present = netif_device_present(netdev);
bc7f75fa
AK		 6607 netif_device_detach(netdev);
6608
a7023819 6609 if (present && netif_running(netdev)) {
bb9e44d0
BA		 6610 int count = E1000_CHECK_RESET_COUNT;
6611
6612 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
ab6973ae 6613 usleep_range(10000, 11000);
bb9e44d0 6614
bc7f75fa 6615 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
28002099
DE		 6616
6617 /* Quiesce the device without resetting the hardware */
6618 e1000e_down(adapter, false);
bc7f75fa
AK		 6619 e1000_free_irq(adapter);
6620 }
a7023819
AD		 6621 rtnl_unlock();
6622
9f47a48e 6623 e1000e_reset_interrupt_capability(adapter);
bc7f75fa 6624
28002099
DE		 6625 /* Allow time for pending master requests to run */
6626 e1000e_disable_pcie_master(&adapter->hw);
6627
6628 return 0;
6629}
6630
6631static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6632{
6633 struct net_device *netdev = pci_get_drvdata(pdev);
6634 struct e1000_adapter *adapter = netdev_priv(netdev);
6635 struct e1000_hw *hw = &adapter->hw;
6bf6be11 6636 u32 ctrl, ctrl_ext, rctl, status, wufc;
28002099
DE		 6637 int retval = 0;
6638
6bf6be11
CY		 6639 /* Runtime suspend should only enable wakeup for link changes */
6640 if (runtime)
6641 wufc = E1000_WUFC_LNKC;
6642 else if (device_may_wakeup(&pdev->dev))
6643 wufc = adapter->wol;
6644 else
6645 wufc = 0;
6646
bc7f75fa
AK		 6647 status = er32(STATUS);
6648 if (status & E1000_STATUS_LU)
6649 wufc &= ~E1000_WUFC_LNKC;
6650
6651 if (wufc) {
6652 e1000_setup_rctl(adapter);
ef9b965a 6653 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 6654
6655 /* turn on all-multi mode if wake on multicast is enabled */
6656 if (wufc & E1000_WUFC_MC) {
6657 rctl = er32(RCTL);
6658 rctl |= E1000_RCTL_MPE;
6659 ew32(RCTL, rctl);
6660 }
6661
6662 ctrl = er32(CTRL);
a4f58f54
BA		 6663 ctrl |= E1000_CTRL_ADVD3WUC;
6664 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6665 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 6666 ew32(CTRL, ctrl);
6667
318a94d6
JK		 6668 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6669 adapter->hw.phy.media_type ==
6670 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 6671 /* keep the laser running in D3 */
6672 ctrl_ext = er32(CTRL_EXT);
93a23f48 6673 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 6674 ew32(CTRL_EXT, ctrl_ext);
6675 }
6676
63eb48f1
DE		 6677 if (!runtime)
6678 e1000e_power_up_phy(adapter);
6679
97ac8cae 6680 if (adapter->flags & FLAG_IS_ICH)
99730e4c 6681 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 6682
82776a4b 6683 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 6684 /* enable wakeup by the PHY */
6685 retval = e1000_init_phy_wakeup(adapter, wufc);
0a6ad4d9
VL		 6686 if (retval) {
6687 e_err("Failed to enable wakeup\n");
6688 goto skip_phy_configurations;
6689 }
a4f58f54
BA		 6690 } else {
6691 /* enable wakeup by the MAC */
6692 ew32(WUFC, wufc);
6693 ew32(WUC, E1000_WUC_PME_EN);
6694 }
bc7f75fa
AK		 6695 } else {
6696 ew32(WUC, 0);
6697 ew32(WUFC, 0);
28002099
DE		 6698
6699 e1000_power_down_phy(adapter);
bc7f75fa
AK		 6700 }
6701
74f350ee 6702 if (adapter->hw.phy.type == e1000_phy_igp_3) {
bc7f75fa 6703 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
c8744f44 6704 } else if (hw->mac.type >= e1000_pch_lpt) {
662200e3 6705 if (wufc && !(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) {
74f350ee
DE		 6706 /* ULP does not support wake from unicast, multicast
6707 * or broadcast.
6708 */
6709 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
0a6ad4d9
VL		 6710 if (retval) {
6711 e_err("Failed to enable ULP\n");
6712 goto skip_phy_configurations;
6713 }
662200e3 6714 }
74f350ee
DE		 6715 }
6716
f5ac7445
RA		 6717 /* Ensure that the appropriate bits are set in LPI_CTRL
6718 * for EEE in Sx
6719 */
6720 if ((hw->phy.type >= e1000_phy_i217) &&
6721 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6722 u16 lpi_ctrl = 0;
6723
6724 retval = hw->phy.ops.acquire(hw);
6725 if (!retval) {
6726 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6727 &lpi_ctrl);
6728 if (!retval) {
6729 if (adapter->eee_advert &
6730 hw->dev_spec.ich8lan.eee_lp_ability &
6731 I82579_EEE_100_SUPPORTED)
6732 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6733 if (adapter->eee_advert &
6734 hw->dev_spec.ich8lan.eee_lp_ability &
6735 I82579_EEE_1000_SUPPORTED)
6736 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6737
6738 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6739 lpi_ctrl);
6740 }
6741 }
6742 hw->phy.ops.release(hw);
6743 }
bc7f75fa 6744
0a6ad4d9 6745skip_phy_configurations:
e921eb1a 6746 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6747 * would have already happened in close and is redundant.
6748 */
31dbe5b4 6749 e1000e_release_hw_control(adapter);
bc7f75fa 6750
24b41c97
DN		 6751 pci_clear_master(pdev);
6752
e921eb1a 6753 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 6754 * correctable error when the MAC transitions from D0 to D3. To
6755 * prevent this we need to mask off the correctable errors on the
6756 * downstream port of the pci-e switch.
e8c254c5
LZ		 6757 *
6758 * We don't have the associated upstream bridge while assigning
6759 * the PCI device into guest. For example, the KVM on power is
6760 * one of the cases.
005cbdfc
AD		 6761 */
6762 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6763 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 6764 u16 devctl;
6765
e8c254c5
LZ		 6766 if (!us_dev)
6767 return 0;
6768
f8c0fcac
JL		 6769 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6770 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6771 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6772
66148bab
KK		 6773 pci_save_state(pdev);
6774 pci_prepare_to_sleep(pdev);
005cbdfc 6775
f8c0fcac 6776 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6777 }
66148bab
KK		 6778
6779 return 0;
bc7f75fa
AK		 6780}
6781
13129d9b 6782/**
beb0a152 6783 * __e1000e_disable_aspm - Disable ASPM states
13129d9b
CW		 6784 * @pdev: pointer to PCI device struct
6785 * @state: bit-mask of ASPM states to disable
beb0a152 6786 * @locked: indication if this context holds pci_bus_sem locked.
13129d9b
CW		 6787 *
6788 * Some devices *must* have certain ASPM states disabled per hardware errata.
6789 **/
beb0a152 6790static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6f461f6c 6791{
13129d9b
CW		 6792 struct pci_dev *parent = pdev->bus->self;
6793 u16 aspm_dis_mask = 0;
6794 u16 pdev_aspmc, parent_aspmc;
6795
6796 switch (state) {
6797 case PCIE_LINK_STATE_L0S:
6798 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6799 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
5463fce6 6800 fallthrough; /* can't have L1 without L0s */
13129d9b
CW		 6801 case PCIE_LINK_STATE_L1:
6802 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6803 break;
6804 default:
6805 return;
6806 }
6807
6808 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6809 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6810
6811 if (parent) {
6812 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6813 &parent_aspmc);
6814 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6815 }
6816
6817 /* Nothing to do if the ASPM states to be disabled already are */
6818 if (!(pdev_aspmc & aspm_dis_mask) &&
6819 (!parent || !(parent_aspmc & aspm_dis_mask)))
6820 return;
6821
6822 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6823 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6824 "L0s" : "",
6825 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6826 "L1" : "");
6827
6828#ifdef CONFIG_PCIEASPM
beb0a152
YL		 6829 if (locked)
6830 pci_disable_link_state_locked(pdev, state);
6831 else
6832 pci_disable_link_state(pdev, state);
ffe0b2ff 6833
13129d9b
CW		 6834 /* Double-check ASPM control. If not disabled by the above, the
6835 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6836 * not enabled); override by writing PCI config space directly.
6837 */
6838 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6839 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6840
6841 if (!(aspm_dis_mask & pdev_aspmc))
6842 return;
6843#endif
ffe0b2ff 6844
e921eb1a 6845 /* Both device and parent should have the same ASPM setting.
6f461f6c 6846 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6847 */
13129d9b 6848 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6f461f6c 6849
13129d9b
CW		 6850 if (parent)
6851 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6852 aspm_dis_mask);
1eae4eb2
AK		 6853}
6854
beb0a152
YL		 6855/**
6856 * e1000e_disable_aspm - Disable ASPM states.
6857 * @pdev: pointer to PCI device struct
6858 * @state: bit-mask of ASPM states to disable
6859 *
6860 * This function acquires the pci_bus_sem!
6861 * Some devices *must* have certain ASPM states disabled per hardware errata.
6862 **/
6863static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6864{
6865 __e1000e_disable_aspm(pdev, state, 0);
6866}
6867
6868/**
39da2cac 6869 * e1000e_disable_aspm_locked - Disable ASPM states.
beb0a152
YL		 6870 * @pdev: pointer to PCI device struct
6871 * @state: bit-mask of ASPM states to disable
6872 *
6873 * This function must be called with pci_bus_sem acquired!
6874 * Some devices *must* have certain ASPM states disabled per hardware errata.
6875 **/
6876static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6877{
6878 __e1000e_disable_aspm(pdev, state, 1);
6879}
6880
a7023819
AD		 6881static int e1000e_pm_thaw(struct device *dev)
6882{
6883 struct net_device *netdev = dev_get_drvdata(dev);
6884 struct e1000_adapter *adapter = netdev_priv(netdev);
6885 int rc = 0;
6886
6887 e1000e_set_interrupt_capability(adapter);
6888
6889 rtnl_lock();
6890 if (netif_running(netdev)) {
6891 rc = e1000_request_irq(adapter);
6892 if (rc)
6893 goto err_irq;
6894
6895 e1000e_up(adapter);
6896 }
6897
6898 netif_device_attach(netdev);
6899err_irq:
6900 rtnl_unlock();
6901
6902 return rc;
6903}
6904
23606cf5 6905static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6906{
6907 struct net_device *netdev = pci_get_drvdata(pdev);
6908 struct e1000_adapter *adapter = netdev_priv(netdev);
6909 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6910 u16 aspm_disable_flag = 0;
bc7f75fa 6911
78cd29d5
BA		 6912 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6913 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6914 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6915 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6916 if (aspm_disable_flag)
2758f9ed 6917 e1000e_disable_aspm(pdev, aspm_disable_flag);
78cd29d5 6918
66148bab 6919 pci_set_master(pdev);
6e4f6f6b 6920
2fbe4526 6921 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6922 e1000_resume_workarounds_pchlan(&adapter->hw);
6923
bc7f75fa 6924 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6925
6926 /* report the system wakeup cause from S3/S4 */
6927 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6928 u16 phy_data;
6929
6930 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6931 if (phy_data) {
6932 e_info("PHY Wakeup cause - %s\n",
17e813ec
BA		 6933 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6934 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6935 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6936 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6937 phy_data & E1000_WUS_LNKC ?
6938 "Link Status Change" : "other");
a4f58f54
BA		 6939 }
6940 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6941 } else {
6942 u32 wus = er32(WUS);
6cf08d1c 6943
a4f58f54
BA		 6944 if (wus) {
6945 e_info("MAC Wakeup cause - %s\n",
17e813ec
BA		 6946 wus & E1000_WUS_EX ? "Unicast Packet" :
6947 wus & E1000_WUS_MC ? "Multicast Packet" :
6948 wus & E1000_WUS_BC ? "Broadcast Packet" :
6949 wus & E1000_WUS_MAG ? "Magic Packet" :
6950 wus & E1000_WUS_LNKC ? "Link Status Change" :
6951 "other");
a4f58f54
BA		 6952 }
6953 ew32(WUS, ~0);
6954 }
6955
bc7f75fa 6956 e1000e_reset(adapter);
bc7f75fa 6957
cd791618 6958 e1000_init_manageability_pt(adapter);
bc7f75fa 6959
e921eb1a 6960 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6961 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6962 * under the control of the driver.
6963 */
c43bc57e 6964 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6965 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6966
6967 return 0;
6968}
23606cf5 6969
75a3f93b 6970static int e1000e_pm_prepare(struct device *dev)
ccf8b940
CY		 6971{
6972 return pm_runtime_suspended(dev) &&
6973 pm_suspend_via_firmware();
6974}
6975
75a3f93b 6976static int e1000e_pm_suspend(struct device *dev)
a0340162 6977{
f15bb6dd
SN		 6978 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6979 struct e1000_adapter *adapter = netdev_priv(netdev);
a0340162 6980 struct pci_dev *pdev = to_pci_dev(dev);
833521eb 6981 int rc;
a0340162 6982
2a7e19af
DE		 6983 e1000e_flush_lpic(pdev);
6984
28002099
DE		 6985 e1000e_pm_freeze(dev);
6986
833521eb 6987 rc = __e1000_shutdown(pdev, false);
0a6ad4d9 6988 if (!rc) {
808e0d88 6989 /* Introduce S0ix implementation */
3c98cbf2 6990 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
808e0d88
ML		 6991 e1000e_s0ix_entry_flow(adapter);
6992 }
f15bb6dd 6993
0a6ad4d9 6994 return 0;
a0340162
RW		 6995}
6996
75a3f93b 6997static int e1000e_pm_resume(struct device *dev)
23606cf5 6998{
f15bb6dd
SN		 6999 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
7000 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 7001 struct pci_dev *pdev = to_pci_dev(dev);
28002099 7002 int rc;
23606cf5 7003
f15bb6dd 7004 /* Introduce S0ix implementation */
3c98cbf2 7005 if (adapter->flags2 & FLAG2_ENABLE_S0IX_FLOWS)
f15bb6dd
SN		 7006 e1000e_s0ix_exit_flow(adapter);
7007
28002099
DE		 7008 rc = __e1000_resume(pdev);
7009 if (rc)
7010 return rc;
23606cf5 7011
28002099 7012 return e1000e_pm_thaw(dev);
23606cf5 7013}
a0340162 7014
880e6269 7015static __maybe_unused int e1000e_pm_runtime_idle(struct device *dev)
a0340162 7016{
ee2e80c1 7017 struct net_device *netdev = dev_get_drvdata(dev);
a0340162 7018 struct e1000_adapter *adapter = netdev_priv(netdev);
2116bc25 7019 u16 eee_lp;
a0340162 7020
2116bc25
DE		 7021 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
7022
7023 if (!e1000e_has_link(adapter)) {
7024 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
63eb48f1 7025 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
2116bc25 7026 }
a0340162 7027
63eb48f1 7028 return -EBUSY;
a0340162
RW		 7029}
7030
75a3f93b 7031static int e1000e_pm_runtime_resume(struct device *dev)
a0340162
RW		 7032{
7033 struct pci_dev *pdev = to_pci_dev(dev);
7034 struct net_device *netdev = pci_get_drvdata(pdev);
7035 struct e1000_adapter *adapter = netdev_priv(netdev);
63eb48f1 7036 int rc;
a0340162 7037
d1470851
KHF		 7038 pdev->pme_poll = true;
7039
63eb48f1
DE		 7040 rc = __e1000_resume(pdev);
7041 if (rc)
7042 return rc;
a0340162 7043
63eb48f1 7044 if (netdev->flags & IFF_UP)
386164d9 7045 e1000e_up(adapter);
a0340162 7046
63eb48f1 7047 return rc;
a0340162 7048}
23606cf5 7049
75a3f93b 7050static int e1000e_pm_runtime_suspend(struct device *dev)
23606cf5
RW		 7051{
7052 struct pci_dev *pdev = to_pci_dev(dev);
7053 struct net_device *netdev = pci_get_drvdata(pdev);
7054 struct e1000_adapter *adapter = netdev_priv(netdev);
7055
63eb48f1
DE		 7056 if (netdev->flags & IFF_UP) {
7057 int count = E1000_CHECK_RESET_COUNT;
7058
7059 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
ab6973ae 7060 usleep_range(10000, 11000);
23606cf5 7061
63eb48f1
DE		 7062 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
7063
7064 /* Down the device without resetting the hardware */
7065 e1000e_down(adapter, false);
7066 }
7067
7068 if (__e1000_shutdown(pdev, true)) {
7069 e1000e_pm_runtime_resume(dev);
7070 return -EBUSY;
7071 }
7072
7073 return 0;
23606cf5 7074}
bc7f75fa
AK		 7075
7076static void e1000_shutdown(struct pci_dev *pdev)
7077{
2a7e19af
DE		 7078 e1000e_flush_lpic(pdev);
7079
28002099
DE		 7080 e1000e_pm_freeze(&pdev->dev);
7081
66148bab 7082 __e1000_shutdown(pdev, false);
bc7f75fa
AK		 7083}
7084
7085#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c 7086
8bb62869 7087static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
147b2c8c
DD		 7088{
7089 struct net_device *netdev = data;
7090 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 7091
7092 if (adapter->msix_entries) {
90da0669
BA		 7093 int vector, msix_irq;
7094
147b2c8c
DD		 7095 vector = 0;
7096 msix_irq = adapter->msix_entries[vector].vector;
fd8e597b
KK		 7097 if (disable_hardirq(msix_irq))
7098 e1000_intr_msix_rx(msix_irq, netdev);
147b2c8c
DD		 7099 enable_irq(msix_irq);
7100
7101 vector++;
7102 msix_irq = adapter->msix_entries[vector].vector;
fd8e597b
KK		 7103 if (disable_hardirq(msix_irq))
7104 e1000_intr_msix_tx(msix_irq, netdev);
147b2c8c
DD		 7105 enable_irq(msix_irq);
7106
7107 vector++;
7108 msix_irq = adapter->msix_entries[vector].vector;
fd8e597b
KK		 7109 if (disable_hardirq(msix_irq))
7110 e1000_msix_other(msix_irq, netdev);
147b2c8c
DD		 7111 enable_irq(msix_irq);
7112 }
7113
7114 return IRQ_HANDLED;
7115}
7116
e921eb1a
BA		 7117/**
7118 * e1000_netpoll
7119 * @netdev: network interface device structure
7120 *
bc7f75fa
AK		 7121 * Polling 'interrupt' - used by things like netconsole to send skbs
7122 * without having to re-enable interrupts. It's not called while
7123 * the interrupt routine is executing.
7124 */
7125static void e1000_netpoll(struct net_device *netdev)
7126{
7127 struct e1000_adapter *adapter = netdev_priv(netdev);
7128
147b2c8c
DD		 7129 switch (adapter->int_mode) {
7130 case E1000E_INT_MODE_MSIX:
7131 e1000_intr_msix(adapter->pdev->irq, netdev);
7132 break;
7133 case E1000E_INT_MODE_MSI:
31119129
WC		 7134 if (disable_hardirq(adapter->pdev->irq))
7135 e1000_intr_msi(adapter->pdev->irq, netdev);
147b2c8c
DD		 7136 enable_irq(adapter->pdev->irq);
7137 break;
e80bd1d1 7138 default: /* E1000E_INT_MODE_LEGACY */
31119129
WC		 7139 if (disable_hardirq(adapter->pdev->irq))
7140 e1000_intr(adapter->pdev->irq, netdev);
147b2c8c
DD		 7141 enable_irq(adapter->pdev->irq);
7142 break;
7143 }
bc7f75fa
AK		 7144}
7145#endif
7146
7147/**
7148 * e1000_io_error_detected - called when PCI error is detected
7149 * @pdev: Pointer to PCI device
7150 * @state: The current pci connection state
7151 *
7152 * This function is called after a PCI bus error affecting
7153 * this device has been detected.
7154 */
7155static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
7156 pci_channel_state_t state)
7157{
a7023819 7158 e1000e_pm_freeze(&pdev->dev);
bc7f75fa 7159
c93b5a76
MM		 7160 if (state == pci_channel_io_perm_failure)
7161 return PCI_ERS_RESULT_DISCONNECT;
7162
bc7f75fa
AK		 7163 pci_disable_device(pdev);
7164
800b74a5 7165 /* Request a slot reset. */
bc7f75fa
AK		 7166 return PCI_ERS_RESULT_NEED_RESET;
7167}
7168
7169/**
7170 * e1000_io_slot_reset - called after the pci bus has been reset.
7171 * @pdev: Pointer to PCI device
7172 *
7173 * Restart the card from scratch, as if from a cold-boot. Implementation
28002099 7174 * resembles the first-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 7175 */
7176static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
7177{
7178 struct net_device *netdev = pci_get_drvdata(pdev);
7179 struct e1000_adapter *adapter = netdev_priv(netdev);
7180 struct e1000_hw *hw = &adapter->hw;
78cd29d5 7181 u16 aspm_disable_flag = 0;
6e4f6f6b 7182 int err;
111b9dc5 7183 pci_ers_result_t result;
bc7f75fa 7184
78cd29d5
BA		 7185 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
7186 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 7187 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 7188 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7189 if (aspm_disable_flag)
2758f9ed 7190 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
78cd29d5 7191
f0f422e5 7192 err = pci_enable_device_mem(pdev);
6e4f6f6b 7193 if (err) {
bc7f75fa
AK		 7194 dev_err(&pdev->dev,
7195 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 7196 result = PCI_ERS_RESULT_DISCONNECT;
7197 } else {
23606cf5 7198 pdev->state_saved = true;
111b9dc5 7199 pci_restore_state(pdev);
66148bab 7200 pci_set_master(pdev);
bc7f75fa 7201
111b9dc5
JB		 7202 pci_enable_wake(pdev, PCI_D3hot, 0);
7203 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 7204
111b9dc5
JB		 7205 e1000e_reset(adapter);
7206 ew32(WUS, ~0);
7207 result = PCI_ERS_RESULT_RECOVERED;
7208 }
bc7f75fa 7209
111b9dc5 7210 return result;
bc7f75fa
AK		 7211}
7212
7213/**
7214 * e1000_io_resume - called when traffic can start flowing again.
7215 * @pdev: Pointer to PCI device
7216 *
7217 * This callback is called when the error recovery driver tells us that
7218 * its OK to resume normal operation. Implementation resembles the
28002099 7219 * second-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 7220 */
7221static void e1000_io_resume(struct pci_dev *pdev)
7222{
7223 struct net_device *netdev = pci_get_drvdata(pdev);
7224 struct e1000_adapter *adapter = netdev_priv(netdev);
7225
cd791618 7226 e1000_init_manageability_pt(adapter);
bc7f75fa 7227
a7023819 7228 e1000e_pm_thaw(&pdev->dev);
bc7f75fa 7229
e921eb1a 7230 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 7231 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 7232 * under the control of the driver.
7233 */
c43bc57e 7234 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 7235 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 7236}
7237
7238static void e1000_print_device_info(struct e1000_adapter *adapter)
7239{
7240 struct e1000_hw *hw = &adapter->hw;
7241 struct net_device *netdev = adapter->netdev;
073287c0
BA		 7242 u32 ret_val;
7243 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 7244
7245 /* print bus type/speed/width info */
a5cc7642 7246 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 7247 /* bus width */
7248 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
f0ff4398 7249 "Width x1"),
44defeb3 7250 /* MAC address */
7c510e4b 7251 netdev->dev_addr);
44defeb3
JK		 7252 e_info("Intel(R) PRO/%s Network Connection\n",
7253 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 7254 ret_val = e1000_read_pba_string_generic(hw, pba_str,
7255 E1000_PBANUM_LENGTH);
7256 if (ret_val)
f029c781 7257 strscpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 7258 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
7259 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 7260}
7261
10aa4c04
AK		 7262static void e1000_eeprom_checks(struct e1000_adapter *adapter)
7263{
7264 struct e1000_hw *hw = &adapter->hw;
7265 int ret_val;
7266 u16 buf = 0;
7267
7268 if (hw->mac.type != e1000_82573)
7269 return;
7270
7271 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762 7272 le16_to_cpus(&buf);
18dd2392 7273 if (!ret_val && (!(buf & BIT(0)))) {
10aa4c04 7274 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 7275 dev_warn(&adapter->pdev->dev,
7276 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 7277 }
10aa4c04
AK		 7278}
7279
55e7fe5b
AD		 7280static netdev_features_t e1000_fix_features(struct net_device *netdev,
7281 netdev_features_t features)
7282{
7283 struct e1000_adapter *adapter = netdev_priv(netdev);
7284 struct e1000_hw *hw = &adapter->hw;
7285
7286 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7287 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
7288 features &= ~NETIF_F_RXFCS;
7289
83808641
JW		 7290 /* Since there is no support for separate Rx/Tx vlan accel
7291 * enable/disable make sure Tx flag is always in same state as Rx.
7292 */
7293 if (features & NETIF_F_HW_VLAN_CTAG_RX)
7294 features |= NETIF_F_HW_VLAN_CTAG_TX;
7295 else
7296 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
7297
55e7fe5b
AD		 7298 return features;
7299}
7300
c8f44aff 7301static int e1000_set_features(struct net_device *netdev,
70495a50 7302 netdev_features_t features)
dc221294
BA		 7303{
7304 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 7305 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 7306
7307 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
7308 adapter->flags |= FLAG_TSO_FORCE;
7309
f646968f 7310 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
cf955e6c
BG		 7311 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
7312 NETIF_F_RXALL)))
dc221294
BA		 7313 return 0;
7314
0184039a
BG		 7315 if (changed & NETIF_F_RXFCS) {
7316 if (features & NETIF_F_RXFCS) {
7317 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7318 } else {
7319 /* We need to take it back to defaults, which might mean
7320 * stripping is still disabled at the adapter level.
7321 */
7322 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
7323 adapter->flags2 |= FLAG2_CRC_STRIPPING;
7324 else
7325 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
7326 }
7327 }
7328
70495a50
BA		 7329 netdev->features = features;
7330
dc221294
BA		 7331 if (netif_running(netdev))
7332 e1000e_reinit_locked(adapter);
7333 else
7334 e1000e_reset(adapter);
7335
b0ddfe2b 7336 return 1;
dc221294
BA		 7337}
7338
651c2466 7339static const struct net_device_ops e1000e_netdev_ops = {
d5ea45da
SA		 7340 .ndo_open = e1000e_open,
7341 .ndo_stop = e1000e_close,
00829823 7342 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 7343 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 7344 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 7345 .ndo_set_mac_address = e1000_set_mac,
7346 .ndo_change_mtu = e1000_change_mtu,
a7605370 7347 .ndo_eth_ioctl = e1000_ioctl,
651c2466
SH		 7348 .ndo_tx_timeout = e1000_tx_timeout,
7349 .ndo_validate_addr = eth_validate_addr,
7350
651c2466
SH		 7351 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
7352 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
7353#ifdef CONFIG_NET_POLL_CONTROLLER
7354 .ndo_poll_controller = e1000_netpoll,
7355#endif
39aa687a
PW		 7356 .ndo_set_features = e1000_set_features,
7357 .ndo_fix_features = e1000_fix_features,
f2701b18 7358 .ndo_features_check = passthru_features_check,
39aa687a
PW		 7359 .ndo_hwtstamp_get = e1000e_hwtstamp_get,
7360 .ndo_hwtstamp_set = e1000e_hwtstamp_set,
651c2466
SH		 7361};
7362
bc7f75fa
AK		 7363/**
7364 * e1000_probe - Device Initialization Routine
7365 * @pdev: PCI device information struct
7366 * @ent: entry in e1000_pci_tbl
7367 *
7368 * Returns 0 on success, negative on failure
7369 *
7370 * e1000_probe initializes an adapter identified by a pci_dev structure.
7371 * The OS initialization, configuring of the adapter private structure,
7372 * and a hardware reset occur.
7373 **/
1dd06ae8 7374static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 7375{
7376 struct net_device *netdev;
7377 struct e1000_adapter *adapter;
7378 struct e1000_hw *hw;
7379 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 7380 resource_size_t mmio_start, mmio_len;
7381 resource_size_t flash_start, flash_len;
bc7f75fa 7382 static int cards_found;
78cd29d5 7383 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 7384 u16 eeprom_data = 0;
7385 u16 eeprom_apme_mask = E1000_EEPROM_APME;
a34a42d8 7386 int bars, i, err;
847042a6 7387 s32 ret_val = 0;
bc7f75fa 7388
78cd29d5
BA		 7389 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7390 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 7391 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 7392 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7393 if (aspm_disable_flag)
7394 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 7395
f0f422e5 7396 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 7397 if (err)
7398 return err;
7399
718a39eb 7400 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
a34a42d8
CJ		 7401 if (err) {
7402 dev_err(&pdev->dev,
7403 "No usable DMA configuration, aborting\n");
7404 goto err_dma;
bc7f75fa
AK		 7405 }
7406
17e813ec
BA		 7407 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7408 err = pci_request_selected_regions_exclusive(pdev, bars,
7409 e1000e_driver_name);
bc7f75fa
AK		 7410 if (err)
7411 goto err_pci_reg;
7412
7413 pci_set_master(pdev);
438b365a
BA		 7414 /* PCI config space info */
7415 err = pci_save_state(pdev);
7416 if (err)
7417 goto err_alloc_etherdev;
bc7f75fa
AK		 7418
7419 err = -ENOMEM;
7420 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7421 if (!netdev)
7422 goto err_alloc_etherdev;
7423
bc7f75fa
AK		 7424 SET_NETDEV_DEV(netdev, &pdev->dev);
7425
f85e4dfa
TH		 7426 netdev->irq = pdev->irq;
7427
bc7f75fa
AK		 7428 pci_set_drvdata(pdev, netdev);
7429 adapter = netdev_priv(netdev);
7430 hw = &adapter->hw;
7431 adapter->netdev = netdev;
7432 adapter->pdev = pdev;
7433 adapter->ei = ei;
7434 adapter->pba = ei->pba;
7435 adapter->flags = ei->flags;
eb7c3adb 7436 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 7437 adapter->hw.adapter = adapter;
7438 adapter->hw.mac.type = ei->mac;
2adc55c9 7439 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 7440 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 7441
7442 mmio_start = pci_resource_start(pdev, 0);
7443 mmio_len = pci_resource_len(pdev, 0);
7444
7445 err = -EIO;
7446 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7447 if (!adapter->hw.hw_addr)
7448 goto err_ioremap;
7449
7450 if ((adapter->flags & FLAG_HAS_FLASH) &&
1103a631
YL		 7451 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7452 (hw->mac.type < e1000_pch_spt)) {
bc7f75fa
AK		 7453 flash_start = pci_resource_start(pdev, 1);
7454 flash_len = pci_resource_len(pdev, 1);
7455 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7456 if (!adapter->hw.flash_address)
7457 goto err_flashmap;
7458 }
7459
d495bcb8
BA		 7460 /* Set default EEE advertisement */
7461 if (adapter->flags2 & FLAG2_HAS_EEE)
7462 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7463
bc7f75fa 7464 /* construct the net_device struct */
e80bd1d1 7465 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 7466 e1000e_set_ethtool_ops(netdev);
e80bd1d1 7467 netdev->watchdog_timeo = 5 * HZ;
b48b89f9 7468 netif_napi_add(netdev, &adapter->napi, e1000e_poll);
f029c781 7469 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 7470
7471 netdev->mem_start = mmio_start;
7472 netdev->mem_end = mmio_start + mmio_len;
7473
7474 adapter->bd_number = cards_found++;
7475
4662e82b
BA		 7476 e1000e_check_options(adapter);
7477
bc7f75fa
AK		 7478 /* setup adapter struct */
7479 err = e1000_sw_init(adapter);
7480 if (err)
7481 goto err_sw_init;
7482
bc7f75fa
AK		 7483 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7484 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7485 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7486
69e3fd8c 7487 err = ei->get_variants(adapter);
bc7f75fa
AK		 7488 if (err)
7489 goto err_hw_init;
7490
4a770358 7491 if ((adapter->flags & FLAG_IS_ICH) &&
152c0a97
YL		 7492 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7493 (hw->mac.type < e1000_pch_spt))
4a770358
BA		 7494 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7495
bc7f75fa
AK		 7496 hw->mac.ops.get_bus_info(&adapter->hw);
7497
318a94d6 7498 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 7499
7500 /* Copper options */
318a94d6 7501 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 7502 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7503 adapter->hw.phy.disable_polarity_correction = 0;
7504 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7505 }
7506
470a5420 7507 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 7508 dev_info(&pdev->dev,
7509 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 7510
dc221294
BA		 7511 /* Set initial default active device features */
7512 netdev->features = (NETIF_F_SG |
f646968f
PM		 7513 NETIF_F_HW_VLAN_CTAG_RX |
7514 NETIF_F_HW_VLAN_CTAG_TX |
dc221294
BA		 7515 NETIF_F_TSO |
7516 NETIF_F_TSO6 |
70495a50 7517 NETIF_F_RXHASH |
dc221294
BA		 7518 NETIF_F_RXCSUM |
7519 NETIF_F_HW_CSUM);
7520
67d47b95
SB		 7521 /* disable TSO for pcie and 10/100 speeds to avoid
7522 * some hardware issues and for i219 to fix transfer
7523 * speed being capped at 60%
7524 */
7525 if (!(adapter->flags & FLAG_TSO_FORCE)) {
7526 switch (adapter->link_speed) {
7527 case SPEED_10:
7528 case SPEED_100:
7529 e_info("10/100 speed: disabling TSO\n");
7530 netdev->features &= ~NETIF_F_TSO;
7531 netdev->features &= ~NETIF_F_TSO6;
7532 break;
7533 case SPEED_1000:
7534 netdev->features |= NETIF_F_TSO;
7535 netdev->features |= NETIF_F_TSO6;
7536 break;
7537 default:
7538 /* oops */
7539 break;
7540 }
7541 if (hw->mac.type == e1000_pch_spt) {
7542 netdev->features &= ~NETIF_F_TSO;
7543 netdev->features &= ~NETIF_F_TSO6;
7544 }
7545 }
7546
dc221294
BA		 7547 /* Set user-changeable features (subset of all device features) */
7548 netdev->hw_features = netdev->features;
0184039a 7549 netdev->hw_features |= NETIF_F_RXFCS;
943146de 7550 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 7551 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 7552
7553 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
f646968f 7554 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
bc7f75fa 7555
dc221294
BA		 7556 netdev->vlan_features |= (NETIF_F_SG |
7557 NETIF_F_TSO |
7558 NETIF_F_TSO6 |
7559 NETIF_F_HW_CSUM);
a5136e23 7560
ef9b965a
JB		 7561 netdev->priv_flags |= IFF_UNICAST_FLT;
7562
a34a42d8
CJ		 7563 netdev->features |= NETIF_F_HIGHDMA;
7564 netdev->vlan_features |= NETIF_F_HIGHDMA;
bc7f75fa 7565
91c527a5
JW		 7566 /* MTU range: 68 - max_hw_frame_size */
7567 netdev->min_mtu = ETH_MIN_MTU;
7568 netdev->max_mtu = adapter->max_hw_frame_size -
7569 (VLAN_ETH_HLEN + ETH_FCS_LEN);
7570
bc7f75fa
AK		 7571 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7572 adapter->flags |= FLAG_MNG_PT_ENABLED;
7573
e921eb1a 7574 /* before reading the NVM, reset the controller to
ad68076e
BA		 7575 * put the device in a known good starting state
7576 */
bc7f75fa
AK		 7577 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7578
e921eb1a 7579 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 7580 * attempt. Let's give it a few tries
7581 */
7582 for (i = 0;; i++) {
7583 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7584 break;
7585 if (i == 2) {
185095fb 7586 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 7587 err = -EIO;
7588 goto err_eeprom;
7589 }
7590 }
7591
10aa4c04
AK		 7592 e1000_eeprom_checks(adapter);
7593
608f8a0d 7594 /* copy the MAC address */
bc7f75fa 7595 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 7596 dev_err(&pdev->dev,
7597 "NVM Read Error while reading MAC address\n");
bc7f75fa 7598
a05e4c0a 7599 eth_hw_addr_set(netdev, adapter->hw.mac.addr);
bc7f75fa 7600
aaeb6cdf 7601 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 7602 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 7603 netdev->dev_addr);
bc7f75fa
AK		 7604 err = -EIO;
7605 goto err_eeprom;
7606 }
7607
d5ad7a6a 7608 timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0);
26566eae 7609 timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0);
bc7f75fa
AK		 7610
7611 INIT_WORK(&adapter->reset_task, e1000_reset_task);
d5ad7a6a 7612 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 7613 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7614 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 7615 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 7616
bc7f75fa
AK		 7617 /* Initialize link parameters. User can change them with ethtool */
7618 adapter->hw.mac.autoneg = 1;
3db1cd5c 7619 adapter->fc_autoneg = true;
5c48ef3e
BA		 7620 adapter->hw.fc.requested_mode = e1000_fc_default;
7621 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 7622 adapter->hw.phy.autoneg_advertised = 0x2f;
7623
e921eb1a 7624 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 7625 * the EEPROM, enable the ACPI Magic Packet filter
7626 */
7627 if (adapter->flags & FLAG_APME_IN_WUC) {
7628 /* APME bit in EEPROM is mapped to WUC.APME */
7629 eeprom_data = er32(WUC);
7630 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 7631 if ((hw->mac.type > e1000_ich10lan) &&
7632 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 7633 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 7634 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7635 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7636 (adapter->hw.bus.func == 1))
847042a6 7637 ret_val = e1000_read_nvm(&adapter->hw,
491a04d2
DE		 7638 NVM_INIT_CONTROL3_PORT_B,
7639 1, &eeprom_data);
bc7f75fa 7640 else
847042a6 7641 ret_val = e1000_read_nvm(&adapter->hw,
491a04d2
DE		 7642 NVM_INIT_CONTROL3_PORT_A,
7643 1, &eeprom_data);
bc7f75fa
AK		 7644 }
7645
7646 /* fetch WoL from EEPROM */
847042a6
BW		 7647 if (ret_val)
7648 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
491a04d2 7649 else if (eeprom_data & eeprom_apme_mask)
bc7f75fa
AK		 7650 adapter->eeprom_wol |= E1000_WUFC_MAG;
7651
e921eb1a 7652 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 7653 * where the eeprom may be wrong or the board simply won't support
7654 * wake on lan on a particular port
7655 */
7656 if (!(adapter->flags & FLAG_HAS_WOL))
7657 adapter->eeprom_wol = 0;
7658
7659 /* initialize the wol settings based on the eeprom settings */
7660 adapter->wol = adapter->eeprom_wol;
66148bab
KK		 7661
7662 /* make sure adapter isn't asleep if manageability is enabled */
7663 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7664 (hw->mac.ops.check_mng_mode(hw)))
7665 device_wakeup_enable(&pdev->dev);
bc7f75fa 7666
84527590 7667 /* save off EEPROM version number */
847042a6 7668 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
491a04d2 7669
847042a6
BW		 7670 if (ret_val) {
7671 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
491a04d2
DE		 7672 adapter->eeprom_vers = 0;
7673 }
84527590 7674
aa524b66
JK		 7675 /* init PTP hardware clock */
7676 e1000e_ptp_init(adapter);
7677
bc7f75fa
AK		 7678 /* reset the hardware with the new settings */
7679 e1000e_reset(adapter);
7680
e921eb1a 7681 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 7682 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 7683 * under the control of the driver.
7684 */
c43bc57e 7685 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 7686 e1000e_get_hw_control(adapter);
bc7f75fa 7687
3c98cbf2
ML		 7688 if (hw->mac.type >= e1000_pch_cnp)
7689 adapter->flags2 |= FLAG2_ENABLE_S0IX_FLOWS;
7690
f029c781 7691 strscpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 7692 err = register_netdev(netdev);
7693 if (err)
7694 goto err_register;
7695
9c563d20
JB		 7696 /* carrier off reporting is important to ethtool even BEFORE open */
7697 netif_carrier_off(netdev);
7698
bc7f75fa
AK		 7699 e1000_print_device_info(adapter);
7700
ccf8b940 7701 dev_pm_set_driver_flags(&pdev->dev, DPM_FLAG_SMART_PREPARE);
59f58708 7702
d1470851 7703 if (pci_dev_run_wake(pdev))
f3ec4f87 7704 pm_runtime_put_noidle(&pdev->dev);
23606cf5 7705
bc7f75fa
AK		 7706 return 0;
7707
7708err_register:
c43bc57e 7709 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 7710 e1000e_release_hw_control(adapter);
bc7f75fa 7711err_eeprom:
470a5420 7712 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 7713 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 7714err_hw_init:
bc7f75fa
AK		 7715 kfree(adapter->tx_ring);
7716 kfree(adapter->rx_ring);
7717err_sw_init:
1103a631 7718 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
c43bc57e 7719 iounmap(adapter->hw.flash_address);
e82f54ba 7720 e1000e_reset_interrupt_capability(adapter);
c43bc57e 7721err_flashmap:
bc7f75fa
AK		 7722 iounmap(adapter->hw.hw_addr);
7723err_ioremap:
7724 free_netdev(netdev);
7725err_alloc_etherdev:
56d766d6 7726 pci_release_mem_regions(pdev);
bc7f75fa
AK		 7727err_pci_reg:
7728err_dma:
7729 pci_disable_device(pdev);
7730 return err;
7731}
7732
7733/**
7734 * e1000_remove - Device Removal Routine
7735 * @pdev: PCI device information struct
7736 *
7737 * e1000_remove is called by the PCI subsystem to alert the driver
e0bc64d3 7738 * that it should release a PCI device. This could be caused by a
bc7f75fa
AK		 7739 * Hot-Plug event, or because the driver is going to be removed from
7740 * memory.
7741 **/
9f9a12f8 7742static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 7743{
7744 struct net_device *netdev = pci_get_drvdata(pdev);
7745 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 7746
d89777bf
BA		 7747 e1000e_ptp_remove(adapter);
7748
e921eb1a 7749 /* The timers may be rescheduled, so explicitly disable them
23f333a2 7750 * from being rescheduled.
ad68076e 7751 */
daee5598 7752 set_bit(__E1000_DOWN, &adapter->state);
8fa7292f
TG		 7753 timer_delete_sync(&adapter->watchdog_timer);
7754 timer_delete_sync(&adapter->phy_info_timer);
bc7f75fa 7755
41cec6f1 7756 cancel_work_sync(&adapter->reset_task);
d5ad7a6a 7757 cancel_work_sync(&adapter->watchdog_task);
41cec6f1
BA		 7758 cancel_work_sync(&adapter->downshift_task);
7759 cancel_work_sync(&adapter->update_phy_task);
7760 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 7761
b67e1913
BA		 7762 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7763 cancel_work_sync(&adapter->tx_hwtstamp_work);
7764 if (adapter->tx_hwtstamp_skb) {
377b6273 7765 dev_consume_skb_any(adapter->tx_hwtstamp_skb);
b67e1913
BA		 7766 adapter->tx_hwtstamp_skb = NULL;
7767 }
7768 }
7769
17f208de
BA		 7770 unregister_netdev(netdev);
7771
f3ec4f87
AS		 7772 if (pci_dev_run_wake(pdev))
7773 pm_runtime_get_noresume(&pdev->dev);
23606cf5 7774
e921eb1a 7775 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 7776 * would have already happened in close and is redundant.
7777 */
31dbe5b4 7778 e1000e_release_hw_control(adapter);
bc7f75fa 7779
4662e82b 7780 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 7781 kfree(adapter->tx_ring);
7782 kfree(adapter->rx_ring);
7783
7784 iounmap(adapter->hw.hw_addr);
1103a631
YL		 7785 if ((adapter->hw.flash_address) &&
7786 (adapter->hw.mac.type < e1000_pch_spt))
bc7f75fa 7787 iounmap(adapter->hw.flash_address);
56d766d6 7788 pci_release_mem_regions(pdev);
bc7f75fa
AK		 7789
7790 free_netdev(netdev);
7791
7792 pci_disable_device(pdev);
7793}
7794
7795/* PCI Error Recovery (ERS) */
3646f0e5 7796static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 7797 .error_detected = e1000_io_error_detected,
7798 .slot_reset = e1000_io_slot_reset,
7799 .resume = e1000_io_resume,
7800};
7801
0e8e842b 7802static const struct pci_device_id e1000_pci_tbl[] = {
bc7f75fa
AK		 7803 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7804 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7805 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
c29c3ba5
BA		 7806 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7807 board_82571 },
bc7f75fa
AK		 7808 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7809 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 7810 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7811 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7812 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 7813
bc7f75fa
AK		 7814 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7815 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7816 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7817 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 7818
bc7f75fa
AK		 7819 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7820 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7821 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 7822
4662e82b 7823 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 7824 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 7825 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 7826
bc7f75fa
AK		 7827 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7828 board_80003es2lan },
7829 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7830 board_80003es2lan },
7831 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7832 board_80003es2lan },
7833 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7834 board_80003es2lan },
ad68076e 7835
bc7f75fa
AK		 7836 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7837 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7838 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7839 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7840 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7841 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7842 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 7843 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 7844
bc7f75fa
AK		 7845 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7846 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7847 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7848 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7849 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 7850 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 7851 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7852 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7853 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7854
7855 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7856 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7857 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 7858
f4187b56
BA		 7859 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7860 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 7861 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 7862
a4f58f54
BA		 7863 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7864 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7865 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7866 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7867
d3738bb8
BA		 7868 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7869 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7870
2fbe4526
BA		 7871 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7872 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 7873 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7874 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
91a3d82f
BA		 7875 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7876 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7877 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7878 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
79849ebc
DE		 7879 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7880 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7881 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7882 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
f3ed935d 7883 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
9cd34b3a
RA		 7884 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7885 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7886 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7887 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
3a3173b9
SN		 7888 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
7889 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
7890 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
7891 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
48f76b68
SN		 7892 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
7893 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
7894 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
7895 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
914ee9c4
SN		 7896 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM10), board_pch_cnp },
7897 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V10), board_pch_cnp },
7898 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM11), board_pch_cnp },
7899 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V11), board_pch_cnp },
7900 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_LM12), board_pch_spt },
7901 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CMP_I219_V12), board_pch_spt },
280db5d4
SN		 7902 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM13), board_pch_tgp },
7903 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V13), board_pch_tgp },
7904 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM14), board_pch_tgp },
7905 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V14), board_pch_tgp },
7906 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_LM15), board_pch_tgp },
7907 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_TGP_I219_V15), board_pch_tgp },
68defd52
SN		 7908 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM23), board_pch_adp },
7909 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V23), board_pch_adp },
7910 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM16), board_pch_adp },
7911 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V16), board_pch_adp },
7912 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM17), board_pch_adp },
7913 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V17), board_pch_adp },
7914 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_LM22), board_pch_adp },
7915 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_RPL_I219_V22), board_pch_adp },
9d9e5347
VL		 7916 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_LM19), board_pch_adp },
7917 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ADP_I219_V19), board_pch_adp },
db2d737d
SN		 7918 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_LM18), board_pch_mtp },
7919 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_MTP_I219_V18), board_pch_mtp },
db2d737d
SN		 7920 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM20), board_pch_mtp },
7921 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V20), board_pch_mtp },
7922 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_LM21), board_pch_mtp },
7923 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LNP_I219_V21), board_pch_mtp },
0c9183ce
SN		 7924 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_LM24), board_pch_mtp },
7925 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ARL_I219_V24), board_pch_mtp },
7926 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM25), board_pch_mtp },
7927 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V25), board_pch_mtp },
7928 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM26), board_pch_mtp },
7929 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V26), board_pch_mtp },
7930 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_LM27), board_pch_mtp },
7931 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_PTP_I219_V27), board_pch_mtp },
1fe4f45e
SN		 7932 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_LM29), board_pch_mtp },
7933 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_NVL_I219_V29), board_pch_mtp },
2fbe4526 7934
f36bb6ca 7935 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 7936};
7937MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7938
75a3f93b 7939static const struct dev_pm_ops e1000e_pm_ops = {
ccf8b940 7940 .prepare = e1000e_pm_prepare,
28002099
DE		 7941 .suspend = e1000e_pm_suspend,
7942 .resume = e1000e_pm_resume,
7943 .freeze = e1000e_pm_freeze,
7944 .thaw = e1000e_pm_thaw,
7945 .poweroff = e1000e_pm_suspend,
7946 .restore = e1000e_pm_resume,
75a3f93b
JB		 7947 RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7948 e1000e_pm_runtime_idle)
23606cf5
RW		 7949};
7950
bc7f75fa
AK		 7951/* PCI Device API Driver */
7952static struct pci_driver e1000_driver = {
7953 .name = e1000e_driver_name,
7954 .id_table = e1000_pci_tbl,
7955 .probe = e1000_probe,
9f9a12f8 7956 .remove = e1000_remove,
75a3f93b 7957 .driver.pm = pm_ptr(&e1000e_pm_ops),
bc7f75fa
AK		 7958 .shutdown = e1000_shutdown,
7959 .err_handler = &e1000_err_handler
7960};
7961
7962/**
7963 * e1000_init_module - Driver Registration Routine
7964 *
7965 * e1000_init_module is the first routine called when the driver is
7966 * loaded. All it does is register with the PCI subsystem.
7967 **/
7968static int __init e1000_init_module(void)
7969{
34a2a3b8 7970 pr_info("Intel(R) PRO/1000 Network Driver\n");
529498cd 7971 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
53ec5498 7972
5a5e889c 7973 return pci_register_driver(&e1000_driver);
bc7f75fa
AK		 7974}
7975module_init(e1000_init_module);
7976
7977/**
7978 * e1000_exit_module - Driver Exit Cleanup Routine
7979 *
7980 * e1000_exit_module is called just before the driver is removed
7981 * from memory.
7982 **/
7983static void __exit e1000_exit_module(void)
7984{
7985 pci_unregister_driver(&e1000_driver);
7986}
7987module_exit(e1000_exit_module);
7988
bc7f75fa 7989MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
98674ebe 7990MODULE_LICENSE("GPL v2");
bc7f75fa 7991
06c24b91 7992/* netdev.c */
Linux 6.x block layer and io_uring tree(s)