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ixgbe: driver fix for link flap
[linux-block.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
f5e261e6 4 Copyright(c) 1999 - 2012 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
058e8edd 59#define DRV_VERSION "1.9.5" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
b3f4d599 63#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
64static int debug = -1;
65module_param(debug, int, 0);
66MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
67
78cd29d5
BA		 68static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
69
bc7f75fa
AK		 70static const struct e1000_info *e1000_info_tbl[] = {
71 [board_82571] = &e1000_82571_info,
72 [board_82572] = &e1000_82572_info,
73 [board_82573] = &e1000_82573_info,
4662e82b 74 [board_82574] = &e1000_82574_info,
8c81c9c3 75 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 76 [board_80003es2lan] = &e1000_es2_info,
77 [board_ich8lan] = &e1000_ich8_info,
78 [board_ich9lan] = &e1000_ich9_info,
f4187b56 79 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 80 [board_pchlan] = &e1000_pch_info,
d3738bb8 81 [board_pch2lan] = &e1000_pch2_info,
bc7f75fa
AK		 82};
83
84f4ee90
TI		 84struct e1000_reg_info {
85 u32 ofs;
86 char *name;
87};
88
af667a29
BA		 89#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
90#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
91#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
92#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
93#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
94
95#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
96#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
97#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
98#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
99#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 100
101static const struct e1000_reg_info e1000_reg_info_tbl[] = {
102
103 /* General Registers */
104 {E1000_CTRL, "CTRL"},
105 {E1000_STATUS, "STATUS"},
106 {E1000_CTRL_EXT, "CTRL_EXT"},
107
108 /* Interrupt Registers */
109 {E1000_ICR, "ICR"},
110
af667a29 111 /* Rx Registers */
84f4ee90
TI		 112 {E1000_RCTL, "RCTL"},
113 {E1000_RDLEN, "RDLEN"},
114 {E1000_RDH, "RDH"},
115 {E1000_RDT, "RDT"},
116 {E1000_RDTR, "RDTR"},
117 {E1000_RXDCTL(0), "RXDCTL"},
118 {E1000_ERT, "ERT"},
119 {E1000_RDBAL, "RDBAL"},
120 {E1000_RDBAH, "RDBAH"},
121 {E1000_RDFH, "RDFH"},
122 {E1000_RDFT, "RDFT"},
123 {E1000_RDFHS, "RDFHS"},
124 {E1000_RDFTS, "RDFTS"},
125 {E1000_RDFPC, "RDFPC"},
126
af667a29 127 /* Tx Registers */
84f4ee90
TI		 128 {E1000_TCTL, "TCTL"},
129 {E1000_TDBAL, "TDBAL"},
130 {E1000_TDBAH, "TDBAH"},
131 {E1000_TDLEN, "TDLEN"},
132 {E1000_TDH, "TDH"},
133 {E1000_TDT, "TDT"},
134 {E1000_TIDV, "TIDV"},
135 {E1000_TXDCTL(0), "TXDCTL"},
136 {E1000_TADV, "TADV"},
137 {E1000_TARC(0), "TARC"},
138 {E1000_TDFH, "TDFH"},
139 {E1000_TDFT, "TDFT"},
140 {E1000_TDFHS, "TDFHS"},
141 {E1000_TDFTS, "TDFTS"},
142 {E1000_TDFPC, "TDFPC"},
143
144 /* List Terminator */
f36bb6ca 145 {0, NULL}
84f4ee90
TI		 146};
147
148/*
149 * e1000_regdump - register printout routine
150 */
151static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
152{
153 int n = 0;
154 char rname[16];
155 u32 regs[8];
156
157 switch (reginfo->ofs) {
158 case E1000_RXDCTL(0):
159 for (n = 0; n < 2; n++)
160 regs[n] = __er32(hw, E1000_RXDCTL(n));
161 break;
162 case E1000_TXDCTL(0):
163 for (n = 0; n < 2; n++)
164 regs[n] = __er32(hw, E1000_TXDCTL(n));
165 break;
166 case E1000_TARC(0):
167 for (n = 0; n < 2; n++)
168 regs[n] = __er32(hw, E1000_TARC(n));
169 break;
170 default:
ef456f85
JK		 171 pr_info("%-15s %08x\n",
172 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 173 return;
174 }
175
176 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 177 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 178}
179
84f4ee90 180/*
af667a29 181 * e1000e_dump - Print registers, Tx-ring and Rx-ring
84f4ee90
TI		 182 */
183static void e1000e_dump(struct e1000_adapter *adapter)
184{
185 struct net_device *netdev = adapter->netdev;
186 struct e1000_hw *hw = &adapter->hw;
187 struct e1000_reg_info *reginfo;
188 struct e1000_ring *tx_ring = adapter->tx_ring;
189 struct e1000_tx_desc *tx_desc;
af667a29 190 struct my_u0 {
e885d762
BA		 191 __le64 a;
192 __le64 b;
af667a29 193 } *u0;
84f4ee90
TI		 194 struct e1000_buffer *buffer_info;
195 struct e1000_ring *rx_ring = adapter->rx_ring;
196 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 197 union e1000_rx_desc_extended *rx_desc;
af667a29 198 struct my_u1 {
e885d762
BA		 199 __le64 a;
200 __le64 b;
201 __le64 c;
202 __le64 d;
af667a29 203 } *u1;
84f4ee90
TI		 204 u32 staterr;
205 int i = 0;
206
207 if (!netif_msg_hw(adapter))
208 return;
209
210 /* Print netdevice Info */
211 if (netdev) {
212 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 213 pr_info("Device Name state trans_start last_rx\n");
214 pr_info("%-15s %016lX %016lX %016lX\n",
215 netdev->name, netdev->state, netdev->trans_start,
216 netdev->last_rx);
84f4ee90
TI		 217 }
218
219 /* Print Registers */
220 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 221 pr_info(" Register Name Value\n");
84f4ee90
TI		 222 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
223 reginfo->name; reginfo++) {
224 e1000_regdump(hw, reginfo);
225 }
226
af667a29 227 /* Print Tx Ring Summary */
84f4ee90 228 if (!netdev || !netif_running(netdev))
fe1e980f 229 return;
84f4ee90 230
af667a29 231 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 232 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 233 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 234 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
235 0, tx_ring->next_to_use, tx_ring->next_to_clean,
236 (unsigned long long)buffer_info->dma,
237 buffer_info->length,
238 buffer_info->next_to_watch,
239 (unsigned long long)buffer_info->time_stamp);
84f4ee90 240
af667a29 241 /* Print Tx Ring */
84f4ee90
TI		 242 if (!netif_msg_tx_done(adapter))
243 goto rx_ring_summary;
244
af667a29 245 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 246
247 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
248 *
249 * Legacy Transmit Descriptor
250 * +--------------------------------------------------------------+
251 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
252 * +--------------------------------------------------------------+
253 * 8 | Special | CSS | Status | CMD | CSO | Length |
254 * +--------------------------------------------------------------+
255 * 63 48 47 36 35 32 31 24 23 16 15 0
256 *
257 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
258 * 63 48 47 40 39 32 31 16 15 8 7 0
259 * +----------------------------------------------------------------+
260 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
261 * +----------------------------------------------------------------+
262 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
263 * +----------------------------------------------------------------+
264 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
265 *
266 * Extended Data Descriptor (DTYP=0x1)
267 * +----------------------------------------------------------------+
268 * 0 | Buffer Address [63:0] |
269 * +----------------------------------------------------------------+
270 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
271 * +----------------------------------------------------------------+
272 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
273 */
ef456f85
JK		 274 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
275 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
276 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 277 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 278 const char *next_desc;
84f4ee90
TI		 279 tx_desc = E1000_TX_DESC(*tx_ring, i);
280 buffer_info = &tx_ring->buffer_info[i];
281 u0 = (struct my_u0 *)tx_desc;
84f4ee90 282 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 283 next_desc = " NTC/U";
84f4ee90 284 else if (i == tx_ring->next_to_use)
ef456f85 285 next_desc = " NTU";
84f4ee90 286 else if (i == tx_ring->next_to_clean)
ef456f85 287 next_desc = " NTC";
84f4ee90 288 else
ef456f85
JK		 289 next_desc = "";
290 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
291 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
292 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
293 i,
294 (unsigned long long)le64_to_cpu(u0->a),
295 (unsigned long long)le64_to_cpu(u0->b),
296 (unsigned long long)buffer_info->dma,
297 buffer_info->length, buffer_info->next_to_watch,
298 (unsigned long long)buffer_info->time_stamp,
299 buffer_info->skb, next_desc);
84f4ee90
TI		 300
301 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
302 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
af667a29
BA		 303 16, 1, phys_to_virt(buffer_info->dma),
304 buffer_info->length, true);
84f4ee90
TI		 305 }
306
af667a29 307 /* Print Rx Ring Summary */
84f4ee90 308rx_ring_summary:
af667a29 309 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 310 pr_info("Queue [NTU] [NTC]\n");
311 pr_info(" %5d %5X %5X\n",
312 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 313
af667a29 314 /* Print Rx Ring */
84f4ee90 315 if (!netif_msg_rx_status(adapter))
fe1e980f 316 return;
84f4ee90 317
af667a29 318 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 319 switch (adapter->rx_ps_pages) {
320 case 1:
321 case 2:
322 case 3:
323 /* [Extended] Packet Split Receive Descriptor Format
324 *
325 * +-----------------------------------------------------+
326 * 0 | Buffer Address 0 [63:0] |
327 * +-----------------------------------------------------+
328 * 8 | Buffer Address 1 [63:0] |
329 * +-----------------------------------------------------+
330 * 16 | Buffer Address 2 [63:0] |
331 * +-----------------------------------------------------+
332 * 24 | Buffer Address 3 [63:0] |
333 * +-----------------------------------------------------+
334 */
ef456f85 335 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 336 /* [Extended] Receive Descriptor (Write-Back) Format
337 *
338 * 63 48 47 32 31 13 12 8 7 4 3 0
339 * +------------------------------------------------------+
340 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
341 * | Checksum | Ident | | Queue | | Type |
342 * +------------------------------------------------------+
343 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
344 * +------------------------------------------------------+
345 * 63 48 47 32 31 20 19 0
346 */
ef456f85 347 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 348 for (i = 0; i < rx_ring->count; i++) {
ef456f85 349 const char *next_desc;
84f4ee90
TI		 350 buffer_info = &rx_ring->buffer_info[i];
351 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
352 u1 = (struct my_u1 *)rx_desc_ps;
353 staterr =
af667a29 354 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 355
356 if (i == rx_ring->next_to_use)
357 next_desc = " NTU";
358 else if (i == rx_ring->next_to_clean)
359 next_desc = " NTC";
360 else
361 next_desc = "";
362
84f4ee90
TI		 363 if (staterr & E1000_RXD_STAT_DD) {
364 /* Descriptor Done */
ef456f85
JK		 365 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
366 "RWB", i,
367 (unsigned long long)le64_to_cpu(u1->a),
368 (unsigned long long)le64_to_cpu(u1->b),
369 (unsigned long long)le64_to_cpu(u1->c),
370 (unsigned long long)le64_to_cpu(u1->d),
371 buffer_info->skb, next_desc);
84f4ee90 372 } else {
ef456f85
JK		 373 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
374 "R ", i,
375 (unsigned long long)le64_to_cpu(u1->a),
376 (unsigned long long)le64_to_cpu(u1->b),
377 (unsigned long long)le64_to_cpu(u1->c),
378 (unsigned long long)le64_to_cpu(u1->d),
379 (unsigned long long)buffer_info->dma,
380 buffer_info->skb, next_desc);
84f4ee90
TI		 381
382 if (netif_msg_pktdata(adapter))
383 print_hex_dump(KERN_INFO, "",
384 DUMP_PREFIX_ADDRESS, 16, 1,
385 phys_to_virt(buffer_info->dma),
386 adapter->rx_ps_bsize0, true);
387 }
84f4ee90
TI		 388 }
389 break;
390 default:
391 case 0:
5f450212 392 /* Extended Receive Descriptor (Read) Format
84f4ee90 393 *
5f450212
BA		 394 * +-----------------------------------------------------+
395 * 0 | Buffer Address [63:0] |
396 * +-----------------------------------------------------+
397 * 8 | Reserved |
398 * +-----------------------------------------------------+
84f4ee90 399 */
ef456f85 400 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 401 /* Extended Receive Descriptor (Write-Back) Format
402 *
403 * 63 48 47 32 31 24 23 4 3 0
404 * +------------------------------------------------------+
405 * | RSS Hash | | | |
406 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
407 * | Packet | IP | | | Type |
408 * | Checksum | Ident | | | |
409 * +------------------------------------------------------+
410 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
411 * +------------------------------------------------------+
412 * 63 48 47 32 31 20 19 0
413 */
ef456f85 414 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 415
416 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 417 const char *next_desc;
418
84f4ee90 419 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 420 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
421 u1 = (struct my_u1 *)rx_desc;
422 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 423
424 if (i == rx_ring->next_to_use)
425 next_desc = " NTU";
426 else if (i == rx_ring->next_to_clean)
427 next_desc = " NTC";
428 else
429 next_desc = "";
430
5f450212
BA		 431 if (staterr & E1000_RXD_STAT_DD) {
432 /* Descriptor Done */
ef456f85
JK		 433 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
434 "RWB", i,
435 (unsigned long long)le64_to_cpu(u1->a),
436 (unsigned long long)le64_to_cpu(u1->b),
437 buffer_info->skb, next_desc);
5f450212 438 } else {
ef456f85
JK		 439 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
440 "R ", i,
441 (unsigned long long)le64_to_cpu(u1->a),
442 (unsigned long long)le64_to_cpu(u1->b),
443 (unsigned long long)buffer_info->dma,
444 buffer_info->skb, next_desc);
5f450212
BA		 445
446 if (netif_msg_pktdata(adapter))
447 print_hex_dump(KERN_INFO, "",
448 DUMP_PREFIX_ADDRESS, 16,
449 1,
450 phys_to_virt
451 (buffer_info->dma),
452 adapter->rx_buffer_len,
453 true);
454 }
84f4ee90
TI		 455 }
456 }
84f4ee90
TI		 457}
458
bc7f75fa
AK		 459/**
460 * e1000_desc_unused - calculate if we have unused descriptors
461 **/
462static int e1000_desc_unused(struct e1000_ring *ring)
463{
464 if (ring->next_to_clean > ring->next_to_use)
465 return ring->next_to_clean - ring->next_to_use - 1;
466
467 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
468}
469
470/**
ad68076e 471 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa
AK		 472 * @adapter: board private structure
473 * @status: descriptor status field as written by hardware
474 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
475 * @skb: pointer to sk_buff to be indicated to stack
476 **/
477static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 478 struct net_device *netdev, struct sk_buff *skb,
a39fe742 479 u8 status, __le16 vlan)
bc7f75fa 480{
86d70e53 481 u16 tag = le16_to_cpu(vlan);
bc7f75fa
AK		 482 skb->protocol = eth_type_trans(skb, netdev);
483
86d70e53
JK		 484 if (status & E1000_RXD_STAT_VP)
485 __vlan_hwaccel_put_tag(skb, tag);
486
487 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 488}
489
490/**
af667a29 491 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 492 * @adapter: board private structure
493 * @status_err: receive descriptor status and error fields
494 * @csum: receive descriptor csum field
495 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 496 **/
497static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
afd12939 498 __le16 csum, struct sk_buff *skb)
bc7f75fa
AK		 499{
500 u16 status = (u16)status_err;
501 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 502
503 skb_checksum_none_assert(skb);
bc7f75fa 504
afd12939
BA		 505 /* Rx checksum disabled */
506 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
507 return;
508
bc7f75fa
AK		 509 /* Ignore Checksum bit is set */
510 if (status & E1000_RXD_STAT_IXSM)
511 return;
afd12939 512
bc7f75fa
AK		 513 /* TCP/UDP checksum error bit is set */
514 if (errors & E1000_RXD_ERR_TCPE) {
515 /* let the stack verify checksum errors */
516 adapter->hw_csum_err++;
517 return;
518 }
519
520 /* TCP/UDP Checksum has not been calculated */
521 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
522 return;
523
524 /* It must be a TCP or UDP packet with a valid checksum */
525 if (status & E1000_RXD_STAT_TCPCS) {
526 /* TCP checksum is good */
527 skb->ip_summed = CHECKSUM_UNNECESSARY;
528 } else {
ad68076e
BA		 529 /*
530 * IP fragment with UDP payload
531 * Hardware complements the payload checksum, so we undo it
bc7f75fa
AK		 532 * and then put the value in host order for further stack use.
533 */
afd12939 534 __sum16 sum = (__force __sum16)swab16((__force u16)csum);
a39fe742 535 skb->csum = csum_unfold(~sum);
bc7f75fa
AK		 536 skb->ip_summed = CHECKSUM_COMPLETE;
537 }
538 adapter->hw_csum_good++;
539}
540
c6e7f51e
BA		 541/**
542 * e1000e_update_tail_wa - helper function for e1000e_update_[rt]dt_wa()
543 * @hw: pointer to the HW structure
544 * @tail: address of tail descriptor register
545 * @i: value to write to tail descriptor register
546 *
547 * When updating the tail register, the ME could be accessing Host CSR
548 * registers at the same time. Normally, this is handled in h/w by an
549 * arbiter but on some parts there is a bug that acknowledges Host accesses
550 * later than it should which could result in the descriptor register to
551 * have an incorrect value. Workaround this by checking the FWSM register
552 * which has bit 24 set while ME is accessing Host CSR registers, wait
553 * if it is set and try again a number of times.
554 **/
c5083cf6 555static inline s32 e1000e_update_tail_wa(struct e1000_hw *hw, void __iomem *tail,
c6e7f51e
BA		 556 unsigned int i)
557{
558 unsigned int j = 0;
559
560 while ((j++ < E1000_ICH_FWSM_PCIM2PCI_COUNT) &&
561 (er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI))
562 udelay(50);
563
564 writel(i, tail);
565
566 if ((j == E1000_ICH_FWSM_PCIM2PCI_COUNT) && (i != readl(tail)))
567 return E1000_ERR_SWFW_SYNC;
568
569 return 0;
570}
571
55aa6985 572static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 573{
55aa6985 574 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e
BA		 575 struct e1000_hw *hw = &adapter->hw;
576
55aa6985 577 if (e1000e_update_tail_wa(hw, rx_ring->tail, i)) {
c6e7f51e
BA		 578 u32 rctl = er32(RCTL);
579 ew32(RCTL, rctl & ~E1000_RCTL_EN);
580 e_err("ME firmware caused invalid RDT - resetting\n");
581 schedule_work(&adapter->reset_task);
582 }
583}
584
55aa6985 585static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 586{
55aa6985 587 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e
BA		 588 struct e1000_hw *hw = &adapter->hw;
589
55aa6985 590 if (e1000e_update_tail_wa(hw, tx_ring->tail, i)) {
c6e7f51e
BA		 591 u32 tctl = er32(TCTL);
592 ew32(TCTL, tctl & ~E1000_TCTL_EN);
593 e_err("ME firmware caused invalid TDT - resetting\n");
594 schedule_work(&adapter->reset_task);
595 }
596}
597
bc7f75fa 598/**
5f450212 599 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 600 * @rx_ring: Rx descriptor ring
bc7f75fa 601 **/
55aa6985 602static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 603 int cleaned_count, gfp_t gfp)
bc7f75fa 604{
55aa6985 605 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 606 struct net_device *netdev = adapter->netdev;
607 struct pci_dev *pdev = adapter->pdev;
5f450212 608 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 609 struct e1000_buffer *buffer_info;
610 struct sk_buff *skb;
611 unsigned int i;
89d71a66 612 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 613
614 i = rx_ring->next_to_use;
615 buffer_info = &rx_ring->buffer_info[i];
616
617 while (cleaned_count--) {
618 skb = buffer_info->skb;
619 if (skb) {
620 skb_trim(skb, 0);
621 goto map_skb;
622 }
623
c2fed996 624 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 625 if (!skb) {
626 /* Better luck next round */
627 adapter->alloc_rx_buff_failed++;
628 break;
629 }
630
bc7f75fa
AK		 631 buffer_info->skb = skb;
632map_skb:
0be3f55f 633 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 634 adapter->rx_buffer_len,
0be3f55f
NN		 635 DMA_FROM_DEVICE);
636 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 637 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 638 adapter->rx_dma_failed++;
639 break;
640 }
641
5f450212
BA		 642 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
643 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 644
50849d79
TH		 645 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
646 /*
647 * Force memory writes to complete before letting h/w
648 * know there are new descriptors to fetch. (Only
649 * applicable for weak-ordered memory model archs,
650 * such as IA-64).
651 */
652 wmb();
c6e7f51e 653 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 654 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 655 else
c5083cf6 656 writel(i, rx_ring->tail);
50849d79 657 }
bc7f75fa
AK		 658 i++;
659 if (i == rx_ring->count)
660 i = 0;
661 buffer_info = &rx_ring->buffer_info[i];
662 }
663
50849d79 664 rx_ring->next_to_use = i;
bc7f75fa
AK		 665}
666
667/**
668 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 669 * @rx_ring: Rx descriptor ring
bc7f75fa 670 **/
55aa6985 671static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 672 int cleaned_count, gfp_t gfp)
bc7f75fa 673{
55aa6985 674 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 675 struct net_device *netdev = adapter->netdev;
676 struct pci_dev *pdev = adapter->pdev;
677 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 678 struct e1000_buffer *buffer_info;
679 struct e1000_ps_page *ps_page;
680 struct sk_buff *skb;
681 unsigned int i, j;
682
683 i = rx_ring->next_to_use;
684 buffer_info = &rx_ring->buffer_info[i];
685
686 while (cleaned_count--) {
687 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
688
689 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 690 ps_page = &buffer_info->ps_pages[j];
691 if (j >= adapter->rx_ps_pages) {
692 /* all unused desc entries get hw null ptr */
af667a29
BA		 693 rx_desc->read.buffer_addr[j + 1] =
694 ~cpu_to_le64(0);
47f44e40
AK		 695 continue;
696 }
697 if (!ps_page->page) {
c2fed996 698 ps_page->page = alloc_page(gfp);
bc7f75fa 699 if (!ps_page->page) {
47f44e40
AK		 700 adapter->alloc_rx_buff_failed++;
701 goto no_buffers;
702 }
0be3f55f
NN		 703 ps_page->dma = dma_map_page(&pdev->dev,
704 ps_page->page,
705 0, PAGE_SIZE,
706 DMA_FROM_DEVICE);
707 if (dma_mapping_error(&pdev->dev,
708 ps_page->dma)) {
47f44e40 709 dev_err(&adapter->pdev->dev,
af667a29 710 "Rx DMA page map failed\n");
47f44e40
AK		 711 adapter->rx_dma_failed++;
712 goto no_buffers;
bc7f75fa 713 }
bc7f75fa 714 }
47f44e40
AK		 715 /*
716 * Refresh the desc even if buffer_addrs
717 * didn't change because each write-back
718 * erases this info.
719 */
af667a29
BA		 720 rx_desc->read.buffer_addr[j + 1] =
721 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 722 }
723
c2fed996
JK		 724 skb = __netdev_alloc_skb_ip_align(netdev,
725 adapter->rx_ps_bsize0,
726 gfp);
bc7f75fa
AK		 727
728 if (!skb) {
729 adapter->alloc_rx_buff_failed++;
730 break;
731 }
732
bc7f75fa 733 buffer_info->skb = skb;
0be3f55f 734 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 735 adapter->rx_ps_bsize0,
0be3f55f
NN		 736 DMA_FROM_DEVICE);
737 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 738 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 739 adapter->rx_dma_failed++;
740 /* cleanup skb */
741 dev_kfree_skb_any(skb);
742 buffer_info->skb = NULL;
743 break;
744 }
745
746 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
747
50849d79
TH		 748 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
749 /*
750 * Force memory writes to complete before letting h/w
751 * know there are new descriptors to fetch. (Only
752 * applicable for weak-ordered memory model archs,
753 * such as IA-64).
754 */
755 wmb();
c6e7f51e 756 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 757 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 758 else
c5083cf6 759 writel(i << 1, rx_ring->tail);
50849d79
TH		 760 }
761
bc7f75fa
AK		 762 i++;
763 if (i == rx_ring->count)
764 i = 0;
765 buffer_info = &rx_ring->buffer_info[i];
766 }
767
768no_buffers:
50849d79 769 rx_ring->next_to_use = i;
bc7f75fa
AK		 770}
771
97ac8cae
BA		 772/**
773 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 774 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 775 * @cleaned_count: number of buffers to allocate this pass
776 **/
777
55aa6985 778static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 779 int cleaned_count, gfp_t gfp)
97ac8cae 780{
55aa6985 781 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 782 struct net_device *netdev = adapter->netdev;
783 struct pci_dev *pdev = adapter->pdev;
5f450212 784 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 785 struct e1000_buffer *buffer_info;
786 struct sk_buff *skb;
787 unsigned int i;
89d71a66 788 unsigned int bufsz = 256 - 16 /* for skb_reserve */;
97ac8cae
BA		 789
790 i = rx_ring->next_to_use;
791 buffer_info = &rx_ring->buffer_info[i];
792
793 while (cleaned_count--) {
794 skb = buffer_info->skb;
795 if (skb) {
796 skb_trim(skb, 0);
797 goto check_page;
798 }
799
c2fed996 800 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 801 if (unlikely(!skb)) {
802 /* Better luck next round */
803 adapter->alloc_rx_buff_failed++;
804 break;
805 }
806
97ac8cae
BA		 807 buffer_info->skb = skb;
808check_page:
809 /* allocate a new page if necessary */
810 if (!buffer_info->page) {
c2fed996 811 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 812 if (unlikely(!buffer_info->page)) {
813 adapter->alloc_rx_buff_failed++;
814 break;
815 }
816 }
817
818 if (!buffer_info->dma)
0be3f55f 819 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 820 buffer_info->page, 0,
821 PAGE_SIZE,
0be3f55f 822 DMA_FROM_DEVICE);
97ac8cae 823
5f450212
BA		 824 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
825 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 826
827 if (unlikely(++i == rx_ring->count))
828 i = 0;
829 buffer_info = &rx_ring->buffer_info[i];
830 }
831
832 if (likely(rx_ring->next_to_use != i)) {
833 rx_ring->next_to_use = i;
834 if (unlikely(i-- == 0))
835 i = (rx_ring->count - 1);
836
837 /* Force memory writes to complete before letting h/w
838 * know there are new descriptors to fetch. (Only
839 * applicable for weak-ordered memory model archs,
840 * such as IA-64). */
841 wmb();
c6e7f51e 842 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 843 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 844 else
c5083cf6 845 writel(i, rx_ring->tail);
97ac8cae
BA		 846 }
847}
848
70495a50
BA		 849static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
850 struct sk_buff *skb)
851{
852 if (netdev->features & NETIF_F_RXHASH)
853 skb->rxhash = le32_to_cpu(rss);
854}
855
bc7f75fa 856/**
55aa6985
BA		 857 * e1000_clean_rx_irq - Send received data up the network stack
858 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 859 *
860 * the return value indicates whether actual cleaning was done, there
861 * is no guarantee that everything was cleaned
862 **/
55aa6985
BA		 863static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
864 int work_to_do)
bc7f75fa 865{
55aa6985 866 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 867 struct net_device *netdev = adapter->netdev;
868 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 869 struct e1000_hw *hw = &adapter->hw;
5f450212 870 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 871 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 872 u32 length, staterr;
bc7f75fa
AK		 873 unsigned int i;
874 int cleaned_count = 0;
3db1cd5c 875 bool cleaned = false;
bc7f75fa
AK		 876 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
877
878 i = rx_ring->next_to_clean;
5f450212
BA		 879 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
880 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 881 buffer_info = &rx_ring->buffer_info[i];
882
5f450212 883 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 884 struct sk_buff *skb;
bc7f75fa
AK		 885
886 if (*work_done >= work_to_do)
887 break;
888 (*work_done)++;
2d0bb1c1 889 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 890
bc7f75fa
AK		 891 skb = buffer_info->skb;
892 buffer_info->skb = NULL;
893
894 prefetch(skb->data - NET_IP_ALIGN);
895
896 i++;
897 if (i == rx_ring->count)
898 i = 0;
5f450212 899 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 900 prefetch(next_rxd);
901
902 next_buffer = &rx_ring->buffer_info[i];
903
3db1cd5c 904 cleaned = true;
bc7f75fa 905 cleaned_count++;
0be3f55f 906 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 907 buffer_info->dma,
908 adapter->rx_buffer_len,
0be3f55f 909 DMA_FROM_DEVICE);
bc7f75fa
AK		 910 buffer_info->dma = 0;
911
5f450212 912 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 913
b94b5028
JB		 914 /*
915 * !EOP means multiple descriptors were used to store a single
916 * packet, if that's the case we need to toss it. In fact, we
917 * need to toss every packet with the EOP bit clear and the
918 * next frame that _does_ have the EOP bit set, as it is by
919 * definition only a frame fragment
920 */
5f450212 921 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 922 adapter->flags2 |= FLAG2_IS_DISCARDING;
923
924 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 925 /* All receives must fit into a single buffer */
3bb99fe2 926 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 927 /* recycle */
928 buffer_info->skb = skb;
5f450212 929 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 930 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 931 goto next_desc;
932 }
933
cf955e6c
BG		 934 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
935 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 936 /* recycle */
937 buffer_info->skb = skb;
938 goto next_desc;
939 }
940
eb7c3adb 941 /* adjust length to remove Ethernet CRC */
0184039a
BG		 942 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
943 /* If configured to store CRC, don't subtract FCS,
944 * but keep the FCS bytes out of the total_rx_bytes
945 * counter
946 */
947 if (netdev->features & NETIF_F_RXFCS)
948 total_rx_bytes -= 4;
949 else
950 length -= 4;
951 }
eb7c3adb 952
bc7f75fa
AK		 953 total_rx_bytes += length;
954 total_rx_packets++;
955
ad68076e
BA		 956 /*
957 * code added for copybreak, this should improve
bc7f75fa 958 * performance for small packets with large amounts
ad68076e
BA		 959 * of reassembly being done in the stack
960 */
bc7f75fa
AK		 961 if (length < copybreak) {
962 struct sk_buff *new_skb =
89d71a66 963 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 964 if (new_skb) {
808ff676
BA		 965 skb_copy_to_linear_data_offset(new_skb,
966 -NET_IP_ALIGN,
967 (skb->data -
968 NET_IP_ALIGN),
969 (length +
970 NET_IP_ALIGN));
bc7f75fa
AK		 971 /* save the skb in buffer_info as good */
972 buffer_info->skb = skb;
973 skb = new_skb;
974 }
975 /* else just continue with the old one */
976 }
977 /* end copybreak code */
978 skb_put(skb, length);
979
980 /* Receive Checksum Offload */
5f450212 981 e1000_rx_checksum(adapter, staterr,
afd12939 982 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 983
70495a50
BA		 984 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
985
5f450212
BA		 986 e1000_receive_skb(adapter, netdev, skb, staterr,
987 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 988
989next_desc:
5f450212 990 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 991
992 /* return some buffers to hardware, one at a time is too slow */
993 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 994 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 995 GFP_ATOMIC);
bc7f75fa
AK		 996 cleaned_count = 0;
997 }
998
999 /* use prefetched values */
1000 rx_desc = next_rxd;
1001 buffer_info = next_buffer;
5f450212
BA		 1002
1003 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1004 }
1005 rx_ring->next_to_clean = i;
1006
1007 cleaned_count = e1000_desc_unused(rx_ring);
1008 if (cleaned_count)
55aa6985 1009 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1010
bc7f75fa 1011 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1012 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1013 return cleaned;
1014}
1015
55aa6985
BA		 1016static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1017 struct e1000_buffer *buffer_info)
bc7f75fa 1018{
55aa6985
BA		 1019 struct e1000_adapter *adapter = tx_ring->adapter;
1020
03b1320d
AD		 1021 if (buffer_info->dma) {
1022 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1023 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1024 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1025 else
0be3f55f
NN		 1026 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1027 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1028 buffer_info->dma = 0;
1029 }
bc7f75fa
AK		 1030 if (buffer_info->skb) {
1031 dev_kfree_skb_any(buffer_info->skb);
1032 buffer_info->skb = NULL;
1033 }
1b7719c4 1034 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1035}
1036
41cec6f1 1037static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1038{
41cec6f1
BA		 1039 struct e1000_adapter *adapter = container_of(work,
1040 struct e1000_adapter,
1041 print_hang_task);
09357b00 1042 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1043 struct e1000_ring *tx_ring = adapter->tx_ring;
1044 unsigned int i = tx_ring->next_to_clean;
1045 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1046 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1047 struct e1000_hw *hw = &adapter->hw;
1048 u16 phy_status, phy_1000t_status, phy_ext_status;
1049 u16 pci_status;
1050
615b32af
JB		 1051 if (test_bit(__E1000_DOWN, &adapter->state))
1052 return;
1053
09357b00
JK		 1054 if (!adapter->tx_hang_recheck &&
1055 (adapter->flags2 & FLAG2_DMA_BURST)) {
1056 /* May be block on write-back, flush and detect again
1057 * flush pending descriptor writebacks to memory
1058 */
1059 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1060 /* execute the writes immediately */
1061 e1e_flush();
1062 adapter->tx_hang_recheck = true;
1063 return;
1064 }
1065 /* Real hang detected */
1066 adapter->tx_hang_recheck = false;
1067 netif_stop_queue(netdev);
1068
41cec6f1
BA		 1069 e1e_rphy(hw, PHY_STATUS, &phy_status);
1070 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1071 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1072
41cec6f1
BA		 1073 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1074
1075 /* detected Hardware unit hang */
1076 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1077 " TDH <%x>\n"
1078 " TDT <%x>\n"
1079 " next_to_use <%x>\n"
1080 " next_to_clean <%x>\n"
1081 "buffer_info[next_to_clean]:\n"
1082 " time_stamp <%lx>\n"
1083 " next_to_watch <%x>\n"
1084 " jiffies <%lx>\n"
41cec6f1
BA		 1085 " next_to_watch.status <%x>\n"
1086 "MAC Status <%x>\n"
1087 "PHY Status <%x>\n"
1088 "PHY 1000BASE-T Status <%x>\n"
1089 "PHY Extended Status <%x>\n"
1090 "PCI Status <%x>\n",
c5083cf6
BA		 1091 readl(tx_ring->head),
1092 readl(tx_ring->tail),
44defeb3
JK		 1093 tx_ring->next_to_use,
1094 tx_ring->next_to_clean,
1095 tx_ring->buffer_info[eop].time_stamp,
1096 eop,
1097 jiffies,
41cec6f1
BA		 1098 eop_desc->upper.fields.status,
1099 er32(STATUS),
1100 phy_status,
1101 phy_1000t_status,
1102 phy_ext_status,
1103 pci_status);
bc7f75fa
AK		 1104}
1105
1106/**
1107 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1108 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1109 *
1110 * the return value indicates whether actual cleaning was done, there
1111 * is no guarantee that everything was cleaned
1112 **/
55aa6985 1113static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1114{
55aa6985 1115 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1116 struct net_device *netdev = adapter->netdev;
1117 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1118 struct e1000_tx_desc *tx_desc, *eop_desc;
1119 struct e1000_buffer *buffer_info;
1120 unsigned int i, eop;
1121 unsigned int count = 0;
bc7f75fa 1122 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1123 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1124
1125 i = tx_ring->next_to_clean;
1126 eop = tx_ring->buffer_info[i].next_to_watch;
1127 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1128
12d04a3c
AD		 1129 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1130 (count < tx_ring->count)) {
a86043c2 1131 bool cleaned = false;
2d0bb1c1 1132 rmb(); /* read buffer_info after eop_desc */
a86043c2 1133 for (; !cleaned; count++) {
bc7f75fa
AK		 1134 tx_desc = E1000_TX_DESC(*tx_ring, i);
1135 buffer_info = &tx_ring->buffer_info[i];
1136 cleaned = (i == eop);
1137
1138 if (cleaned) {
9ed318d5
TH		 1139 total_tx_packets += buffer_info->segs;
1140 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1141 if (buffer_info->skb) {
1142 bytes_compl += buffer_info->skb->len;
1143 pkts_compl++;
1144 }
bc7f75fa
AK		 1145 }
1146
55aa6985 1147 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1148 tx_desc->upper.data = 0;
1149
1150 i++;
1151 if (i == tx_ring->count)
1152 i = 0;
1153 }
1154
dac87619
TL		 1155 if (i == tx_ring->next_to_use)
1156 break;
bc7f75fa
AK		 1157 eop = tx_ring->buffer_info[i].next_to_watch;
1158 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1159 }
1160
1161 tx_ring->next_to_clean = i;
1162
3f0cfa3b
TH		 1163 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1164
bc7f75fa 1165#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1166 if (count && netif_carrier_ok(netdev) &&
1167 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1168 /* Make sure that anybody stopping the queue after this
1169 * sees the new next_to_clean.
1170 */
1171 smp_mb();
1172
1173 if (netif_queue_stopped(netdev) &&
1174 !(test_bit(__E1000_DOWN, &adapter->state))) {
1175 netif_wake_queue(netdev);
1176 ++adapter->restart_queue;
1177 }
1178 }
1179
1180 if (adapter->detect_tx_hung) {
41cec6f1
BA		 1181 /*
1182 * Detect a transmit hang in hardware, this serializes the
1183 * check with the clearing of time_stamp and movement of i
1184 */
3db1cd5c 1185 adapter->detect_tx_hung = false;
12d04a3c
AD		 1186 if (tx_ring->buffer_info[i].time_stamp &&
1187 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1188 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1189 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1190 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1191 else
1192 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1193 }
1194 adapter->total_tx_bytes += total_tx_bytes;
1195 adapter->total_tx_packets += total_tx_packets;
807540ba 1196 return count < tx_ring->count;
bc7f75fa
AK		 1197}
1198
bc7f75fa
AK		 1199/**
1200 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1201 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1202 *
1203 * the return value indicates whether actual cleaning was done, there
1204 * is no guarantee that everything was cleaned
1205 **/
55aa6985
BA		 1206static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1207 int work_to_do)
bc7f75fa 1208{
55aa6985 1209 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1210 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1211 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1212 struct net_device *netdev = adapter->netdev;
1213 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1214 struct e1000_buffer *buffer_info, *next_buffer;
1215 struct e1000_ps_page *ps_page;
1216 struct sk_buff *skb;
1217 unsigned int i, j;
1218 u32 length, staterr;
1219 int cleaned_count = 0;
3db1cd5c 1220 bool cleaned = false;
bc7f75fa
AK		 1221 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1222
1223 i = rx_ring->next_to_clean;
1224 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1225 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1226 buffer_info = &rx_ring->buffer_info[i];
1227
1228 while (staterr & E1000_RXD_STAT_DD) {
1229 if (*work_done >= work_to_do)
1230 break;
1231 (*work_done)++;
1232 skb = buffer_info->skb;
2d0bb1c1 1233 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1234
1235 /* in the packet split case this is header only */
1236 prefetch(skb->data - NET_IP_ALIGN);
1237
1238 i++;
1239 if (i == rx_ring->count)
1240 i = 0;
1241 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1242 prefetch(next_rxd);
1243
1244 next_buffer = &rx_ring->buffer_info[i];
1245
3db1cd5c 1246 cleaned = true;
bc7f75fa 1247 cleaned_count++;
0be3f55f 1248 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1249 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1250 buffer_info->dma = 0;
1251
af667a29 1252 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1253 if (!(staterr & E1000_RXD_STAT_EOP))
1254 adapter->flags2 |= FLAG2_IS_DISCARDING;
1255
1256 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1257 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1258 dev_kfree_skb_irq(skb);
b94b5028
JB		 1259 if (staterr & E1000_RXD_STAT_EOP)
1260 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1261 goto next_desc;
1262 }
1263
cf955e6c
BG		 1264 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1265 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1266 dev_kfree_skb_irq(skb);
1267 goto next_desc;
1268 }
1269
1270 length = le16_to_cpu(rx_desc->wb.middle.length0);
1271
1272 if (!length) {
ef456f85 1273 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1274 dev_kfree_skb_irq(skb);
1275 goto next_desc;
1276 }
1277
1278 /* Good Receive */
1279 skb_put(skb, length);
1280
1281 {
0e15df49
BA		 1282 /*
1283 * this looks ugly, but it seems compiler issues make
1284 * it more efficient than reusing j
1285 */
1286 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1287
ad68076e 1288 /*
0e15df49
BA		 1289 * page alloc/put takes too long and effects small
1290 * packet throughput, so unsplit small packets and
1291 * save the alloc/put only valid in softirq (napi)
1292 * context to call kmap_*
ad68076e 1293 */
0e15df49
BA		 1294 if (l1 && (l1 <= copybreak) &&
1295 ((length + l1) <= adapter->rx_ps_bsize0)) {
1296 u8 *vaddr;
1297
1298 ps_page = &buffer_info->ps_pages[0];
1299
1300 /*
1301 * there is no documentation about how to call
1302 * kmap_atomic, so we can't hold the mapping
1303 * very long
1304 */
1305 dma_sync_single_for_cpu(&pdev->dev,
1306 ps_page->dma,
1307 PAGE_SIZE,
1308 DMA_FROM_DEVICE);
9f393834 1309 vaddr = kmap_atomic(ps_page->page);
0e15df49 1310 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1311 kunmap_atomic(vaddr);
0e15df49
BA		 1312 dma_sync_single_for_device(&pdev->dev,
1313 ps_page->dma,
1314 PAGE_SIZE,
1315 DMA_FROM_DEVICE);
1316
1317 /* remove the CRC */
0184039a
BG		 1318 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1319 if (!(netdev->features & NETIF_F_RXFCS))
1320 l1 -= 4;
1321 }
0e15df49
BA		 1322
1323 skb_put(skb, l1);
1324 goto copydone;
1325 } /* if */
bc7f75fa
AK		 1326 }
1327
1328 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1329 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1330 if (!length)
1331 break;
1332
47f44e40 1333 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1334 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1335 DMA_FROM_DEVICE);
bc7f75fa
AK		 1336 ps_page->dma = 0;
1337 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1338 ps_page->page = NULL;
1339 skb->len += length;
1340 skb->data_len += length;
98a045d7 1341 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1342 }
1343
eb7c3adb
JK		 1344 /* strip the ethernet crc, problem is we're using pages now so
1345 * this whole operation can get a little cpu intensive
1346 */
0184039a
BG		 1347 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1348 if (!(netdev->features & NETIF_F_RXFCS))
1349 pskb_trim(skb, skb->len - 4);
1350 }
eb7c3adb 1351
bc7f75fa
AK		 1352copydone:
1353 total_rx_bytes += skb->len;
1354 total_rx_packets++;
1355
afd12939
BA		 1356 e1000_rx_checksum(adapter, staterr,
1357 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 1358
70495a50
BA		 1359 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1360
bc7f75fa
AK		 1361 if (rx_desc->wb.upper.header_status &
1362 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1363 adapter->rx_hdr_split++;
1364
1365 e1000_receive_skb(adapter, netdev, skb,
1366 staterr, rx_desc->wb.middle.vlan);
1367
1368next_desc:
1369 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1370 buffer_info->skb = NULL;
1371
1372 /* return some buffers to hardware, one at a time is too slow */
1373 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1374 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1375 GFP_ATOMIC);
bc7f75fa
AK		 1376 cleaned_count = 0;
1377 }
1378
1379 /* use prefetched values */
1380 rx_desc = next_rxd;
1381 buffer_info = next_buffer;
1382
1383 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1384 }
1385 rx_ring->next_to_clean = i;
1386
1387 cleaned_count = e1000_desc_unused(rx_ring);
1388 if (cleaned_count)
55aa6985 1389 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1390
bc7f75fa 1391 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1392 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1393 return cleaned;
1394}
1395
97ac8cae
BA		 1396/**
1397 * e1000_consume_page - helper function
1398 **/
1399static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1400 u16 length)
1401{
1402 bi->page = NULL;
1403 skb->len += length;
1404 skb->data_len += length;
98a045d7 1405 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1406}
1407
1408/**
1409 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1410 * @adapter: board private structure
1411 *
1412 * the return value indicates whether actual cleaning was done, there
1413 * is no guarantee that everything was cleaned
1414 **/
55aa6985
BA		 1415static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1416 int work_to_do)
97ac8cae 1417{
55aa6985 1418 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1419 struct net_device *netdev = adapter->netdev;
1420 struct pci_dev *pdev = adapter->pdev;
5f450212 1421 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1422 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1423 u32 length, staterr;
97ac8cae
BA		 1424 unsigned int i;
1425 int cleaned_count = 0;
1426 bool cleaned = false;
1427 unsigned int total_rx_bytes=0, total_rx_packets=0;
1428
1429 i = rx_ring->next_to_clean;
5f450212
BA		 1430 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1431 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1432 buffer_info = &rx_ring->buffer_info[i];
1433
5f450212 1434 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1435 struct sk_buff *skb;
97ac8cae
BA		 1436
1437 if (*work_done >= work_to_do)
1438 break;
1439 (*work_done)++;
2d0bb1c1 1440 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1441
97ac8cae
BA		 1442 skb = buffer_info->skb;
1443 buffer_info->skb = NULL;
1444
1445 ++i;
1446 if (i == rx_ring->count)
1447 i = 0;
5f450212 1448 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1449 prefetch(next_rxd);
1450
1451 next_buffer = &rx_ring->buffer_info[i];
1452
1453 cleaned = true;
1454 cleaned_count++;
0be3f55f
NN		 1455 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1456 DMA_FROM_DEVICE);
97ac8cae
BA		 1457 buffer_info->dma = 0;
1458
5f450212 1459 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1460
1461 /* errors is only valid for DD + EOP descriptors */
5f450212 1462 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1463 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1464 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1465 /* recycle both page and skb */
1466 buffer_info->skb = skb;
1467 /* an error means any chain goes out the window too */
1468 if (rx_ring->rx_skb_top)
1469 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1470 rx_ring->rx_skb_top = NULL;
1471 goto next_desc;
97ac8cae
BA		 1472 }
1473
f0f1a172 1474#define rxtop (rx_ring->rx_skb_top)
5f450212 1475 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1476 /* this descriptor is only the beginning (or middle) */
1477 if (!rxtop) {
1478 /* this is the beginning of a chain */
1479 rxtop = skb;
1480 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1481 0, length);
1482 } else {
1483 /* this is the middle of a chain */
1484 skb_fill_page_desc(rxtop,
1485 skb_shinfo(rxtop)->nr_frags,
1486 buffer_info->page, 0, length);
1487 /* re-use the skb, only consumed the page */
1488 buffer_info->skb = skb;
1489 }
1490 e1000_consume_page(buffer_info, rxtop, length);
1491 goto next_desc;
1492 } else {
1493 if (rxtop) {
1494 /* end of the chain */
1495 skb_fill_page_desc(rxtop,
1496 skb_shinfo(rxtop)->nr_frags,
1497 buffer_info->page, 0, length);
1498 /* re-use the current skb, we only consumed the
1499 * page */
1500 buffer_info->skb = skb;
1501 skb = rxtop;
1502 rxtop = NULL;
1503 e1000_consume_page(buffer_info, skb, length);
1504 } else {
1505 /* no chain, got EOP, this buf is the packet
1506 * copybreak to save the put_page/alloc_page */
1507 if (length <= copybreak &&
1508 skb_tailroom(skb) >= length) {
1509 u8 *vaddr;
4679026d 1510 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1511 memcpy(skb_tail_pointer(skb), vaddr,
1512 length);
4679026d 1513 kunmap_atomic(vaddr);
97ac8cae
BA		 1514 /* re-use the page, so don't erase
1515 * buffer_info->page */
1516 skb_put(skb, length);
1517 } else {
1518 skb_fill_page_desc(skb, 0,
1519 buffer_info->page, 0,
1520 length);
1521 e1000_consume_page(buffer_info, skb,
1522 length);
1523 }
1524 }
1525 }
1526
1527 /* Receive Checksum Offload XXX recompute due to CRC strip? */
5f450212 1528 e1000_rx_checksum(adapter, staterr,
afd12939 1529 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
97ac8cae 1530
70495a50
BA		 1531 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1532
97ac8cae
BA		 1533 /* probably a little skewed due to removing CRC */
1534 total_rx_bytes += skb->len;
1535 total_rx_packets++;
1536
1537 /* eth type trans needs skb->data to point to something */
1538 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1539 e_err("pskb_may_pull failed.\n");
ef5ab89c 1540 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1541 goto next_desc;
1542 }
1543
5f450212
BA		 1544 e1000_receive_skb(adapter, netdev, skb, staterr,
1545 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1546
1547next_desc:
5f450212 1548 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1549
1550 /* return some buffers to hardware, one at a time is too slow */
1551 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1552 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1553 GFP_ATOMIC);
97ac8cae
BA		 1554 cleaned_count = 0;
1555 }
1556
1557 /* use prefetched values */
1558 rx_desc = next_rxd;
1559 buffer_info = next_buffer;
5f450212
BA		 1560
1561 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1562 }
1563 rx_ring->next_to_clean = i;
1564
1565 cleaned_count = e1000_desc_unused(rx_ring);
1566 if (cleaned_count)
55aa6985 1567 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1568
1569 adapter->total_rx_bytes += total_rx_bytes;
1570 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1571 return cleaned;
1572}
1573
bc7f75fa
AK		 1574/**
1575 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1576 * @rx_ring: Rx descriptor ring
bc7f75fa 1577 **/
55aa6985 1578static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1579{
55aa6985 1580 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1581 struct e1000_buffer *buffer_info;
1582 struct e1000_ps_page *ps_page;
1583 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1584 unsigned int i, j;
1585
1586 /* Free all the Rx ring sk_buffs */
1587 for (i = 0; i < rx_ring->count; i++) {
1588 buffer_info = &rx_ring->buffer_info[i];
1589 if (buffer_info->dma) {
1590 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1591 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1592 adapter->rx_buffer_len,
0be3f55f 1593 DMA_FROM_DEVICE);
97ac8cae 1594 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1595 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1596 PAGE_SIZE,
0be3f55f 1597 DMA_FROM_DEVICE);
bc7f75fa 1598 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1599 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1600 adapter->rx_ps_bsize0,
0be3f55f 1601 DMA_FROM_DEVICE);
bc7f75fa
AK		 1602 buffer_info->dma = 0;
1603 }
1604
97ac8cae
BA		 1605 if (buffer_info->page) {
1606 put_page(buffer_info->page);
1607 buffer_info->page = NULL;
1608 }
1609
bc7f75fa
AK		 1610 if (buffer_info->skb) {
1611 dev_kfree_skb(buffer_info->skb);
1612 buffer_info->skb = NULL;
1613 }
1614
1615 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1616 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1617 if (!ps_page->page)
1618 break;
0be3f55f
NN		 1619 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1620 DMA_FROM_DEVICE);
bc7f75fa
AK		 1621 ps_page->dma = 0;
1622 put_page(ps_page->page);
1623 ps_page->page = NULL;
1624 }
1625 }
1626
1627 /* there also may be some cached data from a chained receive */
1628 if (rx_ring->rx_skb_top) {
1629 dev_kfree_skb(rx_ring->rx_skb_top);
1630 rx_ring->rx_skb_top = NULL;
1631 }
1632
bc7f75fa
AK		 1633 /* Zero out the descriptor ring */
1634 memset(rx_ring->desc, 0, rx_ring->size);
1635
1636 rx_ring->next_to_clean = 0;
1637 rx_ring->next_to_use = 0;
b94b5028 1638 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1639
c5083cf6
BA		 1640 writel(0, rx_ring->head);
1641 writel(0, rx_ring->tail);
bc7f75fa
AK		 1642}
1643
a8f88ff5
JB		 1644static void e1000e_downshift_workaround(struct work_struct *work)
1645{
1646 struct e1000_adapter *adapter = container_of(work,
1647 struct e1000_adapter, downshift_task);
1648
615b32af
JB		 1649 if (test_bit(__E1000_DOWN, &adapter->state))
1650 return;
1651
a8f88ff5
JB		 1652 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1653}
1654
bc7f75fa
AK		 1655/**
1656 * e1000_intr_msi - Interrupt Handler
1657 * @irq: interrupt number
1658 * @data: pointer to a network interface device structure
1659 **/
1660static irqreturn_t e1000_intr_msi(int irq, void *data)
1661{
1662 struct net_device *netdev = data;
1663 struct e1000_adapter *adapter = netdev_priv(netdev);
1664 struct e1000_hw *hw = &adapter->hw;
1665 u32 icr = er32(ICR);
1666
ad68076e
BA		 1667 /*
1668 * read ICR disables interrupts using IAM
1669 */
bc7f75fa 1670
573cca8c 1671 if (icr & E1000_ICR_LSC) {
f92518dd 1672 hw->mac.get_link_status = true;
ad68076e
BA		 1673 /*
1674 * ICH8 workaround-- Call gig speed drop workaround on cable
1675 * disconnect (LSC) before accessing any PHY registers
1676 */
bc7f75fa
AK		 1677 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1678 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1679 schedule_work(&adapter->downshift_task);
bc7f75fa 1680
ad68076e
BA		 1681 /*
1682 * 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1683 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1684 * adapter in watchdog
1685 */
bc7f75fa
AK		 1686 if (netif_carrier_ok(netdev) &&
1687 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1688 /* disable receives */
1689 u32 rctl = er32(RCTL);
1690 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1691 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1692 }
1693 /* guard against interrupt when we're going down */
1694 if (!test_bit(__E1000_DOWN, &adapter->state))
1695 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1696 }
1697
288379f0 1698 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1699 adapter->total_tx_bytes = 0;
1700 adapter->total_tx_packets = 0;
1701 adapter->total_rx_bytes = 0;
1702 adapter->total_rx_packets = 0;
288379f0 1703 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1704 }
1705
1706 return IRQ_HANDLED;
1707}
1708
1709/**
1710 * e1000_intr - Interrupt Handler
1711 * @irq: interrupt number
1712 * @data: pointer to a network interface device structure
1713 **/
1714static irqreturn_t e1000_intr(int irq, void *data)
1715{
1716 struct net_device *netdev = data;
1717 struct e1000_adapter *adapter = netdev_priv(netdev);
1718 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1719 u32 rctl, icr = er32(ICR);
4662e82b 1720
a68ea775 1721 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1722 return IRQ_NONE; /* Not our interrupt */
1723
ad68076e
BA		 1724 /*
1725 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1726 * not set, then the adapter didn't send an interrupt
1727 */
bc7f75fa
AK		 1728 if (!(icr & E1000_ICR_INT_ASSERTED))
1729 return IRQ_NONE;
1730
ad68076e
BA		 1731 /*
1732 * Interrupt Auto-Mask...upon reading ICR,
1733 * interrupts are masked. No need for the
1734 * IMC write
1735 */
bc7f75fa 1736
573cca8c 1737 if (icr & E1000_ICR_LSC) {
f92518dd 1738 hw->mac.get_link_status = true;
ad68076e
BA		 1739 /*
1740 * ICH8 workaround-- Call gig speed drop workaround on cable
1741 * disconnect (LSC) before accessing any PHY registers
1742 */
bc7f75fa
AK		 1743 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1744 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1745 schedule_work(&adapter->downshift_task);
bc7f75fa 1746
ad68076e
BA		 1747 /*
1748 * 80003ES2LAN workaround--
bc7f75fa
AK		 1749 * For packet buffer work-around on link down event;
1750 * disable receives here in the ISR and
1751 * reset adapter in watchdog
1752 */
1753 if (netif_carrier_ok(netdev) &&
1754 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1755 /* disable receives */
1756 rctl = er32(RCTL);
1757 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1758 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1759 }
1760 /* guard against interrupt when we're going down */
1761 if (!test_bit(__E1000_DOWN, &adapter->state))
1762 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1763 }
1764
288379f0 1765 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1766 adapter->total_tx_bytes = 0;
1767 adapter->total_tx_packets = 0;
1768 adapter->total_rx_bytes = 0;
1769 adapter->total_rx_packets = 0;
288379f0 1770 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1771 }
1772
1773 return IRQ_HANDLED;
1774}
1775
4662e82b
BA		 1776static irqreturn_t e1000_msix_other(int irq, void *data)
1777{
1778 struct net_device *netdev = data;
1779 struct e1000_adapter *adapter = netdev_priv(netdev);
1780 struct e1000_hw *hw = &adapter->hw;
1781 u32 icr = er32(ICR);
1782
1783 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1784 if (!test_bit(__E1000_DOWN, &adapter->state))
1785 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1786 return IRQ_NONE;
1787 }
1788
1789 if (icr & adapter->eiac_mask)
1790 ew32(ICS, (icr & adapter->eiac_mask));
1791
1792 if (icr & E1000_ICR_OTHER) {
1793 if (!(icr & E1000_ICR_LSC))
1794 goto no_link_interrupt;
f92518dd 1795 hw->mac.get_link_status = true;
4662e82b
BA		 1796 /* guard against interrupt when we're going down */
1797 if (!test_bit(__E1000_DOWN, &adapter->state))
1798 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1799 }
1800
1801no_link_interrupt:
a3c69fef
JB		 1802 if (!test_bit(__E1000_DOWN, &adapter->state))
1803 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1804
1805 return IRQ_HANDLED;
1806}
1807
1808
1809static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1810{
1811 struct net_device *netdev = data;
1812 struct e1000_adapter *adapter = netdev_priv(netdev);
1813 struct e1000_hw *hw = &adapter->hw;
1814 struct e1000_ring *tx_ring = adapter->tx_ring;
1815
1816
1817 adapter->total_tx_bytes = 0;
1818 adapter->total_tx_packets = 0;
1819
55aa6985 1820 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1821 /* Ring was not completely cleaned, so fire another interrupt */
1822 ew32(ICS, tx_ring->ims_val);
1823
1824 return IRQ_HANDLED;
1825}
1826
1827static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1828{
1829 struct net_device *netdev = data;
1830 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1831 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1832
1833 /* Write the ITR value calculated at the end of the
1834 * previous interrupt.
1835 */
55aa6985
BA		 1836 if (rx_ring->set_itr) {
1837 writel(1000000000 / (rx_ring->itr_val * 256),
1838 rx_ring->itr_register);
1839 rx_ring->set_itr = 0;
4662e82b
BA		 1840 }
1841
288379f0 1842 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1843 adapter->total_rx_bytes = 0;
1844 adapter->total_rx_packets = 0;
288379f0 1845 __napi_schedule(&adapter->napi);
4662e82b
BA		 1846 }
1847 return IRQ_HANDLED;
1848}
1849
1850/**
1851 * e1000_configure_msix - Configure MSI-X hardware
1852 *
1853 * e1000_configure_msix sets up the hardware to properly
1854 * generate MSI-X interrupts.
1855 **/
1856static void e1000_configure_msix(struct e1000_adapter *adapter)
1857{
1858 struct e1000_hw *hw = &adapter->hw;
1859 struct e1000_ring *rx_ring = adapter->rx_ring;
1860 struct e1000_ring *tx_ring = adapter->tx_ring;
1861 int vector = 0;
1862 u32 ctrl_ext, ivar = 0;
1863
1864 adapter->eiac_mask = 0;
1865
1866 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1867 if (hw->mac.type == e1000_82574) {
1868 u32 rfctl = er32(RFCTL);
1869 rfctl |= E1000_RFCTL_ACK_DIS;
1870 ew32(RFCTL, rfctl);
1871 }
1872
1873#define E1000_IVAR_INT_ALLOC_VALID 0x8
1874 /* Configure Rx vector */
1875 rx_ring->ims_val = E1000_IMS_RXQ0;
1876 adapter->eiac_mask |= rx_ring->ims_val;
1877 if (rx_ring->itr_val)
1878 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1879 rx_ring->itr_register);
4662e82b 1880 else
c5083cf6 1881 writel(1, rx_ring->itr_register);
4662e82b
BA		 1882 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1883
1884 /* Configure Tx vector */
1885 tx_ring->ims_val = E1000_IMS_TXQ0;
1886 vector++;
1887 if (tx_ring->itr_val)
1888 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1889 tx_ring->itr_register);
4662e82b 1890 else
c5083cf6 1891 writel(1, tx_ring->itr_register);
4662e82b
BA		 1892 adapter->eiac_mask |= tx_ring->ims_val;
1893 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1894
1895 /* set vector for Other Causes, e.g. link changes */
1896 vector++;
1897 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1898 if (rx_ring->itr_val)
1899 writel(1000000000 / (rx_ring->itr_val * 256),
1900 hw->hw_addr + E1000_EITR_82574(vector));
1901 else
1902 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1903
1904 /* Cause Tx interrupts on every write back */
1905 ivar |= (1 << 31);
1906
1907 ew32(IVAR, ivar);
1908
1909 /* enable MSI-X PBA support */
1910 ctrl_ext = er32(CTRL_EXT);
1911 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1912
1913 /* Auto-Mask Other interrupts upon ICR read */
1914#define E1000_EIAC_MASK_82574 0x01F00000
1915 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1916 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1917 ew32(CTRL_EXT, ctrl_ext);
1918 e1e_flush();
1919}
1920
1921void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
1922{
1923 if (adapter->msix_entries) {
1924 pci_disable_msix(adapter->pdev);
1925 kfree(adapter->msix_entries);
1926 adapter->msix_entries = NULL;
1927 } else if (adapter->flags & FLAG_MSI_ENABLED) {
1928 pci_disable_msi(adapter->pdev);
1929 adapter->flags &= ~FLAG_MSI_ENABLED;
1930 }
4662e82b
BA		 1931}
1932
1933/**
1934 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1935 *
1936 * Attempt to configure interrupts using the best available
1937 * capabilities of the hardware and kernel.
1938 **/
1939void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
1940{
1941 int err;
8e86acd7 1942 int i;
4662e82b
BA		 1943
1944 switch (adapter->int_mode) {
1945 case E1000E_INT_MODE_MSIX:
1946 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 1947 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
1948 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 1949 sizeof(struct msix_entry),
1950 GFP_KERNEL);
1951 if (adapter->msix_entries) {
8e86acd7 1952 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 1953 adapter->msix_entries[i].entry = i;
1954
1955 err = pci_enable_msix(adapter->pdev,
1956 adapter->msix_entries,
8e86acd7 1957 adapter->num_vectors);
b1cdfead 1958 if (err == 0)
4662e82b
BA		 1959 return;
1960 }
1961 /* MSI-X failed, so fall through and try MSI */
ef456f85 1962 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 1963 e1000e_reset_interrupt_capability(adapter);
1964 }
1965 adapter->int_mode = E1000E_INT_MODE_MSI;
1966 /* Fall through */
1967 case E1000E_INT_MODE_MSI:
1968 if (!pci_enable_msi(adapter->pdev)) {
1969 adapter->flags |= FLAG_MSI_ENABLED;
1970 } else {
1971 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 1972 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 1973 }
1974 /* Fall through */
1975 case E1000E_INT_MODE_LEGACY:
1976 /* Don't do anything; this is the system default */
1977 break;
1978 }
8e86acd7
JK		 1979
1980 /* store the number of vectors being used */
1981 adapter->num_vectors = 1;
4662e82b
BA		 1982}
1983
1984/**
1985 * e1000_request_msix - Initialize MSI-X interrupts
1986 *
1987 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1988 * kernel.
1989 **/
1990static int e1000_request_msix(struct e1000_adapter *adapter)
1991{
1992 struct net_device *netdev = adapter->netdev;
1993 int err = 0, vector = 0;
1994
1995 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1996 snprintf(adapter->rx_ring->name,
1997 sizeof(adapter->rx_ring->name) - 1,
1998 "%s-rx-0", netdev->name);
4662e82b
BA		 1999 else
2000 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2001 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2002 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2003 netdev);
2004 if (err)
5015e53a 2005 return err;
c5083cf6
BA		 2006 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2007 E1000_EITR_82574(vector);
4662e82b
BA		 2008 adapter->rx_ring->itr_val = adapter->itr;
2009 vector++;
2010
2011 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2012 snprintf(adapter->tx_ring->name,
2013 sizeof(adapter->tx_ring->name) - 1,
2014 "%s-tx-0", netdev->name);
4662e82b
BA		 2015 else
2016 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2017 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2018 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2019 netdev);
2020 if (err)
5015e53a 2021 return err;
c5083cf6
BA		 2022 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2023 E1000_EITR_82574(vector);
4662e82b
BA		 2024 adapter->tx_ring->itr_val = adapter->itr;
2025 vector++;
2026
2027 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2028 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2029 if (err)
5015e53a 2030 return err;
4662e82b
BA		 2031
2032 e1000_configure_msix(adapter);
5015e53a 2033
4662e82b 2034 return 0;
4662e82b
BA		 2035}
2036
f8d59f78
BA		 2037/**
2038 * e1000_request_irq - initialize interrupts
2039 *
2040 * Attempts to configure interrupts using the best available
2041 * capabilities of the hardware and kernel.
2042 **/
bc7f75fa
AK		 2043static int e1000_request_irq(struct e1000_adapter *adapter)
2044{
2045 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2046 int err;
2047
4662e82b
BA		 2048 if (adapter->msix_entries) {
2049 err = e1000_request_msix(adapter);
2050 if (!err)
2051 return err;
2052 /* fall back to MSI */
2053 e1000e_reset_interrupt_capability(adapter);
2054 adapter->int_mode = E1000E_INT_MODE_MSI;
2055 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2056 }
4662e82b 2057 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2058 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2059 netdev->name, netdev);
2060 if (!err)
2061 return err;
bc7f75fa 2062
4662e82b
BA		 2063 /* fall back to legacy interrupt */
2064 e1000e_reset_interrupt_capability(adapter);
2065 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2066 }
2067
a0607fd3 2068 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2069 netdev->name, netdev);
2070 if (err)
2071 e_err("Unable to allocate interrupt, Error: %d\n", err);
2072
bc7f75fa
AK		 2073 return err;
2074}
2075
2076static void e1000_free_irq(struct e1000_adapter *adapter)
2077{
2078 struct net_device *netdev = adapter->netdev;
2079
4662e82b
BA		 2080 if (adapter->msix_entries) {
2081 int vector = 0;
2082
2083 free_irq(adapter->msix_entries[vector].vector, netdev);
2084 vector++;
2085
2086 free_irq(adapter->msix_entries[vector].vector, netdev);
2087 vector++;
2088
2089 /* Other Causes interrupt vector */
2090 free_irq(adapter->msix_entries[vector].vector, netdev);
2091 return;
bc7f75fa 2092 }
4662e82b
BA		 2093
2094 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2095}
2096
2097/**
2098 * e1000_irq_disable - Mask off interrupt generation on the NIC
2099 **/
2100static void e1000_irq_disable(struct e1000_adapter *adapter)
2101{
2102 struct e1000_hw *hw = &adapter->hw;
2103
bc7f75fa 2104 ew32(IMC, ~0);
4662e82b
BA		 2105 if (adapter->msix_entries)
2106 ew32(EIAC_82574, 0);
bc7f75fa 2107 e1e_flush();
8e86acd7
JK		 2108
2109 if (adapter->msix_entries) {
2110 int i;
2111 for (i = 0; i < adapter->num_vectors; i++)
2112 synchronize_irq(adapter->msix_entries[i].vector);
2113 } else {
2114 synchronize_irq(adapter->pdev->irq);
2115 }
bc7f75fa
AK		 2116}
2117
2118/**
2119 * e1000_irq_enable - Enable default interrupt generation settings
2120 **/
2121static void e1000_irq_enable(struct e1000_adapter *adapter)
2122{
2123 struct e1000_hw *hw = &adapter->hw;
2124
4662e82b
BA		 2125 if (adapter->msix_entries) {
2126 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2127 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2128 } else {
2129 ew32(IMS, IMS_ENABLE_MASK);
2130 }
74ef9c39 2131 e1e_flush();
bc7f75fa
AK		 2132}
2133
2134/**
31dbe5b4 2135 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2136 * @adapter: address of board private structure
2137 *
31dbe5b4 2138 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2139 * For ASF and Pass Through versions of f/w this means that
2140 * the driver is loaded. For AMT version (only with 82573)
2141 * of the f/w this means that the network i/f is open.
2142 **/
31dbe5b4 2143void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2144{
2145 struct e1000_hw *hw = &adapter->hw;
2146 u32 ctrl_ext;
2147 u32 swsm;
2148
2149 /* Let firmware know the driver has taken over */
2150 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2151 swsm = er32(SWSM);
2152 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2153 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2154 ctrl_ext = er32(CTRL_EXT);
ad68076e 2155 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2156 }
2157}
2158
2159/**
31dbe5b4 2160 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2161 * @adapter: address of board private structure
2162 *
31dbe5b4 2163 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2164 * For ASF and Pass Through versions of f/w this means that the
2165 * driver is no longer loaded. For AMT version (only with 82573) i
2166 * of the f/w this means that the network i/f is closed.
2167 *
2168 **/
31dbe5b4 2169void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2170{
2171 struct e1000_hw *hw = &adapter->hw;
2172 u32 ctrl_ext;
2173 u32 swsm;
2174
2175 /* Let firmware taken over control of h/w */
2176 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2177 swsm = er32(SWSM);
2178 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2179 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2180 ctrl_ext = er32(CTRL_EXT);
ad68076e 2181 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2182 }
2183}
2184
bc7f75fa
AK		 2185/**
2186 * @e1000_alloc_ring - allocate memory for a ring structure
2187 **/
2188static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2189 struct e1000_ring *ring)
2190{
2191 struct pci_dev *pdev = adapter->pdev;
2192
2193 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2194 GFP_KERNEL);
2195 if (!ring->desc)
2196 return -ENOMEM;
2197
2198 return 0;
2199}
2200
2201/**
2202 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2203 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2204 *
2205 * Return 0 on success, negative on failure
2206 **/
55aa6985 2207int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2208{
55aa6985 2209 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2210 int err = -ENOMEM, size;
2211
2212 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2213 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2214 if (!tx_ring->buffer_info)
2215 goto err;
bc7f75fa
AK		 2216
2217 /* round up to nearest 4K */
2218 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2219 tx_ring->size = ALIGN(tx_ring->size, 4096);
2220
2221 err = e1000_alloc_ring_dma(adapter, tx_ring);
2222 if (err)
2223 goto err;
2224
2225 tx_ring->next_to_use = 0;
2226 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2227
2228 return 0;
2229err:
2230 vfree(tx_ring->buffer_info);
44defeb3 2231 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2232 return err;
2233}
2234
2235/**
2236 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2237 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2238 *
2239 * Returns 0 on success, negative on failure
2240 **/
55aa6985 2241int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2242{
55aa6985 2243 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2244 struct e1000_buffer *buffer_info;
2245 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2246
2247 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2248 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2249 if (!rx_ring->buffer_info)
2250 goto err;
bc7f75fa 2251
47f44e40
AK		 2252 for (i = 0; i < rx_ring->count; i++) {
2253 buffer_info = &rx_ring->buffer_info[i];
2254 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2255 sizeof(struct e1000_ps_page),
2256 GFP_KERNEL);
2257 if (!buffer_info->ps_pages)
2258 goto err_pages;
2259 }
bc7f75fa
AK		 2260
2261 desc_len = sizeof(union e1000_rx_desc_packet_split);
2262
2263 /* Round up to nearest 4K */
2264 rx_ring->size = rx_ring->count * desc_len;
2265 rx_ring->size = ALIGN(rx_ring->size, 4096);
2266
2267 err = e1000_alloc_ring_dma(adapter, rx_ring);
2268 if (err)
47f44e40 2269 goto err_pages;
bc7f75fa
AK		 2270
2271 rx_ring->next_to_clean = 0;
2272 rx_ring->next_to_use = 0;
2273 rx_ring->rx_skb_top = NULL;
2274
2275 return 0;
47f44e40
AK		 2276
2277err_pages:
2278 for (i = 0; i < rx_ring->count; i++) {
2279 buffer_info = &rx_ring->buffer_info[i];
2280 kfree(buffer_info->ps_pages);
2281 }
bc7f75fa
AK		 2282err:
2283 vfree(rx_ring->buffer_info);
e9262447 2284 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2285 return err;
2286}
2287
2288/**
2289 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2290 * @tx_ring: Tx descriptor ring
bc7f75fa 2291 **/
55aa6985 2292static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2293{
55aa6985 2294 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2295 struct e1000_buffer *buffer_info;
2296 unsigned long size;
2297 unsigned int i;
2298
2299 for (i = 0; i < tx_ring->count; i++) {
2300 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2301 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2302 }
2303
3f0cfa3b 2304 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2305 size = sizeof(struct e1000_buffer) * tx_ring->count;
2306 memset(tx_ring->buffer_info, 0, size);
2307
2308 memset(tx_ring->desc, 0, tx_ring->size);
2309
2310 tx_ring->next_to_use = 0;
2311 tx_ring->next_to_clean = 0;
2312
c5083cf6
BA		 2313 writel(0, tx_ring->head);
2314 writel(0, tx_ring->tail);
bc7f75fa
AK		 2315}
2316
2317/**
2318 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2319 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2320 *
2321 * Free all transmit software resources
2322 **/
55aa6985 2323void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2324{
55aa6985 2325 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2326 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2327
55aa6985 2328 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2329
2330 vfree(tx_ring->buffer_info);
2331 tx_ring->buffer_info = NULL;
2332
2333 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2334 tx_ring->dma);
2335 tx_ring->desc = NULL;
2336}
2337
2338/**
2339 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2340 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2341 *
2342 * Free all receive software resources
2343 **/
55aa6985 2344void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2345{
55aa6985 2346 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2347 struct pci_dev *pdev = adapter->pdev;
47f44e40 2348 int i;
bc7f75fa 2349
55aa6985 2350 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2351
b1cdfead 2352 for (i = 0; i < rx_ring->count; i++)
47f44e40 2353 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2354
bc7f75fa
AK		 2355 vfree(rx_ring->buffer_info);
2356 rx_ring->buffer_info = NULL;
2357
bc7f75fa
AK		 2358 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2359 rx_ring->dma);
2360 rx_ring->desc = NULL;
2361}
2362
2363/**
2364 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2365 * @adapter: pointer to adapter
2366 * @itr_setting: current adapter->itr
2367 * @packets: the number of packets during this measurement interval
2368 * @bytes: the number of bytes during this measurement interval
2369 *
bc7f75fa
AK		 2370 * Stores a new ITR value based on packets and byte
2371 * counts during the last interrupt. The advantage of per interrupt
2372 * computation is faster updates and more accurate ITR for the current
2373 * traffic pattern. Constants in this function were computed
2374 * based on theoretical maximum wire speed and thresholds were set based
2375 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2376 * while increasing bulk throughput. This functionality is controlled
2377 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2378 **/
2379static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2380 u16 itr_setting, int packets,
2381 int bytes)
2382{
2383 unsigned int retval = itr_setting;
2384
2385 if (packets == 0)
5015e53a 2386 return itr_setting;
bc7f75fa
AK		 2387
2388 switch (itr_setting) {
2389 case lowest_latency:
2390 /* handle TSO and jumbo frames */
2391 if (bytes/packets > 8000)
2392 retval = bulk_latency;
b1cdfead 2393 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2394 retval = low_latency;
bc7f75fa
AK		 2395 break;
2396 case low_latency: /* 50 usec aka 20000 ints/s */
2397 if (bytes > 10000) {
2398 /* this if handles the TSO accounting */
b1cdfead 2399 if (bytes/packets > 8000)
bc7f75fa 2400 retval = bulk_latency;
b1cdfead 2401 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2402 retval = bulk_latency;
b1cdfead 2403 else if ((packets > 35))
bc7f75fa 2404 retval = lowest_latency;
bc7f75fa
AK		 2405 } else if (bytes/packets > 2000) {
2406 retval = bulk_latency;
2407 } else if (packets <= 2 && bytes < 512) {
2408 retval = lowest_latency;
2409 }
2410 break;
2411 case bulk_latency: /* 250 usec aka 4000 ints/s */
2412 if (bytes > 25000) {
b1cdfead 2413 if (packets > 35)
bc7f75fa 2414 retval = low_latency;
bc7f75fa
AK		 2415 } else if (bytes < 6000) {
2416 retval = low_latency;
2417 }
2418 break;
2419 }
2420
bc7f75fa
AK		 2421 return retval;
2422}
2423
2424static void e1000_set_itr(struct e1000_adapter *adapter)
2425{
2426 struct e1000_hw *hw = &adapter->hw;
2427 u16 current_itr;
2428 u32 new_itr = adapter->itr;
2429
2430 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2431 if (adapter->link_speed != SPEED_1000) {
2432 current_itr = 0;
2433 new_itr = 4000;
2434 goto set_itr_now;
2435 }
2436
828bac87
BA		 2437 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2438 new_itr = 0;
2439 goto set_itr_now;
2440 }
2441
bc7f75fa
AK		 2442 adapter->tx_itr = e1000_update_itr(adapter,
2443 adapter->tx_itr,
2444 adapter->total_tx_packets,
2445 adapter->total_tx_bytes);
2446 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2447 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2448 adapter->tx_itr = low_latency;
2449
2450 adapter->rx_itr = e1000_update_itr(adapter,
2451 adapter->rx_itr,
2452 adapter->total_rx_packets,
2453 adapter->total_rx_bytes);
2454 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2455 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2456 adapter->rx_itr = low_latency;
2457
2458 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2459
2460 switch (current_itr) {
2461 /* counts and packets in update_itr are dependent on these numbers */
2462 case lowest_latency:
2463 new_itr = 70000;
2464 break;
2465 case low_latency:
2466 new_itr = 20000; /* aka hwitr = ~200 */
2467 break;
2468 case bulk_latency:
2469 new_itr = 4000;
2470 break;
2471 default:
2472 break;
2473 }
2474
2475set_itr_now:
2476 if (new_itr != adapter->itr) {
ad68076e
BA		 2477 /*
2478 * this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2479 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2480 * increasing
2481 */
bc7f75fa
AK		 2482 new_itr = new_itr > adapter->itr ?
2483 min(adapter->itr + (new_itr >> 2), new_itr) :
2484 new_itr;
2485 adapter->itr = new_itr;
4662e82b
BA		 2486 adapter->rx_ring->itr_val = new_itr;
2487 if (adapter->msix_entries)
2488 adapter->rx_ring->set_itr = 1;
2489 else
828bac87
BA		 2490 if (new_itr)
2491 ew32(ITR, 1000000000 / (new_itr * 256));
2492 else
2493 ew32(ITR, 0);
bc7f75fa
AK		 2494 }
2495}
2496
4662e82b
BA		 2497/**
2498 * e1000_alloc_queues - Allocate memory for all rings
2499 * @adapter: board private structure to initialize
2500 **/
2501static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
2502{
55aa6985
BA		 2503 int size = sizeof(struct e1000_ring);
2504
2505 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2506 if (!adapter->tx_ring)
2507 goto err;
55aa6985
BA		 2508 adapter->tx_ring->count = adapter->tx_ring_count;
2509 adapter->tx_ring->adapter = adapter;
4662e82b 2510
55aa6985 2511 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2512 if (!adapter->rx_ring)
2513 goto err;
55aa6985
BA		 2514 adapter->rx_ring->count = adapter->rx_ring_count;
2515 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2516
2517 return 0;
2518err:
2519 e_err("Unable to allocate memory for queues\n");
2520 kfree(adapter->rx_ring);
2521 kfree(adapter->tx_ring);
2522 return -ENOMEM;
2523}
2524
bc7f75fa
AK		 2525/**
2526 * e1000_clean - NAPI Rx polling callback
ad68076e 2527 * @napi: struct associated with this polling callback
489815ce 2528 * @budget: amount of packets driver is allowed to process this poll
bc7f75fa
AK		 2529 **/
2530static int e1000_clean(struct napi_struct *napi, int budget)
2531{
2532 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
4662e82b 2533 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2534 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2535 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2536
4cf1653a 2537 adapter = netdev_priv(poll_dev);
bc7f75fa 2538
4662e82b
BA		 2539 if (adapter->msix_entries &&
2540 !(adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2541 goto clean_rx;
2542
55aa6985 2543 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
bc7f75fa 2544
4662e82b 2545clean_rx:
55aa6985 2546 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
d2c7ddd6 2547
12d04a3c 2548 if (!tx_cleaned)
d2c7ddd6 2549 work_done = budget;
bc7f75fa 2550
53e52c72
DM		 2551 /* If budget not fully consumed, exit the polling mode */
2552 if (work_done < budget) {
bc7f75fa
AK		 2553 if (adapter->itr_setting & 3)
2554 e1000_set_itr(adapter);
288379f0 2555 napi_complete(napi);
a3c69fef
JB		 2556 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2557 if (adapter->msix_entries)
2558 ew32(IMS, adapter->rx_ring->ims_val);
2559 else
2560 e1000_irq_enable(adapter);
2561 }
bc7f75fa
AK		 2562 }
2563
2564 return work_done;
2565}
2566
8e586137 2567static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2568{
2569 struct e1000_adapter *adapter = netdev_priv(netdev);
2570 struct e1000_hw *hw = &adapter->hw;
2571 u32 vfta, index;
2572
2573 /* don't update vlan cookie if already programmed */
2574 if ((adapter->hw.mng_cookie.status &
2575 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2576 (vid == adapter->mng_vlan_id))
8e586137 2577 return 0;
caaddaf8 2578
bc7f75fa 2579 /* add VID to filter table */
caaddaf8
BA		 2580 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2581 index = (vid >> 5) & 0x7F;
2582 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2583 vfta |= (1 << (vid & 0x1F));
2584 hw->mac.ops.write_vfta(hw, index, vfta);
2585 }
86d70e53
JK		 2586
2587 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2588
2589 return 0;
bc7f75fa
AK		 2590}
2591
8e586137 2592static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2593{
2594 struct e1000_adapter *adapter = netdev_priv(netdev);
2595 struct e1000_hw *hw = &adapter->hw;
2596 u32 vfta, index;
2597
bc7f75fa
AK		 2598 if ((adapter->hw.mng_cookie.status &
2599 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2600 (vid == adapter->mng_vlan_id)) {
2601 /* release control to f/w */
31dbe5b4 2602 e1000e_release_hw_control(adapter);
8e586137 2603 return 0;
bc7f75fa
AK		 2604 }
2605
2606 /* remove VID from filter table */
caaddaf8
BA		 2607 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2608 index = (vid >> 5) & 0x7F;
2609 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2610 vfta &= ~(1 << (vid & 0x1F));
2611 hw->mac.ops.write_vfta(hw, index, vfta);
2612 }
86d70e53
JK		 2613
2614 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2615
2616 return 0;
bc7f75fa
AK		 2617}
2618
86d70e53
JK		 2619/**
2620 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2621 * @adapter: board private structure to initialize
2622 **/
2623static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2624{
2625 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2626 struct e1000_hw *hw = &adapter->hw;
2627 u32 rctl;
bc7f75fa 2628
86d70e53
JK		 2629 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2630 /* disable VLAN receive filtering */
2631 rctl = er32(RCTL);
2632 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2633 ew32(RCTL, rctl);
2634
2635 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2636 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2637 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2638 }
bc7f75fa
AK		 2639 }
2640}
2641
86d70e53
JK		 2642/**
2643 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2644 * @adapter: board private structure to initialize
2645 **/
2646static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2647{
2648 struct e1000_hw *hw = &adapter->hw;
2649 u32 rctl;
2650
2651 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2652 /* enable VLAN receive filtering */
2653 rctl = er32(RCTL);
2654 rctl |= E1000_RCTL_VFE;
2655 rctl &= ~E1000_RCTL_CFIEN;
2656 ew32(RCTL, rctl);
2657 }
2658}
bc7f75fa 2659
86d70e53
JK		 2660/**
2661 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2662 * @adapter: board private structure to initialize
2663 **/
2664static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2665{
bc7f75fa 2666 struct e1000_hw *hw = &adapter->hw;
86d70e53 2667 u32 ctrl;
bc7f75fa 2668
86d70e53
JK		 2669 /* disable VLAN tag insert/strip */
2670 ctrl = er32(CTRL);
2671 ctrl &= ~E1000_CTRL_VME;
2672 ew32(CTRL, ctrl);
2673}
bc7f75fa 2674
86d70e53
JK		 2675/**
2676 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2677 * @adapter: board private structure to initialize
2678 **/
2679static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2680{
2681 struct e1000_hw *hw = &adapter->hw;
2682 u32 ctrl;
bc7f75fa 2683
86d70e53
JK		 2684 /* enable VLAN tag insert/strip */
2685 ctrl = er32(CTRL);
2686 ctrl |= E1000_CTRL_VME;
2687 ew32(CTRL, ctrl);
2688}
bc7f75fa 2689
86d70e53
JK		 2690static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2691{
2692 struct net_device *netdev = adapter->netdev;
2693 u16 vid = adapter->hw.mng_cookie.vlan_id;
2694 u16 old_vid = adapter->mng_vlan_id;
2695
2696 if (adapter->hw.mng_cookie.status &
2697 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2698 e1000_vlan_rx_add_vid(netdev, vid);
2699 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2700 }
2701
86d70e53
JK		 2702 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2703 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2704}
2705
2706static void e1000_restore_vlan(struct e1000_adapter *adapter)
2707{
2708 u16 vid;
2709
86d70e53 2710 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2711
86d70e53 2712 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2713 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2714}
2715
cd791618 2716static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2717{
2718 struct e1000_hw *hw = &adapter->hw;
cd791618 2719 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2720
2721 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2722 return;
2723
2724 manc = er32(MANC);
2725
ad68076e
BA		 2726 /*
2727 * enable receiving management packets to the host. this will probably
bc7f75fa 2728 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2729 * the packets will be handled on SMBUS
2730 */
bc7f75fa
AK		 2731 manc |= E1000_MANC_EN_MNG2HOST;
2732 manc2h = er32(MANC2H);
cd791618
BA		 2733
2734 switch (hw->mac.type) {
2735 default:
2736 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2737 break;
2738 case e1000_82574:
2739 case e1000_82583:
2740 /*
2741 * Check if IPMI pass-through decision filter already exists;
2742 * if so, enable it.
2743 */
2744 for (i = 0, j = 0; i < 8; i++) {
2745 mdef = er32(MDEF(i));
2746
2747 /* Ignore filters with anything other than IPMI ports */
3b21b508 2748 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2749 continue;
2750
2751 /* Enable this decision filter in MANC2H */
2752 if (mdef)
2753 manc2h |= (1 << i);
2754
2755 j |= mdef;
2756 }
2757
2758 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2759 break;
2760
2761 /* Create new decision filter in an empty filter */
2762 for (i = 0, j = 0; i < 8; i++)
2763 if (er32(MDEF(i)) == 0) {
2764 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2765 E1000_MDEF_PORT_664));
2766 manc2h |= (1 << 1);
2767 j++;
2768 break;
2769 }
2770
2771 if (!j)
2772 e_warn("Unable to create IPMI pass-through filter\n");
2773 break;
2774 }
2775
bc7f75fa
AK		 2776 ew32(MANC2H, manc2h);
2777 ew32(MANC, manc);
2778}
2779
2780/**
af667a29 2781 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2782 * @adapter: board private structure
2783 *
2784 * Configure the Tx unit of the MAC after a reset.
2785 **/
2786static void e1000_configure_tx(struct e1000_adapter *adapter)
2787{
2788 struct e1000_hw *hw = &adapter->hw;
2789 struct e1000_ring *tx_ring = adapter->tx_ring;
2790 u64 tdba;
c550b121 2791 u32 tdlen, tarc;
bc7f75fa
AK		 2792
2793 /* Setup the HW Tx Head and Tail descriptor pointers */
2794 tdba = tx_ring->dma;
2795 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
284901a9 2796 ew32(TDBAL, (tdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 2797 ew32(TDBAH, (tdba >> 32));
2798 ew32(TDLEN, tdlen);
2799 ew32(TDH, 0);
2800 ew32(TDT, 0);
c5083cf6
BA		 2801 tx_ring->head = adapter->hw.hw_addr + E1000_TDH;
2802 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT;
bc7f75fa 2803
bc7f75fa
AK		 2804 /* Set the Tx Interrupt Delay register */
2805 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2806 /* Tx irq moderation */
bc7f75fa
AK		 2807 ew32(TADV, adapter->tx_abs_int_delay);
2808
3a3b7586
JB		 2809 if (adapter->flags2 & FLAG2_DMA_BURST) {
2810 u32 txdctl = er32(TXDCTL(0));
2811 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2812 E1000_TXDCTL_WTHRESH);
2813 /*
2814 * set up some performance related parameters to encourage the
2815 * hardware to use the bus more efficiently in bursts, depends
2816 * on the tx_int_delay to be enabled,
2817 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2818 * hthresh = 1 ==> prefetch when one or more available
2819 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2820 * BEWARE: this seems to work but should be considered first if
af667a29 2821 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2822 */
2823 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2824 ew32(TXDCTL(0), txdctl);
3a3b7586 2825 }
56032be7
BA		 2826 /* erratum work around: set txdctl the same for both queues */
2827 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2828
bc7f75fa 2829 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2830 tarc = er32(TARC(0));
ad68076e
BA		 2831 /*
2832 * set the speed mode bit, we'll clear it if we're not at
2833 * gigabit link later
2834 */
bc7f75fa
AK		 2835#define SPEED_MODE_BIT (1 << 21)
2836 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2837 ew32(TARC(0), tarc);
bc7f75fa
AK		 2838 }
2839
2840 /* errata: program both queues to unweighted RR */
2841 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2842 tarc = er32(TARC(0));
bc7f75fa 2843 tarc |= 1;
e9ec2c0f
JK		 2844 ew32(TARC(0), tarc);
2845 tarc = er32(TARC(1));
bc7f75fa 2846 tarc |= 1;
e9ec2c0f 2847 ew32(TARC(1), tarc);
bc7f75fa
AK		 2848 }
2849
bc7f75fa
AK		 2850 /* Setup Transmit Descriptor Settings for eop descriptor */
2851 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2852
2853 /* only set IDE if we are delaying interrupts using the timers */
2854 if (adapter->tx_int_delay)
2855 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2856
2857 /* enable Report Status bit */
2858 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2859
57cde763 2860 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2861}
2862
2863/**
2864 * e1000_setup_rctl - configure the receive control registers
2865 * @adapter: Board private structure
2866 **/
2867#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2868 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2869static void e1000_setup_rctl(struct e1000_adapter *adapter)
2870{
2871 struct e1000_hw *hw = &adapter->hw;
2872 u32 rctl, rfctl;
bc7f75fa
AK		 2873 u32 pages = 0;
2874
a1ce6473
BA		 2875 /* Workaround Si errata on 82579 - configure jumbo frame flow */
2876 if (hw->mac.type == e1000_pch2lan) {
2877 s32 ret_val;
2878
2879 if (adapter->netdev->mtu > ETH_DATA_LEN)
2880 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2881 else
2882 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2883
2884 if (ret_val)
2885 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2886 }
2887
bc7f75fa
AK		 2888 /* Program MC offset vector base */
2889 rctl = er32(RCTL);
2890 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2891 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2892 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2893 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2894
2895 /* Do not Store bad packets */
2896 rctl &= ~E1000_RCTL_SBP;
2897
2898 /* Enable Long Packet receive */
2899 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2900 rctl &= ~E1000_RCTL_LPE;
2901 else
2902 rctl |= E1000_RCTL_LPE;
2903
eb7c3adb
JK		 2904 /* Some systems expect that the CRC is included in SMBUS traffic. The
2905 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2906 * host memory when this is enabled
2907 */
2908 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2909 rctl |= E1000_RCTL_SECRC;
5918bd88 2910
a4f58f54
BA		 2911 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2912 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2913 u16 phy_data;
2914
2915 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2916 phy_data &= 0xfff8;
2917 phy_data |= (1 << 2);
2918 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2919
2920 e1e_rphy(hw, 22, &phy_data);
2921 phy_data &= 0x0fff;
2922 phy_data |= (1 << 14);
2923 e1e_wphy(hw, 0x10, 0x2823);
2924 e1e_wphy(hw, 0x11, 0x0003);
2925 e1e_wphy(hw, 22, phy_data);
2926 }
2927
bc7f75fa
AK		 2928 /* Setup buffer sizes */
2929 rctl &= ~E1000_RCTL_SZ_4096;
2930 rctl |= E1000_RCTL_BSEX;
2931 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 2932 case 2048:
2933 default:
2934 rctl |= E1000_RCTL_SZ_2048;
2935 rctl &= ~E1000_RCTL_BSEX;
2936 break;
2937 case 4096:
2938 rctl |= E1000_RCTL_SZ_4096;
2939 break;
2940 case 8192:
2941 rctl |= E1000_RCTL_SZ_8192;
2942 break;
2943 case 16384:
2944 rctl |= E1000_RCTL_SZ_16384;
2945 break;
2946 }
2947
5f450212
BA		 2948 /* Enable Extended Status in all Receive Descriptors */
2949 rfctl = er32(RFCTL);
2950 rfctl |= E1000_RFCTL_EXTEN;
2951
bc7f75fa
AK		 2952 /*
2953 * 82571 and greater support packet-split where the protocol
2954 * header is placed in skb->data and the packet data is
2955 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2956 * In the case of a non-split, skb->data is linearly filled,
2957 * followed by the page buffers. Therefore, skb->data is
2958 * sized to hold the largest protocol header.
2959 *
2960 * allocations using alloc_page take too long for regular MTU
2961 * so only enable packet split for jumbo frames
2962 *
2963 * Using pages when the page size is greater than 16k wastes
2964 * a lot of memory, since we allocate 3 pages at all times
2965 * per packet.
2966 */
bc7f75fa 2967 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 2968 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 2969 adapter->rx_ps_pages = pages;
97ac8cae
BA		 2970 else
2971 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 2972
2973 if (adapter->rx_ps_pages) {
90da0669
BA		 2974 u32 psrctl = 0;
2975
ad68076e
BA		 2976 /*
2977 * disable packet split support for IPv6 extension headers,
2978 * because some malformed IPv6 headers can hang the Rx
2979 */
bc7f75fa
AK		 2980 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
2981 E1000_RFCTL_NEW_IPV6_EXT_DIS);
2982
140a7480
AK		 2983 /* Enable Packet split descriptors */
2984 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 2985
2986 psrctl |= adapter->rx_ps_bsize0 >>
2987 E1000_PSRCTL_BSIZE0_SHIFT;
2988
2989 switch (adapter->rx_ps_pages) {
2990 case 3:
2991 psrctl |= PAGE_SIZE <<
2992 E1000_PSRCTL_BSIZE3_SHIFT;
2993 case 2:
2994 psrctl |= PAGE_SIZE <<
2995 E1000_PSRCTL_BSIZE2_SHIFT;
2996 case 1:
2997 psrctl |= PAGE_SIZE >>
2998 E1000_PSRCTL_BSIZE1_SHIFT;
2999 break;
3000 }
3001
3002 ew32(PSRCTL, psrctl);
3003 }
3004
cf955e6c
BG		 3005 /* This is useful for sniffing bad packets. */
3006 if (adapter->netdev->features & NETIF_F_RXALL) {
3007 /* UPE and MPE will be handled by normal PROMISC logic
3008 * in e1000e_set_rx_mode */
3009 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3010 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3011 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
3012
3013 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3014 E1000_RCTL_DPF | /* Allow filtered pause */
3015 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
3016 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3017 * and that breaks VLANs.
3018 */
3019 }
3020
5f450212 3021 ew32(RFCTL, rfctl);
bc7f75fa 3022 ew32(RCTL, rctl);
318a94d6
JK		 3023 /* just started the receive unit, no need to restart */
3024 adapter->flags &= ~FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 3025}
3026
3027/**
3028 * e1000_configure_rx - Configure Receive Unit after Reset
3029 * @adapter: board private structure
3030 *
3031 * Configure the Rx unit of the MAC after a reset.
3032 **/
3033static void e1000_configure_rx(struct e1000_adapter *adapter)
3034{
3035 struct e1000_hw *hw = &adapter->hw;
3036 struct e1000_ring *rx_ring = adapter->rx_ring;
3037 u64 rdba;
3038 u32 rdlen, rctl, rxcsum, ctrl_ext;
3039
3040 if (adapter->rx_ps_pages) {
3041 /* this is a 32 byte descriptor */
3042 rdlen = rx_ring->count *
af667a29 3043 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3044 adapter->clean_rx = e1000_clean_rx_irq_ps;
3045 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3046 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3047 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3048 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3049 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3050 } else {
5f450212 3051 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3052 adapter->clean_rx = e1000_clean_rx_irq;
3053 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3054 }
3055
3056 /* disable receives while setting up the descriptors */
3057 rctl = er32(RCTL);
7f99ae63
BA		 3058 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3059 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3060 e1e_flush();
1bba4386 3061 usleep_range(10000, 20000);
bc7f75fa 3062
3a3b7586
JB		 3063 if (adapter->flags2 & FLAG2_DMA_BURST) {
3064 /*
3065 * set the writeback threshold (only takes effect if the RDTR
3066 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3067 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3068 * granularity = 01
3069 * wthresh = 04,
3070 * hthresh = 04,
3071 * pthresh = 0x20
3072 */
3073 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3074 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3075
3076 /*
3077 * override the delay timers for enabling bursting, only if
3078 * the value was not set by the user via module options
3079 */
3080 if (adapter->rx_int_delay == DEFAULT_RDTR)
3081 adapter->rx_int_delay = BURST_RDTR;
3082 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3083 adapter->rx_abs_int_delay = BURST_RADV;
3084 }
3085
bc7f75fa
AK		 3086 /* set the Receive Delay Timer Register */
3087 ew32(RDTR, adapter->rx_int_delay);
3088
3089 /* irq moderation */
3090 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3091 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
ad68076e 3092 ew32(ITR, 1000000000 / (adapter->itr * 256));
bc7f75fa
AK		 3093
3094 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3095 /* Auto-Mask interrupts upon ICR access */
3096 ctrl_ext |= E1000_CTRL_EXT_IAME;
3097 ew32(IAM, 0xffffffff);
3098 ew32(CTRL_EXT, ctrl_ext);
3099 e1e_flush();
3100
ad68076e
BA		 3101 /*
3102 * Setup the HW Rx Head and Tail Descriptor Pointers and
3103 * the Base and Length of the Rx Descriptor Ring
3104 */
bc7f75fa 3105 rdba = rx_ring->dma;
284901a9 3106 ew32(RDBAL, (rdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 3107 ew32(RDBAH, (rdba >> 32));
3108 ew32(RDLEN, rdlen);
3109 ew32(RDH, 0);
3110 ew32(RDT, 0);
c5083cf6
BA		 3111 rx_ring->head = adapter->hw.hw_addr + E1000_RDH;
3112 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT;
bc7f75fa
AK		 3113
3114 /* Enable Receive Checksum Offload for TCP and UDP */
3115 rxcsum = er32(RXCSUM);
dc221294 3116 if (adapter->netdev->features & NETIF_F_RXCSUM) {
bc7f75fa
AK		 3117 rxcsum |= E1000_RXCSUM_TUOFL;
3118
ad68076e
BA		 3119 /*
3120 * IPv4 payload checksum for UDP fragments must be
3121 * used in conjunction with packet-split.
3122 */
bc7f75fa
AK		 3123 if (adapter->rx_ps_pages)
3124 rxcsum |= E1000_RXCSUM_IPPCSE;
3125 } else {
3126 rxcsum &= ~E1000_RXCSUM_TUOFL;
3127 /* no need to clear IPPCSE as it defaults to 0 */
3128 }
3129 ew32(RXCSUM, rxcsum);
3130
79d4e908
BA		 3131 if (adapter->hw.mac.type == e1000_pch2lan) {
3132 /*
3133 * With jumbo frames, excessive C-state transition
3134 * latencies result in dropped transactions.
3135 */
53ec5498
BA		 3136 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3137 u32 rxdctl = er32(RXDCTL(0));
3138 ew32(RXDCTL(0), rxdctl | 0x3);
af667a29 3139 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3140 } else {
af667a29
BA		 3141 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3142 PM_QOS_DEFAULT_VALUE);
53ec5498 3143 }
97ac8cae 3144 }
bc7f75fa
AK		 3145
3146 /* Enable Receives */
3147 ew32(RCTL, rctl);
3148}
3149
3150/**
ef9b965a
JB		 3151 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3152 * @netdev: network interface device structure
bc7f75fa 3153 *
ef9b965a
JB		 3154 * Writes multicast address list to the MTA hash table.
3155 * Returns: -ENOMEM on failure
3156 * 0 on no addresses written
3157 * X on writing X addresses to MTA
3158 */
3159static int e1000e_write_mc_addr_list(struct net_device *netdev)
3160{
3161 struct e1000_adapter *adapter = netdev_priv(netdev);
3162 struct e1000_hw *hw = &adapter->hw;
3163 struct netdev_hw_addr *ha;
3164 u8 *mta_list;
3165 int i;
3166
3167 if (netdev_mc_empty(netdev)) {
3168 /* nothing to program, so clear mc list */
3169 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3170 return 0;
3171 }
3172
3173 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3174 if (!mta_list)
3175 return -ENOMEM;
3176
3177 /* update_mc_addr_list expects a packed array of only addresses. */
3178 i = 0;
3179 netdev_for_each_mc_addr(ha, netdev)
3180 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3181
3182 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3183 kfree(mta_list);
3184
3185 return netdev_mc_count(netdev);
3186}
3187
3188/**
3189 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3190 * @netdev: network interface device structure
bc7f75fa 3191 *
ef9b965a
JB		 3192 * Writes unicast address list to the RAR table.
3193 * Returns: -ENOMEM on failure/insufficient address space
3194 * 0 on no addresses written
3195 * X on writing X addresses to the RAR table
bc7f75fa 3196 **/
ef9b965a 3197static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3198{
ef9b965a
JB		 3199 struct e1000_adapter *adapter = netdev_priv(netdev);
3200 struct e1000_hw *hw = &adapter->hw;
3201 unsigned int rar_entries = hw->mac.rar_entry_count;
3202 int count = 0;
3203
3204 /* save a rar entry for our hardware address */
3205 rar_entries--;
3206
3207 /* save a rar entry for the LAA workaround */
3208 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3209 rar_entries--;
3210
3211 /* return ENOMEM indicating insufficient memory for addresses */
3212 if (netdev_uc_count(netdev) > rar_entries)
3213 return -ENOMEM;
3214
3215 if (!netdev_uc_empty(netdev) && rar_entries) {
3216 struct netdev_hw_addr *ha;
3217
3218 /*
3219 * write the addresses in reverse order to avoid write
3220 * combining
3221 */
3222 netdev_for_each_uc_addr(ha, netdev) {
3223 if (!rar_entries)
3224 break;
3225 e1000e_rar_set(hw, ha->addr, rar_entries--);
3226 count++;
3227 }
3228 }
3229
3230 /* zero out the remaining RAR entries not used above */
3231 for (; rar_entries > 0; rar_entries--) {
3232 ew32(RAH(rar_entries), 0);
3233 ew32(RAL(rar_entries), 0);
3234 }
3235 e1e_flush();
3236
3237 return count;
bc7f75fa
AK		 3238}
3239
3240/**
ef9b965a 3241 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3242 * @netdev: network interface device structure
3243 *
ef9b965a
JB		 3244 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3245 * address list or the network interface flags are updated. This routine is
3246 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3247 * promiscuous mode, and all-multi behavior.
3248 **/
ef9b965a 3249static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3250{
3251 struct e1000_adapter *adapter = netdev_priv(netdev);
3252 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3253 u32 rctl;
bc7f75fa
AK		 3254
3255 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3256 rctl = er32(RCTL);
3257
ef9b965a
JB		 3258 /* clear the affected bits */
3259 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3260
bc7f75fa
AK		 3261 if (netdev->flags & IFF_PROMISC) {
3262 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3263 /* Do not hardware filter VLANs in promisc mode */
3264 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3265 } else {
ef9b965a 3266 int count;
3d3a1676 3267
746b9f02
PM		 3268 if (netdev->flags & IFF_ALLMULTI) {
3269 rctl |= E1000_RCTL_MPE;
746b9f02 3270 } else {
ef9b965a
JB		 3271 /*
3272 * Write addresses to the MTA, if the attempt fails
3273 * then we should just turn on promiscuous mode so
3274 * that we can at least receive multicast traffic
3275 */
3276 count = e1000e_write_mc_addr_list(netdev);
3277 if (count < 0)
3278 rctl |= E1000_RCTL_MPE;
746b9f02 3279 }
86d70e53 3280 e1000e_vlan_filter_enable(adapter);
bc7f75fa 3281 /*
ef9b965a
JB		 3282 * Write addresses to available RAR registers, if there is not
3283 * sufficient space to store all the addresses then enable
3284 * unicast promiscuous mode
bc7f75fa 3285 */
ef9b965a
JB		 3286 count = e1000e_write_uc_addr_list(netdev);
3287 if (count < 0)
3288 rctl |= E1000_RCTL_UPE;
bc7f75fa 3289 }
86d70e53 3290
ef9b965a
JB		 3291 ew32(RCTL, rctl);
3292
86d70e53
JK		 3293 if (netdev->features & NETIF_F_HW_VLAN_RX)
3294 e1000e_vlan_strip_enable(adapter);
3295 else
3296 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3297}
3298
70495a50
BA		 3299static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3300{
3301 struct e1000_hw *hw = &adapter->hw;
3302 u32 mrqc, rxcsum;
3303 int i;
3304 static const u32 rsskey[10] = {
3305 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3306 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3307 };
3308
3309 /* Fill out hash function seed */
3310 for (i = 0; i < 10; i++)
3311 ew32(RSSRK(i), rsskey[i]);
3312
3313 /* Direct all traffic to queue 0 */
3314 for (i = 0; i < 32; i++)
3315 ew32(RETA(i), 0);
3316
3317 /*
3318 * Disable raw packet checksumming so that RSS hash is placed in
3319 * descriptor on writeback.
3320 */
3321 rxcsum = er32(RXCSUM);
3322 rxcsum |= E1000_RXCSUM_PCSD;
3323
3324 ew32(RXCSUM, rxcsum);
3325
3326 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3327 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3328 E1000_MRQC_RSS_FIELD_IPV6 |
3329 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3330 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3331
3332 ew32(MRQC, mrqc);
3333}
3334
bc7f75fa 3335/**
ad68076e 3336 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3337 * @adapter: private board structure
3338 **/
3339static void e1000_configure(struct e1000_adapter *adapter)
3340{
55aa6985
BA		 3341 struct e1000_ring *rx_ring = adapter->rx_ring;
3342
ef9b965a 3343 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3344
3345 e1000_restore_vlan(adapter);
cd791618 3346 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3347
3348 e1000_configure_tx(adapter);
70495a50
BA		 3349
3350 if (adapter->netdev->features & NETIF_F_RXHASH)
3351 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3352 e1000_setup_rctl(adapter);
3353 e1000_configure_rx(adapter);
55aa6985 3354 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3355}
3356
3357/**
3358 * e1000e_power_up_phy - restore link in case the phy was powered down
3359 * @adapter: address of board private structure
3360 *
3361 * The phy may be powered down to save power and turn off link when the
3362 * driver is unloaded and wake on lan is not enabled (among others)
3363 * *** this routine MUST be followed by a call to e1000e_reset ***
3364 **/
3365void e1000e_power_up_phy(struct e1000_adapter *adapter)
3366{
17f208de
BA		 3367 if (adapter->hw.phy.ops.power_up)
3368 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3369
3370 adapter->hw.mac.ops.setup_link(&adapter->hw);
3371}
3372
3373/**
3374 * e1000_power_down_phy - Power down the PHY
3375 *
17f208de
BA		 3376 * Power down the PHY so no link is implied when interface is down.
3377 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3378 */
3379static void e1000_power_down_phy(struct e1000_adapter *adapter)
3380{
bc7f75fa 3381 /* WoL is enabled */
23b66e2b 3382 if (adapter->wol)
bc7f75fa
AK		 3383 return;
3384
17f208de
BA		 3385 if (adapter->hw.phy.ops.power_down)
3386 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3387}
3388
3389/**
3390 * e1000e_reset - bring the hardware into a known good state
3391 *
3392 * This function boots the hardware and enables some settings that
3393 * require a configuration cycle of the hardware - those cannot be
3394 * set/changed during runtime. After reset the device needs to be
ad68076e 3395 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3396 */
3397void e1000e_reset(struct e1000_adapter *adapter)
3398{
3399 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3400 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3401 struct e1000_hw *hw = &adapter->hw;
3402 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3403 u32 pba = adapter->pba;
bc7f75fa
AK		 3404 u16 hwm;
3405
ad68076e 3406 /* reset Packet Buffer Allocation to default */
318a94d6 3407 ew32(PBA, pba);
df762464 3408
318a94d6 3409 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
ad68076e
BA		 3410 /*
3411 * To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3412 * large enough to accommodate two full transmit packets,
3413 * rounded up to the next 1KB and expressed in KB. Likewise,
3414 * the Rx FIFO should be large enough to accommodate at least
3415 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3416 * expressed in KB.
3417 */
df762464 3418 pba = er32(PBA);
bc7f75fa 3419 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3420 tx_space = pba >> 16;
bc7f75fa 3421 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3422 pba &= 0xffff;
ad68076e 3423 /*
af667a29 3424 * the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3425 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3426 */
3427 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3428 sizeof(struct e1000_tx_desc) -
3429 ETH_FCS_LEN) * 2;
3430 min_tx_space = ALIGN(min_tx_space, 1024);
3431 min_tx_space >>= 10;
3432 /* software strips receive CRC, so leave room for it */
318a94d6 3433 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3434 min_rx_space = ALIGN(min_rx_space, 1024);
3435 min_rx_space >>= 10;
3436
ad68076e
BA		 3437 /*
3438 * If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3439 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3440 * allocation, take space away from current Rx allocation
3441 */
df762464
AK		 3442 if ((tx_space < min_tx_space) &&
3443 ((min_tx_space - tx_space) < pba)) {
3444 pba -= min_tx_space - tx_space;
bc7f75fa 3445
ad68076e 3446 /*
af667a29 3447 * if short on Rx space, Rx wins and must trump Tx
ad68076e
BA		 3448 * adjustment or use Early Receive if available
3449 */
79d4e908 3450 if (pba < min_rx_space)
df762464 3451 pba = min_rx_space;
bc7f75fa 3452 }
df762464
AK		 3453
3454 ew32(PBA, pba);
bc7f75fa
AK		 3455 }
3456
ad68076e
BA		 3457 /*
3458 * flow control settings
3459 *
38eb394e 3460 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3461 * (or the size used for early receive) above it in the Rx FIFO.
3462 * Set it to the lower of:
3463 * - 90% of the Rx FIFO size, and
38eb394e 3464 * - the full Rx FIFO size minus one full frame
ad68076e 3465 */
d3738bb8
BA		 3466 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3467 fc->pause_time = 0xFFFF;
3468 else
3469 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3470 fc->send_xon = true;
d3738bb8
BA		 3471 fc->current_mode = fc->requested_mode;
3472
3473 switch (hw->mac.type) {
79d4e908
BA		 3474 case e1000_ich9lan:
3475 case e1000_ich10lan:
3476 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3477 pba = 14;
3478 ew32(PBA, pba);
3479 fc->high_water = 0x2800;
3480 fc->low_water = fc->high_water - 8;
3481 break;
3482 }
3483 /* fall-through */
d3738bb8 3484 default:
79d4e908
BA		 3485 hwm = min(((pba << 10) * 9 / 10),
3486 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3487
3488 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3489 fc->low_water = fc->high_water - 8;
3490 break;
3491 case e1000_pchlan:
38eb394e
BA		 3492 /*
3493 * Workaround PCH LOM adapter hangs with certain network
3494 * loads. If hangs persist, try disabling Tx flow control.
3495 */
3496 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3497 fc->high_water = 0x3500;
3498 fc->low_water = 0x1500;
3499 } else {
3500 fc->high_water = 0x5000;
3501 fc->low_water = 0x3000;
3502 }
a305595b 3503 fc->refresh_time = 0x1000;
d3738bb8
BA		 3504 break;
3505 case e1000_pch2lan:
3506 fc->high_water = 0x05C20;
3507 fc->low_water = 0x05048;
3508 fc->pause_time = 0x0650;
3509 fc->refresh_time = 0x0400;
828bac87
BA		 3510 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3511 pba = 14;
3512 ew32(PBA, pba);
3513 }
d3738bb8 3514 break;
38eb394e 3515 }
bc7f75fa 3516
828bac87
BA		 3517 /*
3518 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3519 * fit in receive buffer.
828bac87
BA		 3520 */
3521 if (adapter->itr_setting & 0x3) {
79d4e908 3522 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3523 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3524 dev_info(&adapter->pdev->dev,
3525 "Interrupt Throttle Rate turned off\n");
3526 adapter->flags2 |= FLAG2_DISABLE_AIM;
3527 ew32(ITR, 0);
3528 }
3529 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3530 dev_info(&adapter->pdev->dev,
3531 "Interrupt Throttle Rate turned on\n");
3532 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3533 adapter->itr = 20000;
3534 ew32(ITR, 1000000000 / (adapter->itr * 256));
3535 }
3536 }
3537
bc7f75fa
AK		 3538 /* Allow time for pending master requests to run */
3539 mac->ops.reset_hw(hw);
97ac8cae
BA		 3540
3541 /*
3542 * For parts with AMT enabled, let the firmware know
3543 * that the network interface is in control
3544 */
c43bc57e 3545 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3546 e1000e_get_hw_control(adapter);
97ac8cae 3547
bc7f75fa
AK		 3548 ew32(WUC, 0);
3549
3550 if (mac->ops.init_hw(hw))
44defeb3 3551 e_err("Hardware Error\n");
bc7f75fa
AK		 3552
3553 e1000_update_mng_vlan(adapter);
3554
3555 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3556 ew32(VET, ETH_P_8021Q);
3557
3558 e1000e_reset_adaptive(hw);
31dbe5b4
BA		 3559
3560 if (!netif_running(adapter->netdev) &&
3561 !test_bit(__E1000_TESTING, &adapter->state)) {
3562 e1000_power_down_phy(adapter);
3563 return;
3564 }
3565
bc7f75fa
AK		 3566 e1000_get_phy_info(hw);
3567
918d7197
BA		 3568 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3569 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3570 u16 phy_data = 0;
ad68076e
BA		 3571 /*
3572 * speed up time to link by disabling smart power down, ignore
bc7f75fa 3573 * the return value of this function because there is nothing
ad68076e
BA		 3574 * different we would do if it failed
3575 */
bc7f75fa
AK		 3576 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3577 phy_data &= ~IGP02E1000_PM_SPD;
3578 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3579 }
bc7f75fa
AK		 3580}
3581
3582int e1000e_up(struct e1000_adapter *adapter)
3583{
3584 struct e1000_hw *hw = &adapter->hw;
3585
3586 /* hardware has been reset, we need to reload some things */
3587 e1000_configure(adapter);
3588
3589 clear_bit(__E1000_DOWN, &adapter->state);
3590
4662e82b
BA		 3591 if (adapter->msix_entries)
3592 e1000_configure_msix(adapter);
bc7f75fa
AK		 3593 e1000_irq_enable(adapter);
3594
400484fa 3595 netif_start_queue(adapter->netdev);
4cb9be7a 3596
bc7f75fa 3597 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3598 if (adapter->msix_entries)
3599 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3600 else
3601 ew32(ICS, E1000_ICS_LSC);
3602
bc7f75fa
AK		 3603 return 0;
3604}
3605
713b3c9e
JB		 3606static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3607{
3608 struct e1000_hw *hw = &adapter->hw;
3609
3610 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3611 return;
3612
3613 /* flush pending descriptor writebacks to memory */
3614 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3615 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3616
3617 /* execute the writes immediately */
3618 e1e_flush();
3619}
3620
67fd4fcb
JK		 3621static void e1000e_update_stats(struct e1000_adapter *adapter);
3622
bc7f75fa
AK		 3623void e1000e_down(struct e1000_adapter *adapter)
3624{
3625 struct net_device *netdev = adapter->netdev;
3626 struct e1000_hw *hw = &adapter->hw;
3627 u32 tctl, rctl;
3628
ad68076e
BA		 3629 /*
3630 * signal that we're down so the interrupt handler does not
3631 * reschedule our watchdog timer
3632 */
bc7f75fa
AK		 3633 set_bit(__E1000_DOWN, &adapter->state);
3634
3635 /* disable receives in the hardware */
3636 rctl = er32(RCTL);
7f99ae63
BA		 3637 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3638 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3639 /* flush and sleep below */
3640
4cb9be7a 3641 netif_stop_queue(netdev);
bc7f75fa
AK		 3642
3643 /* disable transmits in the hardware */
3644 tctl = er32(TCTL);
3645 tctl &= ~E1000_TCTL_EN;
3646 ew32(TCTL, tctl);
7f99ae63 3647
bc7f75fa
AK		 3648 /* flush both disables and wait for them to finish */
3649 e1e_flush();
1bba4386 3650 usleep_range(10000, 20000);
bc7f75fa 3651
bc7f75fa
AK		 3652 e1000_irq_disable(adapter);
3653
3654 del_timer_sync(&adapter->watchdog_timer);
3655 del_timer_sync(&adapter->phy_info_timer);
3656
bc7f75fa 3657 netif_carrier_off(netdev);
67fd4fcb
JK		 3658
3659 spin_lock(&adapter->stats64_lock);
3660 e1000e_update_stats(adapter);
3661 spin_unlock(&adapter->stats64_lock);
3662
400484fa 3663 e1000e_flush_descriptors(adapter);
55aa6985
BA		 3664 e1000_clean_tx_ring(adapter->tx_ring);
3665 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 3666
bc7f75fa
AK		 3667 adapter->link_speed = 0;
3668 adapter->link_duplex = 0;
3669
52cc3086
JK		 3670 if (!pci_channel_offline(adapter->pdev))
3671 e1000e_reset(adapter);
713b3c9e 3672
bc7f75fa
AK		 3673 /*
3674 * TODO: for power management, we could drop the link and
3675 * pci_disable_device here.
3676 */
3677}
3678
3679void e1000e_reinit_locked(struct e1000_adapter *adapter)
3680{
3681 might_sleep();
3682 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3683 usleep_range(1000, 2000);
bc7f75fa
AK		 3684 e1000e_down(adapter);
3685 e1000e_up(adapter);
3686 clear_bit(__E1000_RESETTING, &adapter->state);
3687}
3688
3689/**
3690 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3691 * @adapter: board private structure to initialize
3692 *
3693 * e1000_sw_init initializes the Adapter private data structure.
3694 * Fields are initialized based on PCI device information and
3695 * OS network device settings (MTU size).
3696 **/
3697static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
3698{
bc7f75fa
AK		 3699 struct net_device *netdev = adapter->netdev;
3700
3701 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3702 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3703 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3704 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 3705 adapter->tx_ring_count = E1000_DEFAULT_TXD;
3706 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 3707
67fd4fcb
JK		 3708 spin_lock_init(&adapter->stats64_lock);
3709
4662e82b 3710 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3711
4662e82b
BA		 3712 if (e1000_alloc_queues(adapter))
3713 return -ENOMEM;
bc7f75fa 3714
bc7f75fa 3715 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3716 e1000_irq_disable(adapter);
3717
bc7f75fa
AK		 3718 set_bit(__E1000_DOWN, &adapter->state);
3719 return 0;
bc7f75fa
AK		 3720}
3721
f8d59f78
BA		 3722/**
3723 * e1000_intr_msi_test - Interrupt Handler
3724 * @irq: interrupt number
3725 * @data: pointer to a network interface device structure
3726 **/
3727static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3728{
3729 struct net_device *netdev = data;
3730 struct e1000_adapter *adapter = netdev_priv(netdev);
3731 struct e1000_hw *hw = &adapter->hw;
3732 u32 icr = er32(ICR);
3733
3bb99fe2 3734 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 3735 if (icr & E1000_ICR_RXSEQ) {
3736 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
3737 wmb();
3738 }
3739
3740 return IRQ_HANDLED;
3741}
3742
3743/**
3744 * e1000_test_msi_interrupt - Returns 0 for successful test
3745 * @adapter: board private struct
3746 *
3747 * code flow taken from tg3.c
3748 **/
3749static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3750{
3751 struct net_device *netdev = adapter->netdev;
3752 struct e1000_hw *hw = &adapter->hw;
3753 int err;
3754
3755 /* poll_enable hasn't been called yet, so don't need disable */
3756 /* clear any pending events */
3757 er32(ICR);
3758
3759 /* free the real vector and request a test handler */
3760 e1000_free_irq(adapter);
4662e82b 3761 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 3762
3763 /* Assume that the test fails, if it succeeds then the test
3764 * MSI irq handler will unset this flag */
3765 adapter->flags |= FLAG_MSI_TEST_FAILED;
3766
3767 err = pci_enable_msi(adapter->pdev);
3768 if (err)
3769 goto msi_test_failed;
3770
a0607fd3 3771 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 3772 netdev->name, netdev);
3773 if (err) {
3774 pci_disable_msi(adapter->pdev);
3775 goto msi_test_failed;
3776 }
3777
3778 wmb();
3779
3780 e1000_irq_enable(adapter);
3781
3782 /* fire an unusual interrupt on the test handler */
3783 ew32(ICS, E1000_ICS_RXSEQ);
3784 e1e_flush();
3785 msleep(50);
3786
3787 e1000_irq_disable(adapter);
3788
3789 rmb();
3790
3791 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 3792 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 3793 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 3794 } else {
068e8a30 3795 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 3796 }
f8d59f78
BA		 3797
3798 free_irq(adapter->pdev->irq, netdev);
3799 pci_disable_msi(adapter->pdev);
3800
f8d59f78 3801msi_test_failed:
4662e82b 3802 e1000e_set_interrupt_capability(adapter);
068e8a30 3803 return e1000_request_irq(adapter);
f8d59f78
BA		 3804}
3805
3806/**
3807 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3808 * @adapter: board private struct
3809 *
3810 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3811 **/
3812static int e1000_test_msi(struct e1000_adapter *adapter)
3813{
3814 int err;
3815 u16 pci_cmd;
3816
3817 if (!(adapter->flags & FLAG_MSI_ENABLED))
3818 return 0;
3819
3820 /* disable SERR in case the MSI write causes a master abort */
3821 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 3822 if (pci_cmd & PCI_COMMAND_SERR)
3823 pci_write_config_word(adapter->pdev, PCI_COMMAND,
3824 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 3825
3826 err = e1000_test_msi_interrupt(adapter);
3827
36f2407f
DN		 3828 /* re-enable SERR */
3829 if (pci_cmd & PCI_COMMAND_SERR) {
3830 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
3831 pci_cmd |= PCI_COMMAND_SERR;
3832 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
3833 }
f8d59f78 3834
f8d59f78
BA		 3835 return err;
3836}
3837
bc7f75fa
AK		 3838/**
3839 * e1000_open - Called when a network interface is made active
3840 * @netdev: network interface device structure
3841 *
3842 * Returns 0 on success, negative value on failure
3843 *
3844 * The open entry point is called when a network interface is made
3845 * active by the system (IFF_UP). At this point all resources needed
3846 * for transmit and receive operations are allocated, the interrupt
3847 * handler is registered with the OS, the watchdog timer is started,
3848 * and the stack is notified that the interface is ready.
3849 **/
3850static int e1000_open(struct net_device *netdev)
3851{
3852 struct e1000_adapter *adapter = netdev_priv(netdev);
3853 struct e1000_hw *hw = &adapter->hw;
23606cf5 3854 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3855 int err;
3856
3857 /* disallow open during test */
3858 if (test_bit(__E1000_TESTING, &adapter->state))
3859 return -EBUSY;
3860
23606cf5
RW		 3861 pm_runtime_get_sync(&pdev->dev);
3862
9c563d20
JB		 3863 netif_carrier_off(netdev);
3864
bc7f75fa 3865 /* allocate transmit descriptors */
55aa6985 3866 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3867 if (err)
3868 goto err_setup_tx;
3869
3870 /* allocate receive descriptors */
55aa6985 3871 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 3872 if (err)
3873 goto err_setup_rx;
3874
11b08be8
BA		 3875 /*
3876 * If AMT is enabled, let the firmware know that the network
3877 * interface is now open and reset the part to a known state.
3878 */
3879 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 3880 e1000e_get_hw_control(adapter);
11b08be8
BA		 3881 e1000e_reset(adapter);
3882 }
3883
bc7f75fa
AK		 3884 e1000e_power_up_phy(adapter);
3885
3886 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3887 if ((adapter->hw.mng_cookie.status &
3888 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3889 e1000_update_mng_vlan(adapter);
3890
79d4e908
BA		 3891 /* DMA latency requirement to workaround jumbo issue */
3892 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014
LT		 3893 pm_qos_add_request(&adapter->netdev->pm_qos_req,
3894 PM_QOS_CPU_DMA_LATENCY,
3895 PM_QOS_DEFAULT_VALUE);
c128ec29 3896
ad68076e
BA		 3897 /*
3898 * before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 3899 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3900 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 3901 * clean_rx handler before we do so.
3902 */
bc7f75fa
AK		 3903 e1000_configure(adapter);
3904
3905 err = e1000_request_irq(adapter);
3906 if (err)
3907 goto err_req_irq;
3908
f8d59f78
BA		 3909 /*
3910 * Work around PCIe errata with MSI interrupts causing some chipsets to
3911 * ignore e1000e MSI messages, which means we need to test our MSI
3912 * interrupt now
3913 */
4662e82b 3914 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 3915 err = e1000_test_msi(adapter);
3916 if (err) {
3917 e_err("Interrupt allocation failed\n");
3918 goto err_req_irq;
3919 }
3920 }
3921
bc7f75fa
AK		 3922 /* From here on the code is the same as e1000e_up() */
3923 clear_bit(__E1000_DOWN, &adapter->state);
3924
3925 napi_enable(&adapter->napi);
3926
3927 e1000_irq_enable(adapter);
3928
09357b00 3929 adapter->tx_hang_recheck = false;
4cb9be7a 3930 netif_start_queue(netdev);
d55b53ff 3931
23606cf5
RW		 3932 adapter->idle_check = true;
3933 pm_runtime_put(&pdev->dev);
3934
bc7f75fa 3935 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 3936 if (adapter->msix_entries)
3937 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3938 else
3939 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 3940
3941 return 0;
3942
3943err_req_irq:
31dbe5b4 3944 e1000e_release_hw_control(adapter);
bc7f75fa 3945 e1000_power_down_phy(adapter);
55aa6985 3946 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3947err_setup_rx:
55aa6985 3948 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3949err_setup_tx:
3950 e1000e_reset(adapter);
23606cf5 3951 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 3952
3953 return err;
3954}
3955
3956/**
3957 * e1000_close - Disables a network interface
3958 * @netdev: network interface device structure
3959 *
3960 * Returns 0, this is not allowed to fail
3961 *
3962 * The close entry point is called when an interface is de-activated
3963 * by the OS. The hardware is still under the drivers control, but
3964 * needs to be disabled. A global MAC reset is issued to stop the
3965 * hardware, and all transmit and receive resources are freed.
3966 **/
3967static int e1000_close(struct net_device *netdev)
3968{
3969 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 3970 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3971
3972 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 3973
3974 pm_runtime_get_sync(&pdev->dev);
3975
5f4a780d
BA		 3976 napi_disable(&adapter->napi);
3977
23606cf5
RW		 3978 if (!test_bit(__E1000_DOWN, &adapter->state)) {
3979 e1000e_down(adapter);
3980 e1000_free_irq(adapter);
3981 }
bc7f75fa 3982 e1000_power_down_phy(adapter);
bc7f75fa 3983
55aa6985
BA		 3984 e1000e_free_tx_resources(adapter->tx_ring);
3985 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3986
ad68076e
BA		 3987 /*
3988 * kill manageability vlan ID if supported, but not if a vlan with
3989 * the same ID is registered on the host OS (let 8021q kill it)
3990 */
86d70e53
JK		 3991 if (adapter->hw.mng_cookie.status &
3992 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 3993 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3994
ad68076e
BA		 3995 /*
3996 * If AMT is enabled, let the firmware know that the network
3997 * interface is now closed
3998 */
31dbe5b4
BA		 3999 if ((adapter->flags & FLAG_HAS_AMT) &&
4000 !test_bit(__E1000_TESTING, &adapter->state))
4001 e1000e_release_hw_control(adapter);
bc7f75fa 4002
79d4e908 4003 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014 4004 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4005
23606cf5
RW		 4006 pm_runtime_put_sync(&pdev->dev);
4007
bc7f75fa
AK		 4008 return 0;
4009}
4010/**
4011 * e1000_set_mac - Change the Ethernet Address of the NIC
4012 * @netdev: network interface device structure
4013 * @p: pointer to an address structure
4014 *
4015 * Returns 0 on success, negative on failure
4016 **/
4017static int e1000_set_mac(struct net_device *netdev, void *p)
4018{
4019 struct e1000_adapter *adapter = netdev_priv(netdev);
4020 struct sockaddr *addr = p;
4021
4022 if (!is_valid_ether_addr(addr->sa_data))
4023 return -EADDRNOTAVAIL;
4024
4025 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4026 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4027
4028 e1000e_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4029
4030 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4031 /* activate the work around */
4032 e1000e_set_laa_state_82571(&adapter->hw, 1);
4033
ad68076e
BA		 4034 /*
4035 * Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4036 * between the time RAR[0] gets clobbered and the time it
4037 * gets fixed (in e1000_watchdog), the actual LAA is in one
4038 * of the RARs and no incoming packets directed to this port
4039 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4040 * RAR[14]
4041 */
bc7f75fa
AK		 4042 e1000e_rar_set(&adapter->hw,
4043 adapter->hw.mac.addr,
4044 adapter->hw.mac.rar_entry_count - 1);
4045 }
4046
4047 return 0;
4048}
4049
a8f88ff5
JB		 4050/**
4051 * e1000e_update_phy_task - work thread to update phy
4052 * @work: pointer to our work struct
4053 *
4054 * this worker thread exists because we must acquire a
4055 * semaphore to read the phy, which we could msleep while
4056 * waiting for it, and we can't msleep in a timer.
4057 **/
4058static void e1000e_update_phy_task(struct work_struct *work)
4059{
4060 struct e1000_adapter *adapter = container_of(work,
4061 struct e1000_adapter, update_phy_task);
615b32af
JB		 4062
4063 if (test_bit(__E1000_DOWN, &adapter->state))
4064 return;
4065
a8f88ff5
JB		 4066 e1000_get_phy_info(&adapter->hw);
4067}
4068
ad68076e
BA		 4069/*
4070 * Need to wait a few seconds after link up to get diagnostic information from
4071 * the phy
4072 */
bc7f75fa
AK		 4073static void e1000_update_phy_info(unsigned long data)
4074{
4075 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4076
4077 if (test_bit(__E1000_DOWN, &adapter->state))
4078 return;
4079
a8f88ff5 4080 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4081}
4082
8c7bbb92
BA		 4083/**
4084 * e1000e_update_phy_stats - Update the PHY statistics counters
4085 * @adapter: board private structure
2b6b168d
BA		 4086 *
4087 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4088 **/
4089static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4090{
4091 struct e1000_hw *hw = &adapter->hw;
4092 s32 ret_val;
4093 u16 phy_data;
4094
4095 ret_val = hw->phy.ops.acquire(hw);
4096 if (ret_val)
4097 return;
4098
8c7bbb92
BA		 4099 /*
4100 * A page set is expensive so check if already on desired page.
4101 * If not, set to the page with the PHY status registers.
4102 */
2b6b168d 4103 hw->phy.addr = 1;
8c7bbb92
BA		 4104 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4105 &phy_data);
4106 if (ret_val)
4107 goto release;
2b6b168d
BA		 4108 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4109 ret_val = hw->phy.ops.set_page(hw,
4110 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4111 if (ret_val)
4112 goto release;
4113 }
4114
8c7bbb92 4115 /* Single Collision Count */
2b6b168d
BA		 4116 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4117 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4118 if (!ret_val)
4119 adapter->stats.scc += phy_data;
4120
4121 /* Excessive Collision Count */
2b6b168d
BA		 4122 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4123 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4124 if (!ret_val)
4125 adapter->stats.ecol += phy_data;
4126
4127 /* Multiple Collision Count */
2b6b168d
BA		 4128 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4129 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4130 if (!ret_val)
4131 adapter->stats.mcc += phy_data;
4132
4133 /* Late Collision Count */
2b6b168d
BA		 4134 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4135 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4136 if (!ret_val)
4137 adapter->stats.latecol += phy_data;
4138
4139 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4140 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4141 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4142 if (!ret_val)
4143 hw->mac.collision_delta = phy_data;
4144
4145 /* Defer Count */
2b6b168d
BA		 4146 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4147 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4148 if (!ret_val)
4149 adapter->stats.dc += phy_data;
4150
4151 /* Transmit with no CRS */
2b6b168d
BA		 4152 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4153 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4154 if (!ret_val)
4155 adapter->stats.tncrs += phy_data;
4156
4157release:
4158 hw->phy.ops.release(hw);
4159}
4160
bc7f75fa
AK		 4161/**
4162 * e1000e_update_stats - Update the board statistics counters
4163 * @adapter: board private structure
4164 **/
67fd4fcb 4165static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4166{
7274c20f 4167 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4168 struct e1000_hw *hw = &adapter->hw;
4169 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4170
4171 /*
4172 * Prevent stats update while adapter is being reset, or if the pci
4173 * connection is down.
4174 */
4175 if (adapter->link_speed == 0)
4176 return;
4177 if (pci_channel_offline(pdev))
4178 return;
4179
bc7f75fa
AK		 4180 adapter->stats.crcerrs += er32(CRCERRS);
4181 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4182 adapter->stats.gorc += er32(GORCL);
4183 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4184 adapter->stats.bprc += er32(BPRC);
4185 adapter->stats.mprc += er32(MPRC);
4186 adapter->stats.roc += er32(ROC);
4187
bc7f75fa 4188 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4189
4190 /* Half-duplex statistics */
4191 if (adapter->link_duplex == HALF_DUPLEX) {
4192 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4193 e1000e_update_phy_stats(adapter);
4194 } else {
4195 adapter->stats.scc += er32(SCC);
4196 adapter->stats.ecol += er32(ECOL);
4197 adapter->stats.mcc += er32(MCC);
4198 adapter->stats.latecol += er32(LATECOL);
4199 adapter->stats.dc += er32(DC);
4200
4201 hw->mac.collision_delta = er32(COLC);
4202
4203 if ((hw->mac.type != e1000_82574) &&
4204 (hw->mac.type != e1000_82583))
4205 adapter->stats.tncrs += er32(TNCRS);
4206 }
4207 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4208 }
8c7bbb92 4209
bc7f75fa
AK		 4210 adapter->stats.xonrxc += er32(XONRXC);
4211 adapter->stats.xontxc += er32(XONTXC);
4212 adapter->stats.xoffrxc += er32(XOFFRXC);
4213 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4214 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4215 adapter->stats.gotc += er32(GOTCL);
4216 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4217 adapter->stats.rnbc += er32(RNBC);
4218 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4219
4220 adapter->stats.mptc += er32(MPTC);
4221 adapter->stats.bptc += er32(BPTC);
4222
4223 /* used for adaptive IFS */
4224
4225 hw->mac.tx_packet_delta = er32(TPT);
4226 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4227
4228 adapter->stats.algnerrc += er32(ALGNERRC);
4229 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4230 adapter->stats.cexterr += er32(CEXTERR);
4231 adapter->stats.tsctc += er32(TSCTC);
4232 adapter->stats.tsctfc += er32(TSCTFC);
4233
bc7f75fa 4234 /* Fill out the OS statistics structure */
7274c20f
AK		 4235 netdev->stats.multicast = adapter->stats.mprc;
4236 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4237
4238 /* Rx Errors */
4239
ad68076e
BA		 4240 /*
4241 * RLEC on some newer hardware can be incorrect so build
4242 * our own version based on RUC and ROC
4243 */
7274c20f 4244 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4245 adapter->stats.crcerrs + adapter->stats.algnerrc +
4246 adapter->stats.ruc + adapter->stats.roc +
4247 adapter->stats.cexterr;
7274c20f 4248 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4249 adapter->stats.roc;
7274c20f
AK		 4250 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4251 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4252 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4253
4254 /* Tx Errors */
7274c20f 4255 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4256 adapter->stats.latecol;
7274c20f
AK		 4257 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4258 netdev->stats.tx_window_errors = adapter->stats.latecol;
4259 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4260
4261 /* Tx Dropped needs to be maintained elsewhere */
4262
bc7f75fa
AK		 4263 /* Management Stats */
4264 adapter->stats.mgptc += er32(MGTPTC);
4265 adapter->stats.mgprc += er32(MGTPRC);
4266 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4267}
4268
7c25769f
BA		 4269/**
4270 * e1000_phy_read_status - Update the PHY register status snapshot
4271 * @adapter: board private structure
4272 **/
4273static void e1000_phy_read_status(struct e1000_adapter *adapter)
4274{
4275 struct e1000_hw *hw = &adapter->hw;
4276 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4277
4278 if ((er32(STATUS) & E1000_STATUS_LU) &&
4279 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4280 int ret_val;
4281
7c25769f
BA		 4282 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4283 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4284 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4285 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4286 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4287 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4288 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4289 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4290 if (ret_val)
44defeb3 4291 e_warn("Error reading PHY register\n");
7c25769f
BA		 4292 } else {
4293 /*
4294 * Do not read PHY registers if link is not up
4295 * Set values to typical power-on defaults
4296 */
4297 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4298 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4299 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4300 BMSR_ERCAP);
4301 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4302 ADVERTISE_ALL | ADVERTISE_CSMA);
4303 phy->lpa = 0;
4304 phy->expansion = EXPANSION_ENABLENPAGE;
4305 phy->ctrl1000 = ADVERTISE_1000FULL;
4306 phy->stat1000 = 0;
4307 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4308 }
7c25769f
BA		 4309}
4310
bc7f75fa
AK		 4311static void e1000_print_link_info(struct e1000_adapter *adapter)
4312{
bc7f75fa
AK		 4313 struct e1000_hw *hw = &adapter->hw;
4314 u32 ctrl = er32(CTRL);
4315
8f12fe86 4316 /* Link status message must follow this format for user tools */
ef456f85
JK		 4317 printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4318 adapter->netdev->name,
4319 adapter->link_speed,
4320 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4321 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4322 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4323 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4324}
4325
0c6bdb30 4326static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4327{
4328 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4329 bool link_active = false;
318a94d6
JK		 4330 s32 ret_val = 0;
4331
4332 /*
4333 * get_link_status is set on LSC (link status) interrupt or
4334 * Rx sequence error interrupt. get_link_status will stay
4335 * false until the check_for_link establishes link
4336 * for copper adapters ONLY
4337 */
4338 switch (hw->phy.media_type) {
4339 case e1000_media_type_copper:
4340 if (hw->mac.get_link_status) {
4341 ret_val = hw->mac.ops.check_for_link(hw);
4342 link_active = !hw->mac.get_link_status;
4343 } else {
3db1cd5c 4344 link_active = true;
318a94d6
JK		 4345 }
4346 break;
4347 case e1000_media_type_fiber:
4348 ret_val = hw->mac.ops.check_for_link(hw);
4349 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4350 break;
4351 case e1000_media_type_internal_serdes:
4352 ret_val = hw->mac.ops.check_for_link(hw);
4353 link_active = adapter->hw.mac.serdes_has_link;
4354 break;
4355 default:
4356 case e1000_media_type_unknown:
4357 break;
4358 }
4359
4360 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4361 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4362 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4363 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4364 }
4365
4366 return link_active;
4367}
4368
4369static void e1000e_enable_receives(struct e1000_adapter *adapter)
4370{
4371 /* make sure the receive unit is started */
4372 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
4373 (adapter->flags & FLAG_RX_RESTART_NOW)) {
4374 struct e1000_hw *hw = &adapter->hw;
4375 u32 rctl = er32(RCTL);
4376 ew32(RCTL, rctl | E1000_RCTL_EN);
4377 adapter->flags &= ~FLAG_RX_RESTART_NOW;
4378 }
4379}
4380
ff10e13c
CW		 4381static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4382{
4383 struct e1000_hw *hw = &adapter->hw;
4384
4385 /*
4386 * With 82574 controllers, PHY needs to be checked periodically
4387 * for hung state and reset, if two calls return true
4388 */
4389 if (e1000_check_phy_82574(hw))
4390 adapter->phy_hang_count++;
4391 else
4392 adapter->phy_hang_count = 0;
4393
4394 if (adapter->phy_hang_count > 1) {
4395 adapter->phy_hang_count = 0;
4396 schedule_work(&adapter->reset_task);
4397 }
4398}
4399
bc7f75fa
AK		 4400/**
4401 * e1000_watchdog - Timer Call-back
4402 * @data: pointer to adapter cast into an unsigned long
4403 **/
4404static void e1000_watchdog(unsigned long data)
4405{
4406 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4407
4408 /* Do the rest outside of interrupt context */
4409 schedule_work(&adapter->watchdog_task);
4410
4411 /* TODO: make this use queue_delayed_work() */
4412}
4413
4414static void e1000_watchdog_task(struct work_struct *work)
4415{
4416 struct e1000_adapter *adapter = container_of(work,
4417 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4418 struct net_device *netdev = adapter->netdev;
4419 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4420 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4421 struct e1000_ring *tx_ring = adapter->tx_ring;
4422 struct e1000_hw *hw = &adapter->hw;
4423 u32 link, tctl;
bc7f75fa 4424
615b32af
JB		 4425 if (test_bit(__E1000_DOWN, &adapter->state))
4426 return;
4427
b405e8df 4428 link = e1000e_has_link(adapter);
318a94d6 4429 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4430 /* Cancel scheduled suspend requests. */
4431 pm_runtime_resume(netdev->dev.parent);
4432
318a94d6 4433 e1000e_enable_receives(adapter);
bc7f75fa 4434 goto link_up;
bc7f75fa
AK		 4435 }
4436
4437 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4438 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4439 e1000_update_mng_vlan(adapter);
4440
bc7f75fa
AK		 4441 if (link) {
4442 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4443 bool txb2b = true;
23606cf5
RW		 4444
4445 /* Cancel scheduled suspend requests. */
4446 pm_runtime_resume(netdev->dev.parent);
4447
318a94d6 4448 /* update snapshot of PHY registers on LSC */
7c25769f 4449 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4450 mac->ops.get_link_up_info(&adapter->hw,
4451 &adapter->link_speed,
4452 &adapter->link_duplex);
4453 e1000_print_link_info(adapter);
f4187b56
BA		 4454 /*
4455 * On supported PHYs, check for duplex mismatch only
4456 * if link has autonegotiated at 10/100 half
4457 */
4458 if ((hw->phy.type == e1000_phy_igp_3 ||
4459 hw->phy.type == e1000_phy_bm) &&
4460 (hw->mac.autoneg == true) &&
4461 (adapter->link_speed == SPEED_10 ||
4462 adapter->link_speed == SPEED_100) &&
4463 (adapter->link_duplex == HALF_DUPLEX)) {
4464 u16 autoneg_exp;
4465
4466 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4467
4468 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4469 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4470 }
4471
f49c57e1 4472 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4473 adapter->tx_timeout_factor = 1;
4474 switch (adapter->link_speed) {
4475 case SPEED_10:
3db1cd5c 4476 txb2b = false;
10f1b492 4477 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4478 break;
4479 case SPEED_100:
3db1cd5c 4480 txb2b = false;
4c86e0b9 4481 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4482 break;
4483 }
4484
ad68076e
BA		 4485 /*
4486 * workaround: re-program speed mode bit after
4487 * link-up event
4488 */
bc7f75fa
AK		 4489 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4490 !txb2b) {
4491 u32 tarc0;
e9ec2c0f 4492 tarc0 = er32(TARC(0));
bc7f75fa 4493 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4494 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4495 }
4496
ad68076e
BA		 4497 /*
4498 * disable TSO for pcie and 10/100 speeds, to avoid
4499 * some hardware issues
4500 */
bc7f75fa
AK		 4501 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4502 switch (adapter->link_speed) {
4503 case SPEED_10:
4504 case SPEED_100:
44defeb3 4505 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4506 netdev->features &= ~NETIF_F_TSO;
4507 netdev->features &= ~NETIF_F_TSO6;
4508 break;
4509 case SPEED_1000:
4510 netdev->features |= NETIF_F_TSO;
4511 netdev->features |= NETIF_F_TSO6;
4512 break;
4513 default:
4514 /* oops */
4515 break;
4516 }
4517 }
4518
ad68076e
BA		 4519 /*
4520 * enable transmits in the hardware, need to do this
4521 * after setting TARC(0)
4522 */
bc7f75fa
AK		 4523 tctl = er32(TCTL);
4524 tctl |= E1000_TCTL_EN;
4525 ew32(TCTL, tctl);
4526
75eb0fad
BA		 4527 /*
4528 * Perform any post-link-up configuration before
4529 * reporting link up.
4530 */
4531 if (phy->ops.cfg_on_link_up)
4532 phy->ops.cfg_on_link_up(hw);
4533
bc7f75fa 4534 netif_carrier_on(netdev);
bc7f75fa
AK		 4535
4536 if (!test_bit(__E1000_DOWN, &adapter->state))
4537 mod_timer(&adapter->phy_info_timer,
4538 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4539 }
4540 } else {
4541 if (netif_carrier_ok(netdev)) {
4542 adapter->link_speed = 0;
4543 adapter->link_duplex = 0;
8f12fe86
BA		 4544 /* Link status message must follow this format */
4545 printk(KERN_INFO "e1000e: %s NIC Link is Down\n",
4546 adapter->netdev->name);
bc7f75fa 4547 netif_carrier_off(netdev);
bc7f75fa
AK		 4548 if (!test_bit(__E1000_DOWN, &adapter->state))
4549 mod_timer(&adapter->phy_info_timer,
4550 round_jiffies(jiffies + 2 * HZ));
4551
4552 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
4553 schedule_work(&adapter->reset_task);
23606cf5
RW		 4554 else
4555 pm_schedule_suspend(netdev->dev.parent,
4556 LINK_TIMEOUT);
bc7f75fa
AK		 4557 }
4558 }
4559
4560link_up:
67fd4fcb 4561 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4562 e1000e_update_stats(adapter);
4563
4564 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4565 adapter->tpt_old = adapter->stats.tpt;
4566 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4567 adapter->colc_old = adapter->stats.colc;
4568
7c25769f
BA		 4569 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4570 adapter->gorc_old = adapter->stats.gorc;
4571 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4572 adapter->gotc_old = adapter->stats.gotc;
2084b114 4573 spin_unlock(&adapter->stats64_lock);
bc7f75fa
AK		 4574
4575 e1000e_update_adaptive(&adapter->hw);
4576
90da0669
BA		 4577 if (!netif_carrier_ok(netdev) &&
4578 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
4579 /*
4580 * We've lost link, so the controller stops DMA,
4581 * but we've got queued Tx work that's never going
4582 * to get done, so reset controller to flush Tx.
4583 * (Do the reset outside of interrupt context).
4584 */
90da0669
BA		 4585 schedule_work(&adapter->reset_task);
4586 /* return immediately since reset is imminent */
4587 return;
bc7f75fa
AK		 4588 }
4589
eab2abf5
JB		 4590 /* Simple mode for Interrupt Throttle Rate (ITR) */
4591 if (adapter->itr_setting == 4) {
4592 /*
4593 * Symmetric Tx/Rx gets a reduced ITR=2000;
4594 * Total asymmetrical Tx or Rx gets ITR=8000;
4595 * everyone else is between 2000-8000.
4596 */
4597 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4598 u32 dif = (adapter->gotc > adapter->gorc ?
4599 adapter->gotc - adapter->gorc :
4600 adapter->gorc - adapter->gotc) / 10000;
4601 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4602
4603 ew32(ITR, 1000000000 / (itr * 256));
4604 }
4605
ad68076e 4606 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4607 if (adapter->msix_entries)
4608 ew32(ICS, adapter->rx_ring->ims_val);
4609 else
4610 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4611
713b3c9e
JB		 4612 /* flush pending descriptors to memory before detecting Tx hang */
4613 e1000e_flush_descriptors(adapter);
4614
bc7f75fa 4615 /* Force detection of hung controller every watchdog period */
3db1cd5c 4616 adapter->detect_tx_hung = true;
bc7f75fa 4617
ad68076e
BA		 4618 /*
4619 * With 82571 controllers, LAA may be overwritten due to controller
4620 * reset from the other port. Set the appropriate LAA in RAR[0]
4621 */
bc7f75fa
AK		 4622 if (e1000e_get_laa_state_82571(hw))
4623 e1000e_rar_set(hw, adapter->hw.mac.addr, 0);
4624
ff10e13c
CW		 4625 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4626 e1000e_check_82574_phy_workaround(adapter);
4627
bc7f75fa
AK		 4628 /* Reset the timer */
4629 if (!test_bit(__E1000_DOWN, &adapter->state))
4630 mod_timer(&adapter->watchdog_timer,
4631 round_jiffies(jiffies + 2 * HZ));
4632}
4633
4634#define E1000_TX_FLAGS_CSUM 0x00000001
4635#define E1000_TX_FLAGS_VLAN 0x00000002
4636#define E1000_TX_FLAGS_TSO 0x00000004
4637#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 4638#define E1000_TX_FLAGS_NO_FCS 0x00000010
bc7f75fa
AK		 4639#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4640#define E1000_TX_FLAGS_VLAN_SHIFT 16
4641
55aa6985 4642static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4643{
bc7f75fa
AK		 4644 struct e1000_context_desc *context_desc;
4645 struct e1000_buffer *buffer_info;
4646 unsigned int i;
4647 u32 cmd_length = 0;
4648 u16 ipcse = 0, tucse, mss;
4649 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4650
3d5e33c9
BA		 4651 if (!skb_is_gso(skb))
4652 return 0;
bc7f75fa 4653
3d5e33c9 4654 if (skb_header_cloned(skb)) {
90da0669
BA		 4655 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4656
3d5e33c9
BA		 4657 if (err)
4658 return err;
bc7f75fa
AK		 4659 }
4660
3d5e33c9
BA		 4661 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4662 mss = skb_shinfo(skb)->gso_size;
4663 if (skb->protocol == htons(ETH_P_IP)) {
4664 struct iphdr *iph = ip_hdr(skb);
4665 iph->tot_len = 0;
4666 iph->check = 0;
4667 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4668 0, IPPROTO_TCP, 0);
4669 cmd_length = E1000_TXD_CMD_IP;
4670 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4671 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4672 ipv6_hdr(skb)->payload_len = 0;
4673 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4674 &ipv6_hdr(skb)->daddr,
4675 0, IPPROTO_TCP, 0);
4676 ipcse = 0;
4677 }
4678 ipcss = skb_network_offset(skb);
4679 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4680 tucss = skb_transport_offset(skb);
4681 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
4682 tucse = 0;
4683
4684 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4685 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4686
4687 i = tx_ring->next_to_use;
4688 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4689 buffer_info = &tx_ring->buffer_info[i];
4690
4691 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4692 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4693 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4694 context_desc->upper_setup.tcp_fields.tucss = tucss;
4695 context_desc->upper_setup.tcp_fields.tucso = tucso;
4696 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
4697 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4698 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4699 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4700
4701 buffer_info->time_stamp = jiffies;
4702 buffer_info->next_to_watch = i;
4703
4704 i++;
4705 if (i == tx_ring->count)
4706 i = 0;
4707 tx_ring->next_to_use = i;
4708
4709 return 1;
bc7f75fa
AK		 4710}
4711
55aa6985 4712static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4713{
55aa6985 4714 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4715 struct e1000_context_desc *context_desc;
4716 struct e1000_buffer *buffer_info;
4717 unsigned int i;
4718 u8 css;
af807c82 4719 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4720 __be16 protocol;
bc7f75fa 4721
af807c82
DG		 4722 if (skb->ip_summed != CHECKSUM_PARTIAL)
4723 return 0;
bc7f75fa 4724
5f66f208
AJ		 4725 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4726 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4727 else
4728 protocol = skb->protocol;
4729
3f518390 4730 switch (protocol) {
09640e63 4731 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 4732 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4733 cmd_len |= E1000_TXD_CMD_TCP;
4734 break;
09640e63 4735 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 4736 /* XXX not handling all IPV6 headers */
4737 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4738 cmd_len |= E1000_TXD_CMD_TCP;
4739 break;
4740 default:
4741 if (unlikely(net_ratelimit()))
5f66f208
AJ		 4742 e_warn("checksum_partial proto=%x!\n",
4743 be16_to_cpu(protocol));
af807c82 4744 break;
bc7f75fa
AK		 4745 }
4746
0d0b1672 4747 css = skb_checksum_start_offset(skb);
af807c82
DG		 4748
4749 i = tx_ring->next_to_use;
4750 buffer_info = &tx_ring->buffer_info[i];
4751 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4752
4753 context_desc->lower_setup.ip_config = 0;
4754 context_desc->upper_setup.tcp_fields.tucss = css;
4755 context_desc->upper_setup.tcp_fields.tucso =
4756 css + skb->csum_offset;
4757 context_desc->upper_setup.tcp_fields.tucse = 0;
4758 context_desc->tcp_seg_setup.data = 0;
4759 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
4760
4761 buffer_info->time_stamp = jiffies;
4762 buffer_info->next_to_watch = i;
4763
4764 i++;
4765 if (i == tx_ring->count)
4766 i = 0;
4767 tx_ring->next_to_use = i;
4768
4769 return 1;
bc7f75fa
AK		 4770}
4771
4772#define E1000_MAX_PER_TXD 8192
4773#define E1000_MAX_TXD_PWR 12
4774
55aa6985
BA		 4775static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
4776 unsigned int first, unsigned int max_per_txd,
4777 unsigned int nr_frags, unsigned int mss)
bc7f75fa 4778{
55aa6985 4779 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 4780 struct pci_dev *pdev = adapter->pdev;
1b7719c4 4781 struct e1000_buffer *buffer_info;
8ddc951c 4782 unsigned int len = skb_headlen(skb);
03b1320d 4783 unsigned int offset = 0, size, count = 0, i;
9ed318d5 4784 unsigned int f, bytecount, segs;
bc7f75fa
AK		 4785
4786 i = tx_ring->next_to_use;
4787
4788 while (len) {
1b7719c4 4789 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 4790 size = min(len, max_per_txd);
4791
bc7f75fa 4792 buffer_info->length = size;
bc7f75fa 4793 buffer_info->time_stamp = jiffies;
bc7f75fa 4794 buffer_info->next_to_watch = i;
0be3f55f
NN		 4795 buffer_info->dma = dma_map_single(&pdev->dev,
4796 skb->data + offset,
af667a29 4797 size, DMA_TO_DEVICE);
03b1320d 4798 buffer_info->mapped_as_page = false;
0be3f55f 4799 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4800 goto dma_error;
bc7f75fa
AK		 4801
4802 len -= size;
4803 offset += size;
03b1320d 4804 count++;
1b7719c4
AD		 4805
4806 if (len) {
4807 i++;
4808 if (i == tx_ring->count)
4809 i = 0;
4810 }
bc7f75fa
AK		 4811 }
4812
4813 for (f = 0; f < nr_frags; f++) {
9e903e08 4814 const struct skb_frag_struct *frag;
bc7f75fa
AK		 4815
4816 frag = &skb_shinfo(skb)->frags[f];
9e903e08 4817 len = skb_frag_size(frag);
877749bf 4818 offset = 0;
bc7f75fa
AK		 4819
4820 while (len) {
1b7719c4
AD		 4821 i++;
4822 if (i == tx_ring->count)
4823 i = 0;
4824
bc7f75fa
AK		 4825 buffer_info = &tx_ring->buffer_info[i];
4826 size = min(len, max_per_txd);
bc7f75fa
AK		 4827
4828 buffer_info->length = size;
4829 buffer_info->time_stamp = jiffies;
bc7f75fa 4830 buffer_info->next_to_watch = i;
877749bf
IC		 4831 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
4832 offset, size, DMA_TO_DEVICE);
03b1320d 4833 buffer_info->mapped_as_page = true;
0be3f55f 4834 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4835 goto dma_error;
bc7f75fa
AK		 4836
4837 len -= size;
4838 offset += size;
4839 count++;
bc7f75fa
AK		 4840 }
4841 }
4842
af667a29 4843 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 4844 /* multiply data chunks by size of headers */
4845 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
4846
bc7f75fa 4847 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 4848 tx_ring->buffer_info[i].segs = segs;
4849 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 4850 tx_ring->buffer_info[first].next_to_watch = i;
4851
4852 return count;
03b1320d
AD		 4853
4854dma_error:
af667a29 4855 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 4856 buffer_info->dma = 0;
c1fa347f 4857 if (count)
03b1320d 4858 count--;
c1fa347f
RK		 4859
4860 while (count--) {
af667a29 4861 if (i == 0)
03b1320d 4862 i += tx_ring->count;
c1fa347f 4863 i--;
03b1320d 4864 buffer_info = &tx_ring->buffer_info[i];
55aa6985 4865 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 4866 }
4867
4868 return 0;
bc7f75fa
AK		 4869}
4870
55aa6985 4871static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 4872{
55aa6985 4873 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4874 struct e1000_tx_desc *tx_desc = NULL;
4875 struct e1000_buffer *buffer_info;
4876 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
4877 unsigned int i;
4878
4879 if (tx_flags & E1000_TX_FLAGS_TSO) {
4880 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
4881 E1000_TXD_CMD_TSE;
4882 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4883
4884 if (tx_flags & E1000_TX_FLAGS_IPV4)
4885 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
4886 }
4887
4888 if (tx_flags & E1000_TX_FLAGS_CSUM) {
4889 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
4890 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4891 }
4892
4893 if (tx_flags & E1000_TX_FLAGS_VLAN) {
4894 txd_lower |= E1000_TXD_CMD_VLE;
4895 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
4896 }
4897
943146de
BG		 4898 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4899 txd_lower &= ~(E1000_TXD_CMD_IFCS);
4900
bc7f75fa
AK		 4901 i = tx_ring->next_to_use;
4902
36b973df 4903 do {
bc7f75fa
AK		 4904 buffer_info = &tx_ring->buffer_info[i];
4905 tx_desc = E1000_TX_DESC(*tx_ring, i);
4906 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4907 tx_desc->lower.data =
4908 cpu_to_le32(txd_lower | buffer_info->length);
4909 tx_desc->upper.data = cpu_to_le32(txd_upper);
4910
4911 i++;
4912 if (i == tx_ring->count)
4913 i = 0;
36b973df 4914 } while (--count > 0);
bc7f75fa
AK		 4915
4916 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
4917
943146de
BG		 4918 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
4919 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
4920 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
4921
ad68076e
BA		 4922 /*
4923 * Force memory writes to complete before letting h/w
bc7f75fa
AK		 4924 * know there are new descriptors to fetch. (Only
4925 * applicable for weak-ordered memory model archs,
ad68076e
BA		 4926 * such as IA-64).
4927 */
bc7f75fa
AK		 4928 wmb();
4929
4930 tx_ring->next_to_use = i;
c6e7f51e
BA		 4931
4932 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 4933 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 4934 else
c5083cf6 4935 writel(i, tx_ring->tail);
c6e7f51e 4936
ad68076e
BA		 4937 /*
4938 * we need this if more than one processor can write to our tail
4939 * at a time, it synchronizes IO on IA64/Altix systems
4940 */
bc7f75fa
AK		 4941 mmiowb();
4942}
4943
4944#define MINIMUM_DHCP_PACKET_SIZE 282
4945static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
4946 struct sk_buff *skb)
4947{
4948 struct e1000_hw *hw = &adapter->hw;
4949 u16 length, offset;
4950
4951 if (vlan_tx_tag_present(skb)) {
8e95a202
JP		 4952 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
4953 (adapter->hw.mng_cookie.status &
bc7f75fa
AK		 4954 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4955 return 0;
4956 }
4957
4958 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
4959 return 0;
4960
4961 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
4962 return 0;
4963
4964 {
4965 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
4966 struct udphdr *udp;
4967
4968 if (ip->protocol != IPPROTO_UDP)
4969 return 0;
4970
4971 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
4972 if (ntohs(udp->dest) != 67)
4973 return 0;
4974
4975 offset = (u8 *)udp + 8 - skb->data;
4976 length = skb->len - offset;
4977 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
4978 }
4979
4980 return 0;
4981}
4982
55aa6985 4983static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4984{
55aa6985 4985 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 4986
55aa6985 4987 netif_stop_queue(adapter->netdev);
ad68076e
BA		 4988 /*
4989 * Herbert's original patch had:
bc7f75fa 4990 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 4991 * but since that doesn't exist yet, just open code it.
4992 */
bc7f75fa
AK		 4993 smp_mb();
4994
ad68076e
BA		 4995 /*
4996 * We need to check again in a case another CPU has just
4997 * made room available.
4998 */
55aa6985 4999 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5000 return -EBUSY;
5001
5002 /* A reprieve! */
55aa6985 5003 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5004 ++adapter->restart_queue;
5005 return 0;
5006}
5007
55aa6985 5008static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5009{
55aa6985 5010 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5011 return 0;
55aa6985 5012 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5013}
5014
0e15df49 5015#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1)
3b29a56d
SH		 5016static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5017 struct net_device *netdev)
bc7f75fa
AK		 5018{
5019 struct e1000_adapter *adapter = netdev_priv(netdev);
5020 struct e1000_ring *tx_ring = adapter->tx_ring;
5021 unsigned int first;
5022 unsigned int max_per_txd = E1000_MAX_PER_TXD;
5023 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
5024 unsigned int tx_flags = 0;
e743d313 5025 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5026 unsigned int nr_frags;
5027 unsigned int mss;
bc7f75fa
AK		 5028 int count = 0;
5029 int tso;
5030 unsigned int f;
bc7f75fa
AK		 5031
5032 if (test_bit(__E1000_DOWN, &adapter->state)) {
5033 dev_kfree_skb_any(skb);
5034 return NETDEV_TX_OK;
5035 }
5036
5037 if (skb->len <= 0) {
5038 dev_kfree_skb_any(skb);
5039 return NETDEV_TX_OK;
5040 }
5041
5042 mss = skb_shinfo(skb)->gso_size;
ad68076e
BA		 5043 /*
5044 * The controller does a simple calculation to
bc7f75fa
AK		 5045 * make sure there is enough room in the FIFO before
5046 * initiating the DMA for each buffer. The calc is:
5047 * 4 = ceil(buffer len/mss). To make sure we don't
5048 * overrun the FIFO, adjust the max buffer len if mss
ad68076e
BA		 5049 * drops.
5050 */
bc7f75fa
AK		 5051 if (mss) {
5052 u8 hdr_len;
5053 max_per_txd = min(mss << 2, max_per_txd);
5054 max_txd_pwr = fls(max_per_txd) - 1;
5055
ad68076e
BA		 5056 /*
5057 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
5058 * points to just header, pull a few bytes of payload from
5059 * frags into skb->data
5060 */
bc7f75fa 5061 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
ad68076e
BA		 5062 /*
5063 * we do this workaround for ES2LAN, but it is un-necessary,
5064 * avoiding it could save a lot of cycles
5065 */
4e6c709c 5066 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5067 unsigned int pull_size;
5068
a2a5b323 5069 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5070 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5071 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5072 dev_kfree_skb_any(skb);
5073 return NETDEV_TX_OK;
5074 }
e743d313 5075 len = skb_headlen(skb);
bc7f75fa
AK		 5076 }
5077 }
5078
5079 /* reserve a descriptor for the offload context */
5080 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5081 count++;
5082 count++;
5083
5084 count += TXD_USE_COUNT(len, max_txd_pwr);
5085
5086 nr_frags = skb_shinfo(skb)->nr_frags;
5087 for (f = 0; f < nr_frags; f++)
9e903e08 5088 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->frags[f]),
bc7f75fa
AK		 5089 max_txd_pwr);
5090
5091 if (adapter->hw.mac.tx_pkt_filtering)
5092 e1000_transfer_dhcp_info(adapter, skb);
5093
ad68076e
BA		 5094 /*
5095 * need: count + 2 desc gap to keep tail from touching
5096 * head, otherwise try next time
5097 */
55aa6985 5098 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5099 return NETDEV_TX_BUSY;
bc7f75fa 5100
eab6d18d 5101 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5102 tx_flags |= E1000_TX_FLAGS_VLAN;
5103 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5104 }
5105
5106 first = tx_ring->next_to_use;
5107
55aa6985 5108 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5109 if (tso < 0) {
5110 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5111 return NETDEV_TX_OK;
5112 }
5113
5114 if (tso)
5115 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5116 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5117 tx_flags |= E1000_TX_FLAGS_CSUM;
5118
ad68076e
BA		 5119 /*
5120 * Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5121 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5122 * no longer assume, we must.
5123 */
bc7f75fa
AK		 5124 if (skb->protocol == htons(ETH_P_IP))
5125 tx_flags |= E1000_TX_FLAGS_IPV4;
5126
943146de
BG		 5127 if (unlikely(skb->no_fcs))
5128 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5129
25985edc 5130 /* if count is 0 then mapping error has occurred */
55aa6985 5131 count = e1000_tx_map(tx_ring, skb, first, max_per_txd, nr_frags, mss);
1b7719c4 5132 if (count) {
3f0cfa3b 5133 netdev_sent_queue(netdev, skb->len);
55aa6985 5134 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5135 /* Make sure there is space in the ring for the next send. */
55aa6985 5136 e1000_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 2);
1b7719c4
AD		 5137
5138 } else {
bc7f75fa 5139 dev_kfree_skb_any(skb);
1b7719c4
AD		 5140 tx_ring->buffer_info[first].time_stamp = 0;
5141 tx_ring->next_to_use = first;
bc7f75fa
AK		 5142 }
5143
bc7f75fa
AK		 5144 return NETDEV_TX_OK;
5145}
5146
5147/**
5148 * e1000_tx_timeout - Respond to a Tx Hang
5149 * @netdev: network interface device structure
5150 **/
5151static void e1000_tx_timeout(struct net_device *netdev)
5152{
5153 struct e1000_adapter *adapter = netdev_priv(netdev);
5154
5155 /* Do the reset outside of interrupt context */
5156 adapter->tx_timeout_count++;
5157 schedule_work(&adapter->reset_task);
5158}
5159
5160static void e1000_reset_task(struct work_struct *work)
5161{
5162 struct e1000_adapter *adapter;
5163 adapter = container_of(work, struct e1000_adapter, reset_task);
5164
615b32af
JB		 5165 /* don't run the task if already down */
5166 if (test_bit(__E1000_DOWN, &adapter->state))
5167 return;
5168
affa9dfb
CW		 5169 if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5170 (adapter->flags & FLAG_RX_RESTART_NOW))) {
5171 e1000e_dump(adapter);
5172 e_err("Reset adapter\n");
5173 }
bc7f75fa
AK		 5174 e1000e_reinit_locked(adapter);
5175}
5176
5177/**
67fd4fcb 5178 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5179 * @netdev: network interface device structure
67fd4fcb 5180 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5181 *
5182 * Returns the address of the device statistics structure.
bc7f75fa 5183 **/
67fd4fcb
JK		 5184struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5185 struct rtnl_link_stats64 *stats)
bc7f75fa 5186{
67fd4fcb
JK		 5187 struct e1000_adapter *adapter = netdev_priv(netdev);
5188
5189 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5190 spin_lock(&adapter->stats64_lock);
5191 e1000e_update_stats(adapter);
5192 /* Fill out the OS statistics structure */
5193 stats->rx_bytes = adapter->stats.gorc;
5194 stats->rx_packets = adapter->stats.gprc;
5195 stats->tx_bytes = adapter->stats.gotc;
5196 stats->tx_packets = adapter->stats.gptc;
5197 stats->multicast = adapter->stats.mprc;
5198 stats->collisions = adapter->stats.colc;
5199
5200 /* Rx Errors */
5201
5202 /*
5203 * RLEC on some newer hardware can be incorrect so build
5204 * our own version based on RUC and ROC
5205 */
5206 stats->rx_errors = adapter->stats.rxerrc +
5207 adapter->stats.crcerrs + adapter->stats.algnerrc +
5208 adapter->stats.ruc + adapter->stats.roc +
5209 adapter->stats.cexterr;
5210 stats->rx_length_errors = adapter->stats.ruc +
5211 adapter->stats.roc;
5212 stats->rx_crc_errors = adapter->stats.crcerrs;
5213 stats->rx_frame_errors = adapter->stats.algnerrc;
5214 stats->rx_missed_errors = adapter->stats.mpc;
5215
5216 /* Tx Errors */
5217 stats->tx_errors = adapter->stats.ecol +
5218 adapter->stats.latecol;
5219 stats->tx_aborted_errors = adapter->stats.ecol;
5220 stats->tx_window_errors = adapter->stats.latecol;
5221 stats->tx_carrier_errors = adapter->stats.tncrs;
5222
5223 /* Tx Dropped needs to be maintained elsewhere */
5224
5225 spin_unlock(&adapter->stats64_lock);
5226 return stats;
bc7f75fa
AK		 5227}
5228
5229/**
5230 * e1000_change_mtu - Change the Maximum Transfer Unit
5231 * @netdev: network interface device structure
5232 * @new_mtu: new value for maximum frame size
5233 *
5234 * Returns 0 on success, negative on failure
5235 **/
5236static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5237{
5238 struct e1000_adapter *adapter = netdev_priv(netdev);
5239 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5240
2adc55c9 5241 /* Jumbo frame support */
70495a50
BA		 5242 if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) {
5243 if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5244 e_err("Jumbo Frames not supported.\n");
5245 return -EINVAL;
5246 }
5247
5248 /*
5249 * IP payload checksum (enabled with jumbos/packet-split when
5250 * Rx checksum is enabled) and generation of RSS hash is
5251 * mutually exclusive in the hardware.
5252 */
5253 if ((netdev->features & NETIF_F_RXCSUM) &&
5254 (netdev->features & NETIF_F_RXHASH)) {
5255 e_err("Jumbo frames cannot be enabled when both receive checksum offload and receive hashing are enabled. Disable one of the receive offload features before enabling jumbos.\n");
5256 return -EINVAL;
5257 }
bc7f75fa
AK		 5258 }
5259
2adc55c9
BA		 5260 /* Supported frame sizes */
5261 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5262 (max_frame > adapter->max_hw_frame_size)) {
5263 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5264 return -EINVAL;
5265 }
5266
a1ce6473
BA		 5267 /* Jumbo frame workaround on 82579 requires CRC be stripped */
5268 if ((adapter->hw.mac.type == e1000_pch2lan) &&
5269 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5270 (new_mtu > ETH_DATA_LEN)) {
ef456f85 5271 e_err("Jumbo Frames not supported on 82579 when CRC stripping is disabled.\n");
a1ce6473
BA		 5272 return -EINVAL;
5273 }
5274
6f461f6c
BA		 5275 /* 82573 Errata 17 */
5276 if (((adapter->hw.mac.type == e1000_82573) ||
5277 (adapter->hw.mac.type == e1000_82574)) &&
5278 (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN)) {
5279 adapter->flags2 |= FLAG2_DISABLE_ASPM_L1;
5280 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L1);
5281 }
5282
bc7f75fa 5283 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5284 usleep_range(1000, 2000);
610c9928 5285 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5286 adapter->max_frame_size = max_frame;
610c9928
BA		 5287 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5288 netdev->mtu = new_mtu;
bc7f75fa
AK		 5289 if (netif_running(netdev))
5290 e1000e_down(adapter);
5291
ad68076e
BA		 5292 /*
5293 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5294 * means we reserve 2 more, this pushes us to allocate from the next
5295 * larger slab size.
ad68076e 5296 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5297 * However with the new *_jumbo_rx* routines, jumbo receives will use
5298 * fragmented skbs
ad68076e 5299 */
bc7f75fa 5300
9926146b 5301 if (max_frame <= 2048)
bc7f75fa
AK		 5302 adapter->rx_buffer_len = 2048;
5303 else
5304 adapter->rx_buffer_len = 4096;
5305
5306 /* adjust allocation if LPE protects us, and we aren't using SBP */
5307 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5308 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5309 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5310 + ETH_FCS_LEN;
bc7f75fa 5311
bc7f75fa
AK		 5312 if (netif_running(netdev))
5313 e1000e_up(adapter);
5314 else
5315 e1000e_reset(adapter);
5316
5317 clear_bit(__E1000_RESETTING, &adapter->state);
5318
5319 return 0;
5320}
5321
5322static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5323 int cmd)
5324{
5325 struct e1000_adapter *adapter = netdev_priv(netdev);
5326 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5327
318a94d6 5328 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5329 return -EOPNOTSUPP;
5330
5331 switch (cmd) {
5332 case SIOCGMIIPHY:
5333 data->phy_id = adapter->hw.phy.addr;
5334 break;
5335 case SIOCGMIIREG:
b16a002e
BA		 5336 e1000_phy_read_status(adapter);
5337
7c25769f
BA		 5338 switch (data->reg_num & 0x1F) {
5339 case MII_BMCR:
5340 data->val_out = adapter->phy_regs.bmcr;
5341 break;
5342 case MII_BMSR:
5343 data->val_out = adapter->phy_regs.bmsr;
5344 break;
5345 case MII_PHYSID1:
5346 data->val_out = (adapter->hw.phy.id >> 16);
5347 break;
5348 case MII_PHYSID2:
5349 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5350 break;
5351 case MII_ADVERTISE:
5352 data->val_out = adapter->phy_regs.advertise;
5353 break;
5354 case MII_LPA:
5355 data->val_out = adapter->phy_regs.lpa;
5356 break;
5357 case MII_EXPANSION:
5358 data->val_out = adapter->phy_regs.expansion;
5359 break;
5360 case MII_CTRL1000:
5361 data->val_out = adapter->phy_regs.ctrl1000;
5362 break;
5363 case MII_STAT1000:
5364 data->val_out = adapter->phy_regs.stat1000;
5365 break;
5366 case MII_ESTATUS:
5367 data->val_out = adapter->phy_regs.estatus;
5368 break;
5369 default:
bc7f75fa
AK		 5370 return -EIO;
5371 }
bc7f75fa
AK		 5372 break;
5373 case SIOCSMIIREG:
5374 default:
5375 return -EOPNOTSUPP;
5376 }
5377 return 0;
5378}
5379
5380static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5381{
5382 switch (cmd) {
5383 case SIOCGMIIPHY:
5384 case SIOCGMIIREG:
5385 case SIOCSMIIREG:
5386 return e1000_mii_ioctl(netdev, ifr, cmd);
5387 default:
5388 return -EOPNOTSUPP;
5389 }
5390}
5391
a4f58f54
BA		 5392static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5393{
5394 struct e1000_hw *hw = &adapter->hw;
5395 u32 i, mac_reg;
2b6b168d 5396 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5397 int retval = 0;
5398
5399 /* copy MAC RARs to PHY RARs */
d3738bb8 5400 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5401
2b6b168d
BA		 5402 retval = hw->phy.ops.acquire(hw);
5403 if (retval) {
5404 e_err("Could not acquire PHY\n");
5405 return retval;
5406 }
5407
5408 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5409 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5410 if (retval)
75ce1532 5411 goto release;
2b6b168d
BA		 5412
5413 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5414 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5415 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5416 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5417 (u16)(mac_reg & 0xFFFF));
5418 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5419 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5420 }
5421
5422 /* configure PHY Rx Control register */
2b6b168d 5423 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5424 mac_reg = er32(RCTL);
5425 if (mac_reg & E1000_RCTL_UPE)
5426 phy_reg |= BM_RCTL_UPE;
5427 if (mac_reg & E1000_RCTL_MPE)
5428 phy_reg |= BM_RCTL_MPE;
5429 phy_reg &= ~(BM_RCTL_MO_MASK);
5430 if (mac_reg & E1000_RCTL_MO_3)
5431 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5432 << BM_RCTL_MO_SHIFT);
5433 if (mac_reg & E1000_RCTL_BAM)
5434 phy_reg |= BM_RCTL_BAM;
5435 if (mac_reg & E1000_RCTL_PMCF)
5436 phy_reg |= BM_RCTL_PMCF;
5437 mac_reg = er32(CTRL);
5438 if (mac_reg & E1000_CTRL_RFCE)
5439 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5440 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5441
5442 /* enable PHY wakeup in MAC register */
5443 ew32(WUFC, wufc);
5444 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5445
5446 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5447 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5448 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5449
5450 /* activate PHY wakeup */
2b6b168d
BA		 5451 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5452 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5453 if (retval)
5454 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5455release:
94d8186a 5456 hw->phy.ops.release(hw);
a4f58f54
BA		 5457
5458 return retval;
5459}
5460
23606cf5
RW		 5461static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5462 bool runtime)
bc7f75fa
AK		 5463{
5464 struct net_device *netdev = pci_get_drvdata(pdev);
5465 struct e1000_adapter *adapter = netdev_priv(netdev);
5466 struct e1000_hw *hw = &adapter->hw;
5467 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5468 /* Runtime suspend should only enable wakeup for link changes */
5469 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5470 int retval = 0;
5471
5472 netif_device_detach(netdev);
5473
5474 if (netif_running(netdev)) {
5475 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5476 e1000e_down(adapter);
5477 e1000_free_irq(adapter);
5478 }
4662e82b 5479 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5480
5481 retval = pci_save_state(pdev);
5482 if (retval)
5483 return retval;
5484
5485 status = er32(STATUS);
5486 if (status & E1000_STATUS_LU)
5487 wufc &= ~E1000_WUFC_LNKC;
5488
5489 if (wufc) {
5490 e1000_setup_rctl(adapter);
ef9b965a 5491 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5492
5493 /* turn on all-multi mode if wake on multicast is enabled */
5494 if (wufc & E1000_WUFC_MC) {
5495 rctl = er32(RCTL);
5496 rctl |= E1000_RCTL_MPE;
5497 ew32(RCTL, rctl);
5498 }
5499
5500 ctrl = er32(CTRL);
5501 /* advertise wake from D3Cold */
5502 #define E1000_CTRL_ADVD3WUC 0x00100000
5503 /* phy power management enable */
5504 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5505 ctrl |= E1000_CTRL_ADVD3WUC;
5506 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5507 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5508 ew32(CTRL, ctrl);
5509
318a94d6
JK		 5510 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5511 adapter->hw.phy.media_type ==
5512 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5513 /* keep the laser running in D3 */
5514 ctrl_ext = er32(CTRL_EXT);
93a23f48 5515 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5516 ew32(CTRL_EXT, ctrl_ext);
5517 }
5518
97ac8cae 5519 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5520 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5521
bc7f75fa
AK		 5522 /* Allow time for pending master requests to run */
5523 e1000e_disable_pcie_master(&adapter->hw);
5524
82776a4b 5525 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5526 /* enable wakeup by the PHY */
5527 retval = e1000_init_phy_wakeup(adapter, wufc);
5528 if (retval)
5529 return retval;
5530 } else {
5531 /* enable wakeup by the MAC */
5532 ew32(WUFC, wufc);
5533 ew32(WUC, E1000_WUC_PME_EN);
5534 }
bc7f75fa
AK		 5535 } else {
5536 ew32(WUC, 0);
5537 ew32(WUFC, 0);
bc7f75fa
AK		 5538 }
5539
4f9de721
RW		 5540 *enable_wake = !!wufc;
5541
bc7f75fa 5542 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5543 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5544 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5545 *enable_wake = true;
bc7f75fa
AK		 5546
5547 if (adapter->hw.phy.type == e1000_phy_igp_3)
5548 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5549
ad68076e
BA		 5550 /*
5551 * Release control of h/w to f/w. If f/w is AMT enabled, this
5552 * would have already happened in close and is redundant.
5553 */
31dbe5b4 5554 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5555
5556 pci_disable_device(pdev);
5557
4f9de721
RW		 5558 return 0;
5559}
5560
5561static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5562{
5563 if (sleep && wake) {
5564 pci_prepare_to_sleep(pdev);
5565 return;
5566 }
5567
5568 pci_wake_from_d3(pdev, wake);
5569 pci_set_power_state(pdev, PCI_D3hot);
5570}
5571
5572static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5573 bool wake)
5574{
5575 struct net_device *netdev = pci_get_drvdata(pdev);
5576 struct e1000_adapter *adapter = netdev_priv(netdev);
5577
005cbdfc
AD		 5578 /*
5579 * The pci-e switch on some quad port adapters will report a
5580 * correctable error when the MAC transitions from D0 to D3. To
5581 * prevent this we need to mask off the correctable errors on the
5582 * downstream port of the pci-e switch.
5583 */
5584 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5585 struct pci_dev *us_dev = pdev->bus->self;
353064de 5586 int pos = pci_pcie_cap(us_dev);
005cbdfc
AD		 5587 u16 devctl;
5588
5589 pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
5590 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
5591 (devctl & ~PCI_EXP_DEVCTL_CERE));
5592
4f9de721 5593 e1000_power_off(pdev, sleep, wake);
005cbdfc
AD		 5594
5595 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
5596 } else {
4f9de721 5597 e1000_power_off(pdev, sleep, wake);
005cbdfc 5598 }
bc7f75fa
AK		 5599}
5600
6f461f6c
BA		 5601#ifdef CONFIG_PCIEASPM
5602static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5603{
9f728f53 5604 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5605}
5606#else
5607static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2
AK		 5608{
5609 int pos;
6f461f6c 5610 u16 reg16;
1eae4eb2
AK		 5611
5612 /*
6f461f6c
BA		 5613 * Both device and parent should have the same ASPM setting.
5614 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5615 */
6f461f6c
BA		 5616 pos = pci_pcie_cap(pdev);
5617 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
5618 reg16 &= ~state;
5619 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
5620
0c75ba22
AB		 5621 if (!pdev->bus->self)
5622 return;
5623
6f461f6c
BA		 5624 pos = pci_pcie_cap(pdev->bus->self);
5625 pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, &reg16);
5626 reg16 &= ~state;
5627 pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
5628}
5629#endif
78cd29d5 5630static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5631{
5632 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5633 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5634 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5635
5636 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5637}
5638
aa338601 5639#ifdef CONFIG_PM
23606cf5 5640static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5641{
23606cf5 5642 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5643}
5644
23606cf5 5645static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5646{
5647 struct net_device *netdev = pci_get_drvdata(pdev);
5648 struct e1000_adapter *adapter = netdev_priv(netdev);
5649 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5650 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5651 u32 err;
5652
78cd29d5
BA		 5653 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5654 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5655 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5656 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5657 if (aspm_disable_flag)
5658 e1000e_disable_aspm(pdev, aspm_disable_flag);
5659
bc7f75fa
AK		 5660 pci_set_power_state(pdev, PCI_D0);
5661 pci_restore_state(pdev);
28b8f04a 5662 pci_save_state(pdev);
6e4f6f6b 5663
4662e82b 5664 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5665 if (netif_running(netdev)) {
5666 err = e1000_request_irq(adapter);
5667 if (err)
5668 return err;
5669 }
5670
99730e4c
BA		 5671 if (hw->mac.type == e1000_pch2lan)
5672 e1000_resume_workarounds_pchlan(&adapter->hw);
5673
bc7f75fa 5674 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5675
5676 /* report the system wakeup cause from S3/S4 */
5677 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5678 u16 phy_data;
5679
5680 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5681 if (phy_data) {
5682 e_info("PHY Wakeup cause - %s\n",
5683 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5684 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5685 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5686 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5687 phy_data & E1000_WUS_LNKC ?
5688 "Link Status Change" : "other");
a4f58f54
BA		 5689 }
5690 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5691 } else {
5692 u32 wus = er32(WUS);
5693 if (wus) {
5694 e_info("MAC Wakeup cause - %s\n",
5695 wus & E1000_WUS_EX ? "Unicast Packet" :
5696 wus & E1000_WUS_MC ? "Multicast Packet" :
5697 wus & E1000_WUS_BC ? "Broadcast Packet" :
5698 wus & E1000_WUS_MAG ? "Magic Packet" :
5699 wus & E1000_WUS_LNKC ? "Link Status Change" :
5700 "other");
5701 }
5702 ew32(WUS, ~0);
5703 }
5704
bc7f75fa 5705 e1000e_reset(adapter);
bc7f75fa 5706
cd791618 5707 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5708
5709 if (netif_running(netdev))
5710 e1000e_up(adapter);
5711
5712 netif_device_attach(netdev);
5713
ad68076e
BA		 5714 /*
5715 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5716 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5717 * under the control of the driver.
5718 */
c43bc57e 5719 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5720 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5721
5722 return 0;
5723}
23606cf5 5724
a0340162
RW		 5725#ifdef CONFIG_PM_SLEEP
5726static int e1000_suspend(struct device *dev)
5727{
5728 struct pci_dev *pdev = to_pci_dev(dev);
5729 int retval;
5730 bool wake;
5731
5732 retval = __e1000_shutdown(pdev, &wake, false);
5733 if (!retval)
5734 e1000_complete_shutdown(pdev, true, wake);
5735
5736 return retval;
5737}
5738
23606cf5
RW		 5739static int e1000_resume(struct device *dev)
5740{
5741 struct pci_dev *pdev = to_pci_dev(dev);
5742 struct net_device *netdev = pci_get_drvdata(pdev);
5743 struct e1000_adapter *adapter = netdev_priv(netdev);
5744
5745 if (e1000e_pm_ready(adapter))
5746 adapter->idle_check = true;
5747
5748 return __e1000_resume(pdev);
5749}
a0340162
RW		 5750#endif /* CONFIG_PM_SLEEP */
5751
5752#ifdef CONFIG_PM_RUNTIME
5753static int e1000_runtime_suspend(struct device *dev)
5754{
5755 struct pci_dev *pdev = to_pci_dev(dev);
5756 struct net_device *netdev = pci_get_drvdata(pdev);
5757 struct e1000_adapter *adapter = netdev_priv(netdev);
5758
5759 if (e1000e_pm_ready(adapter)) {
5760 bool wake;
5761
5762 __e1000_shutdown(pdev, &wake, true);
5763 }
5764
5765 return 0;
5766}
5767
5768static int e1000_idle(struct device *dev)
5769{
5770 struct pci_dev *pdev = to_pci_dev(dev);
5771 struct net_device *netdev = pci_get_drvdata(pdev);
5772 struct e1000_adapter *adapter = netdev_priv(netdev);
5773
5774 if (!e1000e_pm_ready(adapter))
5775 return 0;
5776
5777 if (adapter->idle_check) {
5778 adapter->idle_check = false;
5779 if (!e1000e_has_link(adapter))
5780 pm_schedule_suspend(dev, MSEC_PER_SEC);
5781 }
5782
5783 return -EBUSY;
5784}
23606cf5
RW		 5785
5786static int e1000_runtime_resume(struct device *dev)
5787{
5788 struct pci_dev *pdev = to_pci_dev(dev);
5789 struct net_device *netdev = pci_get_drvdata(pdev);
5790 struct e1000_adapter *adapter = netdev_priv(netdev);
5791
5792 if (!e1000e_pm_ready(adapter))
5793 return 0;
5794
5795 adapter->idle_check = !dev->power.runtime_auto;
5796 return __e1000_resume(pdev);
5797}
a0340162 5798#endif /* CONFIG_PM_RUNTIME */
aa338601 5799#endif /* CONFIG_PM */
bc7f75fa
AK		 5800
5801static void e1000_shutdown(struct pci_dev *pdev)
5802{
4f9de721
RW		 5803 bool wake = false;
5804
23606cf5 5805 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 5806
5807 if (system_state == SYSTEM_POWER_OFF)
5808 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 5809}
5810
5811#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 5812
5813static irqreturn_t e1000_intr_msix(int irq, void *data)
5814{
5815 struct net_device *netdev = data;
5816 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 5817
5818 if (adapter->msix_entries) {
90da0669
BA		 5819 int vector, msix_irq;
5820
147b2c8c
DD		 5821 vector = 0;
5822 msix_irq = adapter->msix_entries[vector].vector;
5823 disable_irq(msix_irq);
5824 e1000_intr_msix_rx(msix_irq, netdev);
5825 enable_irq(msix_irq);
5826
5827 vector++;
5828 msix_irq = adapter->msix_entries[vector].vector;
5829 disable_irq(msix_irq);
5830 e1000_intr_msix_tx(msix_irq, netdev);
5831 enable_irq(msix_irq);
5832
5833 vector++;
5834 msix_irq = adapter->msix_entries[vector].vector;
5835 disable_irq(msix_irq);
5836 e1000_msix_other(msix_irq, netdev);
5837 enable_irq(msix_irq);
5838 }
5839
5840 return IRQ_HANDLED;
5841}
5842
bc7f75fa
AK		 5843/*
5844 * Polling 'interrupt' - used by things like netconsole to send skbs
5845 * without having to re-enable interrupts. It's not called while
5846 * the interrupt routine is executing.
5847 */
5848static void e1000_netpoll(struct net_device *netdev)
5849{
5850 struct e1000_adapter *adapter = netdev_priv(netdev);
5851
147b2c8c
DD		 5852 switch (adapter->int_mode) {
5853 case E1000E_INT_MODE_MSIX:
5854 e1000_intr_msix(adapter->pdev->irq, netdev);
5855 break;
5856 case E1000E_INT_MODE_MSI:
5857 disable_irq(adapter->pdev->irq);
5858 e1000_intr_msi(adapter->pdev->irq, netdev);
5859 enable_irq(adapter->pdev->irq);
5860 break;
5861 default: /* E1000E_INT_MODE_LEGACY */
5862 disable_irq(adapter->pdev->irq);
5863 e1000_intr(adapter->pdev->irq, netdev);
5864 enable_irq(adapter->pdev->irq);
5865 break;
5866 }
bc7f75fa
AK		 5867}
5868#endif
5869
5870/**
5871 * e1000_io_error_detected - called when PCI error is detected
5872 * @pdev: Pointer to PCI device
5873 * @state: The current pci connection state
5874 *
5875 * This function is called after a PCI bus error affecting
5876 * this device has been detected.
5877 */
5878static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
5879 pci_channel_state_t state)
5880{
5881 struct net_device *netdev = pci_get_drvdata(pdev);
5882 struct e1000_adapter *adapter = netdev_priv(netdev);
5883
5884 netif_device_detach(netdev);
5885
c93b5a76
MM		 5886 if (state == pci_channel_io_perm_failure)
5887 return PCI_ERS_RESULT_DISCONNECT;
5888
bc7f75fa
AK		 5889 if (netif_running(netdev))
5890 e1000e_down(adapter);
5891 pci_disable_device(pdev);
5892
5893 /* Request a slot slot reset. */
5894 return PCI_ERS_RESULT_NEED_RESET;
5895}
5896
5897/**
5898 * e1000_io_slot_reset - called after the pci bus has been reset.
5899 * @pdev: Pointer to PCI device
5900 *
5901 * Restart the card from scratch, as if from a cold-boot. Implementation
5902 * resembles the first-half of the e1000_resume routine.
5903 */
5904static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5905{
5906 struct net_device *netdev = pci_get_drvdata(pdev);
5907 struct e1000_adapter *adapter = netdev_priv(netdev);
5908 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5909 u16 aspm_disable_flag = 0;
6e4f6f6b 5910 int err;
111b9dc5 5911 pci_ers_result_t result;
bc7f75fa 5912
78cd29d5
BA		 5913 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5914 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5915 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 5916 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5917 if (aspm_disable_flag)
5918 e1000e_disable_aspm(pdev, aspm_disable_flag);
5919
f0f422e5 5920 err = pci_enable_device_mem(pdev);
6e4f6f6b 5921 if (err) {
bc7f75fa
AK		 5922 dev_err(&pdev->dev,
5923 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 5924 result = PCI_ERS_RESULT_DISCONNECT;
5925 } else {
5926 pci_set_master(pdev);
23606cf5 5927 pdev->state_saved = true;
111b9dc5 5928 pci_restore_state(pdev);
bc7f75fa 5929
111b9dc5
JB		 5930 pci_enable_wake(pdev, PCI_D3hot, 0);
5931 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 5932
111b9dc5
JB		 5933 e1000e_reset(adapter);
5934 ew32(WUS, ~0);
5935 result = PCI_ERS_RESULT_RECOVERED;
5936 }
bc7f75fa 5937
111b9dc5
JB		 5938 pci_cleanup_aer_uncorrect_error_status(pdev);
5939
5940 return result;
bc7f75fa
AK		 5941}
5942
5943/**
5944 * e1000_io_resume - called when traffic can start flowing again.
5945 * @pdev: Pointer to PCI device
5946 *
5947 * This callback is called when the error recovery driver tells us that
5948 * its OK to resume normal operation. Implementation resembles the
5949 * second-half of the e1000_resume routine.
5950 */
5951static void e1000_io_resume(struct pci_dev *pdev)
5952{
5953 struct net_device *netdev = pci_get_drvdata(pdev);
5954 struct e1000_adapter *adapter = netdev_priv(netdev);
5955
cd791618 5956 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5957
5958 if (netif_running(netdev)) {
5959 if (e1000e_up(adapter)) {
5960 dev_err(&pdev->dev,
5961 "can't bring device back up after reset\n");
5962 return;
5963 }
5964 }
5965
5966 netif_device_attach(netdev);
5967
ad68076e
BA		 5968 /*
5969 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5970 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5971 * under the control of the driver.
5972 */
c43bc57e 5973 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5974 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5975
5976}
5977
5978static void e1000_print_device_info(struct e1000_adapter *adapter)
5979{
5980 struct e1000_hw *hw = &adapter->hw;
5981 struct net_device *netdev = adapter->netdev;
073287c0
BA		 5982 u32 ret_val;
5983 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 5984
5985 /* print bus type/speed/width info */
a5cc7642 5986 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 5987 /* bus width */
5988 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
5989 "Width x1"),
5990 /* MAC address */
7c510e4b 5991 netdev->dev_addr);
44defeb3
JK		 5992 e_info("Intel(R) PRO/%s Network Connection\n",
5993 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 5994 ret_val = e1000_read_pba_string_generic(hw, pba_str,
5995 E1000_PBANUM_LENGTH);
5996 if (ret_val)
f2315bf1 5997 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 5998 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
5999 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6000}
6001
10aa4c04
AK		 6002static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6003{
6004 struct e1000_hw *hw = &adapter->hw;
6005 int ret_val;
6006 u16 buf = 0;
6007
6008 if (hw->mac.type != e1000_82573)
6009 return;
6010
6011 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6012 le16_to_cpus(&buf);
6013 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6014 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6015 dev_warn(&adapter->pdev->dev,
6016 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6017 }
10aa4c04
AK		 6018}
6019
c8f44aff 6020static int e1000_set_features(struct net_device *netdev,
70495a50 6021 netdev_features_t features)
dc221294
BA		 6022{
6023 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6024 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6025
6026 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6027 adapter->flags |= FLAG_TSO_FORCE;
6028
6029 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
cf955e6c
BG		 6030 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6031 NETIF_F_RXALL)))
dc221294
BA		 6032 return 0;
6033
70495a50
BA		 6034 /*
6035 * IP payload checksum (enabled with jumbos/packet-split when Rx
6036 * checksum is enabled) and generation of RSS hash is mutually
6037 * exclusive in the hardware.
6038 */
6039 if (adapter->rx_ps_pages &&
6040 (features & NETIF_F_RXCSUM) && (features & NETIF_F_RXHASH)) {
6041 e_err("Enabling both receive checksum offload and receive hashing is not possible with jumbo frames. Disable jumbos or enable only one of the receive offload features.\n");
6042 return -EINVAL;
6043 }
6044
0184039a
BG		 6045 if (changed & NETIF_F_RXFCS) {
6046 if (features & NETIF_F_RXFCS) {
6047 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6048 } else {
6049 /* We need to take it back to defaults, which might mean
6050 * stripping is still disabled at the adapter level.
6051 */
6052 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6053 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6054 else
6055 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6056 }
6057 }
6058
70495a50
BA		 6059 netdev->features = features;
6060
dc221294
BA		 6061 if (netif_running(netdev))
6062 e1000e_reinit_locked(adapter);
6063 else
6064 e1000e_reset(adapter);
6065
6066 return 0;
6067}
6068
651c2466
SH		 6069static const struct net_device_ops e1000e_netdev_ops = {
6070 .ndo_open = e1000_open,
6071 .ndo_stop = e1000_close,
00829823 6072 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6073 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6074 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6075 .ndo_set_mac_address = e1000_set_mac,
6076 .ndo_change_mtu = e1000_change_mtu,
6077 .ndo_do_ioctl = e1000_ioctl,
6078 .ndo_tx_timeout = e1000_tx_timeout,
6079 .ndo_validate_addr = eth_validate_addr,
6080
651c2466
SH		 6081 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6082 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6083#ifdef CONFIG_NET_POLL_CONTROLLER
6084 .ndo_poll_controller = e1000_netpoll,
6085#endif
dc221294 6086 .ndo_set_features = e1000_set_features,
651c2466
SH		 6087};
6088
bc7f75fa
AK		 6089/**
6090 * e1000_probe - Device Initialization Routine
6091 * @pdev: PCI device information struct
6092 * @ent: entry in e1000_pci_tbl
6093 *
6094 * Returns 0 on success, negative on failure
6095 *
6096 * e1000_probe initializes an adapter identified by a pci_dev structure.
6097 * The OS initialization, configuring of the adapter private structure,
6098 * and a hardware reset occur.
6099 **/
6100static int __devinit e1000_probe(struct pci_dev *pdev,
6101 const struct pci_device_id *ent)
6102{
6103 struct net_device *netdev;
6104 struct e1000_adapter *adapter;
6105 struct e1000_hw *hw;
6106 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6107 resource_size_t mmio_start, mmio_len;
6108 resource_size_t flash_start, flash_len;
bc7f75fa 6109 static int cards_found;
78cd29d5 6110 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6111 int i, err, pci_using_dac;
6112 u16 eeprom_data = 0;
6113 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6114
78cd29d5
BA		 6115 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6116 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6117 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6118 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6119 if (aspm_disable_flag)
6120 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6121
f0f422e5 6122 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6123 if (err)
6124 return err;
6125
6126 pci_using_dac = 0;
0be3f55f 6127 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6128 if (!err) {
0be3f55f 6129 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6130 if (!err)
6131 pci_using_dac = 1;
6132 } else {
0be3f55f 6133 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6134 if (err) {
0be3f55f
NN		 6135 err = dma_set_coherent_mask(&pdev->dev,
6136 DMA_BIT_MASK(32));
bc7f75fa 6137 if (err) {
ef456f85 6138 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6139 goto err_dma;
6140 }
6141 }
6142 }
6143
e8de1481 6144 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6145 pci_select_bars(pdev, IORESOURCE_MEM),
6146 e1000e_driver_name);
bc7f75fa
AK		 6147 if (err)
6148 goto err_pci_reg;
6149
68eac460 6150 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6151 pci_enable_pcie_error_reporting(pdev);
68eac460 6152
bc7f75fa 6153 pci_set_master(pdev);
438b365a
BA		 6154 /* PCI config space info */
6155 err = pci_save_state(pdev);
6156 if (err)
6157 goto err_alloc_etherdev;
bc7f75fa
AK		 6158
6159 err = -ENOMEM;
6160 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6161 if (!netdev)
6162 goto err_alloc_etherdev;
6163
bc7f75fa
AK		 6164 SET_NETDEV_DEV(netdev, &pdev->dev);
6165
f85e4dfa
TH		 6166 netdev->irq = pdev->irq;
6167
bc7f75fa
AK		 6168 pci_set_drvdata(pdev, netdev);
6169 adapter = netdev_priv(netdev);
6170 hw = &adapter->hw;
6171 adapter->netdev = netdev;
6172 adapter->pdev = pdev;
6173 adapter->ei = ei;
6174 adapter->pba = ei->pba;
6175 adapter->flags = ei->flags;
eb7c3adb 6176 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6177 adapter->hw.adapter = adapter;
6178 adapter->hw.mac.type = ei->mac;
2adc55c9 6179 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6180 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6181
6182 mmio_start = pci_resource_start(pdev, 0);
6183 mmio_len = pci_resource_len(pdev, 0);
6184
6185 err = -EIO;
6186 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6187 if (!adapter->hw.hw_addr)
6188 goto err_ioremap;
6189
6190 if ((adapter->flags & FLAG_HAS_FLASH) &&
6191 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6192 flash_start = pci_resource_start(pdev, 1);
6193 flash_len = pci_resource_len(pdev, 1);
6194 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6195 if (!adapter->hw.flash_address)
6196 goto err_flashmap;
6197 }
6198
6199 /* construct the net_device struct */
651c2466 6200 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6201 e1000e_set_ethtool_ops(netdev);
bc7f75fa
AK		 6202 netdev->watchdog_timeo = 5 * HZ;
6203 netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
f2315bf1 6204 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6205
6206 netdev->mem_start = mmio_start;
6207 netdev->mem_end = mmio_start + mmio_len;
6208
6209 adapter->bd_number = cards_found++;
6210
4662e82b
BA		 6211 e1000e_check_options(adapter);
6212
bc7f75fa
AK		 6213 /* setup adapter struct */
6214 err = e1000_sw_init(adapter);
6215 if (err)
6216 goto err_sw_init;
6217
bc7f75fa
AK		 6218 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6219 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6220 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6221
69e3fd8c 6222 err = ei->get_variants(adapter);
bc7f75fa
AK		 6223 if (err)
6224 goto err_hw_init;
6225
4a770358
BA		 6226 if ((adapter->flags & FLAG_IS_ICH) &&
6227 (adapter->flags & FLAG_READ_ONLY_NVM))
6228 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6229
bc7f75fa
AK		 6230 hw->mac.ops.get_bus_info(&adapter->hw);
6231
318a94d6 6232 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6233
6234 /* Copper options */
318a94d6 6235 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6236 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6237 adapter->hw.phy.disable_polarity_correction = 0;
6238 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6239 }
6240
44abd5c1 6241 if (hw->phy.ops.check_reset_block(hw))
44defeb3 6242 e_info("PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6243
dc221294
BA		 6244 /* Set initial default active device features */
6245 netdev->features = (NETIF_F_SG |
6246 NETIF_F_HW_VLAN_RX |
6247 NETIF_F_HW_VLAN_TX |
6248 NETIF_F_TSO |
6249 NETIF_F_TSO6 |
70495a50 6250 NETIF_F_RXHASH |
dc221294
BA		 6251 NETIF_F_RXCSUM |
6252 NETIF_F_HW_CSUM);
6253
6254 /* Set user-changeable features (subset of all device features) */
6255 netdev->hw_features = netdev->features;
0184039a 6256 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6257 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6258 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6259
6260 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6261 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6262
dc221294
BA		 6263 netdev->vlan_features |= (NETIF_F_SG |
6264 NETIF_F_TSO |
6265 NETIF_F_TSO6 |
6266 NETIF_F_HW_CSUM);
a5136e23 6267
ef9b965a
JB		 6268 netdev->priv_flags |= IFF_UNICAST_FLT;
6269
7b872a55 6270 if (pci_using_dac) {
bc7f75fa 6271 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6272 netdev->vlan_features |= NETIF_F_HIGHDMA;
6273 }
bc7f75fa 6274
bc7f75fa
AK		 6275 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6276 adapter->flags |= FLAG_MNG_PT_ENABLED;
6277
ad68076e
BA		 6278 /*
6279 * before reading the NVM, reset the controller to
6280 * put the device in a known good starting state
6281 */
bc7f75fa
AK		 6282 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6283
6284 /*
6285 * systems with ASPM and others may see the checksum fail on the first
6286 * attempt. Let's give it a few tries
6287 */
6288 for (i = 0;; i++) {
6289 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6290 break;
6291 if (i == 2) {
44defeb3 6292 e_err("The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6293 err = -EIO;
6294 goto err_eeprom;
6295 }
6296 }
6297
10aa4c04
AK		 6298 e1000_eeprom_checks(adapter);
6299
608f8a0d 6300 /* copy the MAC address */
bc7f75fa 6301 if (e1000e_read_mac_addr(&adapter->hw))
44defeb3 6302 e_err("NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6303
6304 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
6305 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
6306
6307 if (!is_valid_ether_addr(netdev->perm_addr)) {
7c510e4b 6308 e_err("Invalid MAC Address: %pM\n", netdev->perm_addr);
bc7f75fa
AK		 6309 err = -EIO;
6310 goto err_eeprom;
6311 }
6312
6313 init_timer(&adapter->watchdog_timer);
c061b18d 6314 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6315 adapter->watchdog_timer.data = (unsigned long) adapter;
6316
6317 init_timer(&adapter->phy_info_timer);
c061b18d 6318 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6319 adapter->phy_info_timer.data = (unsigned long) adapter;
6320
6321 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6322 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6323 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6324 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6325 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6326
bc7f75fa
AK		 6327 /* Initialize link parameters. User can change them with ethtool */
6328 adapter->hw.mac.autoneg = 1;
3db1cd5c 6329 adapter->fc_autoneg = true;
5c48ef3e
BA		 6330 adapter->hw.fc.requested_mode = e1000_fc_default;
6331 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6332 adapter->hw.phy.autoneg_advertised = 0x2f;
6333
6334 /* ring size defaults */
6335 adapter->rx_ring->count = 256;
6336 adapter->tx_ring->count = 256;
6337
6338 /*
6339 * Initial Wake on LAN setting - If APM wake is enabled in
6340 * the EEPROM, enable the ACPI Magic Packet filter
6341 */
6342 if (adapter->flags & FLAG_APME_IN_WUC) {
6343 /* APME bit in EEPROM is mapped to WUC.APME */
6344 eeprom_data = er32(WUC);
6345 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6346 if ((hw->mac.type > e1000_ich10lan) &&
6347 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6348 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6349 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6350 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6351 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6352 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6353 1, &eeprom_data);
bc7f75fa 6354 else
3d3a1676
BA		 6355 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6356 1, &eeprom_data);
bc7f75fa
AK		 6357 }
6358
6359 /* fetch WoL from EEPROM */
6360 if (eeprom_data & eeprom_apme_mask)
6361 adapter->eeprom_wol |= E1000_WUFC_MAG;
6362
6363 /*
6364 * now that we have the eeprom settings, apply the special cases
6365 * where the eeprom may be wrong or the board simply won't support
6366 * wake on lan on a particular port
6367 */
6368 if (!(adapter->flags & FLAG_HAS_WOL))
6369 adapter->eeprom_wol = 0;
6370
6371 /* initialize the wol settings based on the eeprom settings */
6372 adapter->wol = adapter->eeprom_wol;
6ff68026 6373 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6374
84527590
BA		 6375 /* save off EEPROM version number */
6376 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6377
bc7f75fa
AK		 6378 /* reset the hardware with the new settings */
6379 e1000e_reset(adapter);
6380
ad68076e
BA		 6381 /*
6382 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6383 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6384 * under the control of the driver.
6385 */
c43bc57e 6386 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6387 e1000e_get_hw_control(adapter);
bc7f75fa 6388
f2315bf1 6389 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6390 err = register_netdev(netdev);
6391 if (err)
6392 goto err_register;
6393
9c563d20
JB		 6394 /* carrier off reporting is important to ethtool even BEFORE open */
6395 netif_carrier_off(netdev);
6396
bc7f75fa
AK		 6397 e1000_print_device_info(adapter);
6398
f3ec4f87
AS		 6399 if (pci_dev_run_wake(pdev))
6400 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6401
bc7f75fa
AK		 6402 return 0;
6403
6404err_register:
c43bc57e 6405 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6406 e1000e_release_hw_control(adapter);
bc7f75fa 6407err_eeprom:
44abd5c1 6408 if (!hw->phy.ops.check_reset_block(hw))
bc7f75fa 6409 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6410err_hw_init:
bc7f75fa
AK		 6411 kfree(adapter->tx_ring);
6412 kfree(adapter->rx_ring);
6413err_sw_init:
c43bc57e
JB		 6414 if (adapter->hw.flash_address)
6415 iounmap(adapter->hw.flash_address);
e82f54ba 6416 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6417err_flashmap:
bc7f75fa
AK		 6418 iounmap(adapter->hw.hw_addr);
6419err_ioremap:
6420 free_netdev(netdev);
6421err_alloc_etherdev:
f0f422e5
BA		 6422 pci_release_selected_regions(pdev,
6423 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6424err_pci_reg:
6425err_dma:
6426 pci_disable_device(pdev);
6427 return err;
6428}
6429
6430/**
6431 * e1000_remove - Device Removal Routine
6432 * @pdev: PCI device information struct
6433 *
6434 * e1000_remove is called by the PCI subsystem to alert the driver
6435 * that it should release a PCI device. The could be caused by a
6436 * Hot-Plug event, or because the driver is going to be removed from
6437 * memory.
6438 **/
6439static void __devexit e1000_remove(struct pci_dev *pdev)
6440{
6441 struct net_device *netdev = pci_get_drvdata(pdev);
6442 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6443 bool down = test_bit(__E1000_DOWN, &adapter->state);
6444
ad68076e 6445 /*
23f333a2
TH		 6446 * The timers may be rescheduled, so explicitly disable them
6447 * from being rescheduled.
ad68076e 6448 */
23606cf5
RW		 6449 if (!down)
6450 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6451 del_timer_sync(&adapter->watchdog_timer);
6452 del_timer_sync(&adapter->phy_info_timer);
6453
41cec6f1
BA		 6454 cancel_work_sync(&adapter->reset_task);
6455 cancel_work_sync(&adapter->watchdog_task);
6456 cancel_work_sync(&adapter->downshift_task);
6457 cancel_work_sync(&adapter->update_phy_task);
6458 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6459
17f208de
BA		 6460 if (!(netdev->flags & IFF_UP))
6461 e1000_power_down_phy(adapter);
6462
23606cf5
RW		 6463 /* Don't lie to e1000_close() down the road. */
6464 if (!down)
6465 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6466 unregister_netdev(netdev);
6467
f3ec4f87
AS		 6468 if (pci_dev_run_wake(pdev))
6469 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6470
ad68076e
BA		 6471 /*
6472 * Release control of h/w to f/w. If f/w is AMT enabled, this
6473 * would have already happened in close and is redundant.
6474 */
31dbe5b4 6475 e1000e_release_hw_control(adapter);
bc7f75fa 6476
4662e82b 6477 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6478 kfree(adapter->tx_ring);
6479 kfree(adapter->rx_ring);
6480
6481 iounmap(adapter->hw.hw_addr);
6482 if (adapter->hw.flash_address)
6483 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6484 pci_release_selected_regions(pdev,
6485 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6486
6487 free_netdev(netdev);
6488
111b9dc5 6489 /* AER disable */
19d5afd4 6490 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6491
bc7f75fa
AK		 6492 pci_disable_device(pdev);
6493}
6494
6495/* PCI Error Recovery (ERS) */
6496static struct pci_error_handlers e1000_err_handler = {
6497 .error_detected = e1000_io_error_detected,
6498 .slot_reset = e1000_io_slot_reset,
6499 .resume = e1000_io_resume,
6500};
6501
a3aa1884 6502static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6504 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6505 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6506 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6507 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6508 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6509 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6510 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6511 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6512
bc7f75fa
AK		 6513 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6514 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6515 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6516 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6517
bc7f75fa
AK		 6518 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6519 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6520 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6521
4662e82b 6522 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6523 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6524 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6525
bc7f75fa
AK		 6526 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6527 board_80003es2lan },
6528 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6529 board_80003es2lan },
6530 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6531 board_80003es2lan },
6532 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6533 board_80003es2lan },
ad68076e 6534
bc7f75fa
AK		 6535 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6536 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6537 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6538 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6539 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6540 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6541 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6542 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6543
bc7f75fa
AK		 6544 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6545 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6546 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6547 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6548 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6549 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6550 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6551 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6552 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6553
6554 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6555 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6556 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6557
f4187b56
BA		 6558 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6559 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6560 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6561
a4f58f54
BA		 6562 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6563 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6564 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6565 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6566
d3738bb8
BA		 6567 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6568 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6569
f36bb6ca 6570 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 6571};
6572MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6573
aa338601 6574#ifdef CONFIG_PM
23606cf5 6575static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6576 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6577 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6578 e1000_runtime_resume, e1000_idle)
23606cf5 6579};
e50208a0 6580#endif
23606cf5 6581
bc7f75fa
AK		 6582/* PCI Device API Driver */
6583static struct pci_driver e1000_driver = {
6584 .name = e1000e_driver_name,
6585 .id_table = e1000_pci_tbl,
6586 .probe = e1000_probe,
6587 .remove = __devexit_p(e1000_remove),
aa338601 6588#ifdef CONFIG_PM
f36bb6ca
BA		 6589 .driver = {
6590 .pm = &e1000_pm_ops,
6591 },
bc7f75fa
AK		 6592#endif
6593 .shutdown = e1000_shutdown,
6594 .err_handler = &e1000_err_handler
6595};
6596
6597/**
6598 * e1000_init_module - Driver Registration Routine
6599 *
6600 * e1000_init_module is the first routine called when the driver is
6601 * loaded. All it does is register with the PCI subsystem.
6602 **/
6603static int __init e1000_init_module(void)
6604{
6605 int ret;
8544b9f7
BA		 6606 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6607 e1000e_driver_version);
f5e261e6 6608 pr_info("Copyright(c) 1999 - 2012 Intel Corporation.\n");
bc7f75fa 6609 ret = pci_register_driver(&e1000_driver);
53ec5498 6610
bc7f75fa
AK		 6611 return ret;
6612}
6613module_init(e1000_init_module);
6614
6615/**
6616 * e1000_exit_module - Driver Exit Cleanup Routine
6617 *
6618 * e1000_exit_module is called just before the driver is removed
6619 * from memory.
6620 **/
6621static void __exit e1000_exit_module(void)
6622{
6623 pci_unregister_driver(&e1000_driver);
6624}
6625module_exit(e1000_exit_module);
6626
6627
6628MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6629MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6630MODULE_LICENSE("GPL");
6631MODULE_VERSION(DRV_VERSION);
6632
06c24b91 6633/* netdev.c */
Linux 6.x block layer and io_uring tree(s)