Commit | Line | Data |
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e78b80b1 | 1 | /* Intel PRO/1000 Linux driver |
529498cd | 2 | * Copyright(c) 1999 - 2015 Intel Corporation. |
e78b80b1 DE |
3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * The full GNU General Public License is included in this distribution in | |
14 | * the file called "COPYING". | |
15 | * | |
16 | * Contact Information: | |
17 | * Linux NICS <linux.nics@intel.com> | |
18 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
20 | */ | |
bc7f75fa | 21 | |
8544b9f7 BA |
22 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
23 | ||
bc7f75fa AK |
24 | #include <linux/module.h> |
25 | #include <linux/types.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/pci.h> | |
28 | #include <linux/vmalloc.h> | |
29 | #include <linux/pagemap.h> | |
30 | #include <linux/delay.h> | |
31 | #include <linux/netdevice.h> | |
9fb7a5f7 | 32 | #include <linux/interrupt.h> |
bc7f75fa AK |
33 | #include <linux/tcp.h> |
34 | #include <linux/ipv6.h> | |
5a0e3ad6 | 35 | #include <linux/slab.h> |
bc7f75fa AK |
36 | #include <net/checksum.h> |
37 | #include <net/ip6_checksum.h> | |
bc7f75fa AK |
38 | #include <linux/ethtool.h> |
39 | #include <linux/if_vlan.h> | |
40 | #include <linux/cpu.h> | |
41 | #include <linux/smp.h> | |
e8db0be1 | 42 | #include <linux/pm_qos.h> |
23606cf5 | 43 | #include <linux/pm_runtime.h> |
111b9dc5 | 44 | #include <linux/aer.h> |
70c71606 | 45 | #include <linux/prefetch.h> |
bc7f75fa AK |
46 | |
47 | #include "e1000.h" | |
48 | ||
b3ccf267 | 49 | #define DRV_EXTRAVERSION "-k" |
c14c643b | 50 | |
d2d7d4e4 | 51 | #define DRV_VERSION "3.2.6" DRV_EXTRAVERSION |
bc7f75fa AK |
52 | char e1000e_driver_name[] = "e1000e"; |
53 | const char e1000e_driver_version[] = DRV_VERSION; | |
54 | ||
b3f4d599 | 55 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
56 | static int debug = -1; | |
57 | module_param(debug, int, 0); | |
58 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
59 | ||
bc7f75fa AK |
60 | static const struct e1000_info *e1000_info_tbl[] = { |
61 | [board_82571] = &e1000_82571_info, | |
62 | [board_82572] = &e1000_82572_info, | |
63 | [board_82573] = &e1000_82573_info, | |
4662e82b | 64 | [board_82574] = &e1000_82574_info, |
8c81c9c3 | 65 | [board_82583] = &e1000_82583_info, |
bc7f75fa AK |
66 | [board_80003es2lan] = &e1000_es2_info, |
67 | [board_ich8lan] = &e1000_ich8_info, | |
68 | [board_ich9lan] = &e1000_ich9_info, | |
f4187b56 | 69 | [board_ich10lan] = &e1000_ich10_info, |
a4f58f54 | 70 | [board_pchlan] = &e1000_pch_info, |
d3738bb8 | 71 | [board_pch2lan] = &e1000_pch2_info, |
2fbe4526 | 72 | [board_pch_lpt] = &e1000_pch_lpt_info, |
79849ebc | 73 | [board_pch_spt] = &e1000_pch_spt_info, |
3a3173b9 | 74 | [board_pch_cnp] = &e1000_pch_cnp_info, |
bc7f75fa AK |
75 | }; |
76 | ||
84f4ee90 TI |
77 | struct e1000_reg_info { |
78 | u32 ofs; | |
79 | char *name; | |
80 | }; | |
81 | ||
84f4ee90 | 82 | static const struct e1000_reg_info e1000_reg_info_tbl[] = { |
84f4ee90 TI |
83 | /* General Registers */ |
84 | {E1000_CTRL, "CTRL"}, | |
85 | {E1000_STATUS, "STATUS"}, | |
86 | {E1000_CTRL_EXT, "CTRL_EXT"}, | |
87 | ||
88 | /* Interrupt Registers */ | |
89 | {E1000_ICR, "ICR"}, | |
90 | ||
af667a29 | 91 | /* Rx Registers */ |
84f4ee90 | 92 | {E1000_RCTL, "RCTL"}, |
1e36052e BA |
93 | {E1000_RDLEN(0), "RDLEN"}, |
94 | {E1000_RDH(0), "RDH"}, | |
95 | {E1000_RDT(0), "RDT"}, | |
84f4ee90 TI |
96 | {E1000_RDTR, "RDTR"}, |
97 | {E1000_RXDCTL(0), "RXDCTL"}, | |
98 | {E1000_ERT, "ERT"}, | |
1e36052e BA |
99 | {E1000_RDBAL(0), "RDBAL"}, |
100 | {E1000_RDBAH(0), "RDBAH"}, | |
84f4ee90 TI |
101 | {E1000_RDFH, "RDFH"}, |
102 | {E1000_RDFT, "RDFT"}, | |
103 | {E1000_RDFHS, "RDFHS"}, | |
104 | {E1000_RDFTS, "RDFTS"}, | |
105 | {E1000_RDFPC, "RDFPC"}, | |
106 | ||
af667a29 | 107 | /* Tx Registers */ |
84f4ee90 | 108 | {E1000_TCTL, "TCTL"}, |
1e36052e BA |
109 | {E1000_TDBAL(0), "TDBAL"}, |
110 | {E1000_TDBAH(0), "TDBAH"}, | |
111 | {E1000_TDLEN(0), "TDLEN"}, | |
112 | {E1000_TDH(0), "TDH"}, | |
113 | {E1000_TDT(0), "TDT"}, | |
84f4ee90 TI |
114 | {E1000_TIDV, "TIDV"}, |
115 | {E1000_TXDCTL(0), "TXDCTL"}, | |
116 | {E1000_TADV, "TADV"}, | |
117 | {E1000_TARC(0), "TARC"}, | |
118 | {E1000_TDFH, "TDFH"}, | |
119 | {E1000_TDFT, "TDFT"}, | |
120 | {E1000_TDFHS, "TDFHS"}, | |
121 | {E1000_TDFTS, "TDFTS"}, | |
122 | {E1000_TDFPC, "TDFPC"}, | |
123 | ||
124 | /* List Terminator */ | |
f36bb6ca | 125 | {0, NULL} |
84f4ee90 TI |
126 | }; |
127 | ||
c6f3148c AK |
128 | /** |
129 | * __ew32_prepare - prepare to write to MAC CSR register on certain parts | |
130 | * @hw: pointer to the HW structure | |
131 | * | |
132 | * When updating the MAC CSR registers, the Manageability Engine (ME) could | |
133 | * be accessing the registers at the same time. Normally, this is handled in | |
134 | * h/w by an arbiter but on some parts there is a bug that acknowledges Host | |
135 | * accesses later than it should which could result in the register to have | |
136 | * an incorrect value. Workaround this by checking the FWSM register which | |
137 | * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set | |
138 | * and try again a number of times. | |
139 | **/ | |
140 | s32 __ew32_prepare(struct e1000_hw *hw) | |
141 | { | |
142 | s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT; | |
143 | ||
144 | while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i) | |
145 | udelay(50); | |
146 | ||
147 | return i; | |
148 | } | |
149 | ||
150 | void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val) | |
151 | { | |
152 | if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) | |
153 | __ew32_prepare(hw); | |
154 | ||
155 | writel(val, hw->hw_addr + reg); | |
156 | } | |
157 | ||
e921eb1a | 158 | /** |
84f4ee90 | 159 | * e1000_regdump - register printout routine |
e921eb1a BA |
160 | * @hw: pointer to the HW structure |
161 | * @reginfo: pointer to the register info table | |
162 | **/ | |
84f4ee90 TI |
163 | static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo) |
164 | { | |
165 | int n = 0; | |
166 | char rname[16]; | |
167 | u32 regs[8]; | |
168 | ||
169 | switch (reginfo->ofs) { | |
170 | case E1000_RXDCTL(0): | |
171 | for (n = 0; n < 2; n++) | |
172 | regs[n] = __er32(hw, E1000_RXDCTL(n)); | |
173 | break; | |
174 | case E1000_TXDCTL(0): | |
175 | for (n = 0; n < 2; n++) | |
176 | regs[n] = __er32(hw, E1000_TXDCTL(n)); | |
177 | break; | |
178 | case E1000_TARC(0): | |
179 | for (n = 0; n < 2; n++) | |
180 | regs[n] = __er32(hw, E1000_TARC(n)); | |
181 | break; | |
182 | default: | |
ef456f85 JK |
183 | pr_info("%-15s %08x\n", |
184 | reginfo->name, __er32(hw, reginfo->ofs)); | |
84f4ee90 TI |
185 | return; |
186 | } | |
187 | ||
188 | snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]"); | |
ef456f85 | 189 | pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]); |
84f4ee90 TI |
190 | } |
191 | ||
f0c5dadf ET |
192 | static void e1000e_dump_ps_pages(struct e1000_adapter *adapter, |
193 | struct e1000_buffer *bi) | |
194 | { | |
195 | int i; | |
196 | struct e1000_ps_page *ps_page; | |
197 | ||
198 | for (i = 0; i < adapter->rx_ps_pages; i++) { | |
199 | ps_page = &bi->ps_pages[i]; | |
200 | ||
201 | if (ps_page->page) { | |
202 | pr_info("packet dump for ps_page %d:\n", i); | |
203 | print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, | |
204 | 16, 1, page_address(ps_page->page), | |
205 | PAGE_SIZE, true); | |
206 | } | |
207 | } | |
208 | } | |
209 | ||
e921eb1a | 210 | /** |
af667a29 | 211 | * e1000e_dump - Print registers, Tx-ring and Rx-ring |
e921eb1a BA |
212 | * @adapter: board private structure |
213 | **/ | |
84f4ee90 TI |
214 | static void e1000e_dump(struct e1000_adapter *adapter) |
215 | { | |
216 | struct net_device *netdev = adapter->netdev; | |
217 | struct e1000_hw *hw = &adapter->hw; | |
218 | struct e1000_reg_info *reginfo; | |
219 | struct e1000_ring *tx_ring = adapter->tx_ring; | |
220 | struct e1000_tx_desc *tx_desc; | |
af667a29 | 221 | struct my_u0 { |
e885d762 BA |
222 | __le64 a; |
223 | __le64 b; | |
af667a29 | 224 | } *u0; |
84f4ee90 TI |
225 | struct e1000_buffer *buffer_info; |
226 | struct e1000_ring *rx_ring = adapter->rx_ring; | |
227 | union e1000_rx_desc_packet_split *rx_desc_ps; | |
5f450212 | 228 | union e1000_rx_desc_extended *rx_desc; |
af667a29 | 229 | struct my_u1 { |
e885d762 BA |
230 | __le64 a; |
231 | __le64 b; | |
232 | __le64 c; | |
233 | __le64 d; | |
af667a29 | 234 | } *u1; |
84f4ee90 TI |
235 | u32 staterr; |
236 | int i = 0; | |
237 | ||
238 | if (!netif_msg_hw(adapter)) | |
239 | return; | |
240 | ||
241 | /* Print netdevice Info */ | |
242 | if (netdev) { | |
243 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
4a7c9726 TK |
244 | pr_info("Device Name state trans_start\n"); |
245 | pr_info("%-15s %016lX %016lX\n", netdev->name, | |
246 | netdev->state, dev_trans_start(netdev)); | |
84f4ee90 TI |
247 | } |
248 | ||
249 | /* Print Registers */ | |
250 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
ef456f85 | 251 | pr_info(" Register Name Value\n"); |
84f4ee90 TI |
252 | for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl; |
253 | reginfo->name; reginfo++) { | |
254 | e1000_regdump(hw, reginfo); | |
255 | } | |
256 | ||
af667a29 | 257 | /* Print Tx Ring Summary */ |
84f4ee90 | 258 | if (!netdev || !netif_running(netdev)) |
fe1e980f | 259 | return; |
84f4ee90 | 260 | |
af667a29 | 261 | dev_info(&adapter->pdev->dev, "Tx Ring Summary\n"); |
ef456f85 | 262 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
84f4ee90 | 263 | buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean]; |
ef456f85 JK |
264 | pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n", |
265 | 0, tx_ring->next_to_use, tx_ring->next_to_clean, | |
266 | (unsigned long long)buffer_info->dma, | |
267 | buffer_info->length, | |
268 | buffer_info->next_to_watch, | |
269 | (unsigned long long)buffer_info->time_stamp); | |
84f4ee90 | 270 | |
af667a29 | 271 | /* Print Tx Ring */ |
84f4ee90 TI |
272 | if (!netif_msg_tx_done(adapter)) |
273 | goto rx_ring_summary; | |
274 | ||
af667a29 | 275 | dev_info(&adapter->pdev->dev, "Tx Ring Dump\n"); |
84f4ee90 TI |
276 | |
277 | /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended) | |
278 | * | |
279 | * Legacy Transmit Descriptor | |
280 | * +--------------------------------------------------------------+ | |
281 | * 0 | Buffer Address [63:0] (Reserved on Write Back) | | |
282 | * +--------------------------------------------------------------+ | |
283 | * 8 | Special | CSS | Status | CMD | CSO | Length | | |
284 | * +--------------------------------------------------------------+ | |
285 | * 63 48 47 36 35 32 31 24 23 16 15 0 | |
286 | * | |
287 | * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload | |
288 | * 63 48 47 40 39 32 31 16 15 8 7 0 | |
289 | * +----------------------------------------------------------------+ | |
290 | * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS | | |
291 | * +----------------------------------------------------------------+ | |
292 | * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN | | |
293 | * +----------------------------------------------------------------+ | |
294 | * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 | |
295 | * | |
296 | * Extended Data Descriptor (DTYP=0x1) | |
297 | * +----------------------------------------------------------------+ | |
298 | * 0 | Buffer Address [63:0] | | |
299 | * +----------------------------------------------------------------+ | |
300 | * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN | | |
301 | * +----------------------------------------------------------------+ | |
302 | * 63 48 47 40 39 36 35 32 31 24 23 20 19 0 | |
303 | */ | |
ef456f85 JK |
304 | pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n"); |
305 | pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n"); | |
306 | pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n"); | |
84f4ee90 | 307 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { |
ef456f85 | 308 | const char *next_desc; |
84f4ee90 TI |
309 | tx_desc = E1000_TX_DESC(*tx_ring, i); |
310 | buffer_info = &tx_ring->buffer_info[i]; | |
311 | u0 = (struct my_u0 *)tx_desc; | |
84f4ee90 | 312 | if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean) |
ef456f85 | 313 | next_desc = " NTC/U"; |
84f4ee90 | 314 | else if (i == tx_ring->next_to_use) |
ef456f85 | 315 | next_desc = " NTU"; |
84f4ee90 | 316 | else if (i == tx_ring->next_to_clean) |
ef456f85 | 317 | next_desc = " NTC"; |
84f4ee90 | 318 | else |
ef456f85 JK |
319 | next_desc = ""; |
320 | pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n", | |
18dd2392 JK |
321 | (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' : |
322 | ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')), | |
ef456f85 JK |
323 | i, |
324 | (unsigned long long)le64_to_cpu(u0->a), | |
325 | (unsigned long long)le64_to_cpu(u0->b), | |
326 | (unsigned long long)buffer_info->dma, | |
327 | buffer_info->length, buffer_info->next_to_watch, | |
328 | (unsigned long long)buffer_info->time_stamp, | |
329 | buffer_info->skb, next_desc); | |
84f4ee90 | 330 | |
f0c5dadf | 331 | if (netif_msg_pktdata(adapter) && buffer_info->skb) |
84f4ee90 | 332 | print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS, |
f0c5dadf ET |
333 | 16, 1, buffer_info->skb->data, |
334 | buffer_info->skb->len, true); | |
84f4ee90 TI |
335 | } |
336 | ||
af667a29 | 337 | /* Print Rx Ring Summary */ |
84f4ee90 | 338 | rx_ring_summary: |
af667a29 | 339 | dev_info(&adapter->pdev->dev, "Rx Ring Summary\n"); |
ef456f85 JK |
340 | pr_info("Queue [NTU] [NTC]\n"); |
341 | pr_info(" %5d %5X %5X\n", | |
342 | 0, rx_ring->next_to_use, rx_ring->next_to_clean); | |
84f4ee90 | 343 | |
af667a29 | 344 | /* Print Rx Ring */ |
84f4ee90 | 345 | if (!netif_msg_rx_status(adapter)) |
fe1e980f | 346 | return; |
84f4ee90 | 347 | |
af667a29 | 348 | dev_info(&adapter->pdev->dev, "Rx Ring Dump\n"); |
84f4ee90 TI |
349 | switch (adapter->rx_ps_pages) { |
350 | case 1: | |
351 | case 2: | |
352 | case 3: | |
353 | /* [Extended] Packet Split Receive Descriptor Format | |
354 | * | |
355 | * +-----------------------------------------------------+ | |
356 | * 0 | Buffer Address 0 [63:0] | | |
357 | * +-----------------------------------------------------+ | |
358 | * 8 | Buffer Address 1 [63:0] | | |
359 | * +-----------------------------------------------------+ | |
360 | * 16 | Buffer Address 2 [63:0] | | |
361 | * +-----------------------------------------------------+ | |
362 | * 24 | Buffer Address 3 [63:0] | | |
363 | * +-----------------------------------------------------+ | |
364 | */ | |
ef456f85 | 365 | pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n"); |
84f4ee90 TI |
366 | /* [Extended] Receive Descriptor (Write-Back) Format |
367 | * | |
368 | * 63 48 47 32 31 13 12 8 7 4 3 0 | |
369 | * +------------------------------------------------------+ | |
370 | * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS | | |
371 | * | Checksum | Ident | | Queue | | Type | | |
372 | * +------------------------------------------------------+ | |
373 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
374 | * +------------------------------------------------------+ | |
375 | * 63 48 47 32 31 20 19 0 | |
376 | */ | |
ef456f85 | 377 | pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n"); |
84f4ee90 | 378 | for (i = 0; i < rx_ring->count; i++) { |
ef456f85 | 379 | const char *next_desc; |
84f4ee90 TI |
380 | buffer_info = &rx_ring->buffer_info[i]; |
381 | rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i); | |
382 | u1 = (struct my_u1 *)rx_desc_ps; | |
383 | staterr = | |
af667a29 | 384 | le32_to_cpu(rx_desc_ps->wb.middle.status_error); |
ef456f85 JK |
385 | |
386 | if (i == rx_ring->next_to_use) | |
387 | next_desc = " NTU"; | |
388 | else if (i == rx_ring->next_to_clean) | |
389 | next_desc = " NTC"; | |
390 | else | |
391 | next_desc = ""; | |
392 | ||
84f4ee90 TI |
393 | if (staterr & E1000_RXD_STAT_DD) { |
394 | /* Descriptor Done */ | |
ef456f85 JK |
395 | pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n", |
396 | "RWB", i, | |
397 | (unsigned long long)le64_to_cpu(u1->a), | |
398 | (unsigned long long)le64_to_cpu(u1->b), | |
399 | (unsigned long long)le64_to_cpu(u1->c), | |
400 | (unsigned long long)le64_to_cpu(u1->d), | |
401 | buffer_info->skb, next_desc); | |
84f4ee90 | 402 | } else { |
ef456f85 JK |
403 | pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n", |
404 | "R ", i, | |
405 | (unsigned long long)le64_to_cpu(u1->a), | |
406 | (unsigned long long)le64_to_cpu(u1->b), | |
407 | (unsigned long long)le64_to_cpu(u1->c), | |
408 | (unsigned long long)le64_to_cpu(u1->d), | |
409 | (unsigned long long)buffer_info->dma, | |
410 | buffer_info->skb, next_desc); | |
84f4ee90 TI |
411 | |
412 | if (netif_msg_pktdata(adapter)) | |
f0c5dadf ET |
413 | e1000e_dump_ps_pages(adapter, |
414 | buffer_info); | |
84f4ee90 | 415 | } |
84f4ee90 TI |
416 | } |
417 | break; | |
418 | default: | |
419 | case 0: | |
5f450212 | 420 | /* Extended Receive Descriptor (Read) Format |
84f4ee90 | 421 | * |
5f450212 BA |
422 | * +-----------------------------------------------------+ |
423 | * 0 | Buffer Address [63:0] | | |
424 | * +-----------------------------------------------------+ | |
425 | * 8 | Reserved | | |
426 | * +-----------------------------------------------------+ | |
84f4ee90 | 427 | */ |
ef456f85 | 428 | pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n"); |
5f450212 BA |
429 | /* Extended Receive Descriptor (Write-Back) Format |
430 | * | |
431 | * 63 48 47 32 31 24 23 4 3 0 | |
432 | * +------------------------------------------------------+ | |
433 | * | RSS Hash | | | | | |
434 | * 0 +-------------------+ Rsvd | Reserved | MRQ RSS | | |
435 | * | Packet | IP | | | Type | | |
436 | * | Checksum | Ident | | | | | |
437 | * +------------------------------------------------------+ | |
438 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
439 | * +------------------------------------------------------+ | |
440 | * 63 48 47 32 31 20 19 0 | |
441 | */ | |
ef456f85 | 442 | pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n"); |
5f450212 BA |
443 | |
444 | for (i = 0; i < rx_ring->count; i++) { | |
ef456f85 JK |
445 | const char *next_desc; |
446 | ||
84f4ee90 | 447 | buffer_info = &rx_ring->buffer_info[i]; |
5f450212 BA |
448 | rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); |
449 | u1 = (struct my_u1 *)rx_desc; | |
450 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
ef456f85 JK |
451 | |
452 | if (i == rx_ring->next_to_use) | |
453 | next_desc = " NTU"; | |
454 | else if (i == rx_ring->next_to_clean) | |
455 | next_desc = " NTC"; | |
456 | else | |
457 | next_desc = ""; | |
458 | ||
5f450212 BA |
459 | if (staterr & E1000_RXD_STAT_DD) { |
460 | /* Descriptor Done */ | |
ef456f85 JK |
461 | pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n", |
462 | "RWB", i, | |
463 | (unsigned long long)le64_to_cpu(u1->a), | |
464 | (unsigned long long)le64_to_cpu(u1->b), | |
465 | buffer_info->skb, next_desc); | |
5f450212 | 466 | } else { |
ef456f85 JK |
467 | pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n", |
468 | "R ", i, | |
469 | (unsigned long long)le64_to_cpu(u1->a), | |
470 | (unsigned long long)le64_to_cpu(u1->b), | |
471 | (unsigned long long)buffer_info->dma, | |
472 | buffer_info->skb, next_desc); | |
5f450212 | 473 | |
f0c5dadf ET |
474 | if (netif_msg_pktdata(adapter) && |
475 | buffer_info->skb) | |
5f450212 BA |
476 | print_hex_dump(KERN_INFO, "", |
477 | DUMP_PREFIX_ADDRESS, 16, | |
478 | 1, | |
f0c5dadf | 479 | buffer_info->skb->data, |
5f450212 BA |
480 | adapter->rx_buffer_len, |
481 | true); | |
482 | } | |
84f4ee90 TI |
483 | } |
484 | } | |
84f4ee90 TI |
485 | } |
486 | ||
bc7f75fa AK |
487 | /** |
488 | * e1000_desc_unused - calculate if we have unused descriptors | |
489 | **/ | |
490 | static int e1000_desc_unused(struct e1000_ring *ring) | |
491 | { | |
492 | if (ring->next_to_clean > ring->next_to_use) | |
493 | return ring->next_to_clean - ring->next_to_use - 1; | |
494 | ||
495 | return ring->count + ring->next_to_clean - ring->next_to_use - 1; | |
496 | } | |
497 | ||
b67e1913 BA |
498 | /** |
499 | * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp | |
500 | * @adapter: board private structure | |
501 | * @hwtstamps: time stamp structure to update | |
502 | * @systim: unsigned 64bit system time value. | |
503 | * | |
504 | * Convert the system time value stored in the RX/TXSTMP registers into a | |
505 | * hwtstamp which can be used by the upper level time stamping functions. | |
506 | * | |
507 | * The 'systim_lock' spinlock is used to protect the consistency of the | |
508 | * system time value. This is needed because reading the 64 bit time | |
509 | * value involves reading two 32 bit registers. The first read latches the | |
510 | * value. | |
511 | **/ | |
512 | static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter, | |
513 | struct skb_shared_hwtstamps *hwtstamps, | |
514 | u64 systim) | |
515 | { | |
516 | u64 ns; | |
517 | unsigned long flags; | |
518 | ||
519 | spin_lock_irqsave(&adapter->systim_lock, flags); | |
520 | ns = timecounter_cyc2time(&adapter->tc, systim); | |
521 | spin_unlock_irqrestore(&adapter->systim_lock, flags); | |
522 | ||
523 | memset(hwtstamps, 0, sizeof(*hwtstamps)); | |
524 | hwtstamps->hwtstamp = ns_to_ktime(ns); | |
525 | } | |
526 | ||
527 | /** | |
528 | * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp | |
529 | * @adapter: board private structure | |
530 | * @status: descriptor extended error and status field | |
531 | * @skb: particular skb to include time stamp | |
532 | * | |
533 | * If the time stamp is valid, convert it into the timecounter ns value | |
534 | * and store that result into the shhwtstamps structure which is passed | |
535 | * up the network stack. | |
536 | **/ | |
537 | static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status, | |
538 | struct sk_buff *skb) | |
539 | { | |
540 | struct e1000_hw *hw = &adapter->hw; | |
541 | u64 rxstmp; | |
542 | ||
543 | if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) || | |
544 | !(status & E1000_RXDEXT_STATERR_TST) || | |
545 | !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) | |
546 | return; | |
547 | ||
548 | /* The Rx time stamp registers contain the time stamp. No other | |
549 | * received packet will be time stamped until the Rx time stamp | |
550 | * registers are read. Because only one packet can be time stamped | |
551 | * at a time, the register values must belong to this packet and | |
552 | * therefore none of the other additional attributes need to be | |
553 | * compared. | |
554 | */ | |
555 | rxstmp = (u64)er32(RXSTMPL); | |
556 | rxstmp |= (u64)er32(RXSTMPH) << 32; | |
557 | e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp); | |
558 | ||
559 | adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP; | |
560 | } | |
561 | ||
bc7f75fa | 562 | /** |
ad68076e | 563 | * e1000_receive_skb - helper function to handle Rx indications |
bc7f75fa | 564 | * @adapter: board private structure |
b67e1913 | 565 | * @staterr: descriptor extended error and status field as written by hardware |
bc7f75fa AK |
566 | * @vlan: descriptor vlan field as written by hardware (no le/be conversion) |
567 | * @skb: pointer to sk_buff to be indicated to stack | |
568 | **/ | |
569 | static void e1000_receive_skb(struct e1000_adapter *adapter, | |
af667a29 | 570 | struct net_device *netdev, struct sk_buff *skb, |
b67e1913 | 571 | u32 staterr, __le16 vlan) |
bc7f75fa | 572 | { |
86d70e53 | 573 | u16 tag = le16_to_cpu(vlan); |
b67e1913 BA |
574 | |
575 | e1000e_rx_hwtstamp(adapter, staterr, skb); | |
576 | ||
bc7f75fa AK |
577 | skb->protocol = eth_type_trans(skb, netdev); |
578 | ||
b67e1913 | 579 | if (staterr & E1000_RXD_STAT_VP) |
86a9bad3 | 580 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag); |
86d70e53 JK |
581 | |
582 | napi_gro_receive(&adapter->napi, skb); | |
bc7f75fa AK |
583 | } |
584 | ||
585 | /** | |
af667a29 | 586 | * e1000_rx_checksum - Receive Checksum Offload |
afd12939 BA |
587 | * @adapter: board private structure |
588 | * @status_err: receive descriptor status and error fields | |
589 | * @csum: receive descriptor csum field | |
590 | * @sk_buff: socket buffer with received data | |
bc7f75fa AK |
591 | **/ |
592 | static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err, | |
2e1706f2 | 593 | struct sk_buff *skb) |
bc7f75fa AK |
594 | { |
595 | u16 status = (u16)status_err; | |
596 | u8 errors = (u8)(status_err >> 24); | |
bc8acf2c ED |
597 | |
598 | skb_checksum_none_assert(skb); | |
bc7f75fa | 599 | |
afd12939 BA |
600 | /* Rx checksum disabled */ |
601 | if (!(adapter->netdev->features & NETIF_F_RXCSUM)) | |
602 | return; | |
603 | ||
bc7f75fa AK |
604 | /* Ignore Checksum bit is set */ |
605 | if (status & E1000_RXD_STAT_IXSM) | |
606 | return; | |
afd12939 | 607 | |
2e1706f2 BA |
608 | /* TCP/UDP checksum error bit or IP checksum error bit is set */ |
609 | if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) { | |
bc7f75fa AK |
610 | /* let the stack verify checksum errors */ |
611 | adapter->hw_csum_err++; | |
612 | return; | |
613 | } | |
614 | ||
615 | /* TCP/UDP Checksum has not been calculated */ | |
616 | if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))) | |
617 | return; | |
618 | ||
619 | /* It must be a TCP or UDP packet with a valid checksum */ | |
2e1706f2 | 620 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
bc7f75fa AK |
621 | adapter->hw_csum_good++; |
622 | } | |
623 | ||
55aa6985 | 624 | static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i) |
c6e7f51e | 625 | { |
55aa6985 | 626 | struct e1000_adapter *adapter = rx_ring->adapter; |
c6e7f51e | 627 | struct e1000_hw *hw = &adapter->hw; |
bdc125f7 BA |
628 | s32 ret_val = __ew32_prepare(hw); |
629 | ||
630 | writel(i, rx_ring->tail); | |
c6e7f51e | 631 | |
bdc125f7 | 632 | if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) { |
c6e7f51e | 633 | u32 rctl = er32(RCTL); |
6cf08d1c | 634 | |
c6e7f51e BA |
635 | ew32(RCTL, rctl & ~E1000_RCTL_EN); |
636 | e_err("ME firmware caused invalid RDT - resetting\n"); | |
637 | schedule_work(&adapter->reset_task); | |
638 | } | |
639 | } | |
640 | ||
55aa6985 | 641 | static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i) |
c6e7f51e | 642 | { |
55aa6985 | 643 | struct e1000_adapter *adapter = tx_ring->adapter; |
c6e7f51e | 644 | struct e1000_hw *hw = &adapter->hw; |
bdc125f7 | 645 | s32 ret_val = __ew32_prepare(hw); |
c6e7f51e | 646 | |
bdc125f7 BA |
647 | writel(i, tx_ring->tail); |
648 | ||
649 | if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) { | |
c6e7f51e | 650 | u32 tctl = er32(TCTL); |
6cf08d1c | 651 | |
c6e7f51e BA |
652 | ew32(TCTL, tctl & ~E1000_TCTL_EN); |
653 | e_err("ME firmware caused invalid TDT - resetting\n"); | |
654 | schedule_work(&adapter->reset_task); | |
655 | } | |
656 | } | |
657 | ||
bc7f75fa | 658 | /** |
5f450212 | 659 | * e1000_alloc_rx_buffers - Replace used receive buffers |
55aa6985 | 660 | * @rx_ring: Rx descriptor ring |
bc7f75fa | 661 | **/ |
55aa6985 | 662 | static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring, |
c2fed996 | 663 | int cleaned_count, gfp_t gfp) |
bc7f75fa | 664 | { |
55aa6985 | 665 | struct e1000_adapter *adapter = rx_ring->adapter; |
bc7f75fa AK |
666 | struct net_device *netdev = adapter->netdev; |
667 | struct pci_dev *pdev = adapter->pdev; | |
5f450212 | 668 | union e1000_rx_desc_extended *rx_desc; |
bc7f75fa AK |
669 | struct e1000_buffer *buffer_info; |
670 | struct sk_buff *skb; | |
671 | unsigned int i; | |
89d71a66 | 672 | unsigned int bufsz = adapter->rx_buffer_len; |
bc7f75fa AK |
673 | |
674 | i = rx_ring->next_to_use; | |
675 | buffer_info = &rx_ring->buffer_info[i]; | |
676 | ||
677 | while (cleaned_count--) { | |
678 | skb = buffer_info->skb; | |
679 | if (skb) { | |
680 | skb_trim(skb, 0); | |
681 | goto map_skb; | |
682 | } | |
683 | ||
c2fed996 | 684 | skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); |
bc7f75fa AK |
685 | if (!skb) { |
686 | /* Better luck next round */ | |
687 | adapter->alloc_rx_buff_failed++; | |
688 | break; | |
689 | } | |
690 | ||
bc7f75fa AK |
691 | buffer_info->skb = skb; |
692 | map_skb: | |
0be3f55f | 693 | buffer_info->dma = dma_map_single(&pdev->dev, skb->data, |
bc7f75fa | 694 | adapter->rx_buffer_len, |
0be3f55f NN |
695 | DMA_FROM_DEVICE); |
696 | if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { | |
af667a29 | 697 | dev_err(&pdev->dev, "Rx DMA map failed\n"); |
bc7f75fa AK |
698 | adapter->rx_dma_failed++; |
699 | break; | |
700 | } | |
701 | ||
5f450212 BA |
702 | rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); |
703 | rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); | |
bc7f75fa | 704 | |
50849d79 | 705 | if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { |
e921eb1a | 706 | /* Force memory writes to complete before letting h/w |
50849d79 TH |
707 | * know there are new descriptors to fetch. (Only |
708 | * applicable for weak-ordered memory model archs, | |
709 | * such as IA-64). | |
710 | */ | |
711 | wmb(); | |
c6e7f51e | 712 | if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) |
55aa6985 | 713 | e1000e_update_rdt_wa(rx_ring, i); |
c6e7f51e | 714 | else |
c5083cf6 | 715 | writel(i, rx_ring->tail); |
50849d79 | 716 | } |
bc7f75fa AK |
717 | i++; |
718 | if (i == rx_ring->count) | |
719 | i = 0; | |
720 | buffer_info = &rx_ring->buffer_info[i]; | |
721 | } | |
722 | ||
50849d79 | 723 | rx_ring->next_to_use = i; |
bc7f75fa AK |
724 | } |
725 | ||
726 | /** | |
727 | * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split | |
55aa6985 | 728 | * @rx_ring: Rx descriptor ring |
bc7f75fa | 729 | **/ |
55aa6985 | 730 | static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring, |
c2fed996 | 731 | int cleaned_count, gfp_t gfp) |
bc7f75fa | 732 | { |
55aa6985 | 733 | struct e1000_adapter *adapter = rx_ring->adapter; |
bc7f75fa AK |
734 | struct net_device *netdev = adapter->netdev; |
735 | struct pci_dev *pdev = adapter->pdev; | |
736 | union e1000_rx_desc_packet_split *rx_desc; | |
bc7f75fa AK |
737 | struct e1000_buffer *buffer_info; |
738 | struct e1000_ps_page *ps_page; | |
739 | struct sk_buff *skb; | |
740 | unsigned int i, j; | |
741 | ||
742 | i = rx_ring->next_to_use; | |
743 | buffer_info = &rx_ring->buffer_info[i]; | |
744 | ||
745 | while (cleaned_count--) { | |
746 | rx_desc = E1000_RX_DESC_PS(*rx_ring, i); | |
747 | ||
748 | for (j = 0; j < PS_PAGE_BUFFERS; j++) { | |
47f44e40 AK |
749 | ps_page = &buffer_info->ps_pages[j]; |
750 | if (j >= adapter->rx_ps_pages) { | |
751 | /* all unused desc entries get hw null ptr */ | |
af667a29 BA |
752 | rx_desc->read.buffer_addr[j + 1] = |
753 | ~cpu_to_le64(0); | |
47f44e40 AK |
754 | continue; |
755 | } | |
756 | if (!ps_page->page) { | |
c2fed996 | 757 | ps_page->page = alloc_page(gfp); |
bc7f75fa | 758 | if (!ps_page->page) { |
47f44e40 AK |
759 | adapter->alloc_rx_buff_failed++; |
760 | goto no_buffers; | |
761 | } | |
0be3f55f NN |
762 | ps_page->dma = dma_map_page(&pdev->dev, |
763 | ps_page->page, | |
764 | 0, PAGE_SIZE, | |
765 | DMA_FROM_DEVICE); | |
766 | if (dma_mapping_error(&pdev->dev, | |
767 | ps_page->dma)) { | |
47f44e40 | 768 | dev_err(&adapter->pdev->dev, |
af667a29 | 769 | "Rx DMA page map failed\n"); |
47f44e40 AK |
770 | adapter->rx_dma_failed++; |
771 | goto no_buffers; | |
bc7f75fa | 772 | } |
bc7f75fa | 773 | } |
e921eb1a | 774 | /* Refresh the desc even if buffer_addrs |
47f44e40 AK |
775 | * didn't change because each write-back |
776 | * erases this info. | |
777 | */ | |
af667a29 BA |
778 | rx_desc->read.buffer_addr[j + 1] = |
779 | cpu_to_le64(ps_page->dma); | |
bc7f75fa AK |
780 | } |
781 | ||
e5fe2541 | 782 | skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0, |
c2fed996 | 783 | gfp); |
bc7f75fa AK |
784 | |
785 | if (!skb) { | |
786 | adapter->alloc_rx_buff_failed++; | |
787 | break; | |
788 | } | |
789 | ||
bc7f75fa | 790 | buffer_info->skb = skb; |
0be3f55f | 791 | buffer_info->dma = dma_map_single(&pdev->dev, skb->data, |
bc7f75fa | 792 | adapter->rx_ps_bsize0, |
0be3f55f NN |
793 | DMA_FROM_DEVICE); |
794 | if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { | |
af667a29 | 795 | dev_err(&pdev->dev, "Rx DMA map failed\n"); |
bc7f75fa AK |
796 | adapter->rx_dma_failed++; |
797 | /* cleanup skb */ | |
798 | dev_kfree_skb_any(skb); | |
799 | buffer_info->skb = NULL; | |
800 | break; | |
801 | } | |
802 | ||
803 | rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma); | |
804 | ||
50849d79 | 805 | if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) { |
e921eb1a | 806 | /* Force memory writes to complete before letting h/w |
50849d79 TH |
807 | * know there are new descriptors to fetch. (Only |
808 | * applicable for weak-ordered memory model archs, | |
809 | * such as IA-64). | |
810 | */ | |
811 | wmb(); | |
c6e7f51e | 812 | if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) |
55aa6985 | 813 | e1000e_update_rdt_wa(rx_ring, i << 1); |
c6e7f51e | 814 | else |
c5083cf6 | 815 | writel(i << 1, rx_ring->tail); |
50849d79 TH |
816 | } |
817 | ||
bc7f75fa AK |
818 | i++; |
819 | if (i == rx_ring->count) | |
820 | i = 0; | |
821 | buffer_info = &rx_ring->buffer_info[i]; | |
822 | } | |
823 | ||
824 | no_buffers: | |
50849d79 | 825 | rx_ring->next_to_use = i; |
bc7f75fa AK |
826 | } |
827 | ||
97ac8cae BA |
828 | /** |
829 | * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers | |
55aa6985 | 830 | * @rx_ring: Rx descriptor ring |
97ac8cae BA |
831 | * @cleaned_count: number of buffers to allocate this pass |
832 | **/ | |
833 | ||
55aa6985 | 834 | static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring, |
c2fed996 | 835 | int cleaned_count, gfp_t gfp) |
97ac8cae | 836 | { |
55aa6985 | 837 | struct e1000_adapter *adapter = rx_ring->adapter; |
97ac8cae BA |
838 | struct net_device *netdev = adapter->netdev; |
839 | struct pci_dev *pdev = adapter->pdev; | |
5f450212 | 840 | union e1000_rx_desc_extended *rx_desc; |
97ac8cae BA |
841 | struct e1000_buffer *buffer_info; |
842 | struct sk_buff *skb; | |
843 | unsigned int i; | |
2a2293b9 | 844 | unsigned int bufsz = 256 - 16; /* for skb_reserve */ |
97ac8cae BA |
845 | |
846 | i = rx_ring->next_to_use; | |
847 | buffer_info = &rx_ring->buffer_info[i]; | |
848 | ||
849 | while (cleaned_count--) { | |
850 | skb = buffer_info->skb; | |
851 | if (skb) { | |
852 | skb_trim(skb, 0); | |
853 | goto check_page; | |
854 | } | |
855 | ||
c2fed996 | 856 | skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp); |
97ac8cae BA |
857 | if (unlikely(!skb)) { |
858 | /* Better luck next round */ | |
859 | adapter->alloc_rx_buff_failed++; | |
860 | break; | |
861 | } | |
862 | ||
97ac8cae BA |
863 | buffer_info->skb = skb; |
864 | check_page: | |
865 | /* allocate a new page if necessary */ | |
866 | if (!buffer_info->page) { | |
c2fed996 | 867 | buffer_info->page = alloc_page(gfp); |
97ac8cae BA |
868 | if (unlikely(!buffer_info->page)) { |
869 | adapter->alloc_rx_buff_failed++; | |
870 | break; | |
871 | } | |
872 | } | |
873 | ||
37287fae | 874 | if (!buffer_info->dma) { |
0be3f55f | 875 | buffer_info->dma = dma_map_page(&pdev->dev, |
f0ff4398 BA |
876 | buffer_info->page, 0, |
877 | PAGE_SIZE, | |
0be3f55f | 878 | DMA_FROM_DEVICE); |
37287fae CP |
879 | if (dma_mapping_error(&pdev->dev, buffer_info->dma)) { |
880 | adapter->alloc_rx_buff_failed++; | |
881 | break; | |
882 | } | |
883 | } | |
97ac8cae | 884 | |
5f450212 BA |
885 | rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); |
886 | rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma); | |
97ac8cae BA |
887 | |
888 | if (unlikely(++i == rx_ring->count)) | |
889 | i = 0; | |
890 | buffer_info = &rx_ring->buffer_info[i]; | |
891 | } | |
892 | ||
893 | if (likely(rx_ring->next_to_use != i)) { | |
894 | rx_ring->next_to_use = i; | |
895 | if (unlikely(i-- == 0)) | |
896 | i = (rx_ring->count - 1); | |
897 | ||
898 | /* Force memory writes to complete before letting h/w | |
899 | * know there are new descriptors to fetch. (Only | |
900 | * applicable for weak-ordered memory model archs, | |
e921eb1a BA |
901 | * such as IA-64). |
902 | */ | |
97ac8cae | 903 | wmb(); |
c6e7f51e | 904 | if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) |
55aa6985 | 905 | e1000e_update_rdt_wa(rx_ring, i); |
c6e7f51e | 906 | else |
c5083cf6 | 907 | writel(i, rx_ring->tail); |
97ac8cae BA |
908 | } |
909 | } | |
910 | ||
70495a50 BA |
911 | static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss, |
912 | struct sk_buff *skb) | |
913 | { | |
914 | if (netdev->features & NETIF_F_RXHASH) | |
e25909bc | 915 | skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3); |
70495a50 BA |
916 | } |
917 | ||
bc7f75fa | 918 | /** |
55aa6985 BA |
919 | * e1000_clean_rx_irq - Send received data up the network stack |
920 | * @rx_ring: Rx descriptor ring | |
bc7f75fa AK |
921 | * |
922 | * the return value indicates whether actual cleaning was done, there | |
923 | * is no guarantee that everything was cleaned | |
924 | **/ | |
55aa6985 BA |
925 | static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done, |
926 | int work_to_do) | |
bc7f75fa | 927 | { |
55aa6985 | 928 | struct e1000_adapter *adapter = rx_ring->adapter; |
bc7f75fa AK |
929 | struct net_device *netdev = adapter->netdev; |
930 | struct pci_dev *pdev = adapter->pdev; | |
3bb99fe2 | 931 | struct e1000_hw *hw = &adapter->hw; |
5f450212 | 932 | union e1000_rx_desc_extended *rx_desc, *next_rxd; |
bc7f75fa | 933 | struct e1000_buffer *buffer_info, *next_buffer; |
5f450212 | 934 | u32 length, staterr; |
bc7f75fa AK |
935 | unsigned int i; |
936 | int cleaned_count = 0; | |
3db1cd5c | 937 | bool cleaned = false; |
bc7f75fa AK |
938 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
939 | ||
940 | i = rx_ring->next_to_clean; | |
5f450212 BA |
941 | rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); |
942 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
bc7f75fa AK |
943 | buffer_info = &rx_ring->buffer_info[i]; |
944 | ||
5f450212 | 945 | while (staterr & E1000_RXD_STAT_DD) { |
bc7f75fa | 946 | struct sk_buff *skb; |
bc7f75fa AK |
947 | |
948 | if (*work_done >= work_to_do) | |
949 | break; | |
950 | (*work_done)++; | |
837a1dba | 951 | dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ |
bc7f75fa | 952 | |
bc7f75fa AK |
953 | skb = buffer_info->skb; |
954 | buffer_info->skb = NULL; | |
955 | ||
956 | prefetch(skb->data - NET_IP_ALIGN); | |
957 | ||
958 | i++; | |
959 | if (i == rx_ring->count) | |
960 | i = 0; | |
5f450212 | 961 | next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); |
bc7f75fa AK |
962 | prefetch(next_rxd); |
963 | ||
964 | next_buffer = &rx_ring->buffer_info[i]; | |
965 | ||
3db1cd5c | 966 | cleaned = true; |
bc7f75fa | 967 | cleaned_count++; |
e5fe2541 BA |
968 | dma_unmap_single(&pdev->dev, buffer_info->dma, |
969 | adapter->rx_buffer_len, DMA_FROM_DEVICE); | |
bc7f75fa AK |
970 | buffer_info->dma = 0; |
971 | ||
5f450212 | 972 | length = le16_to_cpu(rx_desc->wb.upper.length); |
bc7f75fa | 973 | |
e921eb1a | 974 | /* !EOP means multiple descriptors were used to store a single |
b94b5028 JB |
975 | * packet, if that's the case we need to toss it. In fact, we |
976 | * need to toss every packet with the EOP bit clear and the | |
977 | * next frame that _does_ have the EOP bit set, as it is by | |
978 | * definition only a frame fragment | |
979 | */ | |
5f450212 | 980 | if (unlikely(!(staterr & E1000_RXD_STAT_EOP))) |
b94b5028 JB |
981 | adapter->flags2 |= FLAG2_IS_DISCARDING; |
982 | ||
983 | if (adapter->flags2 & FLAG2_IS_DISCARDING) { | |
bc7f75fa | 984 | /* All receives must fit into a single buffer */ |
3bb99fe2 | 985 | e_dbg("Receive packet consumed multiple buffers\n"); |
bc7f75fa AK |
986 | /* recycle */ |
987 | buffer_info->skb = skb; | |
5f450212 | 988 | if (staterr & E1000_RXD_STAT_EOP) |
b94b5028 | 989 | adapter->flags2 &= ~FLAG2_IS_DISCARDING; |
bc7f75fa AK |
990 | goto next_desc; |
991 | } | |
992 | ||
cf955e6c BG |
993 | if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && |
994 | !(netdev->features & NETIF_F_RXALL))) { | |
bc7f75fa AK |
995 | /* recycle */ |
996 | buffer_info->skb = skb; | |
997 | goto next_desc; | |
998 | } | |
999 | ||
eb7c3adb | 1000 | /* adjust length to remove Ethernet CRC */ |
0184039a BG |
1001 | if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { |
1002 | /* If configured to store CRC, don't subtract FCS, | |
1003 | * but keep the FCS bytes out of the total_rx_bytes | |
1004 | * counter | |
1005 | */ | |
1006 | if (netdev->features & NETIF_F_RXFCS) | |
1007 | total_rx_bytes -= 4; | |
1008 | else | |
1009 | length -= 4; | |
1010 | } | |
eb7c3adb | 1011 | |
bc7f75fa AK |
1012 | total_rx_bytes += length; |
1013 | total_rx_packets++; | |
1014 | ||
e921eb1a | 1015 | /* code added for copybreak, this should improve |
bc7f75fa | 1016 | * performance for small packets with large amounts |
ad68076e BA |
1017 | * of reassembly being done in the stack |
1018 | */ | |
bc7f75fa AK |
1019 | if (length < copybreak) { |
1020 | struct sk_buff *new_skb = | |
67fd893e | 1021 | napi_alloc_skb(&adapter->napi, length); |
bc7f75fa | 1022 | if (new_skb) { |
808ff676 BA |
1023 | skb_copy_to_linear_data_offset(new_skb, |
1024 | -NET_IP_ALIGN, | |
1025 | (skb->data - | |
1026 | NET_IP_ALIGN), | |
1027 | (length + | |
1028 | NET_IP_ALIGN)); | |
bc7f75fa AK |
1029 | /* save the skb in buffer_info as good */ |
1030 | buffer_info->skb = skb; | |
1031 | skb = new_skb; | |
1032 | } | |
1033 | /* else just continue with the old one */ | |
1034 | } | |
1035 | /* end copybreak code */ | |
1036 | skb_put(skb, length); | |
1037 | ||
1038 | /* Receive Checksum Offload */ | |
2e1706f2 | 1039 | e1000_rx_checksum(adapter, staterr, skb); |
bc7f75fa | 1040 | |
70495a50 BA |
1041 | e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); |
1042 | ||
5f450212 BA |
1043 | e1000_receive_skb(adapter, netdev, skb, staterr, |
1044 | rx_desc->wb.upper.vlan); | |
bc7f75fa AK |
1045 | |
1046 | next_desc: | |
5f450212 | 1047 | rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); |
bc7f75fa AK |
1048 | |
1049 | /* return some buffers to hardware, one at a time is too slow */ | |
1050 | if (cleaned_count >= E1000_RX_BUFFER_WRITE) { | |
55aa6985 | 1051 | adapter->alloc_rx_buf(rx_ring, cleaned_count, |
c2fed996 | 1052 | GFP_ATOMIC); |
bc7f75fa AK |
1053 | cleaned_count = 0; |
1054 | } | |
1055 | ||
1056 | /* use prefetched values */ | |
1057 | rx_desc = next_rxd; | |
1058 | buffer_info = next_buffer; | |
5f450212 BA |
1059 | |
1060 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
bc7f75fa AK |
1061 | } |
1062 | rx_ring->next_to_clean = i; | |
1063 | ||
1064 | cleaned_count = e1000_desc_unused(rx_ring); | |
1065 | if (cleaned_count) | |
55aa6985 | 1066 | adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); |
bc7f75fa | 1067 | |
bc7f75fa | 1068 | adapter->total_rx_bytes += total_rx_bytes; |
7c25769f | 1069 | adapter->total_rx_packets += total_rx_packets; |
bc7f75fa AK |
1070 | return cleaned; |
1071 | } | |
1072 | ||
55aa6985 | 1073 | static void e1000_put_txbuf(struct e1000_ring *tx_ring, |
377b6273 FF |
1074 | struct e1000_buffer *buffer_info, |
1075 | bool drop) | |
bc7f75fa | 1076 | { |
55aa6985 BA |
1077 | struct e1000_adapter *adapter = tx_ring->adapter; |
1078 | ||
03b1320d AD |
1079 | if (buffer_info->dma) { |
1080 | if (buffer_info->mapped_as_page) | |
0be3f55f NN |
1081 | dma_unmap_page(&adapter->pdev->dev, buffer_info->dma, |
1082 | buffer_info->length, DMA_TO_DEVICE); | |
03b1320d | 1083 | else |
0be3f55f NN |
1084 | dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, |
1085 | buffer_info->length, DMA_TO_DEVICE); | |
03b1320d AD |
1086 | buffer_info->dma = 0; |
1087 | } | |
bc7f75fa | 1088 | if (buffer_info->skb) { |
377b6273 FF |
1089 | if (drop) |
1090 | dev_kfree_skb_any(buffer_info->skb); | |
1091 | else | |
1092 | dev_consume_skb_any(buffer_info->skb); | |
bc7f75fa AK |
1093 | buffer_info->skb = NULL; |
1094 | } | |
1b7719c4 | 1095 | buffer_info->time_stamp = 0; |
bc7f75fa AK |
1096 | } |
1097 | ||
41cec6f1 | 1098 | static void e1000_print_hw_hang(struct work_struct *work) |
bc7f75fa | 1099 | { |
41cec6f1 | 1100 | struct e1000_adapter *adapter = container_of(work, |
f0ff4398 BA |
1101 | struct e1000_adapter, |
1102 | print_hang_task); | |
09357b00 | 1103 | struct net_device *netdev = adapter->netdev; |
bc7f75fa AK |
1104 | struct e1000_ring *tx_ring = adapter->tx_ring; |
1105 | unsigned int i = tx_ring->next_to_clean; | |
1106 | unsigned int eop = tx_ring->buffer_info[i].next_to_watch; | |
1107 | struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop); | |
41cec6f1 BA |
1108 | struct e1000_hw *hw = &adapter->hw; |
1109 | u16 phy_status, phy_1000t_status, phy_ext_status; | |
1110 | u16 pci_status; | |
1111 | ||
615b32af JB |
1112 | if (test_bit(__E1000_DOWN, &adapter->state)) |
1113 | return; | |
1114 | ||
e5fe2541 | 1115 | if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) { |
e921eb1a | 1116 | /* May be block on write-back, flush and detect again |
09357b00 JK |
1117 | * flush pending descriptor writebacks to memory |
1118 | */ | |
1119 | ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); | |
1120 | /* execute the writes immediately */ | |
1121 | e1e_flush(); | |
e921eb1a | 1122 | /* Due to rare timing issues, write to TIDV again to ensure |
bf03085f MV |
1123 | * the write is successful |
1124 | */ | |
1125 | ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); | |
1126 | /* execute the writes immediately */ | |
1127 | e1e_flush(); | |
09357b00 JK |
1128 | adapter->tx_hang_recheck = true; |
1129 | return; | |
1130 | } | |
09357b00 | 1131 | adapter->tx_hang_recheck = false; |
d9554e96 DE |
1132 | |
1133 | if (er32(TDH(0)) == er32(TDT(0))) { | |
1134 | e_dbg("false hang detected, ignoring\n"); | |
1135 | return; | |
1136 | } | |
1137 | ||
1138 | /* Real hang detected */ | |
09357b00 JK |
1139 | netif_stop_queue(netdev); |
1140 | ||
c2ade1a4 BA |
1141 | e1e_rphy(hw, MII_BMSR, &phy_status); |
1142 | e1e_rphy(hw, MII_STAT1000, &phy_1000t_status); | |
1143 | e1e_rphy(hw, MII_ESTATUS, &phy_ext_status); | |
bc7f75fa | 1144 | |
41cec6f1 BA |
1145 | pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status); |
1146 | ||
1147 | /* detected Hardware unit hang */ | |
1148 | e_err("Detected Hardware Unit Hang:\n" | |
44defeb3 JK |
1149 | " TDH <%x>\n" |
1150 | " TDT <%x>\n" | |
1151 | " next_to_use <%x>\n" | |
1152 | " next_to_clean <%x>\n" | |
1153 | "buffer_info[next_to_clean]:\n" | |
1154 | " time_stamp <%lx>\n" | |
1155 | " next_to_watch <%x>\n" | |
1156 | " jiffies <%lx>\n" | |
41cec6f1 BA |
1157 | " next_to_watch.status <%x>\n" |
1158 | "MAC Status <%x>\n" | |
1159 | "PHY Status <%x>\n" | |
1160 | "PHY 1000BASE-T Status <%x>\n" | |
1161 | "PHY Extended Status <%x>\n" | |
1162 | "PCI Status <%x>\n", | |
e5fe2541 BA |
1163 | readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use, |
1164 | tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp, | |
1165 | eop, jiffies, eop_desc->upper.fields.status, er32(STATUS), | |
1166 | phy_status, phy_1000t_status, phy_ext_status, pci_status); | |
7c0427ee | 1167 | |
d9554e96 DE |
1168 | e1000e_dump(adapter); |
1169 | ||
7c0427ee BA |
1170 | /* Suggest workaround for known h/w issue */ |
1171 | if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE)) | |
1172 | e_err("Try turning off Tx pause (flow control) via ethtool\n"); | |
bc7f75fa AK |
1173 | } |
1174 | ||
b67e1913 BA |
1175 | /** |
1176 | * e1000e_tx_hwtstamp_work - check for Tx time stamp | |
1177 | * @work: pointer to work struct | |
1178 | * | |
1179 | * This work function polls the TSYNCTXCTL valid bit to determine when a | |
1180 | * timestamp has been taken for the current stored skb. The timestamp must | |
1181 | * be for this skb because only one such packet is allowed in the queue. | |
1182 | */ | |
1183 | static void e1000e_tx_hwtstamp_work(struct work_struct *work) | |
1184 | { | |
1185 | struct e1000_adapter *adapter = container_of(work, struct e1000_adapter, | |
1186 | tx_hwtstamp_work); | |
1187 | struct e1000_hw *hw = &adapter->hw; | |
1188 | ||
b67e1913 | 1189 | if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) { |
5012863b | 1190 | struct sk_buff *skb = adapter->tx_hwtstamp_skb; |
b67e1913 BA |
1191 | struct skb_shared_hwtstamps shhwtstamps; |
1192 | u64 txstmp; | |
1193 | ||
1194 | txstmp = er32(TXSTMPL); | |
1195 | txstmp |= (u64)er32(TXSTMPH) << 32; | |
1196 | ||
1197 | e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp); | |
1198 | ||
5012863b JK |
1199 | /* Clear the global tx_hwtstamp_skb pointer and force writes |
1200 | * prior to notifying the stack of a Tx timestamp. | |
1201 | */ | |
b67e1913 | 1202 | adapter->tx_hwtstamp_skb = NULL; |
5012863b JK |
1203 | wmb(); /* force write prior to skb_tstamp_tx */ |
1204 | ||
1205 | skb_tstamp_tx(skb, &shhwtstamps); | |
377b6273 | 1206 | dev_consume_skb_any(skb); |
59c871c5 JK |
1207 | } else if (time_after(jiffies, adapter->tx_hwtstamp_start |
1208 | + adapter->tx_timeout_factor * HZ)) { | |
1209 | dev_kfree_skb_any(adapter->tx_hwtstamp_skb); | |
1210 | adapter->tx_hwtstamp_skb = NULL; | |
1211 | adapter->tx_hwtstamp_timeouts++; | |
c5ffe7e1 | 1212 | e_warn("clearing Tx timestamp hang\n"); |
b67e1913 BA |
1213 | } else { |
1214 | /* reschedule to check later */ | |
1215 | schedule_work(&adapter->tx_hwtstamp_work); | |
1216 | } | |
1217 | } | |
1218 | ||
bc7f75fa AK |
1219 | /** |
1220 | * e1000_clean_tx_irq - Reclaim resources after transmit completes | |
55aa6985 | 1221 | * @tx_ring: Tx descriptor ring |
bc7f75fa AK |
1222 | * |
1223 | * the return value indicates whether actual cleaning was done, there | |
1224 | * is no guarantee that everything was cleaned | |
1225 | **/ | |
55aa6985 | 1226 | static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring) |
bc7f75fa | 1227 | { |
55aa6985 | 1228 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa AK |
1229 | struct net_device *netdev = adapter->netdev; |
1230 | struct e1000_hw *hw = &adapter->hw; | |
bc7f75fa AK |
1231 | struct e1000_tx_desc *tx_desc, *eop_desc; |
1232 | struct e1000_buffer *buffer_info; | |
1233 | unsigned int i, eop; | |
1234 | unsigned int count = 0; | |
bc7f75fa | 1235 | unsigned int total_tx_bytes = 0, total_tx_packets = 0; |
3f0cfa3b | 1236 | unsigned int bytes_compl = 0, pkts_compl = 0; |
bc7f75fa AK |
1237 | |
1238 | i = tx_ring->next_to_clean; | |
1239 | eop = tx_ring->buffer_info[i].next_to_watch; | |
1240 | eop_desc = E1000_TX_DESC(*tx_ring, eop); | |
1241 | ||
12d04a3c AD |
1242 | while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) && |
1243 | (count < tx_ring->count)) { | |
a86043c2 | 1244 | bool cleaned = false; |
6cf08d1c | 1245 | |
837a1dba | 1246 | dma_rmb(); /* read buffer_info after eop_desc */ |
a86043c2 | 1247 | for (; !cleaned; count++) { |
bc7f75fa AK |
1248 | tx_desc = E1000_TX_DESC(*tx_ring, i); |
1249 | buffer_info = &tx_ring->buffer_info[i]; | |
1250 | cleaned = (i == eop); | |
1251 | ||
1252 | if (cleaned) { | |
9ed318d5 TH |
1253 | total_tx_packets += buffer_info->segs; |
1254 | total_tx_bytes += buffer_info->bytecount; | |
3f0cfa3b TH |
1255 | if (buffer_info->skb) { |
1256 | bytes_compl += buffer_info->skb->len; | |
1257 | pkts_compl++; | |
1258 | } | |
bc7f75fa AK |
1259 | } |
1260 | ||
377b6273 | 1261 | e1000_put_txbuf(tx_ring, buffer_info, false); |
bc7f75fa AK |
1262 | tx_desc->upper.data = 0; |
1263 | ||
1264 | i++; | |
1265 | if (i == tx_ring->count) | |
1266 | i = 0; | |
1267 | } | |
1268 | ||
dac87619 TL |
1269 | if (i == tx_ring->next_to_use) |
1270 | break; | |
bc7f75fa AK |
1271 | eop = tx_ring->buffer_info[i].next_to_watch; |
1272 | eop_desc = E1000_TX_DESC(*tx_ring, eop); | |
bc7f75fa AK |
1273 | } |
1274 | ||
1275 | tx_ring->next_to_clean = i; | |
1276 | ||
3f0cfa3b TH |
1277 | netdev_completed_queue(netdev, pkts_compl, bytes_compl); |
1278 | ||
bc7f75fa | 1279 | #define TX_WAKE_THRESHOLD 32 |
a86043c2 JB |
1280 | if (count && netif_carrier_ok(netdev) && |
1281 | e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { | |
bc7f75fa AK |
1282 | /* Make sure that anybody stopping the queue after this |
1283 | * sees the new next_to_clean. | |
1284 | */ | |
1285 | smp_mb(); | |
1286 | ||
1287 | if (netif_queue_stopped(netdev) && | |
1288 | !(test_bit(__E1000_DOWN, &adapter->state))) { | |
1289 | netif_wake_queue(netdev); | |
1290 | ++adapter->restart_queue; | |
1291 | } | |
1292 | } | |
1293 | ||
1294 | if (adapter->detect_tx_hung) { | |
e921eb1a | 1295 | /* Detect a transmit hang in hardware, this serializes the |
41cec6f1 BA |
1296 | * check with the clearing of time_stamp and movement of i |
1297 | */ | |
3db1cd5c | 1298 | adapter->detect_tx_hung = false; |
12d04a3c AD |
1299 | if (tx_ring->buffer_info[i].time_stamp && |
1300 | time_after(jiffies, tx_ring->buffer_info[i].time_stamp | |
8e95a202 | 1301 | + (adapter->tx_timeout_factor * HZ)) && |
09357b00 | 1302 | !(er32(STATUS) & E1000_STATUS_TXOFF)) |
41cec6f1 | 1303 | schedule_work(&adapter->print_hang_task); |
09357b00 JK |
1304 | else |
1305 | adapter->tx_hang_recheck = false; | |
bc7f75fa AK |
1306 | } |
1307 | adapter->total_tx_bytes += total_tx_bytes; | |
1308 | adapter->total_tx_packets += total_tx_packets; | |
807540ba | 1309 | return count < tx_ring->count; |
bc7f75fa AK |
1310 | } |
1311 | ||
bc7f75fa AK |
1312 | /** |
1313 | * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split | |
55aa6985 | 1314 | * @rx_ring: Rx descriptor ring |
bc7f75fa AK |
1315 | * |
1316 | * the return value indicates whether actual cleaning was done, there | |
1317 | * is no guarantee that everything was cleaned | |
1318 | **/ | |
55aa6985 BA |
1319 | static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done, |
1320 | int work_to_do) | |
bc7f75fa | 1321 | { |
55aa6985 | 1322 | struct e1000_adapter *adapter = rx_ring->adapter; |
3bb99fe2 | 1323 | struct e1000_hw *hw = &adapter->hw; |
bc7f75fa AK |
1324 | union e1000_rx_desc_packet_split *rx_desc, *next_rxd; |
1325 | struct net_device *netdev = adapter->netdev; | |
1326 | struct pci_dev *pdev = adapter->pdev; | |
bc7f75fa AK |
1327 | struct e1000_buffer *buffer_info, *next_buffer; |
1328 | struct e1000_ps_page *ps_page; | |
1329 | struct sk_buff *skb; | |
1330 | unsigned int i, j; | |
1331 | u32 length, staterr; | |
1332 | int cleaned_count = 0; | |
3db1cd5c | 1333 | bool cleaned = false; |
bc7f75fa AK |
1334 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
1335 | ||
1336 | i = rx_ring->next_to_clean; | |
1337 | rx_desc = E1000_RX_DESC_PS(*rx_ring, i); | |
1338 | staterr = le32_to_cpu(rx_desc->wb.middle.status_error); | |
1339 | buffer_info = &rx_ring->buffer_info[i]; | |
1340 | ||
1341 | while (staterr & E1000_RXD_STAT_DD) { | |
1342 | if (*work_done >= work_to_do) | |
1343 | break; | |
1344 | (*work_done)++; | |
1345 | skb = buffer_info->skb; | |
837a1dba | 1346 | dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ |
bc7f75fa AK |
1347 | |
1348 | /* in the packet split case this is header only */ | |
1349 | prefetch(skb->data - NET_IP_ALIGN); | |
1350 | ||
1351 | i++; | |
1352 | if (i == rx_ring->count) | |
1353 | i = 0; | |
1354 | next_rxd = E1000_RX_DESC_PS(*rx_ring, i); | |
1355 | prefetch(next_rxd); | |
1356 | ||
1357 | next_buffer = &rx_ring->buffer_info[i]; | |
1358 | ||
3db1cd5c | 1359 | cleaned = true; |
bc7f75fa | 1360 | cleaned_count++; |
0be3f55f | 1361 | dma_unmap_single(&pdev->dev, buffer_info->dma, |
af667a29 | 1362 | adapter->rx_ps_bsize0, DMA_FROM_DEVICE); |
bc7f75fa AK |
1363 | buffer_info->dma = 0; |
1364 | ||
af667a29 | 1365 | /* see !EOP comment in other Rx routine */ |
b94b5028 JB |
1366 | if (!(staterr & E1000_RXD_STAT_EOP)) |
1367 | adapter->flags2 |= FLAG2_IS_DISCARDING; | |
1368 | ||
1369 | if (adapter->flags2 & FLAG2_IS_DISCARDING) { | |
ef456f85 | 1370 | e_dbg("Packet Split buffers didn't pick up the full packet\n"); |
bc7f75fa | 1371 | dev_kfree_skb_irq(skb); |
b94b5028 JB |
1372 | if (staterr & E1000_RXD_STAT_EOP) |
1373 | adapter->flags2 &= ~FLAG2_IS_DISCARDING; | |
bc7f75fa AK |
1374 | goto next_desc; |
1375 | } | |
1376 | ||
cf955e6c BG |
1377 | if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && |
1378 | !(netdev->features & NETIF_F_RXALL))) { | |
bc7f75fa AK |
1379 | dev_kfree_skb_irq(skb); |
1380 | goto next_desc; | |
1381 | } | |
1382 | ||
1383 | length = le16_to_cpu(rx_desc->wb.middle.length0); | |
1384 | ||
1385 | if (!length) { | |
ef456f85 | 1386 | e_dbg("Last part of the packet spanning multiple descriptors\n"); |
bc7f75fa AK |
1387 | dev_kfree_skb_irq(skb); |
1388 | goto next_desc; | |
1389 | } | |
1390 | ||
1391 | /* Good Receive */ | |
1392 | skb_put(skb, length); | |
1393 | ||
1394 | { | |
e921eb1a | 1395 | /* this looks ugly, but it seems compiler issues make |
0e15df49 BA |
1396 | * it more efficient than reusing j |
1397 | */ | |
1398 | int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]); | |
bc7f75fa | 1399 | |
e921eb1a | 1400 | /* page alloc/put takes too long and effects small |
0e15df49 BA |
1401 | * packet throughput, so unsplit small packets and |
1402 | * save the alloc/put only valid in softirq (napi) | |
1403 | * context to call kmap_* | |
ad68076e | 1404 | */ |
0e15df49 BA |
1405 | if (l1 && (l1 <= copybreak) && |
1406 | ((length + l1) <= adapter->rx_ps_bsize0)) { | |
1407 | u8 *vaddr; | |
1408 | ||
1409 | ps_page = &buffer_info->ps_pages[0]; | |
1410 | ||
e921eb1a | 1411 | /* there is no documentation about how to call |
0e15df49 BA |
1412 | * kmap_atomic, so we can't hold the mapping |
1413 | * very long | |
1414 | */ | |
1415 | dma_sync_single_for_cpu(&pdev->dev, | |
1416 | ps_page->dma, | |
1417 | PAGE_SIZE, | |
1418 | DMA_FROM_DEVICE); | |
9f393834 | 1419 | vaddr = kmap_atomic(ps_page->page); |
0e15df49 | 1420 | memcpy(skb_tail_pointer(skb), vaddr, l1); |
9f393834 | 1421 | kunmap_atomic(vaddr); |
0e15df49 BA |
1422 | dma_sync_single_for_device(&pdev->dev, |
1423 | ps_page->dma, | |
1424 | PAGE_SIZE, | |
1425 | DMA_FROM_DEVICE); | |
1426 | ||
1427 | /* remove the CRC */ | |
0184039a BG |
1428 | if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { |
1429 | if (!(netdev->features & NETIF_F_RXFCS)) | |
1430 | l1 -= 4; | |
1431 | } | |
0e15df49 BA |
1432 | |
1433 | skb_put(skb, l1); | |
1434 | goto copydone; | |
e80bd1d1 | 1435 | } /* if */ |
bc7f75fa AK |
1436 | } |
1437 | ||
1438 | for (j = 0; j < PS_PAGE_BUFFERS; j++) { | |
1439 | length = le16_to_cpu(rx_desc->wb.upper.length[j]); | |
1440 | if (!length) | |
1441 | break; | |
1442 | ||
47f44e40 | 1443 | ps_page = &buffer_info->ps_pages[j]; |
0be3f55f NN |
1444 | dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, |
1445 | DMA_FROM_DEVICE); | |
bc7f75fa AK |
1446 | ps_page->dma = 0; |
1447 | skb_fill_page_desc(skb, j, ps_page->page, 0, length); | |
1448 | ps_page->page = NULL; | |
1449 | skb->len += length; | |
1450 | skb->data_len += length; | |
98a045d7 | 1451 | skb->truesize += PAGE_SIZE; |
bc7f75fa AK |
1452 | } |
1453 | ||
eb7c3adb JK |
1454 | /* strip the ethernet crc, problem is we're using pages now so |
1455 | * this whole operation can get a little cpu intensive | |
1456 | */ | |
0184039a BG |
1457 | if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) { |
1458 | if (!(netdev->features & NETIF_F_RXFCS)) | |
1459 | pskb_trim(skb, skb->len - 4); | |
1460 | } | |
eb7c3adb | 1461 | |
bc7f75fa AK |
1462 | copydone: |
1463 | total_rx_bytes += skb->len; | |
1464 | total_rx_packets++; | |
1465 | ||
2e1706f2 | 1466 | e1000_rx_checksum(adapter, staterr, skb); |
bc7f75fa | 1467 | |
70495a50 BA |
1468 | e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); |
1469 | ||
bc7f75fa | 1470 | if (rx_desc->wb.upper.header_status & |
17e813ec | 1471 | cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP)) |
bc7f75fa AK |
1472 | adapter->rx_hdr_split++; |
1473 | ||
b67e1913 BA |
1474 | e1000_receive_skb(adapter, netdev, skb, staterr, |
1475 | rx_desc->wb.middle.vlan); | |
bc7f75fa AK |
1476 | |
1477 | next_desc: | |
1478 | rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF); | |
1479 | buffer_info->skb = NULL; | |
1480 | ||
1481 | /* return some buffers to hardware, one at a time is too slow */ | |
1482 | if (cleaned_count >= E1000_RX_BUFFER_WRITE) { | |
55aa6985 | 1483 | adapter->alloc_rx_buf(rx_ring, cleaned_count, |
c2fed996 | 1484 | GFP_ATOMIC); |
bc7f75fa AK |
1485 | cleaned_count = 0; |
1486 | } | |
1487 | ||
1488 | /* use prefetched values */ | |
1489 | rx_desc = next_rxd; | |
1490 | buffer_info = next_buffer; | |
1491 | ||
1492 | staterr = le32_to_cpu(rx_desc->wb.middle.status_error); | |
1493 | } | |
1494 | rx_ring->next_to_clean = i; | |
1495 | ||
1496 | cleaned_count = e1000_desc_unused(rx_ring); | |
1497 | if (cleaned_count) | |
55aa6985 | 1498 | adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); |
bc7f75fa | 1499 | |
bc7f75fa | 1500 | adapter->total_rx_bytes += total_rx_bytes; |
7c25769f | 1501 | adapter->total_rx_packets += total_rx_packets; |
bc7f75fa AK |
1502 | return cleaned; |
1503 | } | |
1504 | ||
97ac8cae BA |
1505 | /** |
1506 | * e1000_consume_page - helper function | |
1507 | **/ | |
1508 | static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb, | |
66501f56 | 1509 | u16 length) |
97ac8cae BA |
1510 | { |
1511 | bi->page = NULL; | |
1512 | skb->len += length; | |
1513 | skb->data_len += length; | |
98a045d7 | 1514 | skb->truesize += PAGE_SIZE; |
97ac8cae BA |
1515 | } |
1516 | ||
1517 | /** | |
1518 | * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy | |
1519 | * @adapter: board private structure | |
1520 | * | |
1521 | * the return value indicates whether actual cleaning was done, there | |
1522 | * is no guarantee that everything was cleaned | |
1523 | **/ | |
55aa6985 BA |
1524 | static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done, |
1525 | int work_to_do) | |
97ac8cae | 1526 | { |
55aa6985 | 1527 | struct e1000_adapter *adapter = rx_ring->adapter; |
97ac8cae BA |
1528 | struct net_device *netdev = adapter->netdev; |
1529 | struct pci_dev *pdev = adapter->pdev; | |
5f450212 | 1530 | union e1000_rx_desc_extended *rx_desc, *next_rxd; |
97ac8cae | 1531 | struct e1000_buffer *buffer_info, *next_buffer; |
5f450212 | 1532 | u32 length, staterr; |
97ac8cae BA |
1533 | unsigned int i; |
1534 | int cleaned_count = 0; | |
1535 | bool cleaned = false; | |
362e20ca | 1536 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
17e813ec | 1537 | struct skb_shared_info *shinfo; |
97ac8cae BA |
1538 | |
1539 | i = rx_ring->next_to_clean; | |
5f450212 BA |
1540 | rx_desc = E1000_RX_DESC_EXT(*rx_ring, i); |
1541 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
97ac8cae BA |
1542 | buffer_info = &rx_ring->buffer_info[i]; |
1543 | ||
5f450212 | 1544 | while (staterr & E1000_RXD_STAT_DD) { |
97ac8cae | 1545 | struct sk_buff *skb; |
97ac8cae BA |
1546 | |
1547 | if (*work_done >= work_to_do) | |
1548 | break; | |
1549 | (*work_done)++; | |
837a1dba | 1550 | dma_rmb(); /* read descriptor and rx_buffer_info after status DD */ |
97ac8cae | 1551 | |
97ac8cae BA |
1552 | skb = buffer_info->skb; |
1553 | buffer_info->skb = NULL; | |
1554 | ||
1555 | ++i; | |
1556 | if (i == rx_ring->count) | |
1557 | i = 0; | |
5f450212 | 1558 | next_rxd = E1000_RX_DESC_EXT(*rx_ring, i); |
97ac8cae BA |
1559 | prefetch(next_rxd); |
1560 | ||
1561 | next_buffer = &rx_ring->buffer_info[i]; | |
1562 | ||
1563 | cleaned = true; | |
1564 | cleaned_count++; | |
0be3f55f NN |
1565 | dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE, |
1566 | DMA_FROM_DEVICE); | |
97ac8cae BA |
1567 | buffer_info->dma = 0; |
1568 | ||
5f450212 | 1569 | length = le16_to_cpu(rx_desc->wb.upper.length); |
97ac8cae BA |
1570 | |
1571 | /* errors is only valid for DD + EOP descriptors */ | |
5f450212 | 1572 | if (unlikely((staterr & E1000_RXD_STAT_EOP) && |
cf955e6c BG |
1573 | ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) && |
1574 | !(netdev->features & NETIF_F_RXALL)))) { | |
5f450212 BA |
1575 | /* recycle both page and skb */ |
1576 | buffer_info->skb = skb; | |
1577 | /* an error means any chain goes out the window too */ | |
1578 | if (rx_ring->rx_skb_top) | |
1579 | dev_kfree_skb_irq(rx_ring->rx_skb_top); | |
1580 | rx_ring->rx_skb_top = NULL; | |
1581 | goto next_desc; | |
97ac8cae | 1582 | } |
f0f1a172 | 1583 | #define rxtop (rx_ring->rx_skb_top) |
5f450212 | 1584 | if (!(staterr & E1000_RXD_STAT_EOP)) { |
97ac8cae BA |
1585 | /* this descriptor is only the beginning (or middle) */ |
1586 | if (!rxtop) { | |
1587 | /* this is the beginning of a chain */ | |
1588 | rxtop = skb; | |
1589 | skb_fill_page_desc(rxtop, 0, buffer_info->page, | |
f0ff4398 | 1590 | 0, length); |
97ac8cae BA |
1591 | } else { |
1592 | /* this is the middle of a chain */ | |
17e813ec BA |
1593 | shinfo = skb_shinfo(rxtop); |
1594 | skb_fill_page_desc(rxtop, shinfo->nr_frags, | |
1595 | buffer_info->page, 0, | |
1596 | length); | |
97ac8cae BA |
1597 | /* re-use the skb, only consumed the page */ |
1598 | buffer_info->skb = skb; | |
1599 | } | |
1600 | e1000_consume_page(buffer_info, rxtop, length); | |
1601 | goto next_desc; | |
1602 | } else { | |
1603 | if (rxtop) { | |
1604 | /* end of the chain */ | |
17e813ec BA |
1605 | shinfo = skb_shinfo(rxtop); |
1606 | skb_fill_page_desc(rxtop, shinfo->nr_frags, | |
1607 | buffer_info->page, 0, | |
1608 | length); | |
97ac8cae | 1609 | /* re-use the current skb, we only consumed the |
e921eb1a BA |
1610 | * page |
1611 | */ | |
97ac8cae BA |
1612 | buffer_info->skb = skb; |
1613 | skb = rxtop; | |
1614 | rxtop = NULL; | |
1615 | e1000_consume_page(buffer_info, skb, length); | |
1616 | } else { | |
1617 | /* no chain, got EOP, this buf is the packet | |
e921eb1a BA |
1618 | * copybreak to save the put_page/alloc_page |
1619 | */ | |
97ac8cae BA |
1620 | if (length <= copybreak && |
1621 | skb_tailroom(skb) >= length) { | |
1622 | u8 *vaddr; | |
4679026d | 1623 | vaddr = kmap_atomic(buffer_info->page); |
97ac8cae BA |
1624 | memcpy(skb_tail_pointer(skb), vaddr, |
1625 | length); | |
4679026d | 1626 | kunmap_atomic(vaddr); |
97ac8cae | 1627 | /* re-use the page, so don't erase |
e921eb1a BA |
1628 | * buffer_info->page |
1629 | */ | |
97ac8cae BA |
1630 | skb_put(skb, length); |
1631 | } else { | |
1632 | skb_fill_page_desc(skb, 0, | |
f0ff4398 BA |
1633 | buffer_info->page, 0, |
1634 | length); | |
97ac8cae | 1635 | e1000_consume_page(buffer_info, skb, |
f0ff4398 | 1636 | length); |
97ac8cae BA |
1637 | } |
1638 | } | |
1639 | } | |
1640 | ||
2e1706f2 BA |
1641 | /* Receive Checksum Offload */ |
1642 | e1000_rx_checksum(adapter, staterr, skb); | |
97ac8cae | 1643 | |
70495a50 BA |
1644 | e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb); |
1645 | ||
97ac8cae BA |
1646 | /* probably a little skewed due to removing CRC */ |
1647 | total_rx_bytes += skb->len; | |
1648 | total_rx_packets++; | |
1649 | ||
1650 | /* eth type trans needs skb->data to point to something */ | |
1651 | if (!pskb_may_pull(skb, ETH_HLEN)) { | |
44defeb3 | 1652 | e_err("pskb_may_pull failed.\n"); |
ef5ab89c | 1653 | dev_kfree_skb_irq(skb); |
97ac8cae BA |
1654 | goto next_desc; |
1655 | } | |
1656 | ||
5f450212 BA |
1657 | e1000_receive_skb(adapter, netdev, skb, staterr, |
1658 | rx_desc->wb.upper.vlan); | |
97ac8cae BA |
1659 | |
1660 | next_desc: | |
5f450212 | 1661 | rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF); |
97ac8cae BA |
1662 | |
1663 | /* return some buffers to hardware, one at a time is too slow */ | |
1664 | if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) { | |
55aa6985 | 1665 | adapter->alloc_rx_buf(rx_ring, cleaned_count, |
c2fed996 | 1666 | GFP_ATOMIC); |
97ac8cae BA |
1667 | cleaned_count = 0; |
1668 | } | |
1669 | ||
1670 | /* use prefetched values */ | |
1671 | rx_desc = next_rxd; | |
1672 | buffer_info = next_buffer; | |
5f450212 BA |
1673 | |
1674 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
97ac8cae BA |
1675 | } |
1676 | rx_ring->next_to_clean = i; | |
1677 | ||
1678 | cleaned_count = e1000_desc_unused(rx_ring); | |
1679 | if (cleaned_count) | |
55aa6985 | 1680 | adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC); |
97ac8cae BA |
1681 | |
1682 | adapter->total_rx_bytes += total_rx_bytes; | |
1683 | adapter->total_rx_packets += total_rx_packets; | |
97ac8cae BA |
1684 | return cleaned; |
1685 | } | |
1686 | ||
bc7f75fa AK |
1687 | /** |
1688 | * e1000_clean_rx_ring - Free Rx Buffers per Queue | |
55aa6985 | 1689 | * @rx_ring: Rx descriptor ring |
bc7f75fa | 1690 | **/ |
55aa6985 | 1691 | static void e1000_clean_rx_ring(struct e1000_ring *rx_ring) |
bc7f75fa | 1692 | { |
55aa6985 | 1693 | struct e1000_adapter *adapter = rx_ring->adapter; |
bc7f75fa AK |
1694 | struct e1000_buffer *buffer_info; |
1695 | struct e1000_ps_page *ps_page; | |
1696 | struct pci_dev *pdev = adapter->pdev; | |
bc7f75fa AK |
1697 | unsigned int i, j; |
1698 | ||
1699 | /* Free all the Rx ring sk_buffs */ | |
1700 | for (i = 0; i < rx_ring->count; i++) { | |
1701 | buffer_info = &rx_ring->buffer_info[i]; | |
1702 | if (buffer_info->dma) { | |
1703 | if (adapter->clean_rx == e1000_clean_rx_irq) | |
0be3f55f | 1704 | dma_unmap_single(&pdev->dev, buffer_info->dma, |
bc7f75fa | 1705 | adapter->rx_buffer_len, |
0be3f55f | 1706 | DMA_FROM_DEVICE); |
97ac8cae | 1707 | else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq) |
0be3f55f | 1708 | dma_unmap_page(&pdev->dev, buffer_info->dma, |
f0ff4398 | 1709 | PAGE_SIZE, DMA_FROM_DEVICE); |
bc7f75fa | 1710 | else if (adapter->clean_rx == e1000_clean_rx_irq_ps) |
0be3f55f | 1711 | dma_unmap_single(&pdev->dev, buffer_info->dma, |
bc7f75fa | 1712 | adapter->rx_ps_bsize0, |
0be3f55f | 1713 | DMA_FROM_DEVICE); |
bc7f75fa AK |
1714 | buffer_info->dma = 0; |
1715 | } | |
1716 | ||
97ac8cae BA |
1717 | if (buffer_info->page) { |
1718 | put_page(buffer_info->page); | |
1719 | buffer_info->page = NULL; | |
1720 | } | |
1721 | ||
bc7f75fa AK |
1722 | if (buffer_info->skb) { |
1723 | dev_kfree_skb(buffer_info->skb); | |
1724 | buffer_info->skb = NULL; | |
1725 | } | |
1726 | ||
1727 | for (j = 0; j < PS_PAGE_BUFFERS; j++) { | |
47f44e40 | 1728 | ps_page = &buffer_info->ps_pages[j]; |
bc7f75fa AK |
1729 | if (!ps_page->page) |
1730 | break; | |
0be3f55f NN |
1731 | dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE, |
1732 | DMA_FROM_DEVICE); | |
bc7f75fa AK |
1733 | ps_page->dma = 0; |
1734 | put_page(ps_page->page); | |
1735 | ps_page->page = NULL; | |
1736 | } | |
1737 | } | |
1738 | ||
1739 | /* there also may be some cached data from a chained receive */ | |
1740 | if (rx_ring->rx_skb_top) { | |
1741 | dev_kfree_skb(rx_ring->rx_skb_top); | |
1742 | rx_ring->rx_skb_top = NULL; | |
1743 | } | |
1744 | ||
bc7f75fa AK |
1745 | /* Zero out the descriptor ring */ |
1746 | memset(rx_ring->desc, 0, rx_ring->size); | |
1747 | ||
1748 | rx_ring->next_to_clean = 0; | |
1749 | rx_ring->next_to_use = 0; | |
b94b5028 | 1750 | adapter->flags2 &= ~FLAG2_IS_DISCARDING; |
bc7f75fa AK |
1751 | } |
1752 | ||
a8f88ff5 JB |
1753 | static void e1000e_downshift_workaround(struct work_struct *work) |
1754 | { | |
1755 | struct e1000_adapter *adapter = container_of(work, | |
17e813ec BA |
1756 | struct e1000_adapter, |
1757 | downshift_task); | |
a8f88ff5 | 1758 | |
615b32af JB |
1759 | if (test_bit(__E1000_DOWN, &adapter->state)) |
1760 | return; | |
1761 | ||
a8f88ff5 JB |
1762 | e1000e_gig_downshift_workaround_ich8lan(&adapter->hw); |
1763 | } | |
1764 | ||
bc7f75fa AK |
1765 | /** |
1766 | * e1000_intr_msi - Interrupt Handler | |
1767 | * @irq: interrupt number | |
1768 | * @data: pointer to a network interface device structure | |
1769 | **/ | |
8bb62869 | 1770 | static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data) |
bc7f75fa AK |
1771 | { |
1772 | struct net_device *netdev = data; | |
1773 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
1774 | struct e1000_hw *hw = &adapter->hw; | |
1775 | u32 icr = er32(ICR); | |
1776 | ||
e921eb1a | 1777 | /* read ICR disables interrupts using IAM */ |
573cca8c | 1778 | if (icr & E1000_ICR_LSC) { |
f92518dd | 1779 | hw->mac.get_link_status = true; |
e921eb1a | 1780 | /* ICH8 workaround-- Call gig speed drop workaround on cable |
ad68076e BA |
1781 | * disconnect (LSC) before accessing any PHY registers |
1782 | */ | |
bc7f75fa AK |
1783 | if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && |
1784 | (!(er32(STATUS) & E1000_STATUS_LU))) | |
a8f88ff5 | 1785 | schedule_work(&adapter->downshift_task); |
bc7f75fa | 1786 | |
e921eb1a | 1787 | /* 80003ES2LAN workaround-- For packet buffer work-around on |
bc7f75fa | 1788 | * link down event; disable receives here in the ISR and reset |
ad68076e BA |
1789 | * adapter in watchdog |
1790 | */ | |
bc7f75fa AK |
1791 | if (netif_carrier_ok(netdev) && |
1792 | adapter->flags & FLAG_RX_NEEDS_RESTART) { | |
1793 | /* disable receives */ | |
1794 | u32 rctl = er32(RCTL); | |
6cf08d1c | 1795 | |
bc7f75fa | 1796 | ew32(RCTL, rctl & ~E1000_RCTL_EN); |
12d43f7d | 1797 | adapter->flags |= FLAG_RESTART_NOW; |
bc7f75fa AK |
1798 | } |
1799 | /* guard against interrupt when we're going down */ | |
1800 | if (!test_bit(__E1000_DOWN, &adapter->state)) | |
1801 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
1802 | } | |
1803 | ||
94fb848b | 1804 | /* Reset on uncorrectable ECC error */ |
c8744f44 | 1805 | if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { |
94fb848b BA |
1806 | u32 pbeccsts = er32(PBECCSTS); |
1807 | ||
1808 | adapter->corr_errors += | |
1809 | pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; | |
1810 | adapter->uncorr_errors += | |
1811 | (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> | |
1812 | E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; | |
1813 | ||
1814 | /* Do the reset outside of interrupt context */ | |
1815 | schedule_work(&adapter->reset_task); | |
1816 | ||
1817 | /* return immediately since reset is imminent */ | |
1818 | return IRQ_HANDLED; | |
1819 | } | |
1820 | ||
288379f0 | 1821 | if (napi_schedule_prep(&adapter->napi)) { |
bc7f75fa AK |
1822 | adapter->total_tx_bytes = 0; |
1823 | adapter->total_tx_packets = 0; | |
1824 | adapter->total_rx_bytes = 0; | |
1825 | adapter->total_rx_packets = 0; | |
288379f0 | 1826 | __napi_schedule(&adapter->napi); |
bc7f75fa AK |
1827 | } |
1828 | ||
1829 | return IRQ_HANDLED; | |
1830 | } | |
1831 | ||
1832 | /** | |
1833 | * e1000_intr - Interrupt Handler | |
1834 | * @irq: interrupt number | |
1835 | * @data: pointer to a network interface device structure | |
1836 | **/ | |
8bb62869 | 1837 | static irqreturn_t e1000_intr(int __always_unused irq, void *data) |
bc7f75fa AK |
1838 | { |
1839 | struct net_device *netdev = data; | |
1840 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
1841 | struct e1000_hw *hw = &adapter->hw; | |
bc7f75fa | 1842 | u32 rctl, icr = er32(ICR); |
4662e82b | 1843 | |
a68ea775 | 1844 | if (!icr || test_bit(__E1000_DOWN, &adapter->state)) |
e80bd1d1 | 1845 | return IRQ_NONE; /* Not our interrupt */ |
bc7f75fa | 1846 | |
e921eb1a | 1847 | /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is |
ad68076e BA |
1848 | * not set, then the adapter didn't send an interrupt |
1849 | */ | |
bc7f75fa AK |
1850 | if (!(icr & E1000_ICR_INT_ASSERTED)) |
1851 | return IRQ_NONE; | |
1852 | ||
e921eb1a | 1853 | /* Interrupt Auto-Mask...upon reading ICR, |
ad68076e BA |
1854 | * interrupts are masked. No need for the |
1855 | * IMC write | |
1856 | */ | |
bc7f75fa | 1857 | |
573cca8c | 1858 | if (icr & E1000_ICR_LSC) { |
f92518dd | 1859 | hw->mac.get_link_status = true; |
e921eb1a | 1860 | /* ICH8 workaround-- Call gig speed drop workaround on cable |
ad68076e BA |
1861 | * disconnect (LSC) before accessing any PHY registers |
1862 | */ | |
bc7f75fa AK |
1863 | if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) && |
1864 | (!(er32(STATUS) & E1000_STATUS_LU))) | |
a8f88ff5 | 1865 | schedule_work(&adapter->downshift_task); |
bc7f75fa | 1866 | |
e921eb1a | 1867 | /* 80003ES2LAN workaround-- |
bc7f75fa AK |
1868 | * For packet buffer work-around on link down event; |
1869 | * disable receives here in the ISR and | |
1870 | * reset adapter in watchdog | |
1871 | */ | |
1872 | if (netif_carrier_ok(netdev) && | |
1873 | (adapter->flags & FLAG_RX_NEEDS_RESTART)) { | |
1874 | /* disable receives */ | |
1875 | rctl = er32(RCTL); | |
1876 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | |
12d43f7d | 1877 | adapter->flags |= FLAG_RESTART_NOW; |
bc7f75fa AK |
1878 | } |
1879 | /* guard against interrupt when we're going down */ | |
1880 | if (!test_bit(__E1000_DOWN, &adapter->state)) | |
1881 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
1882 | } | |
1883 | ||
94fb848b | 1884 | /* Reset on uncorrectable ECC error */ |
c8744f44 | 1885 | if ((icr & E1000_ICR_ECCER) && (hw->mac.type >= e1000_pch_lpt)) { |
94fb848b BA |
1886 | u32 pbeccsts = er32(PBECCSTS); |
1887 | ||
1888 | adapter->corr_errors += | |
1889 | pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; | |
1890 | adapter->uncorr_errors += | |
1891 | (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> | |
1892 | E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; | |
1893 | ||
1894 | /* Do the reset outside of interrupt context */ | |
1895 | schedule_work(&adapter->reset_task); | |
1896 | ||
1897 | /* return immediately since reset is imminent */ | |
1898 | return IRQ_HANDLED; | |
1899 | } | |
1900 | ||
288379f0 | 1901 | if (napi_schedule_prep(&adapter->napi)) { |
bc7f75fa AK |
1902 | adapter->total_tx_bytes = 0; |
1903 | adapter->total_tx_packets = 0; | |
1904 | adapter->total_rx_bytes = 0; | |
1905 | adapter->total_rx_packets = 0; | |
288379f0 | 1906 | __napi_schedule(&adapter->napi); |
bc7f75fa AK |
1907 | } |
1908 | ||
1909 | return IRQ_HANDLED; | |
1910 | } | |
1911 | ||
8bb62869 | 1912 | static irqreturn_t e1000_msix_other(int __always_unused irq, void *data) |
4662e82b BA |
1913 | { |
1914 | struct net_device *netdev = data; | |
1915 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
1916 | struct e1000_hw *hw = &adapter->hw; | |
116f4a64 | 1917 | u32 icr = er32(ICR); |
745d0bd3 | 1918 | |
361a954e BP |
1919 | if (icr & adapter->eiac_mask) |
1920 | ew32(ICS, (icr & adapter->eiac_mask)); | |
1921 | ||
4aea7a5c | 1922 | if (icr & E1000_ICR_LSC) { |
4aea7a5c BP |
1923 | hw->mac.get_link_status = true; |
1924 | /* guard against interrupt when we're going down */ | |
1925 | if (!test_bit(__E1000_DOWN, &adapter->state)) | |
1926 | mod_timer(&adapter->watchdog_timer, jiffies + 1); | |
1927 | } | |
4662e82b | 1928 | |
1f0ea197 | 1929 | if (!test_bit(__E1000_DOWN, &adapter->state)) |
116f4a64 | 1930 | ew32(IMS, E1000_IMS_OTHER | IMS_OTHER_MASK); |
4662e82b | 1931 | |
4662e82b BA |
1932 | return IRQ_HANDLED; |
1933 | } | |
1934 | ||
8bb62869 | 1935 | static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data) |
4662e82b BA |
1936 | { |
1937 | struct net_device *netdev = data; | |
1938 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
1939 | struct e1000_hw *hw = &adapter->hw; | |
1940 | struct e1000_ring *tx_ring = adapter->tx_ring; | |
1941 | ||
4662e82b BA |
1942 | adapter->total_tx_bytes = 0; |
1943 | adapter->total_tx_packets = 0; | |
1944 | ||
55aa6985 | 1945 | if (!e1000_clean_tx_irq(tx_ring)) |
4662e82b BA |
1946 | /* Ring was not completely cleaned, so fire another interrupt */ |
1947 | ew32(ICS, tx_ring->ims_val); | |
1948 | ||
0a8047ac BP |
1949 | if (!test_bit(__E1000_DOWN, &adapter->state)) |
1950 | ew32(IMS, adapter->tx_ring->ims_val); | |
1951 | ||
4662e82b BA |
1952 | return IRQ_HANDLED; |
1953 | } | |
1954 | ||
8bb62869 | 1955 | static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data) |
4662e82b BA |
1956 | { |
1957 | struct net_device *netdev = data; | |
1958 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
55aa6985 | 1959 | struct e1000_ring *rx_ring = adapter->rx_ring; |
4662e82b BA |
1960 | |
1961 | /* Write the ITR value calculated at the end of the | |
1962 | * previous interrupt. | |
1963 | */ | |
55aa6985 | 1964 | if (rx_ring->set_itr) { |
b77ac46b DF |
1965 | u32 itr = rx_ring->itr_val ? |
1966 | 1000000000 / (rx_ring->itr_val * 256) : 0; | |
1967 | ||
1968 | writel(itr, rx_ring->itr_register); | |
55aa6985 | 1969 | rx_ring->set_itr = 0; |
4662e82b BA |
1970 | } |
1971 | ||
288379f0 | 1972 | if (napi_schedule_prep(&adapter->napi)) { |
4662e82b BA |
1973 | adapter->total_rx_bytes = 0; |
1974 | adapter->total_rx_packets = 0; | |
288379f0 | 1975 | __napi_schedule(&adapter->napi); |
4662e82b BA |
1976 | } |
1977 | return IRQ_HANDLED; | |
1978 | } | |
1979 | ||
1980 | /** | |
1981 | * e1000_configure_msix - Configure MSI-X hardware | |
1982 | * | |
1983 | * e1000_configure_msix sets up the hardware to properly | |
1984 | * generate MSI-X interrupts. | |
1985 | **/ | |
1986 | static void e1000_configure_msix(struct e1000_adapter *adapter) | |
1987 | { | |
1988 | struct e1000_hw *hw = &adapter->hw; | |
1989 | struct e1000_ring *rx_ring = adapter->rx_ring; | |
1990 | struct e1000_ring *tx_ring = adapter->tx_ring; | |
1991 | int vector = 0; | |
1992 | u32 ctrl_ext, ivar = 0; | |
1993 | ||
1994 | adapter->eiac_mask = 0; | |
1995 | ||
1996 | /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */ | |
1997 | if (hw->mac.type == e1000_82574) { | |
1998 | u32 rfctl = er32(RFCTL); | |
6cf08d1c | 1999 | |
4662e82b BA |
2000 | rfctl |= E1000_RFCTL_ACK_DIS; |
2001 | ew32(RFCTL, rfctl); | |
2002 | } | |
2003 | ||
4662e82b BA |
2004 | /* Configure Rx vector */ |
2005 | rx_ring->ims_val = E1000_IMS_RXQ0; | |
2006 | adapter->eiac_mask |= rx_ring->ims_val; | |
2007 | if (rx_ring->itr_val) | |
2008 | writel(1000000000 / (rx_ring->itr_val * 256), | |
c5083cf6 | 2009 | rx_ring->itr_register); |
4662e82b | 2010 | else |
c5083cf6 | 2011 | writel(1, rx_ring->itr_register); |
4662e82b BA |
2012 | ivar = E1000_IVAR_INT_ALLOC_VALID | vector; |
2013 | ||
2014 | /* Configure Tx vector */ | |
2015 | tx_ring->ims_val = E1000_IMS_TXQ0; | |
2016 | vector++; | |
2017 | if (tx_ring->itr_val) | |
2018 | writel(1000000000 / (tx_ring->itr_val * 256), | |
c5083cf6 | 2019 | tx_ring->itr_register); |
4662e82b | 2020 | else |
c5083cf6 | 2021 | writel(1, tx_ring->itr_register); |
4662e82b BA |
2022 | adapter->eiac_mask |= tx_ring->ims_val; |
2023 | ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8); | |
2024 | ||
2025 | /* set vector for Other Causes, e.g. link changes */ | |
2026 | vector++; | |
2027 | ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16); | |
2028 | if (rx_ring->itr_val) | |
2029 | writel(1000000000 / (rx_ring->itr_val * 256), | |
2030 | hw->hw_addr + E1000_EITR_82574(vector)); | |
2031 | else | |
2032 | writel(1, hw->hw_addr + E1000_EITR_82574(vector)); | |
2033 | ||
2034 | /* Cause Tx interrupts on every write back */ | |
18dd2392 | 2035 | ivar |= BIT(31); |
4662e82b BA |
2036 | |
2037 | ew32(IVAR, ivar); | |
2038 | ||
2039 | /* enable MSI-X PBA support */ | |
0a8047ac BP |
2040 | ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME; |
2041 | ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME; | |
4662e82b BA |
2042 | ew32(CTRL_EXT, ctrl_ext); |
2043 | e1e_flush(); | |
2044 | } | |
2045 | ||
2046 | void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter) | |
2047 | { | |
2048 | if (adapter->msix_entries) { | |
2049 | pci_disable_msix(adapter->pdev); | |
2050 | kfree(adapter->msix_entries); | |
2051 | adapter->msix_entries = NULL; | |
2052 | } else if (adapter->flags & FLAG_MSI_ENABLED) { | |
2053 | pci_disable_msi(adapter->pdev); | |
2054 | adapter->flags &= ~FLAG_MSI_ENABLED; | |
2055 | } | |
4662e82b BA |
2056 | } |
2057 | ||
2058 | /** | |
2059 | * e1000e_set_interrupt_capability - set MSI or MSI-X if supported | |
2060 | * | |
2061 | * Attempt to configure interrupts using the best available | |
2062 | * capabilities of the hardware and kernel. | |
2063 | **/ | |
2064 | void e1000e_set_interrupt_capability(struct e1000_adapter *adapter) | |
2065 | { | |
2066 | int err; | |
8e86acd7 | 2067 | int i; |
4662e82b BA |
2068 | |
2069 | switch (adapter->int_mode) { | |
2070 | case E1000E_INT_MODE_MSIX: | |
2071 | if (adapter->flags & FLAG_HAS_MSIX) { | |
8e86acd7 JK |
2072 | adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */ |
2073 | adapter->msix_entries = kcalloc(adapter->num_vectors, | |
17e813ec BA |
2074 | sizeof(struct |
2075 | msix_entry), | |
2076 | GFP_KERNEL); | |
4662e82b | 2077 | if (adapter->msix_entries) { |
0cc7c959 AG |
2078 | struct e1000_adapter *a = adapter; |
2079 | ||
8e86acd7 | 2080 | for (i = 0; i < adapter->num_vectors; i++) |
4662e82b BA |
2081 | adapter->msix_entries[i].entry = i; |
2082 | ||
0cc7c959 AG |
2083 | err = pci_enable_msix_range(a->pdev, |
2084 | a->msix_entries, | |
2085 | a->num_vectors, | |
2086 | a->num_vectors); | |
2087 | if (err > 0) | |
4662e82b BA |
2088 | return; |
2089 | } | |
2090 | /* MSI-X failed, so fall through and try MSI */ | |
ef456f85 | 2091 | e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n"); |
4662e82b BA |
2092 | e1000e_reset_interrupt_capability(adapter); |
2093 | } | |
2094 | adapter->int_mode = E1000E_INT_MODE_MSI; | |
2095 | /* Fall through */ | |
2096 | case E1000E_INT_MODE_MSI: | |
2097 | if (!pci_enable_msi(adapter->pdev)) { | |
2098 | adapter->flags |= FLAG_MSI_ENABLED; | |
2099 | } else { | |
2100 | adapter->int_mode = E1000E_INT_MODE_LEGACY; | |
ef456f85 | 2101 | e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n"); |
4662e82b BA |
2102 | } |
2103 | /* Fall through */ | |
2104 | case E1000E_INT_MODE_LEGACY: | |
2105 | /* Don't do anything; this is the system default */ | |
2106 | break; | |
2107 | } | |
8e86acd7 JK |
2108 | |
2109 | /* store the number of vectors being used */ | |
2110 | adapter->num_vectors = 1; | |
4662e82b BA |
2111 | } |
2112 | ||
2113 | /** | |
2114 | * e1000_request_msix - Initialize MSI-X interrupts | |
2115 | * | |
2116 | * e1000_request_msix allocates MSI-X vectors and requests interrupts from the | |
2117 | * kernel. | |
2118 | **/ | |
2119 | static int e1000_request_msix(struct e1000_adapter *adapter) | |
2120 | { | |
2121 | struct net_device *netdev = adapter->netdev; | |
2122 | int err = 0, vector = 0; | |
2123 | ||
2124 | if (strlen(netdev->name) < (IFNAMSIZ - 5)) | |
79f5e840 BA |
2125 | snprintf(adapter->rx_ring->name, |
2126 | sizeof(adapter->rx_ring->name) - 1, | |
2127 | "%s-rx-0", netdev->name); | |
4662e82b BA |
2128 | else |
2129 | memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ); | |
2130 | err = request_irq(adapter->msix_entries[vector].vector, | |
a0607fd3 | 2131 | e1000_intr_msix_rx, 0, adapter->rx_ring->name, |
4662e82b BA |
2132 | netdev); |
2133 | if (err) | |
5015e53a | 2134 | return err; |
c5083cf6 BA |
2135 | adapter->rx_ring->itr_register = adapter->hw.hw_addr + |
2136 | E1000_EITR_82574(vector); | |
4662e82b BA |
2137 | adapter->rx_ring->itr_val = adapter->itr; |
2138 | vector++; | |
2139 | ||
2140 | if (strlen(netdev->name) < (IFNAMSIZ - 5)) | |
79f5e840 BA |
2141 | snprintf(adapter->tx_ring->name, |
2142 | sizeof(adapter->tx_ring->name) - 1, | |
2143 | "%s-tx-0", netdev->name); | |
4662e82b BA |
2144 | else |
2145 | memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ); | |
2146 | err = request_irq(adapter->msix_entries[vector].vector, | |
a0607fd3 | 2147 | e1000_intr_msix_tx, 0, adapter->tx_ring->name, |
4662e82b BA |
2148 | netdev); |
2149 | if (err) | |
5015e53a | 2150 | return err; |
c5083cf6 BA |
2151 | adapter->tx_ring->itr_register = adapter->hw.hw_addr + |
2152 | E1000_EITR_82574(vector); | |
4662e82b BA |
2153 | adapter->tx_ring->itr_val = adapter->itr; |
2154 | vector++; | |
2155 | ||
2156 | err = request_irq(adapter->msix_entries[vector].vector, | |
a0607fd3 | 2157 | e1000_msix_other, 0, netdev->name, netdev); |
4662e82b | 2158 | if (err) |
5015e53a | 2159 | return err; |
4662e82b BA |
2160 | |
2161 | e1000_configure_msix(adapter); | |
5015e53a | 2162 | |
4662e82b | 2163 | return 0; |
4662e82b BA |
2164 | } |
2165 | ||
f8d59f78 BA |
2166 | /** |
2167 | * e1000_request_irq - initialize interrupts | |
2168 | * | |
2169 | * Attempts to configure interrupts using the best available | |
2170 | * capabilities of the hardware and kernel. | |
2171 | **/ | |
bc7f75fa AK |
2172 | static int e1000_request_irq(struct e1000_adapter *adapter) |
2173 | { | |
2174 | struct net_device *netdev = adapter->netdev; | |
bc7f75fa AK |
2175 | int err; |
2176 | ||
4662e82b BA |
2177 | if (adapter->msix_entries) { |
2178 | err = e1000_request_msix(adapter); | |
2179 | if (!err) | |
2180 | return err; | |
2181 | /* fall back to MSI */ | |
2182 | e1000e_reset_interrupt_capability(adapter); | |
2183 | adapter->int_mode = E1000E_INT_MODE_MSI; | |
2184 | e1000e_set_interrupt_capability(adapter); | |
bc7f75fa | 2185 | } |
4662e82b | 2186 | if (adapter->flags & FLAG_MSI_ENABLED) { |
a0607fd3 | 2187 | err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0, |
4662e82b BA |
2188 | netdev->name, netdev); |
2189 | if (!err) | |
2190 | return err; | |
bc7f75fa | 2191 | |
4662e82b BA |
2192 | /* fall back to legacy interrupt */ |
2193 | e1000e_reset_interrupt_capability(adapter); | |
2194 | adapter->int_mode = E1000E_INT_MODE_LEGACY; | |
bc7f75fa AK |
2195 | } |
2196 | ||
a0607fd3 | 2197 | err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED, |
4662e82b BA |
2198 | netdev->name, netdev); |
2199 | if (err) | |
2200 | e_err("Unable to allocate interrupt, Error: %d\n", err); | |
2201 | ||
bc7f75fa AK |
2202 | return err; |
2203 | } | |
2204 | ||
2205 | static void e1000_free_irq(struct e1000_adapter *adapter) | |
2206 | { | |
2207 | struct net_device *netdev = adapter->netdev; | |
2208 | ||
4662e82b BA |
2209 | if (adapter->msix_entries) { |
2210 | int vector = 0; | |
2211 | ||
2212 | free_irq(adapter->msix_entries[vector].vector, netdev); | |
2213 | vector++; | |
2214 | ||
2215 | free_irq(adapter->msix_entries[vector].vector, netdev); | |
2216 | vector++; | |
2217 | ||
2218 | /* Other Causes interrupt vector */ | |
2219 | free_irq(adapter->msix_entries[vector].vector, netdev); | |
2220 | return; | |
bc7f75fa | 2221 | } |
4662e82b BA |
2222 | |
2223 | free_irq(adapter->pdev->irq, netdev); | |
bc7f75fa AK |
2224 | } |
2225 | ||
2226 | /** | |
2227 | * e1000_irq_disable - Mask off interrupt generation on the NIC | |
2228 | **/ | |
2229 | static void e1000_irq_disable(struct e1000_adapter *adapter) | |
2230 | { | |
2231 | struct e1000_hw *hw = &adapter->hw; | |
2232 | ||
bc7f75fa | 2233 | ew32(IMC, ~0); |
4662e82b BA |
2234 | if (adapter->msix_entries) |
2235 | ew32(EIAC_82574, 0); | |
bc7f75fa | 2236 | e1e_flush(); |
8e86acd7 JK |
2237 | |
2238 | if (adapter->msix_entries) { | |
2239 | int i; | |
6cf08d1c | 2240 | |
8e86acd7 JK |
2241 | for (i = 0; i < adapter->num_vectors; i++) |
2242 | synchronize_irq(adapter->msix_entries[i].vector); | |
2243 | } else { | |
2244 | synchronize_irq(adapter->pdev->irq); | |
2245 | } | |
bc7f75fa AK |
2246 | } |
2247 | ||
2248 | /** | |
2249 | * e1000_irq_enable - Enable default interrupt generation settings | |
2250 | **/ | |
2251 | static void e1000_irq_enable(struct e1000_adapter *adapter) | |
2252 | { | |
2253 | struct e1000_hw *hw = &adapter->hw; | |
2254 | ||
4662e82b BA |
2255 | if (adapter->msix_entries) { |
2256 | ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574); | |
116f4a64 BP |
2257 | ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | |
2258 | IMS_OTHER_MASK); | |
c8744f44 | 2259 | } else if (hw->mac.type >= e1000_pch_lpt) { |
94fb848b | 2260 | ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER); |
4662e82b BA |
2261 | } else { |
2262 | ew32(IMS, IMS_ENABLE_MASK); | |
2263 | } | |
74ef9c39 | 2264 | e1e_flush(); |
bc7f75fa AK |
2265 | } |
2266 | ||
2267 | /** | |
31dbe5b4 | 2268 | * e1000e_get_hw_control - get control of the h/w from f/w |
bc7f75fa AK |
2269 | * @adapter: address of board private structure |
2270 | * | |
31dbe5b4 | 2271 | * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit. |
bc7f75fa AK |
2272 | * For ASF and Pass Through versions of f/w this means that |
2273 | * the driver is loaded. For AMT version (only with 82573) | |
2274 | * of the f/w this means that the network i/f is open. | |
2275 | **/ | |
31dbe5b4 | 2276 | void e1000e_get_hw_control(struct e1000_adapter *adapter) |
bc7f75fa AK |
2277 | { |
2278 | struct e1000_hw *hw = &adapter->hw; | |
2279 | u32 ctrl_ext; | |
2280 | u32 swsm; | |
2281 | ||
2282 | /* Let firmware know the driver has taken over */ | |
2283 | if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { | |
2284 | swsm = er32(SWSM); | |
2285 | ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD); | |
2286 | } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { | |
2287 | ctrl_ext = er32(CTRL_EXT); | |
ad68076e | 2288 | ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); |
bc7f75fa AK |
2289 | } |
2290 | } | |
2291 | ||
2292 | /** | |
31dbe5b4 | 2293 | * e1000e_release_hw_control - release control of the h/w to f/w |
bc7f75fa AK |
2294 | * @adapter: address of board private structure |
2295 | * | |
31dbe5b4 | 2296 | * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit. |
bc7f75fa AK |
2297 | * For ASF and Pass Through versions of f/w this means that the |
2298 | * driver is no longer loaded. For AMT version (only with 82573) i | |
2299 | * of the f/w this means that the network i/f is closed. | |
2300 | * | |
2301 | **/ | |
31dbe5b4 | 2302 | void e1000e_release_hw_control(struct e1000_adapter *adapter) |
bc7f75fa AK |
2303 | { |
2304 | struct e1000_hw *hw = &adapter->hw; | |
2305 | u32 ctrl_ext; | |
2306 | u32 swsm; | |
2307 | ||
2308 | /* Let firmware taken over control of h/w */ | |
2309 | if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) { | |
2310 | swsm = er32(SWSM); | |
2311 | ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD); | |
2312 | } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) { | |
2313 | ctrl_ext = er32(CTRL_EXT); | |
ad68076e | 2314 | ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); |
bc7f75fa AK |
2315 | } |
2316 | } | |
2317 | ||
bc7f75fa | 2318 | /** |
49ce9c2c | 2319 | * e1000_alloc_ring_dma - allocate memory for a ring structure |
bc7f75fa AK |
2320 | **/ |
2321 | static int e1000_alloc_ring_dma(struct e1000_adapter *adapter, | |
2322 | struct e1000_ring *ring) | |
2323 | { | |
2324 | struct pci_dev *pdev = adapter->pdev; | |
2325 | ||
aea3fca0 PYK |
2326 | ring->desc = dma_zalloc_coherent(&pdev->dev, ring->size, &ring->dma, |
2327 | GFP_KERNEL); | |
bc7f75fa AK |
2328 | if (!ring->desc) |
2329 | return -ENOMEM; | |
2330 | ||
2331 | return 0; | |
2332 | } | |
2333 | ||
2334 | /** | |
2335 | * e1000e_setup_tx_resources - allocate Tx resources (Descriptors) | |
55aa6985 | 2336 | * @tx_ring: Tx descriptor ring |
bc7f75fa AK |
2337 | * |
2338 | * Return 0 on success, negative on failure | |
2339 | **/ | |
55aa6985 | 2340 | int e1000e_setup_tx_resources(struct e1000_ring *tx_ring) |
bc7f75fa | 2341 | { |
55aa6985 | 2342 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa AK |
2343 | int err = -ENOMEM, size; |
2344 | ||
2345 | size = sizeof(struct e1000_buffer) * tx_ring->count; | |
89bf67f1 | 2346 | tx_ring->buffer_info = vzalloc(size); |
bc7f75fa AK |
2347 | if (!tx_ring->buffer_info) |
2348 | goto err; | |
bc7f75fa AK |
2349 | |
2350 | /* round up to nearest 4K */ | |
2351 | tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc); | |
2352 | tx_ring->size = ALIGN(tx_ring->size, 4096); | |
2353 | ||
2354 | err = e1000_alloc_ring_dma(adapter, tx_ring); | |
2355 | if (err) | |
2356 | goto err; | |
2357 | ||
2358 | tx_ring->next_to_use = 0; | |
2359 | tx_ring->next_to_clean = 0; | |
bc7f75fa AK |
2360 | |
2361 | return 0; | |
2362 | err: | |
2363 | vfree(tx_ring->buffer_info); | |
44defeb3 | 2364 | e_err("Unable to allocate memory for the transmit descriptor ring\n"); |
bc7f75fa AK |
2365 | return err; |
2366 | } | |
2367 | ||
2368 | /** | |
2369 | * e1000e_setup_rx_resources - allocate Rx resources (Descriptors) | |
55aa6985 | 2370 | * @rx_ring: Rx descriptor ring |
bc7f75fa AK |
2371 | * |
2372 | * Returns 0 on success, negative on failure | |
2373 | **/ | |
55aa6985 | 2374 | int e1000e_setup_rx_resources(struct e1000_ring *rx_ring) |
bc7f75fa | 2375 | { |
55aa6985 | 2376 | struct e1000_adapter *adapter = rx_ring->adapter; |
47f44e40 AK |
2377 | struct e1000_buffer *buffer_info; |
2378 | int i, size, desc_len, err = -ENOMEM; | |
bc7f75fa AK |
2379 | |
2380 | size = sizeof(struct e1000_buffer) * rx_ring->count; | |
89bf67f1 | 2381 | rx_ring->buffer_info = vzalloc(size); |
bc7f75fa AK |
2382 | if (!rx_ring->buffer_info) |
2383 | goto err; | |
bc7f75fa | 2384 | |
47f44e40 AK |
2385 | for (i = 0; i < rx_ring->count; i++) { |
2386 | buffer_info = &rx_ring->buffer_info[i]; | |
2387 | buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS, | |
2388 | sizeof(struct e1000_ps_page), | |
2389 | GFP_KERNEL); | |
2390 | if (!buffer_info->ps_pages) | |
2391 | goto err_pages; | |
2392 | } | |
bc7f75fa AK |
2393 | |
2394 | desc_len = sizeof(union e1000_rx_desc_packet_split); | |
2395 | ||
2396 | /* Round up to nearest 4K */ | |
2397 | rx_ring->size = rx_ring->count * desc_len; | |
2398 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
2399 | ||
2400 | err = e1000_alloc_ring_dma(adapter, rx_ring); | |
2401 | if (err) | |
47f44e40 | 2402 | goto err_pages; |
bc7f75fa AK |
2403 | |
2404 | rx_ring->next_to_clean = 0; | |
2405 | rx_ring->next_to_use = 0; | |
2406 | rx_ring->rx_skb_top = NULL; | |
2407 | ||
2408 | return 0; | |
47f44e40 AK |
2409 | |
2410 | err_pages: | |
2411 | for (i = 0; i < rx_ring->count; i++) { | |
2412 | buffer_info = &rx_ring->buffer_info[i]; | |
2413 | kfree(buffer_info->ps_pages); | |
2414 | } | |
bc7f75fa AK |
2415 | err: |
2416 | vfree(rx_ring->buffer_info); | |
e9262447 | 2417 | e_err("Unable to allocate memory for the receive descriptor ring\n"); |
bc7f75fa AK |
2418 | return err; |
2419 | } | |
2420 | ||
2421 | /** | |
2422 | * e1000_clean_tx_ring - Free Tx Buffers | |
55aa6985 | 2423 | * @tx_ring: Tx descriptor ring |
bc7f75fa | 2424 | **/ |
55aa6985 | 2425 | static void e1000_clean_tx_ring(struct e1000_ring *tx_ring) |
bc7f75fa | 2426 | { |
55aa6985 | 2427 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa AK |
2428 | struct e1000_buffer *buffer_info; |
2429 | unsigned long size; | |
2430 | unsigned int i; | |
2431 | ||
2432 | for (i = 0; i < tx_ring->count; i++) { | |
2433 | buffer_info = &tx_ring->buffer_info[i]; | |
377b6273 | 2434 | e1000_put_txbuf(tx_ring, buffer_info, false); |
bc7f75fa AK |
2435 | } |
2436 | ||
3f0cfa3b | 2437 | netdev_reset_queue(adapter->netdev); |
bc7f75fa AK |
2438 | size = sizeof(struct e1000_buffer) * tx_ring->count; |
2439 | memset(tx_ring->buffer_info, 0, size); | |
2440 | ||
2441 | memset(tx_ring->desc, 0, tx_ring->size); | |
2442 | ||
2443 | tx_ring->next_to_use = 0; | |
2444 | tx_ring->next_to_clean = 0; | |
bc7f75fa AK |
2445 | } |
2446 | ||
2447 | /** | |
2448 | * e1000e_free_tx_resources - Free Tx Resources per Queue | |
55aa6985 | 2449 | * @tx_ring: Tx descriptor ring |
bc7f75fa AK |
2450 | * |
2451 | * Free all transmit software resources | |
2452 | **/ | |
55aa6985 | 2453 | void e1000e_free_tx_resources(struct e1000_ring *tx_ring) |
bc7f75fa | 2454 | { |
55aa6985 | 2455 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa | 2456 | struct pci_dev *pdev = adapter->pdev; |
bc7f75fa | 2457 | |
55aa6985 | 2458 | e1000_clean_tx_ring(tx_ring); |
bc7f75fa AK |
2459 | |
2460 | vfree(tx_ring->buffer_info); | |
2461 | tx_ring->buffer_info = NULL; | |
2462 | ||
2463 | dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, | |
2464 | tx_ring->dma); | |
2465 | tx_ring->desc = NULL; | |
2466 | } | |
2467 | ||
2468 | /** | |
2469 | * e1000e_free_rx_resources - Free Rx Resources | |
55aa6985 | 2470 | * @rx_ring: Rx descriptor ring |
bc7f75fa AK |
2471 | * |
2472 | * Free all receive software resources | |
2473 | **/ | |
55aa6985 | 2474 | void e1000e_free_rx_resources(struct e1000_ring *rx_ring) |
bc7f75fa | 2475 | { |
55aa6985 | 2476 | struct e1000_adapter *adapter = rx_ring->adapter; |
bc7f75fa | 2477 | struct pci_dev *pdev = adapter->pdev; |
47f44e40 | 2478 | int i; |
bc7f75fa | 2479 | |
55aa6985 | 2480 | e1000_clean_rx_ring(rx_ring); |
bc7f75fa | 2481 | |
b1cdfead | 2482 | for (i = 0; i < rx_ring->count; i++) |
47f44e40 | 2483 | kfree(rx_ring->buffer_info[i].ps_pages); |
47f44e40 | 2484 | |
bc7f75fa AK |
2485 | vfree(rx_ring->buffer_info); |
2486 | rx_ring->buffer_info = NULL; | |
2487 | ||
bc7f75fa AK |
2488 | dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, |
2489 | rx_ring->dma); | |
2490 | rx_ring->desc = NULL; | |
2491 | } | |
2492 | ||
2493 | /** | |
2494 | * e1000_update_itr - update the dynamic ITR value based on statistics | |
489815ce AK |
2495 | * @adapter: pointer to adapter |
2496 | * @itr_setting: current adapter->itr | |
2497 | * @packets: the number of packets during this measurement interval | |
2498 | * @bytes: the number of bytes during this measurement interval | |
2499 | * | |
bc7f75fa AK |
2500 | * Stores a new ITR value based on packets and byte |
2501 | * counts during the last interrupt. The advantage of per interrupt | |
2502 | * computation is faster updates and more accurate ITR for the current | |
2503 | * traffic pattern. Constants in this function were computed | |
2504 | * based on theoretical maximum wire speed and thresholds were set based | |
2505 | * on testing data as well as attempting to minimize response time | |
4662e82b BA |
2506 | * while increasing bulk throughput. This functionality is controlled |
2507 | * by the InterruptThrottleRate module parameter. | |
bc7f75fa | 2508 | **/ |
8bb62869 | 2509 | static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes) |
bc7f75fa AK |
2510 | { |
2511 | unsigned int retval = itr_setting; | |
2512 | ||
2513 | if (packets == 0) | |
5015e53a | 2514 | return itr_setting; |
bc7f75fa AK |
2515 | |
2516 | switch (itr_setting) { | |
2517 | case lowest_latency: | |
2518 | /* handle TSO and jumbo frames */ | |
362e20ca | 2519 | if (bytes / packets > 8000) |
bc7f75fa | 2520 | retval = bulk_latency; |
b1cdfead | 2521 | else if ((packets < 5) && (bytes > 512)) |
bc7f75fa | 2522 | retval = low_latency; |
bc7f75fa | 2523 | break; |
e80bd1d1 | 2524 | case low_latency: /* 50 usec aka 20000 ints/s */ |
bc7f75fa AK |
2525 | if (bytes > 10000) { |
2526 | /* this if handles the TSO accounting */ | |
362e20ca | 2527 | if (bytes / packets > 8000) |
bc7f75fa | 2528 | retval = bulk_latency; |
362e20ca | 2529 | else if ((packets < 10) || ((bytes / packets) > 1200)) |
bc7f75fa | 2530 | retval = bulk_latency; |
b1cdfead | 2531 | else if ((packets > 35)) |
bc7f75fa | 2532 | retval = lowest_latency; |
362e20ca | 2533 | } else if (bytes / packets > 2000) { |
bc7f75fa AK |
2534 | retval = bulk_latency; |
2535 | } else if (packets <= 2 && bytes < 512) { | |
2536 | retval = lowest_latency; | |
2537 | } | |
2538 | break; | |
e80bd1d1 | 2539 | case bulk_latency: /* 250 usec aka 4000 ints/s */ |
bc7f75fa | 2540 | if (bytes > 25000) { |
b1cdfead | 2541 | if (packets > 35) |
bc7f75fa | 2542 | retval = low_latency; |
bc7f75fa AK |
2543 | } else if (bytes < 6000) { |
2544 | retval = low_latency; | |
2545 | } | |
2546 | break; | |
2547 | } | |
2548 | ||
bc7f75fa AK |
2549 | return retval; |
2550 | } | |
2551 | ||
2552 | static void e1000_set_itr(struct e1000_adapter *adapter) | |
2553 | { | |
bc7f75fa AK |
2554 | u16 current_itr; |
2555 | u32 new_itr = adapter->itr; | |
2556 | ||
2557 | /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ | |
2558 | if (adapter->link_speed != SPEED_1000) { | |
2559 | current_itr = 0; | |
2560 | new_itr = 4000; | |
2561 | goto set_itr_now; | |
2562 | } | |
2563 | ||
828bac87 BA |
2564 | if (adapter->flags2 & FLAG2_DISABLE_AIM) { |
2565 | new_itr = 0; | |
2566 | goto set_itr_now; | |
2567 | } | |
2568 | ||
8bb62869 BA |
2569 | adapter->tx_itr = e1000_update_itr(adapter->tx_itr, |
2570 | adapter->total_tx_packets, | |
2571 | adapter->total_tx_bytes); | |
bc7f75fa AK |
2572 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
2573 | if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency) | |
2574 | adapter->tx_itr = low_latency; | |
2575 | ||
8bb62869 BA |
2576 | adapter->rx_itr = e1000_update_itr(adapter->rx_itr, |
2577 | adapter->total_rx_packets, | |
2578 | adapter->total_rx_bytes); | |
bc7f75fa AK |
2579 | /* conservative mode (itr 3) eliminates the lowest_latency setting */ |
2580 | if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency) | |
2581 | adapter->rx_itr = low_latency; | |
2582 | ||
2583 | current_itr = max(adapter->rx_itr, adapter->tx_itr); | |
2584 | ||
bc7f75fa | 2585 | /* counts and packets in update_itr are dependent on these numbers */ |
33550cec | 2586 | switch (current_itr) { |
bc7f75fa AK |
2587 | case lowest_latency: |
2588 | new_itr = 70000; | |
2589 | break; | |
2590 | case low_latency: | |
e80bd1d1 | 2591 | new_itr = 20000; /* aka hwitr = ~200 */ |
bc7f75fa AK |
2592 | break; |
2593 | case bulk_latency: | |
2594 | new_itr = 4000; | |
2595 | break; | |
2596 | default: | |
2597 | break; | |
2598 | } | |
2599 | ||
2600 | set_itr_now: | |
2601 | if (new_itr != adapter->itr) { | |
e921eb1a | 2602 | /* this attempts to bias the interrupt rate towards Bulk |
bc7f75fa | 2603 | * by adding intermediate steps when interrupt rate is |
ad68076e BA |
2604 | * increasing |
2605 | */ | |
bc7f75fa | 2606 | new_itr = new_itr > adapter->itr ? |
f0ff4398 | 2607 | min(adapter->itr + (new_itr >> 2), new_itr) : new_itr; |
bc7f75fa | 2608 | adapter->itr = new_itr; |
4662e82b BA |
2609 | adapter->rx_ring->itr_val = new_itr; |
2610 | if (adapter->msix_entries) | |
2611 | adapter->rx_ring->set_itr = 1; | |
2612 | else | |
e3d14b08 | 2613 | e1000e_write_itr(adapter, new_itr); |
bc7f75fa AK |
2614 | } |
2615 | } | |
2616 | ||
22a4cca2 MV |
2617 | /** |
2618 | * e1000e_write_itr - write the ITR value to the appropriate registers | |
2619 | * @adapter: address of board private structure | |
2620 | * @itr: new ITR value to program | |
2621 | * | |
2622 | * e1000e_write_itr determines if the adapter is in MSI-X mode | |
2623 | * and, if so, writes the EITR registers with the ITR value. | |
2624 | * Otherwise, it writes the ITR value into the ITR register. | |
2625 | **/ | |
2626 | void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr) | |
2627 | { | |
2628 | struct e1000_hw *hw = &adapter->hw; | |
2629 | u32 new_itr = itr ? 1000000000 / (itr * 256) : 0; | |
2630 | ||
2631 | if (adapter->msix_entries) { | |
2632 | int vector; | |
2633 | ||
2634 | for (vector = 0; vector < adapter->num_vectors; vector++) | |
2635 | writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector)); | |
2636 | } else { | |
2637 | ew32(ITR, new_itr); | |
2638 | } | |
2639 | } | |
2640 | ||
4662e82b BA |
2641 | /** |
2642 | * e1000_alloc_queues - Allocate memory for all rings | |
2643 | * @adapter: board private structure to initialize | |
2644 | **/ | |
9f9a12f8 | 2645 | static int e1000_alloc_queues(struct e1000_adapter *adapter) |
4662e82b | 2646 | { |
55aa6985 BA |
2647 | int size = sizeof(struct e1000_ring); |
2648 | ||
2649 | adapter->tx_ring = kzalloc(size, GFP_KERNEL); | |
4662e82b BA |
2650 | if (!adapter->tx_ring) |
2651 | goto err; | |
55aa6985 BA |
2652 | adapter->tx_ring->count = adapter->tx_ring_count; |
2653 | adapter->tx_ring->adapter = adapter; | |
4662e82b | 2654 | |
55aa6985 | 2655 | adapter->rx_ring = kzalloc(size, GFP_KERNEL); |
4662e82b BA |
2656 | if (!adapter->rx_ring) |
2657 | goto err; | |
55aa6985 BA |
2658 | adapter->rx_ring->count = adapter->rx_ring_count; |
2659 | adapter->rx_ring->adapter = adapter; | |
4662e82b BA |
2660 | |
2661 | return 0; | |
2662 | err: | |
2663 | e_err("Unable to allocate memory for queues\n"); | |
2664 | kfree(adapter->rx_ring); | |
2665 | kfree(adapter->tx_ring); | |
2666 | return -ENOMEM; | |
2667 | } | |
2668 | ||
bc7f75fa | 2669 | /** |
c58c8a78 | 2670 | * e1000e_poll - NAPI Rx polling callback |
ad68076e | 2671 | * @napi: struct associated with this polling callback |
c58c8a78 | 2672 | * @weight: number of packets driver is allowed to process this poll |
bc7f75fa | 2673 | **/ |
c58c8a78 | 2674 | static int e1000e_poll(struct napi_struct *napi, int weight) |
bc7f75fa | 2675 | { |
c58c8a78 BA |
2676 | struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, |
2677 | napi); | |
4662e82b | 2678 | struct e1000_hw *hw = &adapter->hw; |
bc7f75fa | 2679 | struct net_device *poll_dev = adapter->netdev; |
679e8a0f | 2680 | int tx_cleaned = 1, work_done = 0; |
bc7f75fa | 2681 | |
4cf1653a | 2682 | adapter = netdev_priv(poll_dev); |
bc7f75fa | 2683 | |
c58c8a78 BA |
2684 | if (!adapter->msix_entries || |
2685 | (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val)) | |
2686 | tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring); | |
4662e82b | 2687 | |
c58c8a78 | 2688 | adapter->clean_rx(adapter->rx_ring, &work_done, weight); |
d2c7ddd6 | 2689 | |
12d04a3c | 2690 | if (!tx_cleaned) |
c58c8a78 | 2691 | work_done = weight; |
bc7f75fa | 2692 | |
c58c8a78 BA |
2693 | /* If weight not fully consumed, exit the polling mode */ |
2694 | if (work_done < weight) { | |
bc7f75fa AK |
2695 | if (adapter->itr_setting & 3) |
2696 | e1000_set_itr(adapter); | |
32b3e08f | 2697 | napi_complete_done(napi, work_done); |
a3c69fef JB |
2698 | if (!test_bit(__E1000_DOWN, &adapter->state)) { |
2699 | if (adapter->msix_entries) | |
1f0ea197 | 2700 | ew32(IMS, adapter->rx_ring->ims_val); |
a3c69fef JB |
2701 | else |
2702 | e1000_irq_enable(adapter); | |
2703 | } | |
bc7f75fa AK |
2704 | } |
2705 | ||
2706 | return work_done; | |
2707 | } | |
2708 | ||
80d5c368 | 2709 | static int e1000_vlan_rx_add_vid(struct net_device *netdev, |
603cdca9 | 2710 | __always_unused __be16 proto, u16 vid) |
bc7f75fa AK |
2711 | { |
2712 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
2713 | struct e1000_hw *hw = &adapter->hw; | |
2714 | u32 vfta, index; | |
2715 | ||
2716 | /* don't update vlan cookie if already programmed */ | |
2717 | if ((adapter->hw.mng_cookie.status & | |
2718 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
2719 | (vid == adapter->mng_vlan_id)) | |
8e586137 | 2720 | return 0; |
caaddaf8 | 2721 | |
bc7f75fa | 2722 | /* add VID to filter table */ |
caaddaf8 BA |
2723 | if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { |
2724 | index = (vid >> 5) & 0x7F; | |
2725 | vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); | |
18dd2392 | 2726 | vfta |= BIT((vid & 0x1F)); |
caaddaf8 BA |
2727 | hw->mac.ops.write_vfta(hw, index, vfta); |
2728 | } | |
86d70e53 JK |
2729 | |
2730 | set_bit(vid, adapter->active_vlans); | |
8e586137 JP |
2731 | |
2732 | return 0; | |
bc7f75fa AK |
2733 | } |
2734 | ||
80d5c368 | 2735 | static int e1000_vlan_rx_kill_vid(struct net_device *netdev, |
603cdca9 | 2736 | __always_unused __be16 proto, u16 vid) |
bc7f75fa AK |
2737 | { |
2738 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
2739 | struct e1000_hw *hw = &adapter->hw; | |
2740 | u32 vfta, index; | |
2741 | ||
bc7f75fa AK |
2742 | if ((adapter->hw.mng_cookie.status & |
2743 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN) && | |
2744 | (vid == adapter->mng_vlan_id)) { | |
2745 | /* release control to f/w */ | |
31dbe5b4 | 2746 | e1000e_release_hw_control(adapter); |
8e586137 | 2747 | return 0; |
bc7f75fa AK |
2748 | } |
2749 | ||
2750 | /* remove VID from filter table */ | |
caaddaf8 BA |
2751 | if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { |
2752 | index = (vid >> 5) & 0x7F; | |
2753 | vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index); | |
18dd2392 | 2754 | vfta &= ~BIT((vid & 0x1F)); |
caaddaf8 BA |
2755 | hw->mac.ops.write_vfta(hw, index, vfta); |
2756 | } | |
86d70e53 JK |
2757 | |
2758 | clear_bit(vid, adapter->active_vlans); | |
8e586137 JP |
2759 | |
2760 | return 0; | |
bc7f75fa AK |
2761 | } |
2762 | ||
86d70e53 JK |
2763 | /** |
2764 | * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering | |
2765 | * @adapter: board private structure to initialize | |
2766 | **/ | |
2767 | static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter) | |
bc7f75fa AK |
2768 | { |
2769 | struct net_device *netdev = adapter->netdev; | |
86d70e53 JK |
2770 | struct e1000_hw *hw = &adapter->hw; |
2771 | u32 rctl; | |
bc7f75fa | 2772 | |
86d70e53 JK |
2773 | if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { |
2774 | /* disable VLAN receive filtering */ | |
2775 | rctl = er32(RCTL); | |
2776 | rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN); | |
2777 | ew32(RCTL, rctl); | |
2778 | ||
2779 | if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) { | |
80d5c368 PM |
2780 | e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), |
2781 | adapter->mng_vlan_id); | |
86d70e53 | 2782 | adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; |
bc7f75fa | 2783 | } |
bc7f75fa AK |
2784 | } |
2785 | } | |
2786 | ||
86d70e53 JK |
2787 | /** |
2788 | * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering | |
2789 | * @adapter: board private structure to initialize | |
2790 | **/ | |
2791 | static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter) | |
2792 | { | |
2793 | struct e1000_hw *hw = &adapter->hw; | |
2794 | u32 rctl; | |
2795 | ||
2796 | if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) { | |
2797 | /* enable VLAN receive filtering */ | |
2798 | rctl = er32(RCTL); | |
2799 | rctl |= E1000_RCTL_VFE; | |
2800 | rctl &= ~E1000_RCTL_CFIEN; | |
2801 | ew32(RCTL, rctl); | |
2802 | } | |
2803 | } | |
bc7f75fa | 2804 | |
86d70e53 | 2805 | /** |
889ad456 | 2806 | * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping |
86d70e53 JK |
2807 | * @adapter: board private structure to initialize |
2808 | **/ | |
2809 | static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter) | |
bc7f75fa | 2810 | { |
bc7f75fa | 2811 | struct e1000_hw *hw = &adapter->hw; |
86d70e53 | 2812 | u32 ctrl; |
bc7f75fa | 2813 | |
86d70e53 JK |
2814 | /* disable VLAN tag insert/strip */ |
2815 | ctrl = er32(CTRL); | |
2816 | ctrl &= ~E1000_CTRL_VME; | |
2817 | ew32(CTRL, ctrl); | |
2818 | } | |
bc7f75fa | 2819 | |
86d70e53 JK |
2820 | /** |
2821 | * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping | |
2822 | * @adapter: board private structure to initialize | |
2823 | **/ | |
2824 | static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter) | |
2825 | { | |
2826 | struct e1000_hw *hw = &adapter->hw; | |
2827 | u32 ctrl; | |
bc7f75fa | 2828 | |
86d70e53 JK |
2829 | /* enable VLAN tag insert/strip */ |
2830 | ctrl = er32(CTRL); | |
2831 | ctrl |= E1000_CTRL_VME; | |
2832 | ew32(CTRL, ctrl); | |
2833 | } | |
bc7f75fa | 2834 | |
86d70e53 JK |
2835 | static void e1000_update_mng_vlan(struct e1000_adapter *adapter) |
2836 | { | |
2837 | struct net_device *netdev = adapter->netdev; | |
2838 | u16 vid = adapter->hw.mng_cookie.vlan_id; | |
2839 | u16 old_vid = adapter->mng_vlan_id; | |
2840 | ||
e5fe2541 | 2841 | if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { |
80d5c368 | 2842 | e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid); |
86d70e53 | 2843 | adapter->mng_vlan_id = vid; |
bc7f75fa AK |
2844 | } |
2845 | ||
86d70e53 | 2846 | if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid)) |
80d5c368 | 2847 | e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid); |
bc7f75fa AK |
2848 | } |
2849 | ||
2850 | static void e1000_restore_vlan(struct e1000_adapter *adapter) | |
2851 | { | |
2852 | u16 vid; | |
2853 | ||
80d5c368 | 2854 | e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0); |
bc7f75fa | 2855 | |
86d70e53 | 2856 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) |
80d5c368 | 2857 | e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); |
bc7f75fa AK |
2858 | } |
2859 | ||
cd791618 | 2860 | static void e1000_init_manageability_pt(struct e1000_adapter *adapter) |
bc7f75fa AK |
2861 | { |
2862 | struct e1000_hw *hw = &adapter->hw; | |
cd791618 | 2863 | u32 manc, manc2h, mdef, i, j; |
bc7f75fa AK |
2864 | |
2865 | if (!(adapter->flags & FLAG_MNG_PT_ENABLED)) | |
2866 | return; | |
2867 | ||
2868 | manc = er32(MANC); | |
2869 | ||
e921eb1a | 2870 | /* enable receiving management packets to the host. this will probably |
bc7f75fa | 2871 | * generate destination unreachable messages from the host OS, but |
ad68076e BA |
2872 | * the packets will be handled on SMBUS |
2873 | */ | |
bc7f75fa AK |
2874 | manc |= E1000_MANC_EN_MNG2HOST; |
2875 | manc2h = er32(MANC2H); | |
cd791618 BA |
2876 | |
2877 | switch (hw->mac.type) { | |
2878 | default: | |
2879 | manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664); | |
2880 | break; | |
2881 | case e1000_82574: | |
2882 | case e1000_82583: | |
e921eb1a | 2883 | /* Check if IPMI pass-through decision filter already exists; |
cd791618 BA |
2884 | * if so, enable it. |
2885 | */ | |
2886 | for (i = 0, j = 0; i < 8; i++) { | |
2887 | mdef = er32(MDEF(i)); | |
2888 | ||
2889 | /* Ignore filters with anything other than IPMI ports */ | |
3b21b508 | 2890 | if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) |
cd791618 BA |
2891 | continue; |
2892 | ||
2893 | /* Enable this decision filter in MANC2H */ | |
2894 | if (mdef) | |
18dd2392 | 2895 | manc2h |= BIT(i); |
cd791618 BA |
2896 | |
2897 | j |= mdef; | |
2898 | } | |
2899 | ||
2900 | if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664)) | |
2901 | break; | |
2902 | ||
2903 | /* Create new decision filter in an empty filter */ | |
2904 | for (i = 0, j = 0; i < 8; i++) | |
2905 | if (er32(MDEF(i)) == 0) { | |
2906 | ew32(MDEF(i), (E1000_MDEF_PORT_623 | | |
2907 | E1000_MDEF_PORT_664)); | |
18dd2392 | 2908 | manc2h |= BIT(1); |
cd791618 BA |
2909 | j++; |
2910 | break; | |
2911 | } | |
2912 | ||
2913 | if (!j) | |
2914 | e_warn("Unable to create IPMI pass-through filter\n"); | |
2915 | break; | |
2916 | } | |
2917 | ||
bc7f75fa AK |
2918 | ew32(MANC2H, manc2h); |
2919 | ew32(MANC, manc); | |
2920 | } | |
2921 | ||
2922 | /** | |
af667a29 | 2923 | * e1000_configure_tx - Configure Transmit Unit after Reset |
bc7f75fa AK |
2924 | * @adapter: board private structure |
2925 | * | |
2926 | * Configure the Tx unit of the MAC after a reset. | |
2927 | **/ | |
2928 | static void e1000_configure_tx(struct e1000_adapter *adapter) | |
2929 | { | |
2930 | struct e1000_hw *hw = &adapter->hw; | |
2931 | struct e1000_ring *tx_ring = adapter->tx_ring; | |
2932 | u64 tdba; | |
e7e834aa | 2933 | u32 tdlen, tctl, tarc; |
bc7f75fa AK |
2934 | |
2935 | /* Setup the HW Tx Head and Tail descriptor pointers */ | |
2936 | tdba = tx_ring->dma; | |
2937 | tdlen = tx_ring->count * sizeof(struct e1000_tx_desc); | |
1e36052e BA |
2938 | ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32))); |
2939 | ew32(TDBAH(0), (tdba >> 32)); | |
2940 | ew32(TDLEN(0), tdlen); | |
2941 | ew32(TDH(0), 0); | |
2942 | ew32(TDT(0), 0); | |
2943 | tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0); | |
2944 | tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0); | |
bc7f75fa | 2945 | |
0845d45e JJB |
2946 | writel(0, tx_ring->head); |
2947 | if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) | |
2948 | e1000e_update_tdt_wa(tx_ring, 0); | |
2949 | else | |
2950 | writel(0, tx_ring->tail); | |
2951 | ||
bc7f75fa AK |
2952 | /* Set the Tx Interrupt Delay register */ |
2953 | ew32(TIDV, adapter->tx_int_delay); | |
ad68076e | 2954 | /* Tx irq moderation */ |
bc7f75fa AK |
2955 | ew32(TADV, adapter->tx_abs_int_delay); |
2956 | ||
3a3b7586 JB |
2957 | if (adapter->flags2 & FLAG2_DMA_BURST) { |
2958 | u32 txdctl = er32(TXDCTL(0)); | |
6cf08d1c | 2959 | |
3a3b7586 JB |
2960 | txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH | |
2961 | E1000_TXDCTL_WTHRESH); | |
e921eb1a | 2962 | /* set up some performance related parameters to encourage the |
3a3b7586 JB |
2963 | * hardware to use the bus more efficiently in bursts, depends |
2964 | * on the tx_int_delay to be enabled, | |
8edc0e62 | 2965 | * wthresh = 1 ==> burst write is disabled to avoid Tx stalls |
3a3b7586 JB |
2966 | * hthresh = 1 ==> prefetch when one or more available |
2967 | * pthresh = 0x1f ==> prefetch if internal cache 31 or less | |
2968 | * BEWARE: this seems to work but should be considered first if | |
af667a29 | 2969 | * there are Tx hangs or other Tx related bugs |
3a3b7586 JB |
2970 | */ |
2971 | txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE; | |
2972 | ew32(TXDCTL(0), txdctl); | |
3a3b7586 | 2973 | } |
56032be7 BA |
2974 | /* erratum work around: set txdctl the same for both queues */ |
2975 | ew32(TXDCTL(1), er32(TXDCTL(0))); | |
3a3b7586 | 2976 | |
e7e834aa DE |
2977 | /* Program the Transmit Control Register */ |
2978 | tctl = er32(TCTL); | |
2979 | tctl &= ~E1000_TCTL_CT; | |
2980 | tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | | |
2981 | (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); | |
2982 | ||
bc7f75fa | 2983 | if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) { |
e9ec2c0f | 2984 | tarc = er32(TARC(0)); |
e921eb1a | 2985 | /* set the speed mode bit, we'll clear it if we're not at |
ad68076e BA |
2986 | * gigabit link later |
2987 | */ | |
18dd2392 | 2988 | #define SPEED_MODE_BIT BIT(21) |
bc7f75fa | 2989 | tarc |= SPEED_MODE_BIT; |
e9ec2c0f | 2990 | ew32(TARC(0), tarc); |
bc7f75fa AK |
2991 | } |
2992 | ||
2993 | /* errata: program both queues to unweighted RR */ | |
2994 | if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) { | |
e9ec2c0f | 2995 | tarc = er32(TARC(0)); |
bc7f75fa | 2996 | tarc |= 1; |
e9ec2c0f JK |
2997 | ew32(TARC(0), tarc); |
2998 | tarc = er32(TARC(1)); | |
bc7f75fa | 2999 | tarc |= 1; |
e9ec2c0f | 3000 | ew32(TARC(1), tarc); |
bc7f75fa AK |
3001 | } |
3002 | ||
bc7f75fa AK |
3003 | /* Setup Transmit Descriptor Settings for eop descriptor */ |
3004 | adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; | |
3005 | ||
3006 | /* only set IDE if we are delaying interrupts using the timers */ | |
3007 | if (adapter->tx_int_delay) | |
3008 | adapter->txd_cmd |= E1000_TXD_CMD_IDE; | |
3009 | ||
3010 | /* enable Report Status bit */ | |
3011 | adapter->txd_cmd |= E1000_TXD_CMD_RS; | |
3012 | ||
e7e834aa DE |
3013 | ew32(TCTL, tctl); |
3014 | ||
57cde763 | 3015 | hw->mac.ops.config_collision_dist(hw); |
79849ebc | 3016 | |
b10effb9 SN |
3017 | /* SPT and KBL Si errata workaround to avoid data corruption */ |
3018 | if (hw->mac.type == e1000_pch_spt) { | |
79849ebc DE |
3019 | u32 reg_val; |
3020 | ||
3021 | reg_val = er32(IOSFPC); | |
3022 | reg_val |= E1000_RCTL_RDMTS_HEX; | |
3023 | ew32(IOSFPC, reg_val); | |
3024 | ||
3025 | reg_val = er32(TARC(0)); | |
c0f4b163 SN |
3026 | /* SPT and KBL Si errata workaround to avoid Tx hang. |
3027 | * Dropping the number of outstanding requests from | |
3028 | * 3 to 2 in order to avoid a buffer overrun. | |
3029 | */ | |
3030 | reg_val &= ~E1000_TARC0_CB_MULTIQ_3_REQ; | |
3031 | reg_val |= E1000_TARC0_CB_MULTIQ_2_REQ; | |
79849ebc DE |
3032 | ew32(TARC(0), reg_val); |
3033 | } | |
bc7f75fa AK |
3034 | } |
3035 | ||
3036 | /** | |
3037 | * e1000_setup_rctl - configure the receive control registers | |
3038 | * @adapter: Board private structure | |
3039 | **/ | |
3040 | #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \ | |
3041 | (((S) & (PAGE_SIZE - 1)) ? 1 : 0)) | |
3042 | static void e1000_setup_rctl(struct e1000_adapter *adapter) | |
3043 | { | |
3044 | struct e1000_hw *hw = &adapter->hw; | |
3045 | u32 rctl, rfctl; | |
bc7f75fa AK |
3046 | u32 pages = 0; |
3047 | ||
b20a7744 DE |
3048 | /* Workaround Si errata on PCHx - configure jumbo frame flow. |
3049 | * If jumbo frames not set, program related MAC/PHY registers | |
3050 | * to h/w defaults | |
3051 | */ | |
3052 | if (hw->mac.type >= e1000_pch2lan) { | |
3053 | s32 ret_val; | |
3054 | ||
3055 | if (adapter->netdev->mtu > ETH_DATA_LEN) | |
3056 | ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true); | |
3057 | else | |
3058 | ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false); | |
3059 | ||
3060 | if (ret_val) | |
3061 | e_dbg("failed to enable|disable jumbo frame workaround mode\n"); | |
3062 | } | |
a1ce6473 | 3063 | |
bc7f75fa AK |
3064 | /* Program MC offset vector base */ |
3065 | rctl = er32(RCTL); | |
3066 | rctl &= ~(3 << E1000_RCTL_MO_SHIFT); | |
3067 | rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | | |
f0ff4398 BA |
3068 | E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF | |
3069 | (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT); | |
bc7f75fa AK |
3070 | |
3071 | /* Do not Store bad packets */ | |
3072 | rctl &= ~E1000_RCTL_SBP; | |
3073 | ||
3074 | /* Enable Long Packet receive */ | |
3075 | if (adapter->netdev->mtu <= ETH_DATA_LEN) | |
3076 | rctl &= ~E1000_RCTL_LPE; | |
3077 | else | |
3078 | rctl |= E1000_RCTL_LPE; | |
3079 | ||
eb7c3adb JK |
3080 | /* Some systems expect that the CRC is included in SMBUS traffic. The |
3081 | * hardware strips the CRC before sending to both SMBUS (BMC) and to | |
3082 | * host memory when this is enabled | |
3083 | */ | |
3084 | if (adapter->flags2 & FLAG2_CRC_STRIPPING) | |
3085 | rctl |= E1000_RCTL_SECRC; | |
5918bd88 | 3086 | |
a4f58f54 BA |
3087 | /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */ |
3088 | if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) { | |
3089 | u16 phy_data; | |
3090 | ||
3091 | e1e_rphy(hw, PHY_REG(770, 26), &phy_data); | |
3092 | phy_data &= 0xfff8; | |
18dd2392 | 3093 | phy_data |= BIT(2); |
a4f58f54 BA |
3094 | e1e_wphy(hw, PHY_REG(770, 26), phy_data); |
3095 | ||
3096 | e1e_rphy(hw, 22, &phy_data); | |
3097 | phy_data &= 0x0fff; | |
18dd2392 | 3098 | phy_data |= BIT(14); |
a4f58f54 BA |
3099 | e1e_wphy(hw, 0x10, 0x2823); |
3100 | e1e_wphy(hw, 0x11, 0x0003); | |
3101 | e1e_wphy(hw, 22, phy_data); | |
3102 | } | |
3103 | ||
bc7f75fa AK |
3104 | /* Setup buffer sizes */ |
3105 | rctl &= ~E1000_RCTL_SZ_4096; | |
3106 | rctl |= E1000_RCTL_BSEX; | |
3107 | switch (adapter->rx_buffer_len) { | |
bc7f75fa AK |
3108 | case 2048: |
3109 | default: | |
3110 | rctl |= E1000_RCTL_SZ_2048; | |
3111 | rctl &= ~E1000_RCTL_BSEX; | |
3112 | break; | |
3113 | case 4096: | |
3114 | rctl |= E1000_RCTL_SZ_4096; | |
3115 | break; | |
3116 | case 8192: | |
3117 | rctl |= E1000_RCTL_SZ_8192; | |
3118 | break; | |
3119 | case 16384: | |
3120 | rctl |= E1000_RCTL_SZ_16384; | |
3121 | break; | |
3122 | } | |
3123 | ||
5f450212 BA |
3124 | /* Enable Extended Status in all Receive Descriptors */ |
3125 | rfctl = er32(RFCTL); | |
3126 | rfctl |= E1000_RFCTL_EXTEN; | |
f6bd5577 | 3127 | ew32(RFCTL, rfctl); |
5f450212 | 3128 | |
e921eb1a | 3129 | /* 82571 and greater support packet-split where the protocol |
bc7f75fa AK |
3130 | * header is placed in skb->data and the packet data is |
3131 | * placed in pages hanging off of skb_shinfo(skb)->nr_frags. | |
3132 | * In the case of a non-split, skb->data is linearly filled, | |
3133 | * followed by the page buffers. Therefore, skb->data is | |
3134 | * sized to hold the largest protocol header. | |
3135 | * | |
3136 | * allocations using alloc_page take too long for regular MTU | |
3137 | * so only enable packet split for jumbo frames | |
3138 | * | |
3139 | * Using pages when the page size is greater than 16k wastes | |
3140 | * a lot of memory, since we allocate 3 pages at all times | |
3141 | * per packet. | |
3142 | */ | |
bc7f75fa | 3143 | pages = PAGE_USE_COUNT(adapter->netdev->mtu); |
79d4e908 | 3144 | if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE)) |
bc7f75fa | 3145 | adapter->rx_ps_pages = pages; |
97ac8cae BA |
3146 | else |
3147 | adapter->rx_ps_pages = 0; | |
bc7f75fa AK |
3148 | |
3149 | if (adapter->rx_ps_pages) { | |
90da0669 BA |
3150 | u32 psrctl = 0; |
3151 | ||
140a7480 AK |
3152 | /* Enable Packet split descriptors */ |
3153 | rctl |= E1000_RCTL_DTYP_PS; | |
bc7f75fa | 3154 | |
e5fe2541 | 3155 | psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT; |
bc7f75fa AK |
3156 | |
3157 | switch (adapter->rx_ps_pages) { | |
3158 | case 3: | |
e5fe2541 BA |
3159 | psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT; |
3160 | /* fall-through */ | |
bc7f75fa | 3161 | case 2: |
e5fe2541 BA |
3162 | psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT; |
3163 | /* fall-through */ | |
bc7f75fa | 3164 | case 1: |
e5fe2541 | 3165 | psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT; |
bc7f75fa AK |
3166 | break; |
3167 | } | |
3168 | ||
3169 | ew32(PSRCTL, psrctl); | |
3170 | } | |
3171 | ||
cf955e6c BG |
3172 | /* This is useful for sniffing bad packets. */ |
3173 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3174 | /* UPE and MPE will be handled by normal PROMISC logic | |
e921eb1a BA |
3175 | * in e1000e_set_rx_mode |
3176 | */ | |
e80bd1d1 BA |
3177 | rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ |
3178 | E1000_RCTL_BAM | /* RX All Bcast Pkts */ | |
3179 | E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ | |
cf955e6c | 3180 | |
e80bd1d1 BA |
3181 | rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ |
3182 | E1000_RCTL_DPF | /* Allow filtered pause */ | |
3183 | E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ | |
cf955e6c BG |
3184 | /* Do not mess with E1000_CTRL_VME, it affects transmit as well, |
3185 | * and that breaks VLANs. | |
3186 | */ | |
3187 | } | |
3188 | ||
bc7f75fa | 3189 | ew32(RCTL, rctl); |
318a94d6 | 3190 | /* just started the receive unit, no need to restart */ |
12d43f7d | 3191 | adapter->flags &= ~FLAG_RESTART_NOW; |
bc7f75fa AK |
3192 | } |
3193 | ||
3194 | /** | |
3195 | * e1000_configure_rx - Configure Receive Unit after Reset | |
3196 | * @adapter: board private structure | |
3197 | * | |
3198 | * Configure the Rx unit of the MAC after a reset. | |
3199 | **/ | |
3200 | static void e1000_configure_rx(struct e1000_adapter *adapter) | |
3201 | { | |
3202 | struct e1000_hw *hw = &adapter->hw; | |
3203 | struct e1000_ring *rx_ring = adapter->rx_ring; | |
3204 | u64 rdba; | |
3205 | u32 rdlen, rctl, rxcsum, ctrl_ext; | |
3206 | ||
3207 | if (adapter->rx_ps_pages) { | |
3208 | /* this is a 32 byte descriptor */ | |
3209 | rdlen = rx_ring->count * | |
af667a29 | 3210 | sizeof(union e1000_rx_desc_packet_split); |
bc7f75fa AK |
3211 | adapter->clean_rx = e1000_clean_rx_irq_ps; |
3212 | adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps; | |
97ac8cae | 3213 | } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) { |
5f450212 | 3214 | rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); |
97ac8cae BA |
3215 | adapter->clean_rx = e1000_clean_jumbo_rx_irq; |
3216 | adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers; | |
bc7f75fa | 3217 | } else { |
5f450212 | 3218 | rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended); |
bc7f75fa AK |
3219 | adapter->clean_rx = e1000_clean_rx_irq; |
3220 | adapter->alloc_rx_buf = e1000_alloc_rx_buffers; | |
3221 | } | |
3222 | ||
3223 | /* disable receives while setting up the descriptors */ | |
3224 | rctl = er32(RCTL); | |
7f99ae63 BA |
3225 | if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) |
3226 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | |
bc7f75fa | 3227 | e1e_flush(); |
1bba4386 | 3228 | usleep_range(10000, 20000); |
bc7f75fa | 3229 | |
3a3b7586 | 3230 | if (adapter->flags2 & FLAG2_DMA_BURST) { |
e921eb1a | 3231 | /* set the writeback threshold (only takes effect if the RDTR |
3a3b7586 | 3232 | * is set). set GRAN=1 and write back up to 0x4 worth, and |
af667a29 | 3233 | * enable prefetching of 0x20 Rx descriptors |
3a3b7586 JB |
3234 | * granularity = 01 |
3235 | * wthresh = 04, | |
3236 | * hthresh = 04, | |
3237 | * pthresh = 0x20 | |
3238 | */ | |
3239 | ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE); | |
3240 | ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE); | |
3a3b7586 JB |
3241 | } |
3242 | ||
bc7f75fa AK |
3243 | /* set the Receive Delay Timer Register */ |
3244 | ew32(RDTR, adapter->rx_int_delay); | |
3245 | ||
3246 | /* irq moderation */ | |
3247 | ew32(RADV, adapter->rx_abs_int_delay); | |
828bac87 | 3248 | if ((adapter->itr_setting != 0) && (adapter->itr != 0)) |
22a4cca2 | 3249 | e1000e_write_itr(adapter, adapter->itr); |
bc7f75fa AK |
3250 | |
3251 | ctrl_ext = er32(CTRL_EXT); | |
bc7f75fa AK |
3252 | /* Auto-Mask interrupts upon ICR access */ |
3253 | ctrl_ext |= E1000_CTRL_EXT_IAME; | |
3254 | ew32(IAM, 0xffffffff); | |
3255 | ew32(CTRL_EXT, ctrl_ext); | |
3256 | e1e_flush(); | |
3257 | ||
e921eb1a | 3258 | /* Setup the HW Rx Head and Tail Descriptor Pointers and |
ad68076e BA |
3259 | * the Base and Length of the Rx Descriptor Ring |
3260 | */ | |
bc7f75fa | 3261 | rdba = rx_ring->dma; |
1e36052e BA |
3262 | ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32))); |
3263 | ew32(RDBAH(0), (rdba >> 32)); | |
3264 | ew32(RDLEN(0), rdlen); | |
3265 | ew32(RDH(0), 0); | |
3266 | ew32(RDT(0), 0); | |
3267 | rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0); | |
3268 | rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0); | |
bc7f75fa | 3269 | |
0845d45e JJB |
3270 | writel(0, rx_ring->head); |
3271 | if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) | |
3272 | e1000e_update_rdt_wa(rx_ring, 0); | |
3273 | else | |
3274 | writel(0, rx_ring->tail); | |
3275 | ||
bc7f75fa AK |
3276 | /* Enable Receive Checksum Offload for TCP and UDP */ |
3277 | rxcsum = er32(RXCSUM); | |
2e1706f2 | 3278 | if (adapter->netdev->features & NETIF_F_RXCSUM) |
bc7f75fa | 3279 | rxcsum |= E1000_RXCSUM_TUOFL; |
2e1706f2 | 3280 | else |
bc7f75fa | 3281 | rxcsum &= ~E1000_RXCSUM_TUOFL; |
bc7f75fa AK |
3282 | ew32(RXCSUM, rxcsum); |
3283 | ||
3e35d991 BA |
3284 | /* With jumbo frames, excessive C-state transition latencies result |
3285 | * in dropped transactions. | |
3286 | */ | |
3287 | if (adapter->netdev->mtu > ETH_DATA_LEN) { | |
3288 | u32 lat = | |
3289 | ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 - | |
3290 | adapter->max_frame_size) * 8 / 1000; | |
3291 | ||
3292 | if (adapter->flags & FLAG_IS_ICH) { | |
53ec5498 | 3293 | u32 rxdctl = er32(RXDCTL(0)); |
6cf08d1c | 3294 | |
b701cacd | 3295 | ew32(RXDCTL(0), rxdctl | 0x3 | BIT(8)); |
53ec5498 | 3296 | } |
3e35d991 | 3297 | |
8299b006 MT |
3298 | dev_info(&adapter->pdev->dev, |
3299 | "Some CPU C-states have been disabled in order to enable jumbo frames\n"); | |
e2c65448 | 3300 | pm_qos_update_request(&adapter->pm_qos_req, lat); |
3e35d991 | 3301 | } else { |
e2c65448 | 3302 | pm_qos_update_request(&adapter->pm_qos_req, |
3e35d991 | 3303 | PM_QOS_DEFAULT_VALUE); |
97ac8cae | 3304 | } |
bc7f75fa AK |
3305 | |
3306 | /* Enable Receives */ | |
3307 | ew32(RCTL, rctl); | |
3308 | } | |
3309 | ||
3310 | /** | |
ef9b965a JB |
3311 | * e1000e_write_mc_addr_list - write multicast addresses to MTA |
3312 | * @netdev: network interface device structure | |
bc7f75fa | 3313 | * |
ef9b965a JB |
3314 | * Writes multicast address list to the MTA hash table. |
3315 | * Returns: -ENOMEM on failure | |
3316 | * 0 on no addresses written | |
3317 | * X on writing X addresses to MTA | |
3318 | */ | |
3319 | static int e1000e_write_mc_addr_list(struct net_device *netdev) | |
3320 | { | |
3321 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
3322 | struct e1000_hw *hw = &adapter->hw; | |
3323 | struct netdev_hw_addr *ha; | |
3324 | u8 *mta_list; | |
3325 | int i; | |
3326 | ||
3327 | if (netdev_mc_empty(netdev)) { | |
3328 | /* nothing to program, so clear mc list */ | |
3329 | hw->mac.ops.update_mc_addr_list(hw, NULL, 0); | |
3330 | return 0; | |
3331 | } | |
3332 | ||
3333 | mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC); | |
3334 | if (!mta_list) | |
3335 | return -ENOMEM; | |
3336 | ||
3337 | /* update_mc_addr_list expects a packed array of only addresses. */ | |
3338 | i = 0; | |
3339 | netdev_for_each_mc_addr(ha, netdev) | |
f0ff4398 | 3340 | memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); |
ef9b965a JB |
3341 | |
3342 | hw->mac.ops.update_mc_addr_list(hw, mta_list, i); | |
3343 | kfree(mta_list); | |
3344 | ||
3345 | return netdev_mc_count(netdev); | |
3346 | } | |
3347 | ||
3348 | /** | |
3349 | * e1000e_write_uc_addr_list - write unicast addresses to RAR table | |
3350 | * @netdev: network interface device structure | |
bc7f75fa | 3351 | * |
ef9b965a JB |
3352 | * Writes unicast address list to the RAR table. |
3353 | * Returns: -ENOMEM on failure/insufficient address space | |
3354 | * 0 on no addresses written | |
3355 | * X on writing X addresses to the RAR table | |
bc7f75fa | 3356 | **/ |
ef9b965a | 3357 | static int e1000e_write_uc_addr_list(struct net_device *netdev) |
bc7f75fa | 3358 | { |
ef9b965a JB |
3359 | struct e1000_adapter *adapter = netdev_priv(netdev); |
3360 | struct e1000_hw *hw = &adapter->hw; | |
b3e5bf1f | 3361 | unsigned int rar_entries; |
ef9b965a JB |
3362 | int count = 0; |
3363 | ||
b3e5bf1f DE |
3364 | rar_entries = hw->mac.ops.rar_get_count(hw); |
3365 | ||
ef9b965a JB |
3366 | /* save a rar entry for our hardware address */ |
3367 | rar_entries--; | |
3368 | ||
3369 | /* save a rar entry for the LAA workaround */ | |
3370 | if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) | |
3371 | rar_entries--; | |
3372 | ||
3373 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3374 | if (netdev_uc_count(netdev) > rar_entries) | |
3375 | return -ENOMEM; | |
3376 | ||
3377 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3378 | struct netdev_hw_addr *ha; | |
3379 | ||
e921eb1a | 3380 | /* write the addresses in reverse order to avoid write |
ef9b965a JB |
3381 | * combining |
3382 | */ | |
3383 | netdev_for_each_uc_addr(ha, netdev) { | |
847042a6 | 3384 | int ret_val; |
b3e5bf1f | 3385 | |
ef9b965a JB |
3386 | if (!rar_entries) |
3387 | break; | |
847042a6 BW |
3388 | ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--); |
3389 | if (ret_val < 0) | |
b3e5bf1f | 3390 | return -ENOMEM; |
ef9b965a JB |
3391 | count++; |
3392 | } | |
3393 | } | |
3394 | ||
3395 | /* zero out the remaining RAR entries not used above */ | |
3396 | for (; rar_entries > 0; rar_entries--) { | |
3397 | ew32(RAH(rar_entries), 0); | |
3398 | ew32(RAL(rar_entries), 0); | |
3399 | } | |
3400 | e1e_flush(); | |
3401 | ||
3402 | return count; | |
bc7f75fa AK |
3403 | } |
3404 | ||
3405 | /** | |
ef9b965a | 3406 | * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set |
bc7f75fa AK |
3407 | * @netdev: network interface device structure |
3408 | * | |
ef9b965a JB |
3409 | * The ndo_set_rx_mode entry point is called whenever the unicast or multicast |
3410 | * address list or the network interface flags are updated. This routine is | |
3411 | * responsible for configuring the hardware for proper unicast, multicast, | |
bc7f75fa AK |
3412 | * promiscuous mode, and all-multi behavior. |
3413 | **/ | |
ef9b965a | 3414 | static void e1000e_set_rx_mode(struct net_device *netdev) |
bc7f75fa AK |
3415 | { |
3416 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
3417 | struct e1000_hw *hw = &adapter->hw; | |
bc7f75fa | 3418 | u32 rctl; |
bc7f75fa | 3419 | |
63eb48f1 DE |
3420 | if (pm_runtime_suspended(netdev->dev.parent)) |
3421 | return; | |
3422 | ||
bc7f75fa | 3423 | /* Check for Promiscuous and All Multicast modes */ |
bc7f75fa AK |
3424 | rctl = er32(RCTL); |
3425 | ||
ef9b965a JB |
3426 | /* clear the affected bits */ |
3427 | rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE); | |
3428 | ||
bc7f75fa AK |
3429 | if (netdev->flags & IFF_PROMISC) { |
3430 | rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); | |
86d70e53 JK |
3431 | /* Do not hardware filter VLANs in promisc mode */ |
3432 | e1000e_vlan_filter_disable(adapter); | |
bc7f75fa | 3433 | } else { |
ef9b965a | 3434 | int count; |
3d3a1676 | 3435 | |
746b9f02 PM |
3436 | if (netdev->flags & IFF_ALLMULTI) { |
3437 | rctl |= E1000_RCTL_MPE; | |
746b9f02 | 3438 | } else { |
e921eb1a | 3439 | /* Write addresses to the MTA, if the attempt fails |
ef9b965a JB |
3440 | * then we should just turn on promiscuous mode so |
3441 | * that we can at least receive multicast traffic | |
3442 | */ | |
3443 | count = e1000e_write_mc_addr_list(netdev); | |
3444 | if (count < 0) | |
3445 | rctl |= E1000_RCTL_MPE; | |
746b9f02 | 3446 | } |
86d70e53 | 3447 | e1000e_vlan_filter_enable(adapter); |
e921eb1a | 3448 | /* Write addresses to available RAR registers, if there is not |
ef9b965a JB |
3449 | * sufficient space to store all the addresses then enable |
3450 | * unicast promiscuous mode | |
bc7f75fa | 3451 | */ |
ef9b965a JB |
3452 | count = e1000e_write_uc_addr_list(netdev); |
3453 | if (count < 0) | |
3454 | rctl |= E1000_RCTL_UPE; | |
bc7f75fa | 3455 | } |
86d70e53 | 3456 | |
ef9b965a JB |
3457 | ew32(RCTL, rctl); |
3458 | ||
83808641 | 3459 | if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) |
86d70e53 JK |
3460 | e1000e_vlan_strip_enable(adapter); |
3461 | else | |
3462 | e1000e_vlan_strip_disable(adapter); | |
bc7f75fa AK |
3463 | } |
3464 | ||
70495a50 BA |
3465 | static void e1000e_setup_rss_hash(struct e1000_adapter *adapter) |
3466 | { | |
3467 | struct e1000_hw *hw = &adapter->hw; | |
3468 | u32 mrqc, rxcsum; | |
5c8d19da | 3469 | u32 rss_key[10]; |
70495a50 | 3470 | int i; |
70495a50 | 3471 | |
5c8d19da | 3472 | netdev_rss_key_fill(rss_key, sizeof(rss_key)); |
70495a50 | 3473 | for (i = 0; i < 10; i++) |
5c8d19da | 3474 | ew32(RSSRK(i), rss_key[i]); |
70495a50 BA |
3475 | |
3476 | /* Direct all traffic to queue 0 */ | |
3477 | for (i = 0; i < 32; i++) | |
3478 | ew32(RETA(i), 0); | |
3479 | ||
e921eb1a | 3480 | /* Disable raw packet checksumming so that RSS hash is placed in |
70495a50 BA |
3481 | * descriptor on writeback. |
3482 | */ | |
3483 | rxcsum = er32(RXCSUM); | |
3484 | rxcsum |= E1000_RXCSUM_PCSD; | |
3485 | ||
3486 | ew32(RXCSUM, rxcsum); | |
3487 | ||
3488 | mrqc = (E1000_MRQC_RSS_FIELD_IPV4 | | |
3489 | E1000_MRQC_RSS_FIELD_IPV4_TCP | | |
3490 | E1000_MRQC_RSS_FIELD_IPV6 | | |
3491 | E1000_MRQC_RSS_FIELD_IPV6_TCP | | |
3492 | E1000_MRQC_RSS_FIELD_IPV6_TCP_EX); | |
3493 | ||
3494 | ew32(MRQC, mrqc); | |
3495 | } | |
3496 | ||
b67e1913 BA |
3497 | /** |
3498 | * e1000e_get_base_timinca - get default SYSTIM time increment attributes | |
3499 | * @adapter: board private structure | |
3500 | * @timinca: pointer to returned time increment attributes | |
3501 | * | |
3502 | * Get attributes for incrementing the System Time Register SYSTIML/H at | |
3503 | * the default base frequency, and set the cyclecounter shift value. | |
3504 | **/ | |
d89777bf | 3505 | s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca) |
b67e1913 BA |
3506 | { |
3507 | struct e1000_hw *hw = &adapter->hw; | |
3508 | u32 incvalue, incperiod, shift; | |
3509 | ||
79849ebc DE |
3510 | /* Make sure clock is enabled on I217/I218/I219 before checking |
3511 | * the frequency | |
3512 | */ | |
c8744f44 | 3513 | if ((hw->mac.type >= e1000_pch_lpt) && |
b67e1913 BA |
3514 | !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) && |
3515 | !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) { | |
3516 | u32 fextnvm7 = er32(FEXTNVM7); | |
3517 | ||
18dd2392 JK |
3518 | if (!(fextnvm7 & BIT(0))) { |
3519 | ew32(FEXTNVM7, fextnvm7 | BIT(0)); | |
b67e1913 BA |
3520 | e1e_flush(); |
3521 | } | |
3522 | } | |
3523 | ||
3524 | switch (hw->mac.type) { | |
3525 | case e1000_pch2lan: | |
5313eecc | 3526 | /* Stable 96MHz frequency */ |
68fe1d5d SN |
3527 | incperiod = INCPERIOD_96MHZ; |
3528 | incvalue = INCVALUE_96MHZ; | |
3529 | shift = INCVALUE_SHIFT_96MHZ; | |
3530 | adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; | |
5313eecc | 3531 | break; |
b67e1913 | 3532 | case e1000_pch_lpt: |
83129b37 | 3533 | if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { |
b67e1913 | 3534 | /* Stable 96MHz frequency */ |
68fe1d5d SN |
3535 | incperiod = INCPERIOD_96MHZ; |
3536 | incvalue = INCVALUE_96MHZ; | |
3537 | shift = INCVALUE_SHIFT_96MHZ; | |
3538 | adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHZ; | |
83129b37 YL |
3539 | } else { |
3540 | /* Stable 25MHz frequency */ | |
68fe1d5d SN |
3541 | incperiod = INCPERIOD_25MHZ; |
3542 | incvalue = INCVALUE_25MHZ; | |
3543 | shift = INCVALUE_SHIFT_25MHZ; | |
83129b37 YL |
3544 | adapter->cc.shift = shift; |
3545 | } | |
3546 | break; | |
3547 | case e1000_pch_spt: | |
3548 | if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { | |
3549 | /* Stable 24MHz frequency */ | |
68fe1d5d SN |
3550 | incperiod = INCPERIOD_24MHZ; |
3551 | incvalue = INCVALUE_24MHZ; | |
3552 | shift = INCVALUE_SHIFT_24MHZ; | |
83129b37 | 3553 | adapter->cc.shift = shift; |
b67e1913 BA |
3554 | break; |
3555 | } | |
83129b37 | 3556 | return -EINVAL; |
68fe1d5d SN |
3557 | case e1000_pch_cnp: |
3558 | if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) { | |
3559 | /* Stable 24MHz frequency */ | |
3560 | incperiod = INCPERIOD_24MHZ; | |
3561 | incvalue = INCVALUE_24MHZ; | |
3562 | shift = INCVALUE_SHIFT_24MHZ; | |
3563 | adapter->cc.shift = shift; | |
3564 | } else { | |
3565 | /* Stable 38400KHz frequency */ | |
3566 | incperiod = INCPERIOD_38400KHZ; | |
3567 | incvalue = INCVALUE_38400KHZ; | |
3568 | shift = INCVALUE_SHIFT_38400KHZ; | |
3569 | adapter->cc.shift = shift; | |
3570 | } | |
3571 | break; | |
b67e1913 BA |
3572 | case e1000_82574: |
3573 | case e1000_82583: | |
3574 | /* Stable 25MHz frequency */ | |
68fe1d5d SN |
3575 | incperiod = INCPERIOD_25MHZ; |
3576 | incvalue = INCVALUE_25MHZ; | |
3577 | shift = INCVALUE_SHIFT_25MHZ; | |
b67e1913 BA |
3578 | adapter->cc.shift = shift; |
3579 | break; | |
3580 | default: | |
3581 | return -EINVAL; | |
3582 | } | |
3583 | ||
3584 | *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) | | |
3585 | ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK)); | |
3586 | ||
3587 | return 0; | |
3588 | } | |
3589 | ||
3590 | /** | |
3591 | * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable | |
3592 | * @adapter: board private structure | |
3593 | * | |
3594 | * Outgoing time stamping can be enabled and disabled. Play nice and | |
3595 | * disable it when requested, although it shouldn't cause any overhead | |
3596 | * when no packet needs it. At most one packet in the queue may be | |
3597 | * marked for time stamping, otherwise it would be impossible to tell | |
3598 | * for sure to which packet the hardware time stamp belongs. | |
3599 | * | |
3600 | * Incoming time stamping has to be configured via the hardware filters. | |
3601 | * Not all combinations are supported, in particular event type has to be | |
3602 | * specified. Matching the kind of event packet is not supported, with the | |
3603 | * exception of "all V2 events regardless of level 2 or 4". | |
3604 | **/ | |
62d7e3a2 BH |
3605 | static int e1000e_config_hwtstamp(struct e1000_adapter *adapter, |
3606 | struct hwtstamp_config *config) | |
b67e1913 BA |
3607 | { |
3608 | struct e1000_hw *hw = &adapter->hw; | |
b67e1913 BA |
3609 | u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; |
3610 | u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; | |
d89777bf BA |
3611 | u32 rxmtrl = 0; |
3612 | u16 rxudp = 0; | |
3613 | bool is_l4 = false; | |
3614 | bool is_l2 = false; | |
b67e1913 | 3615 | u32 regval; |
b67e1913 BA |
3616 | |
3617 | if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) | |
3618 | return -EINVAL; | |
3619 | ||
3620 | /* flags reserved for future extensions - must be zero */ | |
3621 | if (config->flags) | |
3622 | return -EINVAL; | |
3623 | ||
3624 | switch (config->tx_type) { | |
3625 | case HWTSTAMP_TX_OFF: | |
3626 | tsync_tx_ctl = 0; | |
3627 | break; | |
3628 | case HWTSTAMP_TX_ON: | |
3629 | break; | |
3630 | default: | |
3631 | return -ERANGE; | |
3632 | } | |
3633 | ||
3634 | switch (config->rx_filter) { | |
3635 | case HWTSTAMP_FILTER_NONE: | |
3636 | tsync_rx_ctl = 0; | |
3637 | break; | |
d89777bf BA |
3638 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
3639 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
3640 | rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE; | |
3641 | is_l4 = true; | |
3642 | break; | |
3643 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
3644 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; | |
3645 | rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE; | |
3646 | is_l4 = true; | |
3647 | break; | |
3648 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
3649 | /* Also time stamps V2 L2 Path Delay Request/Response */ | |
3650 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; | |
3651 | rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; | |
3652 | is_l2 = true; | |
3653 | break; | |
3654 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
3655 | /* Also time stamps V2 L2 Path Delay Request/Response. */ | |
3656 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2; | |
3657 | rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; | |
3658 | is_l2 = true; | |
3659 | break; | |
3660 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
3661 | /* Hardware cannot filter just V2 L4 Sync messages; | |
3662 | * fall-through to V2 (both L2 and L4) Sync. | |
3663 | */ | |
3664 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
3665 | /* Also time stamps V2 Path Delay Request/Response. */ | |
3666 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; | |
3667 | rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE; | |
3668 | is_l2 = true; | |
3669 | is_l4 = true; | |
3670 | break; | |
3671 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
3672 | /* Hardware cannot filter just V2 L4 Delay Request messages; | |
3673 | * fall-through to V2 (both L2 and L4) Delay Request. | |
3674 | */ | |
3675 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
3676 | /* Also time stamps V2 Path Delay Request/Response. */ | |
3677 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2; | |
3678 | rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE; | |
3679 | is_l2 = true; | |
3680 | is_l4 = true; | |
3681 | break; | |
3682 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
3683 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
3684 | /* Hardware cannot filter just V2 L4 or L2 Event messages; | |
3685 | * fall-through to all V2 (both L2 and L4) Events. | |
3686 | */ | |
3687 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
3688 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; | |
3689 | config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; | |
3690 | is_l2 = true; | |
3691 | is_l4 = true; | |
3692 | break; | |
3693 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
3694 | /* For V1, the hardware can only filter Sync messages or | |
3695 | * Delay Request messages but not both so fall-through to | |
3696 | * time stamp all packets. | |
3697 | */ | |
e3412575 | 3698 | case HWTSTAMP_FILTER_NTP_ALL: |
b67e1913 | 3699 | case HWTSTAMP_FILTER_ALL: |
d89777bf BA |
3700 | is_l2 = true; |
3701 | is_l4 = true; | |
b67e1913 BA |
3702 | tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; |
3703 | config->rx_filter = HWTSTAMP_FILTER_ALL; | |
3704 | break; | |
3705 | default: | |
3706 | return -ERANGE; | |
3707 | } | |
3708 | ||
62d7e3a2 BH |
3709 | adapter->hwtstamp_config = *config; |
3710 | ||
b67e1913 BA |
3711 | /* enable/disable Tx h/w time stamping */ |
3712 | regval = er32(TSYNCTXCTL); | |
3713 | regval &= ~E1000_TSYNCTXCTL_ENABLED; | |
3714 | regval |= tsync_tx_ctl; | |
3715 | ew32(TSYNCTXCTL, regval); | |
3716 | if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) != | |
3717 | (regval & E1000_TSYNCTXCTL_ENABLED)) { | |
3718 | e_err("Timesync Tx Control register not set as expected\n"); | |
3719 | return -EAGAIN; | |
3720 | } | |
3721 | ||
3722 | /* enable/disable Rx h/w time stamping */ | |
3723 | regval = er32(TSYNCRXCTL); | |
3724 | regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); | |
3725 | regval |= tsync_rx_ctl; | |
3726 | ew32(TSYNCRXCTL, regval); | |
3727 | if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED | | |
3728 | E1000_TSYNCRXCTL_TYPE_MASK)) != | |
3729 | (regval & (E1000_TSYNCRXCTL_ENABLED | | |
3730 | E1000_TSYNCRXCTL_TYPE_MASK))) { | |
3731 | e_err("Timesync Rx Control register not set as expected\n"); | |
3732 | return -EAGAIN; | |
3733 | } | |
3734 | ||
d89777bf BA |
3735 | /* L2: define ethertype filter for time stamped packets */ |
3736 | if (is_l2) | |
3737 | rxmtrl |= ETH_P_1588; | |
3738 | ||
3739 | /* define which PTP packets get time stamped */ | |
3740 | ew32(RXMTRL, rxmtrl); | |
3741 | ||
3742 | /* Filter by destination port */ | |
3743 | if (is_l4) { | |
3744 | rxudp = PTP_EV_PORT; | |
3745 | cpu_to_be16s(&rxudp); | |
3746 | } | |
3747 | ew32(RXUDP, rxudp); | |
3748 | ||
3749 | e1e_flush(); | |
3750 | ||
b67e1913 | 3751 | /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */ |
70806a7f BA |
3752 | er32(RXSTMPH); |
3753 | er32(TXSTMPH); | |
b67e1913 | 3754 | |
b67e1913 BA |
3755 | return 0; |
3756 | } | |
3757 | ||
bc7f75fa | 3758 | /** |
ad68076e | 3759 | * e1000_configure - configure the hardware for Rx and Tx |
bc7f75fa AK |
3760 | * @adapter: private board structure |
3761 | **/ | |
3762 | static void e1000_configure(struct e1000_adapter *adapter) | |
3763 | { | |
55aa6985 BA |
3764 | struct e1000_ring *rx_ring = adapter->rx_ring; |
3765 | ||
ef9b965a | 3766 | e1000e_set_rx_mode(adapter->netdev); |
bc7f75fa AK |
3767 | |
3768 | e1000_restore_vlan(adapter); | |
cd791618 | 3769 | e1000_init_manageability_pt(adapter); |
bc7f75fa AK |
3770 | |
3771 | e1000_configure_tx(adapter); | |
70495a50 BA |
3772 | |
3773 | if (adapter->netdev->features & NETIF_F_RXHASH) | |
3774 | e1000e_setup_rss_hash(adapter); | |
bc7f75fa AK |
3775 | e1000_setup_rctl(adapter); |
3776 | e1000_configure_rx(adapter); | |
55aa6985 | 3777 | adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL); |
bc7f75fa AK |
3778 | } |
3779 | ||
3780 | /** | |
3781 | * e1000e_power_up_phy - restore link in case the phy was powered down | |
3782 | * @adapter: address of board private structure | |
3783 | * | |
3784 | * The phy may be powered down to save power and turn off link when the | |
3785 | * driver is unloaded and wake on lan is not enabled (among others) | |
3786 | * *** this routine MUST be followed by a call to e1000e_reset *** | |
3787 | **/ | |
3788 | void e1000e_power_up_phy(struct e1000_adapter *adapter) | |
3789 | { | |
17f208de BA |
3790 | if (adapter->hw.phy.ops.power_up) |
3791 | adapter->hw.phy.ops.power_up(&adapter->hw); | |
bc7f75fa AK |
3792 | |
3793 | adapter->hw.mac.ops.setup_link(&adapter->hw); | |
3794 | } | |
3795 | ||
3796 | /** | |
3797 | * e1000_power_down_phy - Power down the PHY | |
3798 | * | |
17f208de BA |
3799 | * Power down the PHY so no link is implied when interface is down. |
3800 | * The PHY cannot be powered down if management or WoL is active. | |
bc7f75fa AK |
3801 | */ |
3802 | static void e1000_power_down_phy(struct e1000_adapter *adapter) | |
3803 | { | |
17f208de BA |
3804 | if (adapter->hw.phy.ops.power_down) |
3805 | adapter->hw.phy.ops.power_down(&adapter->hw); | |
bc7f75fa AK |
3806 | } |
3807 | ||
ad851fbb YL |
3808 | /** |
3809 | * e1000_flush_tx_ring - remove all descriptors from the tx_ring | |
3810 | * | |
3811 | * We want to clear all pending descriptors from the TX ring. | |
3812 | * zeroing happens when the HW reads the regs. We assign the ring itself as | |
3813 | * the data of the next descriptor. We don't care about the data we are about | |
3814 | * to reset the HW. | |
3815 | */ | |
3816 | static void e1000_flush_tx_ring(struct e1000_adapter *adapter) | |
3817 | { | |
3818 | struct e1000_hw *hw = &adapter->hw; | |
3819 | struct e1000_ring *tx_ring = adapter->tx_ring; | |
3820 | struct e1000_tx_desc *tx_desc = NULL; | |
3821 | u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS; | |
3822 | u16 size = 512; | |
3823 | ||
3824 | tctl = er32(TCTL); | |
3825 | ew32(TCTL, tctl | E1000_TCTL_EN); | |
3826 | tdt = er32(TDT(0)); | |
3827 | BUG_ON(tdt != tx_ring->next_to_use); | |
3828 | tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use); | |
3829 | tx_desc->buffer_addr = tx_ring->dma; | |
3830 | ||
3831 | tx_desc->lower.data = cpu_to_le32(txd_lower | size); | |
3832 | tx_desc->upper.data = 0; | |
3833 | /* flush descriptors to memory before notifying the HW */ | |
3834 | wmb(); | |
3835 | tx_ring->next_to_use++; | |
3836 | if (tx_ring->next_to_use == tx_ring->count) | |
3837 | tx_ring->next_to_use = 0; | |
3838 | ew32(TDT(0), tx_ring->next_to_use); | |
3839 | mmiowb(); | |
3840 | usleep_range(200, 250); | |
3841 | } | |
3842 | ||
3843 | /** | |
3844 | * e1000_flush_rx_ring - remove all descriptors from the rx_ring | |
3845 | * | |
3846 | * Mark all descriptors in the RX ring as consumed and disable the rx ring | |
3847 | */ | |
3848 | static void e1000_flush_rx_ring(struct e1000_adapter *adapter) | |
3849 | { | |
3850 | u32 rctl, rxdctl; | |
3851 | struct e1000_hw *hw = &adapter->hw; | |
3852 | ||
3853 | rctl = er32(RCTL); | |
3854 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | |
3855 | e1e_flush(); | |
3856 | usleep_range(100, 150); | |
3857 | ||
3858 | rxdctl = er32(RXDCTL(0)); | |
3859 | /* zero the lower 14 bits (prefetch and host thresholds) */ | |
3860 | rxdctl &= 0xffffc000; | |
3861 | ||
3862 | /* update thresholds: prefetch threshold to 31, host threshold to 1 | |
3863 | * and make sure the granularity is "descriptors" and not "cache lines" | |
3864 | */ | |
18dd2392 | 3865 | rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC); |
ad851fbb YL |
3866 | |
3867 | ew32(RXDCTL(0), rxdctl); | |
3868 | /* momentarily enable the RX ring for the changes to take effect */ | |
3869 | ew32(RCTL, rctl | E1000_RCTL_EN); | |
3870 | e1e_flush(); | |
3871 | usleep_range(100, 150); | |
3872 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | |
3873 | } | |
3874 | ||
3875 | /** | |
3876 | * e1000_flush_desc_rings - remove all descriptors from the descriptor rings | |
3877 | * | |
3878 | * In i219, the descriptor rings must be emptied before resetting the HW | |
3879 | * or before changing the device state to D3 during runtime (runtime PM). | |
3880 | * | |
3881 | * Failure to do this will cause the HW to enter a unit hang state which can | |
3882 | * only be released by PCI reset on the device | |
3883 | * | |
3884 | */ | |
3885 | ||
3886 | static void e1000_flush_desc_rings(struct e1000_adapter *adapter) | |
3887 | { | |
ff917429 | 3888 | u16 hang_state; |
ad851fbb YL |
3889 | u32 fext_nvm11, tdlen; |
3890 | struct e1000_hw *hw = &adapter->hw; | |
3891 | ||
3892 | /* First, disable MULR fix in FEXTNVM11 */ | |
3893 | fext_nvm11 = er32(FEXTNVM11); | |
3894 | fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX; | |
3895 | ew32(FEXTNVM11, fext_nvm11); | |
3896 | /* do nothing if we're not in faulty state, or if the queue is empty */ | |
3897 | tdlen = er32(TDLEN(0)); | |
ff917429 YL |
3898 | pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, |
3899 | &hang_state); | |
3900 | if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen) | |
ad851fbb YL |
3901 | return; |
3902 | e1000_flush_tx_ring(adapter); | |
3903 | /* recheck, maybe the fault is caused by the rx ring */ | |
ff917429 YL |
3904 | pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS, |
3905 | &hang_state); | |
3906 | if (hang_state & FLUSH_DESC_REQUIRED) | |
ad851fbb YL |
3907 | e1000_flush_rx_ring(adapter); |
3908 | } | |
3909 | ||
aa524b66 JK |
3910 | /** |
3911 | * e1000e_systim_reset - reset the timesync registers after a hardware reset | |
3912 | * @adapter: board private structure | |
3913 | * | |
3914 | * When the MAC is reset, all hardware bits for timesync will be reset to the | |
3915 | * default values. This function will restore the settings last in place. | |
3916 | * Since the clock SYSTIME registers are reset, we will simply restore the | |
3917 | * cyclecounter to the kernel real clock time. | |
3918 | **/ | |
3919 | static void e1000e_systim_reset(struct e1000_adapter *adapter) | |
3920 | { | |
3921 | struct ptp_clock_info *info = &adapter->ptp_clock_info; | |
3922 | struct e1000_hw *hw = &adapter->hw; | |
3923 | unsigned long flags; | |
3924 | u32 timinca; | |
3925 | s32 ret_val; | |
3926 | ||
3927 | if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP)) | |
3928 | return; | |
3929 | ||
3930 | if (info->adjfreq) { | |
3931 | /* restore the previous ptp frequency delta */ | |
3932 | ret_val = info->adjfreq(info, adapter->ptp_delta); | |
3933 | } else { | |
3934 | /* set the default base frequency if no adjustment possible */ | |
3935 | ret_val = e1000e_get_base_timinca(adapter, &timinca); | |
3936 | if (!ret_val) | |
3937 | ew32(TIMINCA, timinca); | |
3938 | } | |
3939 | ||
3940 | if (ret_val) { | |
3941 | dev_warn(&adapter->pdev->dev, | |
3942 | "Failed to restore TIMINCA clock rate delta: %d\n", | |
3943 | ret_val); | |
3944 | return; | |
3945 | } | |
3946 | ||
3947 | /* reset the systim ns time counter */ | |
3948 | spin_lock_irqsave(&adapter->systim_lock, flags); | |
3949 | timecounter_init(&adapter->tc, &adapter->cc, | |
3950 | ktime_to_ns(ktime_get_real())); | |
3951 | spin_unlock_irqrestore(&adapter->systim_lock, flags); | |
3952 | ||
3953 | /* restore the previous hwtstamp configuration settings */ | |
3954 | e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config); | |
3955 | } | |
3956 | ||
bc7f75fa AK |
3957 | /** |
3958 | * e1000e_reset - bring the hardware into a known good state | |
3959 | * | |
3960 | * This function boots the hardware and enables some settings that | |
3961 | * require a configuration cycle of the hardware - those cannot be | |
3962 | * set/changed during runtime. After reset the device needs to be | |
ad68076e | 3963 | * properly configured for Rx, Tx etc. |
bc7f75fa AK |
3964 | */ |
3965 | void e1000e_reset(struct e1000_adapter *adapter) | |
3966 | { | |
3967 | struct e1000_mac_info *mac = &adapter->hw.mac; | |
318a94d6 | 3968 | struct e1000_fc_info *fc = &adapter->hw.fc; |
bc7f75fa AK |
3969 | struct e1000_hw *hw = &adapter->hw; |
3970 | u32 tx_space, min_tx_space, min_rx_space; | |
318a94d6 | 3971 | u32 pba = adapter->pba; |
bc7f75fa AK |
3972 | u16 hwm; |
3973 | ||
ad68076e | 3974 | /* reset Packet Buffer Allocation to default */ |
318a94d6 | 3975 | ew32(PBA, pba); |
df762464 | 3976 | |
8084b86d | 3977 | if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) { |
e921eb1a | 3978 | /* To maintain wire speed transmits, the Tx FIFO should be |
bc7f75fa AK |
3979 | * large enough to accommodate two full transmit packets, |
3980 | * rounded up to the next 1KB and expressed in KB. Likewise, | |
3981 | * the Rx FIFO should be large enough to accommodate at least | |
3982 | * one full receive packet and is similarly rounded up and | |
ad68076e BA |
3983 | * expressed in KB. |
3984 | */ | |
df762464 | 3985 | pba = er32(PBA); |
bc7f75fa | 3986 | /* upper 16 bits has Tx packet buffer allocation size in KB */ |
df762464 | 3987 | tx_space = pba >> 16; |
bc7f75fa | 3988 | /* lower 16 bits has Rx packet buffer allocation size in KB */ |
df762464 | 3989 | pba &= 0xffff; |
e921eb1a | 3990 | /* the Tx fifo also stores 16 bytes of information about the Tx |
ad68076e | 3991 | * but don't include ethernet FCS because hardware appends it |
318a94d6 JK |
3992 | */ |
3993 | min_tx_space = (adapter->max_frame_size + | |
e5fe2541 | 3994 | sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2; |
bc7f75fa AK |
3995 | min_tx_space = ALIGN(min_tx_space, 1024); |
3996 | min_tx_space >>= 10; | |
3997 | /* software strips receive CRC, so leave room for it */ | |
318a94d6 | 3998 | min_rx_space = adapter->max_frame_size; |
bc7f75fa AK |
3999 | min_rx_space = ALIGN(min_rx_space, 1024); |
4000 | min_rx_space >>= 10; | |
4001 | ||
e921eb1a | 4002 | /* If current Tx allocation is less than the min Tx FIFO size, |
bc7f75fa | 4003 | * and the min Tx FIFO size is less than the current Rx FIFO |
ad68076e BA |
4004 | * allocation, take space away from current Rx allocation |
4005 | */ | |
df762464 AK |
4006 | if ((tx_space < min_tx_space) && |
4007 | ((min_tx_space - tx_space) < pba)) { | |
4008 | pba -= min_tx_space - tx_space; | |
bc7f75fa | 4009 | |
e921eb1a | 4010 | /* if short on Rx space, Rx wins and must trump Tx |
419e551c | 4011 | * adjustment |
ad68076e | 4012 | */ |
79d4e908 | 4013 | if (pba < min_rx_space) |
df762464 | 4014 | pba = min_rx_space; |
bc7f75fa | 4015 | } |
df762464 AK |
4016 | |
4017 | ew32(PBA, pba); | |
bc7f75fa AK |
4018 | } |
4019 | ||
e921eb1a | 4020 | /* flow control settings |
ad68076e | 4021 | * |
38eb394e | 4022 | * The high water mark must be low enough to fit one full frame |
bc7f75fa AK |
4023 | * (or the size used for early receive) above it in the Rx FIFO. |
4024 | * Set it to the lower of: | |
4025 | * - 90% of the Rx FIFO size, and | |
38eb394e | 4026 | * - the full Rx FIFO size minus one full frame |
ad68076e | 4027 | */ |
d3738bb8 BA |
4028 | if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME) |
4029 | fc->pause_time = 0xFFFF; | |
4030 | else | |
4031 | fc->pause_time = E1000_FC_PAUSE_TIME; | |
b20caa80 | 4032 | fc->send_xon = true; |
d3738bb8 BA |
4033 | fc->current_mode = fc->requested_mode; |
4034 | ||
4035 | switch (hw->mac.type) { | |
79d4e908 BA |
4036 | case e1000_ich9lan: |
4037 | case e1000_ich10lan: | |
4038 | if (adapter->netdev->mtu > ETH_DATA_LEN) { | |
4039 | pba = 14; | |
4040 | ew32(PBA, pba); | |
4041 | fc->high_water = 0x2800; | |
4042 | fc->low_water = fc->high_water - 8; | |
4043 | break; | |
4044 | } | |
4045 | /* fall-through */ | |
d3738bb8 | 4046 | default: |
79d4e908 BA |
4047 | hwm = min(((pba << 10) * 9 / 10), |
4048 | ((pba << 10) - adapter->max_frame_size)); | |
d3738bb8 | 4049 | |
e80bd1d1 | 4050 | fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */ |
d3738bb8 BA |
4051 | fc->low_water = fc->high_water - 8; |
4052 | break; | |
4053 | case e1000_pchlan: | |
e921eb1a | 4054 | /* Workaround PCH LOM adapter hangs with certain network |
38eb394e BA |
4055 | * loads. If hangs persist, try disabling Tx flow control. |
4056 | */ | |
4057 | if (adapter->netdev->mtu > ETH_DATA_LEN) { | |
4058 | fc->high_water = 0x3500; | |
e80bd1d1 | 4059 | fc->low_water = 0x1500; |
38eb394e BA |
4060 | } else { |
4061 | fc->high_water = 0x5000; | |
e80bd1d1 | 4062 | fc->low_water = 0x3000; |
38eb394e | 4063 | } |
a305595b | 4064 | fc->refresh_time = 0x1000; |
d3738bb8 BA |
4065 | break; |
4066 | case e1000_pch2lan: | |
2fbe4526 | 4067 | case e1000_pch_lpt: |
79849ebc | 4068 | case e1000_pch_spt: |
c8744f44 | 4069 | case e1000_pch_cnp: |
d3738bb8 | 4070 | fc->refresh_time = 0x0400; |
347b5201 BA |
4071 | |
4072 | if (adapter->netdev->mtu <= ETH_DATA_LEN) { | |
4073 | fc->high_water = 0x05C20; | |
4074 | fc->low_water = 0x05048; | |
4075 | fc->pause_time = 0x0650; | |
4076 | break; | |
828bac87 | 4077 | } |
347b5201 | 4078 | |
ce345e08 BA |
4079 | pba = 14; |
4080 | ew32(PBA, pba); | |
347b5201 BA |
4081 | fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH; |
4082 | fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL; | |
d3738bb8 | 4083 | break; |
38eb394e | 4084 | } |
bc7f75fa | 4085 | |
e921eb1a | 4086 | /* Alignment of Tx data is on an arbitrary byte boundary with the |
d821a4c4 BA |
4087 | * maximum size per Tx descriptor limited only to the transmit |
4088 | * allocation of the packet buffer minus 96 bytes with an upper | |
4089 | * limit of 24KB due to receive synchronization limitations. | |
4090 | */ | |
4091 | adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96, | |
4092 | 24 << 10); | |
4093 | ||
e921eb1a | 4094 | /* Disable Adaptive Interrupt Moderation if 2 full packets cannot |
79d4e908 | 4095 | * fit in receive buffer. |
828bac87 BA |
4096 | */ |
4097 | if (adapter->itr_setting & 0x3) { | |
79d4e908 | 4098 | if ((adapter->max_frame_size * 2) > (pba << 10)) { |
828bac87 BA |
4099 | if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) { |
4100 | dev_info(&adapter->pdev->dev, | |
17e813ec | 4101 | "Interrupt Throttle Rate off\n"); |
828bac87 | 4102 | adapter->flags2 |= FLAG2_DISABLE_AIM; |
22a4cca2 | 4103 | e1000e_write_itr(adapter, 0); |
828bac87 BA |
4104 | } |
4105 | } else if (adapter->flags2 & FLAG2_DISABLE_AIM) { | |
4106 | dev_info(&adapter->pdev->dev, | |
17e813ec | 4107 | "Interrupt Throttle Rate on\n"); |
828bac87 BA |
4108 | adapter->flags2 &= ~FLAG2_DISABLE_AIM; |
4109 | adapter->itr = 20000; | |
22a4cca2 | 4110 | e1000e_write_itr(adapter, adapter->itr); |
828bac87 BA |
4111 | } |
4112 | } | |
4113 | ||
c8744f44 | 4114 | if (hw->mac.type >= e1000_pch_spt) |
0ffc5646 | 4115 | e1000_flush_desc_rings(adapter); |
bc7f75fa AK |
4116 | /* Allow time for pending master requests to run */ |
4117 | mac->ops.reset_hw(hw); | |
97ac8cae | 4118 | |
e921eb1a | 4119 | /* For parts with AMT enabled, let the firmware know |
97ac8cae BA |
4120 | * that the network interface is in control |
4121 | */ | |
c43bc57e | 4122 | if (adapter->flags & FLAG_HAS_AMT) |
31dbe5b4 | 4123 | e1000e_get_hw_control(adapter); |
97ac8cae | 4124 | |
bc7f75fa AK |
4125 | ew32(WUC, 0); |
4126 | ||
4127 | if (mac->ops.init_hw(hw)) | |
44defeb3 | 4128 | e_err("Hardware Error\n"); |
bc7f75fa AK |
4129 | |
4130 | e1000_update_mng_vlan(adapter); | |
4131 | ||
4132 | /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ | |
4133 | ew32(VET, ETH_P_8021Q); | |
4134 | ||
4135 | e1000e_reset_adaptive(hw); | |
31dbe5b4 | 4136 | |
aa524b66 JK |
4137 | /* restore systim and hwtstamp settings */ |
4138 | e1000e_systim_reset(adapter); | |
b67e1913 | 4139 | |
d495bcb8 BA |
4140 | /* Set EEE advertisement as appropriate */ |
4141 | if (adapter->flags2 & FLAG2_HAS_EEE) { | |
4142 | s32 ret_val; | |
4143 | u16 adv_addr; | |
4144 | ||
4145 | switch (hw->phy.type) { | |
4146 | case e1000_phy_82579: | |
4147 | adv_addr = I82579_EEE_ADVERTISEMENT; | |
4148 | break; | |
4149 | case e1000_phy_i217: | |
4150 | adv_addr = I217_EEE_ADVERTISEMENT; | |
4151 | break; | |
4152 | default: | |
4153 | dev_err(&adapter->pdev->dev, | |
4154 | "Invalid PHY type setting EEE advertisement\n"); | |
4155 | return; | |
4156 | } | |
4157 | ||
4158 | ret_val = hw->phy.ops.acquire(hw); | |
4159 | if (ret_val) { | |
4160 | dev_err(&adapter->pdev->dev, | |
4161 | "EEE advertisement - unable to acquire PHY\n"); | |
4162 | return; | |
4163 | } | |
4164 | ||
4165 | e1000_write_emi_reg_locked(hw, adv_addr, | |
4166 | hw->dev_spec.ich8lan.eee_disable ? | |
4167 | 0 : adapter->eee_advert); | |
4168 | ||
4169 | hw->phy.ops.release(hw); | |
4170 | } | |
4171 | ||
31dbe5b4 | 4172 | if (!netif_running(adapter->netdev) && |
28002099 | 4173 | !test_bit(__E1000_TESTING, &adapter->state)) |
31dbe5b4 | 4174 | e1000_power_down_phy(adapter); |
31dbe5b4 | 4175 | |
bc7f75fa AK |
4176 | e1000_get_phy_info(hw); |
4177 | ||
918d7197 BA |
4178 | if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) && |
4179 | !(adapter->flags & FLAG_SMART_POWER_DOWN)) { | |
bc7f75fa | 4180 | u16 phy_data = 0; |
e921eb1a | 4181 | /* speed up time to link by disabling smart power down, ignore |
bc7f75fa | 4182 | * the return value of this function because there is nothing |
ad68076e BA |
4183 | * different we would do if it failed |
4184 | */ | |
bc7f75fa AK |
4185 | e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data); |
4186 | phy_data &= ~IGP02E1000_PM_SPD; | |
4187 | e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data); | |
4188 | } | |
c8744f44 | 4189 | if (hw->mac.type >= e1000_pch_spt && adapter->int_mode == 0) { |
ec945cfb YL |
4190 | u32 reg; |
4191 | ||
4192 | /* Fextnvm7 @ 0xe4[2] = 1 */ | |
4193 | reg = er32(FEXTNVM7); | |
4194 | reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE; | |
4195 | ew32(FEXTNVM7, reg); | |
4196 | /* Fextnvm9 @ 0x5bb4[13:12] = 11 */ | |
4197 | reg = er32(FEXTNVM9); | |
4198 | reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS | | |
4199 | E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS; | |
4200 | ew32(FEXTNVM9, reg); | |
4201 | } | |
4202 | ||
bc7f75fa AK |
4203 | } |
4204 | ||
a61cfe4f BP |
4205 | /** |
4206 | * e1000e_trigger_lsc - trigger an LSC interrupt | |
4207 | * @adapter: | |
4208 | * | |
4209 | * Fire a link status change interrupt to start the watchdog. | |
4210 | **/ | |
4211 | static void e1000e_trigger_lsc(struct e1000_adapter *adapter) | |
bc7f75fa AK |
4212 | { |
4213 | struct e1000_hw *hw = &adapter->hw; | |
4214 | ||
a61cfe4f | 4215 | if (adapter->msix_entries) |
4aea7a5c | 4216 | ew32(ICS, E1000_ICS_LSC | E1000_ICS_OTHER); |
a61cfe4f BP |
4217 | else |
4218 | ew32(ICS, E1000_ICS_LSC); | |
4219 | } | |
4220 | ||
4221 | void e1000e_up(struct e1000_adapter *adapter) | |
4222 | { | |
bc7f75fa AK |
4223 | /* hardware has been reset, we need to reload some things */ |
4224 | e1000_configure(adapter); | |
4225 | ||
4226 | clear_bit(__E1000_DOWN, &adapter->state); | |
4227 | ||
4662e82b BA |
4228 | if (adapter->msix_entries) |
4229 | e1000_configure_msix(adapter); | |
bc7f75fa AK |
4230 | e1000_irq_enable(adapter); |
4231 | ||
400484fa | 4232 | netif_start_queue(adapter->netdev); |
4cb9be7a | 4233 | |
a61cfe4f | 4234 | e1000e_trigger_lsc(adapter); |
bc7f75fa AK |
4235 | } |
4236 | ||
713b3c9e JB |
4237 | static void e1000e_flush_descriptors(struct e1000_adapter *adapter) |
4238 | { | |
4239 | struct e1000_hw *hw = &adapter->hw; | |
4240 | ||
4241 | if (!(adapter->flags2 & FLAG2_DMA_BURST)) | |
4242 | return; | |
4243 | ||
4244 | /* flush pending descriptor writebacks to memory */ | |
4245 | ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); | |
4246 | ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); | |
4247 | ||
4248 | /* execute the writes immediately */ | |
4249 | e1e_flush(); | |
bf03085f | 4250 | |
e921eb1a | 4251 | /* due to rare timing issues, write to TIDV/RDTR again to ensure the |
bf03085f MV |
4252 | * write is successful |
4253 | */ | |
4254 | ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD); | |
4255 | ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD); | |
713b3c9e JB |
4256 | |
4257 | /* execute the writes immediately */ | |
4258 | e1e_flush(); | |
4259 | } | |
4260 | ||
67fd4fcb JK |
4261 | static void e1000e_update_stats(struct e1000_adapter *adapter); |
4262 | ||
28002099 DE |
4263 | /** |
4264 | * e1000e_down - quiesce the device and optionally reset the hardware | |
4265 | * @adapter: board private structure | |
4266 | * @reset: boolean flag to reset the hardware or not | |
4267 | */ | |
4268 | void e1000e_down(struct e1000_adapter *adapter, bool reset) | |
bc7f75fa AK |
4269 | { |
4270 | struct net_device *netdev = adapter->netdev; | |
4271 | struct e1000_hw *hw = &adapter->hw; | |
4272 | u32 tctl, rctl; | |
4273 | ||
e921eb1a | 4274 | /* signal that we're down so the interrupt handler does not |
ad68076e BA |
4275 | * reschedule our watchdog timer |
4276 | */ | |
bc7f75fa AK |
4277 | set_bit(__E1000_DOWN, &adapter->state); |
4278 | ||
a60a132e ET |
4279 | netif_carrier_off(netdev); |
4280 | ||
bc7f75fa AK |
4281 | /* disable receives in the hardware */ |
4282 | rctl = er32(RCTL); | |
7f99ae63 BA |
4283 | if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX)) |
4284 | ew32(RCTL, rctl & ~E1000_RCTL_EN); | |
bc7f75fa AK |
4285 | /* flush and sleep below */ |
4286 | ||
4cb9be7a | 4287 | netif_stop_queue(netdev); |
bc7f75fa AK |
4288 | |
4289 | /* disable transmits in the hardware */ | |
4290 | tctl = er32(TCTL); | |
4291 | tctl &= ~E1000_TCTL_EN; | |
4292 | ew32(TCTL, tctl); | |
7f99ae63 | 4293 | |
bc7f75fa AK |
4294 | /* flush both disables and wait for them to finish */ |
4295 | e1e_flush(); | |
1bba4386 | 4296 | usleep_range(10000, 20000); |
bc7f75fa | 4297 | |
bc7f75fa AK |
4298 | e1000_irq_disable(adapter); |
4299 | ||
a3b87a4c BA |
4300 | napi_synchronize(&adapter->napi); |
4301 | ||
bc7f75fa AK |
4302 | del_timer_sync(&adapter->watchdog_timer); |
4303 | del_timer_sync(&adapter->phy_info_timer); | |
4304 | ||
67fd4fcb JK |
4305 | spin_lock(&adapter->stats64_lock); |
4306 | e1000e_update_stats(adapter); | |
4307 | spin_unlock(&adapter->stats64_lock); | |
4308 | ||
400484fa | 4309 | e1000e_flush_descriptors(adapter); |
400484fa | 4310 | |
bc7f75fa AK |
4311 | adapter->link_speed = 0; |
4312 | adapter->link_duplex = 0; | |
4313 | ||
da1e2046 BA |
4314 | /* Disable Si errata workaround on PCHx for jumbo frame flow */ |
4315 | if ((hw->mac.type >= e1000_pch2lan) && | |
4316 | (adapter->netdev->mtu > ETH_DATA_LEN) && | |
4317 | e1000_lv_jumbo_workaround_ich8lan(hw, false)) | |
4318 | e_dbg("failed to disable jumbo frame workaround mode\n"); | |
4319 | ||
0ffc5646 YL |
4320 | if (!pci_channel_offline(adapter->pdev)) { |
4321 | if (reset) | |
4322 | e1000e_reset(adapter); | |
c8744f44 | 4323 | else if (hw->mac.type >= e1000_pch_spt) |
0ffc5646 YL |
4324 | e1000_flush_desc_rings(adapter); |
4325 | } | |
4326 | e1000_clean_tx_ring(adapter->tx_ring); | |
4327 | e1000_clean_rx_ring(adapter->rx_ring); | |
bc7f75fa AK |
4328 | } |
4329 | ||
4330 | void e1000e_reinit_locked(struct e1000_adapter *adapter) | |
4331 | { | |
4332 | might_sleep(); | |
4333 | while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) | |
1bba4386 | 4334 | usleep_range(1000, 2000); |
28002099 | 4335 | e1000e_down(adapter, true); |
bc7f75fa AK |
4336 | e1000e_up(adapter); |
4337 | clear_bit(__E1000_RESETTING, &adapter->state); | |
4338 | } | |
4339 | ||
0be5b96c JW |
4340 | /** |
4341 | * e1000e_sanitize_systim - sanitize raw cycle counter reads | |
4342 | * @hw: pointer to the HW structure | |
a5a1d1c2 | 4343 | * @systim: time value read, sanitized and returned |
0be5b96c JW |
4344 | * |
4345 | * Errata for 82574/82583 possible bad bits read from SYSTIMH/L: | |
4346 | * check to see that the time is incrementing at a reasonable | |
4347 | * rate and is a multiple of incvalue. | |
4348 | **/ | |
a5a1d1c2 | 4349 | static u64 e1000e_sanitize_systim(struct e1000_hw *hw, u64 systim) |
0be5b96c JW |
4350 | { |
4351 | u64 time_delta, rem, temp; | |
a5a1d1c2 | 4352 | u64 systim_next; |
0be5b96c JW |
4353 | u32 incvalue; |
4354 | int i; | |
4355 | ||
4356 | incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK; | |
4357 | for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) { | |
4358 | /* latch SYSTIMH on read of SYSTIML */ | |
a5a1d1c2 TG |
4359 | systim_next = (u64)er32(SYSTIML); |
4360 | systim_next |= (u64)er32(SYSTIMH) << 32; | |
0be5b96c JW |
4361 | |
4362 | time_delta = systim_next - systim; | |
4363 | temp = time_delta; | |
4364 | /* VMWare users have seen incvalue of zero, don't div / 0 */ | |
4365 | rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0); | |
4366 | ||
4367 | systim = systim_next; | |
4368 | ||
4369 | if ((time_delta < E1000_82574_SYSTIM_EPSILON) && (rem == 0)) | |
4370 | break; | |
4371 | } | |
4372 | ||
4373 | return systim; | |
4374 | } | |
4375 | ||
b67e1913 BA |
4376 | /** |
4377 | * e1000e_cyclecounter_read - read raw cycle counter (used by time counter) | |
4378 | * @cc: cyclecounter structure | |
4379 | **/ | |
a5a1d1c2 | 4380 | static u64 e1000e_cyclecounter_read(const struct cyclecounter *cc) |
b67e1913 BA |
4381 | { |
4382 | struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter, | |
4383 | cc); | |
4384 | struct e1000_hw *hw = &adapter->hw; | |
ab507c9a | 4385 | u32 systimel, systimeh; |
a5a1d1c2 | 4386 | u64 systim; |
37b12910 RA |
4387 | /* SYSTIMH latching upon SYSTIML read does not work well. |
4388 | * This means that if SYSTIML overflows after we read it but before | |
4389 | * we read SYSTIMH, the value of SYSTIMH has been incremented and we | |
4390 | * will experience a huge non linear increment in the systime value | |
4391 | * to fix that we test for overflow and if true, we re-read systime. | |
83129b37 | 4392 | */ |
ab507c9a | 4393 | systimel = er32(SYSTIML); |
37b12910 | 4394 | systimeh = er32(SYSTIMH); |
ab507c9a DV |
4395 | /* Is systimel is so large that overflow is possible? */ |
4396 | if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) { | |
4397 | u32 systimel_2 = er32(SYSTIML); | |
4398 | if (systimel > systimel_2) { | |
4399 | /* There was an overflow, read again SYSTIMH, and use | |
4400 | * systimel_2 | |
4401 | */ | |
4402 | systimeh = er32(SYSTIMH); | |
4403 | systimel = systimel_2; | |
4404 | } | |
37b12910 | 4405 | } |
a5a1d1c2 TG |
4406 | systim = (u64)systimel; |
4407 | systim |= (u64)systimeh << 32; | |
b67e1913 | 4408 | |
0be5b96c JW |
4409 | if (adapter->flags2 & FLAG2_CHECK_SYSTIM_OVERFLOW) |
4410 | systim = e1000e_sanitize_systim(hw, systim); | |
5e7ff970 | 4411 | |
b67e1913 BA |
4412 | return systim; |
4413 | } | |
4414 | ||
bc7f75fa AK |
4415 | /** |
4416 | * e1000_sw_init - Initialize general software structures (struct e1000_adapter) | |
4417 | * @adapter: board private structure to initialize | |
4418 | * | |
4419 | * e1000_sw_init initializes the Adapter private data structure. | |
4420 | * Fields are initialized based on PCI device information and | |
4421 | * OS network device settings (MTU size). | |
4422 | **/ | |
9f9a12f8 | 4423 | static int e1000_sw_init(struct e1000_adapter *adapter) |
bc7f75fa | 4424 | { |
bc7f75fa AK |
4425 | struct net_device *netdev = adapter->netdev; |
4426 | ||
8084b86d | 4427 | adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; |
bc7f75fa | 4428 | adapter->rx_ps_bsize0 = 128; |
8084b86d | 4429 | adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; |
318a94d6 | 4430 | adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; |
55aa6985 BA |
4431 | adapter->tx_ring_count = E1000_DEFAULT_TXD; |
4432 | adapter->rx_ring_count = E1000_DEFAULT_RXD; | |
bc7f75fa | 4433 | |
67fd4fcb JK |
4434 | spin_lock_init(&adapter->stats64_lock); |
4435 | ||
4662e82b | 4436 | e1000e_set_interrupt_capability(adapter); |
bc7f75fa | 4437 | |
4662e82b BA |
4438 | if (e1000_alloc_queues(adapter)) |
4439 | return -ENOMEM; | |
bc7f75fa | 4440 | |
b67e1913 BA |
4441 | /* Setup hardware time stamping cyclecounter */ |
4442 | if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { | |
4443 | adapter->cc.read = e1000e_cyclecounter_read; | |
4d045b4c | 4444 | adapter->cc.mask = CYCLECOUNTER_MASK(64); |
b67e1913 BA |
4445 | adapter->cc.mult = 1; |
4446 | /* cc.shift set in e1000e_get_base_tininca() */ | |
4447 | ||
4448 | spin_lock_init(&adapter->systim_lock); | |
4449 | INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work); | |
4450 | } | |
4451 | ||
bc7f75fa | 4452 | /* Explicitly disable IRQ since the NIC can be in any state. */ |
bc7f75fa AK |
4453 | e1000_irq_disable(adapter); |
4454 | ||
bc7f75fa AK |
4455 | set_bit(__E1000_DOWN, &adapter->state); |
4456 | return 0; | |
bc7f75fa AK |
4457 | } |
4458 | ||
f8d59f78 BA |
4459 | /** |
4460 | * e1000_intr_msi_test - Interrupt Handler | |
4461 | * @irq: interrupt number | |
4462 | * @data: pointer to a network interface device structure | |
4463 | **/ | |
8bb62869 | 4464 | static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data) |
f8d59f78 BA |
4465 | { |
4466 | struct net_device *netdev = data; | |
4467 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
4468 | struct e1000_hw *hw = &adapter->hw; | |
4469 | u32 icr = er32(ICR); | |
4470 | ||
3bb99fe2 | 4471 | e_dbg("icr is %08X\n", icr); |
f8d59f78 BA |
4472 | if (icr & E1000_ICR_RXSEQ) { |
4473 | adapter->flags &= ~FLAG_MSI_TEST_FAILED; | |
e921eb1a | 4474 | /* Force memory writes to complete before acknowledging the |
bc76329d BA |
4475 | * interrupt is handled. |
4476 | */ | |
f8d59f78 BA |
4477 | wmb(); |
4478 | } | |
4479 | ||
4480 | return IRQ_HANDLED; | |
4481 | } | |
4482 | ||
4483 | /** | |
4484 | * e1000_test_msi_interrupt - Returns 0 for successful test | |
4485 | * @adapter: board private struct | |
4486 | * | |
4487 | * code flow taken from tg3.c | |
4488 | **/ | |
4489 | static int e1000_test_msi_interrupt(struct e1000_adapter *adapter) | |
4490 | { | |
4491 | struct net_device *netdev = adapter->netdev; | |
4492 | struct e1000_hw *hw = &adapter->hw; | |
4493 | int err; | |
4494 | ||
4495 | /* poll_enable hasn't been called yet, so don't need disable */ | |
4496 | /* clear any pending events */ | |
4497 | er32(ICR); | |
4498 | ||
4499 | /* free the real vector and request a test handler */ | |
4500 | e1000_free_irq(adapter); | |
4662e82b | 4501 | e1000e_reset_interrupt_capability(adapter); |
f8d59f78 BA |
4502 | |
4503 | /* Assume that the test fails, if it succeeds then the test | |
e921eb1a BA |
4504 | * MSI irq handler will unset this flag |
4505 | */ | |
f8d59f78 BA |
4506 | adapter->flags |= FLAG_MSI_TEST_FAILED; |
4507 | ||
4508 | err = pci_enable_msi(adapter->pdev); | |
4509 | if (err) | |
4510 | goto msi_test_failed; | |
4511 | ||
a0607fd3 | 4512 | err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0, |
f8d59f78 BA |
4513 | netdev->name, netdev); |
4514 | if (err) { | |
4515 | pci_disable_msi(adapter->pdev); | |
4516 | goto msi_test_failed; | |
4517 | } | |
4518 | ||
e921eb1a | 4519 | /* Force memory writes to complete before enabling and firing an |
bc76329d BA |
4520 | * interrupt. |
4521 | */ | |
f8d59f78 BA |
4522 | wmb(); |
4523 | ||
4524 | e1000_irq_enable(adapter); | |
4525 | ||
4526 | /* fire an unusual interrupt on the test handler */ | |
4527 | ew32(ICS, E1000_ICS_RXSEQ); | |
4528 | e1e_flush(); | |
569a3aff | 4529 | msleep(100); |
f8d59f78 BA |
4530 | |
4531 | e1000_irq_disable(adapter); | |
4532 | ||
bc76329d | 4533 | rmb(); /* read flags after interrupt has been fired */ |
f8d59f78 BA |
4534 | |
4535 | if (adapter->flags & FLAG_MSI_TEST_FAILED) { | |
4662e82b | 4536 | adapter->int_mode = E1000E_INT_MODE_LEGACY; |
068e8a30 | 4537 | e_info("MSI interrupt test failed, using legacy interrupt.\n"); |
24b706b2 | 4538 | } else { |
068e8a30 | 4539 | e_dbg("MSI interrupt test succeeded!\n"); |
24b706b2 | 4540 | } |
f8d59f78 BA |
4541 | |
4542 | free_irq(adapter->pdev->irq, netdev); | |
4543 | pci_disable_msi(adapter->pdev); | |
4544 | ||
f8d59f78 | 4545 | msi_test_failed: |
4662e82b | 4546 | e1000e_set_interrupt_capability(adapter); |
068e8a30 | 4547 | return e1000_request_irq(adapter); |
f8d59f78 BA |
4548 | } |
4549 | ||
4550 | /** | |
4551 | * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored | |
4552 | * @adapter: board private struct | |
4553 | * | |
4554 | * code flow taken from tg3.c, called with e1000 interrupts disabled. | |
4555 | **/ | |
4556 | static int e1000_test_msi(struct e1000_adapter *adapter) | |
4557 | { | |
4558 | int err; | |
4559 | u16 pci_cmd; | |
4560 | ||
4561 | if (!(adapter->flags & FLAG_MSI_ENABLED)) | |
4562 | return 0; | |
4563 | ||
4564 | /* disable SERR in case the MSI write causes a master abort */ | |
4565 | pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); | |
36f2407f DN |
4566 | if (pci_cmd & PCI_COMMAND_SERR) |
4567 | pci_write_config_word(adapter->pdev, PCI_COMMAND, | |
4568 | pci_cmd & ~PCI_COMMAND_SERR); | |
f8d59f78 BA |
4569 | |
4570 | err = e1000_test_msi_interrupt(adapter); | |
4571 | ||
36f2407f DN |
4572 | /* re-enable SERR */ |
4573 | if (pci_cmd & PCI_COMMAND_SERR) { | |
4574 | pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd); | |
4575 | pci_cmd |= PCI_COMMAND_SERR; | |
4576 | pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd); | |
4577 | } | |
f8d59f78 | 4578 | |
f8d59f78 BA |
4579 | return err; |
4580 | } | |
4581 | ||
bc7f75fa | 4582 | /** |
d5ea45da | 4583 | * e1000e_open - Called when a network interface is made active |
bc7f75fa AK |
4584 | * @netdev: network interface device structure |
4585 | * | |
4586 | * Returns 0 on success, negative value on failure | |
4587 | * | |
4588 | * The open entry point is called when a network interface is made | |
4589 | * active by the system (IFF_UP). At this point all resources needed | |
4590 | * for transmit and receive operations are allocated, the interrupt | |
4591 | * handler is registered with the OS, the watchdog timer is started, | |
4592 | * and the stack is notified that the interface is ready. | |
4593 | **/ | |
d5ea45da | 4594 | int e1000e_open(struct net_device *netdev) |
bc7f75fa AK |
4595 | { |
4596 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
4597 | struct e1000_hw *hw = &adapter->hw; | |
23606cf5 | 4598 | struct pci_dev *pdev = adapter->pdev; |
bc7f75fa AK |
4599 | int err; |
4600 | ||
4601 | /* disallow open during test */ | |
4602 | if (test_bit(__E1000_TESTING, &adapter->state)) | |
4603 | return -EBUSY; | |
4604 | ||
23606cf5 RW |
4605 | pm_runtime_get_sync(&pdev->dev); |
4606 | ||
9c563d20 JB |
4607 | netif_carrier_off(netdev); |
4608 | ||
bc7f75fa | 4609 | /* allocate transmit descriptors */ |
55aa6985 | 4610 | err = e1000e_setup_tx_resources(adapter->tx_ring); |
bc7f75fa AK |
4611 | if (err) |
4612 | goto err_setup_tx; | |
4613 | ||
4614 | /* allocate receive descriptors */ | |
55aa6985 | 4615 | err = e1000e_setup_rx_resources(adapter->rx_ring); |
bc7f75fa AK |
4616 | if (err) |
4617 | goto err_setup_rx; | |
4618 | ||
e921eb1a | 4619 | /* If AMT is enabled, let the firmware know that the network |
11b08be8 BA |
4620 | * interface is now open and reset the part to a known state. |
4621 | */ | |
4622 | if (adapter->flags & FLAG_HAS_AMT) { | |
31dbe5b4 | 4623 | e1000e_get_hw_control(adapter); |
11b08be8 BA |
4624 | e1000e_reset(adapter); |
4625 | } | |
4626 | ||
bc7f75fa AK |
4627 | e1000e_power_up_phy(adapter); |
4628 | ||
4629 | adapter->mng_vlan_id = E1000_MNG_VLAN_NONE; | |
e5fe2541 | 4630 | if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)) |
bc7f75fa AK |
4631 | e1000_update_mng_vlan(adapter); |
4632 | ||
79d4e908 | 4633 | /* DMA latency requirement to workaround jumbo issue */ |
e2c65448 | 4634 | pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, |
3e35d991 | 4635 | PM_QOS_DEFAULT_VALUE); |
c128ec29 | 4636 | |
e921eb1a | 4637 | /* before we allocate an interrupt, we must be ready to handle it. |
bc7f75fa AK |
4638 | * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt |
4639 | * as soon as we call pci_request_irq, so we have to setup our | |
ad68076e BA |
4640 | * clean_rx handler before we do so. |
4641 | */ | |
bc7f75fa AK |
4642 | e1000_configure(adapter); |
4643 | ||
4644 | err = e1000_request_irq(adapter); | |
4645 | if (err) | |
4646 | goto err_req_irq; | |
4647 | ||
e921eb1a | 4648 | /* Work around PCIe errata with MSI interrupts causing some chipsets to |
f8d59f78 BA |
4649 | * ignore e1000e MSI messages, which means we need to test our MSI |
4650 | * interrupt now | |
4651 | */ | |
4662e82b | 4652 | if (adapter->int_mode != E1000E_INT_MODE_LEGACY) { |
f8d59f78 BA |
4653 | err = e1000_test_msi(adapter); |
4654 | if (err) { | |
4655 | e_err("Interrupt allocation failed\n"); | |
4656 | goto err_req_irq; | |
4657 | } | |
4658 | } | |
4659 | ||
bc7f75fa AK |
4660 | /* From here on the code is the same as e1000e_up() */ |
4661 | clear_bit(__E1000_DOWN, &adapter->state); | |
4662 | ||
4663 | napi_enable(&adapter->napi); | |
4664 | ||
4665 | e1000_irq_enable(adapter); | |
4666 | ||
09357b00 | 4667 | adapter->tx_hang_recheck = false; |
4cb9be7a | 4668 | netif_start_queue(netdev); |
d55b53ff | 4669 | |
66148bab | 4670 | hw->mac.get_link_status = true; |
23606cf5 RW |
4671 | pm_runtime_put(&pdev->dev); |
4672 | ||
a61cfe4f | 4673 | e1000e_trigger_lsc(adapter); |
bc7f75fa AK |
4674 | |
4675 | return 0; | |
4676 | ||
4677 | err_req_irq: | |
7faae964 | 4678 | pm_qos_remove_request(&adapter->pm_qos_req); |
31dbe5b4 | 4679 | e1000e_release_hw_control(adapter); |
bc7f75fa | 4680 | e1000_power_down_phy(adapter); |
55aa6985 | 4681 | e1000e_free_rx_resources(adapter->rx_ring); |
bc7f75fa | 4682 | err_setup_rx: |
55aa6985 | 4683 | e1000e_free_tx_resources(adapter->tx_ring); |
bc7f75fa AK |
4684 | err_setup_tx: |
4685 | e1000e_reset(adapter); | |
23606cf5 | 4686 | pm_runtime_put_sync(&pdev->dev); |
bc7f75fa AK |
4687 | |
4688 | return err; | |
4689 | } | |
4690 | ||
4691 | /** | |
d5ea45da | 4692 | * e1000e_close - Disables a network interface |
bc7f75fa AK |
4693 | * @netdev: network interface device structure |
4694 | * | |
4695 | * Returns 0, this is not allowed to fail | |
4696 | * | |
4697 | * The close entry point is called when an interface is de-activated | |
4698 | * by the OS. The hardware is still under the drivers control, but | |
4699 | * needs to be disabled. A global MAC reset is issued to stop the | |
4700 | * hardware, and all transmit and receive resources are freed. | |
4701 | **/ | |
d5ea45da | 4702 | int e1000e_close(struct net_device *netdev) |
bc7f75fa AK |
4703 | { |
4704 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
23606cf5 | 4705 | struct pci_dev *pdev = adapter->pdev; |
bb9e44d0 BA |
4706 | int count = E1000_CHECK_RESET_COUNT; |
4707 | ||
4708 | while (test_bit(__E1000_RESETTING, &adapter->state) && count--) | |
4709 | usleep_range(10000, 20000); | |
bc7f75fa AK |
4710 | |
4711 | WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); | |
23606cf5 RW |
4712 | |
4713 | pm_runtime_get_sync(&pdev->dev); | |
4714 | ||
4715 | if (!test_bit(__E1000_DOWN, &adapter->state)) { | |
28002099 | 4716 | e1000e_down(adapter, true); |
23606cf5 | 4717 | e1000_free_irq(adapter); |
63eb48f1 DE |
4718 | |
4719 | /* Link status message must follow this format */ | |
4720 | pr_info("%s NIC Link is Down\n", adapter->netdev->name); | |
23606cf5 | 4721 | } |
a3b87a4c BA |
4722 | |
4723 | napi_disable(&adapter->napi); | |
4724 | ||
55aa6985 BA |
4725 | e1000e_free_tx_resources(adapter->tx_ring); |
4726 | e1000e_free_rx_resources(adapter->rx_ring); | |
bc7f75fa | 4727 | |
e921eb1a | 4728 | /* kill manageability vlan ID if supported, but not if a vlan with |
ad68076e BA |
4729 | * the same ID is registered on the host OS (let 8021q kill it) |
4730 | */ | |
e5fe2541 | 4731 | if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) |
80d5c368 PM |
4732 | e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), |
4733 | adapter->mng_vlan_id); | |
bc7f75fa | 4734 | |
e921eb1a | 4735 | /* If AMT is enabled, let the firmware know that the network |
ad68076e BA |
4736 | * interface is now closed |
4737 | */ | |
31dbe5b4 BA |
4738 | if ((adapter->flags & FLAG_HAS_AMT) && |
4739 | !test_bit(__E1000_TESTING, &adapter->state)) | |
4740 | e1000e_release_hw_control(adapter); | |
bc7f75fa | 4741 | |
e2c65448 | 4742 | pm_qos_remove_request(&adapter->pm_qos_req); |
c128ec29 | 4743 | |
23606cf5 RW |
4744 | pm_runtime_put_sync(&pdev->dev); |
4745 | ||
bc7f75fa AK |
4746 | return 0; |
4747 | } | |
fc830b78 | 4748 | |
bc7f75fa AK |
4749 | /** |
4750 | * e1000_set_mac - Change the Ethernet Address of the NIC | |
4751 | * @netdev: network interface device structure | |
4752 | * @p: pointer to an address structure | |
4753 | * | |
4754 | * Returns 0 on success, negative on failure | |
4755 | **/ | |
4756 | static int e1000_set_mac(struct net_device *netdev, void *p) | |
4757 | { | |
4758 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
69e1e019 | 4759 | struct e1000_hw *hw = &adapter->hw; |
bc7f75fa AK |
4760 | struct sockaddr *addr = p; |
4761 | ||
4762 | if (!is_valid_ether_addr(addr->sa_data)) | |
4763 | return -EADDRNOTAVAIL; | |
4764 | ||
4765 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
4766 | memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len); | |
4767 | ||
69e1e019 | 4768 | hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0); |
bc7f75fa AK |
4769 | |
4770 | if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) { | |
4771 | /* activate the work around */ | |
4772 | e1000e_set_laa_state_82571(&adapter->hw, 1); | |
4773 | ||
e921eb1a | 4774 | /* Hold a copy of the LAA in RAR[14] This is done so that |
bc7f75fa AK |
4775 | * between the time RAR[0] gets clobbered and the time it |
4776 | * gets fixed (in e1000_watchdog), the actual LAA is in one | |
4777 | * of the RARs and no incoming packets directed to this port | |
4778 | * are dropped. Eventually the LAA will be in RAR[0] and | |
ad68076e BA |
4779 | * RAR[14] |
4780 | */ | |
69e1e019 BA |
4781 | hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, |
4782 | adapter->hw.mac.rar_entry_count - 1); | |
bc7f75fa AK |
4783 | } |
4784 | ||
4785 | return 0; | |
4786 | } | |
4787 | ||
a8f88ff5 JB |
4788 | /** |
4789 | * e1000e_update_phy_task - work thread to update phy | |
4790 | * @work: pointer to our work struct | |
4791 | * | |
4792 | * this worker thread exists because we must acquire a | |
4793 | * semaphore to read the phy, which we could msleep while | |
4794 | * waiting for it, and we can't msleep in a timer. | |
4795 | **/ | |
4796 | static void e1000e_update_phy_task(struct work_struct *work) | |
4797 | { | |
4798 | struct e1000_adapter *adapter = container_of(work, | |
17e813ec BA |
4799 | struct e1000_adapter, |
4800 | update_phy_task); | |
a03206ed | 4801 | struct e1000_hw *hw = &adapter->hw; |
615b32af JB |
4802 | |
4803 | if (test_bit(__E1000_DOWN, &adapter->state)) | |
4804 | return; | |
4805 | ||
a03206ed DE |
4806 | e1000_get_phy_info(hw); |
4807 | ||
4808 | /* Enable EEE on 82579 after link up */ | |
50844bb7 | 4809 | if (hw->phy.type >= e1000_phy_82579) |
a03206ed | 4810 | e1000_set_eee_pchlan(hw); |
a8f88ff5 JB |
4811 | } |
4812 | ||
e921eb1a BA |
4813 | /** |
4814 | * e1000_update_phy_info - timre call-back to update PHY info | |
4815 | * @data: pointer to adapter cast into an unsigned long | |
4816 | * | |
ad68076e BA |
4817 | * Need to wait a few seconds after link up to get diagnostic information from |
4818 | * the phy | |
e921eb1a | 4819 | **/ |
26566eae | 4820 | static void e1000_update_phy_info(struct timer_list *t) |
bc7f75fa | 4821 | { |
26566eae | 4822 | struct e1000_adapter *adapter = from_timer(adapter, t, phy_info_timer); |
615b32af JB |
4823 | |
4824 | if (test_bit(__E1000_DOWN, &adapter->state)) | |
4825 | return; | |
4826 | ||
a8f88ff5 | 4827 | schedule_work(&adapter->update_phy_task); |
bc7f75fa AK |
4828 | } |
4829 | ||
8c7bbb92 BA |
4830 | /** |
4831 | * e1000e_update_phy_stats - Update the PHY statistics counters | |
4832 | * @adapter: board private structure | |
2b6b168d BA |
4833 | * |
4834 | * Read/clear the upper 16-bit PHY registers and read/accumulate lower | |
8c7bbb92 BA |
4835 | **/ |
4836 | static void e1000e_update_phy_stats(struct e1000_adapter *adapter) | |
4837 | { | |
4838 | struct e1000_hw *hw = &adapter->hw; | |
4839 | s32 ret_val; | |
4840 | u16 phy_data; | |
4841 | ||
4842 | ret_val = hw->phy.ops.acquire(hw); | |
4843 | if (ret_val) | |
4844 | return; | |
4845 | ||
e921eb1a | 4846 | /* A page set is expensive so check if already on desired page. |
8c7bbb92 BA |
4847 | * If not, set to the page with the PHY status registers. |
4848 | */ | |
2b6b168d | 4849 | hw->phy.addr = 1; |
8c7bbb92 BA |
4850 | ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, |
4851 | &phy_data); | |
4852 | if (ret_val) | |
4853 | goto release; | |
2b6b168d BA |
4854 | if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) { |
4855 | ret_val = hw->phy.ops.set_page(hw, | |
4856 | HV_STATS_PAGE << IGP_PAGE_SHIFT); | |
8c7bbb92 BA |
4857 | if (ret_val) |
4858 | goto release; | |
4859 | } | |
4860 | ||
8c7bbb92 | 4861 | /* Single Collision Count */ |
2b6b168d BA |
4862 | hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); |
4863 | ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); | |
8c7bbb92 BA |
4864 | if (!ret_val) |
4865 | adapter->stats.scc += phy_data; | |
4866 | ||
4867 | /* Excessive Collision Count */ | |
2b6b168d BA |
4868 | hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); |
4869 | ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); | |
8c7bbb92 BA |
4870 | if (!ret_val) |
4871 | adapter->stats.ecol += phy_data; | |
4872 | ||
4873 | /* Multiple Collision Count */ | |
2b6b168d BA |
4874 | hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); |
4875 | ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); | |
8c7bbb92 BA |
4876 | if (!ret_val) |
4877 | adapter->stats.mcc += phy_data; | |
4878 | ||
4879 | /* Late Collision Count */ | |
2b6b168d BA |
4880 | hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); |
4881 | ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); | |
8c7bbb92 BA |
4882 | if (!ret_val) |
4883 | adapter->stats.latecol += phy_data; | |
4884 | ||
4885 | /* Collision Count - also used for adaptive IFS */ | |
2b6b168d BA |
4886 | hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); |
4887 | ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); | |
8c7bbb92 BA |
4888 | if (!ret_val) |
4889 | hw->mac.collision_delta = phy_data; | |
4890 | ||
4891 | /* Defer Count */ | |
2b6b168d BA |
4892 | hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); |
4893 | ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); | |
8c7bbb92 BA |
4894 | if (!ret_val) |
4895 | adapter->stats.dc += phy_data; | |
4896 | ||
4897 | /* Transmit with no CRS */ | |
2b6b168d BA |
4898 | hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); |
4899 | ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); | |
8c7bbb92 BA |
4900 | if (!ret_val) |
4901 | adapter->stats.tncrs += phy_data; | |
4902 | ||
4903 | release: | |
4904 | hw->phy.ops.release(hw); | |
4905 | } | |
4906 | ||
bc7f75fa AK |
4907 | /** |
4908 | * e1000e_update_stats - Update the board statistics counters | |
4909 | * @adapter: board private structure | |
4910 | **/ | |
67fd4fcb | 4911 | static void e1000e_update_stats(struct e1000_adapter *adapter) |
bc7f75fa | 4912 | { |
7274c20f | 4913 | struct net_device *netdev = adapter->netdev; |
bc7f75fa AK |
4914 | struct e1000_hw *hw = &adapter->hw; |
4915 | struct pci_dev *pdev = adapter->pdev; | |
bc7f75fa | 4916 | |
e921eb1a | 4917 | /* Prevent stats update while adapter is being reset, or if the pci |
bc7f75fa AK |
4918 | * connection is down. |
4919 | */ | |
4920 | if (adapter->link_speed == 0) | |
4921 | return; | |
4922 | if (pci_channel_offline(pdev)) | |
4923 | return; | |
4924 | ||
bc7f75fa AK |
4925 | adapter->stats.crcerrs += er32(CRCERRS); |
4926 | adapter->stats.gprc += er32(GPRC); | |
7c25769f | 4927 | adapter->stats.gorc += er32(GORCL); |
e80bd1d1 | 4928 | er32(GORCH); /* Clear gorc */ |
bc7f75fa AK |
4929 | adapter->stats.bprc += er32(BPRC); |
4930 | adapter->stats.mprc += er32(MPRC); | |
4931 | adapter->stats.roc += er32(ROC); | |
4932 | ||
bc7f75fa | 4933 | adapter->stats.mpc += er32(MPC); |
8c7bbb92 BA |
4934 | |
4935 | /* Half-duplex statistics */ | |
4936 | if (adapter->link_duplex == HALF_DUPLEX) { | |
4937 | if (adapter->flags2 & FLAG2_HAS_PHY_STATS) { | |
4938 | e1000e_update_phy_stats(adapter); | |
4939 | } else { | |
4940 | adapter->stats.scc += er32(SCC); | |
4941 | adapter->stats.ecol += er32(ECOL); | |
4942 | adapter->stats.mcc += er32(MCC); | |
4943 | adapter->stats.latecol += er32(LATECOL); | |
4944 | adapter->stats.dc += er32(DC); | |
4945 | ||
4946 | hw->mac.collision_delta = er32(COLC); | |
4947 | ||
4948 | if ((hw->mac.type != e1000_82574) && | |
4949 | (hw->mac.type != e1000_82583)) | |
4950 | adapter->stats.tncrs += er32(TNCRS); | |
4951 | } | |
4952 | adapter->stats.colc += hw->mac.collision_delta; | |
a4f58f54 | 4953 | } |
8c7bbb92 | 4954 | |
bc7f75fa AK |
4955 | adapter->stats.xonrxc += er32(XONRXC); |
4956 | adapter->stats.xontxc += er32(XONTXC); | |
4957 | adapter->stats.xoffrxc += er32(XOFFRXC); | |
4958 | adapter->stats.xofftxc += er32(XOFFTXC); | |
bc7f75fa | 4959 | adapter->stats.gptc += er32(GPTC); |
7c25769f | 4960 | adapter->stats.gotc += er32(GOTCL); |
e80bd1d1 | 4961 | er32(GOTCH); /* Clear gotc */ |
bc7f75fa AK |
4962 | adapter->stats.rnbc += er32(RNBC); |
4963 | adapter->stats.ruc += er32(RUC); | |
bc7f75fa AK |
4964 | |
4965 | adapter->stats.mptc += er32(MPTC); | |
4966 | adapter->stats.bptc += er32(BPTC); | |
4967 | ||
4968 | /* used for adaptive IFS */ | |
4969 | ||
4970 | hw->mac.tx_packet_delta = er32(TPT); | |
4971 | adapter->stats.tpt += hw->mac.tx_packet_delta; | |
bc7f75fa AK |
4972 | |
4973 | adapter->stats.algnerrc += er32(ALGNERRC); | |
4974 | adapter->stats.rxerrc += er32(RXERRC); | |
bc7f75fa AK |
4975 | adapter->stats.cexterr += er32(CEXTERR); |
4976 | adapter->stats.tsctc += er32(TSCTC); | |
4977 | adapter->stats.tsctfc += er32(TSCTFC); | |
4978 | ||
bc7f75fa | 4979 | /* Fill out the OS statistics structure */ |
7274c20f AK |
4980 | netdev->stats.multicast = adapter->stats.mprc; |
4981 | netdev->stats.collisions = adapter->stats.colc; | |
bc7f75fa AK |
4982 | |
4983 | /* Rx Errors */ | |
4984 | ||
e921eb1a | 4985 | /* RLEC on some newer hardware can be incorrect so build |
ad68076e BA |
4986 | * our own version based on RUC and ROC |
4987 | */ | |
7274c20f | 4988 | netdev->stats.rx_errors = adapter->stats.rxerrc + |
f0ff4398 BA |
4989 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
4990 | adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; | |
7274c20f | 4991 | netdev->stats.rx_length_errors = adapter->stats.ruc + |
f0ff4398 | 4992 | adapter->stats.roc; |
7274c20f AK |
4993 | netdev->stats.rx_crc_errors = adapter->stats.crcerrs; |
4994 | netdev->stats.rx_frame_errors = adapter->stats.algnerrc; | |
4995 | netdev->stats.rx_missed_errors = adapter->stats.mpc; | |
bc7f75fa AK |
4996 | |
4997 | /* Tx Errors */ | |
f0ff4398 | 4998 | netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol; |
7274c20f AK |
4999 | netdev->stats.tx_aborted_errors = adapter->stats.ecol; |
5000 | netdev->stats.tx_window_errors = adapter->stats.latecol; | |
5001 | netdev->stats.tx_carrier_errors = adapter->stats.tncrs; | |
bc7f75fa AK |
5002 | |
5003 | /* Tx Dropped needs to be maintained elsewhere */ | |
5004 | ||
bc7f75fa AK |
5005 | /* Management Stats */ |
5006 | adapter->stats.mgptc += er32(MGTPTC); | |
5007 | adapter->stats.mgprc += er32(MGTPRC); | |
5008 | adapter->stats.mgpdc += er32(MGTPDC); | |
94fb848b BA |
5009 | |
5010 | /* Correctable ECC Errors */ | |
c8744f44 | 5011 | if (hw->mac.type >= e1000_pch_lpt) { |
94fb848b | 5012 | u32 pbeccsts = er32(PBECCSTS); |
6cf08d1c | 5013 | |
94fb848b BA |
5014 | adapter->corr_errors += |
5015 | pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK; | |
5016 | adapter->uncorr_errors += | |
5017 | (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >> | |
5018 | E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT; | |
5019 | } | |
bc7f75fa AK |
5020 | } |
5021 | ||
7c25769f BA |
5022 | /** |
5023 | * e1000_phy_read_status - Update the PHY register status snapshot | |
5024 | * @adapter: board private structure | |
5025 | **/ | |
5026 | static void e1000_phy_read_status(struct e1000_adapter *adapter) | |
5027 | { | |
5028 | struct e1000_hw *hw = &adapter->hw; | |
5029 | struct e1000_phy_regs *phy = &adapter->phy_regs; | |
7c25769f | 5030 | |
97390ab8 BA |
5031 | if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) && |
5032 | (er32(STATUS) & E1000_STATUS_LU) && | |
7c25769f | 5033 | (adapter->hw.phy.media_type == e1000_media_type_copper)) { |
90da0669 BA |
5034 | int ret_val; |
5035 | ||
c2ade1a4 BA |
5036 | ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr); |
5037 | ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr); | |
5038 | ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise); | |
5039 | ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa); | |
5040 | ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion); | |
5041 | ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000); | |
5042 | ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000); | |
5043 | ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus); | |
7c25769f | 5044 | if (ret_val) |
44defeb3 | 5045 | e_warn("Error reading PHY register\n"); |
7c25769f | 5046 | } else { |
e921eb1a | 5047 | /* Do not read PHY registers if link is not up |
7c25769f BA |
5048 | * Set values to typical power-on defaults |
5049 | */ | |
5050 | phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX); | |
5051 | phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | | |
5052 | BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE | | |
5053 | BMSR_ERCAP); | |
5054 | phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP | | |
5055 | ADVERTISE_ALL | ADVERTISE_CSMA); | |
5056 | phy->lpa = 0; | |
5057 | phy->expansion = EXPANSION_ENABLENPAGE; | |
5058 | phy->ctrl1000 = ADVERTISE_1000FULL; | |
5059 | phy->stat1000 = 0; | |
5060 | phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF); | |
5061 | } | |
7c25769f BA |
5062 | } |
5063 | ||
bc7f75fa AK |
5064 | static void e1000_print_link_info(struct e1000_adapter *adapter) |
5065 | { | |
bc7f75fa AK |
5066 | struct e1000_hw *hw = &adapter->hw; |
5067 | u32 ctrl = er32(CTRL); | |
5068 | ||
8f12fe86 | 5069 | /* Link status message must follow this format for user tools */ |
7dbc1672 BA |
5070 | pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", |
5071 | adapter->netdev->name, adapter->link_speed, | |
ef456f85 JK |
5072 | adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half", |
5073 | (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" : | |
5074 | (ctrl & E1000_CTRL_RFCE) ? "Rx" : | |
5075 | (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None"); | |
bc7f75fa AK |
5076 | } |
5077 | ||
0c6bdb30 | 5078 | static bool e1000e_has_link(struct e1000_adapter *adapter) |
318a94d6 JK |
5079 | { |
5080 | struct e1000_hw *hw = &adapter->hw; | |
3db1cd5c | 5081 | bool link_active = false; |
318a94d6 JK |
5082 | s32 ret_val = 0; |
5083 | ||
e921eb1a | 5084 | /* get_link_status is set on LSC (link status) interrupt or |
318a94d6 | 5085 | * Rx sequence error interrupt. get_link_status will stay |
65a29da1 | 5086 | * true until the check_for_link establishes link |
318a94d6 JK |
5087 | * for copper adapters ONLY |
5088 | */ | |
5089 | switch (hw->phy.media_type) { | |
5090 | case e1000_media_type_copper: | |
5091 | if (hw->mac.get_link_status) { | |
5092 | ret_val = hw->mac.ops.check_for_link(hw); | |
19110cfb | 5093 | link_active = ret_val > 0; |
318a94d6 | 5094 | } else { |
3db1cd5c | 5095 | link_active = true; |
318a94d6 JK |
5096 | } |
5097 | break; | |
5098 | case e1000_media_type_fiber: | |
5099 | ret_val = hw->mac.ops.check_for_link(hw); | |
5100 | link_active = !!(er32(STATUS) & E1000_STATUS_LU); | |
5101 | break; | |
5102 | case e1000_media_type_internal_serdes: | |
5103 | ret_val = hw->mac.ops.check_for_link(hw); | |
65a29da1 | 5104 | link_active = hw->mac.serdes_has_link; |
318a94d6 JK |
5105 | break; |
5106 | default: | |
5107 | case e1000_media_type_unknown: | |
5108 | break; | |
5109 | } | |
5110 | ||
d3509f8b | 5111 | if ((ret_val == -E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) && |
318a94d6 JK |
5112 | (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) { |
5113 | /* See e1000_kmrn_lock_loss_workaround_ich8lan() */ | |
44defeb3 | 5114 | e_info("Gigabit has been disabled, downgrading speed\n"); |
318a94d6 JK |
5115 | } |
5116 | ||
5117 | return link_active; | |
5118 | } | |
5119 | ||
5120 | static void e1000e_enable_receives(struct e1000_adapter *adapter) | |
5121 | { | |
5122 | /* make sure the receive unit is started */ | |
5123 | if ((adapter->flags & FLAG_RX_NEEDS_RESTART) && | |
12d43f7d | 5124 | (adapter->flags & FLAG_RESTART_NOW)) { |
318a94d6 JK |
5125 | struct e1000_hw *hw = &adapter->hw; |
5126 | u32 rctl = er32(RCTL); | |
6cf08d1c | 5127 | |
318a94d6 | 5128 | ew32(RCTL, rctl | E1000_RCTL_EN); |
12d43f7d | 5129 | adapter->flags &= ~FLAG_RESTART_NOW; |
318a94d6 JK |
5130 | } |
5131 | } | |
5132 | ||
ff10e13c CW |
5133 | static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter) |
5134 | { | |
5135 | struct e1000_hw *hw = &adapter->hw; | |
5136 | ||
e921eb1a | 5137 | /* With 82574 controllers, PHY needs to be checked periodically |
ff10e13c CW |
5138 | * for hung state and reset, if two calls return true |
5139 | */ | |
5140 | if (e1000_check_phy_82574(hw)) | |
5141 | adapter->phy_hang_count++; | |
5142 | else | |
5143 | adapter->phy_hang_count = 0; | |
5144 | ||
5145 | if (adapter->phy_hang_count > 1) { | |
5146 | adapter->phy_hang_count = 0; | |
d9554e96 | 5147 | e_dbg("PHY appears hung - resetting\n"); |
ff10e13c CW |
5148 | schedule_work(&adapter->reset_task); |
5149 | } | |
5150 | } | |
5151 | ||
bc7f75fa AK |
5152 | /** |
5153 | * e1000_watchdog - Timer Call-back | |
5154 | * @data: pointer to adapter cast into an unsigned long | |
5155 | **/ | |
26566eae | 5156 | static void e1000_watchdog(struct timer_list *t) |
bc7f75fa | 5157 | { |
26566eae | 5158 | struct e1000_adapter *adapter = from_timer(adapter, t, watchdog_timer); |
bc7f75fa AK |
5159 | |
5160 | /* Do the rest outside of interrupt context */ | |
5161 | schedule_work(&adapter->watchdog_task); | |
5162 | ||
5163 | /* TODO: make this use queue_delayed_work() */ | |
5164 | } | |
5165 | ||
5166 | static void e1000_watchdog_task(struct work_struct *work) | |
5167 | { | |
5168 | struct e1000_adapter *adapter = container_of(work, | |
17e813ec BA |
5169 | struct e1000_adapter, |
5170 | watchdog_task); | |
bc7f75fa AK |
5171 | struct net_device *netdev = adapter->netdev; |
5172 | struct e1000_mac_info *mac = &adapter->hw.mac; | |
75eb0fad | 5173 | struct e1000_phy_info *phy = &adapter->hw.phy; |
bc7f75fa AK |
5174 | struct e1000_ring *tx_ring = adapter->tx_ring; |
5175 | struct e1000_hw *hw = &adapter->hw; | |
5176 | u32 link, tctl; | |
bc7f75fa | 5177 | |
615b32af JB |
5178 | if (test_bit(__E1000_DOWN, &adapter->state)) |
5179 | return; | |
5180 | ||
b405e8df | 5181 | link = e1000e_has_link(adapter); |
318a94d6 | 5182 | if ((netif_carrier_ok(netdev)) && link) { |
23606cf5 RW |
5183 | /* Cancel scheduled suspend requests. */ |
5184 | pm_runtime_resume(netdev->dev.parent); | |
5185 | ||
318a94d6 | 5186 | e1000e_enable_receives(adapter); |
bc7f75fa | 5187 | goto link_up; |
bc7f75fa AK |
5188 | } |
5189 | ||
5190 | if ((e1000e_enable_tx_pkt_filtering(hw)) && | |
5191 | (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id)) | |
5192 | e1000_update_mng_vlan(adapter); | |
5193 | ||
bc7f75fa AK |
5194 | if (link) { |
5195 | if (!netif_carrier_ok(netdev)) { | |
3db1cd5c | 5196 | bool txb2b = true; |
23606cf5 RW |
5197 | |
5198 | /* Cancel scheduled suspend requests. */ | |
5199 | pm_runtime_resume(netdev->dev.parent); | |
5200 | ||
318a94d6 | 5201 | /* update snapshot of PHY registers on LSC */ |
7c25769f | 5202 | e1000_phy_read_status(adapter); |
bc7f75fa | 5203 | mac->ops.get_link_up_info(&adapter->hw, |
17e813ec BA |
5204 | &adapter->link_speed, |
5205 | &adapter->link_duplex); | |
bc7f75fa | 5206 | e1000_print_link_info(adapter); |
e792cd91 KS |
5207 | |
5208 | /* check if SmartSpeed worked */ | |
5209 | e1000e_check_downshift(hw); | |
5210 | if (phy->speed_downgraded) | |
5211 | netdev_warn(netdev, | |
5212 | "Link Speed was downgraded by SmartSpeed\n"); | |
5213 | ||
e921eb1a | 5214 | /* On supported PHYs, check for duplex mismatch only |
f4187b56 BA |
5215 | * if link has autonegotiated at 10/100 half |
5216 | */ | |
5217 | if ((hw->phy.type == e1000_phy_igp_3 || | |
5218 | hw->phy.type == e1000_phy_bm) && | |
138953bb | 5219 | hw->mac.autoneg && |
f4187b56 BA |
5220 | (adapter->link_speed == SPEED_10 || |
5221 | adapter->link_speed == SPEED_100) && | |
5222 | (adapter->link_duplex == HALF_DUPLEX)) { | |
5223 | u16 autoneg_exp; | |
5224 | ||
c2ade1a4 | 5225 | e1e_rphy(hw, MII_EXPANSION, &autoneg_exp); |
f4187b56 | 5226 | |
c2ade1a4 | 5227 | if (!(autoneg_exp & EXPANSION_NWAY)) |
ef456f85 | 5228 | e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n"); |
f4187b56 BA |
5229 | } |
5230 | ||
f49c57e1 | 5231 | /* adjust timeout factor according to speed/duplex */ |
bc7f75fa AK |
5232 | adapter->tx_timeout_factor = 1; |
5233 | switch (adapter->link_speed) { | |
5234 | case SPEED_10: | |
3db1cd5c | 5235 | txb2b = false; |
10f1b492 | 5236 | adapter->tx_timeout_factor = 16; |
bc7f75fa AK |
5237 | break; |
5238 | case SPEED_100: | |
3db1cd5c | 5239 | txb2b = false; |
4c86e0b9 | 5240 | adapter->tx_timeout_factor = 10; |
bc7f75fa AK |
5241 | break; |
5242 | } | |
5243 | ||
e921eb1a | 5244 | /* workaround: re-program speed mode bit after |
ad68076e BA |
5245 | * link-up event |
5246 | */ | |
bc7f75fa AK |
5247 | if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) && |
5248 | !txb2b) { | |
5249 | u32 tarc0; | |
6cf08d1c | 5250 | |
e9ec2c0f | 5251 | tarc0 = er32(TARC(0)); |
bc7f75fa | 5252 | tarc0 &= ~SPEED_MODE_BIT; |
e9ec2c0f | 5253 | ew32(TARC(0), tarc0); |
bc7f75fa AK |
5254 | } |
5255 | ||
e921eb1a | 5256 | /* disable TSO for pcie and 10/100 speeds, to avoid |
ad68076e BA |
5257 | * some hardware issues |
5258 | */ | |
bc7f75fa AK |
5259 | if (!(adapter->flags & FLAG_TSO_FORCE)) { |
5260 | switch (adapter->link_speed) { | |
5261 | case SPEED_10: | |
5262 | case SPEED_100: | |
44defeb3 | 5263 | e_info("10/100 speed: disabling TSO\n"); |
bc7f75fa AK |
5264 | netdev->features &= ~NETIF_F_TSO; |
5265 | netdev->features &= ~NETIF_F_TSO6; | |
5266 | break; | |
5267 | case SPEED_1000: | |
5268 | netdev->features |= NETIF_F_TSO; | |
5269 | netdev->features |= NETIF_F_TSO6; | |
5270 | break; | |
5271 | default: | |
5272 | /* oops */ | |
5273 | break; | |
5274 | } | |
5275 | } | |
5276 | ||
e921eb1a | 5277 | /* enable transmits in the hardware, need to do this |
ad68076e BA |
5278 | * after setting TARC(0) |
5279 | */ | |
bc7f75fa AK |
5280 | tctl = er32(TCTL); |
5281 | tctl |= E1000_TCTL_EN; | |
5282 | ew32(TCTL, tctl); | |
5283 | ||
e921eb1a | 5284 | /* Perform any post-link-up configuration before |
75eb0fad BA |
5285 | * reporting link up. |
5286 | */ | |
5287 | if (phy->ops.cfg_on_link_up) | |
5288 | phy->ops.cfg_on_link_up(hw); | |
5289 | ||
bc7f75fa | 5290 | netif_carrier_on(netdev); |
bc7f75fa AK |
5291 | |
5292 | if (!test_bit(__E1000_DOWN, &adapter->state)) | |
5293 | mod_timer(&adapter->phy_info_timer, | |
5294 | round_jiffies(jiffies + 2 * HZ)); | |
bc7f75fa AK |
5295 | } |
5296 | } else { | |
5297 | if (netif_carrier_ok(netdev)) { | |
5298 | adapter->link_speed = 0; | |
5299 | adapter->link_duplex = 0; | |
8f12fe86 | 5300 | /* Link status message must follow this format */ |
7dbc1672 | 5301 | pr_info("%s NIC Link is Down\n", adapter->netdev->name); |
bc7f75fa | 5302 | netif_carrier_off(netdev); |
bc7f75fa AK |
5303 | if (!test_bit(__E1000_DOWN, &adapter->state)) |
5304 | mod_timer(&adapter->phy_info_timer, | |
5305 | round_jiffies(jiffies + 2 * HZ)); | |
5306 | ||
d9554e96 DE |
5307 | /* 8000ES2LAN requires a Rx packet buffer work-around |
5308 | * on link down event; reset the controller to flush | |
5309 | * the Rx packet buffer. | |
12d43f7d | 5310 | */ |
d9554e96 | 5311 | if (adapter->flags & FLAG_RX_NEEDS_RESTART) |
12d43f7d | 5312 | adapter->flags |= FLAG_RESTART_NOW; |
23606cf5 RW |
5313 | else |
5314 | pm_schedule_suspend(netdev->dev.parent, | |
17e813ec | 5315 | LINK_TIMEOUT); |
bc7f75fa AK |
5316 | } |
5317 | } | |
5318 | ||
5319 | link_up: | |
67fd4fcb | 5320 | spin_lock(&adapter->stats64_lock); |
bc7f75fa AK |
5321 | e1000e_update_stats(adapter); |
5322 | ||
5323 | mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old; | |
5324 | adapter->tpt_old = adapter->stats.tpt; | |
5325 | mac->collision_delta = adapter->stats.colc - adapter->colc_old; | |
5326 | adapter->colc_old = adapter->stats.colc; | |
5327 | ||
7c25769f BA |
5328 | adapter->gorc = adapter->stats.gorc - adapter->gorc_old; |
5329 | adapter->gorc_old = adapter->stats.gorc; | |
5330 | adapter->gotc = adapter->stats.gotc - adapter->gotc_old; | |
5331 | adapter->gotc_old = adapter->stats.gotc; | |
2084b114 | 5332 | spin_unlock(&adapter->stats64_lock); |
bc7f75fa | 5333 | |
d9554e96 DE |
5334 | /* If the link is lost the controller stops DMA, but |
5335 | * if there is queued Tx work it cannot be done. So | |
5336 | * reset the controller to flush the Tx packet buffers. | |
5337 | */ | |
5338 | if (!netif_carrier_ok(netdev) && | |
5339 | (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) | |
5340 | adapter->flags |= FLAG_RESTART_NOW; | |
5341 | ||
5342 | /* If reset is necessary, do it outside of interrupt context. */ | |
12d43f7d | 5343 | if (adapter->flags & FLAG_RESTART_NOW) { |
90da0669 BA |
5344 | schedule_work(&adapter->reset_task); |
5345 | /* return immediately since reset is imminent */ | |
5346 | return; | |
bc7f75fa AK |
5347 | } |
5348 | ||
12d43f7d BA |
5349 | e1000e_update_adaptive(&adapter->hw); |
5350 | ||
eab2abf5 JB |
5351 | /* Simple mode for Interrupt Throttle Rate (ITR) */ |
5352 | if (adapter->itr_setting == 4) { | |
e921eb1a | 5353 | /* Symmetric Tx/Rx gets a reduced ITR=2000; |
eab2abf5 JB |
5354 | * Total asymmetrical Tx or Rx gets ITR=8000; |
5355 | * everyone else is between 2000-8000. | |
5356 | */ | |
5357 | u32 goc = (adapter->gotc + adapter->gorc) / 10000; | |
5358 | u32 dif = (adapter->gotc > adapter->gorc ? | |
17e813ec BA |
5359 | adapter->gotc - adapter->gorc : |
5360 | adapter->gorc - adapter->gotc) / 10000; | |
eab2abf5 JB |
5361 | u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000; |
5362 | ||
22a4cca2 | 5363 | e1000e_write_itr(adapter, itr); |
eab2abf5 JB |
5364 | } |
5365 | ||
ad68076e | 5366 | /* Cause software interrupt to ensure Rx ring is cleaned */ |
4662e82b BA |
5367 | if (adapter->msix_entries) |
5368 | ew32(ICS, adapter->rx_ring->ims_val); | |
5369 | else | |
5370 | ew32(ICS, E1000_ICS_RXDMT0); | |
bc7f75fa | 5371 | |
713b3c9e JB |
5372 | /* flush pending descriptors to memory before detecting Tx hang */ |
5373 | e1000e_flush_descriptors(adapter); | |
5374 | ||
bc7f75fa | 5375 | /* Force detection of hung controller every watchdog period */ |
3db1cd5c | 5376 | adapter->detect_tx_hung = true; |
bc7f75fa | 5377 | |
e921eb1a | 5378 | /* With 82571 controllers, LAA may be overwritten due to controller |
ad68076e BA |
5379 | * reset from the other port. Set the appropriate LAA in RAR[0] |
5380 | */ | |
bc7f75fa | 5381 | if (e1000e_get_laa_state_82571(hw)) |
69e1e019 | 5382 | hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0); |
bc7f75fa | 5383 | |
ff10e13c CW |
5384 | if (adapter->flags2 & FLAG2_CHECK_PHY_HANG) |
5385 | e1000e_check_82574_phy_workaround(adapter); | |
5386 | ||
b67e1913 BA |
5387 | /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */ |
5388 | if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) { | |
5389 | if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) && | |
5390 | (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) { | |
5391 | er32(RXSTMPH); | |
5392 | adapter->rx_hwtstamp_cleared++; | |
5393 | } else { | |
5394 | adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP; | |
5395 | } | |
5396 | } | |
5397 | ||
bc7f75fa AK |
5398 | /* Reset the timer */ |
5399 | if (!test_bit(__E1000_DOWN, &adapter->state)) | |
5400 | mod_timer(&adapter->watchdog_timer, | |
5401 | round_jiffies(jiffies + 2 * HZ)); | |
5402 | } | |
5403 | ||
5404 | #define E1000_TX_FLAGS_CSUM 0x00000001 | |
5405 | #define E1000_TX_FLAGS_VLAN 0x00000002 | |
5406 | #define E1000_TX_FLAGS_TSO 0x00000004 | |
5407 | #define E1000_TX_FLAGS_IPV4 0x00000008 | |
943146de | 5408 | #define E1000_TX_FLAGS_NO_FCS 0x00000010 |
b67e1913 | 5409 | #define E1000_TX_FLAGS_HWTSTAMP 0x00000020 |
bc7f75fa AK |
5410 | #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000 |
5411 | #define E1000_TX_FLAGS_VLAN_SHIFT 16 | |
5412 | ||
47ccd1ed VY |
5413 | static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb, |
5414 | __be16 protocol) | |
bc7f75fa | 5415 | { |
bc7f75fa AK |
5416 | struct e1000_context_desc *context_desc; |
5417 | struct e1000_buffer *buffer_info; | |
5418 | unsigned int i; | |
5419 | u32 cmd_length = 0; | |
70443ae9 | 5420 | u16 ipcse = 0, mss; |
bc7f75fa | 5421 | u8 ipcss, ipcso, tucss, tucso, hdr_len; |
bcf1f57f | 5422 | int err; |
bc7f75fa | 5423 | |
3d5e33c9 BA |
5424 | if (!skb_is_gso(skb)) |
5425 | return 0; | |
bc7f75fa | 5426 | |
bcf1f57f FR |
5427 | err = skb_cow_head(skb, 0); |
5428 | if (err < 0) | |
5429 | return err; | |
bc7f75fa | 5430 | |
3d5e33c9 BA |
5431 | hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
5432 | mss = skb_shinfo(skb)->gso_size; | |
47ccd1ed | 5433 | if (protocol == htons(ETH_P_IP)) { |
3d5e33c9 BA |
5434 | struct iphdr *iph = ip_hdr(skb); |
5435 | iph->tot_len = 0; | |
5436 | iph->check = 0; | |
5437 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, | |
f0ff4398 | 5438 | 0, IPPROTO_TCP, 0); |
3d5e33c9 BA |
5439 | cmd_length = E1000_TXD_CMD_IP; |
5440 | ipcse = skb_transport_offset(skb) - 1; | |
8e1e8a47 | 5441 | } else if (skb_is_gso_v6(skb)) { |
3d5e33c9 BA |
5442 | ipv6_hdr(skb)->payload_len = 0; |
5443 | tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
f0ff4398 BA |
5444 | &ipv6_hdr(skb)->daddr, |
5445 | 0, IPPROTO_TCP, 0); | |
3d5e33c9 BA |
5446 | ipcse = 0; |
5447 | } | |
5448 | ipcss = skb_network_offset(skb); | |
5449 | ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data; | |
5450 | tucss = skb_transport_offset(skb); | |
5451 | tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data; | |
3d5e33c9 BA |
5452 | |
5453 | cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE | | |
f0ff4398 | 5454 | E1000_TXD_CMD_TCP | (skb->len - (hdr_len))); |
3d5e33c9 BA |
5455 | |
5456 | i = tx_ring->next_to_use; | |
5457 | context_desc = E1000_CONTEXT_DESC(*tx_ring, i); | |
5458 | buffer_info = &tx_ring->buffer_info[i]; | |
5459 | ||
e80bd1d1 BA |
5460 | context_desc->lower_setup.ip_fields.ipcss = ipcss; |
5461 | context_desc->lower_setup.ip_fields.ipcso = ipcso; | |
5462 | context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse); | |
3d5e33c9 BA |
5463 | context_desc->upper_setup.tcp_fields.tucss = tucss; |
5464 | context_desc->upper_setup.tcp_fields.tucso = tucso; | |
70443ae9 | 5465 | context_desc->upper_setup.tcp_fields.tucse = 0; |
e80bd1d1 | 5466 | context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss); |
3d5e33c9 BA |
5467 | context_desc->tcp_seg_setup.fields.hdr_len = hdr_len; |
5468 | context_desc->cmd_and_length = cpu_to_le32(cmd_length); | |
5469 | ||
5470 | buffer_info->time_stamp = jiffies; | |
5471 | buffer_info->next_to_watch = i; | |
5472 | ||
5473 | i++; | |
5474 | if (i == tx_ring->count) | |
5475 | i = 0; | |
5476 | tx_ring->next_to_use = i; | |
5477 | ||
5478 | return 1; | |
bc7f75fa AK |
5479 | } |
5480 | ||
47ccd1ed VY |
5481 | static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb, |
5482 | __be16 protocol) | |
bc7f75fa | 5483 | { |
55aa6985 | 5484 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa AK |
5485 | struct e1000_context_desc *context_desc; |
5486 | struct e1000_buffer *buffer_info; | |
5487 | unsigned int i; | |
5488 | u8 css; | |
af807c82 | 5489 | u32 cmd_len = E1000_TXD_CMD_DEXT; |
bc7f75fa | 5490 | |
af807c82 | 5491 | if (skb->ip_summed != CHECKSUM_PARTIAL) |
3992c8ed | 5492 | return false; |
bc7f75fa | 5493 | |
3f518390 | 5494 | switch (protocol) { |
09640e63 | 5495 | case cpu_to_be16(ETH_P_IP): |
af807c82 DG |
5496 | if (ip_hdr(skb)->protocol == IPPROTO_TCP) |
5497 | cmd_len |= E1000_TXD_CMD_TCP; | |
5498 | break; | |
09640e63 | 5499 | case cpu_to_be16(ETH_P_IPV6): |
af807c82 DG |
5500 | /* XXX not handling all IPV6 headers */ |
5501 | if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP) | |
5502 | cmd_len |= E1000_TXD_CMD_TCP; | |
5503 | break; | |
5504 | default: | |
5505 | if (unlikely(net_ratelimit())) | |
5f66f208 AJ |
5506 | e_warn("checksum_partial proto=%x!\n", |
5507 | be16_to_cpu(protocol)); | |
af807c82 | 5508 | break; |
bc7f75fa AK |
5509 | } |
5510 | ||
0d0b1672 | 5511 | css = skb_checksum_start_offset(skb); |
af807c82 DG |
5512 | |
5513 | i = tx_ring->next_to_use; | |
5514 | buffer_info = &tx_ring->buffer_info[i]; | |
5515 | context_desc = E1000_CONTEXT_DESC(*tx_ring, i); | |
5516 | ||
5517 | context_desc->lower_setup.ip_config = 0; | |
5518 | context_desc->upper_setup.tcp_fields.tucss = css; | |
f0ff4398 | 5519 | context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset; |
af807c82 DG |
5520 | context_desc->upper_setup.tcp_fields.tucse = 0; |
5521 | context_desc->tcp_seg_setup.data = 0; | |
5522 | context_desc->cmd_and_length = cpu_to_le32(cmd_len); | |
5523 | ||
5524 | buffer_info->time_stamp = jiffies; | |
5525 | buffer_info->next_to_watch = i; | |
5526 | ||
5527 | i++; | |
5528 | if (i == tx_ring->count) | |
5529 | i = 0; | |
5530 | tx_ring->next_to_use = i; | |
5531 | ||
3992c8ed | 5532 | return true; |
bc7f75fa AK |
5533 | } |
5534 | ||
55aa6985 BA |
5535 | static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb, |
5536 | unsigned int first, unsigned int max_per_txd, | |
d821a4c4 | 5537 | unsigned int nr_frags) |
bc7f75fa | 5538 | { |
55aa6985 | 5539 | struct e1000_adapter *adapter = tx_ring->adapter; |
03b1320d | 5540 | struct pci_dev *pdev = adapter->pdev; |
1b7719c4 | 5541 | struct e1000_buffer *buffer_info; |
8ddc951c | 5542 | unsigned int len = skb_headlen(skb); |
03b1320d | 5543 | unsigned int offset = 0, size, count = 0, i; |
9ed318d5 | 5544 | unsigned int f, bytecount, segs; |
bc7f75fa AK |
5545 | |
5546 | i = tx_ring->next_to_use; | |
5547 | ||
5548 | while (len) { | |
1b7719c4 | 5549 | buffer_info = &tx_ring->buffer_info[i]; |
bc7f75fa AK |
5550 | size = min(len, max_per_txd); |
5551 | ||
bc7f75fa | 5552 | buffer_info->length = size; |
bc7f75fa | 5553 | buffer_info->time_stamp = jiffies; |
bc7f75fa | 5554 | buffer_info->next_to_watch = i; |
0be3f55f NN |
5555 | buffer_info->dma = dma_map_single(&pdev->dev, |
5556 | skb->data + offset, | |
af667a29 | 5557 | size, DMA_TO_DEVICE); |
03b1320d | 5558 | buffer_info->mapped_as_page = false; |
0be3f55f | 5559 | if (dma_mapping_error(&pdev->dev, buffer_info->dma)) |
03b1320d | 5560 | goto dma_error; |
bc7f75fa AK |
5561 | |
5562 | len -= size; | |
5563 | offset += size; | |
03b1320d | 5564 | count++; |
1b7719c4 AD |
5565 | |
5566 | if (len) { | |
5567 | i++; | |
5568 | if (i == tx_ring->count) | |
5569 | i = 0; | |
5570 | } | |
bc7f75fa AK |
5571 | } |
5572 | ||
5573 | for (f = 0; f < nr_frags; f++) { | |
9e903e08 | 5574 | const struct skb_frag_struct *frag; |
bc7f75fa AK |
5575 | |
5576 | frag = &skb_shinfo(skb)->frags[f]; | |
9e903e08 | 5577 | len = skb_frag_size(frag); |
877749bf | 5578 | offset = 0; |
bc7f75fa AK |
5579 | |
5580 | while (len) { | |
1b7719c4 AD |
5581 | i++; |
5582 | if (i == tx_ring->count) | |
5583 | i = 0; | |
5584 | ||
bc7f75fa AK |
5585 | buffer_info = &tx_ring->buffer_info[i]; |
5586 | size = min(len, max_per_txd); | |
bc7f75fa AK |
5587 | |
5588 | buffer_info->length = size; | |
5589 | buffer_info->time_stamp = jiffies; | |
bc7f75fa | 5590 | buffer_info->next_to_watch = i; |
877749bf | 5591 | buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag, |
17e813ec BA |
5592 | offset, size, |
5593 | DMA_TO_DEVICE); | |
03b1320d | 5594 | buffer_info->mapped_as_page = true; |
0be3f55f | 5595 | if (dma_mapping_error(&pdev->dev, buffer_info->dma)) |
03b1320d | 5596 | goto dma_error; |
bc7f75fa AK |
5597 | |
5598 | len -= size; | |
5599 | offset += size; | |
5600 | count++; | |
bc7f75fa AK |
5601 | } |
5602 | } | |
5603 | ||
af667a29 | 5604 | segs = skb_shinfo(skb)->gso_segs ? : 1; |
9ed318d5 TH |
5605 | /* multiply data chunks by size of headers */ |
5606 | bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len; | |
5607 | ||
bc7f75fa | 5608 | tx_ring->buffer_info[i].skb = skb; |
9ed318d5 TH |
5609 | tx_ring->buffer_info[i].segs = segs; |
5610 | tx_ring->buffer_info[i].bytecount = bytecount; | |
bc7f75fa AK |
5611 | tx_ring->buffer_info[first].next_to_watch = i; |
5612 | ||
5613 | return count; | |
03b1320d AD |
5614 | |
5615 | dma_error: | |
af667a29 | 5616 | dev_err(&pdev->dev, "Tx DMA map failed\n"); |
03b1320d | 5617 | buffer_info->dma = 0; |
c1fa347f | 5618 | if (count) |
03b1320d | 5619 | count--; |
c1fa347f RK |
5620 | |
5621 | while (count--) { | |
af667a29 | 5622 | if (i == 0) |
03b1320d | 5623 | i += tx_ring->count; |
c1fa347f | 5624 | i--; |
03b1320d | 5625 | buffer_info = &tx_ring->buffer_info[i]; |
377b6273 | 5626 | e1000_put_txbuf(tx_ring, buffer_info, true); |
03b1320d AD |
5627 | } |
5628 | ||
5629 | return 0; | |
bc7f75fa AK |
5630 | } |
5631 | ||
55aa6985 | 5632 | static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count) |
bc7f75fa | 5633 | { |
55aa6985 | 5634 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa AK |
5635 | struct e1000_tx_desc *tx_desc = NULL; |
5636 | struct e1000_buffer *buffer_info; | |
5637 | u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS; | |
5638 | unsigned int i; | |
5639 | ||
5640 | if (tx_flags & E1000_TX_FLAGS_TSO) { | |
5641 | txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D | | |
f0ff4398 | 5642 | E1000_TXD_CMD_TSE; |
bc7f75fa AK |
5643 | txd_upper |= E1000_TXD_POPTS_TXSM << 8; |
5644 | ||
5645 | if (tx_flags & E1000_TX_FLAGS_IPV4) | |
5646 | txd_upper |= E1000_TXD_POPTS_IXSM << 8; | |
5647 | } | |
5648 | ||
5649 | if (tx_flags & E1000_TX_FLAGS_CSUM) { | |
5650 | txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; | |
5651 | txd_upper |= E1000_TXD_POPTS_TXSM << 8; | |
5652 | } | |
5653 | ||
5654 | if (tx_flags & E1000_TX_FLAGS_VLAN) { | |
5655 | txd_lower |= E1000_TXD_CMD_VLE; | |
5656 | txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK); | |
5657 | } | |
5658 | ||
943146de BG |
5659 | if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) |
5660 | txd_lower &= ~(E1000_TXD_CMD_IFCS); | |
5661 | ||
b67e1913 BA |
5662 | if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) { |
5663 | txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D; | |
5664 | txd_upper |= E1000_TXD_EXTCMD_TSTAMP; | |
5665 | } | |
5666 | ||
bc7f75fa AK |
5667 | i = tx_ring->next_to_use; |
5668 | ||
36b973df | 5669 | do { |
bc7f75fa AK |
5670 | buffer_info = &tx_ring->buffer_info[i]; |
5671 | tx_desc = E1000_TX_DESC(*tx_ring, i); | |
5672 | tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma); | |
f0ff4398 BA |
5673 | tx_desc->lower.data = cpu_to_le32(txd_lower | |
5674 | buffer_info->length); | |
bc7f75fa AK |
5675 | tx_desc->upper.data = cpu_to_le32(txd_upper); |
5676 | ||
5677 | i++; | |
5678 | if (i == tx_ring->count) | |
5679 | i = 0; | |
36b973df | 5680 | } while (--count > 0); |
bc7f75fa AK |
5681 | |
5682 | tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd); | |
5683 | ||
943146de BG |
5684 | /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */ |
5685 | if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS)) | |
5686 | tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS)); | |
5687 | ||
e921eb1a | 5688 | /* Force memory writes to complete before letting h/w |
bc7f75fa AK |
5689 | * know there are new descriptors to fetch. (Only |
5690 | * applicable for weak-ordered memory model archs, | |
ad68076e BA |
5691 | * such as IA-64). |
5692 | */ | |
bc7f75fa AK |
5693 | wmb(); |
5694 | ||
5695 | tx_ring->next_to_use = i; | |
bc7f75fa AK |
5696 | } |
5697 | ||
5698 | #define MINIMUM_DHCP_PACKET_SIZE 282 | |
5699 | static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter, | |
5700 | struct sk_buff *skb) | |
5701 | { | |
e80bd1d1 | 5702 | struct e1000_hw *hw = &adapter->hw; |
bc7f75fa AK |
5703 | u16 length, offset; |
5704 | ||
df8a39de JP |
5705 | if (skb_vlan_tag_present(skb) && |
5706 | !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) && | |
d60923c4 BA |
5707 | (adapter->hw.mng_cookie.status & |
5708 | E1000_MNG_DHCP_COOKIE_STATUS_VLAN))) | |
5709 | return 0; | |
bc7f75fa AK |
5710 | |
5711 | if (skb->len <= MINIMUM_DHCP_PACKET_SIZE) | |
5712 | return 0; | |
5713 | ||
53aa82da | 5714 | if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP)) |
bc7f75fa AK |
5715 | return 0; |
5716 | ||
5717 | { | |
362e20ca | 5718 | const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14); |
bc7f75fa AK |
5719 | struct udphdr *udp; |
5720 | ||
5721 | if (ip->protocol != IPPROTO_UDP) | |
5722 | return 0; | |
5723 | ||
5724 | udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2)); | |
5725 | if (ntohs(udp->dest) != 67) | |
5726 | return 0; | |
5727 | ||
5728 | offset = (u8 *)udp + 8 - skb->data; | |
5729 | length = skb->len - offset; | |
5730 | return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length); | |
5731 | } | |
5732 | ||
5733 | return 0; | |
5734 | } | |
5735 | ||
55aa6985 | 5736 | static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) |
bc7f75fa | 5737 | { |
55aa6985 | 5738 | struct e1000_adapter *adapter = tx_ring->adapter; |
bc7f75fa | 5739 | |
55aa6985 | 5740 | netif_stop_queue(adapter->netdev); |
e921eb1a | 5741 | /* Herbert's original patch had: |
bc7f75fa | 5742 | * smp_mb__after_netif_stop_queue(); |
ad68076e BA |
5743 | * but since that doesn't exist yet, just open code it. |
5744 | */ | |
bc7f75fa AK |
5745 | smp_mb(); |
5746 | ||
e921eb1a | 5747 | /* We need to check again in a case another CPU has just |
ad68076e BA |
5748 | * made room available. |
5749 | */ | |
55aa6985 | 5750 | if (e1000_desc_unused(tx_ring) < size) |
bc7f75fa AK |
5751 | return -EBUSY; |
5752 | ||
5753 | /* A reprieve! */ | |
55aa6985 | 5754 | netif_start_queue(adapter->netdev); |
bc7f75fa AK |
5755 | ++adapter->restart_queue; |
5756 | return 0; | |
5757 | } | |
5758 | ||
55aa6985 | 5759 | static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size) |
bc7f75fa | 5760 | { |
d821a4c4 BA |
5761 | BUG_ON(size > tx_ring->count); |
5762 | ||
55aa6985 | 5763 | if (e1000_desc_unused(tx_ring) >= size) |
bc7f75fa | 5764 | return 0; |
55aa6985 | 5765 | return __e1000_maybe_stop_tx(tx_ring, size); |
bc7f75fa AK |
5766 | } |
5767 | ||
3b29a56d SH |
5768 | static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb, |
5769 | struct net_device *netdev) | |
bc7f75fa AK |
5770 | { |
5771 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
5772 | struct e1000_ring *tx_ring = adapter->tx_ring; | |
5773 | unsigned int first; | |
bc7f75fa | 5774 | unsigned int tx_flags = 0; |
e743d313 | 5775 | unsigned int len = skb_headlen(skb); |
4e6c709c AK |
5776 | unsigned int nr_frags; |
5777 | unsigned int mss; | |
bc7f75fa AK |
5778 | int count = 0; |
5779 | int tso; | |
5780 | unsigned int f; | |
47ccd1ed | 5781 | __be16 protocol = vlan_get_protocol(skb); |
bc7f75fa AK |
5782 | |
5783 | if (test_bit(__E1000_DOWN, &adapter->state)) { | |
5784 | dev_kfree_skb_any(skb); | |
5785 | return NETDEV_TX_OK; | |
5786 | } | |
5787 | ||
5788 | if (skb->len <= 0) { | |
5789 | dev_kfree_skb_any(skb); | |
5790 | return NETDEV_TX_OK; | |
5791 | } | |
5792 | ||
e921eb1a | 5793 | /* The minimum packet size with TCTL.PSP set is 17 bytes so |
6e97c170 TD |
5794 | * pad skb in order to meet this minimum size requirement |
5795 | */ | |
a94d9e22 AD |
5796 | if (skb_put_padto(skb, 17)) |
5797 | return NETDEV_TX_OK; | |
6e97c170 | 5798 | |
bc7f75fa | 5799 | mss = skb_shinfo(skb)->gso_size; |
bc7f75fa AK |
5800 | if (mss) { |
5801 | u8 hdr_len; | |
bc7f75fa | 5802 | |
e921eb1a | 5803 | /* TSO Workaround for 82571/2/3 Controllers -- if skb->data |
ad68076e BA |
5804 | * points to just header, pull a few bytes of payload from |
5805 | * frags into skb->data | |
5806 | */ | |
bc7f75fa | 5807 | hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); |
e921eb1a | 5808 | /* we do this workaround for ES2LAN, but it is un-necessary, |
ad68076e BA |
5809 | * avoiding it could save a lot of cycles |
5810 | */ | |
4e6c709c | 5811 | if (skb->data_len && (hdr_len == len)) { |
bc7f75fa AK |
5812 | unsigned int pull_size; |
5813 | ||
a2a5b323 | 5814 | pull_size = min_t(unsigned int, 4, skb->data_len); |
bc7f75fa | 5815 | if (!__pskb_pull_tail(skb, pull_size)) { |
44defeb3 | 5816 | e_err("__pskb_pull_tail failed.\n"); |
bc7f75fa AK |
5817 | dev_kfree_skb_any(skb); |
5818 | return NETDEV_TX_OK; | |
5819 | } | |
e743d313 | 5820 | len = skb_headlen(skb); |
bc7f75fa AK |
5821 | } |
5822 | } | |
5823 | ||
5824 | /* reserve a descriptor for the offload context */ | |
5825 | if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL)) | |
5826 | count++; | |
5827 | count++; | |
5828 | ||
d821a4c4 | 5829 | count += DIV_ROUND_UP(len, adapter->tx_fifo_limit); |
bc7f75fa AK |
5830 | |
5831 | nr_frags = skb_shinfo(skb)->nr_frags; | |
5832 | for (f = 0; f < nr_frags; f++) | |
d821a4c4 BA |
5833 | count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]), |
5834 | adapter->tx_fifo_limit); | |
bc7f75fa AK |
5835 | |
5836 | if (adapter->hw.mac.tx_pkt_filtering) | |
5837 | e1000_transfer_dhcp_info(adapter, skb); | |
5838 | ||
e921eb1a | 5839 | /* need: count + 2 desc gap to keep tail from touching |
ad68076e BA |
5840 | * head, otherwise try next time |
5841 | */ | |
55aa6985 | 5842 | if (e1000_maybe_stop_tx(tx_ring, count + 2)) |
bc7f75fa | 5843 | return NETDEV_TX_BUSY; |
bc7f75fa | 5844 | |
df8a39de | 5845 | if (skb_vlan_tag_present(skb)) { |
bc7f75fa | 5846 | tx_flags |= E1000_TX_FLAGS_VLAN; |
df8a39de JP |
5847 | tx_flags |= (skb_vlan_tag_get(skb) << |
5848 | E1000_TX_FLAGS_VLAN_SHIFT); | |
bc7f75fa AK |
5849 | } |
5850 | ||
5851 | first = tx_ring->next_to_use; | |
5852 | ||
47ccd1ed | 5853 | tso = e1000_tso(tx_ring, skb, protocol); |
bc7f75fa AK |
5854 | if (tso < 0) { |
5855 | dev_kfree_skb_any(skb); | |
bc7f75fa AK |
5856 | return NETDEV_TX_OK; |
5857 | } | |
5858 | ||
5859 | if (tso) | |
5860 | tx_flags |= E1000_TX_FLAGS_TSO; | |
47ccd1ed | 5861 | else if (e1000_tx_csum(tx_ring, skb, protocol)) |
bc7f75fa AK |
5862 | tx_flags |= E1000_TX_FLAGS_CSUM; |
5863 | ||
e921eb1a | 5864 | /* Old method was to assume IPv4 packet by default if TSO was enabled. |
bc7f75fa | 5865 | * 82571 hardware supports TSO capabilities for IPv6 as well... |
ad68076e BA |
5866 | * no longer assume, we must. |
5867 | */ | |
47ccd1ed | 5868 | if (protocol == htons(ETH_P_IP)) |
bc7f75fa AK |
5869 | tx_flags |= E1000_TX_FLAGS_IPV4; |
5870 | ||
943146de BG |
5871 | if (unlikely(skb->no_fcs)) |
5872 | tx_flags |= E1000_TX_FLAGS_NO_FCS; | |
5873 | ||
25985edc | 5874 | /* if count is 0 then mapping error has occurred */ |
d821a4c4 BA |
5875 | count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit, |
5876 | nr_frags); | |
1b7719c4 | 5877 | if (count) { |
6930895d | 5878 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && |
cff57141 JK |
5879 | (adapter->flags & FLAG_HAS_HW_TIMESTAMP)) { |
5880 | if (!adapter->tx_hwtstamp_skb) { | |
5881 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
5882 | tx_flags |= E1000_TX_FLAGS_HWTSTAMP; | |
5883 | adapter->tx_hwtstamp_skb = skb_get(skb); | |
5884 | adapter->tx_hwtstamp_start = jiffies; | |
5885 | schedule_work(&adapter->tx_hwtstamp_work); | |
5886 | } else { | |
5887 | adapter->tx_hwtstamp_skipped++; | |
5888 | } | |
b67e1913 | 5889 | } |
80be3129 | 5890 | |
74abc9b1 ML |
5891 | skb_tx_timestamp(skb); |
5892 | ||
3f0cfa3b | 5893 | netdev_sent_queue(netdev, skb->len); |
55aa6985 | 5894 | e1000_tx_queue(tx_ring, tx_flags, count); |
1b7719c4 | 5895 | /* Make sure there is space in the ring for the next send. */ |
d821a4c4 BA |
5896 | e1000_maybe_stop_tx(tx_ring, |
5897 | (MAX_SKB_FRAGS * | |
5898 | DIV_ROUND_UP(PAGE_SIZE, | |
5899 | adapter->tx_fifo_limit) + 2)); | |
472f31f5 FW |
5900 | |
5901 | if (!skb->xmit_more || | |
5902 | netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) { | |
5903 | if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA) | |
5904 | e1000e_update_tdt_wa(tx_ring, | |
5905 | tx_ring->next_to_use); | |
5906 | else | |
5907 | writel(tx_ring->next_to_use, tx_ring->tail); | |
5908 | ||
5909 | /* we need this if more than one processor can write | |
5910 | * to our tail at a time, it synchronizes IO on | |
5911 | *IA64/Altix systems | |
5912 | */ | |
5913 | mmiowb(); | |
5914 | } | |
1b7719c4 | 5915 | } else { |
bc7f75fa | 5916 | dev_kfree_skb_any(skb); |
1b7719c4 AD |
5917 | tx_ring->buffer_info[first].time_stamp = 0; |
5918 | tx_ring->next_to_use = first; | |
bc7f75fa AK |
5919 | } |
5920 | ||
bc7f75fa AK |
5921 | return NETDEV_TX_OK; |
5922 | } | |
5923 | ||
5924 | /** | |
5925 | * e1000_tx_timeout - Respond to a Tx Hang | |
5926 | * @netdev: network interface device structure | |
5927 | **/ | |
5928 | static void e1000_tx_timeout(struct net_device *netdev) | |
5929 | { | |
5930 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
5931 | ||
5932 | /* Do the reset outside of interrupt context */ | |
5933 | adapter->tx_timeout_count++; | |
5934 | schedule_work(&adapter->reset_task); | |
5935 | } | |
5936 | ||
5937 | static void e1000_reset_task(struct work_struct *work) | |
5938 | { | |
5939 | struct e1000_adapter *adapter; | |
5940 | adapter = container_of(work, struct e1000_adapter, reset_task); | |
5941 | ||
615b32af JB |
5942 | /* don't run the task if already down */ |
5943 | if (test_bit(__E1000_DOWN, &adapter->state)) | |
5944 | return; | |
5945 | ||
12d43f7d | 5946 | if (!(adapter->flags & FLAG_RESTART_NOW)) { |
affa9dfb | 5947 | e1000e_dump(adapter); |
12d43f7d | 5948 | e_err("Reset adapter unexpectedly\n"); |
affa9dfb | 5949 | } |
bc7f75fa AK |
5950 | e1000e_reinit_locked(adapter); |
5951 | } | |
5952 | ||
5953 | /** | |
67fd4fcb | 5954 | * e1000_get_stats64 - Get System Network Statistics |
bc7f75fa | 5955 | * @netdev: network interface device structure |
67fd4fcb | 5956 | * @stats: rtnl_link_stats64 pointer |
bc7f75fa AK |
5957 | * |
5958 | * Returns the address of the device statistics structure. | |
bc7f75fa | 5959 | **/ |
bc1f4470 | 5960 | void e1000e_get_stats64(struct net_device *netdev, |
5961 | struct rtnl_link_stats64 *stats) | |
bc7f75fa | 5962 | { |
67fd4fcb JK |
5963 | struct e1000_adapter *adapter = netdev_priv(netdev); |
5964 | ||
67fd4fcb JK |
5965 | spin_lock(&adapter->stats64_lock); |
5966 | e1000e_update_stats(adapter); | |
5967 | /* Fill out the OS statistics structure */ | |
5968 | stats->rx_bytes = adapter->stats.gorc; | |
5969 | stats->rx_packets = adapter->stats.gprc; | |
5970 | stats->tx_bytes = adapter->stats.gotc; | |
5971 | stats->tx_packets = adapter->stats.gptc; | |
5972 | stats->multicast = adapter->stats.mprc; | |
5973 | stats->collisions = adapter->stats.colc; | |
5974 | ||
5975 | /* Rx Errors */ | |
5976 | ||
e921eb1a | 5977 | /* RLEC on some newer hardware can be incorrect so build |
67fd4fcb JK |
5978 | * our own version based on RUC and ROC |
5979 | */ | |
5980 | stats->rx_errors = adapter->stats.rxerrc + | |
f0ff4398 BA |
5981 | adapter->stats.crcerrs + adapter->stats.algnerrc + |
5982 | adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr; | |
5983 | stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc; | |
67fd4fcb JK |
5984 | stats->rx_crc_errors = adapter->stats.crcerrs; |
5985 | stats->rx_frame_errors = adapter->stats.algnerrc; | |
5986 | stats->rx_missed_errors = adapter->stats.mpc; | |
5987 | ||
5988 | /* Tx Errors */ | |
f0ff4398 | 5989 | stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol; |
67fd4fcb JK |
5990 | stats->tx_aborted_errors = adapter->stats.ecol; |
5991 | stats->tx_window_errors = adapter->stats.latecol; | |
5992 | stats->tx_carrier_errors = adapter->stats.tncrs; | |
5993 | ||
5994 | /* Tx Dropped needs to be maintained elsewhere */ | |
5995 | ||
5996 | spin_unlock(&adapter->stats64_lock); | |
bc7f75fa AK |
5997 | } |
5998 | ||
5999 | /** | |
6000 | * e1000_change_mtu - Change the Maximum Transfer Unit | |
6001 | * @netdev: network interface device structure | |
6002 | * @new_mtu: new value for maximum frame size | |
6003 | * | |
6004 | * Returns 0 on success, negative on failure | |
6005 | **/ | |
6006 | static int e1000_change_mtu(struct net_device *netdev, int new_mtu) | |
6007 | { | |
6008 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
8084b86d | 6009 | int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; |
bc7f75fa | 6010 | |
2adc55c9 | 6011 | /* Jumbo frame support */ |
91c527a5 | 6012 | if ((new_mtu > ETH_DATA_LEN) && |
2e1706f2 BA |
6013 | !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) { |
6014 | e_err("Jumbo Frames not supported.\n"); | |
6015 | return -EINVAL; | |
bc7f75fa AK |
6016 | } |
6017 | ||
2fbe4526 BA |
6018 | /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ |
6019 | if ((adapter->hw.mac.type >= e1000_pch2lan) && | |
a1ce6473 BA |
6020 | !(adapter->flags2 & FLAG2_CRC_STRIPPING) && |
6021 | (new_mtu > ETH_DATA_LEN)) { | |
2fbe4526 | 6022 | e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n"); |
a1ce6473 BA |
6023 | return -EINVAL; |
6024 | } | |
6025 | ||
bc7f75fa | 6026 | while (test_and_set_bit(__E1000_RESETTING, &adapter->state)) |
1bba4386 | 6027 | usleep_range(1000, 2000); |
610c9928 | 6028 | /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */ |
318a94d6 | 6029 | adapter->max_frame_size = max_frame; |
610c9928 BA |
6030 | e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
6031 | netdev->mtu = new_mtu; | |
63eb48f1 DE |
6032 | |
6033 | pm_runtime_get_sync(netdev->dev.parent); | |
6034 | ||
bc7f75fa | 6035 | if (netif_running(netdev)) |
28002099 | 6036 | e1000e_down(adapter, true); |
bc7f75fa | 6037 | |
e921eb1a | 6038 | /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN |
bc7f75fa AK |
6039 | * means we reserve 2 more, this pushes us to allocate from the next |
6040 | * larger slab size. | |
ad68076e | 6041 | * i.e. RXBUFFER_2048 --> size-4096 slab |
97ac8cae BA |
6042 | * However with the new *_jumbo_rx* routines, jumbo receives will use |
6043 | * fragmented skbs | |
ad68076e | 6044 | */ |
bc7f75fa | 6045 | |
9926146b | 6046 | if (max_frame <= 2048) |
bc7f75fa AK |
6047 | adapter->rx_buffer_len = 2048; |
6048 | else | |
6049 | adapter->rx_buffer_len = 4096; | |
6050 | ||
6051 | /* adjust allocation if LPE protects us, and we aren't using SBP */ | |
8084b86d AD |
6052 | if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) |
6053 | adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN; | |
bc7f75fa | 6054 | |
bc7f75fa AK |
6055 | if (netif_running(netdev)) |
6056 | e1000e_up(adapter); | |
6057 | else | |
6058 | e1000e_reset(adapter); | |
6059 | ||
63eb48f1 DE |
6060 | pm_runtime_put_sync(netdev->dev.parent); |
6061 | ||
bc7f75fa AK |
6062 | clear_bit(__E1000_RESETTING, &adapter->state); |
6063 | ||
6064 | return 0; | |
6065 | } | |
6066 | ||
6067 | static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, | |
6068 | int cmd) | |
6069 | { | |
6070 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6071 | struct mii_ioctl_data *data = if_mii(ifr); | |
bc7f75fa | 6072 | |
318a94d6 | 6073 | if (adapter->hw.phy.media_type != e1000_media_type_copper) |
bc7f75fa AK |
6074 | return -EOPNOTSUPP; |
6075 | ||
6076 | switch (cmd) { | |
6077 | case SIOCGMIIPHY: | |
6078 | data->phy_id = adapter->hw.phy.addr; | |
6079 | break; | |
6080 | case SIOCGMIIREG: | |
b16a002e BA |
6081 | e1000_phy_read_status(adapter); |
6082 | ||
7c25769f BA |
6083 | switch (data->reg_num & 0x1F) { |
6084 | case MII_BMCR: | |
6085 | data->val_out = adapter->phy_regs.bmcr; | |
6086 | break; | |
6087 | case MII_BMSR: | |
6088 | data->val_out = adapter->phy_regs.bmsr; | |
6089 | break; | |
6090 | case MII_PHYSID1: | |
6091 | data->val_out = (adapter->hw.phy.id >> 16); | |
6092 | break; | |
6093 | case MII_PHYSID2: | |
6094 | data->val_out = (adapter->hw.phy.id & 0xFFFF); | |
6095 | break; | |
6096 | case MII_ADVERTISE: | |
6097 | data->val_out = adapter->phy_regs.advertise; | |
6098 | break; | |
6099 | case MII_LPA: | |
6100 | data->val_out = adapter->phy_regs.lpa; | |
6101 | break; | |
6102 | case MII_EXPANSION: | |
6103 | data->val_out = adapter->phy_regs.expansion; | |
6104 | break; | |
6105 | case MII_CTRL1000: | |
6106 | data->val_out = adapter->phy_regs.ctrl1000; | |
6107 | break; | |
6108 | case MII_STAT1000: | |
6109 | data->val_out = adapter->phy_regs.stat1000; | |
6110 | break; | |
6111 | case MII_ESTATUS: | |
6112 | data->val_out = adapter->phy_regs.estatus; | |
6113 | break; | |
6114 | default: | |
bc7f75fa AK |
6115 | return -EIO; |
6116 | } | |
bc7f75fa AK |
6117 | break; |
6118 | case SIOCSMIIREG: | |
6119 | default: | |
6120 | return -EOPNOTSUPP; | |
6121 | } | |
6122 | return 0; | |
6123 | } | |
6124 | ||
b67e1913 BA |
6125 | /** |
6126 | * e1000e_hwtstamp_ioctl - control hardware time stamping | |
6127 | * @netdev: network interface device structure | |
6128 | * @ifreq: interface request | |
6129 | * | |
6130 | * Outgoing time stamping can be enabled and disabled. Play nice and | |
6131 | * disable it when requested, although it shouldn't cause any overhead | |
6132 | * when no packet needs it. At most one packet in the queue may be | |
6133 | * marked for time stamping, otherwise it would be impossible to tell | |
6134 | * for sure to which packet the hardware time stamp belongs. | |
6135 | * | |
6136 | * Incoming time stamping has to be configured via the hardware filters. | |
6137 | * Not all combinations are supported, in particular event type has to be | |
6138 | * specified. Matching the kind of event packet is not supported, with the | |
6139 | * exception of "all V2 events regardless of level 2 or 4". | |
6140 | **/ | |
4e8cff64 | 6141 | static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr) |
b67e1913 BA |
6142 | { |
6143 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6144 | struct hwtstamp_config config; | |
6145 | int ret_val; | |
6146 | ||
6147 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
6148 | return -EFAULT; | |
6149 | ||
62d7e3a2 | 6150 | ret_val = e1000e_config_hwtstamp(adapter, &config); |
b67e1913 BA |
6151 | if (ret_val) |
6152 | return ret_val; | |
6153 | ||
d89777bf BA |
6154 | switch (config.rx_filter) { |
6155 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
6156 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
6157 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
6158 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
6159 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
6160 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
6161 | /* With V2 type filters which specify a Sync or Delay Request, | |
6162 | * Path Delay Request/Response messages are also time stamped | |
6163 | * by hardware so notify the caller the requested packets plus | |
6164 | * some others are time stamped. | |
6165 | */ | |
6166 | config.rx_filter = HWTSTAMP_FILTER_SOME; | |
6167 | break; | |
6168 | default: | |
6169 | break; | |
6170 | } | |
6171 | ||
b67e1913 BA |
6172 | return copy_to_user(ifr->ifr_data, &config, |
6173 | sizeof(config)) ? -EFAULT : 0; | |
6174 | } | |
6175 | ||
4e8cff64 BH |
6176 | static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr) |
6177 | { | |
6178 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6179 | ||
6180 | return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config, | |
6181 | sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0; | |
6182 | } | |
6183 | ||
bc7f75fa AK |
6184 | static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) |
6185 | { | |
6186 | switch (cmd) { | |
6187 | case SIOCGMIIPHY: | |
6188 | case SIOCGMIIREG: | |
6189 | case SIOCSMIIREG: | |
6190 | return e1000_mii_ioctl(netdev, ifr, cmd); | |
b67e1913 | 6191 | case SIOCSHWTSTAMP: |
4e8cff64 BH |
6192 | return e1000e_hwtstamp_set(netdev, ifr); |
6193 | case SIOCGHWTSTAMP: | |
6194 | return e1000e_hwtstamp_get(netdev, ifr); | |
bc7f75fa AK |
6195 | default: |
6196 | return -EOPNOTSUPP; | |
6197 | } | |
6198 | } | |
6199 | ||
a4f58f54 BA |
6200 | static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc) |
6201 | { | |
6202 | struct e1000_hw *hw = &adapter->hw; | |
74f350ee | 6203 | u32 i, mac_reg, wuc; |
2b6b168d | 6204 | u16 phy_reg, wuc_enable; |
70806a7f | 6205 | int retval; |
a4f58f54 BA |
6206 | |
6207 | /* copy MAC RARs to PHY RARs */ | |
d3738bb8 | 6208 | e1000_copy_rx_addrs_to_phy_ich8lan(hw); |
a4f58f54 | 6209 | |
2b6b168d BA |
6210 | retval = hw->phy.ops.acquire(hw); |
6211 | if (retval) { | |
6212 | e_err("Could not acquire PHY\n"); | |
6213 | return retval; | |
6214 | } | |
6215 | ||
6216 | /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */ | |
6217 | retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable); | |
6218 | if (retval) | |
75ce1532 | 6219 | goto release; |
2b6b168d BA |
6220 | |
6221 | /* copy MAC MTA to PHY MTA - only needed for pchlan */ | |
a4f58f54 BA |
6222 | for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) { |
6223 | mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i); | |
2b6b168d BA |
6224 | hw->phy.ops.write_reg_page(hw, BM_MTA(i), |
6225 | (u16)(mac_reg & 0xFFFF)); | |
6226 | hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1, | |
6227 | (u16)((mac_reg >> 16) & 0xFFFF)); | |
a4f58f54 BA |
6228 | } |
6229 | ||
6230 | /* configure PHY Rx Control register */ | |
2b6b168d | 6231 | hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg); |
a4f58f54 BA |
6232 | mac_reg = er32(RCTL); |
6233 | if (mac_reg & E1000_RCTL_UPE) | |
6234 | phy_reg |= BM_RCTL_UPE; | |
6235 | if (mac_reg & E1000_RCTL_MPE) | |
6236 | phy_reg |= BM_RCTL_MPE; | |
6237 | phy_reg &= ~(BM_RCTL_MO_MASK); | |
6238 | if (mac_reg & E1000_RCTL_MO_3) | |
6239 | phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT) | |
17e813ec | 6240 | << BM_RCTL_MO_SHIFT); |
a4f58f54 BA |
6241 | if (mac_reg & E1000_RCTL_BAM) |
6242 | phy_reg |= BM_RCTL_BAM; | |
6243 | if (mac_reg & E1000_RCTL_PMCF) | |
6244 | phy_reg |= BM_RCTL_PMCF; | |
6245 | mac_reg = er32(CTRL); | |
6246 | if (mac_reg & E1000_CTRL_RFCE) | |
6247 | phy_reg |= BM_RCTL_RFCE; | |
2b6b168d | 6248 | hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg); |
a4f58f54 | 6249 | |
74f350ee DE |
6250 | wuc = E1000_WUC_PME_EN; |
6251 | if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC)) | |
6252 | wuc |= E1000_WUC_APME; | |
6253 | ||
a4f58f54 BA |
6254 | /* enable PHY wakeup in MAC register */ |
6255 | ew32(WUFC, wufc); | |
74f350ee DE |
6256 | ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME | |
6257 | E1000_WUC_PME_STATUS | wuc)); | |
a4f58f54 BA |
6258 | |
6259 | /* configure and enable PHY wakeup in PHY registers */ | |
2b6b168d | 6260 | hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc); |
74f350ee | 6261 | hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc); |
a4f58f54 BA |
6262 | |
6263 | /* activate PHY wakeup */ | |
2b6b168d BA |
6264 | wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT; |
6265 | retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable); | |
a4f58f54 BA |
6266 | if (retval) |
6267 | e_err("Could not set PHY Host Wakeup bit\n"); | |
75ce1532 | 6268 | release: |
94d8186a | 6269 | hw->phy.ops.release(hw); |
a4f58f54 BA |
6270 | |
6271 | return retval; | |
6272 | } | |
6273 | ||
2a7e19af DE |
6274 | static void e1000e_flush_lpic(struct pci_dev *pdev) |
6275 | { | |
6276 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6277 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6278 | struct e1000_hw *hw = &adapter->hw; | |
6279 | u32 ret_val; | |
6280 | ||
6281 | pm_runtime_get_sync(netdev->dev.parent); | |
6282 | ||
6283 | ret_val = hw->phy.ops.acquire(hw); | |
6284 | if (ret_val) | |
6285 | goto fl_out; | |
6286 | ||
6287 | pr_info("EEE TX LPI TIMER: %08X\n", | |
6288 | er32(LPIC) >> E1000_LPIC_LPIET_SHIFT); | |
6289 | ||
6290 | hw->phy.ops.release(hw); | |
6291 | ||
6292 | fl_out: | |
6293 | pm_runtime_put_sync(netdev->dev.parent); | |
6294 | } | |
6295 | ||
28002099 | 6296 | static int e1000e_pm_freeze(struct device *dev) |
bc7f75fa | 6297 | { |
28002099 | 6298 | struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); |
bc7f75fa | 6299 | struct e1000_adapter *adapter = netdev_priv(netdev); |
bc7f75fa AK |
6300 | |
6301 | netif_device_detach(netdev); | |
6302 | ||
6303 | if (netif_running(netdev)) { | |
bb9e44d0 BA |
6304 | int count = E1000_CHECK_RESET_COUNT; |
6305 | ||
6306 | while (test_bit(__E1000_RESETTING, &adapter->state) && count--) | |
6307 | usleep_range(10000, 20000); | |
6308 | ||
bc7f75fa | 6309 | WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); |
28002099 DE |
6310 | |
6311 | /* Quiesce the device without resetting the hardware */ | |
6312 | e1000e_down(adapter, false); | |
bc7f75fa AK |
6313 | e1000_free_irq(adapter); |
6314 | } | |
9f47a48e | 6315 | e1000e_reset_interrupt_capability(adapter); |
bc7f75fa | 6316 | |
28002099 DE |
6317 | /* Allow time for pending master requests to run */ |
6318 | e1000e_disable_pcie_master(&adapter->hw); | |
6319 | ||
6320 | return 0; | |
6321 | } | |
6322 | ||
6323 | static int __e1000_shutdown(struct pci_dev *pdev, bool runtime) | |
6324 | { | |
6325 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6326 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6327 | struct e1000_hw *hw = &adapter->hw; | |
6328 | u32 ctrl, ctrl_ext, rctl, status; | |
6329 | /* Runtime suspend should only enable wakeup for link changes */ | |
6330 | u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; | |
6331 | int retval = 0; | |
6332 | ||
bc7f75fa AK |
6333 | status = er32(STATUS); |
6334 | if (status & E1000_STATUS_LU) | |
6335 | wufc &= ~E1000_WUFC_LNKC; | |
6336 | ||
6337 | if (wufc) { | |
6338 | e1000_setup_rctl(adapter); | |
ef9b965a | 6339 | e1000e_set_rx_mode(netdev); |
bc7f75fa AK |
6340 | |
6341 | /* turn on all-multi mode if wake on multicast is enabled */ | |
6342 | if (wufc & E1000_WUFC_MC) { | |
6343 | rctl = er32(RCTL); | |
6344 | rctl |= E1000_RCTL_MPE; | |
6345 | ew32(RCTL, rctl); | |
6346 | } | |
6347 | ||
6348 | ctrl = er32(CTRL); | |
a4f58f54 BA |
6349 | ctrl |= E1000_CTRL_ADVD3WUC; |
6350 | if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP)) | |
6351 | ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT; | |
bc7f75fa AK |
6352 | ew32(CTRL, ctrl); |
6353 | ||
318a94d6 JK |
6354 | if (adapter->hw.phy.media_type == e1000_media_type_fiber || |
6355 | adapter->hw.phy.media_type == | |
6356 | e1000_media_type_internal_serdes) { | |
bc7f75fa AK |
6357 | /* keep the laser running in D3 */ |
6358 | ctrl_ext = er32(CTRL_EXT); | |
93a23f48 | 6359 | ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA; |
bc7f75fa AK |
6360 | ew32(CTRL_EXT, ctrl_ext); |
6361 | } | |
6362 | ||
63eb48f1 DE |
6363 | if (!runtime) |
6364 | e1000e_power_up_phy(adapter); | |
6365 | ||
97ac8cae | 6366 | if (adapter->flags & FLAG_IS_ICH) |
99730e4c | 6367 | e1000_suspend_workarounds_ich8lan(&adapter->hw); |
97ac8cae | 6368 | |
82776a4b | 6369 | if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { |
a4f58f54 BA |
6370 | /* enable wakeup by the PHY */ |
6371 | retval = e1000_init_phy_wakeup(adapter, wufc); | |
6372 | if (retval) | |
6373 | return retval; | |
6374 | } else { | |
6375 | /* enable wakeup by the MAC */ | |
6376 | ew32(WUFC, wufc); | |
6377 | ew32(WUC, E1000_WUC_PME_EN); | |
6378 | } | |
bc7f75fa AK |
6379 | } else { |
6380 | ew32(WUC, 0); | |
6381 | ew32(WUFC, 0); | |
28002099 DE |
6382 | |
6383 | e1000_power_down_phy(adapter); | |
bc7f75fa AK |
6384 | } |
6385 | ||
74f350ee | 6386 | if (adapter->hw.phy.type == e1000_phy_igp_3) { |
bc7f75fa | 6387 | e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw); |
c8744f44 | 6388 | } else if (hw->mac.type >= e1000_pch_lpt) { |
74f350ee DE |
6389 | if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC))) |
6390 | /* ULP does not support wake from unicast, multicast | |
6391 | * or broadcast. | |
6392 | */ | |
6393 | retval = e1000_enable_ulp_lpt_lp(hw, !runtime); | |
6394 | ||
6395 | if (retval) | |
6396 | return retval; | |
6397 | } | |
6398 | ||
f5ac7445 RA |
6399 | /* Ensure that the appropriate bits are set in LPI_CTRL |
6400 | * for EEE in Sx | |
6401 | */ | |
6402 | if ((hw->phy.type >= e1000_phy_i217) && | |
6403 | adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) { | |
6404 | u16 lpi_ctrl = 0; | |
6405 | ||
6406 | retval = hw->phy.ops.acquire(hw); | |
6407 | if (!retval) { | |
6408 | retval = e1e_rphy_locked(hw, I82579_LPI_CTRL, | |
6409 | &lpi_ctrl); | |
6410 | if (!retval) { | |
6411 | if (adapter->eee_advert & | |
6412 | hw->dev_spec.ich8lan.eee_lp_ability & | |
6413 | I82579_EEE_100_SUPPORTED) | |
6414 | lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; | |
6415 | if (adapter->eee_advert & | |
6416 | hw->dev_spec.ich8lan.eee_lp_ability & | |
6417 | I82579_EEE_1000_SUPPORTED) | |
6418 | lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; | |
6419 | ||
6420 | retval = e1e_wphy_locked(hw, I82579_LPI_CTRL, | |
6421 | lpi_ctrl); | |
6422 | } | |
6423 | } | |
6424 | hw->phy.ops.release(hw); | |
6425 | } | |
bc7f75fa | 6426 | |
e921eb1a | 6427 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
ad68076e BA |
6428 | * would have already happened in close and is redundant. |
6429 | */ | |
31dbe5b4 | 6430 | e1000e_release_hw_control(adapter); |
bc7f75fa | 6431 | |
24b41c97 DN |
6432 | pci_clear_master(pdev); |
6433 | ||
e921eb1a | 6434 | /* The pci-e switch on some quad port adapters will report a |
005cbdfc AD |
6435 | * correctable error when the MAC transitions from D0 to D3. To |
6436 | * prevent this we need to mask off the correctable errors on the | |
6437 | * downstream port of the pci-e switch. | |
e8c254c5 LZ |
6438 | * |
6439 | * We don't have the associated upstream bridge while assigning | |
6440 | * the PCI device into guest. For example, the KVM on power is | |
6441 | * one of the cases. | |
005cbdfc AD |
6442 | */ |
6443 | if (adapter->flags & FLAG_IS_QUAD_PORT) { | |
6444 | struct pci_dev *us_dev = pdev->bus->self; | |
005cbdfc AD |
6445 | u16 devctl; |
6446 | ||
e8c254c5 LZ |
6447 | if (!us_dev) |
6448 | return 0; | |
6449 | ||
f8c0fcac JL |
6450 | pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl); |
6451 | pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, | |
6452 | (devctl & ~PCI_EXP_DEVCTL_CERE)); | |
005cbdfc | 6453 | |
66148bab KK |
6454 | pci_save_state(pdev); |
6455 | pci_prepare_to_sleep(pdev); | |
005cbdfc | 6456 | |
f8c0fcac | 6457 | pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl); |
005cbdfc | 6458 | } |
66148bab KK |
6459 | |
6460 | return 0; | |
bc7f75fa AK |
6461 | } |
6462 | ||
13129d9b | 6463 | /** |
beb0a152 | 6464 | * __e1000e_disable_aspm - Disable ASPM states |
13129d9b CW |
6465 | * @pdev: pointer to PCI device struct |
6466 | * @state: bit-mask of ASPM states to disable | |
beb0a152 | 6467 | * @locked: indication if this context holds pci_bus_sem locked. |
13129d9b CW |
6468 | * |
6469 | * Some devices *must* have certain ASPM states disabled per hardware errata. | |
6470 | **/ | |
beb0a152 | 6471 | static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked) |
6f461f6c | 6472 | { |
13129d9b CW |
6473 | struct pci_dev *parent = pdev->bus->self; |
6474 | u16 aspm_dis_mask = 0; | |
6475 | u16 pdev_aspmc, parent_aspmc; | |
6476 | ||
6477 | switch (state) { | |
6478 | case PCIE_LINK_STATE_L0S: | |
6479 | case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1: | |
6480 | aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S; | |
6481 | /* fall-through - can't have L1 without L0s */ | |
6482 | case PCIE_LINK_STATE_L1: | |
6483 | aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1; | |
6484 | break; | |
6485 | default: | |
6486 | return; | |
6487 | } | |
6488 | ||
6489 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); | |
6490 | pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; | |
6491 | ||
6492 | if (parent) { | |
6493 | pcie_capability_read_word(parent, PCI_EXP_LNKCTL, | |
6494 | &parent_aspmc); | |
6495 | parent_aspmc &= PCI_EXP_LNKCTL_ASPMC; | |
6496 | } | |
6497 | ||
6498 | /* Nothing to do if the ASPM states to be disabled already are */ | |
6499 | if (!(pdev_aspmc & aspm_dis_mask) && | |
6500 | (!parent || !(parent_aspmc & aspm_dis_mask))) | |
6501 | return; | |
6502 | ||
6503 | dev_info(&pdev->dev, "Disabling ASPM %s %s\n", | |
6504 | (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ? | |
6505 | "L0s" : "", | |
6506 | (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ? | |
6507 | "L1" : ""); | |
6508 | ||
6509 | #ifdef CONFIG_PCIEASPM | |
beb0a152 YL |
6510 | if (locked) |
6511 | pci_disable_link_state_locked(pdev, state); | |
6512 | else | |
6513 | pci_disable_link_state(pdev, state); | |
ffe0b2ff | 6514 | |
13129d9b CW |
6515 | /* Double-check ASPM control. If not disabled by the above, the |
6516 | * BIOS is preventing that from happening (or CONFIG_PCIEASPM is | |
6517 | * not enabled); override by writing PCI config space directly. | |
6518 | */ | |
6519 | pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc); | |
6520 | pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC; | |
6521 | ||
6522 | if (!(aspm_dis_mask & pdev_aspmc)) | |
6523 | return; | |
6524 | #endif | |
ffe0b2ff | 6525 | |
e921eb1a | 6526 | /* Both device and parent should have the same ASPM setting. |
6f461f6c | 6527 | * Disable ASPM in downstream component first and then upstream. |
1eae4eb2 | 6528 | */ |
13129d9b | 6529 | pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask); |
6f461f6c | 6530 | |
13129d9b CW |
6531 | if (parent) |
6532 | pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, | |
6533 | aspm_dis_mask); | |
1eae4eb2 AK |
6534 | } |
6535 | ||
beb0a152 YL |
6536 | /** |
6537 | * e1000e_disable_aspm - Disable ASPM states. | |
6538 | * @pdev: pointer to PCI device struct | |
6539 | * @state: bit-mask of ASPM states to disable | |
6540 | * | |
6541 | * This function acquires the pci_bus_sem! | |
6542 | * Some devices *must* have certain ASPM states disabled per hardware errata. | |
6543 | **/ | |
6544 | static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state) | |
6545 | { | |
6546 | __e1000e_disable_aspm(pdev, state, 0); | |
6547 | } | |
6548 | ||
6549 | /** | |
6550 | * e1000e_disable_aspm_locked Disable ASPM states. | |
6551 | * @pdev: pointer to PCI device struct | |
6552 | * @state: bit-mask of ASPM states to disable | |
6553 | * | |
6554 | * This function must be called with pci_bus_sem acquired! | |
6555 | * Some devices *must* have certain ASPM states disabled per hardware errata. | |
6556 | **/ | |
6557 | static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state) | |
6558 | { | |
6559 | __e1000e_disable_aspm(pdev, state, 1); | |
6560 | } | |
6561 | ||
aa338601 | 6562 | #ifdef CONFIG_PM |
23606cf5 | 6563 | static int __e1000_resume(struct pci_dev *pdev) |
bc7f75fa AK |
6564 | { |
6565 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6566 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6567 | struct e1000_hw *hw = &adapter->hw; | |
78cd29d5 | 6568 | u16 aspm_disable_flag = 0; |
bc7f75fa | 6569 | |
78cd29d5 BA |
6570 | if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) |
6571 | aspm_disable_flag = PCIE_LINK_STATE_L0S; | |
6572 | if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) | |
6573 | aspm_disable_flag |= PCIE_LINK_STATE_L1; | |
6574 | if (aspm_disable_flag) | |
2758f9ed | 6575 | e1000e_disable_aspm(pdev, aspm_disable_flag); |
78cd29d5 | 6576 | |
66148bab | 6577 | pci_set_master(pdev); |
6e4f6f6b | 6578 | |
2fbe4526 | 6579 | if (hw->mac.type >= e1000_pch2lan) |
99730e4c BA |
6580 | e1000_resume_workarounds_pchlan(&adapter->hw); |
6581 | ||
bc7f75fa | 6582 | e1000e_power_up_phy(adapter); |
a4f58f54 BA |
6583 | |
6584 | /* report the system wakeup cause from S3/S4 */ | |
6585 | if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) { | |
6586 | u16 phy_data; | |
6587 | ||
6588 | e1e_rphy(&adapter->hw, BM_WUS, &phy_data); | |
6589 | if (phy_data) { | |
6590 | e_info("PHY Wakeup cause - %s\n", | |
17e813ec BA |
6591 | phy_data & E1000_WUS_EX ? "Unicast Packet" : |
6592 | phy_data & E1000_WUS_MC ? "Multicast Packet" : | |
6593 | phy_data & E1000_WUS_BC ? "Broadcast Packet" : | |
6594 | phy_data & E1000_WUS_MAG ? "Magic Packet" : | |
6595 | phy_data & E1000_WUS_LNKC ? | |
6596 | "Link Status Change" : "other"); | |
a4f58f54 BA |
6597 | } |
6598 | e1e_wphy(&adapter->hw, BM_WUS, ~0); | |
6599 | } else { | |
6600 | u32 wus = er32(WUS); | |
6cf08d1c | 6601 | |
a4f58f54 BA |
6602 | if (wus) { |
6603 | e_info("MAC Wakeup cause - %s\n", | |
17e813ec BA |
6604 | wus & E1000_WUS_EX ? "Unicast Packet" : |
6605 | wus & E1000_WUS_MC ? "Multicast Packet" : | |
6606 | wus & E1000_WUS_BC ? "Broadcast Packet" : | |
6607 | wus & E1000_WUS_MAG ? "Magic Packet" : | |
6608 | wus & E1000_WUS_LNKC ? "Link Status Change" : | |
6609 | "other"); | |
a4f58f54 BA |
6610 | } |
6611 | ew32(WUS, ~0); | |
6612 | } | |
6613 | ||
bc7f75fa | 6614 | e1000e_reset(adapter); |
bc7f75fa | 6615 | |
cd791618 | 6616 | e1000_init_manageability_pt(adapter); |
bc7f75fa | 6617 | |
e921eb1a | 6618 | /* If the controller has AMT, do not set DRV_LOAD until the interface |
bc7f75fa | 6619 | * is up. For all other cases, let the f/w know that the h/w is now |
ad68076e BA |
6620 | * under the control of the driver. |
6621 | */ | |
c43bc57e | 6622 | if (!(adapter->flags & FLAG_HAS_AMT)) |
31dbe5b4 | 6623 | e1000e_get_hw_control(adapter); |
bc7f75fa AK |
6624 | |
6625 | return 0; | |
6626 | } | |
23606cf5 | 6627 | |
3e7986f6 | 6628 | #ifdef CONFIG_PM_SLEEP |
28002099 DE |
6629 | static int e1000e_pm_thaw(struct device *dev) |
6630 | { | |
6631 | struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev)); | |
6632 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6633 | ||
6634 | e1000e_set_interrupt_capability(adapter); | |
6635 | if (netif_running(netdev)) { | |
6636 | u32 err = e1000_request_irq(adapter); | |
6637 | ||
6638 | if (err) | |
6639 | return err; | |
6640 | ||
6641 | e1000e_up(adapter); | |
6642 | } | |
6643 | ||
6644 | netif_device_attach(netdev); | |
6645 | ||
6646 | return 0; | |
6647 | } | |
6648 | ||
28002099 | 6649 | static int e1000e_pm_suspend(struct device *dev) |
a0340162 RW |
6650 | { |
6651 | struct pci_dev *pdev = to_pci_dev(dev); | |
833521eb | 6652 | int rc; |
a0340162 | 6653 | |
2a7e19af DE |
6654 | e1000e_flush_lpic(pdev); |
6655 | ||
28002099 DE |
6656 | e1000e_pm_freeze(dev); |
6657 | ||
833521eb CW |
6658 | rc = __e1000_shutdown(pdev, false); |
6659 | if (rc) | |
6660 | e1000e_pm_thaw(dev); | |
6661 | ||
6662 | return rc; | |
a0340162 RW |
6663 | } |
6664 | ||
28002099 | 6665 | static int e1000e_pm_resume(struct device *dev) |
23606cf5 RW |
6666 | { |
6667 | struct pci_dev *pdev = to_pci_dev(dev); | |
28002099 | 6668 | int rc; |
23606cf5 | 6669 | |
28002099 DE |
6670 | rc = __e1000_resume(pdev); |
6671 | if (rc) | |
6672 | return rc; | |
23606cf5 | 6673 | |
28002099 | 6674 | return e1000e_pm_thaw(dev); |
23606cf5 | 6675 | } |
38a529b5 | 6676 | #endif /* CONFIG_PM_SLEEP */ |
a0340162 | 6677 | |
63eb48f1 | 6678 | static int e1000e_pm_runtime_idle(struct device *dev) |
a0340162 RW |
6679 | { |
6680 | struct pci_dev *pdev = to_pci_dev(dev); | |
6681 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6682 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
2116bc25 | 6683 | u16 eee_lp; |
a0340162 | 6684 | |
2116bc25 DE |
6685 | eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability; |
6686 | ||
6687 | if (!e1000e_has_link(adapter)) { | |
6688 | adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp; | |
63eb48f1 | 6689 | pm_schedule_suspend(dev, 5 * MSEC_PER_SEC); |
2116bc25 | 6690 | } |
a0340162 | 6691 | |
63eb48f1 | 6692 | return -EBUSY; |
a0340162 RW |
6693 | } |
6694 | ||
63eb48f1 | 6695 | static int e1000e_pm_runtime_resume(struct device *dev) |
a0340162 RW |
6696 | { |
6697 | struct pci_dev *pdev = to_pci_dev(dev); | |
6698 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6699 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
63eb48f1 | 6700 | int rc; |
a0340162 | 6701 | |
63eb48f1 DE |
6702 | rc = __e1000_resume(pdev); |
6703 | if (rc) | |
6704 | return rc; | |
a0340162 | 6705 | |
63eb48f1 | 6706 | if (netdev->flags & IFF_UP) |
386164d9 | 6707 | e1000e_up(adapter); |
a0340162 | 6708 | |
63eb48f1 | 6709 | return rc; |
a0340162 | 6710 | } |
23606cf5 | 6711 | |
63eb48f1 | 6712 | static int e1000e_pm_runtime_suspend(struct device *dev) |
23606cf5 RW |
6713 | { |
6714 | struct pci_dev *pdev = to_pci_dev(dev); | |
6715 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6716 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6717 | ||
63eb48f1 DE |
6718 | if (netdev->flags & IFF_UP) { |
6719 | int count = E1000_CHECK_RESET_COUNT; | |
6720 | ||
6721 | while (test_bit(__E1000_RESETTING, &adapter->state) && count--) | |
6722 | usleep_range(10000, 20000); | |
23606cf5 | 6723 | |
63eb48f1 DE |
6724 | WARN_ON(test_bit(__E1000_RESETTING, &adapter->state)); |
6725 | ||
6726 | /* Down the device without resetting the hardware */ | |
6727 | e1000e_down(adapter, false); | |
6728 | } | |
6729 | ||
6730 | if (__e1000_shutdown(pdev, true)) { | |
6731 | e1000e_pm_runtime_resume(dev); | |
6732 | return -EBUSY; | |
6733 | } | |
6734 | ||
6735 | return 0; | |
23606cf5 | 6736 | } |
aa338601 | 6737 | #endif /* CONFIG_PM */ |
bc7f75fa AK |
6738 | |
6739 | static void e1000_shutdown(struct pci_dev *pdev) | |
6740 | { | |
2a7e19af DE |
6741 | e1000e_flush_lpic(pdev); |
6742 | ||
28002099 DE |
6743 | e1000e_pm_freeze(&pdev->dev); |
6744 | ||
66148bab | 6745 | __e1000_shutdown(pdev, false); |
bc7f75fa AK |
6746 | } |
6747 | ||
6748 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
147b2c8c | 6749 | |
8bb62869 | 6750 | static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data) |
147b2c8c DD |
6751 | { |
6752 | struct net_device *netdev = data; | |
6753 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
147b2c8c DD |
6754 | |
6755 | if (adapter->msix_entries) { | |
90da0669 BA |
6756 | int vector, msix_irq; |
6757 | ||
147b2c8c DD |
6758 | vector = 0; |
6759 | msix_irq = adapter->msix_entries[vector].vector; | |
fd8e597b KK |
6760 | if (disable_hardirq(msix_irq)) |
6761 | e1000_intr_msix_rx(msix_irq, netdev); | |
147b2c8c DD |
6762 | enable_irq(msix_irq); |
6763 | ||
6764 | vector++; | |
6765 | msix_irq = adapter->msix_entries[vector].vector; | |
fd8e597b KK |
6766 | if (disable_hardirq(msix_irq)) |
6767 | e1000_intr_msix_tx(msix_irq, netdev); | |
147b2c8c DD |
6768 | enable_irq(msix_irq); |
6769 | ||
6770 | vector++; | |
6771 | msix_irq = adapter->msix_entries[vector].vector; | |
fd8e597b KK |
6772 | if (disable_hardirq(msix_irq)) |
6773 | e1000_msix_other(msix_irq, netdev); | |
147b2c8c DD |
6774 | enable_irq(msix_irq); |
6775 | } | |
6776 | ||
6777 | return IRQ_HANDLED; | |
6778 | } | |
6779 | ||
e921eb1a BA |
6780 | /** |
6781 | * e1000_netpoll | |
6782 | * @netdev: network interface device structure | |
6783 | * | |
bc7f75fa AK |
6784 | * Polling 'interrupt' - used by things like netconsole to send skbs |
6785 | * without having to re-enable interrupts. It's not called while | |
6786 | * the interrupt routine is executing. | |
6787 | */ | |
6788 | static void e1000_netpoll(struct net_device *netdev) | |
6789 | { | |
6790 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6791 | ||
147b2c8c DD |
6792 | switch (adapter->int_mode) { |
6793 | case E1000E_INT_MODE_MSIX: | |
6794 | e1000_intr_msix(adapter->pdev->irq, netdev); | |
6795 | break; | |
6796 | case E1000E_INT_MODE_MSI: | |
31119129 WC |
6797 | if (disable_hardirq(adapter->pdev->irq)) |
6798 | e1000_intr_msi(adapter->pdev->irq, netdev); | |
147b2c8c DD |
6799 | enable_irq(adapter->pdev->irq); |
6800 | break; | |
e80bd1d1 | 6801 | default: /* E1000E_INT_MODE_LEGACY */ |
31119129 WC |
6802 | if (disable_hardirq(adapter->pdev->irq)) |
6803 | e1000_intr(adapter->pdev->irq, netdev); | |
147b2c8c DD |
6804 | enable_irq(adapter->pdev->irq); |
6805 | break; | |
6806 | } | |
bc7f75fa AK |
6807 | } |
6808 | #endif | |
6809 | ||
6810 | /** | |
6811 | * e1000_io_error_detected - called when PCI error is detected | |
6812 | * @pdev: Pointer to PCI device | |
6813 | * @state: The current pci connection state | |
6814 | * | |
6815 | * This function is called after a PCI bus error affecting | |
6816 | * this device has been detected. | |
6817 | */ | |
6818 | static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev, | |
6819 | pci_channel_state_t state) | |
6820 | { | |
6821 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6822 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6823 | ||
6824 | netif_device_detach(netdev); | |
6825 | ||
c93b5a76 MM |
6826 | if (state == pci_channel_io_perm_failure) |
6827 | return PCI_ERS_RESULT_DISCONNECT; | |
6828 | ||
bc7f75fa | 6829 | if (netif_running(netdev)) |
28002099 | 6830 | e1000e_down(adapter, true); |
bc7f75fa AK |
6831 | pci_disable_device(pdev); |
6832 | ||
6833 | /* Request a slot slot reset. */ | |
6834 | return PCI_ERS_RESULT_NEED_RESET; | |
6835 | } | |
6836 | ||
6837 | /** | |
6838 | * e1000_io_slot_reset - called after the pci bus has been reset. | |
6839 | * @pdev: Pointer to PCI device | |
6840 | * | |
6841 | * Restart the card from scratch, as if from a cold-boot. Implementation | |
28002099 | 6842 | * resembles the first-half of the e1000e_pm_resume routine. |
bc7f75fa AK |
6843 | */ |
6844 | static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev) | |
6845 | { | |
6846 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6847 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6848 | struct e1000_hw *hw = &adapter->hw; | |
78cd29d5 | 6849 | u16 aspm_disable_flag = 0; |
6e4f6f6b | 6850 | int err; |
111b9dc5 | 6851 | pci_ers_result_t result; |
bc7f75fa | 6852 | |
78cd29d5 BA |
6853 | if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S) |
6854 | aspm_disable_flag = PCIE_LINK_STATE_L0S; | |
6f461f6c | 6855 | if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1) |
78cd29d5 BA |
6856 | aspm_disable_flag |= PCIE_LINK_STATE_L1; |
6857 | if (aspm_disable_flag) | |
2758f9ed | 6858 | e1000e_disable_aspm_locked(pdev, aspm_disable_flag); |
78cd29d5 | 6859 | |
f0f422e5 | 6860 | err = pci_enable_device_mem(pdev); |
6e4f6f6b | 6861 | if (err) { |
bc7f75fa AK |
6862 | dev_err(&pdev->dev, |
6863 | "Cannot re-enable PCI device after reset.\n"); | |
111b9dc5 JB |
6864 | result = PCI_ERS_RESULT_DISCONNECT; |
6865 | } else { | |
23606cf5 | 6866 | pdev->state_saved = true; |
111b9dc5 | 6867 | pci_restore_state(pdev); |
66148bab | 6868 | pci_set_master(pdev); |
bc7f75fa | 6869 | |
111b9dc5 JB |
6870 | pci_enable_wake(pdev, PCI_D3hot, 0); |
6871 | pci_enable_wake(pdev, PCI_D3cold, 0); | |
bc7f75fa | 6872 | |
111b9dc5 JB |
6873 | e1000e_reset(adapter); |
6874 | ew32(WUS, ~0); | |
6875 | result = PCI_ERS_RESULT_RECOVERED; | |
6876 | } | |
bc7f75fa | 6877 | |
111b9dc5 JB |
6878 | pci_cleanup_aer_uncorrect_error_status(pdev); |
6879 | ||
6880 | return result; | |
bc7f75fa AK |
6881 | } |
6882 | ||
6883 | /** | |
6884 | * e1000_io_resume - called when traffic can start flowing again. | |
6885 | * @pdev: Pointer to PCI device | |
6886 | * | |
6887 | * This callback is called when the error recovery driver tells us that | |
6888 | * its OK to resume normal operation. Implementation resembles the | |
28002099 | 6889 | * second-half of the e1000e_pm_resume routine. |
bc7f75fa AK |
6890 | */ |
6891 | static void e1000_io_resume(struct pci_dev *pdev) | |
6892 | { | |
6893 | struct net_device *netdev = pci_get_drvdata(pdev); | |
6894 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6895 | ||
cd791618 | 6896 | e1000_init_manageability_pt(adapter); |
bc7f75fa | 6897 | |
386164d9 AD |
6898 | if (netif_running(netdev)) |
6899 | e1000e_up(adapter); | |
bc7f75fa AK |
6900 | |
6901 | netif_device_attach(netdev); | |
6902 | ||
e921eb1a | 6903 | /* If the controller has AMT, do not set DRV_LOAD until the interface |
bc7f75fa | 6904 | * is up. For all other cases, let the f/w know that the h/w is now |
ad68076e BA |
6905 | * under the control of the driver. |
6906 | */ | |
c43bc57e | 6907 | if (!(adapter->flags & FLAG_HAS_AMT)) |
31dbe5b4 | 6908 | e1000e_get_hw_control(adapter); |
bc7f75fa AK |
6909 | } |
6910 | ||
6911 | static void e1000_print_device_info(struct e1000_adapter *adapter) | |
6912 | { | |
6913 | struct e1000_hw *hw = &adapter->hw; | |
6914 | struct net_device *netdev = adapter->netdev; | |
073287c0 BA |
6915 | u32 ret_val; |
6916 | u8 pba_str[E1000_PBANUM_LENGTH]; | |
bc7f75fa AK |
6917 | |
6918 | /* print bus type/speed/width info */ | |
a5cc7642 | 6919 | e_info("(PCI Express:2.5GT/s:%s) %pM\n", |
44defeb3 JK |
6920 | /* bus width */ |
6921 | ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : | |
f0ff4398 | 6922 | "Width x1"), |
44defeb3 | 6923 | /* MAC address */ |
7c510e4b | 6924 | netdev->dev_addr); |
44defeb3 JK |
6925 | e_info("Intel(R) PRO/%s Network Connection\n", |
6926 | (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000"); | |
073287c0 BA |
6927 | ret_val = e1000_read_pba_string_generic(hw, pba_str, |
6928 | E1000_PBANUM_LENGTH); | |
6929 | if (ret_val) | |
f2315bf1 | 6930 | strlcpy((char *)pba_str, "Unknown", sizeof(pba_str)); |
073287c0 BA |
6931 | e_info("MAC: %d, PHY: %d, PBA No: %s\n", |
6932 | hw->mac.type, hw->phy.type, pba_str); | |
bc7f75fa AK |
6933 | } |
6934 | ||
10aa4c04 AK |
6935 | static void e1000_eeprom_checks(struct e1000_adapter *adapter) |
6936 | { | |
6937 | struct e1000_hw *hw = &adapter->hw; | |
6938 | int ret_val; | |
6939 | u16 buf = 0; | |
6940 | ||
6941 | if (hw->mac.type != e1000_82573) | |
6942 | return; | |
6943 | ||
6944 | ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf); | |
e885d762 | 6945 | le16_to_cpus(&buf); |
18dd2392 | 6946 | if (!ret_val && (!(buf & BIT(0)))) { |
10aa4c04 | 6947 | /* Deep Smart Power Down (DSPD) */ |
6c2a9efa FP |
6948 | dev_warn(&adapter->pdev->dev, |
6949 | "Warning: detected DSPD enabled in EEPROM\n"); | |
10aa4c04 | 6950 | } |
10aa4c04 AK |
6951 | } |
6952 | ||
55e7fe5b AD |
6953 | static netdev_features_t e1000_fix_features(struct net_device *netdev, |
6954 | netdev_features_t features) | |
6955 | { | |
6956 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
6957 | struct e1000_hw *hw = &adapter->hw; | |
6958 | ||
6959 | /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */ | |
6960 | if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN)) | |
6961 | features &= ~NETIF_F_RXFCS; | |
6962 | ||
83808641 JW |
6963 | /* Since there is no support for separate Rx/Tx vlan accel |
6964 | * enable/disable make sure Tx flag is always in same state as Rx. | |
6965 | */ | |
6966 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
6967 | features |= NETIF_F_HW_VLAN_CTAG_TX; | |
6968 | else | |
6969 | features &= ~NETIF_F_HW_VLAN_CTAG_TX; | |
6970 | ||
55e7fe5b AD |
6971 | return features; |
6972 | } | |
6973 | ||
c8f44aff | 6974 | static int e1000_set_features(struct net_device *netdev, |
70495a50 | 6975 | netdev_features_t features) |
dc221294 BA |
6976 | { |
6977 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
c8f44aff | 6978 | netdev_features_t changed = features ^ netdev->features; |
dc221294 BA |
6979 | |
6980 | if (changed & (NETIF_F_TSO | NETIF_F_TSO6)) | |
6981 | adapter->flags |= FLAG_TSO_FORCE; | |
6982 | ||
f646968f | 6983 | if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX | |
cf955e6c BG |
6984 | NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS | |
6985 | NETIF_F_RXALL))) | |
dc221294 BA |
6986 | return 0; |
6987 | ||
0184039a BG |
6988 | if (changed & NETIF_F_RXFCS) { |
6989 | if (features & NETIF_F_RXFCS) { | |
6990 | adapter->flags2 &= ~FLAG2_CRC_STRIPPING; | |
6991 | } else { | |
6992 | /* We need to take it back to defaults, which might mean | |
6993 | * stripping is still disabled at the adapter level. | |
6994 | */ | |
6995 | if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING) | |
6996 | adapter->flags2 |= FLAG2_CRC_STRIPPING; | |
6997 | else | |
6998 | adapter->flags2 &= ~FLAG2_CRC_STRIPPING; | |
6999 | } | |
7000 | } | |
7001 | ||
70495a50 BA |
7002 | netdev->features = features; |
7003 | ||
dc221294 BA |
7004 | if (netif_running(netdev)) |
7005 | e1000e_reinit_locked(adapter); | |
7006 | else | |
7007 | e1000e_reset(adapter); | |
7008 | ||
7009 | return 0; | |
7010 | } | |
7011 | ||
651c2466 | 7012 | static const struct net_device_ops e1000e_netdev_ops = { |
d5ea45da SA |
7013 | .ndo_open = e1000e_open, |
7014 | .ndo_stop = e1000e_close, | |
00829823 | 7015 | .ndo_start_xmit = e1000_xmit_frame, |
67fd4fcb | 7016 | .ndo_get_stats64 = e1000e_get_stats64, |
ef9b965a | 7017 | .ndo_set_rx_mode = e1000e_set_rx_mode, |
651c2466 SH |
7018 | .ndo_set_mac_address = e1000_set_mac, |
7019 | .ndo_change_mtu = e1000_change_mtu, | |
7020 | .ndo_do_ioctl = e1000_ioctl, | |
7021 | .ndo_tx_timeout = e1000_tx_timeout, | |
7022 | .ndo_validate_addr = eth_validate_addr, | |
7023 | ||
651c2466 SH |
7024 | .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid, |
7025 | .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid, | |
7026 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
7027 | .ndo_poll_controller = e1000_netpoll, | |
7028 | #endif | |
dc221294 | 7029 | .ndo_set_features = e1000_set_features, |
55e7fe5b | 7030 | .ndo_fix_features = e1000_fix_features, |
f2701b18 | 7031 | .ndo_features_check = passthru_features_check, |
651c2466 SH |
7032 | }; |
7033 | ||
bc7f75fa AK |
7034 | /** |
7035 | * e1000_probe - Device Initialization Routine | |
7036 | * @pdev: PCI device information struct | |
7037 | * @ent: entry in e1000_pci_tbl | |
7038 | * | |
7039 | * Returns 0 on success, negative on failure | |
7040 | * | |
7041 | * e1000_probe initializes an adapter identified by a pci_dev structure. | |
7042 | * The OS initialization, configuring of the adapter private structure, | |
7043 | * and a hardware reset occur. | |
7044 | **/ | |
1dd06ae8 | 7045 | static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent) |
bc7f75fa AK |
7046 | { |
7047 | struct net_device *netdev; | |
7048 | struct e1000_adapter *adapter; | |
7049 | struct e1000_hw *hw; | |
7050 | const struct e1000_info *ei = e1000_info_tbl[ent->driver_data]; | |
f47e81fc BB |
7051 | resource_size_t mmio_start, mmio_len; |
7052 | resource_size_t flash_start, flash_len; | |
bc7f75fa | 7053 | static int cards_found; |
78cd29d5 | 7054 | u16 aspm_disable_flag = 0; |
17e813ec | 7055 | int bars, i, err, pci_using_dac; |
bc7f75fa AK |
7056 | u16 eeprom_data = 0; |
7057 | u16 eeprom_apme_mask = E1000_EEPROM_APME; | |
847042a6 | 7058 | s32 ret_val = 0; |
bc7f75fa | 7059 | |
78cd29d5 BA |
7060 | if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S) |
7061 | aspm_disable_flag = PCIE_LINK_STATE_L0S; | |
6f461f6c | 7062 | if (ei->flags2 & FLAG2_DISABLE_ASPM_L1) |
78cd29d5 BA |
7063 | aspm_disable_flag |= PCIE_LINK_STATE_L1; |
7064 | if (aspm_disable_flag) | |
7065 | e1000e_disable_aspm(pdev, aspm_disable_flag); | |
6e4f6f6b | 7066 | |
f0f422e5 | 7067 | err = pci_enable_device_mem(pdev); |
bc7f75fa AK |
7068 | if (err) |
7069 | return err; | |
7070 | ||
7071 | pci_using_dac = 0; | |
718a39eb | 7072 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
bc7f75fa | 7073 | if (!err) { |
718a39eb | 7074 | pci_using_dac = 1; |
bc7f75fa | 7075 | } else { |
718a39eb | 7076 | err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
bc7f75fa | 7077 | if (err) { |
718a39eb RK |
7078 | dev_err(&pdev->dev, |
7079 | "No usable DMA configuration, aborting\n"); | |
7080 | goto err_dma; | |
bc7f75fa AK |
7081 | } |
7082 | } | |
7083 | ||
17e813ec BA |
7084 | bars = pci_select_bars(pdev, IORESOURCE_MEM); |
7085 | err = pci_request_selected_regions_exclusive(pdev, bars, | |
7086 | e1000e_driver_name); | |
bc7f75fa AK |
7087 | if (err) |
7088 | goto err_pci_reg; | |
7089 | ||
68eac460 | 7090 | /* AER (Advanced Error Reporting) hooks */ |
19d5afd4 | 7091 | pci_enable_pcie_error_reporting(pdev); |
68eac460 | 7092 | |
bc7f75fa | 7093 | pci_set_master(pdev); |
438b365a BA |
7094 | /* PCI config space info */ |
7095 | err = pci_save_state(pdev); | |
7096 | if (err) | |
7097 | goto err_alloc_etherdev; | |
bc7f75fa AK |
7098 | |
7099 | err = -ENOMEM; | |
7100 | netdev = alloc_etherdev(sizeof(struct e1000_adapter)); | |
7101 | if (!netdev) | |
7102 | goto err_alloc_etherdev; | |
7103 | ||
bc7f75fa AK |
7104 | SET_NETDEV_DEV(netdev, &pdev->dev); |
7105 | ||
f85e4dfa TH |
7106 | netdev->irq = pdev->irq; |
7107 | ||
bc7f75fa AK |
7108 | pci_set_drvdata(pdev, netdev); |
7109 | adapter = netdev_priv(netdev); | |
7110 | hw = &adapter->hw; | |
7111 | adapter->netdev = netdev; | |
7112 | adapter->pdev = pdev; | |
7113 | adapter->ei = ei; | |
7114 | adapter->pba = ei->pba; | |
7115 | adapter->flags = ei->flags; | |
eb7c3adb | 7116 | adapter->flags2 = ei->flags2; |
bc7f75fa AK |
7117 | adapter->hw.adapter = adapter; |
7118 | adapter->hw.mac.type = ei->mac; | |
2adc55c9 | 7119 | adapter->max_hw_frame_size = ei->max_hw_frame_size; |
b3f4d599 | 7120 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
bc7f75fa AK |
7121 | |
7122 | mmio_start = pci_resource_start(pdev, 0); | |
7123 | mmio_len = pci_resource_len(pdev, 0); | |
7124 | ||
7125 | err = -EIO; | |
7126 | adapter->hw.hw_addr = ioremap(mmio_start, mmio_len); | |
7127 | if (!adapter->hw.hw_addr) | |
7128 | goto err_ioremap; | |
7129 | ||
7130 | if ((adapter->flags & FLAG_HAS_FLASH) && | |
1103a631 YL |
7131 | (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) && |
7132 | (hw->mac.type < e1000_pch_spt)) { | |
bc7f75fa AK |
7133 | flash_start = pci_resource_start(pdev, 1); |
7134 | flash_len = pci_resource_len(pdev, 1); | |
7135 | adapter->hw.flash_address = ioremap(flash_start, flash_len); | |
7136 | if (!adapter->hw.flash_address) | |
7137 | goto err_flashmap; | |
7138 | } | |
7139 | ||
d495bcb8 BA |
7140 | /* Set default EEE advertisement */ |
7141 | if (adapter->flags2 & FLAG2_HAS_EEE) | |
7142 | adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; | |
7143 | ||
bc7f75fa | 7144 | /* construct the net_device struct */ |
e80bd1d1 | 7145 | netdev->netdev_ops = &e1000e_netdev_ops; |
bc7f75fa | 7146 | e1000e_set_ethtool_ops(netdev); |
e80bd1d1 | 7147 | netdev->watchdog_timeo = 5 * HZ; |
c58c8a78 | 7148 | netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64); |
f2315bf1 | 7149 | strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name)); |
bc7f75fa AK |
7150 | |
7151 | netdev->mem_start = mmio_start; | |
7152 | netdev->mem_end = mmio_start + mmio_len; | |
7153 | ||
7154 | adapter->bd_number = cards_found++; | |
7155 | ||
4662e82b BA |
7156 | e1000e_check_options(adapter); |
7157 | ||
bc7f75fa AK |
7158 | /* setup adapter struct */ |
7159 | err = e1000_sw_init(adapter); | |
7160 | if (err) | |
7161 | goto err_sw_init; | |
7162 | ||
bc7f75fa AK |
7163 | memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); |
7164 | memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); | |
7165 | memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); | |
7166 | ||
69e3fd8c | 7167 | err = ei->get_variants(adapter); |
bc7f75fa AK |
7168 | if (err) |
7169 | goto err_hw_init; | |
7170 | ||
4a770358 | 7171 | if ((adapter->flags & FLAG_IS_ICH) && |
152c0a97 YL |
7172 | (adapter->flags & FLAG_READ_ONLY_NVM) && |
7173 | (hw->mac.type < e1000_pch_spt)) | |
4a770358 BA |
7174 | e1000e_write_protect_nvm_ich8lan(&adapter->hw); |
7175 | ||
bc7f75fa AK |
7176 | hw->mac.ops.get_bus_info(&adapter->hw); |
7177 | ||
318a94d6 | 7178 | adapter->hw.phy.autoneg_wait_to_complete = 0; |
bc7f75fa AK |
7179 | |
7180 | /* Copper options */ | |
318a94d6 | 7181 | if (adapter->hw.phy.media_type == e1000_media_type_copper) { |
bc7f75fa AK |
7182 | adapter->hw.phy.mdix = AUTO_ALL_MODES; |
7183 | adapter->hw.phy.disable_polarity_correction = 0; | |
7184 | adapter->hw.phy.ms_type = e1000_ms_hw_default; | |
7185 | } | |
7186 | ||
470a5420 | 7187 | if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw)) |
185095fb BA |
7188 | dev_info(&pdev->dev, |
7189 | "PHY reset is blocked due to SOL/IDER session.\n"); | |
bc7f75fa | 7190 | |
dc221294 BA |
7191 | /* Set initial default active device features */ |
7192 | netdev->features = (NETIF_F_SG | | |
f646968f PM |
7193 | NETIF_F_HW_VLAN_CTAG_RX | |
7194 | NETIF_F_HW_VLAN_CTAG_TX | | |
dc221294 BA |
7195 | NETIF_F_TSO | |
7196 | NETIF_F_TSO6 | | |
70495a50 | 7197 | NETIF_F_RXHASH | |
dc221294 BA |
7198 | NETIF_F_RXCSUM | |
7199 | NETIF_F_HW_CSUM); | |
7200 | ||
7201 | /* Set user-changeable features (subset of all device features) */ | |
7202 | netdev->hw_features = netdev->features; | |
0184039a | 7203 | netdev->hw_features |= NETIF_F_RXFCS; |
943146de | 7204 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
cf955e6c | 7205 | netdev->hw_features |= NETIF_F_RXALL; |
bc7f75fa AK |
7206 | |
7207 | if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) | |
f646968f | 7208 | netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; |
bc7f75fa | 7209 | |
dc221294 BA |
7210 | netdev->vlan_features |= (NETIF_F_SG | |
7211 | NETIF_F_TSO | | |
7212 | NETIF_F_TSO6 | | |
7213 | NETIF_F_HW_CSUM); | |
a5136e23 | 7214 | |
ef9b965a JB |
7215 | netdev->priv_flags |= IFF_UNICAST_FLT; |
7216 | ||
7b872a55 | 7217 | if (pci_using_dac) { |
bc7f75fa | 7218 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7219 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7220 | } | |
bc7f75fa | 7221 | |
91c527a5 JW |
7222 | /* MTU range: 68 - max_hw_frame_size */ |
7223 | netdev->min_mtu = ETH_MIN_MTU; | |
7224 | netdev->max_mtu = adapter->max_hw_frame_size - | |
7225 | (VLAN_ETH_HLEN + ETH_FCS_LEN); | |
7226 | ||
bc7f75fa AK |
7227 | if (e1000e_enable_mng_pass_thru(&adapter->hw)) |
7228 | adapter->flags |= FLAG_MNG_PT_ENABLED; | |
7229 | ||
e921eb1a | 7230 | /* before reading the NVM, reset the controller to |
ad68076e BA |
7231 | * put the device in a known good starting state |
7232 | */ | |
bc7f75fa AK |
7233 | adapter->hw.mac.ops.reset_hw(&adapter->hw); |
7234 | ||
e921eb1a | 7235 | /* systems with ASPM and others may see the checksum fail on the first |
bc7f75fa AK |
7236 | * attempt. Let's give it a few tries |
7237 | */ | |
7238 | for (i = 0;; i++) { | |
7239 | if (e1000_validate_nvm_checksum(&adapter->hw) >= 0) | |
7240 | break; | |
7241 | if (i == 2) { | |
185095fb | 7242 | dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); |
bc7f75fa AK |
7243 | err = -EIO; |
7244 | goto err_eeprom; | |
7245 | } | |
7246 | } | |
7247 | ||
10aa4c04 AK |
7248 | e1000_eeprom_checks(adapter); |
7249 | ||
608f8a0d | 7250 | /* copy the MAC address */ |
bc7f75fa | 7251 | if (e1000e_read_mac_addr(&adapter->hw)) |
185095fb BA |
7252 | dev_err(&pdev->dev, |
7253 | "NVM Read Error while reading MAC address\n"); | |
bc7f75fa AK |
7254 | |
7255 | memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); | |
bc7f75fa | 7256 | |
aaeb6cdf | 7257 | if (!is_valid_ether_addr(netdev->dev_addr)) { |
185095fb | 7258 | dev_err(&pdev->dev, "Invalid MAC Address: %pM\n", |
aaeb6cdf | 7259 | netdev->dev_addr); |
bc7f75fa AK |
7260 | err = -EIO; |
7261 | goto err_eeprom; | |
7262 | } | |
7263 | ||
26566eae KC |
7264 | timer_setup(&adapter->watchdog_timer, e1000_watchdog, 0); |
7265 | timer_setup(&adapter->phy_info_timer, e1000_update_phy_info, 0); | |
bc7f75fa AK |
7266 | |
7267 | INIT_WORK(&adapter->reset_task, e1000_reset_task); | |
7268 | INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task); | |
a8f88ff5 JB |
7269 | INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround); |
7270 | INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task); | |
41cec6f1 | 7271 | INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang); |
bc7f75fa | 7272 | |
bc7f75fa AK |
7273 | /* Initialize link parameters. User can change them with ethtool */ |
7274 | adapter->hw.mac.autoneg = 1; | |
3db1cd5c | 7275 | adapter->fc_autoneg = true; |
5c48ef3e BA |
7276 | adapter->hw.fc.requested_mode = e1000_fc_default; |
7277 | adapter->hw.fc.current_mode = e1000_fc_default; | |
bc7f75fa AK |
7278 | adapter->hw.phy.autoneg_advertised = 0x2f; |
7279 | ||
e921eb1a | 7280 | /* Initial Wake on LAN setting - If APM wake is enabled in |
bc7f75fa AK |
7281 | * the EEPROM, enable the ACPI Magic Packet filter |
7282 | */ | |
7283 | if (adapter->flags & FLAG_APME_IN_WUC) { | |
7284 | /* APME bit in EEPROM is mapped to WUC.APME */ | |
7285 | eeprom_data = er32(WUC); | |
7286 | eeprom_apme_mask = E1000_WUC_APME; | |
4def99bb BA |
7287 | if ((hw->mac.type > e1000_ich10lan) && |
7288 | (eeprom_data & E1000_WUC_PHY_WAKE)) | |
a4f58f54 | 7289 | adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP; |
bc7f75fa AK |
7290 | } else if (adapter->flags & FLAG_APME_IN_CTRL3) { |
7291 | if (adapter->flags & FLAG_APME_CHECK_PORT_B && | |
7292 | (adapter->hw.bus.func == 1)) | |
847042a6 | 7293 | ret_val = e1000_read_nvm(&adapter->hw, |
491a04d2 DE |
7294 | NVM_INIT_CONTROL3_PORT_B, |
7295 | 1, &eeprom_data); | |
bc7f75fa | 7296 | else |
847042a6 | 7297 | ret_val = e1000_read_nvm(&adapter->hw, |
491a04d2 DE |
7298 | NVM_INIT_CONTROL3_PORT_A, |
7299 | 1, &eeprom_data); | |
bc7f75fa AK |
7300 | } |
7301 | ||
7302 | /* fetch WoL from EEPROM */ | |
847042a6 BW |
7303 | if (ret_val) |
7304 | e_dbg("NVM read error getting WoL initial values: %d\n", ret_val); | |
491a04d2 | 7305 | else if (eeprom_data & eeprom_apme_mask) |
bc7f75fa AK |
7306 | adapter->eeprom_wol |= E1000_WUFC_MAG; |
7307 | ||
e921eb1a | 7308 | /* now that we have the eeprom settings, apply the special cases |
bc7f75fa AK |
7309 | * where the eeprom may be wrong or the board simply won't support |
7310 | * wake on lan on a particular port | |
7311 | */ | |
7312 | if (!(adapter->flags & FLAG_HAS_WOL)) | |
7313 | adapter->eeprom_wol = 0; | |
7314 | ||
7315 | /* initialize the wol settings based on the eeprom settings */ | |
7316 | adapter->wol = adapter->eeprom_wol; | |
66148bab KK |
7317 | |
7318 | /* make sure adapter isn't asleep if manageability is enabled */ | |
7319 | if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) || | |
7320 | (hw->mac.ops.check_mng_mode(hw))) | |
7321 | device_wakeup_enable(&pdev->dev); | |
bc7f75fa | 7322 | |
84527590 | 7323 | /* save off EEPROM version number */ |
847042a6 | 7324 | ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers); |
491a04d2 | 7325 | |
847042a6 BW |
7326 | if (ret_val) { |
7327 | e_dbg("NVM read error getting EEPROM version: %d\n", ret_val); | |
491a04d2 DE |
7328 | adapter->eeprom_vers = 0; |
7329 | } | |
84527590 | 7330 | |
aa524b66 JK |
7331 | /* init PTP hardware clock */ |
7332 | e1000e_ptp_init(adapter); | |
7333 | ||
bc7f75fa AK |
7334 | /* reset the hardware with the new settings */ |
7335 | e1000e_reset(adapter); | |
7336 | ||
e921eb1a | 7337 | /* If the controller has AMT, do not set DRV_LOAD until the interface |
bc7f75fa | 7338 | * is up. For all other cases, let the f/w know that the h/w is now |
ad68076e BA |
7339 | * under the control of the driver. |
7340 | */ | |
c43bc57e | 7341 | if (!(adapter->flags & FLAG_HAS_AMT)) |
31dbe5b4 | 7342 | e1000e_get_hw_control(adapter); |
bc7f75fa | 7343 | |
f2315bf1 | 7344 | strlcpy(netdev->name, "eth%d", sizeof(netdev->name)); |
bc7f75fa AK |
7345 | err = register_netdev(netdev); |
7346 | if (err) | |
7347 | goto err_register; | |
7348 | ||
9c563d20 JB |
7349 | /* carrier off reporting is important to ethtool even BEFORE open */ |
7350 | netif_carrier_off(netdev); | |
7351 | ||
bc7f75fa AK |
7352 | e1000_print_device_info(adapter); |
7353 | ||
f3ec4f87 AS |
7354 | if (pci_dev_run_wake(pdev)) |
7355 | pm_runtime_put_noidle(&pdev->dev); | |
23606cf5 | 7356 | |
bc7f75fa AK |
7357 | return 0; |
7358 | ||
7359 | err_register: | |
c43bc57e | 7360 | if (!(adapter->flags & FLAG_HAS_AMT)) |
31dbe5b4 | 7361 | e1000e_release_hw_control(adapter); |
bc7f75fa | 7362 | err_eeprom: |
470a5420 | 7363 | if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw)) |
bc7f75fa | 7364 | e1000_phy_hw_reset(&adapter->hw); |
c43bc57e | 7365 | err_hw_init: |
bc7f75fa AK |
7366 | kfree(adapter->tx_ring); |
7367 | kfree(adapter->rx_ring); | |
7368 | err_sw_init: | |
1103a631 | 7369 | if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt)) |
c43bc57e | 7370 | iounmap(adapter->hw.flash_address); |
e82f54ba | 7371 | e1000e_reset_interrupt_capability(adapter); |
c43bc57e | 7372 | err_flashmap: |
bc7f75fa AK |
7373 | iounmap(adapter->hw.hw_addr); |
7374 | err_ioremap: | |
7375 | free_netdev(netdev); | |
7376 | err_alloc_etherdev: | |
56d766d6 | 7377 | pci_release_mem_regions(pdev); |
bc7f75fa AK |
7378 | err_pci_reg: |
7379 | err_dma: | |
7380 | pci_disable_device(pdev); | |
7381 | return err; | |
7382 | } | |
7383 | ||
7384 | /** | |
7385 | * e1000_remove - Device Removal Routine | |
7386 | * @pdev: PCI device information struct | |
7387 | * | |
7388 | * e1000_remove is called by the PCI subsystem to alert the driver | |
7389 | * that it should release a PCI device. The could be caused by a | |
7390 | * Hot-Plug event, or because the driver is going to be removed from | |
7391 | * memory. | |
7392 | **/ | |
9f9a12f8 | 7393 | static void e1000_remove(struct pci_dev *pdev) |
bc7f75fa AK |
7394 | { |
7395 | struct net_device *netdev = pci_get_drvdata(pdev); | |
7396 | struct e1000_adapter *adapter = netdev_priv(netdev); | |
23606cf5 RW |
7397 | bool down = test_bit(__E1000_DOWN, &adapter->state); |
7398 | ||
d89777bf BA |
7399 | e1000e_ptp_remove(adapter); |
7400 | ||
e921eb1a | 7401 | /* The timers may be rescheduled, so explicitly disable them |
23f333a2 | 7402 | * from being rescheduled. |
ad68076e | 7403 | */ |
23606cf5 RW |
7404 | if (!down) |
7405 | set_bit(__E1000_DOWN, &adapter->state); | |
bc7f75fa AK |
7406 | del_timer_sync(&adapter->watchdog_timer); |
7407 | del_timer_sync(&adapter->phy_info_timer); | |
7408 | ||
41cec6f1 BA |
7409 | cancel_work_sync(&adapter->reset_task); |
7410 | cancel_work_sync(&adapter->watchdog_task); | |
7411 | cancel_work_sync(&adapter->downshift_task); | |
7412 | cancel_work_sync(&adapter->update_phy_task); | |
7413 | cancel_work_sync(&adapter->print_hang_task); | |
bc7f75fa | 7414 | |
b67e1913 BA |
7415 | if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) { |
7416 | cancel_work_sync(&adapter->tx_hwtstamp_work); | |
7417 | if (adapter->tx_hwtstamp_skb) { | |
377b6273 | 7418 | dev_consume_skb_any(adapter->tx_hwtstamp_skb); |
b67e1913 BA |
7419 | adapter->tx_hwtstamp_skb = NULL; |
7420 | } | |
7421 | } | |
7422 | ||
23606cf5 RW |
7423 | /* Don't lie to e1000_close() down the road. */ |
7424 | if (!down) | |
7425 | clear_bit(__E1000_DOWN, &adapter->state); | |
17f208de BA |
7426 | unregister_netdev(netdev); |
7427 | ||
f3ec4f87 AS |
7428 | if (pci_dev_run_wake(pdev)) |
7429 | pm_runtime_get_noresume(&pdev->dev); | |
23606cf5 | 7430 | |
e921eb1a | 7431 | /* Release control of h/w to f/w. If f/w is AMT enabled, this |
ad68076e BA |
7432 | * would have already happened in close and is redundant. |
7433 | */ | |
31dbe5b4 | 7434 | e1000e_release_hw_control(adapter); |
bc7f75fa | 7435 | |
4662e82b | 7436 | e1000e_reset_interrupt_capability(adapter); |
bc7f75fa AK |
7437 | kfree(adapter->tx_ring); |
7438 | kfree(adapter->rx_ring); | |
7439 | ||
7440 | iounmap(adapter->hw.hw_addr); | |
1103a631 YL |
7441 | if ((adapter->hw.flash_address) && |
7442 | (adapter->hw.mac.type < e1000_pch_spt)) | |
bc7f75fa | 7443 | iounmap(adapter->hw.flash_address); |
56d766d6 | 7444 | pci_release_mem_regions(pdev); |
bc7f75fa AK |
7445 | |
7446 | free_netdev(netdev); | |
7447 | ||
111b9dc5 | 7448 | /* AER disable */ |
19d5afd4 | 7449 | pci_disable_pcie_error_reporting(pdev); |
111b9dc5 | 7450 | |
bc7f75fa AK |
7451 | pci_disable_device(pdev); |
7452 | } | |
7453 | ||
7454 | /* PCI Error Recovery (ERS) */ | |
3646f0e5 | 7455 | static const struct pci_error_handlers e1000_err_handler = { |
bc7f75fa AK |
7456 | .error_detected = e1000_io_error_detected, |
7457 | .slot_reset = e1000_io_slot_reset, | |
7458 | .resume = e1000_io_resume, | |
7459 | }; | |
7460 | ||
0e8e842b | 7461 | static const struct pci_device_id e1000_pci_tbl[] = { |
bc7f75fa AK |
7462 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 }, |
7463 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 }, | |
7464 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 }, | |
c29c3ba5 BA |
7465 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), |
7466 | board_82571 }, | |
bc7f75fa AK |
7467 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 }, |
7468 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 }, | |
040babf9 AK |
7469 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 }, |
7470 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 }, | |
7471 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 }, | |
ad68076e | 7472 | |
bc7f75fa AK |
7473 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 }, |
7474 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 }, | |
7475 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 }, | |
7476 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 }, | |
ad68076e | 7477 | |
bc7f75fa AK |
7478 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 }, |
7479 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 }, | |
7480 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 }, | |
ad68076e | 7481 | |
4662e82b | 7482 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 }, |
bef28b11 | 7483 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 }, |
8c81c9c3 | 7484 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 }, |
4662e82b | 7485 | |
bc7f75fa AK |
7486 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT), |
7487 | board_80003es2lan }, | |
7488 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT), | |
7489 | board_80003es2lan }, | |
7490 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT), | |
7491 | board_80003es2lan }, | |
7492 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT), | |
7493 | board_80003es2lan }, | |
ad68076e | 7494 | |
bc7f75fa AK |
7495 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan }, |
7496 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan }, | |
7497 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan }, | |
7498 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan }, | |
7499 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan }, | |
7500 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan }, | |
7501 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan }, | |
9e135a2e | 7502 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan }, |
ad68076e | 7503 | |
bc7f75fa AK |
7504 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan }, |
7505 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan }, | |
7506 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan }, | |
7507 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan }, | |
7508 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan }, | |
2f15f9d6 | 7509 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan }, |
97ac8cae BA |
7510 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan }, |
7511 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan }, | |
7512 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan }, | |
7513 | ||
7514 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan }, | |
7515 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan }, | |
7516 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan }, | |
bc7f75fa | 7517 | |
f4187b56 BA |
7518 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan }, |
7519 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan }, | |
10df0b91 | 7520 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan }, |
f4187b56 | 7521 | |
a4f58f54 BA |
7522 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan }, |
7523 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan }, | |
7524 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan }, | |
7525 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan }, | |
7526 | ||
d3738bb8 BA |
7527 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan }, |
7528 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan }, | |
7529 | ||
2fbe4526 BA |
7530 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt }, |
7531 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt }, | |
16e310ae BA |
7532 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt }, |
7533 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt }, | |
91a3d82f BA |
7534 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt }, |
7535 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt }, | |
7536 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt }, | |
7537 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt }, | |
79849ebc DE |
7538 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt }, |
7539 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt }, | |
7540 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt }, | |
7541 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt }, | |
f3ed935d | 7542 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt }, |
9cd34b3a RA |
7543 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt }, |
7544 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, | |
7545 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, | |
7546 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, | |
3a3173b9 SN |
7547 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp }, |
7548 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp }, | |
7549 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp }, | |
7550 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp }, | |
48f76b68 SN |
7551 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp }, |
7552 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp }, | |
7553 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp }, | |
7554 | { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp }, | |
2fbe4526 | 7555 | |
f36bb6ca | 7556 | { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ |
bc7f75fa AK |
7557 | }; |
7558 | MODULE_DEVICE_TABLE(pci, e1000_pci_tbl); | |
7559 | ||
23606cf5 | 7560 | static const struct dev_pm_ops e1000_pm_ops = { |
72f72dcc | 7561 | #ifdef CONFIG_PM_SLEEP |
28002099 DE |
7562 | .suspend = e1000e_pm_suspend, |
7563 | .resume = e1000e_pm_resume, | |
7564 | .freeze = e1000e_pm_freeze, | |
7565 | .thaw = e1000e_pm_thaw, | |
7566 | .poweroff = e1000e_pm_suspend, | |
7567 | .restore = e1000e_pm_resume, | |
72f72dcc | 7568 | #endif |
63eb48f1 DE |
7569 | SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume, |
7570 | e1000e_pm_runtime_idle) | |
23606cf5 RW |
7571 | }; |
7572 | ||
bc7f75fa AK |
7573 | /* PCI Device API Driver */ |
7574 | static struct pci_driver e1000_driver = { | |
7575 | .name = e1000e_driver_name, | |
7576 | .id_table = e1000_pci_tbl, | |
7577 | .probe = e1000_probe, | |
9f9a12f8 | 7578 | .remove = e1000_remove, |
f36bb6ca BA |
7579 | .driver = { |
7580 | .pm = &e1000_pm_ops, | |
7581 | }, | |
bc7f75fa AK |
7582 | .shutdown = e1000_shutdown, |
7583 | .err_handler = &e1000_err_handler | |
7584 | }; | |
7585 | ||
7586 | /** | |
7587 | * e1000_init_module - Driver Registration Routine | |
7588 | * | |
7589 | * e1000_init_module is the first routine called when the driver is | |
7590 | * loaded. All it does is register with the PCI subsystem. | |
7591 | **/ | |
7592 | static int __init e1000_init_module(void) | |
7593 | { | |
8544b9f7 BA |
7594 | pr_info("Intel(R) PRO/1000 Network Driver - %s\n", |
7595 | e1000e_driver_version); | |
529498cd | 7596 | pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n"); |
53ec5498 | 7597 | |
5a5e889c | 7598 | return pci_register_driver(&e1000_driver); |
bc7f75fa AK |
7599 | } |
7600 | module_init(e1000_init_module); | |
7601 | ||
7602 | /** | |
7603 | * e1000_exit_module - Driver Exit Cleanup Routine | |
7604 | * | |
7605 | * e1000_exit_module is called just before the driver is removed | |
7606 | * from memory. | |
7607 | **/ | |
7608 | static void __exit e1000_exit_module(void) | |
7609 | { | |
7610 | pci_unregister_driver(&e1000_driver); | |
7611 | } | |
7612 | module_exit(e1000_exit_module); | |
7613 | ||
bc7f75fa AK |
7614 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
7615 | MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver"); | |
7616 | MODULE_LICENSE("GPL"); | |
7617 | MODULE_VERSION(DRV_VERSION); | |
7618 | ||
06c24b91 | 7619 | /* netdev.c */ |