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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec...
[linux-2.6-block.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
e78b80b1
DE		 1/* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
bc7f75fa 21
8544b9f7
BA		 22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
bc7f75fa
AK		 24#include <linux/module.h>
25#include <linux/types.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/vmalloc.h>
29#include <linux/pagemap.h>
30#include <linux/delay.h>
31#include <linux/netdevice.h>
9fb7a5f7 32#include <linux/interrupt.h>
bc7f75fa
AK		 33#include <linux/tcp.h>
34#include <linux/ipv6.h>
5a0e3ad6 35#include <linux/slab.h>
bc7f75fa
AK		 36#include <net/checksum.h>
37#include <net/ip6_checksum.h>
bc7f75fa
AK		 38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/cpu.h>
41#include <linux/smp.h>
e8db0be1 42#include <linux/pm_qos.h>
23606cf5 43#include <linux/pm_runtime.h>
111b9dc5 44#include <linux/aer.h>
70c71606 45#include <linux/prefetch.h>
bc7f75fa
AK		 46
47#include "e1000.h"
48
b3ccf267 49#define DRV_EXTRAVERSION "-k"
c14c643b 50
8defe713 51#define DRV_VERSION "2.3.2" DRV_EXTRAVERSION
bc7f75fa
AK		 52char e1000e_driver_name[] = "e1000e";
53const char e1000e_driver_version[] = DRV_VERSION;
54
b3f4d599 55#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
56static int debug = -1;
57module_param(debug, int, 0);
58MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
bc7f75fa
AK		 60static const struct e1000_info *e1000_info_tbl[] = {
61 [board_82571] = &e1000_82571_info,
62 [board_82572] = &e1000_82572_info,
63 [board_82573] = &e1000_82573_info,
4662e82b 64 [board_82574] = &e1000_82574_info,
8c81c9c3 65 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 66 [board_80003es2lan] = &e1000_es2_info,
67 [board_ich8lan] = &e1000_ich8_info,
68 [board_ich9lan] = &e1000_ich9_info,
f4187b56 69 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 70 [board_pchlan] = &e1000_pch_info,
d3738bb8 71 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 72 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 73};
74
84f4ee90
TI		 75struct e1000_reg_info {
76 u32 ofs;
77 char *name;
78};
79
84f4ee90 80static const struct e1000_reg_info e1000_reg_info_tbl[] = {
84f4ee90
TI		 81 /* General Registers */
82 {E1000_CTRL, "CTRL"},
83 {E1000_STATUS, "STATUS"},
84 {E1000_CTRL_EXT, "CTRL_EXT"},
85
86 /* Interrupt Registers */
87 {E1000_ICR, "ICR"},
88
af667a29 89 /* Rx Registers */
84f4ee90 90 {E1000_RCTL, "RCTL"},
1e36052e
BA		 91 {E1000_RDLEN(0), "RDLEN"},
92 {E1000_RDH(0), "RDH"},
93 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 94 {E1000_RDTR, "RDTR"},
95 {E1000_RXDCTL(0), "RXDCTL"},
96 {E1000_ERT, "ERT"},
1e36052e
BA		 97 {E1000_RDBAL(0), "RDBAL"},
98 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 99 {E1000_RDFH, "RDFH"},
100 {E1000_RDFT, "RDFT"},
101 {E1000_RDFHS, "RDFHS"},
102 {E1000_RDFTS, "RDFTS"},
103 {E1000_RDFPC, "RDFPC"},
104
af667a29 105 /* Tx Registers */
84f4ee90 106 {E1000_TCTL, "TCTL"},
1e36052e
BA		 107 {E1000_TDBAL(0), "TDBAL"},
108 {E1000_TDBAH(0), "TDBAH"},
109 {E1000_TDLEN(0), "TDLEN"},
110 {E1000_TDH(0), "TDH"},
111 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 112 {E1000_TIDV, "TIDV"},
113 {E1000_TXDCTL(0), "TXDCTL"},
114 {E1000_TADV, "TADV"},
115 {E1000_TARC(0), "TARC"},
116 {E1000_TDFH, "TDFH"},
117 {E1000_TDFT, "TDFT"},
118 {E1000_TDFHS, "TDFHS"},
119 {E1000_TDFTS, "TDFTS"},
120 {E1000_TDFPC, "TDFPC"},
121
122 /* List Terminator */
f36bb6ca 123 {0, NULL}
84f4ee90
TI		 124};
125
e921eb1a 126/**
84f4ee90 127 * e1000_regdump - register printout routine
e921eb1a
BA		 128 * @hw: pointer to the HW structure
129 * @reginfo: pointer to the register info table
130 **/
84f4ee90
TI		 131static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
132{
133 int n = 0;
134 char rname[16];
135 u32 regs[8];
136
137 switch (reginfo->ofs) {
138 case E1000_RXDCTL(0):
139 for (n = 0; n < 2; n++)
140 regs[n] = __er32(hw, E1000_RXDCTL(n));
141 break;
142 case E1000_TXDCTL(0):
143 for (n = 0; n < 2; n++)
144 regs[n] = __er32(hw, E1000_TXDCTL(n));
145 break;
146 case E1000_TARC(0):
147 for (n = 0; n < 2; n++)
148 regs[n] = __er32(hw, E1000_TARC(n));
149 break;
150 default:
ef456f85
JK		 151 pr_info("%-15s %08x\n",
152 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 153 return;
154 }
155
156 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 157 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 158}
159
f0c5dadf
ET		 160static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
161 struct e1000_buffer *bi)
162{
163 int i;
164 struct e1000_ps_page *ps_page;
165
166 for (i = 0; i < adapter->rx_ps_pages; i++) {
167 ps_page = &bi->ps_pages[i];
168
169 if (ps_page->page) {
170 pr_info("packet dump for ps_page %d:\n", i);
171 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
172 16, 1, page_address(ps_page->page),
173 PAGE_SIZE, true);
174 }
175 }
176}
177
e921eb1a 178/**
af667a29 179 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 180 * @adapter: board private structure
181 **/
84f4ee90
TI		 182static void e1000e_dump(struct e1000_adapter *adapter)
183{
184 struct net_device *netdev = adapter->netdev;
185 struct e1000_hw *hw = &adapter->hw;
186 struct e1000_reg_info *reginfo;
187 struct e1000_ring *tx_ring = adapter->tx_ring;
188 struct e1000_tx_desc *tx_desc;
af667a29 189 struct my_u0 {
e885d762
BA		 190 __le64 a;
191 __le64 b;
af667a29 192 } *u0;
84f4ee90
TI		 193 struct e1000_buffer *buffer_info;
194 struct e1000_ring *rx_ring = adapter->rx_ring;
195 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 196 union e1000_rx_desc_extended *rx_desc;
af667a29 197 struct my_u1 {
e885d762
BA		 198 __le64 a;
199 __le64 b;
200 __le64 c;
201 __le64 d;
af667a29 202 } *u1;
84f4ee90
TI		 203 u32 staterr;
204 int i = 0;
205
206 if (!netif_msg_hw(adapter))
207 return;
208
209 /* Print netdevice Info */
210 if (netdev) {
211 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85 212 pr_info("Device Name state trans_start last_rx\n");
e5fe2541
BA		 213 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
214 netdev->state, netdev->trans_start, netdev->last_rx);
84f4ee90
TI		 215 }
216
217 /* Print Registers */
218 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 219 pr_info(" Register Name Value\n");
84f4ee90
TI		 220 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
221 reginfo->name; reginfo++) {
222 e1000_regdump(hw, reginfo);
223 }
224
af667a29 225 /* Print Tx Ring Summary */
84f4ee90 226 if (!netdev || !netif_running(netdev))
fe1e980f 227 return;
84f4ee90 228
af667a29 229 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 230 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 231 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 232 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
233 0, tx_ring->next_to_use, tx_ring->next_to_clean,
234 (unsigned long long)buffer_info->dma,
235 buffer_info->length,
236 buffer_info->next_to_watch,
237 (unsigned long long)buffer_info->time_stamp);
84f4ee90 238
af667a29 239 /* Print Tx Ring */
84f4ee90
TI		 240 if (!netif_msg_tx_done(adapter))
241 goto rx_ring_summary;
242
af667a29 243 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 244
245 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
246 *
247 * Legacy Transmit Descriptor
248 * +--------------------------------------------------------------+
249 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
250 * +--------------------------------------------------------------+
251 * 8 | Special | CSS | Status | CMD | CSO | Length |
252 * +--------------------------------------------------------------+
253 * 63 48 47 36 35 32 31 24 23 16 15 0
254 *
255 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
256 * 63 48 47 40 39 32 31 16 15 8 7 0
257 * +----------------------------------------------------------------+
258 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
259 * +----------------------------------------------------------------+
260 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
261 * +----------------------------------------------------------------+
262 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
263 *
264 * Extended Data Descriptor (DTYP=0x1)
265 * +----------------------------------------------------------------+
266 * 0 | Buffer Address [63:0] |
267 * +----------------------------------------------------------------+
268 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
269 * +----------------------------------------------------------------+
270 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
271 */
ef456f85
JK		 272 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
273 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
274 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 275 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 276 const char *next_desc;
84f4ee90
TI		 277 tx_desc = E1000_TX_DESC(*tx_ring, i);
278 buffer_info = &tx_ring->buffer_info[i];
279 u0 = (struct my_u0 *)tx_desc;
84f4ee90 280 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 281 next_desc = " NTC/U";
84f4ee90 282 else if (i == tx_ring->next_to_use)
ef456f85 283 next_desc = " NTU";
84f4ee90 284 else if (i == tx_ring->next_to_clean)
ef456f85 285 next_desc = " NTC";
84f4ee90 286 else
ef456f85
JK		 287 next_desc = "";
288 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
289 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
290 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
291 i,
292 (unsigned long long)le64_to_cpu(u0->a),
293 (unsigned long long)le64_to_cpu(u0->b),
294 (unsigned long long)buffer_info->dma,
295 buffer_info->length, buffer_info->next_to_watch,
296 (unsigned long long)buffer_info->time_stamp,
297 buffer_info->skb, next_desc);
84f4ee90 298
f0c5dadf 299 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 300 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 301 16, 1, buffer_info->skb->data,
302 buffer_info->skb->len, true);
84f4ee90
TI		 303 }
304
af667a29 305 /* Print Rx Ring Summary */
84f4ee90 306rx_ring_summary:
af667a29 307 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 308 pr_info("Queue [NTU] [NTC]\n");
309 pr_info(" %5d %5X %5X\n",
310 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 311
af667a29 312 /* Print Rx Ring */
84f4ee90 313 if (!netif_msg_rx_status(adapter))
fe1e980f 314 return;
84f4ee90 315
af667a29 316 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 317 switch (adapter->rx_ps_pages) {
318 case 1:
319 case 2:
320 case 3:
321 /* [Extended] Packet Split Receive Descriptor Format
322 *
323 * +-----------------------------------------------------+
324 * 0 | Buffer Address 0 [63:0] |
325 * +-----------------------------------------------------+
326 * 8 | Buffer Address 1 [63:0] |
327 * +-----------------------------------------------------+
328 * 16 | Buffer Address 2 [63:0] |
329 * +-----------------------------------------------------+
330 * 24 | Buffer Address 3 [63:0] |
331 * +-----------------------------------------------------+
332 */
ef456f85 333 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 334 /* [Extended] Receive Descriptor (Write-Back) Format
335 *
336 * 63 48 47 32 31 13 12 8 7 4 3 0
337 * +------------------------------------------------------+
338 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
339 * | Checksum | Ident | | Queue | | Type |
340 * +------------------------------------------------------+
341 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
342 * +------------------------------------------------------+
343 * 63 48 47 32 31 20 19 0
344 */
ef456f85 345 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 346 for (i = 0; i < rx_ring->count; i++) {
ef456f85 347 const char *next_desc;
84f4ee90
TI		 348 buffer_info = &rx_ring->buffer_info[i];
349 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
350 u1 = (struct my_u1 *)rx_desc_ps;
351 staterr =
af667a29 352 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 353
354 if (i == rx_ring->next_to_use)
355 next_desc = " NTU";
356 else if (i == rx_ring->next_to_clean)
357 next_desc = " NTC";
358 else
359 next_desc = "";
360
84f4ee90
TI		 361 if (staterr & E1000_RXD_STAT_DD) {
362 /* Descriptor Done */
ef456f85
JK		 363 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
364 "RWB", i,
365 (unsigned long long)le64_to_cpu(u1->a),
366 (unsigned long long)le64_to_cpu(u1->b),
367 (unsigned long long)le64_to_cpu(u1->c),
368 (unsigned long long)le64_to_cpu(u1->d),
369 buffer_info->skb, next_desc);
84f4ee90 370 } else {
ef456f85
JK		 371 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
372 "R ", i,
373 (unsigned long long)le64_to_cpu(u1->a),
374 (unsigned long long)le64_to_cpu(u1->b),
375 (unsigned long long)le64_to_cpu(u1->c),
376 (unsigned long long)le64_to_cpu(u1->d),
377 (unsigned long long)buffer_info->dma,
378 buffer_info->skb, next_desc);
84f4ee90
TI		 379
380 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 381 e1000e_dump_ps_pages(adapter,
382 buffer_info);
84f4ee90 383 }
84f4ee90
TI		 384 }
385 break;
386 default:
387 case 0:
5f450212 388 /* Extended Receive Descriptor (Read) Format
84f4ee90 389 *
5f450212
BA		 390 * +-----------------------------------------------------+
391 * 0 | Buffer Address [63:0] |
392 * +-----------------------------------------------------+
393 * 8 | Reserved |
394 * +-----------------------------------------------------+
84f4ee90 395 */
ef456f85 396 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 397 /* Extended Receive Descriptor (Write-Back) Format
398 *
399 * 63 48 47 32 31 24 23 4 3 0
400 * +------------------------------------------------------+
401 * | RSS Hash | | | |
402 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
403 * | Packet | IP | | | Type |
404 * | Checksum | Ident | | | |
405 * +------------------------------------------------------+
406 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
407 * +------------------------------------------------------+
408 * 63 48 47 32 31 20 19 0
409 */
ef456f85 410 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 411
412 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 413 const char *next_desc;
414
84f4ee90 415 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 416 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
417 u1 = (struct my_u1 *)rx_desc;
418 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 419
420 if (i == rx_ring->next_to_use)
421 next_desc = " NTU";
422 else if (i == rx_ring->next_to_clean)
423 next_desc = " NTC";
424 else
425 next_desc = "";
426
5f450212
BA		 427 if (staterr & E1000_RXD_STAT_DD) {
428 /* Descriptor Done */
ef456f85
JK		 429 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
430 "RWB", i,
431 (unsigned long long)le64_to_cpu(u1->a),
432 (unsigned long long)le64_to_cpu(u1->b),
433 buffer_info->skb, next_desc);
5f450212 434 } else {
ef456f85
JK		 435 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
436 "R ", i,
437 (unsigned long long)le64_to_cpu(u1->a),
438 (unsigned long long)le64_to_cpu(u1->b),
439 (unsigned long long)buffer_info->dma,
440 buffer_info->skb, next_desc);
5f450212 441
f0c5dadf
ET		 442 if (netif_msg_pktdata(adapter) &&
443 buffer_info->skb)
5f450212
BA		 444 print_hex_dump(KERN_INFO, "",
445 DUMP_PREFIX_ADDRESS, 16,
446 1,
f0c5dadf 447 buffer_info->skb->data,
5f450212
BA		 448 adapter->rx_buffer_len,
449 true);
450 }
84f4ee90
TI		 451 }
452 }
84f4ee90
TI		 453}
454
bc7f75fa
AK		 455/**
456 * e1000_desc_unused - calculate if we have unused descriptors
457 **/
458static int e1000_desc_unused(struct e1000_ring *ring)
459{
460 if (ring->next_to_clean > ring->next_to_use)
461 return ring->next_to_clean - ring->next_to_use - 1;
462
463 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
464}
465
b67e1913
BA		 466/**
467 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
468 * @adapter: board private structure
469 * @hwtstamps: time stamp structure to update
470 * @systim: unsigned 64bit system time value.
471 *
472 * Convert the system time value stored in the RX/TXSTMP registers into a
473 * hwtstamp which can be used by the upper level time stamping functions.
474 *
475 * The 'systim_lock' spinlock is used to protect the consistency of the
476 * system time value. This is needed because reading the 64 bit time
477 * value involves reading two 32 bit registers. The first read latches the
478 * value.
479 **/
480static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
481 struct skb_shared_hwtstamps *hwtstamps,
482 u64 systim)
483{
484 u64 ns;
485 unsigned long flags;
486
487 spin_lock_irqsave(&adapter->systim_lock, flags);
488 ns = timecounter_cyc2time(&adapter->tc, systim);
489 spin_unlock_irqrestore(&adapter->systim_lock, flags);
490
491 memset(hwtstamps, 0, sizeof(*hwtstamps));
492 hwtstamps->hwtstamp = ns_to_ktime(ns);
493}
494
495/**
496 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
497 * @adapter: board private structure
498 * @status: descriptor extended error and status field
499 * @skb: particular skb to include time stamp
500 *
501 * If the time stamp is valid, convert it into the timecounter ns value
502 * and store that result into the shhwtstamps structure which is passed
503 * up the network stack.
504 **/
505static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
506 struct sk_buff *skb)
507{
508 struct e1000_hw *hw = &adapter->hw;
509 u64 rxstmp;
510
511 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
512 !(status & E1000_RXDEXT_STATERR_TST) ||
513 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
514 return;
515
516 /* The Rx time stamp registers contain the time stamp. No other
517 * received packet will be time stamped until the Rx time stamp
518 * registers are read. Because only one packet can be time stamped
519 * at a time, the register values must belong to this packet and
520 * therefore none of the other additional attributes need to be
521 * compared.
522 */
523 rxstmp = (u64)er32(RXSTMPL);
524 rxstmp |= (u64)er32(RXSTMPH) << 32;
525 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
526
527 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
528}
529
bc7f75fa 530/**
ad68076e 531 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 532 * @adapter: board private structure
b67e1913 533 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 534 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
535 * @skb: pointer to sk_buff to be indicated to stack
536 **/
537static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 538 struct net_device *netdev, struct sk_buff *skb,
b67e1913 539 u32 staterr, __le16 vlan)
bc7f75fa 540{
86d70e53 541 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 542
543 e1000e_rx_hwtstamp(adapter, staterr, skb);
544
bc7f75fa
AK		 545 skb->protocol = eth_type_trans(skb, netdev);
546
b67e1913 547 if (staterr & E1000_RXD_STAT_VP)
86a9bad3 548 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
86d70e53
JK		 549
550 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 551}
552
553/**
af667a29 554 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 555 * @adapter: board private structure
556 * @status_err: receive descriptor status and error fields
557 * @csum: receive descriptor csum field
558 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 559 **/
560static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 561 struct sk_buff *skb)
bc7f75fa
AK		 562{
563 u16 status = (u16)status_err;
564 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 565
566 skb_checksum_none_assert(skb);
bc7f75fa 567
afd12939
BA		 568 /* Rx checksum disabled */
569 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
570 return;
571
bc7f75fa
AK		 572 /* Ignore Checksum bit is set */
573 if (status & E1000_RXD_STAT_IXSM)
574 return;
afd12939 575
2e1706f2
BA		 576 /* TCP/UDP checksum error bit or IP checksum error bit is set */
577 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 578 /* let the stack verify checksum errors */
579 adapter->hw_csum_err++;
580 return;
581 }
582
583 /* TCP/UDP Checksum has not been calculated */
584 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
585 return;
586
587 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 588 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 589 adapter->hw_csum_good++;
590}
591
55aa6985 592static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 593{
55aa6985 594 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 595 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 596 s32 ret_val = __ew32_prepare(hw);
597
598 writel(i, rx_ring->tail);
c6e7f51e 599
bdc125f7 600 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 601 u32 rctl = er32(RCTL);
602 ew32(RCTL, rctl & ~E1000_RCTL_EN);
603 e_err("ME firmware caused invalid RDT - resetting\n");
604 schedule_work(&adapter->reset_task);
605 }
606}
607
55aa6985 608static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 609{
55aa6985 610 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 611 struct e1000_hw *hw = &adapter->hw;
bdc125f7 612 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 613
bdc125f7
BA		 614 writel(i, tx_ring->tail);
615
616 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 617 u32 tctl = er32(TCTL);
618 ew32(TCTL, tctl & ~E1000_TCTL_EN);
619 e_err("ME firmware caused invalid TDT - resetting\n");
620 schedule_work(&adapter->reset_task);
621 }
622}
623
bc7f75fa 624/**
5f450212 625 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 626 * @rx_ring: Rx descriptor ring
bc7f75fa 627 **/
55aa6985 628static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 629 int cleaned_count, gfp_t gfp)
bc7f75fa 630{
55aa6985 631 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 632 struct net_device *netdev = adapter->netdev;
633 struct pci_dev *pdev = adapter->pdev;
5f450212 634 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 635 struct e1000_buffer *buffer_info;
636 struct sk_buff *skb;
637 unsigned int i;
89d71a66 638 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 639
640 i = rx_ring->next_to_use;
641 buffer_info = &rx_ring->buffer_info[i];
642
643 while (cleaned_count--) {
644 skb = buffer_info->skb;
645 if (skb) {
646 skb_trim(skb, 0);
647 goto map_skb;
648 }
649
c2fed996 650 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 651 if (!skb) {
652 /* Better luck next round */
653 adapter->alloc_rx_buff_failed++;
654 break;
655 }
656
bc7f75fa
AK		 657 buffer_info->skb = skb;
658map_skb:
0be3f55f 659 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 660 adapter->rx_buffer_len,
0be3f55f
NN		 661 DMA_FROM_DEVICE);
662 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 663 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 664 adapter->rx_dma_failed++;
665 break;
666 }
667
5f450212
BA		 668 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
669 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 670
50849d79 671 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 672 /* Force memory writes to complete before letting h/w
50849d79
TH		 673 * know there are new descriptors to fetch. (Only
674 * applicable for weak-ordered memory model archs,
675 * such as IA-64).
676 */
677 wmb();
c6e7f51e 678 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 679 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 680 else
c5083cf6 681 writel(i, rx_ring->tail);
50849d79 682 }
bc7f75fa
AK		 683 i++;
684 if (i == rx_ring->count)
685 i = 0;
686 buffer_info = &rx_ring->buffer_info[i];
687 }
688
50849d79 689 rx_ring->next_to_use = i;
bc7f75fa
AK		 690}
691
692/**
693 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 694 * @rx_ring: Rx descriptor ring
bc7f75fa 695 **/
55aa6985 696static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 697 int cleaned_count, gfp_t gfp)
bc7f75fa 698{
55aa6985 699 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 700 struct net_device *netdev = adapter->netdev;
701 struct pci_dev *pdev = adapter->pdev;
702 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 703 struct e1000_buffer *buffer_info;
704 struct e1000_ps_page *ps_page;
705 struct sk_buff *skb;
706 unsigned int i, j;
707
708 i = rx_ring->next_to_use;
709 buffer_info = &rx_ring->buffer_info[i];
710
711 while (cleaned_count--) {
712 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
713
714 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 715 ps_page = &buffer_info->ps_pages[j];
716 if (j >= adapter->rx_ps_pages) {
717 /* all unused desc entries get hw null ptr */
af667a29
BA		 718 rx_desc->read.buffer_addr[j + 1] =
719 ~cpu_to_le64(0);
47f44e40
AK		 720 continue;
721 }
722 if (!ps_page->page) {
c2fed996 723 ps_page->page = alloc_page(gfp);
bc7f75fa 724 if (!ps_page->page) {
47f44e40
AK		 725 adapter->alloc_rx_buff_failed++;
726 goto no_buffers;
727 }
0be3f55f
NN		 728 ps_page->dma = dma_map_page(&pdev->dev,
729 ps_page->page,
730 0, PAGE_SIZE,
731 DMA_FROM_DEVICE);
732 if (dma_mapping_error(&pdev->dev,
733 ps_page->dma)) {
47f44e40 734 dev_err(&adapter->pdev->dev,
af667a29 735 "Rx DMA page map failed\n");
47f44e40
AK		 736 adapter->rx_dma_failed++;
737 goto no_buffers;
bc7f75fa 738 }
bc7f75fa 739 }
e921eb1a 740 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 741 * didn't change because each write-back
742 * erases this info.
743 */
af667a29
BA		 744 rx_desc->read.buffer_addr[j + 1] =
745 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 746 }
747
e5fe2541 748 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
c2fed996 749 gfp);
bc7f75fa
AK		 750
751 if (!skb) {
752 adapter->alloc_rx_buff_failed++;
753 break;
754 }
755
bc7f75fa 756 buffer_info->skb = skb;
0be3f55f 757 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 758 adapter->rx_ps_bsize0,
0be3f55f
NN		 759 DMA_FROM_DEVICE);
760 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 761 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 762 adapter->rx_dma_failed++;
763 /* cleanup skb */
764 dev_kfree_skb_any(skb);
765 buffer_info->skb = NULL;
766 break;
767 }
768
769 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
770
50849d79 771 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 772 /* Force memory writes to complete before letting h/w
50849d79
TH		 773 * know there are new descriptors to fetch. (Only
774 * applicable for weak-ordered memory model archs,
775 * such as IA-64).
776 */
777 wmb();
c6e7f51e 778 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 779 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 780 else
c5083cf6 781 writel(i << 1, rx_ring->tail);
50849d79
TH		 782 }
783
bc7f75fa
AK		 784 i++;
785 if (i == rx_ring->count)
786 i = 0;
787 buffer_info = &rx_ring->buffer_info[i];
788 }
789
790no_buffers:
50849d79 791 rx_ring->next_to_use = i;
bc7f75fa
AK		 792}
793
97ac8cae
BA		 794/**
795 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 796 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 797 * @cleaned_count: number of buffers to allocate this pass
798 **/
799
55aa6985 800static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 801 int cleaned_count, gfp_t gfp)
97ac8cae 802{
55aa6985 803 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 804 struct net_device *netdev = adapter->netdev;
805 struct pci_dev *pdev = adapter->pdev;
5f450212 806 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 807 struct e1000_buffer *buffer_info;
808 struct sk_buff *skb;
809 unsigned int i;
2a2293b9 810 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 811
812 i = rx_ring->next_to_use;
813 buffer_info = &rx_ring->buffer_info[i];
814
815 while (cleaned_count--) {
816 skb = buffer_info->skb;
817 if (skb) {
818 skb_trim(skb, 0);
819 goto check_page;
820 }
821
c2fed996 822 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 823 if (unlikely(!skb)) {
824 /* Better luck next round */
825 adapter->alloc_rx_buff_failed++;
826 break;
827 }
828
97ac8cae
BA		 829 buffer_info->skb = skb;
830check_page:
831 /* allocate a new page if necessary */
832 if (!buffer_info->page) {
c2fed996 833 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 834 if (unlikely(!buffer_info->page)) {
835 adapter->alloc_rx_buff_failed++;
836 break;
837 }
838 }
839
37287fae 840 if (!buffer_info->dma) {
0be3f55f 841 buffer_info->dma = dma_map_page(&pdev->dev,
f0ff4398
BA		 842 buffer_info->page, 0,
843 PAGE_SIZE,
0be3f55f 844 DMA_FROM_DEVICE);
37287fae
CP		 845 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
846 adapter->alloc_rx_buff_failed++;
847 break;
848 }
849 }
97ac8cae 850
5f450212
BA		 851 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
852 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 853
854 if (unlikely(++i == rx_ring->count))
855 i = 0;
856 buffer_info = &rx_ring->buffer_info[i];
857 }
858
859 if (likely(rx_ring->next_to_use != i)) {
860 rx_ring->next_to_use = i;
861 if (unlikely(i-- == 0))
862 i = (rx_ring->count - 1);
863
864 /* Force memory writes to complete before letting h/w
865 * know there are new descriptors to fetch. (Only
866 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 867 * such as IA-64).
868 */
97ac8cae 869 wmb();
c6e7f51e 870 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 871 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 872 else
c5083cf6 873 writel(i, rx_ring->tail);
97ac8cae
BA		 874 }
875}
876
70495a50
BA		 877static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
878 struct sk_buff *skb)
879{
880 if (netdev->features & NETIF_F_RXHASH)
e25909bc 881 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
70495a50
BA		 882}
883
bc7f75fa 884/**
55aa6985
BA		 885 * e1000_clean_rx_irq - Send received data up the network stack
886 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 887 *
888 * the return value indicates whether actual cleaning was done, there
889 * is no guarantee that everything was cleaned
890 **/
55aa6985
BA		 891static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
892 int work_to_do)
bc7f75fa 893{
55aa6985 894 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 895 struct net_device *netdev = adapter->netdev;
896 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 897 struct e1000_hw *hw = &adapter->hw;
5f450212 898 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 899 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 900 u32 length, staterr;
bc7f75fa
AK		 901 unsigned int i;
902 int cleaned_count = 0;
3db1cd5c 903 bool cleaned = false;
bc7f75fa
AK		 904 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
905
906 i = rx_ring->next_to_clean;
5f450212
BA		 907 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
908 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 909 buffer_info = &rx_ring->buffer_info[i];
910
5f450212 911 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 912 struct sk_buff *skb;
bc7f75fa
AK		 913
914 if (*work_done >= work_to_do)
915 break;
916 (*work_done)++;
2d0bb1c1 917 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 918
bc7f75fa
AK		 919 skb = buffer_info->skb;
920 buffer_info->skb = NULL;
921
922 prefetch(skb->data - NET_IP_ALIGN);
923
924 i++;
925 if (i == rx_ring->count)
926 i = 0;
5f450212 927 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 928 prefetch(next_rxd);
929
930 next_buffer = &rx_ring->buffer_info[i];
931
3db1cd5c 932 cleaned = true;
bc7f75fa 933 cleaned_count++;
e5fe2541
BA		 934 dma_unmap_single(&pdev->dev, buffer_info->dma,
935 adapter->rx_buffer_len, DMA_FROM_DEVICE);
bc7f75fa
AK		 936 buffer_info->dma = 0;
937
5f450212 938 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 939
e921eb1a 940 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 941 * packet, if that's the case we need to toss it. In fact, we
942 * need to toss every packet with the EOP bit clear and the
943 * next frame that _does_ have the EOP bit set, as it is by
944 * definition only a frame fragment
945 */
5f450212 946 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 947 adapter->flags2 |= FLAG2_IS_DISCARDING;
948
949 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 950 /* All receives must fit into a single buffer */
3bb99fe2 951 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 952 /* recycle */
953 buffer_info->skb = skb;
5f450212 954 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 955 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 956 goto next_desc;
957 }
958
cf955e6c
BG		 959 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
960 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 961 /* recycle */
962 buffer_info->skb = skb;
963 goto next_desc;
964 }
965
eb7c3adb 966 /* adjust length to remove Ethernet CRC */
0184039a
BG		 967 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
968 /* If configured to store CRC, don't subtract FCS,
969 * but keep the FCS bytes out of the total_rx_bytes
970 * counter
971 */
972 if (netdev->features & NETIF_F_RXFCS)
973 total_rx_bytes -= 4;
974 else
975 length -= 4;
976 }
eb7c3adb 977
bc7f75fa
AK		 978 total_rx_bytes += length;
979 total_rx_packets++;
980
e921eb1a 981 /* code added for copybreak, this should improve
bc7f75fa 982 * performance for small packets with large amounts
ad68076e
BA		 983 * of reassembly being done in the stack
984 */
bc7f75fa
AK		 985 if (length < copybreak) {
986 struct sk_buff *new_skb =
89d71a66 987 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 988 if (new_skb) {
808ff676
BA		 989 skb_copy_to_linear_data_offset(new_skb,
990 -NET_IP_ALIGN,
991 (skb->data -
992 NET_IP_ALIGN),
993 (length +
994 NET_IP_ALIGN));
bc7f75fa
AK		 995 /* save the skb in buffer_info as good */
996 buffer_info->skb = skb;
997 skb = new_skb;
998 }
999 /* else just continue with the old one */
1000 }
1001 /* end copybreak code */
1002 skb_put(skb, length);
1003
1004 /* Receive Checksum Offload */
2e1706f2 1005 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1006
70495a50
BA		 1007 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1008
5f450212
BA		 1009 e1000_receive_skb(adapter, netdev, skb, staterr,
1010 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1011
1012next_desc:
5f450212 1013 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1014
1015 /* return some buffers to hardware, one at a time is too slow */
1016 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1017 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1018 GFP_ATOMIC);
bc7f75fa
AK		 1019 cleaned_count = 0;
1020 }
1021
1022 /* use prefetched values */
1023 rx_desc = next_rxd;
1024 buffer_info = next_buffer;
5f450212
BA		 1025
1026 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1027 }
1028 rx_ring->next_to_clean = i;
1029
1030 cleaned_count = e1000_desc_unused(rx_ring);
1031 if (cleaned_count)
55aa6985 1032 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1033
bc7f75fa 1034 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1035 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1036 return cleaned;
1037}
1038
55aa6985
BA		 1039static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1040 struct e1000_buffer *buffer_info)
bc7f75fa 1041{
55aa6985
BA		 1042 struct e1000_adapter *adapter = tx_ring->adapter;
1043
03b1320d
AD		 1044 if (buffer_info->dma) {
1045 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1046 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1047 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1048 else
0be3f55f
NN		 1049 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1050 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1051 buffer_info->dma = 0;
1052 }
bc7f75fa
AK		 1053 if (buffer_info->skb) {
1054 dev_kfree_skb_any(buffer_info->skb);
1055 buffer_info->skb = NULL;
1056 }
1b7719c4 1057 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1058}
1059
41cec6f1 1060static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1061{
41cec6f1 1062 struct e1000_adapter *adapter = container_of(work,
f0ff4398
BA		 1063 struct e1000_adapter,
1064 print_hang_task);
09357b00 1065 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1066 struct e1000_ring *tx_ring = adapter->tx_ring;
1067 unsigned int i = tx_ring->next_to_clean;
1068 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1069 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1070 struct e1000_hw *hw = &adapter->hw;
1071 u16 phy_status, phy_1000t_status, phy_ext_status;
1072 u16 pci_status;
1073
615b32af
JB		 1074 if (test_bit(__E1000_DOWN, &adapter->state))
1075 return;
1076
e5fe2541 1077 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1078 /* May be block on write-back, flush and detect again
09357b00
JK		 1079 * flush pending descriptor writebacks to memory
1080 */
1081 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1082 /* execute the writes immediately */
1083 e1e_flush();
e921eb1a 1084 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1085 * the write is successful
1086 */
1087 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1088 /* execute the writes immediately */
1089 e1e_flush();
09357b00
JK		 1090 adapter->tx_hang_recheck = true;
1091 return;
1092 }
1093 /* Real hang detected */
1094 adapter->tx_hang_recheck = false;
1095 netif_stop_queue(netdev);
1096
c2ade1a4
BA		 1097 e1e_rphy(hw, MII_BMSR, &phy_status);
1098 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1099 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
bc7f75fa 1100
41cec6f1
BA		 1101 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1102
1103 /* detected Hardware unit hang */
1104 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1105 " TDH <%x>\n"
1106 " TDT <%x>\n"
1107 " next_to_use <%x>\n"
1108 " next_to_clean <%x>\n"
1109 "buffer_info[next_to_clean]:\n"
1110 " time_stamp <%lx>\n"
1111 " next_to_watch <%x>\n"
1112 " jiffies <%lx>\n"
41cec6f1
BA		 1113 " next_to_watch.status <%x>\n"
1114 "MAC Status <%x>\n"
1115 "PHY Status <%x>\n"
1116 "PHY 1000BASE-T Status <%x>\n"
1117 "PHY Extended Status <%x>\n"
1118 "PCI Status <%x>\n",
e5fe2541
BA		 1119 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1120 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1121 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1122 phy_status, phy_1000t_status, phy_ext_status, pci_status);
7c0427ee
BA		 1123
1124 /* Suggest workaround for known h/w issue */
1125 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1126 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1127}
1128
b67e1913
BA		 1129/**
1130 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1131 * @work: pointer to work struct
1132 *
1133 * This work function polls the TSYNCTXCTL valid bit to determine when a
1134 * timestamp has been taken for the current stored skb. The timestamp must
1135 * be for this skb because only one such packet is allowed in the queue.
1136 */
1137static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1138{
1139 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1140 tx_hwtstamp_work);
1141 struct e1000_hw *hw = &adapter->hw;
1142
1143 if (!adapter->tx_hwtstamp_skb)
1144 return;
1145
1146 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1147 struct skb_shared_hwtstamps shhwtstamps;
1148 u64 txstmp;
1149
1150 txstmp = er32(TXSTMPL);
1151 txstmp |= (u64)er32(TXSTMPH) << 32;
1152
1153 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1154
1155 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1156 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1157 adapter->tx_hwtstamp_skb = NULL;
1158 } else {
1159 /* reschedule to check later */
1160 schedule_work(&adapter->tx_hwtstamp_work);
1161 }
1162}
1163
bc7f75fa
AK		 1164/**
1165 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1166 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1167 *
1168 * the return value indicates whether actual cleaning was done, there
1169 * is no guarantee that everything was cleaned
1170 **/
55aa6985 1171static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1172{
55aa6985 1173 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1174 struct net_device *netdev = adapter->netdev;
1175 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1176 struct e1000_tx_desc *tx_desc, *eop_desc;
1177 struct e1000_buffer *buffer_info;
1178 unsigned int i, eop;
1179 unsigned int count = 0;
bc7f75fa 1180 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1181 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1182
1183 i = tx_ring->next_to_clean;
1184 eop = tx_ring->buffer_info[i].next_to_watch;
1185 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1186
12d04a3c
AD		 1187 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1188 (count < tx_ring->count)) {
a86043c2 1189 bool cleaned = false;
e80bd1d1 1190 rmb(); /* read buffer_info after eop_desc */
a86043c2 1191 for (; !cleaned; count++) {
bc7f75fa
AK		 1192 tx_desc = E1000_TX_DESC(*tx_ring, i);
1193 buffer_info = &tx_ring->buffer_info[i];
1194 cleaned = (i == eop);
1195
1196 if (cleaned) {
9ed318d5
TH		 1197 total_tx_packets += buffer_info->segs;
1198 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1199 if (buffer_info->skb) {
1200 bytes_compl += buffer_info->skb->len;
1201 pkts_compl++;
1202 }
bc7f75fa
AK		 1203 }
1204
55aa6985 1205 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1206 tx_desc->upper.data = 0;
1207
1208 i++;
1209 if (i == tx_ring->count)
1210 i = 0;
1211 }
1212
dac87619
TL		 1213 if (i == tx_ring->next_to_use)
1214 break;
bc7f75fa
AK		 1215 eop = tx_ring->buffer_info[i].next_to_watch;
1216 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1217 }
1218
1219 tx_ring->next_to_clean = i;
1220
3f0cfa3b
TH		 1221 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1222
bc7f75fa 1223#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1224 if (count && netif_carrier_ok(netdev) &&
1225 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1226 /* Make sure that anybody stopping the queue after this
1227 * sees the new next_to_clean.
1228 */
1229 smp_mb();
1230
1231 if (netif_queue_stopped(netdev) &&
1232 !(test_bit(__E1000_DOWN, &adapter->state))) {
1233 netif_wake_queue(netdev);
1234 ++adapter->restart_queue;
1235 }
1236 }
1237
1238 if (adapter->detect_tx_hung) {
e921eb1a 1239 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1240 * check with the clearing of time_stamp and movement of i
1241 */
3db1cd5c 1242 adapter->detect_tx_hung = false;
12d04a3c
AD		 1243 if (tx_ring->buffer_info[i].time_stamp &&
1244 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1245 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1246 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1247 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1248 else
1249 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1250 }
1251 adapter->total_tx_bytes += total_tx_bytes;
1252 adapter->total_tx_packets += total_tx_packets;
807540ba 1253 return count < tx_ring->count;
bc7f75fa
AK		 1254}
1255
bc7f75fa
AK		 1256/**
1257 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1258 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1259 *
1260 * the return value indicates whether actual cleaning was done, there
1261 * is no guarantee that everything was cleaned
1262 **/
55aa6985
BA		 1263static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1264 int work_to_do)
bc7f75fa 1265{
55aa6985 1266 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1267 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1268 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1269 struct net_device *netdev = adapter->netdev;
1270 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1271 struct e1000_buffer *buffer_info, *next_buffer;
1272 struct e1000_ps_page *ps_page;
1273 struct sk_buff *skb;
1274 unsigned int i, j;
1275 u32 length, staterr;
1276 int cleaned_count = 0;
3db1cd5c 1277 bool cleaned = false;
bc7f75fa
AK		 1278 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1279
1280 i = rx_ring->next_to_clean;
1281 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1282 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1283 buffer_info = &rx_ring->buffer_info[i];
1284
1285 while (staterr & E1000_RXD_STAT_DD) {
1286 if (*work_done >= work_to_do)
1287 break;
1288 (*work_done)++;
1289 skb = buffer_info->skb;
2d0bb1c1 1290 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1291
1292 /* in the packet split case this is header only */
1293 prefetch(skb->data - NET_IP_ALIGN);
1294
1295 i++;
1296 if (i == rx_ring->count)
1297 i = 0;
1298 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1299 prefetch(next_rxd);
1300
1301 next_buffer = &rx_ring->buffer_info[i];
1302
3db1cd5c 1303 cleaned = true;
bc7f75fa 1304 cleaned_count++;
0be3f55f 1305 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1306 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1307 buffer_info->dma = 0;
1308
af667a29 1309 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1310 if (!(staterr & E1000_RXD_STAT_EOP))
1311 adapter->flags2 |= FLAG2_IS_DISCARDING;
1312
1313 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1314 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1315 dev_kfree_skb_irq(skb);
b94b5028
JB		 1316 if (staterr & E1000_RXD_STAT_EOP)
1317 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1318 goto next_desc;
1319 }
1320
cf955e6c
BG		 1321 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1322 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1323 dev_kfree_skb_irq(skb);
1324 goto next_desc;
1325 }
1326
1327 length = le16_to_cpu(rx_desc->wb.middle.length0);
1328
1329 if (!length) {
ef456f85 1330 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1331 dev_kfree_skb_irq(skb);
1332 goto next_desc;
1333 }
1334
1335 /* Good Receive */
1336 skb_put(skb, length);
1337
1338 {
e921eb1a 1339 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1340 * it more efficient than reusing j
1341 */
1342 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1343
e921eb1a 1344 /* page alloc/put takes too long and effects small
0e15df49
BA		 1345 * packet throughput, so unsplit small packets and
1346 * save the alloc/put only valid in softirq (napi)
1347 * context to call kmap_*
ad68076e 1348 */
0e15df49
BA		 1349 if (l1 && (l1 <= copybreak) &&
1350 ((length + l1) <= adapter->rx_ps_bsize0)) {
1351 u8 *vaddr;
1352
1353 ps_page = &buffer_info->ps_pages[0];
1354
e921eb1a 1355 /* there is no documentation about how to call
0e15df49
BA		 1356 * kmap_atomic, so we can't hold the mapping
1357 * very long
1358 */
1359 dma_sync_single_for_cpu(&pdev->dev,
1360 ps_page->dma,
1361 PAGE_SIZE,
1362 DMA_FROM_DEVICE);
9f393834 1363 vaddr = kmap_atomic(ps_page->page);
0e15df49 1364 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1365 kunmap_atomic(vaddr);
0e15df49
BA		 1366 dma_sync_single_for_device(&pdev->dev,
1367 ps_page->dma,
1368 PAGE_SIZE,
1369 DMA_FROM_DEVICE);
1370
1371 /* remove the CRC */
0184039a
BG		 1372 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1373 if (!(netdev->features & NETIF_F_RXFCS))
1374 l1 -= 4;
1375 }
0e15df49
BA		 1376
1377 skb_put(skb, l1);
1378 goto copydone;
e80bd1d1 1379 } /* if */
bc7f75fa
AK		 1380 }
1381
1382 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1383 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1384 if (!length)
1385 break;
1386
47f44e40 1387 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1388 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1389 DMA_FROM_DEVICE);
bc7f75fa
AK		 1390 ps_page->dma = 0;
1391 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1392 ps_page->page = NULL;
1393 skb->len += length;
1394 skb->data_len += length;
98a045d7 1395 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1396 }
1397
eb7c3adb
JK		 1398 /* strip the ethernet crc, problem is we're using pages now so
1399 * this whole operation can get a little cpu intensive
1400 */
0184039a
BG		 1401 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1402 if (!(netdev->features & NETIF_F_RXFCS))
1403 pskb_trim(skb, skb->len - 4);
1404 }
eb7c3adb 1405
bc7f75fa
AK		 1406copydone:
1407 total_rx_bytes += skb->len;
1408 total_rx_packets++;
1409
2e1706f2 1410 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1411
70495a50
BA		 1412 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1413
bc7f75fa 1414 if (rx_desc->wb.upper.header_status &
17e813ec 1415 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
bc7f75fa
AK		 1416 adapter->rx_hdr_split++;
1417
b67e1913
BA		 1418 e1000_receive_skb(adapter, netdev, skb, staterr,
1419 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1420
1421next_desc:
1422 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1423 buffer_info->skb = NULL;
1424
1425 /* return some buffers to hardware, one at a time is too slow */
1426 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1427 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1428 GFP_ATOMIC);
bc7f75fa
AK		 1429 cleaned_count = 0;
1430 }
1431
1432 /* use prefetched values */
1433 rx_desc = next_rxd;
1434 buffer_info = next_buffer;
1435
1436 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1437 }
1438 rx_ring->next_to_clean = i;
1439
1440 cleaned_count = e1000_desc_unused(rx_ring);
1441 if (cleaned_count)
55aa6985 1442 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1443
bc7f75fa 1444 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1445 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1446 return cleaned;
1447}
1448
97ac8cae
BA		 1449/**
1450 * e1000_consume_page - helper function
1451 **/
1452static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
66501f56 1453 u16 length)
97ac8cae
BA		 1454{
1455 bi->page = NULL;
1456 skb->len += length;
1457 skb->data_len += length;
98a045d7 1458 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1459}
1460
1461/**
1462 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1463 * @adapter: board private structure
1464 *
1465 * the return value indicates whether actual cleaning was done, there
1466 * is no guarantee that everything was cleaned
1467 **/
55aa6985
BA		 1468static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1469 int work_to_do)
97ac8cae 1470{
55aa6985 1471 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1472 struct net_device *netdev = adapter->netdev;
1473 struct pci_dev *pdev = adapter->pdev;
5f450212 1474 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1475 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1476 u32 length, staterr;
97ac8cae
BA		 1477 unsigned int i;
1478 int cleaned_count = 0;
1479 bool cleaned = false;
362e20ca 1480 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
17e813ec 1481 struct skb_shared_info *shinfo;
97ac8cae
BA		 1482
1483 i = rx_ring->next_to_clean;
5f450212
BA		 1484 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1485 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1486 buffer_info = &rx_ring->buffer_info[i];
1487
5f450212 1488 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1489 struct sk_buff *skb;
97ac8cae
BA		 1490
1491 if (*work_done >= work_to_do)
1492 break;
1493 (*work_done)++;
2d0bb1c1 1494 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1495
97ac8cae
BA		 1496 skb = buffer_info->skb;
1497 buffer_info->skb = NULL;
1498
1499 ++i;
1500 if (i == rx_ring->count)
1501 i = 0;
5f450212 1502 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1503 prefetch(next_rxd);
1504
1505 next_buffer = &rx_ring->buffer_info[i];
1506
1507 cleaned = true;
1508 cleaned_count++;
0be3f55f
NN		 1509 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1510 DMA_FROM_DEVICE);
97ac8cae
BA		 1511 buffer_info->dma = 0;
1512
5f450212 1513 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1514
1515 /* errors is only valid for DD + EOP descriptors */
5f450212 1516 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1517 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1518 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1519 /* recycle both page and skb */
1520 buffer_info->skb = skb;
1521 /* an error means any chain goes out the window too */
1522 if (rx_ring->rx_skb_top)
1523 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1524 rx_ring->rx_skb_top = NULL;
1525 goto next_desc;
97ac8cae 1526 }
f0f1a172 1527#define rxtop (rx_ring->rx_skb_top)
5f450212 1528 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1529 /* this descriptor is only the beginning (or middle) */
1530 if (!rxtop) {
1531 /* this is the beginning of a chain */
1532 rxtop = skb;
1533 skb_fill_page_desc(rxtop, 0, buffer_info->page,
f0ff4398 1534 0, length);
97ac8cae
BA		 1535 } else {
1536 /* this is the middle of a chain */
17e813ec
BA		 1537 shinfo = skb_shinfo(rxtop);
1538 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1539 buffer_info->page, 0,
1540 length);
97ac8cae
BA		 1541 /* re-use the skb, only consumed the page */
1542 buffer_info->skb = skb;
1543 }
1544 e1000_consume_page(buffer_info, rxtop, length);
1545 goto next_desc;
1546 } else {
1547 if (rxtop) {
1548 /* end of the chain */
17e813ec
BA		 1549 shinfo = skb_shinfo(rxtop);
1550 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1551 buffer_info->page, 0,
1552 length);
97ac8cae 1553 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1554 * page
1555 */
97ac8cae
BA		 1556 buffer_info->skb = skb;
1557 skb = rxtop;
1558 rxtop = NULL;
1559 e1000_consume_page(buffer_info, skb, length);
1560 } else {
1561 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1562 * copybreak to save the put_page/alloc_page
1563 */
97ac8cae
BA		 1564 if (length <= copybreak &&
1565 skb_tailroom(skb) >= length) {
1566 u8 *vaddr;
4679026d 1567 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1568 memcpy(skb_tail_pointer(skb), vaddr,
1569 length);
4679026d 1570 kunmap_atomic(vaddr);
97ac8cae 1571 /* re-use the page, so don't erase
e921eb1a
BA		 1572 * buffer_info->page
1573 */
97ac8cae
BA		 1574 skb_put(skb, length);
1575 } else {
1576 skb_fill_page_desc(skb, 0,
f0ff4398
BA		 1577 buffer_info->page, 0,
1578 length);
97ac8cae 1579 e1000_consume_page(buffer_info, skb,
f0ff4398 1580 length);
97ac8cae
BA		 1581 }
1582 }
1583 }
1584
2e1706f2
BA		 1585 /* Receive Checksum Offload */
1586 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1587
70495a50
BA		 1588 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1589
97ac8cae
BA		 1590 /* probably a little skewed due to removing CRC */
1591 total_rx_bytes += skb->len;
1592 total_rx_packets++;
1593
1594 /* eth type trans needs skb->data to point to something */
1595 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1596 e_err("pskb_may_pull failed.\n");
ef5ab89c 1597 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1598 goto next_desc;
1599 }
1600
5f450212
BA		 1601 e1000_receive_skb(adapter, netdev, skb, staterr,
1602 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1603
1604next_desc:
5f450212 1605 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1606
1607 /* return some buffers to hardware, one at a time is too slow */
1608 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1609 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1610 GFP_ATOMIC);
97ac8cae
BA		 1611 cleaned_count = 0;
1612 }
1613
1614 /* use prefetched values */
1615 rx_desc = next_rxd;
1616 buffer_info = next_buffer;
5f450212
BA		 1617
1618 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1619 }
1620 rx_ring->next_to_clean = i;
1621
1622 cleaned_count = e1000_desc_unused(rx_ring);
1623 if (cleaned_count)
55aa6985 1624 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1625
1626 adapter->total_rx_bytes += total_rx_bytes;
1627 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1628 return cleaned;
1629}
1630
bc7f75fa
AK		 1631/**
1632 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1633 * @rx_ring: Rx descriptor ring
bc7f75fa 1634 **/
55aa6985 1635static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1636{
55aa6985 1637 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1638 struct e1000_buffer *buffer_info;
1639 struct e1000_ps_page *ps_page;
1640 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1641 unsigned int i, j;
1642
1643 /* Free all the Rx ring sk_buffs */
1644 for (i = 0; i < rx_ring->count; i++) {
1645 buffer_info = &rx_ring->buffer_info[i];
1646 if (buffer_info->dma) {
1647 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1648 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1649 adapter->rx_buffer_len,
0be3f55f 1650 DMA_FROM_DEVICE);
97ac8cae 1651 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1652 dma_unmap_page(&pdev->dev, buffer_info->dma,
f0ff4398 1653 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa 1654 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1655 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1656 adapter->rx_ps_bsize0,
0be3f55f 1657 DMA_FROM_DEVICE);
bc7f75fa
AK		 1658 buffer_info->dma = 0;
1659 }
1660
97ac8cae
BA		 1661 if (buffer_info->page) {
1662 put_page(buffer_info->page);
1663 buffer_info->page = NULL;
1664 }
1665
bc7f75fa
AK		 1666 if (buffer_info->skb) {
1667 dev_kfree_skb(buffer_info->skb);
1668 buffer_info->skb = NULL;
1669 }
1670
1671 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1672 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1673 if (!ps_page->page)
1674 break;
0be3f55f
NN		 1675 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1676 DMA_FROM_DEVICE);
bc7f75fa
AK		 1677 ps_page->dma = 0;
1678 put_page(ps_page->page);
1679 ps_page->page = NULL;
1680 }
1681 }
1682
1683 /* there also may be some cached data from a chained receive */
1684 if (rx_ring->rx_skb_top) {
1685 dev_kfree_skb(rx_ring->rx_skb_top);
1686 rx_ring->rx_skb_top = NULL;
1687 }
1688
bc7f75fa
AK		 1689 /* Zero out the descriptor ring */
1690 memset(rx_ring->desc, 0, rx_ring->size);
1691
1692 rx_ring->next_to_clean = 0;
1693 rx_ring->next_to_use = 0;
b94b5028 1694 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1695
c5083cf6 1696 writel(0, rx_ring->head);
b485dbae 1697 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
bdc125f7
BA		 1698 e1000e_update_rdt_wa(rx_ring, 0);
1699 else
1700 writel(0, rx_ring->tail);
bc7f75fa
AK		 1701}
1702
a8f88ff5
JB		 1703static void e1000e_downshift_workaround(struct work_struct *work)
1704{
1705 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 1706 struct e1000_adapter,
1707 downshift_task);
a8f88ff5 1708
615b32af
JB		 1709 if (test_bit(__E1000_DOWN, &adapter->state))
1710 return;
1711
a8f88ff5
JB		 1712 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1713}
1714
bc7f75fa
AK		 1715/**
1716 * e1000_intr_msi - Interrupt Handler
1717 * @irq: interrupt number
1718 * @data: pointer to a network interface device structure
1719 **/
8bb62869 1720static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
bc7f75fa
AK		 1721{
1722 struct net_device *netdev = data;
1723 struct e1000_adapter *adapter = netdev_priv(netdev);
1724 struct e1000_hw *hw = &adapter->hw;
1725 u32 icr = er32(ICR);
1726
e921eb1a 1727 /* read ICR disables interrupts using IAM */
573cca8c 1728 if (icr & E1000_ICR_LSC) {
f92518dd 1729 hw->mac.get_link_status = true;
e921eb1a 1730 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1731 * disconnect (LSC) before accessing any PHY registers
1732 */
bc7f75fa
AK		 1733 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1734 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1735 schedule_work(&adapter->downshift_task);
bc7f75fa 1736
e921eb1a 1737 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1738 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1739 * adapter in watchdog
1740 */
bc7f75fa
AK		 1741 if (netif_carrier_ok(netdev) &&
1742 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1743 /* disable receives */
1744 u32 rctl = er32(RCTL);
1745 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1746 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1747 }
1748 /* guard against interrupt when we're going down */
1749 if (!test_bit(__E1000_DOWN, &adapter->state))
1750 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1751 }
1752
94fb848b
BA		 1753 /* Reset on uncorrectable ECC error */
1754 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1755 u32 pbeccsts = er32(PBECCSTS);
1756
1757 adapter->corr_errors +=
1758 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1759 adapter->uncorr_errors +=
1760 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1761 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1762
1763 /* Do the reset outside of interrupt context */
1764 schedule_work(&adapter->reset_task);
1765
1766 /* return immediately since reset is imminent */
1767 return IRQ_HANDLED;
1768 }
1769
288379f0 1770 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1771 adapter->total_tx_bytes = 0;
1772 adapter->total_tx_packets = 0;
1773 adapter->total_rx_bytes = 0;
1774 adapter->total_rx_packets = 0;
288379f0 1775 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1776 }
1777
1778 return IRQ_HANDLED;
1779}
1780
1781/**
1782 * e1000_intr - Interrupt Handler
1783 * @irq: interrupt number
1784 * @data: pointer to a network interface device structure
1785 **/
8bb62869 1786static irqreturn_t e1000_intr(int __always_unused irq, void *data)
bc7f75fa
AK		 1787{
1788 struct net_device *netdev = data;
1789 struct e1000_adapter *adapter = netdev_priv(netdev);
1790 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1791 u32 rctl, icr = er32(ICR);
4662e82b 1792
a68ea775 1793 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
e80bd1d1 1794 return IRQ_NONE; /* Not our interrupt */
bc7f75fa 1795
e921eb1a 1796 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1797 * not set, then the adapter didn't send an interrupt
1798 */
bc7f75fa
AK		 1799 if (!(icr & E1000_ICR_INT_ASSERTED))
1800 return IRQ_NONE;
1801
e921eb1a 1802 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1803 * interrupts are masked. No need for the
1804 * IMC write
1805 */
bc7f75fa 1806
573cca8c 1807 if (icr & E1000_ICR_LSC) {
f92518dd 1808 hw->mac.get_link_status = true;
e921eb1a 1809 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1810 * disconnect (LSC) before accessing any PHY registers
1811 */
bc7f75fa
AK		 1812 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1813 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1814 schedule_work(&adapter->downshift_task);
bc7f75fa 1815
e921eb1a 1816 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1817 * For packet buffer work-around on link down event;
1818 * disable receives here in the ISR and
1819 * reset adapter in watchdog
1820 */
1821 if (netif_carrier_ok(netdev) &&
1822 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1823 /* disable receives */
1824 rctl = er32(RCTL);
1825 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1826 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1827 }
1828 /* guard against interrupt when we're going down */
1829 if (!test_bit(__E1000_DOWN, &adapter->state))
1830 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1831 }
1832
94fb848b
BA		 1833 /* Reset on uncorrectable ECC error */
1834 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1835 u32 pbeccsts = er32(PBECCSTS);
1836
1837 adapter->corr_errors +=
1838 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1839 adapter->uncorr_errors +=
1840 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1841 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1842
1843 /* Do the reset outside of interrupt context */
1844 schedule_work(&adapter->reset_task);
1845
1846 /* return immediately since reset is imminent */
1847 return IRQ_HANDLED;
1848 }
1849
288379f0 1850 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1851 adapter->total_tx_bytes = 0;
1852 adapter->total_tx_packets = 0;
1853 adapter->total_rx_bytes = 0;
1854 adapter->total_rx_packets = 0;
288379f0 1855 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1856 }
1857
1858 return IRQ_HANDLED;
1859}
1860
8bb62869 1861static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
4662e82b
BA		 1862{
1863 struct net_device *netdev = data;
1864 struct e1000_adapter *adapter = netdev_priv(netdev);
1865 struct e1000_hw *hw = &adapter->hw;
1866 u32 icr = er32(ICR);
1867
1868 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1869 if (!test_bit(__E1000_DOWN, &adapter->state))
1870 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1871 return IRQ_NONE;
1872 }
1873
1874 if (icr & adapter->eiac_mask)
1875 ew32(ICS, (icr & adapter->eiac_mask));
1876
1877 if (icr & E1000_ICR_OTHER) {
1878 if (!(icr & E1000_ICR_LSC))
1879 goto no_link_interrupt;
f92518dd 1880 hw->mac.get_link_status = true;
4662e82b
BA		 1881 /* guard against interrupt when we're going down */
1882 if (!test_bit(__E1000_DOWN, &adapter->state))
1883 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1884 }
1885
1886no_link_interrupt:
a3c69fef
JB		 1887 if (!test_bit(__E1000_DOWN, &adapter->state))
1888 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1889
1890 return IRQ_HANDLED;
1891}
1892
8bb62869 1893static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
4662e82b
BA		 1894{
1895 struct net_device *netdev = data;
1896 struct e1000_adapter *adapter = netdev_priv(netdev);
1897 struct e1000_hw *hw = &adapter->hw;
1898 struct e1000_ring *tx_ring = adapter->tx_ring;
1899
4662e82b
BA		 1900 adapter->total_tx_bytes = 0;
1901 adapter->total_tx_packets = 0;
1902
55aa6985 1903 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1904 /* Ring was not completely cleaned, so fire another interrupt */
1905 ew32(ICS, tx_ring->ims_val);
1906
1907 return IRQ_HANDLED;
1908}
1909
8bb62869 1910static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
4662e82b
BA		 1911{
1912 struct net_device *netdev = data;
1913 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1914 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1915
1916 /* Write the ITR value calculated at the end of the
1917 * previous interrupt.
1918 */
55aa6985
BA		 1919 if (rx_ring->set_itr) {
1920 writel(1000000000 / (rx_ring->itr_val * 256),
1921 rx_ring->itr_register);
1922 rx_ring->set_itr = 0;
4662e82b
BA		 1923 }
1924
288379f0 1925 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1926 adapter->total_rx_bytes = 0;
1927 adapter->total_rx_packets = 0;
288379f0 1928 __napi_schedule(&adapter->napi);
4662e82b
BA		 1929 }
1930 return IRQ_HANDLED;
1931}
1932
1933/**
1934 * e1000_configure_msix - Configure MSI-X hardware
1935 *
1936 * e1000_configure_msix sets up the hardware to properly
1937 * generate MSI-X interrupts.
1938 **/
1939static void e1000_configure_msix(struct e1000_adapter *adapter)
1940{
1941 struct e1000_hw *hw = &adapter->hw;
1942 struct e1000_ring *rx_ring = adapter->rx_ring;
1943 struct e1000_ring *tx_ring = adapter->tx_ring;
1944 int vector = 0;
1945 u32 ctrl_ext, ivar = 0;
1946
1947 adapter->eiac_mask = 0;
1948
1949 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1950 if (hw->mac.type == e1000_82574) {
1951 u32 rfctl = er32(RFCTL);
1952 rfctl |= E1000_RFCTL_ACK_DIS;
1953 ew32(RFCTL, rfctl);
1954 }
1955
4662e82b
BA		 1956 /* Configure Rx vector */
1957 rx_ring->ims_val = E1000_IMS_RXQ0;
1958 adapter->eiac_mask |= rx_ring->ims_val;
1959 if (rx_ring->itr_val)
1960 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1961 rx_ring->itr_register);
4662e82b 1962 else
c5083cf6 1963 writel(1, rx_ring->itr_register);
4662e82b
BA		 1964 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1965
1966 /* Configure Tx vector */
1967 tx_ring->ims_val = E1000_IMS_TXQ0;
1968 vector++;
1969 if (tx_ring->itr_val)
1970 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1971 tx_ring->itr_register);
4662e82b 1972 else
c5083cf6 1973 writel(1, tx_ring->itr_register);
4662e82b
BA		 1974 adapter->eiac_mask |= tx_ring->ims_val;
1975 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1976
1977 /* set vector for Other Causes, e.g. link changes */
1978 vector++;
1979 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1980 if (rx_ring->itr_val)
1981 writel(1000000000 / (rx_ring->itr_val * 256),
1982 hw->hw_addr + E1000_EITR_82574(vector));
1983 else
1984 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1985
1986 /* Cause Tx interrupts on every write back */
1987 ivar |= (1 << 31);
1988
1989 ew32(IVAR, ivar);
1990
1991 /* enable MSI-X PBA support */
1992 ctrl_ext = er32(CTRL_EXT);
1993 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1994
1995 /* Auto-Mask Other interrupts upon ICR read */
4662e82b
BA		 1996 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1997 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1998 ew32(CTRL_EXT, ctrl_ext);
1999 e1e_flush();
2000}
2001
2002void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2003{
2004 if (adapter->msix_entries) {
2005 pci_disable_msix(adapter->pdev);
2006 kfree(adapter->msix_entries);
2007 adapter->msix_entries = NULL;
2008 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2009 pci_disable_msi(adapter->pdev);
2010 adapter->flags &= ~FLAG_MSI_ENABLED;
2011 }
4662e82b
BA		 2012}
2013
2014/**
2015 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2016 *
2017 * Attempt to configure interrupts using the best available
2018 * capabilities of the hardware and kernel.
2019 **/
2020void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2021{
2022 int err;
8e86acd7 2023 int i;
4662e82b
BA		 2024
2025 switch (adapter->int_mode) {
2026 case E1000E_INT_MODE_MSIX:
2027 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2028 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2029 adapter->msix_entries = kcalloc(adapter->num_vectors,
17e813ec
BA		 2030 sizeof(struct
2031 msix_entry),
2032 GFP_KERNEL);
4662e82b 2033 if (adapter->msix_entries) {
0cc7c959
AG		 2034 struct e1000_adapter *a = adapter;
2035
8e86acd7 2036 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2037 adapter->msix_entries[i].entry = i;
2038
0cc7c959
AG		 2039 err = pci_enable_msix_range(a->pdev,
2040 a->msix_entries,
2041 a->num_vectors,
2042 a->num_vectors);
2043 if (err > 0)
4662e82b
BA		 2044 return;
2045 }
2046 /* MSI-X failed, so fall through and try MSI */
ef456f85 2047 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2048 e1000e_reset_interrupt_capability(adapter);
2049 }
2050 adapter->int_mode = E1000E_INT_MODE_MSI;
2051 /* Fall through */
2052 case E1000E_INT_MODE_MSI:
2053 if (!pci_enable_msi(adapter->pdev)) {
2054 adapter->flags |= FLAG_MSI_ENABLED;
2055 } else {
2056 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2057 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2058 }
2059 /* Fall through */
2060 case E1000E_INT_MODE_LEGACY:
2061 /* Don't do anything; this is the system default */
2062 break;
2063 }
8e86acd7
JK		 2064
2065 /* store the number of vectors being used */
2066 adapter->num_vectors = 1;
4662e82b
BA		 2067}
2068
2069/**
2070 * e1000_request_msix - Initialize MSI-X interrupts
2071 *
2072 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2073 * kernel.
2074 **/
2075static int e1000_request_msix(struct e1000_adapter *adapter)
2076{
2077 struct net_device *netdev = adapter->netdev;
2078 int err = 0, vector = 0;
2079
2080 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2081 snprintf(adapter->rx_ring->name,
2082 sizeof(adapter->rx_ring->name) - 1,
2083 "%s-rx-0", netdev->name);
4662e82b
BA		 2084 else
2085 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2086 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2087 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2088 netdev);
2089 if (err)
5015e53a 2090 return err;
c5083cf6
BA		 2091 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2092 E1000_EITR_82574(vector);
4662e82b
BA		 2093 adapter->rx_ring->itr_val = adapter->itr;
2094 vector++;
2095
2096 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2097 snprintf(adapter->tx_ring->name,
2098 sizeof(adapter->tx_ring->name) - 1,
2099 "%s-tx-0", netdev->name);
4662e82b
BA		 2100 else
2101 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2102 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2103 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2104 netdev);
2105 if (err)
5015e53a 2106 return err;
c5083cf6
BA		 2107 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2108 E1000_EITR_82574(vector);
4662e82b
BA		 2109 adapter->tx_ring->itr_val = adapter->itr;
2110 vector++;
2111
2112 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2113 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2114 if (err)
5015e53a 2115 return err;
4662e82b
BA		 2116
2117 e1000_configure_msix(adapter);
5015e53a 2118
4662e82b 2119 return 0;
4662e82b
BA		 2120}
2121
f8d59f78
BA		 2122/**
2123 * e1000_request_irq - initialize interrupts
2124 *
2125 * Attempts to configure interrupts using the best available
2126 * capabilities of the hardware and kernel.
2127 **/
bc7f75fa
AK		 2128static int e1000_request_irq(struct e1000_adapter *adapter)
2129{
2130 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2131 int err;
2132
4662e82b
BA		 2133 if (adapter->msix_entries) {
2134 err = e1000_request_msix(adapter);
2135 if (!err)
2136 return err;
2137 /* fall back to MSI */
2138 e1000e_reset_interrupt_capability(adapter);
2139 adapter->int_mode = E1000E_INT_MODE_MSI;
2140 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2141 }
4662e82b 2142 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2143 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2144 netdev->name, netdev);
2145 if (!err)
2146 return err;
bc7f75fa 2147
4662e82b
BA		 2148 /* fall back to legacy interrupt */
2149 e1000e_reset_interrupt_capability(adapter);
2150 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2151 }
2152
a0607fd3 2153 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2154 netdev->name, netdev);
2155 if (err)
2156 e_err("Unable to allocate interrupt, Error: %d\n", err);
2157
bc7f75fa
AK		 2158 return err;
2159}
2160
2161static void e1000_free_irq(struct e1000_adapter *adapter)
2162{
2163 struct net_device *netdev = adapter->netdev;
2164
4662e82b
BA		 2165 if (adapter->msix_entries) {
2166 int vector = 0;
2167
2168 free_irq(adapter->msix_entries[vector].vector, netdev);
2169 vector++;
2170
2171 free_irq(adapter->msix_entries[vector].vector, netdev);
2172 vector++;
2173
2174 /* Other Causes interrupt vector */
2175 free_irq(adapter->msix_entries[vector].vector, netdev);
2176 return;
bc7f75fa 2177 }
4662e82b
BA		 2178
2179 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2180}
2181
2182/**
2183 * e1000_irq_disable - Mask off interrupt generation on the NIC
2184 **/
2185static void e1000_irq_disable(struct e1000_adapter *adapter)
2186{
2187 struct e1000_hw *hw = &adapter->hw;
2188
bc7f75fa 2189 ew32(IMC, ~0);
4662e82b
BA		 2190 if (adapter->msix_entries)
2191 ew32(EIAC_82574, 0);
bc7f75fa 2192 e1e_flush();
8e86acd7
JK		 2193
2194 if (adapter->msix_entries) {
2195 int i;
2196 for (i = 0; i < adapter->num_vectors; i++)
2197 synchronize_irq(adapter->msix_entries[i].vector);
2198 } else {
2199 synchronize_irq(adapter->pdev->irq);
2200 }
bc7f75fa
AK		 2201}
2202
2203/**
2204 * e1000_irq_enable - Enable default interrupt generation settings
2205 **/
2206static void e1000_irq_enable(struct e1000_adapter *adapter)
2207{
2208 struct e1000_hw *hw = &adapter->hw;
2209
4662e82b
BA		 2210 if (adapter->msix_entries) {
2211 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2212 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
94fb848b
BA		 2213 } else if (hw->mac.type == e1000_pch_lpt) {
2214 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2215 } else {
2216 ew32(IMS, IMS_ENABLE_MASK);
2217 }
74ef9c39 2218 e1e_flush();
bc7f75fa
AK		 2219}
2220
2221/**
31dbe5b4 2222 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2223 * @adapter: address of board private structure
2224 *
31dbe5b4 2225 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2226 * For ASF and Pass Through versions of f/w this means that
2227 * the driver is loaded. For AMT version (only with 82573)
2228 * of the f/w this means that the network i/f is open.
2229 **/
31dbe5b4 2230void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2231{
2232 struct e1000_hw *hw = &adapter->hw;
2233 u32 ctrl_ext;
2234 u32 swsm;
2235
2236 /* Let firmware know the driver has taken over */
2237 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2238 swsm = er32(SWSM);
2239 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2240 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2241 ctrl_ext = er32(CTRL_EXT);
ad68076e 2242 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2243 }
2244}
2245
2246/**
31dbe5b4 2247 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2248 * @adapter: address of board private structure
2249 *
31dbe5b4 2250 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2251 * For ASF and Pass Through versions of f/w this means that the
2252 * driver is no longer loaded. For AMT version (only with 82573) i
2253 * of the f/w this means that the network i/f is closed.
2254 *
2255 **/
31dbe5b4 2256void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2257{
2258 struct e1000_hw *hw = &adapter->hw;
2259 u32 ctrl_ext;
2260 u32 swsm;
2261
2262 /* Let firmware taken over control of h/w */
2263 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2264 swsm = er32(SWSM);
2265 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2266 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2267 ctrl_ext = er32(CTRL_EXT);
ad68076e 2268 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2269 }
2270}
2271
bc7f75fa 2272/**
49ce9c2c 2273 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2274 **/
2275static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2276 struct e1000_ring *ring)
2277{
2278 struct pci_dev *pdev = adapter->pdev;
2279
2280 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2281 GFP_KERNEL);
2282 if (!ring->desc)
2283 return -ENOMEM;
2284
2285 return 0;
2286}
2287
2288/**
2289 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2290 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2291 *
2292 * Return 0 on success, negative on failure
2293 **/
55aa6985 2294int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2295{
55aa6985 2296 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2297 int err = -ENOMEM, size;
2298
2299 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2300 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2301 if (!tx_ring->buffer_info)
2302 goto err;
bc7f75fa
AK		 2303
2304 /* round up to nearest 4K */
2305 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2306 tx_ring->size = ALIGN(tx_ring->size, 4096);
2307
2308 err = e1000_alloc_ring_dma(adapter, tx_ring);
2309 if (err)
2310 goto err;
2311
2312 tx_ring->next_to_use = 0;
2313 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2314
2315 return 0;
2316err:
2317 vfree(tx_ring->buffer_info);
44defeb3 2318 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2319 return err;
2320}
2321
2322/**
2323 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2324 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2325 *
2326 * Returns 0 on success, negative on failure
2327 **/
55aa6985 2328int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2329{
55aa6985 2330 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2331 struct e1000_buffer *buffer_info;
2332 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2333
2334 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2335 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2336 if (!rx_ring->buffer_info)
2337 goto err;
bc7f75fa 2338
47f44e40
AK		 2339 for (i = 0; i < rx_ring->count; i++) {
2340 buffer_info = &rx_ring->buffer_info[i];
2341 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2342 sizeof(struct e1000_ps_page),
2343 GFP_KERNEL);
2344 if (!buffer_info->ps_pages)
2345 goto err_pages;
2346 }
bc7f75fa
AK		 2347
2348 desc_len = sizeof(union e1000_rx_desc_packet_split);
2349
2350 /* Round up to nearest 4K */
2351 rx_ring->size = rx_ring->count * desc_len;
2352 rx_ring->size = ALIGN(rx_ring->size, 4096);
2353
2354 err = e1000_alloc_ring_dma(adapter, rx_ring);
2355 if (err)
47f44e40 2356 goto err_pages;
bc7f75fa
AK		 2357
2358 rx_ring->next_to_clean = 0;
2359 rx_ring->next_to_use = 0;
2360 rx_ring->rx_skb_top = NULL;
2361
2362 return 0;
47f44e40
AK		 2363
2364err_pages:
2365 for (i = 0; i < rx_ring->count; i++) {
2366 buffer_info = &rx_ring->buffer_info[i];
2367 kfree(buffer_info->ps_pages);
2368 }
bc7f75fa
AK		 2369err:
2370 vfree(rx_ring->buffer_info);
e9262447 2371 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2372 return err;
2373}
2374
2375/**
2376 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2377 * @tx_ring: Tx descriptor ring
bc7f75fa 2378 **/
55aa6985 2379static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2380{
55aa6985 2381 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2382 struct e1000_buffer *buffer_info;
2383 unsigned long size;
2384 unsigned int i;
2385
2386 for (i = 0; i < tx_ring->count; i++) {
2387 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2388 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2389 }
2390
3f0cfa3b 2391 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2392 size = sizeof(struct e1000_buffer) * tx_ring->count;
2393 memset(tx_ring->buffer_info, 0, size);
2394
2395 memset(tx_ring->desc, 0, tx_ring->size);
2396
2397 tx_ring->next_to_use = 0;
2398 tx_ring->next_to_clean = 0;
2399
c5083cf6 2400 writel(0, tx_ring->head);
b485dbae 2401 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
bdc125f7
BA		 2402 e1000e_update_tdt_wa(tx_ring, 0);
2403 else
2404 writel(0, tx_ring->tail);
bc7f75fa
AK		 2405}
2406
2407/**
2408 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2409 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2410 *
2411 * Free all transmit software resources
2412 **/
55aa6985 2413void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2414{
55aa6985 2415 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2416 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2417
55aa6985 2418 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2419
2420 vfree(tx_ring->buffer_info);
2421 tx_ring->buffer_info = NULL;
2422
2423 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2424 tx_ring->dma);
2425 tx_ring->desc = NULL;
2426}
2427
2428/**
2429 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2430 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2431 *
2432 * Free all receive software resources
2433 **/
55aa6985 2434void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2435{
55aa6985 2436 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2437 struct pci_dev *pdev = adapter->pdev;
47f44e40 2438 int i;
bc7f75fa 2439
55aa6985 2440 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2441
b1cdfead 2442 for (i = 0; i < rx_ring->count; i++)
47f44e40 2443 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2444
bc7f75fa
AK		 2445 vfree(rx_ring->buffer_info);
2446 rx_ring->buffer_info = NULL;
2447
bc7f75fa
AK		 2448 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2449 rx_ring->dma);
2450 rx_ring->desc = NULL;
2451}
2452
2453/**
2454 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2455 * @adapter: pointer to adapter
2456 * @itr_setting: current adapter->itr
2457 * @packets: the number of packets during this measurement interval
2458 * @bytes: the number of bytes during this measurement interval
2459 *
bc7f75fa
AK		 2460 * Stores a new ITR value based on packets and byte
2461 * counts during the last interrupt. The advantage of per interrupt
2462 * computation is faster updates and more accurate ITR for the current
2463 * traffic pattern. Constants in this function were computed
2464 * based on theoretical maximum wire speed and thresholds were set based
2465 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2466 * while increasing bulk throughput. This functionality is controlled
2467 * by the InterruptThrottleRate module parameter.
bc7f75fa 2468 **/
8bb62869 2469static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
bc7f75fa
AK		 2470{
2471 unsigned int retval = itr_setting;
2472
2473 if (packets == 0)
5015e53a 2474 return itr_setting;
bc7f75fa
AK		 2475
2476 switch (itr_setting) {
2477 case lowest_latency:
2478 /* handle TSO and jumbo frames */
362e20ca 2479 if (bytes / packets > 8000)
bc7f75fa 2480 retval = bulk_latency;
b1cdfead 2481 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2482 retval = low_latency;
bc7f75fa 2483 break;
e80bd1d1 2484 case low_latency: /* 50 usec aka 20000 ints/s */
bc7f75fa
AK		 2485 if (bytes > 10000) {
2486 /* this if handles the TSO accounting */
362e20ca 2487 if (bytes / packets > 8000)
bc7f75fa 2488 retval = bulk_latency;
362e20ca 2489 else if ((packets < 10) || ((bytes / packets) > 1200))
bc7f75fa 2490 retval = bulk_latency;
b1cdfead 2491 else if ((packets > 35))
bc7f75fa 2492 retval = lowest_latency;
362e20ca 2493 } else if (bytes / packets > 2000) {
bc7f75fa
AK		 2494 retval = bulk_latency;
2495 } else if (packets <= 2 && bytes < 512) {
2496 retval = lowest_latency;
2497 }
2498 break;
e80bd1d1 2499 case bulk_latency: /* 250 usec aka 4000 ints/s */
bc7f75fa 2500 if (bytes > 25000) {
b1cdfead 2501 if (packets > 35)
bc7f75fa 2502 retval = low_latency;
bc7f75fa
AK		 2503 } else if (bytes < 6000) {
2504 retval = low_latency;
2505 }
2506 break;
2507 }
2508
bc7f75fa
AK		 2509 return retval;
2510}
2511
2512static void e1000_set_itr(struct e1000_adapter *adapter)
2513{
bc7f75fa
AK		 2514 u16 current_itr;
2515 u32 new_itr = adapter->itr;
2516
2517 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2518 if (adapter->link_speed != SPEED_1000) {
2519 current_itr = 0;
2520 new_itr = 4000;
2521 goto set_itr_now;
2522 }
2523
828bac87
BA		 2524 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2525 new_itr = 0;
2526 goto set_itr_now;
2527 }
2528
8bb62869
BA		 2529 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2530 adapter->total_tx_packets,
2531 adapter->total_tx_bytes);
bc7f75fa
AK		 2532 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2533 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2534 adapter->tx_itr = low_latency;
2535
8bb62869
BA		 2536 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2537 adapter->total_rx_packets,
2538 adapter->total_rx_bytes);
bc7f75fa
AK		 2539 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2540 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2541 adapter->rx_itr = low_latency;
2542
2543 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2544
bc7f75fa 2545 /* counts and packets in update_itr are dependent on these numbers */
33550cec 2546 switch (current_itr) {
bc7f75fa
AK		 2547 case lowest_latency:
2548 new_itr = 70000;
2549 break;
2550 case low_latency:
e80bd1d1 2551 new_itr = 20000; /* aka hwitr = ~200 */
bc7f75fa
AK		 2552 break;
2553 case bulk_latency:
2554 new_itr = 4000;
2555 break;
2556 default:
2557 break;
2558 }
2559
2560set_itr_now:
2561 if (new_itr != adapter->itr) {
e921eb1a 2562 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2563 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2564 * increasing
2565 */
bc7f75fa 2566 new_itr = new_itr > adapter->itr ?
f0ff4398 2567 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
bc7f75fa 2568 adapter->itr = new_itr;
4662e82b
BA		 2569 adapter->rx_ring->itr_val = new_itr;
2570 if (adapter->msix_entries)
2571 adapter->rx_ring->set_itr = 1;
2572 else
e3d14b08 2573 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2574 }
2575}
2576
22a4cca2
MV		 2577/**
2578 * e1000e_write_itr - write the ITR value to the appropriate registers
2579 * @adapter: address of board private structure
2580 * @itr: new ITR value to program
2581 *
2582 * e1000e_write_itr determines if the adapter is in MSI-X mode
2583 * and, if so, writes the EITR registers with the ITR value.
2584 * Otherwise, it writes the ITR value into the ITR register.
2585 **/
2586void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2587{
2588 struct e1000_hw *hw = &adapter->hw;
2589 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2590
2591 if (adapter->msix_entries) {
2592 int vector;
2593
2594 for (vector = 0; vector < adapter->num_vectors; vector++)
2595 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2596 } else {
2597 ew32(ITR, new_itr);
2598 }
2599}
2600
4662e82b
BA		 2601/**
2602 * e1000_alloc_queues - Allocate memory for all rings
2603 * @adapter: board private structure to initialize
2604 **/
9f9a12f8 2605static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2606{
55aa6985
BA		 2607 int size = sizeof(struct e1000_ring);
2608
2609 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2610 if (!adapter->tx_ring)
2611 goto err;
55aa6985
BA		 2612 adapter->tx_ring->count = adapter->tx_ring_count;
2613 adapter->tx_ring->adapter = adapter;
4662e82b 2614
55aa6985 2615 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2616 if (!adapter->rx_ring)
2617 goto err;
55aa6985
BA		 2618 adapter->rx_ring->count = adapter->rx_ring_count;
2619 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2620
2621 return 0;
2622err:
2623 e_err("Unable to allocate memory for queues\n");
2624 kfree(adapter->rx_ring);
2625 kfree(adapter->tx_ring);
2626 return -ENOMEM;
2627}
2628
bc7f75fa 2629/**
c58c8a78 2630 * e1000e_poll - NAPI Rx polling callback
ad68076e 2631 * @napi: struct associated with this polling callback
c58c8a78 2632 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2633 **/
c58c8a78 2634static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2635{
c58c8a78
BA		 2636 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2637 napi);
4662e82b 2638 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2639 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2640 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2641
4cf1653a 2642 adapter = netdev_priv(poll_dev);
bc7f75fa 2643
c58c8a78
BA		 2644 if (!adapter->msix_entries ||
2645 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2646 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2647
c58c8a78 2648 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2649
12d04a3c 2650 if (!tx_cleaned)
c58c8a78 2651 work_done = weight;
bc7f75fa 2652
c58c8a78
BA		 2653 /* If weight not fully consumed, exit the polling mode */
2654 if (work_done < weight) {
bc7f75fa
AK		 2655 if (adapter->itr_setting & 3)
2656 e1000_set_itr(adapter);
288379f0 2657 napi_complete(napi);
a3c69fef
JB		 2658 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2659 if (adapter->msix_entries)
2660 ew32(IMS, adapter->rx_ring->ims_val);
2661 else
2662 e1000_irq_enable(adapter);
2663 }
bc7f75fa
AK		 2664 }
2665
2666 return work_done;
2667}
2668
80d5c368 2669static int e1000_vlan_rx_add_vid(struct net_device *netdev,
603cdca9 2670 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2671{
2672 struct e1000_adapter *adapter = netdev_priv(netdev);
2673 struct e1000_hw *hw = &adapter->hw;
2674 u32 vfta, index;
2675
2676 /* don't update vlan cookie if already programmed */
2677 if ((adapter->hw.mng_cookie.status &
2678 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2679 (vid == adapter->mng_vlan_id))
8e586137 2680 return 0;
caaddaf8 2681
bc7f75fa 2682 /* add VID to filter table */
caaddaf8
BA		 2683 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2684 index = (vid >> 5) & 0x7F;
2685 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2686 vfta |= (1 << (vid & 0x1F));
2687 hw->mac.ops.write_vfta(hw, index, vfta);
2688 }
86d70e53
JK		 2689
2690 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2691
2692 return 0;
bc7f75fa
AK		 2693}
2694
80d5c368 2695static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
603cdca9 2696 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2697{
2698 struct e1000_adapter *adapter = netdev_priv(netdev);
2699 struct e1000_hw *hw = &adapter->hw;
2700 u32 vfta, index;
2701
bc7f75fa
AK		 2702 if ((adapter->hw.mng_cookie.status &
2703 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2704 (vid == adapter->mng_vlan_id)) {
2705 /* release control to f/w */
31dbe5b4 2706 e1000e_release_hw_control(adapter);
8e586137 2707 return 0;
bc7f75fa
AK		 2708 }
2709
2710 /* remove VID from filter table */
caaddaf8
BA		 2711 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2712 index = (vid >> 5) & 0x7F;
2713 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2714 vfta &= ~(1 << (vid & 0x1F));
2715 hw->mac.ops.write_vfta(hw, index, vfta);
2716 }
86d70e53
JK		 2717
2718 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2719
2720 return 0;
bc7f75fa
AK		 2721}
2722
86d70e53
JK		 2723/**
2724 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2725 * @adapter: board private structure to initialize
2726 **/
2727static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2728{
2729 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2730 struct e1000_hw *hw = &adapter->hw;
2731 u32 rctl;
bc7f75fa 2732
86d70e53
JK		 2733 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2734 /* disable VLAN receive filtering */
2735 rctl = er32(RCTL);
2736 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2737 ew32(RCTL, rctl);
2738
2739 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
80d5c368
PM		 2740 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2741 adapter->mng_vlan_id);
86d70e53 2742 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2743 }
bc7f75fa
AK		 2744 }
2745}
2746
86d70e53
JK		 2747/**
2748 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2749 * @adapter: board private structure to initialize
2750 **/
2751static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2752{
2753 struct e1000_hw *hw = &adapter->hw;
2754 u32 rctl;
2755
2756 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2757 /* enable VLAN receive filtering */
2758 rctl = er32(RCTL);
2759 rctl |= E1000_RCTL_VFE;
2760 rctl &= ~E1000_RCTL_CFIEN;
2761 ew32(RCTL, rctl);
2762 }
2763}
bc7f75fa 2764
86d70e53
JK		 2765/**
2766 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2767 * @adapter: board private structure to initialize
2768 **/
2769static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2770{
bc7f75fa 2771 struct e1000_hw *hw = &adapter->hw;
86d70e53 2772 u32 ctrl;
bc7f75fa 2773
86d70e53
JK		 2774 /* disable VLAN tag insert/strip */
2775 ctrl = er32(CTRL);
2776 ctrl &= ~E1000_CTRL_VME;
2777 ew32(CTRL, ctrl);
2778}
bc7f75fa 2779
86d70e53
JK		 2780/**
2781 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2782 * @adapter: board private structure to initialize
2783 **/
2784static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2785{
2786 struct e1000_hw *hw = &adapter->hw;
2787 u32 ctrl;
bc7f75fa 2788
86d70e53
JK		 2789 /* enable VLAN tag insert/strip */
2790 ctrl = er32(CTRL);
2791 ctrl |= E1000_CTRL_VME;
2792 ew32(CTRL, ctrl);
2793}
bc7f75fa 2794
86d70e53
JK		 2795static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2796{
2797 struct net_device *netdev = adapter->netdev;
2798 u16 vid = adapter->hw.mng_cookie.vlan_id;
2799 u16 old_vid = adapter->mng_vlan_id;
2800
e5fe2541 2801 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
80d5c368 2802 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
86d70e53 2803 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2804 }
2805
86d70e53 2806 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
80d5c368 2807 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
bc7f75fa
AK		 2808}
2809
2810static void e1000_restore_vlan(struct e1000_adapter *adapter)
2811{
2812 u16 vid;
2813
80d5c368 2814 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
bc7f75fa 2815
86d70e53 2816 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 2817 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
bc7f75fa
AK		 2818}
2819
cd791618 2820static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2821{
2822 struct e1000_hw *hw = &adapter->hw;
cd791618 2823 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2824
2825 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2826 return;
2827
2828 manc = er32(MANC);
2829
e921eb1a 2830 /* enable receiving management packets to the host. this will probably
bc7f75fa 2831 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2832 * the packets will be handled on SMBUS
2833 */
bc7f75fa
AK		 2834 manc |= E1000_MANC_EN_MNG2HOST;
2835 manc2h = er32(MANC2H);
cd791618
BA		 2836
2837 switch (hw->mac.type) {
2838 default:
2839 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2840 break;
2841 case e1000_82574:
2842 case e1000_82583:
e921eb1a 2843 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2844 * if so, enable it.
2845 */
2846 for (i = 0, j = 0; i < 8; i++) {
2847 mdef = er32(MDEF(i));
2848
2849 /* Ignore filters with anything other than IPMI ports */
3b21b508 2850 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2851 continue;
2852
2853 /* Enable this decision filter in MANC2H */
2854 if (mdef)
2855 manc2h |= (1 << i);
2856
2857 j |= mdef;
2858 }
2859
2860 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2861 break;
2862
2863 /* Create new decision filter in an empty filter */
2864 for (i = 0, j = 0; i < 8; i++)
2865 if (er32(MDEF(i)) == 0) {
2866 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2867 E1000_MDEF_PORT_664));
2868 manc2h |= (1 << 1);
2869 j++;
2870 break;
2871 }
2872
2873 if (!j)
2874 e_warn("Unable to create IPMI pass-through filter\n");
2875 break;
2876 }
2877
bc7f75fa
AK		 2878 ew32(MANC2H, manc2h);
2879 ew32(MANC, manc);
2880}
2881
2882/**
af667a29 2883 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2884 * @adapter: board private structure
2885 *
2886 * Configure the Tx unit of the MAC after a reset.
2887 **/
2888static void e1000_configure_tx(struct e1000_adapter *adapter)
2889{
2890 struct e1000_hw *hw = &adapter->hw;
2891 struct e1000_ring *tx_ring = adapter->tx_ring;
2892 u64 tdba;
c550b121 2893 u32 tdlen, tarc;
bc7f75fa
AK		 2894
2895 /* Setup the HW Tx Head and Tail descriptor pointers */
2896 tdba = tx_ring->dma;
2897 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2898 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2899 ew32(TDBAH(0), (tdba >> 32));
2900 ew32(TDLEN(0), tdlen);
2901 ew32(TDH(0), 0);
2902 ew32(TDT(0), 0);
2903 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2904 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2905
bc7f75fa
AK		 2906 /* Set the Tx Interrupt Delay register */
2907 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2908 /* Tx irq moderation */
bc7f75fa
AK		 2909 ew32(TADV, adapter->tx_abs_int_delay);
2910
3a3b7586
JB		 2911 if (adapter->flags2 & FLAG2_DMA_BURST) {
2912 u32 txdctl = er32(TXDCTL(0));
2913 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2914 E1000_TXDCTL_WTHRESH);
e921eb1a 2915 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2916 * hardware to use the bus more efficiently in bursts, depends
2917 * on the tx_int_delay to be enabled,
8edc0e62 2918 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2919 * hthresh = 1 ==> prefetch when one or more available
2920 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2921 * BEWARE: this seems to work but should be considered first if
af667a29 2922 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2923 */
2924 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2925 ew32(TXDCTL(0), txdctl);
3a3b7586 2926 }
56032be7
BA		 2927 /* erratum work around: set txdctl the same for both queues */
2928 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2929
bc7f75fa 2930 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2931 tarc = er32(TARC(0));
e921eb1a 2932 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2933 * gigabit link later
2934 */
bc7f75fa
AK		 2935#define SPEED_MODE_BIT (1 << 21)
2936 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2937 ew32(TARC(0), tarc);
bc7f75fa
AK		 2938 }
2939
2940 /* errata: program both queues to unweighted RR */
2941 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2942 tarc = er32(TARC(0));
bc7f75fa 2943 tarc |= 1;
e9ec2c0f
JK		 2944 ew32(TARC(0), tarc);
2945 tarc = er32(TARC(1));
bc7f75fa 2946 tarc |= 1;
e9ec2c0f 2947 ew32(TARC(1), tarc);
bc7f75fa
AK		 2948 }
2949
bc7f75fa
AK		 2950 /* Setup Transmit Descriptor Settings for eop descriptor */
2951 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2952
2953 /* only set IDE if we are delaying interrupts using the timers */
2954 if (adapter->tx_int_delay)
2955 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2956
2957 /* enable Report Status bit */
2958 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2959
57cde763 2960 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2961}
2962
2963/**
2964 * e1000_setup_rctl - configure the receive control registers
2965 * @adapter: Board private structure
2966 **/
2967#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2968 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2969static void e1000_setup_rctl(struct e1000_adapter *adapter)
2970{
2971 struct e1000_hw *hw = &adapter->hw;
2972 u32 rctl, rfctl;
bc7f75fa
AK		 2973 u32 pages = 0;
2974
2fbe4526 2975 /* Workaround Si errata on PCHx - configure jumbo frame flow */
da1e2046
BA		 2976 if ((hw->mac.type >= e1000_pch2lan) &&
2977 (adapter->netdev->mtu > ETH_DATA_LEN) &&
2978 e1000_lv_jumbo_workaround_ich8lan(hw, true))
2979 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473 2980
bc7f75fa
AK		 2981 /* Program MC offset vector base */
2982 rctl = er32(RCTL);
2983 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2984 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
f0ff4398
BA		 2985 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2986 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
bc7f75fa
AK		 2987
2988 /* Do not Store bad packets */
2989 rctl &= ~E1000_RCTL_SBP;
2990
2991 /* Enable Long Packet receive */
2992 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2993 rctl &= ~E1000_RCTL_LPE;
2994 else
2995 rctl |= E1000_RCTL_LPE;
2996
eb7c3adb
JK		 2997 /* Some systems expect that the CRC is included in SMBUS traffic. The
2998 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2999 * host memory when this is enabled
3000 */
3001 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3002 rctl |= E1000_RCTL_SECRC;
5918bd88 3003
a4f58f54
BA		 3004 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3005 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3006 u16 phy_data;
3007
3008 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3009 phy_data &= 0xfff8;
3010 phy_data |= (1 << 2);
3011 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3012
3013 e1e_rphy(hw, 22, &phy_data);
3014 phy_data &= 0x0fff;
3015 phy_data |= (1 << 14);
3016 e1e_wphy(hw, 0x10, 0x2823);
3017 e1e_wphy(hw, 0x11, 0x0003);
3018 e1e_wphy(hw, 22, phy_data);
3019 }
3020
bc7f75fa
AK		 3021 /* Setup buffer sizes */
3022 rctl &= ~E1000_RCTL_SZ_4096;
3023 rctl |= E1000_RCTL_BSEX;
3024 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3025 case 2048:
3026 default:
3027 rctl |= E1000_RCTL_SZ_2048;
3028 rctl &= ~E1000_RCTL_BSEX;
3029 break;
3030 case 4096:
3031 rctl |= E1000_RCTL_SZ_4096;
3032 break;
3033 case 8192:
3034 rctl |= E1000_RCTL_SZ_8192;
3035 break;
3036 case 16384:
3037 rctl |= E1000_RCTL_SZ_16384;
3038 break;
3039 }
3040
5f450212
BA		 3041 /* Enable Extended Status in all Receive Descriptors */
3042 rfctl = er32(RFCTL);
3043 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3044 ew32(RFCTL, rfctl);
5f450212 3045
e921eb1a 3046 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3047 * header is placed in skb->data and the packet data is
3048 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3049 * In the case of a non-split, skb->data is linearly filled,
3050 * followed by the page buffers. Therefore, skb->data is
3051 * sized to hold the largest protocol header.
3052 *
3053 * allocations using alloc_page take too long for regular MTU
3054 * so only enable packet split for jumbo frames
3055 *
3056 * Using pages when the page size is greater than 16k wastes
3057 * a lot of memory, since we allocate 3 pages at all times
3058 * per packet.
3059 */
bc7f75fa 3060 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3061 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3062 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3063 else
3064 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3065
3066 if (adapter->rx_ps_pages) {
90da0669
BA		 3067 u32 psrctl = 0;
3068
140a7480
AK		 3069 /* Enable Packet split descriptors */
3070 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa 3071
e5fe2541 3072 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
bc7f75fa
AK		 3073
3074 switch (adapter->rx_ps_pages) {
3075 case 3:
e5fe2541
BA		 3076 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3077 /* fall-through */
bc7f75fa 3078 case 2:
e5fe2541
BA		 3079 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3080 /* fall-through */
bc7f75fa 3081 case 1:
e5fe2541 3082 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
bc7f75fa
AK		 3083 break;
3084 }
3085
3086 ew32(PSRCTL, psrctl);
3087 }
3088
cf955e6c
BG		 3089 /* This is useful for sniffing bad packets. */
3090 if (adapter->netdev->features & NETIF_F_RXALL) {
3091 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3092 * in e1000e_set_rx_mode
3093 */
e80bd1d1
BA		 3094 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3095 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3096 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
cf955e6c 3097
e80bd1d1
BA		 3098 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3099 E1000_RCTL_DPF | /* Allow filtered pause */
3100 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
cf955e6c
BG		 3101 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3102 * and that breaks VLANs.
3103 */
3104 }
3105
bc7f75fa 3106 ew32(RCTL, rctl);
318a94d6 3107 /* just started the receive unit, no need to restart */
12d43f7d 3108 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3109}
3110
3111/**
3112 * e1000_configure_rx - Configure Receive Unit after Reset
3113 * @adapter: board private structure
3114 *
3115 * Configure the Rx unit of the MAC after a reset.
3116 **/
3117static void e1000_configure_rx(struct e1000_adapter *adapter)
3118{
3119 struct e1000_hw *hw = &adapter->hw;
3120 struct e1000_ring *rx_ring = adapter->rx_ring;
3121 u64 rdba;
3122 u32 rdlen, rctl, rxcsum, ctrl_ext;
3123
3124 if (adapter->rx_ps_pages) {
3125 /* this is a 32 byte descriptor */
3126 rdlen = rx_ring->count *
af667a29 3127 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3128 adapter->clean_rx = e1000_clean_rx_irq_ps;
3129 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3130 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3131 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3132 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3133 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3134 } else {
5f450212 3135 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3136 adapter->clean_rx = e1000_clean_rx_irq;
3137 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3138 }
3139
3140 /* disable receives while setting up the descriptors */
3141 rctl = er32(RCTL);
7f99ae63
BA		 3142 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3143 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3144 e1e_flush();
1bba4386 3145 usleep_range(10000, 20000);
bc7f75fa 3146
3a3b7586 3147 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3148 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3149 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3150 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3151 * granularity = 01
3152 * wthresh = 04,
3153 * hthresh = 04,
3154 * pthresh = 0x20
3155 */
3156 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3157 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3158
e921eb1a 3159 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3160 * the value was not set by the user via module options
3161 */
3162 if (adapter->rx_int_delay == DEFAULT_RDTR)
3163 adapter->rx_int_delay = BURST_RDTR;
3164 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3165 adapter->rx_abs_int_delay = BURST_RADV;
3166 }
3167
bc7f75fa
AK		 3168 /* set the Receive Delay Timer Register */
3169 ew32(RDTR, adapter->rx_int_delay);
3170
3171 /* irq moderation */
3172 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3173 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3174 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3175
3176 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3177 /* Auto-Mask interrupts upon ICR access */
3178 ctrl_ext |= E1000_CTRL_EXT_IAME;
3179 ew32(IAM, 0xffffffff);
3180 ew32(CTRL_EXT, ctrl_ext);
3181 e1e_flush();
3182
e921eb1a 3183 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3184 * the Base and Length of the Rx Descriptor Ring
3185 */
bc7f75fa 3186 rdba = rx_ring->dma;
1e36052e
BA		 3187 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3188 ew32(RDBAH(0), (rdba >> 32));
3189 ew32(RDLEN(0), rdlen);
3190 ew32(RDH(0), 0);
3191 ew32(RDT(0), 0);
3192 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3193 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3194
3195 /* Enable Receive Checksum Offload for TCP and UDP */
3196 rxcsum = er32(RXCSUM);
2e1706f2 3197 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3198 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3199 else
bc7f75fa 3200 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3201 ew32(RXCSUM, rxcsum);
3202
3e35d991
BA		 3203 /* With jumbo frames, excessive C-state transition latencies result
3204 * in dropped transactions.
3205 */
3206 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3207 u32 lat =
3208 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3209 adapter->max_frame_size) * 8 / 1000;
3210
3211 if (adapter->flags & FLAG_IS_ICH) {
53ec5498
BA		 3212 u32 rxdctl = er32(RXDCTL(0));
3213 ew32(RXDCTL(0), rxdctl | 0x3);
53ec5498 3214 }
3e35d991
BA		 3215
3216 pm_qos_update_request(&adapter->netdev->pm_qos_req, lat);
3217 } else {
3218 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3219 PM_QOS_DEFAULT_VALUE);
97ac8cae 3220 }
bc7f75fa
AK		 3221
3222 /* Enable Receives */
3223 ew32(RCTL, rctl);
3224}
3225
3226/**
ef9b965a
JB		 3227 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3228 * @netdev: network interface device structure
bc7f75fa 3229 *
ef9b965a
JB		 3230 * Writes multicast address list to the MTA hash table.
3231 * Returns: -ENOMEM on failure
3232 * 0 on no addresses written
3233 * X on writing X addresses to MTA
3234 */
3235static int e1000e_write_mc_addr_list(struct net_device *netdev)
3236{
3237 struct e1000_adapter *adapter = netdev_priv(netdev);
3238 struct e1000_hw *hw = &adapter->hw;
3239 struct netdev_hw_addr *ha;
3240 u8 *mta_list;
3241 int i;
3242
3243 if (netdev_mc_empty(netdev)) {
3244 /* nothing to program, so clear mc list */
3245 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3246 return 0;
3247 }
3248
3249 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3250 if (!mta_list)
3251 return -ENOMEM;
3252
3253 /* update_mc_addr_list expects a packed array of only addresses. */
3254 i = 0;
3255 netdev_for_each_mc_addr(ha, netdev)
f0ff4398 3256 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
ef9b965a
JB		 3257
3258 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3259 kfree(mta_list);
3260
3261 return netdev_mc_count(netdev);
3262}
3263
3264/**
3265 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3266 * @netdev: network interface device structure
bc7f75fa 3267 *
ef9b965a
JB		 3268 * Writes unicast address list to the RAR table.
3269 * Returns: -ENOMEM on failure/insufficient address space
3270 * 0 on no addresses written
3271 * X on writing X addresses to the RAR table
bc7f75fa 3272 **/
ef9b965a 3273static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3274{
ef9b965a
JB		 3275 struct e1000_adapter *adapter = netdev_priv(netdev);
3276 struct e1000_hw *hw = &adapter->hw;
3277 unsigned int rar_entries = hw->mac.rar_entry_count;
3278 int count = 0;
3279
3280 /* save a rar entry for our hardware address */
3281 rar_entries--;
3282
3283 /* save a rar entry for the LAA workaround */
3284 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3285 rar_entries--;
3286
3287 /* return ENOMEM indicating insufficient memory for addresses */
3288 if (netdev_uc_count(netdev) > rar_entries)
3289 return -ENOMEM;
3290
3291 if (!netdev_uc_empty(netdev) && rar_entries) {
3292 struct netdev_hw_addr *ha;
3293
e921eb1a 3294 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3295 * combining
3296 */
3297 netdev_for_each_uc_addr(ha, netdev) {
3298 if (!rar_entries)
3299 break;
69e1e019 3300 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3301 count++;
3302 }
3303 }
3304
3305 /* zero out the remaining RAR entries not used above */
3306 for (; rar_entries > 0; rar_entries--) {
3307 ew32(RAH(rar_entries), 0);
3308 ew32(RAL(rar_entries), 0);
3309 }
3310 e1e_flush();
3311
3312 return count;
bc7f75fa
AK		 3313}
3314
3315/**
ef9b965a 3316 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3317 * @netdev: network interface device structure
3318 *
ef9b965a
JB		 3319 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3320 * address list or the network interface flags are updated. This routine is
3321 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3322 * promiscuous mode, and all-multi behavior.
3323 **/
ef9b965a 3324static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3325{
3326 struct e1000_adapter *adapter = netdev_priv(netdev);
3327 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3328 u32 rctl;
bc7f75fa 3329
63eb48f1
DE		 3330 if (pm_runtime_suspended(netdev->dev.parent))
3331 return;
3332
bc7f75fa 3333 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3334 rctl = er32(RCTL);
3335
ef9b965a
JB		 3336 /* clear the affected bits */
3337 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3338
bc7f75fa
AK		 3339 if (netdev->flags & IFF_PROMISC) {
3340 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3341 /* Do not hardware filter VLANs in promisc mode */
3342 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3343 } else {
ef9b965a 3344 int count;
3d3a1676 3345
746b9f02
PM		 3346 if (netdev->flags & IFF_ALLMULTI) {
3347 rctl |= E1000_RCTL_MPE;
746b9f02 3348 } else {
e921eb1a 3349 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3350 * then we should just turn on promiscuous mode so
3351 * that we can at least receive multicast traffic
3352 */
3353 count = e1000e_write_mc_addr_list(netdev);
3354 if (count < 0)
3355 rctl |= E1000_RCTL_MPE;
746b9f02 3356 }
86d70e53 3357 e1000e_vlan_filter_enable(adapter);
e921eb1a 3358 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3359 * sufficient space to store all the addresses then enable
3360 * unicast promiscuous mode
bc7f75fa 3361 */
ef9b965a
JB		 3362 count = e1000e_write_uc_addr_list(netdev);
3363 if (count < 0)
3364 rctl |= E1000_RCTL_UPE;
bc7f75fa 3365 }
86d70e53 3366
ef9b965a
JB		 3367 ew32(RCTL, rctl);
3368
f646968f 3369 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
86d70e53
JK		 3370 e1000e_vlan_strip_enable(adapter);
3371 else
3372 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3373}
3374
70495a50
BA		 3375static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3376{
3377 struct e1000_hw *hw = &adapter->hw;
3378 u32 mrqc, rxcsum;
3379 int i;
3380 static const u32 rsskey[10] = {
3381 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3382 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3383 };
3384
3385 /* Fill out hash function seed */
3386 for (i = 0; i < 10; i++)
3387 ew32(RSSRK(i), rsskey[i]);
3388
3389 /* Direct all traffic to queue 0 */
3390 for (i = 0; i < 32; i++)
3391 ew32(RETA(i), 0);
3392
e921eb1a 3393 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3394 * descriptor on writeback.
3395 */
3396 rxcsum = er32(RXCSUM);
3397 rxcsum |= E1000_RXCSUM_PCSD;
3398
3399 ew32(RXCSUM, rxcsum);
3400
3401 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3402 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3403 E1000_MRQC_RSS_FIELD_IPV6 |
3404 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3405 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3406
3407 ew32(MRQC, mrqc);
3408}
3409
b67e1913
BA		 3410/**
3411 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3412 * @adapter: board private structure
3413 * @timinca: pointer to returned time increment attributes
3414 *
3415 * Get attributes for incrementing the System Time Register SYSTIML/H at
3416 * the default base frequency, and set the cyclecounter shift value.
3417 **/
d89777bf 3418s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3419{
3420 struct e1000_hw *hw = &adapter->hw;
3421 u32 incvalue, incperiod, shift;
3422
3423 /* Make sure clock is enabled on I217 before checking the frequency */
3424 if ((hw->mac.type == e1000_pch_lpt) &&
3425 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3426 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3427 u32 fextnvm7 = er32(FEXTNVM7);
3428
3429 if (!(fextnvm7 & (1 << 0))) {
3430 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3431 e1e_flush();
3432 }
3433 }
3434
3435 switch (hw->mac.type) {
3436 case e1000_pch2lan:
3437 case e1000_pch_lpt:
3438 /* On I217, the clock frequency is 25MHz or 96MHz as
3439 * indicated by the System Clock Frequency Indication
3440 */
3441 if ((hw->mac.type != e1000_pch_lpt) ||
3442 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3443 /* Stable 96MHz frequency */
3444 incperiod = INCPERIOD_96MHz;
3445 incvalue = INCVALUE_96MHz;
3446 shift = INCVALUE_SHIFT_96MHz;
3447 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3448 break;
3449 }
3450 /* fall-through */
3451 case e1000_82574:
3452 case e1000_82583:
3453 /* Stable 25MHz frequency */
3454 incperiod = INCPERIOD_25MHz;
3455 incvalue = INCVALUE_25MHz;
3456 shift = INCVALUE_SHIFT_25MHz;
3457 adapter->cc.shift = shift;
3458 break;
3459 default:
3460 return -EINVAL;
3461 }
3462
3463 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3464 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3465
3466 return 0;
3467}
3468
3469/**
3470 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3471 * @adapter: board private structure
3472 *
3473 * Outgoing time stamping can be enabled and disabled. Play nice and
3474 * disable it when requested, although it shouldn't cause any overhead
3475 * when no packet needs it. At most one packet in the queue may be
3476 * marked for time stamping, otherwise it would be impossible to tell
3477 * for sure to which packet the hardware time stamp belongs.
3478 *
3479 * Incoming time stamping has to be configured via the hardware filters.
3480 * Not all combinations are supported, in particular event type has to be
3481 * specified. Matching the kind of event packet is not supported, with the
3482 * exception of "all V2 events regardless of level 2 or 4".
3483 **/
62d7e3a2
BH		 3484static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3485 struct hwtstamp_config *config)
b67e1913
BA		 3486{
3487 struct e1000_hw *hw = &adapter->hw;
b67e1913
BA		 3488 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3489 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3490 u32 rxmtrl = 0;
3491 u16 rxudp = 0;
3492 bool is_l4 = false;
3493 bool is_l2 = false;
b67e1913
BA		 3494 u32 regval;
3495 s32 ret_val;
3496
3497 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3498 return -EINVAL;
3499
3500 /* flags reserved for future extensions - must be zero */
3501 if (config->flags)
3502 return -EINVAL;
3503
3504 switch (config->tx_type) {
3505 case HWTSTAMP_TX_OFF:
3506 tsync_tx_ctl = 0;
3507 break;
3508 case HWTSTAMP_TX_ON:
3509 break;
3510 default:
3511 return -ERANGE;
3512 }
3513
3514 switch (config->rx_filter) {
3515 case HWTSTAMP_FILTER_NONE:
3516 tsync_rx_ctl = 0;
3517 break;
d89777bf
BA		 3518 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3519 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3520 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3521 is_l4 = true;
3522 break;
3523 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3524 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3525 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3526 is_l4 = true;
3527 break;
3528 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3529 /* Also time stamps V2 L2 Path Delay Request/Response */
3530 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3531 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3532 is_l2 = true;
3533 break;
3534 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3535 /* Also time stamps V2 L2 Path Delay Request/Response. */
3536 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3537 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3538 is_l2 = true;
3539 break;
3540 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3541 /* Hardware cannot filter just V2 L4 Sync messages;
3542 * fall-through to V2 (both L2 and L4) Sync.
3543 */
3544 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3545 /* Also time stamps V2 Path Delay Request/Response. */
3546 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3547 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3548 is_l2 = true;
3549 is_l4 = true;
3550 break;
3551 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3552 /* Hardware cannot filter just V2 L4 Delay Request messages;
3553 * fall-through to V2 (both L2 and L4) Delay Request.
3554 */
3555 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3556 /* Also time stamps V2 Path Delay Request/Response. */
3557 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3558 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3559 is_l2 = true;
3560 is_l4 = true;
3561 break;
3562 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3563 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3564 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3565 * fall-through to all V2 (both L2 and L4) Events.
3566 */
3567 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3568 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3569 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3570 is_l2 = true;
3571 is_l4 = true;
3572 break;
3573 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3574 /* For V1, the hardware can only filter Sync messages or
3575 * Delay Request messages but not both so fall-through to
3576 * time stamp all packets.
3577 */
b67e1913 3578 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3579 is_l2 = true;
3580 is_l4 = true;
b67e1913
BA		 3581 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3582 config->rx_filter = HWTSTAMP_FILTER_ALL;
3583 break;
3584 default:
3585 return -ERANGE;
3586 }
3587
62d7e3a2
BH		 3588 adapter->hwtstamp_config = *config;
3589
b67e1913
BA		 3590 /* enable/disable Tx h/w time stamping */
3591 regval = er32(TSYNCTXCTL);
3592 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3593 regval |= tsync_tx_ctl;
3594 ew32(TSYNCTXCTL, regval);
3595 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3596 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3597 e_err("Timesync Tx Control register not set as expected\n");
3598 return -EAGAIN;
3599 }
3600
3601 /* enable/disable Rx h/w time stamping */
3602 regval = er32(TSYNCRXCTL);
3603 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3604 regval |= tsync_rx_ctl;
3605 ew32(TSYNCRXCTL, regval);
3606 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3607 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3608 (regval & (E1000_TSYNCRXCTL_ENABLED |
3609 E1000_TSYNCRXCTL_TYPE_MASK))) {
3610 e_err("Timesync Rx Control register not set as expected\n");
3611 return -EAGAIN;
3612 }
3613
d89777bf
BA		 3614 /* L2: define ethertype filter for time stamped packets */
3615 if (is_l2)
3616 rxmtrl |= ETH_P_1588;
3617
3618 /* define which PTP packets get time stamped */
3619 ew32(RXMTRL, rxmtrl);
3620
3621 /* Filter by destination port */
3622 if (is_l4) {
3623 rxudp = PTP_EV_PORT;
3624 cpu_to_be16s(&rxudp);
3625 }
3626 ew32(RXUDP, rxudp);
3627
3628 e1e_flush();
3629
b67e1913 3630 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
70806a7f
BA		 3631 er32(RXSTMPH);
3632 er32(TXSTMPH);
b67e1913
BA		 3633
3634 /* Get and set the System Time Register SYSTIM base frequency */
3635 ret_val = e1000e_get_base_timinca(adapter, &regval);
3636 if (ret_val)
3637 return ret_val;
3638 ew32(TIMINCA, regval);
3639
3640 /* reset the ns time counter */
3641 timecounter_init(&adapter->tc, &adapter->cc,
3642 ktime_to_ns(ktime_get_real()));
3643
3644 return 0;
3645}
3646
bc7f75fa 3647/**
ad68076e 3648 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3649 * @adapter: private board structure
3650 **/
3651static void e1000_configure(struct e1000_adapter *adapter)
3652{
55aa6985
BA		 3653 struct e1000_ring *rx_ring = adapter->rx_ring;
3654
ef9b965a 3655 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3656
3657 e1000_restore_vlan(adapter);
cd791618 3658 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3659
3660 e1000_configure_tx(adapter);
70495a50
BA		 3661
3662 if (adapter->netdev->features & NETIF_F_RXHASH)
3663 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3664 e1000_setup_rctl(adapter);
3665 e1000_configure_rx(adapter);
55aa6985 3666 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3667}
3668
3669/**
3670 * e1000e_power_up_phy - restore link in case the phy was powered down
3671 * @adapter: address of board private structure
3672 *
3673 * The phy may be powered down to save power and turn off link when the
3674 * driver is unloaded and wake on lan is not enabled (among others)
3675 * *** this routine MUST be followed by a call to e1000e_reset ***
3676 **/
3677void e1000e_power_up_phy(struct e1000_adapter *adapter)
3678{
17f208de
BA		 3679 if (adapter->hw.phy.ops.power_up)
3680 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3681
3682 adapter->hw.mac.ops.setup_link(&adapter->hw);
3683}
3684
3685/**
3686 * e1000_power_down_phy - Power down the PHY
3687 *
17f208de
BA		 3688 * Power down the PHY so no link is implied when interface is down.
3689 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3690 */
3691static void e1000_power_down_phy(struct e1000_adapter *adapter)
3692{
17f208de
BA		 3693 if (adapter->hw.phy.ops.power_down)
3694 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3695}
3696
3697/**
3698 * e1000e_reset - bring the hardware into a known good state
3699 *
3700 * This function boots the hardware and enables some settings that
3701 * require a configuration cycle of the hardware - those cannot be
3702 * set/changed during runtime. After reset the device needs to be
ad68076e 3703 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3704 */
3705void e1000e_reset(struct e1000_adapter *adapter)
3706{
3707 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3708 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3709 struct e1000_hw *hw = &adapter->hw;
3710 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3711 u32 pba = adapter->pba;
bc7f75fa
AK		 3712 u16 hwm;
3713
ad68076e 3714 /* reset Packet Buffer Allocation to default */
318a94d6 3715 ew32(PBA, pba);
df762464 3716
318a94d6 3717 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3718 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3719 * large enough to accommodate two full transmit packets,
3720 * rounded up to the next 1KB and expressed in KB. Likewise,
3721 * the Rx FIFO should be large enough to accommodate at least
3722 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3723 * expressed in KB.
3724 */
df762464 3725 pba = er32(PBA);
bc7f75fa 3726 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3727 tx_space = pba >> 16;
bc7f75fa 3728 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3729 pba &= 0xffff;
e921eb1a 3730 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3731 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3732 */
3733 min_tx_space = (adapter->max_frame_size +
e5fe2541 3734 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
bc7f75fa
AK		 3735 min_tx_space = ALIGN(min_tx_space, 1024);
3736 min_tx_space >>= 10;
3737 /* software strips receive CRC, so leave room for it */
318a94d6 3738 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3739 min_rx_space = ALIGN(min_rx_space, 1024);
3740 min_rx_space >>= 10;
3741
e921eb1a 3742 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3743 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3744 * allocation, take space away from current Rx allocation
3745 */
df762464
AK		 3746 if ((tx_space < min_tx_space) &&
3747 ((min_tx_space - tx_space) < pba)) {
3748 pba -= min_tx_space - tx_space;
bc7f75fa 3749
e921eb1a 3750 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3751 * adjustment
ad68076e 3752 */
79d4e908 3753 if (pba < min_rx_space)
df762464 3754 pba = min_rx_space;
bc7f75fa 3755 }
df762464
AK		 3756
3757 ew32(PBA, pba);
bc7f75fa
AK		 3758 }
3759
e921eb1a 3760 /* flow control settings
ad68076e 3761 *
38eb394e 3762 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3763 * (or the size used for early receive) above it in the Rx FIFO.
3764 * Set it to the lower of:
3765 * - 90% of the Rx FIFO size, and
38eb394e 3766 * - the full Rx FIFO size minus one full frame
ad68076e 3767 */
d3738bb8
BA		 3768 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3769 fc->pause_time = 0xFFFF;
3770 else
3771 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3772 fc->send_xon = true;
d3738bb8
BA		 3773 fc->current_mode = fc->requested_mode;
3774
3775 switch (hw->mac.type) {
79d4e908
BA		 3776 case e1000_ich9lan:
3777 case e1000_ich10lan:
3778 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3779 pba = 14;
3780 ew32(PBA, pba);
3781 fc->high_water = 0x2800;
3782 fc->low_water = fc->high_water - 8;
3783 break;
3784 }
3785 /* fall-through */
d3738bb8 3786 default:
79d4e908
BA		 3787 hwm = min(((pba << 10) * 9 / 10),
3788 ((pba << 10) - adapter->max_frame_size));
d3738bb8 3789
e80bd1d1 3790 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
d3738bb8
BA		 3791 fc->low_water = fc->high_water - 8;
3792 break;
3793 case e1000_pchlan:
e921eb1a 3794 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3795 * loads. If hangs persist, try disabling Tx flow control.
3796 */
3797 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3798 fc->high_water = 0x3500;
e80bd1d1 3799 fc->low_water = 0x1500;
38eb394e
BA		 3800 } else {
3801 fc->high_water = 0x5000;
e80bd1d1 3802 fc->low_water = 0x3000;
38eb394e 3803 }
a305595b 3804 fc->refresh_time = 0x1000;
d3738bb8
BA		 3805 break;
3806 case e1000_pch2lan:
2fbe4526 3807 case e1000_pch_lpt:
d3738bb8 3808 fc->refresh_time = 0x0400;
347b5201
BA		 3809
3810 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
3811 fc->high_water = 0x05C20;
3812 fc->low_water = 0x05048;
3813 fc->pause_time = 0x0650;
3814 break;
828bac87 3815 }
347b5201 3816
ce345e08
BA		 3817 pba = 14;
3818 ew32(PBA, pba);
347b5201
BA		 3819 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
3820 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 3821 break;
38eb394e 3822 }
bc7f75fa 3823
e921eb1a 3824 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3825 * maximum size per Tx descriptor limited only to the transmit
3826 * allocation of the packet buffer minus 96 bytes with an upper
3827 * limit of 24KB due to receive synchronization limitations.
3828 */
3829 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3830 24 << 10);
3831
e921eb1a 3832 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3833 * fit in receive buffer.
828bac87
BA		 3834 */
3835 if (adapter->itr_setting & 0x3) {
79d4e908 3836 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3837 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3838 dev_info(&adapter->pdev->dev,
17e813ec 3839 "Interrupt Throttle Rate off\n");
828bac87 3840 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3841 e1000e_write_itr(adapter, 0);
828bac87
BA		 3842 }
3843 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3844 dev_info(&adapter->pdev->dev,
17e813ec 3845 "Interrupt Throttle Rate on\n");
828bac87
BA		 3846 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3847 adapter->itr = 20000;
22a4cca2 3848 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3849 }
3850 }
3851
bc7f75fa
AK		 3852 /* Allow time for pending master requests to run */
3853 mac->ops.reset_hw(hw);
97ac8cae 3854
e921eb1a 3855 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3856 * that the network interface is in control
3857 */
c43bc57e 3858 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3859 e1000e_get_hw_control(adapter);
97ac8cae 3860
bc7f75fa
AK		 3861 ew32(WUC, 0);
3862
3863 if (mac->ops.init_hw(hw))
44defeb3 3864 e_err("Hardware Error\n");
bc7f75fa
AK		 3865
3866 e1000_update_mng_vlan(adapter);
3867
3868 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3869 ew32(VET, ETH_P_8021Q);
3870
3871 e1000e_reset_adaptive(hw);
31dbe5b4 3872
b67e1913 3873 /* initialize systim and reset the ns time counter */
62d7e3a2 3874 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
b67e1913 3875
d495bcb8
BA		 3876 /* Set EEE advertisement as appropriate */
3877 if (adapter->flags2 & FLAG2_HAS_EEE) {
3878 s32 ret_val;
3879 u16 adv_addr;
3880
3881 switch (hw->phy.type) {
3882 case e1000_phy_82579:
3883 adv_addr = I82579_EEE_ADVERTISEMENT;
3884 break;
3885 case e1000_phy_i217:
3886 adv_addr = I217_EEE_ADVERTISEMENT;
3887 break;
3888 default:
3889 dev_err(&adapter->pdev->dev,
3890 "Invalid PHY type setting EEE advertisement\n");
3891 return;
3892 }
3893
3894 ret_val = hw->phy.ops.acquire(hw);
3895 if (ret_val) {
3896 dev_err(&adapter->pdev->dev,
3897 "EEE advertisement - unable to acquire PHY\n");
3898 return;
3899 }
3900
3901 e1000_write_emi_reg_locked(hw, adv_addr,
3902 hw->dev_spec.ich8lan.eee_disable ?
3903 0 : adapter->eee_advert);
3904
3905 hw->phy.ops.release(hw);
3906 }
3907
31dbe5b4 3908 if (!netif_running(adapter->netdev) &&
28002099 3909 !test_bit(__E1000_TESTING, &adapter->state))
31dbe5b4 3910 e1000_power_down_phy(adapter);
31dbe5b4 3911
bc7f75fa
AK		 3912 e1000_get_phy_info(hw);
3913
918d7197
BA		 3914 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3915 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3916 u16 phy_data = 0;
e921eb1a 3917 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3918 * the return value of this function because there is nothing
ad68076e
BA		 3919 * different we would do if it failed
3920 */
bc7f75fa
AK		 3921 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3922 phy_data &= ~IGP02E1000_PM_SPD;
3923 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3924 }
bc7f75fa
AK		 3925}
3926
3927int e1000e_up(struct e1000_adapter *adapter)
3928{
3929 struct e1000_hw *hw = &adapter->hw;
3930
3931 /* hardware has been reset, we need to reload some things */
3932 e1000_configure(adapter);
3933
3934 clear_bit(__E1000_DOWN, &adapter->state);
3935
4662e82b
BA		 3936 if (adapter->msix_entries)
3937 e1000_configure_msix(adapter);
bc7f75fa
AK		 3938 e1000_irq_enable(adapter);
3939
400484fa 3940 netif_start_queue(adapter->netdev);
4cb9be7a 3941
bc7f75fa 3942 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3943 if (adapter->msix_entries)
3944 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3945 else
3946 ew32(ICS, E1000_ICS_LSC);
3947
bc7f75fa
AK		 3948 return 0;
3949}
3950
713b3c9e
JB		 3951static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3952{
3953 struct e1000_hw *hw = &adapter->hw;
3954
3955 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3956 return;
3957
3958 /* flush pending descriptor writebacks to memory */
3959 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3960 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3961
3962 /* execute the writes immediately */
3963 e1e_flush();
bf03085f 3964
e921eb1a 3965 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 3966 * write is successful
3967 */
3968 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3969 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3970
3971 /* execute the writes immediately */
3972 e1e_flush();
3973}
3974
67fd4fcb
JK		 3975static void e1000e_update_stats(struct e1000_adapter *adapter);
3976
28002099
DE		 3977/**
3978 * e1000e_down - quiesce the device and optionally reset the hardware
3979 * @adapter: board private structure
3980 * @reset: boolean flag to reset the hardware or not
3981 */
3982void e1000e_down(struct e1000_adapter *adapter, bool reset)
bc7f75fa
AK		 3983{
3984 struct net_device *netdev = adapter->netdev;
3985 struct e1000_hw *hw = &adapter->hw;
3986 u32 tctl, rctl;
3987
e921eb1a 3988 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 3989 * reschedule our watchdog timer
3990 */
bc7f75fa
AK		 3991 set_bit(__E1000_DOWN, &adapter->state);
3992
3993 /* disable receives in the hardware */
3994 rctl = er32(RCTL);
7f99ae63
BA		 3995 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3996 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3997 /* flush and sleep below */
3998
4cb9be7a 3999 netif_stop_queue(netdev);
bc7f75fa
AK		 4000
4001 /* disable transmits in the hardware */
4002 tctl = er32(TCTL);
4003 tctl &= ~E1000_TCTL_EN;
4004 ew32(TCTL, tctl);
7f99ae63 4005
bc7f75fa
AK		 4006 /* flush both disables and wait for them to finish */
4007 e1e_flush();
1bba4386 4008 usleep_range(10000, 20000);
bc7f75fa 4009
bc7f75fa
AK		 4010 e1000_irq_disable(adapter);
4011
a3b87a4c
BA		 4012 napi_synchronize(&adapter->napi);
4013
bc7f75fa
AK		 4014 del_timer_sync(&adapter->watchdog_timer);
4015 del_timer_sync(&adapter->phy_info_timer);
4016
bc7f75fa 4017 netif_carrier_off(netdev);
67fd4fcb
JK		 4018
4019 spin_lock(&adapter->stats64_lock);
4020 e1000e_update_stats(adapter);
4021 spin_unlock(&adapter->stats64_lock);
4022
400484fa 4023 e1000e_flush_descriptors(adapter);
55aa6985
BA		 4024 e1000_clean_tx_ring(adapter->tx_ring);
4025 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 4026
bc7f75fa
AK		 4027 adapter->link_speed = 0;
4028 adapter->link_duplex = 0;
4029
da1e2046
BA		 4030 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4031 if ((hw->mac.type >= e1000_pch2lan) &&
4032 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4033 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4034 e_dbg("failed to disable jumbo frame workaround mode\n");
4035
28002099 4036 if (reset && !pci_channel_offline(adapter->pdev))
52cc3086 4037 e1000e_reset(adapter);
bc7f75fa
AK		 4038}
4039
4040void e1000e_reinit_locked(struct e1000_adapter *adapter)
4041{
4042 might_sleep();
4043 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 4044 usleep_range(1000, 2000);
28002099 4045 e1000e_down(adapter, true);
bc7f75fa
AK		 4046 e1000e_up(adapter);
4047 clear_bit(__E1000_RESETTING, &adapter->state);
4048}
4049
b67e1913
BA		 4050/**
4051 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4052 * @cc: cyclecounter structure
4053 **/
4054static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4055{
4056 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4057 cc);
4058 struct e1000_hw *hw = &adapter->hw;
4059 cycle_t systim;
4060
4061 /* latch SYSTIMH on read of SYSTIML */
4062 systim = (cycle_t)er32(SYSTIML);
4063 systim |= (cycle_t)er32(SYSTIMH) << 32;
4064
4065 return systim;
4066}
4067
bc7f75fa
AK		 4068/**
4069 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4070 * @adapter: board private structure to initialize
4071 *
4072 * e1000_sw_init initializes the Adapter private data structure.
4073 * Fields are initialized based on PCI device information and
4074 * OS network device settings (MTU size).
4075 **/
9f9a12f8 4076static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4077{
bc7f75fa
AK		 4078 struct net_device *netdev = adapter->netdev;
4079
4080 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
4081 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 4082 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4083 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4084 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4085 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4086
67fd4fcb
JK		 4087 spin_lock_init(&adapter->stats64_lock);
4088
4662e82b 4089 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4090
4662e82b
BA		 4091 if (e1000_alloc_queues(adapter))
4092 return -ENOMEM;
bc7f75fa 4093
b67e1913
BA		 4094 /* Setup hardware time stamping cyclecounter */
4095 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4096 adapter->cc.read = e1000e_cyclecounter_read;
4097 adapter->cc.mask = CLOCKSOURCE_MASK(64);
4098 adapter->cc.mult = 1;
4099 /* cc.shift set in e1000e_get_base_tininca() */
4100
4101 spin_lock_init(&adapter->systim_lock);
4102 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4103 }
4104
bc7f75fa 4105 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4106 e1000_irq_disable(adapter);
4107
bc7f75fa
AK		 4108 set_bit(__E1000_DOWN, &adapter->state);
4109 return 0;
bc7f75fa
AK		 4110}
4111
f8d59f78
BA		 4112/**
4113 * e1000_intr_msi_test - Interrupt Handler
4114 * @irq: interrupt number
4115 * @data: pointer to a network interface device structure
4116 **/
8bb62869 4117static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
f8d59f78
BA		 4118{
4119 struct net_device *netdev = data;
4120 struct e1000_adapter *adapter = netdev_priv(netdev);
4121 struct e1000_hw *hw = &adapter->hw;
4122 u32 icr = er32(ICR);
4123
3bb99fe2 4124 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4125 if (icr & E1000_ICR_RXSEQ) {
4126 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4127 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4128 * interrupt is handled.
4129 */
f8d59f78
BA		 4130 wmb();
4131 }
4132
4133 return IRQ_HANDLED;
4134}
4135
4136/**
4137 * e1000_test_msi_interrupt - Returns 0 for successful test
4138 * @adapter: board private struct
4139 *
4140 * code flow taken from tg3.c
4141 **/
4142static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4143{
4144 struct net_device *netdev = adapter->netdev;
4145 struct e1000_hw *hw = &adapter->hw;
4146 int err;
4147
4148 /* poll_enable hasn't been called yet, so don't need disable */
4149 /* clear any pending events */
4150 er32(ICR);
4151
4152 /* free the real vector and request a test handler */
4153 e1000_free_irq(adapter);
4662e82b 4154 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4155
4156 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4157 * MSI irq handler will unset this flag
4158 */
f8d59f78
BA		 4159 adapter->flags |= FLAG_MSI_TEST_FAILED;
4160
4161 err = pci_enable_msi(adapter->pdev);
4162 if (err)
4163 goto msi_test_failed;
4164
a0607fd3 4165 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4166 netdev->name, netdev);
4167 if (err) {
4168 pci_disable_msi(adapter->pdev);
4169 goto msi_test_failed;
4170 }
4171
e921eb1a 4172 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4173 * interrupt.
4174 */
f8d59f78
BA		 4175 wmb();
4176
4177 e1000_irq_enable(adapter);
4178
4179 /* fire an unusual interrupt on the test handler */
4180 ew32(ICS, E1000_ICS_RXSEQ);
4181 e1e_flush();
569a3aff 4182 msleep(100);
f8d59f78
BA		 4183
4184 e1000_irq_disable(adapter);
4185
bc76329d 4186 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4187
4188 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4189 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4190 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4191 } else {
068e8a30 4192 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4193 }
f8d59f78
BA		 4194
4195 free_irq(adapter->pdev->irq, netdev);
4196 pci_disable_msi(adapter->pdev);
4197
f8d59f78 4198msi_test_failed:
4662e82b 4199 e1000e_set_interrupt_capability(adapter);
068e8a30 4200 return e1000_request_irq(adapter);
f8d59f78
BA		 4201}
4202
4203/**
4204 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4205 * @adapter: board private struct
4206 *
4207 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4208 **/
4209static int e1000_test_msi(struct e1000_adapter *adapter)
4210{
4211 int err;
4212 u16 pci_cmd;
4213
4214 if (!(adapter->flags & FLAG_MSI_ENABLED))
4215 return 0;
4216
4217 /* disable SERR in case the MSI write causes a master abort */
4218 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4219 if (pci_cmd & PCI_COMMAND_SERR)
4220 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4221 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4222
4223 err = e1000_test_msi_interrupt(adapter);
4224
36f2407f
DN		 4225 /* re-enable SERR */
4226 if (pci_cmd & PCI_COMMAND_SERR) {
4227 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4228 pci_cmd |= PCI_COMMAND_SERR;
4229 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4230 }
f8d59f78 4231
f8d59f78
BA		 4232 return err;
4233}
4234
bc7f75fa
AK		 4235/**
4236 * e1000_open - Called when a network interface is made active
4237 * @netdev: network interface device structure
4238 *
4239 * Returns 0 on success, negative value on failure
4240 *
4241 * The open entry point is called when a network interface is made
4242 * active by the system (IFF_UP). At this point all resources needed
4243 * for transmit and receive operations are allocated, the interrupt
4244 * handler is registered with the OS, the watchdog timer is started,
4245 * and the stack is notified that the interface is ready.
4246 **/
4247static int e1000_open(struct net_device *netdev)
4248{
4249 struct e1000_adapter *adapter = netdev_priv(netdev);
4250 struct e1000_hw *hw = &adapter->hw;
23606cf5 4251 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4252 int err;
4253
4254 /* disallow open during test */
4255 if (test_bit(__E1000_TESTING, &adapter->state))
4256 return -EBUSY;
4257
23606cf5
RW		 4258 pm_runtime_get_sync(&pdev->dev);
4259
9c563d20
JB		 4260 netif_carrier_off(netdev);
4261
bc7f75fa 4262 /* allocate transmit descriptors */
55aa6985 4263 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4264 if (err)
4265 goto err_setup_tx;
4266
4267 /* allocate receive descriptors */
55aa6985 4268 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4269 if (err)
4270 goto err_setup_rx;
4271
e921eb1a 4272 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4273 * interface is now open and reset the part to a known state.
4274 */
4275 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4276 e1000e_get_hw_control(adapter);
11b08be8
BA		 4277 e1000e_reset(adapter);
4278 }
4279
bc7f75fa
AK		 4280 e1000e_power_up_phy(adapter);
4281
4282 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
e5fe2541 4283 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
bc7f75fa
AK		 4284 e1000_update_mng_vlan(adapter);
4285
79d4e908 4286 /* DMA latency requirement to workaround jumbo issue */
3e35d991
BA		 4287 pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4288 PM_QOS_DEFAULT_VALUE);
c128ec29 4289
e921eb1a 4290 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4291 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4292 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4293 * clean_rx handler before we do so.
4294 */
bc7f75fa
AK		 4295 e1000_configure(adapter);
4296
4297 err = e1000_request_irq(adapter);
4298 if (err)
4299 goto err_req_irq;
4300
e921eb1a 4301 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4302 * ignore e1000e MSI messages, which means we need to test our MSI
4303 * interrupt now
4304 */
4662e82b 4305 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4306 err = e1000_test_msi(adapter);
4307 if (err) {
4308 e_err("Interrupt allocation failed\n");
4309 goto err_req_irq;
4310 }
4311 }
4312
bc7f75fa
AK		 4313 /* From here on the code is the same as e1000e_up() */
4314 clear_bit(__E1000_DOWN, &adapter->state);
4315
4316 napi_enable(&adapter->napi);
4317
4318 e1000_irq_enable(adapter);
4319
09357b00 4320 adapter->tx_hang_recheck = false;
4cb9be7a 4321 netif_start_queue(netdev);
d55b53ff 4322
66148bab 4323 hw->mac.get_link_status = true;
23606cf5
RW		 4324 pm_runtime_put(&pdev->dev);
4325
bc7f75fa 4326 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 4327 if (adapter->msix_entries)
4328 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4329 else
4330 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 4331
4332 return 0;
4333
4334err_req_irq:
31dbe5b4 4335 e1000e_release_hw_control(adapter);
bc7f75fa 4336 e1000_power_down_phy(adapter);
55aa6985 4337 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4338err_setup_rx:
55aa6985 4339 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4340err_setup_tx:
4341 e1000e_reset(adapter);
23606cf5 4342 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4343
4344 return err;
4345}
4346
4347/**
4348 * e1000_close - Disables a network interface
4349 * @netdev: network interface device structure
4350 *
4351 * Returns 0, this is not allowed to fail
4352 *
4353 * The close entry point is called when an interface is de-activated
4354 * by the OS. The hardware is still under the drivers control, but
4355 * needs to be disabled. A global MAC reset is issued to stop the
4356 * hardware, and all transmit and receive resources are freed.
4357 **/
4358static int e1000_close(struct net_device *netdev)
4359{
4360 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4361 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4362 int count = E1000_CHECK_RESET_COUNT;
4363
4364 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4365 usleep_range(10000, 20000);
bc7f75fa
AK		 4366
4367 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4368
4369 pm_runtime_get_sync(&pdev->dev);
4370
4371 if (!test_bit(__E1000_DOWN, &adapter->state)) {
28002099 4372 e1000e_down(adapter, true);
23606cf5 4373 e1000_free_irq(adapter);
63eb48f1
DE		 4374
4375 /* Link status message must follow this format */
4376 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
23606cf5 4377 }
a3b87a4c
BA		 4378
4379 napi_disable(&adapter->napi);
4380
55aa6985
BA		 4381 e1000e_free_tx_resources(adapter->tx_ring);
4382 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4383
e921eb1a 4384 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4385 * the same ID is registered on the host OS (let 8021q kill it)
4386 */
e5fe2541 4387 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
80d5c368
PM		 4388 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4389 adapter->mng_vlan_id);
bc7f75fa 4390
e921eb1a 4391 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4392 * interface is now closed
4393 */
31dbe5b4
BA		 4394 if ((adapter->flags & FLAG_HAS_AMT) &&
4395 !test_bit(__E1000_TESTING, &adapter->state))
4396 e1000e_release_hw_control(adapter);
bc7f75fa 4397
3e35d991 4398 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4399
23606cf5
RW		 4400 pm_runtime_put_sync(&pdev->dev);
4401
bc7f75fa
AK		 4402 return 0;
4403}
fc830b78 4404
bc7f75fa
AK		 4405/**
4406 * e1000_set_mac - Change the Ethernet Address of the NIC
4407 * @netdev: network interface device structure
4408 * @p: pointer to an address structure
4409 *
4410 * Returns 0 on success, negative on failure
4411 **/
4412static int e1000_set_mac(struct net_device *netdev, void *p)
4413{
4414 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4415 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4416 struct sockaddr *addr = p;
4417
4418 if (!is_valid_ether_addr(addr->sa_data))
4419 return -EADDRNOTAVAIL;
4420
4421 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4422 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4423
69e1e019 4424 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4425
4426 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4427 /* activate the work around */
4428 e1000e_set_laa_state_82571(&adapter->hw, 1);
4429
e921eb1a 4430 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4431 * between the time RAR[0] gets clobbered and the time it
4432 * gets fixed (in e1000_watchdog), the actual LAA is in one
4433 * of the RARs and no incoming packets directed to this port
4434 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4435 * RAR[14]
4436 */
69e1e019
BA		 4437 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4438 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4439 }
4440
4441 return 0;
4442}
4443
a8f88ff5
JB		 4444/**
4445 * e1000e_update_phy_task - work thread to update phy
4446 * @work: pointer to our work struct
4447 *
4448 * this worker thread exists because we must acquire a
4449 * semaphore to read the phy, which we could msleep while
4450 * waiting for it, and we can't msleep in a timer.
4451 **/
4452static void e1000e_update_phy_task(struct work_struct *work)
4453{
4454 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4455 struct e1000_adapter,
4456 update_phy_task);
a03206ed 4457 struct e1000_hw *hw = &adapter->hw;
615b32af
JB		 4458
4459 if (test_bit(__E1000_DOWN, &adapter->state))
4460 return;
4461
a03206ed
DE		 4462 e1000_get_phy_info(hw);
4463
4464 /* Enable EEE on 82579 after link up */
4465 if (hw->phy.type == e1000_phy_82579)
4466 e1000_set_eee_pchlan(hw);
a8f88ff5
JB		 4467}
4468
e921eb1a
BA		 4469/**
4470 * e1000_update_phy_info - timre call-back to update PHY info
4471 * @data: pointer to adapter cast into an unsigned long
4472 *
ad68076e
BA		 4473 * Need to wait a few seconds after link up to get diagnostic information from
4474 * the phy
e921eb1a 4475 **/
bc7f75fa
AK		 4476static void e1000_update_phy_info(unsigned long data)
4477{
53aa82da 4478 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
615b32af
JB		 4479
4480 if (test_bit(__E1000_DOWN, &adapter->state))
4481 return;
4482
a8f88ff5 4483 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4484}
4485
8c7bbb92
BA		 4486/**
4487 * e1000e_update_phy_stats - Update the PHY statistics counters
4488 * @adapter: board private structure
2b6b168d
BA		 4489 *
4490 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4491 **/
4492static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4493{
4494 struct e1000_hw *hw = &adapter->hw;
4495 s32 ret_val;
4496 u16 phy_data;
4497
4498 ret_val = hw->phy.ops.acquire(hw);
4499 if (ret_val)
4500 return;
4501
e921eb1a 4502 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4503 * If not, set to the page with the PHY status registers.
4504 */
2b6b168d 4505 hw->phy.addr = 1;
8c7bbb92
BA		 4506 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4507 &phy_data);
4508 if (ret_val)
4509 goto release;
2b6b168d
BA		 4510 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4511 ret_val = hw->phy.ops.set_page(hw,
4512 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4513 if (ret_val)
4514 goto release;
4515 }
4516
8c7bbb92 4517 /* Single Collision Count */
2b6b168d
BA		 4518 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4519 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4520 if (!ret_val)
4521 adapter->stats.scc += phy_data;
4522
4523 /* Excessive Collision Count */
2b6b168d
BA		 4524 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4525 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4526 if (!ret_val)
4527 adapter->stats.ecol += phy_data;
4528
4529 /* Multiple Collision Count */
2b6b168d
BA		 4530 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4531 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4532 if (!ret_val)
4533 adapter->stats.mcc += phy_data;
4534
4535 /* Late Collision Count */
2b6b168d
BA		 4536 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4537 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4538 if (!ret_val)
4539 adapter->stats.latecol += phy_data;
4540
4541 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4542 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4543 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4544 if (!ret_val)
4545 hw->mac.collision_delta = phy_data;
4546
4547 /* Defer Count */
2b6b168d
BA		 4548 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4549 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4550 if (!ret_val)
4551 adapter->stats.dc += phy_data;
4552
4553 /* Transmit with no CRS */
2b6b168d
BA		 4554 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4555 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4556 if (!ret_val)
4557 adapter->stats.tncrs += phy_data;
4558
4559release:
4560 hw->phy.ops.release(hw);
4561}
4562
bc7f75fa
AK		 4563/**
4564 * e1000e_update_stats - Update the board statistics counters
4565 * @adapter: board private structure
4566 **/
67fd4fcb 4567static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4568{
7274c20f 4569 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4570 struct e1000_hw *hw = &adapter->hw;
4571 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4572
e921eb1a 4573 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4574 * connection is down.
4575 */
4576 if (adapter->link_speed == 0)
4577 return;
4578 if (pci_channel_offline(pdev))
4579 return;
4580
bc7f75fa
AK		 4581 adapter->stats.crcerrs += er32(CRCERRS);
4582 adapter->stats.gprc += er32(GPRC);
7c25769f 4583 adapter->stats.gorc += er32(GORCL);
e80bd1d1 4584 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4585 adapter->stats.bprc += er32(BPRC);
4586 adapter->stats.mprc += er32(MPRC);
4587 adapter->stats.roc += er32(ROC);
4588
bc7f75fa 4589 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4590
4591 /* Half-duplex statistics */
4592 if (adapter->link_duplex == HALF_DUPLEX) {
4593 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4594 e1000e_update_phy_stats(adapter);
4595 } else {
4596 adapter->stats.scc += er32(SCC);
4597 adapter->stats.ecol += er32(ECOL);
4598 adapter->stats.mcc += er32(MCC);
4599 adapter->stats.latecol += er32(LATECOL);
4600 adapter->stats.dc += er32(DC);
4601
4602 hw->mac.collision_delta = er32(COLC);
4603
4604 if ((hw->mac.type != e1000_82574) &&
4605 (hw->mac.type != e1000_82583))
4606 adapter->stats.tncrs += er32(TNCRS);
4607 }
4608 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4609 }
8c7bbb92 4610
bc7f75fa
AK		 4611 adapter->stats.xonrxc += er32(XONRXC);
4612 adapter->stats.xontxc += er32(XONTXC);
4613 adapter->stats.xoffrxc += er32(XOFFRXC);
4614 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4615 adapter->stats.gptc += er32(GPTC);
7c25769f 4616 adapter->stats.gotc += er32(GOTCL);
e80bd1d1 4617 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4618 adapter->stats.rnbc += er32(RNBC);
4619 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4620
4621 adapter->stats.mptc += er32(MPTC);
4622 adapter->stats.bptc += er32(BPTC);
4623
4624 /* used for adaptive IFS */
4625
4626 hw->mac.tx_packet_delta = er32(TPT);
4627 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4628
4629 adapter->stats.algnerrc += er32(ALGNERRC);
4630 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4631 adapter->stats.cexterr += er32(CEXTERR);
4632 adapter->stats.tsctc += er32(TSCTC);
4633 adapter->stats.tsctfc += er32(TSCTFC);
4634
bc7f75fa 4635 /* Fill out the OS statistics structure */
7274c20f
AK		 4636 netdev->stats.multicast = adapter->stats.mprc;
4637 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4638
4639 /* Rx Errors */
4640
e921eb1a 4641 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4642 * our own version based on RUC and ROC
4643 */
7274c20f 4644 netdev->stats.rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 4645 adapter->stats.crcerrs + adapter->stats.algnerrc +
4646 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
7274c20f 4647 netdev->stats.rx_length_errors = adapter->stats.ruc +
f0ff4398 4648 adapter->stats.roc;
7274c20f
AK		 4649 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4650 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4651 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4652
4653 /* Tx Errors */
f0ff4398 4654 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
7274c20f
AK		 4655 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4656 netdev->stats.tx_window_errors = adapter->stats.latecol;
4657 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4658
4659 /* Tx Dropped needs to be maintained elsewhere */
4660
bc7f75fa
AK		 4661 /* Management Stats */
4662 adapter->stats.mgptc += er32(MGTPTC);
4663 adapter->stats.mgprc += er32(MGTPRC);
4664 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 4665
4666 /* Correctable ECC Errors */
4667 if (hw->mac.type == e1000_pch_lpt) {
4668 u32 pbeccsts = er32(PBECCSTS);
4669 adapter->corr_errors +=
4670 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4671 adapter->uncorr_errors +=
4672 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4673 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4674 }
bc7f75fa
AK		 4675}
4676
7c25769f
BA		 4677/**
4678 * e1000_phy_read_status - Update the PHY register status snapshot
4679 * @adapter: board private structure
4680 **/
4681static void e1000_phy_read_status(struct e1000_adapter *adapter)
4682{
4683 struct e1000_hw *hw = &adapter->hw;
4684 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f 4685
97390ab8
BA		 4686 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
4687 (er32(STATUS) & E1000_STATUS_LU) &&
7c25769f 4688 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4689 int ret_val;
4690
c2ade1a4
BA		 4691 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4692 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4693 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4694 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4695 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4696 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4697 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4698 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
7c25769f 4699 if (ret_val)
44defeb3 4700 e_warn("Error reading PHY register\n");
7c25769f 4701 } else {
e921eb1a 4702 /* Do not read PHY registers if link is not up
7c25769f
BA		 4703 * Set values to typical power-on defaults
4704 */
4705 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4706 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4707 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4708 BMSR_ERCAP);
4709 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4710 ADVERTISE_ALL | ADVERTISE_CSMA);
4711 phy->lpa = 0;
4712 phy->expansion = EXPANSION_ENABLENPAGE;
4713 phy->ctrl1000 = ADVERTISE_1000FULL;
4714 phy->stat1000 = 0;
4715 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4716 }
7c25769f
BA		 4717}
4718
bc7f75fa
AK		 4719static void e1000_print_link_info(struct e1000_adapter *adapter)
4720{
bc7f75fa
AK		 4721 struct e1000_hw *hw = &adapter->hw;
4722 u32 ctrl = er32(CTRL);
4723
8f12fe86 4724 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4725 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4726 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4727 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4728 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4729 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4730 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4731}
4732
0c6bdb30 4733static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4734{
4735 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4736 bool link_active = false;
318a94d6
JK		 4737 s32 ret_val = 0;
4738
e921eb1a 4739 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4740 * Rx sequence error interrupt. get_link_status will stay
4741 * false until the check_for_link establishes link
4742 * for copper adapters ONLY
4743 */
4744 switch (hw->phy.media_type) {
4745 case e1000_media_type_copper:
4746 if (hw->mac.get_link_status) {
4747 ret_val = hw->mac.ops.check_for_link(hw);
4748 link_active = !hw->mac.get_link_status;
4749 } else {
3db1cd5c 4750 link_active = true;
318a94d6
JK		 4751 }
4752 break;
4753 case e1000_media_type_fiber:
4754 ret_val = hw->mac.ops.check_for_link(hw);
4755 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4756 break;
4757 case e1000_media_type_internal_serdes:
4758 ret_val = hw->mac.ops.check_for_link(hw);
4759 link_active = adapter->hw.mac.serdes_has_link;
4760 break;
4761 default:
4762 case e1000_media_type_unknown:
4763 break;
4764 }
4765
4766 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4767 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4768 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4769 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4770 }
4771
4772 return link_active;
4773}
4774
4775static void e1000e_enable_receives(struct e1000_adapter *adapter)
4776{
4777 /* make sure the receive unit is started */
4778 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 4779 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 4780 struct e1000_hw *hw = &adapter->hw;
4781 u32 rctl = er32(RCTL);
4782 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 4783 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 4784 }
4785}
4786
ff10e13c
CW		 4787static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4788{
4789 struct e1000_hw *hw = &adapter->hw;
4790
e921eb1a 4791 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4792 * for hung state and reset, if two calls return true
4793 */
4794 if (e1000_check_phy_82574(hw))
4795 adapter->phy_hang_count++;
4796 else
4797 adapter->phy_hang_count = 0;
4798
4799 if (adapter->phy_hang_count > 1) {
4800 adapter->phy_hang_count = 0;
4801 schedule_work(&adapter->reset_task);
4802 }
4803}
4804
bc7f75fa
AK		 4805/**
4806 * e1000_watchdog - Timer Call-back
4807 * @data: pointer to adapter cast into an unsigned long
4808 **/
4809static void e1000_watchdog(unsigned long data)
4810{
53aa82da 4811 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
bc7f75fa
AK		 4812
4813 /* Do the rest outside of interrupt context */
4814 schedule_work(&adapter->watchdog_task);
4815
4816 /* TODO: make this use queue_delayed_work() */
4817}
4818
4819static void e1000_watchdog_task(struct work_struct *work)
4820{
4821 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4822 struct e1000_adapter,
4823 watchdog_task);
bc7f75fa
AK		 4824 struct net_device *netdev = adapter->netdev;
4825 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4826 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4827 struct e1000_ring *tx_ring = adapter->tx_ring;
4828 struct e1000_hw *hw = &adapter->hw;
4829 u32 link, tctl;
bc7f75fa 4830
615b32af
JB		 4831 if (test_bit(__E1000_DOWN, &adapter->state))
4832 return;
4833
b405e8df 4834 link = e1000e_has_link(adapter);
318a94d6 4835 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4836 /* Cancel scheduled suspend requests. */
4837 pm_runtime_resume(netdev->dev.parent);
4838
318a94d6 4839 e1000e_enable_receives(adapter);
bc7f75fa 4840 goto link_up;
bc7f75fa
AK		 4841 }
4842
4843 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4844 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4845 e1000_update_mng_vlan(adapter);
4846
bc7f75fa
AK		 4847 if (link) {
4848 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4849 bool txb2b = true;
23606cf5
RW		 4850
4851 /* Cancel scheduled suspend requests. */
4852 pm_runtime_resume(netdev->dev.parent);
4853
318a94d6 4854 /* update snapshot of PHY registers on LSC */
7c25769f 4855 e1000_phy_read_status(adapter);
bc7f75fa 4856 mac->ops.get_link_up_info(&adapter->hw,
17e813ec
BA		 4857 &adapter->link_speed,
4858 &adapter->link_duplex);
bc7f75fa 4859 e1000_print_link_info(adapter);
e792cd91
KS		 4860
4861 /* check if SmartSpeed worked */
4862 e1000e_check_downshift(hw);
4863 if (phy->speed_downgraded)
4864 netdev_warn(netdev,
4865 "Link Speed was downgraded by SmartSpeed\n");
4866
e921eb1a 4867 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4868 * if link has autonegotiated at 10/100 half
4869 */
4870 if ((hw->phy.type == e1000_phy_igp_3 ||
4871 hw->phy.type == e1000_phy_bm) &&
138953bb 4872 hw->mac.autoneg &&
f4187b56
BA		 4873 (adapter->link_speed == SPEED_10 ||
4874 adapter->link_speed == SPEED_100) &&
4875 (adapter->link_duplex == HALF_DUPLEX)) {
4876 u16 autoneg_exp;
4877
c2ade1a4 4878 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
f4187b56 4879
c2ade1a4 4880 if (!(autoneg_exp & EXPANSION_NWAY))
ef456f85 4881 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4882 }
4883
f49c57e1 4884 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4885 adapter->tx_timeout_factor = 1;
4886 switch (adapter->link_speed) {
4887 case SPEED_10:
3db1cd5c 4888 txb2b = false;
10f1b492 4889 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4890 break;
4891 case SPEED_100:
3db1cd5c 4892 txb2b = false;
4c86e0b9 4893 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4894 break;
4895 }
4896
e921eb1a 4897 /* workaround: re-program speed mode bit after
ad68076e
BA		 4898 * link-up event
4899 */
bc7f75fa
AK		 4900 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4901 !txb2b) {
4902 u32 tarc0;
e9ec2c0f 4903 tarc0 = er32(TARC(0));
bc7f75fa 4904 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4905 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4906 }
4907
e921eb1a 4908 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4909 * some hardware issues
4910 */
bc7f75fa
AK		 4911 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4912 switch (adapter->link_speed) {
4913 case SPEED_10:
4914 case SPEED_100:
44defeb3 4915 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4916 netdev->features &= ~NETIF_F_TSO;
4917 netdev->features &= ~NETIF_F_TSO6;
4918 break;
4919 case SPEED_1000:
4920 netdev->features |= NETIF_F_TSO;
4921 netdev->features |= NETIF_F_TSO6;
4922 break;
4923 default:
4924 /* oops */
4925 break;
4926 }
4927 }
4928
e921eb1a 4929 /* enable transmits in the hardware, need to do this
ad68076e
BA		 4930 * after setting TARC(0)
4931 */
bc7f75fa
AK		 4932 tctl = er32(TCTL);
4933 tctl |= E1000_TCTL_EN;
4934 ew32(TCTL, tctl);
4935
e921eb1a 4936 /* Perform any post-link-up configuration before
75eb0fad
BA		 4937 * reporting link up.
4938 */
4939 if (phy->ops.cfg_on_link_up)
4940 phy->ops.cfg_on_link_up(hw);
4941
bc7f75fa 4942 netif_carrier_on(netdev);
bc7f75fa
AK		 4943
4944 if (!test_bit(__E1000_DOWN, &adapter->state))
4945 mod_timer(&adapter->phy_info_timer,
4946 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4947 }
4948 } else {
4949 if (netif_carrier_ok(netdev)) {
4950 adapter->link_speed = 0;
4951 adapter->link_duplex = 0;
8f12fe86 4952 /* Link status message must follow this format */
7dbc1672 4953 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 4954 netif_carrier_off(netdev);
bc7f75fa
AK		 4955 if (!test_bit(__E1000_DOWN, &adapter->state))
4956 mod_timer(&adapter->phy_info_timer,
4957 round_jiffies(jiffies + 2 * HZ));
4958
12d43f7d
BA		 4959 /* The link is lost so the controller stops DMA.
4960 * If there is queued Tx work that cannot be done
4961 * or if on an 8000ES2LAN which requires a Rx packet
4962 * buffer work-around on link down event, reset the
4963 * controller to flush the Tx/Rx packet buffers.
4964 * (Do the reset outside of interrupt context).
4965 */
4966 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) ||
4967 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
4968 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 4969 else
4970 pm_schedule_suspend(netdev->dev.parent,
17e813ec 4971 LINK_TIMEOUT);
bc7f75fa
AK		 4972 }
4973 }
4974
4975link_up:
67fd4fcb 4976 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4977 e1000e_update_stats(adapter);
4978
4979 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4980 adapter->tpt_old = adapter->stats.tpt;
4981 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4982 adapter->colc_old = adapter->stats.colc;
4983
7c25769f
BA		 4984 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4985 adapter->gorc_old = adapter->stats.gorc;
4986 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4987 adapter->gotc_old = adapter->stats.gotc;
2084b114 4988 spin_unlock(&adapter->stats64_lock);
bc7f75fa 4989
12d43f7d 4990 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 4991 schedule_work(&adapter->reset_task);
4992 /* return immediately since reset is imminent */
4993 return;
bc7f75fa
AK		 4994 }
4995
12d43f7d
BA		 4996 e1000e_update_adaptive(&adapter->hw);
4997
eab2abf5
JB		 4998 /* Simple mode for Interrupt Throttle Rate (ITR) */
4999 if (adapter->itr_setting == 4) {
e921eb1a 5000 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 5001 * Total asymmetrical Tx or Rx gets ITR=8000;
5002 * everyone else is between 2000-8000.
5003 */
5004 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5005 u32 dif = (adapter->gotc > adapter->gorc ?
17e813ec
BA		 5006 adapter->gotc - adapter->gorc :
5007 adapter->gorc - adapter->gotc) / 10000;
eab2abf5
JB		 5008 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5009
22a4cca2 5010 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 5011 }
5012
ad68076e 5013 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 5014 if (adapter->msix_entries)
5015 ew32(ICS, adapter->rx_ring->ims_val);
5016 else
5017 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 5018
713b3c9e
JB		 5019 /* flush pending descriptors to memory before detecting Tx hang */
5020 e1000e_flush_descriptors(adapter);
5021
bc7f75fa 5022 /* Force detection of hung controller every watchdog period */
3db1cd5c 5023 adapter->detect_tx_hung = true;
bc7f75fa 5024
e921eb1a 5025 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 5026 * reset from the other port. Set the appropriate LAA in RAR[0]
5027 */
bc7f75fa 5028 if (e1000e_get_laa_state_82571(hw))
69e1e019 5029 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 5030
ff10e13c
CW		 5031 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5032 e1000e_check_82574_phy_workaround(adapter);
5033
b67e1913
BA		 5034 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5035 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5036 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5037 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5038 er32(RXSTMPH);
5039 adapter->rx_hwtstamp_cleared++;
5040 } else {
5041 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5042 }
5043 }
5044
bc7f75fa
AK		 5045 /* Reset the timer */
5046 if (!test_bit(__E1000_DOWN, &adapter->state))
5047 mod_timer(&adapter->watchdog_timer,
5048 round_jiffies(jiffies + 2 * HZ));
5049}
5050
5051#define E1000_TX_FLAGS_CSUM 0x00000001
5052#define E1000_TX_FLAGS_VLAN 0x00000002
5053#define E1000_TX_FLAGS_TSO 0x00000004
5054#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5055#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5056#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5057#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5058#define E1000_TX_FLAGS_VLAN_SHIFT 16
5059
55aa6985 5060static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5061{
bc7f75fa
AK		 5062 struct e1000_context_desc *context_desc;
5063 struct e1000_buffer *buffer_info;
5064 unsigned int i;
5065 u32 cmd_length = 0;
70443ae9 5066 u16 ipcse = 0, mss;
bc7f75fa 5067 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 5068
3d5e33c9
BA		 5069 if (!skb_is_gso(skb))
5070 return 0;
bc7f75fa 5071
3d5e33c9 5072 if (skb_header_cloned(skb)) {
90da0669
BA		 5073 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5074
3d5e33c9
BA		 5075 if (err)
5076 return err;
bc7f75fa
AK		 5077 }
5078
3d5e33c9
BA		 5079 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5080 mss = skb_shinfo(skb)->gso_size;
5081 if (skb->protocol == htons(ETH_P_IP)) {
5082 struct iphdr *iph = ip_hdr(skb);
5083 iph->tot_len = 0;
5084 iph->check = 0;
5085 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
f0ff4398 5086 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5087 cmd_length = E1000_TXD_CMD_IP;
5088 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5089 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 5090 ipv6_hdr(skb)->payload_len = 0;
5091 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
f0ff4398
BA		 5092 &ipv6_hdr(skb)->daddr,
5093 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5094 ipcse = 0;
5095 }
5096 ipcss = skb_network_offset(skb);
5097 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5098 tucss = skb_transport_offset(skb);
5099 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5100
5101 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
f0ff4398 5102 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
3d5e33c9
BA		 5103
5104 i = tx_ring->next_to_use;
5105 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5106 buffer_info = &tx_ring->buffer_info[i];
5107
e80bd1d1
BA		 5108 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5109 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5110 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
3d5e33c9
BA		 5111 context_desc->upper_setup.tcp_fields.tucss = tucss;
5112 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5113 context_desc->upper_setup.tcp_fields.tucse = 0;
e80bd1d1 5114 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
3d5e33c9
BA		 5115 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5116 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5117
5118 buffer_info->time_stamp = jiffies;
5119 buffer_info->next_to_watch = i;
5120
5121 i++;
5122 if (i == tx_ring->count)
5123 i = 0;
5124 tx_ring->next_to_use = i;
5125
5126 return 1;
bc7f75fa
AK		 5127}
5128
55aa6985 5129static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5130{
55aa6985 5131 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5132 struct e1000_context_desc *context_desc;
5133 struct e1000_buffer *buffer_info;
5134 unsigned int i;
5135 u8 css;
af807c82 5136 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 5137 __be16 protocol;
bc7f75fa 5138
af807c82
DG		 5139 if (skb->ip_summed != CHECKSUM_PARTIAL)
5140 return 0;
bc7f75fa 5141
5f66f208
AJ		 5142 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5143 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
5144 else
5145 protocol = skb->protocol;
5146
3f518390 5147 switch (protocol) {
09640e63 5148 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5149 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5150 cmd_len |= E1000_TXD_CMD_TCP;
5151 break;
09640e63 5152 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5153 /* XXX not handling all IPV6 headers */
5154 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5155 cmd_len |= E1000_TXD_CMD_TCP;
5156 break;
5157 default:
5158 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5159 e_warn("checksum_partial proto=%x!\n",
5160 be16_to_cpu(protocol));
af807c82 5161 break;
bc7f75fa
AK		 5162 }
5163
0d0b1672 5164 css = skb_checksum_start_offset(skb);
af807c82
DG		 5165
5166 i = tx_ring->next_to_use;
5167 buffer_info = &tx_ring->buffer_info[i];
5168 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5169
5170 context_desc->lower_setup.ip_config = 0;
5171 context_desc->upper_setup.tcp_fields.tucss = css;
f0ff4398 5172 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
af807c82
DG		 5173 context_desc->upper_setup.tcp_fields.tucse = 0;
5174 context_desc->tcp_seg_setup.data = 0;
5175 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5176
5177 buffer_info->time_stamp = jiffies;
5178 buffer_info->next_to_watch = i;
5179
5180 i++;
5181 if (i == tx_ring->count)
5182 i = 0;
5183 tx_ring->next_to_use = i;
5184
5185 return 1;
bc7f75fa
AK		 5186}
5187
55aa6985
BA		 5188static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5189 unsigned int first, unsigned int max_per_txd,
d821a4c4 5190 unsigned int nr_frags)
bc7f75fa 5191{
55aa6985 5192 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5193 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5194 struct e1000_buffer *buffer_info;
8ddc951c 5195 unsigned int len = skb_headlen(skb);
03b1320d 5196 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5197 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5198
5199 i = tx_ring->next_to_use;
5200
5201 while (len) {
1b7719c4 5202 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5203 size = min(len, max_per_txd);
5204
bc7f75fa 5205 buffer_info->length = size;
bc7f75fa 5206 buffer_info->time_stamp = jiffies;
bc7f75fa 5207 buffer_info->next_to_watch = i;
0be3f55f
NN		 5208 buffer_info->dma = dma_map_single(&pdev->dev,
5209 skb->data + offset,
af667a29 5210 size, DMA_TO_DEVICE);
03b1320d 5211 buffer_info->mapped_as_page = false;
0be3f55f 5212 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5213 goto dma_error;
bc7f75fa
AK		 5214
5215 len -= size;
5216 offset += size;
03b1320d 5217 count++;
1b7719c4
AD		 5218
5219 if (len) {
5220 i++;
5221 if (i == tx_ring->count)
5222 i = 0;
5223 }
bc7f75fa
AK		 5224 }
5225
5226 for (f = 0; f < nr_frags; f++) {
9e903e08 5227 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5228
5229 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5230 len = skb_frag_size(frag);
877749bf 5231 offset = 0;
bc7f75fa
AK		 5232
5233 while (len) {
1b7719c4
AD		 5234 i++;
5235 if (i == tx_ring->count)
5236 i = 0;
5237
bc7f75fa
AK		 5238 buffer_info = &tx_ring->buffer_info[i];
5239 size = min(len, max_per_txd);
bc7f75fa
AK		 5240
5241 buffer_info->length = size;
5242 buffer_info->time_stamp = jiffies;
bc7f75fa 5243 buffer_info->next_to_watch = i;
877749bf 5244 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
17e813ec
BA		 5245 offset, size,
5246 DMA_TO_DEVICE);
03b1320d 5247 buffer_info->mapped_as_page = true;
0be3f55f 5248 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5249 goto dma_error;
bc7f75fa
AK		 5250
5251 len -= size;
5252 offset += size;
5253 count++;
bc7f75fa
AK		 5254 }
5255 }
5256
af667a29 5257 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5258 /* multiply data chunks by size of headers */
5259 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5260
bc7f75fa 5261 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5262 tx_ring->buffer_info[i].segs = segs;
5263 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5264 tx_ring->buffer_info[first].next_to_watch = i;
5265
5266 return count;
03b1320d
AD		 5267
5268dma_error:
af667a29 5269 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5270 buffer_info->dma = 0;
c1fa347f 5271 if (count)
03b1320d 5272 count--;
c1fa347f
RK		 5273
5274 while (count--) {
af667a29 5275 if (i == 0)
03b1320d 5276 i += tx_ring->count;
c1fa347f 5277 i--;
03b1320d 5278 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5279 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5280 }
5281
5282 return 0;
bc7f75fa
AK		 5283}
5284
55aa6985 5285static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5286{
55aa6985 5287 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5288 struct e1000_tx_desc *tx_desc = NULL;
5289 struct e1000_buffer *buffer_info;
5290 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5291 unsigned int i;
5292
5293 if (tx_flags & E1000_TX_FLAGS_TSO) {
5294 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
f0ff4398 5295 E1000_TXD_CMD_TSE;
bc7f75fa
AK		 5296 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5297
5298 if (tx_flags & E1000_TX_FLAGS_IPV4)
5299 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5300 }
5301
5302 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5303 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5304 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5305 }
5306
5307 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5308 txd_lower |= E1000_TXD_CMD_VLE;
5309 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5310 }
5311
943146de
BG		 5312 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5313 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5314
b67e1913
BA		 5315 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5316 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5317 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5318 }
5319
bc7f75fa
AK		 5320 i = tx_ring->next_to_use;
5321
36b973df 5322 do {
bc7f75fa
AK		 5323 buffer_info = &tx_ring->buffer_info[i];
5324 tx_desc = E1000_TX_DESC(*tx_ring, i);
5325 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
f0ff4398
BA		 5326 tx_desc->lower.data = cpu_to_le32(txd_lower |
5327 buffer_info->length);
bc7f75fa
AK		 5328 tx_desc->upper.data = cpu_to_le32(txd_upper);
5329
5330 i++;
5331 if (i == tx_ring->count)
5332 i = 0;
36b973df 5333 } while (--count > 0);
bc7f75fa
AK		 5334
5335 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5336
943146de
BG		 5337 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5338 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5339 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5340
e921eb1a 5341 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5342 * know there are new descriptors to fetch. (Only
5343 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5344 * such as IA-64).
5345 */
bc7f75fa
AK		 5346 wmb();
5347
5348 tx_ring->next_to_use = i;
c6e7f51e
BA		 5349
5350 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 5351 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 5352 else
c5083cf6 5353 writel(i, tx_ring->tail);
c6e7f51e 5354
e921eb1a 5355 /* we need this if more than one processor can write to our tail
ad68076e
BA		 5356 * at a time, it synchronizes IO on IA64/Altix systems
5357 */
bc7f75fa
AK		 5358 mmiowb();
5359}
5360
5361#define MINIMUM_DHCP_PACKET_SIZE 282
5362static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5363 struct sk_buff *skb)
5364{
e80bd1d1 5365 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 5366 u16 length, offset;
5367
d60923c4
BA		 5368 if (vlan_tx_tag_present(skb) &&
5369 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5370 (adapter->hw.mng_cookie.status &
5371 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5372 return 0;
bc7f75fa
AK		 5373
5374 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5375 return 0;
5376
53aa82da 5377 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
bc7f75fa
AK		 5378 return 0;
5379
5380 {
362e20ca 5381 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
bc7f75fa
AK		 5382 struct udphdr *udp;
5383
5384 if (ip->protocol != IPPROTO_UDP)
5385 return 0;
5386
5387 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5388 if (ntohs(udp->dest) != 67)
5389 return 0;
5390
5391 offset = (u8 *)udp + 8 - skb->data;
5392 length = skb->len - offset;
5393 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5394 }
5395
5396 return 0;
5397}
5398
55aa6985 5399static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5400{
55aa6985 5401 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5402
55aa6985 5403 netif_stop_queue(adapter->netdev);
e921eb1a 5404 /* Herbert's original patch had:
bc7f75fa 5405 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5406 * but since that doesn't exist yet, just open code it.
5407 */
bc7f75fa
AK		 5408 smp_mb();
5409
e921eb1a 5410 /* We need to check again in a case another CPU has just
ad68076e
BA		 5411 * made room available.
5412 */
55aa6985 5413 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5414 return -EBUSY;
5415
5416 /* A reprieve! */
55aa6985 5417 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5418 ++adapter->restart_queue;
5419 return 0;
5420}
5421
55aa6985 5422static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5423{
d821a4c4
BA		 5424 BUG_ON(size > tx_ring->count);
5425
55aa6985 5426 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5427 return 0;
55aa6985 5428 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5429}
5430
3b29a56d
SH		 5431static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5432 struct net_device *netdev)
bc7f75fa
AK		 5433{
5434 struct e1000_adapter *adapter = netdev_priv(netdev);
5435 struct e1000_ring *tx_ring = adapter->tx_ring;
5436 unsigned int first;
bc7f75fa 5437 unsigned int tx_flags = 0;
e743d313 5438 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5439 unsigned int nr_frags;
5440 unsigned int mss;
bc7f75fa
AK		 5441 int count = 0;
5442 int tso;
5443 unsigned int f;
bc7f75fa
AK		 5444
5445 if (test_bit(__E1000_DOWN, &adapter->state)) {
5446 dev_kfree_skb_any(skb);
5447 return NETDEV_TX_OK;
5448 }
5449
5450 if (skb->len <= 0) {
5451 dev_kfree_skb_any(skb);
5452 return NETDEV_TX_OK;
5453 }
5454
e921eb1a 5455 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5456 * pad skb in order to meet this minimum size requirement
5457 */
5458 if (unlikely(skb->len < 17)) {
5459 if (skb_pad(skb, 17 - skb->len))
5460 return NETDEV_TX_OK;
5461 skb->len = 17;
5462 skb_set_tail_pointer(skb, 17);
5463 }
5464
bc7f75fa 5465 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5466 if (mss) {
5467 u8 hdr_len;
bc7f75fa 5468
e921eb1a 5469 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5470 * points to just header, pull a few bytes of payload from
5471 * frags into skb->data
5472 */
bc7f75fa 5473 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5474 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5475 * avoiding it could save a lot of cycles
5476 */
4e6c709c 5477 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5478 unsigned int pull_size;
5479
a2a5b323 5480 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5481 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5482 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5483 dev_kfree_skb_any(skb);
5484 return NETDEV_TX_OK;
5485 }
e743d313 5486 len = skb_headlen(skb);
bc7f75fa
AK		 5487 }
5488 }
5489
5490 /* reserve a descriptor for the offload context */
5491 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5492 count++;
5493 count++;
5494
d821a4c4 5495 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5496
5497 nr_frags = skb_shinfo(skb)->nr_frags;
5498 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5499 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5500 adapter->tx_fifo_limit);
bc7f75fa
AK		 5501
5502 if (adapter->hw.mac.tx_pkt_filtering)
5503 e1000_transfer_dhcp_info(adapter, skb);
5504
e921eb1a 5505 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5506 * head, otherwise try next time
5507 */
55aa6985 5508 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5509 return NETDEV_TX_BUSY;
bc7f75fa 5510
eab6d18d 5511 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5512 tx_flags |= E1000_TX_FLAGS_VLAN;
5513 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5514 }
5515
5516 first = tx_ring->next_to_use;
5517
55aa6985 5518 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5519 if (tso < 0) {
5520 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5521 return NETDEV_TX_OK;
5522 }
5523
5524 if (tso)
5525 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5526 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5527 tx_flags |= E1000_TX_FLAGS_CSUM;
5528
e921eb1a 5529 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5530 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5531 * no longer assume, we must.
5532 */
bc7f75fa
AK		 5533 if (skb->protocol == htons(ETH_P_IP))
5534 tx_flags |= E1000_TX_FLAGS_IPV4;
5535
943146de
BG		 5536 if (unlikely(skb->no_fcs))
5537 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5538
25985edc 5539 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5540 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5541 nr_frags);
1b7719c4 5542 if (count) {
b67e1913
BA		 5543 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5544 !adapter->tx_hwtstamp_skb)) {
5545 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5546 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5547 adapter->tx_hwtstamp_skb = skb_get(skb);
5548 schedule_work(&adapter->tx_hwtstamp_work);
5549 } else {
5550 skb_tx_timestamp(skb);
5551 }
80be3129 5552
3f0cfa3b 5553 netdev_sent_queue(netdev, skb->len);
55aa6985 5554 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5555 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5556 e1000_maybe_stop_tx(tx_ring,
5557 (MAX_SKB_FRAGS *
5558 DIV_ROUND_UP(PAGE_SIZE,
5559 adapter->tx_fifo_limit) + 2));
1b7719c4 5560 } else {
bc7f75fa 5561 dev_kfree_skb_any(skb);
1b7719c4
AD		 5562 tx_ring->buffer_info[first].time_stamp = 0;
5563 tx_ring->next_to_use = first;
bc7f75fa
AK		 5564 }
5565
bc7f75fa
AK		 5566 return NETDEV_TX_OK;
5567}
5568
5569/**
5570 * e1000_tx_timeout - Respond to a Tx Hang
5571 * @netdev: network interface device structure
5572 **/
5573static void e1000_tx_timeout(struct net_device *netdev)
5574{
5575 struct e1000_adapter *adapter = netdev_priv(netdev);
5576
5577 /* Do the reset outside of interrupt context */
5578 adapter->tx_timeout_count++;
5579 schedule_work(&adapter->reset_task);
5580}
5581
5582static void e1000_reset_task(struct work_struct *work)
5583{
5584 struct e1000_adapter *adapter;
5585 adapter = container_of(work, struct e1000_adapter, reset_task);
5586
615b32af
JB		 5587 /* don't run the task if already down */
5588 if (test_bit(__E1000_DOWN, &adapter->state))
5589 return;
5590
12d43f7d 5591 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5592 e1000e_dump(adapter);
12d43f7d 5593 e_err("Reset adapter unexpectedly\n");
affa9dfb 5594 }
bc7f75fa
AK		 5595 e1000e_reinit_locked(adapter);
5596}
5597
5598/**
67fd4fcb 5599 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5600 * @netdev: network interface device structure
67fd4fcb 5601 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5602 *
5603 * Returns the address of the device statistics structure.
bc7f75fa 5604 **/
67fd4fcb 5605struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
66501f56 5606 struct rtnl_link_stats64 *stats)
bc7f75fa 5607{
67fd4fcb
JK		 5608 struct e1000_adapter *adapter = netdev_priv(netdev);
5609
5610 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5611 spin_lock(&adapter->stats64_lock);
5612 e1000e_update_stats(adapter);
5613 /* Fill out the OS statistics structure */
5614 stats->rx_bytes = adapter->stats.gorc;
5615 stats->rx_packets = adapter->stats.gprc;
5616 stats->tx_bytes = adapter->stats.gotc;
5617 stats->tx_packets = adapter->stats.gptc;
5618 stats->multicast = adapter->stats.mprc;
5619 stats->collisions = adapter->stats.colc;
5620
5621 /* Rx Errors */
5622
e921eb1a 5623 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5624 * our own version based on RUC and ROC
5625 */
5626 stats->rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 5627 adapter->stats.crcerrs + adapter->stats.algnerrc +
5628 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5629 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
67fd4fcb
JK		 5630 stats->rx_crc_errors = adapter->stats.crcerrs;
5631 stats->rx_frame_errors = adapter->stats.algnerrc;
5632 stats->rx_missed_errors = adapter->stats.mpc;
5633
5634 /* Tx Errors */
f0ff4398 5635 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
67fd4fcb
JK		 5636 stats->tx_aborted_errors = adapter->stats.ecol;
5637 stats->tx_window_errors = adapter->stats.latecol;
5638 stats->tx_carrier_errors = adapter->stats.tncrs;
5639
5640 /* Tx Dropped needs to be maintained elsewhere */
5641
5642 spin_unlock(&adapter->stats64_lock);
5643 return stats;
bc7f75fa
AK		 5644}
5645
5646/**
5647 * e1000_change_mtu - Change the Maximum Transfer Unit
5648 * @netdev: network interface device structure
5649 * @new_mtu: new value for maximum frame size
5650 *
5651 * Returns 0 on success, negative on failure
5652 **/
5653static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5654{
5655 struct e1000_adapter *adapter = netdev_priv(netdev);
5656 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5657
2adc55c9 5658 /* Jumbo frame support */
2e1706f2
BA		 5659 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5660 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5661 e_err("Jumbo Frames not supported.\n");
5662 return -EINVAL;
bc7f75fa
AK		 5663 }
5664
2adc55c9
BA		 5665 /* Supported frame sizes */
5666 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5667 (max_frame > adapter->max_hw_frame_size)) {
5668 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5669 return -EINVAL;
5670 }
5671
2fbe4526
BA		 5672 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5673 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5674 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5675 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5676 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5677 return -EINVAL;
5678 }
5679
bc7f75fa 5680 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5681 usleep_range(1000, 2000);
610c9928 5682 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5683 adapter->max_frame_size = max_frame;
610c9928
BA		 5684 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5685 netdev->mtu = new_mtu;
63eb48f1
DE		 5686
5687 pm_runtime_get_sync(netdev->dev.parent);
5688
bc7f75fa 5689 if (netif_running(netdev))
28002099 5690 e1000e_down(adapter, true);
bc7f75fa 5691
e921eb1a 5692 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5693 * means we reserve 2 more, this pushes us to allocate from the next
5694 * larger slab size.
ad68076e 5695 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5696 * However with the new *_jumbo_rx* routines, jumbo receives will use
5697 * fragmented skbs
ad68076e 5698 */
bc7f75fa 5699
9926146b 5700 if (max_frame <= 2048)
bc7f75fa
AK		 5701 adapter->rx_buffer_len = 2048;
5702 else
5703 adapter->rx_buffer_len = 4096;
5704
5705 /* adjust allocation if LPE protects us, and we aren't using SBP */
5706 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
17e813ec 5707 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
bc7f75fa 5708 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
17e813ec 5709 + ETH_FCS_LEN;
bc7f75fa 5710
bc7f75fa
AK		 5711 if (netif_running(netdev))
5712 e1000e_up(adapter);
5713 else
5714 e1000e_reset(adapter);
5715
63eb48f1
DE		 5716 pm_runtime_put_sync(netdev->dev.parent);
5717
bc7f75fa
AK		 5718 clear_bit(__E1000_RESETTING, &adapter->state);
5719
5720 return 0;
5721}
5722
5723static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5724 int cmd)
5725{
5726 struct e1000_adapter *adapter = netdev_priv(netdev);
5727 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5728
318a94d6 5729 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5730 return -EOPNOTSUPP;
5731
5732 switch (cmd) {
5733 case SIOCGMIIPHY:
5734 data->phy_id = adapter->hw.phy.addr;
5735 break;
5736 case SIOCGMIIREG:
b16a002e
BA		 5737 e1000_phy_read_status(adapter);
5738
7c25769f
BA		 5739 switch (data->reg_num & 0x1F) {
5740 case MII_BMCR:
5741 data->val_out = adapter->phy_regs.bmcr;
5742 break;
5743 case MII_BMSR:
5744 data->val_out = adapter->phy_regs.bmsr;
5745 break;
5746 case MII_PHYSID1:
5747 data->val_out = (adapter->hw.phy.id >> 16);
5748 break;
5749 case MII_PHYSID2:
5750 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5751 break;
5752 case MII_ADVERTISE:
5753 data->val_out = adapter->phy_regs.advertise;
5754 break;
5755 case MII_LPA:
5756 data->val_out = adapter->phy_regs.lpa;
5757 break;
5758 case MII_EXPANSION:
5759 data->val_out = adapter->phy_regs.expansion;
5760 break;
5761 case MII_CTRL1000:
5762 data->val_out = adapter->phy_regs.ctrl1000;
5763 break;
5764 case MII_STAT1000:
5765 data->val_out = adapter->phy_regs.stat1000;
5766 break;
5767 case MII_ESTATUS:
5768 data->val_out = adapter->phy_regs.estatus;
5769 break;
5770 default:
bc7f75fa
AK		 5771 return -EIO;
5772 }
bc7f75fa
AK		 5773 break;
5774 case SIOCSMIIREG:
5775 default:
5776 return -EOPNOTSUPP;
5777 }
5778 return 0;
5779}
5780
b67e1913
BA		 5781/**
5782 * e1000e_hwtstamp_ioctl - control hardware time stamping
5783 * @netdev: network interface device structure
5784 * @ifreq: interface request
5785 *
5786 * Outgoing time stamping can be enabled and disabled. Play nice and
5787 * disable it when requested, although it shouldn't cause any overhead
5788 * when no packet needs it. At most one packet in the queue may be
5789 * marked for time stamping, otherwise it would be impossible to tell
5790 * for sure to which packet the hardware time stamp belongs.
5791 *
5792 * Incoming time stamping has to be configured via the hardware filters.
5793 * Not all combinations are supported, in particular event type has to be
5794 * specified. Matching the kind of event packet is not supported, with the
5795 * exception of "all V2 events regardless of level 2 or 4".
5796 **/
4e8cff64 5797static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
b67e1913
BA		 5798{
5799 struct e1000_adapter *adapter = netdev_priv(netdev);
5800 struct hwtstamp_config config;
5801 int ret_val;
5802
5803 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5804 return -EFAULT;
5805
62d7e3a2 5806 ret_val = e1000e_config_hwtstamp(adapter, &config);
b67e1913
BA		 5807 if (ret_val)
5808 return ret_val;
5809
d89777bf
BA		 5810 switch (config.rx_filter) {
5811 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5812 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5813 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5814 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5815 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5816 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5817 /* With V2 type filters which specify a Sync or Delay Request,
5818 * Path Delay Request/Response messages are also time stamped
5819 * by hardware so notify the caller the requested packets plus
5820 * some others are time stamped.
5821 */
5822 config.rx_filter = HWTSTAMP_FILTER_SOME;
5823 break;
5824 default:
5825 break;
5826 }
5827
b67e1913
BA		 5828 return copy_to_user(ifr->ifr_data, &config,
5829 sizeof(config)) ? -EFAULT : 0;
5830}
5831
4e8cff64
BH		 5832static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
5833{
5834 struct e1000_adapter *adapter = netdev_priv(netdev);
5835
5836 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
5837 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
5838}
5839
bc7f75fa
AK		 5840static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5841{
5842 switch (cmd) {
5843 case SIOCGMIIPHY:
5844 case SIOCGMIIREG:
5845 case SIOCSMIIREG:
5846 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913 5847 case SIOCSHWTSTAMP:
4e8cff64
BH		 5848 return e1000e_hwtstamp_set(netdev, ifr);
5849 case SIOCGHWTSTAMP:
5850 return e1000e_hwtstamp_get(netdev, ifr);
bc7f75fa
AK		 5851 default:
5852 return -EOPNOTSUPP;
5853 }
5854}
5855
a4f58f54
BA		 5856static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5857{
5858 struct e1000_hw *hw = &adapter->hw;
74f350ee 5859 u32 i, mac_reg, wuc;
2b6b168d 5860 u16 phy_reg, wuc_enable;
70806a7f 5861 int retval;
a4f58f54
BA		 5862
5863 /* copy MAC RARs to PHY RARs */
d3738bb8 5864 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5865
2b6b168d
BA		 5866 retval = hw->phy.ops.acquire(hw);
5867 if (retval) {
5868 e_err("Could not acquire PHY\n");
5869 return retval;
5870 }
5871
5872 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5873 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5874 if (retval)
75ce1532 5875 goto release;
2b6b168d
BA		 5876
5877 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5878 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5879 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5880 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5881 (u16)(mac_reg & 0xFFFF));
5882 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5883 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5884 }
5885
5886 /* configure PHY Rx Control register */
2b6b168d 5887 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5888 mac_reg = er32(RCTL);
5889 if (mac_reg & E1000_RCTL_UPE)
5890 phy_reg |= BM_RCTL_UPE;
5891 if (mac_reg & E1000_RCTL_MPE)
5892 phy_reg |= BM_RCTL_MPE;
5893 phy_reg &= ~(BM_RCTL_MO_MASK);
5894 if (mac_reg & E1000_RCTL_MO_3)
5895 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
17e813ec 5896 << BM_RCTL_MO_SHIFT);
a4f58f54
BA		 5897 if (mac_reg & E1000_RCTL_BAM)
5898 phy_reg |= BM_RCTL_BAM;
5899 if (mac_reg & E1000_RCTL_PMCF)
5900 phy_reg |= BM_RCTL_PMCF;
5901 mac_reg = er32(CTRL);
5902 if (mac_reg & E1000_CTRL_RFCE)
5903 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5904 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54 5905
74f350ee
DE		 5906 wuc = E1000_WUC_PME_EN;
5907 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
5908 wuc |= E1000_WUC_APME;
5909
a4f58f54
BA		 5910 /* enable PHY wakeup in MAC register */
5911 ew32(WUFC, wufc);
74f350ee
DE		 5912 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
5913 E1000_WUC_PME_STATUS | wuc));
a4f58f54
BA		 5914
5915 /* configure and enable PHY wakeup in PHY registers */
2b6b168d 5916 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
74f350ee 5917 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
a4f58f54
BA		 5918
5919 /* activate PHY wakeup */
2b6b168d
BA		 5920 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5921 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5922 if (retval)
5923 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5924release:
94d8186a 5925 hw->phy.ops.release(hw);
a4f58f54
BA		 5926
5927 return retval;
5928}
5929
28002099 5930static int e1000e_pm_freeze(struct device *dev)
bc7f75fa 5931{
28002099 5932 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
bc7f75fa 5933 struct e1000_adapter *adapter = netdev_priv(netdev);
bc7f75fa
AK		 5934
5935 netif_device_detach(netdev);
5936
5937 if (netif_running(netdev)) {
bb9e44d0
BA		 5938 int count = E1000_CHECK_RESET_COUNT;
5939
5940 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5941 usleep_range(10000, 20000);
5942
bc7f75fa 5943 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
28002099
DE		 5944
5945 /* Quiesce the device without resetting the hardware */
5946 e1000e_down(adapter, false);
bc7f75fa
AK		 5947 e1000_free_irq(adapter);
5948 }
4662e82b 5949 e1000e_reset_interrupt_capability(adapter);
bc7f75fa 5950
28002099
DE		 5951 /* Allow time for pending master requests to run */
5952 e1000e_disable_pcie_master(&adapter->hw);
5953
5954 return 0;
5955}
5956
5957static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
5958{
5959 struct net_device *netdev = pci_get_drvdata(pdev);
5960 struct e1000_adapter *adapter = netdev_priv(netdev);
5961 struct e1000_hw *hw = &adapter->hw;
5962 u32 ctrl, ctrl_ext, rctl, status;
5963 /* Runtime suspend should only enable wakeup for link changes */
5964 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
5965 int retval = 0;
5966
bc7f75fa
AK		 5967 status = er32(STATUS);
5968 if (status & E1000_STATUS_LU)
5969 wufc &= ~E1000_WUFC_LNKC;
5970
5971 if (wufc) {
5972 e1000_setup_rctl(adapter);
ef9b965a 5973 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5974
5975 /* turn on all-multi mode if wake on multicast is enabled */
5976 if (wufc & E1000_WUFC_MC) {
5977 rctl = er32(RCTL);
5978 rctl |= E1000_RCTL_MPE;
5979 ew32(RCTL, rctl);
5980 }
5981
5982 ctrl = er32(CTRL);
a4f58f54
BA		 5983 ctrl |= E1000_CTRL_ADVD3WUC;
5984 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5985 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5986 ew32(CTRL, ctrl);
5987
318a94d6
JK		 5988 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5989 adapter->hw.phy.media_type ==
5990 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5991 /* keep the laser running in D3 */
5992 ctrl_ext = er32(CTRL_EXT);
93a23f48 5993 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5994 ew32(CTRL_EXT, ctrl_ext);
5995 }
5996
63eb48f1
DE		 5997 if (!runtime)
5998 e1000e_power_up_phy(adapter);
5999
97ac8cae 6000 if (adapter->flags & FLAG_IS_ICH)
99730e4c 6001 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 6002
82776a4b 6003 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 6004 /* enable wakeup by the PHY */
6005 retval = e1000_init_phy_wakeup(adapter, wufc);
6006 if (retval)
6007 return retval;
6008 } else {
6009 /* enable wakeup by the MAC */
6010 ew32(WUFC, wufc);
6011 ew32(WUC, E1000_WUC_PME_EN);
6012 }
bc7f75fa
AK		 6013 } else {
6014 ew32(WUC, 0);
6015 ew32(WUFC, 0);
28002099
DE		 6016
6017 e1000_power_down_phy(adapter);
bc7f75fa
AK		 6018 }
6019
74f350ee 6020 if (adapter->hw.phy.type == e1000_phy_igp_3) {
bc7f75fa 6021 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
74f350ee
DE		 6022 } else if (hw->mac.type == e1000_pch_lpt) {
6023 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6024 /* ULP does not support wake from unicast, multicast
6025 * or broadcast.
6026 */
6027 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6028
6029 if (retval)
6030 return retval;
6031 }
6032
bc7f75fa 6033
e921eb1a 6034 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6035 * would have already happened in close and is redundant.
6036 */
31dbe5b4 6037 e1000e_release_hw_control(adapter);
bc7f75fa 6038
24b41c97
DN		 6039 pci_clear_master(pdev);
6040
e921eb1a 6041 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 6042 * correctable error when the MAC transitions from D0 to D3. To
6043 * prevent this we need to mask off the correctable errors on the
6044 * downstream port of the pci-e switch.
e8c254c5
LZ		 6045 *
6046 * We don't have the associated upstream bridge while assigning
6047 * the PCI device into guest. For example, the KVM on power is
6048 * one of the cases.
005cbdfc
AD		 6049 */
6050 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6051 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 6052 u16 devctl;
6053
e8c254c5
LZ		 6054 if (!us_dev)
6055 return 0;
6056
f8c0fcac
JL		 6057 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6058 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6059 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6060
66148bab
KK		 6061 pci_save_state(pdev);
6062 pci_prepare_to_sleep(pdev);
005cbdfc 6063
f8c0fcac 6064 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6065 }
66148bab
KK		 6066
6067 return 0;
bc7f75fa
AK		 6068}
6069
13129d9b
CW		 6070/**
6071 * e1000e_disable_aspm - Disable ASPM states
6072 * @pdev: pointer to PCI device struct
6073 * @state: bit-mask of ASPM states to disable
6074 *
6075 * Some devices *must* have certain ASPM states disabled per hardware errata.
6076 **/
6077static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c 6078{
13129d9b
CW		 6079 struct pci_dev *parent = pdev->bus->self;
6080 u16 aspm_dis_mask = 0;
6081 u16 pdev_aspmc, parent_aspmc;
6082
6083 switch (state) {
6084 case PCIE_LINK_STATE_L0S:
6085 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6086 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6087 /* fall-through - can't have L1 without L0s */
6088 case PCIE_LINK_STATE_L1:
6089 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6090 break;
6091 default:
6092 return;
6093 }
6094
6095 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6096 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6097
6098 if (parent) {
6099 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6100 &parent_aspmc);
6101 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6102 }
6103
6104 /* Nothing to do if the ASPM states to be disabled already are */
6105 if (!(pdev_aspmc & aspm_dis_mask) &&
6106 (!parent || !(parent_aspmc & aspm_dis_mask)))
6107 return;
6108
6109 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6110 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6111 "L0s" : "",
6112 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6113 "L1" : "");
6114
6115#ifdef CONFIG_PCIEASPM
9f728f53 6116 pci_disable_link_state_locked(pdev, state);
ffe0b2ff 6117
13129d9b
CW		 6118 /* Double-check ASPM control. If not disabled by the above, the
6119 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6120 * not enabled); override by writing PCI config space directly.
6121 */
6122 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6123 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6124
6125 if (!(aspm_dis_mask & pdev_aspmc))
6126 return;
6127#endif
ffe0b2ff 6128
e921eb1a 6129 /* Both device and parent should have the same ASPM setting.
6f461f6c 6130 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6131 */
13129d9b 6132 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6f461f6c 6133
13129d9b
CW		 6134 if (parent)
6135 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6136 aspm_dis_mask);
1eae4eb2
AK		 6137}
6138
aa338601 6139#ifdef CONFIG_PM
23606cf5 6140static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6141{
6142 struct net_device *netdev = pci_get_drvdata(pdev);
6143 struct e1000_adapter *adapter = netdev_priv(netdev);
6144 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6145 u16 aspm_disable_flag = 0;
bc7f75fa 6146
78cd29d5
BA		 6147 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6148 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6149 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6150 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6151 if (aspm_disable_flag)
6152 e1000e_disable_aspm(pdev, aspm_disable_flag);
6153
66148bab 6154 pci_set_master(pdev);
6e4f6f6b 6155
2fbe4526 6156 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6157 e1000_resume_workarounds_pchlan(&adapter->hw);
6158
bc7f75fa 6159 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6160
6161 /* report the system wakeup cause from S3/S4 */
6162 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6163 u16 phy_data;
6164
6165 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6166 if (phy_data) {
6167 e_info("PHY Wakeup cause - %s\n",
17e813ec
BA		 6168 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6169 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6170 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6171 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6172 phy_data & E1000_WUS_LNKC ?
6173 "Link Status Change" : "other");
a4f58f54
BA		 6174 }
6175 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6176 } else {
6177 u32 wus = er32(WUS);
6178 if (wus) {
6179 e_info("MAC Wakeup cause - %s\n",
17e813ec
BA		 6180 wus & E1000_WUS_EX ? "Unicast Packet" :
6181 wus & E1000_WUS_MC ? "Multicast Packet" :
6182 wus & E1000_WUS_BC ? "Broadcast Packet" :
6183 wus & E1000_WUS_MAG ? "Magic Packet" :
6184 wus & E1000_WUS_LNKC ? "Link Status Change" :
6185 "other");
a4f58f54
BA		 6186 }
6187 ew32(WUS, ~0);
6188 }
6189
bc7f75fa 6190 e1000e_reset(adapter);
bc7f75fa 6191
cd791618 6192 e1000_init_manageability_pt(adapter);
bc7f75fa 6193
e921eb1a 6194 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6195 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6196 * under the control of the driver.
6197 */
c43bc57e 6198 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6199 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6200
6201 return 0;
6202}
23606cf5 6203
28002099
DE		 6204static int e1000e_pm_thaw(struct device *dev)
6205{
6206 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6207 struct e1000_adapter *adapter = netdev_priv(netdev);
6208
6209 e1000e_set_interrupt_capability(adapter);
6210 if (netif_running(netdev)) {
6211 u32 err = e1000_request_irq(adapter);
6212
6213 if (err)
6214 return err;
6215
6216 e1000e_up(adapter);
6217 }
6218
6219 netif_device_attach(netdev);
6220
6221 return 0;
6222}
6223
38a529b5 6224#ifdef CONFIG_PM_SLEEP
28002099 6225static int e1000e_pm_suspend(struct device *dev)
a0340162
RW		 6226{
6227 struct pci_dev *pdev = to_pci_dev(dev);
a0340162 6228
28002099
DE		 6229 e1000e_pm_freeze(dev);
6230
66148bab 6231 return __e1000_shutdown(pdev, false);
a0340162
RW		 6232}
6233
28002099 6234static int e1000e_pm_resume(struct device *dev)
23606cf5
RW		 6235{
6236 struct pci_dev *pdev = to_pci_dev(dev);
28002099 6237 int rc;
23606cf5 6238
28002099
DE		 6239 rc = __e1000_resume(pdev);
6240 if (rc)
6241 return rc;
23606cf5 6242
28002099 6243 return e1000e_pm_thaw(dev);
23606cf5 6244}
38a529b5 6245#endif /* CONFIG_PM_SLEEP */
a0340162
RW		 6246
6247#ifdef CONFIG_PM_RUNTIME
63eb48f1 6248static int e1000e_pm_runtime_idle(struct device *dev)
a0340162
RW		 6249{
6250 struct pci_dev *pdev = to_pci_dev(dev);
6251 struct net_device *netdev = pci_get_drvdata(pdev);
6252 struct e1000_adapter *adapter = netdev_priv(netdev);
6253
63eb48f1
DE		 6254 if (!e1000e_has_link(adapter))
6255 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
a0340162 6256
63eb48f1 6257 return -EBUSY;
a0340162
RW		 6258}
6259
63eb48f1 6260static int e1000e_pm_runtime_resume(struct device *dev)
a0340162
RW		 6261{
6262 struct pci_dev *pdev = to_pci_dev(dev);
6263 struct net_device *netdev = pci_get_drvdata(pdev);
6264 struct e1000_adapter *adapter = netdev_priv(netdev);
63eb48f1 6265 int rc;
a0340162 6266
63eb48f1
DE		 6267 rc = __e1000_resume(pdev);
6268 if (rc)
6269 return rc;
a0340162 6270
63eb48f1
DE		 6271 if (netdev->flags & IFF_UP)
6272 rc = e1000e_up(adapter);
a0340162 6273
63eb48f1 6274 return rc;
a0340162 6275}
23606cf5 6276
63eb48f1 6277static int e1000e_pm_runtime_suspend(struct device *dev)
23606cf5
RW		 6278{
6279 struct pci_dev *pdev = to_pci_dev(dev);
6280 struct net_device *netdev = pci_get_drvdata(pdev);
6281 struct e1000_adapter *adapter = netdev_priv(netdev);
6282
63eb48f1
DE		 6283 if (netdev->flags & IFF_UP) {
6284 int count = E1000_CHECK_RESET_COUNT;
6285
6286 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6287 usleep_range(10000, 20000);
23606cf5 6288
63eb48f1
DE		 6289 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6290
6291 /* Down the device without resetting the hardware */
6292 e1000e_down(adapter, false);
6293 }
6294
6295 if (__e1000_shutdown(pdev, true)) {
6296 e1000e_pm_runtime_resume(dev);
6297 return -EBUSY;
6298 }
6299
6300 return 0;
23606cf5 6301}
a0340162 6302#endif /* CONFIG_PM_RUNTIME */
aa338601 6303#endif /* CONFIG_PM */
bc7f75fa
AK		 6304
6305static void e1000_shutdown(struct pci_dev *pdev)
6306{
28002099
DE		 6307 e1000e_pm_freeze(&pdev->dev);
6308
66148bab 6309 __e1000_shutdown(pdev, false);
bc7f75fa
AK		 6310}
6311
6312#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c 6313
8bb62869 6314static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
147b2c8c
DD		 6315{
6316 struct net_device *netdev = data;
6317 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6318
6319 if (adapter->msix_entries) {
90da0669
BA		 6320 int vector, msix_irq;
6321
147b2c8c
DD		 6322 vector = 0;
6323 msix_irq = adapter->msix_entries[vector].vector;
6324 disable_irq(msix_irq);
6325 e1000_intr_msix_rx(msix_irq, netdev);
6326 enable_irq(msix_irq);
6327
6328 vector++;
6329 msix_irq = adapter->msix_entries[vector].vector;
6330 disable_irq(msix_irq);
6331 e1000_intr_msix_tx(msix_irq, netdev);
6332 enable_irq(msix_irq);
6333
6334 vector++;
6335 msix_irq = adapter->msix_entries[vector].vector;
6336 disable_irq(msix_irq);
6337 e1000_msix_other(msix_irq, netdev);
6338 enable_irq(msix_irq);
6339 }
6340
6341 return IRQ_HANDLED;
6342}
6343
e921eb1a
BA		 6344/**
6345 * e1000_netpoll
6346 * @netdev: network interface device structure
6347 *
bc7f75fa
AK		 6348 * Polling 'interrupt' - used by things like netconsole to send skbs
6349 * without having to re-enable interrupts. It's not called while
6350 * the interrupt routine is executing.
6351 */
6352static void e1000_netpoll(struct net_device *netdev)
6353{
6354 struct e1000_adapter *adapter = netdev_priv(netdev);
6355
147b2c8c
DD		 6356 switch (adapter->int_mode) {
6357 case E1000E_INT_MODE_MSIX:
6358 e1000_intr_msix(adapter->pdev->irq, netdev);
6359 break;
6360 case E1000E_INT_MODE_MSI:
6361 disable_irq(adapter->pdev->irq);
6362 e1000_intr_msi(adapter->pdev->irq, netdev);
6363 enable_irq(adapter->pdev->irq);
6364 break;
e80bd1d1 6365 default: /* E1000E_INT_MODE_LEGACY */
147b2c8c
DD		 6366 disable_irq(adapter->pdev->irq);
6367 e1000_intr(adapter->pdev->irq, netdev);
6368 enable_irq(adapter->pdev->irq);
6369 break;
6370 }
bc7f75fa
AK		 6371}
6372#endif
6373
6374/**
6375 * e1000_io_error_detected - called when PCI error is detected
6376 * @pdev: Pointer to PCI device
6377 * @state: The current pci connection state
6378 *
6379 * This function is called after a PCI bus error affecting
6380 * this device has been detected.
6381 */
6382static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6383 pci_channel_state_t state)
6384{
6385 struct net_device *netdev = pci_get_drvdata(pdev);
6386 struct e1000_adapter *adapter = netdev_priv(netdev);
6387
6388 netif_device_detach(netdev);
6389
c93b5a76
MM		 6390 if (state == pci_channel_io_perm_failure)
6391 return PCI_ERS_RESULT_DISCONNECT;
6392
bc7f75fa 6393 if (netif_running(netdev))
28002099 6394 e1000e_down(adapter, true);
bc7f75fa
AK		 6395 pci_disable_device(pdev);
6396
6397 /* Request a slot slot reset. */
6398 return PCI_ERS_RESULT_NEED_RESET;
6399}
6400
6401/**
6402 * e1000_io_slot_reset - called after the pci bus has been reset.
6403 * @pdev: Pointer to PCI device
6404 *
6405 * Restart the card from scratch, as if from a cold-boot. Implementation
28002099 6406 * resembles the first-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6407 */
6408static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6409{
6410 struct net_device *netdev = pci_get_drvdata(pdev);
6411 struct e1000_adapter *adapter = netdev_priv(netdev);
6412 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6413 u16 aspm_disable_flag = 0;
6e4f6f6b 6414 int err;
111b9dc5 6415 pci_ers_result_t result;
bc7f75fa 6416
78cd29d5
BA		 6417 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6418 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6419 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6420 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6421 if (aspm_disable_flag)
6422 e1000e_disable_aspm(pdev, aspm_disable_flag);
6423
f0f422e5 6424 err = pci_enable_device_mem(pdev);
6e4f6f6b 6425 if (err) {
bc7f75fa
AK		 6426 dev_err(&pdev->dev,
6427 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6428 result = PCI_ERS_RESULT_DISCONNECT;
6429 } else {
23606cf5 6430 pdev->state_saved = true;
111b9dc5 6431 pci_restore_state(pdev);
66148bab 6432 pci_set_master(pdev);
bc7f75fa 6433
111b9dc5
JB		 6434 pci_enable_wake(pdev, PCI_D3hot, 0);
6435 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6436
111b9dc5
JB		 6437 e1000e_reset(adapter);
6438 ew32(WUS, ~0);
6439 result = PCI_ERS_RESULT_RECOVERED;
6440 }
bc7f75fa 6441
111b9dc5
JB		 6442 pci_cleanup_aer_uncorrect_error_status(pdev);
6443
6444 return result;
bc7f75fa
AK		 6445}
6446
6447/**
6448 * e1000_io_resume - called when traffic can start flowing again.
6449 * @pdev: Pointer to PCI device
6450 *
6451 * This callback is called when the error recovery driver tells us that
6452 * its OK to resume normal operation. Implementation resembles the
28002099 6453 * second-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6454 */
6455static void e1000_io_resume(struct pci_dev *pdev)
6456{
6457 struct net_device *netdev = pci_get_drvdata(pdev);
6458 struct e1000_adapter *adapter = netdev_priv(netdev);
6459
cd791618 6460 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6461
6462 if (netif_running(netdev)) {
6463 if (e1000e_up(adapter)) {
6464 dev_err(&pdev->dev,
6465 "can't bring device back up after reset\n");
6466 return;
6467 }
6468 }
6469
6470 netif_device_attach(netdev);
6471
e921eb1a 6472 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6473 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6474 * under the control of the driver.
6475 */
c43bc57e 6476 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6477 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6478}
6479
6480static void e1000_print_device_info(struct e1000_adapter *adapter)
6481{
6482 struct e1000_hw *hw = &adapter->hw;
6483 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6484 u32 ret_val;
6485 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6486
6487 /* print bus type/speed/width info */
a5cc7642 6488 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6489 /* bus width */
6490 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
f0ff4398 6491 "Width x1"),
44defeb3 6492 /* MAC address */
7c510e4b 6493 netdev->dev_addr);
44defeb3
JK		 6494 e_info("Intel(R) PRO/%s Network Connection\n",
6495 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6496 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6497 E1000_PBANUM_LENGTH);
6498 if (ret_val)
f2315bf1 6499 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6500 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6501 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6502}
6503
10aa4c04
AK		 6504static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6505{
6506 struct e1000_hw *hw = &adapter->hw;
6507 int ret_val;
6508 u16 buf = 0;
6509
6510 if (hw->mac.type != e1000_82573)
6511 return;
6512
6513 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6514 le16_to_cpus(&buf);
6515 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6516 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6517 dev_warn(&adapter->pdev->dev,
6518 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6519 }
10aa4c04
AK		 6520}
6521
c8f44aff 6522static int e1000_set_features(struct net_device *netdev,
70495a50 6523 netdev_features_t features)
dc221294
BA		 6524{
6525 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6526 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6527
6528 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6529 adapter->flags |= FLAG_TSO_FORCE;
6530
f646968f 6531 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
cf955e6c
BG		 6532 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6533 NETIF_F_RXALL)))
dc221294
BA		 6534 return 0;
6535
0184039a
BG		 6536 if (changed & NETIF_F_RXFCS) {
6537 if (features & NETIF_F_RXFCS) {
6538 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6539 } else {
6540 /* We need to take it back to defaults, which might mean
6541 * stripping is still disabled at the adapter level.
6542 */
6543 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6544 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6545 else
6546 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6547 }
6548 }
6549
70495a50
BA		 6550 netdev->features = features;
6551
dc221294
BA		 6552 if (netif_running(netdev))
6553 e1000e_reinit_locked(adapter);
6554 else
6555 e1000e_reset(adapter);
6556
6557 return 0;
6558}
6559
651c2466
SH		 6560static const struct net_device_ops e1000e_netdev_ops = {
6561 .ndo_open = e1000_open,
6562 .ndo_stop = e1000_close,
00829823 6563 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6564 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6565 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6566 .ndo_set_mac_address = e1000_set_mac,
6567 .ndo_change_mtu = e1000_change_mtu,
6568 .ndo_do_ioctl = e1000_ioctl,
6569 .ndo_tx_timeout = e1000_tx_timeout,
6570 .ndo_validate_addr = eth_validate_addr,
6571
651c2466
SH		 6572 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6573 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6574#ifdef CONFIG_NET_POLL_CONTROLLER
6575 .ndo_poll_controller = e1000_netpoll,
6576#endif
dc221294 6577 .ndo_set_features = e1000_set_features,
651c2466
SH		 6578};
6579
bc7f75fa
AK		 6580/**
6581 * e1000_probe - Device Initialization Routine
6582 * @pdev: PCI device information struct
6583 * @ent: entry in e1000_pci_tbl
6584 *
6585 * Returns 0 on success, negative on failure
6586 *
6587 * e1000_probe initializes an adapter identified by a pci_dev structure.
6588 * The OS initialization, configuring of the adapter private structure,
6589 * and a hardware reset occur.
6590 **/
1dd06ae8 6591static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6592{
6593 struct net_device *netdev;
6594 struct e1000_adapter *adapter;
6595 struct e1000_hw *hw;
6596 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6597 resource_size_t mmio_start, mmio_len;
6598 resource_size_t flash_start, flash_len;
bc7f75fa 6599 static int cards_found;
78cd29d5 6600 u16 aspm_disable_flag = 0;
17e813ec 6601 int bars, i, err, pci_using_dac;
bc7f75fa
AK		 6602 u16 eeprom_data = 0;
6603 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6604
78cd29d5
BA		 6605 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6606 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6607 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6608 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6609 if (aspm_disable_flag)
6610 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6611
f0f422e5 6612 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6613 if (err)
6614 return err;
6615
6616 pci_using_dac = 0;
718a39eb 6617 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6618 if (!err) {
718a39eb 6619 pci_using_dac = 1;
bc7f75fa 6620 } else {
718a39eb 6621 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6622 if (err) {
718a39eb
RK		 6623 dev_err(&pdev->dev,
6624 "No usable DMA configuration, aborting\n");
6625 goto err_dma;
bc7f75fa
AK		 6626 }
6627 }
6628
17e813ec
BA		 6629 bars = pci_select_bars(pdev, IORESOURCE_MEM);
6630 err = pci_request_selected_regions_exclusive(pdev, bars,
6631 e1000e_driver_name);
bc7f75fa
AK		 6632 if (err)
6633 goto err_pci_reg;
6634
68eac460 6635 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6636 pci_enable_pcie_error_reporting(pdev);
68eac460 6637
bc7f75fa 6638 pci_set_master(pdev);
438b365a
BA		 6639 /* PCI config space info */
6640 err = pci_save_state(pdev);
6641 if (err)
6642 goto err_alloc_etherdev;
bc7f75fa
AK		 6643
6644 err = -ENOMEM;
6645 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6646 if (!netdev)
6647 goto err_alloc_etherdev;
6648
bc7f75fa
AK		 6649 SET_NETDEV_DEV(netdev, &pdev->dev);
6650
f85e4dfa
TH		 6651 netdev->irq = pdev->irq;
6652
bc7f75fa
AK		 6653 pci_set_drvdata(pdev, netdev);
6654 adapter = netdev_priv(netdev);
6655 hw = &adapter->hw;
6656 adapter->netdev = netdev;
6657 adapter->pdev = pdev;
6658 adapter->ei = ei;
6659 adapter->pba = ei->pba;
6660 adapter->flags = ei->flags;
eb7c3adb 6661 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6662 adapter->hw.adapter = adapter;
6663 adapter->hw.mac.type = ei->mac;
2adc55c9 6664 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6665 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6666
6667 mmio_start = pci_resource_start(pdev, 0);
6668 mmio_len = pci_resource_len(pdev, 0);
6669
6670 err = -EIO;
6671 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6672 if (!adapter->hw.hw_addr)
6673 goto err_ioremap;
6674
6675 if ((adapter->flags & FLAG_HAS_FLASH) &&
6676 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6677 flash_start = pci_resource_start(pdev, 1);
6678 flash_len = pci_resource_len(pdev, 1);
6679 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6680 if (!adapter->hw.flash_address)
6681 goto err_flashmap;
6682 }
6683
d495bcb8
BA		 6684 /* Set default EEE advertisement */
6685 if (adapter->flags2 & FLAG2_HAS_EEE)
6686 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
6687
bc7f75fa 6688 /* construct the net_device struct */
e80bd1d1 6689 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6690 e1000e_set_ethtool_ops(netdev);
e80bd1d1 6691 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6692 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6693 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6694
6695 netdev->mem_start = mmio_start;
6696 netdev->mem_end = mmio_start + mmio_len;
6697
6698 adapter->bd_number = cards_found++;
6699
4662e82b
BA		 6700 e1000e_check_options(adapter);
6701
bc7f75fa
AK		 6702 /* setup adapter struct */
6703 err = e1000_sw_init(adapter);
6704 if (err)
6705 goto err_sw_init;
6706
bc7f75fa
AK		 6707 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6708 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6709 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6710
69e3fd8c 6711 err = ei->get_variants(adapter);
bc7f75fa
AK		 6712 if (err)
6713 goto err_hw_init;
6714
4a770358
BA		 6715 if ((adapter->flags & FLAG_IS_ICH) &&
6716 (adapter->flags & FLAG_READ_ONLY_NVM))
6717 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6718
bc7f75fa
AK		 6719 hw->mac.ops.get_bus_info(&adapter->hw);
6720
318a94d6 6721 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6722
6723 /* Copper options */
318a94d6 6724 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6725 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6726 adapter->hw.phy.disable_polarity_correction = 0;
6727 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6728 }
6729
470a5420 6730 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6731 dev_info(&pdev->dev,
6732 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6733
dc221294
BA		 6734 /* Set initial default active device features */
6735 netdev->features = (NETIF_F_SG |
f646968f
PM		 6736 NETIF_F_HW_VLAN_CTAG_RX |
6737 NETIF_F_HW_VLAN_CTAG_TX |
dc221294
BA		 6738 NETIF_F_TSO |
6739 NETIF_F_TSO6 |
70495a50 6740 NETIF_F_RXHASH |
dc221294
BA		 6741 NETIF_F_RXCSUM |
6742 NETIF_F_HW_CSUM);
6743
6744 /* Set user-changeable features (subset of all device features) */
6745 netdev->hw_features = netdev->features;
0184039a 6746 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6747 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6748 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6749
6750 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
f646968f 6751 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
bc7f75fa 6752
dc221294
BA		 6753 netdev->vlan_features |= (NETIF_F_SG |
6754 NETIF_F_TSO |
6755 NETIF_F_TSO6 |
6756 NETIF_F_HW_CSUM);
a5136e23 6757
ef9b965a
JB		 6758 netdev->priv_flags |= IFF_UNICAST_FLT;
6759
7b872a55 6760 if (pci_using_dac) {
bc7f75fa 6761 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6762 netdev->vlan_features |= NETIF_F_HIGHDMA;
6763 }
bc7f75fa 6764
bc7f75fa
AK		 6765 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6766 adapter->flags |= FLAG_MNG_PT_ENABLED;
6767
e921eb1a 6768 /* before reading the NVM, reset the controller to
ad68076e
BA		 6769 * put the device in a known good starting state
6770 */
bc7f75fa
AK		 6771 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6772
e921eb1a 6773 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6774 * attempt. Let's give it a few tries
6775 */
6776 for (i = 0;; i++) {
6777 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6778 break;
6779 if (i == 2) {
185095fb 6780 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6781 err = -EIO;
6782 goto err_eeprom;
6783 }
6784 }
6785
10aa4c04
AK		 6786 e1000_eeprom_checks(adapter);
6787
608f8a0d 6788 /* copy the MAC address */
bc7f75fa 6789 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6790 dev_err(&pdev->dev,
6791 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6792
6793 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 6794
aaeb6cdf 6795 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 6796 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 6797 netdev->dev_addr);
bc7f75fa
AK		 6798 err = -EIO;
6799 goto err_eeprom;
6800 }
6801
6802 init_timer(&adapter->watchdog_timer);
c061b18d 6803 adapter->watchdog_timer.function = e1000_watchdog;
53aa82da 6804 adapter->watchdog_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6805
6806 init_timer(&adapter->phy_info_timer);
c061b18d 6807 adapter->phy_info_timer.function = e1000_update_phy_info;
53aa82da 6808 adapter->phy_info_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6809
6810 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6811 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6812 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6813 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6814 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6815
bc7f75fa
AK		 6816 /* Initialize link parameters. User can change them with ethtool */
6817 adapter->hw.mac.autoneg = 1;
3db1cd5c 6818 adapter->fc_autoneg = true;
5c48ef3e
BA		 6819 adapter->hw.fc.requested_mode = e1000_fc_default;
6820 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6821 adapter->hw.phy.autoneg_advertised = 0x2f;
6822
e921eb1a 6823 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6824 * the EEPROM, enable the ACPI Magic Packet filter
6825 */
6826 if (adapter->flags & FLAG_APME_IN_WUC) {
6827 /* APME bit in EEPROM is mapped to WUC.APME */
6828 eeprom_data = er32(WUC);
6829 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6830 if ((hw->mac.type > e1000_ich10lan) &&
6831 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6832 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6833 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6834 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6835 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6836 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6837 1, &eeprom_data);
bc7f75fa 6838 else
3d3a1676
BA		 6839 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6840 1, &eeprom_data);
bc7f75fa
AK		 6841 }
6842
6843 /* fetch WoL from EEPROM */
6844 if (eeprom_data & eeprom_apme_mask)
6845 adapter->eeprom_wol |= E1000_WUFC_MAG;
6846
e921eb1a 6847 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6848 * where the eeprom may be wrong or the board simply won't support
6849 * wake on lan on a particular port
6850 */
6851 if (!(adapter->flags & FLAG_HAS_WOL))
6852 adapter->eeprom_wol = 0;
6853
6854 /* initialize the wol settings based on the eeprom settings */
6855 adapter->wol = adapter->eeprom_wol;
66148bab
KK		 6856
6857 /* make sure adapter isn't asleep if manageability is enabled */
6858 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
6859 (hw->mac.ops.check_mng_mode(hw)))
6860 device_wakeup_enable(&pdev->dev);
bc7f75fa 6861
84527590
BA		 6862 /* save off EEPROM version number */
6863 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6864
bc7f75fa
AK		 6865 /* reset the hardware with the new settings */
6866 e1000e_reset(adapter);
6867
e921eb1a 6868 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6869 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6870 * under the control of the driver.
6871 */
c43bc57e 6872 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6873 e1000e_get_hw_control(adapter);
bc7f75fa 6874
f2315bf1 6875 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6876 err = register_netdev(netdev);
6877 if (err)
6878 goto err_register;
6879
9c563d20
JB		 6880 /* carrier off reporting is important to ethtool even BEFORE open */
6881 netif_carrier_off(netdev);
6882
d89777bf
BA		 6883 /* init PTP hardware clock */
6884 e1000e_ptp_init(adapter);
6885
bc7f75fa
AK		 6886 e1000_print_device_info(adapter);
6887
f3ec4f87
AS		 6888 if (pci_dev_run_wake(pdev))
6889 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6890
bc7f75fa
AK		 6891 return 0;
6892
6893err_register:
c43bc57e 6894 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6895 e1000e_release_hw_control(adapter);
bc7f75fa 6896err_eeprom:
470a5420 6897 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6898 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6899err_hw_init:
bc7f75fa
AK		 6900 kfree(adapter->tx_ring);
6901 kfree(adapter->rx_ring);
6902err_sw_init:
c43bc57e
JB		 6903 if (adapter->hw.flash_address)
6904 iounmap(adapter->hw.flash_address);
e82f54ba 6905 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6906err_flashmap:
bc7f75fa
AK		 6907 iounmap(adapter->hw.hw_addr);
6908err_ioremap:
6909 free_netdev(netdev);
6910err_alloc_etherdev:
f0f422e5 6911 pci_release_selected_regions(pdev,
f0ff4398 6912 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6913err_pci_reg:
6914err_dma:
6915 pci_disable_device(pdev);
6916 return err;
6917}
6918
6919/**
6920 * e1000_remove - Device Removal Routine
6921 * @pdev: PCI device information struct
6922 *
6923 * e1000_remove is called by the PCI subsystem to alert the driver
6924 * that it should release a PCI device. The could be caused by a
6925 * Hot-Plug event, or because the driver is going to be removed from
6926 * memory.
6927 **/
9f9a12f8 6928static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 6929{
6930 struct net_device *netdev = pci_get_drvdata(pdev);
6931 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6932 bool down = test_bit(__E1000_DOWN, &adapter->state);
6933
d89777bf
BA		 6934 e1000e_ptp_remove(adapter);
6935
e921eb1a 6936 /* The timers may be rescheduled, so explicitly disable them
23f333a2 6937 * from being rescheduled.
ad68076e 6938 */
23606cf5
RW		 6939 if (!down)
6940 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6941 del_timer_sync(&adapter->watchdog_timer);
6942 del_timer_sync(&adapter->phy_info_timer);
6943
41cec6f1
BA		 6944 cancel_work_sync(&adapter->reset_task);
6945 cancel_work_sync(&adapter->watchdog_task);
6946 cancel_work_sync(&adapter->downshift_task);
6947 cancel_work_sync(&adapter->update_phy_task);
6948 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6949
b67e1913
BA		 6950 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
6951 cancel_work_sync(&adapter->tx_hwtstamp_work);
6952 if (adapter->tx_hwtstamp_skb) {
6953 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
6954 adapter->tx_hwtstamp_skb = NULL;
6955 }
6956 }
6957
23606cf5
RW		 6958 /* Don't lie to e1000_close() down the road. */
6959 if (!down)
6960 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6961 unregister_netdev(netdev);
6962
f3ec4f87
AS		 6963 if (pci_dev_run_wake(pdev))
6964 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6965
e921eb1a 6966 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6967 * would have already happened in close and is redundant.
6968 */
31dbe5b4 6969 e1000e_release_hw_control(adapter);
bc7f75fa 6970
4662e82b 6971 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6972 kfree(adapter->tx_ring);
6973 kfree(adapter->rx_ring);
6974
6975 iounmap(adapter->hw.hw_addr);
6976 if (adapter->hw.flash_address)
6977 iounmap(adapter->hw.flash_address);
f0f422e5 6978 pci_release_selected_regions(pdev,
f0ff4398 6979 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6980
6981 free_netdev(netdev);
6982
111b9dc5 6983 /* AER disable */
19d5afd4 6984 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6985
bc7f75fa
AK		 6986 pci_disable_device(pdev);
6987}
6988
6989/* PCI Error Recovery (ERS) */
3646f0e5 6990static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 6991 .error_detected = e1000_io_error_detected,
6992 .slot_reset = e1000_io_slot_reset,
6993 .resume = e1000_io_resume,
6994};
6995
a3aa1884 6996static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6997 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6998 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6999 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
c29c3ba5
BA		 7000 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7001 board_82571 },
bc7f75fa
AK		 7002 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7003 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 7004 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7005 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7006 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 7007
bc7f75fa
AK		 7008 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7009 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7010 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7011 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 7012
bc7f75fa
AK		 7013 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7014 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7015 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 7016
4662e82b 7017 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 7018 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 7019 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 7020
bc7f75fa
AK		 7021 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7022 board_80003es2lan },
7023 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7024 board_80003es2lan },
7025 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7026 board_80003es2lan },
7027 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7028 board_80003es2lan },
ad68076e 7029
bc7f75fa
AK		 7030 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7031 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7032 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7033 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7034 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7035 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7036 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 7037 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 7038
bc7f75fa
AK		 7039 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7040 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7041 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7042 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7043 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 7044 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 7045 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7046 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7047 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7048
7049 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7050 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7051 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 7052
f4187b56
BA		 7053 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7054 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 7055 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 7056
a4f58f54
BA		 7057 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7058 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7059 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7060 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7061
d3738bb8
BA		 7062 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7063 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7064
2fbe4526
BA		 7065 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7066 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 7067 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7068 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
91a3d82f
BA		 7069 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7070 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7071 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7072 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
2fbe4526 7073
f36bb6ca 7074 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 7075};
7076MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7077
23606cf5 7078static const struct dev_pm_ops e1000_pm_ops = {
72f72dcc 7079#ifdef CONFIG_PM_SLEEP
28002099
DE		 7080 .suspend = e1000e_pm_suspend,
7081 .resume = e1000e_pm_resume,
7082 .freeze = e1000e_pm_freeze,
7083 .thaw = e1000e_pm_thaw,
7084 .poweroff = e1000e_pm_suspend,
7085 .restore = e1000e_pm_resume,
72f72dcc 7086#endif
63eb48f1
DE		 7087 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7088 e1000e_pm_runtime_idle)
23606cf5
RW		 7089};
7090
bc7f75fa
AK		 7091/* PCI Device API Driver */
7092static struct pci_driver e1000_driver = {
7093 .name = e1000e_driver_name,
7094 .id_table = e1000_pci_tbl,
7095 .probe = e1000_probe,
9f9a12f8 7096 .remove = e1000_remove,
f36bb6ca
BA		 7097 .driver = {
7098 .pm = &e1000_pm_ops,
7099 },
bc7f75fa
AK		 7100 .shutdown = e1000_shutdown,
7101 .err_handler = &e1000_err_handler
7102};
7103
7104/**
7105 * e1000_init_module - Driver Registration Routine
7106 *
7107 * e1000_init_module is the first routine called when the driver is
7108 * loaded. All it does is register with the PCI subsystem.
7109 **/
7110static int __init e1000_init_module(void)
7111{
7112 int ret;
8544b9f7
BA		 7113 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7114 e1000e_driver_version);
e78b80b1 7115 pr_info("Copyright(c) 1999 - 2014 Intel Corporation.\n");
bc7f75fa 7116 ret = pci_register_driver(&e1000_driver);
53ec5498 7117
bc7f75fa
AK		 7118 return ret;
7119}
7120module_init(e1000_init_module);
7121
7122/**
7123 * e1000_exit_module - Driver Exit Cleanup Routine
7124 *
7125 * e1000_exit_module is called just before the driver is removed
7126 * from memory.
7127 **/
7128static void __exit e1000_exit_module(void)
7129{
7130 pci_unregister_driver(&e1000_driver);
7131}
7132module_exit(e1000_exit_module);
7133
bc7f75fa
AK		 7134MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7135MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7136MODULE_LICENSE("GPL");
7137MODULE_VERSION(DRV_VERSION);
7138
06c24b91 7139/* netdev.c */
Linux 6.x block layer and io_uring tree(s)