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e1000e: re-enable alternate MAC address for all devices which support it
[linux-block.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
0d6057e4 4 Copyright(c) 1999 - 2011 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
c5778b43 59#define DRV_VERSION "1.5.1" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
78cd29d5
BA		 63static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
64
bc7f75fa
AK		 65static const struct e1000_info *e1000_info_tbl[] = {
66 [board_82571] = &e1000_82571_info,
67 [board_82572] = &e1000_82572_info,
68 [board_82573] = &e1000_82573_info,
4662e82b 69 [board_82574] = &e1000_82574_info,
8c81c9c3 70 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 71 [board_80003es2lan] = &e1000_es2_info,
72 [board_ich8lan] = &e1000_ich8_info,
73 [board_ich9lan] = &e1000_ich9_info,
f4187b56 74 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 75 [board_pchlan] = &e1000_pch_info,
d3738bb8 76 [board_pch2lan] = &e1000_pch2_info,
bc7f75fa
AK		 77};
78
84f4ee90
TI		 79struct e1000_reg_info {
80 u32 ofs;
81 char *name;
82};
83
af667a29
BA		 84#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
85#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
86#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
87#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
88#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
89
90#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
91#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
92#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
93#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
94#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 95
96static const struct e1000_reg_info e1000_reg_info_tbl[] = {
97
98 /* General Registers */
99 {E1000_CTRL, "CTRL"},
100 {E1000_STATUS, "STATUS"},
101 {E1000_CTRL_EXT, "CTRL_EXT"},
102
103 /* Interrupt Registers */
104 {E1000_ICR, "ICR"},
105
af667a29 106 /* Rx Registers */
84f4ee90
TI		 107 {E1000_RCTL, "RCTL"},
108 {E1000_RDLEN, "RDLEN"},
109 {E1000_RDH, "RDH"},
110 {E1000_RDT, "RDT"},
111 {E1000_RDTR, "RDTR"},
112 {E1000_RXDCTL(0), "RXDCTL"},
113 {E1000_ERT, "ERT"},
114 {E1000_RDBAL, "RDBAL"},
115 {E1000_RDBAH, "RDBAH"},
116 {E1000_RDFH, "RDFH"},
117 {E1000_RDFT, "RDFT"},
118 {E1000_RDFHS, "RDFHS"},
119 {E1000_RDFTS, "RDFTS"},
120 {E1000_RDFPC, "RDFPC"},
121
af667a29 122 /* Tx Registers */
84f4ee90
TI		 123 {E1000_TCTL, "TCTL"},
124 {E1000_TDBAL, "TDBAL"},
125 {E1000_TDBAH, "TDBAH"},
126 {E1000_TDLEN, "TDLEN"},
127 {E1000_TDH, "TDH"},
128 {E1000_TDT, "TDT"},
129 {E1000_TIDV, "TIDV"},
130 {E1000_TXDCTL(0), "TXDCTL"},
131 {E1000_TADV, "TADV"},
132 {E1000_TARC(0), "TARC"},
133 {E1000_TDFH, "TDFH"},
134 {E1000_TDFT, "TDFT"},
135 {E1000_TDFHS, "TDFHS"},
136 {E1000_TDFTS, "TDFTS"},
137 {E1000_TDFPC, "TDFPC"},
138
139 /* List Terminator */
140 {}
141};
142
143/*
144 * e1000_regdump - register printout routine
145 */
146static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
147{
148 int n = 0;
149 char rname[16];
150 u32 regs[8];
151
152 switch (reginfo->ofs) {
153 case E1000_RXDCTL(0):
154 for (n = 0; n < 2; n++)
155 regs[n] = __er32(hw, E1000_RXDCTL(n));
156 break;
157 case E1000_TXDCTL(0):
158 for (n = 0; n < 2; n++)
159 regs[n] = __er32(hw, E1000_TXDCTL(n));
160 break;
161 case E1000_TARC(0):
162 for (n = 0; n < 2; n++)
163 regs[n] = __er32(hw, E1000_TARC(n));
164 break;
165 default:
ef456f85
JK		 166 pr_info("%-15s %08x\n",
167 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 168 return;
169 }
170
171 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 172 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 173}
174
84f4ee90 175/*
af667a29 176 * e1000e_dump - Print registers, Tx-ring and Rx-ring
84f4ee90
TI		 177 */
178static void e1000e_dump(struct e1000_adapter *adapter)
179{
180 struct net_device *netdev = adapter->netdev;
181 struct e1000_hw *hw = &adapter->hw;
182 struct e1000_reg_info *reginfo;
183 struct e1000_ring *tx_ring = adapter->tx_ring;
184 struct e1000_tx_desc *tx_desc;
af667a29
BA		 185 struct my_u0 {
186 u64 a;
187 u64 b;
188 } *u0;
84f4ee90
TI		 189 struct e1000_buffer *buffer_info;
190 struct e1000_ring *rx_ring = adapter->rx_ring;
191 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 192 union e1000_rx_desc_extended *rx_desc;
af667a29
BA		 193 struct my_u1 {
194 u64 a;
195 u64 b;
196 u64 c;
197 u64 d;
198 } *u1;
84f4ee90
TI		 199 u32 staterr;
200 int i = 0;
201
202 if (!netif_msg_hw(adapter))
203 return;
204
205 /* Print netdevice Info */
206 if (netdev) {
207 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 208 pr_info("Device Name state trans_start last_rx\n");
209 pr_info("%-15s %016lX %016lX %016lX\n",
210 netdev->name, netdev->state, netdev->trans_start,
211 netdev->last_rx);
84f4ee90
TI		 212 }
213
214 /* Print Registers */
215 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 216 pr_info(" Register Name Value\n");
84f4ee90
TI		 217 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
218 reginfo->name; reginfo++) {
219 e1000_regdump(hw, reginfo);
220 }
221
af667a29 222 /* Print Tx Ring Summary */
84f4ee90
TI		 223 if (!netdev || !netif_running(netdev))
224 goto exit;
225
af667a29 226 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 227 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 228 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 229 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
230 0, tx_ring->next_to_use, tx_ring->next_to_clean,
231 (unsigned long long)buffer_info->dma,
232 buffer_info->length,
233 buffer_info->next_to_watch,
234 (unsigned long long)buffer_info->time_stamp);
84f4ee90 235
af667a29 236 /* Print Tx Ring */
84f4ee90
TI		 237 if (!netif_msg_tx_done(adapter))
238 goto rx_ring_summary;
239
af667a29 240 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 241
242 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
243 *
244 * Legacy Transmit Descriptor
245 * +--------------------------------------------------------------+
246 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
247 * +--------------------------------------------------------------+
248 * 8 | Special | CSS | Status | CMD | CSO | Length |
249 * +--------------------------------------------------------------+
250 * 63 48 47 36 35 32 31 24 23 16 15 0
251 *
252 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
253 * 63 48 47 40 39 32 31 16 15 8 7 0
254 * +----------------------------------------------------------------+
255 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
256 * +----------------------------------------------------------------+
257 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
258 * +----------------------------------------------------------------+
259 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
260 *
261 * Extended Data Descriptor (DTYP=0x1)
262 * +----------------------------------------------------------------+
263 * 0 | Buffer Address [63:0] |
264 * +----------------------------------------------------------------+
265 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
266 * +----------------------------------------------------------------+
267 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
268 */
ef456f85
JK		 269 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
270 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
271 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 272 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 273 const char *next_desc;
84f4ee90
TI		 274 tx_desc = E1000_TX_DESC(*tx_ring, i);
275 buffer_info = &tx_ring->buffer_info[i];
276 u0 = (struct my_u0 *)tx_desc;
84f4ee90 277 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 278 next_desc = " NTC/U";
84f4ee90 279 else if (i == tx_ring->next_to_use)
ef456f85 280 next_desc = " NTU";
84f4ee90 281 else if (i == tx_ring->next_to_clean)
ef456f85 282 next_desc = " NTC";
84f4ee90 283 else
ef456f85
JK		 284 next_desc = "";
285 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
286 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
287 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
288 i,
289 (unsigned long long)le64_to_cpu(u0->a),
290 (unsigned long long)le64_to_cpu(u0->b),
291 (unsigned long long)buffer_info->dma,
292 buffer_info->length, buffer_info->next_to_watch,
293 (unsigned long long)buffer_info->time_stamp,
294 buffer_info->skb, next_desc);
84f4ee90
TI		 295
296 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
297 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
af667a29
BA		 298 16, 1, phys_to_virt(buffer_info->dma),
299 buffer_info->length, true);
84f4ee90
TI		 300 }
301
af667a29 302 /* Print Rx Ring Summary */
84f4ee90 303rx_ring_summary:
af667a29 304 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 305 pr_info("Queue [NTU] [NTC]\n");
306 pr_info(" %5d %5X %5X\n",
307 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 308
af667a29 309 /* Print Rx Ring */
84f4ee90
TI		 310 if (!netif_msg_rx_status(adapter))
311 goto exit;
312
af667a29 313 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 314 switch (adapter->rx_ps_pages) {
315 case 1:
316 case 2:
317 case 3:
318 /* [Extended] Packet Split Receive Descriptor Format
319 *
320 * +-----------------------------------------------------+
321 * 0 | Buffer Address 0 [63:0] |
322 * +-----------------------------------------------------+
323 * 8 | Buffer Address 1 [63:0] |
324 * +-----------------------------------------------------+
325 * 16 | Buffer Address 2 [63:0] |
326 * +-----------------------------------------------------+
327 * 24 | Buffer Address 3 [63:0] |
328 * +-----------------------------------------------------+
329 */
ef456f85 330 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 331 /* [Extended] Receive Descriptor (Write-Back) Format
332 *
333 * 63 48 47 32 31 13 12 8 7 4 3 0
334 * +------------------------------------------------------+
335 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
336 * | Checksum | Ident | | Queue | | Type |
337 * +------------------------------------------------------+
338 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
339 * +------------------------------------------------------+
340 * 63 48 47 32 31 20 19 0
341 */
ef456f85 342 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 343 for (i = 0; i < rx_ring->count; i++) {
ef456f85 344 const char *next_desc;
84f4ee90
TI		 345 buffer_info = &rx_ring->buffer_info[i];
346 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
347 u1 = (struct my_u1 *)rx_desc_ps;
348 staterr =
af667a29 349 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 350
351 if (i == rx_ring->next_to_use)
352 next_desc = " NTU";
353 else if (i == rx_ring->next_to_clean)
354 next_desc = " NTC";
355 else
356 next_desc = "";
357
84f4ee90
TI		 358 if (staterr & E1000_RXD_STAT_DD) {
359 /* Descriptor Done */
ef456f85
JK		 360 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
361 "RWB", i,
362 (unsigned long long)le64_to_cpu(u1->a),
363 (unsigned long long)le64_to_cpu(u1->b),
364 (unsigned long long)le64_to_cpu(u1->c),
365 (unsigned long long)le64_to_cpu(u1->d),
366 buffer_info->skb, next_desc);
84f4ee90 367 } else {
ef456f85
JK		 368 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
369 "R ", i,
370 (unsigned long long)le64_to_cpu(u1->a),
371 (unsigned long long)le64_to_cpu(u1->b),
372 (unsigned long long)le64_to_cpu(u1->c),
373 (unsigned long long)le64_to_cpu(u1->d),
374 (unsigned long long)buffer_info->dma,
375 buffer_info->skb, next_desc);
84f4ee90
TI		 376
377 if (netif_msg_pktdata(adapter))
378 print_hex_dump(KERN_INFO, "",
379 DUMP_PREFIX_ADDRESS, 16, 1,
380 phys_to_virt(buffer_info->dma),
381 adapter->rx_ps_bsize0, true);
382 }
84f4ee90
TI		 383 }
384 break;
385 default:
386 case 0:
5f450212 387 /* Extended Receive Descriptor (Read) Format
84f4ee90 388 *
5f450212
BA		 389 * +-----------------------------------------------------+
390 * 0 | Buffer Address [63:0] |
391 * +-----------------------------------------------------+
392 * 8 | Reserved |
393 * +-----------------------------------------------------+
84f4ee90 394 */
ef456f85 395 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 396 /* Extended Receive Descriptor (Write-Back) Format
397 *
398 * 63 48 47 32 31 24 23 4 3 0
399 * +------------------------------------------------------+
400 * | RSS Hash | | | |
401 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
402 * | Packet | IP | | | Type |
403 * | Checksum | Ident | | | |
404 * +------------------------------------------------------+
405 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
406 * +------------------------------------------------------+
407 * 63 48 47 32 31 20 19 0
408 */
ef456f85 409 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 410
411 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 412 const char *next_desc;
413
84f4ee90 414 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 415 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
416 u1 = (struct my_u1 *)rx_desc;
417 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 418
419 if (i == rx_ring->next_to_use)
420 next_desc = " NTU";
421 else if (i == rx_ring->next_to_clean)
422 next_desc = " NTC";
423 else
424 next_desc = "";
425
5f450212
BA		 426 if (staterr & E1000_RXD_STAT_DD) {
427 /* Descriptor Done */
ef456f85
JK		 428 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
429 "RWB", i,
430 (unsigned long long)le64_to_cpu(u1->a),
431 (unsigned long long)le64_to_cpu(u1->b),
432 buffer_info->skb, next_desc);
5f450212 433 } else {
ef456f85
JK		 434 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
435 "R ", i,
436 (unsigned long long)le64_to_cpu(u1->a),
437 (unsigned long long)le64_to_cpu(u1->b),
438 (unsigned long long)buffer_info->dma,
439 buffer_info->skb, next_desc);
5f450212
BA		 440
441 if (netif_msg_pktdata(adapter))
442 print_hex_dump(KERN_INFO, "",
443 DUMP_PREFIX_ADDRESS, 16,
444 1,
445 phys_to_virt
446 (buffer_info->dma),
447 adapter->rx_buffer_len,
448 true);
449 }
84f4ee90
TI		 450 }
451 }
452
453exit:
454 return;
455}
456
bc7f75fa
AK		 457/**
458 * e1000_desc_unused - calculate if we have unused descriptors
459 **/
460static int e1000_desc_unused(struct e1000_ring *ring)
461{
462 if (ring->next_to_clean > ring->next_to_use)
463 return ring->next_to_clean - ring->next_to_use - 1;
464
465 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
466}
467
468/**
ad68076e 469 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa
AK		 470 * @adapter: board private structure
471 * @status: descriptor status field as written by hardware
472 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
473 * @skb: pointer to sk_buff to be indicated to stack
474 **/
475static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 476 struct net_device *netdev, struct sk_buff *skb,
a39fe742 477 u8 status, __le16 vlan)
bc7f75fa 478{
86d70e53 479 u16 tag = le16_to_cpu(vlan);
bc7f75fa
AK		 480 skb->protocol = eth_type_trans(skb, netdev);
481
86d70e53
JK		 482 if (status & E1000_RXD_STAT_VP)
483 __vlan_hwaccel_put_tag(skb, tag);
484
485 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 486}
487
488/**
af667a29 489 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 490 * @adapter: board private structure
491 * @status_err: receive descriptor status and error fields
492 * @csum: receive descriptor csum field
493 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 494 **/
495static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
afd12939 496 __le16 csum, struct sk_buff *skb)
bc7f75fa
AK		 497{
498 u16 status = (u16)status_err;
499 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 500
501 skb_checksum_none_assert(skb);
bc7f75fa 502
afd12939
BA		 503 /* Rx checksum disabled */
504 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
505 return;
506
bc7f75fa
AK		 507 /* Ignore Checksum bit is set */
508 if (status & E1000_RXD_STAT_IXSM)
509 return;
afd12939 510
bc7f75fa
AK		 511 /* TCP/UDP checksum error bit is set */
512 if (errors & E1000_RXD_ERR_TCPE) {
513 /* let the stack verify checksum errors */
514 adapter->hw_csum_err++;
515 return;
516 }
517
518 /* TCP/UDP Checksum has not been calculated */
519 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
520 return;
521
522 /* It must be a TCP or UDP packet with a valid checksum */
523 if (status & E1000_RXD_STAT_TCPCS) {
524 /* TCP checksum is good */
525 skb->ip_summed = CHECKSUM_UNNECESSARY;
526 } else {
ad68076e
BA		 527 /*
528 * IP fragment with UDP payload
529 * Hardware complements the payload checksum, so we undo it
bc7f75fa
AK		 530 * and then put the value in host order for further stack use.
531 */
afd12939 532 __sum16 sum = (__force __sum16)swab16((__force u16)csum);
a39fe742 533 skb->csum = csum_unfold(~sum);
bc7f75fa
AK		 534 skb->ip_summed = CHECKSUM_COMPLETE;
535 }
536 adapter->hw_csum_good++;
537}
538
c6e7f51e
BA		 539/**
540 * e1000e_update_tail_wa - helper function for e1000e_update_[rt]dt_wa()
541 * @hw: pointer to the HW structure
542 * @tail: address of tail descriptor register
543 * @i: value to write to tail descriptor register
544 *
545 * When updating the tail register, the ME could be accessing Host CSR
546 * registers at the same time. Normally, this is handled in h/w by an
547 * arbiter but on some parts there is a bug that acknowledges Host accesses
548 * later than it should which could result in the descriptor register to
549 * have an incorrect value. Workaround this by checking the FWSM register
550 * which has bit 24 set while ME is accessing Host CSR registers, wait
551 * if it is set and try again a number of times.
552 **/
553static inline s32 e1000e_update_tail_wa(struct e1000_hw *hw, u8 __iomem * tail,
554 unsigned int i)
555{
556 unsigned int j = 0;
557
558 while ((j++ < E1000_ICH_FWSM_PCIM2PCI_COUNT) &&
559 (er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI))
560 udelay(50);
561
562 writel(i, tail);
563
564 if ((j == E1000_ICH_FWSM_PCIM2PCI_COUNT) && (i != readl(tail)))
565 return E1000_ERR_SWFW_SYNC;
566
567 return 0;
568}
569
570static void e1000e_update_rdt_wa(struct e1000_adapter *adapter, unsigned int i)
571{
572 u8 __iomem *tail = (adapter->hw.hw_addr + adapter->rx_ring->tail);
573 struct e1000_hw *hw = &adapter->hw;
574
575 if (e1000e_update_tail_wa(hw, tail, i)) {
576 u32 rctl = er32(RCTL);
577 ew32(RCTL, rctl & ~E1000_RCTL_EN);
578 e_err("ME firmware caused invalid RDT - resetting\n");
579 schedule_work(&adapter->reset_task);
580 }
581}
582
583static void e1000e_update_tdt_wa(struct e1000_adapter *adapter, unsigned int i)
584{
585 u8 __iomem *tail = (adapter->hw.hw_addr + adapter->tx_ring->tail);
586 struct e1000_hw *hw = &adapter->hw;
587
588 if (e1000e_update_tail_wa(hw, tail, i)) {
589 u32 tctl = er32(TCTL);
590 ew32(TCTL, tctl & ~E1000_TCTL_EN);
591 e_err("ME firmware caused invalid TDT - resetting\n");
592 schedule_work(&adapter->reset_task);
593 }
594}
595
bc7f75fa 596/**
5f450212 597 * e1000_alloc_rx_buffers - Replace used receive buffers
bc7f75fa
AK		 598 * @adapter: address of board private structure
599 **/
600static void e1000_alloc_rx_buffers(struct e1000_adapter *adapter,
c2fed996 601 int cleaned_count, gfp_t gfp)
bc7f75fa
AK		 602{
603 struct net_device *netdev = adapter->netdev;
604 struct pci_dev *pdev = adapter->pdev;
605 struct e1000_ring *rx_ring = adapter->rx_ring;
5f450212 606 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 607 struct e1000_buffer *buffer_info;
608 struct sk_buff *skb;
609 unsigned int i;
89d71a66 610 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 611
612 i = rx_ring->next_to_use;
613 buffer_info = &rx_ring->buffer_info[i];
614
615 while (cleaned_count--) {
616 skb = buffer_info->skb;
617 if (skb) {
618 skb_trim(skb, 0);
619 goto map_skb;
620 }
621
c2fed996 622 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 623 if (!skb) {
624 /* Better luck next round */
625 adapter->alloc_rx_buff_failed++;
626 break;
627 }
628
bc7f75fa
AK		 629 buffer_info->skb = skb;
630map_skb:
0be3f55f 631 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 632 adapter->rx_buffer_len,
0be3f55f
NN		 633 DMA_FROM_DEVICE);
634 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 635 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 636 adapter->rx_dma_failed++;
637 break;
638 }
639
5f450212
BA		 640 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
641 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 642
50849d79
TH		 643 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
644 /*
645 * Force memory writes to complete before letting h/w
646 * know there are new descriptors to fetch. (Only
647 * applicable for weak-ordered memory model archs,
648 * such as IA-64).
649 */
650 wmb();
c6e7f51e
BA		 651 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
652 e1000e_update_rdt_wa(adapter, i);
653 else
654 writel(i, adapter->hw.hw_addr + rx_ring->tail);
50849d79 655 }
bc7f75fa
AK		 656 i++;
657 if (i == rx_ring->count)
658 i = 0;
659 buffer_info = &rx_ring->buffer_info[i];
660 }
661
50849d79 662 rx_ring->next_to_use = i;
bc7f75fa
AK		 663}
664
665/**
666 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
667 * @adapter: address of board private structure
668 **/
669static void e1000_alloc_rx_buffers_ps(struct e1000_adapter *adapter,
c2fed996 670 int cleaned_count, gfp_t gfp)
bc7f75fa
AK		 671{
672 struct net_device *netdev = adapter->netdev;
673 struct pci_dev *pdev = adapter->pdev;
674 union e1000_rx_desc_packet_split *rx_desc;
675 struct e1000_ring *rx_ring = adapter->rx_ring;
676 struct e1000_buffer *buffer_info;
677 struct e1000_ps_page *ps_page;
678 struct sk_buff *skb;
679 unsigned int i, j;
680
681 i = rx_ring->next_to_use;
682 buffer_info = &rx_ring->buffer_info[i];
683
684 while (cleaned_count--) {
685 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
686
687 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 688 ps_page = &buffer_info->ps_pages[j];
689 if (j >= adapter->rx_ps_pages) {
690 /* all unused desc entries get hw null ptr */
af667a29
BA		 691 rx_desc->read.buffer_addr[j + 1] =
692 ~cpu_to_le64(0);
47f44e40
AK		 693 continue;
694 }
695 if (!ps_page->page) {
c2fed996 696 ps_page->page = alloc_page(gfp);
bc7f75fa 697 if (!ps_page->page) {
47f44e40
AK		 698 adapter->alloc_rx_buff_failed++;
699 goto no_buffers;
700 }
0be3f55f
NN		 701 ps_page->dma = dma_map_page(&pdev->dev,
702 ps_page->page,
703 0, PAGE_SIZE,
704 DMA_FROM_DEVICE);
705 if (dma_mapping_error(&pdev->dev,
706 ps_page->dma)) {
47f44e40 707 dev_err(&adapter->pdev->dev,
af667a29 708 "Rx DMA page map failed\n");
47f44e40
AK		 709 adapter->rx_dma_failed++;
710 goto no_buffers;
bc7f75fa 711 }
bc7f75fa 712 }
47f44e40
AK		 713 /*
714 * Refresh the desc even if buffer_addrs
715 * didn't change because each write-back
716 * erases this info.
717 */
af667a29
BA		 718 rx_desc->read.buffer_addr[j + 1] =
719 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 720 }
721
c2fed996
JK		 722 skb = __netdev_alloc_skb_ip_align(netdev,
723 adapter->rx_ps_bsize0,
724 gfp);
bc7f75fa
AK		 725
726 if (!skb) {
727 adapter->alloc_rx_buff_failed++;
728 break;
729 }
730
bc7f75fa 731 buffer_info->skb = skb;
0be3f55f 732 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 733 adapter->rx_ps_bsize0,
0be3f55f
NN		 734 DMA_FROM_DEVICE);
735 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 736 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 737 adapter->rx_dma_failed++;
738 /* cleanup skb */
739 dev_kfree_skb_any(skb);
740 buffer_info->skb = NULL;
741 break;
742 }
743
744 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
745
50849d79
TH		 746 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
747 /*
748 * Force memory writes to complete before letting h/w
749 * know there are new descriptors to fetch. (Only
750 * applicable for weak-ordered memory model archs,
751 * such as IA-64).
752 */
753 wmb();
c6e7f51e
BA		 754 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
755 e1000e_update_rdt_wa(adapter, i << 1);
756 else
757 writel(i << 1,
758 adapter->hw.hw_addr + rx_ring->tail);
50849d79
TH		 759 }
760
bc7f75fa
AK		 761 i++;
762 if (i == rx_ring->count)
763 i = 0;
764 buffer_info = &rx_ring->buffer_info[i];
765 }
766
767no_buffers:
50849d79 768 rx_ring->next_to_use = i;
bc7f75fa
AK		 769}
770
97ac8cae
BA		 771/**
772 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
773 * @adapter: address of board private structure
97ac8cae
BA		 774 * @cleaned_count: number of buffers to allocate this pass
775 **/
776
777static void e1000_alloc_jumbo_rx_buffers(struct e1000_adapter *adapter,
c2fed996 778 int cleaned_count, gfp_t gfp)
97ac8cae
BA		 779{
780 struct net_device *netdev = adapter->netdev;
781 struct pci_dev *pdev = adapter->pdev;
5f450212 782 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 783 struct e1000_ring *rx_ring = adapter->rx_ring;
784 struct e1000_buffer *buffer_info;
785 struct sk_buff *skb;
786 unsigned int i;
89d71a66 787 unsigned int bufsz = 256 - 16 /* for skb_reserve */;
97ac8cae
BA		 788
789 i = rx_ring->next_to_use;
790 buffer_info = &rx_ring->buffer_info[i];
791
792 while (cleaned_count--) {
793 skb = buffer_info->skb;
794 if (skb) {
795 skb_trim(skb, 0);
796 goto check_page;
797 }
798
c2fed996 799 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 800 if (unlikely(!skb)) {
801 /* Better luck next round */
802 adapter->alloc_rx_buff_failed++;
803 break;
804 }
805
97ac8cae
BA		 806 buffer_info->skb = skb;
807check_page:
808 /* allocate a new page if necessary */
809 if (!buffer_info->page) {
c2fed996 810 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 811 if (unlikely(!buffer_info->page)) {
812 adapter->alloc_rx_buff_failed++;
813 break;
814 }
815 }
816
817 if (!buffer_info->dma)
0be3f55f 818 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 819 buffer_info->page, 0,
820 PAGE_SIZE,
0be3f55f 821 DMA_FROM_DEVICE);
97ac8cae 822
5f450212
BA		 823 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
824 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 825
826 if (unlikely(++i == rx_ring->count))
827 i = 0;
828 buffer_info = &rx_ring->buffer_info[i];
829 }
830
831 if (likely(rx_ring->next_to_use != i)) {
832 rx_ring->next_to_use = i;
833 if (unlikely(i-- == 0))
834 i = (rx_ring->count - 1);
835
836 /* Force memory writes to complete before letting h/w
837 * know there are new descriptors to fetch. (Only
838 * applicable for weak-ordered memory model archs,
839 * such as IA-64). */
840 wmb();
c6e7f51e
BA		 841 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
842 e1000e_update_rdt_wa(adapter, i);
843 else
844 writel(i, adapter->hw.hw_addr + rx_ring->tail);
97ac8cae
BA		 845 }
846}
847
70495a50
BA		 848static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
849 struct sk_buff *skb)
850{
851 if (netdev->features & NETIF_F_RXHASH)
852 skb->rxhash = le32_to_cpu(rss);
853}
854
bc7f75fa
AK		 855/**
856 * e1000_clean_rx_irq - Send received data up the network stack; legacy
857 * @adapter: board private structure
858 *
859 * the return value indicates whether actual cleaning was done, there
860 * is no guarantee that everything was cleaned
861 **/
862static bool e1000_clean_rx_irq(struct e1000_adapter *adapter,
863 int *work_done, int work_to_do)
864{
865 struct net_device *netdev = adapter->netdev;
866 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 867 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 868 struct e1000_ring *rx_ring = adapter->rx_ring;
5f450212 869 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 870 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 871 u32 length, staterr;
bc7f75fa
AK		 872 unsigned int i;
873 int cleaned_count = 0;
3db1cd5c 874 bool cleaned = false;
bc7f75fa
AK		 875 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
876
877 i = rx_ring->next_to_clean;
5f450212
BA		 878 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
879 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 880 buffer_info = &rx_ring->buffer_info[i];
881
5f450212 882 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 883 struct sk_buff *skb;
bc7f75fa
AK		 884
885 if (*work_done >= work_to_do)
886 break;
887 (*work_done)++;
2d0bb1c1 888 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 889
bc7f75fa
AK		 890 skb = buffer_info->skb;
891 buffer_info->skb = NULL;
892
893 prefetch(skb->data - NET_IP_ALIGN);
894
895 i++;
896 if (i == rx_ring->count)
897 i = 0;
5f450212 898 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 899 prefetch(next_rxd);
900
901 next_buffer = &rx_ring->buffer_info[i];
902
3db1cd5c 903 cleaned = true;
bc7f75fa 904 cleaned_count++;
0be3f55f 905 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 906 buffer_info->dma,
907 adapter->rx_buffer_len,
0be3f55f 908 DMA_FROM_DEVICE);
bc7f75fa
AK		 909 buffer_info->dma = 0;
910
5f450212 911 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 912
b94b5028
JB		 913 /*
914 * !EOP means multiple descriptors were used to store a single
915 * packet, if that's the case we need to toss it. In fact, we
916 * need to toss every packet with the EOP bit clear and the
917 * next frame that _does_ have the EOP bit set, as it is by
918 * definition only a frame fragment
919 */
5f450212 920 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 921 adapter->flags2 |= FLAG2_IS_DISCARDING;
922
923 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 924 /* All receives must fit into a single buffer */
3bb99fe2 925 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 926 /* recycle */
927 buffer_info->skb = skb;
5f450212 928 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 929 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 930 goto next_desc;
931 }
932
5f450212 933 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
bc7f75fa
AK		 934 /* recycle */
935 buffer_info->skb = skb;
936 goto next_desc;
937 }
938
eb7c3adb
JK		 939 /* adjust length to remove Ethernet CRC */
940 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
941 length -= 4;
942
bc7f75fa
AK		 943 total_rx_bytes += length;
944 total_rx_packets++;
945
ad68076e
BA		 946 /*
947 * code added for copybreak, this should improve
bc7f75fa 948 * performance for small packets with large amounts
ad68076e
BA		 949 * of reassembly being done in the stack
950 */
bc7f75fa
AK		 951 if (length < copybreak) {
952 struct sk_buff *new_skb =
89d71a66 953 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 954 if (new_skb) {
808ff676
BA		 955 skb_copy_to_linear_data_offset(new_skb,
956 -NET_IP_ALIGN,
957 (skb->data -
958 NET_IP_ALIGN),
959 (length +
960 NET_IP_ALIGN));
bc7f75fa
AK		 961 /* save the skb in buffer_info as good */
962 buffer_info->skb = skb;
963 skb = new_skb;
964 }
965 /* else just continue with the old one */
966 }
967 /* end copybreak code */
968 skb_put(skb, length);
969
970 /* Receive Checksum Offload */
5f450212 971 e1000_rx_checksum(adapter, staterr,
afd12939 972 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 973
70495a50
BA		 974 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
975
5f450212
BA		 976 e1000_receive_skb(adapter, netdev, skb, staterr,
977 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 978
979next_desc:
5f450212 980 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 981
982 /* return some buffers to hardware, one at a time is too slow */
983 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
c2fed996
JK		 984 adapter->alloc_rx_buf(adapter, cleaned_count,
985 GFP_ATOMIC);
bc7f75fa
AK		 986 cleaned_count = 0;
987 }
988
989 /* use prefetched values */
990 rx_desc = next_rxd;
991 buffer_info = next_buffer;
5f450212
BA		 992
993 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 994 }
995 rx_ring->next_to_clean = i;
996
997 cleaned_count = e1000_desc_unused(rx_ring);
998 if (cleaned_count)
c2fed996 999 adapter->alloc_rx_buf(adapter, cleaned_count, GFP_ATOMIC);
bc7f75fa 1000
bc7f75fa 1001 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1002 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1003 return cleaned;
1004}
1005
bc7f75fa
AK		 1006static void e1000_put_txbuf(struct e1000_adapter *adapter,
1007 struct e1000_buffer *buffer_info)
1008{
03b1320d
AD		 1009 if (buffer_info->dma) {
1010 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1011 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1012 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1013 else
0be3f55f
NN		 1014 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1015 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1016 buffer_info->dma = 0;
1017 }
bc7f75fa
AK		 1018 if (buffer_info->skb) {
1019 dev_kfree_skb_any(buffer_info->skb);
1020 buffer_info->skb = NULL;
1021 }
1b7719c4 1022 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1023}
1024
41cec6f1 1025static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1026{
41cec6f1
BA		 1027 struct e1000_adapter *adapter = container_of(work,
1028 struct e1000_adapter,
1029 print_hang_task);
09357b00 1030 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1031 struct e1000_ring *tx_ring = adapter->tx_ring;
1032 unsigned int i = tx_ring->next_to_clean;
1033 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1034 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1035 struct e1000_hw *hw = &adapter->hw;
1036 u16 phy_status, phy_1000t_status, phy_ext_status;
1037 u16 pci_status;
1038
615b32af
JB		 1039 if (test_bit(__E1000_DOWN, &adapter->state))
1040 return;
1041
09357b00
JK		 1042 if (!adapter->tx_hang_recheck &&
1043 (adapter->flags2 & FLAG2_DMA_BURST)) {
1044 /* May be block on write-back, flush and detect again
1045 * flush pending descriptor writebacks to memory
1046 */
1047 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1048 /* execute the writes immediately */
1049 e1e_flush();
1050 adapter->tx_hang_recheck = true;
1051 return;
1052 }
1053 /* Real hang detected */
1054 adapter->tx_hang_recheck = false;
1055 netif_stop_queue(netdev);
1056
41cec6f1
BA		 1057 e1e_rphy(hw, PHY_STATUS, &phy_status);
1058 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1059 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1060
41cec6f1
BA		 1061 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1062
1063 /* detected Hardware unit hang */
1064 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1065 " TDH <%x>\n"
1066 " TDT <%x>\n"
1067 " next_to_use <%x>\n"
1068 " next_to_clean <%x>\n"
1069 "buffer_info[next_to_clean]:\n"
1070 " time_stamp <%lx>\n"
1071 " next_to_watch <%x>\n"
1072 " jiffies <%lx>\n"
41cec6f1
BA		 1073 " next_to_watch.status <%x>\n"
1074 "MAC Status <%x>\n"
1075 "PHY Status <%x>\n"
1076 "PHY 1000BASE-T Status <%x>\n"
1077 "PHY Extended Status <%x>\n"
1078 "PCI Status <%x>\n",
44defeb3
JK		 1079 readl(adapter->hw.hw_addr + tx_ring->head),
1080 readl(adapter->hw.hw_addr + tx_ring->tail),
1081 tx_ring->next_to_use,
1082 tx_ring->next_to_clean,
1083 tx_ring->buffer_info[eop].time_stamp,
1084 eop,
1085 jiffies,
41cec6f1
BA		 1086 eop_desc->upper.fields.status,
1087 er32(STATUS),
1088 phy_status,
1089 phy_1000t_status,
1090 phy_ext_status,
1091 pci_status);
bc7f75fa
AK		 1092}
1093
1094/**
1095 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1096 * @adapter: board private structure
1097 *
1098 * the return value indicates whether actual cleaning was done, there
1099 * is no guarantee that everything was cleaned
1100 **/
1101static bool e1000_clean_tx_irq(struct e1000_adapter *adapter)
1102{
1103 struct net_device *netdev = adapter->netdev;
1104 struct e1000_hw *hw = &adapter->hw;
1105 struct e1000_ring *tx_ring = adapter->tx_ring;
1106 struct e1000_tx_desc *tx_desc, *eop_desc;
1107 struct e1000_buffer *buffer_info;
1108 unsigned int i, eop;
1109 unsigned int count = 0;
bc7f75fa 1110 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1111 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1112
1113 i = tx_ring->next_to_clean;
1114 eop = tx_ring->buffer_info[i].next_to_watch;
1115 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1116
12d04a3c
AD		 1117 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1118 (count < tx_ring->count)) {
a86043c2 1119 bool cleaned = false;
2d0bb1c1 1120 rmb(); /* read buffer_info after eop_desc */
a86043c2 1121 for (; !cleaned; count++) {
bc7f75fa
AK		 1122 tx_desc = E1000_TX_DESC(*tx_ring, i);
1123 buffer_info = &tx_ring->buffer_info[i];
1124 cleaned = (i == eop);
1125
1126 if (cleaned) {
9ed318d5
TH		 1127 total_tx_packets += buffer_info->segs;
1128 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1129 if (buffer_info->skb) {
1130 bytes_compl += buffer_info->skb->len;
1131 pkts_compl++;
1132 }
bc7f75fa
AK		 1133 }
1134
1135 e1000_put_txbuf(adapter, buffer_info);
1136 tx_desc->upper.data = 0;
1137
1138 i++;
1139 if (i == tx_ring->count)
1140 i = 0;
1141 }
1142
dac87619
TL		 1143 if (i == tx_ring->next_to_use)
1144 break;
bc7f75fa
AK		 1145 eop = tx_ring->buffer_info[i].next_to_watch;
1146 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1147 }
1148
1149 tx_ring->next_to_clean = i;
1150
3f0cfa3b
TH		 1151 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1152
bc7f75fa 1153#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1154 if (count && netif_carrier_ok(netdev) &&
1155 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1156 /* Make sure that anybody stopping the queue after this
1157 * sees the new next_to_clean.
1158 */
1159 smp_mb();
1160
1161 if (netif_queue_stopped(netdev) &&
1162 !(test_bit(__E1000_DOWN, &adapter->state))) {
1163 netif_wake_queue(netdev);
1164 ++adapter->restart_queue;
1165 }
1166 }
1167
1168 if (adapter->detect_tx_hung) {
41cec6f1
BA		 1169 /*
1170 * Detect a transmit hang in hardware, this serializes the
1171 * check with the clearing of time_stamp and movement of i
1172 */
3db1cd5c 1173 adapter->detect_tx_hung = false;
12d04a3c
AD		 1174 if (tx_ring->buffer_info[i].time_stamp &&
1175 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1176 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1177 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1178 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1179 else
1180 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1181 }
1182 adapter->total_tx_bytes += total_tx_bytes;
1183 adapter->total_tx_packets += total_tx_packets;
807540ba 1184 return count < tx_ring->count;
bc7f75fa
AK		 1185}
1186
bc7f75fa
AK		 1187/**
1188 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1189 * @adapter: board private structure
1190 *
1191 * the return value indicates whether actual cleaning was done, there
1192 * is no guarantee that everything was cleaned
1193 **/
1194static bool e1000_clean_rx_irq_ps(struct e1000_adapter *adapter,
1195 int *work_done, int work_to_do)
1196{
3bb99fe2 1197 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1198 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1199 struct net_device *netdev = adapter->netdev;
1200 struct pci_dev *pdev = adapter->pdev;
1201 struct e1000_ring *rx_ring = adapter->rx_ring;
1202 struct e1000_buffer *buffer_info, *next_buffer;
1203 struct e1000_ps_page *ps_page;
1204 struct sk_buff *skb;
1205 unsigned int i, j;
1206 u32 length, staterr;
1207 int cleaned_count = 0;
3db1cd5c 1208 bool cleaned = false;
bc7f75fa
AK		 1209 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1210
1211 i = rx_ring->next_to_clean;
1212 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1213 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1214 buffer_info = &rx_ring->buffer_info[i];
1215
1216 while (staterr & E1000_RXD_STAT_DD) {
1217 if (*work_done >= work_to_do)
1218 break;
1219 (*work_done)++;
1220 skb = buffer_info->skb;
2d0bb1c1 1221 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1222
1223 /* in the packet split case this is header only */
1224 prefetch(skb->data - NET_IP_ALIGN);
1225
1226 i++;
1227 if (i == rx_ring->count)
1228 i = 0;
1229 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1230 prefetch(next_rxd);
1231
1232 next_buffer = &rx_ring->buffer_info[i];
1233
3db1cd5c 1234 cleaned = true;
bc7f75fa 1235 cleaned_count++;
0be3f55f 1236 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1237 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1238 buffer_info->dma = 0;
1239
af667a29 1240 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1241 if (!(staterr & E1000_RXD_STAT_EOP))
1242 adapter->flags2 |= FLAG2_IS_DISCARDING;
1243
1244 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1245 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1246 dev_kfree_skb_irq(skb);
b94b5028
JB		 1247 if (staterr & E1000_RXD_STAT_EOP)
1248 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1249 goto next_desc;
1250 }
1251
1252 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
1253 dev_kfree_skb_irq(skb);
1254 goto next_desc;
1255 }
1256
1257 length = le16_to_cpu(rx_desc->wb.middle.length0);
1258
1259 if (!length) {
ef456f85 1260 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1261 dev_kfree_skb_irq(skb);
1262 goto next_desc;
1263 }
1264
1265 /* Good Receive */
1266 skb_put(skb, length);
1267
1268 {
ad68076e
BA		 1269 /*
1270 * this looks ugly, but it seems compiler issues make it
1271 * more efficient than reusing j
1272 */
bc7f75fa
AK		 1273 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1274
ad68076e
BA		 1275 /*
1276 * page alloc/put takes too long and effects small packet
1277 * throughput, so unsplit small packets and save the alloc/put
1278 * only valid in softirq (napi) context to call kmap_*
1279 */
bc7f75fa
AK		 1280 if (l1 && (l1 <= copybreak) &&
1281 ((length + l1) <= adapter->rx_ps_bsize0)) {
1282 u8 *vaddr;
1283
47f44e40 1284 ps_page = &buffer_info->ps_pages[0];
bc7f75fa 1285
ad68076e
BA		 1286 /*
1287 * there is no documentation about how to call
bc7f75fa 1288 * kmap_atomic, so we can't hold the mapping
ad68076e
BA		 1289 * very long
1290 */
0be3f55f
NN		 1291 dma_sync_single_for_cpu(&pdev->dev, ps_page->dma,
1292 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa
AK		 1293 vaddr = kmap_atomic(ps_page->page, KM_SKB_DATA_SOFTIRQ);
1294 memcpy(skb_tail_pointer(skb), vaddr, l1);
1295 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
0be3f55f
NN		 1296 dma_sync_single_for_device(&pdev->dev, ps_page->dma,
1297 PAGE_SIZE, DMA_FROM_DEVICE);
140a7480 1298
eb7c3adb
JK		 1299 /* remove the CRC */
1300 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
1301 l1 -= 4;
1302
bc7f75fa
AK		 1303 skb_put(skb, l1);
1304 goto copydone;
1305 } /* if */
1306 }
1307
1308 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1309 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1310 if (!length)
1311 break;
1312
47f44e40 1313 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1314 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1315 DMA_FROM_DEVICE);
bc7f75fa
AK		 1316 ps_page->dma = 0;
1317 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1318 ps_page->page = NULL;
1319 skb->len += length;
1320 skb->data_len += length;
98a045d7 1321 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1322 }
1323
eb7c3adb
JK		 1324 /* strip the ethernet crc, problem is we're using pages now so
1325 * this whole operation can get a little cpu intensive
1326 */
1327 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
1328 pskb_trim(skb, skb->len - 4);
1329
bc7f75fa
AK		 1330copydone:
1331 total_rx_bytes += skb->len;
1332 total_rx_packets++;
1333
afd12939
BA		 1334 e1000_rx_checksum(adapter, staterr,
1335 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 1336
70495a50
BA		 1337 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1338
bc7f75fa
AK		 1339 if (rx_desc->wb.upper.header_status &
1340 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1341 adapter->rx_hdr_split++;
1342
1343 e1000_receive_skb(adapter, netdev, skb,
1344 staterr, rx_desc->wb.middle.vlan);
1345
1346next_desc:
1347 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1348 buffer_info->skb = NULL;
1349
1350 /* return some buffers to hardware, one at a time is too slow */
1351 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
c2fed996
JK		 1352 adapter->alloc_rx_buf(adapter, cleaned_count,
1353 GFP_ATOMIC);
bc7f75fa
AK		 1354 cleaned_count = 0;
1355 }
1356
1357 /* use prefetched values */
1358 rx_desc = next_rxd;
1359 buffer_info = next_buffer;
1360
1361 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1362 }
1363 rx_ring->next_to_clean = i;
1364
1365 cleaned_count = e1000_desc_unused(rx_ring);
1366 if (cleaned_count)
c2fed996 1367 adapter->alloc_rx_buf(adapter, cleaned_count, GFP_ATOMIC);
bc7f75fa 1368
bc7f75fa 1369 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1370 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1371 return cleaned;
1372}
1373
97ac8cae
BA		 1374/**
1375 * e1000_consume_page - helper function
1376 **/
1377static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1378 u16 length)
1379{
1380 bi->page = NULL;
1381 skb->len += length;
1382 skb->data_len += length;
98a045d7 1383 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1384}
1385
1386/**
1387 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1388 * @adapter: board private structure
1389 *
1390 * the return value indicates whether actual cleaning was done, there
1391 * is no guarantee that everything was cleaned
1392 **/
1393
1394static bool e1000_clean_jumbo_rx_irq(struct e1000_adapter *adapter,
1395 int *work_done, int work_to_do)
1396{
1397 struct net_device *netdev = adapter->netdev;
1398 struct pci_dev *pdev = adapter->pdev;
1399 struct e1000_ring *rx_ring = adapter->rx_ring;
5f450212 1400 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1401 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1402 u32 length, staterr;
97ac8cae
BA		 1403 unsigned int i;
1404 int cleaned_count = 0;
1405 bool cleaned = false;
1406 unsigned int total_rx_bytes=0, total_rx_packets=0;
1407
1408 i = rx_ring->next_to_clean;
5f450212
BA		 1409 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1410 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1411 buffer_info = &rx_ring->buffer_info[i];
1412
5f450212 1413 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1414 struct sk_buff *skb;
97ac8cae
BA		 1415
1416 if (*work_done >= work_to_do)
1417 break;
1418 (*work_done)++;
2d0bb1c1 1419 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1420
97ac8cae
BA		 1421 skb = buffer_info->skb;
1422 buffer_info->skb = NULL;
1423
1424 ++i;
1425 if (i == rx_ring->count)
1426 i = 0;
5f450212 1427 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1428 prefetch(next_rxd);
1429
1430 next_buffer = &rx_ring->buffer_info[i];
1431
1432 cleaned = true;
1433 cleaned_count++;
0be3f55f
NN		 1434 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1435 DMA_FROM_DEVICE);
97ac8cae
BA		 1436 buffer_info->dma = 0;
1437
5f450212 1438 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1439
1440 /* errors is only valid for DD + EOP descriptors */
5f450212
BA		 1441 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1442 (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK))) {
1443 /* recycle both page and skb */
1444 buffer_info->skb = skb;
1445 /* an error means any chain goes out the window too */
1446 if (rx_ring->rx_skb_top)
1447 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1448 rx_ring->rx_skb_top = NULL;
1449 goto next_desc;
97ac8cae
BA		 1450 }
1451
f0f1a172 1452#define rxtop (rx_ring->rx_skb_top)
5f450212 1453 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1454 /* this descriptor is only the beginning (or middle) */
1455 if (!rxtop) {
1456 /* this is the beginning of a chain */
1457 rxtop = skb;
1458 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1459 0, length);
1460 } else {
1461 /* this is the middle of a chain */
1462 skb_fill_page_desc(rxtop,
1463 skb_shinfo(rxtop)->nr_frags,
1464 buffer_info->page, 0, length);
1465 /* re-use the skb, only consumed the page */
1466 buffer_info->skb = skb;
1467 }
1468 e1000_consume_page(buffer_info, rxtop, length);
1469 goto next_desc;
1470 } else {
1471 if (rxtop) {
1472 /* end of the chain */
1473 skb_fill_page_desc(rxtop,
1474 skb_shinfo(rxtop)->nr_frags,
1475 buffer_info->page, 0, length);
1476 /* re-use the current skb, we only consumed the
1477 * page */
1478 buffer_info->skb = skb;
1479 skb = rxtop;
1480 rxtop = NULL;
1481 e1000_consume_page(buffer_info, skb, length);
1482 } else {
1483 /* no chain, got EOP, this buf is the packet
1484 * copybreak to save the put_page/alloc_page */
1485 if (length <= copybreak &&
1486 skb_tailroom(skb) >= length) {
1487 u8 *vaddr;
1488 vaddr = kmap_atomic(buffer_info->page,
1489 KM_SKB_DATA_SOFTIRQ);
1490 memcpy(skb_tail_pointer(skb), vaddr,
1491 length);
1492 kunmap_atomic(vaddr,
1493 KM_SKB_DATA_SOFTIRQ);
1494 /* re-use the page, so don't erase
1495 * buffer_info->page */
1496 skb_put(skb, length);
1497 } else {
1498 skb_fill_page_desc(skb, 0,
1499 buffer_info->page, 0,
1500 length);
1501 e1000_consume_page(buffer_info, skb,
1502 length);
1503 }
1504 }
1505 }
1506
1507 /* Receive Checksum Offload XXX recompute due to CRC strip? */
5f450212 1508 e1000_rx_checksum(adapter, staterr,
afd12939 1509 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
97ac8cae 1510
70495a50
BA		 1511 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1512
97ac8cae
BA		 1513 /* probably a little skewed due to removing CRC */
1514 total_rx_bytes += skb->len;
1515 total_rx_packets++;
1516
1517 /* eth type trans needs skb->data to point to something */
1518 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1519 e_err("pskb_may_pull failed.\n");
ef5ab89c 1520 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1521 goto next_desc;
1522 }
1523
5f450212
BA		 1524 e1000_receive_skb(adapter, netdev, skb, staterr,
1525 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1526
1527next_desc:
5f450212 1528 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1529
1530 /* return some buffers to hardware, one at a time is too slow */
1531 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
c2fed996
JK		 1532 adapter->alloc_rx_buf(adapter, cleaned_count,
1533 GFP_ATOMIC);
97ac8cae
BA		 1534 cleaned_count = 0;
1535 }
1536
1537 /* use prefetched values */
1538 rx_desc = next_rxd;
1539 buffer_info = next_buffer;
5f450212
BA		 1540
1541 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1542 }
1543 rx_ring->next_to_clean = i;
1544
1545 cleaned_count = e1000_desc_unused(rx_ring);
1546 if (cleaned_count)
c2fed996 1547 adapter->alloc_rx_buf(adapter, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1548
1549 adapter->total_rx_bytes += total_rx_bytes;
1550 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1551 return cleaned;
1552}
1553
bc7f75fa
AK		 1554/**
1555 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1556 * @adapter: board private structure
1557 **/
1558static void e1000_clean_rx_ring(struct e1000_adapter *adapter)
1559{
1560 struct e1000_ring *rx_ring = adapter->rx_ring;
1561 struct e1000_buffer *buffer_info;
1562 struct e1000_ps_page *ps_page;
1563 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1564 unsigned int i, j;
1565
1566 /* Free all the Rx ring sk_buffs */
1567 for (i = 0; i < rx_ring->count; i++) {
1568 buffer_info = &rx_ring->buffer_info[i];
1569 if (buffer_info->dma) {
1570 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1571 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1572 adapter->rx_buffer_len,
0be3f55f 1573 DMA_FROM_DEVICE);
97ac8cae 1574 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1575 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1576 PAGE_SIZE,
0be3f55f 1577 DMA_FROM_DEVICE);
bc7f75fa 1578 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1579 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1580 adapter->rx_ps_bsize0,
0be3f55f 1581 DMA_FROM_DEVICE);
bc7f75fa
AK		 1582 buffer_info->dma = 0;
1583 }
1584
97ac8cae
BA		 1585 if (buffer_info->page) {
1586 put_page(buffer_info->page);
1587 buffer_info->page = NULL;
1588 }
1589
bc7f75fa
AK		 1590 if (buffer_info->skb) {
1591 dev_kfree_skb(buffer_info->skb);
1592 buffer_info->skb = NULL;
1593 }
1594
1595 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1596 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1597 if (!ps_page->page)
1598 break;
0be3f55f
NN		 1599 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1600 DMA_FROM_DEVICE);
bc7f75fa
AK		 1601 ps_page->dma = 0;
1602 put_page(ps_page->page);
1603 ps_page->page = NULL;
1604 }
1605 }
1606
1607 /* there also may be some cached data from a chained receive */
1608 if (rx_ring->rx_skb_top) {
1609 dev_kfree_skb(rx_ring->rx_skb_top);
1610 rx_ring->rx_skb_top = NULL;
1611 }
1612
bc7f75fa
AK		 1613 /* Zero out the descriptor ring */
1614 memset(rx_ring->desc, 0, rx_ring->size);
1615
1616 rx_ring->next_to_clean = 0;
1617 rx_ring->next_to_use = 0;
b94b5028 1618 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1619
1620 writel(0, adapter->hw.hw_addr + rx_ring->head);
1621 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1622}
1623
a8f88ff5
JB		 1624static void e1000e_downshift_workaround(struct work_struct *work)
1625{
1626 struct e1000_adapter *adapter = container_of(work,
1627 struct e1000_adapter, downshift_task);
1628
615b32af
JB		 1629 if (test_bit(__E1000_DOWN, &adapter->state))
1630 return;
1631
a8f88ff5
JB		 1632 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1633}
1634
bc7f75fa
AK		 1635/**
1636 * e1000_intr_msi - Interrupt Handler
1637 * @irq: interrupt number
1638 * @data: pointer to a network interface device structure
1639 **/
1640static irqreturn_t e1000_intr_msi(int irq, void *data)
1641{
1642 struct net_device *netdev = data;
1643 struct e1000_adapter *adapter = netdev_priv(netdev);
1644 struct e1000_hw *hw = &adapter->hw;
1645 u32 icr = er32(ICR);
1646
ad68076e
BA		 1647 /*
1648 * read ICR disables interrupts using IAM
1649 */
bc7f75fa 1650
573cca8c 1651 if (icr & E1000_ICR_LSC) {
bc7f75fa 1652 hw->mac.get_link_status = 1;
ad68076e
BA		 1653 /*
1654 * ICH8 workaround-- Call gig speed drop workaround on cable
1655 * disconnect (LSC) before accessing any PHY registers
1656 */
bc7f75fa
AK		 1657 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1658 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1659 schedule_work(&adapter->downshift_task);
bc7f75fa 1660
ad68076e
BA		 1661 /*
1662 * 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1663 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1664 * adapter in watchdog
1665 */
bc7f75fa
AK		 1666 if (netif_carrier_ok(netdev) &&
1667 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1668 /* disable receives */
1669 u32 rctl = er32(RCTL);
1670 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1671 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1672 }
1673 /* guard against interrupt when we're going down */
1674 if (!test_bit(__E1000_DOWN, &adapter->state))
1675 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1676 }
1677
288379f0 1678 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1679 adapter->total_tx_bytes = 0;
1680 adapter->total_tx_packets = 0;
1681 adapter->total_rx_bytes = 0;
1682 adapter->total_rx_packets = 0;
288379f0 1683 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1684 }
1685
1686 return IRQ_HANDLED;
1687}
1688
1689/**
1690 * e1000_intr - Interrupt Handler
1691 * @irq: interrupt number
1692 * @data: pointer to a network interface device structure
1693 **/
1694static irqreturn_t e1000_intr(int irq, void *data)
1695{
1696 struct net_device *netdev = data;
1697 struct e1000_adapter *adapter = netdev_priv(netdev);
1698 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1699 u32 rctl, icr = er32(ICR);
4662e82b 1700
a68ea775 1701 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1702 return IRQ_NONE; /* Not our interrupt */
1703
ad68076e
BA		 1704 /*
1705 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1706 * not set, then the adapter didn't send an interrupt
1707 */
bc7f75fa
AK		 1708 if (!(icr & E1000_ICR_INT_ASSERTED))
1709 return IRQ_NONE;
1710
ad68076e
BA		 1711 /*
1712 * Interrupt Auto-Mask...upon reading ICR,
1713 * interrupts are masked. No need for the
1714 * IMC write
1715 */
bc7f75fa 1716
573cca8c 1717 if (icr & E1000_ICR_LSC) {
bc7f75fa 1718 hw->mac.get_link_status = 1;
ad68076e
BA		 1719 /*
1720 * ICH8 workaround-- Call gig speed drop workaround on cable
1721 * disconnect (LSC) before accessing any PHY registers
1722 */
bc7f75fa
AK		 1723 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1724 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1725 schedule_work(&adapter->downshift_task);
bc7f75fa 1726
ad68076e
BA		 1727 /*
1728 * 80003ES2LAN workaround--
bc7f75fa
AK		 1729 * For packet buffer work-around on link down event;
1730 * disable receives here in the ISR and
1731 * reset adapter in watchdog
1732 */
1733 if (netif_carrier_ok(netdev) &&
1734 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1735 /* disable receives */
1736 rctl = er32(RCTL);
1737 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1738 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1739 }
1740 /* guard against interrupt when we're going down */
1741 if (!test_bit(__E1000_DOWN, &adapter->state))
1742 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1743 }
1744
288379f0 1745 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1746 adapter->total_tx_bytes = 0;
1747 adapter->total_tx_packets = 0;
1748 adapter->total_rx_bytes = 0;
1749 adapter->total_rx_packets = 0;
288379f0 1750 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1751 }
1752
1753 return IRQ_HANDLED;
1754}
1755
4662e82b
BA		 1756static irqreturn_t e1000_msix_other(int irq, void *data)
1757{
1758 struct net_device *netdev = data;
1759 struct e1000_adapter *adapter = netdev_priv(netdev);
1760 struct e1000_hw *hw = &adapter->hw;
1761 u32 icr = er32(ICR);
1762
1763 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1764 if (!test_bit(__E1000_DOWN, &adapter->state))
1765 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1766 return IRQ_NONE;
1767 }
1768
1769 if (icr & adapter->eiac_mask)
1770 ew32(ICS, (icr & adapter->eiac_mask));
1771
1772 if (icr & E1000_ICR_OTHER) {
1773 if (!(icr & E1000_ICR_LSC))
1774 goto no_link_interrupt;
1775 hw->mac.get_link_status = 1;
1776 /* guard against interrupt when we're going down */
1777 if (!test_bit(__E1000_DOWN, &adapter->state))
1778 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1779 }
1780
1781no_link_interrupt:
a3c69fef
JB		 1782 if (!test_bit(__E1000_DOWN, &adapter->state))
1783 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1784
1785 return IRQ_HANDLED;
1786}
1787
1788
1789static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1790{
1791 struct net_device *netdev = data;
1792 struct e1000_adapter *adapter = netdev_priv(netdev);
1793 struct e1000_hw *hw = &adapter->hw;
1794 struct e1000_ring *tx_ring = adapter->tx_ring;
1795
1796
1797 adapter->total_tx_bytes = 0;
1798 adapter->total_tx_packets = 0;
1799
1800 if (!e1000_clean_tx_irq(adapter))
1801 /* Ring was not completely cleaned, so fire another interrupt */
1802 ew32(ICS, tx_ring->ims_val);
1803
1804 return IRQ_HANDLED;
1805}
1806
1807static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1808{
1809 struct net_device *netdev = data;
1810 struct e1000_adapter *adapter = netdev_priv(netdev);
1811
1812 /* Write the ITR value calculated at the end of the
1813 * previous interrupt.
1814 */
1815 if (adapter->rx_ring->set_itr) {
1816 writel(1000000000 / (adapter->rx_ring->itr_val * 256),
1817 adapter->hw.hw_addr + adapter->rx_ring->itr_register);
1818 adapter->rx_ring->set_itr = 0;
1819 }
1820
288379f0 1821 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1822 adapter->total_rx_bytes = 0;
1823 adapter->total_rx_packets = 0;
288379f0 1824 __napi_schedule(&adapter->napi);
4662e82b
BA		 1825 }
1826 return IRQ_HANDLED;
1827}
1828
1829/**
1830 * e1000_configure_msix - Configure MSI-X hardware
1831 *
1832 * e1000_configure_msix sets up the hardware to properly
1833 * generate MSI-X interrupts.
1834 **/
1835static void e1000_configure_msix(struct e1000_adapter *adapter)
1836{
1837 struct e1000_hw *hw = &adapter->hw;
1838 struct e1000_ring *rx_ring = adapter->rx_ring;
1839 struct e1000_ring *tx_ring = adapter->tx_ring;
1840 int vector = 0;
1841 u32 ctrl_ext, ivar = 0;
1842
1843 adapter->eiac_mask = 0;
1844
1845 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1846 if (hw->mac.type == e1000_82574) {
1847 u32 rfctl = er32(RFCTL);
1848 rfctl |= E1000_RFCTL_ACK_DIS;
1849 ew32(RFCTL, rfctl);
1850 }
1851
1852#define E1000_IVAR_INT_ALLOC_VALID 0x8
1853 /* Configure Rx vector */
1854 rx_ring->ims_val = E1000_IMS_RXQ0;
1855 adapter->eiac_mask |= rx_ring->ims_val;
1856 if (rx_ring->itr_val)
1857 writel(1000000000 / (rx_ring->itr_val * 256),
1858 hw->hw_addr + rx_ring->itr_register);
1859 else
1860 writel(1, hw->hw_addr + rx_ring->itr_register);
1861 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1862
1863 /* Configure Tx vector */
1864 tx_ring->ims_val = E1000_IMS_TXQ0;
1865 vector++;
1866 if (tx_ring->itr_val)
1867 writel(1000000000 / (tx_ring->itr_val * 256),
1868 hw->hw_addr + tx_ring->itr_register);
1869 else
1870 writel(1, hw->hw_addr + tx_ring->itr_register);
1871 adapter->eiac_mask |= tx_ring->ims_val;
1872 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1873
1874 /* set vector for Other Causes, e.g. link changes */
1875 vector++;
1876 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1877 if (rx_ring->itr_val)
1878 writel(1000000000 / (rx_ring->itr_val * 256),
1879 hw->hw_addr + E1000_EITR_82574(vector));
1880 else
1881 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1882
1883 /* Cause Tx interrupts on every write back */
1884 ivar |= (1 << 31);
1885
1886 ew32(IVAR, ivar);
1887
1888 /* enable MSI-X PBA support */
1889 ctrl_ext = er32(CTRL_EXT);
1890 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1891
1892 /* Auto-Mask Other interrupts upon ICR read */
1893#define E1000_EIAC_MASK_82574 0x01F00000
1894 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1895 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1896 ew32(CTRL_EXT, ctrl_ext);
1897 e1e_flush();
1898}
1899
1900void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
1901{
1902 if (adapter->msix_entries) {
1903 pci_disable_msix(adapter->pdev);
1904 kfree(adapter->msix_entries);
1905 adapter->msix_entries = NULL;
1906 } else if (adapter->flags & FLAG_MSI_ENABLED) {
1907 pci_disable_msi(adapter->pdev);
1908 adapter->flags &= ~FLAG_MSI_ENABLED;
1909 }
4662e82b
BA		 1910}
1911
1912/**
1913 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1914 *
1915 * Attempt to configure interrupts using the best available
1916 * capabilities of the hardware and kernel.
1917 **/
1918void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
1919{
1920 int err;
8e86acd7 1921 int i;
4662e82b
BA		 1922
1923 switch (adapter->int_mode) {
1924 case E1000E_INT_MODE_MSIX:
1925 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 1926 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
1927 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 1928 sizeof(struct msix_entry),
1929 GFP_KERNEL);
1930 if (adapter->msix_entries) {
8e86acd7 1931 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 1932 adapter->msix_entries[i].entry = i;
1933
1934 err = pci_enable_msix(adapter->pdev,
1935 adapter->msix_entries,
8e86acd7 1936 adapter->num_vectors);
b1cdfead 1937 if (err == 0)
4662e82b
BA		 1938 return;
1939 }
1940 /* MSI-X failed, so fall through and try MSI */
ef456f85 1941 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 1942 e1000e_reset_interrupt_capability(adapter);
1943 }
1944 adapter->int_mode = E1000E_INT_MODE_MSI;
1945 /* Fall through */
1946 case E1000E_INT_MODE_MSI:
1947 if (!pci_enable_msi(adapter->pdev)) {
1948 adapter->flags |= FLAG_MSI_ENABLED;
1949 } else {
1950 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 1951 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 1952 }
1953 /* Fall through */
1954 case E1000E_INT_MODE_LEGACY:
1955 /* Don't do anything; this is the system default */
1956 break;
1957 }
8e86acd7
JK		 1958
1959 /* store the number of vectors being used */
1960 adapter->num_vectors = 1;
4662e82b
BA		 1961}
1962
1963/**
1964 * e1000_request_msix - Initialize MSI-X interrupts
1965 *
1966 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1967 * kernel.
1968 **/
1969static int e1000_request_msix(struct e1000_adapter *adapter)
1970{
1971 struct net_device *netdev = adapter->netdev;
1972 int err = 0, vector = 0;
1973
1974 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1975 snprintf(adapter->rx_ring->name,
1976 sizeof(adapter->rx_ring->name) - 1,
1977 "%s-rx-0", netdev->name);
4662e82b
BA		 1978 else
1979 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
1980 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1981 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 1982 netdev);
1983 if (err)
1984 goto out;
1985 adapter->rx_ring->itr_register = E1000_EITR_82574(vector);
1986 adapter->rx_ring->itr_val = adapter->itr;
1987 vector++;
1988
1989 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1990 snprintf(adapter->tx_ring->name,
1991 sizeof(adapter->tx_ring->name) - 1,
1992 "%s-tx-0", netdev->name);
4662e82b
BA		 1993 else
1994 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
1995 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1996 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 1997 netdev);
1998 if (err)
1999 goto out;
2000 adapter->tx_ring->itr_register = E1000_EITR_82574(vector);
2001 adapter->tx_ring->itr_val = adapter->itr;
2002 vector++;
2003
2004 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2005 e1000_msix_other, 0, netdev->name, netdev);
4662e82b
BA		 2006 if (err)
2007 goto out;
2008
2009 e1000_configure_msix(adapter);
2010 return 0;
2011out:
2012 return err;
2013}
2014
f8d59f78
BA		 2015/**
2016 * e1000_request_irq - initialize interrupts
2017 *
2018 * Attempts to configure interrupts using the best available
2019 * capabilities of the hardware and kernel.
2020 **/
bc7f75fa
AK		 2021static int e1000_request_irq(struct e1000_adapter *adapter)
2022{
2023 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2024 int err;
2025
4662e82b
BA		 2026 if (adapter->msix_entries) {
2027 err = e1000_request_msix(adapter);
2028 if (!err)
2029 return err;
2030 /* fall back to MSI */
2031 e1000e_reset_interrupt_capability(adapter);
2032 adapter->int_mode = E1000E_INT_MODE_MSI;
2033 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2034 }
4662e82b 2035 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2036 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2037 netdev->name, netdev);
2038 if (!err)
2039 return err;
bc7f75fa 2040
4662e82b
BA		 2041 /* fall back to legacy interrupt */
2042 e1000e_reset_interrupt_capability(adapter);
2043 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2044 }
2045
a0607fd3 2046 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2047 netdev->name, netdev);
2048 if (err)
2049 e_err("Unable to allocate interrupt, Error: %d\n", err);
2050
bc7f75fa
AK		 2051 return err;
2052}
2053
2054static void e1000_free_irq(struct e1000_adapter *adapter)
2055{
2056 struct net_device *netdev = adapter->netdev;
2057
4662e82b
BA		 2058 if (adapter->msix_entries) {
2059 int vector = 0;
2060
2061 free_irq(adapter->msix_entries[vector].vector, netdev);
2062 vector++;
2063
2064 free_irq(adapter->msix_entries[vector].vector, netdev);
2065 vector++;
2066
2067 /* Other Causes interrupt vector */
2068 free_irq(adapter->msix_entries[vector].vector, netdev);
2069 return;
bc7f75fa 2070 }
4662e82b
BA		 2071
2072 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2073}
2074
2075/**
2076 * e1000_irq_disable - Mask off interrupt generation on the NIC
2077 **/
2078static void e1000_irq_disable(struct e1000_adapter *adapter)
2079{
2080 struct e1000_hw *hw = &adapter->hw;
2081
bc7f75fa 2082 ew32(IMC, ~0);
4662e82b
BA		 2083 if (adapter->msix_entries)
2084 ew32(EIAC_82574, 0);
bc7f75fa 2085 e1e_flush();
8e86acd7
JK		 2086
2087 if (adapter->msix_entries) {
2088 int i;
2089 for (i = 0; i < adapter->num_vectors; i++)
2090 synchronize_irq(adapter->msix_entries[i].vector);
2091 } else {
2092 synchronize_irq(adapter->pdev->irq);
2093 }
bc7f75fa
AK		 2094}
2095
2096/**
2097 * e1000_irq_enable - Enable default interrupt generation settings
2098 **/
2099static void e1000_irq_enable(struct e1000_adapter *adapter)
2100{
2101 struct e1000_hw *hw = &adapter->hw;
2102
4662e82b
BA		 2103 if (adapter->msix_entries) {
2104 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2105 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2106 } else {
2107 ew32(IMS, IMS_ENABLE_MASK);
2108 }
74ef9c39 2109 e1e_flush();
bc7f75fa
AK		 2110}
2111
2112/**
31dbe5b4 2113 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2114 * @adapter: address of board private structure
2115 *
31dbe5b4 2116 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2117 * For ASF and Pass Through versions of f/w this means that
2118 * the driver is loaded. For AMT version (only with 82573)
2119 * of the f/w this means that the network i/f is open.
2120 **/
31dbe5b4 2121void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2122{
2123 struct e1000_hw *hw = &adapter->hw;
2124 u32 ctrl_ext;
2125 u32 swsm;
2126
2127 /* Let firmware know the driver has taken over */
2128 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2129 swsm = er32(SWSM);
2130 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2131 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2132 ctrl_ext = er32(CTRL_EXT);
ad68076e 2133 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2134 }
2135}
2136
2137/**
31dbe5b4 2138 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2139 * @adapter: address of board private structure
2140 *
31dbe5b4 2141 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2142 * For ASF and Pass Through versions of f/w this means that the
2143 * driver is no longer loaded. For AMT version (only with 82573) i
2144 * of the f/w this means that the network i/f is closed.
2145 *
2146 **/
31dbe5b4 2147void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2148{
2149 struct e1000_hw *hw = &adapter->hw;
2150 u32 ctrl_ext;
2151 u32 swsm;
2152
2153 /* Let firmware taken over control of h/w */
2154 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2155 swsm = er32(SWSM);
2156 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2157 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2158 ctrl_ext = er32(CTRL_EXT);
ad68076e 2159 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2160 }
2161}
2162
bc7f75fa
AK		 2163/**
2164 * @e1000_alloc_ring - allocate memory for a ring structure
2165 **/
2166static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2167 struct e1000_ring *ring)
2168{
2169 struct pci_dev *pdev = adapter->pdev;
2170
2171 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2172 GFP_KERNEL);
2173 if (!ring->desc)
2174 return -ENOMEM;
2175
2176 return 0;
2177}
2178
2179/**
2180 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2181 * @adapter: board private structure
2182 *
2183 * Return 0 on success, negative on failure
2184 **/
2185int e1000e_setup_tx_resources(struct e1000_adapter *adapter)
2186{
2187 struct e1000_ring *tx_ring = adapter->tx_ring;
2188 int err = -ENOMEM, size;
2189
2190 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2191 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2192 if (!tx_ring->buffer_info)
2193 goto err;
bc7f75fa
AK		 2194
2195 /* round up to nearest 4K */
2196 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2197 tx_ring->size = ALIGN(tx_ring->size, 4096);
2198
2199 err = e1000_alloc_ring_dma(adapter, tx_ring);
2200 if (err)
2201 goto err;
2202
2203 tx_ring->next_to_use = 0;
2204 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2205
2206 return 0;
2207err:
2208 vfree(tx_ring->buffer_info);
44defeb3 2209 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2210 return err;
2211}
2212
2213/**
2214 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2215 * @adapter: board private structure
2216 *
2217 * Returns 0 on success, negative on failure
2218 **/
2219int e1000e_setup_rx_resources(struct e1000_adapter *adapter)
2220{
2221 struct e1000_ring *rx_ring = adapter->rx_ring;
47f44e40
AK		 2222 struct e1000_buffer *buffer_info;
2223 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2224
2225 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2226 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2227 if (!rx_ring->buffer_info)
2228 goto err;
bc7f75fa 2229
47f44e40
AK		 2230 for (i = 0; i < rx_ring->count; i++) {
2231 buffer_info = &rx_ring->buffer_info[i];
2232 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2233 sizeof(struct e1000_ps_page),
2234 GFP_KERNEL);
2235 if (!buffer_info->ps_pages)
2236 goto err_pages;
2237 }
bc7f75fa
AK		 2238
2239 desc_len = sizeof(union e1000_rx_desc_packet_split);
2240
2241 /* Round up to nearest 4K */
2242 rx_ring->size = rx_ring->count * desc_len;
2243 rx_ring->size = ALIGN(rx_ring->size, 4096);
2244
2245 err = e1000_alloc_ring_dma(adapter, rx_ring);
2246 if (err)
47f44e40 2247 goto err_pages;
bc7f75fa
AK		 2248
2249 rx_ring->next_to_clean = 0;
2250 rx_ring->next_to_use = 0;
2251 rx_ring->rx_skb_top = NULL;
2252
2253 return 0;
47f44e40
AK		 2254
2255err_pages:
2256 for (i = 0; i < rx_ring->count; i++) {
2257 buffer_info = &rx_ring->buffer_info[i];
2258 kfree(buffer_info->ps_pages);
2259 }
bc7f75fa
AK		 2260err:
2261 vfree(rx_ring->buffer_info);
e9262447 2262 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2263 return err;
2264}
2265
2266/**
2267 * e1000_clean_tx_ring - Free Tx Buffers
2268 * @adapter: board private structure
2269 **/
2270static void e1000_clean_tx_ring(struct e1000_adapter *adapter)
2271{
2272 struct e1000_ring *tx_ring = adapter->tx_ring;
2273 struct e1000_buffer *buffer_info;
2274 unsigned long size;
2275 unsigned int i;
2276
2277 for (i = 0; i < tx_ring->count; i++) {
2278 buffer_info = &tx_ring->buffer_info[i];
2279 e1000_put_txbuf(adapter, buffer_info);
2280 }
2281
3f0cfa3b 2282 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2283 size = sizeof(struct e1000_buffer) * tx_ring->count;
2284 memset(tx_ring->buffer_info, 0, size);
2285
2286 memset(tx_ring->desc, 0, tx_ring->size);
2287
2288 tx_ring->next_to_use = 0;
2289 tx_ring->next_to_clean = 0;
2290
2291 writel(0, adapter->hw.hw_addr + tx_ring->head);
2292 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2293}
2294
2295/**
2296 * e1000e_free_tx_resources - Free Tx Resources per Queue
2297 * @adapter: board private structure
2298 *
2299 * Free all transmit software resources
2300 **/
2301void e1000e_free_tx_resources(struct e1000_adapter *adapter)
2302{
2303 struct pci_dev *pdev = adapter->pdev;
2304 struct e1000_ring *tx_ring = adapter->tx_ring;
2305
2306 e1000_clean_tx_ring(adapter);
2307
2308 vfree(tx_ring->buffer_info);
2309 tx_ring->buffer_info = NULL;
2310
2311 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2312 tx_ring->dma);
2313 tx_ring->desc = NULL;
2314}
2315
2316/**
2317 * e1000e_free_rx_resources - Free Rx Resources
2318 * @adapter: board private structure
2319 *
2320 * Free all receive software resources
2321 **/
2322
2323void e1000e_free_rx_resources(struct e1000_adapter *adapter)
2324{
2325 struct pci_dev *pdev = adapter->pdev;
2326 struct e1000_ring *rx_ring = adapter->rx_ring;
47f44e40 2327 int i;
bc7f75fa
AK		 2328
2329 e1000_clean_rx_ring(adapter);
2330
b1cdfead 2331 for (i = 0; i < rx_ring->count; i++)
47f44e40 2332 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2333
bc7f75fa
AK		 2334 vfree(rx_ring->buffer_info);
2335 rx_ring->buffer_info = NULL;
2336
bc7f75fa
AK		 2337 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2338 rx_ring->dma);
2339 rx_ring->desc = NULL;
2340}
2341
2342/**
2343 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2344 * @adapter: pointer to adapter
2345 * @itr_setting: current adapter->itr
2346 * @packets: the number of packets during this measurement interval
2347 * @bytes: the number of bytes during this measurement interval
2348 *
bc7f75fa
AK		 2349 * Stores a new ITR value based on packets and byte
2350 * counts during the last interrupt. The advantage of per interrupt
2351 * computation is faster updates and more accurate ITR for the current
2352 * traffic pattern. Constants in this function were computed
2353 * based on theoretical maximum wire speed and thresholds were set based
2354 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2355 * while increasing bulk throughput. This functionality is controlled
2356 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2357 **/
2358static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2359 u16 itr_setting, int packets,
2360 int bytes)
2361{
2362 unsigned int retval = itr_setting;
2363
2364 if (packets == 0)
2365 goto update_itr_done;
2366
2367 switch (itr_setting) {
2368 case lowest_latency:
2369 /* handle TSO and jumbo frames */
2370 if (bytes/packets > 8000)
2371 retval = bulk_latency;
b1cdfead 2372 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2373 retval = low_latency;
bc7f75fa
AK		 2374 break;
2375 case low_latency: /* 50 usec aka 20000 ints/s */
2376 if (bytes > 10000) {
2377 /* this if handles the TSO accounting */
b1cdfead 2378 if (bytes/packets > 8000)
bc7f75fa 2379 retval = bulk_latency;
b1cdfead 2380 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2381 retval = bulk_latency;
b1cdfead 2382 else if ((packets > 35))
bc7f75fa 2383 retval = lowest_latency;
bc7f75fa
AK		 2384 } else if (bytes/packets > 2000) {
2385 retval = bulk_latency;
2386 } else if (packets <= 2 && bytes < 512) {
2387 retval = lowest_latency;
2388 }
2389 break;
2390 case bulk_latency: /* 250 usec aka 4000 ints/s */
2391 if (bytes > 25000) {
b1cdfead 2392 if (packets > 35)
bc7f75fa 2393 retval = low_latency;
bc7f75fa
AK		 2394 } else if (bytes < 6000) {
2395 retval = low_latency;
2396 }
2397 break;
2398 }
2399
2400update_itr_done:
2401 return retval;
2402}
2403
2404static void e1000_set_itr(struct e1000_adapter *adapter)
2405{
2406 struct e1000_hw *hw = &adapter->hw;
2407 u16 current_itr;
2408 u32 new_itr = adapter->itr;
2409
2410 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2411 if (adapter->link_speed != SPEED_1000) {
2412 current_itr = 0;
2413 new_itr = 4000;
2414 goto set_itr_now;
2415 }
2416
828bac87
BA		 2417 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2418 new_itr = 0;
2419 goto set_itr_now;
2420 }
2421
bc7f75fa
AK		 2422 adapter->tx_itr = e1000_update_itr(adapter,
2423 adapter->tx_itr,
2424 adapter->total_tx_packets,
2425 adapter->total_tx_bytes);
2426 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2427 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2428 adapter->tx_itr = low_latency;
2429
2430 adapter->rx_itr = e1000_update_itr(adapter,
2431 adapter->rx_itr,
2432 adapter->total_rx_packets,
2433 adapter->total_rx_bytes);
2434 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2435 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2436 adapter->rx_itr = low_latency;
2437
2438 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2439
2440 switch (current_itr) {
2441 /* counts and packets in update_itr are dependent on these numbers */
2442 case lowest_latency:
2443 new_itr = 70000;
2444 break;
2445 case low_latency:
2446 new_itr = 20000; /* aka hwitr = ~200 */
2447 break;
2448 case bulk_latency:
2449 new_itr = 4000;
2450 break;
2451 default:
2452 break;
2453 }
2454
2455set_itr_now:
2456 if (new_itr != adapter->itr) {
ad68076e
BA		 2457 /*
2458 * this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2459 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2460 * increasing
2461 */
bc7f75fa
AK		 2462 new_itr = new_itr > adapter->itr ?
2463 min(adapter->itr + (new_itr >> 2), new_itr) :
2464 new_itr;
2465 adapter->itr = new_itr;
4662e82b
BA		 2466 adapter->rx_ring->itr_val = new_itr;
2467 if (adapter->msix_entries)
2468 adapter->rx_ring->set_itr = 1;
2469 else
828bac87
BA		 2470 if (new_itr)
2471 ew32(ITR, 1000000000 / (new_itr * 256));
2472 else
2473 ew32(ITR, 0);
bc7f75fa
AK		 2474 }
2475}
2476
4662e82b
BA		 2477/**
2478 * e1000_alloc_queues - Allocate memory for all rings
2479 * @adapter: board private structure to initialize
2480 **/
2481static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
2482{
2483 adapter->tx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
2484 if (!adapter->tx_ring)
2485 goto err;
2486
2487 adapter->rx_ring = kzalloc(sizeof(struct e1000_ring), GFP_KERNEL);
2488 if (!adapter->rx_ring)
2489 goto err;
2490
2491 return 0;
2492err:
2493 e_err("Unable to allocate memory for queues\n");
2494 kfree(adapter->rx_ring);
2495 kfree(adapter->tx_ring);
2496 return -ENOMEM;
2497}
2498
bc7f75fa
AK		 2499/**
2500 * e1000_clean - NAPI Rx polling callback
ad68076e 2501 * @napi: struct associated with this polling callback
489815ce 2502 * @budget: amount of packets driver is allowed to process this poll
bc7f75fa
AK		 2503 **/
2504static int e1000_clean(struct napi_struct *napi, int budget)
2505{
2506 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
4662e82b 2507 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2508 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2509 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2510
4cf1653a 2511 adapter = netdev_priv(poll_dev);
bc7f75fa 2512
4662e82b
BA		 2513 if (adapter->msix_entries &&
2514 !(adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2515 goto clean_rx;
2516
92af3e95 2517 tx_cleaned = e1000_clean_tx_irq(adapter);
bc7f75fa 2518
4662e82b 2519clean_rx:
bc7f75fa 2520 adapter->clean_rx(adapter, &work_done, budget);
d2c7ddd6 2521
12d04a3c 2522 if (!tx_cleaned)
d2c7ddd6 2523 work_done = budget;
bc7f75fa 2524
53e52c72
DM		 2525 /* If budget not fully consumed, exit the polling mode */
2526 if (work_done < budget) {
bc7f75fa
AK		 2527 if (adapter->itr_setting & 3)
2528 e1000_set_itr(adapter);
288379f0 2529 napi_complete(napi);
a3c69fef
JB		 2530 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2531 if (adapter->msix_entries)
2532 ew32(IMS, adapter->rx_ring->ims_val);
2533 else
2534 e1000_irq_enable(adapter);
2535 }
bc7f75fa
AK		 2536 }
2537
2538 return work_done;
2539}
2540
8e586137 2541static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2542{
2543 struct e1000_adapter *adapter = netdev_priv(netdev);
2544 struct e1000_hw *hw = &adapter->hw;
2545 u32 vfta, index;
2546
2547 /* don't update vlan cookie if already programmed */
2548 if ((adapter->hw.mng_cookie.status &
2549 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2550 (vid == adapter->mng_vlan_id))
8e586137 2551 return 0;
caaddaf8 2552
bc7f75fa 2553 /* add VID to filter table */
caaddaf8
BA		 2554 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2555 index = (vid >> 5) & 0x7F;
2556 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2557 vfta |= (1 << (vid & 0x1F));
2558 hw->mac.ops.write_vfta(hw, index, vfta);
2559 }
86d70e53
JK		 2560
2561 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2562
2563 return 0;
bc7f75fa
AK		 2564}
2565
8e586137 2566static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2567{
2568 struct e1000_adapter *adapter = netdev_priv(netdev);
2569 struct e1000_hw *hw = &adapter->hw;
2570 u32 vfta, index;
2571
bc7f75fa
AK		 2572 if ((adapter->hw.mng_cookie.status &
2573 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2574 (vid == adapter->mng_vlan_id)) {
2575 /* release control to f/w */
31dbe5b4 2576 e1000e_release_hw_control(adapter);
8e586137 2577 return 0;
bc7f75fa
AK		 2578 }
2579
2580 /* remove VID from filter table */
caaddaf8
BA		 2581 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2582 index = (vid >> 5) & 0x7F;
2583 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2584 vfta &= ~(1 << (vid & 0x1F));
2585 hw->mac.ops.write_vfta(hw, index, vfta);
2586 }
86d70e53
JK		 2587
2588 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2589
2590 return 0;
bc7f75fa
AK		 2591}
2592
86d70e53
JK		 2593/**
2594 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2595 * @adapter: board private structure to initialize
2596 **/
2597static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2598{
2599 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2600 struct e1000_hw *hw = &adapter->hw;
2601 u32 rctl;
bc7f75fa 2602
86d70e53
JK		 2603 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2604 /* disable VLAN receive filtering */
2605 rctl = er32(RCTL);
2606 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2607 ew32(RCTL, rctl);
2608
2609 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2610 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2611 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2612 }
bc7f75fa
AK		 2613 }
2614}
2615
86d70e53
JK		 2616/**
2617 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2618 * @adapter: board private structure to initialize
2619 **/
2620static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2621{
2622 struct e1000_hw *hw = &adapter->hw;
2623 u32 rctl;
2624
2625 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2626 /* enable VLAN receive filtering */
2627 rctl = er32(RCTL);
2628 rctl |= E1000_RCTL_VFE;
2629 rctl &= ~E1000_RCTL_CFIEN;
2630 ew32(RCTL, rctl);
2631 }
2632}
bc7f75fa 2633
86d70e53
JK		 2634/**
2635 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2636 * @adapter: board private structure to initialize
2637 **/
2638static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2639{
bc7f75fa 2640 struct e1000_hw *hw = &adapter->hw;
86d70e53 2641 u32 ctrl;
bc7f75fa 2642
86d70e53
JK		 2643 /* disable VLAN tag insert/strip */
2644 ctrl = er32(CTRL);
2645 ctrl &= ~E1000_CTRL_VME;
2646 ew32(CTRL, ctrl);
2647}
bc7f75fa 2648
86d70e53
JK		 2649/**
2650 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2651 * @adapter: board private structure to initialize
2652 **/
2653static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2654{
2655 struct e1000_hw *hw = &adapter->hw;
2656 u32 ctrl;
bc7f75fa 2657
86d70e53
JK		 2658 /* enable VLAN tag insert/strip */
2659 ctrl = er32(CTRL);
2660 ctrl |= E1000_CTRL_VME;
2661 ew32(CTRL, ctrl);
2662}
bc7f75fa 2663
86d70e53
JK		 2664static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2665{
2666 struct net_device *netdev = adapter->netdev;
2667 u16 vid = adapter->hw.mng_cookie.vlan_id;
2668 u16 old_vid = adapter->mng_vlan_id;
2669
2670 if (adapter->hw.mng_cookie.status &
2671 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2672 e1000_vlan_rx_add_vid(netdev, vid);
2673 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2674 }
2675
86d70e53
JK		 2676 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2677 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2678}
2679
2680static void e1000_restore_vlan(struct e1000_adapter *adapter)
2681{
2682 u16 vid;
2683
86d70e53 2684 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2685
86d70e53 2686 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2687 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2688}
2689
cd791618 2690static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2691{
2692 struct e1000_hw *hw = &adapter->hw;
cd791618 2693 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2694
2695 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2696 return;
2697
2698 manc = er32(MANC);
2699
ad68076e
BA		 2700 /*
2701 * enable receiving management packets to the host. this will probably
bc7f75fa 2702 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2703 * the packets will be handled on SMBUS
2704 */
bc7f75fa
AK		 2705 manc |= E1000_MANC_EN_MNG2HOST;
2706 manc2h = er32(MANC2H);
cd791618
BA		 2707
2708 switch (hw->mac.type) {
2709 default:
2710 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2711 break;
2712 case e1000_82574:
2713 case e1000_82583:
2714 /*
2715 * Check if IPMI pass-through decision filter already exists;
2716 * if so, enable it.
2717 */
2718 for (i = 0, j = 0; i < 8; i++) {
2719 mdef = er32(MDEF(i));
2720
2721 /* Ignore filters with anything other than IPMI ports */
3b21b508 2722 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2723 continue;
2724
2725 /* Enable this decision filter in MANC2H */
2726 if (mdef)
2727 manc2h |= (1 << i);
2728
2729 j |= mdef;
2730 }
2731
2732 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2733 break;
2734
2735 /* Create new decision filter in an empty filter */
2736 for (i = 0, j = 0; i < 8; i++)
2737 if (er32(MDEF(i)) == 0) {
2738 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2739 E1000_MDEF_PORT_664));
2740 manc2h |= (1 << 1);
2741 j++;
2742 break;
2743 }
2744
2745 if (!j)
2746 e_warn("Unable to create IPMI pass-through filter\n");
2747 break;
2748 }
2749
bc7f75fa
AK		 2750 ew32(MANC2H, manc2h);
2751 ew32(MANC, manc);
2752}
2753
2754/**
af667a29 2755 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2756 * @adapter: board private structure
2757 *
2758 * Configure the Tx unit of the MAC after a reset.
2759 **/
2760static void e1000_configure_tx(struct e1000_adapter *adapter)
2761{
2762 struct e1000_hw *hw = &adapter->hw;
2763 struct e1000_ring *tx_ring = adapter->tx_ring;
2764 u64 tdba;
2765 u32 tdlen, tctl, tipg, tarc;
2766 u32 ipgr1, ipgr2;
2767
2768 /* Setup the HW Tx Head and Tail descriptor pointers */
2769 tdba = tx_ring->dma;
2770 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
284901a9 2771 ew32(TDBAL, (tdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 2772 ew32(TDBAH, (tdba >> 32));
2773 ew32(TDLEN, tdlen);
2774 ew32(TDH, 0);
2775 ew32(TDT, 0);
2776 tx_ring->head = E1000_TDH;
2777 tx_ring->tail = E1000_TDT;
2778
2779 /* Set the default values for the Tx Inter Packet Gap timer */
2780 tipg = DEFAULT_82543_TIPG_IPGT_COPPER; /* 8 */
2781 ipgr1 = DEFAULT_82543_TIPG_IPGR1; /* 8 */
2782 ipgr2 = DEFAULT_82543_TIPG_IPGR2; /* 6 */
2783
2784 if (adapter->flags & FLAG_TIPG_MEDIUM_FOR_80003ESLAN)
2785 ipgr2 = DEFAULT_80003ES2LAN_TIPG_IPGR2; /* 7 */
2786
2787 tipg |= ipgr1 << E1000_TIPG_IPGR1_SHIFT;
2788 tipg |= ipgr2 << E1000_TIPG_IPGR2_SHIFT;
2789 ew32(TIPG, tipg);
2790
2791 /* Set the Tx Interrupt Delay register */
2792 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2793 /* Tx irq moderation */
bc7f75fa
AK		 2794 ew32(TADV, adapter->tx_abs_int_delay);
2795
3a3b7586
JB		 2796 if (adapter->flags2 & FLAG2_DMA_BURST) {
2797 u32 txdctl = er32(TXDCTL(0));
2798 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2799 E1000_TXDCTL_WTHRESH);
2800 /*
2801 * set up some performance related parameters to encourage the
2802 * hardware to use the bus more efficiently in bursts, depends
2803 * on the tx_int_delay to be enabled,
2804 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2805 * hthresh = 1 ==> prefetch when one or more available
2806 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2807 * BEWARE: this seems to work but should be considered first if
af667a29 2808 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2809 */
2810 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2811 ew32(TXDCTL(0), txdctl);
2812 /* erratum work around: set txdctl the same for both queues */
2813 ew32(TXDCTL(1), txdctl);
2814 }
2815
bc7f75fa
AK		 2816 /* Program the Transmit Control Register */
2817 tctl = er32(TCTL);
2818 tctl &= ~E1000_TCTL_CT;
2819 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2820 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2821
2822 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2823 tarc = er32(TARC(0));
ad68076e
BA		 2824 /*
2825 * set the speed mode bit, we'll clear it if we're not at
2826 * gigabit link later
2827 */
bc7f75fa
AK		 2828#define SPEED_MODE_BIT (1 << 21)
2829 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2830 ew32(TARC(0), tarc);
bc7f75fa
AK		 2831 }
2832
2833 /* errata: program both queues to unweighted RR */
2834 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2835 tarc = er32(TARC(0));
bc7f75fa 2836 tarc |= 1;
e9ec2c0f
JK		 2837 ew32(TARC(0), tarc);
2838 tarc = er32(TARC(1));
bc7f75fa 2839 tarc |= 1;
e9ec2c0f 2840 ew32(TARC(1), tarc);
bc7f75fa
AK		 2841 }
2842
bc7f75fa
AK		 2843 /* Setup Transmit Descriptor Settings for eop descriptor */
2844 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2845
2846 /* only set IDE if we are delaying interrupts using the timers */
2847 if (adapter->tx_int_delay)
2848 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2849
2850 /* enable Report Status bit */
2851 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2852
2853 ew32(TCTL, tctl);
2854
edfea6e6 2855 e1000e_config_collision_dist(hw);
bc7f75fa
AK		 2856}
2857
2858/**
2859 * e1000_setup_rctl - configure the receive control registers
2860 * @adapter: Board private structure
2861 **/
2862#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2863 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2864static void e1000_setup_rctl(struct e1000_adapter *adapter)
2865{
2866 struct e1000_hw *hw = &adapter->hw;
2867 u32 rctl, rfctl;
bc7f75fa
AK		 2868 u32 pages = 0;
2869
a1ce6473
BA		 2870 /* Workaround Si errata on 82579 - configure jumbo frame flow */
2871 if (hw->mac.type == e1000_pch2lan) {
2872 s32 ret_val;
2873
2874 if (adapter->netdev->mtu > ETH_DATA_LEN)
2875 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2876 else
2877 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2878
2879 if (ret_val)
2880 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2881 }
2882
bc7f75fa
AK		 2883 /* Program MC offset vector base */
2884 rctl = er32(RCTL);
2885 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2886 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2887 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2888 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2889
2890 /* Do not Store bad packets */
2891 rctl &= ~E1000_RCTL_SBP;
2892
2893 /* Enable Long Packet receive */
2894 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2895 rctl &= ~E1000_RCTL_LPE;
2896 else
2897 rctl |= E1000_RCTL_LPE;
2898
eb7c3adb
JK		 2899 /* Some systems expect that the CRC is included in SMBUS traffic. The
2900 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2901 * host memory when this is enabled
2902 */
2903 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2904 rctl |= E1000_RCTL_SECRC;
5918bd88 2905
a4f58f54
BA		 2906 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2907 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2908 u16 phy_data;
2909
2910 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2911 phy_data &= 0xfff8;
2912 phy_data |= (1 << 2);
2913 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2914
2915 e1e_rphy(hw, 22, &phy_data);
2916 phy_data &= 0x0fff;
2917 phy_data |= (1 << 14);
2918 e1e_wphy(hw, 0x10, 0x2823);
2919 e1e_wphy(hw, 0x11, 0x0003);
2920 e1e_wphy(hw, 22, phy_data);
2921 }
2922
bc7f75fa
AK		 2923 /* Setup buffer sizes */
2924 rctl &= ~E1000_RCTL_SZ_4096;
2925 rctl |= E1000_RCTL_BSEX;
2926 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 2927 case 2048:
2928 default:
2929 rctl |= E1000_RCTL_SZ_2048;
2930 rctl &= ~E1000_RCTL_BSEX;
2931 break;
2932 case 4096:
2933 rctl |= E1000_RCTL_SZ_4096;
2934 break;
2935 case 8192:
2936 rctl |= E1000_RCTL_SZ_8192;
2937 break;
2938 case 16384:
2939 rctl |= E1000_RCTL_SZ_16384;
2940 break;
2941 }
2942
5f450212
BA		 2943 /* Enable Extended Status in all Receive Descriptors */
2944 rfctl = er32(RFCTL);
2945 rfctl |= E1000_RFCTL_EXTEN;
2946
bc7f75fa
AK		 2947 /*
2948 * 82571 and greater support packet-split where the protocol
2949 * header is placed in skb->data and the packet data is
2950 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2951 * In the case of a non-split, skb->data is linearly filled,
2952 * followed by the page buffers. Therefore, skb->data is
2953 * sized to hold the largest protocol header.
2954 *
2955 * allocations using alloc_page take too long for regular MTU
2956 * so only enable packet split for jumbo frames
2957 *
2958 * Using pages when the page size is greater than 16k wastes
2959 * a lot of memory, since we allocate 3 pages at all times
2960 * per packet.
2961 */
bc7f75fa 2962 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
dbcb9fec 2963 if (!(adapter->flags & FLAG_HAS_ERT) && (pages <= 3) &&
97ac8cae 2964 (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 2965 adapter->rx_ps_pages = pages;
97ac8cae
BA		 2966 else
2967 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 2968
2969 if (adapter->rx_ps_pages) {
90da0669
BA		 2970 u32 psrctl = 0;
2971
ad68076e
BA		 2972 /*
2973 * disable packet split support for IPv6 extension headers,
2974 * because some malformed IPv6 headers can hang the Rx
2975 */
bc7f75fa
AK		 2976 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
2977 E1000_RFCTL_NEW_IPV6_EXT_DIS);
2978
140a7480
AK		 2979 /* Enable Packet split descriptors */
2980 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 2981
2982 psrctl |= adapter->rx_ps_bsize0 >>
2983 E1000_PSRCTL_BSIZE0_SHIFT;
2984
2985 switch (adapter->rx_ps_pages) {
2986 case 3:
2987 psrctl |= PAGE_SIZE <<
2988 E1000_PSRCTL_BSIZE3_SHIFT;
2989 case 2:
2990 psrctl |= PAGE_SIZE <<
2991 E1000_PSRCTL_BSIZE2_SHIFT;
2992 case 1:
2993 psrctl |= PAGE_SIZE >>
2994 E1000_PSRCTL_BSIZE1_SHIFT;
2995 break;
2996 }
2997
2998 ew32(PSRCTL, psrctl);
2999 }
3000
5f450212 3001 ew32(RFCTL, rfctl);
bc7f75fa 3002 ew32(RCTL, rctl);
318a94d6
JK		 3003 /* just started the receive unit, no need to restart */
3004 adapter->flags &= ~FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 3005}
3006
3007/**
3008 * e1000_configure_rx - Configure Receive Unit after Reset
3009 * @adapter: board private structure
3010 *
3011 * Configure the Rx unit of the MAC after a reset.
3012 **/
3013static void e1000_configure_rx(struct e1000_adapter *adapter)
3014{
3015 struct e1000_hw *hw = &adapter->hw;
3016 struct e1000_ring *rx_ring = adapter->rx_ring;
3017 u64 rdba;
3018 u32 rdlen, rctl, rxcsum, ctrl_ext;
3019
3020 if (adapter->rx_ps_pages) {
3021 /* this is a 32 byte descriptor */
3022 rdlen = rx_ring->count *
af667a29 3023 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3024 adapter->clean_rx = e1000_clean_rx_irq_ps;
3025 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3026 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3027 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3028 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3029 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3030 } else {
5f450212 3031 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3032 adapter->clean_rx = e1000_clean_rx_irq;
3033 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3034 }
3035
3036 /* disable receives while setting up the descriptors */
3037 rctl = er32(RCTL);
7f99ae63
BA		 3038 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3039 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3040 e1e_flush();
1bba4386 3041 usleep_range(10000, 20000);
bc7f75fa 3042
3a3b7586
JB		 3043 if (adapter->flags2 & FLAG2_DMA_BURST) {
3044 /*
3045 * set the writeback threshold (only takes effect if the RDTR
3046 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3047 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3048 * granularity = 01
3049 * wthresh = 04,
3050 * hthresh = 04,
3051 * pthresh = 0x20
3052 */
3053 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3054 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3055
3056 /*
3057 * override the delay timers for enabling bursting, only if
3058 * the value was not set by the user via module options
3059 */
3060 if (adapter->rx_int_delay == DEFAULT_RDTR)
3061 adapter->rx_int_delay = BURST_RDTR;
3062 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3063 adapter->rx_abs_int_delay = BURST_RADV;
3064 }
3065
bc7f75fa
AK		 3066 /* set the Receive Delay Timer Register */
3067 ew32(RDTR, adapter->rx_int_delay);
3068
3069 /* irq moderation */
3070 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3071 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
ad68076e 3072 ew32(ITR, 1000000000 / (adapter->itr * 256));
bc7f75fa
AK		 3073
3074 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3075 /* Auto-Mask interrupts upon ICR access */
3076 ctrl_ext |= E1000_CTRL_EXT_IAME;
3077 ew32(IAM, 0xffffffff);
3078 ew32(CTRL_EXT, ctrl_ext);
3079 e1e_flush();
3080
ad68076e
BA		 3081 /*
3082 * Setup the HW Rx Head and Tail Descriptor Pointers and
3083 * the Base and Length of the Rx Descriptor Ring
3084 */
bc7f75fa 3085 rdba = rx_ring->dma;
284901a9 3086 ew32(RDBAL, (rdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 3087 ew32(RDBAH, (rdba >> 32));
3088 ew32(RDLEN, rdlen);
3089 ew32(RDH, 0);
3090 ew32(RDT, 0);
3091 rx_ring->head = E1000_RDH;
3092 rx_ring->tail = E1000_RDT;
3093
3094 /* Enable Receive Checksum Offload for TCP and UDP */
3095 rxcsum = er32(RXCSUM);
dc221294 3096 if (adapter->netdev->features & NETIF_F_RXCSUM) {
bc7f75fa
AK		 3097 rxcsum |= E1000_RXCSUM_TUOFL;
3098
ad68076e
BA		 3099 /*
3100 * IPv4 payload checksum for UDP fragments must be
3101 * used in conjunction with packet-split.
3102 */
bc7f75fa
AK		 3103 if (adapter->rx_ps_pages)
3104 rxcsum |= E1000_RXCSUM_IPPCSE;
3105 } else {
3106 rxcsum &= ~E1000_RXCSUM_TUOFL;
3107 /* no need to clear IPPCSE as it defaults to 0 */
3108 }
3109 ew32(RXCSUM, rxcsum);
3110
ad68076e
BA		 3111 /*
3112 * Enable early receives on supported devices, only takes effect when
bc7f75fa 3113 * packet size is equal or larger than the specified value (in 8 byte
ad68076e
BA		 3114 * units), e.g. using jumbo frames when setting to E1000_ERT_2048
3115 */
828bac87
BA		 3116 if ((adapter->flags & FLAG_HAS_ERT) ||
3117 (adapter->hw.mac.type == e1000_pch2lan)) {
53ec5498
BA		 3118 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3119 u32 rxdctl = er32(RXDCTL(0));
3120 ew32(RXDCTL(0), rxdctl | 0x3);
828bac87
BA		 3121 if (adapter->flags & FLAG_HAS_ERT)
3122 ew32(ERT, E1000_ERT_2048 | (1 << 13));
53ec5498
BA		 3123 /*
3124 * With jumbo frames and early-receive enabled,
3125 * excessive C-state transition latencies result in
3126 * dropped transactions.
3127 */
af667a29 3128 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3129 } else {
af667a29
BA		 3130 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3131 PM_QOS_DEFAULT_VALUE);
53ec5498 3132 }
97ac8cae 3133 }
bc7f75fa
AK		 3134
3135 /* Enable Receives */
3136 ew32(RCTL, rctl);
3137}
3138
3139/**
ef9b965a
JB		 3140 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3141 * @netdev: network interface device structure
bc7f75fa 3142 *
ef9b965a
JB		 3143 * Writes multicast address list to the MTA hash table.
3144 * Returns: -ENOMEM on failure
3145 * 0 on no addresses written
3146 * X on writing X addresses to MTA
3147 */
3148static int e1000e_write_mc_addr_list(struct net_device *netdev)
3149{
3150 struct e1000_adapter *adapter = netdev_priv(netdev);
3151 struct e1000_hw *hw = &adapter->hw;
3152 struct netdev_hw_addr *ha;
3153 u8 *mta_list;
3154 int i;
3155
3156 if (netdev_mc_empty(netdev)) {
3157 /* nothing to program, so clear mc list */
3158 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3159 return 0;
3160 }
3161
3162 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3163 if (!mta_list)
3164 return -ENOMEM;
3165
3166 /* update_mc_addr_list expects a packed array of only addresses. */
3167 i = 0;
3168 netdev_for_each_mc_addr(ha, netdev)
3169 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3170
3171 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3172 kfree(mta_list);
3173
3174 return netdev_mc_count(netdev);
3175}
3176
3177/**
3178 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3179 * @netdev: network interface device structure
bc7f75fa 3180 *
ef9b965a
JB		 3181 * Writes unicast address list to the RAR table.
3182 * Returns: -ENOMEM on failure/insufficient address space
3183 * 0 on no addresses written
3184 * X on writing X addresses to the RAR table
bc7f75fa 3185 **/
ef9b965a 3186static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3187{
ef9b965a
JB		 3188 struct e1000_adapter *adapter = netdev_priv(netdev);
3189 struct e1000_hw *hw = &adapter->hw;
3190 unsigned int rar_entries = hw->mac.rar_entry_count;
3191 int count = 0;
3192
3193 /* save a rar entry for our hardware address */
3194 rar_entries--;
3195
3196 /* save a rar entry for the LAA workaround */
3197 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3198 rar_entries--;
3199
3200 /* return ENOMEM indicating insufficient memory for addresses */
3201 if (netdev_uc_count(netdev) > rar_entries)
3202 return -ENOMEM;
3203
3204 if (!netdev_uc_empty(netdev) && rar_entries) {
3205 struct netdev_hw_addr *ha;
3206
3207 /*
3208 * write the addresses in reverse order to avoid write
3209 * combining
3210 */
3211 netdev_for_each_uc_addr(ha, netdev) {
3212 if (!rar_entries)
3213 break;
3214 e1000e_rar_set(hw, ha->addr, rar_entries--);
3215 count++;
3216 }
3217 }
3218
3219 /* zero out the remaining RAR entries not used above */
3220 for (; rar_entries > 0; rar_entries--) {
3221 ew32(RAH(rar_entries), 0);
3222 ew32(RAL(rar_entries), 0);
3223 }
3224 e1e_flush();
3225
3226 return count;
bc7f75fa
AK		 3227}
3228
3229/**
ef9b965a 3230 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3231 * @netdev: network interface device structure
3232 *
ef9b965a
JB		 3233 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3234 * address list or the network interface flags are updated. This routine is
3235 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3236 * promiscuous mode, and all-multi behavior.
3237 **/
ef9b965a 3238static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3239{
3240 struct e1000_adapter *adapter = netdev_priv(netdev);
3241 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3242 u32 rctl;
bc7f75fa
AK		 3243
3244 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3245 rctl = er32(RCTL);
3246
ef9b965a
JB		 3247 /* clear the affected bits */
3248 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3249
bc7f75fa
AK		 3250 if (netdev->flags & IFF_PROMISC) {
3251 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3252 /* Do not hardware filter VLANs in promisc mode */
3253 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3254 } else {
ef9b965a 3255 int count;
746b9f02
PM		 3256 if (netdev->flags & IFF_ALLMULTI) {
3257 rctl |= E1000_RCTL_MPE;
746b9f02 3258 } else {
ef9b965a
JB		 3259 /*
3260 * Write addresses to the MTA, if the attempt fails
3261 * then we should just turn on promiscuous mode so
3262 * that we can at least receive multicast traffic
3263 */
3264 count = e1000e_write_mc_addr_list(netdev);
3265 if (count < 0)
3266 rctl |= E1000_RCTL_MPE;
746b9f02 3267 }
86d70e53 3268 e1000e_vlan_filter_enable(adapter);
bc7f75fa 3269 /*
ef9b965a
JB		 3270 * Write addresses to available RAR registers, if there is not
3271 * sufficient space to store all the addresses then enable
3272 * unicast promiscuous mode
bc7f75fa 3273 */
ef9b965a
JB		 3274 count = e1000e_write_uc_addr_list(netdev);
3275 if (count < 0)
3276 rctl |= E1000_RCTL_UPE;
bc7f75fa 3277 }
86d70e53 3278
ef9b965a
JB		 3279 ew32(RCTL, rctl);
3280
86d70e53
JK		 3281 if (netdev->features & NETIF_F_HW_VLAN_RX)
3282 e1000e_vlan_strip_enable(adapter);
3283 else
3284 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3285}
3286
70495a50
BA		 3287static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3288{
3289 struct e1000_hw *hw = &adapter->hw;
3290 u32 mrqc, rxcsum;
3291 int i;
3292 static const u32 rsskey[10] = {
3293 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3294 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3295 };
3296
3297 /* Fill out hash function seed */
3298 for (i = 0; i < 10; i++)
3299 ew32(RSSRK(i), rsskey[i]);
3300
3301 /* Direct all traffic to queue 0 */
3302 for (i = 0; i < 32; i++)
3303 ew32(RETA(i), 0);
3304
3305 /*
3306 * Disable raw packet checksumming so that RSS hash is placed in
3307 * descriptor on writeback.
3308 */
3309 rxcsum = er32(RXCSUM);
3310 rxcsum |= E1000_RXCSUM_PCSD;
3311
3312 ew32(RXCSUM, rxcsum);
3313
3314 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3315 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3316 E1000_MRQC_RSS_FIELD_IPV6 |
3317 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3318 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3319
3320 ew32(MRQC, mrqc);
3321}
3322
bc7f75fa 3323/**
ad68076e 3324 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3325 * @adapter: private board structure
3326 **/
3327static void e1000_configure(struct e1000_adapter *adapter)
3328{
ef9b965a 3329 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3330
3331 e1000_restore_vlan(adapter);
cd791618 3332 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3333
3334 e1000_configure_tx(adapter);
70495a50
BA		 3335
3336 if (adapter->netdev->features & NETIF_F_RXHASH)
3337 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3338 e1000_setup_rctl(adapter);
3339 e1000_configure_rx(adapter);
c2fed996
JK		 3340 adapter->alloc_rx_buf(adapter, e1000_desc_unused(adapter->rx_ring),
3341 GFP_KERNEL);
bc7f75fa
AK		 3342}
3343
3344/**
3345 * e1000e_power_up_phy - restore link in case the phy was powered down
3346 * @adapter: address of board private structure
3347 *
3348 * The phy may be powered down to save power and turn off link when the
3349 * driver is unloaded and wake on lan is not enabled (among others)
3350 * *** this routine MUST be followed by a call to e1000e_reset ***
3351 **/
3352void e1000e_power_up_phy(struct e1000_adapter *adapter)
3353{
17f208de
BA		 3354 if (adapter->hw.phy.ops.power_up)
3355 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3356
3357 adapter->hw.mac.ops.setup_link(&adapter->hw);
3358}
3359
3360/**
3361 * e1000_power_down_phy - Power down the PHY
3362 *
17f208de
BA		 3363 * Power down the PHY so no link is implied when interface is down.
3364 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3365 */
3366static void e1000_power_down_phy(struct e1000_adapter *adapter)
3367{
bc7f75fa 3368 /* WoL is enabled */
23b66e2b 3369 if (adapter->wol)
bc7f75fa
AK		 3370 return;
3371
17f208de
BA		 3372 if (adapter->hw.phy.ops.power_down)
3373 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3374}
3375
3376/**
3377 * e1000e_reset - bring the hardware into a known good state
3378 *
3379 * This function boots the hardware and enables some settings that
3380 * require a configuration cycle of the hardware - those cannot be
3381 * set/changed during runtime. After reset the device needs to be
ad68076e 3382 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3383 */
3384void e1000e_reset(struct e1000_adapter *adapter)
3385{
3386 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3387 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3388 struct e1000_hw *hw = &adapter->hw;
3389 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3390 u32 pba = adapter->pba;
bc7f75fa
AK		 3391 u16 hwm;
3392
ad68076e 3393 /* reset Packet Buffer Allocation to default */
318a94d6 3394 ew32(PBA, pba);
df762464 3395
318a94d6 3396 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
ad68076e
BA		 3397 /*
3398 * To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3399 * large enough to accommodate two full transmit packets,
3400 * rounded up to the next 1KB and expressed in KB. Likewise,
3401 * the Rx FIFO should be large enough to accommodate at least
3402 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3403 * expressed in KB.
3404 */
df762464 3405 pba = er32(PBA);
bc7f75fa 3406 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3407 tx_space = pba >> 16;
bc7f75fa 3408 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3409 pba &= 0xffff;
ad68076e 3410 /*
af667a29 3411 * the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3412 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3413 */
3414 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3415 sizeof(struct e1000_tx_desc) -
3416 ETH_FCS_LEN) * 2;
3417 min_tx_space = ALIGN(min_tx_space, 1024);
3418 min_tx_space >>= 10;
3419 /* software strips receive CRC, so leave room for it */
318a94d6 3420 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3421 min_rx_space = ALIGN(min_rx_space, 1024);
3422 min_rx_space >>= 10;
3423
ad68076e
BA		 3424 /*
3425 * If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3426 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3427 * allocation, take space away from current Rx allocation
3428 */
df762464
AK		 3429 if ((tx_space < min_tx_space) &&
3430 ((min_tx_space - tx_space) < pba)) {
3431 pba -= min_tx_space - tx_space;
bc7f75fa 3432
ad68076e 3433 /*
af667a29 3434 * if short on Rx space, Rx wins and must trump Tx
ad68076e
BA		 3435 * adjustment or use Early Receive if available
3436 */
df762464 3437 if ((pba < min_rx_space) &&
bc7f75fa
AK		 3438 (!(adapter->flags & FLAG_HAS_ERT)))
3439 /* ERT enabled in e1000_configure_rx */
df762464 3440 pba = min_rx_space;
bc7f75fa 3441 }
df762464
AK		 3442
3443 ew32(PBA, pba);
bc7f75fa
AK		 3444 }
3445
ad68076e
BA		 3446 /*
3447 * flow control settings
3448 *
38eb394e 3449 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3450 * (or the size used for early receive) above it in the Rx FIFO.
3451 * Set it to the lower of:
3452 * - 90% of the Rx FIFO size, and
3453 * - the full Rx FIFO size minus the early receive size (for parts
3454 * with ERT support assuming ERT set to E1000_ERT_2048), or
38eb394e 3455 * - the full Rx FIFO size minus one full frame
ad68076e 3456 */
d3738bb8
BA		 3457 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3458 fc->pause_time = 0xFFFF;
3459 else
3460 fc->pause_time = E1000_FC_PAUSE_TIME;
3461 fc->send_xon = 1;
3462 fc->current_mode = fc->requested_mode;
3463
3464 switch (hw->mac.type) {
3465 default:
3466 if ((adapter->flags & FLAG_HAS_ERT) &&
3467 (adapter->netdev->mtu > ETH_DATA_LEN))
3468 hwm = min(((pba << 10) * 9 / 10),
3469 ((pba << 10) - (E1000_ERT_2048 << 3)));
3470 else
3471 hwm = min(((pba << 10) * 9 / 10),
3472 ((pba << 10) - adapter->max_frame_size));
3473
3474 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3475 fc->low_water = fc->high_water - 8;
3476 break;
3477 case e1000_pchlan:
38eb394e
BA		 3478 /*
3479 * Workaround PCH LOM adapter hangs with certain network
3480 * loads. If hangs persist, try disabling Tx flow control.
3481 */
3482 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3483 fc->high_water = 0x3500;
3484 fc->low_water = 0x1500;
3485 } else {
3486 fc->high_water = 0x5000;
3487 fc->low_water = 0x3000;
3488 }
a305595b 3489 fc->refresh_time = 0x1000;
d3738bb8
BA		 3490 break;
3491 case e1000_pch2lan:
3492 fc->high_water = 0x05C20;
3493 fc->low_water = 0x05048;
3494 fc->pause_time = 0x0650;
3495 fc->refresh_time = 0x0400;
828bac87
BA		 3496 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3497 pba = 14;
3498 ew32(PBA, pba);
3499 }
d3738bb8 3500 break;
38eb394e 3501 }
bc7f75fa 3502
828bac87
BA		 3503 /*
3504 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
3505 * fit in receive buffer and early-receive not supported.
3506 */
3507 if (adapter->itr_setting & 0x3) {
3508 if (((adapter->max_frame_size * 2) > (pba << 10)) &&
3509 !(adapter->flags & FLAG_HAS_ERT)) {
3510 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3511 dev_info(&adapter->pdev->dev,
3512 "Interrupt Throttle Rate turned off\n");
3513 adapter->flags2 |= FLAG2_DISABLE_AIM;
3514 ew32(ITR, 0);
3515 }
3516 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3517 dev_info(&adapter->pdev->dev,
3518 "Interrupt Throttle Rate turned on\n");
3519 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3520 adapter->itr = 20000;
3521 ew32(ITR, 1000000000 / (adapter->itr * 256));
3522 }
3523 }
3524
bc7f75fa
AK		 3525 /* Allow time for pending master requests to run */
3526 mac->ops.reset_hw(hw);
97ac8cae
BA		 3527
3528 /*
3529 * For parts with AMT enabled, let the firmware know
3530 * that the network interface is in control
3531 */
c43bc57e 3532 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3533 e1000e_get_hw_control(adapter);
97ac8cae 3534
bc7f75fa
AK		 3535 ew32(WUC, 0);
3536
3537 if (mac->ops.init_hw(hw))
44defeb3 3538 e_err("Hardware Error\n");
bc7f75fa
AK		 3539
3540 e1000_update_mng_vlan(adapter);
3541
3542 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3543 ew32(VET, ETH_P_8021Q);
3544
3545 e1000e_reset_adaptive(hw);
31dbe5b4
BA		 3546
3547 if (!netif_running(adapter->netdev) &&
3548 !test_bit(__E1000_TESTING, &adapter->state)) {
3549 e1000_power_down_phy(adapter);
3550 return;
3551 }
3552
bc7f75fa
AK		 3553 e1000_get_phy_info(hw);
3554
918d7197
BA		 3555 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3556 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3557 u16 phy_data = 0;
ad68076e
BA		 3558 /*
3559 * speed up time to link by disabling smart power down, ignore
bc7f75fa 3560 * the return value of this function because there is nothing
ad68076e
BA		 3561 * different we would do if it failed
3562 */
bc7f75fa
AK		 3563 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3564 phy_data &= ~IGP02E1000_PM_SPD;
3565 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3566 }
bc7f75fa
AK		 3567}
3568
3569int e1000e_up(struct e1000_adapter *adapter)
3570{
3571 struct e1000_hw *hw = &adapter->hw;
3572
3573 /* hardware has been reset, we need to reload some things */
3574 e1000_configure(adapter);
3575
3576 clear_bit(__E1000_DOWN, &adapter->state);
3577
4662e82b
BA		 3578 if (adapter->msix_entries)
3579 e1000_configure_msix(adapter);
bc7f75fa
AK		 3580 e1000_irq_enable(adapter);
3581
400484fa 3582 netif_start_queue(adapter->netdev);
4cb9be7a 3583
bc7f75fa 3584 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3585 if (adapter->msix_entries)
3586 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3587 else
3588 ew32(ICS, E1000_ICS_LSC);
3589
bc7f75fa
AK		 3590 return 0;
3591}
3592
713b3c9e
JB		 3593static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3594{
3595 struct e1000_hw *hw = &adapter->hw;
3596
3597 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3598 return;
3599
3600 /* flush pending descriptor writebacks to memory */
3601 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3602 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3603
3604 /* execute the writes immediately */
3605 e1e_flush();
3606}
3607
67fd4fcb
JK		 3608static void e1000e_update_stats(struct e1000_adapter *adapter);
3609
bc7f75fa
AK		 3610void e1000e_down(struct e1000_adapter *adapter)
3611{
3612 struct net_device *netdev = adapter->netdev;
3613 struct e1000_hw *hw = &adapter->hw;
3614 u32 tctl, rctl;
3615
ad68076e
BA		 3616 /*
3617 * signal that we're down so the interrupt handler does not
3618 * reschedule our watchdog timer
3619 */
bc7f75fa
AK		 3620 set_bit(__E1000_DOWN, &adapter->state);
3621
3622 /* disable receives in the hardware */
3623 rctl = er32(RCTL);
7f99ae63
BA		 3624 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3625 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3626 /* flush and sleep below */
3627
4cb9be7a 3628 netif_stop_queue(netdev);
bc7f75fa
AK		 3629
3630 /* disable transmits in the hardware */
3631 tctl = er32(TCTL);
3632 tctl &= ~E1000_TCTL_EN;
3633 ew32(TCTL, tctl);
7f99ae63 3634
bc7f75fa
AK		 3635 /* flush both disables and wait for them to finish */
3636 e1e_flush();
1bba4386 3637 usleep_range(10000, 20000);
bc7f75fa 3638
bc7f75fa
AK		 3639 e1000_irq_disable(adapter);
3640
3641 del_timer_sync(&adapter->watchdog_timer);
3642 del_timer_sync(&adapter->phy_info_timer);
3643
bc7f75fa 3644 netif_carrier_off(netdev);
67fd4fcb
JK		 3645
3646 spin_lock(&adapter->stats64_lock);
3647 e1000e_update_stats(adapter);
3648 spin_unlock(&adapter->stats64_lock);
3649
400484fa
BA		 3650 e1000e_flush_descriptors(adapter);
3651 e1000_clean_tx_ring(adapter);
3652 e1000_clean_rx_ring(adapter);
3653
bc7f75fa
AK		 3654 adapter->link_speed = 0;
3655 adapter->link_duplex = 0;
3656
52cc3086
JK		 3657 if (!pci_channel_offline(adapter->pdev))
3658 e1000e_reset(adapter);
713b3c9e 3659
bc7f75fa
AK		 3660 /*
3661 * TODO: for power management, we could drop the link and
3662 * pci_disable_device here.
3663 */
3664}
3665
3666void e1000e_reinit_locked(struct e1000_adapter *adapter)
3667{
3668 might_sleep();
3669 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3670 usleep_range(1000, 2000);
bc7f75fa
AK		 3671 e1000e_down(adapter);
3672 e1000e_up(adapter);
3673 clear_bit(__E1000_RESETTING, &adapter->state);
3674}
3675
3676/**
3677 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3678 * @adapter: board private structure to initialize
3679 *
3680 * e1000_sw_init initializes the Adapter private data structure.
3681 * Fields are initialized based on PCI device information and
3682 * OS network device settings (MTU size).
3683 **/
3684static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
3685{
bc7f75fa
AK		 3686 struct net_device *netdev = adapter->netdev;
3687
3688 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3689 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3690 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3691 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
bc7f75fa 3692
67fd4fcb
JK		 3693 spin_lock_init(&adapter->stats64_lock);
3694
4662e82b 3695 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3696
4662e82b
BA		 3697 if (e1000_alloc_queues(adapter))
3698 return -ENOMEM;
bc7f75fa 3699
bc7f75fa 3700 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3701 e1000_irq_disable(adapter);
3702
bc7f75fa
AK		 3703 set_bit(__E1000_DOWN, &adapter->state);
3704 return 0;
bc7f75fa
AK		 3705}
3706
f8d59f78
BA		 3707/**
3708 * e1000_intr_msi_test - Interrupt Handler
3709 * @irq: interrupt number
3710 * @data: pointer to a network interface device structure
3711 **/
3712static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3713{
3714 struct net_device *netdev = data;
3715 struct e1000_adapter *adapter = netdev_priv(netdev);
3716 struct e1000_hw *hw = &adapter->hw;
3717 u32 icr = er32(ICR);
3718
3bb99fe2 3719 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 3720 if (icr & E1000_ICR_RXSEQ) {
3721 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
3722 wmb();
3723 }
3724
3725 return IRQ_HANDLED;
3726}
3727
3728/**
3729 * e1000_test_msi_interrupt - Returns 0 for successful test
3730 * @adapter: board private struct
3731 *
3732 * code flow taken from tg3.c
3733 **/
3734static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3735{
3736 struct net_device *netdev = adapter->netdev;
3737 struct e1000_hw *hw = &adapter->hw;
3738 int err;
3739
3740 /* poll_enable hasn't been called yet, so don't need disable */
3741 /* clear any pending events */
3742 er32(ICR);
3743
3744 /* free the real vector and request a test handler */
3745 e1000_free_irq(adapter);
4662e82b 3746 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 3747
3748 /* Assume that the test fails, if it succeeds then the test
3749 * MSI irq handler will unset this flag */
3750 adapter->flags |= FLAG_MSI_TEST_FAILED;
3751
3752 err = pci_enable_msi(adapter->pdev);
3753 if (err)
3754 goto msi_test_failed;
3755
a0607fd3 3756 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 3757 netdev->name, netdev);
3758 if (err) {
3759 pci_disable_msi(adapter->pdev);
3760 goto msi_test_failed;
3761 }
3762
3763 wmb();
3764
3765 e1000_irq_enable(adapter);
3766
3767 /* fire an unusual interrupt on the test handler */
3768 ew32(ICS, E1000_ICS_RXSEQ);
3769 e1e_flush();
3770 msleep(50);
3771
3772 e1000_irq_disable(adapter);
3773
3774 rmb();
3775
3776 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 3777 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30
JD		 3778 e_info("MSI interrupt test failed, using legacy interrupt.\n");
3779 } else
3780 e_dbg("MSI interrupt test succeeded!\n");
f8d59f78
BA		 3781
3782 free_irq(adapter->pdev->irq, netdev);
3783 pci_disable_msi(adapter->pdev);
3784
f8d59f78 3785msi_test_failed:
4662e82b 3786 e1000e_set_interrupt_capability(adapter);
068e8a30 3787 return e1000_request_irq(adapter);
f8d59f78
BA		 3788}
3789
3790/**
3791 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3792 * @adapter: board private struct
3793 *
3794 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3795 **/
3796static int e1000_test_msi(struct e1000_adapter *adapter)
3797{
3798 int err;
3799 u16 pci_cmd;
3800
3801 if (!(adapter->flags & FLAG_MSI_ENABLED))
3802 return 0;
3803
3804 /* disable SERR in case the MSI write causes a master abort */
3805 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 3806 if (pci_cmd & PCI_COMMAND_SERR)
3807 pci_write_config_word(adapter->pdev, PCI_COMMAND,
3808 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 3809
3810 err = e1000_test_msi_interrupt(adapter);
3811
36f2407f
DN		 3812 /* re-enable SERR */
3813 if (pci_cmd & PCI_COMMAND_SERR) {
3814 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
3815 pci_cmd |= PCI_COMMAND_SERR;
3816 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
3817 }
f8d59f78 3818
f8d59f78
BA		 3819 return err;
3820}
3821
bc7f75fa
AK		 3822/**
3823 * e1000_open - Called when a network interface is made active
3824 * @netdev: network interface device structure
3825 *
3826 * Returns 0 on success, negative value on failure
3827 *
3828 * The open entry point is called when a network interface is made
3829 * active by the system (IFF_UP). At this point all resources needed
3830 * for transmit and receive operations are allocated, the interrupt
3831 * handler is registered with the OS, the watchdog timer is started,
3832 * and the stack is notified that the interface is ready.
3833 **/
3834static int e1000_open(struct net_device *netdev)
3835{
3836 struct e1000_adapter *adapter = netdev_priv(netdev);
3837 struct e1000_hw *hw = &adapter->hw;
23606cf5 3838 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3839 int err;
3840
3841 /* disallow open during test */
3842 if (test_bit(__E1000_TESTING, &adapter->state))
3843 return -EBUSY;
3844
23606cf5
RW		 3845 pm_runtime_get_sync(&pdev->dev);
3846
9c563d20
JB		 3847 netif_carrier_off(netdev);
3848
bc7f75fa
AK		 3849 /* allocate transmit descriptors */
3850 err = e1000e_setup_tx_resources(adapter);
3851 if (err)
3852 goto err_setup_tx;
3853
3854 /* allocate receive descriptors */
3855 err = e1000e_setup_rx_resources(adapter);
3856 if (err)
3857 goto err_setup_rx;
3858
11b08be8
BA		 3859 /*
3860 * If AMT is enabled, let the firmware know that the network
3861 * interface is now open and reset the part to a known state.
3862 */
3863 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 3864 e1000e_get_hw_control(adapter);
11b08be8
BA		 3865 e1000e_reset(adapter);
3866 }
3867
bc7f75fa
AK		 3868 e1000e_power_up_phy(adapter);
3869
3870 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3871 if ((adapter->hw.mng_cookie.status &
3872 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3873 e1000_update_mng_vlan(adapter);
3874
c128ec29 3875 /* DMA latency requirement to workaround early-receive/jumbo issue */
828bac87
BA		 3876 if ((adapter->flags & FLAG_HAS_ERT) ||
3877 (adapter->hw.mac.type == e1000_pch2lan))
6ba74014
LT		 3878 pm_qos_add_request(&adapter->netdev->pm_qos_req,
3879 PM_QOS_CPU_DMA_LATENCY,
3880 PM_QOS_DEFAULT_VALUE);
c128ec29 3881
ad68076e
BA		 3882 /*
3883 * before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 3884 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3885 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 3886 * clean_rx handler before we do so.
3887 */
bc7f75fa
AK		 3888 e1000_configure(adapter);
3889
3890 err = e1000_request_irq(adapter);
3891 if (err)
3892 goto err_req_irq;
3893
f8d59f78
BA		 3894 /*
3895 * Work around PCIe errata with MSI interrupts causing some chipsets to
3896 * ignore e1000e MSI messages, which means we need to test our MSI
3897 * interrupt now
3898 */
4662e82b 3899 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 3900 err = e1000_test_msi(adapter);
3901 if (err) {
3902 e_err("Interrupt allocation failed\n");
3903 goto err_req_irq;
3904 }
3905 }
3906
bc7f75fa
AK		 3907 /* From here on the code is the same as e1000e_up() */
3908 clear_bit(__E1000_DOWN, &adapter->state);
3909
3910 napi_enable(&adapter->napi);
3911
3912 e1000_irq_enable(adapter);
3913
09357b00 3914 adapter->tx_hang_recheck = false;
4cb9be7a 3915 netif_start_queue(netdev);
d55b53ff 3916
23606cf5
RW		 3917 adapter->idle_check = true;
3918 pm_runtime_put(&pdev->dev);
3919
bc7f75fa 3920 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 3921 if (adapter->msix_entries)
3922 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3923 else
3924 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 3925
3926 return 0;
3927
3928err_req_irq:
31dbe5b4 3929 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 3930 e1000_power_down_phy(adapter);
3931 e1000e_free_rx_resources(adapter);
3932err_setup_rx:
3933 e1000e_free_tx_resources(adapter);
3934err_setup_tx:
3935 e1000e_reset(adapter);
23606cf5 3936 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 3937
3938 return err;
3939}
3940
3941/**
3942 * e1000_close - Disables a network interface
3943 * @netdev: network interface device structure
3944 *
3945 * Returns 0, this is not allowed to fail
3946 *
3947 * The close entry point is called when an interface is de-activated
3948 * by the OS. The hardware is still under the drivers control, but
3949 * needs to be disabled. A global MAC reset is issued to stop the
3950 * hardware, and all transmit and receive resources are freed.
3951 **/
3952static int e1000_close(struct net_device *netdev)
3953{
3954 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 3955 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3956
3957 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 3958
3959 pm_runtime_get_sync(&pdev->dev);
3960
5f4a780d
BA		 3961 napi_disable(&adapter->napi);
3962
23606cf5
RW		 3963 if (!test_bit(__E1000_DOWN, &adapter->state)) {
3964 e1000e_down(adapter);
3965 e1000_free_irq(adapter);
3966 }
bc7f75fa 3967 e1000_power_down_phy(adapter);
bc7f75fa
AK		 3968
3969 e1000e_free_tx_resources(adapter);
3970 e1000e_free_rx_resources(adapter);
3971
ad68076e
BA		 3972 /*
3973 * kill manageability vlan ID if supported, but not if a vlan with
3974 * the same ID is registered on the host OS (let 8021q kill it)
3975 */
86d70e53
JK		 3976 if (adapter->hw.mng_cookie.status &
3977 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 3978 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3979
ad68076e
BA		 3980 /*
3981 * If AMT is enabled, let the firmware know that the network
3982 * interface is now closed
3983 */
31dbe5b4
BA		 3984 if ((adapter->flags & FLAG_HAS_AMT) &&
3985 !test_bit(__E1000_TESTING, &adapter->state))
3986 e1000e_release_hw_control(adapter);
bc7f75fa 3987
828bac87
BA		 3988 if ((adapter->flags & FLAG_HAS_ERT) ||
3989 (adapter->hw.mac.type == e1000_pch2lan))
6ba74014 3990 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 3991
23606cf5
RW		 3992 pm_runtime_put_sync(&pdev->dev);
3993
bc7f75fa
AK		 3994 return 0;
3995}
3996/**
3997 * e1000_set_mac - Change the Ethernet Address of the NIC
3998 * @netdev: network interface device structure
3999 * @p: pointer to an address structure
4000 *
4001 * Returns 0 on success, negative on failure
4002 **/
4003static int e1000_set_mac(struct net_device *netdev, void *p)
4004{
4005 struct e1000_adapter *adapter = netdev_priv(netdev);
4006 struct sockaddr *addr = p;
4007
4008 if (!is_valid_ether_addr(addr->sa_data))
4009 return -EADDRNOTAVAIL;
4010
4011 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4012 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4013
4014 e1000e_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
4015
4016 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4017 /* activate the work around */
4018 e1000e_set_laa_state_82571(&adapter->hw, 1);
4019
ad68076e
BA		 4020 /*
4021 * Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4022 * between the time RAR[0] gets clobbered and the time it
4023 * gets fixed (in e1000_watchdog), the actual LAA is in one
4024 * of the RARs and no incoming packets directed to this port
4025 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4026 * RAR[14]
4027 */
bc7f75fa
AK		 4028 e1000e_rar_set(&adapter->hw,
4029 adapter->hw.mac.addr,
4030 adapter->hw.mac.rar_entry_count - 1);
4031 }
4032
4033 return 0;
4034}
4035
a8f88ff5
JB		 4036/**
4037 * e1000e_update_phy_task - work thread to update phy
4038 * @work: pointer to our work struct
4039 *
4040 * this worker thread exists because we must acquire a
4041 * semaphore to read the phy, which we could msleep while
4042 * waiting for it, and we can't msleep in a timer.
4043 **/
4044static void e1000e_update_phy_task(struct work_struct *work)
4045{
4046 struct e1000_adapter *adapter = container_of(work,
4047 struct e1000_adapter, update_phy_task);
615b32af
JB		 4048
4049 if (test_bit(__E1000_DOWN, &adapter->state))
4050 return;
4051
a8f88ff5
JB		 4052 e1000_get_phy_info(&adapter->hw);
4053}
4054
ad68076e
BA		 4055/*
4056 * Need to wait a few seconds after link up to get diagnostic information from
4057 * the phy
4058 */
bc7f75fa
AK		 4059static void e1000_update_phy_info(unsigned long data)
4060{
4061 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4062
4063 if (test_bit(__E1000_DOWN, &adapter->state))
4064 return;
4065
a8f88ff5 4066 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4067}
4068
8c7bbb92
BA		 4069/**
4070 * e1000e_update_phy_stats - Update the PHY statistics counters
4071 * @adapter: board private structure
2b6b168d
BA		 4072 *
4073 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4074 **/
4075static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4076{
4077 struct e1000_hw *hw = &adapter->hw;
4078 s32 ret_val;
4079 u16 phy_data;
4080
4081 ret_val = hw->phy.ops.acquire(hw);
4082 if (ret_val)
4083 return;
4084
8c7bbb92
BA		 4085 /*
4086 * A page set is expensive so check if already on desired page.
4087 * If not, set to the page with the PHY status registers.
4088 */
2b6b168d 4089 hw->phy.addr = 1;
8c7bbb92
BA		 4090 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4091 &phy_data);
4092 if (ret_val)
4093 goto release;
2b6b168d
BA		 4094 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4095 ret_val = hw->phy.ops.set_page(hw,
4096 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4097 if (ret_val)
4098 goto release;
4099 }
4100
8c7bbb92 4101 /* Single Collision Count */
2b6b168d
BA		 4102 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4103 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4104 if (!ret_val)
4105 adapter->stats.scc += phy_data;
4106
4107 /* Excessive Collision Count */
2b6b168d
BA		 4108 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4109 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4110 if (!ret_val)
4111 adapter->stats.ecol += phy_data;
4112
4113 /* Multiple Collision Count */
2b6b168d
BA		 4114 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4115 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4116 if (!ret_val)
4117 adapter->stats.mcc += phy_data;
4118
4119 /* Late Collision Count */
2b6b168d
BA		 4120 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4121 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4122 if (!ret_val)
4123 adapter->stats.latecol += phy_data;
4124
4125 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4126 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4127 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4128 if (!ret_val)
4129 hw->mac.collision_delta = phy_data;
4130
4131 /* Defer Count */
2b6b168d
BA		 4132 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4133 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4134 if (!ret_val)
4135 adapter->stats.dc += phy_data;
4136
4137 /* Transmit with no CRS */
2b6b168d
BA		 4138 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4139 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4140 if (!ret_val)
4141 adapter->stats.tncrs += phy_data;
4142
4143release:
4144 hw->phy.ops.release(hw);
4145}
4146
bc7f75fa
AK		 4147/**
4148 * e1000e_update_stats - Update the board statistics counters
4149 * @adapter: board private structure
4150 **/
67fd4fcb 4151static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4152{
7274c20f 4153 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4154 struct e1000_hw *hw = &adapter->hw;
4155 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4156
4157 /*
4158 * Prevent stats update while adapter is being reset, or if the pci
4159 * connection is down.
4160 */
4161 if (adapter->link_speed == 0)
4162 return;
4163 if (pci_channel_offline(pdev))
4164 return;
4165
bc7f75fa
AK		 4166 adapter->stats.crcerrs += er32(CRCERRS);
4167 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4168 adapter->stats.gorc += er32(GORCL);
4169 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4170 adapter->stats.bprc += er32(BPRC);
4171 adapter->stats.mprc += er32(MPRC);
4172 adapter->stats.roc += er32(ROC);
4173
bc7f75fa 4174 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4175
4176 /* Half-duplex statistics */
4177 if (adapter->link_duplex == HALF_DUPLEX) {
4178 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4179 e1000e_update_phy_stats(adapter);
4180 } else {
4181 adapter->stats.scc += er32(SCC);
4182 adapter->stats.ecol += er32(ECOL);
4183 adapter->stats.mcc += er32(MCC);
4184 adapter->stats.latecol += er32(LATECOL);
4185 adapter->stats.dc += er32(DC);
4186
4187 hw->mac.collision_delta = er32(COLC);
4188
4189 if ((hw->mac.type != e1000_82574) &&
4190 (hw->mac.type != e1000_82583))
4191 adapter->stats.tncrs += er32(TNCRS);
4192 }
4193 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4194 }
8c7bbb92 4195
bc7f75fa
AK		 4196 adapter->stats.xonrxc += er32(XONRXC);
4197 adapter->stats.xontxc += er32(XONTXC);
4198 adapter->stats.xoffrxc += er32(XOFFRXC);
4199 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4200 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4201 adapter->stats.gotc += er32(GOTCL);
4202 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4203 adapter->stats.rnbc += er32(RNBC);
4204 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4205
4206 adapter->stats.mptc += er32(MPTC);
4207 adapter->stats.bptc += er32(BPTC);
4208
4209 /* used for adaptive IFS */
4210
4211 hw->mac.tx_packet_delta = er32(TPT);
4212 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4213
4214 adapter->stats.algnerrc += er32(ALGNERRC);
4215 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4216 adapter->stats.cexterr += er32(CEXTERR);
4217 adapter->stats.tsctc += er32(TSCTC);
4218 adapter->stats.tsctfc += er32(TSCTFC);
4219
bc7f75fa 4220 /* Fill out the OS statistics structure */
7274c20f
AK		 4221 netdev->stats.multicast = adapter->stats.mprc;
4222 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4223
4224 /* Rx Errors */
4225
ad68076e
BA		 4226 /*
4227 * RLEC on some newer hardware can be incorrect so build
4228 * our own version based on RUC and ROC
4229 */
7274c20f 4230 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4231 adapter->stats.crcerrs + adapter->stats.algnerrc +
4232 adapter->stats.ruc + adapter->stats.roc +
4233 adapter->stats.cexterr;
7274c20f 4234 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4235 adapter->stats.roc;
7274c20f
AK		 4236 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4237 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4238 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4239
4240 /* Tx Errors */
7274c20f 4241 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4242 adapter->stats.latecol;
7274c20f
AK		 4243 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4244 netdev->stats.tx_window_errors = adapter->stats.latecol;
4245 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4246
4247 /* Tx Dropped needs to be maintained elsewhere */
4248
bc7f75fa
AK		 4249 /* Management Stats */
4250 adapter->stats.mgptc += er32(MGTPTC);
4251 adapter->stats.mgprc += er32(MGTPRC);
4252 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4253}
4254
7c25769f
BA		 4255/**
4256 * e1000_phy_read_status - Update the PHY register status snapshot
4257 * @adapter: board private structure
4258 **/
4259static void e1000_phy_read_status(struct e1000_adapter *adapter)
4260{
4261 struct e1000_hw *hw = &adapter->hw;
4262 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4263
4264 if ((er32(STATUS) & E1000_STATUS_LU) &&
4265 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4266 int ret_val;
4267
7c25769f
BA		 4268 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4269 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4270 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4271 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4272 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4273 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4274 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4275 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4276 if (ret_val)
44defeb3 4277 e_warn("Error reading PHY register\n");
7c25769f
BA		 4278 } else {
4279 /*
4280 * Do not read PHY registers if link is not up
4281 * Set values to typical power-on defaults
4282 */
4283 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4284 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4285 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4286 BMSR_ERCAP);
4287 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4288 ADVERTISE_ALL | ADVERTISE_CSMA);
4289 phy->lpa = 0;
4290 phy->expansion = EXPANSION_ENABLENPAGE;
4291 phy->ctrl1000 = ADVERTISE_1000FULL;
4292 phy->stat1000 = 0;
4293 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4294 }
7c25769f
BA		 4295}
4296
bc7f75fa
AK		 4297static void e1000_print_link_info(struct e1000_adapter *adapter)
4298{
bc7f75fa
AK		 4299 struct e1000_hw *hw = &adapter->hw;
4300 u32 ctrl = er32(CTRL);
4301
8f12fe86 4302 /* Link status message must follow this format for user tools */
ef456f85
JK		 4303 printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4304 adapter->netdev->name,
4305 adapter->link_speed,
4306 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4307 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4308 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4309 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4310}
4311
0c6bdb30 4312static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4313{
4314 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4315 bool link_active = false;
318a94d6
JK		 4316 s32 ret_val = 0;
4317
4318 /*
4319 * get_link_status is set on LSC (link status) interrupt or
4320 * Rx sequence error interrupt. get_link_status will stay
4321 * false until the check_for_link establishes link
4322 * for copper adapters ONLY
4323 */
4324 switch (hw->phy.media_type) {
4325 case e1000_media_type_copper:
4326 if (hw->mac.get_link_status) {
4327 ret_val = hw->mac.ops.check_for_link(hw);
4328 link_active = !hw->mac.get_link_status;
4329 } else {
3db1cd5c 4330 link_active = true;
318a94d6
JK		 4331 }
4332 break;
4333 case e1000_media_type_fiber:
4334 ret_val = hw->mac.ops.check_for_link(hw);
4335 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4336 break;
4337 case e1000_media_type_internal_serdes:
4338 ret_val = hw->mac.ops.check_for_link(hw);
4339 link_active = adapter->hw.mac.serdes_has_link;
4340 break;
4341 default:
4342 case e1000_media_type_unknown:
4343 break;
4344 }
4345
4346 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4347 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4348 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4349 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4350 }
4351
4352 return link_active;
4353}
4354
4355static void e1000e_enable_receives(struct e1000_adapter *adapter)
4356{
4357 /* make sure the receive unit is started */
4358 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
4359 (adapter->flags & FLAG_RX_RESTART_NOW)) {
4360 struct e1000_hw *hw = &adapter->hw;
4361 u32 rctl = er32(RCTL);
4362 ew32(RCTL, rctl | E1000_RCTL_EN);
4363 adapter->flags &= ~FLAG_RX_RESTART_NOW;
4364 }
4365}
4366
ff10e13c
CW		 4367static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4368{
4369 struct e1000_hw *hw = &adapter->hw;
4370
4371 /*
4372 * With 82574 controllers, PHY needs to be checked periodically
4373 * for hung state and reset, if two calls return true
4374 */
4375 if (e1000_check_phy_82574(hw))
4376 adapter->phy_hang_count++;
4377 else
4378 adapter->phy_hang_count = 0;
4379
4380 if (adapter->phy_hang_count > 1) {
4381 adapter->phy_hang_count = 0;
4382 schedule_work(&adapter->reset_task);
4383 }
4384}
4385
bc7f75fa
AK		 4386/**
4387 * e1000_watchdog - Timer Call-back
4388 * @data: pointer to adapter cast into an unsigned long
4389 **/
4390static void e1000_watchdog(unsigned long data)
4391{
4392 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4393
4394 /* Do the rest outside of interrupt context */
4395 schedule_work(&adapter->watchdog_task);
4396
4397 /* TODO: make this use queue_delayed_work() */
4398}
4399
4400static void e1000_watchdog_task(struct work_struct *work)
4401{
4402 struct e1000_adapter *adapter = container_of(work,
4403 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4404 struct net_device *netdev = adapter->netdev;
4405 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4406 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4407 struct e1000_ring *tx_ring = adapter->tx_ring;
4408 struct e1000_hw *hw = &adapter->hw;
4409 u32 link, tctl;
bc7f75fa 4410
615b32af
JB		 4411 if (test_bit(__E1000_DOWN, &adapter->state))
4412 return;
4413
b405e8df 4414 link = e1000e_has_link(adapter);
318a94d6 4415 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4416 /* Cancel scheduled suspend requests. */
4417 pm_runtime_resume(netdev->dev.parent);
4418
318a94d6 4419 e1000e_enable_receives(adapter);
bc7f75fa 4420 goto link_up;
bc7f75fa
AK		 4421 }
4422
4423 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4424 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4425 e1000_update_mng_vlan(adapter);
4426
bc7f75fa
AK		 4427 if (link) {
4428 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4429 bool txb2b = true;
23606cf5
RW		 4430
4431 /* Cancel scheduled suspend requests. */
4432 pm_runtime_resume(netdev->dev.parent);
4433
318a94d6 4434 /* update snapshot of PHY registers on LSC */
7c25769f 4435 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4436 mac->ops.get_link_up_info(&adapter->hw,
4437 &adapter->link_speed,
4438 &adapter->link_duplex);
4439 e1000_print_link_info(adapter);
f4187b56
BA		 4440 /*
4441 * On supported PHYs, check for duplex mismatch only
4442 * if link has autonegotiated at 10/100 half
4443 */
4444 if ((hw->phy.type == e1000_phy_igp_3 ||
4445 hw->phy.type == e1000_phy_bm) &&
4446 (hw->mac.autoneg == true) &&
4447 (adapter->link_speed == SPEED_10 ||
4448 adapter->link_speed == SPEED_100) &&
4449 (adapter->link_duplex == HALF_DUPLEX)) {
4450 u16 autoneg_exp;
4451
4452 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4453
4454 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4455 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4456 }
4457
f49c57e1 4458 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4459 adapter->tx_timeout_factor = 1;
4460 switch (adapter->link_speed) {
4461 case SPEED_10:
3db1cd5c 4462 txb2b = false;
10f1b492 4463 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4464 break;
4465 case SPEED_100:
3db1cd5c 4466 txb2b = false;
4c86e0b9 4467 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4468 break;
4469 }
4470
ad68076e
BA		 4471 /*
4472 * workaround: re-program speed mode bit after
4473 * link-up event
4474 */
bc7f75fa
AK		 4475 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4476 !txb2b) {
4477 u32 tarc0;
e9ec2c0f 4478 tarc0 = er32(TARC(0));
bc7f75fa 4479 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4480 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4481 }
4482
ad68076e
BA		 4483 /*
4484 * disable TSO for pcie and 10/100 speeds, to avoid
4485 * some hardware issues
4486 */
bc7f75fa
AK		 4487 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4488 switch (adapter->link_speed) {
4489 case SPEED_10:
4490 case SPEED_100:
44defeb3 4491 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4492 netdev->features &= ~NETIF_F_TSO;
4493 netdev->features &= ~NETIF_F_TSO6;
4494 break;
4495 case SPEED_1000:
4496 netdev->features |= NETIF_F_TSO;
4497 netdev->features |= NETIF_F_TSO6;
4498 break;
4499 default:
4500 /* oops */
4501 break;
4502 }
4503 }
4504
ad68076e
BA		 4505 /*
4506 * enable transmits in the hardware, need to do this
4507 * after setting TARC(0)
4508 */
bc7f75fa
AK		 4509 tctl = er32(TCTL);
4510 tctl |= E1000_TCTL_EN;
4511 ew32(TCTL, tctl);
4512
75eb0fad
BA		 4513 /*
4514 * Perform any post-link-up configuration before
4515 * reporting link up.
4516 */
4517 if (phy->ops.cfg_on_link_up)
4518 phy->ops.cfg_on_link_up(hw);
4519
bc7f75fa 4520 netif_carrier_on(netdev);
bc7f75fa
AK		 4521
4522 if (!test_bit(__E1000_DOWN, &adapter->state))
4523 mod_timer(&adapter->phy_info_timer,
4524 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4525 }
4526 } else {
4527 if (netif_carrier_ok(netdev)) {
4528 adapter->link_speed = 0;
4529 adapter->link_duplex = 0;
8f12fe86
BA		 4530 /* Link status message must follow this format */
4531 printk(KERN_INFO "e1000e: %s NIC Link is Down\n",
4532 adapter->netdev->name);
bc7f75fa 4533 netif_carrier_off(netdev);
bc7f75fa
AK		 4534 if (!test_bit(__E1000_DOWN, &adapter->state))
4535 mod_timer(&adapter->phy_info_timer,
4536 round_jiffies(jiffies + 2 * HZ));
4537
4538 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
4539 schedule_work(&adapter->reset_task);
23606cf5
RW		 4540 else
4541 pm_schedule_suspend(netdev->dev.parent,
4542 LINK_TIMEOUT);
bc7f75fa
AK		 4543 }
4544 }
4545
4546link_up:
67fd4fcb 4547 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4548 e1000e_update_stats(adapter);
4549
4550 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4551 adapter->tpt_old = adapter->stats.tpt;
4552 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4553 adapter->colc_old = adapter->stats.colc;
4554
7c25769f
BA		 4555 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4556 adapter->gorc_old = adapter->stats.gorc;
4557 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4558 adapter->gotc_old = adapter->stats.gotc;
2084b114 4559 spin_unlock(&adapter->stats64_lock);
bc7f75fa
AK		 4560
4561 e1000e_update_adaptive(&adapter->hw);
4562
90da0669
BA		 4563 if (!netif_carrier_ok(netdev) &&
4564 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
4565 /*
4566 * We've lost link, so the controller stops DMA,
4567 * but we've got queued Tx work that's never going
4568 * to get done, so reset controller to flush Tx.
4569 * (Do the reset outside of interrupt context).
4570 */
90da0669
BA		 4571 schedule_work(&adapter->reset_task);
4572 /* return immediately since reset is imminent */
4573 return;
bc7f75fa
AK		 4574 }
4575
eab2abf5
JB		 4576 /* Simple mode for Interrupt Throttle Rate (ITR) */
4577 if (adapter->itr_setting == 4) {
4578 /*
4579 * Symmetric Tx/Rx gets a reduced ITR=2000;
4580 * Total asymmetrical Tx or Rx gets ITR=8000;
4581 * everyone else is between 2000-8000.
4582 */
4583 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4584 u32 dif = (adapter->gotc > adapter->gorc ?
4585 adapter->gotc - adapter->gorc :
4586 adapter->gorc - adapter->gotc) / 10000;
4587 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4588
4589 ew32(ITR, 1000000000 / (itr * 256));
4590 }
4591
ad68076e 4592 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4593 if (adapter->msix_entries)
4594 ew32(ICS, adapter->rx_ring->ims_val);
4595 else
4596 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4597
713b3c9e
JB		 4598 /* flush pending descriptors to memory before detecting Tx hang */
4599 e1000e_flush_descriptors(adapter);
4600
bc7f75fa 4601 /* Force detection of hung controller every watchdog period */
3db1cd5c 4602 adapter->detect_tx_hung = true;
bc7f75fa 4603
ad68076e
BA		 4604 /*
4605 * With 82571 controllers, LAA may be overwritten due to controller
4606 * reset from the other port. Set the appropriate LAA in RAR[0]
4607 */
bc7f75fa
AK		 4608 if (e1000e_get_laa_state_82571(hw))
4609 e1000e_rar_set(hw, adapter->hw.mac.addr, 0);
4610
ff10e13c
CW		 4611 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4612 e1000e_check_82574_phy_workaround(adapter);
4613
bc7f75fa
AK		 4614 /* Reset the timer */
4615 if (!test_bit(__E1000_DOWN, &adapter->state))
4616 mod_timer(&adapter->watchdog_timer,
4617 round_jiffies(jiffies + 2 * HZ));
4618}
4619
4620#define E1000_TX_FLAGS_CSUM 0x00000001
4621#define E1000_TX_FLAGS_VLAN 0x00000002
4622#define E1000_TX_FLAGS_TSO 0x00000004
4623#define E1000_TX_FLAGS_IPV4 0x00000008
4624#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4625#define E1000_TX_FLAGS_VLAN_SHIFT 16
4626
4627static int e1000_tso(struct e1000_adapter *adapter,
4628 struct sk_buff *skb)
4629{
4630 struct e1000_ring *tx_ring = adapter->tx_ring;
4631 struct e1000_context_desc *context_desc;
4632 struct e1000_buffer *buffer_info;
4633 unsigned int i;
4634 u32 cmd_length = 0;
4635 u16 ipcse = 0, tucse, mss;
4636 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4637
3d5e33c9
BA		 4638 if (!skb_is_gso(skb))
4639 return 0;
bc7f75fa 4640
3d5e33c9 4641 if (skb_header_cloned(skb)) {
90da0669
BA		 4642 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4643
3d5e33c9
BA		 4644 if (err)
4645 return err;
bc7f75fa
AK		 4646 }
4647
3d5e33c9
BA		 4648 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4649 mss = skb_shinfo(skb)->gso_size;
4650 if (skb->protocol == htons(ETH_P_IP)) {
4651 struct iphdr *iph = ip_hdr(skb);
4652 iph->tot_len = 0;
4653 iph->check = 0;
4654 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4655 0, IPPROTO_TCP, 0);
4656 cmd_length = E1000_TXD_CMD_IP;
4657 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4658 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4659 ipv6_hdr(skb)->payload_len = 0;
4660 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4661 &ipv6_hdr(skb)->daddr,
4662 0, IPPROTO_TCP, 0);
4663 ipcse = 0;
4664 }
4665 ipcss = skb_network_offset(skb);
4666 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4667 tucss = skb_transport_offset(skb);
4668 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
4669 tucse = 0;
4670
4671 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4672 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4673
4674 i = tx_ring->next_to_use;
4675 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4676 buffer_info = &tx_ring->buffer_info[i];
4677
4678 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4679 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4680 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4681 context_desc->upper_setup.tcp_fields.tucss = tucss;
4682 context_desc->upper_setup.tcp_fields.tucso = tucso;
4683 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
4684 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4685 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4686 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4687
4688 buffer_info->time_stamp = jiffies;
4689 buffer_info->next_to_watch = i;
4690
4691 i++;
4692 if (i == tx_ring->count)
4693 i = 0;
4694 tx_ring->next_to_use = i;
4695
4696 return 1;
bc7f75fa
AK		 4697}
4698
4699static bool e1000_tx_csum(struct e1000_adapter *adapter, struct sk_buff *skb)
4700{
4701 struct e1000_ring *tx_ring = adapter->tx_ring;
4702 struct e1000_context_desc *context_desc;
4703 struct e1000_buffer *buffer_info;
4704 unsigned int i;
4705 u8 css;
af807c82 4706 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4707 __be16 protocol;
bc7f75fa 4708
af807c82
DG		 4709 if (skb->ip_summed != CHECKSUM_PARTIAL)
4710 return 0;
bc7f75fa 4711
5f66f208
AJ		 4712 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4713 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4714 else
4715 protocol = skb->protocol;
4716
3f518390 4717 switch (protocol) {
09640e63 4718 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 4719 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4720 cmd_len |= E1000_TXD_CMD_TCP;
4721 break;
09640e63 4722 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 4723 /* XXX not handling all IPV6 headers */
4724 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4725 cmd_len |= E1000_TXD_CMD_TCP;
4726 break;
4727 default:
4728 if (unlikely(net_ratelimit()))
5f66f208
AJ		 4729 e_warn("checksum_partial proto=%x!\n",
4730 be16_to_cpu(protocol));
af807c82 4731 break;
bc7f75fa
AK		 4732 }
4733
0d0b1672 4734 css = skb_checksum_start_offset(skb);
af807c82
DG		 4735
4736 i = tx_ring->next_to_use;
4737 buffer_info = &tx_ring->buffer_info[i];
4738 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4739
4740 context_desc->lower_setup.ip_config = 0;
4741 context_desc->upper_setup.tcp_fields.tucss = css;
4742 context_desc->upper_setup.tcp_fields.tucso =
4743 css + skb->csum_offset;
4744 context_desc->upper_setup.tcp_fields.tucse = 0;
4745 context_desc->tcp_seg_setup.data = 0;
4746 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
4747
4748 buffer_info->time_stamp = jiffies;
4749 buffer_info->next_to_watch = i;
4750
4751 i++;
4752 if (i == tx_ring->count)
4753 i = 0;
4754 tx_ring->next_to_use = i;
4755
4756 return 1;
bc7f75fa
AK		 4757}
4758
4759#define E1000_MAX_PER_TXD 8192
4760#define E1000_MAX_TXD_PWR 12
4761
4762static int e1000_tx_map(struct e1000_adapter *adapter,
4763 struct sk_buff *skb, unsigned int first,
4764 unsigned int max_per_txd, unsigned int nr_frags,
4765 unsigned int mss)
4766{
4767 struct e1000_ring *tx_ring = adapter->tx_ring;
03b1320d 4768 struct pci_dev *pdev = adapter->pdev;
1b7719c4 4769 struct e1000_buffer *buffer_info;
8ddc951c 4770 unsigned int len = skb_headlen(skb);
03b1320d 4771 unsigned int offset = 0, size, count = 0, i;
9ed318d5 4772 unsigned int f, bytecount, segs;
bc7f75fa
AK		 4773
4774 i = tx_ring->next_to_use;
4775
4776 while (len) {
1b7719c4 4777 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 4778 size = min(len, max_per_txd);
4779
bc7f75fa 4780 buffer_info->length = size;
bc7f75fa 4781 buffer_info->time_stamp = jiffies;
bc7f75fa 4782 buffer_info->next_to_watch = i;
0be3f55f
NN		 4783 buffer_info->dma = dma_map_single(&pdev->dev,
4784 skb->data + offset,
af667a29 4785 size, DMA_TO_DEVICE);
03b1320d 4786 buffer_info->mapped_as_page = false;
0be3f55f 4787 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4788 goto dma_error;
bc7f75fa
AK		 4789
4790 len -= size;
4791 offset += size;
03b1320d 4792 count++;
1b7719c4
AD		 4793
4794 if (len) {
4795 i++;
4796 if (i == tx_ring->count)
4797 i = 0;
4798 }
bc7f75fa
AK		 4799 }
4800
4801 for (f = 0; f < nr_frags; f++) {
9e903e08 4802 const struct skb_frag_struct *frag;
bc7f75fa
AK		 4803
4804 frag = &skb_shinfo(skb)->frags[f];
9e903e08 4805 len = skb_frag_size(frag);
877749bf 4806 offset = 0;
bc7f75fa
AK		 4807
4808 while (len) {
1b7719c4
AD		 4809 i++;
4810 if (i == tx_ring->count)
4811 i = 0;
4812
bc7f75fa
AK		 4813 buffer_info = &tx_ring->buffer_info[i];
4814 size = min(len, max_per_txd);
bc7f75fa
AK		 4815
4816 buffer_info->length = size;
4817 buffer_info->time_stamp = jiffies;
bc7f75fa 4818 buffer_info->next_to_watch = i;
877749bf
IC		 4819 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
4820 offset, size, DMA_TO_DEVICE);
03b1320d 4821 buffer_info->mapped_as_page = true;
0be3f55f 4822 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4823 goto dma_error;
bc7f75fa
AK		 4824
4825 len -= size;
4826 offset += size;
4827 count++;
bc7f75fa
AK		 4828 }
4829 }
4830
af667a29 4831 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 4832 /* multiply data chunks by size of headers */
4833 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
4834
bc7f75fa 4835 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 4836 tx_ring->buffer_info[i].segs = segs;
4837 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 4838 tx_ring->buffer_info[first].next_to_watch = i;
4839
4840 return count;
03b1320d
AD		 4841
4842dma_error:
af667a29 4843 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 4844 buffer_info->dma = 0;
c1fa347f 4845 if (count)
03b1320d 4846 count--;
c1fa347f
RK		 4847
4848 while (count--) {
af667a29 4849 if (i == 0)
03b1320d 4850 i += tx_ring->count;
c1fa347f 4851 i--;
03b1320d 4852 buffer_info = &tx_ring->buffer_info[i];
1d51c418 4853 e1000_put_txbuf(adapter, buffer_info);
03b1320d
AD		 4854 }
4855
4856 return 0;
bc7f75fa
AK		 4857}
4858
4859static void e1000_tx_queue(struct e1000_adapter *adapter,
4860 int tx_flags, int count)
4861{
4862 struct e1000_ring *tx_ring = adapter->tx_ring;
4863 struct e1000_tx_desc *tx_desc = NULL;
4864 struct e1000_buffer *buffer_info;
4865 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
4866 unsigned int i;
4867
4868 if (tx_flags & E1000_TX_FLAGS_TSO) {
4869 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
4870 E1000_TXD_CMD_TSE;
4871 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4872
4873 if (tx_flags & E1000_TX_FLAGS_IPV4)
4874 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
4875 }
4876
4877 if (tx_flags & E1000_TX_FLAGS_CSUM) {
4878 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
4879 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4880 }
4881
4882 if (tx_flags & E1000_TX_FLAGS_VLAN) {
4883 txd_lower |= E1000_TXD_CMD_VLE;
4884 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
4885 }
4886
4887 i = tx_ring->next_to_use;
4888
36b973df 4889 do {
bc7f75fa
AK		 4890 buffer_info = &tx_ring->buffer_info[i];
4891 tx_desc = E1000_TX_DESC(*tx_ring, i);
4892 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4893 tx_desc->lower.data =
4894 cpu_to_le32(txd_lower | buffer_info->length);
4895 tx_desc->upper.data = cpu_to_le32(txd_upper);
4896
4897 i++;
4898 if (i == tx_ring->count)
4899 i = 0;
36b973df 4900 } while (--count > 0);
bc7f75fa
AK		 4901
4902 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
4903
ad68076e
BA		 4904 /*
4905 * Force memory writes to complete before letting h/w
bc7f75fa
AK		 4906 * know there are new descriptors to fetch. (Only
4907 * applicable for weak-ordered memory model archs,
ad68076e
BA		 4908 * such as IA-64).
4909 */
bc7f75fa
AK		 4910 wmb();
4911
4912 tx_ring->next_to_use = i;
c6e7f51e
BA		 4913
4914 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
4915 e1000e_update_tdt_wa(adapter, i);
4916 else
4917 writel(i, adapter->hw.hw_addr + tx_ring->tail);
4918
ad68076e
BA		 4919 /*
4920 * we need this if more than one processor can write to our tail
4921 * at a time, it synchronizes IO on IA64/Altix systems
4922 */
bc7f75fa
AK		 4923 mmiowb();
4924}
4925
4926#define MINIMUM_DHCP_PACKET_SIZE 282
4927static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
4928 struct sk_buff *skb)
4929{
4930 struct e1000_hw *hw = &adapter->hw;
4931 u16 length, offset;
4932
4933 if (vlan_tx_tag_present(skb)) {
8e95a202
JP		 4934 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
4935 (adapter->hw.mng_cookie.status &
bc7f75fa
AK		 4936 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4937 return 0;
4938 }
4939
4940 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
4941 return 0;
4942
4943 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
4944 return 0;
4945
4946 {
4947 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
4948 struct udphdr *udp;
4949
4950 if (ip->protocol != IPPROTO_UDP)
4951 return 0;
4952
4953 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
4954 if (ntohs(udp->dest) != 67)
4955 return 0;
4956
4957 offset = (u8 *)udp + 8 - skb->data;
4958 length = skb->len - offset;
4959 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
4960 }
4961
4962 return 0;
4963}
4964
4965static int __e1000_maybe_stop_tx(struct net_device *netdev, int size)
4966{
4967 struct e1000_adapter *adapter = netdev_priv(netdev);
4968
4969 netif_stop_queue(netdev);
ad68076e
BA		 4970 /*
4971 * Herbert's original patch had:
bc7f75fa 4972 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 4973 * but since that doesn't exist yet, just open code it.
4974 */
bc7f75fa
AK		 4975 smp_mb();
4976
ad68076e
BA		 4977 /*
4978 * We need to check again in a case another CPU has just
4979 * made room available.
4980 */
bc7f75fa
AK		 4981 if (e1000_desc_unused(adapter->tx_ring) < size)
4982 return -EBUSY;
4983
4984 /* A reprieve! */
4985 netif_start_queue(netdev);
4986 ++adapter->restart_queue;
4987 return 0;
4988}
4989
4990static int e1000_maybe_stop_tx(struct net_device *netdev, int size)
4991{
4992 struct e1000_adapter *adapter = netdev_priv(netdev);
4993
4994 if (e1000_desc_unused(adapter->tx_ring) >= size)
4995 return 0;
4996 return __e1000_maybe_stop_tx(netdev, size);
4997}
4998
4999#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
3b29a56d
SH		 5000static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5001 struct net_device *netdev)
bc7f75fa
AK		 5002{
5003 struct e1000_adapter *adapter = netdev_priv(netdev);
5004 struct e1000_ring *tx_ring = adapter->tx_ring;
5005 unsigned int first;
5006 unsigned int max_per_txd = E1000_MAX_PER_TXD;
5007 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
5008 unsigned int tx_flags = 0;
e743d313 5009 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5010 unsigned int nr_frags;
5011 unsigned int mss;
bc7f75fa
AK		 5012 int count = 0;
5013 int tso;
5014 unsigned int f;
bc7f75fa
AK		 5015
5016 if (test_bit(__E1000_DOWN, &adapter->state)) {
5017 dev_kfree_skb_any(skb);
5018 return NETDEV_TX_OK;
5019 }
5020
5021 if (skb->len <= 0) {
5022 dev_kfree_skb_any(skb);
5023 return NETDEV_TX_OK;
5024 }
5025
5026 mss = skb_shinfo(skb)->gso_size;
ad68076e
BA		 5027 /*
5028 * The controller does a simple calculation to
bc7f75fa
AK		 5029 * make sure there is enough room in the FIFO before
5030 * initiating the DMA for each buffer. The calc is:
5031 * 4 = ceil(buffer len/mss). To make sure we don't
5032 * overrun the FIFO, adjust the max buffer len if mss
ad68076e
BA		 5033 * drops.
5034 */
bc7f75fa
AK		 5035 if (mss) {
5036 u8 hdr_len;
5037 max_per_txd = min(mss << 2, max_per_txd);
5038 max_txd_pwr = fls(max_per_txd) - 1;
5039
ad68076e
BA		 5040 /*
5041 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
5042 * points to just header, pull a few bytes of payload from
5043 * frags into skb->data
5044 */
bc7f75fa 5045 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
ad68076e
BA		 5046 /*
5047 * we do this workaround for ES2LAN, but it is un-necessary,
5048 * avoiding it could save a lot of cycles
5049 */
4e6c709c 5050 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5051 unsigned int pull_size;
5052
5053 pull_size = min((unsigned int)4, skb->data_len);
5054 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5055 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5056 dev_kfree_skb_any(skb);
5057 return NETDEV_TX_OK;
5058 }
e743d313 5059 len = skb_headlen(skb);
bc7f75fa
AK		 5060 }
5061 }
5062
5063 /* reserve a descriptor for the offload context */
5064 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5065 count++;
5066 count++;
5067
5068 count += TXD_USE_COUNT(len, max_txd_pwr);
5069
5070 nr_frags = skb_shinfo(skb)->nr_frags;
5071 for (f = 0; f < nr_frags; f++)
9e903e08 5072 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->frags[f]),
bc7f75fa
AK		 5073 max_txd_pwr);
5074
5075 if (adapter->hw.mac.tx_pkt_filtering)
5076 e1000_transfer_dhcp_info(adapter, skb);
5077
ad68076e
BA		 5078 /*
5079 * need: count + 2 desc gap to keep tail from touching
5080 * head, otherwise try next time
5081 */
92af3e95 5082 if (e1000_maybe_stop_tx(netdev, count + 2))
bc7f75fa 5083 return NETDEV_TX_BUSY;
bc7f75fa 5084
eab6d18d 5085 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5086 tx_flags |= E1000_TX_FLAGS_VLAN;
5087 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5088 }
5089
5090 first = tx_ring->next_to_use;
5091
5092 tso = e1000_tso(adapter, skb);
5093 if (tso < 0) {
5094 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5095 return NETDEV_TX_OK;
5096 }
5097
5098 if (tso)
5099 tx_flags |= E1000_TX_FLAGS_TSO;
5100 else if (e1000_tx_csum(adapter, skb))
5101 tx_flags |= E1000_TX_FLAGS_CSUM;
5102
ad68076e
BA		 5103 /*
5104 * Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5105 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5106 * no longer assume, we must.
5107 */
bc7f75fa
AK		 5108 if (skb->protocol == htons(ETH_P_IP))
5109 tx_flags |= E1000_TX_FLAGS_IPV4;
5110
25985edc 5111 /* if count is 0 then mapping error has occurred */
bc7f75fa 5112 count = e1000_tx_map(adapter, skb, first, max_per_txd, nr_frags, mss);
1b7719c4 5113 if (count) {
3f0cfa3b 5114 netdev_sent_queue(netdev, skb->len);
1b7719c4 5115 e1000_tx_queue(adapter, tx_flags, count);
1b7719c4
AD		 5116 /* Make sure there is space in the ring for the next send. */
5117 e1000_maybe_stop_tx(netdev, MAX_SKB_FRAGS + 2);
5118
5119 } else {
bc7f75fa 5120 dev_kfree_skb_any(skb);
1b7719c4
AD		 5121 tx_ring->buffer_info[first].time_stamp = 0;
5122 tx_ring->next_to_use = first;
bc7f75fa
AK		 5123 }
5124
bc7f75fa
AK		 5125 return NETDEV_TX_OK;
5126}
5127
5128/**
5129 * e1000_tx_timeout - Respond to a Tx Hang
5130 * @netdev: network interface device structure
5131 **/
5132static void e1000_tx_timeout(struct net_device *netdev)
5133{
5134 struct e1000_adapter *adapter = netdev_priv(netdev);
5135
5136 /* Do the reset outside of interrupt context */
5137 adapter->tx_timeout_count++;
5138 schedule_work(&adapter->reset_task);
5139}
5140
5141static void e1000_reset_task(struct work_struct *work)
5142{
5143 struct e1000_adapter *adapter;
5144 adapter = container_of(work, struct e1000_adapter, reset_task);
5145
615b32af
JB		 5146 /* don't run the task if already down */
5147 if (test_bit(__E1000_DOWN, &adapter->state))
5148 return;
5149
affa9dfb
CW		 5150 if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5151 (adapter->flags & FLAG_RX_RESTART_NOW))) {
5152 e1000e_dump(adapter);
5153 e_err("Reset adapter\n");
5154 }
bc7f75fa
AK		 5155 e1000e_reinit_locked(adapter);
5156}
5157
5158/**
67fd4fcb 5159 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5160 * @netdev: network interface device structure
67fd4fcb 5161 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5162 *
5163 * Returns the address of the device statistics structure.
bc7f75fa 5164 **/
67fd4fcb
JK		 5165struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5166 struct rtnl_link_stats64 *stats)
bc7f75fa 5167{
67fd4fcb
JK		 5168 struct e1000_adapter *adapter = netdev_priv(netdev);
5169
5170 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5171 spin_lock(&adapter->stats64_lock);
5172 e1000e_update_stats(adapter);
5173 /* Fill out the OS statistics structure */
5174 stats->rx_bytes = adapter->stats.gorc;
5175 stats->rx_packets = adapter->stats.gprc;
5176 stats->tx_bytes = adapter->stats.gotc;
5177 stats->tx_packets = adapter->stats.gptc;
5178 stats->multicast = adapter->stats.mprc;
5179 stats->collisions = adapter->stats.colc;
5180
5181 /* Rx Errors */
5182
5183 /*
5184 * RLEC on some newer hardware can be incorrect so build
5185 * our own version based on RUC and ROC
5186 */
5187 stats->rx_errors = adapter->stats.rxerrc +
5188 adapter->stats.crcerrs + adapter->stats.algnerrc +
5189 adapter->stats.ruc + adapter->stats.roc +
5190 adapter->stats.cexterr;
5191 stats->rx_length_errors = adapter->stats.ruc +
5192 adapter->stats.roc;
5193 stats->rx_crc_errors = adapter->stats.crcerrs;
5194 stats->rx_frame_errors = adapter->stats.algnerrc;
5195 stats->rx_missed_errors = adapter->stats.mpc;
5196
5197 /* Tx Errors */
5198 stats->tx_errors = adapter->stats.ecol +
5199 adapter->stats.latecol;
5200 stats->tx_aborted_errors = adapter->stats.ecol;
5201 stats->tx_window_errors = adapter->stats.latecol;
5202 stats->tx_carrier_errors = adapter->stats.tncrs;
5203
5204 /* Tx Dropped needs to be maintained elsewhere */
5205
5206 spin_unlock(&adapter->stats64_lock);
5207 return stats;
bc7f75fa
AK		 5208}
5209
5210/**
5211 * e1000_change_mtu - Change the Maximum Transfer Unit
5212 * @netdev: network interface device structure
5213 * @new_mtu: new value for maximum frame size
5214 *
5215 * Returns 0 on success, negative on failure
5216 **/
5217static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5218{
5219 struct e1000_adapter *adapter = netdev_priv(netdev);
5220 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5221
2adc55c9 5222 /* Jumbo frame support */
70495a50
BA		 5223 if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) {
5224 if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5225 e_err("Jumbo Frames not supported.\n");
5226 return -EINVAL;
5227 }
5228
5229 /*
5230 * IP payload checksum (enabled with jumbos/packet-split when
5231 * Rx checksum is enabled) and generation of RSS hash is
5232 * mutually exclusive in the hardware.
5233 */
5234 if ((netdev->features & NETIF_F_RXCSUM) &&
5235 (netdev->features & NETIF_F_RXHASH)) {
5236 e_err("Jumbo frames cannot be enabled when both receive checksum offload and receive hashing are enabled. Disable one of the receive offload features before enabling jumbos.\n");
5237 return -EINVAL;
5238 }
bc7f75fa
AK		 5239 }
5240
2adc55c9
BA		 5241 /* Supported frame sizes */
5242 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5243 (max_frame > adapter->max_hw_frame_size)) {
5244 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5245 return -EINVAL;
5246 }
5247
a1ce6473
BA		 5248 /* Jumbo frame workaround on 82579 requires CRC be stripped */
5249 if ((adapter->hw.mac.type == e1000_pch2lan) &&
5250 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5251 (new_mtu > ETH_DATA_LEN)) {
ef456f85 5252 e_err("Jumbo Frames not supported on 82579 when CRC stripping is disabled.\n");
a1ce6473
BA		 5253 return -EINVAL;
5254 }
5255
6f461f6c
BA		 5256 /* 82573 Errata 17 */
5257 if (((adapter->hw.mac.type == e1000_82573) ||
5258 (adapter->hw.mac.type == e1000_82574)) &&
5259 (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN)) {
5260 adapter->flags2 |= FLAG2_DISABLE_ASPM_L1;
5261 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L1);
5262 }
5263
bc7f75fa 5264 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5265 usleep_range(1000, 2000);
610c9928 5266 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5267 adapter->max_frame_size = max_frame;
610c9928
BA		 5268 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5269 netdev->mtu = new_mtu;
bc7f75fa
AK		 5270 if (netif_running(netdev))
5271 e1000e_down(adapter);
5272
ad68076e
BA		 5273 /*
5274 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5275 * means we reserve 2 more, this pushes us to allocate from the next
5276 * larger slab size.
ad68076e 5277 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5278 * However with the new *_jumbo_rx* routines, jumbo receives will use
5279 * fragmented skbs
ad68076e 5280 */
bc7f75fa 5281
9926146b 5282 if (max_frame <= 2048)
bc7f75fa
AK		 5283 adapter->rx_buffer_len = 2048;
5284 else
5285 adapter->rx_buffer_len = 4096;
5286
5287 /* adjust allocation if LPE protects us, and we aren't using SBP */
5288 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5289 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5290 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5291 + ETH_FCS_LEN;
bc7f75fa 5292
bc7f75fa
AK		 5293 if (netif_running(netdev))
5294 e1000e_up(adapter);
5295 else
5296 e1000e_reset(adapter);
5297
5298 clear_bit(__E1000_RESETTING, &adapter->state);
5299
5300 return 0;
5301}
5302
5303static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5304 int cmd)
5305{
5306 struct e1000_adapter *adapter = netdev_priv(netdev);
5307 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5308
318a94d6 5309 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5310 return -EOPNOTSUPP;
5311
5312 switch (cmd) {
5313 case SIOCGMIIPHY:
5314 data->phy_id = adapter->hw.phy.addr;
5315 break;
5316 case SIOCGMIIREG:
b16a002e
BA		 5317 e1000_phy_read_status(adapter);
5318
7c25769f
BA		 5319 switch (data->reg_num & 0x1F) {
5320 case MII_BMCR:
5321 data->val_out = adapter->phy_regs.bmcr;
5322 break;
5323 case MII_BMSR:
5324 data->val_out = adapter->phy_regs.bmsr;
5325 break;
5326 case MII_PHYSID1:
5327 data->val_out = (adapter->hw.phy.id >> 16);
5328 break;
5329 case MII_PHYSID2:
5330 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5331 break;
5332 case MII_ADVERTISE:
5333 data->val_out = adapter->phy_regs.advertise;
5334 break;
5335 case MII_LPA:
5336 data->val_out = adapter->phy_regs.lpa;
5337 break;
5338 case MII_EXPANSION:
5339 data->val_out = adapter->phy_regs.expansion;
5340 break;
5341 case MII_CTRL1000:
5342 data->val_out = adapter->phy_regs.ctrl1000;
5343 break;
5344 case MII_STAT1000:
5345 data->val_out = adapter->phy_regs.stat1000;
5346 break;
5347 case MII_ESTATUS:
5348 data->val_out = adapter->phy_regs.estatus;
5349 break;
5350 default:
bc7f75fa
AK		 5351 return -EIO;
5352 }
bc7f75fa
AK		 5353 break;
5354 case SIOCSMIIREG:
5355 default:
5356 return -EOPNOTSUPP;
5357 }
5358 return 0;
5359}
5360
5361static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5362{
5363 switch (cmd) {
5364 case SIOCGMIIPHY:
5365 case SIOCGMIIREG:
5366 case SIOCSMIIREG:
5367 return e1000_mii_ioctl(netdev, ifr, cmd);
5368 default:
5369 return -EOPNOTSUPP;
5370 }
5371}
5372
a4f58f54
BA		 5373static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5374{
5375 struct e1000_hw *hw = &adapter->hw;
5376 u32 i, mac_reg;
2b6b168d 5377 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5378 int retval = 0;
5379
5380 /* copy MAC RARs to PHY RARs */
d3738bb8 5381 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5382
2b6b168d
BA		 5383 retval = hw->phy.ops.acquire(hw);
5384 if (retval) {
5385 e_err("Could not acquire PHY\n");
5386 return retval;
5387 }
5388
5389 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5390 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5391 if (retval)
5392 goto out;
5393
5394 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5395 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5396 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5397 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5398 (u16)(mac_reg & 0xFFFF));
5399 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5400 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5401 }
5402
5403 /* configure PHY Rx Control register */
2b6b168d 5404 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5405 mac_reg = er32(RCTL);
5406 if (mac_reg & E1000_RCTL_UPE)
5407 phy_reg |= BM_RCTL_UPE;
5408 if (mac_reg & E1000_RCTL_MPE)
5409 phy_reg |= BM_RCTL_MPE;
5410 phy_reg &= ~(BM_RCTL_MO_MASK);
5411 if (mac_reg & E1000_RCTL_MO_3)
5412 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5413 << BM_RCTL_MO_SHIFT);
5414 if (mac_reg & E1000_RCTL_BAM)
5415 phy_reg |= BM_RCTL_BAM;
5416 if (mac_reg & E1000_RCTL_PMCF)
5417 phy_reg |= BM_RCTL_PMCF;
5418 mac_reg = er32(CTRL);
5419 if (mac_reg & E1000_CTRL_RFCE)
5420 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5421 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5422
5423 /* enable PHY wakeup in MAC register */
5424 ew32(WUFC, wufc);
5425 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5426
5427 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5428 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5429 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5430
5431 /* activate PHY wakeup */
2b6b168d
BA		 5432 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5433 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5434 if (retval)
5435 e_err("Could not set PHY Host Wakeup bit\n");
5436out:
94d8186a 5437 hw->phy.ops.release(hw);
a4f58f54
BA		 5438
5439 return retval;
5440}
5441
23606cf5
RW		 5442static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5443 bool runtime)
bc7f75fa
AK		 5444{
5445 struct net_device *netdev = pci_get_drvdata(pdev);
5446 struct e1000_adapter *adapter = netdev_priv(netdev);
5447 struct e1000_hw *hw = &adapter->hw;
5448 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5449 /* Runtime suspend should only enable wakeup for link changes */
5450 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5451 int retval = 0;
5452
5453 netif_device_detach(netdev);
5454
5455 if (netif_running(netdev)) {
5456 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5457 e1000e_down(adapter);
5458 e1000_free_irq(adapter);
5459 }
4662e82b 5460 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5461
5462 retval = pci_save_state(pdev);
5463 if (retval)
5464 return retval;
5465
5466 status = er32(STATUS);
5467 if (status & E1000_STATUS_LU)
5468 wufc &= ~E1000_WUFC_LNKC;
5469
5470 if (wufc) {
5471 e1000_setup_rctl(adapter);
ef9b965a 5472 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5473
5474 /* turn on all-multi mode if wake on multicast is enabled */
5475 if (wufc & E1000_WUFC_MC) {
5476 rctl = er32(RCTL);
5477 rctl |= E1000_RCTL_MPE;
5478 ew32(RCTL, rctl);
5479 }
5480
5481 ctrl = er32(CTRL);
5482 /* advertise wake from D3Cold */
5483 #define E1000_CTRL_ADVD3WUC 0x00100000
5484 /* phy power management enable */
5485 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5486 ctrl |= E1000_CTRL_ADVD3WUC;
5487 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5488 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5489 ew32(CTRL, ctrl);
5490
318a94d6
JK		 5491 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5492 adapter->hw.phy.media_type ==
5493 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5494 /* keep the laser running in D3 */
5495 ctrl_ext = er32(CTRL_EXT);
93a23f48 5496 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5497 ew32(CTRL_EXT, ctrl_ext);
5498 }
5499
97ac8cae 5500 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5501 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5502
bc7f75fa
AK		 5503 /* Allow time for pending master requests to run */
5504 e1000e_disable_pcie_master(&adapter->hw);
5505
82776a4b 5506 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5507 /* enable wakeup by the PHY */
5508 retval = e1000_init_phy_wakeup(adapter, wufc);
5509 if (retval)
5510 return retval;
5511 } else {
5512 /* enable wakeup by the MAC */
5513 ew32(WUFC, wufc);
5514 ew32(WUC, E1000_WUC_PME_EN);
5515 }
bc7f75fa
AK		 5516 } else {
5517 ew32(WUC, 0);
5518 ew32(WUFC, 0);
bc7f75fa
AK		 5519 }
5520
4f9de721
RW		 5521 *enable_wake = !!wufc;
5522
bc7f75fa 5523 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5524 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5525 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5526 *enable_wake = true;
bc7f75fa
AK		 5527
5528 if (adapter->hw.phy.type == e1000_phy_igp_3)
5529 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5530
ad68076e
BA		 5531 /*
5532 * Release control of h/w to f/w. If f/w is AMT enabled, this
5533 * would have already happened in close and is redundant.
5534 */
31dbe5b4 5535 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5536
5537 pci_disable_device(pdev);
5538
4f9de721
RW		 5539 return 0;
5540}
5541
5542static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5543{
5544 if (sleep && wake) {
5545 pci_prepare_to_sleep(pdev);
5546 return;
5547 }
5548
5549 pci_wake_from_d3(pdev, wake);
5550 pci_set_power_state(pdev, PCI_D3hot);
5551}
5552
5553static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5554 bool wake)
5555{
5556 struct net_device *netdev = pci_get_drvdata(pdev);
5557 struct e1000_adapter *adapter = netdev_priv(netdev);
5558
005cbdfc
AD		 5559 /*
5560 * The pci-e switch on some quad port adapters will report a
5561 * correctable error when the MAC transitions from D0 to D3. To
5562 * prevent this we need to mask off the correctable errors on the
5563 * downstream port of the pci-e switch.
5564 */
5565 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5566 struct pci_dev *us_dev = pdev->bus->self;
353064de 5567 int pos = pci_pcie_cap(us_dev);
005cbdfc
AD		 5568 u16 devctl;
5569
5570 pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
5571 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
5572 (devctl & ~PCI_EXP_DEVCTL_CERE));
5573
4f9de721 5574 e1000_power_off(pdev, sleep, wake);
005cbdfc
AD		 5575
5576 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
5577 } else {
4f9de721 5578 e1000_power_off(pdev, sleep, wake);
005cbdfc 5579 }
bc7f75fa
AK		 5580}
5581
6f461f6c
BA		 5582#ifdef CONFIG_PCIEASPM
5583static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5584{
9f728f53 5585 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5586}
5587#else
5588static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2
AK		 5589{
5590 int pos;
6f461f6c 5591 u16 reg16;
1eae4eb2
AK		 5592
5593 /*
6f461f6c
BA		 5594 * Both device and parent should have the same ASPM setting.
5595 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5596 */
6f461f6c
BA		 5597 pos = pci_pcie_cap(pdev);
5598 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
5599 reg16 &= ~state;
5600 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
5601
0c75ba22
AB		 5602 if (!pdev->bus->self)
5603 return;
5604
6f461f6c
BA		 5605 pos = pci_pcie_cap(pdev->bus->self);
5606 pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, &reg16);
5607 reg16 &= ~state;
5608 pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
5609}
5610#endif
78cd29d5 5611static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5612{
5613 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5614 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5615 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5616
5617 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5618}
5619
aa338601 5620#ifdef CONFIG_PM
23606cf5 5621static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5622{
23606cf5 5623 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5624}
5625
23606cf5 5626static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5627{
5628 struct net_device *netdev = pci_get_drvdata(pdev);
5629 struct e1000_adapter *adapter = netdev_priv(netdev);
5630 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5631 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5632 u32 err;
5633
78cd29d5
BA		 5634 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5635 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5636 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5637 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5638 if (aspm_disable_flag)
5639 e1000e_disable_aspm(pdev, aspm_disable_flag);
5640
bc7f75fa
AK		 5641 pci_set_power_state(pdev, PCI_D0);
5642 pci_restore_state(pdev);
28b8f04a 5643 pci_save_state(pdev);
6e4f6f6b 5644
4662e82b 5645 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5646 if (netif_running(netdev)) {
5647 err = e1000_request_irq(adapter);
5648 if (err)
5649 return err;
5650 }
5651
99730e4c
BA		 5652 if (hw->mac.type == e1000_pch2lan)
5653 e1000_resume_workarounds_pchlan(&adapter->hw);
5654
bc7f75fa 5655 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5656
5657 /* report the system wakeup cause from S3/S4 */
5658 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5659 u16 phy_data;
5660
5661 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5662 if (phy_data) {
5663 e_info("PHY Wakeup cause - %s\n",
5664 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5665 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5666 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5667 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5668 phy_data & E1000_WUS_LNKC ?
5669 "Link Status Change" : "other");
a4f58f54
BA		 5670 }
5671 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5672 } else {
5673 u32 wus = er32(WUS);
5674 if (wus) {
5675 e_info("MAC Wakeup cause - %s\n",
5676 wus & E1000_WUS_EX ? "Unicast Packet" :
5677 wus & E1000_WUS_MC ? "Multicast Packet" :
5678 wus & E1000_WUS_BC ? "Broadcast Packet" :
5679 wus & E1000_WUS_MAG ? "Magic Packet" :
5680 wus & E1000_WUS_LNKC ? "Link Status Change" :
5681 "other");
5682 }
5683 ew32(WUS, ~0);
5684 }
5685
bc7f75fa 5686 e1000e_reset(adapter);
bc7f75fa 5687
cd791618 5688 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5689
5690 if (netif_running(netdev))
5691 e1000e_up(adapter);
5692
5693 netif_device_attach(netdev);
5694
ad68076e
BA		 5695 /*
5696 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5697 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5698 * under the control of the driver.
5699 */
c43bc57e 5700 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5701 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5702
5703 return 0;
5704}
23606cf5 5705
a0340162
RW		 5706#ifdef CONFIG_PM_SLEEP
5707static int e1000_suspend(struct device *dev)
5708{
5709 struct pci_dev *pdev = to_pci_dev(dev);
5710 int retval;
5711 bool wake;
5712
5713 retval = __e1000_shutdown(pdev, &wake, false);
5714 if (!retval)
5715 e1000_complete_shutdown(pdev, true, wake);
5716
5717 return retval;
5718}
5719
23606cf5
RW		 5720static int e1000_resume(struct device *dev)
5721{
5722 struct pci_dev *pdev = to_pci_dev(dev);
5723 struct net_device *netdev = pci_get_drvdata(pdev);
5724 struct e1000_adapter *adapter = netdev_priv(netdev);
5725
5726 if (e1000e_pm_ready(adapter))
5727 adapter->idle_check = true;
5728
5729 return __e1000_resume(pdev);
5730}
a0340162
RW		 5731#endif /* CONFIG_PM_SLEEP */
5732
5733#ifdef CONFIG_PM_RUNTIME
5734static int e1000_runtime_suspend(struct device *dev)
5735{
5736 struct pci_dev *pdev = to_pci_dev(dev);
5737 struct net_device *netdev = pci_get_drvdata(pdev);
5738 struct e1000_adapter *adapter = netdev_priv(netdev);
5739
5740 if (e1000e_pm_ready(adapter)) {
5741 bool wake;
5742
5743 __e1000_shutdown(pdev, &wake, true);
5744 }
5745
5746 return 0;
5747}
5748
5749static int e1000_idle(struct device *dev)
5750{
5751 struct pci_dev *pdev = to_pci_dev(dev);
5752 struct net_device *netdev = pci_get_drvdata(pdev);
5753 struct e1000_adapter *adapter = netdev_priv(netdev);
5754
5755 if (!e1000e_pm_ready(adapter))
5756 return 0;
5757
5758 if (adapter->idle_check) {
5759 adapter->idle_check = false;
5760 if (!e1000e_has_link(adapter))
5761 pm_schedule_suspend(dev, MSEC_PER_SEC);
5762 }
5763
5764 return -EBUSY;
5765}
23606cf5
RW		 5766
5767static int e1000_runtime_resume(struct device *dev)
5768{
5769 struct pci_dev *pdev = to_pci_dev(dev);
5770 struct net_device *netdev = pci_get_drvdata(pdev);
5771 struct e1000_adapter *adapter = netdev_priv(netdev);
5772
5773 if (!e1000e_pm_ready(adapter))
5774 return 0;
5775
5776 adapter->idle_check = !dev->power.runtime_auto;
5777 return __e1000_resume(pdev);
5778}
a0340162 5779#endif /* CONFIG_PM_RUNTIME */
aa338601 5780#endif /* CONFIG_PM */
bc7f75fa
AK		 5781
5782static void e1000_shutdown(struct pci_dev *pdev)
5783{
4f9de721
RW		 5784 bool wake = false;
5785
23606cf5 5786 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 5787
5788 if (system_state == SYSTEM_POWER_OFF)
5789 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 5790}
5791
5792#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 5793
5794static irqreturn_t e1000_intr_msix(int irq, void *data)
5795{
5796 struct net_device *netdev = data;
5797 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 5798
5799 if (adapter->msix_entries) {
90da0669
BA		 5800 int vector, msix_irq;
5801
147b2c8c
DD		 5802 vector = 0;
5803 msix_irq = adapter->msix_entries[vector].vector;
5804 disable_irq(msix_irq);
5805 e1000_intr_msix_rx(msix_irq, netdev);
5806 enable_irq(msix_irq);
5807
5808 vector++;
5809 msix_irq = adapter->msix_entries[vector].vector;
5810 disable_irq(msix_irq);
5811 e1000_intr_msix_tx(msix_irq, netdev);
5812 enable_irq(msix_irq);
5813
5814 vector++;
5815 msix_irq = adapter->msix_entries[vector].vector;
5816 disable_irq(msix_irq);
5817 e1000_msix_other(msix_irq, netdev);
5818 enable_irq(msix_irq);
5819 }
5820
5821 return IRQ_HANDLED;
5822}
5823
bc7f75fa
AK		 5824/*
5825 * Polling 'interrupt' - used by things like netconsole to send skbs
5826 * without having to re-enable interrupts. It's not called while
5827 * the interrupt routine is executing.
5828 */
5829static void e1000_netpoll(struct net_device *netdev)
5830{
5831 struct e1000_adapter *adapter = netdev_priv(netdev);
5832
147b2c8c
DD		 5833 switch (adapter->int_mode) {
5834 case E1000E_INT_MODE_MSIX:
5835 e1000_intr_msix(adapter->pdev->irq, netdev);
5836 break;
5837 case E1000E_INT_MODE_MSI:
5838 disable_irq(adapter->pdev->irq);
5839 e1000_intr_msi(adapter->pdev->irq, netdev);
5840 enable_irq(adapter->pdev->irq);
5841 break;
5842 default: /* E1000E_INT_MODE_LEGACY */
5843 disable_irq(adapter->pdev->irq);
5844 e1000_intr(adapter->pdev->irq, netdev);
5845 enable_irq(adapter->pdev->irq);
5846 break;
5847 }
bc7f75fa
AK		 5848}
5849#endif
5850
5851/**
5852 * e1000_io_error_detected - called when PCI error is detected
5853 * @pdev: Pointer to PCI device
5854 * @state: The current pci connection state
5855 *
5856 * This function is called after a PCI bus error affecting
5857 * this device has been detected.
5858 */
5859static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
5860 pci_channel_state_t state)
5861{
5862 struct net_device *netdev = pci_get_drvdata(pdev);
5863 struct e1000_adapter *adapter = netdev_priv(netdev);
5864
5865 netif_device_detach(netdev);
5866
c93b5a76
MM		 5867 if (state == pci_channel_io_perm_failure)
5868 return PCI_ERS_RESULT_DISCONNECT;
5869
bc7f75fa
AK		 5870 if (netif_running(netdev))
5871 e1000e_down(adapter);
5872 pci_disable_device(pdev);
5873
5874 /* Request a slot slot reset. */
5875 return PCI_ERS_RESULT_NEED_RESET;
5876}
5877
5878/**
5879 * e1000_io_slot_reset - called after the pci bus has been reset.
5880 * @pdev: Pointer to PCI device
5881 *
5882 * Restart the card from scratch, as if from a cold-boot. Implementation
5883 * resembles the first-half of the e1000_resume routine.
5884 */
5885static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5886{
5887 struct net_device *netdev = pci_get_drvdata(pdev);
5888 struct e1000_adapter *adapter = netdev_priv(netdev);
5889 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5890 u16 aspm_disable_flag = 0;
6e4f6f6b 5891 int err;
111b9dc5 5892 pci_ers_result_t result;
bc7f75fa 5893
78cd29d5
BA		 5894 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5895 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5896 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 5897 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5898 if (aspm_disable_flag)
5899 e1000e_disable_aspm(pdev, aspm_disable_flag);
5900
f0f422e5 5901 err = pci_enable_device_mem(pdev);
6e4f6f6b 5902 if (err) {
bc7f75fa
AK		 5903 dev_err(&pdev->dev,
5904 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 5905 result = PCI_ERS_RESULT_DISCONNECT;
5906 } else {
5907 pci_set_master(pdev);
23606cf5 5908 pdev->state_saved = true;
111b9dc5 5909 pci_restore_state(pdev);
bc7f75fa 5910
111b9dc5
JB		 5911 pci_enable_wake(pdev, PCI_D3hot, 0);
5912 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 5913
111b9dc5
JB		 5914 e1000e_reset(adapter);
5915 ew32(WUS, ~0);
5916 result = PCI_ERS_RESULT_RECOVERED;
5917 }
bc7f75fa 5918
111b9dc5
JB		 5919 pci_cleanup_aer_uncorrect_error_status(pdev);
5920
5921 return result;
bc7f75fa
AK		 5922}
5923
5924/**
5925 * e1000_io_resume - called when traffic can start flowing again.
5926 * @pdev: Pointer to PCI device
5927 *
5928 * This callback is called when the error recovery driver tells us that
5929 * its OK to resume normal operation. Implementation resembles the
5930 * second-half of the e1000_resume routine.
5931 */
5932static void e1000_io_resume(struct pci_dev *pdev)
5933{
5934 struct net_device *netdev = pci_get_drvdata(pdev);
5935 struct e1000_adapter *adapter = netdev_priv(netdev);
5936
cd791618 5937 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5938
5939 if (netif_running(netdev)) {
5940 if (e1000e_up(adapter)) {
5941 dev_err(&pdev->dev,
5942 "can't bring device back up after reset\n");
5943 return;
5944 }
5945 }
5946
5947 netif_device_attach(netdev);
5948
ad68076e
BA		 5949 /*
5950 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5951 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5952 * under the control of the driver.
5953 */
c43bc57e 5954 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5955 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5956
5957}
5958
5959static void e1000_print_device_info(struct e1000_adapter *adapter)
5960{
5961 struct e1000_hw *hw = &adapter->hw;
5962 struct net_device *netdev = adapter->netdev;
073287c0
BA		 5963 u32 ret_val;
5964 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 5965
5966 /* print bus type/speed/width info */
a5cc7642 5967 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 5968 /* bus width */
5969 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
5970 "Width x1"),
5971 /* MAC address */
7c510e4b 5972 netdev->dev_addr);
44defeb3
JK		 5973 e_info("Intel(R) PRO/%s Network Connection\n",
5974 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 5975 ret_val = e1000_read_pba_string_generic(hw, pba_str,
5976 E1000_PBANUM_LENGTH);
5977 if (ret_val)
e0dc4f12 5978 strncpy((char *)pba_str, "Unknown", sizeof(pba_str) - 1);
073287c0
BA		 5979 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
5980 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 5981}
5982
10aa4c04
AK		 5983static void e1000_eeprom_checks(struct e1000_adapter *adapter)
5984{
5985 struct e1000_hw *hw = &adapter->hw;
5986 int ret_val;
5987 u16 buf = 0;
5988
5989 if (hw->mac.type != e1000_82573)
5990 return;
5991
5992 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e243455d 5993 if (!ret_val && (!(le16_to_cpu(buf) & (1 << 0)))) {
10aa4c04 5994 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 5995 dev_warn(&adapter->pdev->dev,
5996 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 5997 }
10aa4c04
AK		 5998}
5999
c8f44aff 6000static int e1000_set_features(struct net_device *netdev,
70495a50 6001 netdev_features_t features)
dc221294
BA		 6002{
6003 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6004 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6005
6006 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6007 adapter->flags |= FLAG_TSO_FORCE;
6008
6009 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
70495a50 6010 NETIF_F_RXCSUM | NETIF_F_RXHASH)))
dc221294
BA		 6011 return 0;
6012
70495a50
BA		 6013 /*
6014 * IP payload checksum (enabled with jumbos/packet-split when Rx
6015 * checksum is enabled) and generation of RSS hash is mutually
6016 * exclusive in the hardware.
6017 */
6018 if (adapter->rx_ps_pages &&
6019 (features & NETIF_F_RXCSUM) && (features & NETIF_F_RXHASH)) {
6020 e_err("Enabling both receive checksum offload and receive hashing is not possible with jumbo frames. Disable jumbos or enable only one of the receive offload features.\n");
6021 return -EINVAL;
6022 }
6023
6024 netdev->features = features;
6025
dc221294
BA		 6026 if (netif_running(netdev))
6027 e1000e_reinit_locked(adapter);
6028 else
6029 e1000e_reset(adapter);
6030
6031 return 0;
6032}
6033
651c2466
SH		 6034static const struct net_device_ops e1000e_netdev_ops = {
6035 .ndo_open = e1000_open,
6036 .ndo_stop = e1000_close,
00829823 6037 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6038 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6039 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6040 .ndo_set_mac_address = e1000_set_mac,
6041 .ndo_change_mtu = e1000_change_mtu,
6042 .ndo_do_ioctl = e1000_ioctl,
6043 .ndo_tx_timeout = e1000_tx_timeout,
6044 .ndo_validate_addr = eth_validate_addr,
6045
651c2466
SH		 6046 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6047 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6048#ifdef CONFIG_NET_POLL_CONTROLLER
6049 .ndo_poll_controller = e1000_netpoll,
6050#endif
dc221294 6051 .ndo_set_features = e1000_set_features,
651c2466
SH		 6052};
6053
bc7f75fa
AK		 6054/**
6055 * e1000_probe - Device Initialization Routine
6056 * @pdev: PCI device information struct
6057 * @ent: entry in e1000_pci_tbl
6058 *
6059 * Returns 0 on success, negative on failure
6060 *
6061 * e1000_probe initializes an adapter identified by a pci_dev structure.
6062 * The OS initialization, configuring of the adapter private structure,
6063 * and a hardware reset occur.
6064 **/
6065static int __devinit e1000_probe(struct pci_dev *pdev,
6066 const struct pci_device_id *ent)
6067{
6068 struct net_device *netdev;
6069 struct e1000_adapter *adapter;
6070 struct e1000_hw *hw;
6071 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6072 resource_size_t mmio_start, mmio_len;
6073 resource_size_t flash_start, flash_len;
bc7f75fa
AK		 6074
6075 static int cards_found;
78cd29d5 6076 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6077 int i, err, pci_using_dac;
6078 u16 eeprom_data = 0;
6079 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6080
78cd29d5
BA		 6081 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6082 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6083 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6084 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6085 if (aspm_disable_flag)
6086 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6087
f0f422e5 6088 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6089 if (err)
6090 return err;
6091
6092 pci_using_dac = 0;
0be3f55f 6093 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6094 if (!err) {
0be3f55f 6095 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6096 if (!err)
6097 pci_using_dac = 1;
6098 } else {
0be3f55f 6099 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6100 if (err) {
0be3f55f
NN		 6101 err = dma_set_coherent_mask(&pdev->dev,
6102 DMA_BIT_MASK(32));
bc7f75fa 6103 if (err) {
ef456f85 6104 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6105 goto err_dma;
6106 }
6107 }
6108 }
6109
e8de1481 6110 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6111 pci_select_bars(pdev, IORESOURCE_MEM),
6112 e1000e_driver_name);
bc7f75fa
AK		 6113 if (err)
6114 goto err_pci_reg;
6115
68eac460 6116 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6117 pci_enable_pcie_error_reporting(pdev);
68eac460 6118
bc7f75fa 6119 pci_set_master(pdev);
438b365a
BA		 6120 /* PCI config space info */
6121 err = pci_save_state(pdev);
6122 if (err)
6123 goto err_alloc_etherdev;
bc7f75fa
AK		 6124
6125 err = -ENOMEM;
6126 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6127 if (!netdev)
6128 goto err_alloc_etherdev;
6129
bc7f75fa
AK		 6130 SET_NETDEV_DEV(netdev, &pdev->dev);
6131
f85e4dfa
TH		 6132 netdev->irq = pdev->irq;
6133
bc7f75fa
AK		 6134 pci_set_drvdata(pdev, netdev);
6135 adapter = netdev_priv(netdev);
6136 hw = &adapter->hw;
6137 adapter->netdev = netdev;
6138 adapter->pdev = pdev;
6139 adapter->ei = ei;
6140 adapter->pba = ei->pba;
6141 adapter->flags = ei->flags;
eb7c3adb 6142 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6143 adapter->hw.adapter = adapter;
6144 adapter->hw.mac.type = ei->mac;
2adc55c9 6145 adapter->max_hw_frame_size = ei->max_hw_frame_size;
bc7f75fa
AK		 6146 adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1;
6147
6148 mmio_start = pci_resource_start(pdev, 0);
6149 mmio_len = pci_resource_len(pdev, 0);
6150
6151 err = -EIO;
6152 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6153 if (!adapter->hw.hw_addr)
6154 goto err_ioremap;
6155
6156 if ((adapter->flags & FLAG_HAS_FLASH) &&
6157 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6158 flash_start = pci_resource_start(pdev, 1);
6159 flash_len = pci_resource_len(pdev, 1);
6160 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6161 if (!adapter->hw.flash_address)
6162 goto err_flashmap;
6163 }
6164
6165 /* construct the net_device struct */
651c2466 6166 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6167 e1000e_set_ethtool_ops(netdev);
bc7f75fa
AK		 6168 netdev->watchdog_timeo = 5 * HZ;
6169 netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
bc7f75fa
AK		 6170 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
6171
6172 netdev->mem_start = mmio_start;
6173 netdev->mem_end = mmio_start + mmio_len;
6174
6175 adapter->bd_number = cards_found++;
6176
4662e82b
BA		 6177 e1000e_check_options(adapter);
6178
bc7f75fa
AK		 6179 /* setup adapter struct */
6180 err = e1000_sw_init(adapter);
6181 if (err)
6182 goto err_sw_init;
6183
bc7f75fa
AK		 6184 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6185 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6186 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6187
69e3fd8c 6188 err = ei->get_variants(adapter);
bc7f75fa
AK		 6189 if (err)
6190 goto err_hw_init;
6191
4a770358
BA		 6192 if ((adapter->flags & FLAG_IS_ICH) &&
6193 (adapter->flags & FLAG_READ_ONLY_NVM))
6194 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6195
bc7f75fa
AK		 6196 hw->mac.ops.get_bus_info(&adapter->hw);
6197
318a94d6 6198 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6199
6200 /* Copper options */
318a94d6 6201 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6202 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6203 adapter->hw.phy.disable_polarity_correction = 0;
6204 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6205 }
6206
6207 if (e1000_check_reset_block(&adapter->hw))
44defeb3 6208 e_info("PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6209
dc221294
BA		 6210 /* Set initial default active device features */
6211 netdev->features = (NETIF_F_SG |
6212 NETIF_F_HW_VLAN_RX |
6213 NETIF_F_HW_VLAN_TX |
6214 NETIF_F_TSO |
6215 NETIF_F_TSO6 |
70495a50 6216 NETIF_F_RXHASH |
dc221294
BA		 6217 NETIF_F_RXCSUM |
6218 NETIF_F_HW_CSUM);
6219
6220 /* Set user-changeable features (subset of all device features) */
6221 netdev->hw_features = netdev->features;
bc7f75fa
AK		 6222
6223 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6224 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6225
dc221294
BA		 6226 netdev->vlan_features |= (NETIF_F_SG |
6227 NETIF_F_TSO |
6228 NETIF_F_TSO6 |
6229 NETIF_F_HW_CSUM);
a5136e23 6230
ef9b965a
JB		 6231 netdev->priv_flags |= IFF_UNICAST_FLT;
6232
7b872a55 6233 if (pci_using_dac) {
bc7f75fa 6234 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6235 netdev->vlan_features |= NETIF_F_HIGHDMA;
6236 }
bc7f75fa 6237
bc7f75fa
AK		 6238 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6239 adapter->flags |= FLAG_MNG_PT_ENABLED;
6240
ad68076e
BA		 6241 /*
6242 * before reading the NVM, reset the controller to
6243 * put the device in a known good starting state
6244 */
bc7f75fa
AK		 6245 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6246
6247 /*
6248 * systems with ASPM and others may see the checksum fail on the first
6249 * attempt. Let's give it a few tries
6250 */
6251 for (i = 0;; i++) {
6252 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6253 break;
6254 if (i == 2) {
44defeb3 6255 e_err("The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6256 err = -EIO;
6257 goto err_eeprom;
6258 }
6259 }
6260
10aa4c04
AK		 6261 e1000_eeprom_checks(adapter);
6262
608f8a0d 6263 /* copy the MAC address */
bc7f75fa 6264 if (e1000e_read_mac_addr(&adapter->hw))
44defeb3 6265 e_err("NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6266
6267 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
6268 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
6269
6270 if (!is_valid_ether_addr(netdev->perm_addr)) {
7c510e4b 6271 e_err("Invalid MAC Address: %pM\n", netdev->perm_addr);
bc7f75fa
AK		 6272 err = -EIO;
6273 goto err_eeprom;
6274 }
6275
6276 init_timer(&adapter->watchdog_timer);
c061b18d 6277 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6278 adapter->watchdog_timer.data = (unsigned long) adapter;
6279
6280 init_timer(&adapter->phy_info_timer);
c061b18d 6281 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6282 adapter->phy_info_timer.data = (unsigned long) adapter;
6283
6284 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6285 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6286 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6287 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6288 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6289
bc7f75fa
AK		 6290 /* Initialize link parameters. User can change them with ethtool */
6291 adapter->hw.mac.autoneg = 1;
3db1cd5c 6292 adapter->fc_autoneg = true;
5c48ef3e
BA		 6293 adapter->hw.fc.requested_mode = e1000_fc_default;
6294 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6295 adapter->hw.phy.autoneg_advertised = 0x2f;
6296
6297 /* ring size defaults */
6298 adapter->rx_ring->count = 256;
6299 adapter->tx_ring->count = 256;
6300
6301 /*
6302 * Initial Wake on LAN setting - If APM wake is enabled in
6303 * the EEPROM, enable the ACPI Magic Packet filter
6304 */
6305 if (adapter->flags & FLAG_APME_IN_WUC) {
6306 /* APME bit in EEPROM is mapped to WUC.APME */
6307 eeprom_data = er32(WUC);
6308 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6309 if ((hw->mac.type > e1000_ich10lan) &&
6310 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6311 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6312 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6313 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6314 (adapter->hw.bus.func == 1))
6315 e1000_read_nvm(&adapter->hw,
6316 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
6317 else
6318 e1000_read_nvm(&adapter->hw,
6319 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
6320 }
6321
6322 /* fetch WoL from EEPROM */
6323 if (eeprom_data & eeprom_apme_mask)
6324 adapter->eeprom_wol |= E1000_WUFC_MAG;
6325
6326 /*
6327 * now that we have the eeprom settings, apply the special cases
6328 * where the eeprom may be wrong or the board simply won't support
6329 * wake on lan on a particular port
6330 */
6331 if (!(adapter->flags & FLAG_HAS_WOL))
6332 adapter->eeprom_wol = 0;
6333
6334 /* initialize the wol settings based on the eeprom settings */
6335 adapter->wol = adapter->eeprom_wol;
6ff68026 6336 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6337
84527590
BA		 6338 /* save off EEPROM version number */
6339 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6340
bc7f75fa
AK		 6341 /* reset the hardware with the new settings */
6342 e1000e_reset(adapter);
6343
ad68076e
BA		 6344 /*
6345 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6346 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6347 * under the control of the driver.
6348 */
c43bc57e 6349 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6350 e1000e_get_hw_control(adapter);
bc7f75fa 6351
e0dc4f12 6352 strncpy(netdev->name, "eth%d", sizeof(netdev->name) - 1);
bc7f75fa
AK		 6353 err = register_netdev(netdev);
6354 if (err)
6355 goto err_register;
6356
9c563d20
JB		 6357 /* carrier off reporting is important to ethtool even BEFORE open */
6358 netif_carrier_off(netdev);
6359
bc7f75fa
AK		 6360 e1000_print_device_info(adapter);
6361
f3ec4f87
AS		 6362 if (pci_dev_run_wake(pdev))
6363 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6364
bc7f75fa
AK		 6365 return 0;
6366
6367err_register:
c43bc57e 6368 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6369 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 6370err_eeprom:
6371 if (!e1000_check_reset_block(&adapter->hw))
6372 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6373err_hw_init:
bc7f75fa
AK		 6374 kfree(adapter->tx_ring);
6375 kfree(adapter->rx_ring);
6376err_sw_init:
c43bc57e
JB		 6377 if (adapter->hw.flash_address)
6378 iounmap(adapter->hw.flash_address);
e82f54ba 6379 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6380err_flashmap:
bc7f75fa
AK		 6381 iounmap(adapter->hw.hw_addr);
6382err_ioremap:
6383 free_netdev(netdev);
6384err_alloc_etherdev:
f0f422e5
BA		 6385 pci_release_selected_regions(pdev,
6386 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6387err_pci_reg:
6388err_dma:
6389 pci_disable_device(pdev);
6390 return err;
6391}
6392
6393/**
6394 * e1000_remove - Device Removal Routine
6395 * @pdev: PCI device information struct
6396 *
6397 * e1000_remove is called by the PCI subsystem to alert the driver
6398 * that it should release a PCI device. The could be caused by a
6399 * Hot-Plug event, or because the driver is going to be removed from
6400 * memory.
6401 **/
6402static void __devexit e1000_remove(struct pci_dev *pdev)
6403{
6404 struct net_device *netdev = pci_get_drvdata(pdev);
6405 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6406 bool down = test_bit(__E1000_DOWN, &adapter->state);
6407
ad68076e 6408 /*
23f333a2
TH		 6409 * The timers may be rescheduled, so explicitly disable them
6410 * from being rescheduled.
ad68076e 6411 */
23606cf5
RW		 6412 if (!down)
6413 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6414 del_timer_sync(&adapter->watchdog_timer);
6415 del_timer_sync(&adapter->phy_info_timer);
6416
41cec6f1
BA		 6417 cancel_work_sync(&adapter->reset_task);
6418 cancel_work_sync(&adapter->watchdog_task);
6419 cancel_work_sync(&adapter->downshift_task);
6420 cancel_work_sync(&adapter->update_phy_task);
6421 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6422
17f208de
BA		 6423 if (!(netdev->flags & IFF_UP))
6424 e1000_power_down_phy(adapter);
6425
23606cf5
RW		 6426 /* Don't lie to e1000_close() down the road. */
6427 if (!down)
6428 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6429 unregister_netdev(netdev);
6430
f3ec4f87
AS		 6431 if (pci_dev_run_wake(pdev))
6432 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6433
ad68076e
BA		 6434 /*
6435 * Release control of h/w to f/w. If f/w is AMT enabled, this
6436 * would have already happened in close and is redundant.
6437 */
31dbe5b4 6438 e1000e_release_hw_control(adapter);
bc7f75fa 6439
4662e82b 6440 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6441 kfree(adapter->tx_ring);
6442 kfree(adapter->rx_ring);
6443
6444 iounmap(adapter->hw.hw_addr);
6445 if (adapter->hw.flash_address)
6446 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6447 pci_release_selected_regions(pdev,
6448 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6449
6450 free_netdev(netdev);
6451
111b9dc5 6452 /* AER disable */
19d5afd4 6453 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6454
bc7f75fa
AK		 6455 pci_disable_device(pdev);
6456}
6457
6458/* PCI Error Recovery (ERS) */
6459static struct pci_error_handlers e1000_err_handler = {
6460 .error_detected = e1000_io_error_detected,
6461 .slot_reset = e1000_io_slot_reset,
6462 .resume = e1000_io_resume,
6463};
6464
a3aa1884 6465static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6466 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6467 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6468 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6469 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6470 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6471 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6472 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6473 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6474 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6475
bc7f75fa
AK		 6476 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6477 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6478 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6479 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6480
bc7f75fa
AK		 6481 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6482 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6483 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6484
4662e82b 6485 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6487 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6488
bc7f75fa
AK		 6489 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6490 board_80003es2lan },
6491 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6492 board_80003es2lan },
6493 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6494 board_80003es2lan },
6495 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6496 board_80003es2lan },
ad68076e 6497
bc7f75fa
AK		 6498 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6499 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6500 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6501 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6502 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6504 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6505 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6506
bc7f75fa
AK		 6507 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6508 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6509 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6510 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6511 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6512 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6513 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6514 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6515 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6516
6517 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6518 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6519 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6520
f4187b56
BA		 6521 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6522 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6523 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6524
a4f58f54
BA		 6525 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6526 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6527 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6528 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6529
d3738bb8
BA		 6530 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6531 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6532
bc7f75fa
AK		 6533 { } /* terminate list */
6534};
6535MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6536
aa338601 6537#ifdef CONFIG_PM
23606cf5 6538static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6539 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6540 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6541 e1000_runtime_resume, e1000_idle)
23606cf5 6542};
e50208a0 6543#endif
23606cf5 6544
bc7f75fa
AK		 6545/* PCI Device API Driver */
6546static struct pci_driver e1000_driver = {
6547 .name = e1000e_driver_name,
6548 .id_table = e1000_pci_tbl,
6549 .probe = e1000_probe,
6550 .remove = __devexit_p(e1000_remove),
aa338601 6551#ifdef CONFIG_PM
23606cf5 6552 .driver.pm = &e1000_pm_ops,
bc7f75fa
AK		 6553#endif
6554 .shutdown = e1000_shutdown,
6555 .err_handler = &e1000_err_handler
6556};
6557
6558/**
6559 * e1000_init_module - Driver Registration Routine
6560 *
6561 * e1000_init_module is the first routine called when the driver is
6562 * loaded. All it does is register with the PCI subsystem.
6563 **/
6564static int __init e1000_init_module(void)
6565{
6566 int ret;
8544b9f7
BA		 6567 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6568 e1000e_driver_version);
0d6057e4 6569 pr_info("Copyright(c) 1999 - 2011 Intel Corporation.\n");
bc7f75fa 6570 ret = pci_register_driver(&e1000_driver);
53ec5498 6571
bc7f75fa
AK		 6572 return ret;
6573}
6574module_init(e1000_init_module);
6575
6576/**
6577 * e1000_exit_module - Driver Exit Cleanup Routine
6578 *
6579 * e1000_exit_module is called just before the driver is removed
6580 * from memory.
6581 **/
6582static void __exit e1000_exit_module(void)
6583{
6584 pci_unregister_driver(&e1000_driver);
6585}
6586module_exit(e1000_exit_module);
6587
6588
6589MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6590MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6591MODULE_LICENSE("GPL");
6592MODULE_VERSION(DRV_VERSION);
6593
6594/* e1000_main.c */
Linux 6.x block layer and io_uring tree(s)