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e1000e: concatenate long debug strings which span multiple lines
[linux-2.6-block.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
bc7f75fa
AK		 1/*******************************************************************************
2
3 Intel PRO/1000 Linux driver
0d6057e4 4 Copyright(c) 1999 - 2011 Intel Corporation.
bc7f75fa
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
8544b9f7
BA		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
bc7f75fa
AK		 31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/init.h>
34#include <linux/pci.h>
35#include <linux/vmalloc.h>
36#include <linux/pagemap.h>
37#include <linux/delay.h>
38#include <linux/netdevice.h>
9fb7a5f7 39#include <linux/interrupt.h>
bc7f75fa
AK		 40#include <linux/tcp.h>
41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
bc7f75fa
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/mii.h>
46#include <linux/ethtool.h>
47#include <linux/if_vlan.h>
48#include <linux/cpu.h>
49#include <linux/smp.h>
e8db0be1 50#include <linux/pm_qos.h>
23606cf5 51#include <linux/pm_runtime.h>
111b9dc5 52#include <linux/aer.h>
70c71606 53#include <linux/prefetch.h>
bc7f75fa
AK		 54
55#include "e1000.h"
56
b3ccf267 57#define DRV_EXTRAVERSION "-k"
c14c643b 58
c5778b43 59#define DRV_VERSION "1.5.1" DRV_EXTRAVERSION
bc7f75fa
AK		 60char e1000e_driver_name[] = "e1000e";
61const char e1000e_driver_version[] = DRV_VERSION;
62
78cd29d5
BA		 63static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state);
64
bc7f75fa
AK		 65static const struct e1000_info *e1000_info_tbl[] = {
66 [board_82571] = &e1000_82571_info,
67 [board_82572] = &e1000_82572_info,
68 [board_82573] = &e1000_82573_info,
4662e82b 69 [board_82574] = &e1000_82574_info,
8c81c9c3 70 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 71 [board_80003es2lan] = &e1000_es2_info,
72 [board_ich8lan] = &e1000_ich8_info,
73 [board_ich9lan] = &e1000_ich9_info,
f4187b56 74 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 75 [board_pchlan] = &e1000_pch_info,
d3738bb8 76 [board_pch2lan] = &e1000_pch2_info,
bc7f75fa
AK		 77};
78
84f4ee90
TI		 79struct e1000_reg_info {
80 u32 ofs;
81 char *name;
82};
83
af667a29
BA		 84#define E1000_RDFH 0x02410 /* Rx Data FIFO Head - RW */
85#define E1000_RDFT 0x02418 /* Rx Data FIFO Tail - RW */
86#define E1000_RDFHS 0x02420 /* Rx Data FIFO Head Saved - RW */
87#define E1000_RDFTS 0x02428 /* Rx Data FIFO Tail Saved - RW */
88#define E1000_RDFPC 0x02430 /* Rx Data FIFO Packet Count - RW */
89
90#define E1000_TDFH 0x03410 /* Tx Data FIFO Head - RW */
91#define E1000_TDFT 0x03418 /* Tx Data FIFO Tail - RW */
92#define E1000_TDFHS 0x03420 /* Tx Data FIFO Head Saved - RW */
93#define E1000_TDFTS 0x03428 /* Tx Data FIFO Tail Saved - RW */
94#define E1000_TDFPC 0x03430 /* Tx Data FIFO Packet Count - RW */
84f4ee90
TI		 95
96static const struct e1000_reg_info e1000_reg_info_tbl[] = {
97
98 /* General Registers */
99 {E1000_CTRL, "CTRL"},
100 {E1000_STATUS, "STATUS"},
101 {E1000_CTRL_EXT, "CTRL_EXT"},
102
103 /* Interrupt Registers */
104 {E1000_ICR, "ICR"},
105
af667a29 106 /* Rx Registers */
84f4ee90
TI		 107 {E1000_RCTL, "RCTL"},
108 {E1000_RDLEN, "RDLEN"},
109 {E1000_RDH, "RDH"},
110 {E1000_RDT, "RDT"},
111 {E1000_RDTR, "RDTR"},
112 {E1000_RXDCTL(0), "RXDCTL"},
113 {E1000_ERT, "ERT"},
114 {E1000_RDBAL, "RDBAL"},
115 {E1000_RDBAH, "RDBAH"},
116 {E1000_RDFH, "RDFH"},
117 {E1000_RDFT, "RDFT"},
118 {E1000_RDFHS, "RDFHS"},
119 {E1000_RDFTS, "RDFTS"},
120 {E1000_RDFPC, "RDFPC"},
121
af667a29 122 /* Tx Registers */
84f4ee90
TI		 123 {E1000_TCTL, "TCTL"},
124 {E1000_TDBAL, "TDBAL"},
125 {E1000_TDBAH, "TDBAH"},
126 {E1000_TDLEN, "TDLEN"},
127 {E1000_TDH, "TDH"},
128 {E1000_TDT, "TDT"},
129 {E1000_TIDV, "TIDV"},
130 {E1000_TXDCTL(0), "TXDCTL"},
131 {E1000_TADV, "TADV"},
132 {E1000_TARC(0), "TARC"},
133 {E1000_TDFH, "TDFH"},
134 {E1000_TDFT, "TDFT"},
135 {E1000_TDFHS, "TDFHS"},
136 {E1000_TDFTS, "TDFTS"},
137 {E1000_TDFPC, "TDFPC"},
138
139 /* List Terminator */
140 {}
141};
142
143/*
144 * e1000_regdump - register printout routine
145 */
146static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
147{
148 int n = 0;
149 char rname[16];
150 u32 regs[8];
151
152 switch (reginfo->ofs) {
153 case E1000_RXDCTL(0):
154 for (n = 0; n < 2; n++)
155 regs[n] = __er32(hw, E1000_RXDCTL(n));
156 break;
157 case E1000_TXDCTL(0):
158 for (n = 0; n < 2; n++)
159 regs[n] = __er32(hw, E1000_TXDCTL(n));
160 break;
161 case E1000_TARC(0):
162 for (n = 0; n < 2; n++)
163 regs[n] = __er32(hw, E1000_TARC(n));
164 break;
165 default:
ef456f85
JK		 166 pr_info("%-15s %08x\n",
167 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 168 return;
169 }
170
171 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 172 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 173}
174
84f4ee90 175/*
af667a29 176 * e1000e_dump - Print registers, Tx-ring and Rx-ring
84f4ee90
TI		 177 */
178static void e1000e_dump(struct e1000_adapter *adapter)
179{
180 struct net_device *netdev = adapter->netdev;
181 struct e1000_hw *hw = &adapter->hw;
182 struct e1000_reg_info *reginfo;
183 struct e1000_ring *tx_ring = adapter->tx_ring;
184 struct e1000_tx_desc *tx_desc;
af667a29
BA		 185 struct my_u0 {
186 u64 a;
187 u64 b;
188 } *u0;
84f4ee90
TI		 189 struct e1000_buffer *buffer_info;
190 struct e1000_ring *rx_ring = adapter->rx_ring;
191 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 192 union e1000_rx_desc_extended *rx_desc;
af667a29
BA		 193 struct my_u1 {
194 u64 a;
195 u64 b;
196 u64 c;
197 u64 d;
198 } *u1;
84f4ee90
TI		 199 u32 staterr;
200 int i = 0;
201
202 if (!netif_msg_hw(adapter))
203 return;
204
205 /* Print netdevice Info */
206 if (netdev) {
207 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85
JK		 208 pr_info("Device Name state trans_start last_rx\n");
209 pr_info("%-15s %016lX %016lX %016lX\n",
210 netdev->name, netdev->state, netdev->trans_start,
211 netdev->last_rx);
84f4ee90
TI		 212 }
213
214 /* Print Registers */
215 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 216 pr_info(" Register Name Value\n");
84f4ee90
TI		 217 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
218 reginfo->name; reginfo++) {
219 e1000_regdump(hw, reginfo);
220 }
221
af667a29 222 /* Print Tx Ring Summary */
84f4ee90
TI		 223 if (!netdev || !netif_running(netdev))
224 goto exit;
225
af667a29 226 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 227 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 228 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 229 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
230 0, tx_ring->next_to_use, tx_ring->next_to_clean,
231 (unsigned long long)buffer_info->dma,
232 buffer_info->length,
233 buffer_info->next_to_watch,
234 (unsigned long long)buffer_info->time_stamp);
84f4ee90 235
af667a29 236 /* Print Tx Ring */
84f4ee90
TI		 237 if (!netif_msg_tx_done(adapter))
238 goto rx_ring_summary;
239
af667a29 240 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 241
242 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
243 *
244 * Legacy Transmit Descriptor
245 * +--------------------------------------------------------------+
246 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
247 * +--------------------------------------------------------------+
248 * 8 | Special | CSS | Status | CMD | CSO | Length |
249 * +--------------------------------------------------------------+
250 * 63 48 47 36 35 32 31 24 23 16 15 0
251 *
252 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
253 * 63 48 47 40 39 32 31 16 15 8 7 0
254 * +----------------------------------------------------------------+
255 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
256 * +----------------------------------------------------------------+
257 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
258 * +----------------------------------------------------------------+
259 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
260 *
261 * Extended Data Descriptor (DTYP=0x1)
262 * +----------------------------------------------------------------+
263 * 0 | Buffer Address [63:0] |
264 * +----------------------------------------------------------------+
265 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
266 * +----------------------------------------------------------------+
267 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
268 */
ef456f85
JK		 269 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
270 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
271 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 272 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 273 const char *next_desc;
84f4ee90
TI		 274 tx_desc = E1000_TX_DESC(*tx_ring, i);
275 buffer_info = &tx_ring->buffer_info[i];
276 u0 = (struct my_u0 *)tx_desc;
84f4ee90 277 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 278 next_desc = " NTC/U";
84f4ee90 279 else if (i == tx_ring->next_to_use)
ef456f85 280 next_desc = " NTU";
84f4ee90 281 else if (i == tx_ring->next_to_clean)
ef456f85 282 next_desc = " NTC";
84f4ee90 283 else
ef456f85
JK		 284 next_desc = "";
285 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
286 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
287 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
288 i,
289 (unsigned long long)le64_to_cpu(u0->a),
290 (unsigned long long)le64_to_cpu(u0->b),
291 (unsigned long long)buffer_info->dma,
292 buffer_info->length, buffer_info->next_to_watch,
293 (unsigned long long)buffer_info->time_stamp,
294 buffer_info->skb, next_desc);
84f4ee90
TI		 295
296 if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
297 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
af667a29
BA		 298 16, 1, phys_to_virt(buffer_info->dma),
299 buffer_info->length, true);
84f4ee90
TI		 300 }
301
af667a29 302 /* Print Rx Ring Summary */
84f4ee90 303rx_ring_summary:
af667a29 304 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 305 pr_info("Queue [NTU] [NTC]\n");
306 pr_info(" %5d %5X %5X\n",
307 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 308
af667a29 309 /* Print Rx Ring */
84f4ee90
TI		 310 if (!netif_msg_rx_status(adapter))
311 goto exit;
312
af667a29 313 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 314 switch (adapter->rx_ps_pages) {
315 case 1:
316 case 2:
317 case 3:
318 /* [Extended] Packet Split Receive Descriptor Format
319 *
320 * +-----------------------------------------------------+
321 * 0 | Buffer Address 0 [63:0] |
322 * +-----------------------------------------------------+
323 * 8 | Buffer Address 1 [63:0] |
324 * +-----------------------------------------------------+
325 * 16 | Buffer Address 2 [63:0] |
326 * +-----------------------------------------------------+
327 * 24 | Buffer Address 3 [63:0] |
328 * +-----------------------------------------------------+
329 */
ef456f85 330 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 331 /* [Extended] Receive Descriptor (Write-Back) Format
332 *
333 * 63 48 47 32 31 13 12 8 7 4 3 0
334 * +------------------------------------------------------+
335 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
336 * | Checksum | Ident | | Queue | | Type |
337 * +------------------------------------------------------+
338 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
339 * +------------------------------------------------------+
340 * 63 48 47 32 31 20 19 0
341 */
ef456f85 342 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 343 for (i = 0; i < rx_ring->count; i++) {
ef456f85 344 const char *next_desc;
84f4ee90
TI		 345 buffer_info = &rx_ring->buffer_info[i];
346 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
347 u1 = (struct my_u1 *)rx_desc_ps;
348 staterr =
af667a29 349 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 350
351 if (i == rx_ring->next_to_use)
352 next_desc = " NTU";
353 else if (i == rx_ring->next_to_clean)
354 next_desc = " NTC";
355 else
356 next_desc = "";
357
84f4ee90
TI		 358 if (staterr & E1000_RXD_STAT_DD) {
359 /* Descriptor Done */
ef456f85
JK		 360 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
361 "RWB", i,
362 (unsigned long long)le64_to_cpu(u1->a),
363 (unsigned long long)le64_to_cpu(u1->b),
364 (unsigned long long)le64_to_cpu(u1->c),
365 (unsigned long long)le64_to_cpu(u1->d),
366 buffer_info->skb, next_desc);
84f4ee90 367 } else {
ef456f85
JK		 368 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
369 "R ", i,
370 (unsigned long long)le64_to_cpu(u1->a),
371 (unsigned long long)le64_to_cpu(u1->b),
372 (unsigned long long)le64_to_cpu(u1->c),
373 (unsigned long long)le64_to_cpu(u1->d),
374 (unsigned long long)buffer_info->dma,
375 buffer_info->skb, next_desc);
84f4ee90
TI		 376
377 if (netif_msg_pktdata(adapter))
378 print_hex_dump(KERN_INFO, "",
379 DUMP_PREFIX_ADDRESS, 16, 1,
380 phys_to_virt(buffer_info->dma),
381 adapter->rx_ps_bsize0, true);
382 }
84f4ee90
TI		 383 }
384 break;
385 default:
386 case 0:
5f450212 387 /* Extended Receive Descriptor (Read) Format
84f4ee90 388 *
5f450212
BA		 389 * +-----------------------------------------------------+
390 * 0 | Buffer Address [63:0] |
391 * +-----------------------------------------------------+
392 * 8 | Reserved |
393 * +-----------------------------------------------------+
84f4ee90 394 */
ef456f85 395 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 396 /* Extended Receive Descriptor (Write-Back) Format
397 *
398 * 63 48 47 32 31 24 23 4 3 0
399 * +------------------------------------------------------+
400 * | RSS Hash | | | |
401 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
402 * | Packet | IP | | | Type |
403 * | Checksum | Ident | | | |
404 * +------------------------------------------------------+
405 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
406 * +------------------------------------------------------+
407 * 63 48 47 32 31 20 19 0
408 */
ef456f85 409 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 410
411 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 412 const char *next_desc;
413
84f4ee90 414 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 415 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
416 u1 = (struct my_u1 *)rx_desc;
417 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 418
419 if (i == rx_ring->next_to_use)
420 next_desc = " NTU";
421 else if (i == rx_ring->next_to_clean)
422 next_desc = " NTC";
423 else
424 next_desc = "";
425
5f450212
BA		 426 if (staterr & E1000_RXD_STAT_DD) {
427 /* Descriptor Done */
ef456f85
JK		 428 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
429 "RWB", i,
430 (unsigned long long)le64_to_cpu(u1->a),
431 (unsigned long long)le64_to_cpu(u1->b),
432 buffer_info->skb, next_desc);
5f450212 433 } else {
ef456f85
JK		 434 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
435 "R ", i,
436 (unsigned long long)le64_to_cpu(u1->a),
437 (unsigned long long)le64_to_cpu(u1->b),
438 (unsigned long long)buffer_info->dma,
439 buffer_info->skb, next_desc);
5f450212
BA		 440
441 if (netif_msg_pktdata(adapter))
442 print_hex_dump(KERN_INFO, "",
443 DUMP_PREFIX_ADDRESS, 16,
444 1,
445 phys_to_virt
446 (buffer_info->dma),
447 adapter->rx_buffer_len,
448 true);
449 }
84f4ee90
TI		 450 }
451 }
452
453exit:
454 return;
455}
456
bc7f75fa
AK		 457/**
458 * e1000_desc_unused - calculate if we have unused descriptors
459 **/
460static int e1000_desc_unused(struct e1000_ring *ring)
461{
462 if (ring->next_to_clean > ring->next_to_use)
463 return ring->next_to_clean - ring->next_to_use - 1;
464
465 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
466}
467
468/**
ad68076e 469 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa
AK		 470 * @adapter: board private structure
471 * @status: descriptor status field as written by hardware
472 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
473 * @skb: pointer to sk_buff to be indicated to stack
474 **/
475static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 476 struct net_device *netdev, struct sk_buff *skb,
a39fe742 477 u8 status, __le16 vlan)
bc7f75fa 478{
86d70e53 479 u16 tag = le16_to_cpu(vlan);
bc7f75fa
AK		 480 skb->protocol = eth_type_trans(skb, netdev);
481
86d70e53
JK		 482 if (status & E1000_RXD_STAT_VP)
483 __vlan_hwaccel_put_tag(skb, tag);
484
485 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 486}
487
488/**
af667a29 489 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 490 * @adapter: board private structure
491 * @status_err: receive descriptor status and error fields
492 * @csum: receive descriptor csum field
493 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 494 **/
495static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
afd12939 496 __le16 csum, struct sk_buff *skb)
bc7f75fa
AK		 497{
498 u16 status = (u16)status_err;
499 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 500
501 skb_checksum_none_assert(skb);
bc7f75fa 502
afd12939
BA		 503 /* Rx checksum disabled */
504 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
505 return;
506
bc7f75fa
AK		 507 /* Ignore Checksum bit is set */
508 if (status & E1000_RXD_STAT_IXSM)
509 return;
afd12939 510
bc7f75fa
AK		 511 /* TCP/UDP checksum error bit is set */
512 if (errors & E1000_RXD_ERR_TCPE) {
513 /* let the stack verify checksum errors */
514 adapter->hw_csum_err++;
515 return;
516 }
517
518 /* TCP/UDP Checksum has not been calculated */
519 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
520 return;
521
522 /* It must be a TCP or UDP packet with a valid checksum */
523 if (status & E1000_RXD_STAT_TCPCS) {
524 /* TCP checksum is good */
525 skb->ip_summed = CHECKSUM_UNNECESSARY;
526 } else {
ad68076e
BA		 527 /*
528 * IP fragment with UDP payload
529 * Hardware complements the payload checksum, so we undo it
bc7f75fa
AK		 530 * and then put the value in host order for further stack use.
531 */
afd12939 532 __sum16 sum = (__force __sum16)swab16((__force u16)csum);
a39fe742 533 skb->csum = csum_unfold(~sum);
bc7f75fa
AK		 534 skb->ip_summed = CHECKSUM_COMPLETE;
535 }
536 adapter->hw_csum_good++;
537}
538
c6e7f51e
BA		 539/**
540 * e1000e_update_tail_wa - helper function for e1000e_update_[rt]dt_wa()
541 * @hw: pointer to the HW structure
542 * @tail: address of tail descriptor register
543 * @i: value to write to tail descriptor register
544 *
545 * When updating the tail register, the ME could be accessing Host CSR
546 * registers at the same time. Normally, this is handled in h/w by an
547 * arbiter but on some parts there is a bug that acknowledges Host accesses
548 * later than it should which could result in the descriptor register to
549 * have an incorrect value. Workaround this by checking the FWSM register
550 * which has bit 24 set while ME is accessing Host CSR registers, wait
551 * if it is set and try again a number of times.
552 **/
c5083cf6 553static inline s32 e1000e_update_tail_wa(struct e1000_hw *hw, void __iomem *tail,
c6e7f51e
BA		 554 unsigned int i)
555{
556 unsigned int j = 0;
557
558 while ((j++ < E1000_ICH_FWSM_PCIM2PCI_COUNT) &&
559 (er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI))
560 udelay(50);
561
562 writel(i, tail);
563
564 if ((j == E1000_ICH_FWSM_PCIM2PCI_COUNT) && (i != readl(tail)))
565 return E1000_ERR_SWFW_SYNC;
566
567 return 0;
568}
569
55aa6985 570static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 571{
55aa6985 572 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e
BA		 573 struct e1000_hw *hw = &adapter->hw;
574
55aa6985 575 if (e1000e_update_tail_wa(hw, rx_ring->tail, i)) {
c6e7f51e
BA		 576 u32 rctl = er32(RCTL);
577 ew32(RCTL, rctl & ~E1000_RCTL_EN);
578 e_err("ME firmware caused invalid RDT - resetting\n");
579 schedule_work(&adapter->reset_task);
580 }
581}
582
55aa6985 583static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 584{
55aa6985 585 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e
BA		 586 struct e1000_hw *hw = &adapter->hw;
587
55aa6985 588 if (e1000e_update_tail_wa(hw, tx_ring->tail, i)) {
c6e7f51e
BA		 589 u32 tctl = er32(TCTL);
590 ew32(TCTL, tctl & ~E1000_TCTL_EN);
591 e_err("ME firmware caused invalid TDT - resetting\n");
592 schedule_work(&adapter->reset_task);
593 }
594}
595
bc7f75fa 596/**
5f450212 597 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 598 * @rx_ring: Rx descriptor ring
bc7f75fa 599 **/
55aa6985 600static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 601 int cleaned_count, gfp_t gfp)
bc7f75fa 602{
55aa6985 603 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 604 struct net_device *netdev = adapter->netdev;
605 struct pci_dev *pdev = adapter->pdev;
5f450212 606 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 607 struct e1000_buffer *buffer_info;
608 struct sk_buff *skb;
609 unsigned int i;
89d71a66 610 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 611
612 i = rx_ring->next_to_use;
613 buffer_info = &rx_ring->buffer_info[i];
614
615 while (cleaned_count--) {
616 skb = buffer_info->skb;
617 if (skb) {
618 skb_trim(skb, 0);
619 goto map_skb;
620 }
621
c2fed996 622 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 623 if (!skb) {
624 /* Better luck next round */
625 adapter->alloc_rx_buff_failed++;
626 break;
627 }
628
bc7f75fa
AK		 629 buffer_info->skb = skb;
630map_skb:
0be3f55f 631 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 632 adapter->rx_buffer_len,
0be3f55f
NN		 633 DMA_FROM_DEVICE);
634 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 635 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 636 adapter->rx_dma_failed++;
637 break;
638 }
639
5f450212
BA		 640 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
641 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 642
50849d79
TH		 643 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
644 /*
645 * Force memory writes to complete before letting h/w
646 * know there are new descriptors to fetch. (Only
647 * applicable for weak-ordered memory model archs,
648 * such as IA-64).
649 */
650 wmb();
c6e7f51e 651 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 652 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 653 else
c5083cf6 654 writel(i, rx_ring->tail);
50849d79 655 }
bc7f75fa
AK		 656 i++;
657 if (i == rx_ring->count)
658 i = 0;
659 buffer_info = &rx_ring->buffer_info[i];
660 }
661
50849d79 662 rx_ring->next_to_use = i;
bc7f75fa
AK		 663}
664
665/**
666 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 667 * @rx_ring: Rx descriptor ring
bc7f75fa 668 **/
55aa6985 669static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 670 int cleaned_count, gfp_t gfp)
bc7f75fa 671{
55aa6985 672 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 673 struct net_device *netdev = adapter->netdev;
674 struct pci_dev *pdev = adapter->pdev;
675 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 676 struct e1000_buffer *buffer_info;
677 struct e1000_ps_page *ps_page;
678 struct sk_buff *skb;
679 unsigned int i, j;
680
681 i = rx_ring->next_to_use;
682 buffer_info = &rx_ring->buffer_info[i];
683
684 while (cleaned_count--) {
685 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
686
687 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 688 ps_page = &buffer_info->ps_pages[j];
689 if (j >= adapter->rx_ps_pages) {
690 /* all unused desc entries get hw null ptr */
af667a29
BA		 691 rx_desc->read.buffer_addr[j + 1] =
692 ~cpu_to_le64(0);
47f44e40
AK		 693 continue;
694 }
695 if (!ps_page->page) {
c2fed996 696 ps_page->page = alloc_page(gfp);
bc7f75fa 697 if (!ps_page->page) {
47f44e40
AK		 698 adapter->alloc_rx_buff_failed++;
699 goto no_buffers;
700 }
0be3f55f
NN		 701 ps_page->dma = dma_map_page(&pdev->dev,
702 ps_page->page,
703 0, PAGE_SIZE,
704 DMA_FROM_DEVICE);
705 if (dma_mapping_error(&pdev->dev,
706 ps_page->dma)) {
47f44e40 707 dev_err(&adapter->pdev->dev,
af667a29 708 "Rx DMA page map failed\n");
47f44e40
AK		 709 adapter->rx_dma_failed++;
710 goto no_buffers;
bc7f75fa 711 }
bc7f75fa 712 }
47f44e40
AK		 713 /*
714 * Refresh the desc even if buffer_addrs
715 * didn't change because each write-back
716 * erases this info.
717 */
af667a29
BA		 718 rx_desc->read.buffer_addr[j + 1] =
719 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 720 }
721
c2fed996
JK		 722 skb = __netdev_alloc_skb_ip_align(netdev,
723 adapter->rx_ps_bsize0,
724 gfp);
bc7f75fa
AK		 725
726 if (!skb) {
727 adapter->alloc_rx_buff_failed++;
728 break;
729 }
730
bc7f75fa 731 buffer_info->skb = skb;
0be3f55f 732 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 733 adapter->rx_ps_bsize0,
0be3f55f
NN		 734 DMA_FROM_DEVICE);
735 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 736 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 737 adapter->rx_dma_failed++;
738 /* cleanup skb */
739 dev_kfree_skb_any(skb);
740 buffer_info->skb = NULL;
741 break;
742 }
743
744 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
745
50849d79
TH		 746 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
747 /*
748 * Force memory writes to complete before letting h/w
749 * know there are new descriptors to fetch. (Only
750 * applicable for weak-ordered memory model archs,
751 * such as IA-64).
752 */
753 wmb();
c6e7f51e 754 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 755 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 756 else
c5083cf6 757 writel(i << 1, rx_ring->tail);
50849d79
TH		 758 }
759
bc7f75fa
AK		 760 i++;
761 if (i == rx_ring->count)
762 i = 0;
763 buffer_info = &rx_ring->buffer_info[i];
764 }
765
766no_buffers:
50849d79 767 rx_ring->next_to_use = i;
bc7f75fa
AK		 768}
769
97ac8cae
BA		 770/**
771 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 772 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 773 * @cleaned_count: number of buffers to allocate this pass
774 **/
775
55aa6985 776static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 777 int cleaned_count, gfp_t gfp)
97ac8cae 778{
55aa6985 779 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 780 struct net_device *netdev = adapter->netdev;
781 struct pci_dev *pdev = adapter->pdev;
5f450212 782 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 783 struct e1000_buffer *buffer_info;
784 struct sk_buff *skb;
785 unsigned int i;
89d71a66 786 unsigned int bufsz = 256 - 16 /* for skb_reserve */;
97ac8cae
BA		 787
788 i = rx_ring->next_to_use;
789 buffer_info = &rx_ring->buffer_info[i];
790
791 while (cleaned_count--) {
792 skb = buffer_info->skb;
793 if (skb) {
794 skb_trim(skb, 0);
795 goto check_page;
796 }
797
c2fed996 798 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 799 if (unlikely(!skb)) {
800 /* Better luck next round */
801 adapter->alloc_rx_buff_failed++;
802 break;
803 }
804
97ac8cae
BA		 805 buffer_info->skb = skb;
806check_page:
807 /* allocate a new page if necessary */
808 if (!buffer_info->page) {
c2fed996 809 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 810 if (unlikely(!buffer_info->page)) {
811 adapter->alloc_rx_buff_failed++;
812 break;
813 }
814 }
815
816 if (!buffer_info->dma)
0be3f55f 817 buffer_info->dma = dma_map_page(&pdev->dev,
97ac8cae
BA		 818 buffer_info->page, 0,
819 PAGE_SIZE,
0be3f55f 820 DMA_FROM_DEVICE);
97ac8cae 821
5f450212
BA		 822 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
823 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 824
825 if (unlikely(++i == rx_ring->count))
826 i = 0;
827 buffer_info = &rx_ring->buffer_info[i];
828 }
829
830 if (likely(rx_ring->next_to_use != i)) {
831 rx_ring->next_to_use = i;
832 if (unlikely(i-- == 0))
833 i = (rx_ring->count - 1);
834
835 /* Force memory writes to complete before letting h/w
836 * know there are new descriptors to fetch. (Only
837 * applicable for weak-ordered memory model archs,
838 * such as IA-64). */
839 wmb();
c6e7f51e 840 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 841 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 842 else
c5083cf6 843 writel(i, rx_ring->tail);
97ac8cae
BA		 844 }
845}
846
70495a50
BA		 847static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
848 struct sk_buff *skb)
849{
850 if (netdev->features & NETIF_F_RXHASH)
851 skb->rxhash = le32_to_cpu(rss);
852}
853
bc7f75fa 854/**
55aa6985
BA		 855 * e1000_clean_rx_irq - Send received data up the network stack
856 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 857 *
858 * the return value indicates whether actual cleaning was done, there
859 * is no guarantee that everything was cleaned
860 **/
55aa6985
BA		 861static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
862 int work_to_do)
bc7f75fa 863{
55aa6985 864 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 865 struct net_device *netdev = adapter->netdev;
866 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 867 struct e1000_hw *hw = &adapter->hw;
5f450212 868 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 869 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 870 u32 length, staterr;
bc7f75fa
AK		 871 unsigned int i;
872 int cleaned_count = 0;
3db1cd5c 873 bool cleaned = false;
bc7f75fa
AK		 874 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
875
876 i = rx_ring->next_to_clean;
5f450212
BA		 877 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
878 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 879 buffer_info = &rx_ring->buffer_info[i];
880
5f450212 881 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 882 struct sk_buff *skb;
bc7f75fa
AK		 883
884 if (*work_done >= work_to_do)
885 break;
886 (*work_done)++;
2d0bb1c1 887 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 888
bc7f75fa
AK		 889 skb = buffer_info->skb;
890 buffer_info->skb = NULL;
891
892 prefetch(skb->data - NET_IP_ALIGN);
893
894 i++;
895 if (i == rx_ring->count)
896 i = 0;
5f450212 897 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 898 prefetch(next_rxd);
899
900 next_buffer = &rx_ring->buffer_info[i];
901
3db1cd5c 902 cleaned = true;
bc7f75fa 903 cleaned_count++;
0be3f55f 904 dma_unmap_single(&pdev->dev,
bc7f75fa
AK		 905 buffer_info->dma,
906 adapter->rx_buffer_len,
0be3f55f 907 DMA_FROM_DEVICE);
bc7f75fa
AK		 908 buffer_info->dma = 0;
909
5f450212 910 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 911
b94b5028
JB		 912 /*
913 * !EOP means multiple descriptors were used to store a single
914 * packet, if that's the case we need to toss it. In fact, we
915 * need to toss every packet with the EOP bit clear and the
916 * next frame that _does_ have the EOP bit set, as it is by
917 * definition only a frame fragment
918 */
5f450212 919 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 920 adapter->flags2 |= FLAG2_IS_DISCARDING;
921
922 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 923 /* All receives must fit into a single buffer */
3bb99fe2 924 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 925 /* recycle */
926 buffer_info->skb = skb;
5f450212 927 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 928 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 929 goto next_desc;
930 }
931
5f450212 932 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
bc7f75fa
AK		 933 /* recycle */
934 buffer_info->skb = skb;
935 goto next_desc;
936 }
937
eb7c3adb
JK		 938 /* adjust length to remove Ethernet CRC */
939 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
940 length -= 4;
941
bc7f75fa
AK		 942 total_rx_bytes += length;
943 total_rx_packets++;
944
ad68076e
BA		 945 /*
946 * code added for copybreak, this should improve
bc7f75fa 947 * performance for small packets with large amounts
ad68076e
BA		 948 * of reassembly being done in the stack
949 */
bc7f75fa
AK		 950 if (length < copybreak) {
951 struct sk_buff *new_skb =
89d71a66 952 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 953 if (new_skb) {
808ff676
BA		 954 skb_copy_to_linear_data_offset(new_skb,
955 -NET_IP_ALIGN,
956 (skb->data -
957 NET_IP_ALIGN),
958 (length +
959 NET_IP_ALIGN));
bc7f75fa
AK		 960 /* save the skb in buffer_info as good */
961 buffer_info->skb = skb;
962 skb = new_skb;
963 }
964 /* else just continue with the old one */
965 }
966 /* end copybreak code */
967 skb_put(skb, length);
968
969 /* Receive Checksum Offload */
5f450212 970 e1000_rx_checksum(adapter, staterr,
afd12939 971 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 972
70495a50
BA		 973 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
974
5f450212
BA		 975 e1000_receive_skb(adapter, netdev, skb, staterr,
976 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 977
978next_desc:
5f450212 979 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 980
981 /* return some buffers to hardware, one at a time is too slow */
982 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 983 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 984 GFP_ATOMIC);
bc7f75fa
AK		 985 cleaned_count = 0;
986 }
987
988 /* use prefetched values */
989 rx_desc = next_rxd;
990 buffer_info = next_buffer;
5f450212
BA		 991
992 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 993 }
994 rx_ring->next_to_clean = i;
995
996 cleaned_count = e1000_desc_unused(rx_ring);
997 if (cleaned_count)
55aa6985 998 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 999
bc7f75fa 1000 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1001 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1002 return cleaned;
1003}
1004
55aa6985
BA		 1005static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1006 struct e1000_buffer *buffer_info)
bc7f75fa 1007{
55aa6985
BA		 1008 struct e1000_adapter *adapter = tx_ring->adapter;
1009
03b1320d
AD		 1010 if (buffer_info->dma) {
1011 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1012 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1013 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1014 else
0be3f55f
NN		 1015 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1016 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1017 buffer_info->dma = 0;
1018 }
bc7f75fa
AK		 1019 if (buffer_info->skb) {
1020 dev_kfree_skb_any(buffer_info->skb);
1021 buffer_info->skb = NULL;
1022 }
1b7719c4 1023 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1024}
1025
41cec6f1 1026static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1027{
41cec6f1
BA		 1028 struct e1000_adapter *adapter = container_of(work,
1029 struct e1000_adapter,
1030 print_hang_task);
09357b00 1031 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1032 struct e1000_ring *tx_ring = adapter->tx_ring;
1033 unsigned int i = tx_ring->next_to_clean;
1034 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1035 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1036 struct e1000_hw *hw = &adapter->hw;
1037 u16 phy_status, phy_1000t_status, phy_ext_status;
1038 u16 pci_status;
1039
615b32af
JB		 1040 if (test_bit(__E1000_DOWN, &adapter->state))
1041 return;
1042
09357b00
JK		 1043 if (!adapter->tx_hang_recheck &&
1044 (adapter->flags2 & FLAG2_DMA_BURST)) {
1045 /* May be block on write-back, flush and detect again
1046 * flush pending descriptor writebacks to memory
1047 */
1048 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1049 /* execute the writes immediately */
1050 e1e_flush();
1051 adapter->tx_hang_recheck = true;
1052 return;
1053 }
1054 /* Real hang detected */
1055 adapter->tx_hang_recheck = false;
1056 netif_stop_queue(netdev);
1057
41cec6f1
BA		 1058 e1e_rphy(hw, PHY_STATUS, &phy_status);
1059 e1e_rphy(hw, PHY_1000T_STATUS, &phy_1000t_status);
1060 e1e_rphy(hw, PHY_EXT_STATUS, &phy_ext_status);
bc7f75fa 1061
41cec6f1
BA		 1062 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1063
1064 /* detected Hardware unit hang */
1065 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1066 " TDH <%x>\n"
1067 " TDT <%x>\n"
1068 " next_to_use <%x>\n"
1069 " next_to_clean <%x>\n"
1070 "buffer_info[next_to_clean]:\n"
1071 " time_stamp <%lx>\n"
1072 " next_to_watch <%x>\n"
1073 " jiffies <%lx>\n"
41cec6f1
BA		 1074 " next_to_watch.status <%x>\n"
1075 "MAC Status <%x>\n"
1076 "PHY Status <%x>\n"
1077 "PHY 1000BASE-T Status <%x>\n"
1078 "PHY Extended Status <%x>\n"
1079 "PCI Status <%x>\n",
c5083cf6
BA		 1080 readl(tx_ring->head),
1081 readl(tx_ring->tail),
44defeb3
JK		 1082 tx_ring->next_to_use,
1083 tx_ring->next_to_clean,
1084 tx_ring->buffer_info[eop].time_stamp,
1085 eop,
1086 jiffies,
41cec6f1
BA		 1087 eop_desc->upper.fields.status,
1088 er32(STATUS),
1089 phy_status,
1090 phy_1000t_status,
1091 phy_ext_status,
1092 pci_status);
bc7f75fa
AK		 1093}
1094
1095/**
1096 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1097 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1098 *
1099 * the return value indicates whether actual cleaning was done, there
1100 * is no guarantee that everything was cleaned
1101 **/
55aa6985 1102static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1103{
55aa6985 1104 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1105 struct net_device *netdev = adapter->netdev;
1106 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1107 struct e1000_tx_desc *tx_desc, *eop_desc;
1108 struct e1000_buffer *buffer_info;
1109 unsigned int i, eop;
1110 unsigned int count = 0;
bc7f75fa 1111 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1112 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1113
1114 i = tx_ring->next_to_clean;
1115 eop = tx_ring->buffer_info[i].next_to_watch;
1116 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1117
12d04a3c
AD		 1118 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1119 (count < tx_ring->count)) {
a86043c2 1120 bool cleaned = false;
2d0bb1c1 1121 rmb(); /* read buffer_info after eop_desc */
a86043c2 1122 for (; !cleaned; count++) {
bc7f75fa
AK		 1123 tx_desc = E1000_TX_DESC(*tx_ring, i);
1124 buffer_info = &tx_ring->buffer_info[i];
1125 cleaned = (i == eop);
1126
1127 if (cleaned) {
9ed318d5
TH		 1128 total_tx_packets += buffer_info->segs;
1129 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1130 if (buffer_info->skb) {
1131 bytes_compl += buffer_info->skb->len;
1132 pkts_compl++;
1133 }
bc7f75fa
AK		 1134 }
1135
55aa6985 1136 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1137 tx_desc->upper.data = 0;
1138
1139 i++;
1140 if (i == tx_ring->count)
1141 i = 0;
1142 }
1143
dac87619
TL		 1144 if (i == tx_ring->next_to_use)
1145 break;
bc7f75fa
AK		 1146 eop = tx_ring->buffer_info[i].next_to_watch;
1147 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1148 }
1149
1150 tx_ring->next_to_clean = i;
1151
3f0cfa3b
TH		 1152 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1153
bc7f75fa 1154#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1155 if (count && netif_carrier_ok(netdev) &&
1156 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1157 /* Make sure that anybody stopping the queue after this
1158 * sees the new next_to_clean.
1159 */
1160 smp_mb();
1161
1162 if (netif_queue_stopped(netdev) &&
1163 !(test_bit(__E1000_DOWN, &adapter->state))) {
1164 netif_wake_queue(netdev);
1165 ++adapter->restart_queue;
1166 }
1167 }
1168
1169 if (adapter->detect_tx_hung) {
41cec6f1
BA		 1170 /*
1171 * Detect a transmit hang in hardware, this serializes the
1172 * check with the clearing of time_stamp and movement of i
1173 */
3db1cd5c 1174 adapter->detect_tx_hung = false;
12d04a3c
AD		 1175 if (tx_ring->buffer_info[i].time_stamp &&
1176 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1177 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1178 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1179 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1180 else
1181 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1182 }
1183 adapter->total_tx_bytes += total_tx_bytes;
1184 adapter->total_tx_packets += total_tx_packets;
807540ba 1185 return count < tx_ring->count;
bc7f75fa
AK		 1186}
1187
bc7f75fa
AK		 1188/**
1189 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1190 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1191 *
1192 * the return value indicates whether actual cleaning was done, there
1193 * is no guarantee that everything was cleaned
1194 **/
55aa6985
BA		 1195static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1196 int work_to_do)
bc7f75fa 1197{
55aa6985 1198 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1199 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1200 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1201 struct net_device *netdev = adapter->netdev;
1202 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1203 struct e1000_buffer *buffer_info, *next_buffer;
1204 struct e1000_ps_page *ps_page;
1205 struct sk_buff *skb;
1206 unsigned int i, j;
1207 u32 length, staterr;
1208 int cleaned_count = 0;
3db1cd5c 1209 bool cleaned = false;
bc7f75fa
AK		 1210 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1211
1212 i = rx_ring->next_to_clean;
1213 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1214 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1215 buffer_info = &rx_ring->buffer_info[i];
1216
1217 while (staterr & E1000_RXD_STAT_DD) {
1218 if (*work_done >= work_to_do)
1219 break;
1220 (*work_done)++;
1221 skb = buffer_info->skb;
2d0bb1c1 1222 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1223
1224 /* in the packet split case this is header only */
1225 prefetch(skb->data - NET_IP_ALIGN);
1226
1227 i++;
1228 if (i == rx_ring->count)
1229 i = 0;
1230 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1231 prefetch(next_rxd);
1232
1233 next_buffer = &rx_ring->buffer_info[i];
1234
3db1cd5c 1235 cleaned = true;
bc7f75fa 1236 cleaned_count++;
0be3f55f 1237 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1238 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1239 buffer_info->dma = 0;
1240
af667a29 1241 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1242 if (!(staterr & E1000_RXD_STAT_EOP))
1243 adapter->flags2 |= FLAG2_IS_DISCARDING;
1244
1245 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1246 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1247 dev_kfree_skb_irq(skb);
b94b5028
JB		 1248 if (staterr & E1000_RXD_STAT_EOP)
1249 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1250 goto next_desc;
1251 }
1252
1253 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
1254 dev_kfree_skb_irq(skb);
1255 goto next_desc;
1256 }
1257
1258 length = le16_to_cpu(rx_desc->wb.middle.length0);
1259
1260 if (!length) {
ef456f85 1261 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1262 dev_kfree_skb_irq(skb);
1263 goto next_desc;
1264 }
1265
1266 /* Good Receive */
1267 skb_put(skb, length);
1268
1269 {
ad68076e
BA		 1270 /*
1271 * this looks ugly, but it seems compiler issues make it
1272 * more efficient than reusing j
1273 */
bc7f75fa
AK		 1274 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
1275
ad68076e
BA		 1276 /*
1277 * page alloc/put takes too long and effects small packet
1278 * throughput, so unsplit small packets and save the alloc/put
1279 * only valid in softirq (napi) context to call kmap_*
1280 */
bc7f75fa
AK		 1281 if (l1 && (l1 <= copybreak) &&
1282 ((length + l1) <= adapter->rx_ps_bsize0)) {
1283 u8 *vaddr;
1284
47f44e40 1285 ps_page = &buffer_info->ps_pages[0];
bc7f75fa 1286
ad68076e
BA		 1287 /*
1288 * there is no documentation about how to call
bc7f75fa 1289 * kmap_atomic, so we can't hold the mapping
ad68076e
BA		 1290 * very long
1291 */
0be3f55f
NN		 1292 dma_sync_single_for_cpu(&pdev->dev, ps_page->dma,
1293 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa
AK		 1294 vaddr = kmap_atomic(ps_page->page, KM_SKB_DATA_SOFTIRQ);
1295 memcpy(skb_tail_pointer(skb), vaddr, l1);
1296 kunmap_atomic(vaddr, KM_SKB_DATA_SOFTIRQ);
0be3f55f
NN		 1297 dma_sync_single_for_device(&pdev->dev, ps_page->dma,
1298 PAGE_SIZE, DMA_FROM_DEVICE);
140a7480 1299
eb7c3adb
JK		 1300 /* remove the CRC */
1301 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
1302 l1 -= 4;
1303
bc7f75fa
AK		 1304 skb_put(skb, l1);
1305 goto copydone;
1306 } /* if */
1307 }
1308
1309 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1310 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1311 if (!length)
1312 break;
1313
47f44e40 1314 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1315 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1316 DMA_FROM_DEVICE);
bc7f75fa
AK		 1317 ps_page->dma = 0;
1318 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1319 ps_page->page = NULL;
1320 skb->len += length;
1321 skb->data_len += length;
98a045d7 1322 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1323 }
1324
eb7c3adb
JK		 1325 /* strip the ethernet crc, problem is we're using pages now so
1326 * this whole operation can get a little cpu intensive
1327 */
1328 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING))
1329 pskb_trim(skb, skb->len - 4);
1330
bc7f75fa
AK		 1331copydone:
1332 total_rx_bytes += skb->len;
1333 total_rx_packets++;
1334
afd12939
BA		 1335 e1000_rx_checksum(adapter, staterr,
1336 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
bc7f75fa 1337
70495a50
BA		 1338 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1339
bc7f75fa
AK		 1340 if (rx_desc->wb.upper.header_status &
1341 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
1342 adapter->rx_hdr_split++;
1343
1344 e1000_receive_skb(adapter, netdev, skb,
1345 staterr, rx_desc->wb.middle.vlan);
1346
1347next_desc:
1348 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1349 buffer_info->skb = NULL;
1350
1351 /* return some buffers to hardware, one at a time is too slow */
1352 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1353 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1354 GFP_ATOMIC);
bc7f75fa
AK		 1355 cleaned_count = 0;
1356 }
1357
1358 /* use prefetched values */
1359 rx_desc = next_rxd;
1360 buffer_info = next_buffer;
1361
1362 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1363 }
1364 rx_ring->next_to_clean = i;
1365
1366 cleaned_count = e1000_desc_unused(rx_ring);
1367 if (cleaned_count)
55aa6985 1368 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1369
bc7f75fa 1370 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1371 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1372 return cleaned;
1373}
1374
97ac8cae
BA		 1375/**
1376 * e1000_consume_page - helper function
1377 **/
1378static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
1379 u16 length)
1380{
1381 bi->page = NULL;
1382 skb->len += length;
1383 skb->data_len += length;
98a045d7 1384 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1385}
1386
1387/**
1388 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1389 * @adapter: board private structure
1390 *
1391 * the return value indicates whether actual cleaning was done, there
1392 * is no guarantee that everything was cleaned
1393 **/
55aa6985
BA		 1394static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1395 int work_to_do)
97ac8cae 1396{
55aa6985 1397 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1398 struct net_device *netdev = adapter->netdev;
1399 struct pci_dev *pdev = adapter->pdev;
5f450212 1400 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1401 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1402 u32 length, staterr;
97ac8cae
BA		 1403 unsigned int i;
1404 int cleaned_count = 0;
1405 bool cleaned = false;
1406 unsigned int total_rx_bytes=0, total_rx_packets=0;
1407
1408 i = rx_ring->next_to_clean;
5f450212
BA		 1409 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1410 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1411 buffer_info = &rx_ring->buffer_info[i];
1412
5f450212 1413 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1414 struct sk_buff *skb;
97ac8cae
BA		 1415
1416 if (*work_done >= work_to_do)
1417 break;
1418 (*work_done)++;
2d0bb1c1 1419 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1420
97ac8cae
BA		 1421 skb = buffer_info->skb;
1422 buffer_info->skb = NULL;
1423
1424 ++i;
1425 if (i == rx_ring->count)
1426 i = 0;
5f450212 1427 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1428 prefetch(next_rxd);
1429
1430 next_buffer = &rx_ring->buffer_info[i];
1431
1432 cleaned = true;
1433 cleaned_count++;
0be3f55f
NN		 1434 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1435 DMA_FROM_DEVICE);
97ac8cae
BA		 1436 buffer_info->dma = 0;
1437
5f450212 1438 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1439
1440 /* errors is only valid for DD + EOP descriptors */
5f450212
BA		 1441 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
1442 (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK))) {
1443 /* recycle both page and skb */
1444 buffer_info->skb = skb;
1445 /* an error means any chain goes out the window too */
1446 if (rx_ring->rx_skb_top)
1447 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1448 rx_ring->rx_skb_top = NULL;
1449 goto next_desc;
97ac8cae
BA		 1450 }
1451
f0f1a172 1452#define rxtop (rx_ring->rx_skb_top)
5f450212 1453 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1454 /* this descriptor is only the beginning (or middle) */
1455 if (!rxtop) {
1456 /* this is the beginning of a chain */
1457 rxtop = skb;
1458 skb_fill_page_desc(rxtop, 0, buffer_info->page,
1459 0, length);
1460 } else {
1461 /* this is the middle of a chain */
1462 skb_fill_page_desc(rxtop,
1463 skb_shinfo(rxtop)->nr_frags,
1464 buffer_info->page, 0, length);
1465 /* re-use the skb, only consumed the page */
1466 buffer_info->skb = skb;
1467 }
1468 e1000_consume_page(buffer_info, rxtop, length);
1469 goto next_desc;
1470 } else {
1471 if (rxtop) {
1472 /* end of the chain */
1473 skb_fill_page_desc(rxtop,
1474 skb_shinfo(rxtop)->nr_frags,
1475 buffer_info->page, 0, length);
1476 /* re-use the current skb, we only consumed the
1477 * page */
1478 buffer_info->skb = skb;
1479 skb = rxtop;
1480 rxtop = NULL;
1481 e1000_consume_page(buffer_info, skb, length);
1482 } else {
1483 /* no chain, got EOP, this buf is the packet
1484 * copybreak to save the put_page/alloc_page */
1485 if (length <= copybreak &&
1486 skb_tailroom(skb) >= length) {
1487 u8 *vaddr;
1488 vaddr = kmap_atomic(buffer_info->page,
1489 KM_SKB_DATA_SOFTIRQ);
1490 memcpy(skb_tail_pointer(skb), vaddr,
1491 length);
1492 kunmap_atomic(vaddr,
1493 KM_SKB_DATA_SOFTIRQ);
1494 /* re-use the page, so don't erase
1495 * buffer_info->page */
1496 skb_put(skb, length);
1497 } else {
1498 skb_fill_page_desc(skb, 0,
1499 buffer_info->page, 0,
1500 length);
1501 e1000_consume_page(buffer_info, skb,
1502 length);
1503 }
1504 }
1505 }
1506
1507 /* Receive Checksum Offload XXX recompute due to CRC strip? */
5f450212 1508 e1000_rx_checksum(adapter, staterr,
afd12939 1509 rx_desc->wb.lower.hi_dword.csum_ip.csum, skb);
97ac8cae 1510
70495a50
BA		 1511 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1512
97ac8cae
BA		 1513 /* probably a little skewed due to removing CRC */
1514 total_rx_bytes += skb->len;
1515 total_rx_packets++;
1516
1517 /* eth type trans needs skb->data to point to something */
1518 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1519 e_err("pskb_may_pull failed.\n");
ef5ab89c 1520 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1521 goto next_desc;
1522 }
1523
5f450212
BA		 1524 e1000_receive_skb(adapter, netdev, skb, staterr,
1525 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1526
1527next_desc:
5f450212 1528 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1529
1530 /* return some buffers to hardware, one at a time is too slow */
1531 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1532 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1533 GFP_ATOMIC);
97ac8cae
BA		 1534 cleaned_count = 0;
1535 }
1536
1537 /* use prefetched values */
1538 rx_desc = next_rxd;
1539 buffer_info = next_buffer;
5f450212
BA		 1540
1541 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1542 }
1543 rx_ring->next_to_clean = i;
1544
1545 cleaned_count = e1000_desc_unused(rx_ring);
1546 if (cleaned_count)
55aa6985 1547 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1548
1549 adapter->total_rx_bytes += total_rx_bytes;
1550 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1551 return cleaned;
1552}
1553
bc7f75fa
AK		 1554/**
1555 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1556 * @rx_ring: Rx descriptor ring
bc7f75fa 1557 **/
55aa6985 1558static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1559{
55aa6985 1560 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1561 struct e1000_buffer *buffer_info;
1562 struct e1000_ps_page *ps_page;
1563 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1564 unsigned int i, j;
1565
1566 /* Free all the Rx ring sk_buffs */
1567 for (i = 0; i < rx_ring->count; i++) {
1568 buffer_info = &rx_ring->buffer_info[i];
1569 if (buffer_info->dma) {
1570 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1571 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1572 adapter->rx_buffer_len,
0be3f55f 1573 DMA_FROM_DEVICE);
97ac8cae 1574 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1575 dma_unmap_page(&pdev->dev, buffer_info->dma,
97ac8cae 1576 PAGE_SIZE,
0be3f55f 1577 DMA_FROM_DEVICE);
bc7f75fa 1578 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1579 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1580 adapter->rx_ps_bsize0,
0be3f55f 1581 DMA_FROM_DEVICE);
bc7f75fa
AK		 1582 buffer_info->dma = 0;
1583 }
1584
97ac8cae
BA		 1585 if (buffer_info->page) {
1586 put_page(buffer_info->page);
1587 buffer_info->page = NULL;
1588 }
1589
bc7f75fa
AK		 1590 if (buffer_info->skb) {
1591 dev_kfree_skb(buffer_info->skb);
1592 buffer_info->skb = NULL;
1593 }
1594
1595 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1596 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1597 if (!ps_page->page)
1598 break;
0be3f55f
NN		 1599 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1600 DMA_FROM_DEVICE);
bc7f75fa
AK		 1601 ps_page->dma = 0;
1602 put_page(ps_page->page);
1603 ps_page->page = NULL;
1604 }
1605 }
1606
1607 /* there also may be some cached data from a chained receive */
1608 if (rx_ring->rx_skb_top) {
1609 dev_kfree_skb(rx_ring->rx_skb_top);
1610 rx_ring->rx_skb_top = NULL;
1611 }
1612
bc7f75fa
AK		 1613 /* Zero out the descriptor ring */
1614 memset(rx_ring->desc, 0, rx_ring->size);
1615
1616 rx_ring->next_to_clean = 0;
1617 rx_ring->next_to_use = 0;
b94b5028 1618 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1619
c5083cf6
BA		 1620 writel(0, rx_ring->head);
1621 writel(0, rx_ring->tail);
bc7f75fa
AK		 1622}
1623
a8f88ff5
JB		 1624static void e1000e_downshift_workaround(struct work_struct *work)
1625{
1626 struct e1000_adapter *adapter = container_of(work,
1627 struct e1000_adapter, downshift_task);
1628
615b32af
JB		 1629 if (test_bit(__E1000_DOWN, &adapter->state))
1630 return;
1631
a8f88ff5
JB		 1632 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1633}
1634
bc7f75fa
AK		 1635/**
1636 * e1000_intr_msi - Interrupt Handler
1637 * @irq: interrupt number
1638 * @data: pointer to a network interface device structure
1639 **/
1640static irqreturn_t e1000_intr_msi(int irq, void *data)
1641{
1642 struct net_device *netdev = data;
1643 struct e1000_adapter *adapter = netdev_priv(netdev);
1644 struct e1000_hw *hw = &adapter->hw;
1645 u32 icr = er32(ICR);
1646
ad68076e
BA		 1647 /*
1648 * read ICR disables interrupts using IAM
1649 */
bc7f75fa 1650
573cca8c 1651 if (icr & E1000_ICR_LSC) {
bc7f75fa 1652 hw->mac.get_link_status = 1;
ad68076e
BA		 1653 /*
1654 * ICH8 workaround-- Call gig speed drop workaround on cable
1655 * disconnect (LSC) before accessing any PHY registers
1656 */
bc7f75fa
AK		 1657 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1658 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1659 schedule_work(&adapter->downshift_task);
bc7f75fa 1660
ad68076e
BA		 1661 /*
1662 * 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1663 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1664 * adapter in watchdog
1665 */
bc7f75fa
AK		 1666 if (netif_carrier_ok(netdev) &&
1667 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1668 /* disable receives */
1669 u32 rctl = er32(RCTL);
1670 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1671 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1672 }
1673 /* guard against interrupt when we're going down */
1674 if (!test_bit(__E1000_DOWN, &adapter->state))
1675 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1676 }
1677
288379f0 1678 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1679 adapter->total_tx_bytes = 0;
1680 adapter->total_tx_packets = 0;
1681 adapter->total_rx_bytes = 0;
1682 adapter->total_rx_packets = 0;
288379f0 1683 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1684 }
1685
1686 return IRQ_HANDLED;
1687}
1688
1689/**
1690 * e1000_intr - Interrupt Handler
1691 * @irq: interrupt number
1692 * @data: pointer to a network interface device structure
1693 **/
1694static irqreturn_t e1000_intr(int irq, void *data)
1695{
1696 struct net_device *netdev = data;
1697 struct e1000_adapter *adapter = netdev_priv(netdev);
1698 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1699 u32 rctl, icr = er32(ICR);
4662e82b 1700
a68ea775 1701 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
bc7f75fa
AK		 1702 return IRQ_NONE; /* Not our interrupt */
1703
ad68076e
BA		 1704 /*
1705 * IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1706 * not set, then the adapter didn't send an interrupt
1707 */
bc7f75fa
AK		 1708 if (!(icr & E1000_ICR_INT_ASSERTED))
1709 return IRQ_NONE;
1710
ad68076e
BA		 1711 /*
1712 * Interrupt Auto-Mask...upon reading ICR,
1713 * interrupts are masked. No need for the
1714 * IMC write
1715 */
bc7f75fa 1716
573cca8c 1717 if (icr & E1000_ICR_LSC) {
bc7f75fa 1718 hw->mac.get_link_status = 1;
ad68076e
BA		 1719 /*
1720 * ICH8 workaround-- Call gig speed drop workaround on cable
1721 * disconnect (LSC) before accessing any PHY registers
1722 */
bc7f75fa
AK		 1723 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1724 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1725 schedule_work(&adapter->downshift_task);
bc7f75fa 1726
ad68076e
BA		 1727 /*
1728 * 80003ES2LAN workaround--
bc7f75fa
AK		 1729 * For packet buffer work-around on link down event;
1730 * disable receives here in the ISR and
1731 * reset adapter in watchdog
1732 */
1733 if (netif_carrier_ok(netdev) &&
1734 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1735 /* disable receives */
1736 rctl = er32(RCTL);
1737 ew32(RCTL, rctl & ~E1000_RCTL_EN);
318a94d6 1738 adapter->flags |= FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 1739 }
1740 /* guard against interrupt when we're going down */
1741 if (!test_bit(__E1000_DOWN, &adapter->state))
1742 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1743 }
1744
288379f0 1745 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1746 adapter->total_tx_bytes = 0;
1747 adapter->total_tx_packets = 0;
1748 adapter->total_rx_bytes = 0;
1749 adapter->total_rx_packets = 0;
288379f0 1750 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1751 }
1752
1753 return IRQ_HANDLED;
1754}
1755
4662e82b
BA		 1756static irqreturn_t e1000_msix_other(int irq, void *data)
1757{
1758 struct net_device *netdev = data;
1759 struct e1000_adapter *adapter = netdev_priv(netdev);
1760 struct e1000_hw *hw = &adapter->hw;
1761 u32 icr = er32(ICR);
1762
1763 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1764 if (!test_bit(__E1000_DOWN, &adapter->state))
1765 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1766 return IRQ_NONE;
1767 }
1768
1769 if (icr & adapter->eiac_mask)
1770 ew32(ICS, (icr & adapter->eiac_mask));
1771
1772 if (icr & E1000_ICR_OTHER) {
1773 if (!(icr & E1000_ICR_LSC))
1774 goto no_link_interrupt;
1775 hw->mac.get_link_status = 1;
1776 /* guard against interrupt when we're going down */
1777 if (!test_bit(__E1000_DOWN, &adapter->state))
1778 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1779 }
1780
1781no_link_interrupt:
a3c69fef
JB		 1782 if (!test_bit(__E1000_DOWN, &adapter->state))
1783 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1784
1785 return IRQ_HANDLED;
1786}
1787
1788
1789static irqreturn_t e1000_intr_msix_tx(int irq, void *data)
1790{
1791 struct net_device *netdev = data;
1792 struct e1000_adapter *adapter = netdev_priv(netdev);
1793 struct e1000_hw *hw = &adapter->hw;
1794 struct e1000_ring *tx_ring = adapter->tx_ring;
1795
1796
1797 adapter->total_tx_bytes = 0;
1798 adapter->total_tx_packets = 0;
1799
55aa6985 1800 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1801 /* Ring was not completely cleaned, so fire another interrupt */
1802 ew32(ICS, tx_ring->ims_val);
1803
1804 return IRQ_HANDLED;
1805}
1806
1807static irqreturn_t e1000_intr_msix_rx(int irq, void *data)
1808{
1809 struct net_device *netdev = data;
1810 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1811 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1812
1813 /* Write the ITR value calculated at the end of the
1814 * previous interrupt.
1815 */
55aa6985
BA		 1816 if (rx_ring->set_itr) {
1817 writel(1000000000 / (rx_ring->itr_val * 256),
1818 rx_ring->itr_register);
1819 rx_ring->set_itr = 0;
4662e82b
BA		 1820 }
1821
288379f0 1822 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1823 adapter->total_rx_bytes = 0;
1824 adapter->total_rx_packets = 0;
288379f0 1825 __napi_schedule(&adapter->napi);
4662e82b
BA		 1826 }
1827 return IRQ_HANDLED;
1828}
1829
1830/**
1831 * e1000_configure_msix - Configure MSI-X hardware
1832 *
1833 * e1000_configure_msix sets up the hardware to properly
1834 * generate MSI-X interrupts.
1835 **/
1836static void e1000_configure_msix(struct e1000_adapter *adapter)
1837{
1838 struct e1000_hw *hw = &adapter->hw;
1839 struct e1000_ring *rx_ring = adapter->rx_ring;
1840 struct e1000_ring *tx_ring = adapter->tx_ring;
1841 int vector = 0;
1842 u32 ctrl_ext, ivar = 0;
1843
1844 adapter->eiac_mask = 0;
1845
1846 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1847 if (hw->mac.type == e1000_82574) {
1848 u32 rfctl = er32(RFCTL);
1849 rfctl |= E1000_RFCTL_ACK_DIS;
1850 ew32(RFCTL, rfctl);
1851 }
1852
1853#define E1000_IVAR_INT_ALLOC_VALID 0x8
1854 /* Configure Rx vector */
1855 rx_ring->ims_val = E1000_IMS_RXQ0;
1856 adapter->eiac_mask |= rx_ring->ims_val;
1857 if (rx_ring->itr_val)
1858 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1859 rx_ring->itr_register);
4662e82b 1860 else
c5083cf6 1861 writel(1, rx_ring->itr_register);
4662e82b
BA		 1862 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1863
1864 /* Configure Tx vector */
1865 tx_ring->ims_val = E1000_IMS_TXQ0;
1866 vector++;
1867 if (tx_ring->itr_val)
1868 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1869 tx_ring->itr_register);
4662e82b 1870 else
c5083cf6 1871 writel(1, tx_ring->itr_register);
4662e82b
BA		 1872 adapter->eiac_mask |= tx_ring->ims_val;
1873 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1874
1875 /* set vector for Other Causes, e.g. link changes */
1876 vector++;
1877 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1878 if (rx_ring->itr_val)
1879 writel(1000000000 / (rx_ring->itr_val * 256),
1880 hw->hw_addr + E1000_EITR_82574(vector));
1881 else
1882 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1883
1884 /* Cause Tx interrupts on every write back */
1885 ivar |= (1 << 31);
1886
1887 ew32(IVAR, ivar);
1888
1889 /* enable MSI-X PBA support */
1890 ctrl_ext = er32(CTRL_EXT);
1891 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
1892
1893 /* Auto-Mask Other interrupts upon ICR read */
1894#define E1000_EIAC_MASK_82574 0x01F00000
1895 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
1896 ctrl_ext |= E1000_CTRL_EXT_EIAME;
1897 ew32(CTRL_EXT, ctrl_ext);
1898 e1e_flush();
1899}
1900
1901void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
1902{
1903 if (adapter->msix_entries) {
1904 pci_disable_msix(adapter->pdev);
1905 kfree(adapter->msix_entries);
1906 adapter->msix_entries = NULL;
1907 } else if (adapter->flags & FLAG_MSI_ENABLED) {
1908 pci_disable_msi(adapter->pdev);
1909 adapter->flags &= ~FLAG_MSI_ENABLED;
1910 }
4662e82b
BA		 1911}
1912
1913/**
1914 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
1915 *
1916 * Attempt to configure interrupts using the best available
1917 * capabilities of the hardware and kernel.
1918 **/
1919void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
1920{
1921 int err;
8e86acd7 1922 int i;
4662e82b
BA		 1923
1924 switch (adapter->int_mode) {
1925 case E1000E_INT_MODE_MSIX:
1926 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 1927 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
1928 adapter->msix_entries = kcalloc(adapter->num_vectors,
4662e82b
BA		 1929 sizeof(struct msix_entry),
1930 GFP_KERNEL);
1931 if (adapter->msix_entries) {
8e86acd7 1932 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 1933 adapter->msix_entries[i].entry = i;
1934
1935 err = pci_enable_msix(adapter->pdev,
1936 adapter->msix_entries,
8e86acd7 1937 adapter->num_vectors);
b1cdfead 1938 if (err == 0)
4662e82b
BA		 1939 return;
1940 }
1941 /* MSI-X failed, so fall through and try MSI */
ef456f85 1942 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 1943 e1000e_reset_interrupt_capability(adapter);
1944 }
1945 adapter->int_mode = E1000E_INT_MODE_MSI;
1946 /* Fall through */
1947 case E1000E_INT_MODE_MSI:
1948 if (!pci_enable_msi(adapter->pdev)) {
1949 adapter->flags |= FLAG_MSI_ENABLED;
1950 } else {
1951 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 1952 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 1953 }
1954 /* Fall through */
1955 case E1000E_INT_MODE_LEGACY:
1956 /* Don't do anything; this is the system default */
1957 break;
1958 }
8e86acd7
JK		 1959
1960 /* store the number of vectors being used */
1961 adapter->num_vectors = 1;
4662e82b
BA		 1962}
1963
1964/**
1965 * e1000_request_msix - Initialize MSI-X interrupts
1966 *
1967 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
1968 * kernel.
1969 **/
1970static int e1000_request_msix(struct e1000_adapter *adapter)
1971{
1972 struct net_device *netdev = adapter->netdev;
1973 int err = 0, vector = 0;
1974
1975 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1976 snprintf(adapter->rx_ring->name,
1977 sizeof(adapter->rx_ring->name) - 1,
1978 "%s-rx-0", netdev->name);
4662e82b
BA		 1979 else
1980 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
1981 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1982 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 1983 netdev);
1984 if (err)
1985 goto out;
c5083cf6
BA		 1986 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
1987 E1000_EITR_82574(vector);
4662e82b
BA		 1988 adapter->rx_ring->itr_val = adapter->itr;
1989 vector++;
1990
1991 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 1992 snprintf(adapter->tx_ring->name,
1993 sizeof(adapter->tx_ring->name) - 1,
1994 "%s-tx-0", netdev->name);
4662e82b
BA		 1995 else
1996 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
1997 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 1998 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 1999 netdev);
2000 if (err)
2001 goto out;
c5083cf6
BA		 2002 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2003 E1000_EITR_82574(vector);
4662e82b
BA		 2004 adapter->tx_ring->itr_val = adapter->itr;
2005 vector++;
2006
2007 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2008 e1000_msix_other, 0, netdev->name, netdev);
4662e82b
BA		 2009 if (err)
2010 goto out;
2011
2012 e1000_configure_msix(adapter);
2013 return 0;
2014out:
2015 return err;
2016}
2017
f8d59f78
BA		 2018/**
2019 * e1000_request_irq - initialize interrupts
2020 *
2021 * Attempts to configure interrupts using the best available
2022 * capabilities of the hardware and kernel.
2023 **/
bc7f75fa
AK		 2024static int e1000_request_irq(struct e1000_adapter *adapter)
2025{
2026 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2027 int err;
2028
4662e82b
BA		 2029 if (adapter->msix_entries) {
2030 err = e1000_request_msix(adapter);
2031 if (!err)
2032 return err;
2033 /* fall back to MSI */
2034 e1000e_reset_interrupt_capability(adapter);
2035 adapter->int_mode = E1000E_INT_MODE_MSI;
2036 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2037 }
4662e82b 2038 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2039 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2040 netdev->name, netdev);
2041 if (!err)
2042 return err;
bc7f75fa 2043
4662e82b
BA		 2044 /* fall back to legacy interrupt */
2045 e1000e_reset_interrupt_capability(adapter);
2046 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2047 }
2048
a0607fd3 2049 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2050 netdev->name, netdev);
2051 if (err)
2052 e_err("Unable to allocate interrupt, Error: %d\n", err);
2053
bc7f75fa
AK		 2054 return err;
2055}
2056
2057static void e1000_free_irq(struct e1000_adapter *adapter)
2058{
2059 struct net_device *netdev = adapter->netdev;
2060
4662e82b
BA		 2061 if (adapter->msix_entries) {
2062 int vector = 0;
2063
2064 free_irq(adapter->msix_entries[vector].vector, netdev);
2065 vector++;
2066
2067 free_irq(adapter->msix_entries[vector].vector, netdev);
2068 vector++;
2069
2070 /* Other Causes interrupt vector */
2071 free_irq(adapter->msix_entries[vector].vector, netdev);
2072 return;
bc7f75fa 2073 }
4662e82b
BA		 2074
2075 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2076}
2077
2078/**
2079 * e1000_irq_disable - Mask off interrupt generation on the NIC
2080 **/
2081static void e1000_irq_disable(struct e1000_adapter *adapter)
2082{
2083 struct e1000_hw *hw = &adapter->hw;
2084
bc7f75fa 2085 ew32(IMC, ~0);
4662e82b
BA		 2086 if (adapter->msix_entries)
2087 ew32(EIAC_82574, 0);
bc7f75fa 2088 e1e_flush();
8e86acd7
JK		 2089
2090 if (adapter->msix_entries) {
2091 int i;
2092 for (i = 0; i < adapter->num_vectors; i++)
2093 synchronize_irq(adapter->msix_entries[i].vector);
2094 } else {
2095 synchronize_irq(adapter->pdev->irq);
2096 }
bc7f75fa
AK		 2097}
2098
2099/**
2100 * e1000_irq_enable - Enable default interrupt generation settings
2101 **/
2102static void e1000_irq_enable(struct e1000_adapter *adapter)
2103{
2104 struct e1000_hw *hw = &adapter->hw;
2105
4662e82b
BA		 2106 if (adapter->msix_entries) {
2107 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2108 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
2109 } else {
2110 ew32(IMS, IMS_ENABLE_MASK);
2111 }
74ef9c39 2112 e1e_flush();
bc7f75fa
AK		 2113}
2114
2115/**
31dbe5b4 2116 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2117 * @adapter: address of board private structure
2118 *
31dbe5b4 2119 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2120 * For ASF and Pass Through versions of f/w this means that
2121 * the driver is loaded. For AMT version (only with 82573)
2122 * of the f/w this means that the network i/f is open.
2123 **/
31dbe5b4 2124void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2125{
2126 struct e1000_hw *hw = &adapter->hw;
2127 u32 ctrl_ext;
2128 u32 swsm;
2129
2130 /* Let firmware know the driver has taken over */
2131 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2132 swsm = er32(SWSM);
2133 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2134 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2135 ctrl_ext = er32(CTRL_EXT);
ad68076e 2136 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2137 }
2138}
2139
2140/**
31dbe5b4 2141 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2142 * @adapter: address of board private structure
2143 *
31dbe5b4 2144 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2145 * For ASF and Pass Through versions of f/w this means that the
2146 * driver is no longer loaded. For AMT version (only with 82573) i
2147 * of the f/w this means that the network i/f is closed.
2148 *
2149 **/
31dbe5b4 2150void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2151{
2152 struct e1000_hw *hw = &adapter->hw;
2153 u32 ctrl_ext;
2154 u32 swsm;
2155
2156 /* Let firmware taken over control of h/w */
2157 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2158 swsm = er32(SWSM);
2159 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2160 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2161 ctrl_ext = er32(CTRL_EXT);
ad68076e 2162 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2163 }
2164}
2165
bc7f75fa
AK		 2166/**
2167 * @e1000_alloc_ring - allocate memory for a ring structure
2168 **/
2169static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2170 struct e1000_ring *ring)
2171{
2172 struct pci_dev *pdev = adapter->pdev;
2173
2174 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2175 GFP_KERNEL);
2176 if (!ring->desc)
2177 return -ENOMEM;
2178
2179 return 0;
2180}
2181
2182/**
2183 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2184 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2185 *
2186 * Return 0 on success, negative on failure
2187 **/
55aa6985 2188int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2189{
55aa6985 2190 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2191 int err = -ENOMEM, size;
2192
2193 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2194 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2195 if (!tx_ring->buffer_info)
2196 goto err;
bc7f75fa
AK		 2197
2198 /* round up to nearest 4K */
2199 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2200 tx_ring->size = ALIGN(tx_ring->size, 4096);
2201
2202 err = e1000_alloc_ring_dma(adapter, tx_ring);
2203 if (err)
2204 goto err;
2205
2206 tx_ring->next_to_use = 0;
2207 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2208
2209 return 0;
2210err:
2211 vfree(tx_ring->buffer_info);
44defeb3 2212 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2213 return err;
2214}
2215
2216/**
2217 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2218 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2219 *
2220 * Returns 0 on success, negative on failure
2221 **/
55aa6985 2222int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2223{
55aa6985 2224 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2225 struct e1000_buffer *buffer_info;
2226 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2227
2228 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2229 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2230 if (!rx_ring->buffer_info)
2231 goto err;
bc7f75fa 2232
47f44e40
AK		 2233 for (i = 0; i < rx_ring->count; i++) {
2234 buffer_info = &rx_ring->buffer_info[i];
2235 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2236 sizeof(struct e1000_ps_page),
2237 GFP_KERNEL);
2238 if (!buffer_info->ps_pages)
2239 goto err_pages;
2240 }
bc7f75fa
AK		 2241
2242 desc_len = sizeof(union e1000_rx_desc_packet_split);
2243
2244 /* Round up to nearest 4K */
2245 rx_ring->size = rx_ring->count * desc_len;
2246 rx_ring->size = ALIGN(rx_ring->size, 4096);
2247
2248 err = e1000_alloc_ring_dma(adapter, rx_ring);
2249 if (err)
47f44e40 2250 goto err_pages;
bc7f75fa
AK		 2251
2252 rx_ring->next_to_clean = 0;
2253 rx_ring->next_to_use = 0;
2254 rx_ring->rx_skb_top = NULL;
2255
2256 return 0;
47f44e40
AK		 2257
2258err_pages:
2259 for (i = 0; i < rx_ring->count; i++) {
2260 buffer_info = &rx_ring->buffer_info[i];
2261 kfree(buffer_info->ps_pages);
2262 }
bc7f75fa
AK		 2263err:
2264 vfree(rx_ring->buffer_info);
e9262447 2265 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2266 return err;
2267}
2268
2269/**
2270 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2271 * @tx_ring: Tx descriptor ring
bc7f75fa 2272 **/
55aa6985 2273static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2274{
55aa6985 2275 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2276 struct e1000_buffer *buffer_info;
2277 unsigned long size;
2278 unsigned int i;
2279
2280 for (i = 0; i < tx_ring->count; i++) {
2281 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2282 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2283 }
2284
3f0cfa3b 2285 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2286 size = sizeof(struct e1000_buffer) * tx_ring->count;
2287 memset(tx_ring->buffer_info, 0, size);
2288
2289 memset(tx_ring->desc, 0, tx_ring->size);
2290
2291 tx_ring->next_to_use = 0;
2292 tx_ring->next_to_clean = 0;
2293
c5083cf6
BA		 2294 writel(0, tx_ring->head);
2295 writel(0, tx_ring->tail);
bc7f75fa
AK		 2296}
2297
2298/**
2299 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2300 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2301 *
2302 * Free all transmit software resources
2303 **/
55aa6985 2304void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2305{
55aa6985 2306 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2307 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2308
55aa6985 2309 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2310
2311 vfree(tx_ring->buffer_info);
2312 tx_ring->buffer_info = NULL;
2313
2314 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2315 tx_ring->dma);
2316 tx_ring->desc = NULL;
2317}
2318
2319/**
2320 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2321 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2322 *
2323 * Free all receive software resources
2324 **/
55aa6985 2325void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2326{
55aa6985 2327 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2328 struct pci_dev *pdev = adapter->pdev;
47f44e40 2329 int i;
bc7f75fa 2330
55aa6985 2331 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2332
b1cdfead 2333 for (i = 0; i < rx_ring->count; i++)
47f44e40 2334 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2335
bc7f75fa
AK		 2336 vfree(rx_ring->buffer_info);
2337 rx_ring->buffer_info = NULL;
2338
bc7f75fa
AK		 2339 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2340 rx_ring->dma);
2341 rx_ring->desc = NULL;
2342}
2343
2344/**
2345 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2346 * @adapter: pointer to adapter
2347 * @itr_setting: current adapter->itr
2348 * @packets: the number of packets during this measurement interval
2349 * @bytes: the number of bytes during this measurement interval
2350 *
bc7f75fa
AK		 2351 * Stores a new ITR value based on packets and byte
2352 * counts during the last interrupt. The advantage of per interrupt
2353 * computation is faster updates and more accurate ITR for the current
2354 * traffic pattern. Constants in this function were computed
2355 * based on theoretical maximum wire speed and thresholds were set based
2356 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2357 * while increasing bulk throughput. This functionality is controlled
2358 * by the InterruptThrottleRate module parameter.
bc7f75fa
AK		 2359 **/
2360static unsigned int e1000_update_itr(struct e1000_adapter *adapter,
2361 u16 itr_setting, int packets,
2362 int bytes)
2363{
2364 unsigned int retval = itr_setting;
2365
2366 if (packets == 0)
2367 goto update_itr_done;
2368
2369 switch (itr_setting) {
2370 case lowest_latency:
2371 /* handle TSO and jumbo frames */
2372 if (bytes/packets > 8000)
2373 retval = bulk_latency;
b1cdfead 2374 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2375 retval = low_latency;
bc7f75fa
AK		 2376 break;
2377 case low_latency: /* 50 usec aka 20000 ints/s */
2378 if (bytes > 10000) {
2379 /* this if handles the TSO accounting */
b1cdfead 2380 if (bytes/packets > 8000)
bc7f75fa 2381 retval = bulk_latency;
b1cdfead 2382 else if ((packets < 10) || ((bytes/packets) > 1200))
bc7f75fa 2383 retval = bulk_latency;
b1cdfead 2384 else if ((packets > 35))
bc7f75fa 2385 retval = lowest_latency;
bc7f75fa
AK		 2386 } else if (bytes/packets > 2000) {
2387 retval = bulk_latency;
2388 } else if (packets <= 2 && bytes < 512) {
2389 retval = lowest_latency;
2390 }
2391 break;
2392 case bulk_latency: /* 250 usec aka 4000 ints/s */
2393 if (bytes > 25000) {
b1cdfead 2394 if (packets > 35)
bc7f75fa 2395 retval = low_latency;
bc7f75fa
AK		 2396 } else if (bytes < 6000) {
2397 retval = low_latency;
2398 }
2399 break;
2400 }
2401
2402update_itr_done:
2403 return retval;
2404}
2405
2406static void e1000_set_itr(struct e1000_adapter *adapter)
2407{
2408 struct e1000_hw *hw = &adapter->hw;
2409 u16 current_itr;
2410 u32 new_itr = adapter->itr;
2411
2412 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2413 if (adapter->link_speed != SPEED_1000) {
2414 current_itr = 0;
2415 new_itr = 4000;
2416 goto set_itr_now;
2417 }
2418
828bac87
BA		 2419 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2420 new_itr = 0;
2421 goto set_itr_now;
2422 }
2423
bc7f75fa
AK		 2424 adapter->tx_itr = e1000_update_itr(adapter,
2425 adapter->tx_itr,
2426 adapter->total_tx_packets,
2427 adapter->total_tx_bytes);
2428 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2429 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2430 adapter->tx_itr = low_latency;
2431
2432 adapter->rx_itr = e1000_update_itr(adapter,
2433 adapter->rx_itr,
2434 adapter->total_rx_packets,
2435 adapter->total_rx_bytes);
2436 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2437 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2438 adapter->rx_itr = low_latency;
2439
2440 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2441
2442 switch (current_itr) {
2443 /* counts and packets in update_itr are dependent on these numbers */
2444 case lowest_latency:
2445 new_itr = 70000;
2446 break;
2447 case low_latency:
2448 new_itr = 20000; /* aka hwitr = ~200 */
2449 break;
2450 case bulk_latency:
2451 new_itr = 4000;
2452 break;
2453 default:
2454 break;
2455 }
2456
2457set_itr_now:
2458 if (new_itr != adapter->itr) {
ad68076e
BA		 2459 /*
2460 * this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2461 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2462 * increasing
2463 */
bc7f75fa
AK		 2464 new_itr = new_itr > adapter->itr ?
2465 min(adapter->itr + (new_itr >> 2), new_itr) :
2466 new_itr;
2467 adapter->itr = new_itr;
4662e82b
BA		 2468 adapter->rx_ring->itr_val = new_itr;
2469 if (adapter->msix_entries)
2470 adapter->rx_ring->set_itr = 1;
2471 else
828bac87
BA		 2472 if (new_itr)
2473 ew32(ITR, 1000000000 / (new_itr * 256));
2474 else
2475 ew32(ITR, 0);
bc7f75fa
AK		 2476 }
2477}
2478
4662e82b
BA		 2479/**
2480 * e1000_alloc_queues - Allocate memory for all rings
2481 * @adapter: board private structure to initialize
2482 **/
2483static int __devinit e1000_alloc_queues(struct e1000_adapter *adapter)
2484{
55aa6985
BA		 2485 int size = sizeof(struct e1000_ring);
2486
2487 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2488 if (!adapter->tx_ring)
2489 goto err;
55aa6985
BA		 2490 adapter->tx_ring->count = adapter->tx_ring_count;
2491 adapter->tx_ring->adapter = adapter;
4662e82b 2492
55aa6985 2493 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2494 if (!adapter->rx_ring)
2495 goto err;
55aa6985
BA		 2496 adapter->rx_ring->count = adapter->rx_ring_count;
2497 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2498
2499 return 0;
2500err:
2501 e_err("Unable to allocate memory for queues\n");
2502 kfree(adapter->rx_ring);
2503 kfree(adapter->tx_ring);
2504 return -ENOMEM;
2505}
2506
bc7f75fa
AK		 2507/**
2508 * e1000_clean - NAPI Rx polling callback
ad68076e 2509 * @napi: struct associated with this polling callback
489815ce 2510 * @budget: amount of packets driver is allowed to process this poll
bc7f75fa
AK		 2511 **/
2512static int e1000_clean(struct napi_struct *napi, int budget)
2513{
2514 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter, napi);
4662e82b 2515 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2516 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2517 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2518
4cf1653a 2519 adapter = netdev_priv(poll_dev);
bc7f75fa 2520
4662e82b
BA		 2521 if (adapter->msix_entries &&
2522 !(adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2523 goto clean_rx;
2524
55aa6985 2525 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
bc7f75fa 2526
4662e82b 2527clean_rx:
55aa6985 2528 adapter->clean_rx(adapter->rx_ring, &work_done, budget);
d2c7ddd6 2529
12d04a3c 2530 if (!tx_cleaned)
d2c7ddd6 2531 work_done = budget;
bc7f75fa 2532
53e52c72
DM		 2533 /* If budget not fully consumed, exit the polling mode */
2534 if (work_done < budget) {
bc7f75fa
AK		 2535 if (adapter->itr_setting & 3)
2536 e1000_set_itr(adapter);
288379f0 2537 napi_complete(napi);
a3c69fef
JB		 2538 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2539 if (adapter->msix_entries)
2540 ew32(IMS, adapter->rx_ring->ims_val);
2541 else
2542 e1000_irq_enable(adapter);
2543 }
bc7f75fa
AK		 2544 }
2545
2546 return work_done;
2547}
2548
8e586137 2549static int e1000_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2550{
2551 struct e1000_adapter *adapter = netdev_priv(netdev);
2552 struct e1000_hw *hw = &adapter->hw;
2553 u32 vfta, index;
2554
2555 /* don't update vlan cookie if already programmed */
2556 if ((adapter->hw.mng_cookie.status &
2557 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2558 (vid == adapter->mng_vlan_id))
8e586137 2559 return 0;
caaddaf8 2560
bc7f75fa 2561 /* add VID to filter table */
caaddaf8
BA		 2562 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2563 index = (vid >> 5) & 0x7F;
2564 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2565 vfta |= (1 << (vid & 0x1F));
2566 hw->mac.ops.write_vfta(hw, index, vfta);
2567 }
86d70e53
JK		 2568
2569 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2570
2571 return 0;
bc7f75fa
AK		 2572}
2573
8e586137 2574static int e1000_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
bc7f75fa
AK		 2575{
2576 struct e1000_adapter *adapter = netdev_priv(netdev);
2577 struct e1000_hw *hw = &adapter->hw;
2578 u32 vfta, index;
2579
bc7f75fa
AK		 2580 if ((adapter->hw.mng_cookie.status &
2581 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2582 (vid == adapter->mng_vlan_id)) {
2583 /* release control to f/w */
31dbe5b4 2584 e1000e_release_hw_control(adapter);
8e586137 2585 return 0;
bc7f75fa
AK		 2586 }
2587
2588 /* remove VID from filter table */
caaddaf8
BA		 2589 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2590 index = (vid >> 5) & 0x7F;
2591 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2592 vfta &= ~(1 << (vid & 0x1F));
2593 hw->mac.ops.write_vfta(hw, index, vfta);
2594 }
86d70e53
JK		 2595
2596 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2597
2598 return 0;
bc7f75fa
AK		 2599}
2600
86d70e53
JK		 2601/**
2602 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2603 * @adapter: board private structure to initialize
2604 **/
2605static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2606{
2607 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2608 struct e1000_hw *hw = &adapter->hw;
2609 u32 rctl;
bc7f75fa 2610
86d70e53
JK		 2611 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2612 /* disable VLAN receive filtering */
2613 rctl = er32(RCTL);
2614 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2615 ew32(RCTL, rctl);
2616
2617 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
2618 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
2619 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2620 }
bc7f75fa
AK		 2621 }
2622}
2623
86d70e53
JK		 2624/**
2625 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2626 * @adapter: board private structure to initialize
2627 **/
2628static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2629{
2630 struct e1000_hw *hw = &adapter->hw;
2631 u32 rctl;
2632
2633 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2634 /* enable VLAN receive filtering */
2635 rctl = er32(RCTL);
2636 rctl |= E1000_RCTL_VFE;
2637 rctl &= ~E1000_RCTL_CFIEN;
2638 ew32(RCTL, rctl);
2639 }
2640}
bc7f75fa 2641
86d70e53
JK		 2642/**
2643 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2644 * @adapter: board private structure to initialize
2645 **/
2646static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2647{
bc7f75fa 2648 struct e1000_hw *hw = &adapter->hw;
86d70e53 2649 u32 ctrl;
bc7f75fa 2650
86d70e53
JK		 2651 /* disable VLAN tag insert/strip */
2652 ctrl = er32(CTRL);
2653 ctrl &= ~E1000_CTRL_VME;
2654 ew32(CTRL, ctrl);
2655}
bc7f75fa 2656
86d70e53
JK		 2657/**
2658 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2659 * @adapter: board private structure to initialize
2660 **/
2661static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2662{
2663 struct e1000_hw *hw = &adapter->hw;
2664 u32 ctrl;
bc7f75fa 2665
86d70e53
JK		 2666 /* enable VLAN tag insert/strip */
2667 ctrl = er32(CTRL);
2668 ctrl |= E1000_CTRL_VME;
2669 ew32(CTRL, ctrl);
2670}
bc7f75fa 2671
86d70e53
JK		 2672static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2673{
2674 struct net_device *netdev = adapter->netdev;
2675 u16 vid = adapter->hw.mng_cookie.vlan_id;
2676 u16 old_vid = adapter->mng_vlan_id;
2677
2678 if (adapter->hw.mng_cookie.status &
2679 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
2680 e1000_vlan_rx_add_vid(netdev, vid);
2681 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2682 }
2683
86d70e53
JK		 2684 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
2685 e1000_vlan_rx_kill_vid(netdev, old_vid);
bc7f75fa
AK		 2686}
2687
2688static void e1000_restore_vlan(struct e1000_adapter *adapter)
2689{
2690 u16 vid;
2691
86d70e53 2692 e1000_vlan_rx_add_vid(adapter->netdev, 0);
bc7f75fa 2693
86d70e53 2694 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
bc7f75fa 2695 e1000_vlan_rx_add_vid(adapter->netdev, vid);
bc7f75fa
AK		 2696}
2697
cd791618 2698static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2699{
2700 struct e1000_hw *hw = &adapter->hw;
cd791618 2701 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2702
2703 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2704 return;
2705
2706 manc = er32(MANC);
2707
ad68076e
BA		 2708 /*
2709 * enable receiving management packets to the host. this will probably
bc7f75fa 2710 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2711 * the packets will be handled on SMBUS
2712 */
bc7f75fa
AK		 2713 manc |= E1000_MANC_EN_MNG2HOST;
2714 manc2h = er32(MANC2H);
cd791618
BA		 2715
2716 switch (hw->mac.type) {
2717 default:
2718 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2719 break;
2720 case e1000_82574:
2721 case e1000_82583:
2722 /*
2723 * Check if IPMI pass-through decision filter already exists;
2724 * if so, enable it.
2725 */
2726 for (i = 0, j = 0; i < 8; i++) {
2727 mdef = er32(MDEF(i));
2728
2729 /* Ignore filters with anything other than IPMI ports */
3b21b508 2730 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2731 continue;
2732
2733 /* Enable this decision filter in MANC2H */
2734 if (mdef)
2735 manc2h |= (1 << i);
2736
2737 j |= mdef;
2738 }
2739
2740 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2741 break;
2742
2743 /* Create new decision filter in an empty filter */
2744 for (i = 0, j = 0; i < 8; i++)
2745 if (er32(MDEF(i)) == 0) {
2746 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2747 E1000_MDEF_PORT_664));
2748 manc2h |= (1 << 1);
2749 j++;
2750 break;
2751 }
2752
2753 if (!j)
2754 e_warn("Unable to create IPMI pass-through filter\n");
2755 break;
2756 }
2757
bc7f75fa
AK		 2758 ew32(MANC2H, manc2h);
2759 ew32(MANC, manc);
2760}
2761
2762/**
af667a29 2763 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2764 * @adapter: board private structure
2765 *
2766 * Configure the Tx unit of the MAC after a reset.
2767 **/
2768static void e1000_configure_tx(struct e1000_adapter *adapter)
2769{
2770 struct e1000_hw *hw = &adapter->hw;
2771 struct e1000_ring *tx_ring = adapter->tx_ring;
2772 u64 tdba;
c550b121 2773 u32 tdlen, tarc;
bc7f75fa
AK		 2774
2775 /* Setup the HW Tx Head and Tail descriptor pointers */
2776 tdba = tx_ring->dma;
2777 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
284901a9 2778 ew32(TDBAL, (tdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 2779 ew32(TDBAH, (tdba >> 32));
2780 ew32(TDLEN, tdlen);
2781 ew32(TDH, 0);
2782 ew32(TDT, 0);
c5083cf6
BA		 2783 tx_ring->head = adapter->hw.hw_addr + E1000_TDH;
2784 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT;
bc7f75fa 2785
bc7f75fa
AK		 2786 /* Set the Tx Interrupt Delay register */
2787 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2788 /* Tx irq moderation */
bc7f75fa
AK		 2789 ew32(TADV, adapter->tx_abs_int_delay);
2790
3a3b7586
JB		 2791 if (adapter->flags2 & FLAG2_DMA_BURST) {
2792 u32 txdctl = er32(TXDCTL(0));
2793 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2794 E1000_TXDCTL_WTHRESH);
2795 /*
2796 * set up some performance related parameters to encourage the
2797 * hardware to use the bus more efficiently in bursts, depends
2798 * on the tx_int_delay to be enabled,
2799 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time
2800 * hthresh = 1 ==> prefetch when one or more available
2801 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2802 * BEWARE: this seems to work but should be considered first if
af667a29 2803 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2804 */
2805 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2806 ew32(TXDCTL(0), txdctl);
3a3b7586 2807 }
56032be7
BA		 2808 /* erratum work around: set txdctl the same for both queues */
2809 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2810
bc7f75fa 2811 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2812 tarc = er32(TARC(0));
ad68076e
BA		 2813 /*
2814 * set the speed mode bit, we'll clear it if we're not at
2815 * gigabit link later
2816 */
bc7f75fa
AK		 2817#define SPEED_MODE_BIT (1 << 21)
2818 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2819 ew32(TARC(0), tarc);
bc7f75fa
AK		 2820 }
2821
2822 /* errata: program both queues to unweighted RR */
2823 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2824 tarc = er32(TARC(0));
bc7f75fa 2825 tarc |= 1;
e9ec2c0f
JK		 2826 ew32(TARC(0), tarc);
2827 tarc = er32(TARC(1));
bc7f75fa 2828 tarc |= 1;
e9ec2c0f 2829 ew32(TARC(1), tarc);
bc7f75fa
AK		 2830 }
2831
bc7f75fa
AK		 2832 /* Setup Transmit Descriptor Settings for eop descriptor */
2833 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2834
2835 /* only set IDE if we are delaying interrupts using the timers */
2836 if (adapter->tx_int_delay)
2837 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2838
2839 /* enable Report Status bit */
2840 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2841
edfea6e6 2842 e1000e_config_collision_dist(hw);
bc7f75fa
AK		 2843}
2844
2845/**
2846 * e1000_setup_rctl - configure the receive control registers
2847 * @adapter: Board private structure
2848 **/
2849#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2850 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2851static void e1000_setup_rctl(struct e1000_adapter *adapter)
2852{
2853 struct e1000_hw *hw = &adapter->hw;
2854 u32 rctl, rfctl;
bc7f75fa
AK		 2855 u32 pages = 0;
2856
a1ce6473
BA		 2857 /* Workaround Si errata on 82579 - configure jumbo frame flow */
2858 if (hw->mac.type == e1000_pch2lan) {
2859 s32 ret_val;
2860
2861 if (adapter->netdev->mtu > ETH_DATA_LEN)
2862 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
2863 else
2864 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
dd93f95e
BA		 2865
2866 if (ret_val)
2867 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473
BA		 2868 }
2869
bc7f75fa
AK		 2870 /* Program MC offset vector base */
2871 rctl = er32(RCTL);
2872 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2873 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
2874 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
2875 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2876
2877 /* Do not Store bad packets */
2878 rctl &= ~E1000_RCTL_SBP;
2879
2880 /* Enable Long Packet receive */
2881 if (adapter->netdev->mtu <= ETH_DATA_LEN)
2882 rctl &= ~E1000_RCTL_LPE;
2883 else
2884 rctl |= E1000_RCTL_LPE;
2885
eb7c3adb
JK		 2886 /* Some systems expect that the CRC is included in SMBUS traffic. The
2887 * hardware strips the CRC before sending to both SMBUS (BMC) and to
2888 * host memory when this is enabled
2889 */
2890 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
2891 rctl |= E1000_RCTL_SECRC;
5918bd88 2892
a4f58f54
BA		 2893 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
2894 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
2895 u16 phy_data;
2896
2897 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
2898 phy_data &= 0xfff8;
2899 phy_data |= (1 << 2);
2900 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
2901
2902 e1e_rphy(hw, 22, &phy_data);
2903 phy_data &= 0x0fff;
2904 phy_data |= (1 << 14);
2905 e1e_wphy(hw, 0x10, 0x2823);
2906 e1e_wphy(hw, 0x11, 0x0003);
2907 e1e_wphy(hw, 22, phy_data);
2908 }
2909
bc7f75fa
AK		 2910 /* Setup buffer sizes */
2911 rctl &= ~E1000_RCTL_SZ_4096;
2912 rctl |= E1000_RCTL_BSEX;
2913 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 2914 case 2048:
2915 default:
2916 rctl |= E1000_RCTL_SZ_2048;
2917 rctl &= ~E1000_RCTL_BSEX;
2918 break;
2919 case 4096:
2920 rctl |= E1000_RCTL_SZ_4096;
2921 break;
2922 case 8192:
2923 rctl |= E1000_RCTL_SZ_8192;
2924 break;
2925 case 16384:
2926 rctl |= E1000_RCTL_SZ_16384;
2927 break;
2928 }
2929
5f450212
BA		 2930 /* Enable Extended Status in all Receive Descriptors */
2931 rfctl = er32(RFCTL);
2932 rfctl |= E1000_RFCTL_EXTEN;
2933
bc7f75fa
AK		 2934 /*
2935 * 82571 and greater support packet-split where the protocol
2936 * header is placed in skb->data and the packet data is
2937 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
2938 * In the case of a non-split, skb->data is linearly filled,
2939 * followed by the page buffers. Therefore, skb->data is
2940 * sized to hold the largest protocol header.
2941 *
2942 * allocations using alloc_page take too long for regular MTU
2943 * so only enable packet split for jumbo frames
2944 *
2945 * Using pages when the page size is greater than 16k wastes
2946 * a lot of memory, since we allocate 3 pages at all times
2947 * per packet.
2948 */
bc7f75fa 2949 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 2950 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 2951 adapter->rx_ps_pages = pages;
97ac8cae
BA		 2952 else
2953 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 2954
2955 if (adapter->rx_ps_pages) {
90da0669
BA		 2956 u32 psrctl = 0;
2957
ad68076e
BA		 2958 /*
2959 * disable packet split support for IPv6 extension headers,
2960 * because some malformed IPv6 headers can hang the Rx
2961 */
bc7f75fa
AK		 2962 rfctl |= (E1000_RFCTL_IPV6_EX_DIS |
2963 E1000_RFCTL_NEW_IPV6_EXT_DIS);
2964
140a7480
AK		 2965 /* Enable Packet split descriptors */
2966 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa
AK		 2967
2968 psrctl |= adapter->rx_ps_bsize0 >>
2969 E1000_PSRCTL_BSIZE0_SHIFT;
2970
2971 switch (adapter->rx_ps_pages) {
2972 case 3:
2973 psrctl |= PAGE_SIZE <<
2974 E1000_PSRCTL_BSIZE3_SHIFT;
2975 case 2:
2976 psrctl |= PAGE_SIZE <<
2977 E1000_PSRCTL_BSIZE2_SHIFT;
2978 case 1:
2979 psrctl |= PAGE_SIZE >>
2980 E1000_PSRCTL_BSIZE1_SHIFT;
2981 break;
2982 }
2983
2984 ew32(PSRCTL, psrctl);
2985 }
2986
5f450212 2987 ew32(RFCTL, rfctl);
bc7f75fa 2988 ew32(RCTL, rctl);
318a94d6
JK		 2989 /* just started the receive unit, no need to restart */
2990 adapter->flags &= ~FLAG_RX_RESTART_NOW;
bc7f75fa
AK		 2991}
2992
2993/**
2994 * e1000_configure_rx - Configure Receive Unit after Reset
2995 * @adapter: board private structure
2996 *
2997 * Configure the Rx unit of the MAC after a reset.
2998 **/
2999static void e1000_configure_rx(struct e1000_adapter *adapter)
3000{
3001 struct e1000_hw *hw = &adapter->hw;
3002 struct e1000_ring *rx_ring = adapter->rx_ring;
3003 u64 rdba;
3004 u32 rdlen, rctl, rxcsum, ctrl_ext;
3005
3006 if (adapter->rx_ps_pages) {
3007 /* this is a 32 byte descriptor */
3008 rdlen = rx_ring->count *
af667a29 3009 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3010 adapter->clean_rx = e1000_clean_rx_irq_ps;
3011 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3012 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3013 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3014 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3015 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3016 } else {
5f450212 3017 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3018 adapter->clean_rx = e1000_clean_rx_irq;
3019 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3020 }
3021
3022 /* disable receives while setting up the descriptors */
3023 rctl = er32(RCTL);
7f99ae63
BA		 3024 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3025 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3026 e1e_flush();
1bba4386 3027 usleep_range(10000, 20000);
bc7f75fa 3028
3a3b7586
JB		 3029 if (adapter->flags2 & FLAG2_DMA_BURST) {
3030 /*
3031 * set the writeback threshold (only takes effect if the RDTR
3032 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3033 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3034 * granularity = 01
3035 * wthresh = 04,
3036 * hthresh = 04,
3037 * pthresh = 0x20
3038 */
3039 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3040 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3041
3042 /*
3043 * override the delay timers for enabling bursting, only if
3044 * the value was not set by the user via module options
3045 */
3046 if (adapter->rx_int_delay == DEFAULT_RDTR)
3047 adapter->rx_int_delay = BURST_RDTR;
3048 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3049 adapter->rx_abs_int_delay = BURST_RADV;
3050 }
3051
bc7f75fa
AK		 3052 /* set the Receive Delay Timer Register */
3053 ew32(RDTR, adapter->rx_int_delay);
3054
3055 /* irq moderation */
3056 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3057 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
ad68076e 3058 ew32(ITR, 1000000000 / (adapter->itr * 256));
bc7f75fa
AK		 3059
3060 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3061 /* Auto-Mask interrupts upon ICR access */
3062 ctrl_ext |= E1000_CTRL_EXT_IAME;
3063 ew32(IAM, 0xffffffff);
3064 ew32(CTRL_EXT, ctrl_ext);
3065 e1e_flush();
3066
ad68076e
BA		 3067 /*
3068 * Setup the HW Rx Head and Tail Descriptor Pointers and
3069 * the Base and Length of the Rx Descriptor Ring
3070 */
bc7f75fa 3071 rdba = rx_ring->dma;
284901a9 3072 ew32(RDBAL, (rdba & DMA_BIT_MASK(32)));
bc7f75fa
AK		 3073 ew32(RDBAH, (rdba >> 32));
3074 ew32(RDLEN, rdlen);
3075 ew32(RDH, 0);
3076 ew32(RDT, 0);
c5083cf6
BA		 3077 rx_ring->head = adapter->hw.hw_addr + E1000_RDH;
3078 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT;
bc7f75fa
AK		 3079
3080 /* Enable Receive Checksum Offload for TCP and UDP */
3081 rxcsum = er32(RXCSUM);
dc221294 3082 if (adapter->netdev->features & NETIF_F_RXCSUM) {
bc7f75fa
AK		 3083 rxcsum |= E1000_RXCSUM_TUOFL;
3084
ad68076e
BA		 3085 /*
3086 * IPv4 payload checksum for UDP fragments must be
3087 * used in conjunction with packet-split.
3088 */
bc7f75fa
AK		 3089 if (adapter->rx_ps_pages)
3090 rxcsum |= E1000_RXCSUM_IPPCSE;
3091 } else {
3092 rxcsum &= ~E1000_RXCSUM_TUOFL;
3093 /* no need to clear IPPCSE as it defaults to 0 */
3094 }
3095 ew32(RXCSUM, rxcsum);
3096
79d4e908
BA		 3097 if (adapter->hw.mac.type == e1000_pch2lan) {
3098 /*
3099 * With jumbo frames, excessive C-state transition
3100 * latencies result in dropped transactions.
3101 */
53ec5498
BA		 3102 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3103 u32 rxdctl = er32(RXDCTL(0));
3104 ew32(RXDCTL(0), rxdctl | 0x3);
af667a29 3105 pm_qos_update_request(&adapter->netdev->pm_qos_req, 55);
53ec5498 3106 } else {
af667a29
BA		 3107 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3108 PM_QOS_DEFAULT_VALUE);
53ec5498 3109 }
97ac8cae 3110 }
bc7f75fa
AK		 3111
3112 /* Enable Receives */
3113 ew32(RCTL, rctl);
3114}
3115
3116/**
ef9b965a
JB		 3117 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3118 * @netdev: network interface device structure
bc7f75fa 3119 *
ef9b965a
JB		 3120 * Writes multicast address list to the MTA hash table.
3121 * Returns: -ENOMEM on failure
3122 * 0 on no addresses written
3123 * X on writing X addresses to MTA
3124 */
3125static int e1000e_write_mc_addr_list(struct net_device *netdev)
3126{
3127 struct e1000_adapter *adapter = netdev_priv(netdev);
3128 struct e1000_hw *hw = &adapter->hw;
3129 struct netdev_hw_addr *ha;
3130 u8 *mta_list;
3131 int i;
3132
3133 if (netdev_mc_empty(netdev)) {
3134 /* nothing to program, so clear mc list */
3135 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3136 return 0;
3137 }
3138
3139 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3140 if (!mta_list)
3141 return -ENOMEM;
3142
3143 /* update_mc_addr_list expects a packed array of only addresses. */
3144 i = 0;
3145 netdev_for_each_mc_addr(ha, netdev)
3146 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3147
3148 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3149 kfree(mta_list);
3150
3151 return netdev_mc_count(netdev);
3152}
3153
3154/**
3155 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3156 * @netdev: network interface device structure
bc7f75fa 3157 *
ef9b965a
JB		 3158 * Writes unicast address list to the RAR table.
3159 * Returns: -ENOMEM on failure/insufficient address space
3160 * 0 on no addresses written
3161 * X on writing X addresses to the RAR table
bc7f75fa 3162 **/
ef9b965a 3163static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3164{
ef9b965a
JB		 3165 struct e1000_adapter *adapter = netdev_priv(netdev);
3166 struct e1000_hw *hw = &adapter->hw;
3167 unsigned int rar_entries = hw->mac.rar_entry_count;
3168 int count = 0;
3169
3170 /* save a rar entry for our hardware address */
3171 rar_entries--;
3172
3173 /* save a rar entry for the LAA workaround */
3174 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3175 rar_entries--;
3176
3177 /* return ENOMEM indicating insufficient memory for addresses */
3178 if (netdev_uc_count(netdev) > rar_entries)
3179 return -ENOMEM;
3180
3181 if (!netdev_uc_empty(netdev) && rar_entries) {
3182 struct netdev_hw_addr *ha;
3183
3184 /*
3185 * write the addresses in reverse order to avoid write
3186 * combining
3187 */
3188 netdev_for_each_uc_addr(ha, netdev) {
3189 if (!rar_entries)
3190 break;
3191 e1000e_rar_set(hw, ha->addr, rar_entries--);
3192 count++;
3193 }
3194 }
3195
3196 /* zero out the remaining RAR entries not used above */
3197 for (; rar_entries > 0; rar_entries--) {
3198 ew32(RAH(rar_entries), 0);
3199 ew32(RAL(rar_entries), 0);
3200 }
3201 e1e_flush();
3202
3203 return count;
bc7f75fa
AK		 3204}
3205
3206/**
ef9b965a 3207 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3208 * @netdev: network interface device structure
3209 *
ef9b965a
JB		 3210 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3211 * address list or the network interface flags are updated. This routine is
3212 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3213 * promiscuous mode, and all-multi behavior.
3214 **/
ef9b965a 3215static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3216{
3217 struct e1000_adapter *adapter = netdev_priv(netdev);
3218 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3219 u32 rctl;
bc7f75fa
AK		 3220
3221 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3222 rctl = er32(RCTL);
3223
ef9b965a
JB		 3224 /* clear the affected bits */
3225 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3226
bc7f75fa
AK		 3227 if (netdev->flags & IFF_PROMISC) {
3228 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3229 /* Do not hardware filter VLANs in promisc mode */
3230 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3231 } else {
ef9b965a 3232 int count;
746b9f02
PM		 3233 if (netdev->flags & IFF_ALLMULTI) {
3234 rctl |= E1000_RCTL_MPE;
746b9f02 3235 } else {
ef9b965a
JB		 3236 /*
3237 * Write addresses to the MTA, if the attempt fails
3238 * then we should just turn on promiscuous mode so
3239 * that we can at least receive multicast traffic
3240 */
3241 count = e1000e_write_mc_addr_list(netdev);
3242 if (count < 0)
3243 rctl |= E1000_RCTL_MPE;
746b9f02 3244 }
86d70e53 3245 e1000e_vlan_filter_enable(adapter);
bc7f75fa 3246 /*
ef9b965a
JB		 3247 * Write addresses to available RAR registers, if there is not
3248 * sufficient space to store all the addresses then enable
3249 * unicast promiscuous mode
bc7f75fa 3250 */
ef9b965a
JB		 3251 count = e1000e_write_uc_addr_list(netdev);
3252 if (count < 0)
3253 rctl |= E1000_RCTL_UPE;
bc7f75fa 3254 }
86d70e53 3255
ef9b965a
JB		 3256 ew32(RCTL, rctl);
3257
86d70e53
JK		 3258 if (netdev->features & NETIF_F_HW_VLAN_RX)
3259 e1000e_vlan_strip_enable(adapter);
3260 else
3261 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3262}
3263
70495a50
BA		 3264static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3265{
3266 struct e1000_hw *hw = &adapter->hw;
3267 u32 mrqc, rxcsum;
3268 int i;
3269 static const u32 rsskey[10] = {
3270 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3271 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3272 };
3273
3274 /* Fill out hash function seed */
3275 for (i = 0; i < 10; i++)
3276 ew32(RSSRK(i), rsskey[i]);
3277
3278 /* Direct all traffic to queue 0 */
3279 for (i = 0; i < 32; i++)
3280 ew32(RETA(i), 0);
3281
3282 /*
3283 * Disable raw packet checksumming so that RSS hash is placed in
3284 * descriptor on writeback.
3285 */
3286 rxcsum = er32(RXCSUM);
3287 rxcsum |= E1000_RXCSUM_PCSD;
3288
3289 ew32(RXCSUM, rxcsum);
3290
3291 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3292 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3293 E1000_MRQC_RSS_FIELD_IPV6 |
3294 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3295 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3296
3297 ew32(MRQC, mrqc);
3298}
3299
bc7f75fa 3300/**
ad68076e 3301 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3302 * @adapter: private board structure
3303 **/
3304static void e1000_configure(struct e1000_adapter *adapter)
3305{
55aa6985
BA		 3306 struct e1000_ring *rx_ring = adapter->rx_ring;
3307
ef9b965a 3308 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3309
3310 e1000_restore_vlan(adapter);
cd791618 3311 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3312
3313 e1000_configure_tx(adapter);
70495a50
BA		 3314
3315 if (adapter->netdev->features & NETIF_F_RXHASH)
3316 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3317 e1000_setup_rctl(adapter);
3318 e1000_configure_rx(adapter);
55aa6985 3319 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3320}
3321
3322/**
3323 * e1000e_power_up_phy - restore link in case the phy was powered down
3324 * @adapter: address of board private structure
3325 *
3326 * The phy may be powered down to save power and turn off link when the
3327 * driver is unloaded and wake on lan is not enabled (among others)
3328 * *** this routine MUST be followed by a call to e1000e_reset ***
3329 **/
3330void e1000e_power_up_phy(struct e1000_adapter *adapter)
3331{
17f208de
BA		 3332 if (adapter->hw.phy.ops.power_up)
3333 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3334
3335 adapter->hw.mac.ops.setup_link(&adapter->hw);
3336}
3337
3338/**
3339 * e1000_power_down_phy - Power down the PHY
3340 *
17f208de
BA		 3341 * Power down the PHY so no link is implied when interface is down.
3342 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3343 */
3344static void e1000_power_down_phy(struct e1000_adapter *adapter)
3345{
bc7f75fa 3346 /* WoL is enabled */
23b66e2b 3347 if (adapter->wol)
bc7f75fa
AK		 3348 return;
3349
17f208de
BA		 3350 if (adapter->hw.phy.ops.power_down)
3351 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3352}
3353
3354/**
3355 * e1000e_reset - bring the hardware into a known good state
3356 *
3357 * This function boots the hardware and enables some settings that
3358 * require a configuration cycle of the hardware - those cannot be
3359 * set/changed during runtime. After reset the device needs to be
ad68076e 3360 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3361 */
3362void e1000e_reset(struct e1000_adapter *adapter)
3363{
3364 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3365 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3366 struct e1000_hw *hw = &adapter->hw;
3367 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3368 u32 pba = adapter->pba;
bc7f75fa
AK		 3369 u16 hwm;
3370
ad68076e 3371 /* reset Packet Buffer Allocation to default */
318a94d6 3372 ew32(PBA, pba);
df762464 3373
318a94d6 3374 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
ad68076e
BA		 3375 /*
3376 * To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3377 * large enough to accommodate two full transmit packets,
3378 * rounded up to the next 1KB and expressed in KB. Likewise,
3379 * the Rx FIFO should be large enough to accommodate at least
3380 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3381 * expressed in KB.
3382 */
df762464 3383 pba = er32(PBA);
bc7f75fa 3384 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3385 tx_space = pba >> 16;
bc7f75fa 3386 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3387 pba &= 0xffff;
ad68076e 3388 /*
af667a29 3389 * the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3390 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3391 */
3392 min_tx_space = (adapter->max_frame_size +
bc7f75fa
AK		 3393 sizeof(struct e1000_tx_desc) -
3394 ETH_FCS_LEN) * 2;
3395 min_tx_space = ALIGN(min_tx_space, 1024);
3396 min_tx_space >>= 10;
3397 /* software strips receive CRC, so leave room for it */
318a94d6 3398 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3399 min_rx_space = ALIGN(min_rx_space, 1024);
3400 min_rx_space >>= 10;
3401
ad68076e
BA		 3402 /*
3403 * If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3404 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3405 * allocation, take space away from current Rx allocation
3406 */
df762464
AK		 3407 if ((tx_space < min_tx_space) &&
3408 ((min_tx_space - tx_space) < pba)) {
3409 pba -= min_tx_space - tx_space;
bc7f75fa 3410
ad68076e 3411 /*
af667a29 3412 * if short on Rx space, Rx wins and must trump Tx
ad68076e
BA		 3413 * adjustment or use Early Receive if available
3414 */
79d4e908 3415 if (pba < min_rx_space)
df762464 3416 pba = min_rx_space;
bc7f75fa 3417 }
df762464
AK		 3418
3419 ew32(PBA, pba);
bc7f75fa
AK		 3420 }
3421
ad68076e
BA		 3422 /*
3423 * flow control settings
3424 *
38eb394e 3425 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3426 * (or the size used for early receive) above it in the Rx FIFO.
3427 * Set it to the lower of:
3428 * - 90% of the Rx FIFO size, and
38eb394e 3429 * - the full Rx FIFO size minus one full frame
ad68076e 3430 */
d3738bb8
BA		 3431 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3432 fc->pause_time = 0xFFFF;
3433 else
3434 fc->pause_time = E1000_FC_PAUSE_TIME;
3435 fc->send_xon = 1;
3436 fc->current_mode = fc->requested_mode;
3437
3438 switch (hw->mac.type) {
79d4e908
BA		 3439 case e1000_ich9lan:
3440 case e1000_ich10lan:
3441 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3442 pba = 14;
3443 ew32(PBA, pba);
3444 fc->high_water = 0x2800;
3445 fc->low_water = fc->high_water - 8;
3446 break;
3447 }
3448 /* fall-through */
d3738bb8 3449 default:
79d4e908
BA		 3450 hwm = min(((pba << 10) * 9 / 10),
3451 ((pba << 10) - adapter->max_frame_size));
d3738bb8
BA		 3452
3453 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
3454 fc->low_water = fc->high_water - 8;
3455 break;
3456 case e1000_pchlan:
38eb394e
BA		 3457 /*
3458 * Workaround PCH LOM adapter hangs with certain network
3459 * loads. If hangs persist, try disabling Tx flow control.
3460 */
3461 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3462 fc->high_water = 0x3500;
3463 fc->low_water = 0x1500;
3464 } else {
3465 fc->high_water = 0x5000;
3466 fc->low_water = 0x3000;
3467 }
a305595b 3468 fc->refresh_time = 0x1000;
d3738bb8
BA		 3469 break;
3470 case e1000_pch2lan:
3471 fc->high_water = 0x05C20;
3472 fc->low_water = 0x05048;
3473 fc->pause_time = 0x0650;
3474 fc->refresh_time = 0x0400;
828bac87
BA		 3475 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3476 pba = 14;
3477 ew32(PBA, pba);
3478 }
d3738bb8 3479 break;
38eb394e 3480 }
bc7f75fa 3481
828bac87
BA		 3482 /*
3483 * Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3484 * fit in receive buffer.
828bac87
BA		 3485 */
3486 if (adapter->itr_setting & 0x3) {
79d4e908 3487 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3488 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3489 dev_info(&adapter->pdev->dev,
3490 "Interrupt Throttle Rate turned off\n");
3491 adapter->flags2 |= FLAG2_DISABLE_AIM;
3492 ew32(ITR, 0);
3493 }
3494 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3495 dev_info(&adapter->pdev->dev,
3496 "Interrupt Throttle Rate turned on\n");
3497 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3498 adapter->itr = 20000;
3499 ew32(ITR, 1000000000 / (adapter->itr * 256));
3500 }
3501 }
3502
bc7f75fa
AK		 3503 /* Allow time for pending master requests to run */
3504 mac->ops.reset_hw(hw);
97ac8cae
BA		 3505
3506 /*
3507 * For parts with AMT enabled, let the firmware know
3508 * that the network interface is in control
3509 */
c43bc57e 3510 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3511 e1000e_get_hw_control(adapter);
97ac8cae 3512
bc7f75fa
AK		 3513 ew32(WUC, 0);
3514
3515 if (mac->ops.init_hw(hw))
44defeb3 3516 e_err("Hardware Error\n");
bc7f75fa
AK		 3517
3518 e1000_update_mng_vlan(adapter);
3519
3520 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3521 ew32(VET, ETH_P_8021Q);
3522
3523 e1000e_reset_adaptive(hw);
31dbe5b4
BA		 3524
3525 if (!netif_running(adapter->netdev) &&
3526 !test_bit(__E1000_TESTING, &adapter->state)) {
3527 e1000_power_down_phy(adapter);
3528 return;
3529 }
3530
bc7f75fa
AK		 3531 e1000_get_phy_info(hw);
3532
918d7197
BA		 3533 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3534 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3535 u16 phy_data = 0;
ad68076e
BA		 3536 /*
3537 * speed up time to link by disabling smart power down, ignore
bc7f75fa 3538 * the return value of this function because there is nothing
ad68076e
BA		 3539 * different we would do if it failed
3540 */
bc7f75fa
AK		 3541 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3542 phy_data &= ~IGP02E1000_PM_SPD;
3543 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3544 }
bc7f75fa
AK		 3545}
3546
3547int e1000e_up(struct e1000_adapter *adapter)
3548{
3549 struct e1000_hw *hw = &adapter->hw;
3550
3551 /* hardware has been reset, we need to reload some things */
3552 e1000_configure(adapter);
3553
3554 clear_bit(__E1000_DOWN, &adapter->state);
3555
4662e82b
BA		 3556 if (adapter->msix_entries)
3557 e1000_configure_msix(adapter);
bc7f75fa
AK		 3558 e1000_irq_enable(adapter);
3559
400484fa 3560 netif_start_queue(adapter->netdev);
4cb9be7a 3561
bc7f75fa 3562 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3563 if (adapter->msix_entries)
3564 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3565 else
3566 ew32(ICS, E1000_ICS_LSC);
3567
bc7f75fa
AK		 3568 return 0;
3569}
3570
713b3c9e
JB		 3571static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3572{
3573 struct e1000_hw *hw = &adapter->hw;
3574
3575 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3576 return;
3577
3578 /* flush pending descriptor writebacks to memory */
3579 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3580 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3581
3582 /* execute the writes immediately */
3583 e1e_flush();
3584}
3585
67fd4fcb
JK		 3586static void e1000e_update_stats(struct e1000_adapter *adapter);
3587
bc7f75fa
AK		 3588void e1000e_down(struct e1000_adapter *adapter)
3589{
3590 struct net_device *netdev = adapter->netdev;
3591 struct e1000_hw *hw = &adapter->hw;
3592 u32 tctl, rctl;
3593
ad68076e
BA		 3594 /*
3595 * signal that we're down so the interrupt handler does not
3596 * reschedule our watchdog timer
3597 */
bc7f75fa
AK		 3598 set_bit(__E1000_DOWN, &adapter->state);
3599
3600 /* disable receives in the hardware */
3601 rctl = er32(RCTL);
7f99ae63
BA		 3602 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3603 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 3604 /* flush and sleep below */
3605
4cb9be7a 3606 netif_stop_queue(netdev);
bc7f75fa
AK		 3607
3608 /* disable transmits in the hardware */
3609 tctl = er32(TCTL);
3610 tctl &= ~E1000_TCTL_EN;
3611 ew32(TCTL, tctl);
7f99ae63 3612
bc7f75fa
AK		 3613 /* flush both disables and wait for them to finish */
3614 e1e_flush();
1bba4386 3615 usleep_range(10000, 20000);
bc7f75fa 3616
bc7f75fa
AK		 3617 e1000_irq_disable(adapter);
3618
3619 del_timer_sync(&adapter->watchdog_timer);
3620 del_timer_sync(&adapter->phy_info_timer);
3621
bc7f75fa 3622 netif_carrier_off(netdev);
67fd4fcb
JK		 3623
3624 spin_lock(&adapter->stats64_lock);
3625 e1000e_update_stats(adapter);
3626 spin_unlock(&adapter->stats64_lock);
3627
400484fa 3628 e1000e_flush_descriptors(adapter);
55aa6985
BA		 3629 e1000_clean_tx_ring(adapter->tx_ring);
3630 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 3631
bc7f75fa
AK		 3632 adapter->link_speed = 0;
3633 adapter->link_duplex = 0;
3634
52cc3086
JK		 3635 if (!pci_channel_offline(adapter->pdev))
3636 e1000e_reset(adapter);
713b3c9e 3637
bc7f75fa
AK		 3638 /*
3639 * TODO: for power management, we could drop the link and
3640 * pci_disable_device here.
3641 */
3642}
3643
3644void e1000e_reinit_locked(struct e1000_adapter *adapter)
3645{
3646 might_sleep();
3647 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 3648 usleep_range(1000, 2000);
bc7f75fa
AK		 3649 e1000e_down(adapter);
3650 e1000e_up(adapter);
3651 clear_bit(__E1000_RESETTING, &adapter->state);
3652}
3653
3654/**
3655 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3656 * @adapter: board private structure to initialize
3657 *
3658 * e1000_sw_init initializes the Adapter private data structure.
3659 * Fields are initialized based on PCI device information and
3660 * OS network device settings (MTU size).
3661 **/
3662static int __devinit e1000_sw_init(struct e1000_adapter *adapter)
3663{
bc7f75fa
AK		 3664 struct net_device *netdev = adapter->netdev;
3665
3666 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
3667 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 3668 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3669 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 3670 adapter->tx_ring_count = E1000_DEFAULT_TXD;
3671 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 3672
67fd4fcb
JK		 3673 spin_lock_init(&adapter->stats64_lock);
3674
4662e82b 3675 e1000e_set_interrupt_capability(adapter);
bc7f75fa 3676
4662e82b
BA		 3677 if (e1000_alloc_queues(adapter))
3678 return -ENOMEM;
bc7f75fa 3679
bc7f75fa 3680 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 3681 e1000_irq_disable(adapter);
3682
bc7f75fa
AK		 3683 set_bit(__E1000_DOWN, &adapter->state);
3684 return 0;
bc7f75fa
AK		 3685}
3686
f8d59f78
BA		 3687/**
3688 * e1000_intr_msi_test - Interrupt Handler
3689 * @irq: interrupt number
3690 * @data: pointer to a network interface device structure
3691 **/
3692static irqreturn_t e1000_intr_msi_test(int irq, void *data)
3693{
3694 struct net_device *netdev = data;
3695 struct e1000_adapter *adapter = netdev_priv(netdev);
3696 struct e1000_hw *hw = &adapter->hw;
3697 u32 icr = er32(ICR);
3698
3bb99fe2 3699 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 3700 if (icr & E1000_ICR_RXSEQ) {
3701 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
3702 wmb();
3703 }
3704
3705 return IRQ_HANDLED;
3706}
3707
3708/**
3709 * e1000_test_msi_interrupt - Returns 0 for successful test
3710 * @adapter: board private struct
3711 *
3712 * code flow taken from tg3.c
3713 **/
3714static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
3715{
3716 struct net_device *netdev = adapter->netdev;
3717 struct e1000_hw *hw = &adapter->hw;
3718 int err;
3719
3720 /* poll_enable hasn't been called yet, so don't need disable */
3721 /* clear any pending events */
3722 er32(ICR);
3723
3724 /* free the real vector and request a test handler */
3725 e1000_free_irq(adapter);
4662e82b 3726 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 3727
3728 /* Assume that the test fails, if it succeeds then the test
3729 * MSI irq handler will unset this flag */
3730 adapter->flags |= FLAG_MSI_TEST_FAILED;
3731
3732 err = pci_enable_msi(adapter->pdev);
3733 if (err)
3734 goto msi_test_failed;
3735
a0607fd3 3736 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 3737 netdev->name, netdev);
3738 if (err) {
3739 pci_disable_msi(adapter->pdev);
3740 goto msi_test_failed;
3741 }
3742
3743 wmb();
3744
3745 e1000_irq_enable(adapter);
3746
3747 /* fire an unusual interrupt on the test handler */
3748 ew32(ICS, E1000_ICS_RXSEQ);
3749 e1e_flush();
3750 msleep(50);
3751
3752 e1000_irq_disable(adapter);
3753
3754 rmb();
3755
3756 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 3757 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30
JD		 3758 e_info("MSI interrupt test failed, using legacy interrupt.\n");
3759 } else
3760 e_dbg("MSI interrupt test succeeded!\n");
f8d59f78
BA		 3761
3762 free_irq(adapter->pdev->irq, netdev);
3763 pci_disable_msi(adapter->pdev);
3764
f8d59f78 3765msi_test_failed:
4662e82b 3766 e1000e_set_interrupt_capability(adapter);
068e8a30 3767 return e1000_request_irq(adapter);
f8d59f78
BA		 3768}
3769
3770/**
3771 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
3772 * @adapter: board private struct
3773 *
3774 * code flow taken from tg3.c, called with e1000 interrupts disabled.
3775 **/
3776static int e1000_test_msi(struct e1000_adapter *adapter)
3777{
3778 int err;
3779 u16 pci_cmd;
3780
3781 if (!(adapter->flags & FLAG_MSI_ENABLED))
3782 return 0;
3783
3784 /* disable SERR in case the MSI write causes a master abort */
3785 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 3786 if (pci_cmd & PCI_COMMAND_SERR)
3787 pci_write_config_word(adapter->pdev, PCI_COMMAND,
3788 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 3789
3790 err = e1000_test_msi_interrupt(adapter);
3791
36f2407f
DN		 3792 /* re-enable SERR */
3793 if (pci_cmd & PCI_COMMAND_SERR) {
3794 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
3795 pci_cmd |= PCI_COMMAND_SERR;
3796 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
3797 }
f8d59f78 3798
f8d59f78
BA		 3799 return err;
3800}
3801
bc7f75fa
AK		 3802/**
3803 * e1000_open - Called when a network interface is made active
3804 * @netdev: network interface device structure
3805 *
3806 * Returns 0 on success, negative value on failure
3807 *
3808 * The open entry point is called when a network interface is made
3809 * active by the system (IFF_UP). At this point all resources needed
3810 * for transmit and receive operations are allocated, the interrupt
3811 * handler is registered with the OS, the watchdog timer is started,
3812 * and the stack is notified that the interface is ready.
3813 **/
3814static int e1000_open(struct net_device *netdev)
3815{
3816 struct e1000_adapter *adapter = netdev_priv(netdev);
3817 struct e1000_hw *hw = &adapter->hw;
23606cf5 3818 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3819 int err;
3820
3821 /* disallow open during test */
3822 if (test_bit(__E1000_TESTING, &adapter->state))
3823 return -EBUSY;
3824
23606cf5
RW		 3825 pm_runtime_get_sync(&pdev->dev);
3826
9c563d20
JB		 3827 netif_carrier_off(netdev);
3828
bc7f75fa 3829 /* allocate transmit descriptors */
55aa6985 3830 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3831 if (err)
3832 goto err_setup_tx;
3833
3834 /* allocate receive descriptors */
55aa6985 3835 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 3836 if (err)
3837 goto err_setup_rx;
3838
11b08be8
BA		 3839 /*
3840 * If AMT is enabled, let the firmware know that the network
3841 * interface is now open and reset the part to a known state.
3842 */
3843 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 3844 e1000e_get_hw_control(adapter);
11b08be8
BA		 3845 e1000e_reset(adapter);
3846 }
3847
bc7f75fa
AK		 3848 e1000e_power_up_phy(adapter);
3849
3850 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
3851 if ((adapter->hw.mng_cookie.status &
3852 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
3853 e1000_update_mng_vlan(adapter);
3854
79d4e908
BA		 3855 /* DMA latency requirement to workaround jumbo issue */
3856 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014
LT		 3857 pm_qos_add_request(&adapter->netdev->pm_qos_req,
3858 PM_QOS_CPU_DMA_LATENCY,
3859 PM_QOS_DEFAULT_VALUE);
c128ec29 3860
ad68076e
BA		 3861 /*
3862 * before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 3863 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3864 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 3865 * clean_rx handler before we do so.
3866 */
bc7f75fa
AK		 3867 e1000_configure(adapter);
3868
3869 err = e1000_request_irq(adapter);
3870 if (err)
3871 goto err_req_irq;
3872
f8d59f78
BA		 3873 /*
3874 * Work around PCIe errata with MSI interrupts causing some chipsets to
3875 * ignore e1000e MSI messages, which means we need to test our MSI
3876 * interrupt now
3877 */
4662e82b 3878 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 3879 err = e1000_test_msi(adapter);
3880 if (err) {
3881 e_err("Interrupt allocation failed\n");
3882 goto err_req_irq;
3883 }
3884 }
3885
bc7f75fa
AK		 3886 /* From here on the code is the same as e1000e_up() */
3887 clear_bit(__E1000_DOWN, &adapter->state);
3888
3889 napi_enable(&adapter->napi);
3890
3891 e1000_irq_enable(adapter);
3892
09357b00 3893 adapter->tx_hang_recheck = false;
4cb9be7a 3894 netif_start_queue(netdev);
d55b53ff 3895
23606cf5
RW		 3896 adapter->idle_check = true;
3897 pm_runtime_put(&pdev->dev);
3898
bc7f75fa 3899 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 3900 if (adapter->msix_entries)
3901 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3902 else
3903 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 3904
3905 return 0;
3906
3907err_req_irq:
31dbe5b4 3908 e1000e_release_hw_control(adapter);
bc7f75fa 3909 e1000_power_down_phy(adapter);
55aa6985 3910 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3911err_setup_rx:
55aa6985 3912 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 3913err_setup_tx:
3914 e1000e_reset(adapter);
23606cf5 3915 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 3916
3917 return err;
3918}
3919
3920/**
3921 * e1000_close - Disables a network interface
3922 * @netdev: network interface device structure
3923 *
3924 * Returns 0, this is not allowed to fail
3925 *
3926 * The close entry point is called when an interface is de-activated
3927 * by the OS. The hardware is still under the drivers control, but
3928 * needs to be disabled. A global MAC reset is issued to stop the
3929 * hardware, and all transmit and receive resources are freed.
3930 **/
3931static int e1000_close(struct net_device *netdev)
3932{
3933 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 3934 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 3935
3936 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 3937
3938 pm_runtime_get_sync(&pdev->dev);
3939
5f4a780d
BA		 3940 napi_disable(&adapter->napi);
3941
23606cf5
RW		 3942 if (!test_bit(__E1000_DOWN, &adapter->state)) {
3943 e1000e_down(adapter);
3944 e1000_free_irq(adapter);
3945 }
bc7f75fa 3946 e1000_power_down_phy(adapter);
bc7f75fa 3947
55aa6985
BA		 3948 e1000e_free_tx_resources(adapter->tx_ring);
3949 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 3950
ad68076e
BA		 3951 /*
3952 * kill manageability vlan ID if supported, but not if a vlan with
3953 * the same ID is registered on the host OS (let 8021q kill it)
3954 */
86d70e53
JK		 3955 if (adapter->hw.mng_cookie.status &
3956 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
bc7f75fa
AK		 3957 e1000_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3958
ad68076e
BA		 3959 /*
3960 * If AMT is enabled, let the firmware know that the network
3961 * interface is now closed
3962 */
31dbe5b4
BA		 3963 if ((adapter->flags & FLAG_HAS_AMT) &&
3964 !test_bit(__E1000_TESTING, &adapter->state))
3965 e1000e_release_hw_control(adapter);
bc7f75fa 3966
79d4e908 3967 if (adapter->hw.mac.type == e1000_pch2lan)
6ba74014 3968 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 3969
23606cf5
RW		 3970 pm_runtime_put_sync(&pdev->dev);
3971
bc7f75fa
AK		 3972 return 0;
3973}
3974/**
3975 * e1000_set_mac - Change the Ethernet Address of the NIC
3976 * @netdev: network interface device structure
3977 * @p: pointer to an address structure
3978 *
3979 * Returns 0 on success, negative on failure
3980 **/
3981static int e1000_set_mac(struct net_device *netdev, void *p)
3982{
3983 struct e1000_adapter *adapter = netdev_priv(netdev);
3984 struct sockaddr *addr = p;
3985
3986 if (!is_valid_ether_addr(addr->sa_data))
3987 return -EADDRNOTAVAIL;
3988
3989 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3990 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
3991
3992 e1000e_rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
3993
3994 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
3995 /* activate the work around */
3996 e1000e_set_laa_state_82571(&adapter->hw, 1);
3997
ad68076e
BA		 3998 /*
3999 * Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4000 * between the time RAR[0] gets clobbered and the time it
4001 * gets fixed (in e1000_watchdog), the actual LAA is in one
4002 * of the RARs and no incoming packets directed to this port
4003 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4004 * RAR[14]
4005 */
bc7f75fa
AK		 4006 e1000e_rar_set(&adapter->hw,
4007 adapter->hw.mac.addr,
4008 adapter->hw.mac.rar_entry_count - 1);
4009 }
4010
4011 return 0;
4012}
4013
a8f88ff5
JB		 4014/**
4015 * e1000e_update_phy_task - work thread to update phy
4016 * @work: pointer to our work struct
4017 *
4018 * this worker thread exists because we must acquire a
4019 * semaphore to read the phy, which we could msleep while
4020 * waiting for it, and we can't msleep in a timer.
4021 **/
4022static void e1000e_update_phy_task(struct work_struct *work)
4023{
4024 struct e1000_adapter *adapter = container_of(work,
4025 struct e1000_adapter, update_phy_task);
615b32af
JB		 4026
4027 if (test_bit(__E1000_DOWN, &adapter->state))
4028 return;
4029
a8f88ff5
JB		 4030 e1000_get_phy_info(&adapter->hw);
4031}
4032
ad68076e
BA		 4033/*
4034 * Need to wait a few seconds after link up to get diagnostic information from
4035 * the phy
4036 */
bc7f75fa
AK		 4037static void e1000_update_phy_info(unsigned long data)
4038{
4039 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
615b32af
JB		 4040
4041 if (test_bit(__E1000_DOWN, &adapter->state))
4042 return;
4043
a8f88ff5 4044 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4045}
4046
8c7bbb92
BA		 4047/**
4048 * e1000e_update_phy_stats - Update the PHY statistics counters
4049 * @adapter: board private structure
2b6b168d
BA		 4050 *
4051 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4052 **/
4053static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4054{
4055 struct e1000_hw *hw = &adapter->hw;
4056 s32 ret_val;
4057 u16 phy_data;
4058
4059 ret_val = hw->phy.ops.acquire(hw);
4060 if (ret_val)
4061 return;
4062
8c7bbb92
BA		 4063 /*
4064 * A page set is expensive so check if already on desired page.
4065 * If not, set to the page with the PHY status registers.
4066 */
2b6b168d 4067 hw->phy.addr = 1;
8c7bbb92
BA		 4068 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4069 &phy_data);
4070 if (ret_val)
4071 goto release;
2b6b168d
BA		 4072 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4073 ret_val = hw->phy.ops.set_page(hw,
4074 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4075 if (ret_val)
4076 goto release;
4077 }
4078
8c7bbb92 4079 /* Single Collision Count */
2b6b168d
BA		 4080 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4081 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4082 if (!ret_val)
4083 adapter->stats.scc += phy_data;
4084
4085 /* Excessive Collision Count */
2b6b168d
BA		 4086 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4087 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4088 if (!ret_val)
4089 adapter->stats.ecol += phy_data;
4090
4091 /* Multiple Collision Count */
2b6b168d
BA		 4092 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4093 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4094 if (!ret_val)
4095 adapter->stats.mcc += phy_data;
4096
4097 /* Late Collision Count */
2b6b168d
BA		 4098 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4099 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4100 if (!ret_val)
4101 adapter->stats.latecol += phy_data;
4102
4103 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4104 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4105 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4106 if (!ret_val)
4107 hw->mac.collision_delta = phy_data;
4108
4109 /* Defer Count */
2b6b168d
BA		 4110 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4111 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4112 if (!ret_val)
4113 adapter->stats.dc += phy_data;
4114
4115 /* Transmit with no CRS */
2b6b168d
BA		 4116 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4117 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4118 if (!ret_val)
4119 adapter->stats.tncrs += phy_data;
4120
4121release:
4122 hw->phy.ops.release(hw);
4123}
4124
bc7f75fa
AK		 4125/**
4126 * e1000e_update_stats - Update the board statistics counters
4127 * @adapter: board private structure
4128 **/
67fd4fcb 4129static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4130{
7274c20f 4131 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4132 struct e1000_hw *hw = &adapter->hw;
4133 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4134
4135 /*
4136 * Prevent stats update while adapter is being reset, or if the pci
4137 * connection is down.
4138 */
4139 if (adapter->link_speed == 0)
4140 return;
4141 if (pci_channel_offline(pdev))
4142 return;
4143
bc7f75fa
AK		 4144 adapter->stats.crcerrs += er32(CRCERRS);
4145 adapter->stats.gprc += er32(GPRC);
7c25769f
BA		 4146 adapter->stats.gorc += er32(GORCL);
4147 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4148 adapter->stats.bprc += er32(BPRC);
4149 adapter->stats.mprc += er32(MPRC);
4150 adapter->stats.roc += er32(ROC);
4151
bc7f75fa 4152 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4153
4154 /* Half-duplex statistics */
4155 if (adapter->link_duplex == HALF_DUPLEX) {
4156 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4157 e1000e_update_phy_stats(adapter);
4158 } else {
4159 adapter->stats.scc += er32(SCC);
4160 adapter->stats.ecol += er32(ECOL);
4161 adapter->stats.mcc += er32(MCC);
4162 adapter->stats.latecol += er32(LATECOL);
4163 adapter->stats.dc += er32(DC);
4164
4165 hw->mac.collision_delta = er32(COLC);
4166
4167 if ((hw->mac.type != e1000_82574) &&
4168 (hw->mac.type != e1000_82583))
4169 adapter->stats.tncrs += er32(TNCRS);
4170 }
4171 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4172 }
8c7bbb92 4173
bc7f75fa
AK		 4174 adapter->stats.xonrxc += er32(XONRXC);
4175 adapter->stats.xontxc += er32(XONTXC);
4176 adapter->stats.xoffrxc += er32(XOFFRXC);
4177 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4178 adapter->stats.gptc += er32(GPTC);
7c25769f
BA		 4179 adapter->stats.gotc += er32(GOTCL);
4180 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4181 adapter->stats.rnbc += er32(RNBC);
4182 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4183
4184 adapter->stats.mptc += er32(MPTC);
4185 adapter->stats.bptc += er32(BPTC);
4186
4187 /* used for adaptive IFS */
4188
4189 hw->mac.tx_packet_delta = er32(TPT);
4190 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4191
4192 adapter->stats.algnerrc += er32(ALGNERRC);
4193 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4194 adapter->stats.cexterr += er32(CEXTERR);
4195 adapter->stats.tsctc += er32(TSCTC);
4196 adapter->stats.tsctfc += er32(TSCTFC);
4197
bc7f75fa 4198 /* Fill out the OS statistics structure */
7274c20f
AK		 4199 netdev->stats.multicast = adapter->stats.mprc;
4200 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4201
4202 /* Rx Errors */
4203
ad68076e
BA		 4204 /*
4205 * RLEC on some newer hardware can be incorrect so build
4206 * our own version based on RUC and ROC
4207 */
7274c20f 4208 netdev->stats.rx_errors = adapter->stats.rxerrc +
bc7f75fa
AK		 4209 adapter->stats.crcerrs + adapter->stats.algnerrc +
4210 adapter->stats.ruc + adapter->stats.roc +
4211 adapter->stats.cexterr;
7274c20f 4212 netdev->stats.rx_length_errors = adapter->stats.ruc +
bc7f75fa 4213 adapter->stats.roc;
7274c20f
AK		 4214 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4215 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4216 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4217
4218 /* Tx Errors */
7274c20f 4219 netdev->stats.tx_errors = adapter->stats.ecol +
bc7f75fa 4220 adapter->stats.latecol;
7274c20f
AK		 4221 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4222 netdev->stats.tx_window_errors = adapter->stats.latecol;
4223 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4224
4225 /* Tx Dropped needs to be maintained elsewhere */
4226
bc7f75fa
AK		 4227 /* Management Stats */
4228 adapter->stats.mgptc += er32(MGTPTC);
4229 adapter->stats.mgprc += er32(MGTPRC);
4230 adapter->stats.mgpdc += er32(MGTPDC);
bc7f75fa
AK		 4231}
4232
7c25769f
BA		 4233/**
4234 * e1000_phy_read_status - Update the PHY register status snapshot
4235 * @adapter: board private structure
4236 **/
4237static void e1000_phy_read_status(struct e1000_adapter *adapter)
4238{
4239 struct e1000_hw *hw = &adapter->hw;
4240 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f
BA		 4241
4242 if ((er32(STATUS) & E1000_STATUS_LU) &&
4243 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4244 int ret_val;
4245
7c25769f
BA		 4246 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy->bmcr);
4247 ret_val |= e1e_rphy(hw, PHY_STATUS, &phy->bmsr);
4248 ret_val |= e1e_rphy(hw, PHY_AUTONEG_ADV, &phy->advertise);
4249 ret_val |= e1e_rphy(hw, PHY_LP_ABILITY, &phy->lpa);
4250 ret_val |= e1e_rphy(hw, PHY_AUTONEG_EXP, &phy->expansion);
4251 ret_val |= e1e_rphy(hw, PHY_1000T_CTRL, &phy->ctrl1000);
4252 ret_val |= e1e_rphy(hw, PHY_1000T_STATUS, &phy->stat1000);
4253 ret_val |= e1e_rphy(hw, PHY_EXT_STATUS, &phy->estatus);
4254 if (ret_val)
44defeb3 4255 e_warn("Error reading PHY register\n");
7c25769f
BA		 4256 } else {
4257 /*
4258 * Do not read PHY registers if link is not up
4259 * Set values to typical power-on defaults
4260 */
4261 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4262 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4263 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4264 BMSR_ERCAP);
4265 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4266 ADVERTISE_ALL | ADVERTISE_CSMA);
4267 phy->lpa = 0;
4268 phy->expansion = EXPANSION_ENABLENPAGE;
4269 phy->ctrl1000 = ADVERTISE_1000FULL;
4270 phy->stat1000 = 0;
4271 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4272 }
7c25769f
BA		 4273}
4274
bc7f75fa
AK		 4275static void e1000_print_link_info(struct e1000_adapter *adapter)
4276{
bc7f75fa
AK		 4277 struct e1000_hw *hw = &adapter->hw;
4278 u32 ctrl = er32(CTRL);
4279
8f12fe86 4280 /* Link status message must follow this format for user tools */
ef456f85
JK		 4281 printk(KERN_INFO "e1000e: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4282 adapter->netdev->name,
4283 adapter->link_speed,
4284 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4285 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4286 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4287 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4288}
4289
0c6bdb30 4290static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4291{
4292 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4293 bool link_active = false;
318a94d6
JK		 4294 s32 ret_val = 0;
4295
4296 /*
4297 * get_link_status is set on LSC (link status) interrupt or
4298 * Rx sequence error interrupt. get_link_status will stay
4299 * false until the check_for_link establishes link
4300 * for copper adapters ONLY
4301 */
4302 switch (hw->phy.media_type) {
4303 case e1000_media_type_copper:
4304 if (hw->mac.get_link_status) {
4305 ret_val = hw->mac.ops.check_for_link(hw);
4306 link_active = !hw->mac.get_link_status;
4307 } else {
3db1cd5c 4308 link_active = true;
318a94d6
JK		 4309 }
4310 break;
4311 case e1000_media_type_fiber:
4312 ret_val = hw->mac.ops.check_for_link(hw);
4313 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4314 break;
4315 case e1000_media_type_internal_serdes:
4316 ret_val = hw->mac.ops.check_for_link(hw);
4317 link_active = adapter->hw.mac.serdes_has_link;
4318 break;
4319 default:
4320 case e1000_media_type_unknown:
4321 break;
4322 }
4323
4324 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4325 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4326 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4327 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4328 }
4329
4330 return link_active;
4331}
4332
4333static void e1000e_enable_receives(struct e1000_adapter *adapter)
4334{
4335 /* make sure the receive unit is started */
4336 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
4337 (adapter->flags & FLAG_RX_RESTART_NOW)) {
4338 struct e1000_hw *hw = &adapter->hw;
4339 u32 rctl = er32(RCTL);
4340 ew32(RCTL, rctl | E1000_RCTL_EN);
4341 adapter->flags &= ~FLAG_RX_RESTART_NOW;
4342 }
4343}
4344
ff10e13c
CW		 4345static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4346{
4347 struct e1000_hw *hw = &adapter->hw;
4348
4349 /*
4350 * With 82574 controllers, PHY needs to be checked periodically
4351 * for hung state and reset, if two calls return true
4352 */
4353 if (e1000_check_phy_82574(hw))
4354 adapter->phy_hang_count++;
4355 else
4356 adapter->phy_hang_count = 0;
4357
4358 if (adapter->phy_hang_count > 1) {
4359 adapter->phy_hang_count = 0;
4360 schedule_work(&adapter->reset_task);
4361 }
4362}
4363
bc7f75fa
AK		 4364/**
4365 * e1000_watchdog - Timer Call-back
4366 * @data: pointer to adapter cast into an unsigned long
4367 **/
4368static void e1000_watchdog(unsigned long data)
4369{
4370 struct e1000_adapter *adapter = (struct e1000_adapter *) data;
4371
4372 /* Do the rest outside of interrupt context */
4373 schedule_work(&adapter->watchdog_task);
4374
4375 /* TODO: make this use queue_delayed_work() */
4376}
4377
4378static void e1000_watchdog_task(struct work_struct *work)
4379{
4380 struct e1000_adapter *adapter = container_of(work,
4381 struct e1000_adapter, watchdog_task);
bc7f75fa
AK		 4382 struct net_device *netdev = adapter->netdev;
4383 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4384 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4385 struct e1000_ring *tx_ring = adapter->tx_ring;
4386 struct e1000_hw *hw = &adapter->hw;
4387 u32 link, tctl;
bc7f75fa 4388
615b32af
JB		 4389 if (test_bit(__E1000_DOWN, &adapter->state))
4390 return;
4391
b405e8df 4392 link = e1000e_has_link(adapter);
318a94d6 4393 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4394 /* Cancel scheduled suspend requests. */
4395 pm_runtime_resume(netdev->dev.parent);
4396
318a94d6 4397 e1000e_enable_receives(adapter);
bc7f75fa 4398 goto link_up;
bc7f75fa
AK		 4399 }
4400
4401 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4402 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4403 e1000_update_mng_vlan(adapter);
4404
bc7f75fa
AK		 4405 if (link) {
4406 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4407 bool txb2b = true;
23606cf5
RW		 4408
4409 /* Cancel scheduled suspend requests. */
4410 pm_runtime_resume(netdev->dev.parent);
4411
318a94d6 4412 /* update snapshot of PHY registers on LSC */
7c25769f 4413 e1000_phy_read_status(adapter);
bc7f75fa
AK		 4414 mac->ops.get_link_up_info(&adapter->hw,
4415 &adapter->link_speed,
4416 &adapter->link_duplex);
4417 e1000_print_link_info(adapter);
f4187b56
BA		 4418 /*
4419 * On supported PHYs, check for duplex mismatch only
4420 * if link has autonegotiated at 10/100 half
4421 */
4422 if ((hw->phy.type == e1000_phy_igp_3 ||
4423 hw->phy.type == e1000_phy_bm) &&
4424 (hw->mac.autoneg == true) &&
4425 (adapter->link_speed == SPEED_10 ||
4426 adapter->link_speed == SPEED_100) &&
4427 (adapter->link_duplex == HALF_DUPLEX)) {
4428 u16 autoneg_exp;
4429
4430 e1e_rphy(hw, PHY_AUTONEG_EXP, &autoneg_exp);
4431
4432 if (!(autoneg_exp & NWAY_ER_LP_NWAY_CAPS))
ef456f85 4433 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4434 }
4435
f49c57e1 4436 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4437 adapter->tx_timeout_factor = 1;
4438 switch (adapter->link_speed) {
4439 case SPEED_10:
3db1cd5c 4440 txb2b = false;
10f1b492 4441 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4442 break;
4443 case SPEED_100:
3db1cd5c 4444 txb2b = false;
4c86e0b9 4445 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4446 break;
4447 }
4448
ad68076e
BA		 4449 /*
4450 * workaround: re-program speed mode bit after
4451 * link-up event
4452 */
bc7f75fa
AK		 4453 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4454 !txb2b) {
4455 u32 tarc0;
e9ec2c0f 4456 tarc0 = er32(TARC(0));
bc7f75fa 4457 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4458 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4459 }
4460
ad68076e
BA		 4461 /*
4462 * disable TSO for pcie and 10/100 speeds, to avoid
4463 * some hardware issues
4464 */
bc7f75fa
AK		 4465 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4466 switch (adapter->link_speed) {
4467 case SPEED_10:
4468 case SPEED_100:
44defeb3 4469 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4470 netdev->features &= ~NETIF_F_TSO;
4471 netdev->features &= ~NETIF_F_TSO6;
4472 break;
4473 case SPEED_1000:
4474 netdev->features |= NETIF_F_TSO;
4475 netdev->features |= NETIF_F_TSO6;
4476 break;
4477 default:
4478 /* oops */
4479 break;
4480 }
4481 }
4482
ad68076e
BA		 4483 /*
4484 * enable transmits in the hardware, need to do this
4485 * after setting TARC(0)
4486 */
bc7f75fa
AK		 4487 tctl = er32(TCTL);
4488 tctl |= E1000_TCTL_EN;
4489 ew32(TCTL, tctl);
4490
75eb0fad
BA		 4491 /*
4492 * Perform any post-link-up configuration before
4493 * reporting link up.
4494 */
4495 if (phy->ops.cfg_on_link_up)
4496 phy->ops.cfg_on_link_up(hw);
4497
bc7f75fa 4498 netif_carrier_on(netdev);
bc7f75fa
AK		 4499
4500 if (!test_bit(__E1000_DOWN, &adapter->state))
4501 mod_timer(&adapter->phy_info_timer,
4502 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4503 }
4504 } else {
4505 if (netif_carrier_ok(netdev)) {
4506 adapter->link_speed = 0;
4507 adapter->link_duplex = 0;
8f12fe86
BA		 4508 /* Link status message must follow this format */
4509 printk(KERN_INFO "e1000e: %s NIC Link is Down\n",
4510 adapter->netdev->name);
bc7f75fa 4511 netif_carrier_off(netdev);
bc7f75fa
AK		 4512 if (!test_bit(__E1000_DOWN, &adapter->state))
4513 mod_timer(&adapter->phy_info_timer,
4514 round_jiffies(jiffies + 2 * HZ));
4515
4516 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
4517 schedule_work(&adapter->reset_task);
23606cf5
RW		 4518 else
4519 pm_schedule_suspend(netdev->dev.parent,
4520 LINK_TIMEOUT);
bc7f75fa
AK		 4521 }
4522 }
4523
4524link_up:
67fd4fcb 4525 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4526 e1000e_update_stats(adapter);
4527
4528 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4529 adapter->tpt_old = adapter->stats.tpt;
4530 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4531 adapter->colc_old = adapter->stats.colc;
4532
7c25769f
BA		 4533 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
4534 adapter->gorc_old = adapter->stats.gorc;
4535 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
4536 adapter->gotc_old = adapter->stats.gotc;
2084b114 4537 spin_unlock(&adapter->stats64_lock);
bc7f75fa
AK		 4538
4539 e1000e_update_adaptive(&adapter->hw);
4540
90da0669
BA		 4541 if (!netif_carrier_ok(netdev) &&
4542 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count)) {
4543 /*
4544 * We've lost link, so the controller stops DMA,
4545 * but we've got queued Tx work that's never going
4546 * to get done, so reset controller to flush Tx.
4547 * (Do the reset outside of interrupt context).
4548 */
90da0669
BA		 4549 schedule_work(&adapter->reset_task);
4550 /* return immediately since reset is imminent */
4551 return;
bc7f75fa
AK		 4552 }
4553
eab2abf5
JB		 4554 /* Simple mode for Interrupt Throttle Rate (ITR) */
4555 if (adapter->itr_setting == 4) {
4556 /*
4557 * Symmetric Tx/Rx gets a reduced ITR=2000;
4558 * Total asymmetrical Tx or Rx gets ITR=8000;
4559 * everyone else is between 2000-8000.
4560 */
4561 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
4562 u32 dif = (adapter->gotc > adapter->gorc ?
4563 adapter->gotc - adapter->gorc :
4564 adapter->gorc - adapter->gotc) / 10000;
4565 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
4566
4567 ew32(ITR, 1000000000 / (itr * 256));
4568 }
4569
ad68076e 4570 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 4571 if (adapter->msix_entries)
4572 ew32(ICS, adapter->rx_ring->ims_val);
4573 else
4574 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 4575
713b3c9e
JB		 4576 /* flush pending descriptors to memory before detecting Tx hang */
4577 e1000e_flush_descriptors(adapter);
4578
bc7f75fa 4579 /* Force detection of hung controller every watchdog period */
3db1cd5c 4580 adapter->detect_tx_hung = true;
bc7f75fa 4581
ad68076e
BA		 4582 /*
4583 * With 82571 controllers, LAA may be overwritten due to controller
4584 * reset from the other port. Set the appropriate LAA in RAR[0]
4585 */
bc7f75fa
AK		 4586 if (e1000e_get_laa_state_82571(hw))
4587 e1000e_rar_set(hw, adapter->hw.mac.addr, 0);
4588
ff10e13c
CW		 4589 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
4590 e1000e_check_82574_phy_workaround(adapter);
4591
bc7f75fa
AK		 4592 /* Reset the timer */
4593 if (!test_bit(__E1000_DOWN, &adapter->state))
4594 mod_timer(&adapter->watchdog_timer,
4595 round_jiffies(jiffies + 2 * HZ));
4596}
4597
4598#define E1000_TX_FLAGS_CSUM 0x00000001
4599#define E1000_TX_FLAGS_VLAN 0x00000002
4600#define E1000_TX_FLAGS_TSO 0x00000004
4601#define E1000_TX_FLAGS_IPV4 0x00000008
4602#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
4603#define E1000_TX_FLAGS_VLAN_SHIFT 16
4604
55aa6985 4605static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4606{
bc7f75fa
AK		 4607 struct e1000_context_desc *context_desc;
4608 struct e1000_buffer *buffer_info;
4609 unsigned int i;
4610 u32 cmd_length = 0;
4611 u16 ipcse = 0, tucse, mss;
4612 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 4613
3d5e33c9
BA		 4614 if (!skb_is_gso(skb))
4615 return 0;
bc7f75fa 4616
3d5e33c9 4617 if (skb_header_cloned(skb)) {
90da0669
BA		 4618 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4619
3d5e33c9
BA		 4620 if (err)
4621 return err;
bc7f75fa
AK		 4622 }
4623
3d5e33c9
BA		 4624 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
4625 mss = skb_shinfo(skb)->gso_size;
4626 if (skb->protocol == htons(ETH_P_IP)) {
4627 struct iphdr *iph = ip_hdr(skb);
4628 iph->tot_len = 0;
4629 iph->check = 0;
4630 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
4631 0, IPPROTO_TCP, 0);
4632 cmd_length = E1000_TXD_CMD_IP;
4633 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 4634 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 4635 ipv6_hdr(skb)->payload_len = 0;
4636 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4637 &ipv6_hdr(skb)->daddr,
4638 0, IPPROTO_TCP, 0);
4639 ipcse = 0;
4640 }
4641 ipcss = skb_network_offset(skb);
4642 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
4643 tucss = skb_transport_offset(skb);
4644 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
4645 tucse = 0;
4646
4647 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
4648 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
4649
4650 i = tx_ring->next_to_use;
4651 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4652 buffer_info = &tx_ring->buffer_info[i];
4653
4654 context_desc->lower_setup.ip_fields.ipcss = ipcss;
4655 context_desc->lower_setup.ip_fields.ipcso = ipcso;
4656 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
4657 context_desc->upper_setup.tcp_fields.tucss = tucss;
4658 context_desc->upper_setup.tcp_fields.tucso = tucso;
4659 context_desc->upper_setup.tcp_fields.tucse = cpu_to_le16(tucse);
4660 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
4661 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
4662 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
4663
4664 buffer_info->time_stamp = jiffies;
4665 buffer_info->next_to_watch = i;
4666
4667 i++;
4668 if (i == tx_ring->count)
4669 i = 0;
4670 tx_ring->next_to_use = i;
4671
4672 return 1;
bc7f75fa
AK		 4673}
4674
55aa6985 4675static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 4676{
55aa6985 4677 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4678 struct e1000_context_desc *context_desc;
4679 struct e1000_buffer *buffer_info;
4680 unsigned int i;
4681 u8 css;
af807c82 4682 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 4683 __be16 protocol;
bc7f75fa 4684
af807c82
DG		 4685 if (skb->ip_summed != CHECKSUM_PARTIAL)
4686 return 0;
bc7f75fa 4687
5f66f208
AJ		 4688 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4689 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
4690 else
4691 protocol = skb->protocol;
4692
3f518390 4693 switch (protocol) {
09640e63 4694 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 4695 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4696 cmd_len |= E1000_TXD_CMD_TCP;
4697 break;
09640e63 4698 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 4699 /* XXX not handling all IPV6 headers */
4700 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4701 cmd_len |= E1000_TXD_CMD_TCP;
4702 break;
4703 default:
4704 if (unlikely(net_ratelimit()))
5f66f208
AJ		 4705 e_warn("checksum_partial proto=%x!\n",
4706 be16_to_cpu(protocol));
af807c82 4707 break;
bc7f75fa
AK		 4708 }
4709
0d0b1672 4710 css = skb_checksum_start_offset(skb);
af807c82
DG		 4711
4712 i = tx_ring->next_to_use;
4713 buffer_info = &tx_ring->buffer_info[i];
4714 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
4715
4716 context_desc->lower_setup.ip_config = 0;
4717 context_desc->upper_setup.tcp_fields.tucss = css;
4718 context_desc->upper_setup.tcp_fields.tucso =
4719 css + skb->csum_offset;
4720 context_desc->upper_setup.tcp_fields.tucse = 0;
4721 context_desc->tcp_seg_setup.data = 0;
4722 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
4723
4724 buffer_info->time_stamp = jiffies;
4725 buffer_info->next_to_watch = i;
4726
4727 i++;
4728 if (i == tx_ring->count)
4729 i = 0;
4730 tx_ring->next_to_use = i;
4731
4732 return 1;
bc7f75fa
AK		 4733}
4734
4735#define E1000_MAX_PER_TXD 8192
4736#define E1000_MAX_TXD_PWR 12
4737
55aa6985
BA		 4738static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
4739 unsigned int first, unsigned int max_per_txd,
4740 unsigned int nr_frags, unsigned int mss)
bc7f75fa 4741{
55aa6985 4742 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 4743 struct pci_dev *pdev = adapter->pdev;
1b7719c4 4744 struct e1000_buffer *buffer_info;
8ddc951c 4745 unsigned int len = skb_headlen(skb);
03b1320d 4746 unsigned int offset = 0, size, count = 0, i;
9ed318d5 4747 unsigned int f, bytecount, segs;
bc7f75fa
AK		 4748
4749 i = tx_ring->next_to_use;
4750
4751 while (len) {
1b7719c4 4752 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 4753 size = min(len, max_per_txd);
4754
bc7f75fa 4755 buffer_info->length = size;
bc7f75fa 4756 buffer_info->time_stamp = jiffies;
bc7f75fa 4757 buffer_info->next_to_watch = i;
0be3f55f
NN		 4758 buffer_info->dma = dma_map_single(&pdev->dev,
4759 skb->data + offset,
af667a29 4760 size, DMA_TO_DEVICE);
03b1320d 4761 buffer_info->mapped_as_page = false;
0be3f55f 4762 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4763 goto dma_error;
bc7f75fa
AK		 4764
4765 len -= size;
4766 offset += size;
03b1320d 4767 count++;
1b7719c4
AD		 4768
4769 if (len) {
4770 i++;
4771 if (i == tx_ring->count)
4772 i = 0;
4773 }
bc7f75fa
AK		 4774 }
4775
4776 for (f = 0; f < nr_frags; f++) {
9e903e08 4777 const struct skb_frag_struct *frag;
bc7f75fa
AK		 4778
4779 frag = &skb_shinfo(skb)->frags[f];
9e903e08 4780 len = skb_frag_size(frag);
877749bf 4781 offset = 0;
bc7f75fa
AK		 4782
4783 while (len) {
1b7719c4
AD		 4784 i++;
4785 if (i == tx_ring->count)
4786 i = 0;
4787
bc7f75fa
AK		 4788 buffer_info = &tx_ring->buffer_info[i];
4789 size = min(len, max_per_txd);
bc7f75fa
AK		 4790
4791 buffer_info->length = size;
4792 buffer_info->time_stamp = jiffies;
bc7f75fa 4793 buffer_info->next_to_watch = i;
877749bf
IC		 4794 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
4795 offset, size, DMA_TO_DEVICE);
03b1320d 4796 buffer_info->mapped_as_page = true;
0be3f55f 4797 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 4798 goto dma_error;
bc7f75fa
AK		 4799
4800 len -= size;
4801 offset += size;
4802 count++;
bc7f75fa
AK		 4803 }
4804 }
4805
af667a29 4806 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 4807 /* multiply data chunks by size of headers */
4808 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
4809
bc7f75fa 4810 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 4811 tx_ring->buffer_info[i].segs = segs;
4812 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 4813 tx_ring->buffer_info[first].next_to_watch = i;
4814
4815 return count;
03b1320d
AD		 4816
4817dma_error:
af667a29 4818 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 4819 buffer_info->dma = 0;
c1fa347f 4820 if (count)
03b1320d 4821 count--;
c1fa347f
RK		 4822
4823 while (count--) {
af667a29 4824 if (i == 0)
03b1320d 4825 i += tx_ring->count;
c1fa347f 4826 i--;
03b1320d 4827 buffer_info = &tx_ring->buffer_info[i];
55aa6985 4828 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 4829 }
4830
4831 return 0;
bc7f75fa
AK		 4832}
4833
55aa6985 4834static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 4835{
55aa6985 4836 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 4837 struct e1000_tx_desc *tx_desc = NULL;
4838 struct e1000_buffer *buffer_info;
4839 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
4840 unsigned int i;
4841
4842 if (tx_flags & E1000_TX_FLAGS_TSO) {
4843 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
4844 E1000_TXD_CMD_TSE;
4845 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4846
4847 if (tx_flags & E1000_TX_FLAGS_IPV4)
4848 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
4849 }
4850
4851 if (tx_flags & E1000_TX_FLAGS_CSUM) {
4852 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
4853 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
4854 }
4855
4856 if (tx_flags & E1000_TX_FLAGS_VLAN) {
4857 txd_lower |= E1000_TXD_CMD_VLE;
4858 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
4859 }
4860
4861 i = tx_ring->next_to_use;
4862
36b973df 4863 do {
bc7f75fa
AK		 4864 buffer_info = &tx_ring->buffer_info[i];
4865 tx_desc = E1000_TX_DESC(*tx_ring, i);
4866 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
4867 tx_desc->lower.data =
4868 cpu_to_le32(txd_lower | buffer_info->length);
4869 tx_desc->upper.data = cpu_to_le32(txd_upper);
4870
4871 i++;
4872 if (i == tx_ring->count)
4873 i = 0;
36b973df 4874 } while (--count > 0);
bc7f75fa
AK		 4875
4876 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
4877
ad68076e
BA		 4878 /*
4879 * Force memory writes to complete before letting h/w
bc7f75fa
AK		 4880 * know there are new descriptors to fetch. (Only
4881 * applicable for weak-ordered memory model archs,
ad68076e
BA		 4882 * such as IA-64).
4883 */
bc7f75fa
AK		 4884 wmb();
4885
4886 tx_ring->next_to_use = i;
c6e7f51e
BA		 4887
4888 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 4889 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 4890 else
c5083cf6 4891 writel(i, tx_ring->tail);
c6e7f51e 4892
ad68076e
BA		 4893 /*
4894 * we need this if more than one processor can write to our tail
4895 * at a time, it synchronizes IO on IA64/Altix systems
4896 */
bc7f75fa
AK		 4897 mmiowb();
4898}
4899
4900#define MINIMUM_DHCP_PACKET_SIZE 282
4901static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
4902 struct sk_buff *skb)
4903{
4904 struct e1000_hw *hw = &adapter->hw;
4905 u16 length, offset;
4906
4907 if (vlan_tx_tag_present(skb)) {
8e95a202
JP		 4908 if (!((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
4909 (adapter->hw.mng_cookie.status &
bc7f75fa
AK		 4910 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
4911 return 0;
4912 }
4913
4914 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
4915 return 0;
4916
4917 if (((struct ethhdr *) skb->data)->h_proto != htons(ETH_P_IP))
4918 return 0;
4919
4920 {
4921 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data+14);
4922 struct udphdr *udp;
4923
4924 if (ip->protocol != IPPROTO_UDP)
4925 return 0;
4926
4927 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
4928 if (ntohs(udp->dest) != 67)
4929 return 0;
4930
4931 offset = (u8 *)udp + 8 - skb->data;
4932 length = skb->len - offset;
4933 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
4934 }
4935
4936 return 0;
4937}
4938
55aa6985 4939static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4940{
55aa6985 4941 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 4942
55aa6985 4943 netif_stop_queue(adapter->netdev);
ad68076e
BA		 4944 /*
4945 * Herbert's original patch had:
bc7f75fa 4946 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 4947 * but since that doesn't exist yet, just open code it.
4948 */
bc7f75fa
AK		 4949 smp_mb();
4950
ad68076e
BA		 4951 /*
4952 * We need to check again in a case another CPU has just
4953 * made room available.
4954 */
55aa6985 4955 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 4956 return -EBUSY;
4957
4958 /* A reprieve! */
55aa6985 4959 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 4960 ++adapter->restart_queue;
4961 return 0;
4962}
4963
55aa6985 4964static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 4965{
55aa6985 4966 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 4967 return 0;
55aa6985 4968 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 4969}
4970
4971#define TXD_USE_COUNT(S, X) (((S) >> (X)) + 1 )
3b29a56d
SH		 4972static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
4973 struct net_device *netdev)
bc7f75fa
AK		 4974{
4975 struct e1000_adapter *adapter = netdev_priv(netdev);
4976 struct e1000_ring *tx_ring = adapter->tx_ring;
4977 unsigned int first;
4978 unsigned int max_per_txd = E1000_MAX_PER_TXD;
4979 unsigned int max_txd_pwr = E1000_MAX_TXD_PWR;
4980 unsigned int tx_flags = 0;
e743d313 4981 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 4982 unsigned int nr_frags;
4983 unsigned int mss;
bc7f75fa
AK		 4984 int count = 0;
4985 int tso;
4986 unsigned int f;
bc7f75fa
AK		 4987
4988 if (test_bit(__E1000_DOWN, &adapter->state)) {
4989 dev_kfree_skb_any(skb);
4990 return NETDEV_TX_OK;
4991 }
4992
4993 if (skb->len <= 0) {
4994 dev_kfree_skb_any(skb);
4995 return NETDEV_TX_OK;
4996 }
4997
4998 mss = skb_shinfo(skb)->gso_size;
ad68076e
BA		 4999 /*
5000 * The controller does a simple calculation to
bc7f75fa
AK		 5001 * make sure there is enough room in the FIFO before
5002 * initiating the DMA for each buffer. The calc is:
5003 * 4 = ceil(buffer len/mss). To make sure we don't
5004 * overrun the FIFO, adjust the max buffer len if mss
ad68076e
BA		 5005 * drops.
5006 */
bc7f75fa
AK		 5007 if (mss) {
5008 u8 hdr_len;
5009 max_per_txd = min(mss << 2, max_per_txd);
5010 max_txd_pwr = fls(max_per_txd) - 1;
5011
ad68076e
BA		 5012 /*
5013 * TSO Workaround for 82571/2/3 Controllers -- if skb->data
5014 * points to just header, pull a few bytes of payload from
5015 * frags into skb->data
5016 */
bc7f75fa 5017 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
ad68076e
BA		 5018 /*
5019 * we do this workaround for ES2LAN, but it is un-necessary,
5020 * avoiding it could save a lot of cycles
5021 */
4e6c709c 5022 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5023 unsigned int pull_size;
5024
5025 pull_size = min((unsigned int)4, skb->data_len);
5026 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5027 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5028 dev_kfree_skb_any(skb);
5029 return NETDEV_TX_OK;
5030 }
e743d313 5031 len = skb_headlen(skb);
bc7f75fa
AK		 5032 }
5033 }
5034
5035 /* reserve a descriptor for the offload context */
5036 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5037 count++;
5038 count++;
5039
5040 count += TXD_USE_COUNT(len, max_txd_pwr);
5041
5042 nr_frags = skb_shinfo(skb)->nr_frags;
5043 for (f = 0; f < nr_frags; f++)
9e903e08 5044 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->frags[f]),
bc7f75fa
AK		 5045 max_txd_pwr);
5046
5047 if (adapter->hw.mac.tx_pkt_filtering)
5048 e1000_transfer_dhcp_info(adapter, skb);
5049
ad68076e
BA		 5050 /*
5051 * need: count + 2 desc gap to keep tail from touching
5052 * head, otherwise try next time
5053 */
55aa6985 5054 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5055 return NETDEV_TX_BUSY;
bc7f75fa 5056
eab6d18d 5057 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5058 tx_flags |= E1000_TX_FLAGS_VLAN;
5059 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5060 }
5061
5062 first = tx_ring->next_to_use;
5063
55aa6985 5064 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5065 if (tso < 0) {
5066 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5067 return NETDEV_TX_OK;
5068 }
5069
5070 if (tso)
5071 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5072 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5073 tx_flags |= E1000_TX_FLAGS_CSUM;
5074
ad68076e
BA		 5075 /*
5076 * Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5077 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5078 * no longer assume, we must.
5079 */
bc7f75fa
AK		 5080 if (skb->protocol == htons(ETH_P_IP))
5081 tx_flags |= E1000_TX_FLAGS_IPV4;
5082
25985edc 5083 /* if count is 0 then mapping error has occurred */
55aa6985 5084 count = e1000_tx_map(tx_ring, skb, first, max_per_txd, nr_frags, mss);
1b7719c4 5085 if (count) {
3f0cfa3b 5086 netdev_sent_queue(netdev, skb->len);
55aa6985 5087 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5088 /* Make sure there is space in the ring for the next send. */
55aa6985 5089 e1000_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 2);
1b7719c4
AD		 5090
5091 } else {
bc7f75fa 5092 dev_kfree_skb_any(skb);
1b7719c4
AD		 5093 tx_ring->buffer_info[first].time_stamp = 0;
5094 tx_ring->next_to_use = first;
bc7f75fa
AK		 5095 }
5096
bc7f75fa
AK		 5097 return NETDEV_TX_OK;
5098}
5099
5100/**
5101 * e1000_tx_timeout - Respond to a Tx Hang
5102 * @netdev: network interface device structure
5103 **/
5104static void e1000_tx_timeout(struct net_device *netdev)
5105{
5106 struct e1000_adapter *adapter = netdev_priv(netdev);
5107
5108 /* Do the reset outside of interrupt context */
5109 adapter->tx_timeout_count++;
5110 schedule_work(&adapter->reset_task);
5111}
5112
5113static void e1000_reset_task(struct work_struct *work)
5114{
5115 struct e1000_adapter *adapter;
5116 adapter = container_of(work, struct e1000_adapter, reset_task);
5117
615b32af
JB		 5118 /* don't run the task if already down */
5119 if (test_bit(__E1000_DOWN, &adapter->state))
5120 return;
5121
affa9dfb
CW		 5122 if (!((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
5123 (adapter->flags & FLAG_RX_RESTART_NOW))) {
5124 e1000e_dump(adapter);
5125 e_err("Reset adapter\n");
5126 }
bc7f75fa
AK		 5127 e1000e_reinit_locked(adapter);
5128}
5129
5130/**
67fd4fcb 5131 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5132 * @netdev: network interface device structure
67fd4fcb 5133 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5134 *
5135 * Returns the address of the device statistics structure.
bc7f75fa 5136 **/
67fd4fcb
JK		 5137struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
5138 struct rtnl_link_stats64 *stats)
bc7f75fa 5139{
67fd4fcb
JK		 5140 struct e1000_adapter *adapter = netdev_priv(netdev);
5141
5142 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5143 spin_lock(&adapter->stats64_lock);
5144 e1000e_update_stats(adapter);
5145 /* Fill out the OS statistics structure */
5146 stats->rx_bytes = adapter->stats.gorc;
5147 stats->rx_packets = adapter->stats.gprc;
5148 stats->tx_bytes = adapter->stats.gotc;
5149 stats->tx_packets = adapter->stats.gptc;
5150 stats->multicast = adapter->stats.mprc;
5151 stats->collisions = adapter->stats.colc;
5152
5153 /* Rx Errors */
5154
5155 /*
5156 * RLEC on some newer hardware can be incorrect so build
5157 * our own version based on RUC and ROC
5158 */
5159 stats->rx_errors = adapter->stats.rxerrc +
5160 adapter->stats.crcerrs + adapter->stats.algnerrc +
5161 adapter->stats.ruc + adapter->stats.roc +
5162 adapter->stats.cexterr;
5163 stats->rx_length_errors = adapter->stats.ruc +
5164 adapter->stats.roc;
5165 stats->rx_crc_errors = adapter->stats.crcerrs;
5166 stats->rx_frame_errors = adapter->stats.algnerrc;
5167 stats->rx_missed_errors = adapter->stats.mpc;
5168
5169 /* Tx Errors */
5170 stats->tx_errors = adapter->stats.ecol +
5171 adapter->stats.latecol;
5172 stats->tx_aborted_errors = adapter->stats.ecol;
5173 stats->tx_window_errors = adapter->stats.latecol;
5174 stats->tx_carrier_errors = adapter->stats.tncrs;
5175
5176 /* Tx Dropped needs to be maintained elsewhere */
5177
5178 spin_unlock(&adapter->stats64_lock);
5179 return stats;
bc7f75fa
AK		 5180}
5181
5182/**
5183 * e1000_change_mtu - Change the Maximum Transfer Unit
5184 * @netdev: network interface device structure
5185 * @new_mtu: new value for maximum frame size
5186 *
5187 * Returns 0 on success, negative on failure
5188 **/
5189static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5190{
5191 struct e1000_adapter *adapter = netdev_priv(netdev);
5192 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5193
2adc55c9 5194 /* Jumbo frame support */
70495a50
BA		 5195 if (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) {
5196 if (!(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5197 e_err("Jumbo Frames not supported.\n");
5198 return -EINVAL;
5199 }
5200
5201 /*
5202 * IP payload checksum (enabled with jumbos/packet-split when
5203 * Rx checksum is enabled) and generation of RSS hash is
5204 * mutually exclusive in the hardware.
5205 */
5206 if ((netdev->features & NETIF_F_RXCSUM) &&
5207 (netdev->features & NETIF_F_RXHASH)) {
5208 e_err("Jumbo frames cannot be enabled when both receive checksum offload and receive hashing are enabled. Disable one of the receive offload features before enabling jumbos.\n");
5209 return -EINVAL;
5210 }
bc7f75fa
AK		 5211 }
5212
2adc55c9
BA		 5213 /* Supported frame sizes */
5214 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5215 (max_frame > adapter->max_hw_frame_size)) {
5216 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5217 return -EINVAL;
5218 }
5219
a1ce6473
BA		 5220 /* Jumbo frame workaround on 82579 requires CRC be stripped */
5221 if ((adapter->hw.mac.type == e1000_pch2lan) &&
5222 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5223 (new_mtu > ETH_DATA_LEN)) {
ef456f85 5224 e_err("Jumbo Frames not supported on 82579 when CRC stripping is disabled.\n");
a1ce6473
BA		 5225 return -EINVAL;
5226 }
5227
6f461f6c
BA		 5228 /* 82573 Errata 17 */
5229 if (((adapter->hw.mac.type == e1000_82573) ||
5230 (adapter->hw.mac.type == e1000_82574)) &&
5231 (max_frame > ETH_FRAME_LEN + ETH_FCS_LEN)) {
5232 adapter->flags2 |= FLAG2_DISABLE_ASPM_L1;
5233 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L1);
5234 }
5235
bc7f75fa 5236 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5237 usleep_range(1000, 2000);
610c9928 5238 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5239 adapter->max_frame_size = max_frame;
610c9928
BA		 5240 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5241 netdev->mtu = new_mtu;
bc7f75fa
AK		 5242 if (netif_running(netdev))
5243 e1000e_down(adapter);
5244
ad68076e
BA		 5245 /*
5246 * NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5247 * means we reserve 2 more, this pushes us to allocate from the next
5248 * larger slab size.
ad68076e 5249 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5250 * However with the new *_jumbo_rx* routines, jumbo receives will use
5251 * fragmented skbs
ad68076e 5252 */
bc7f75fa 5253
9926146b 5254 if (max_frame <= 2048)
bc7f75fa
AK		 5255 adapter->rx_buffer_len = 2048;
5256 else
5257 adapter->rx_buffer_len = 4096;
5258
5259 /* adjust allocation if LPE protects us, and we aren't using SBP */
5260 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
5261 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
5262 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
ad68076e 5263 + ETH_FCS_LEN;
bc7f75fa 5264
bc7f75fa
AK		 5265 if (netif_running(netdev))
5266 e1000e_up(adapter);
5267 else
5268 e1000e_reset(adapter);
5269
5270 clear_bit(__E1000_RESETTING, &adapter->state);
5271
5272 return 0;
5273}
5274
5275static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5276 int cmd)
5277{
5278 struct e1000_adapter *adapter = netdev_priv(netdev);
5279 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5280
318a94d6 5281 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5282 return -EOPNOTSUPP;
5283
5284 switch (cmd) {
5285 case SIOCGMIIPHY:
5286 data->phy_id = adapter->hw.phy.addr;
5287 break;
5288 case SIOCGMIIREG:
b16a002e
BA		 5289 e1000_phy_read_status(adapter);
5290
7c25769f
BA		 5291 switch (data->reg_num & 0x1F) {
5292 case MII_BMCR:
5293 data->val_out = adapter->phy_regs.bmcr;
5294 break;
5295 case MII_BMSR:
5296 data->val_out = adapter->phy_regs.bmsr;
5297 break;
5298 case MII_PHYSID1:
5299 data->val_out = (adapter->hw.phy.id >> 16);
5300 break;
5301 case MII_PHYSID2:
5302 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5303 break;
5304 case MII_ADVERTISE:
5305 data->val_out = adapter->phy_regs.advertise;
5306 break;
5307 case MII_LPA:
5308 data->val_out = adapter->phy_regs.lpa;
5309 break;
5310 case MII_EXPANSION:
5311 data->val_out = adapter->phy_regs.expansion;
5312 break;
5313 case MII_CTRL1000:
5314 data->val_out = adapter->phy_regs.ctrl1000;
5315 break;
5316 case MII_STAT1000:
5317 data->val_out = adapter->phy_regs.stat1000;
5318 break;
5319 case MII_ESTATUS:
5320 data->val_out = adapter->phy_regs.estatus;
5321 break;
5322 default:
bc7f75fa
AK		 5323 return -EIO;
5324 }
bc7f75fa
AK		 5325 break;
5326 case SIOCSMIIREG:
5327 default:
5328 return -EOPNOTSUPP;
5329 }
5330 return 0;
5331}
5332
5333static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5334{
5335 switch (cmd) {
5336 case SIOCGMIIPHY:
5337 case SIOCGMIIREG:
5338 case SIOCSMIIREG:
5339 return e1000_mii_ioctl(netdev, ifr, cmd);
5340 default:
5341 return -EOPNOTSUPP;
5342 }
5343}
5344
a4f58f54
BA		 5345static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5346{
5347 struct e1000_hw *hw = &adapter->hw;
5348 u32 i, mac_reg;
2b6b168d 5349 u16 phy_reg, wuc_enable;
a4f58f54
BA		 5350 int retval = 0;
5351
5352 /* copy MAC RARs to PHY RARs */
d3738bb8 5353 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5354
2b6b168d
BA		 5355 retval = hw->phy.ops.acquire(hw);
5356 if (retval) {
5357 e_err("Could not acquire PHY\n");
5358 return retval;
5359 }
5360
5361 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5362 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5363 if (retval)
5364 goto out;
5365
5366 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5367 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5368 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5369 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5370 (u16)(mac_reg & 0xFFFF));
5371 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5372 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5373 }
5374
5375 /* configure PHY Rx Control register */
2b6b168d 5376 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5377 mac_reg = er32(RCTL);
5378 if (mac_reg & E1000_RCTL_UPE)
5379 phy_reg |= BM_RCTL_UPE;
5380 if (mac_reg & E1000_RCTL_MPE)
5381 phy_reg |= BM_RCTL_MPE;
5382 phy_reg &= ~(BM_RCTL_MO_MASK);
5383 if (mac_reg & E1000_RCTL_MO_3)
5384 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
5385 << BM_RCTL_MO_SHIFT);
5386 if (mac_reg & E1000_RCTL_BAM)
5387 phy_reg |= BM_RCTL_BAM;
5388 if (mac_reg & E1000_RCTL_PMCF)
5389 phy_reg |= BM_RCTL_PMCF;
5390 mac_reg = er32(CTRL);
5391 if (mac_reg & E1000_CTRL_RFCE)
5392 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5393 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54
BA		 5394
5395 /* enable PHY wakeup in MAC register */
5396 ew32(WUFC, wufc);
5397 ew32(WUC, E1000_WUC_PHY_WAKE | E1000_WUC_PME_EN);
5398
5399 /* configure and enable PHY wakeup in PHY registers */
2b6b168d
BA		 5400 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
5401 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, E1000_WUC_PME_EN);
a4f58f54
BA		 5402
5403 /* activate PHY wakeup */
2b6b168d
BA		 5404 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5405 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5406 if (retval)
5407 e_err("Could not set PHY Host Wakeup bit\n");
5408out:
94d8186a 5409 hw->phy.ops.release(hw);
a4f58f54
BA		 5410
5411 return retval;
5412}
5413
23606cf5
RW		 5414static int __e1000_shutdown(struct pci_dev *pdev, bool *enable_wake,
5415 bool runtime)
bc7f75fa
AK		 5416{
5417 struct net_device *netdev = pci_get_drvdata(pdev);
5418 struct e1000_adapter *adapter = netdev_priv(netdev);
5419 struct e1000_hw *hw = &adapter->hw;
5420 u32 ctrl, ctrl_ext, rctl, status;
23606cf5
RW		 5421 /* Runtime suspend should only enable wakeup for link changes */
5422 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
bc7f75fa
AK		 5423 int retval = 0;
5424
5425 netif_device_detach(netdev);
5426
5427 if (netif_running(netdev)) {
5428 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
5429 e1000e_down(adapter);
5430 e1000_free_irq(adapter);
5431 }
4662e82b 5432 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 5433
5434 retval = pci_save_state(pdev);
5435 if (retval)
5436 return retval;
5437
5438 status = er32(STATUS);
5439 if (status & E1000_STATUS_LU)
5440 wufc &= ~E1000_WUFC_LNKC;
5441
5442 if (wufc) {
5443 e1000_setup_rctl(adapter);
ef9b965a 5444 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 5445
5446 /* turn on all-multi mode if wake on multicast is enabled */
5447 if (wufc & E1000_WUFC_MC) {
5448 rctl = er32(RCTL);
5449 rctl |= E1000_RCTL_MPE;
5450 ew32(RCTL, rctl);
5451 }
5452
5453 ctrl = er32(CTRL);
5454 /* advertise wake from D3Cold */
5455 #define E1000_CTRL_ADVD3WUC 0x00100000
5456 /* phy power management enable */
5457 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
a4f58f54
BA		 5458 ctrl |= E1000_CTRL_ADVD3WUC;
5459 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
5460 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 5461 ew32(CTRL, ctrl);
5462
318a94d6
JK		 5463 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
5464 adapter->hw.phy.media_type ==
5465 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 5466 /* keep the laser running in D3 */
5467 ctrl_ext = er32(CTRL_EXT);
93a23f48 5468 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 5469 ew32(CTRL_EXT, ctrl_ext);
5470 }
5471
97ac8cae 5472 if (adapter->flags & FLAG_IS_ICH)
99730e4c 5473 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 5474
bc7f75fa
AK		 5475 /* Allow time for pending master requests to run */
5476 e1000e_disable_pcie_master(&adapter->hw);
5477
82776a4b 5478 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 5479 /* enable wakeup by the PHY */
5480 retval = e1000_init_phy_wakeup(adapter, wufc);
5481 if (retval)
5482 return retval;
5483 } else {
5484 /* enable wakeup by the MAC */
5485 ew32(WUFC, wufc);
5486 ew32(WUC, E1000_WUC_PME_EN);
5487 }
bc7f75fa
AK		 5488 } else {
5489 ew32(WUC, 0);
5490 ew32(WUFC, 0);
bc7f75fa
AK		 5491 }
5492
4f9de721
RW		 5493 *enable_wake = !!wufc;
5494
bc7f75fa 5495 /* make sure adapter isn't asleep if manageability is enabled */
82776a4b
BA		 5496 if ((adapter->flags & FLAG_MNG_PT_ENABLED) ||
5497 (hw->mac.ops.check_mng_mode(hw)))
4f9de721 5498 *enable_wake = true;
bc7f75fa
AK		 5499
5500 if (adapter->hw.phy.type == e1000_phy_igp_3)
5501 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
5502
ad68076e
BA		 5503 /*
5504 * Release control of h/w to f/w. If f/w is AMT enabled, this
5505 * would have already happened in close and is redundant.
5506 */
31dbe5b4 5507 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 5508
5509 pci_disable_device(pdev);
5510
4f9de721
RW		 5511 return 0;
5512}
5513
5514static void e1000_power_off(struct pci_dev *pdev, bool sleep, bool wake)
5515{
5516 if (sleep && wake) {
5517 pci_prepare_to_sleep(pdev);
5518 return;
5519 }
5520
5521 pci_wake_from_d3(pdev, wake);
5522 pci_set_power_state(pdev, PCI_D3hot);
5523}
5524
5525static void e1000_complete_shutdown(struct pci_dev *pdev, bool sleep,
5526 bool wake)
5527{
5528 struct net_device *netdev = pci_get_drvdata(pdev);
5529 struct e1000_adapter *adapter = netdev_priv(netdev);
5530
005cbdfc
AD		 5531 /*
5532 * The pci-e switch on some quad port adapters will report a
5533 * correctable error when the MAC transitions from D0 to D3. To
5534 * prevent this we need to mask off the correctable errors on the
5535 * downstream port of the pci-e switch.
5536 */
5537 if (adapter->flags & FLAG_IS_QUAD_PORT) {
5538 struct pci_dev *us_dev = pdev->bus->self;
353064de 5539 int pos = pci_pcie_cap(us_dev);
005cbdfc
AD		 5540 u16 devctl;
5541
5542 pci_read_config_word(us_dev, pos + PCI_EXP_DEVCTL, &devctl);
5543 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL,
5544 (devctl & ~PCI_EXP_DEVCTL_CERE));
5545
4f9de721 5546 e1000_power_off(pdev, sleep, wake);
005cbdfc
AD		 5547
5548 pci_write_config_word(us_dev, pos + PCI_EXP_DEVCTL, devctl);
5549 } else {
4f9de721 5550 e1000_power_off(pdev, sleep, wake);
005cbdfc 5551 }
bc7f75fa
AK		 5552}
5553
6f461f6c
BA		 5554#ifdef CONFIG_PCIEASPM
5555static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
5556{
9f728f53 5557 pci_disable_link_state_locked(pdev, state);
6f461f6c
BA		 5558}
5559#else
5560static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
1eae4eb2
AK		 5561{
5562 int pos;
6f461f6c 5563 u16 reg16;
1eae4eb2
AK		 5564
5565 /*
6f461f6c
BA		 5566 * Both device and parent should have the same ASPM setting.
5567 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 5568 */
6f461f6c
BA		 5569 pos = pci_pcie_cap(pdev);
5570 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
5571 reg16 &= ~state;
5572 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
5573
0c75ba22
AB		 5574 if (!pdev->bus->self)
5575 return;
5576
6f461f6c
BA		 5577 pos = pci_pcie_cap(pdev->bus->self);
5578 pci_read_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, &reg16);
5579 reg16 &= ~state;
5580 pci_write_config_word(pdev->bus->self, pos + PCI_EXP_LNKCTL, reg16);
5581}
5582#endif
78cd29d5 5583static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c
BA		 5584{
5585 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
5586 (state & PCIE_LINK_STATE_L0S) ? "L0s" : "",
5587 (state & PCIE_LINK_STATE_L1) ? "L1" : "");
5588
5589 __e1000e_disable_aspm(pdev, state);
1eae4eb2
AK		 5590}
5591
aa338601 5592#ifdef CONFIG_PM
23606cf5 5593static bool e1000e_pm_ready(struct e1000_adapter *adapter)
4f9de721 5594{
23606cf5 5595 return !!adapter->tx_ring->buffer_info;
4f9de721
RW		 5596}
5597
23606cf5 5598static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 5599{
5600 struct net_device *netdev = pci_get_drvdata(pdev);
5601 struct e1000_adapter *adapter = netdev_priv(netdev);
5602 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5603 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 5604 u32 err;
5605
78cd29d5
BA		 5606 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5607 aspm_disable_flag = PCIE_LINK_STATE_L0S;
5608 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
5609 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5610 if (aspm_disable_flag)
5611 e1000e_disable_aspm(pdev, aspm_disable_flag);
5612
bc7f75fa
AK		 5613 pci_set_power_state(pdev, PCI_D0);
5614 pci_restore_state(pdev);
28b8f04a 5615 pci_save_state(pdev);
6e4f6f6b 5616
4662e82b 5617 e1000e_set_interrupt_capability(adapter);
bc7f75fa
AK		 5618 if (netif_running(netdev)) {
5619 err = e1000_request_irq(adapter);
5620 if (err)
5621 return err;
5622 }
5623
99730e4c
BA		 5624 if (hw->mac.type == e1000_pch2lan)
5625 e1000_resume_workarounds_pchlan(&adapter->hw);
5626
bc7f75fa 5627 e1000e_power_up_phy(adapter);
a4f58f54
BA		 5628
5629 /* report the system wakeup cause from S3/S4 */
5630 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
5631 u16 phy_data;
5632
5633 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
5634 if (phy_data) {
5635 e_info("PHY Wakeup cause - %s\n",
5636 phy_data & E1000_WUS_EX ? "Unicast Packet" :
5637 phy_data & E1000_WUS_MC ? "Multicast Packet" :
5638 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
5639 phy_data & E1000_WUS_MAG ? "Magic Packet" :
ef456f85
JK		 5640 phy_data & E1000_WUS_LNKC ?
5641 "Link Status Change" : "other");
a4f58f54
BA		 5642 }
5643 e1e_wphy(&adapter->hw, BM_WUS, ~0);
5644 } else {
5645 u32 wus = er32(WUS);
5646 if (wus) {
5647 e_info("MAC Wakeup cause - %s\n",
5648 wus & E1000_WUS_EX ? "Unicast Packet" :
5649 wus & E1000_WUS_MC ? "Multicast Packet" :
5650 wus & E1000_WUS_BC ? "Broadcast Packet" :
5651 wus & E1000_WUS_MAG ? "Magic Packet" :
5652 wus & E1000_WUS_LNKC ? "Link Status Change" :
5653 "other");
5654 }
5655 ew32(WUS, ~0);
5656 }
5657
bc7f75fa 5658 e1000e_reset(adapter);
bc7f75fa 5659
cd791618 5660 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5661
5662 if (netif_running(netdev))
5663 e1000e_up(adapter);
5664
5665 netif_device_attach(netdev);
5666
ad68076e
BA		 5667 /*
5668 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5669 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5670 * under the control of the driver.
5671 */
c43bc57e 5672 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5673 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5674
5675 return 0;
5676}
23606cf5 5677
a0340162
RW		 5678#ifdef CONFIG_PM_SLEEP
5679static int e1000_suspend(struct device *dev)
5680{
5681 struct pci_dev *pdev = to_pci_dev(dev);
5682 int retval;
5683 bool wake;
5684
5685 retval = __e1000_shutdown(pdev, &wake, false);
5686 if (!retval)
5687 e1000_complete_shutdown(pdev, true, wake);
5688
5689 return retval;
5690}
5691
23606cf5
RW		 5692static int e1000_resume(struct device *dev)
5693{
5694 struct pci_dev *pdev = to_pci_dev(dev);
5695 struct net_device *netdev = pci_get_drvdata(pdev);
5696 struct e1000_adapter *adapter = netdev_priv(netdev);
5697
5698 if (e1000e_pm_ready(adapter))
5699 adapter->idle_check = true;
5700
5701 return __e1000_resume(pdev);
5702}
a0340162
RW		 5703#endif /* CONFIG_PM_SLEEP */
5704
5705#ifdef CONFIG_PM_RUNTIME
5706static int e1000_runtime_suspend(struct device *dev)
5707{
5708 struct pci_dev *pdev = to_pci_dev(dev);
5709 struct net_device *netdev = pci_get_drvdata(pdev);
5710 struct e1000_adapter *adapter = netdev_priv(netdev);
5711
5712 if (e1000e_pm_ready(adapter)) {
5713 bool wake;
5714
5715 __e1000_shutdown(pdev, &wake, true);
5716 }
5717
5718 return 0;
5719}
5720
5721static int e1000_idle(struct device *dev)
5722{
5723 struct pci_dev *pdev = to_pci_dev(dev);
5724 struct net_device *netdev = pci_get_drvdata(pdev);
5725 struct e1000_adapter *adapter = netdev_priv(netdev);
5726
5727 if (!e1000e_pm_ready(adapter))
5728 return 0;
5729
5730 if (adapter->idle_check) {
5731 adapter->idle_check = false;
5732 if (!e1000e_has_link(adapter))
5733 pm_schedule_suspend(dev, MSEC_PER_SEC);
5734 }
5735
5736 return -EBUSY;
5737}
23606cf5
RW		 5738
5739static int e1000_runtime_resume(struct device *dev)
5740{
5741 struct pci_dev *pdev = to_pci_dev(dev);
5742 struct net_device *netdev = pci_get_drvdata(pdev);
5743 struct e1000_adapter *adapter = netdev_priv(netdev);
5744
5745 if (!e1000e_pm_ready(adapter))
5746 return 0;
5747
5748 adapter->idle_check = !dev->power.runtime_auto;
5749 return __e1000_resume(pdev);
5750}
a0340162 5751#endif /* CONFIG_PM_RUNTIME */
aa338601 5752#endif /* CONFIG_PM */
bc7f75fa
AK		 5753
5754static void e1000_shutdown(struct pci_dev *pdev)
5755{
4f9de721
RW		 5756 bool wake = false;
5757
23606cf5 5758 __e1000_shutdown(pdev, &wake, false);
4f9de721
RW		 5759
5760 if (system_state == SYSTEM_POWER_OFF)
5761 e1000_complete_shutdown(pdev, false, wake);
bc7f75fa
AK		 5762}
5763
5764#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c
DD		 5765
5766static irqreturn_t e1000_intr_msix(int irq, void *data)
5767{
5768 struct net_device *netdev = data;
5769 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 5770
5771 if (adapter->msix_entries) {
90da0669
BA		 5772 int vector, msix_irq;
5773
147b2c8c
DD		 5774 vector = 0;
5775 msix_irq = adapter->msix_entries[vector].vector;
5776 disable_irq(msix_irq);
5777 e1000_intr_msix_rx(msix_irq, netdev);
5778 enable_irq(msix_irq);
5779
5780 vector++;
5781 msix_irq = adapter->msix_entries[vector].vector;
5782 disable_irq(msix_irq);
5783 e1000_intr_msix_tx(msix_irq, netdev);
5784 enable_irq(msix_irq);
5785
5786 vector++;
5787 msix_irq = adapter->msix_entries[vector].vector;
5788 disable_irq(msix_irq);
5789 e1000_msix_other(msix_irq, netdev);
5790 enable_irq(msix_irq);
5791 }
5792
5793 return IRQ_HANDLED;
5794}
5795
bc7f75fa
AK		 5796/*
5797 * Polling 'interrupt' - used by things like netconsole to send skbs
5798 * without having to re-enable interrupts. It's not called while
5799 * the interrupt routine is executing.
5800 */
5801static void e1000_netpoll(struct net_device *netdev)
5802{
5803 struct e1000_adapter *adapter = netdev_priv(netdev);
5804
147b2c8c
DD		 5805 switch (adapter->int_mode) {
5806 case E1000E_INT_MODE_MSIX:
5807 e1000_intr_msix(adapter->pdev->irq, netdev);
5808 break;
5809 case E1000E_INT_MODE_MSI:
5810 disable_irq(adapter->pdev->irq);
5811 e1000_intr_msi(adapter->pdev->irq, netdev);
5812 enable_irq(adapter->pdev->irq);
5813 break;
5814 default: /* E1000E_INT_MODE_LEGACY */
5815 disable_irq(adapter->pdev->irq);
5816 e1000_intr(adapter->pdev->irq, netdev);
5817 enable_irq(adapter->pdev->irq);
5818 break;
5819 }
bc7f75fa
AK		 5820}
5821#endif
5822
5823/**
5824 * e1000_io_error_detected - called when PCI error is detected
5825 * @pdev: Pointer to PCI device
5826 * @state: The current pci connection state
5827 *
5828 * This function is called after a PCI bus error affecting
5829 * this device has been detected.
5830 */
5831static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
5832 pci_channel_state_t state)
5833{
5834 struct net_device *netdev = pci_get_drvdata(pdev);
5835 struct e1000_adapter *adapter = netdev_priv(netdev);
5836
5837 netif_device_detach(netdev);
5838
c93b5a76
MM		 5839 if (state == pci_channel_io_perm_failure)
5840 return PCI_ERS_RESULT_DISCONNECT;
5841
bc7f75fa
AK		 5842 if (netif_running(netdev))
5843 e1000e_down(adapter);
5844 pci_disable_device(pdev);
5845
5846 /* Request a slot slot reset. */
5847 return PCI_ERS_RESULT_NEED_RESET;
5848}
5849
5850/**
5851 * e1000_io_slot_reset - called after the pci bus has been reset.
5852 * @pdev: Pointer to PCI device
5853 *
5854 * Restart the card from scratch, as if from a cold-boot. Implementation
5855 * resembles the first-half of the e1000_resume routine.
5856 */
5857static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
5858{
5859 struct net_device *netdev = pci_get_drvdata(pdev);
5860 struct e1000_adapter *adapter = netdev_priv(netdev);
5861 struct e1000_hw *hw = &adapter->hw;
78cd29d5 5862 u16 aspm_disable_flag = 0;
6e4f6f6b 5863 int err;
111b9dc5 5864 pci_ers_result_t result;
bc7f75fa 5865
78cd29d5
BA		 5866 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
5867 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 5868 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 5869 aspm_disable_flag |= PCIE_LINK_STATE_L1;
5870 if (aspm_disable_flag)
5871 e1000e_disable_aspm(pdev, aspm_disable_flag);
5872
f0f422e5 5873 err = pci_enable_device_mem(pdev);
6e4f6f6b 5874 if (err) {
bc7f75fa
AK		 5875 dev_err(&pdev->dev,
5876 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 5877 result = PCI_ERS_RESULT_DISCONNECT;
5878 } else {
5879 pci_set_master(pdev);
23606cf5 5880 pdev->state_saved = true;
111b9dc5 5881 pci_restore_state(pdev);
bc7f75fa 5882
111b9dc5
JB		 5883 pci_enable_wake(pdev, PCI_D3hot, 0);
5884 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 5885
111b9dc5
JB		 5886 e1000e_reset(adapter);
5887 ew32(WUS, ~0);
5888 result = PCI_ERS_RESULT_RECOVERED;
5889 }
bc7f75fa 5890
111b9dc5
JB		 5891 pci_cleanup_aer_uncorrect_error_status(pdev);
5892
5893 return result;
bc7f75fa
AK		 5894}
5895
5896/**
5897 * e1000_io_resume - called when traffic can start flowing again.
5898 * @pdev: Pointer to PCI device
5899 *
5900 * This callback is called when the error recovery driver tells us that
5901 * its OK to resume normal operation. Implementation resembles the
5902 * second-half of the e1000_resume routine.
5903 */
5904static void e1000_io_resume(struct pci_dev *pdev)
5905{
5906 struct net_device *netdev = pci_get_drvdata(pdev);
5907 struct e1000_adapter *adapter = netdev_priv(netdev);
5908
cd791618 5909 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 5910
5911 if (netif_running(netdev)) {
5912 if (e1000e_up(adapter)) {
5913 dev_err(&pdev->dev,
5914 "can't bring device back up after reset\n");
5915 return;
5916 }
5917 }
5918
5919 netif_device_attach(netdev);
5920
ad68076e
BA		 5921 /*
5922 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 5923 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 5924 * under the control of the driver.
5925 */
c43bc57e 5926 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 5927 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 5928
5929}
5930
5931static void e1000_print_device_info(struct e1000_adapter *adapter)
5932{
5933 struct e1000_hw *hw = &adapter->hw;
5934 struct net_device *netdev = adapter->netdev;
073287c0
BA		 5935 u32 ret_val;
5936 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 5937
5938 /* print bus type/speed/width info */
a5cc7642 5939 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 5940 /* bus width */
5941 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
5942 "Width x1"),
5943 /* MAC address */
7c510e4b 5944 netdev->dev_addr);
44defeb3
JK		 5945 e_info("Intel(R) PRO/%s Network Connection\n",
5946 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 5947 ret_val = e1000_read_pba_string_generic(hw, pba_str,
5948 E1000_PBANUM_LENGTH);
5949 if (ret_val)
e0dc4f12 5950 strncpy((char *)pba_str, "Unknown", sizeof(pba_str) - 1);
073287c0
BA		 5951 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
5952 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 5953}
5954
10aa4c04
AK		 5955static void e1000_eeprom_checks(struct e1000_adapter *adapter)
5956{
5957 struct e1000_hw *hw = &adapter->hw;
5958 int ret_val;
5959 u16 buf = 0;
5960
5961 if (hw->mac.type != e1000_82573)
5962 return;
5963
5964 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e243455d 5965 if (!ret_val && (!(le16_to_cpu(buf) & (1 << 0)))) {
10aa4c04 5966 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 5967 dev_warn(&adapter->pdev->dev,
5968 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 5969 }
10aa4c04
AK		 5970}
5971
c8f44aff 5972static int e1000_set_features(struct net_device *netdev,
70495a50 5973 netdev_features_t features)
dc221294
BA		 5974{
5975 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 5976 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 5977
5978 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
5979 adapter->flags |= FLAG_TSO_FORCE;
5980
5981 if (!(changed & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX |
70495a50 5982 NETIF_F_RXCSUM | NETIF_F_RXHASH)))
dc221294
BA		 5983 return 0;
5984
70495a50
BA		 5985 /*
5986 * IP payload checksum (enabled with jumbos/packet-split when Rx
5987 * checksum is enabled) and generation of RSS hash is mutually
5988 * exclusive in the hardware.
5989 */
5990 if (adapter->rx_ps_pages &&
5991 (features & NETIF_F_RXCSUM) && (features & NETIF_F_RXHASH)) {
5992 e_err("Enabling both receive checksum offload and receive hashing is not possible with jumbo frames. Disable jumbos or enable only one of the receive offload features.\n");
5993 return -EINVAL;
5994 }
5995
5996 netdev->features = features;
5997
dc221294
BA		 5998 if (netif_running(netdev))
5999 e1000e_reinit_locked(adapter);
6000 else
6001 e1000e_reset(adapter);
6002
6003 return 0;
6004}
6005
651c2466
SH		 6006static const struct net_device_ops e1000e_netdev_ops = {
6007 .ndo_open = e1000_open,
6008 .ndo_stop = e1000_close,
00829823 6009 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6010 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6011 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6012 .ndo_set_mac_address = e1000_set_mac,
6013 .ndo_change_mtu = e1000_change_mtu,
6014 .ndo_do_ioctl = e1000_ioctl,
6015 .ndo_tx_timeout = e1000_tx_timeout,
6016 .ndo_validate_addr = eth_validate_addr,
6017
651c2466
SH		 6018 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6019 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6020#ifdef CONFIG_NET_POLL_CONTROLLER
6021 .ndo_poll_controller = e1000_netpoll,
6022#endif
dc221294 6023 .ndo_set_features = e1000_set_features,
651c2466
SH		 6024};
6025
bc7f75fa
AK		 6026/**
6027 * e1000_probe - Device Initialization Routine
6028 * @pdev: PCI device information struct
6029 * @ent: entry in e1000_pci_tbl
6030 *
6031 * Returns 0 on success, negative on failure
6032 *
6033 * e1000_probe initializes an adapter identified by a pci_dev structure.
6034 * The OS initialization, configuring of the adapter private structure,
6035 * and a hardware reset occur.
6036 **/
6037static int __devinit e1000_probe(struct pci_dev *pdev,
6038 const struct pci_device_id *ent)
6039{
6040 struct net_device *netdev;
6041 struct e1000_adapter *adapter;
6042 struct e1000_hw *hw;
6043 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6044 resource_size_t mmio_start, mmio_len;
6045 resource_size_t flash_start, flash_len;
bc7f75fa
AK		 6046
6047 static int cards_found;
78cd29d5 6048 u16 aspm_disable_flag = 0;
bc7f75fa
AK		 6049 int i, err, pci_using_dac;
6050 u16 eeprom_data = 0;
6051 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6052
78cd29d5
BA		 6053 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6054 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6055 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6056 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6057 if (aspm_disable_flag)
6058 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6059
f0f422e5 6060 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6061 if (err)
6062 return err;
6063
6064 pci_using_dac = 0;
0be3f55f 6065 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6066 if (!err) {
0be3f55f 6067 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa
AK		 6068 if (!err)
6069 pci_using_dac = 1;
6070 } else {
0be3f55f 6071 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6072 if (err) {
0be3f55f
NN		 6073 err = dma_set_coherent_mask(&pdev->dev,
6074 DMA_BIT_MASK(32));
bc7f75fa 6075 if (err) {
ef456f85 6076 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
bc7f75fa
AK		 6077 goto err_dma;
6078 }
6079 }
6080 }
6081
e8de1481 6082 err = pci_request_selected_regions_exclusive(pdev,
f0f422e5
BA		 6083 pci_select_bars(pdev, IORESOURCE_MEM),
6084 e1000e_driver_name);
bc7f75fa
AK		 6085 if (err)
6086 goto err_pci_reg;
6087
68eac460 6088 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6089 pci_enable_pcie_error_reporting(pdev);
68eac460 6090
bc7f75fa 6091 pci_set_master(pdev);
438b365a
BA		 6092 /* PCI config space info */
6093 err = pci_save_state(pdev);
6094 if (err)
6095 goto err_alloc_etherdev;
bc7f75fa
AK		 6096
6097 err = -ENOMEM;
6098 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6099 if (!netdev)
6100 goto err_alloc_etherdev;
6101
bc7f75fa
AK		 6102 SET_NETDEV_DEV(netdev, &pdev->dev);
6103
f85e4dfa
TH		 6104 netdev->irq = pdev->irq;
6105
bc7f75fa
AK		 6106 pci_set_drvdata(pdev, netdev);
6107 adapter = netdev_priv(netdev);
6108 hw = &adapter->hw;
6109 adapter->netdev = netdev;
6110 adapter->pdev = pdev;
6111 adapter->ei = ei;
6112 adapter->pba = ei->pba;
6113 adapter->flags = ei->flags;
eb7c3adb 6114 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6115 adapter->hw.adapter = adapter;
6116 adapter->hw.mac.type = ei->mac;
2adc55c9 6117 adapter->max_hw_frame_size = ei->max_hw_frame_size;
bc7f75fa
AK		 6118 adapter->msg_enable = (1 << NETIF_MSG_DRV | NETIF_MSG_PROBE) - 1;
6119
6120 mmio_start = pci_resource_start(pdev, 0);
6121 mmio_len = pci_resource_len(pdev, 0);
6122
6123 err = -EIO;
6124 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6125 if (!adapter->hw.hw_addr)
6126 goto err_ioremap;
6127
6128 if ((adapter->flags & FLAG_HAS_FLASH) &&
6129 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6130 flash_start = pci_resource_start(pdev, 1);
6131 flash_len = pci_resource_len(pdev, 1);
6132 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6133 if (!adapter->hw.flash_address)
6134 goto err_flashmap;
6135 }
6136
6137 /* construct the net_device struct */
651c2466 6138 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6139 e1000e_set_ethtool_ops(netdev);
bc7f75fa
AK		 6140 netdev->watchdog_timeo = 5 * HZ;
6141 netif_napi_add(netdev, &adapter->napi, e1000_clean, 64);
bc7f75fa
AK		 6142 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
6143
6144 netdev->mem_start = mmio_start;
6145 netdev->mem_end = mmio_start + mmio_len;
6146
6147 adapter->bd_number = cards_found++;
6148
4662e82b
BA		 6149 e1000e_check_options(adapter);
6150
bc7f75fa
AK		 6151 /* setup adapter struct */
6152 err = e1000_sw_init(adapter);
6153 if (err)
6154 goto err_sw_init;
6155
bc7f75fa
AK		 6156 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6157 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6158 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6159
69e3fd8c 6160 err = ei->get_variants(adapter);
bc7f75fa
AK		 6161 if (err)
6162 goto err_hw_init;
6163
4a770358
BA		 6164 if ((adapter->flags & FLAG_IS_ICH) &&
6165 (adapter->flags & FLAG_READ_ONLY_NVM))
6166 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6167
bc7f75fa
AK		 6168 hw->mac.ops.get_bus_info(&adapter->hw);
6169
318a94d6 6170 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6171
6172 /* Copper options */
318a94d6 6173 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6174 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6175 adapter->hw.phy.disable_polarity_correction = 0;
6176 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6177 }
6178
6179 if (e1000_check_reset_block(&adapter->hw))
44defeb3 6180 e_info("PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6181
dc221294
BA		 6182 /* Set initial default active device features */
6183 netdev->features = (NETIF_F_SG |
6184 NETIF_F_HW_VLAN_RX |
6185 NETIF_F_HW_VLAN_TX |
6186 NETIF_F_TSO |
6187 NETIF_F_TSO6 |
70495a50 6188 NETIF_F_RXHASH |
dc221294
BA		 6189 NETIF_F_RXCSUM |
6190 NETIF_F_HW_CSUM);
6191
6192 /* Set user-changeable features (subset of all device features) */
6193 netdev->hw_features = netdev->features;
bc7f75fa
AK		 6194
6195 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
6196 netdev->features |= NETIF_F_HW_VLAN_FILTER;
6197
dc221294
BA		 6198 netdev->vlan_features |= (NETIF_F_SG |
6199 NETIF_F_TSO |
6200 NETIF_F_TSO6 |
6201 NETIF_F_HW_CSUM);
a5136e23 6202
ef9b965a
JB		 6203 netdev->priv_flags |= IFF_UNICAST_FLT;
6204
7b872a55 6205 if (pci_using_dac) {
bc7f75fa 6206 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6207 netdev->vlan_features |= NETIF_F_HIGHDMA;
6208 }
bc7f75fa 6209
bc7f75fa
AK		 6210 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6211 adapter->flags |= FLAG_MNG_PT_ENABLED;
6212
ad68076e
BA		 6213 /*
6214 * before reading the NVM, reset the controller to
6215 * put the device in a known good starting state
6216 */
bc7f75fa
AK		 6217 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6218
6219 /*
6220 * systems with ASPM and others may see the checksum fail on the first
6221 * attempt. Let's give it a few tries
6222 */
6223 for (i = 0;; i++) {
6224 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6225 break;
6226 if (i == 2) {
44defeb3 6227 e_err("The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6228 err = -EIO;
6229 goto err_eeprom;
6230 }
6231 }
6232
10aa4c04
AK		 6233 e1000_eeprom_checks(adapter);
6234
608f8a0d 6235 /* copy the MAC address */
bc7f75fa 6236 if (e1000e_read_mac_addr(&adapter->hw))
44defeb3 6237 e_err("NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6238
6239 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
6240 memcpy(netdev->perm_addr, adapter->hw.mac.addr, netdev->addr_len);
6241
6242 if (!is_valid_ether_addr(netdev->perm_addr)) {
7c510e4b 6243 e_err("Invalid MAC Address: %pM\n", netdev->perm_addr);
bc7f75fa
AK		 6244 err = -EIO;
6245 goto err_eeprom;
6246 }
6247
6248 init_timer(&adapter->watchdog_timer);
c061b18d 6249 adapter->watchdog_timer.function = e1000_watchdog;
bc7f75fa
AK		 6250 adapter->watchdog_timer.data = (unsigned long) adapter;
6251
6252 init_timer(&adapter->phy_info_timer);
c061b18d 6253 adapter->phy_info_timer.function = e1000_update_phy_info;
bc7f75fa
AK		 6254 adapter->phy_info_timer.data = (unsigned long) adapter;
6255
6256 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6257 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6258 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6259 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6260 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6261
bc7f75fa
AK		 6262 /* Initialize link parameters. User can change them with ethtool */
6263 adapter->hw.mac.autoneg = 1;
3db1cd5c 6264 adapter->fc_autoneg = true;
5c48ef3e
BA		 6265 adapter->hw.fc.requested_mode = e1000_fc_default;
6266 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6267 adapter->hw.phy.autoneg_advertised = 0x2f;
6268
6269 /* ring size defaults */
6270 adapter->rx_ring->count = 256;
6271 adapter->tx_ring->count = 256;
6272
6273 /*
6274 * Initial Wake on LAN setting - If APM wake is enabled in
6275 * the EEPROM, enable the ACPI Magic Packet filter
6276 */
6277 if (adapter->flags & FLAG_APME_IN_WUC) {
6278 /* APME bit in EEPROM is mapped to WUC.APME */
6279 eeprom_data = er32(WUC);
6280 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6281 if ((hw->mac.type > e1000_ich10lan) &&
6282 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6283 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6284 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6285 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6286 (adapter->hw.bus.func == 1))
6287 e1000_read_nvm(&adapter->hw,
6288 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
6289 else
6290 e1000_read_nvm(&adapter->hw,
6291 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
6292 }
6293
6294 /* fetch WoL from EEPROM */
6295 if (eeprom_data & eeprom_apme_mask)
6296 adapter->eeprom_wol |= E1000_WUFC_MAG;
6297
6298 /*
6299 * now that we have the eeprom settings, apply the special cases
6300 * where the eeprom may be wrong or the board simply won't support
6301 * wake on lan on a particular port
6302 */
6303 if (!(adapter->flags & FLAG_HAS_WOL))
6304 adapter->eeprom_wol = 0;
6305
6306 /* initialize the wol settings based on the eeprom settings */
6307 adapter->wol = adapter->eeprom_wol;
6ff68026 6308 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
bc7f75fa 6309
84527590
BA		 6310 /* save off EEPROM version number */
6311 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6312
bc7f75fa
AK		 6313 /* reset the hardware with the new settings */
6314 e1000e_reset(adapter);
6315
ad68076e
BA		 6316 /*
6317 * If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6318 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6319 * under the control of the driver.
6320 */
c43bc57e 6321 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6322 e1000e_get_hw_control(adapter);
bc7f75fa 6323
e0dc4f12 6324 strncpy(netdev->name, "eth%d", sizeof(netdev->name) - 1);
bc7f75fa
AK		 6325 err = register_netdev(netdev);
6326 if (err)
6327 goto err_register;
6328
9c563d20
JB		 6329 /* carrier off reporting is important to ethtool even BEFORE open */
6330 netif_carrier_off(netdev);
6331
bc7f75fa
AK		 6332 e1000_print_device_info(adapter);
6333
f3ec4f87
AS		 6334 if (pci_dev_run_wake(pdev))
6335 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6336
bc7f75fa
AK		 6337 return 0;
6338
6339err_register:
c43bc57e 6340 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6341 e1000e_release_hw_control(adapter);
bc7f75fa
AK		 6342err_eeprom:
6343 if (!e1000_check_reset_block(&adapter->hw))
6344 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6345err_hw_init:
bc7f75fa
AK		 6346 kfree(adapter->tx_ring);
6347 kfree(adapter->rx_ring);
6348err_sw_init:
c43bc57e
JB		 6349 if (adapter->hw.flash_address)
6350 iounmap(adapter->hw.flash_address);
e82f54ba 6351 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6352err_flashmap:
bc7f75fa
AK		 6353 iounmap(adapter->hw.hw_addr);
6354err_ioremap:
6355 free_netdev(netdev);
6356err_alloc_etherdev:
f0f422e5
BA		 6357 pci_release_selected_regions(pdev,
6358 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6359err_pci_reg:
6360err_dma:
6361 pci_disable_device(pdev);
6362 return err;
6363}
6364
6365/**
6366 * e1000_remove - Device Removal Routine
6367 * @pdev: PCI device information struct
6368 *
6369 * e1000_remove is called by the PCI subsystem to alert the driver
6370 * that it should release a PCI device. The could be caused by a
6371 * Hot-Plug event, or because the driver is going to be removed from
6372 * memory.
6373 **/
6374static void __devexit e1000_remove(struct pci_dev *pdev)
6375{
6376 struct net_device *netdev = pci_get_drvdata(pdev);
6377 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6378 bool down = test_bit(__E1000_DOWN, &adapter->state);
6379
ad68076e 6380 /*
23f333a2
TH		 6381 * The timers may be rescheduled, so explicitly disable them
6382 * from being rescheduled.
ad68076e 6383 */
23606cf5
RW		 6384 if (!down)
6385 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6386 del_timer_sync(&adapter->watchdog_timer);
6387 del_timer_sync(&adapter->phy_info_timer);
6388
41cec6f1
BA		 6389 cancel_work_sync(&adapter->reset_task);
6390 cancel_work_sync(&adapter->watchdog_task);
6391 cancel_work_sync(&adapter->downshift_task);
6392 cancel_work_sync(&adapter->update_phy_task);
6393 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6394
17f208de
BA		 6395 if (!(netdev->flags & IFF_UP))
6396 e1000_power_down_phy(adapter);
6397
23606cf5
RW		 6398 /* Don't lie to e1000_close() down the road. */
6399 if (!down)
6400 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6401 unregister_netdev(netdev);
6402
f3ec4f87
AS		 6403 if (pci_dev_run_wake(pdev))
6404 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6405
ad68076e
BA		 6406 /*
6407 * Release control of h/w to f/w. If f/w is AMT enabled, this
6408 * would have already happened in close and is redundant.
6409 */
31dbe5b4 6410 e1000e_release_hw_control(adapter);
bc7f75fa 6411
4662e82b 6412 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6413 kfree(adapter->tx_ring);
6414 kfree(adapter->rx_ring);
6415
6416 iounmap(adapter->hw.hw_addr);
6417 if (adapter->hw.flash_address)
6418 iounmap(adapter->hw.flash_address);
f0f422e5
BA		 6419 pci_release_selected_regions(pdev,
6420 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6421
6422 free_netdev(netdev);
6423
111b9dc5 6424 /* AER disable */
19d5afd4 6425 pci_disable_pcie_error_reporting(pdev);
111b9dc5 6426
bc7f75fa
AK		 6427 pci_disable_device(pdev);
6428}
6429
6430/* PCI Error Recovery (ERS) */
6431static struct pci_error_handlers e1000_err_handler = {
6432 .error_detected = e1000_io_error_detected,
6433 .slot_reset = e1000_io_slot_reset,
6434 .resume = e1000_io_resume,
6435};
6436
a3aa1884 6437static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 6438 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
6439 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
6440 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
6441 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP), board_82571 },
6442 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
6443 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 6444 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
6445 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
6446 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 6447
bc7f75fa
AK		 6448 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
6449 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
6450 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
6451 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 6452
bc7f75fa
AK		 6453 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
6454 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
6455 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 6456
4662e82b 6457 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 6458 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 6459 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 6460
bc7f75fa
AK		 6461 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
6462 board_80003es2lan },
6463 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
6464 board_80003es2lan },
6465 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
6466 board_80003es2lan },
6467 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
6468 board_80003es2lan },
ad68076e 6469
bc7f75fa
AK		 6470 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
6471 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
6472 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
6473 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
6474 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
6475 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
6476 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 6477 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 6478
bc7f75fa
AK		 6479 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
6480 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
6481 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
6482 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
6483 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 6484 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 6485 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
6486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
6487 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
6488
6489 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
6490 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
6491 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 6492
f4187b56
BA		 6493 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
6494 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 6495 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 6496
a4f58f54
BA		 6497 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
6498 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
6499 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
6500 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
6501
d3738bb8
BA		 6502 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
6503 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
6504
bc7f75fa
AK		 6505 { } /* terminate list */
6506};
6507MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
6508
aa338601 6509#ifdef CONFIG_PM
23606cf5 6510static const struct dev_pm_ops e1000_pm_ops = {
a0340162
RW		 6511 SET_SYSTEM_SLEEP_PM_OPS(e1000_suspend, e1000_resume)
6512 SET_RUNTIME_PM_OPS(e1000_runtime_suspend,
6513 e1000_runtime_resume, e1000_idle)
23606cf5 6514};
e50208a0 6515#endif
23606cf5 6516
bc7f75fa
AK		 6517/* PCI Device API Driver */
6518static struct pci_driver e1000_driver = {
6519 .name = e1000e_driver_name,
6520 .id_table = e1000_pci_tbl,
6521 .probe = e1000_probe,
6522 .remove = __devexit_p(e1000_remove),
aa338601 6523#ifdef CONFIG_PM
23606cf5 6524 .driver.pm = &e1000_pm_ops,
bc7f75fa
AK		 6525#endif
6526 .shutdown = e1000_shutdown,
6527 .err_handler = &e1000_err_handler
6528};
6529
6530/**
6531 * e1000_init_module - Driver Registration Routine
6532 *
6533 * e1000_init_module is the first routine called when the driver is
6534 * loaded. All it does is register with the PCI subsystem.
6535 **/
6536static int __init e1000_init_module(void)
6537{
6538 int ret;
8544b9f7
BA		 6539 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
6540 e1000e_driver_version);
0d6057e4 6541 pr_info("Copyright(c) 1999 - 2011 Intel Corporation.\n");
bc7f75fa 6542 ret = pci_register_driver(&e1000_driver);
53ec5498 6543
bc7f75fa
AK		 6544 return ret;
6545}
6546module_init(e1000_init_module);
6547
6548/**
6549 * e1000_exit_module - Driver Exit Cleanup Routine
6550 *
6551 * e1000_exit_module is called just before the driver is removed
6552 * from memory.
6553 **/
6554static void __exit e1000_exit_module(void)
6555{
6556 pci_unregister_driver(&e1000_driver);
6557}
6558module_exit(e1000_exit_module);
6559
6560
6561MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
6562MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
6563MODULE_LICENSE("GPL");
6564MODULE_VERSION(DRV_VERSION);
6565
6566/* e1000_main.c */
Linux 6.x block layer and io_uring tree(s)