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e1000: Elementary checkpatch warnings and checks removed
[linux-block.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
e78b80b1 1/* Intel PRO/1000 Linux driver
529498cd 2 * Copyright(c) 1999 - 2015 Intel Corporation.
e78b80b1
DE		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
bc7f75fa 21
8544b9f7
BA		 22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
bc7f75fa
AK		 24#include <linux/module.h>
25#include <linux/types.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/vmalloc.h>
29#include <linux/pagemap.h>
30#include <linux/delay.h>
31#include <linux/netdevice.h>
9fb7a5f7 32#include <linux/interrupt.h>
bc7f75fa
AK		 33#include <linux/tcp.h>
34#include <linux/ipv6.h>
5a0e3ad6 35#include <linux/slab.h>
bc7f75fa
AK		 36#include <net/checksum.h>
37#include <net/ip6_checksum.h>
bc7f75fa
AK		 38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/cpu.h>
41#include <linux/smp.h>
e8db0be1 42#include <linux/pm_qos.h>
23606cf5 43#include <linux/pm_runtime.h>
111b9dc5 44#include <linux/aer.h>
70c71606 45#include <linux/prefetch.h>
bc7f75fa
AK		 46
47#include "e1000.h"
48
b3ccf267 49#define DRV_EXTRAVERSION "-k"
c14c643b 50
d2d7d4e4 51#define DRV_VERSION "3.2.6" DRV_EXTRAVERSION
bc7f75fa
AK		 52char e1000e_driver_name[] = "e1000e";
53const char e1000e_driver_version[] = DRV_VERSION;
54
b3f4d599 55#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
56static int debug = -1;
57module_param(debug, int, 0);
58MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
bc7f75fa
AK		 60static const struct e1000_info *e1000_info_tbl[] = {
61 [board_82571] = &e1000_82571_info,
62 [board_82572] = &e1000_82572_info,
63 [board_82573] = &e1000_82573_info,
4662e82b 64 [board_82574] = &e1000_82574_info,
8c81c9c3 65 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 66 [board_80003es2lan] = &e1000_es2_info,
67 [board_ich8lan] = &e1000_ich8_info,
68 [board_ich9lan] = &e1000_ich9_info,
f4187b56 69 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 70 [board_pchlan] = &e1000_pch_info,
d3738bb8 71 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 72 [board_pch_lpt] = &e1000_pch_lpt_info,
79849ebc 73 [board_pch_spt] = &e1000_pch_spt_info,
bc7f75fa
AK		 74};
75
84f4ee90
TI		 76struct e1000_reg_info {
77 u32 ofs;
78 char *name;
79};
80
84f4ee90 81static const struct e1000_reg_info e1000_reg_info_tbl[] = {
84f4ee90
TI		 82 /* General Registers */
83 {E1000_CTRL, "CTRL"},
84 {E1000_STATUS, "STATUS"},
85 {E1000_CTRL_EXT, "CTRL_EXT"},
86
87 /* Interrupt Registers */
88 {E1000_ICR, "ICR"},
89
af667a29 90 /* Rx Registers */
84f4ee90 91 {E1000_RCTL, "RCTL"},
1e36052e
BA		 92 {E1000_RDLEN(0), "RDLEN"},
93 {E1000_RDH(0), "RDH"},
94 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 95 {E1000_RDTR, "RDTR"},
96 {E1000_RXDCTL(0), "RXDCTL"},
97 {E1000_ERT, "ERT"},
1e36052e
BA		 98 {E1000_RDBAL(0), "RDBAL"},
99 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 100 {E1000_RDFH, "RDFH"},
101 {E1000_RDFT, "RDFT"},
102 {E1000_RDFHS, "RDFHS"},
103 {E1000_RDFTS, "RDFTS"},
104 {E1000_RDFPC, "RDFPC"},
105
af667a29 106 /* Tx Registers */
84f4ee90 107 {E1000_TCTL, "TCTL"},
1e36052e
BA		 108 {E1000_TDBAL(0), "TDBAL"},
109 {E1000_TDBAH(0), "TDBAH"},
110 {E1000_TDLEN(0), "TDLEN"},
111 {E1000_TDH(0), "TDH"},
112 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 113 {E1000_TIDV, "TIDV"},
114 {E1000_TXDCTL(0), "TXDCTL"},
115 {E1000_TADV, "TADV"},
116 {E1000_TARC(0), "TARC"},
117 {E1000_TDFH, "TDFH"},
118 {E1000_TDFT, "TDFT"},
119 {E1000_TDFHS, "TDFHS"},
120 {E1000_TDFTS, "TDFTS"},
121 {E1000_TDFPC, "TDFPC"},
122
123 /* List Terminator */
f36bb6ca 124 {0, NULL}
84f4ee90
TI		 125};
126
c6f3148c
AK		 127/**
128 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
129 * @hw: pointer to the HW structure
130 *
131 * When updating the MAC CSR registers, the Manageability Engine (ME) could
132 * be accessing the registers at the same time. Normally, this is handled in
133 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
134 * accesses later than it should which could result in the register to have
135 * an incorrect value. Workaround this by checking the FWSM register which
136 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
137 * and try again a number of times.
138 **/
139s32 __ew32_prepare(struct e1000_hw *hw)
140{
141 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
142
143 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
144 udelay(50);
145
146 return i;
147}
148
149void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
150{
151 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
152 __ew32_prepare(hw);
153
154 writel(val, hw->hw_addr + reg);
155}
156
e921eb1a 157/**
84f4ee90 158 * e1000_regdump - register printout routine
e921eb1a
BA		 159 * @hw: pointer to the HW structure
160 * @reginfo: pointer to the register info table
161 **/
84f4ee90
TI		 162static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
163{
164 int n = 0;
165 char rname[16];
166 u32 regs[8];
167
168 switch (reginfo->ofs) {
169 case E1000_RXDCTL(0):
170 for (n = 0; n < 2; n++)
171 regs[n] = __er32(hw, E1000_RXDCTL(n));
172 break;
173 case E1000_TXDCTL(0):
174 for (n = 0; n < 2; n++)
175 regs[n] = __er32(hw, E1000_TXDCTL(n));
176 break;
177 case E1000_TARC(0):
178 for (n = 0; n < 2; n++)
179 regs[n] = __er32(hw, E1000_TARC(n));
180 break;
181 default:
ef456f85
JK		 182 pr_info("%-15s %08x\n",
183 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 184 return;
185 }
186
187 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 188 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 189}
190
f0c5dadf
ET		 191static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
192 struct e1000_buffer *bi)
193{
194 int i;
195 struct e1000_ps_page *ps_page;
196
197 for (i = 0; i < adapter->rx_ps_pages; i++) {
198 ps_page = &bi->ps_pages[i];
199
200 if (ps_page->page) {
201 pr_info("packet dump for ps_page %d:\n", i);
202 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
203 16, 1, page_address(ps_page->page),
204 PAGE_SIZE, true);
205 }
206 }
207}
208
e921eb1a 209/**
af667a29 210 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 211 * @adapter: board private structure
212 **/
84f4ee90
TI		 213static void e1000e_dump(struct e1000_adapter *adapter)
214{
215 struct net_device *netdev = adapter->netdev;
216 struct e1000_hw *hw = &adapter->hw;
217 struct e1000_reg_info *reginfo;
218 struct e1000_ring *tx_ring = adapter->tx_ring;
219 struct e1000_tx_desc *tx_desc;
af667a29 220 struct my_u0 {
e885d762
BA		 221 __le64 a;
222 __le64 b;
af667a29 223 } *u0;
84f4ee90
TI		 224 struct e1000_buffer *buffer_info;
225 struct e1000_ring *rx_ring = adapter->rx_ring;
226 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 227 union e1000_rx_desc_extended *rx_desc;
af667a29 228 struct my_u1 {
e885d762
BA		 229 __le64 a;
230 __le64 b;
231 __le64 c;
232 __le64 d;
af667a29 233 } *u1;
84f4ee90
TI		 234 u32 staterr;
235 int i = 0;
236
237 if (!netif_msg_hw(adapter))
238 return;
239
240 /* Print netdevice Info */
241 if (netdev) {
242 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85 243 pr_info("Device Name state trans_start last_rx\n");
e5fe2541
BA		 244 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
245 netdev->state, netdev->trans_start, netdev->last_rx);
84f4ee90
TI		 246 }
247
248 /* Print Registers */
249 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 250 pr_info(" Register Name Value\n");
84f4ee90
TI		 251 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
252 reginfo->name; reginfo++) {
253 e1000_regdump(hw, reginfo);
254 }
255
af667a29 256 /* Print Tx Ring Summary */
84f4ee90 257 if (!netdev || !netif_running(netdev))
fe1e980f 258 return;
84f4ee90 259
af667a29 260 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 261 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 262 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 263 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
264 0, tx_ring->next_to_use, tx_ring->next_to_clean,
265 (unsigned long long)buffer_info->dma,
266 buffer_info->length,
267 buffer_info->next_to_watch,
268 (unsigned long long)buffer_info->time_stamp);
84f4ee90 269
af667a29 270 /* Print Tx Ring */
84f4ee90
TI		 271 if (!netif_msg_tx_done(adapter))
272 goto rx_ring_summary;
273
af667a29 274 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 275
276 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
277 *
278 * Legacy Transmit Descriptor
279 * +--------------------------------------------------------------+
280 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
281 * +--------------------------------------------------------------+
282 * 8 | Special | CSS | Status | CMD | CSO | Length |
283 * +--------------------------------------------------------------+
284 * 63 48 47 36 35 32 31 24 23 16 15 0
285 *
286 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
287 * 63 48 47 40 39 32 31 16 15 8 7 0
288 * +----------------------------------------------------------------+
289 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
290 * +----------------------------------------------------------------+
291 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
292 * +----------------------------------------------------------------+
293 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
294 *
295 * Extended Data Descriptor (DTYP=0x1)
296 * +----------------------------------------------------------------+
297 * 0 | Buffer Address [63:0] |
298 * +----------------------------------------------------------------+
299 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
300 * +----------------------------------------------------------------+
301 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
302 */
ef456f85
JK		 303 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
304 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
305 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 306 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 307 const char *next_desc;
84f4ee90
TI		 308 tx_desc = E1000_TX_DESC(*tx_ring, i);
309 buffer_info = &tx_ring->buffer_info[i];
310 u0 = (struct my_u0 *)tx_desc;
84f4ee90 311 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 312 next_desc = " NTC/U";
84f4ee90 313 else if (i == tx_ring->next_to_use)
ef456f85 314 next_desc = " NTU";
84f4ee90 315 else if (i == tx_ring->next_to_clean)
ef456f85 316 next_desc = " NTC";
84f4ee90 317 else
ef456f85
JK		 318 next_desc = "";
319 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
320 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
321 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
322 i,
323 (unsigned long long)le64_to_cpu(u0->a),
324 (unsigned long long)le64_to_cpu(u0->b),
325 (unsigned long long)buffer_info->dma,
326 buffer_info->length, buffer_info->next_to_watch,
327 (unsigned long long)buffer_info->time_stamp,
328 buffer_info->skb, next_desc);
84f4ee90 329
f0c5dadf 330 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 331 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 332 16, 1, buffer_info->skb->data,
333 buffer_info->skb->len, true);
84f4ee90
TI		 334 }
335
af667a29 336 /* Print Rx Ring Summary */
84f4ee90 337rx_ring_summary:
af667a29 338 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 339 pr_info("Queue [NTU] [NTC]\n");
340 pr_info(" %5d %5X %5X\n",
341 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 342
af667a29 343 /* Print Rx Ring */
84f4ee90 344 if (!netif_msg_rx_status(adapter))
fe1e980f 345 return;
84f4ee90 346
af667a29 347 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 348 switch (adapter->rx_ps_pages) {
349 case 1:
350 case 2:
351 case 3:
352 /* [Extended] Packet Split Receive Descriptor Format
353 *
354 * +-----------------------------------------------------+
355 * 0 | Buffer Address 0 [63:0] |
356 * +-----------------------------------------------------+
357 * 8 | Buffer Address 1 [63:0] |
358 * +-----------------------------------------------------+
359 * 16 | Buffer Address 2 [63:0] |
360 * +-----------------------------------------------------+
361 * 24 | Buffer Address 3 [63:0] |
362 * +-----------------------------------------------------+
363 */
ef456f85 364 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 365 /* [Extended] Receive Descriptor (Write-Back) Format
366 *
367 * 63 48 47 32 31 13 12 8 7 4 3 0
368 * +------------------------------------------------------+
369 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
370 * | Checksum | Ident | | Queue | | Type |
371 * +------------------------------------------------------+
372 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
373 * +------------------------------------------------------+
374 * 63 48 47 32 31 20 19 0
375 */
ef456f85 376 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 377 for (i = 0; i < rx_ring->count; i++) {
ef456f85 378 const char *next_desc;
84f4ee90
TI		 379 buffer_info = &rx_ring->buffer_info[i];
380 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
381 u1 = (struct my_u1 *)rx_desc_ps;
382 staterr =
af667a29 383 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 384
385 if (i == rx_ring->next_to_use)
386 next_desc = " NTU";
387 else if (i == rx_ring->next_to_clean)
388 next_desc = " NTC";
389 else
390 next_desc = "";
391
84f4ee90
TI		 392 if (staterr & E1000_RXD_STAT_DD) {
393 /* Descriptor Done */
ef456f85
JK		 394 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
395 "RWB", i,
396 (unsigned long long)le64_to_cpu(u1->a),
397 (unsigned long long)le64_to_cpu(u1->b),
398 (unsigned long long)le64_to_cpu(u1->c),
399 (unsigned long long)le64_to_cpu(u1->d),
400 buffer_info->skb, next_desc);
84f4ee90 401 } else {
ef456f85
JK		 402 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
403 "R ", i,
404 (unsigned long long)le64_to_cpu(u1->a),
405 (unsigned long long)le64_to_cpu(u1->b),
406 (unsigned long long)le64_to_cpu(u1->c),
407 (unsigned long long)le64_to_cpu(u1->d),
408 (unsigned long long)buffer_info->dma,
409 buffer_info->skb, next_desc);
84f4ee90
TI		 410
411 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 412 e1000e_dump_ps_pages(adapter,
413 buffer_info);
84f4ee90 414 }
84f4ee90
TI		 415 }
416 break;
417 default:
418 case 0:
5f450212 419 /* Extended Receive Descriptor (Read) Format
84f4ee90 420 *
5f450212
BA		 421 * +-----------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +-----------------------------------------------------+
424 * 8 | Reserved |
425 * +-----------------------------------------------------+
84f4ee90 426 */
ef456f85 427 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 428 /* Extended Receive Descriptor (Write-Back) Format
429 *
430 * 63 48 47 32 31 24 23 4 3 0
431 * +------------------------------------------------------+
432 * | RSS Hash | | | |
433 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
434 * | Packet | IP | | | Type |
435 * | Checksum | Ident | | | |
436 * +------------------------------------------------------+
437 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
438 * +------------------------------------------------------+
439 * 63 48 47 32 31 20 19 0
440 */
ef456f85 441 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 442
443 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 444 const char *next_desc;
445
84f4ee90 446 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 447 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
448 u1 = (struct my_u1 *)rx_desc;
449 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 450
451 if (i == rx_ring->next_to_use)
452 next_desc = " NTU";
453 else if (i == rx_ring->next_to_clean)
454 next_desc = " NTC";
455 else
456 next_desc = "";
457
5f450212
BA		 458 if (staterr & E1000_RXD_STAT_DD) {
459 /* Descriptor Done */
ef456f85
JK		 460 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
461 "RWB", i,
462 (unsigned long long)le64_to_cpu(u1->a),
463 (unsigned long long)le64_to_cpu(u1->b),
464 buffer_info->skb, next_desc);
5f450212 465 } else {
ef456f85
JK		 466 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
467 "R ", i,
468 (unsigned long long)le64_to_cpu(u1->a),
469 (unsigned long long)le64_to_cpu(u1->b),
470 (unsigned long long)buffer_info->dma,
471 buffer_info->skb, next_desc);
5f450212 472
f0c5dadf
ET		 473 if (netif_msg_pktdata(adapter) &&
474 buffer_info->skb)
5f450212
BA		 475 print_hex_dump(KERN_INFO, "",
476 DUMP_PREFIX_ADDRESS, 16,
477 1,
f0c5dadf 478 buffer_info->skb->data,
5f450212
BA		 479 adapter->rx_buffer_len,
480 true);
481 }
84f4ee90
TI		 482 }
483 }
84f4ee90
TI		 484}
485
bc7f75fa
AK		 486/**
487 * e1000_desc_unused - calculate if we have unused descriptors
488 **/
489static int e1000_desc_unused(struct e1000_ring *ring)
490{
491 if (ring->next_to_clean > ring->next_to_use)
492 return ring->next_to_clean - ring->next_to_use - 1;
493
494 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
495}
496
b67e1913
BA		 497/**
498 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
499 * @adapter: board private structure
500 * @hwtstamps: time stamp structure to update
501 * @systim: unsigned 64bit system time value.
502 *
503 * Convert the system time value stored in the RX/TXSTMP registers into a
504 * hwtstamp which can be used by the upper level time stamping functions.
505 *
506 * The 'systim_lock' spinlock is used to protect the consistency of the
507 * system time value. This is needed because reading the 64 bit time
508 * value involves reading two 32 bit registers. The first read latches the
509 * value.
510 **/
511static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
512 struct skb_shared_hwtstamps *hwtstamps,
513 u64 systim)
514{
515 u64 ns;
516 unsigned long flags;
517
518 spin_lock_irqsave(&adapter->systim_lock, flags);
519 ns = timecounter_cyc2time(&adapter->tc, systim);
520 spin_unlock_irqrestore(&adapter->systim_lock, flags);
521
522 memset(hwtstamps, 0, sizeof(*hwtstamps));
523 hwtstamps->hwtstamp = ns_to_ktime(ns);
524}
525
526/**
527 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
528 * @adapter: board private structure
529 * @status: descriptor extended error and status field
530 * @skb: particular skb to include time stamp
531 *
532 * If the time stamp is valid, convert it into the timecounter ns value
533 * and store that result into the shhwtstamps structure which is passed
534 * up the network stack.
535 **/
536static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
537 struct sk_buff *skb)
538{
539 struct e1000_hw *hw = &adapter->hw;
540 u64 rxstmp;
541
542 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
543 !(status & E1000_RXDEXT_STATERR_TST) ||
544 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
545 return;
546
547 /* The Rx time stamp registers contain the time stamp. No other
548 * received packet will be time stamped until the Rx time stamp
549 * registers are read. Because only one packet can be time stamped
550 * at a time, the register values must belong to this packet and
551 * therefore none of the other additional attributes need to be
552 * compared.
553 */
554 rxstmp = (u64)er32(RXSTMPL);
555 rxstmp |= (u64)er32(RXSTMPH) << 32;
556 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
557
558 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
559}
560
bc7f75fa 561/**
ad68076e 562 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 563 * @adapter: board private structure
b67e1913 564 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 565 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
566 * @skb: pointer to sk_buff to be indicated to stack
567 **/
568static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 569 struct net_device *netdev, struct sk_buff *skb,
b67e1913 570 u32 staterr, __le16 vlan)
bc7f75fa 571{
86d70e53 572 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 573
574 e1000e_rx_hwtstamp(adapter, staterr, skb);
575
bc7f75fa
AK		 576 skb->protocol = eth_type_trans(skb, netdev);
577
b67e1913 578 if (staterr & E1000_RXD_STAT_VP)
86a9bad3 579 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
86d70e53
JK		 580
581 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 582}
583
584/**
af667a29 585 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 586 * @adapter: board private structure
587 * @status_err: receive descriptor status and error fields
588 * @csum: receive descriptor csum field
589 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 590 **/
591static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 592 struct sk_buff *skb)
bc7f75fa
AK		 593{
594 u16 status = (u16)status_err;
595 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 596
597 skb_checksum_none_assert(skb);
bc7f75fa 598
afd12939
BA		 599 /* Rx checksum disabled */
600 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
601 return;
602
bc7f75fa
AK		 603 /* Ignore Checksum bit is set */
604 if (status & E1000_RXD_STAT_IXSM)
605 return;
afd12939 606
2e1706f2
BA		 607 /* TCP/UDP checksum error bit or IP checksum error bit is set */
608 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 609 /* let the stack verify checksum errors */
610 adapter->hw_csum_err++;
611 return;
612 }
613
614 /* TCP/UDP Checksum has not been calculated */
615 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
616 return;
617
618 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 619 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 620 adapter->hw_csum_good++;
621}
622
55aa6985 623static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 624{
55aa6985 625 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 626 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 627 s32 ret_val = __ew32_prepare(hw);
628
629 writel(i, rx_ring->tail);
c6e7f51e 630
bdc125f7 631 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e 632 u32 rctl = er32(RCTL);
6cf08d1c 633
c6e7f51e
BA		 634 ew32(RCTL, rctl & ~E1000_RCTL_EN);
635 e_err("ME firmware caused invalid RDT - resetting\n");
636 schedule_work(&adapter->reset_task);
637 }
638}
639
55aa6985 640static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 641{
55aa6985 642 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 643 struct e1000_hw *hw = &adapter->hw;
bdc125f7 644 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 645
bdc125f7
BA		 646 writel(i, tx_ring->tail);
647
648 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e 649 u32 tctl = er32(TCTL);
6cf08d1c 650
c6e7f51e
BA		 651 ew32(TCTL, tctl & ~E1000_TCTL_EN);
652 e_err("ME firmware caused invalid TDT - resetting\n");
653 schedule_work(&adapter->reset_task);
654 }
655}
656
bc7f75fa 657/**
5f450212 658 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 659 * @rx_ring: Rx descriptor ring
bc7f75fa 660 **/
55aa6985 661static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 662 int cleaned_count, gfp_t gfp)
bc7f75fa 663{
55aa6985 664 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 665 struct net_device *netdev = adapter->netdev;
666 struct pci_dev *pdev = adapter->pdev;
5f450212 667 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 668 struct e1000_buffer *buffer_info;
669 struct sk_buff *skb;
670 unsigned int i;
89d71a66 671 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 672
673 i = rx_ring->next_to_use;
674 buffer_info = &rx_ring->buffer_info[i];
675
676 while (cleaned_count--) {
677 skb = buffer_info->skb;
678 if (skb) {
679 skb_trim(skb, 0);
680 goto map_skb;
681 }
682
c2fed996 683 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 684 if (!skb) {
685 /* Better luck next round */
686 adapter->alloc_rx_buff_failed++;
687 break;
688 }
689
bc7f75fa
AK		 690 buffer_info->skb = skb;
691map_skb:
0be3f55f 692 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 693 adapter->rx_buffer_len,
0be3f55f
NN		 694 DMA_FROM_DEVICE);
695 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 696 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 697 adapter->rx_dma_failed++;
698 break;
699 }
700
5f450212
BA		 701 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
702 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 703
50849d79 704 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 705 /* Force memory writes to complete before letting h/w
50849d79
TH		 706 * know there are new descriptors to fetch. (Only
707 * applicable for weak-ordered memory model archs,
708 * such as IA-64).
709 */
710 wmb();
c6e7f51e 711 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 712 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 713 else
c5083cf6 714 writel(i, rx_ring->tail);
50849d79 715 }
bc7f75fa
AK		 716 i++;
717 if (i == rx_ring->count)
718 i = 0;
719 buffer_info = &rx_ring->buffer_info[i];
720 }
721
50849d79 722 rx_ring->next_to_use = i;
bc7f75fa
AK		 723}
724
725/**
726 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 727 * @rx_ring: Rx descriptor ring
bc7f75fa 728 **/
55aa6985 729static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 730 int cleaned_count, gfp_t gfp)
bc7f75fa 731{
55aa6985 732 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 733 struct net_device *netdev = adapter->netdev;
734 struct pci_dev *pdev = adapter->pdev;
735 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 736 struct e1000_buffer *buffer_info;
737 struct e1000_ps_page *ps_page;
738 struct sk_buff *skb;
739 unsigned int i, j;
740
741 i = rx_ring->next_to_use;
742 buffer_info = &rx_ring->buffer_info[i];
743
744 while (cleaned_count--) {
745 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
746
747 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 748 ps_page = &buffer_info->ps_pages[j];
749 if (j >= adapter->rx_ps_pages) {
750 /* all unused desc entries get hw null ptr */
af667a29
BA		 751 rx_desc->read.buffer_addr[j + 1] =
752 ~cpu_to_le64(0);
47f44e40
AK		 753 continue;
754 }
755 if (!ps_page->page) {
c2fed996 756 ps_page->page = alloc_page(gfp);
bc7f75fa 757 if (!ps_page->page) {
47f44e40
AK		 758 adapter->alloc_rx_buff_failed++;
759 goto no_buffers;
760 }
0be3f55f
NN		 761 ps_page->dma = dma_map_page(&pdev->dev,
762 ps_page->page,
763 0, PAGE_SIZE,
764 DMA_FROM_DEVICE);
765 if (dma_mapping_error(&pdev->dev,
766 ps_page->dma)) {
47f44e40 767 dev_err(&adapter->pdev->dev,
af667a29 768 "Rx DMA page map failed\n");
47f44e40
AK		 769 adapter->rx_dma_failed++;
770 goto no_buffers;
bc7f75fa 771 }
bc7f75fa 772 }
e921eb1a 773 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 774 * didn't change because each write-back
775 * erases this info.
776 */
af667a29
BA		 777 rx_desc->read.buffer_addr[j + 1] =
778 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 779 }
780
e5fe2541 781 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
c2fed996 782 gfp);
bc7f75fa
AK		 783
784 if (!skb) {
785 adapter->alloc_rx_buff_failed++;
786 break;
787 }
788
bc7f75fa 789 buffer_info->skb = skb;
0be3f55f 790 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 791 adapter->rx_ps_bsize0,
0be3f55f
NN		 792 DMA_FROM_DEVICE);
793 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 794 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 795 adapter->rx_dma_failed++;
796 /* cleanup skb */
797 dev_kfree_skb_any(skb);
798 buffer_info->skb = NULL;
799 break;
800 }
801
802 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
803
50849d79 804 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 805 /* Force memory writes to complete before letting h/w
50849d79
TH		 806 * know there are new descriptors to fetch. (Only
807 * applicable for weak-ordered memory model archs,
808 * such as IA-64).
809 */
810 wmb();
c6e7f51e 811 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 812 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 813 else
c5083cf6 814 writel(i << 1, rx_ring->tail);
50849d79
TH		 815 }
816
bc7f75fa
AK		 817 i++;
818 if (i == rx_ring->count)
819 i = 0;
820 buffer_info = &rx_ring->buffer_info[i];
821 }
822
823no_buffers:
50849d79 824 rx_ring->next_to_use = i;
bc7f75fa
AK		 825}
826
97ac8cae
BA		 827/**
828 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 829 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 830 * @cleaned_count: number of buffers to allocate this pass
831 **/
832
55aa6985 833static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 834 int cleaned_count, gfp_t gfp)
97ac8cae 835{
55aa6985 836 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 837 struct net_device *netdev = adapter->netdev;
838 struct pci_dev *pdev = adapter->pdev;
5f450212 839 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 840 struct e1000_buffer *buffer_info;
841 struct sk_buff *skb;
842 unsigned int i;
2a2293b9 843 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 844
845 i = rx_ring->next_to_use;
846 buffer_info = &rx_ring->buffer_info[i];
847
848 while (cleaned_count--) {
849 skb = buffer_info->skb;
850 if (skb) {
851 skb_trim(skb, 0);
852 goto check_page;
853 }
854
c2fed996 855 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 856 if (unlikely(!skb)) {
857 /* Better luck next round */
858 adapter->alloc_rx_buff_failed++;
859 break;
860 }
861
97ac8cae
BA		 862 buffer_info->skb = skb;
863check_page:
864 /* allocate a new page if necessary */
865 if (!buffer_info->page) {
c2fed996 866 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 867 if (unlikely(!buffer_info->page)) {
868 adapter->alloc_rx_buff_failed++;
869 break;
870 }
871 }
872
37287fae 873 if (!buffer_info->dma) {
0be3f55f 874 buffer_info->dma = dma_map_page(&pdev->dev,
f0ff4398
BA		 875 buffer_info->page, 0,
876 PAGE_SIZE,
0be3f55f 877 DMA_FROM_DEVICE);
37287fae
CP		 878 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
879 adapter->alloc_rx_buff_failed++;
880 break;
881 }
882 }
97ac8cae 883
5f450212
BA		 884 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
885 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 886
887 if (unlikely(++i == rx_ring->count))
888 i = 0;
889 buffer_info = &rx_ring->buffer_info[i];
890 }
891
892 if (likely(rx_ring->next_to_use != i)) {
893 rx_ring->next_to_use = i;
894 if (unlikely(i-- == 0))
895 i = (rx_ring->count - 1);
896
897 /* Force memory writes to complete before letting h/w
898 * know there are new descriptors to fetch. (Only
899 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 900 * such as IA-64).
901 */
97ac8cae 902 wmb();
c6e7f51e 903 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 904 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 905 else
c5083cf6 906 writel(i, rx_ring->tail);
97ac8cae
BA		 907 }
908}
909
70495a50
BA		 910static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
911 struct sk_buff *skb)
912{
913 if (netdev->features & NETIF_F_RXHASH)
e25909bc 914 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
70495a50
BA		 915}
916
bc7f75fa 917/**
55aa6985
BA		 918 * e1000_clean_rx_irq - Send received data up the network stack
919 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 920 *
921 * the return value indicates whether actual cleaning was done, there
922 * is no guarantee that everything was cleaned
923 **/
55aa6985
BA		 924static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
925 int work_to_do)
bc7f75fa 926{
55aa6985 927 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 928 struct net_device *netdev = adapter->netdev;
929 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 930 struct e1000_hw *hw = &adapter->hw;
5f450212 931 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 932 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 933 u32 length, staterr;
bc7f75fa
AK		 934 unsigned int i;
935 int cleaned_count = 0;
3db1cd5c 936 bool cleaned = false;
bc7f75fa
AK		 937 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
938
939 i = rx_ring->next_to_clean;
5f450212
BA		 940 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
941 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 942 buffer_info = &rx_ring->buffer_info[i];
943
5f450212 944 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 945 struct sk_buff *skb;
bc7f75fa
AK		 946
947 if (*work_done >= work_to_do)
948 break;
949 (*work_done)++;
837a1dba 950 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 951
bc7f75fa
AK		 952 skb = buffer_info->skb;
953 buffer_info->skb = NULL;
954
955 prefetch(skb->data - NET_IP_ALIGN);
956
957 i++;
958 if (i == rx_ring->count)
959 i = 0;
5f450212 960 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 961 prefetch(next_rxd);
962
963 next_buffer = &rx_ring->buffer_info[i];
964
3db1cd5c 965 cleaned = true;
bc7f75fa 966 cleaned_count++;
e5fe2541
BA		 967 dma_unmap_single(&pdev->dev, buffer_info->dma,
968 adapter->rx_buffer_len, DMA_FROM_DEVICE);
bc7f75fa
AK		 969 buffer_info->dma = 0;
970
5f450212 971 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 972
e921eb1a 973 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 974 * packet, if that's the case we need to toss it. In fact, we
975 * need to toss every packet with the EOP bit clear and the
976 * next frame that _does_ have the EOP bit set, as it is by
977 * definition only a frame fragment
978 */
5f450212 979 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 980 adapter->flags2 |= FLAG2_IS_DISCARDING;
981
982 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 983 /* All receives must fit into a single buffer */
3bb99fe2 984 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 985 /* recycle */
986 buffer_info->skb = skb;
5f450212 987 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 988 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 989 goto next_desc;
990 }
991
cf955e6c
BG		 992 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
993 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 994 /* recycle */
995 buffer_info->skb = skb;
996 goto next_desc;
997 }
998
eb7c3adb 999 /* adjust length to remove Ethernet CRC */
0184039a
BG		 1000 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1001 /* If configured to store CRC, don't subtract FCS,
1002 * but keep the FCS bytes out of the total_rx_bytes
1003 * counter
1004 */
1005 if (netdev->features & NETIF_F_RXFCS)
1006 total_rx_bytes -= 4;
1007 else
1008 length -= 4;
1009 }
eb7c3adb 1010
bc7f75fa
AK		 1011 total_rx_bytes += length;
1012 total_rx_packets++;
1013
e921eb1a 1014 /* code added for copybreak, this should improve
bc7f75fa 1015 * performance for small packets with large amounts
ad68076e
BA		 1016 * of reassembly being done in the stack
1017 */
bc7f75fa
AK		 1018 if (length < copybreak) {
1019 struct sk_buff *new_skb =
67fd893e 1020 napi_alloc_skb(&adapter->napi, length);
bc7f75fa 1021 if (new_skb) {
808ff676
BA		 1022 skb_copy_to_linear_data_offset(new_skb,
1023 -NET_IP_ALIGN,
1024 (skb->data -
1025 NET_IP_ALIGN),
1026 (length +
1027 NET_IP_ALIGN));
bc7f75fa
AK		 1028 /* save the skb in buffer_info as good */
1029 buffer_info->skb = skb;
1030 skb = new_skb;
1031 }
1032 /* else just continue with the old one */
1033 }
1034 /* end copybreak code */
1035 skb_put(skb, length);
1036
1037 /* Receive Checksum Offload */
2e1706f2 1038 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1039
70495a50
BA		 1040 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1041
5f450212
BA		 1042 e1000_receive_skb(adapter, netdev, skb, staterr,
1043 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1044
1045next_desc:
5f450212 1046 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1047
1048 /* return some buffers to hardware, one at a time is too slow */
1049 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1050 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1051 GFP_ATOMIC);
bc7f75fa
AK		 1052 cleaned_count = 0;
1053 }
1054
1055 /* use prefetched values */
1056 rx_desc = next_rxd;
1057 buffer_info = next_buffer;
5f450212
BA		 1058
1059 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1060 }
1061 rx_ring->next_to_clean = i;
1062
1063 cleaned_count = e1000_desc_unused(rx_ring);
1064 if (cleaned_count)
55aa6985 1065 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1066
bc7f75fa 1067 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1068 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1069 return cleaned;
1070}
1071
55aa6985
BA		 1072static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1073 struct e1000_buffer *buffer_info)
bc7f75fa 1074{
55aa6985
BA		 1075 struct e1000_adapter *adapter = tx_ring->adapter;
1076
03b1320d
AD		 1077 if (buffer_info->dma) {
1078 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1079 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1080 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1081 else
0be3f55f
NN		 1082 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1083 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1084 buffer_info->dma = 0;
1085 }
bc7f75fa
AK		 1086 if (buffer_info->skb) {
1087 dev_kfree_skb_any(buffer_info->skb);
1088 buffer_info->skb = NULL;
1089 }
1b7719c4 1090 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1091}
1092
41cec6f1 1093static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1094{
41cec6f1 1095 struct e1000_adapter *adapter = container_of(work,
f0ff4398
BA		 1096 struct e1000_adapter,
1097 print_hang_task);
09357b00 1098 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1099 struct e1000_ring *tx_ring = adapter->tx_ring;
1100 unsigned int i = tx_ring->next_to_clean;
1101 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1102 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1103 struct e1000_hw *hw = &adapter->hw;
1104 u16 phy_status, phy_1000t_status, phy_ext_status;
1105 u16 pci_status;
1106
615b32af
JB		 1107 if (test_bit(__E1000_DOWN, &adapter->state))
1108 return;
1109
e5fe2541 1110 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1111 /* May be block on write-back, flush and detect again
09357b00
JK		 1112 * flush pending descriptor writebacks to memory
1113 */
1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1115 /* execute the writes immediately */
1116 e1e_flush();
e921eb1a 1117 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1118 * the write is successful
1119 */
1120 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1121 /* execute the writes immediately */
1122 e1e_flush();
09357b00
JK		 1123 adapter->tx_hang_recheck = true;
1124 return;
1125 }
09357b00 1126 adapter->tx_hang_recheck = false;
d9554e96
DE		 1127
1128 if (er32(TDH(0)) == er32(TDT(0))) {
1129 e_dbg("false hang detected, ignoring\n");
1130 return;
1131 }
1132
1133 /* Real hang detected */
09357b00
JK		 1134 netif_stop_queue(netdev);
1135
c2ade1a4
BA		 1136 e1e_rphy(hw, MII_BMSR, &phy_status);
1137 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1138 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
bc7f75fa 1139
41cec6f1
BA		 1140 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1141
1142 /* detected Hardware unit hang */
1143 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1144 " TDH <%x>\n"
1145 " TDT <%x>\n"
1146 " next_to_use <%x>\n"
1147 " next_to_clean <%x>\n"
1148 "buffer_info[next_to_clean]:\n"
1149 " time_stamp <%lx>\n"
1150 " next_to_watch <%x>\n"
1151 " jiffies <%lx>\n"
41cec6f1
BA		 1152 " next_to_watch.status <%x>\n"
1153 "MAC Status <%x>\n"
1154 "PHY Status <%x>\n"
1155 "PHY 1000BASE-T Status <%x>\n"
1156 "PHY Extended Status <%x>\n"
1157 "PCI Status <%x>\n",
e5fe2541
BA		 1158 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1159 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1160 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1161 phy_status, phy_1000t_status, phy_ext_status, pci_status);
7c0427ee 1162
d9554e96
DE		 1163 e1000e_dump(adapter);
1164
7c0427ee
BA		 1165 /* Suggest workaround for known h/w issue */
1166 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1167 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1168}
1169
b67e1913
BA		 1170/**
1171 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1172 * @work: pointer to work struct
1173 *
1174 * This work function polls the TSYNCTXCTL valid bit to determine when a
1175 * timestamp has been taken for the current stored skb. The timestamp must
1176 * be for this skb because only one such packet is allowed in the queue.
1177 */
1178static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1179{
1180 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1181 tx_hwtstamp_work);
1182 struct e1000_hw *hw = &adapter->hw;
1183
b67e1913
BA		 1184 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1185 struct skb_shared_hwtstamps shhwtstamps;
1186 u64 txstmp;
1187
1188 txstmp = er32(TXSTMPL);
1189 txstmp |= (u64)er32(TXSTMPH) << 32;
1190
1191 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1192
1193 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1194 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1195 adapter->tx_hwtstamp_skb = NULL;
59c871c5
JK		 1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1197 + adapter->tx_timeout_factor * HZ)) {
1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1199 adapter->tx_hwtstamp_skb = NULL;
1200 adapter->tx_hwtstamp_timeouts++;
c5ffe7e1 1201 e_warn("clearing Tx timestamp hang\n");
b67e1913
BA		 1202 } else {
1203 /* reschedule to check later */
1204 schedule_work(&adapter->tx_hwtstamp_work);
1205 }
1206}
1207
bc7f75fa
AK		 1208/**
1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1210 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1211 *
1212 * the return value indicates whether actual cleaning was done, there
1213 * is no guarantee that everything was cleaned
1214 **/
55aa6985 1215static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1216{
55aa6985 1217 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1218 struct net_device *netdev = adapter->netdev;
1219 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1220 struct e1000_tx_desc *tx_desc, *eop_desc;
1221 struct e1000_buffer *buffer_info;
1222 unsigned int i, eop;
1223 unsigned int count = 0;
bc7f75fa 1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1225 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1226
1227 i = tx_ring->next_to_clean;
1228 eop = tx_ring->buffer_info[i].next_to_watch;
1229 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1230
12d04a3c
AD		 1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1232 (count < tx_ring->count)) {
a86043c2 1233 bool cleaned = false;
6cf08d1c 1234
837a1dba 1235 dma_rmb(); /* read buffer_info after eop_desc */
a86043c2 1236 for (; !cleaned; count++) {
bc7f75fa
AK		 1237 tx_desc = E1000_TX_DESC(*tx_ring, i);
1238 buffer_info = &tx_ring->buffer_info[i];
1239 cleaned = (i == eop);
1240
1241 if (cleaned) {
9ed318d5
TH		 1242 total_tx_packets += buffer_info->segs;
1243 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1244 if (buffer_info->skb) {
1245 bytes_compl += buffer_info->skb->len;
1246 pkts_compl++;
1247 }
bc7f75fa
AK		 1248 }
1249
55aa6985 1250 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1251 tx_desc->upper.data = 0;
1252
1253 i++;
1254 if (i == tx_ring->count)
1255 i = 0;
1256 }
1257
dac87619
TL		 1258 if (i == tx_ring->next_to_use)
1259 break;
bc7f75fa
AK		 1260 eop = tx_ring->buffer_info[i].next_to_watch;
1261 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1262 }
1263
1264 tx_ring->next_to_clean = i;
1265
3f0cfa3b
TH		 1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1267
bc7f75fa 1268#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1269 if (count && netif_carrier_ok(netdev) &&
1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1271 /* Make sure that anybody stopping the queue after this
1272 * sees the new next_to_clean.
1273 */
1274 smp_mb();
1275
1276 if (netif_queue_stopped(netdev) &&
1277 !(test_bit(__E1000_DOWN, &adapter->state))) {
1278 netif_wake_queue(netdev);
1279 ++adapter->restart_queue;
1280 }
1281 }
1282
1283 if (adapter->detect_tx_hung) {
e921eb1a 1284 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1285 * check with the clearing of time_stamp and movement of i
1286 */
3db1cd5c 1287 adapter->detect_tx_hung = false;
12d04a3c
AD		 1288 if (tx_ring->buffer_info[i].time_stamp &&
1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1290 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1291 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1292 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1293 else
1294 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1295 }
1296 adapter->total_tx_bytes += total_tx_bytes;
1297 adapter->total_tx_packets += total_tx_packets;
807540ba 1298 return count < tx_ring->count;
bc7f75fa
AK		 1299}
1300
bc7f75fa
AK		 1301/**
1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1303 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1304 *
1305 * the return value indicates whether actual cleaning was done, there
1306 * is no guarantee that everything was cleaned
1307 **/
55aa6985
BA		 1308static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1309 int work_to_do)
bc7f75fa 1310{
55aa6985 1311 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1312 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1313 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1314 struct net_device *netdev = adapter->netdev;
1315 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1316 struct e1000_buffer *buffer_info, *next_buffer;
1317 struct e1000_ps_page *ps_page;
1318 struct sk_buff *skb;
1319 unsigned int i, j;
1320 u32 length, staterr;
1321 int cleaned_count = 0;
3db1cd5c 1322 bool cleaned = false;
bc7f75fa
AK		 1323 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1324
1325 i = rx_ring->next_to_clean;
1326 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1327 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1328 buffer_info = &rx_ring->buffer_info[i];
1329
1330 while (staterr & E1000_RXD_STAT_DD) {
1331 if (*work_done >= work_to_do)
1332 break;
1333 (*work_done)++;
1334 skb = buffer_info->skb;
837a1dba 1335 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1336
1337 /* in the packet split case this is header only */
1338 prefetch(skb->data - NET_IP_ALIGN);
1339
1340 i++;
1341 if (i == rx_ring->count)
1342 i = 0;
1343 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1344 prefetch(next_rxd);
1345
1346 next_buffer = &rx_ring->buffer_info[i];
1347
3db1cd5c 1348 cleaned = true;
bc7f75fa 1349 cleaned_count++;
0be3f55f 1350 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1351 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1352 buffer_info->dma = 0;
1353
af667a29 1354 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1355 if (!(staterr & E1000_RXD_STAT_EOP))
1356 adapter->flags2 |= FLAG2_IS_DISCARDING;
1357
1358 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1359 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1360 dev_kfree_skb_irq(skb);
b94b5028
JB		 1361 if (staterr & E1000_RXD_STAT_EOP)
1362 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1363 goto next_desc;
1364 }
1365
cf955e6c
BG		 1366 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1367 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1368 dev_kfree_skb_irq(skb);
1369 goto next_desc;
1370 }
1371
1372 length = le16_to_cpu(rx_desc->wb.middle.length0);
1373
1374 if (!length) {
ef456f85 1375 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1376 dev_kfree_skb_irq(skb);
1377 goto next_desc;
1378 }
1379
1380 /* Good Receive */
1381 skb_put(skb, length);
1382
1383 {
e921eb1a 1384 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1385 * it more efficient than reusing j
1386 */
1387 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1388
e921eb1a 1389 /* page alloc/put takes too long and effects small
0e15df49
BA		 1390 * packet throughput, so unsplit small packets and
1391 * save the alloc/put only valid in softirq (napi)
1392 * context to call kmap_*
ad68076e 1393 */
0e15df49
BA		 1394 if (l1 && (l1 <= copybreak) &&
1395 ((length + l1) <= adapter->rx_ps_bsize0)) {
1396 u8 *vaddr;
1397
1398 ps_page = &buffer_info->ps_pages[0];
1399
e921eb1a 1400 /* there is no documentation about how to call
0e15df49
BA		 1401 * kmap_atomic, so we can't hold the mapping
1402 * very long
1403 */
1404 dma_sync_single_for_cpu(&pdev->dev,
1405 ps_page->dma,
1406 PAGE_SIZE,
1407 DMA_FROM_DEVICE);
9f393834 1408 vaddr = kmap_atomic(ps_page->page);
0e15df49 1409 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1410 kunmap_atomic(vaddr);
0e15df49
BA		 1411 dma_sync_single_for_device(&pdev->dev,
1412 ps_page->dma,
1413 PAGE_SIZE,
1414 DMA_FROM_DEVICE);
1415
1416 /* remove the CRC */
0184039a
BG		 1417 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1418 if (!(netdev->features & NETIF_F_RXFCS))
1419 l1 -= 4;
1420 }
0e15df49
BA		 1421
1422 skb_put(skb, l1);
1423 goto copydone;
e80bd1d1 1424 } /* if */
bc7f75fa
AK		 1425 }
1426
1427 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1428 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1429 if (!length)
1430 break;
1431
47f44e40 1432 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1433 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1434 DMA_FROM_DEVICE);
bc7f75fa
AK		 1435 ps_page->dma = 0;
1436 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1437 ps_page->page = NULL;
1438 skb->len += length;
1439 skb->data_len += length;
98a045d7 1440 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1441 }
1442
eb7c3adb
JK		 1443 /* strip the ethernet crc, problem is we're using pages now so
1444 * this whole operation can get a little cpu intensive
1445 */
0184039a
BG		 1446 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1447 if (!(netdev->features & NETIF_F_RXFCS))
1448 pskb_trim(skb, skb->len - 4);
1449 }
eb7c3adb 1450
bc7f75fa
AK		 1451copydone:
1452 total_rx_bytes += skb->len;
1453 total_rx_packets++;
1454
2e1706f2 1455 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1456
70495a50
BA		 1457 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1458
bc7f75fa 1459 if (rx_desc->wb.upper.header_status &
17e813ec 1460 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
bc7f75fa
AK		 1461 adapter->rx_hdr_split++;
1462
b67e1913
BA		 1463 e1000_receive_skb(adapter, netdev, skb, staterr,
1464 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1465
1466next_desc:
1467 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1468 buffer_info->skb = NULL;
1469
1470 /* return some buffers to hardware, one at a time is too slow */
1471 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1472 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1473 GFP_ATOMIC);
bc7f75fa
AK		 1474 cleaned_count = 0;
1475 }
1476
1477 /* use prefetched values */
1478 rx_desc = next_rxd;
1479 buffer_info = next_buffer;
1480
1481 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1482 }
1483 rx_ring->next_to_clean = i;
1484
1485 cleaned_count = e1000_desc_unused(rx_ring);
1486 if (cleaned_count)
55aa6985 1487 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1488
bc7f75fa 1489 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1490 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1491 return cleaned;
1492}
1493
97ac8cae
BA		 1494/**
1495 * e1000_consume_page - helper function
1496 **/
1497static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
66501f56 1498 u16 length)
97ac8cae
BA		 1499{
1500 bi->page = NULL;
1501 skb->len += length;
1502 skb->data_len += length;
98a045d7 1503 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1504}
1505
1506/**
1507 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1508 * @adapter: board private structure
1509 *
1510 * the return value indicates whether actual cleaning was done, there
1511 * is no guarantee that everything was cleaned
1512 **/
55aa6985
BA		 1513static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1514 int work_to_do)
97ac8cae 1515{
55aa6985 1516 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1517 struct net_device *netdev = adapter->netdev;
1518 struct pci_dev *pdev = adapter->pdev;
5f450212 1519 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1520 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1521 u32 length, staterr;
97ac8cae
BA		 1522 unsigned int i;
1523 int cleaned_count = 0;
1524 bool cleaned = false;
362e20ca 1525 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
17e813ec 1526 struct skb_shared_info *shinfo;
97ac8cae
BA		 1527
1528 i = rx_ring->next_to_clean;
5f450212
BA		 1529 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1530 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1531 buffer_info = &rx_ring->buffer_info[i];
1532
5f450212 1533 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1534 struct sk_buff *skb;
97ac8cae
BA		 1535
1536 if (*work_done >= work_to_do)
1537 break;
1538 (*work_done)++;
837a1dba 1539 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1540
97ac8cae
BA		 1541 skb = buffer_info->skb;
1542 buffer_info->skb = NULL;
1543
1544 ++i;
1545 if (i == rx_ring->count)
1546 i = 0;
5f450212 1547 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1548 prefetch(next_rxd);
1549
1550 next_buffer = &rx_ring->buffer_info[i];
1551
1552 cleaned = true;
1553 cleaned_count++;
0be3f55f
NN		 1554 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1555 DMA_FROM_DEVICE);
97ac8cae
BA		 1556 buffer_info->dma = 0;
1557
5f450212 1558 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1559
1560 /* errors is only valid for DD + EOP descriptors */
5f450212 1561 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1562 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1563 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1564 /* recycle both page and skb */
1565 buffer_info->skb = skb;
1566 /* an error means any chain goes out the window too */
1567 if (rx_ring->rx_skb_top)
1568 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1569 rx_ring->rx_skb_top = NULL;
1570 goto next_desc;
97ac8cae 1571 }
f0f1a172 1572#define rxtop (rx_ring->rx_skb_top)
5f450212 1573 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1574 /* this descriptor is only the beginning (or middle) */
1575 if (!rxtop) {
1576 /* this is the beginning of a chain */
1577 rxtop = skb;
1578 skb_fill_page_desc(rxtop, 0, buffer_info->page,
f0ff4398 1579 0, length);
97ac8cae
BA		 1580 } else {
1581 /* this is the middle of a chain */
17e813ec
BA		 1582 shinfo = skb_shinfo(rxtop);
1583 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1584 buffer_info->page, 0,
1585 length);
97ac8cae
BA		 1586 /* re-use the skb, only consumed the page */
1587 buffer_info->skb = skb;
1588 }
1589 e1000_consume_page(buffer_info, rxtop, length);
1590 goto next_desc;
1591 } else {
1592 if (rxtop) {
1593 /* end of the chain */
17e813ec
BA		 1594 shinfo = skb_shinfo(rxtop);
1595 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1596 buffer_info->page, 0,
1597 length);
97ac8cae 1598 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1599 * page
1600 */
97ac8cae
BA		 1601 buffer_info->skb = skb;
1602 skb = rxtop;
1603 rxtop = NULL;
1604 e1000_consume_page(buffer_info, skb, length);
1605 } else {
1606 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1607 * copybreak to save the put_page/alloc_page
1608 */
97ac8cae
BA		 1609 if (length <= copybreak &&
1610 skb_tailroom(skb) >= length) {
1611 u8 *vaddr;
4679026d 1612 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1613 memcpy(skb_tail_pointer(skb), vaddr,
1614 length);
4679026d 1615 kunmap_atomic(vaddr);
97ac8cae 1616 /* re-use the page, so don't erase
e921eb1a
BA		 1617 * buffer_info->page
1618 */
97ac8cae
BA		 1619 skb_put(skb, length);
1620 } else {
1621 skb_fill_page_desc(skb, 0,
f0ff4398
BA		 1622 buffer_info->page, 0,
1623 length);
97ac8cae 1624 e1000_consume_page(buffer_info, skb,
f0ff4398 1625 length);
97ac8cae
BA		 1626 }
1627 }
1628 }
1629
2e1706f2
BA		 1630 /* Receive Checksum Offload */
1631 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1632
70495a50
BA		 1633 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1634
97ac8cae
BA		 1635 /* probably a little skewed due to removing CRC */
1636 total_rx_bytes += skb->len;
1637 total_rx_packets++;
1638
1639 /* eth type trans needs skb->data to point to something */
1640 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1641 e_err("pskb_may_pull failed.\n");
ef5ab89c 1642 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1643 goto next_desc;
1644 }
1645
5f450212
BA		 1646 e1000_receive_skb(adapter, netdev, skb, staterr,
1647 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1648
1649next_desc:
5f450212 1650 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1651
1652 /* return some buffers to hardware, one at a time is too slow */
1653 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1654 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1655 GFP_ATOMIC);
97ac8cae
BA		 1656 cleaned_count = 0;
1657 }
1658
1659 /* use prefetched values */
1660 rx_desc = next_rxd;
1661 buffer_info = next_buffer;
5f450212
BA		 1662
1663 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1664 }
1665 rx_ring->next_to_clean = i;
1666
1667 cleaned_count = e1000_desc_unused(rx_ring);
1668 if (cleaned_count)
55aa6985 1669 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1670
1671 adapter->total_rx_bytes += total_rx_bytes;
1672 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1673 return cleaned;
1674}
1675
bc7f75fa
AK		 1676/**
1677 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1678 * @rx_ring: Rx descriptor ring
bc7f75fa 1679 **/
55aa6985 1680static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1681{
55aa6985 1682 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1683 struct e1000_buffer *buffer_info;
1684 struct e1000_ps_page *ps_page;
1685 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1686 unsigned int i, j;
1687
1688 /* Free all the Rx ring sk_buffs */
1689 for (i = 0; i < rx_ring->count; i++) {
1690 buffer_info = &rx_ring->buffer_info[i];
1691 if (buffer_info->dma) {
1692 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1693 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1694 adapter->rx_buffer_len,
0be3f55f 1695 DMA_FROM_DEVICE);
97ac8cae 1696 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1697 dma_unmap_page(&pdev->dev, buffer_info->dma,
f0ff4398 1698 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa 1699 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1700 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1701 adapter->rx_ps_bsize0,
0be3f55f 1702 DMA_FROM_DEVICE);
bc7f75fa
AK		 1703 buffer_info->dma = 0;
1704 }
1705
97ac8cae
BA		 1706 if (buffer_info->page) {
1707 put_page(buffer_info->page);
1708 buffer_info->page = NULL;
1709 }
1710
bc7f75fa
AK		 1711 if (buffer_info->skb) {
1712 dev_kfree_skb(buffer_info->skb);
1713 buffer_info->skb = NULL;
1714 }
1715
1716 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1717 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1718 if (!ps_page->page)
1719 break;
0be3f55f
NN		 1720 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1721 DMA_FROM_DEVICE);
bc7f75fa
AK		 1722 ps_page->dma = 0;
1723 put_page(ps_page->page);
1724 ps_page->page = NULL;
1725 }
1726 }
1727
1728 /* there also may be some cached data from a chained receive */
1729 if (rx_ring->rx_skb_top) {
1730 dev_kfree_skb(rx_ring->rx_skb_top);
1731 rx_ring->rx_skb_top = NULL;
1732 }
1733
bc7f75fa
AK		 1734 /* Zero out the descriptor ring */
1735 memset(rx_ring->desc, 0, rx_ring->size);
1736
1737 rx_ring->next_to_clean = 0;
1738 rx_ring->next_to_use = 0;
b94b5028 1739 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1740}
1741
a8f88ff5
JB		 1742static void e1000e_downshift_workaround(struct work_struct *work)
1743{
1744 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 1745 struct e1000_adapter,
1746 downshift_task);
a8f88ff5 1747
615b32af
JB		 1748 if (test_bit(__E1000_DOWN, &adapter->state))
1749 return;
1750
a8f88ff5
JB		 1751 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1752}
1753
bc7f75fa
AK		 1754/**
1755 * e1000_intr_msi - Interrupt Handler
1756 * @irq: interrupt number
1757 * @data: pointer to a network interface device structure
1758 **/
8bb62869 1759static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
bc7f75fa
AK		 1760{
1761 struct net_device *netdev = data;
1762 struct e1000_adapter *adapter = netdev_priv(netdev);
1763 struct e1000_hw *hw = &adapter->hw;
1764 u32 icr = er32(ICR);
1765
e921eb1a 1766 /* read ICR disables interrupts using IAM */
573cca8c 1767 if (icr & E1000_ICR_LSC) {
f92518dd 1768 hw->mac.get_link_status = true;
e921eb1a 1769 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1770 * disconnect (LSC) before accessing any PHY registers
1771 */
bc7f75fa
AK		 1772 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1773 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1774 schedule_work(&adapter->downshift_task);
bc7f75fa 1775
e921eb1a 1776 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1777 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1778 * adapter in watchdog
1779 */
bc7f75fa
AK		 1780 if (netif_carrier_ok(netdev) &&
1781 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1782 /* disable receives */
1783 u32 rctl = er32(RCTL);
6cf08d1c 1784
bc7f75fa 1785 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1786 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1787 }
1788 /* guard against interrupt when we're going down */
1789 if (!test_bit(__E1000_DOWN, &adapter->state))
1790 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1791 }
1792
94fb848b 1793 /* Reset on uncorrectable ECC error */
79849ebc
DE		 1794 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
1795 (hw->mac.type == e1000_pch_spt))) {
94fb848b
BA		 1796 u32 pbeccsts = er32(PBECCSTS);
1797
1798 adapter->corr_errors +=
1799 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1800 adapter->uncorr_errors +=
1801 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1802 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1803
1804 /* Do the reset outside of interrupt context */
1805 schedule_work(&adapter->reset_task);
1806
1807 /* return immediately since reset is imminent */
1808 return IRQ_HANDLED;
1809 }
1810
288379f0 1811 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1812 adapter->total_tx_bytes = 0;
1813 adapter->total_tx_packets = 0;
1814 adapter->total_rx_bytes = 0;
1815 adapter->total_rx_packets = 0;
288379f0 1816 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1817 }
1818
1819 return IRQ_HANDLED;
1820}
1821
1822/**
1823 * e1000_intr - Interrupt Handler
1824 * @irq: interrupt number
1825 * @data: pointer to a network interface device structure
1826 **/
8bb62869 1827static irqreturn_t e1000_intr(int __always_unused irq, void *data)
bc7f75fa
AK		 1828{
1829 struct net_device *netdev = data;
1830 struct e1000_adapter *adapter = netdev_priv(netdev);
1831 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1832 u32 rctl, icr = er32(ICR);
4662e82b 1833
a68ea775 1834 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
e80bd1d1 1835 return IRQ_NONE; /* Not our interrupt */
bc7f75fa 1836
e921eb1a 1837 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1838 * not set, then the adapter didn't send an interrupt
1839 */
bc7f75fa
AK		 1840 if (!(icr & E1000_ICR_INT_ASSERTED))
1841 return IRQ_NONE;
1842
e921eb1a 1843 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1844 * interrupts are masked. No need for the
1845 * IMC write
1846 */
bc7f75fa 1847
573cca8c 1848 if (icr & E1000_ICR_LSC) {
f92518dd 1849 hw->mac.get_link_status = true;
e921eb1a 1850 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1851 * disconnect (LSC) before accessing any PHY registers
1852 */
bc7f75fa
AK		 1853 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1854 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1855 schedule_work(&adapter->downshift_task);
bc7f75fa 1856
e921eb1a 1857 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1858 * For packet buffer work-around on link down event;
1859 * disable receives here in the ISR and
1860 * reset adapter in watchdog
1861 */
1862 if (netif_carrier_ok(netdev) &&
1863 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1864 /* disable receives */
1865 rctl = er32(RCTL);
1866 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1867 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1868 }
1869 /* guard against interrupt when we're going down */
1870 if (!test_bit(__E1000_DOWN, &adapter->state))
1871 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1872 }
1873
94fb848b 1874 /* Reset on uncorrectable ECC error */
79849ebc
DE		 1875 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
1876 (hw->mac.type == e1000_pch_spt))) {
94fb848b
BA		 1877 u32 pbeccsts = er32(PBECCSTS);
1878
1879 adapter->corr_errors +=
1880 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1881 adapter->uncorr_errors +=
1882 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1883 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1884
1885 /* Do the reset outside of interrupt context */
1886 schedule_work(&adapter->reset_task);
1887
1888 /* return immediately since reset is imminent */
1889 return IRQ_HANDLED;
1890 }
1891
288379f0 1892 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1893 adapter->total_tx_bytes = 0;
1894 adapter->total_tx_packets = 0;
1895 adapter->total_rx_bytes = 0;
1896 adapter->total_rx_packets = 0;
288379f0 1897 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1898 }
1899
1900 return IRQ_HANDLED;
1901}
1902
8bb62869 1903static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
4662e82b
BA		 1904{
1905 struct net_device *netdev = data;
1906 struct e1000_adapter *adapter = netdev_priv(netdev);
1907 struct e1000_hw *hw = &adapter->hw;
1908 u32 icr = er32(ICR);
1909
1910 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1911 if (!test_bit(__E1000_DOWN, &adapter->state))
1912 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1913 return IRQ_NONE;
1914 }
1915
1916 if (icr & adapter->eiac_mask)
1917 ew32(ICS, (icr & adapter->eiac_mask));
1918
1919 if (icr & E1000_ICR_OTHER) {
1920 if (!(icr & E1000_ICR_LSC))
1921 goto no_link_interrupt;
f92518dd 1922 hw->mac.get_link_status = true;
4662e82b
BA		 1923 /* guard against interrupt when we're going down */
1924 if (!test_bit(__E1000_DOWN, &adapter->state))
1925 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1926 }
1927
1928no_link_interrupt:
a3c69fef
JB		 1929 if (!test_bit(__E1000_DOWN, &adapter->state))
1930 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1931
1932 return IRQ_HANDLED;
1933}
1934
8bb62869 1935static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
4662e82b
BA		 1936{
1937 struct net_device *netdev = data;
1938 struct e1000_adapter *adapter = netdev_priv(netdev);
1939 struct e1000_hw *hw = &adapter->hw;
1940 struct e1000_ring *tx_ring = adapter->tx_ring;
1941
4662e82b
BA		 1942 adapter->total_tx_bytes = 0;
1943 adapter->total_tx_packets = 0;
1944
55aa6985 1945 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1946 /* Ring was not completely cleaned, so fire another interrupt */
1947 ew32(ICS, tx_ring->ims_val);
1948
1949 return IRQ_HANDLED;
1950}
1951
8bb62869 1952static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
4662e82b
BA		 1953{
1954 struct net_device *netdev = data;
1955 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1956 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1957
1958 /* Write the ITR value calculated at the end of the
1959 * previous interrupt.
1960 */
55aa6985
BA		 1961 if (rx_ring->set_itr) {
1962 writel(1000000000 / (rx_ring->itr_val * 256),
1963 rx_ring->itr_register);
1964 rx_ring->set_itr = 0;
4662e82b
BA		 1965 }
1966
288379f0 1967 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1968 adapter->total_rx_bytes = 0;
1969 adapter->total_rx_packets = 0;
288379f0 1970 __napi_schedule(&adapter->napi);
4662e82b
BA		 1971 }
1972 return IRQ_HANDLED;
1973}
1974
1975/**
1976 * e1000_configure_msix - Configure MSI-X hardware
1977 *
1978 * e1000_configure_msix sets up the hardware to properly
1979 * generate MSI-X interrupts.
1980 **/
1981static void e1000_configure_msix(struct e1000_adapter *adapter)
1982{
1983 struct e1000_hw *hw = &adapter->hw;
1984 struct e1000_ring *rx_ring = adapter->rx_ring;
1985 struct e1000_ring *tx_ring = adapter->tx_ring;
1986 int vector = 0;
1987 u32 ctrl_ext, ivar = 0;
1988
1989 adapter->eiac_mask = 0;
1990
1991 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1992 if (hw->mac.type == e1000_82574) {
1993 u32 rfctl = er32(RFCTL);
6cf08d1c 1994
4662e82b
BA		 1995 rfctl |= E1000_RFCTL_ACK_DIS;
1996 ew32(RFCTL, rfctl);
1997 }
1998
4662e82b
BA		 1999 /* Configure Rx vector */
2000 rx_ring->ims_val = E1000_IMS_RXQ0;
2001 adapter->eiac_mask |= rx_ring->ims_val;
2002 if (rx_ring->itr_val)
2003 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 2004 rx_ring->itr_register);
4662e82b 2005 else
c5083cf6 2006 writel(1, rx_ring->itr_register);
4662e82b
BA		 2007 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
2008
2009 /* Configure Tx vector */
2010 tx_ring->ims_val = E1000_IMS_TXQ0;
2011 vector++;
2012 if (tx_ring->itr_val)
2013 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 2014 tx_ring->itr_register);
4662e82b 2015 else
c5083cf6 2016 writel(1, tx_ring->itr_register);
4662e82b
BA		 2017 adapter->eiac_mask |= tx_ring->ims_val;
2018 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2019
2020 /* set vector for Other Causes, e.g. link changes */
2021 vector++;
2022 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2023 if (rx_ring->itr_val)
2024 writel(1000000000 / (rx_ring->itr_val * 256),
2025 hw->hw_addr + E1000_EITR_82574(vector));
2026 else
2027 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
2028
2029 /* Cause Tx interrupts on every write back */
2030 ivar |= (1 << 31);
2031
2032 ew32(IVAR, ivar);
2033
2034 /* enable MSI-X PBA support */
2035 ctrl_ext = er32(CTRL_EXT);
2036 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2037
2038 /* Auto-Mask Other interrupts upon ICR read */
4662e82b
BA		 2039 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2040 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2041 ew32(CTRL_EXT, ctrl_ext);
2042 e1e_flush();
2043}
2044
2045void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2046{
2047 if (adapter->msix_entries) {
2048 pci_disable_msix(adapter->pdev);
2049 kfree(adapter->msix_entries);
2050 adapter->msix_entries = NULL;
2051 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2052 pci_disable_msi(adapter->pdev);
2053 adapter->flags &= ~FLAG_MSI_ENABLED;
2054 }
4662e82b
BA		 2055}
2056
2057/**
2058 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2059 *
2060 * Attempt to configure interrupts using the best available
2061 * capabilities of the hardware and kernel.
2062 **/
2063void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2064{
2065 int err;
8e86acd7 2066 int i;
4662e82b
BA		 2067
2068 switch (adapter->int_mode) {
2069 case E1000E_INT_MODE_MSIX:
2070 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2071 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2072 adapter->msix_entries = kcalloc(adapter->num_vectors,
17e813ec
BA		 2073 sizeof(struct
2074 msix_entry),
2075 GFP_KERNEL);
4662e82b 2076 if (adapter->msix_entries) {
0cc7c959
AG		 2077 struct e1000_adapter *a = adapter;
2078
8e86acd7 2079 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2080 adapter->msix_entries[i].entry = i;
2081
0cc7c959
AG		 2082 err = pci_enable_msix_range(a->pdev,
2083 a->msix_entries,
2084 a->num_vectors,
2085 a->num_vectors);
2086 if (err > 0)
4662e82b
BA		 2087 return;
2088 }
2089 /* MSI-X failed, so fall through and try MSI */
ef456f85 2090 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2091 e1000e_reset_interrupt_capability(adapter);
2092 }
2093 adapter->int_mode = E1000E_INT_MODE_MSI;
2094 /* Fall through */
2095 case E1000E_INT_MODE_MSI:
2096 if (!pci_enable_msi(adapter->pdev)) {
2097 adapter->flags |= FLAG_MSI_ENABLED;
2098 } else {
2099 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2100 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2101 }
2102 /* Fall through */
2103 case E1000E_INT_MODE_LEGACY:
2104 /* Don't do anything; this is the system default */
2105 break;
2106 }
8e86acd7
JK		 2107
2108 /* store the number of vectors being used */
2109 adapter->num_vectors = 1;
4662e82b
BA		 2110}
2111
2112/**
2113 * e1000_request_msix - Initialize MSI-X interrupts
2114 *
2115 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2116 * kernel.
2117 **/
2118static int e1000_request_msix(struct e1000_adapter *adapter)
2119{
2120 struct net_device *netdev = adapter->netdev;
2121 int err = 0, vector = 0;
2122
2123 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2124 snprintf(adapter->rx_ring->name,
2125 sizeof(adapter->rx_ring->name) - 1,
2126 "%s-rx-0", netdev->name);
4662e82b
BA		 2127 else
2128 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2129 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2130 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2131 netdev);
2132 if (err)
5015e53a 2133 return err;
c5083cf6
BA		 2134 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2135 E1000_EITR_82574(vector);
4662e82b
BA		 2136 adapter->rx_ring->itr_val = adapter->itr;
2137 vector++;
2138
2139 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2140 snprintf(adapter->tx_ring->name,
2141 sizeof(adapter->tx_ring->name) - 1,
2142 "%s-tx-0", netdev->name);
4662e82b
BA		 2143 else
2144 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2145 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2146 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2147 netdev);
2148 if (err)
5015e53a 2149 return err;
c5083cf6
BA		 2150 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2151 E1000_EITR_82574(vector);
4662e82b
BA		 2152 adapter->tx_ring->itr_val = adapter->itr;
2153 vector++;
2154
2155 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2156 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2157 if (err)
5015e53a 2158 return err;
4662e82b
BA		 2159
2160 e1000_configure_msix(adapter);
5015e53a 2161
4662e82b 2162 return 0;
4662e82b
BA		 2163}
2164
f8d59f78
BA		 2165/**
2166 * e1000_request_irq - initialize interrupts
2167 *
2168 * Attempts to configure interrupts using the best available
2169 * capabilities of the hardware and kernel.
2170 **/
bc7f75fa
AK		 2171static int e1000_request_irq(struct e1000_adapter *adapter)
2172{
2173 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2174 int err;
2175
4662e82b
BA		 2176 if (adapter->msix_entries) {
2177 err = e1000_request_msix(adapter);
2178 if (!err)
2179 return err;
2180 /* fall back to MSI */
2181 e1000e_reset_interrupt_capability(adapter);
2182 adapter->int_mode = E1000E_INT_MODE_MSI;
2183 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2184 }
4662e82b 2185 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2186 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2187 netdev->name, netdev);
2188 if (!err)
2189 return err;
bc7f75fa 2190
4662e82b
BA		 2191 /* fall back to legacy interrupt */
2192 e1000e_reset_interrupt_capability(adapter);
2193 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2194 }
2195
a0607fd3 2196 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2197 netdev->name, netdev);
2198 if (err)
2199 e_err("Unable to allocate interrupt, Error: %d\n", err);
2200
bc7f75fa
AK		 2201 return err;
2202}
2203
2204static void e1000_free_irq(struct e1000_adapter *adapter)
2205{
2206 struct net_device *netdev = adapter->netdev;
2207
4662e82b
BA		 2208 if (adapter->msix_entries) {
2209 int vector = 0;
2210
2211 free_irq(adapter->msix_entries[vector].vector, netdev);
2212 vector++;
2213
2214 free_irq(adapter->msix_entries[vector].vector, netdev);
2215 vector++;
2216
2217 /* Other Causes interrupt vector */
2218 free_irq(adapter->msix_entries[vector].vector, netdev);
2219 return;
bc7f75fa 2220 }
4662e82b
BA		 2221
2222 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2223}
2224
2225/**
2226 * e1000_irq_disable - Mask off interrupt generation on the NIC
2227 **/
2228static void e1000_irq_disable(struct e1000_adapter *adapter)
2229{
2230 struct e1000_hw *hw = &adapter->hw;
2231
bc7f75fa 2232 ew32(IMC, ~0);
4662e82b
BA		 2233 if (adapter->msix_entries)
2234 ew32(EIAC_82574, 0);
bc7f75fa 2235 e1e_flush();
8e86acd7
JK		 2236
2237 if (adapter->msix_entries) {
2238 int i;
6cf08d1c 2239
8e86acd7
JK		 2240 for (i = 0; i < adapter->num_vectors; i++)
2241 synchronize_irq(adapter->msix_entries[i].vector);
2242 } else {
2243 synchronize_irq(adapter->pdev->irq);
2244 }
bc7f75fa
AK		 2245}
2246
2247/**
2248 * e1000_irq_enable - Enable default interrupt generation settings
2249 **/
2250static void e1000_irq_enable(struct e1000_adapter *adapter)
2251{
2252 struct e1000_hw *hw = &adapter->hw;
2253
4662e82b
BA		 2254 if (adapter->msix_entries) {
2255 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2256 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
79849ebc
DE		 2257 } else if ((hw->mac.type == e1000_pch_lpt) ||
2258 (hw->mac.type == e1000_pch_spt)) {
94fb848b 2259 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2260 } else {
2261 ew32(IMS, IMS_ENABLE_MASK);
2262 }
74ef9c39 2263 e1e_flush();
bc7f75fa
AK		 2264}
2265
2266/**
31dbe5b4 2267 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2268 * @adapter: address of board private structure
2269 *
31dbe5b4 2270 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2271 * For ASF and Pass Through versions of f/w this means that
2272 * the driver is loaded. For AMT version (only with 82573)
2273 * of the f/w this means that the network i/f is open.
2274 **/
31dbe5b4 2275void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2276{
2277 struct e1000_hw *hw = &adapter->hw;
2278 u32 ctrl_ext;
2279 u32 swsm;
2280
2281 /* Let firmware know the driver has taken over */
2282 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2283 swsm = er32(SWSM);
2284 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2285 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2286 ctrl_ext = er32(CTRL_EXT);
ad68076e 2287 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2288 }
2289}
2290
2291/**
31dbe5b4 2292 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2293 * @adapter: address of board private structure
2294 *
31dbe5b4 2295 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2296 * For ASF and Pass Through versions of f/w this means that the
2297 * driver is no longer loaded. For AMT version (only with 82573) i
2298 * of the f/w this means that the network i/f is closed.
2299 *
2300 **/
31dbe5b4 2301void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2302{
2303 struct e1000_hw *hw = &adapter->hw;
2304 u32 ctrl_ext;
2305 u32 swsm;
2306
2307 /* Let firmware taken over control of h/w */
2308 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2309 swsm = er32(SWSM);
2310 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2311 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2312 ctrl_ext = er32(CTRL_EXT);
ad68076e 2313 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2314 }
2315}
2316
bc7f75fa 2317/**
49ce9c2c 2318 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2319 **/
2320static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2321 struct e1000_ring *ring)
2322{
2323 struct pci_dev *pdev = adapter->pdev;
2324
2325 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2326 GFP_KERNEL);
2327 if (!ring->desc)
2328 return -ENOMEM;
2329
2330 return 0;
2331}
2332
2333/**
2334 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2335 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2336 *
2337 * Return 0 on success, negative on failure
2338 **/
55aa6985 2339int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2340{
55aa6985 2341 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2342 int err = -ENOMEM, size;
2343
2344 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2345 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2346 if (!tx_ring->buffer_info)
2347 goto err;
bc7f75fa
AK		 2348
2349 /* round up to nearest 4K */
2350 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2351 tx_ring->size = ALIGN(tx_ring->size, 4096);
2352
2353 err = e1000_alloc_ring_dma(adapter, tx_ring);
2354 if (err)
2355 goto err;
2356
2357 tx_ring->next_to_use = 0;
2358 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2359
2360 return 0;
2361err:
2362 vfree(tx_ring->buffer_info);
44defeb3 2363 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2364 return err;
2365}
2366
2367/**
2368 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2369 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2370 *
2371 * Returns 0 on success, negative on failure
2372 **/
55aa6985 2373int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2374{
55aa6985 2375 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2376 struct e1000_buffer *buffer_info;
2377 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2378
2379 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2380 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2381 if (!rx_ring->buffer_info)
2382 goto err;
bc7f75fa 2383
47f44e40
AK		 2384 for (i = 0; i < rx_ring->count; i++) {
2385 buffer_info = &rx_ring->buffer_info[i];
2386 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2387 sizeof(struct e1000_ps_page),
2388 GFP_KERNEL);
2389 if (!buffer_info->ps_pages)
2390 goto err_pages;
2391 }
bc7f75fa
AK		 2392
2393 desc_len = sizeof(union e1000_rx_desc_packet_split);
2394
2395 /* Round up to nearest 4K */
2396 rx_ring->size = rx_ring->count * desc_len;
2397 rx_ring->size = ALIGN(rx_ring->size, 4096);
2398
2399 err = e1000_alloc_ring_dma(adapter, rx_ring);
2400 if (err)
47f44e40 2401 goto err_pages;
bc7f75fa
AK		 2402
2403 rx_ring->next_to_clean = 0;
2404 rx_ring->next_to_use = 0;
2405 rx_ring->rx_skb_top = NULL;
2406
2407 return 0;
47f44e40
AK		 2408
2409err_pages:
2410 for (i = 0; i < rx_ring->count; i++) {
2411 buffer_info = &rx_ring->buffer_info[i];
2412 kfree(buffer_info->ps_pages);
2413 }
bc7f75fa
AK		 2414err:
2415 vfree(rx_ring->buffer_info);
e9262447 2416 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2417 return err;
2418}
2419
2420/**
2421 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2422 * @tx_ring: Tx descriptor ring
bc7f75fa 2423 **/
55aa6985 2424static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2425{
55aa6985 2426 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2427 struct e1000_buffer *buffer_info;
2428 unsigned long size;
2429 unsigned int i;
2430
2431 for (i = 0; i < tx_ring->count; i++) {
2432 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2433 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2434 }
2435
3f0cfa3b 2436 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2437 size = sizeof(struct e1000_buffer) * tx_ring->count;
2438 memset(tx_ring->buffer_info, 0, size);
2439
2440 memset(tx_ring->desc, 0, tx_ring->size);
2441
2442 tx_ring->next_to_use = 0;
2443 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2444}
2445
2446/**
2447 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2448 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2449 *
2450 * Free all transmit software resources
2451 **/
55aa6985 2452void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2453{
55aa6985 2454 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2455 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2456
55aa6985 2457 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2458
2459 vfree(tx_ring->buffer_info);
2460 tx_ring->buffer_info = NULL;
2461
2462 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2463 tx_ring->dma);
2464 tx_ring->desc = NULL;
2465}
2466
2467/**
2468 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2469 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2470 *
2471 * Free all receive software resources
2472 **/
55aa6985 2473void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2474{
55aa6985 2475 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2476 struct pci_dev *pdev = adapter->pdev;
47f44e40 2477 int i;
bc7f75fa 2478
55aa6985 2479 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2480
b1cdfead 2481 for (i = 0; i < rx_ring->count; i++)
47f44e40 2482 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2483
bc7f75fa
AK		 2484 vfree(rx_ring->buffer_info);
2485 rx_ring->buffer_info = NULL;
2486
bc7f75fa
AK		 2487 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2488 rx_ring->dma);
2489 rx_ring->desc = NULL;
2490}
2491
2492/**
2493 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2494 * @adapter: pointer to adapter
2495 * @itr_setting: current adapter->itr
2496 * @packets: the number of packets during this measurement interval
2497 * @bytes: the number of bytes during this measurement interval
2498 *
bc7f75fa
AK		 2499 * Stores a new ITR value based on packets and byte
2500 * counts during the last interrupt. The advantage of per interrupt
2501 * computation is faster updates and more accurate ITR for the current
2502 * traffic pattern. Constants in this function were computed
2503 * based on theoretical maximum wire speed and thresholds were set based
2504 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2505 * while increasing bulk throughput. This functionality is controlled
2506 * by the InterruptThrottleRate module parameter.
bc7f75fa 2507 **/
8bb62869 2508static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
bc7f75fa
AK		 2509{
2510 unsigned int retval = itr_setting;
2511
2512 if (packets == 0)
5015e53a 2513 return itr_setting;
bc7f75fa
AK		 2514
2515 switch (itr_setting) {
2516 case lowest_latency:
2517 /* handle TSO and jumbo frames */
362e20ca 2518 if (bytes / packets > 8000)
bc7f75fa 2519 retval = bulk_latency;
b1cdfead 2520 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2521 retval = low_latency;
bc7f75fa 2522 break;
e80bd1d1 2523 case low_latency: /* 50 usec aka 20000 ints/s */
bc7f75fa
AK		 2524 if (bytes > 10000) {
2525 /* this if handles the TSO accounting */
362e20ca 2526 if (bytes / packets > 8000)
bc7f75fa 2527 retval = bulk_latency;
362e20ca 2528 else if ((packets < 10) || ((bytes / packets) > 1200))
bc7f75fa 2529 retval = bulk_latency;
b1cdfead 2530 else if ((packets > 35))
bc7f75fa 2531 retval = lowest_latency;
362e20ca 2532 } else if (bytes / packets > 2000) {
bc7f75fa
AK		 2533 retval = bulk_latency;
2534 } else if (packets <= 2 && bytes < 512) {
2535 retval = lowest_latency;
2536 }
2537 break;
e80bd1d1 2538 case bulk_latency: /* 250 usec aka 4000 ints/s */
bc7f75fa 2539 if (bytes > 25000) {
b1cdfead 2540 if (packets > 35)
bc7f75fa 2541 retval = low_latency;
bc7f75fa
AK		 2542 } else if (bytes < 6000) {
2543 retval = low_latency;
2544 }
2545 break;
2546 }
2547
bc7f75fa
AK		 2548 return retval;
2549}
2550
2551static void e1000_set_itr(struct e1000_adapter *adapter)
2552{
bc7f75fa
AK		 2553 u16 current_itr;
2554 u32 new_itr = adapter->itr;
2555
2556 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2557 if (adapter->link_speed != SPEED_1000) {
2558 current_itr = 0;
2559 new_itr = 4000;
2560 goto set_itr_now;
2561 }
2562
828bac87
BA		 2563 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2564 new_itr = 0;
2565 goto set_itr_now;
2566 }
2567
8bb62869
BA		 2568 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2569 adapter->total_tx_packets,
2570 adapter->total_tx_bytes);
bc7f75fa
AK		 2571 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2572 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2573 adapter->tx_itr = low_latency;
2574
8bb62869
BA		 2575 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2576 adapter->total_rx_packets,
2577 adapter->total_rx_bytes);
bc7f75fa
AK		 2578 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2579 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2580 adapter->rx_itr = low_latency;
2581
2582 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2583
bc7f75fa 2584 /* counts and packets in update_itr are dependent on these numbers */
33550cec 2585 switch (current_itr) {
bc7f75fa
AK		 2586 case lowest_latency:
2587 new_itr = 70000;
2588 break;
2589 case low_latency:
e80bd1d1 2590 new_itr = 20000; /* aka hwitr = ~200 */
bc7f75fa
AK		 2591 break;
2592 case bulk_latency:
2593 new_itr = 4000;
2594 break;
2595 default:
2596 break;
2597 }
2598
2599set_itr_now:
2600 if (new_itr != adapter->itr) {
e921eb1a 2601 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2602 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2603 * increasing
2604 */
bc7f75fa 2605 new_itr = new_itr > adapter->itr ?
f0ff4398 2606 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
bc7f75fa 2607 adapter->itr = new_itr;
4662e82b
BA		 2608 adapter->rx_ring->itr_val = new_itr;
2609 if (adapter->msix_entries)
2610 adapter->rx_ring->set_itr = 1;
2611 else
e3d14b08 2612 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2613 }
2614}
2615
22a4cca2
MV		 2616/**
2617 * e1000e_write_itr - write the ITR value to the appropriate registers
2618 * @adapter: address of board private structure
2619 * @itr: new ITR value to program
2620 *
2621 * e1000e_write_itr determines if the adapter is in MSI-X mode
2622 * and, if so, writes the EITR registers with the ITR value.
2623 * Otherwise, it writes the ITR value into the ITR register.
2624 **/
2625void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2626{
2627 struct e1000_hw *hw = &adapter->hw;
2628 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2629
2630 if (adapter->msix_entries) {
2631 int vector;
2632
2633 for (vector = 0; vector < adapter->num_vectors; vector++)
2634 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2635 } else {
2636 ew32(ITR, new_itr);
2637 }
2638}
2639
4662e82b
BA		 2640/**
2641 * e1000_alloc_queues - Allocate memory for all rings
2642 * @adapter: board private structure to initialize
2643 **/
9f9a12f8 2644static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2645{
55aa6985
BA		 2646 int size = sizeof(struct e1000_ring);
2647
2648 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2649 if (!adapter->tx_ring)
2650 goto err;
55aa6985
BA		 2651 adapter->tx_ring->count = adapter->tx_ring_count;
2652 adapter->tx_ring->adapter = adapter;
4662e82b 2653
55aa6985 2654 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2655 if (!adapter->rx_ring)
2656 goto err;
55aa6985
BA		 2657 adapter->rx_ring->count = adapter->rx_ring_count;
2658 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2659
2660 return 0;
2661err:
2662 e_err("Unable to allocate memory for queues\n");
2663 kfree(adapter->rx_ring);
2664 kfree(adapter->tx_ring);
2665 return -ENOMEM;
2666}
2667
bc7f75fa 2668/**
c58c8a78 2669 * e1000e_poll - NAPI Rx polling callback
ad68076e 2670 * @napi: struct associated with this polling callback
c58c8a78 2671 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2672 **/
c58c8a78 2673static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2674{
c58c8a78
BA		 2675 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2676 napi);
4662e82b 2677 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2678 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2679 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2680
4cf1653a 2681 adapter = netdev_priv(poll_dev);
bc7f75fa 2682
c58c8a78
BA		 2683 if (!adapter->msix_entries ||
2684 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2685 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2686
c58c8a78 2687 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2688
12d04a3c 2689 if (!tx_cleaned)
c58c8a78 2690 work_done = weight;
bc7f75fa 2691
c58c8a78
BA		 2692 /* If weight not fully consumed, exit the polling mode */
2693 if (work_done < weight) {
bc7f75fa
AK		 2694 if (adapter->itr_setting & 3)
2695 e1000_set_itr(adapter);
32b3e08f 2696 napi_complete_done(napi, work_done);
a3c69fef
JB		 2697 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2698 if (adapter->msix_entries)
2699 ew32(IMS, adapter->rx_ring->ims_val);
2700 else
2701 e1000_irq_enable(adapter);
2702 }
bc7f75fa
AK		 2703 }
2704
2705 return work_done;
2706}
2707
80d5c368 2708static int e1000_vlan_rx_add_vid(struct net_device *netdev,
603cdca9 2709 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2710{
2711 struct e1000_adapter *adapter = netdev_priv(netdev);
2712 struct e1000_hw *hw = &adapter->hw;
2713 u32 vfta, index;
2714
2715 /* don't update vlan cookie if already programmed */
2716 if ((adapter->hw.mng_cookie.status &
2717 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2718 (vid == adapter->mng_vlan_id))
8e586137 2719 return 0;
caaddaf8 2720
bc7f75fa 2721 /* add VID to filter table */
caaddaf8
BA		 2722 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2723 index = (vid >> 5) & 0x7F;
2724 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2725 vfta |= (1 << (vid & 0x1F));
2726 hw->mac.ops.write_vfta(hw, index, vfta);
2727 }
86d70e53
JK		 2728
2729 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2730
2731 return 0;
bc7f75fa
AK		 2732}
2733
80d5c368 2734static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
603cdca9 2735 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2736{
2737 struct e1000_adapter *adapter = netdev_priv(netdev);
2738 struct e1000_hw *hw = &adapter->hw;
2739 u32 vfta, index;
2740
bc7f75fa
AK		 2741 if ((adapter->hw.mng_cookie.status &
2742 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2743 (vid == adapter->mng_vlan_id)) {
2744 /* release control to f/w */
31dbe5b4 2745 e1000e_release_hw_control(adapter);
8e586137 2746 return 0;
bc7f75fa
AK		 2747 }
2748
2749 /* remove VID from filter table */
caaddaf8
BA		 2750 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2751 index = (vid >> 5) & 0x7F;
2752 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2753 vfta &= ~(1 << (vid & 0x1F));
2754 hw->mac.ops.write_vfta(hw, index, vfta);
2755 }
86d70e53
JK		 2756
2757 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2758
2759 return 0;
bc7f75fa
AK		 2760}
2761
86d70e53
JK		 2762/**
2763 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2764 * @adapter: board private structure to initialize
2765 **/
2766static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2767{
2768 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2769 struct e1000_hw *hw = &adapter->hw;
2770 u32 rctl;
bc7f75fa 2771
86d70e53
JK		 2772 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2773 /* disable VLAN receive filtering */
2774 rctl = er32(RCTL);
2775 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2776 ew32(RCTL, rctl);
2777
2778 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
80d5c368
PM		 2779 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2780 adapter->mng_vlan_id);
86d70e53 2781 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2782 }
bc7f75fa
AK		 2783 }
2784}
2785
86d70e53
JK		 2786/**
2787 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2788 * @adapter: board private structure to initialize
2789 **/
2790static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2791{
2792 struct e1000_hw *hw = &adapter->hw;
2793 u32 rctl;
2794
2795 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2796 /* enable VLAN receive filtering */
2797 rctl = er32(RCTL);
2798 rctl |= E1000_RCTL_VFE;
2799 rctl &= ~E1000_RCTL_CFIEN;
2800 ew32(RCTL, rctl);
2801 }
2802}
bc7f75fa 2803
86d70e53
JK		 2804/**
2805 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2806 * @adapter: board private structure to initialize
2807 **/
2808static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2809{
bc7f75fa 2810 struct e1000_hw *hw = &adapter->hw;
86d70e53 2811 u32 ctrl;
bc7f75fa 2812
86d70e53
JK		 2813 /* disable VLAN tag insert/strip */
2814 ctrl = er32(CTRL);
2815 ctrl &= ~E1000_CTRL_VME;
2816 ew32(CTRL, ctrl);
2817}
bc7f75fa 2818
86d70e53
JK		 2819/**
2820 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2821 * @adapter: board private structure to initialize
2822 **/
2823static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2824{
2825 struct e1000_hw *hw = &adapter->hw;
2826 u32 ctrl;
bc7f75fa 2827
86d70e53
JK		 2828 /* enable VLAN tag insert/strip */
2829 ctrl = er32(CTRL);
2830 ctrl |= E1000_CTRL_VME;
2831 ew32(CTRL, ctrl);
2832}
bc7f75fa 2833
86d70e53
JK		 2834static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2835{
2836 struct net_device *netdev = adapter->netdev;
2837 u16 vid = adapter->hw.mng_cookie.vlan_id;
2838 u16 old_vid = adapter->mng_vlan_id;
2839
e5fe2541 2840 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
80d5c368 2841 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
86d70e53 2842 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2843 }
2844
86d70e53 2845 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
80d5c368 2846 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
bc7f75fa
AK		 2847}
2848
2849static void e1000_restore_vlan(struct e1000_adapter *adapter)
2850{
2851 u16 vid;
2852
80d5c368 2853 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
bc7f75fa 2854
86d70e53 2855 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 2856 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
bc7f75fa
AK		 2857}
2858
cd791618 2859static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2860{
2861 struct e1000_hw *hw = &adapter->hw;
cd791618 2862 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2863
2864 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2865 return;
2866
2867 manc = er32(MANC);
2868
e921eb1a 2869 /* enable receiving management packets to the host. this will probably
bc7f75fa 2870 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2871 * the packets will be handled on SMBUS
2872 */
bc7f75fa
AK		 2873 manc |= E1000_MANC_EN_MNG2HOST;
2874 manc2h = er32(MANC2H);
cd791618
BA		 2875
2876 switch (hw->mac.type) {
2877 default:
2878 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2879 break;
2880 case e1000_82574:
2881 case e1000_82583:
e921eb1a 2882 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2883 * if so, enable it.
2884 */
2885 for (i = 0, j = 0; i < 8; i++) {
2886 mdef = er32(MDEF(i));
2887
2888 /* Ignore filters with anything other than IPMI ports */
3b21b508 2889 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2890 continue;
2891
2892 /* Enable this decision filter in MANC2H */
2893 if (mdef)
2894 manc2h |= (1 << i);
2895
2896 j |= mdef;
2897 }
2898
2899 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2900 break;
2901
2902 /* Create new decision filter in an empty filter */
2903 for (i = 0, j = 0; i < 8; i++)
2904 if (er32(MDEF(i)) == 0) {
2905 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2906 E1000_MDEF_PORT_664));
2907 manc2h |= (1 << 1);
2908 j++;
2909 break;
2910 }
2911
2912 if (!j)
2913 e_warn("Unable to create IPMI pass-through filter\n");
2914 break;
2915 }
2916
bc7f75fa
AK		 2917 ew32(MANC2H, manc2h);
2918 ew32(MANC, manc);
2919}
2920
2921/**
af667a29 2922 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2923 * @adapter: board private structure
2924 *
2925 * Configure the Tx unit of the MAC after a reset.
2926 **/
2927static void e1000_configure_tx(struct e1000_adapter *adapter)
2928{
2929 struct e1000_hw *hw = &adapter->hw;
2930 struct e1000_ring *tx_ring = adapter->tx_ring;
2931 u64 tdba;
e7e834aa 2932 u32 tdlen, tctl, tarc;
bc7f75fa
AK		 2933
2934 /* Setup the HW Tx Head and Tail descriptor pointers */
2935 tdba = tx_ring->dma;
2936 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2937 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2938 ew32(TDBAH(0), (tdba >> 32));
2939 ew32(TDLEN(0), tdlen);
2940 ew32(TDH(0), 0);
2941 ew32(TDT(0), 0);
2942 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2943 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2944
0845d45e
JJB		 2945 writel(0, tx_ring->head);
2946 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2947 e1000e_update_tdt_wa(tx_ring, 0);
2948 else
2949 writel(0, tx_ring->tail);
2950
bc7f75fa
AK		 2951 /* Set the Tx Interrupt Delay register */
2952 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2953 /* Tx irq moderation */
bc7f75fa
AK		 2954 ew32(TADV, adapter->tx_abs_int_delay);
2955
3a3b7586
JB		 2956 if (adapter->flags2 & FLAG2_DMA_BURST) {
2957 u32 txdctl = er32(TXDCTL(0));
6cf08d1c 2958
3a3b7586
JB		 2959 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2960 E1000_TXDCTL_WTHRESH);
e921eb1a 2961 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2962 * hardware to use the bus more efficiently in bursts, depends
2963 * on the tx_int_delay to be enabled,
8edc0e62 2964 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2965 * hthresh = 1 ==> prefetch when one or more available
2966 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2967 * BEWARE: this seems to work but should be considered first if
af667a29 2968 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2969 */
2970 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2971 ew32(TXDCTL(0), txdctl);
3a3b7586 2972 }
56032be7
BA		 2973 /* erratum work around: set txdctl the same for both queues */
2974 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2975
e7e834aa
DE		 2976 /* Program the Transmit Control Register */
2977 tctl = er32(TCTL);
2978 tctl &= ~E1000_TCTL_CT;
2979 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2980 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2981
bc7f75fa 2982 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2983 tarc = er32(TARC(0));
e921eb1a 2984 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2985 * gigabit link later
2986 */
bc7f75fa
AK		 2987#define SPEED_MODE_BIT (1 << 21)
2988 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2989 ew32(TARC(0), tarc);
bc7f75fa
AK		 2990 }
2991
2992 /* errata: program both queues to unweighted RR */
2993 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2994 tarc = er32(TARC(0));
bc7f75fa 2995 tarc |= 1;
e9ec2c0f
JK		 2996 ew32(TARC(0), tarc);
2997 tarc = er32(TARC(1));
bc7f75fa 2998 tarc |= 1;
e9ec2c0f 2999 ew32(TARC(1), tarc);
bc7f75fa
AK		 3000 }
3001
bc7f75fa
AK		 3002 /* Setup Transmit Descriptor Settings for eop descriptor */
3003 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
3004
3005 /* only set IDE if we are delaying interrupts using the timers */
3006 if (adapter->tx_int_delay)
3007 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
3008
3009 /* enable Report Status bit */
3010 adapter->txd_cmd |= E1000_TXD_CMD_RS;
3011
e7e834aa
DE		 3012 ew32(TCTL, tctl);
3013
57cde763 3014 hw->mac.ops.config_collision_dist(hw);
79849ebc
DE		 3015
3016 /* SPT Si errata workaround to avoid data corruption */
3017 if (hw->mac.type == e1000_pch_spt) {
3018 u32 reg_val;
3019
3020 reg_val = er32(IOSFPC);
3021 reg_val |= E1000_RCTL_RDMTS_HEX;
3022 ew32(IOSFPC, reg_val);
3023
3024 reg_val = er32(TARC(0));
3025 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ;
3026 ew32(TARC(0), reg_val);
3027 }
bc7f75fa
AK		 3028}
3029
3030/**
3031 * e1000_setup_rctl - configure the receive control registers
3032 * @adapter: Board private structure
3033 **/
3034#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3035 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3036static void e1000_setup_rctl(struct e1000_adapter *adapter)
3037{
3038 struct e1000_hw *hw = &adapter->hw;
3039 u32 rctl, rfctl;
bc7f75fa
AK		 3040 u32 pages = 0;
3041
b20a7744
DE		 3042 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3043 * If jumbo frames not set, program related MAC/PHY registers
3044 * to h/w defaults
3045 */
3046 if (hw->mac.type >= e1000_pch2lan) {
3047 s32 ret_val;
3048
3049 if (adapter->netdev->mtu > ETH_DATA_LEN)
3050 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3051 else
3052 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3053
3054 if (ret_val)
3055 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3056 }
a1ce6473 3057
bc7f75fa
AK		 3058 /* Program MC offset vector base */
3059 rctl = er32(RCTL);
3060 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3061 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
f0ff4398
BA		 3062 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3063 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
bc7f75fa
AK		 3064
3065 /* Do not Store bad packets */
3066 rctl &= ~E1000_RCTL_SBP;
3067
3068 /* Enable Long Packet receive */
3069 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3070 rctl &= ~E1000_RCTL_LPE;
3071 else
3072 rctl |= E1000_RCTL_LPE;
3073
eb7c3adb
JK		 3074 /* Some systems expect that the CRC is included in SMBUS traffic. The
3075 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3076 * host memory when this is enabled
3077 */
3078 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3079 rctl |= E1000_RCTL_SECRC;
5918bd88 3080
a4f58f54
BA		 3081 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3082 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3083 u16 phy_data;
3084
3085 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3086 phy_data &= 0xfff8;
3087 phy_data |= (1 << 2);
3088 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3089
3090 e1e_rphy(hw, 22, &phy_data);
3091 phy_data &= 0x0fff;
3092 phy_data |= (1 << 14);
3093 e1e_wphy(hw, 0x10, 0x2823);
3094 e1e_wphy(hw, 0x11, 0x0003);
3095 e1e_wphy(hw, 22, phy_data);
3096 }
3097
bc7f75fa
AK		 3098 /* Setup buffer sizes */
3099 rctl &= ~E1000_RCTL_SZ_4096;
3100 rctl |= E1000_RCTL_BSEX;
3101 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3102 case 2048:
3103 default:
3104 rctl |= E1000_RCTL_SZ_2048;
3105 rctl &= ~E1000_RCTL_BSEX;
3106 break;
3107 case 4096:
3108 rctl |= E1000_RCTL_SZ_4096;
3109 break;
3110 case 8192:
3111 rctl |= E1000_RCTL_SZ_8192;
3112 break;
3113 case 16384:
3114 rctl |= E1000_RCTL_SZ_16384;
3115 break;
3116 }
3117
5f450212
BA		 3118 /* Enable Extended Status in all Receive Descriptors */
3119 rfctl = er32(RFCTL);
3120 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3121 ew32(RFCTL, rfctl);
5f450212 3122
e921eb1a 3123 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3124 * header is placed in skb->data and the packet data is
3125 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3126 * In the case of a non-split, skb->data is linearly filled,
3127 * followed by the page buffers. Therefore, skb->data is
3128 * sized to hold the largest protocol header.
3129 *
3130 * allocations using alloc_page take too long for regular MTU
3131 * so only enable packet split for jumbo frames
3132 *
3133 * Using pages when the page size is greater than 16k wastes
3134 * a lot of memory, since we allocate 3 pages at all times
3135 * per packet.
3136 */
bc7f75fa 3137 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3138 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3139 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3140 else
3141 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3142
3143 if (adapter->rx_ps_pages) {
90da0669
BA		 3144 u32 psrctl = 0;
3145
140a7480
AK		 3146 /* Enable Packet split descriptors */
3147 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa 3148
e5fe2541 3149 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
bc7f75fa
AK		 3150
3151 switch (adapter->rx_ps_pages) {
3152 case 3:
e5fe2541
BA		 3153 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3154 /* fall-through */
bc7f75fa 3155 case 2:
e5fe2541
BA		 3156 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3157 /* fall-through */
bc7f75fa 3158 case 1:
e5fe2541 3159 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
bc7f75fa
AK		 3160 break;
3161 }
3162
3163 ew32(PSRCTL, psrctl);
3164 }
3165
cf955e6c
BG		 3166 /* This is useful for sniffing bad packets. */
3167 if (adapter->netdev->features & NETIF_F_RXALL) {
3168 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3169 * in e1000e_set_rx_mode
3170 */
e80bd1d1
BA		 3171 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3172 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3173 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
cf955e6c 3174
e80bd1d1
BA		 3175 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3176 E1000_RCTL_DPF | /* Allow filtered pause */
3177 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
cf955e6c
BG		 3178 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3179 * and that breaks VLANs.
3180 */
3181 }
3182
bc7f75fa 3183 ew32(RCTL, rctl);
318a94d6 3184 /* just started the receive unit, no need to restart */
12d43f7d 3185 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3186}
3187
3188/**
3189 * e1000_configure_rx - Configure Receive Unit after Reset
3190 * @adapter: board private structure
3191 *
3192 * Configure the Rx unit of the MAC after a reset.
3193 **/
3194static void e1000_configure_rx(struct e1000_adapter *adapter)
3195{
3196 struct e1000_hw *hw = &adapter->hw;
3197 struct e1000_ring *rx_ring = adapter->rx_ring;
3198 u64 rdba;
3199 u32 rdlen, rctl, rxcsum, ctrl_ext;
3200
3201 if (adapter->rx_ps_pages) {
3202 /* this is a 32 byte descriptor */
3203 rdlen = rx_ring->count *
af667a29 3204 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3205 adapter->clean_rx = e1000_clean_rx_irq_ps;
3206 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3207 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3208 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3209 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3210 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3211 } else {
5f450212 3212 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3213 adapter->clean_rx = e1000_clean_rx_irq;
3214 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3215 }
3216
3217 /* disable receives while setting up the descriptors */
3218 rctl = er32(RCTL);
7f99ae63
BA		 3219 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3220 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3221 e1e_flush();
1bba4386 3222 usleep_range(10000, 20000);
bc7f75fa 3223
3a3b7586 3224 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3225 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3226 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3227 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3228 * granularity = 01
3229 * wthresh = 04,
3230 * hthresh = 04,
3231 * pthresh = 0x20
3232 */
3233 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3234 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3235
e921eb1a 3236 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3237 * the value was not set by the user via module options
3238 */
3239 if (adapter->rx_int_delay == DEFAULT_RDTR)
3240 adapter->rx_int_delay = BURST_RDTR;
3241 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3242 adapter->rx_abs_int_delay = BURST_RADV;
3243 }
3244
bc7f75fa
AK		 3245 /* set the Receive Delay Timer Register */
3246 ew32(RDTR, adapter->rx_int_delay);
3247
3248 /* irq moderation */
3249 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3250 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3251 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3252
3253 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3254 /* Auto-Mask interrupts upon ICR access */
3255 ctrl_ext |= E1000_CTRL_EXT_IAME;
3256 ew32(IAM, 0xffffffff);
3257 ew32(CTRL_EXT, ctrl_ext);
3258 e1e_flush();
3259
e921eb1a 3260 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3261 * the Base and Length of the Rx Descriptor Ring
3262 */
bc7f75fa 3263 rdba = rx_ring->dma;
1e36052e
BA		 3264 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3265 ew32(RDBAH(0), (rdba >> 32));
3266 ew32(RDLEN(0), rdlen);
3267 ew32(RDH(0), 0);
3268 ew32(RDT(0), 0);
3269 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3270 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa 3271
0845d45e
JJB		 3272 writel(0, rx_ring->head);
3273 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3274 e1000e_update_rdt_wa(rx_ring, 0);
3275 else
3276 writel(0, rx_ring->tail);
3277
bc7f75fa
AK		 3278 /* Enable Receive Checksum Offload for TCP and UDP */
3279 rxcsum = er32(RXCSUM);
2e1706f2 3280 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3281 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3282 else
bc7f75fa 3283 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3284 ew32(RXCSUM, rxcsum);
3285
3e35d991
BA		 3286 /* With jumbo frames, excessive C-state transition latencies result
3287 * in dropped transactions.
3288 */
3289 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3290 u32 lat =
3291 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3292 adapter->max_frame_size) * 8 / 1000;
3293
3294 if (adapter->flags & FLAG_IS_ICH) {
53ec5498 3295 u32 rxdctl = er32(RXDCTL(0));
6cf08d1c 3296
53ec5498 3297 ew32(RXDCTL(0), rxdctl | 0x3);
53ec5498 3298 }
3e35d991 3299
e2c65448 3300 pm_qos_update_request(&adapter->pm_qos_req, lat);
3e35d991 3301 } else {
e2c65448 3302 pm_qos_update_request(&adapter->pm_qos_req,
3e35d991 3303 PM_QOS_DEFAULT_VALUE);
97ac8cae 3304 }
bc7f75fa
AK		 3305
3306 /* Enable Receives */
3307 ew32(RCTL, rctl);
3308}
3309
3310/**
ef9b965a
JB		 3311 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3312 * @netdev: network interface device structure
bc7f75fa 3313 *
ef9b965a
JB		 3314 * Writes multicast address list to the MTA hash table.
3315 * Returns: -ENOMEM on failure
3316 * 0 on no addresses written
3317 * X on writing X addresses to MTA
3318 */
3319static int e1000e_write_mc_addr_list(struct net_device *netdev)
3320{
3321 struct e1000_adapter *adapter = netdev_priv(netdev);
3322 struct e1000_hw *hw = &adapter->hw;
3323 struct netdev_hw_addr *ha;
3324 u8 *mta_list;
3325 int i;
3326
3327 if (netdev_mc_empty(netdev)) {
3328 /* nothing to program, so clear mc list */
3329 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3330 return 0;
3331 }
3332
3333 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3334 if (!mta_list)
3335 return -ENOMEM;
3336
3337 /* update_mc_addr_list expects a packed array of only addresses. */
3338 i = 0;
3339 netdev_for_each_mc_addr(ha, netdev)
f0ff4398 3340 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
ef9b965a
JB		 3341
3342 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3343 kfree(mta_list);
3344
3345 return netdev_mc_count(netdev);
3346}
3347
3348/**
3349 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3350 * @netdev: network interface device structure
bc7f75fa 3351 *
ef9b965a
JB		 3352 * Writes unicast address list to the RAR table.
3353 * Returns: -ENOMEM on failure/insufficient address space
3354 * 0 on no addresses written
3355 * X on writing X addresses to the RAR table
bc7f75fa 3356 **/
ef9b965a 3357static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3358{
ef9b965a
JB		 3359 struct e1000_adapter *adapter = netdev_priv(netdev);
3360 struct e1000_hw *hw = &adapter->hw;
b3e5bf1f 3361 unsigned int rar_entries;
ef9b965a
JB		 3362 int count = 0;
3363
b3e5bf1f
DE		 3364 rar_entries = hw->mac.ops.rar_get_count(hw);
3365
ef9b965a
JB		 3366 /* save a rar entry for our hardware address */
3367 rar_entries--;
3368
3369 /* save a rar entry for the LAA workaround */
3370 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3371 rar_entries--;
3372
3373 /* return ENOMEM indicating insufficient memory for addresses */
3374 if (netdev_uc_count(netdev) > rar_entries)
3375 return -ENOMEM;
3376
3377 if (!netdev_uc_empty(netdev) && rar_entries) {
3378 struct netdev_hw_addr *ha;
3379
e921eb1a 3380 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3381 * combining
3382 */
3383 netdev_for_each_uc_addr(ha, netdev) {
b3e5bf1f
DE		 3384 int rval;
3385
ef9b965a
JB		 3386 if (!rar_entries)
3387 break;
b3e5bf1f
DE		 3388 rval = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3389 if (rval < 0)
3390 return -ENOMEM;
ef9b965a
JB		 3391 count++;
3392 }
3393 }
3394
3395 /* zero out the remaining RAR entries not used above */
3396 for (; rar_entries > 0; rar_entries--) {
3397 ew32(RAH(rar_entries), 0);
3398 ew32(RAL(rar_entries), 0);
3399 }
3400 e1e_flush();
3401
3402 return count;
bc7f75fa
AK		 3403}
3404
3405/**
ef9b965a 3406 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3407 * @netdev: network interface device structure
3408 *
ef9b965a
JB		 3409 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3410 * address list or the network interface flags are updated. This routine is
3411 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3412 * promiscuous mode, and all-multi behavior.
3413 **/
ef9b965a 3414static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3415{
3416 struct e1000_adapter *adapter = netdev_priv(netdev);
3417 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3418 u32 rctl;
bc7f75fa 3419
63eb48f1
DE		 3420 if (pm_runtime_suspended(netdev->dev.parent))
3421 return;
3422
bc7f75fa 3423 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3424 rctl = er32(RCTL);
3425
ef9b965a
JB		 3426 /* clear the affected bits */
3427 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3428
bc7f75fa
AK		 3429 if (netdev->flags & IFF_PROMISC) {
3430 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3431 /* Do not hardware filter VLANs in promisc mode */
3432 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3433 } else {
ef9b965a 3434 int count;
3d3a1676 3435
746b9f02
PM		 3436 if (netdev->flags & IFF_ALLMULTI) {
3437 rctl |= E1000_RCTL_MPE;
746b9f02 3438 } else {
e921eb1a 3439 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3440 * then we should just turn on promiscuous mode so
3441 * that we can at least receive multicast traffic
3442 */
3443 count = e1000e_write_mc_addr_list(netdev);
3444 if (count < 0)
3445 rctl |= E1000_RCTL_MPE;
746b9f02 3446 }
86d70e53 3447 e1000e_vlan_filter_enable(adapter);
e921eb1a 3448 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3449 * sufficient space to store all the addresses then enable
3450 * unicast promiscuous mode
bc7f75fa 3451 */
ef9b965a
JB		 3452 count = e1000e_write_uc_addr_list(netdev);
3453 if (count < 0)
3454 rctl |= E1000_RCTL_UPE;
bc7f75fa 3455 }
86d70e53 3456
ef9b965a
JB		 3457 ew32(RCTL, rctl);
3458
f646968f 3459 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
86d70e53
JK		 3460 e1000e_vlan_strip_enable(adapter);
3461 else
3462 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3463}
3464
70495a50
BA		 3465static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3466{
3467 struct e1000_hw *hw = &adapter->hw;
3468 u32 mrqc, rxcsum;
5c8d19da 3469 u32 rss_key[10];
70495a50 3470 int i;
70495a50 3471
5c8d19da 3472 netdev_rss_key_fill(rss_key, sizeof(rss_key));
70495a50 3473 for (i = 0; i < 10; i++)
5c8d19da 3474 ew32(RSSRK(i), rss_key[i]);
70495a50
BA		 3475
3476 /* Direct all traffic to queue 0 */
3477 for (i = 0; i < 32; i++)
3478 ew32(RETA(i), 0);
3479
e921eb1a 3480 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3481 * descriptor on writeback.
3482 */
3483 rxcsum = er32(RXCSUM);
3484 rxcsum |= E1000_RXCSUM_PCSD;
3485
3486 ew32(RXCSUM, rxcsum);
3487
3488 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3489 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3490 E1000_MRQC_RSS_FIELD_IPV6 |
3491 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3492 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3493
3494 ew32(MRQC, mrqc);
3495}
3496
b67e1913
BA		 3497/**
3498 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3499 * @adapter: board private structure
3500 * @timinca: pointer to returned time increment attributes
3501 *
3502 * Get attributes for incrementing the System Time Register SYSTIML/H at
3503 * the default base frequency, and set the cyclecounter shift value.
3504 **/
d89777bf 3505s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3506{
3507 struct e1000_hw *hw = &adapter->hw;
3508 u32 incvalue, incperiod, shift;
3509
79849ebc
DE		 3510 /* Make sure clock is enabled on I217/I218/I219 before checking
3511 * the frequency
3512 */
3513 if (((hw->mac.type == e1000_pch_lpt) ||
3514 (hw->mac.type == e1000_pch_spt)) &&
b67e1913
BA		 3515 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3516 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3517 u32 fextnvm7 = er32(FEXTNVM7);
3518
3519 if (!(fextnvm7 & (1 << 0))) {
3520 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3521 e1e_flush();
3522 }
3523 }
3524
3525 switch (hw->mac.type) {
3526 case e1000_pch2lan:
3527 case e1000_pch_lpt:
83129b37 3528 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
b67e1913
BA		 3529 /* Stable 96MHz frequency */
3530 incperiod = INCPERIOD_96MHz;
3531 incvalue = INCVALUE_96MHz;
3532 shift = INCVALUE_SHIFT_96MHz;
3533 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
83129b37
YL		 3534 } else {
3535 /* Stable 25MHz frequency */
3536 incperiod = INCPERIOD_25MHz;
3537 incvalue = INCVALUE_25MHz;
3538 shift = INCVALUE_SHIFT_25MHz;
3539 adapter->cc.shift = shift;
3540 }
3541 break;
3542 case e1000_pch_spt:
3543 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3544 /* Stable 24MHz frequency */
3545 incperiod = INCPERIOD_24MHz;
3546 incvalue = INCVALUE_24MHz;
3547 shift = INCVALUE_SHIFT_24MHz;
3548 adapter->cc.shift = shift;
b67e1913
BA		 3549 break;
3550 }
83129b37 3551 return -EINVAL;
b67e1913
BA		 3552 case e1000_82574:
3553 case e1000_82583:
3554 /* Stable 25MHz frequency */
3555 incperiod = INCPERIOD_25MHz;
3556 incvalue = INCVALUE_25MHz;
3557 shift = INCVALUE_SHIFT_25MHz;
3558 adapter->cc.shift = shift;
3559 break;
3560 default:
3561 return -EINVAL;
3562 }
3563
3564 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3565 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3566
3567 return 0;
3568}
3569
3570/**
3571 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3572 * @adapter: board private structure
3573 *
3574 * Outgoing time stamping can be enabled and disabled. Play nice and
3575 * disable it when requested, although it shouldn't cause any overhead
3576 * when no packet needs it. At most one packet in the queue may be
3577 * marked for time stamping, otherwise it would be impossible to tell
3578 * for sure to which packet the hardware time stamp belongs.
3579 *
3580 * Incoming time stamping has to be configured via the hardware filters.
3581 * Not all combinations are supported, in particular event type has to be
3582 * specified. Matching the kind of event packet is not supported, with the
3583 * exception of "all V2 events regardless of level 2 or 4".
3584 **/
62d7e3a2
BH		 3585static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3586 struct hwtstamp_config *config)
b67e1913
BA		 3587{
3588 struct e1000_hw *hw = &adapter->hw;
b67e1913
BA		 3589 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3590 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3591 u32 rxmtrl = 0;
3592 u16 rxudp = 0;
3593 bool is_l4 = false;
3594 bool is_l2 = false;
b67e1913
BA		 3595 u32 regval;
3596 s32 ret_val;
3597
3598 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3599 return -EINVAL;
3600
3601 /* flags reserved for future extensions - must be zero */
3602 if (config->flags)
3603 return -EINVAL;
3604
3605 switch (config->tx_type) {
3606 case HWTSTAMP_TX_OFF:
3607 tsync_tx_ctl = 0;
3608 break;
3609 case HWTSTAMP_TX_ON:
3610 break;
3611 default:
3612 return -ERANGE;
3613 }
3614
3615 switch (config->rx_filter) {
3616 case HWTSTAMP_FILTER_NONE:
3617 tsync_rx_ctl = 0;
3618 break;
d89777bf
BA		 3619 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3620 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3621 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3622 is_l4 = true;
3623 break;
3624 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3625 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3626 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3627 is_l4 = true;
3628 break;
3629 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3630 /* Also time stamps V2 L2 Path Delay Request/Response */
3631 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3632 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3633 is_l2 = true;
3634 break;
3635 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3636 /* Also time stamps V2 L2 Path Delay Request/Response. */
3637 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3638 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3639 is_l2 = true;
3640 break;
3641 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3642 /* Hardware cannot filter just V2 L4 Sync messages;
3643 * fall-through to V2 (both L2 and L4) Sync.
3644 */
3645 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3646 /* Also time stamps V2 Path Delay Request/Response. */
3647 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3648 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3649 is_l2 = true;
3650 is_l4 = true;
3651 break;
3652 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3653 /* Hardware cannot filter just V2 L4 Delay Request messages;
3654 * fall-through to V2 (both L2 and L4) Delay Request.
3655 */
3656 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3657 /* Also time stamps V2 Path Delay Request/Response. */
3658 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3659 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3660 is_l2 = true;
3661 is_l4 = true;
3662 break;
3663 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3664 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3665 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3666 * fall-through to all V2 (both L2 and L4) Events.
3667 */
3668 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3669 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3670 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3671 is_l2 = true;
3672 is_l4 = true;
3673 break;
3674 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3675 /* For V1, the hardware can only filter Sync messages or
3676 * Delay Request messages but not both so fall-through to
3677 * time stamp all packets.
3678 */
b67e1913 3679 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3680 is_l2 = true;
3681 is_l4 = true;
b67e1913
BA		 3682 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3683 config->rx_filter = HWTSTAMP_FILTER_ALL;
3684 break;
3685 default:
3686 return -ERANGE;
3687 }
3688
62d7e3a2
BH		 3689 adapter->hwtstamp_config = *config;
3690
b67e1913
BA		 3691 /* enable/disable Tx h/w time stamping */
3692 regval = er32(TSYNCTXCTL);
3693 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3694 regval |= tsync_tx_ctl;
3695 ew32(TSYNCTXCTL, regval);
3696 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3697 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3698 e_err("Timesync Tx Control register not set as expected\n");
3699 return -EAGAIN;
3700 }
3701
3702 /* enable/disable Rx h/w time stamping */
3703 regval = er32(TSYNCRXCTL);
3704 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3705 regval |= tsync_rx_ctl;
3706 ew32(TSYNCRXCTL, regval);
3707 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3708 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3709 (regval & (E1000_TSYNCRXCTL_ENABLED |
3710 E1000_TSYNCRXCTL_TYPE_MASK))) {
3711 e_err("Timesync Rx Control register not set as expected\n");
3712 return -EAGAIN;
3713 }
3714
d89777bf
BA		 3715 /* L2: define ethertype filter for time stamped packets */
3716 if (is_l2)
3717 rxmtrl |= ETH_P_1588;
3718
3719 /* define which PTP packets get time stamped */
3720 ew32(RXMTRL, rxmtrl);
3721
3722 /* Filter by destination port */
3723 if (is_l4) {
3724 rxudp = PTP_EV_PORT;
3725 cpu_to_be16s(&rxudp);
3726 }
3727 ew32(RXUDP, rxudp);
3728
3729 e1e_flush();
3730
b67e1913 3731 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
70806a7f
BA		 3732 er32(RXSTMPH);
3733 er32(TXSTMPH);
b67e1913
BA		 3734
3735 /* Get and set the System Time Register SYSTIM base frequency */
3736 ret_val = e1000e_get_base_timinca(adapter, &regval);
3737 if (ret_val)
3738 return ret_val;
3739 ew32(TIMINCA, regval);
3740
3741 /* reset the ns time counter */
3742 timecounter_init(&adapter->tc, &adapter->cc,
3743 ktime_to_ns(ktime_get_real()));
3744
3745 return 0;
3746}
3747
bc7f75fa 3748/**
ad68076e 3749 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3750 * @adapter: private board structure
3751 **/
3752static void e1000_configure(struct e1000_adapter *adapter)
3753{
55aa6985
BA		 3754 struct e1000_ring *rx_ring = adapter->rx_ring;
3755
ef9b965a 3756 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3757
3758 e1000_restore_vlan(adapter);
cd791618 3759 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3760
3761 e1000_configure_tx(adapter);
70495a50
BA		 3762
3763 if (adapter->netdev->features & NETIF_F_RXHASH)
3764 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3765 e1000_setup_rctl(adapter);
3766 e1000_configure_rx(adapter);
55aa6985 3767 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3768}
3769
3770/**
3771 * e1000e_power_up_phy - restore link in case the phy was powered down
3772 * @adapter: address of board private structure
3773 *
3774 * The phy may be powered down to save power and turn off link when the
3775 * driver is unloaded and wake on lan is not enabled (among others)
3776 * *** this routine MUST be followed by a call to e1000e_reset ***
3777 **/
3778void e1000e_power_up_phy(struct e1000_adapter *adapter)
3779{
17f208de
BA		 3780 if (adapter->hw.phy.ops.power_up)
3781 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3782
3783 adapter->hw.mac.ops.setup_link(&adapter->hw);
3784}
3785
3786/**
3787 * e1000_power_down_phy - Power down the PHY
3788 *
17f208de
BA		 3789 * Power down the PHY so no link is implied when interface is down.
3790 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3791 */
3792static void e1000_power_down_phy(struct e1000_adapter *adapter)
3793{
17f208de
BA		 3794 if (adapter->hw.phy.ops.power_down)
3795 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3796}
3797
ad851fbb
YL		 3798/**
3799 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3800 *
3801 * We want to clear all pending descriptors from the TX ring.
3802 * zeroing happens when the HW reads the regs. We assign the ring itself as
3803 * the data of the next descriptor. We don't care about the data we are about
3804 * to reset the HW.
3805 */
3806static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3807{
3808 struct e1000_hw *hw = &adapter->hw;
3809 struct e1000_ring *tx_ring = adapter->tx_ring;
3810 struct e1000_tx_desc *tx_desc = NULL;
3811 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3812 u16 size = 512;
3813
3814 tctl = er32(TCTL);
3815 ew32(TCTL, tctl | E1000_TCTL_EN);
3816 tdt = er32(TDT(0));
3817 BUG_ON(tdt != tx_ring->next_to_use);
3818 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3819 tx_desc->buffer_addr = tx_ring->dma;
3820
3821 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3822 tx_desc->upper.data = 0;
3823 /* flush descriptors to memory before notifying the HW */
3824 wmb();
3825 tx_ring->next_to_use++;
3826 if (tx_ring->next_to_use == tx_ring->count)
3827 tx_ring->next_to_use = 0;
3828 ew32(TDT(0), tx_ring->next_to_use);
3829 mmiowb();
3830 usleep_range(200, 250);
3831}
3832
3833/**
3834 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3835 *
3836 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3837 */
3838static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3839{
3840 u32 rctl, rxdctl;
3841 struct e1000_hw *hw = &adapter->hw;
3842
3843 rctl = er32(RCTL);
3844 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3845 e1e_flush();
3846 usleep_range(100, 150);
3847
3848 rxdctl = er32(RXDCTL(0));
3849 /* zero the lower 14 bits (prefetch and host thresholds) */
3850 rxdctl &= 0xffffc000;
3851
3852 /* update thresholds: prefetch threshold to 31, host threshold to 1
3853 * and make sure the granularity is "descriptors" and not "cache lines"
3854 */
3855 rxdctl |= (0x1F | (1 << 8) | E1000_RXDCTL_THRESH_UNIT_DESC);
3856
3857 ew32(RXDCTL(0), rxdctl);
3858 /* momentarily enable the RX ring for the changes to take effect */
3859 ew32(RCTL, rctl | E1000_RCTL_EN);
3860 e1e_flush();
3861 usleep_range(100, 150);
3862 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3863}
3864
3865/**
3866 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3867 *
3868 * In i219, the descriptor rings must be emptied before resetting the HW
3869 * or before changing the device state to D3 during runtime (runtime PM).
3870 *
3871 * Failure to do this will cause the HW to enter a unit hang state which can
3872 * only be released by PCI reset on the device
3873 *
3874 */
3875
3876static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3877{
ff917429 3878 u16 hang_state;
ad851fbb
YL		 3879 u32 fext_nvm11, tdlen;
3880 struct e1000_hw *hw = &adapter->hw;
3881
3882 /* First, disable MULR fix in FEXTNVM11 */
3883 fext_nvm11 = er32(FEXTNVM11);
3884 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3885 ew32(FEXTNVM11, fext_nvm11);
3886 /* do nothing if we're not in faulty state, or if the queue is empty */
3887 tdlen = er32(TDLEN(0));
ff917429
YL		 3888 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3889 &hang_state);
3890 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
ad851fbb
YL		 3891 return;
3892 e1000_flush_tx_ring(adapter);
3893 /* recheck, maybe the fault is caused by the rx ring */
ff917429
YL		 3894 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3895 &hang_state);
3896 if (hang_state & FLUSH_DESC_REQUIRED)
ad851fbb
YL		 3897 e1000_flush_rx_ring(adapter);
3898}
3899
bc7f75fa
AK		 3900/**
3901 * e1000e_reset - bring the hardware into a known good state
3902 *
3903 * This function boots the hardware and enables some settings that
3904 * require a configuration cycle of the hardware - those cannot be
3905 * set/changed during runtime. After reset the device needs to be
ad68076e 3906 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3907 */
3908void e1000e_reset(struct e1000_adapter *adapter)
3909{
3910 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3911 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3912 struct e1000_hw *hw = &adapter->hw;
3913 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3914 u32 pba = adapter->pba;
bc7f75fa
AK		 3915 u16 hwm;
3916
ad68076e 3917 /* reset Packet Buffer Allocation to default */
318a94d6 3918 ew32(PBA, pba);
df762464 3919
8084b86d 3920 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
e921eb1a 3921 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3922 * large enough to accommodate two full transmit packets,
3923 * rounded up to the next 1KB and expressed in KB. Likewise,
3924 * the Rx FIFO should be large enough to accommodate at least
3925 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3926 * expressed in KB.
3927 */
df762464 3928 pba = er32(PBA);
bc7f75fa 3929 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3930 tx_space = pba >> 16;
bc7f75fa 3931 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3932 pba &= 0xffff;
e921eb1a 3933 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3934 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3935 */
3936 min_tx_space = (adapter->max_frame_size +
e5fe2541 3937 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
bc7f75fa
AK		 3938 min_tx_space = ALIGN(min_tx_space, 1024);
3939 min_tx_space >>= 10;
3940 /* software strips receive CRC, so leave room for it */
318a94d6 3941 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3942 min_rx_space = ALIGN(min_rx_space, 1024);
3943 min_rx_space >>= 10;
3944
e921eb1a 3945 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3946 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3947 * allocation, take space away from current Rx allocation
3948 */
df762464
AK		 3949 if ((tx_space < min_tx_space) &&
3950 ((min_tx_space - tx_space) < pba)) {
3951 pba -= min_tx_space - tx_space;
bc7f75fa 3952
e921eb1a 3953 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3954 * adjustment
ad68076e 3955 */
79d4e908 3956 if (pba < min_rx_space)
df762464 3957 pba = min_rx_space;
bc7f75fa 3958 }
df762464
AK		 3959
3960 ew32(PBA, pba);
bc7f75fa
AK		 3961 }
3962
e921eb1a 3963 /* flow control settings
ad68076e 3964 *
38eb394e 3965 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3966 * (or the size used for early receive) above it in the Rx FIFO.
3967 * Set it to the lower of:
3968 * - 90% of the Rx FIFO size, and
38eb394e 3969 * - the full Rx FIFO size minus one full frame
ad68076e 3970 */
d3738bb8
BA		 3971 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3972 fc->pause_time = 0xFFFF;
3973 else
3974 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3975 fc->send_xon = true;
d3738bb8
BA		 3976 fc->current_mode = fc->requested_mode;
3977
3978 switch (hw->mac.type) {
79d4e908
BA		 3979 case e1000_ich9lan:
3980 case e1000_ich10lan:
3981 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3982 pba = 14;
3983 ew32(PBA, pba);
3984 fc->high_water = 0x2800;
3985 fc->low_water = fc->high_water - 8;
3986 break;
3987 }
3988 /* fall-through */
d3738bb8 3989 default:
79d4e908
BA		 3990 hwm = min(((pba << 10) * 9 / 10),
3991 ((pba << 10) - adapter->max_frame_size));
d3738bb8 3992
e80bd1d1 3993 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
d3738bb8
BA		 3994 fc->low_water = fc->high_water - 8;
3995 break;
3996 case e1000_pchlan:
e921eb1a 3997 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3998 * loads. If hangs persist, try disabling Tx flow control.
3999 */
4000 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4001 fc->high_water = 0x3500;
e80bd1d1 4002 fc->low_water = 0x1500;
38eb394e
BA		 4003 } else {
4004 fc->high_water = 0x5000;
e80bd1d1 4005 fc->low_water = 0x3000;
38eb394e 4006 }
a305595b 4007 fc->refresh_time = 0x1000;
d3738bb8
BA		 4008 break;
4009 case e1000_pch2lan:
2fbe4526 4010 case e1000_pch_lpt:
79849ebc 4011 case e1000_pch_spt:
d3738bb8 4012 fc->refresh_time = 0x0400;
347b5201
BA		 4013
4014 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4015 fc->high_water = 0x05C20;
4016 fc->low_water = 0x05048;
4017 fc->pause_time = 0x0650;
4018 break;
828bac87 4019 }
347b5201 4020
ce345e08
BA		 4021 pba = 14;
4022 ew32(PBA, pba);
347b5201
BA		 4023 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4024 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 4025 break;
38eb394e 4026 }
bc7f75fa 4027
e921eb1a 4028 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 4029 * maximum size per Tx descriptor limited only to the transmit
4030 * allocation of the packet buffer minus 96 bytes with an upper
4031 * limit of 24KB due to receive synchronization limitations.
4032 */
4033 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4034 24 << 10);
4035
e921eb1a 4036 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 4037 * fit in receive buffer.
828bac87
BA		 4038 */
4039 if (adapter->itr_setting & 0x3) {
79d4e908 4040 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 4041 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4042 dev_info(&adapter->pdev->dev,
17e813ec 4043 "Interrupt Throttle Rate off\n");
828bac87 4044 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 4045 e1000e_write_itr(adapter, 0);
828bac87
BA		 4046 }
4047 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4048 dev_info(&adapter->pdev->dev,
17e813ec 4049 "Interrupt Throttle Rate on\n");
828bac87
BA		 4050 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4051 adapter->itr = 20000;
22a4cca2 4052 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 4053 }
4054 }
4055
0ffc5646
YL		 4056 if (hw->mac.type == e1000_pch_spt)
4057 e1000_flush_desc_rings(adapter);
bc7f75fa
AK		 4058 /* Allow time for pending master requests to run */
4059 mac->ops.reset_hw(hw);
97ac8cae 4060
e921eb1a 4061 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 4062 * that the network interface is in control
4063 */
c43bc57e 4064 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 4065 e1000e_get_hw_control(adapter);
97ac8cae 4066
bc7f75fa
AK		 4067 ew32(WUC, 0);
4068
4069 if (mac->ops.init_hw(hw))
44defeb3 4070 e_err("Hardware Error\n");
bc7f75fa
AK		 4071
4072 e1000_update_mng_vlan(adapter);
4073
4074 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4075 ew32(VET, ETH_P_8021Q);
4076
4077 e1000e_reset_adaptive(hw);
31dbe5b4 4078
b67e1913 4079 /* initialize systim and reset the ns time counter */
62d7e3a2 4080 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
b67e1913 4081
d495bcb8
BA		 4082 /* Set EEE advertisement as appropriate */
4083 if (adapter->flags2 & FLAG2_HAS_EEE) {
4084 s32 ret_val;
4085 u16 adv_addr;
4086
4087 switch (hw->phy.type) {
4088 case e1000_phy_82579:
4089 adv_addr = I82579_EEE_ADVERTISEMENT;
4090 break;
4091 case e1000_phy_i217:
4092 adv_addr = I217_EEE_ADVERTISEMENT;
4093 break;
4094 default:
4095 dev_err(&adapter->pdev->dev,
4096 "Invalid PHY type setting EEE advertisement\n");
4097 return;
4098 }
4099
4100 ret_val = hw->phy.ops.acquire(hw);
4101 if (ret_val) {
4102 dev_err(&adapter->pdev->dev,
4103 "EEE advertisement - unable to acquire PHY\n");
4104 return;
4105 }
4106
4107 e1000_write_emi_reg_locked(hw, adv_addr,
4108 hw->dev_spec.ich8lan.eee_disable ?
4109 0 : adapter->eee_advert);
4110
4111 hw->phy.ops.release(hw);
4112 }
4113
31dbe5b4 4114 if (!netif_running(adapter->netdev) &&
28002099 4115 !test_bit(__E1000_TESTING, &adapter->state))
31dbe5b4 4116 e1000_power_down_phy(adapter);
31dbe5b4 4117
bc7f75fa
AK		 4118 e1000_get_phy_info(hw);
4119
918d7197
BA		 4120 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4121 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 4122 u16 phy_data = 0;
e921eb1a 4123 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 4124 * the return value of this function because there is nothing
ad68076e
BA		 4125 * different we would do if it failed
4126 */
bc7f75fa
AK		 4127 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4128 phy_data &= ~IGP02E1000_PM_SPD;
4129 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4130 }
ec945cfb
YL		 4131 if (hw->mac.type == e1000_pch_spt && adapter->int_mode == 0) {
4132 u32 reg;
4133
4134 /* Fextnvm7 @ 0xe4[2] = 1 */
4135 reg = er32(FEXTNVM7);
4136 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4137 ew32(FEXTNVM7, reg);
4138 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4139 reg = er32(FEXTNVM9);
4140 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4141 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4142 ew32(FEXTNVM9, reg);
4143 }
4144
bc7f75fa
AK		 4145}
4146
4147int e1000e_up(struct e1000_adapter *adapter)
4148{
4149 struct e1000_hw *hw = &adapter->hw;
4150
4151 /* hardware has been reset, we need to reload some things */
4152 e1000_configure(adapter);
4153
4154 clear_bit(__E1000_DOWN, &adapter->state);
4155
4662e82b
BA		 4156 if (adapter->msix_entries)
4157 e1000_configure_msix(adapter);
bc7f75fa
AK		 4158 e1000_irq_enable(adapter);
4159
400484fa 4160 netif_start_queue(adapter->netdev);
4cb9be7a 4161
bc7f75fa 4162 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 4163 if (adapter->msix_entries)
4164 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4165 else
4166 ew32(ICS, E1000_ICS_LSC);
4167
bc7f75fa
AK		 4168 return 0;
4169}
4170
713b3c9e
JB		 4171static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4172{
4173 struct e1000_hw *hw = &adapter->hw;
4174
4175 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4176 return;
4177
4178 /* flush pending descriptor writebacks to memory */
4179 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4180 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4181
4182 /* execute the writes immediately */
4183 e1e_flush();
bf03085f 4184
e921eb1a 4185 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 4186 * write is successful
4187 */
4188 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4189 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 4190
4191 /* execute the writes immediately */
4192 e1e_flush();
4193}
4194
67fd4fcb
JK		 4195static void e1000e_update_stats(struct e1000_adapter *adapter);
4196
28002099
DE		 4197/**
4198 * e1000e_down - quiesce the device and optionally reset the hardware
4199 * @adapter: board private structure
4200 * @reset: boolean flag to reset the hardware or not
4201 */
4202void e1000e_down(struct e1000_adapter *adapter, bool reset)
bc7f75fa
AK		 4203{
4204 struct net_device *netdev = adapter->netdev;
4205 struct e1000_hw *hw = &adapter->hw;
4206 u32 tctl, rctl;
4207
e921eb1a 4208 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 4209 * reschedule our watchdog timer
4210 */
bc7f75fa
AK		 4211 set_bit(__E1000_DOWN, &adapter->state);
4212
a60a132e
ET		 4213 netif_carrier_off(netdev);
4214
bc7f75fa
AK		 4215 /* disable receives in the hardware */
4216 rctl = er32(RCTL);
7f99ae63
BA		 4217 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4218 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 4219 /* flush and sleep below */
4220
4cb9be7a 4221 netif_stop_queue(netdev);
bc7f75fa
AK		 4222
4223 /* disable transmits in the hardware */
4224 tctl = er32(TCTL);
4225 tctl &= ~E1000_TCTL_EN;
4226 ew32(TCTL, tctl);
7f99ae63 4227
bc7f75fa
AK		 4228 /* flush both disables and wait for them to finish */
4229 e1e_flush();
1bba4386 4230 usleep_range(10000, 20000);
bc7f75fa 4231
bc7f75fa
AK		 4232 e1000_irq_disable(adapter);
4233
a3b87a4c
BA		 4234 napi_synchronize(&adapter->napi);
4235
bc7f75fa
AK		 4236 del_timer_sync(&adapter->watchdog_timer);
4237 del_timer_sync(&adapter->phy_info_timer);
4238
67fd4fcb
JK		 4239 spin_lock(&adapter->stats64_lock);
4240 e1000e_update_stats(adapter);
4241 spin_unlock(&adapter->stats64_lock);
4242
400484fa 4243 e1000e_flush_descriptors(adapter);
400484fa 4244
bc7f75fa
AK		 4245 adapter->link_speed = 0;
4246 adapter->link_duplex = 0;
4247
da1e2046
BA		 4248 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4249 if ((hw->mac.type >= e1000_pch2lan) &&
4250 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4251 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4252 e_dbg("failed to disable jumbo frame workaround mode\n");
4253
0ffc5646
YL		 4254 if (!pci_channel_offline(adapter->pdev)) {
4255 if (reset)
4256 e1000e_reset(adapter);
4257 else if (hw->mac.type == e1000_pch_spt)
4258 e1000_flush_desc_rings(adapter);
4259 }
4260 e1000_clean_tx_ring(adapter->tx_ring);
4261 e1000_clean_rx_ring(adapter->rx_ring);
bc7f75fa
AK		 4262}
4263
4264void e1000e_reinit_locked(struct e1000_adapter *adapter)
4265{
4266 might_sleep();
4267 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 4268 usleep_range(1000, 2000);
28002099 4269 e1000e_down(adapter, true);
bc7f75fa
AK		 4270 e1000e_up(adapter);
4271 clear_bit(__E1000_RESETTING, &adapter->state);
4272}
4273
b67e1913
BA		 4274/**
4275 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4276 * @cc: cyclecounter structure
4277 **/
4278static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4279{
4280 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4281 cc);
4282 struct e1000_hw *hw = &adapter->hw;
37b12910 4283 u32 systimel_1, systimel_2, systimeh;
5e7ff970 4284 cycle_t systim, systim_next;
37b12910
RA		 4285 /* SYSTIMH latching upon SYSTIML read does not work well.
4286 * This means that if SYSTIML overflows after we read it but before
4287 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4288 * will experience a huge non linear increment in the systime value
4289 * to fix that we test for overflow and if true, we re-read systime.
83129b37 4290 */
37b12910
RA		 4291 systimel_1 = er32(SYSTIML);
4292 systimeh = er32(SYSTIMH);
4293 systimel_2 = er32(SYSTIML);
4294 /* Check for overflow. If there was no overflow, use the values */
4295 if (systimel_1 < systimel_2) {
4296 systim = (cycle_t)systimel_1;
4297 systim |= (cycle_t)systimeh << 32;
4298 } else {
4299 /* There was an overflow, read again SYSTIMH, and use
4300 * systimel_2
4301 */
4302 systimeh = er32(SYSTIMH);
4303 systim = (cycle_t)systimel_2;
4304 systim |= (cycle_t)systimeh << 32;
4305 }
b67e1913 4306
5e7ff970
TF		 4307 if ((hw->mac.type == e1000_82574) || (hw->mac.type == e1000_82583)) {
4308 u64 incvalue, time_delta, rem, temp;
4309 int i;
4310
4311 /* errata for 82574/82583 possible bad bits read from SYSTIMH/L
4312 * check to see that the time is incrementing at a reasonable
4313 * rate and is a multiple of incvalue
4314 */
4315 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4316 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4317 /* latch SYSTIMH on read of SYSTIML */
4318 systim_next = (cycle_t)er32(SYSTIML);
4319 systim_next |= (cycle_t)er32(SYSTIMH) << 32;
4320
4321 time_delta = systim_next - systim;
4322 temp = time_delta;
4323 rem = do_div(temp, incvalue);
4324
4325 systim = systim_next;
4326
4327 if ((time_delta < E1000_82574_SYSTIM_EPSILON) &&
4328 (rem == 0))
4329 break;
4330 }
4331 }
b67e1913
BA		 4332 return systim;
4333}
4334
bc7f75fa
AK		 4335/**
4336 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4337 * @adapter: board private structure to initialize
4338 *
4339 * e1000_sw_init initializes the Adapter private data structure.
4340 * Fields are initialized based on PCI device information and
4341 * OS network device settings (MTU size).
4342 **/
9f9a12f8 4343static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4344{
bc7f75fa
AK		 4345 struct net_device *netdev = adapter->netdev;
4346
8084b86d 4347 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
bc7f75fa 4348 adapter->rx_ps_bsize0 = 128;
8084b86d 4349 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
318a94d6 4350 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4351 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4352 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4353
67fd4fcb
JK		 4354 spin_lock_init(&adapter->stats64_lock);
4355
4662e82b 4356 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4357
4662e82b
BA		 4358 if (e1000_alloc_queues(adapter))
4359 return -ENOMEM;
bc7f75fa 4360
b67e1913
BA		 4361 /* Setup hardware time stamping cyclecounter */
4362 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4363 adapter->cc.read = e1000e_cyclecounter_read;
4d045b4c 4364 adapter->cc.mask = CYCLECOUNTER_MASK(64);
b67e1913
BA		 4365 adapter->cc.mult = 1;
4366 /* cc.shift set in e1000e_get_base_tininca() */
4367
4368 spin_lock_init(&adapter->systim_lock);
4369 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4370 }
4371
bc7f75fa 4372 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4373 e1000_irq_disable(adapter);
4374
bc7f75fa
AK		 4375 set_bit(__E1000_DOWN, &adapter->state);
4376 return 0;
bc7f75fa
AK		 4377}
4378
f8d59f78
BA		 4379/**
4380 * e1000_intr_msi_test - Interrupt Handler
4381 * @irq: interrupt number
4382 * @data: pointer to a network interface device structure
4383 **/
8bb62869 4384static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
f8d59f78
BA		 4385{
4386 struct net_device *netdev = data;
4387 struct e1000_adapter *adapter = netdev_priv(netdev);
4388 struct e1000_hw *hw = &adapter->hw;
4389 u32 icr = er32(ICR);
4390
3bb99fe2 4391 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4392 if (icr & E1000_ICR_RXSEQ) {
4393 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4394 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4395 * interrupt is handled.
4396 */
f8d59f78
BA		 4397 wmb();
4398 }
4399
4400 return IRQ_HANDLED;
4401}
4402
4403/**
4404 * e1000_test_msi_interrupt - Returns 0 for successful test
4405 * @adapter: board private struct
4406 *
4407 * code flow taken from tg3.c
4408 **/
4409static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4410{
4411 struct net_device *netdev = adapter->netdev;
4412 struct e1000_hw *hw = &adapter->hw;
4413 int err;
4414
4415 /* poll_enable hasn't been called yet, so don't need disable */
4416 /* clear any pending events */
4417 er32(ICR);
4418
4419 /* free the real vector and request a test handler */
4420 e1000_free_irq(adapter);
4662e82b 4421 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4422
4423 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4424 * MSI irq handler will unset this flag
4425 */
f8d59f78
BA		 4426 adapter->flags |= FLAG_MSI_TEST_FAILED;
4427
4428 err = pci_enable_msi(adapter->pdev);
4429 if (err)
4430 goto msi_test_failed;
4431
a0607fd3 4432 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4433 netdev->name, netdev);
4434 if (err) {
4435 pci_disable_msi(adapter->pdev);
4436 goto msi_test_failed;
4437 }
4438
e921eb1a 4439 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4440 * interrupt.
4441 */
f8d59f78
BA		 4442 wmb();
4443
4444 e1000_irq_enable(adapter);
4445
4446 /* fire an unusual interrupt on the test handler */
4447 ew32(ICS, E1000_ICS_RXSEQ);
4448 e1e_flush();
569a3aff 4449 msleep(100);
f8d59f78
BA		 4450
4451 e1000_irq_disable(adapter);
4452
bc76329d 4453 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4454
4455 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4456 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4457 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4458 } else {
068e8a30 4459 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4460 }
f8d59f78
BA		 4461
4462 free_irq(adapter->pdev->irq, netdev);
4463 pci_disable_msi(adapter->pdev);
4464
f8d59f78 4465msi_test_failed:
4662e82b 4466 e1000e_set_interrupt_capability(adapter);
068e8a30 4467 return e1000_request_irq(adapter);
f8d59f78
BA		 4468}
4469
4470/**
4471 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4472 * @adapter: board private struct
4473 *
4474 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4475 **/
4476static int e1000_test_msi(struct e1000_adapter *adapter)
4477{
4478 int err;
4479 u16 pci_cmd;
4480
4481 if (!(adapter->flags & FLAG_MSI_ENABLED))
4482 return 0;
4483
4484 /* disable SERR in case the MSI write causes a master abort */
4485 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4486 if (pci_cmd & PCI_COMMAND_SERR)
4487 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4488 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4489
4490 err = e1000_test_msi_interrupt(adapter);
4491
36f2407f
DN		 4492 /* re-enable SERR */
4493 if (pci_cmd & PCI_COMMAND_SERR) {
4494 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4495 pci_cmd |= PCI_COMMAND_SERR;
4496 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4497 }
f8d59f78 4498
f8d59f78
BA		 4499 return err;
4500}
4501
bc7f75fa
AK		 4502/**
4503 * e1000_open - Called when a network interface is made active
4504 * @netdev: network interface device structure
4505 *
4506 * Returns 0 on success, negative value on failure
4507 *
4508 * The open entry point is called when a network interface is made
4509 * active by the system (IFF_UP). At this point all resources needed
4510 * for transmit and receive operations are allocated, the interrupt
4511 * handler is registered with the OS, the watchdog timer is started,
4512 * and the stack is notified that the interface is ready.
4513 **/
4514static int e1000_open(struct net_device *netdev)
4515{
4516 struct e1000_adapter *adapter = netdev_priv(netdev);
4517 struct e1000_hw *hw = &adapter->hw;
23606cf5 4518 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4519 int err;
4520
4521 /* disallow open during test */
4522 if (test_bit(__E1000_TESTING, &adapter->state))
4523 return -EBUSY;
4524
23606cf5
RW		 4525 pm_runtime_get_sync(&pdev->dev);
4526
9c563d20
JB		 4527 netif_carrier_off(netdev);
4528
bc7f75fa 4529 /* allocate transmit descriptors */
55aa6985 4530 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4531 if (err)
4532 goto err_setup_tx;
4533
4534 /* allocate receive descriptors */
55aa6985 4535 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4536 if (err)
4537 goto err_setup_rx;
4538
e921eb1a 4539 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4540 * interface is now open and reset the part to a known state.
4541 */
4542 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4543 e1000e_get_hw_control(adapter);
11b08be8
BA		 4544 e1000e_reset(adapter);
4545 }
4546
bc7f75fa
AK		 4547 e1000e_power_up_phy(adapter);
4548
4549 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
e5fe2541 4550 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
bc7f75fa
AK		 4551 e1000_update_mng_vlan(adapter);
4552
79d4e908 4553 /* DMA latency requirement to workaround jumbo issue */
e2c65448 4554 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
3e35d991 4555 PM_QOS_DEFAULT_VALUE);
c128ec29 4556
e921eb1a 4557 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4558 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4559 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4560 * clean_rx handler before we do so.
4561 */
bc7f75fa
AK		 4562 e1000_configure(adapter);
4563
4564 err = e1000_request_irq(adapter);
4565 if (err)
4566 goto err_req_irq;
4567
e921eb1a 4568 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4569 * ignore e1000e MSI messages, which means we need to test our MSI
4570 * interrupt now
4571 */
4662e82b 4572 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4573 err = e1000_test_msi(adapter);
4574 if (err) {
4575 e_err("Interrupt allocation failed\n");
4576 goto err_req_irq;
4577 }
4578 }
4579
bc7f75fa
AK		 4580 /* From here on the code is the same as e1000e_up() */
4581 clear_bit(__E1000_DOWN, &adapter->state);
4582
4583 napi_enable(&adapter->napi);
4584
4585 e1000_irq_enable(adapter);
4586
09357b00 4587 adapter->tx_hang_recheck = false;
4cb9be7a 4588 netif_start_queue(netdev);
d55b53ff 4589
66148bab 4590 hw->mac.get_link_status = true;
23606cf5
RW		 4591 pm_runtime_put(&pdev->dev);
4592
bc7f75fa 4593 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 4594 if (adapter->msix_entries)
4595 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4596 else
4597 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 4598
4599 return 0;
4600
4601err_req_irq:
7faae964 4602 pm_qos_remove_request(&adapter->pm_qos_req);
31dbe5b4 4603 e1000e_release_hw_control(adapter);
bc7f75fa 4604 e1000_power_down_phy(adapter);
55aa6985 4605 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4606err_setup_rx:
55aa6985 4607 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4608err_setup_tx:
4609 e1000e_reset(adapter);
23606cf5 4610 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4611
4612 return err;
4613}
4614
4615/**
4616 * e1000_close - Disables a network interface
4617 * @netdev: network interface device structure
4618 *
4619 * Returns 0, this is not allowed to fail
4620 *
4621 * The close entry point is called when an interface is de-activated
4622 * by the OS. The hardware is still under the drivers control, but
4623 * needs to be disabled. A global MAC reset is issued to stop the
4624 * hardware, and all transmit and receive resources are freed.
4625 **/
4626static int e1000_close(struct net_device *netdev)
4627{
4628 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4629 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4630 int count = E1000_CHECK_RESET_COUNT;
4631
4632 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4633 usleep_range(10000, 20000);
bc7f75fa
AK		 4634
4635 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4636
4637 pm_runtime_get_sync(&pdev->dev);
4638
4639 if (!test_bit(__E1000_DOWN, &adapter->state)) {
28002099 4640 e1000e_down(adapter, true);
23606cf5 4641 e1000_free_irq(adapter);
63eb48f1
DE		 4642
4643 /* Link status message must follow this format */
4644 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
23606cf5 4645 }
a3b87a4c
BA		 4646
4647 napi_disable(&adapter->napi);
4648
55aa6985
BA		 4649 e1000e_free_tx_resources(adapter->tx_ring);
4650 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4651
e921eb1a 4652 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4653 * the same ID is registered on the host OS (let 8021q kill it)
4654 */
e5fe2541 4655 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
80d5c368
PM		 4656 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4657 adapter->mng_vlan_id);
bc7f75fa 4658
e921eb1a 4659 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4660 * interface is now closed
4661 */
31dbe5b4
BA		 4662 if ((adapter->flags & FLAG_HAS_AMT) &&
4663 !test_bit(__E1000_TESTING, &adapter->state))
4664 e1000e_release_hw_control(adapter);
bc7f75fa 4665
e2c65448 4666 pm_qos_remove_request(&adapter->pm_qos_req);
c128ec29 4667
23606cf5
RW		 4668 pm_runtime_put_sync(&pdev->dev);
4669
bc7f75fa
AK		 4670 return 0;
4671}
fc830b78 4672
bc7f75fa
AK		 4673/**
4674 * e1000_set_mac - Change the Ethernet Address of the NIC
4675 * @netdev: network interface device structure
4676 * @p: pointer to an address structure
4677 *
4678 * Returns 0 on success, negative on failure
4679 **/
4680static int e1000_set_mac(struct net_device *netdev, void *p)
4681{
4682 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4683 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4684 struct sockaddr *addr = p;
4685
4686 if (!is_valid_ether_addr(addr->sa_data))
4687 return -EADDRNOTAVAIL;
4688
4689 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4690 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4691
69e1e019 4692 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4693
4694 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4695 /* activate the work around */
4696 e1000e_set_laa_state_82571(&adapter->hw, 1);
4697
e921eb1a 4698 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4699 * between the time RAR[0] gets clobbered and the time it
4700 * gets fixed (in e1000_watchdog), the actual LAA is in one
4701 * of the RARs and no incoming packets directed to this port
4702 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4703 * RAR[14]
4704 */
69e1e019
BA		 4705 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4706 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4707 }
4708
4709 return 0;
4710}
4711
a8f88ff5
JB		 4712/**
4713 * e1000e_update_phy_task - work thread to update phy
4714 * @work: pointer to our work struct
4715 *
4716 * this worker thread exists because we must acquire a
4717 * semaphore to read the phy, which we could msleep while
4718 * waiting for it, and we can't msleep in a timer.
4719 **/
4720static void e1000e_update_phy_task(struct work_struct *work)
4721{
4722 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4723 struct e1000_adapter,
4724 update_phy_task);
a03206ed 4725 struct e1000_hw *hw = &adapter->hw;
615b32af
JB		 4726
4727 if (test_bit(__E1000_DOWN, &adapter->state))
4728 return;
4729
a03206ed
DE		 4730 e1000_get_phy_info(hw);
4731
4732 /* Enable EEE on 82579 after link up */
50844bb7 4733 if (hw->phy.type >= e1000_phy_82579)
a03206ed 4734 e1000_set_eee_pchlan(hw);
a8f88ff5
JB		 4735}
4736
e921eb1a
BA		 4737/**
4738 * e1000_update_phy_info - timre call-back to update PHY info
4739 * @data: pointer to adapter cast into an unsigned long
4740 *
ad68076e
BA		 4741 * Need to wait a few seconds after link up to get diagnostic information from
4742 * the phy
e921eb1a 4743 **/
bc7f75fa
AK		 4744static void e1000_update_phy_info(unsigned long data)
4745{
53aa82da 4746 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
615b32af
JB		 4747
4748 if (test_bit(__E1000_DOWN, &adapter->state))
4749 return;
4750
a8f88ff5 4751 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4752}
4753
8c7bbb92
BA		 4754/**
4755 * e1000e_update_phy_stats - Update the PHY statistics counters
4756 * @adapter: board private structure
2b6b168d
BA		 4757 *
4758 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4759 **/
4760static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4761{
4762 struct e1000_hw *hw = &adapter->hw;
4763 s32 ret_val;
4764 u16 phy_data;
4765
4766 ret_val = hw->phy.ops.acquire(hw);
4767 if (ret_val)
4768 return;
4769
e921eb1a 4770 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4771 * If not, set to the page with the PHY status registers.
4772 */
2b6b168d 4773 hw->phy.addr = 1;
8c7bbb92
BA		 4774 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4775 &phy_data);
4776 if (ret_val)
4777 goto release;
2b6b168d
BA		 4778 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4779 ret_val = hw->phy.ops.set_page(hw,
4780 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4781 if (ret_val)
4782 goto release;
4783 }
4784
8c7bbb92 4785 /* Single Collision Count */
2b6b168d
BA		 4786 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4787 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4788 if (!ret_val)
4789 adapter->stats.scc += phy_data;
4790
4791 /* Excessive Collision Count */
2b6b168d
BA		 4792 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4793 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4794 if (!ret_val)
4795 adapter->stats.ecol += phy_data;
4796
4797 /* Multiple Collision Count */
2b6b168d
BA		 4798 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4799 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4800 if (!ret_val)
4801 adapter->stats.mcc += phy_data;
4802
4803 /* Late Collision Count */
2b6b168d
BA		 4804 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4805 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4806 if (!ret_val)
4807 adapter->stats.latecol += phy_data;
4808
4809 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4810 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4811 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4812 if (!ret_val)
4813 hw->mac.collision_delta = phy_data;
4814
4815 /* Defer Count */
2b6b168d
BA		 4816 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4817 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4818 if (!ret_val)
4819 adapter->stats.dc += phy_data;
4820
4821 /* Transmit with no CRS */
2b6b168d
BA		 4822 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4823 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4824 if (!ret_val)
4825 adapter->stats.tncrs += phy_data;
4826
4827release:
4828 hw->phy.ops.release(hw);
4829}
4830
bc7f75fa
AK		 4831/**
4832 * e1000e_update_stats - Update the board statistics counters
4833 * @adapter: board private structure
4834 **/
67fd4fcb 4835static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4836{
7274c20f 4837 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4838 struct e1000_hw *hw = &adapter->hw;
4839 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4840
e921eb1a 4841 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4842 * connection is down.
4843 */
4844 if (adapter->link_speed == 0)
4845 return;
4846 if (pci_channel_offline(pdev))
4847 return;
4848
bc7f75fa
AK		 4849 adapter->stats.crcerrs += er32(CRCERRS);
4850 adapter->stats.gprc += er32(GPRC);
7c25769f 4851 adapter->stats.gorc += er32(GORCL);
e80bd1d1 4852 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4853 adapter->stats.bprc += er32(BPRC);
4854 adapter->stats.mprc += er32(MPRC);
4855 adapter->stats.roc += er32(ROC);
4856
bc7f75fa 4857 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4858
4859 /* Half-duplex statistics */
4860 if (adapter->link_duplex == HALF_DUPLEX) {
4861 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4862 e1000e_update_phy_stats(adapter);
4863 } else {
4864 adapter->stats.scc += er32(SCC);
4865 adapter->stats.ecol += er32(ECOL);
4866 adapter->stats.mcc += er32(MCC);
4867 adapter->stats.latecol += er32(LATECOL);
4868 adapter->stats.dc += er32(DC);
4869
4870 hw->mac.collision_delta = er32(COLC);
4871
4872 if ((hw->mac.type != e1000_82574) &&
4873 (hw->mac.type != e1000_82583))
4874 adapter->stats.tncrs += er32(TNCRS);
4875 }
4876 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4877 }
8c7bbb92 4878
bc7f75fa
AK		 4879 adapter->stats.xonrxc += er32(XONRXC);
4880 adapter->stats.xontxc += er32(XONTXC);
4881 adapter->stats.xoffrxc += er32(XOFFRXC);
4882 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4883 adapter->stats.gptc += er32(GPTC);
7c25769f 4884 adapter->stats.gotc += er32(GOTCL);
e80bd1d1 4885 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4886 adapter->stats.rnbc += er32(RNBC);
4887 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4888
4889 adapter->stats.mptc += er32(MPTC);
4890 adapter->stats.bptc += er32(BPTC);
4891
4892 /* used for adaptive IFS */
4893
4894 hw->mac.tx_packet_delta = er32(TPT);
4895 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4896
4897 adapter->stats.algnerrc += er32(ALGNERRC);
4898 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4899 adapter->stats.cexterr += er32(CEXTERR);
4900 adapter->stats.tsctc += er32(TSCTC);
4901 adapter->stats.tsctfc += er32(TSCTFC);
4902
bc7f75fa 4903 /* Fill out the OS statistics structure */
7274c20f
AK		 4904 netdev->stats.multicast = adapter->stats.mprc;
4905 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4906
4907 /* Rx Errors */
4908
e921eb1a 4909 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4910 * our own version based on RUC and ROC
4911 */
7274c20f 4912 netdev->stats.rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 4913 adapter->stats.crcerrs + adapter->stats.algnerrc +
4914 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
7274c20f 4915 netdev->stats.rx_length_errors = adapter->stats.ruc +
f0ff4398 4916 adapter->stats.roc;
7274c20f
AK		 4917 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4918 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4919 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4920
4921 /* Tx Errors */
f0ff4398 4922 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
7274c20f
AK		 4923 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4924 netdev->stats.tx_window_errors = adapter->stats.latecol;
4925 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4926
4927 /* Tx Dropped needs to be maintained elsewhere */
4928
bc7f75fa
AK		 4929 /* Management Stats */
4930 adapter->stats.mgptc += er32(MGTPTC);
4931 adapter->stats.mgprc += er32(MGTPRC);
4932 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 4933
4934 /* Correctable ECC Errors */
79849ebc
DE		 4935 if ((hw->mac.type == e1000_pch_lpt) ||
4936 (hw->mac.type == e1000_pch_spt)) {
94fb848b 4937 u32 pbeccsts = er32(PBECCSTS);
6cf08d1c 4938
94fb848b
BA		 4939 adapter->corr_errors +=
4940 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4941 adapter->uncorr_errors +=
4942 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4943 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4944 }
bc7f75fa
AK		 4945}
4946
7c25769f
BA		 4947/**
4948 * e1000_phy_read_status - Update the PHY register status snapshot
4949 * @adapter: board private structure
4950 **/
4951static void e1000_phy_read_status(struct e1000_adapter *adapter)
4952{
4953 struct e1000_hw *hw = &adapter->hw;
4954 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f 4955
97390ab8
BA		 4956 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
4957 (er32(STATUS) & E1000_STATUS_LU) &&
7c25769f 4958 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4959 int ret_val;
4960
c2ade1a4
BA		 4961 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4962 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4963 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4964 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4965 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4966 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4967 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4968 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
7c25769f 4969 if (ret_val)
44defeb3 4970 e_warn("Error reading PHY register\n");
7c25769f 4971 } else {
e921eb1a 4972 /* Do not read PHY registers if link is not up
7c25769f
BA		 4973 * Set values to typical power-on defaults
4974 */
4975 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4976 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4977 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4978 BMSR_ERCAP);
4979 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4980 ADVERTISE_ALL | ADVERTISE_CSMA);
4981 phy->lpa = 0;
4982 phy->expansion = EXPANSION_ENABLENPAGE;
4983 phy->ctrl1000 = ADVERTISE_1000FULL;
4984 phy->stat1000 = 0;
4985 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4986 }
7c25769f
BA		 4987}
4988
bc7f75fa
AK		 4989static void e1000_print_link_info(struct e1000_adapter *adapter)
4990{
bc7f75fa
AK		 4991 struct e1000_hw *hw = &adapter->hw;
4992 u32 ctrl = er32(CTRL);
4993
8f12fe86 4994 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4995 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4996 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4997 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4998 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4999 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5000 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 5001}
5002
0c6bdb30 5003static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 5004{
5005 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 5006 bool link_active = false;
318a94d6
JK		 5007 s32 ret_val = 0;
5008
e921eb1a 5009 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 5010 * Rx sequence error interrupt. get_link_status will stay
5011 * false until the check_for_link establishes link
5012 * for copper adapters ONLY
5013 */
5014 switch (hw->phy.media_type) {
5015 case e1000_media_type_copper:
5016 if (hw->mac.get_link_status) {
5017 ret_val = hw->mac.ops.check_for_link(hw);
5018 link_active = !hw->mac.get_link_status;
5019 } else {
3db1cd5c 5020 link_active = true;
318a94d6
JK		 5021 }
5022 break;
5023 case e1000_media_type_fiber:
5024 ret_val = hw->mac.ops.check_for_link(hw);
5025 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5026 break;
5027 case e1000_media_type_internal_serdes:
5028 ret_val = hw->mac.ops.check_for_link(hw);
5029 link_active = adapter->hw.mac.serdes_has_link;
5030 break;
5031 default:
5032 case e1000_media_type_unknown:
5033 break;
5034 }
5035
5036 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5037 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5038 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 5039 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 5040 }
5041
5042 return link_active;
5043}
5044
5045static void e1000e_enable_receives(struct e1000_adapter *adapter)
5046{
5047 /* make sure the receive unit is started */
5048 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 5049 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 5050 struct e1000_hw *hw = &adapter->hw;
5051 u32 rctl = er32(RCTL);
6cf08d1c 5052
318a94d6 5053 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 5054 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 5055 }
5056}
5057
ff10e13c
CW		 5058static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5059{
5060 struct e1000_hw *hw = &adapter->hw;
5061
e921eb1a 5062 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 5063 * for hung state and reset, if two calls return true
5064 */
5065 if (e1000_check_phy_82574(hw))
5066 adapter->phy_hang_count++;
5067 else
5068 adapter->phy_hang_count = 0;
5069
5070 if (adapter->phy_hang_count > 1) {
5071 adapter->phy_hang_count = 0;
d9554e96 5072 e_dbg("PHY appears hung - resetting\n");
ff10e13c
CW		 5073 schedule_work(&adapter->reset_task);
5074 }
5075}
5076
bc7f75fa
AK		 5077/**
5078 * e1000_watchdog - Timer Call-back
5079 * @data: pointer to adapter cast into an unsigned long
5080 **/
5081static void e1000_watchdog(unsigned long data)
5082{
53aa82da 5083 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
bc7f75fa
AK		 5084
5085 /* Do the rest outside of interrupt context */
5086 schedule_work(&adapter->watchdog_task);
5087
5088 /* TODO: make this use queue_delayed_work() */
5089}
5090
5091static void e1000_watchdog_task(struct work_struct *work)
5092{
5093 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 5094 struct e1000_adapter,
5095 watchdog_task);
bc7f75fa
AK		 5096 struct net_device *netdev = adapter->netdev;
5097 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 5098 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 5099 struct e1000_ring *tx_ring = adapter->tx_ring;
5100 struct e1000_hw *hw = &adapter->hw;
5101 u32 link, tctl;
bc7f75fa 5102
615b32af
JB		 5103 if (test_bit(__E1000_DOWN, &adapter->state))
5104 return;
5105
b405e8df 5106 link = e1000e_has_link(adapter);
318a94d6 5107 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 5108 /* Cancel scheduled suspend requests. */
5109 pm_runtime_resume(netdev->dev.parent);
5110
318a94d6 5111 e1000e_enable_receives(adapter);
bc7f75fa 5112 goto link_up;
bc7f75fa
AK		 5113 }
5114
5115 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5116 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5117 e1000_update_mng_vlan(adapter);
5118
bc7f75fa
AK		 5119 if (link) {
5120 if (!netif_carrier_ok(netdev)) {
3db1cd5c 5121 bool txb2b = true;
23606cf5
RW		 5122
5123 /* Cancel scheduled suspend requests. */
5124 pm_runtime_resume(netdev->dev.parent);
5125
318a94d6 5126 /* update snapshot of PHY registers on LSC */
7c25769f 5127 e1000_phy_read_status(adapter);
bc7f75fa 5128 mac->ops.get_link_up_info(&adapter->hw,
17e813ec
BA		 5129 &adapter->link_speed,
5130 &adapter->link_duplex);
bc7f75fa 5131 e1000_print_link_info(adapter);
e792cd91
KS		 5132
5133 /* check if SmartSpeed worked */
5134 e1000e_check_downshift(hw);
5135 if (phy->speed_downgraded)
5136 netdev_warn(netdev,
5137 "Link Speed was downgraded by SmartSpeed\n");
5138
e921eb1a 5139 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 5140 * if link has autonegotiated at 10/100 half
5141 */
5142 if ((hw->phy.type == e1000_phy_igp_3 ||
5143 hw->phy.type == e1000_phy_bm) &&
138953bb 5144 hw->mac.autoneg &&
f4187b56
BA		 5145 (adapter->link_speed == SPEED_10 ||
5146 adapter->link_speed == SPEED_100) &&
5147 (adapter->link_duplex == HALF_DUPLEX)) {
5148 u16 autoneg_exp;
5149
c2ade1a4 5150 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
f4187b56 5151
c2ade1a4 5152 if (!(autoneg_exp & EXPANSION_NWAY))
ef456f85 5153 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 5154 }
5155
f49c57e1 5156 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 5157 adapter->tx_timeout_factor = 1;
5158 switch (adapter->link_speed) {
5159 case SPEED_10:
3db1cd5c 5160 txb2b = false;
10f1b492 5161 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 5162 break;
5163 case SPEED_100:
3db1cd5c 5164 txb2b = false;
4c86e0b9 5165 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 5166 break;
5167 }
5168
e921eb1a 5169 /* workaround: re-program speed mode bit after
ad68076e
BA		 5170 * link-up event
5171 */
bc7f75fa
AK		 5172 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5173 !txb2b) {
5174 u32 tarc0;
6cf08d1c 5175
e9ec2c0f 5176 tarc0 = er32(TARC(0));
bc7f75fa 5177 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 5178 ew32(TARC(0), tarc0);
bc7f75fa
AK		 5179 }
5180
e921eb1a 5181 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 5182 * some hardware issues
5183 */
bc7f75fa
AK		 5184 if (!(adapter->flags & FLAG_TSO_FORCE)) {
5185 switch (adapter->link_speed) {
5186 case SPEED_10:
5187 case SPEED_100:
44defeb3 5188 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 5189 netdev->features &= ~NETIF_F_TSO;
5190 netdev->features &= ~NETIF_F_TSO6;
5191 break;
5192 case SPEED_1000:
5193 netdev->features |= NETIF_F_TSO;
5194 netdev->features |= NETIF_F_TSO6;
5195 break;
5196 default:
5197 /* oops */
5198 break;
5199 }
5200 }
5201
e921eb1a 5202 /* enable transmits in the hardware, need to do this
ad68076e
BA		 5203 * after setting TARC(0)
5204 */
bc7f75fa
AK		 5205 tctl = er32(TCTL);
5206 tctl |= E1000_TCTL_EN;
5207 ew32(TCTL, tctl);
5208
e921eb1a 5209 /* Perform any post-link-up configuration before
75eb0fad
BA		 5210 * reporting link up.
5211 */
5212 if (phy->ops.cfg_on_link_up)
5213 phy->ops.cfg_on_link_up(hw);
5214
bc7f75fa 5215 netif_carrier_on(netdev);
bc7f75fa
AK		 5216
5217 if (!test_bit(__E1000_DOWN, &adapter->state))
5218 mod_timer(&adapter->phy_info_timer,
5219 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 5220 }
5221 } else {
5222 if (netif_carrier_ok(netdev)) {
5223 adapter->link_speed = 0;
5224 adapter->link_duplex = 0;
8f12fe86 5225 /* Link status message must follow this format */
7dbc1672 5226 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 5227 netif_carrier_off(netdev);
bc7f75fa
AK		 5228 if (!test_bit(__E1000_DOWN, &adapter->state))
5229 mod_timer(&adapter->phy_info_timer,
5230 round_jiffies(jiffies + 2 * HZ));
5231
d9554e96
DE		 5232 /* 8000ES2LAN requires a Rx packet buffer work-around
5233 * on link down event; reset the controller to flush
5234 * the Rx packet buffer.
12d43f7d 5235 */
d9554e96 5236 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
12d43f7d 5237 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 5238 else
5239 pm_schedule_suspend(netdev->dev.parent,
17e813ec 5240 LINK_TIMEOUT);
bc7f75fa
AK		 5241 }
5242 }
5243
5244link_up:
67fd4fcb 5245 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 5246 e1000e_update_stats(adapter);
5247
5248 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5249 adapter->tpt_old = adapter->stats.tpt;
5250 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5251 adapter->colc_old = adapter->stats.colc;
5252
7c25769f
BA		 5253 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5254 adapter->gorc_old = adapter->stats.gorc;
5255 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5256 adapter->gotc_old = adapter->stats.gotc;
2084b114 5257 spin_unlock(&adapter->stats64_lock);
bc7f75fa 5258
d9554e96
DE		 5259 /* If the link is lost the controller stops DMA, but
5260 * if there is queued Tx work it cannot be done. So
5261 * reset the controller to flush the Tx packet buffers.
5262 */
5263 if (!netif_carrier_ok(netdev) &&
5264 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5265 adapter->flags |= FLAG_RESTART_NOW;
5266
5267 /* If reset is necessary, do it outside of interrupt context. */
12d43f7d 5268 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 5269 schedule_work(&adapter->reset_task);
5270 /* return immediately since reset is imminent */
5271 return;
bc7f75fa
AK		 5272 }
5273
12d43f7d
BA		 5274 e1000e_update_adaptive(&adapter->hw);
5275
eab2abf5
JB		 5276 /* Simple mode for Interrupt Throttle Rate (ITR) */
5277 if (adapter->itr_setting == 4) {
e921eb1a 5278 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 5279 * Total asymmetrical Tx or Rx gets ITR=8000;
5280 * everyone else is between 2000-8000.
5281 */
5282 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5283 u32 dif = (adapter->gotc > adapter->gorc ?
17e813ec
BA		 5284 adapter->gotc - adapter->gorc :
5285 adapter->gorc - adapter->gotc) / 10000;
eab2abf5
JB		 5286 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5287
22a4cca2 5288 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 5289 }
5290
ad68076e 5291 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 5292 if (adapter->msix_entries)
5293 ew32(ICS, adapter->rx_ring->ims_val);
5294 else
5295 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 5296
713b3c9e
JB		 5297 /* flush pending descriptors to memory before detecting Tx hang */
5298 e1000e_flush_descriptors(adapter);
5299
bc7f75fa 5300 /* Force detection of hung controller every watchdog period */
3db1cd5c 5301 adapter->detect_tx_hung = true;
bc7f75fa 5302
e921eb1a 5303 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 5304 * reset from the other port. Set the appropriate LAA in RAR[0]
5305 */
bc7f75fa 5306 if (e1000e_get_laa_state_82571(hw))
69e1e019 5307 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 5308
ff10e13c
CW		 5309 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5310 e1000e_check_82574_phy_workaround(adapter);
5311
b67e1913
BA		 5312 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5313 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5314 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5315 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5316 er32(RXSTMPH);
5317 adapter->rx_hwtstamp_cleared++;
5318 } else {
5319 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5320 }
5321 }
5322
bc7f75fa
AK		 5323 /* Reset the timer */
5324 if (!test_bit(__E1000_DOWN, &adapter->state))
5325 mod_timer(&adapter->watchdog_timer,
5326 round_jiffies(jiffies + 2 * HZ));
5327}
5328
5329#define E1000_TX_FLAGS_CSUM 0x00000001
5330#define E1000_TX_FLAGS_VLAN 0x00000002
5331#define E1000_TX_FLAGS_TSO 0x00000004
5332#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5333#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5334#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5335#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5336#define E1000_TX_FLAGS_VLAN_SHIFT 16
5337
47ccd1ed
VY		 5338static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5339 __be16 protocol)
bc7f75fa 5340{
bc7f75fa
AK		 5341 struct e1000_context_desc *context_desc;
5342 struct e1000_buffer *buffer_info;
5343 unsigned int i;
5344 u32 cmd_length = 0;
70443ae9 5345 u16 ipcse = 0, mss;
bc7f75fa 5346 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bcf1f57f 5347 int err;
bc7f75fa 5348
3d5e33c9
BA		 5349 if (!skb_is_gso(skb))
5350 return 0;
bc7f75fa 5351
bcf1f57f
FR		 5352 err = skb_cow_head(skb, 0);
5353 if (err < 0)
5354 return err;
bc7f75fa 5355
3d5e33c9
BA		 5356 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5357 mss = skb_shinfo(skb)->gso_size;
47ccd1ed 5358 if (protocol == htons(ETH_P_IP)) {
3d5e33c9
BA		 5359 struct iphdr *iph = ip_hdr(skb);
5360 iph->tot_len = 0;
5361 iph->check = 0;
5362 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
f0ff4398 5363 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5364 cmd_length = E1000_TXD_CMD_IP;
5365 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5366 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 5367 ipv6_hdr(skb)->payload_len = 0;
5368 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
f0ff4398
BA		 5369 &ipv6_hdr(skb)->daddr,
5370 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5371 ipcse = 0;
5372 }
5373 ipcss = skb_network_offset(skb);
5374 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5375 tucss = skb_transport_offset(skb);
5376 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5377
5378 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
f0ff4398 5379 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
3d5e33c9
BA		 5380
5381 i = tx_ring->next_to_use;
5382 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5383 buffer_info = &tx_ring->buffer_info[i];
5384
e80bd1d1
BA		 5385 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5386 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5387 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
3d5e33c9
BA		 5388 context_desc->upper_setup.tcp_fields.tucss = tucss;
5389 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5390 context_desc->upper_setup.tcp_fields.tucse = 0;
e80bd1d1 5391 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
3d5e33c9
BA		 5392 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5393 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5394
5395 buffer_info->time_stamp = jiffies;
5396 buffer_info->next_to_watch = i;
5397
5398 i++;
5399 if (i == tx_ring->count)
5400 i = 0;
5401 tx_ring->next_to_use = i;
5402
5403 return 1;
bc7f75fa
AK		 5404}
5405
47ccd1ed
VY		 5406static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5407 __be16 protocol)
bc7f75fa 5408{
55aa6985 5409 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5410 struct e1000_context_desc *context_desc;
5411 struct e1000_buffer *buffer_info;
5412 unsigned int i;
5413 u8 css;
af807c82 5414 u32 cmd_len = E1000_TXD_CMD_DEXT;
bc7f75fa 5415
af807c82 5416 if (skb->ip_summed != CHECKSUM_PARTIAL)
3992c8ed 5417 return false;
bc7f75fa 5418
3f518390 5419 switch (protocol) {
09640e63 5420 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5421 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5422 cmd_len |= E1000_TXD_CMD_TCP;
5423 break;
09640e63 5424 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5425 /* XXX not handling all IPV6 headers */
5426 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5427 cmd_len |= E1000_TXD_CMD_TCP;
5428 break;
5429 default:
5430 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5431 e_warn("checksum_partial proto=%x!\n",
5432 be16_to_cpu(protocol));
af807c82 5433 break;
bc7f75fa
AK		 5434 }
5435
0d0b1672 5436 css = skb_checksum_start_offset(skb);
af807c82
DG		 5437
5438 i = tx_ring->next_to_use;
5439 buffer_info = &tx_ring->buffer_info[i];
5440 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5441
5442 context_desc->lower_setup.ip_config = 0;
5443 context_desc->upper_setup.tcp_fields.tucss = css;
f0ff4398 5444 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
af807c82
DG		 5445 context_desc->upper_setup.tcp_fields.tucse = 0;
5446 context_desc->tcp_seg_setup.data = 0;
5447 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5448
5449 buffer_info->time_stamp = jiffies;
5450 buffer_info->next_to_watch = i;
5451
5452 i++;
5453 if (i == tx_ring->count)
5454 i = 0;
5455 tx_ring->next_to_use = i;
5456
3992c8ed 5457 return true;
bc7f75fa
AK		 5458}
5459
55aa6985
BA		 5460static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5461 unsigned int first, unsigned int max_per_txd,
d821a4c4 5462 unsigned int nr_frags)
bc7f75fa 5463{
55aa6985 5464 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5465 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5466 struct e1000_buffer *buffer_info;
8ddc951c 5467 unsigned int len = skb_headlen(skb);
03b1320d 5468 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5469 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5470
5471 i = tx_ring->next_to_use;
5472
5473 while (len) {
1b7719c4 5474 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5475 size = min(len, max_per_txd);
5476
bc7f75fa 5477 buffer_info->length = size;
bc7f75fa 5478 buffer_info->time_stamp = jiffies;
bc7f75fa 5479 buffer_info->next_to_watch = i;
0be3f55f
NN		 5480 buffer_info->dma = dma_map_single(&pdev->dev,
5481 skb->data + offset,
af667a29 5482 size, DMA_TO_DEVICE);
03b1320d 5483 buffer_info->mapped_as_page = false;
0be3f55f 5484 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5485 goto dma_error;
bc7f75fa
AK		 5486
5487 len -= size;
5488 offset += size;
03b1320d 5489 count++;
1b7719c4
AD		 5490
5491 if (len) {
5492 i++;
5493 if (i == tx_ring->count)
5494 i = 0;
5495 }
bc7f75fa
AK		 5496 }
5497
5498 for (f = 0; f < nr_frags; f++) {
9e903e08 5499 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5500
5501 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5502 len = skb_frag_size(frag);
877749bf 5503 offset = 0;
bc7f75fa
AK		 5504
5505 while (len) {
1b7719c4
AD		 5506 i++;
5507 if (i == tx_ring->count)
5508 i = 0;
5509
bc7f75fa
AK		 5510 buffer_info = &tx_ring->buffer_info[i];
5511 size = min(len, max_per_txd);
bc7f75fa
AK		 5512
5513 buffer_info->length = size;
5514 buffer_info->time_stamp = jiffies;
bc7f75fa 5515 buffer_info->next_to_watch = i;
877749bf 5516 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
17e813ec
BA		 5517 offset, size,
5518 DMA_TO_DEVICE);
03b1320d 5519 buffer_info->mapped_as_page = true;
0be3f55f 5520 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5521 goto dma_error;
bc7f75fa
AK		 5522
5523 len -= size;
5524 offset += size;
5525 count++;
bc7f75fa
AK		 5526 }
5527 }
5528
af667a29 5529 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5530 /* multiply data chunks by size of headers */
5531 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5532
bc7f75fa 5533 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5534 tx_ring->buffer_info[i].segs = segs;
5535 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5536 tx_ring->buffer_info[first].next_to_watch = i;
5537
5538 return count;
03b1320d
AD		 5539
5540dma_error:
af667a29 5541 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5542 buffer_info->dma = 0;
c1fa347f 5543 if (count)
03b1320d 5544 count--;
c1fa347f
RK		 5545
5546 while (count--) {
af667a29 5547 if (i == 0)
03b1320d 5548 i += tx_ring->count;
c1fa347f 5549 i--;
03b1320d 5550 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5551 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5552 }
5553
5554 return 0;
bc7f75fa
AK		 5555}
5556
55aa6985 5557static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5558{
55aa6985 5559 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5560 struct e1000_tx_desc *tx_desc = NULL;
5561 struct e1000_buffer *buffer_info;
5562 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5563 unsigned int i;
5564
5565 if (tx_flags & E1000_TX_FLAGS_TSO) {
5566 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
f0ff4398 5567 E1000_TXD_CMD_TSE;
bc7f75fa
AK		 5568 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5569
5570 if (tx_flags & E1000_TX_FLAGS_IPV4)
5571 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5572 }
5573
5574 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5575 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5576 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5577 }
5578
5579 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5580 txd_lower |= E1000_TXD_CMD_VLE;
5581 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5582 }
5583
943146de
BG		 5584 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5585 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5586
b67e1913
BA		 5587 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5588 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5589 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5590 }
5591
bc7f75fa
AK		 5592 i = tx_ring->next_to_use;
5593
36b973df 5594 do {
bc7f75fa
AK		 5595 buffer_info = &tx_ring->buffer_info[i];
5596 tx_desc = E1000_TX_DESC(*tx_ring, i);
5597 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
f0ff4398
BA		 5598 tx_desc->lower.data = cpu_to_le32(txd_lower |
5599 buffer_info->length);
bc7f75fa
AK		 5600 tx_desc->upper.data = cpu_to_le32(txd_upper);
5601
5602 i++;
5603 if (i == tx_ring->count)
5604 i = 0;
36b973df 5605 } while (--count > 0);
bc7f75fa
AK		 5606
5607 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5608
943146de
BG		 5609 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5610 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5611 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5612
e921eb1a 5613 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5614 * know there are new descriptors to fetch. (Only
5615 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5616 * such as IA-64).
5617 */
bc7f75fa
AK		 5618 wmb();
5619
5620 tx_ring->next_to_use = i;
bc7f75fa
AK		 5621}
5622
5623#define MINIMUM_DHCP_PACKET_SIZE 282
5624static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5625 struct sk_buff *skb)
5626{
e80bd1d1 5627 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 5628 u16 length, offset;
5629
df8a39de
JP		 5630 if (skb_vlan_tag_present(skb) &&
5631 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
d60923c4
BA		 5632 (adapter->hw.mng_cookie.status &
5633 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5634 return 0;
bc7f75fa
AK		 5635
5636 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5637 return 0;
5638
53aa82da 5639 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
bc7f75fa
AK		 5640 return 0;
5641
5642 {
362e20ca 5643 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
bc7f75fa
AK		 5644 struct udphdr *udp;
5645
5646 if (ip->protocol != IPPROTO_UDP)
5647 return 0;
5648
5649 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5650 if (ntohs(udp->dest) != 67)
5651 return 0;
5652
5653 offset = (u8 *)udp + 8 - skb->data;
5654 length = skb->len - offset;
5655 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5656 }
5657
5658 return 0;
5659}
5660
55aa6985 5661static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5662{
55aa6985 5663 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5664
55aa6985 5665 netif_stop_queue(adapter->netdev);
e921eb1a 5666 /* Herbert's original patch had:
bc7f75fa 5667 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5668 * but since that doesn't exist yet, just open code it.
5669 */
bc7f75fa
AK		 5670 smp_mb();
5671
e921eb1a 5672 /* We need to check again in a case another CPU has just
ad68076e
BA		 5673 * made room available.
5674 */
55aa6985 5675 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5676 return -EBUSY;
5677
5678 /* A reprieve! */
55aa6985 5679 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5680 ++adapter->restart_queue;
5681 return 0;
5682}
5683
55aa6985 5684static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5685{
d821a4c4
BA		 5686 BUG_ON(size > tx_ring->count);
5687
55aa6985 5688 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5689 return 0;
55aa6985 5690 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5691}
5692
3b29a56d
SH		 5693static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5694 struct net_device *netdev)
bc7f75fa
AK		 5695{
5696 struct e1000_adapter *adapter = netdev_priv(netdev);
5697 struct e1000_ring *tx_ring = adapter->tx_ring;
5698 unsigned int first;
bc7f75fa 5699 unsigned int tx_flags = 0;
e743d313 5700 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5701 unsigned int nr_frags;
5702 unsigned int mss;
bc7f75fa
AK		 5703 int count = 0;
5704 int tso;
5705 unsigned int f;
47ccd1ed 5706 __be16 protocol = vlan_get_protocol(skb);
bc7f75fa
AK		 5707
5708 if (test_bit(__E1000_DOWN, &adapter->state)) {
5709 dev_kfree_skb_any(skb);
5710 return NETDEV_TX_OK;
5711 }
5712
5713 if (skb->len <= 0) {
5714 dev_kfree_skb_any(skb);
5715 return NETDEV_TX_OK;
5716 }
5717
e921eb1a 5718 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5719 * pad skb in order to meet this minimum size requirement
5720 */
a94d9e22
AD		 5721 if (skb_put_padto(skb, 17))
5722 return NETDEV_TX_OK;
6e97c170 5723
bc7f75fa 5724 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5725 if (mss) {
5726 u8 hdr_len;
bc7f75fa 5727
e921eb1a 5728 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5729 * points to just header, pull a few bytes of payload from
5730 * frags into skb->data
5731 */
bc7f75fa 5732 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5733 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5734 * avoiding it could save a lot of cycles
5735 */
4e6c709c 5736 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5737 unsigned int pull_size;
5738
a2a5b323 5739 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5740 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5741 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5742 dev_kfree_skb_any(skb);
5743 return NETDEV_TX_OK;
5744 }
e743d313 5745 len = skb_headlen(skb);
bc7f75fa
AK		 5746 }
5747 }
5748
5749 /* reserve a descriptor for the offload context */
5750 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5751 count++;
5752 count++;
5753
d821a4c4 5754 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5755
5756 nr_frags = skb_shinfo(skb)->nr_frags;
5757 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5758 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5759 adapter->tx_fifo_limit);
bc7f75fa
AK		 5760
5761 if (adapter->hw.mac.tx_pkt_filtering)
5762 e1000_transfer_dhcp_info(adapter, skb);
5763
e921eb1a 5764 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5765 * head, otherwise try next time
5766 */
55aa6985 5767 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5768 return NETDEV_TX_BUSY;
bc7f75fa 5769
df8a39de 5770 if (skb_vlan_tag_present(skb)) {
bc7f75fa 5771 tx_flags |= E1000_TX_FLAGS_VLAN;
df8a39de
JP		 5772 tx_flags |= (skb_vlan_tag_get(skb) <<
5773 E1000_TX_FLAGS_VLAN_SHIFT);
bc7f75fa
AK		 5774 }
5775
5776 first = tx_ring->next_to_use;
5777
47ccd1ed 5778 tso = e1000_tso(tx_ring, skb, protocol);
bc7f75fa
AK		 5779 if (tso < 0) {
5780 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5781 return NETDEV_TX_OK;
5782 }
5783
5784 if (tso)
5785 tx_flags |= E1000_TX_FLAGS_TSO;
47ccd1ed 5786 else if (e1000_tx_csum(tx_ring, skb, protocol))
bc7f75fa
AK		 5787 tx_flags |= E1000_TX_FLAGS_CSUM;
5788
e921eb1a 5789 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5790 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5791 * no longer assume, we must.
5792 */
47ccd1ed 5793 if (protocol == htons(ETH_P_IP))
bc7f75fa
AK		 5794 tx_flags |= E1000_TX_FLAGS_IPV4;
5795
943146de
BG		 5796 if (unlikely(skb->no_fcs))
5797 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5798
25985edc 5799 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5800 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5801 nr_frags);
1b7719c4 5802 if (count) {
6930895d
MK		 5803 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5804 (adapter->flags & FLAG_HAS_HW_TIMESTAMP) &&
5805 !adapter->tx_hwtstamp_skb) {
b67e1913
BA		 5806 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5807 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5808 adapter->tx_hwtstamp_skb = skb_get(skb);
59c871c5 5809 adapter->tx_hwtstamp_start = jiffies;
b67e1913
BA		 5810 schedule_work(&adapter->tx_hwtstamp_work);
5811 } else {
5812 skb_tx_timestamp(skb);
5813 }
80be3129 5814
3f0cfa3b 5815 netdev_sent_queue(netdev, skb->len);
55aa6985 5816 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5817 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5818 e1000_maybe_stop_tx(tx_ring,
5819 (MAX_SKB_FRAGS *
5820 DIV_ROUND_UP(PAGE_SIZE,
5821 adapter->tx_fifo_limit) + 2));
472f31f5
FW		 5822
5823 if (!skb->xmit_more ||
5824 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5825 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5826 e1000e_update_tdt_wa(tx_ring,
5827 tx_ring->next_to_use);
5828 else
5829 writel(tx_ring->next_to_use, tx_ring->tail);
5830
5831 /* we need this if more than one processor can write
5832 * to our tail at a time, it synchronizes IO on
5833 *IA64/Altix systems
5834 */
5835 mmiowb();
5836 }
1b7719c4 5837 } else {
bc7f75fa 5838 dev_kfree_skb_any(skb);
1b7719c4
AD		 5839 tx_ring->buffer_info[first].time_stamp = 0;
5840 tx_ring->next_to_use = first;
bc7f75fa
AK		 5841 }
5842
bc7f75fa
AK		 5843 return NETDEV_TX_OK;
5844}
5845
5846/**
5847 * e1000_tx_timeout - Respond to a Tx Hang
5848 * @netdev: network interface device structure
5849 **/
5850static void e1000_tx_timeout(struct net_device *netdev)
5851{
5852 struct e1000_adapter *adapter = netdev_priv(netdev);
5853
5854 /* Do the reset outside of interrupt context */
5855 adapter->tx_timeout_count++;
5856 schedule_work(&adapter->reset_task);
5857}
5858
5859static void e1000_reset_task(struct work_struct *work)
5860{
5861 struct e1000_adapter *adapter;
5862 adapter = container_of(work, struct e1000_adapter, reset_task);
5863
615b32af
JB		 5864 /* don't run the task if already down */
5865 if (test_bit(__E1000_DOWN, &adapter->state))
5866 return;
5867
12d43f7d 5868 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5869 e1000e_dump(adapter);
12d43f7d 5870 e_err("Reset adapter unexpectedly\n");
affa9dfb 5871 }
bc7f75fa
AK		 5872 e1000e_reinit_locked(adapter);
5873}
5874
5875/**
67fd4fcb 5876 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5877 * @netdev: network interface device structure
67fd4fcb 5878 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5879 *
5880 * Returns the address of the device statistics structure.
bc7f75fa 5881 **/
67fd4fcb 5882struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
66501f56 5883 struct rtnl_link_stats64 *stats)
bc7f75fa 5884{
67fd4fcb
JK		 5885 struct e1000_adapter *adapter = netdev_priv(netdev);
5886
5887 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5888 spin_lock(&adapter->stats64_lock);
5889 e1000e_update_stats(adapter);
5890 /* Fill out the OS statistics structure */
5891 stats->rx_bytes = adapter->stats.gorc;
5892 stats->rx_packets = adapter->stats.gprc;
5893 stats->tx_bytes = adapter->stats.gotc;
5894 stats->tx_packets = adapter->stats.gptc;
5895 stats->multicast = adapter->stats.mprc;
5896 stats->collisions = adapter->stats.colc;
5897
5898 /* Rx Errors */
5899
e921eb1a 5900 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5901 * our own version based on RUC and ROC
5902 */
5903 stats->rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 5904 adapter->stats.crcerrs + adapter->stats.algnerrc +
5905 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5906 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
67fd4fcb
JK		 5907 stats->rx_crc_errors = adapter->stats.crcerrs;
5908 stats->rx_frame_errors = adapter->stats.algnerrc;
5909 stats->rx_missed_errors = adapter->stats.mpc;
5910
5911 /* Tx Errors */
f0ff4398 5912 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
67fd4fcb
JK		 5913 stats->tx_aborted_errors = adapter->stats.ecol;
5914 stats->tx_window_errors = adapter->stats.latecol;
5915 stats->tx_carrier_errors = adapter->stats.tncrs;
5916
5917 /* Tx Dropped needs to be maintained elsewhere */
5918
5919 spin_unlock(&adapter->stats64_lock);
5920 return stats;
bc7f75fa
AK		 5921}
5922
5923/**
5924 * e1000_change_mtu - Change the Maximum Transfer Unit
5925 * @netdev: network interface device structure
5926 * @new_mtu: new value for maximum frame size
5927 *
5928 * Returns 0 on success, negative on failure
5929 **/
5930static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5931{
5932 struct e1000_adapter *adapter = netdev_priv(netdev);
8084b86d 5933 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
bc7f75fa 5934
2adc55c9 5935 /* Jumbo frame support */
8084b86d 5936 if ((max_frame > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) &&
2e1706f2
BA		 5937 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5938 e_err("Jumbo Frames not supported.\n");
5939 return -EINVAL;
bc7f75fa
AK		 5940 }
5941
2adc55c9 5942 /* Supported frame sizes */
8084b86d 5943 if ((new_mtu < (VLAN_ETH_ZLEN + ETH_FCS_LEN)) ||
2adc55c9
BA		 5944 (max_frame > adapter->max_hw_frame_size)) {
5945 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5946 return -EINVAL;
5947 }
5948
2fbe4526
BA		 5949 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5950 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5951 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5952 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5953 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5954 return -EINVAL;
5955 }
5956
bc7f75fa 5957 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5958 usleep_range(1000, 2000);
610c9928 5959 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5960 adapter->max_frame_size = max_frame;
610c9928
BA		 5961 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5962 netdev->mtu = new_mtu;
63eb48f1
DE		 5963
5964 pm_runtime_get_sync(netdev->dev.parent);
5965
bc7f75fa 5966 if (netif_running(netdev))
28002099 5967 e1000e_down(adapter, true);
bc7f75fa 5968
e921eb1a 5969 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5970 * means we reserve 2 more, this pushes us to allocate from the next
5971 * larger slab size.
ad68076e 5972 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5973 * However with the new *_jumbo_rx* routines, jumbo receives will use
5974 * fragmented skbs
ad68076e 5975 */
bc7f75fa 5976
9926146b 5977 if (max_frame <= 2048)
bc7f75fa
AK		 5978 adapter->rx_buffer_len = 2048;
5979 else
5980 adapter->rx_buffer_len = 4096;
5981
5982 /* adjust allocation if LPE protects us, and we aren't using SBP */
8084b86d
AD		 5983 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
5984 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
bc7f75fa 5985
bc7f75fa
AK		 5986 if (netif_running(netdev))
5987 e1000e_up(adapter);
5988 else
5989 e1000e_reset(adapter);
5990
63eb48f1
DE		 5991 pm_runtime_put_sync(netdev->dev.parent);
5992
bc7f75fa
AK		 5993 clear_bit(__E1000_RESETTING, &adapter->state);
5994
5995 return 0;
5996}
5997
5998static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5999 int cmd)
6000{
6001 struct e1000_adapter *adapter = netdev_priv(netdev);
6002 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 6003
318a94d6 6004 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 6005 return -EOPNOTSUPP;
6006
6007 switch (cmd) {
6008 case SIOCGMIIPHY:
6009 data->phy_id = adapter->hw.phy.addr;
6010 break;
6011 case SIOCGMIIREG:
b16a002e
BA		 6012 e1000_phy_read_status(adapter);
6013
7c25769f
BA		 6014 switch (data->reg_num & 0x1F) {
6015 case MII_BMCR:
6016 data->val_out = adapter->phy_regs.bmcr;
6017 break;
6018 case MII_BMSR:
6019 data->val_out = adapter->phy_regs.bmsr;
6020 break;
6021 case MII_PHYSID1:
6022 data->val_out = (adapter->hw.phy.id >> 16);
6023 break;
6024 case MII_PHYSID2:
6025 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6026 break;
6027 case MII_ADVERTISE:
6028 data->val_out = adapter->phy_regs.advertise;
6029 break;
6030 case MII_LPA:
6031 data->val_out = adapter->phy_regs.lpa;
6032 break;
6033 case MII_EXPANSION:
6034 data->val_out = adapter->phy_regs.expansion;
6035 break;
6036 case MII_CTRL1000:
6037 data->val_out = adapter->phy_regs.ctrl1000;
6038 break;
6039 case MII_STAT1000:
6040 data->val_out = adapter->phy_regs.stat1000;
6041 break;
6042 case MII_ESTATUS:
6043 data->val_out = adapter->phy_regs.estatus;
6044 break;
6045 default:
bc7f75fa
AK		 6046 return -EIO;
6047 }
bc7f75fa
AK		 6048 break;
6049 case SIOCSMIIREG:
6050 default:
6051 return -EOPNOTSUPP;
6052 }
6053 return 0;
6054}
6055
b67e1913
BA		 6056/**
6057 * e1000e_hwtstamp_ioctl - control hardware time stamping
6058 * @netdev: network interface device structure
6059 * @ifreq: interface request
6060 *
6061 * Outgoing time stamping can be enabled and disabled. Play nice and
6062 * disable it when requested, although it shouldn't cause any overhead
6063 * when no packet needs it. At most one packet in the queue may be
6064 * marked for time stamping, otherwise it would be impossible to tell
6065 * for sure to which packet the hardware time stamp belongs.
6066 *
6067 * Incoming time stamping has to be configured via the hardware filters.
6068 * Not all combinations are supported, in particular event type has to be
6069 * specified. Matching the kind of event packet is not supported, with the
6070 * exception of "all V2 events regardless of level 2 or 4".
6071 **/
4e8cff64 6072static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
b67e1913
BA		 6073{
6074 struct e1000_adapter *adapter = netdev_priv(netdev);
6075 struct hwtstamp_config config;
6076 int ret_val;
6077
6078 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6079 return -EFAULT;
6080
62d7e3a2 6081 ret_val = e1000e_config_hwtstamp(adapter, &config);
b67e1913
BA		 6082 if (ret_val)
6083 return ret_val;
6084
d89777bf
BA		 6085 switch (config.rx_filter) {
6086 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6087 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6088 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6089 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6090 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6091 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6092 /* With V2 type filters which specify a Sync or Delay Request,
6093 * Path Delay Request/Response messages are also time stamped
6094 * by hardware so notify the caller the requested packets plus
6095 * some others are time stamped.
6096 */
6097 config.rx_filter = HWTSTAMP_FILTER_SOME;
6098 break;
6099 default:
6100 break;
6101 }
6102
b67e1913
BA		 6103 return copy_to_user(ifr->ifr_data, &config,
6104 sizeof(config)) ? -EFAULT : 0;
6105}
6106
4e8cff64
BH		 6107static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6108{
6109 struct e1000_adapter *adapter = netdev_priv(netdev);
6110
6111 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6112 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6113}
6114
bc7f75fa
AK		 6115static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6116{
6117 switch (cmd) {
6118 case SIOCGMIIPHY:
6119 case SIOCGMIIREG:
6120 case SIOCSMIIREG:
6121 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913 6122 case SIOCSHWTSTAMP:
4e8cff64
BH		 6123 return e1000e_hwtstamp_set(netdev, ifr);
6124 case SIOCGHWTSTAMP:
6125 return e1000e_hwtstamp_get(netdev, ifr);
bc7f75fa
AK		 6126 default:
6127 return -EOPNOTSUPP;
6128 }
6129}
6130
a4f58f54
BA		 6131static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6132{
6133 struct e1000_hw *hw = &adapter->hw;
74f350ee 6134 u32 i, mac_reg, wuc;
2b6b168d 6135 u16 phy_reg, wuc_enable;
70806a7f 6136 int retval;
a4f58f54
BA		 6137
6138 /* copy MAC RARs to PHY RARs */
d3738bb8 6139 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 6140
2b6b168d
BA		 6141 retval = hw->phy.ops.acquire(hw);
6142 if (retval) {
6143 e_err("Could not acquire PHY\n");
6144 return retval;
6145 }
6146
6147 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6148 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6149 if (retval)
75ce1532 6150 goto release;
2b6b168d
BA		 6151
6152 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 6153 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6154 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 6155 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6156 (u16)(mac_reg & 0xFFFF));
6157 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6158 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 6159 }
6160
6161 /* configure PHY Rx Control register */
2b6b168d 6162 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 6163 mac_reg = er32(RCTL);
6164 if (mac_reg & E1000_RCTL_UPE)
6165 phy_reg |= BM_RCTL_UPE;
6166 if (mac_reg & E1000_RCTL_MPE)
6167 phy_reg |= BM_RCTL_MPE;
6168 phy_reg &= ~(BM_RCTL_MO_MASK);
6169 if (mac_reg & E1000_RCTL_MO_3)
6170 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
17e813ec 6171 << BM_RCTL_MO_SHIFT);
a4f58f54
BA		 6172 if (mac_reg & E1000_RCTL_BAM)
6173 phy_reg |= BM_RCTL_BAM;
6174 if (mac_reg & E1000_RCTL_PMCF)
6175 phy_reg |= BM_RCTL_PMCF;
6176 mac_reg = er32(CTRL);
6177 if (mac_reg & E1000_CTRL_RFCE)
6178 phy_reg |= BM_RCTL_RFCE;
2b6b168d 6179 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54 6180
74f350ee
DE		 6181 wuc = E1000_WUC_PME_EN;
6182 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6183 wuc |= E1000_WUC_APME;
6184
a4f58f54
BA		 6185 /* enable PHY wakeup in MAC register */
6186 ew32(WUFC, wufc);
74f350ee
DE		 6187 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6188 E1000_WUC_PME_STATUS | wuc));
a4f58f54
BA		 6189
6190 /* configure and enable PHY wakeup in PHY registers */
2b6b168d 6191 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
74f350ee 6192 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
a4f58f54
BA		 6193
6194 /* activate PHY wakeup */
2b6b168d
BA		 6195 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6196 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 6197 if (retval)
6198 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 6199release:
94d8186a 6200 hw->phy.ops.release(hw);
a4f58f54
BA		 6201
6202 return retval;
6203}
6204
2a7e19af
DE		 6205static void e1000e_flush_lpic(struct pci_dev *pdev)
6206{
6207 struct net_device *netdev = pci_get_drvdata(pdev);
6208 struct e1000_adapter *adapter = netdev_priv(netdev);
6209 struct e1000_hw *hw = &adapter->hw;
6210 u32 ret_val;
6211
6212 pm_runtime_get_sync(netdev->dev.parent);
6213
6214 ret_val = hw->phy.ops.acquire(hw);
6215 if (ret_val)
6216 goto fl_out;
6217
6218 pr_info("EEE TX LPI TIMER: %08X\n",
6219 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6220
6221 hw->phy.ops.release(hw);
6222
6223fl_out:
6224 pm_runtime_put_sync(netdev->dev.parent);
6225}
6226
28002099 6227static int e1000e_pm_freeze(struct device *dev)
bc7f75fa 6228{
28002099 6229 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
bc7f75fa 6230 struct e1000_adapter *adapter = netdev_priv(netdev);
bc7f75fa
AK		 6231
6232 netif_device_detach(netdev);
6233
6234 if (netif_running(netdev)) {
bb9e44d0
BA		 6235 int count = E1000_CHECK_RESET_COUNT;
6236
6237 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6238 usleep_range(10000, 20000);
6239
bc7f75fa 6240 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
28002099
DE		 6241
6242 /* Quiesce the device without resetting the hardware */
6243 e1000e_down(adapter, false);
bc7f75fa
AK		 6244 e1000_free_irq(adapter);
6245 }
4662e82b 6246 e1000e_reset_interrupt_capability(adapter);
bc7f75fa 6247
28002099
DE		 6248 /* Allow time for pending master requests to run */
6249 e1000e_disable_pcie_master(&adapter->hw);
6250
6251 return 0;
6252}
6253
6254static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6255{
6256 struct net_device *netdev = pci_get_drvdata(pdev);
6257 struct e1000_adapter *adapter = netdev_priv(netdev);
6258 struct e1000_hw *hw = &adapter->hw;
6259 u32 ctrl, ctrl_ext, rctl, status;
6260 /* Runtime suspend should only enable wakeup for link changes */
6261 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6262 int retval = 0;
6263
bc7f75fa
AK		 6264 status = er32(STATUS);
6265 if (status & E1000_STATUS_LU)
6266 wufc &= ~E1000_WUFC_LNKC;
6267
6268 if (wufc) {
6269 e1000_setup_rctl(adapter);
ef9b965a 6270 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 6271
6272 /* turn on all-multi mode if wake on multicast is enabled */
6273 if (wufc & E1000_WUFC_MC) {
6274 rctl = er32(RCTL);
6275 rctl |= E1000_RCTL_MPE;
6276 ew32(RCTL, rctl);
6277 }
6278
6279 ctrl = er32(CTRL);
a4f58f54
BA		 6280 ctrl |= E1000_CTRL_ADVD3WUC;
6281 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6282 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 6283 ew32(CTRL, ctrl);
6284
318a94d6
JK		 6285 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6286 adapter->hw.phy.media_type ==
6287 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 6288 /* keep the laser running in D3 */
6289 ctrl_ext = er32(CTRL_EXT);
93a23f48 6290 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 6291 ew32(CTRL_EXT, ctrl_ext);
6292 }
6293
63eb48f1
DE		 6294 if (!runtime)
6295 e1000e_power_up_phy(adapter);
6296
97ac8cae 6297 if (adapter->flags & FLAG_IS_ICH)
99730e4c 6298 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 6299
82776a4b 6300 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 6301 /* enable wakeup by the PHY */
6302 retval = e1000_init_phy_wakeup(adapter, wufc);
6303 if (retval)
6304 return retval;
6305 } else {
6306 /* enable wakeup by the MAC */
6307 ew32(WUFC, wufc);
6308 ew32(WUC, E1000_WUC_PME_EN);
6309 }
bc7f75fa
AK		 6310 } else {
6311 ew32(WUC, 0);
6312 ew32(WUFC, 0);
28002099
DE		 6313
6314 e1000_power_down_phy(adapter);
bc7f75fa
AK		 6315 }
6316
74f350ee 6317 if (adapter->hw.phy.type == e1000_phy_igp_3) {
bc7f75fa 6318 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
79849ebc
DE		 6319 } else if ((hw->mac.type == e1000_pch_lpt) ||
6320 (hw->mac.type == e1000_pch_spt)) {
74f350ee
DE		 6321 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6322 /* ULP does not support wake from unicast, multicast
6323 * or broadcast.
6324 */
6325 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6326
6327 if (retval)
6328 return retval;
6329 }
6330
f5ac7445
RA		 6331 /* Ensure that the appropriate bits are set in LPI_CTRL
6332 * for EEE in Sx
6333 */
6334 if ((hw->phy.type >= e1000_phy_i217) &&
6335 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6336 u16 lpi_ctrl = 0;
6337
6338 retval = hw->phy.ops.acquire(hw);
6339 if (!retval) {
6340 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6341 &lpi_ctrl);
6342 if (!retval) {
6343 if (adapter->eee_advert &
6344 hw->dev_spec.ich8lan.eee_lp_ability &
6345 I82579_EEE_100_SUPPORTED)
6346 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6347 if (adapter->eee_advert &
6348 hw->dev_spec.ich8lan.eee_lp_ability &
6349 I82579_EEE_1000_SUPPORTED)
6350 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6351
6352 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6353 lpi_ctrl);
6354 }
6355 }
6356 hw->phy.ops.release(hw);
6357 }
bc7f75fa 6358
e921eb1a 6359 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6360 * would have already happened in close and is redundant.
6361 */
31dbe5b4 6362 e1000e_release_hw_control(adapter);
bc7f75fa 6363
24b41c97
DN		 6364 pci_clear_master(pdev);
6365
e921eb1a 6366 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 6367 * correctable error when the MAC transitions from D0 to D3. To
6368 * prevent this we need to mask off the correctable errors on the
6369 * downstream port of the pci-e switch.
e8c254c5
LZ		 6370 *
6371 * We don't have the associated upstream bridge while assigning
6372 * the PCI device into guest. For example, the KVM on power is
6373 * one of the cases.
005cbdfc
AD		 6374 */
6375 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6376 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 6377 u16 devctl;
6378
e8c254c5
LZ		 6379 if (!us_dev)
6380 return 0;
6381
f8c0fcac
JL		 6382 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6383 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6384 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6385
66148bab
KK		 6386 pci_save_state(pdev);
6387 pci_prepare_to_sleep(pdev);
005cbdfc 6388
f8c0fcac 6389 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6390 }
66148bab
KK		 6391
6392 return 0;
bc7f75fa
AK		 6393}
6394
13129d9b 6395/**
beb0a152 6396 * __e1000e_disable_aspm - Disable ASPM states
13129d9b
CW		 6397 * @pdev: pointer to PCI device struct
6398 * @state: bit-mask of ASPM states to disable
beb0a152 6399 * @locked: indication if this context holds pci_bus_sem locked.
13129d9b
CW		 6400 *
6401 * Some devices *must* have certain ASPM states disabled per hardware errata.
6402 **/
beb0a152 6403static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6f461f6c 6404{
13129d9b
CW		 6405 struct pci_dev *parent = pdev->bus->self;
6406 u16 aspm_dis_mask = 0;
6407 u16 pdev_aspmc, parent_aspmc;
6408
6409 switch (state) {
6410 case PCIE_LINK_STATE_L0S:
6411 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6412 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6413 /* fall-through - can't have L1 without L0s */
6414 case PCIE_LINK_STATE_L1:
6415 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6416 break;
6417 default:
6418 return;
6419 }
6420
6421 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6422 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6423
6424 if (parent) {
6425 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6426 &parent_aspmc);
6427 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6428 }
6429
6430 /* Nothing to do if the ASPM states to be disabled already are */
6431 if (!(pdev_aspmc & aspm_dis_mask) &&
6432 (!parent || !(parent_aspmc & aspm_dis_mask)))
6433 return;
6434
6435 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6436 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6437 "L0s" : "",
6438 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6439 "L1" : "");
6440
6441#ifdef CONFIG_PCIEASPM
beb0a152
YL		 6442 if (locked)
6443 pci_disable_link_state_locked(pdev, state);
6444 else
6445 pci_disable_link_state(pdev, state);
ffe0b2ff 6446
13129d9b
CW		 6447 /* Double-check ASPM control. If not disabled by the above, the
6448 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6449 * not enabled); override by writing PCI config space directly.
6450 */
6451 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6452 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6453
6454 if (!(aspm_dis_mask & pdev_aspmc))
6455 return;
6456#endif
ffe0b2ff 6457
e921eb1a 6458 /* Both device and parent should have the same ASPM setting.
6f461f6c 6459 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6460 */
13129d9b 6461 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6f461f6c 6462
13129d9b
CW		 6463 if (parent)
6464 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6465 aspm_dis_mask);
1eae4eb2
AK		 6466}
6467
beb0a152
YL		 6468/**
6469 * e1000e_disable_aspm - Disable ASPM states.
6470 * @pdev: pointer to PCI device struct
6471 * @state: bit-mask of ASPM states to disable
6472 *
6473 * This function acquires the pci_bus_sem!
6474 * Some devices *must* have certain ASPM states disabled per hardware errata.
6475 **/
6476static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6477{
6478 __e1000e_disable_aspm(pdev, state, 0);
6479}
6480
6481/**
6482 * e1000e_disable_aspm_locked Disable ASPM states.
6483 * @pdev: pointer to PCI device struct
6484 * @state: bit-mask of ASPM states to disable
6485 *
6486 * This function must be called with pci_bus_sem acquired!
6487 * Some devices *must* have certain ASPM states disabled per hardware errata.
6488 **/
6489static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6490{
6491 __e1000e_disable_aspm(pdev, state, 1);
6492}
6493
aa338601 6494#ifdef CONFIG_PM
23606cf5 6495static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6496{
6497 struct net_device *netdev = pci_get_drvdata(pdev);
6498 struct e1000_adapter *adapter = netdev_priv(netdev);
6499 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6500 u16 aspm_disable_flag = 0;
bc7f75fa 6501
78cd29d5
BA		 6502 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6503 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6504 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6505 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6506 if (aspm_disable_flag)
2758f9ed 6507 e1000e_disable_aspm(pdev, aspm_disable_flag);
78cd29d5 6508
66148bab 6509 pci_set_master(pdev);
6e4f6f6b 6510
2fbe4526 6511 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6512 e1000_resume_workarounds_pchlan(&adapter->hw);
6513
bc7f75fa 6514 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6515
6516 /* report the system wakeup cause from S3/S4 */
6517 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6518 u16 phy_data;
6519
6520 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6521 if (phy_data) {
6522 e_info("PHY Wakeup cause - %s\n",
17e813ec
BA		 6523 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6524 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6525 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6526 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6527 phy_data & E1000_WUS_LNKC ?
6528 "Link Status Change" : "other");
a4f58f54
BA		 6529 }
6530 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6531 } else {
6532 u32 wus = er32(WUS);
6cf08d1c 6533
a4f58f54
BA		 6534 if (wus) {
6535 e_info("MAC Wakeup cause - %s\n",
17e813ec
BA		 6536 wus & E1000_WUS_EX ? "Unicast Packet" :
6537 wus & E1000_WUS_MC ? "Multicast Packet" :
6538 wus & E1000_WUS_BC ? "Broadcast Packet" :
6539 wus & E1000_WUS_MAG ? "Magic Packet" :
6540 wus & E1000_WUS_LNKC ? "Link Status Change" :
6541 "other");
a4f58f54
BA		 6542 }
6543 ew32(WUS, ~0);
6544 }
6545
bc7f75fa 6546 e1000e_reset(adapter);
bc7f75fa 6547
cd791618 6548 e1000_init_manageability_pt(adapter);
bc7f75fa 6549
e921eb1a 6550 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6551 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6552 * under the control of the driver.
6553 */
c43bc57e 6554 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6555 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6556
6557 return 0;
6558}
23606cf5 6559
3e7986f6 6560#ifdef CONFIG_PM_SLEEP
28002099
DE		 6561static int e1000e_pm_thaw(struct device *dev)
6562{
6563 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6564 struct e1000_adapter *adapter = netdev_priv(netdev);
6565
6566 e1000e_set_interrupt_capability(adapter);
6567 if (netif_running(netdev)) {
6568 u32 err = e1000_request_irq(adapter);
6569
6570 if (err)
6571 return err;
6572
6573 e1000e_up(adapter);
6574 }
6575
6576 netif_device_attach(netdev);
6577
6578 return 0;
6579}
6580
28002099 6581static int e1000e_pm_suspend(struct device *dev)
a0340162
RW		 6582{
6583 struct pci_dev *pdev = to_pci_dev(dev);
a0340162 6584
2a7e19af
DE		 6585 e1000e_flush_lpic(pdev);
6586
28002099
DE		 6587 e1000e_pm_freeze(dev);
6588
66148bab 6589 return __e1000_shutdown(pdev, false);
a0340162
RW		 6590}
6591
28002099 6592static int e1000e_pm_resume(struct device *dev)
23606cf5
RW		 6593{
6594 struct pci_dev *pdev = to_pci_dev(dev);
28002099 6595 int rc;
23606cf5 6596
28002099
DE		 6597 rc = __e1000_resume(pdev);
6598 if (rc)
6599 return rc;
23606cf5 6600
28002099 6601 return e1000e_pm_thaw(dev);
23606cf5 6602}
38a529b5 6603#endif /* CONFIG_PM_SLEEP */
a0340162 6604
63eb48f1 6605static int e1000e_pm_runtime_idle(struct device *dev)
a0340162
RW		 6606{
6607 struct pci_dev *pdev = to_pci_dev(dev);
6608 struct net_device *netdev = pci_get_drvdata(pdev);
6609 struct e1000_adapter *adapter = netdev_priv(netdev);
2116bc25 6610 u16 eee_lp;
a0340162 6611
2116bc25
DE		 6612 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
6613
6614 if (!e1000e_has_link(adapter)) {
6615 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
63eb48f1 6616 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
2116bc25 6617 }
a0340162 6618
63eb48f1 6619 return -EBUSY;
a0340162
RW		 6620}
6621
63eb48f1 6622static int e1000e_pm_runtime_resume(struct device *dev)
a0340162
RW		 6623{
6624 struct pci_dev *pdev = to_pci_dev(dev);
6625 struct net_device *netdev = pci_get_drvdata(pdev);
6626 struct e1000_adapter *adapter = netdev_priv(netdev);
63eb48f1 6627 int rc;
a0340162 6628
63eb48f1
DE		 6629 rc = __e1000_resume(pdev);
6630 if (rc)
6631 return rc;
a0340162 6632
63eb48f1
DE		 6633 if (netdev->flags & IFF_UP)
6634 rc = e1000e_up(adapter);
a0340162 6635
63eb48f1 6636 return rc;
a0340162 6637}
23606cf5 6638
63eb48f1 6639static int e1000e_pm_runtime_suspend(struct device *dev)
23606cf5
RW		 6640{
6641 struct pci_dev *pdev = to_pci_dev(dev);
6642 struct net_device *netdev = pci_get_drvdata(pdev);
6643 struct e1000_adapter *adapter = netdev_priv(netdev);
6644
63eb48f1
DE		 6645 if (netdev->flags & IFF_UP) {
6646 int count = E1000_CHECK_RESET_COUNT;
6647
6648 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6649 usleep_range(10000, 20000);
23606cf5 6650
63eb48f1
DE		 6651 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6652
6653 /* Down the device without resetting the hardware */
6654 e1000e_down(adapter, false);
6655 }
6656
6657 if (__e1000_shutdown(pdev, true)) {
6658 e1000e_pm_runtime_resume(dev);
6659 return -EBUSY;
6660 }
6661
6662 return 0;
23606cf5 6663}
aa338601 6664#endif /* CONFIG_PM */
bc7f75fa
AK		 6665
6666static void e1000_shutdown(struct pci_dev *pdev)
6667{
2a7e19af
DE		 6668 e1000e_flush_lpic(pdev);
6669
28002099
DE		 6670 e1000e_pm_freeze(&pdev->dev);
6671
66148bab 6672 __e1000_shutdown(pdev, false);
bc7f75fa
AK		 6673}
6674
6675#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c 6676
8bb62869 6677static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
147b2c8c
DD		 6678{
6679 struct net_device *netdev = data;
6680 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6681
6682 if (adapter->msix_entries) {
90da0669
BA		 6683 int vector, msix_irq;
6684
147b2c8c
DD		 6685 vector = 0;
6686 msix_irq = adapter->msix_entries[vector].vector;
6687 disable_irq(msix_irq);
6688 e1000_intr_msix_rx(msix_irq, netdev);
6689 enable_irq(msix_irq);
6690
6691 vector++;
6692 msix_irq = adapter->msix_entries[vector].vector;
6693 disable_irq(msix_irq);
6694 e1000_intr_msix_tx(msix_irq, netdev);
6695 enable_irq(msix_irq);
6696
6697 vector++;
6698 msix_irq = adapter->msix_entries[vector].vector;
6699 disable_irq(msix_irq);
6700 e1000_msix_other(msix_irq, netdev);
6701 enable_irq(msix_irq);
6702 }
6703
6704 return IRQ_HANDLED;
6705}
6706
e921eb1a
BA		 6707/**
6708 * e1000_netpoll
6709 * @netdev: network interface device structure
6710 *
bc7f75fa
AK		 6711 * Polling 'interrupt' - used by things like netconsole to send skbs
6712 * without having to re-enable interrupts. It's not called while
6713 * the interrupt routine is executing.
6714 */
6715static void e1000_netpoll(struct net_device *netdev)
6716{
6717 struct e1000_adapter *adapter = netdev_priv(netdev);
6718
147b2c8c
DD		 6719 switch (adapter->int_mode) {
6720 case E1000E_INT_MODE_MSIX:
6721 e1000_intr_msix(adapter->pdev->irq, netdev);
6722 break;
6723 case E1000E_INT_MODE_MSI:
6724 disable_irq(adapter->pdev->irq);
6725 e1000_intr_msi(adapter->pdev->irq, netdev);
6726 enable_irq(adapter->pdev->irq);
6727 break;
e80bd1d1 6728 default: /* E1000E_INT_MODE_LEGACY */
147b2c8c
DD		 6729 disable_irq(adapter->pdev->irq);
6730 e1000_intr(adapter->pdev->irq, netdev);
6731 enable_irq(adapter->pdev->irq);
6732 break;
6733 }
bc7f75fa
AK		 6734}
6735#endif
6736
6737/**
6738 * e1000_io_error_detected - called when PCI error is detected
6739 * @pdev: Pointer to PCI device
6740 * @state: The current pci connection state
6741 *
6742 * This function is called after a PCI bus error affecting
6743 * this device has been detected.
6744 */
6745static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6746 pci_channel_state_t state)
6747{
6748 struct net_device *netdev = pci_get_drvdata(pdev);
6749 struct e1000_adapter *adapter = netdev_priv(netdev);
6750
6751 netif_device_detach(netdev);
6752
c93b5a76
MM		 6753 if (state == pci_channel_io_perm_failure)
6754 return PCI_ERS_RESULT_DISCONNECT;
6755
bc7f75fa 6756 if (netif_running(netdev))
28002099 6757 e1000e_down(adapter, true);
bc7f75fa
AK		 6758 pci_disable_device(pdev);
6759
6760 /* Request a slot slot reset. */
6761 return PCI_ERS_RESULT_NEED_RESET;
6762}
6763
6764/**
6765 * e1000_io_slot_reset - called after the pci bus has been reset.
6766 * @pdev: Pointer to PCI device
6767 *
6768 * Restart the card from scratch, as if from a cold-boot. Implementation
28002099 6769 * resembles the first-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6770 */
6771static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6772{
6773 struct net_device *netdev = pci_get_drvdata(pdev);
6774 struct e1000_adapter *adapter = netdev_priv(netdev);
6775 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6776 u16 aspm_disable_flag = 0;
6e4f6f6b 6777 int err;
111b9dc5 6778 pci_ers_result_t result;
bc7f75fa 6779
78cd29d5
BA		 6780 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6781 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6782 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6783 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6784 if (aspm_disable_flag)
2758f9ed 6785 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
78cd29d5 6786
f0f422e5 6787 err = pci_enable_device_mem(pdev);
6e4f6f6b 6788 if (err) {
bc7f75fa
AK		 6789 dev_err(&pdev->dev,
6790 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6791 result = PCI_ERS_RESULT_DISCONNECT;
6792 } else {
23606cf5 6793 pdev->state_saved = true;
111b9dc5 6794 pci_restore_state(pdev);
66148bab 6795 pci_set_master(pdev);
bc7f75fa 6796
111b9dc5
JB		 6797 pci_enable_wake(pdev, PCI_D3hot, 0);
6798 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6799
111b9dc5
JB		 6800 e1000e_reset(adapter);
6801 ew32(WUS, ~0);
6802 result = PCI_ERS_RESULT_RECOVERED;
6803 }
bc7f75fa 6804
111b9dc5
JB		 6805 pci_cleanup_aer_uncorrect_error_status(pdev);
6806
6807 return result;
bc7f75fa
AK		 6808}
6809
6810/**
6811 * e1000_io_resume - called when traffic can start flowing again.
6812 * @pdev: Pointer to PCI device
6813 *
6814 * This callback is called when the error recovery driver tells us that
6815 * its OK to resume normal operation. Implementation resembles the
28002099 6816 * second-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6817 */
6818static void e1000_io_resume(struct pci_dev *pdev)
6819{
6820 struct net_device *netdev = pci_get_drvdata(pdev);
6821 struct e1000_adapter *adapter = netdev_priv(netdev);
6822
cd791618 6823 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6824
6825 if (netif_running(netdev)) {
6826 if (e1000e_up(adapter)) {
6827 dev_err(&pdev->dev,
6828 "can't bring device back up after reset\n");
6829 return;
6830 }
6831 }
6832
6833 netif_device_attach(netdev);
6834
e921eb1a 6835 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6836 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6837 * under the control of the driver.
6838 */
c43bc57e 6839 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6840 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6841}
6842
6843static void e1000_print_device_info(struct e1000_adapter *adapter)
6844{
6845 struct e1000_hw *hw = &adapter->hw;
6846 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6847 u32 ret_val;
6848 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6849
6850 /* print bus type/speed/width info */
a5cc7642 6851 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6852 /* bus width */
6853 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
f0ff4398 6854 "Width x1"),
44defeb3 6855 /* MAC address */
7c510e4b 6856 netdev->dev_addr);
44defeb3
JK		 6857 e_info("Intel(R) PRO/%s Network Connection\n",
6858 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6859 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6860 E1000_PBANUM_LENGTH);
6861 if (ret_val)
f2315bf1 6862 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6863 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6864 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6865}
6866
10aa4c04
AK		 6867static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6868{
6869 struct e1000_hw *hw = &adapter->hw;
6870 int ret_val;
6871 u16 buf = 0;
6872
6873 if (hw->mac.type != e1000_82573)
6874 return;
6875
6876 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6877 le16_to_cpus(&buf);
6878 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6879 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6880 dev_warn(&adapter->pdev->dev,
6881 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6882 }
10aa4c04
AK		 6883}
6884
55e7fe5b
AD		 6885static netdev_features_t e1000_fix_features(struct net_device *netdev,
6886 netdev_features_t features)
6887{
6888 struct e1000_adapter *adapter = netdev_priv(netdev);
6889 struct e1000_hw *hw = &adapter->hw;
6890
6891 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6892 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
6893 features &= ~NETIF_F_RXFCS;
6894
6895 return features;
6896}
6897
c8f44aff 6898static int e1000_set_features(struct net_device *netdev,
70495a50 6899 netdev_features_t features)
dc221294
BA		 6900{
6901 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6902 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6903
6904 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6905 adapter->flags |= FLAG_TSO_FORCE;
6906
f646968f 6907 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
cf955e6c
BG		 6908 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6909 NETIF_F_RXALL)))
dc221294
BA		 6910 return 0;
6911
0184039a
BG		 6912 if (changed & NETIF_F_RXFCS) {
6913 if (features & NETIF_F_RXFCS) {
6914 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6915 } else {
6916 /* We need to take it back to defaults, which might mean
6917 * stripping is still disabled at the adapter level.
6918 */
6919 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6920 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6921 else
6922 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6923 }
6924 }
6925
70495a50
BA		 6926 netdev->features = features;
6927
dc221294
BA		 6928 if (netif_running(netdev))
6929 e1000e_reinit_locked(adapter);
6930 else
6931 e1000e_reset(adapter);
6932
6933 return 0;
6934}
6935
651c2466
SH		 6936static const struct net_device_ops e1000e_netdev_ops = {
6937 .ndo_open = e1000_open,
6938 .ndo_stop = e1000_close,
00829823 6939 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6940 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6941 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6942 .ndo_set_mac_address = e1000_set_mac,
6943 .ndo_change_mtu = e1000_change_mtu,
6944 .ndo_do_ioctl = e1000_ioctl,
6945 .ndo_tx_timeout = e1000_tx_timeout,
6946 .ndo_validate_addr = eth_validate_addr,
6947
651c2466
SH		 6948 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6949 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6950#ifdef CONFIG_NET_POLL_CONTROLLER
6951 .ndo_poll_controller = e1000_netpoll,
6952#endif
dc221294 6953 .ndo_set_features = e1000_set_features,
55e7fe5b 6954 .ndo_fix_features = e1000_fix_features,
f2701b18 6955 .ndo_features_check = passthru_features_check,
651c2466
SH		 6956};
6957
bc7f75fa
AK		 6958/**
6959 * e1000_probe - Device Initialization Routine
6960 * @pdev: PCI device information struct
6961 * @ent: entry in e1000_pci_tbl
6962 *
6963 * Returns 0 on success, negative on failure
6964 *
6965 * e1000_probe initializes an adapter identified by a pci_dev structure.
6966 * The OS initialization, configuring of the adapter private structure,
6967 * and a hardware reset occur.
6968 **/
1dd06ae8 6969static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6970{
6971 struct net_device *netdev;
6972 struct e1000_adapter *adapter;
6973 struct e1000_hw *hw;
6974 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6975 resource_size_t mmio_start, mmio_len;
6976 resource_size_t flash_start, flash_len;
bc7f75fa 6977 static int cards_found;
78cd29d5 6978 u16 aspm_disable_flag = 0;
17e813ec 6979 int bars, i, err, pci_using_dac;
bc7f75fa
AK		 6980 u16 eeprom_data = 0;
6981 u16 eeprom_apme_mask = E1000_EEPROM_APME;
491a04d2 6982 s32 rval = 0;
bc7f75fa 6983
78cd29d5
BA		 6984 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6985 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6986 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6987 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6988 if (aspm_disable_flag)
6989 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6990
f0f422e5 6991 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6992 if (err)
6993 return err;
6994
6995 pci_using_dac = 0;
718a39eb 6996 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6997 if (!err) {
718a39eb 6998 pci_using_dac = 1;
bc7f75fa 6999 } else {
718a39eb 7000 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 7001 if (err) {
718a39eb
RK		 7002 dev_err(&pdev->dev,
7003 "No usable DMA configuration, aborting\n");
7004 goto err_dma;
bc7f75fa
AK		 7005 }
7006 }
7007
17e813ec
BA		 7008 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7009 err = pci_request_selected_regions_exclusive(pdev, bars,
7010 e1000e_driver_name);
bc7f75fa
AK		 7011 if (err)
7012 goto err_pci_reg;
7013
68eac460 7014 /* AER (Advanced Error Reporting) hooks */
19d5afd4 7015 pci_enable_pcie_error_reporting(pdev);
68eac460 7016
bc7f75fa 7017 pci_set_master(pdev);
438b365a
BA		 7018 /* PCI config space info */
7019 err = pci_save_state(pdev);
7020 if (err)
7021 goto err_alloc_etherdev;
bc7f75fa
AK		 7022
7023 err = -ENOMEM;
7024 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7025 if (!netdev)
7026 goto err_alloc_etherdev;
7027
bc7f75fa
AK		 7028 SET_NETDEV_DEV(netdev, &pdev->dev);
7029
f85e4dfa
TH		 7030 netdev->irq = pdev->irq;
7031
bc7f75fa
AK		 7032 pci_set_drvdata(pdev, netdev);
7033 adapter = netdev_priv(netdev);
7034 hw = &adapter->hw;
7035 adapter->netdev = netdev;
7036 adapter->pdev = pdev;
7037 adapter->ei = ei;
7038 adapter->pba = ei->pba;
7039 adapter->flags = ei->flags;
eb7c3adb 7040 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 7041 adapter->hw.adapter = adapter;
7042 adapter->hw.mac.type = ei->mac;
2adc55c9 7043 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 7044 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 7045
7046 mmio_start = pci_resource_start(pdev, 0);
7047 mmio_len = pci_resource_len(pdev, 0);
7048
7049 err = -EIO;
7050 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7051 if (!adapter->hw.hw_addr)
7052 goto err_ioremap;
7053
7054 if ((adapter->flags & FLAG_HAS_FLASH) &&
1103a631
YL		 7055 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7056 (hw->mac.type < e1000_pch_spt)) {
bc7f75fa
AK		 7057 flash_start = pci_resource_start(pdev, 1);
7058 flash_len = pci_resource_len(pdev, 1);
7059 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7060 if (!adapter->hw.flash_address)
7061 goto err_flashmap;
7062 }
7063
d495bcb8
BA		 7064 /* Set default EEE advertisement */
7065 if (adapter->flags2 & FLAG2_HAS_EEE)
7066 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7067
bc7f75fa 7068 /* construct the net_device struct */
e80bd1d1 7069 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 7070 e1000e_set_ethtool_ops(netdev);
e80bd1d1 7071 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 7072 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 7073 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 7074
7075 netdev->mem_start = mmio_start;
7076 netdev->mem_end = mmio_start + mmio_len;
7077
7078 adapter->bd_number = cards_found++;
7079
4662e82b
BA		 7080 e1000e_check_options(adapter);
7081
bc7f75fa
AK		 7082 /* setup adapter struct */
7083 err = e1000_sw_init(adapter);
7084 if (err)
7085 goto err_sw_init;
7086
bc7f75fa
AK		 7087 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7088 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7089 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7090
69e3fd8c 7091 err = ei->get_variants(adapter);
bc7f75fa
AK		 7092 if (err)
7093 goto err_hw_init;
7094
4a770358 7095 if ((adapter->flags & FLAG_IS_ICH) &&
152c0a97
YL		 7096 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7097 (hw->mac.type < e1000_pch_spt))
4a770358
BA		 7098 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7099
bc7f75fa
AK		 7100 hw->mac.ops.get_bus_info(&adapter->hw);
7101
318a94d6 7102 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 7103
7104 /* Copper options */
318a94d6 7105 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 7106 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7107 adapter->hw.phy.disable_polarity_correction = 0;
7108 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7109 }
7110
470a5420 7111 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 7112 dev_info(&pdev->dev,
7113 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 7114
dc221294
BA		 7115 /* Set initial default active device features */
7116 netdev->features = (NETIF_F_SG |
f646968f
PM		 7117 NETIF_F_HW_VLAN_CTAG_RX |
7118 NETIF_F_HW_VLAN_CTAG_TX |
dc221294
BA		 7119 NETIF_F_TSO |
7120 NETIF_F_TSO6 |
70495a50 7121 NETIF_F_RXHASH |
dc221294
BA		 7122 NETIF_F_RXCSUM |
7123 NETIF_F_HW_CSUM);
7124
7125 /* Set user-changeable features (subset of all device features) */
7126 netdev->hw_features = netdev->features;
0184039a 7127 netdev->hw_features |= NETIF_F_RXFCS;
943146de 7128 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 7129 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 7130
7131 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
f646968f 7132 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
bc7f75fa 7133
dc221294
BA		 7134 netdev->vlan_features |= (NETIF_F_SG |
7135 NETIF_F_TSO |
7136 NETIF_F_TSO6 |
7137 NETIF_F_HW_CSUM);
a5136e23 7138
ef9b965a
JB		 7139 netdev->priv_flags |= IFF_UNICAST_FLT;
7140
7b872a55 7141 if (pci_using_dac) {
bc7f75fa 7142 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7143 netdev->vlan_features |= NETIF_F_HIGHDMA;
7144 }
bc7f75fa 7145
bc7f75fa
AK		 7146 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7147 adapter->flags |= FLAG_MNG_PT_ENABLED;
7148
e921eb1a 7149 /* before reading the NVM, reset the controller to
ad68076e
BA		 7150 * put the device in a known good starting state
7151 */
bc7f75fa
AK		 7152 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7153
e921eb1a 7154 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 7155 * attempt. Let's give it a few tries
7156 */
7157 for (i = 0;; i++) {
7158 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7159 break;
7160 if (i == 2) {
185095fb 7161 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 7162 err = -EIO;
7163 goto err_eeprom;
7164 }
7165 }
7166
10aa4c04
AK		 7167 e1000_eeprom_checks(adapter);
7168
608f8a0d 7169 /* copy the MAC address */
bc7f75fa 7170 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 7171 dev_err(&pdev->dev,
7172 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 7173
7174 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 7175
aaeb6cdf 7176 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 7177 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 7178 netdev->dev_addr);
bc7f75fa
AK		 7179 err = -EIO;
7180 goto err_eeprom;
7181 }
7182
7183 init_timer(&adapter->watchdog_timer);
c061b18d 7184 adapter->watchdog_timer.function = e1000_watchdog;
53aa82da 7185 adapter->watchdog_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 7186
7187 init_timer(&adapter->phy_info_timer);
c061b18d 7188 adapter->phy_info_timer.function = e1000_update_phy_info;
53aa82da 7189 adapter->phy_info_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 7190
7191 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7192 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 7193 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7194 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 7195 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 7196
bc7f75fa
AK		 7197 /* Initialize link parameters. User can change them with ethtool */
7198 adapter->hw.mac.autoneg = 1;
3db1cd5c 7199 adapter->fc_autoneg = true;
5c48ef3e
BA		 7200 adapter->hw.fc.requested_mode = e1000_fc_default;
7201 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 7202 adapter->hw.phy.autoneg_advertised = 0x2f;
7203
e921eb1a 7204 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 7205 * the EEPROM, enable the ACPI Magic Packet filter
7206 */
7207 if (adapter->flags & FLAG_APME_IN_WUC) {
7208 /* APME bit in EEPROM is mapped to WUC.APME */
7209 eeprom_data = er32(WUC);
7210 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 7211 if ((hw->mac.type > e1000_ich10lan) &&
7212 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 7213 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 7214 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7215 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7216 (adapter->hw.bus.func == 1))
491a04d2
DE		 7217 rval = e1000_read_nvm(&adapter->hw,
7218 NVM_INIT_CONTROL3_PORT_B,
7219 1, &eeprom_data);
bc7f75fa 7220 else
491a04d2
DE		 7221 rval = e1000_read_nvm(&adapter->hw,
7222 NVM_INIT_CONTROL3_PORT_A,
7223 1, &eeprom_data);
bc7f75fa
AK		 7224 }
7225
7226 /* fetch WoL from EEPROM */
491a04d2
DE		 7227 if (rval)
7228 e_dbg("NVM read error getting WoL initial values: %d\n", rval);
7229 else if (eeprom_data & eeprom_apme_mask)
bc7f75fa
AK		 7230 adapter->eeprom_wol |= E1000_WUFC_MAG;
7231
e921eb1a 7232 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 7233 * where the eeprom may be wrong or the board simply won't support
7234 * wake on lan on a particular port
7235 */
7236 if (!(adapter->flags & FLAG_HAS_WOL))
7237 adapter->eeprom_wol = 0;
7238
7239 /* initialize the wol settings based on the eeprom settings */
7240 adapter->wol = adapter->eeprom_wol;
66148bab
KK		 7241
7242 /* make sure adapter isn't asleep if manageability is enabled */
7243 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7244 (hw->mac.ops.check_mng_mode(hw)))
7245 device_wakeup_enable(&pdev->dev);
bc7f75fa 7246
84527590 7247 /* save off EEPROM version number */
491a04d2
DE		 7248 rval = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
7249
7250 if (rval) {
7251 e_dbg("NVM read error getting EEPROM version: %d\n", rval);
7252 adapter->eeprom_vers = 0;
7253 }
84527590 7254
bc7f75fa
AK		 7255 /* reset the hardware with the new settings */
7256 e1000e_reset(adapter);
7257
e921eb1a 7258 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 7259 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 7260 * under the control of the driver.
7261 */
c43bc57e 7262 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 7263 e1000e_get_hw_control(adapter);
bc7f75fa 7264
f2315bf1 7265 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 7266 err = register_netdev(netdev);
7267 if (err)
7268 goto err_register;
7269
9c563d20
JB		 7270 /* carrier off reporting is important to ethtool even BEFORE open */
7271 netif_carrier_off(netdev);
7272
d89777bf
BA		 7273 /* init PTP hardware clock */
7274 e1000e_ptp_init(adapter);
7275
bc7f75fa
AK		 7276 e1000_print_device_info(adapter);
7277
f3ec4f87
AS		 7278 if (pci_dev_run_wake(pdev))
7279 pm_runtime_put_noidle(&pdev->dev);
23606cf5 7280
bc7f75fa
AK		 7281 return 0;
7282
7283err_register:
c43bc57e 7284 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 7285 e1000e_release_hw_control(adapter);
bc7f75fa 7286err_eeprom:
470a5420 7287 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 7288 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 7289err_hw_init:
bc7f75fa
AK		 7290 kfree(adapter->tx_ring);
7291 kfree(adapter->rx_ring);
7292err_sw_init:
1103a631 7293 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
c43bc57e 7294 iounmap(adapter->hw.flash_address);
e82f54ba 7295 e1000e_reset_interrupt_capability(adapter);
c43bc57e 7296err_flashmap:
bc7f75fa
AK		 7297 iounmap(adapter->hw.hw_addr);
7298err_ioremap:
7299 free_netdev(netdev);
7300err_alloc_etherdev:
f0f422e5 7301 pci_release_selected_regions(pdev,
f0ff4398 7302 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 7303err_pci_reg:
7304err_dma:
7305 pci_disable_device(pdev);
7306 return err;
7307}
7308
7309/**
7310 * e1000_remove - Device Removal Routine
7311 * @pdev: PCI device information struct
7312 *
7313 * e1000_remove is called by the PCI subsystem to alert the driver
7314 * that it should release a PCI device. The could be caused by a
7315 * Hot-Plug event, or because the driver is going to be removed from
7316 * memory.
7317 **/
9f9a12f8 7318static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 7319{
7320 struct net_device *netdev = pci_get_drvdata(pdev);
7321 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 7322 bool down = test_bit(__E1000_DOWN, &adapter->state);
7323
d89777bf
BA		 7324 e1000e_ptp_remove(adapter);
7325
e921eb1a 7326 /* The timers may be rescheduled, so explicitly disable them
23f333a2 7327 * from being rescheduled.
ad68076e 7328 */
23606cf5
RW		 7329 if (!down)
7330 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 7331 del_timer_sync(&adapter->watchdog_timer);
7332 del_timer_sync(&adapter->phy_info_timer);
7333
41cec6f1
BA		 7334 cancel_work_sync(&adapter->reset_task);
7335 cancel_work_sync(&adapter->watchdog_task);
7336 cancel_work_sync(&adapter->downshift_task);
7337 cancel_work_sync(&adapter->update_phy_task);
7338 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 7339
b67e1913
BA		 7340 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7341 cancel_work_sync(&adapter->tx_hwtstamp_work);
7342 if (adapter->tx_hwtstamp_skb) {
7343 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
7344 adapter->tx_hwtstamp_skb = NULL;
7345 }
7346 }
7347
23606cf5
RW		 7348 /* Don't lie to e1000_close() down the road. */
7349 if (!down)
7350 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 7351 unregister_netdev(netdev);
7352
f3ec4f87
AS		 7353 if (pci_dev_run_wake(pdev))
7354 pm_runtime_get_noresume(&pdev->dev);
23606cf5 7355
e921eb1a 7356 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 7357 * would have already happened in close and is redundant.
7358 */
31dbe5b4 7359 e1000e_release_hw_control(adapter);
bc7f75fa 7360
4662e82b 7361 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 7362 kfree(adapter->tx_ring);
7363 kfree(adapter->rx_ring);
7364
7365 iounmap(adapter->hw.hw_addr);
1103a631
YL		 7366 if ((adapter->hw.flash_address) &&
7367 (adapter->hw.mac.type < e1000_pch_spt))
bc7f75fa 7368 iounmap(adapter->hw.flash_address);
f0f422e5 7369 pci_release_selected_regions(pdev,
f0ff4398 7370 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 7371
7372 free_netdev(netdev);
7373
111b9dc5 7374 /* AER disable */
19d5afd4 7375 pci_disable_pcie_error_reporting(pdev);
111b9dc5 7376
bc7f75fa
AK		 7377 pci_disable_device(pdev);
7378}
7379
7380/* PCI Error Recovery (ERS) */
3646f0e5 7381static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 7382 .error_detected = e1000_io_error_detected,
7383 .slot_reset = e1000_io_slot_reset,
7384 .resume = e1000_io_resume,
7385};
7386
0e8e842b 7387static const struct pci_device_id e1000_pci_tbl[] = {
bc7f75fa
AK		 7388 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7389 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7390 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
c29c3ba5
BA		 7391 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7392 board_82571 },
bc7f75fa
AK		 7393 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7394 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 7395 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7396 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7397 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 7398
bc7f75fa
AK		 7399 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7400 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7401 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7402 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 7403
bc7f75fa
AK		 7404 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7405 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7406 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 7407
4662e82b 7408 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 7409 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 7410 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 7411
bc7f75fa
AK		 7412 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7413 board_80003es2lan },
7414 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7415 board_80003es2lan },
7416 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7417 board_80003es2lan },
7418 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7419 board_80003es2lan },
ad68076e 7420
bc7f75fa
AK		 7421 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7422 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7423 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7424 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7425 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7426 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7427 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 7428 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 7429
bc7f75fa
AK		 7430 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7431 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7432 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7433 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7434 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 7435 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 7436 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7437 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7438 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7439
7440 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7441 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7442 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 7443
f4187b56
BA		 7444 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7445 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 7446 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 7447
a4f58f54
BA		 7448 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7449 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7450 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7451 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7452
d3738bb8
BA		 7453 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7454 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7455
2fbe4526
BA		 7456 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7457 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 7458 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7459 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
91a3d82f
BA		 7460 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7461 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7462 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7463 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
79849ebc
DE		 7464 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7465 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7466 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7467 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
2fbe4526 7468
f36bb6ca 7469 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 7470};
7471MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7472
23606cf5 7473static const struct dev_pm_ops e1000_pm_ops = {
72f72dcc 7474#ifdef CONFIG_PM_SLEEP
28002099
DE		 7475 .suspend = e1000e_pm_suspend,
7476 .resume = e1000e_pm_resume,
7477 .freeze = e1000e_pm_freeze,
7478 .thaw = e1000e_pm_thaw,
7479 .poweroff = e1000e_pm_suspend,
7480 .restore = e1000e_pm_resume,
72f72dcc 7481#endif
63eb48f1
DE		 7482 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7483 e1000e_pm_runtime_idle)
23606cf5
RW		 7484};
7485
bc7f75fa
AK		 7486/* PCI Device API Driver */
7487static struct pci_driver e1000_driver = {
7488 .name = e1000e_driver_name,
7489 .id_table = e1000_pci_tbl,
7490 .probe = e1000_probe,
9f9a12f8 7491 .remove = e1000_remove,
f36bb6ca
BA		 7492 .driver = {
7493 .pm = &e1000_pm_ops,
7494 },
bc7f75fa
AK		 7495 .shutdown = e1000_shutdown,
7496 .err_handler = &e1000_err_handler
7497};
7498
7499/**
7500 * e1000_init_module - Driver Registration Routine
7501 *
7502 * e1000_init_module is the first routine called when the driver is
7503 * loaded. All it does is register with the PCI subsystem.
7504 **/
7505static int __init e1000_init_module(void)
7506{
8544b9f7
BA		 7507 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7508 e1000e_driver_version);
529498cd 7509 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
53ec5498 7510
5a5e889c 7511 return pci_register_driver(&e1000_driver);
bc7f75fa
AK		 7512}
7513module_init(e1000_init_module);
7514
7515/**
7516 * e1000_exit_module - Driver Exit Cleanup Routine
7517 *
7518 * e1000_exit_module is called just before the driver is removed
7519 * from memory.
7520 **/
7521static void __exit e1000_exit_module(void)
7522{
7523 pci_unregister_driver(&e1000_driver);
7524}
7525module_exit(e1000_exit_module);
7526
bc7f75fa
AK		 7527MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7528MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7529MODULE_LICENSE("GPL");
7530MODULE_VERSION(DRV_VERSION);
7531
06c24b91 7532/* netdev.c */
Linux 6.x block layer and io_uring tree(s)