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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[linux-block.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
e78b80b1
DE		 1/* Intel PRO/1000 Linux driver
2 * Copyright(c) 1999 - 2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
bc7f75fa 21
8544b9f7
BA		 22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
bc7f75fa
AK		 24#include <linux/module.h>
25#include <linux/types.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/vmalloc.h>
29#include <linux/pagemap.h>
30#include <linux/delay.h>
31#include <linux/netdevice.h>
9fb7a5f7 32#include <linux/interrupt.h>
bc7f75fa
AK		 33#include <linux/tcp.h>
34#include <linux/ipv6.h>
5a0e3ad6 35#include <linux/slab.h>
bc7f75fa
AK		 36#include <net/checksum.h>
37#include <net/ip6_checksum.h>
bc7f75fa
AK		 38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/cpu.h>
41#include <linux/smp.h>
e8db0be1 42#include <linux/pm_qos.h>
23606cf5 43#include <linux/pm_runtime.h>
111b9dc5 44#include <linux/aer.h>
70c71606 45#include <linux/prefetch.h>
bc7f75fa
AK		 46
47#include "e1000.h"
48
b3ccf267 49#define DRV_EXTRAVERSION "-k"
c14c643b 50
8defe713 51#define DRV_VERSION "2.3.2" DRV_EXTRAVERSION
bc7f75fa
AK		 52char e1000e_driver_name[] = "e1000e";
53const char e1000e_driver_version[] = DRV_VERSION;
54
b3f4d599 55#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
56static int debug = -1;
57module_param(debug, int, 0);
58MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
bc7f75fa
AK		 60static const struct e1000_info *e1000_info_tbl[] = {
61 [board_82571] = &e1000_82571_info,
62 [board_82572] = &e1000_82572_info,
63 [board_82573] = &e1000_82573_info,
4662e82b 64 [board_82574] = &e1000_82574_info,
8c81c9c3 65 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 66 [board_80003es2lan] = &e1000_es2_info,
67 [board_ich8lan] = &e1000_ich8_info,
68 [board_ich9lan] = &e1000_ich9_info,
f4187b56 69 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 70 [board_pchlan] = &e1000_pch_info,
d3738bb8 71 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 72 [board_pch_lpt] = &e1000_pch_lpt_info,
bc7f75fa
AK		 73};
74
84f4ee90
TI		 75struct e1000_reg_info {
76 u32 ofs;
77 char *name;
78};
79
84f4ee90 80static const struct e1000_reg_info e1000_reg_info_tbl[] = {
84f4ee90
TI		 81 /* General Registers */
82 {E1000_CTRL, "CTRL"},
83 {E1000_STATUS, "STATUS"},
84 {E1000_CTRL_EXT, "CTRL_EXT"},
85
86 /* Interrupt Registers */
87 {E1000_ICR, "ICR"},
88
af667a29 89 /* Rx Registers */
84f4ee90 90 {E1000_RCTL, "RCTL"},
1e36052e
BA		 91 {E1000_RDLEN(0), "RDLEN"},
92 {E1000_RDH(0), "RDH"},
93 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 94 {E1000_RDTR, "RDTR"},
95 {E1000_RXDCTL(0), "RXDCTL"},
96 {E1000_ERT, "ERT"},
1e36052e
BA		 97 {E1000_RDBAL(0), "RDBAL"},
98 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 99 {E1000_RDFH, "RDFH"},
100 {E1000_RDFT, "RDFT"},
101 {E1000_RDFHS, "RDFHS"},
102 {E1000_RDFTS, "RDFTS"},
103 {E1000_RDFPC, "RDFPC"},
104
af667a29 105 /* Tx Registers */
84f4ee90 106 {E1000_TCTL, "TCTL"},
1e36052e
BA		 107 {E1000_TDBAL(0), "TDBAL"},
108 {E1000_TDBAH(0), "TDBAH"},
109 {E1000_TDLEN(0), "TDLEN"},
110 {E1000_TDH(0), "TDH"},
111 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 112 {E1000_TIDV, "TIDV"},
113 {E1000_TXDCTL(0), "TXDCTL"},
114 {E1000_TADV, "TADV"},
115 {E1000_TARC(0), "TARC"},
116 {E1000_TDFH, "TDFH"},
117 {E1000_TDFT, "TDFT"},
118 {E1000_TDFHS, "TDFHS"},
119 {E1000_TDFTS, "TDFTS"},
120 {E1000_TDFPC, "TDFPC"},
121
122 /* List Terminator */
f36bb6ca 123 {0, NULL}
84f4ee90
TI		 124};
125
e921eb1a 126/**
84f4ee90 127 * e1000_regdump - register printout routine
e921eb1a
BA		 128 * @hw: pointer to the HW structure
129 * @reginfo: pointer to the register info table
130 **/
84f4ee90
TI		 131static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
132{
133 int n = 0;
134 char rname[16];
135 u32 regs[8];
136
137 switch (reginfo->ofs) {
138 case E1000_RXDCTL(0):
139 for (n = 0; n < 2; n++)
140 regs[n] = __er32(hw, E1000_RXDCTL(n));
141 break;
142 case E1000_TXDCTL(0):
143 for (n = 0; n < 2; n++)
144 regs[n] = __er32(hw, E1000_TXDCTL(n));
145 break;
146 case E1000_TARC(0):
147 for (n = 0; n < 2; n++)
148 regs[n] = __er32(hw, E1000_TARC(n));
149 break;
150 default:
ef456f85
JK		 151 pr_info("%-15s %08x\n",
152 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 153 return;
154 }
155
156 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 157 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 158}
159
f0c5dadf
ET		 160static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
161 struct e1000_buffer *bi)
162{
163 int i;
164 struct e1000_ps_page *ps_page;
165
166 for (i = 0; i < adapter->rx_ps_pages; i++) {
167 ps_page = &bi->ps_pages[i];
168
169 if (ps_page->page) {
170 pr_info("packet dump for ps_page %d:\n", i);
171 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
172 16, 1, page_address(ps_page->page),
173 PAGE_SIZE, true);
174 }
175 }
176}
177
e921eb1a 178/**
af667a29 179 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 180 * @adapter: board private structure
181 **/
84f4ee90
TI		 182static void e1000e_dump(struct e1000_adapter *adapter)
183{
184 struct net_device *netdev = adapter->netdev;
185 struct e1000_hw *hw = &adapter->hw;
186 struct e1000_reg_info *reginfo;
187 struct e1000_ring *tx_ring = adapter->tx_ring;
188 struct e1000_tx_desc *tx_desc;
af667a29 189 struct my_u0 {
e885d762
BA		 190 __le64 a;
191 __le64 b;
af667a29 192 } *u0;
84f4ee90
TI		 193 struct e1000_buffer *buffer_info;
194 struct e1000_ring *rx_ring = adapter->rx_ring;
195 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 196 union e1000_rx_desc_extended *rx_desc;
af667a29 197 struct my_u1 {
e885d762
BA		 198 __le64 a;
199 __le64 b;
200 __le64 c;
201 __le64 d;
af667a29 202 } *u1;
84f4ee90
TI		 203 u32 staterr;
204 int i = 0;
205
206 if (!netif_msg_hw(adapter))
207 return;
208
209 /* Print netdevice Info */
210 if (netdev) {
211 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85 212 pr_info("Device Name state trans_start last_rx\n");
e5fe2541
BA		 213 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
214 netdev->state, netdev->trans_start, netdev->last_rx);
84f4ee90
TI		 215 }
216
217 /* Print Registers */
218 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 219 pr_info(" Register Name Value\n");
84f4ee90
TI		 220 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
221 reginfo->name; reginfo++) {
222 e1000_regdump(hw, reginfo);
223 }
224
af667a29 225 /* Print Tx Ring Summary */
84f4ee90 226 if (!netdev || !netif_running(netdev))
fe1e980f 227 return;
84f4ee90 228
af667a29 229 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 230 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 231 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 232 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
233 0, tx_ring->next_to_use, tx_ring->next_to_clean,
234 (unsigned long long)buffer_info->dma,
235 buffer_info->length,
236 buffer_info->next_to_watch,
237 (unsigned long long)buffer_info->time_stamp);
84f4ee90 238
af667a29 239 /* Print Tx Ring */
84f4ee90
TI		 240 if (!netif_msg_tx_done(adapter))
241 goto rx_ring_summary;
242
af667a29 243 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 244
245 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
246 *
247 * Legacy Transmit Descriptor
248 * +--------------------------------------------------------------+
249 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
250 * +--------------------------------------------------------------+
251 * 8 | Special | CSS | Status | CMD | CSO | Length |
252 * +--------------------------------------------------------------+
253 * 63 48 47 36 35 32 31 24 23 16 15 0
254 *
255 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
256 * 63 48 47 40 39 32 31 16 15 8 7 0
257 * +----------------------------------------------------------------+
258 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
259 * +----------------------------------------------------------------+
260 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
261 * +----------------------------------------------------------------+
262 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
263 *
264 * Extended Data Descriptor (DTYP=0x1)
265 * +----------------------------------------------------------------+
266 * 0 | Buffer Address [63:0] |
267 * +----------------------------------------------------------------+
268 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
269 * +----------------------------------------------------------------+
270 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
271 */
ef456f85
JK		 272 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
273 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
274 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 275 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 276 const char *next_desc;
84f4ee90
TI		 277 tx_desc = E1000_TX_DESC(*tx_ring, i);
278 buffer_info = &tx_ring->buffer_info[i];
279 u0 = (struct my_u0 *)tx_desc;
84f4ee90 280 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 281 next_desc = " NTC/U";
84f4ee90 282 else if (i == tx_ring->next_to_use)
ef456f85 283 next_desc = " NTU";
84f4ee90 284 else if (i == tx_ring->next_to_clean)
ef456f85 285 next_desc = " NTC";
84f4ee90 286 else
ef456f85
JK		 287 next_desc = "";
288 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
289 (!(le64_to_cpu(u0->b) & (1 << 29)) ? 'l' :
290 ((le64_to_cpu(u0->b) & (1 << 20)) ? 'd' : 'c')),
291 i,
292 (unsigned long long)le64_to_cpu(u0->a),
293 (unsigned long long)le64_to_cpu(u0->b),
294 (unsigned long long)buffer_info->dma,
295 buffer_info->length, buffer_info->next_to_watch,
296 (unsigned long long)buffer_info->time_stamp,
297 buffer_info->skb, next_desc);
84f4ee90 298
f0c5dadf 299 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 300 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 301 16, 1, buffer_info->skb->data,
302 buffer_info->skb->len, true);
84f4ee90
TI		 303 }
304
af667a29 305 /* Print Rx Ring Summary */
84f4ee90 306rx_ring_summary:
af667a29 307 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 308 pr_info("Queue [NTU] [NTC]\n");
309 pr_info(" %5d %5X %5X\n",
310 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 311
af667a29 312 /* Print Rx Ring */
84f4ee90 313 if (!netif_msg_rx_status(adapter))
fe1e980f 314 return;
84f4ee90 315
af667a29 316 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 317 switch (adapter->rx_ps_pages) {
318 case 1:
319 case 2:
320 case 3:
321 /* [Extended] Packet Split Receive Descriptor Format
322 *
323 * +-----------------------------------------------------+
324 * 0 | Buffer Address 0 [63:0] |
325 * +-----------------------------------------------------+
326 * 8 | Buffer Address 1 [63:0] |
327 * +-----------------------------------------------------+
328 * 16 | Buffer Address 2 [63:0] |
329 * +-----------------------------------------------------+
330 * 24 | Buffer Address 3 [63:0] |
331 * +-----------------------------------------------------+
332 */
ef456f85 333 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 334 /* [Extended] Receive Descriptor (Write-Back) Format
335 *
336 * 63 48 47 32 31 13 12 8 7 4 3 0
337 * +------------------------------------------------------+
338 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
339 * | Checksum | Ident | | Queue | | Type |
340 * +------------------------------------------------------+
341 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
342 * +------------------------------------------------------+
343 * 63 48 47 32 31 20 19 0
344 */
ef456f85 345 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 346 for (i = 0; i < rx_ring->count; i++) {
ef456f85 347 const char *next_desc;
84f4ee90
TI		 348 buffer_info = &rx_ring->buffer_info[i];
349 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
350 u1 = (struct my_u1 *)rx_desc_ps;
351 staterr =
af667a29 352 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 353
354 if (i == rx_ring->next_to_use)
355 next_desc = " NTU";
356 else if (i == rx_ring->next_to_clean)
357 next_desc = " NTC";
358 else
359 next_desc = "";
360
84f4ee90
TI		 361 if (staterr & E1000_RXD_STAT_DD) {
362 /* Descriptor Done */
ef456f85
JK		 363 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
364 "RWB", i,
365 (unsigned long long)le64_to_cpu(u1->a),
366 (unsigned long long)le64_to_cpu(u1->b),
367 (unsigned long long)le64_to_cpu(u1->c),
368 (unsigned long long)le64_to_cpu(u1->d),
369 buffer_info->skb, next_desc);
84f4ee90 370 } else {
ef456f85
JK		 371 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
372 "R ", i,
373 (unsigned long long)le64_to_cpu(u1->a),
374 (unsigned long long)le64_to_cpu(u1->b),
375 (unsigned long long)le64_to_cpu(u1->c),
376 (unsigned long long)le64_to_cpu(u1->d),
377 (unsigned long long)buffer_info->dma,
378 buffer_info->skb, next_desc);
84f4ee90
TI		 379
380 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 381 e1000e_dump_ps_pages(adapter,
382 buffer_info);
84f4ee90 383 }
84f4ee90
TI		 384 }
385 break;
386 default:
387 case 0:
5f450212 388 /* Extended Receive Descriptor (Read) Format
84f4ee90 389 *
5f450212
BA		 390 * +-----------------------------------------------------+
391 * 0 | Buffer Address [63:0] |
392 * +-----------------------------------------------------+
393 * 8 | Reserved |
394 * +-----------------------------------------------------+
84f4ee90 395 */
ef456f85 396 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 397 /* Extended Receive Descriptor (Write-Back) Format
398 *
399 * 63 48 47 32 31 24 23 4 3 0
400 * +------------------------------------------------------+
401 * | RSS Hash | | | |
402 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
403 * | Packet | IP | | | Type |
404 * | Checksum | Ident | | | |
405 * +------------------------------------------------------+
406 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
407 * +------------------------------------------------------+
408 * 63 48 47 32 31 20 19 0
409 */
ef456f85 410 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 411
412 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 413 const char *next_desc;
414
84f4ee90 415 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 416 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
417 u1 = (struct my_u1 *)rx_desc;
418 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 419
420 if (i == rx_ring->next_to_use)
421 next_desc = " NTU";
422 else if (i == rx_ring->next_to_clean)
423 next_desc = " NTC";
424 else
425 next_desc = "";
426
5f450212
BA		 427 if (staterr & E1000_RXD_STAT_DD) {
428 /* Descriptor Done */
ef456f85
JK		 429 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
430 "RWB", i,
431 (unsigned long long)le64_to_cpu(u1->a),
432 (unsigned long long)le64_to_cpu(u1->b),
433 buffer_info->skb, next_desc);
5f450212 434 } else {
ef456f85
JK		 435 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
436 "R ", i,
437 (unsigned long long)le64_to_cpu(u1->a),
438 (unsigned long long)le64_to_cpu(u1->b),
439 (unsigned long long)buffer_info->dma,
440 buffer_info->skb, next_desc);
5f450212 441
f0c5dadf
ET		 442 if (netif_msg_pktdata(adapter) &&
443 buffer_info->skb)
5f450212
BA		 444 print_hex_dump(KERN_INFO, "",
445 DUMP_PREFIX_ADDRESS, 16,
446 1,
f0c5dadf 447 buffer_info->skb->data,
5f450212
BA		 448 adapter->rx_buffer_len,
449 true);
450 }
84f4ee90
TI		 451 }
452 }
84f4ee90
TI		 453}
454
bc7f75fa
AK		 455/**
456 * e1000_desc_unused - calculate if we have unused descriptors
457 **/
458static int e1000_desc_unused(struct e1000_ring *ring)
459{
460 if (ring->next_to_clean > ring->next_to_use)
461 return ring->next_to_clean - ring->next_to_use - 1;
462
463 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
464}
465
b67e1913
BA		 466/**
467 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
468 * @adapter: board private structure
469 * @hwtstamps: time stamp structure to update
470 * @systim: unsigned 64bit system time value.
471 *
472 * Convert the system time value stored in the RX/TXSTMP registers into a
473 * hwtstamp which can be used by the upper level time stamping functions.
474 *
475 * The 'systim_lock' spinlock is used to protect the consistency of the
476 * system time value. This is needed because reading the 64 bit time
477 * value involves reading two 32 bit registers. The first read latches the
478 * value.
479 **/
480static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
481 struct skb_shared_hwtstamps *hwtstamps,
482 u64 systim)
483{
484 u64 ns;
485 unsigned long flags;
486
487 spin_lock_irqsave(&adapter->systim_lock, flags);
488 ns = timecounter_cyc2time(&adapter->tc, systim);
489 spin_unlock_irqrestore(&adapter->systim_lock, flags);
490
491 memset(hwtstamps, 0, sizeof(*hwtstamps));
492 hwtstamps->hwtstamp = ns_to_ktime(ns);
493}
494
495/**
496 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
497 * @adapter: board private structure
498 * @status: descriptor extended error and status field
499 * @skb: particular skb to include time stamp
500 *
501 * If the time stamp is valid, convert it into the timecounter ns value
502 * and store that result into the shhwtstamps structure which is passed
503 * up the network stack.
504 **/
505static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
506 struct sk_buff *skb)
507{
508 struct e1000_hw *hw = &adapter->hw;
509 u64 rxstmp;
510
511 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
512 !(status & E1000_RXDEXT_STATERR_TST) ||
513 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
514 return;
515
516 /* The Rx time stamp registers contain the time stamp. No other
517 * received packet will be time stamped until the Rx time stamp
518 * registers are read. Because only one packet can be time stamped
519 * at a time, the register values must belong to this packet and
520 * therefore none of the other additional attributes need to be
521 * compared.
522 */
523 rxstmp = (u64)er32(RXSTMPL);
524 rxstmp |= (u64)er32(RXSTMPH) << 32;
525 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
526
527 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
528}
529
bc7f75fa 530/**
ad68076e 531 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 532 * @adapter: board private structure
b67e1913 533 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 534 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
535 * @skb: pointer to sk_buff to be indicated to stack
536 **/
537static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 538 struct net_device *netdev, struct sk_buff *skb,
b67e1913 539 u32 staterr, __le16 vlan)
bc7f75fa 540{
86d70e53 541 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 542
543 e1000e_rx_hwtstamp(adapter, staterr, skb);
544
bc7f75fa
AK		 545 skb->protocol = eth_type_trans(skb, netdev);
546
b67e1913 547 if (staterr & E1000_RXD_STAT_VP)
86a9bad3 548 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
86d70e53
JK		 549
550 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 551}
552
553/**
af667a29 554 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 555 * @adapter: board private structure
556 * @status_err: receive descriptor status and error fields
557 * @csum: receive descriptor csum field
558 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 559 **/
560static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 561 struct sk_buff *skb)
bc7f75fa
AK		 562{
563 u16 status = (u16)status_err;
564 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 565
566 skb_checksum_none_assert(skb);
bc7f75fa 567
afd12939
BA		 568 /* Rx checksum disabled */
569 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
570 return;
571
bc7f75fa
AK		 572 /* Ignore Checksum bit is set */
573 if (status & E1000_RXD_STAT_IXSM)
574 return;
afd12939 575
2e1706f2
BA		 576 /* TCP/UDP checksum error bit or IP checksum error bit is set */
577 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 578 /* let the stack verify checksum errors */
579 adapter->hw_csum_err++;
580 return;
581 }
582
583 /* TCP/UDP Checksum has not been calculated */
584 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
585 return;
586
587 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 588 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 589 adapter->hw_csum_good++;
590}
591
55aa6985 592static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 593{
55aa6985 594 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 595 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 596 s32 ret_val = __ew32_prepare(hw);
597
598 writel(i, rx_ring->tail);
c6e7f51e 599
bdc125f7 600 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e
BA		 601 u32 rctl = er32(RCTL);
602 ew32(RCTL, rctl & ~E1000_RCTL_EN);
603 e_err("ME firmware caused invalid RDT - resetting\n");
604 schedule_work(&adapter->reset_task);
605 }
606}
607
55aa6985 608static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 609{
55aa6985 610 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 611 struct e1000_hw *hw = &adapter->hw;
bdc125f7 612 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 613
bdc125f7
BA		 614 writel(i, tx_ring->tail);
615
616 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e
BA		 617 u32 tctl = er32(TCTL);
618 ew32(TCTL, tctl & ~E1000_TCTL_EN);
619 e_err("ME firmware caused invalid TDT - resetting\n");
620 schedule_work(&adapter->reset_task);
621 }
622}
623
bc7f75fa 624/**
5f450212 625 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 626 * @rx_ring: Rx descriptor ring
bc7f75fa 627 **/
55aa6985 628static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 629 int cleaned_count, gfp_t gfp)
bc7f75fa 630{
55aa6985 631 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 632 struct net_device *netdev = adapter->netdev;
633 struct pci_dev *pdev = adapter->pdev;
5f450212 634 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 635 struct e1000_buffer *buffer_info;
636 struct sk_buff *skb;
637 unsigned int i;
89d71a66 638 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 639
640 i = rx_ring->next_to_use;
641 buffer_info = &rx_ring->buffer_info[i];
642
643 while (cleaned_count--) {
644 skb = buffer_info->skb;
645 if (skb) {
646 skb_trim(skb, 0);
647 goto map_skb;
648 }
649
c2fed996 650 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 651 if (!skb) {
652 /* Better luck next round */
653 adapter->alloc_rx_buff_failed++;
654 break;
655 }
656
bc7f75fa
AK		 657 buffer_info->skb = skb;
658map_skb:
0be3f55f 659 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 660 adapter->rx_buffer_len,
0be3f55f
NN		 661 DMA_FROM_DEVICE);
662 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 663 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 664 adapter->rx_dma_failed++;
665 break;
666 }
667
5f450212
BA		 668 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
669 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 670
50849d79 671 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 672 /* Force memory writes to complete before letting h/w
50849d79
TH		 673 * know there are new descriptors to fetch. (Only
674 * applicable for weak-ordered memory model archs,
675 * such as IA-64).
676 */
677 wmb();
c6e7f51e 678 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 679 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 680 else
c5083cf6 681 writel(i, rx_ring->tail);
50849d79 682 }
bc7f75fa
AK		 683 i++;
684 if (i == rx_ring->count)
685 i = 0;
686 buffer_info = &rx_ring->buffer_info[i];
687 }
688
50849d79 689 rx_ring->next_to_use = i;
bc7f75fa
AK		 690}
691
692/**
693 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 694 * @rx_ring: Rx descriptor ring
bc7f75fa 695 **/
55aa6985 696static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 697 int cleaned_count, gfp_t gfp)
bc7f75fa 698{
55aa6985 699 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 700 struct net_device *netdev = adapter->netdev;
701 struct pci_dev *pdev = adapter->pdev;
702 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 703 struct e1000_buffer *buffer_info;
704 struct e1000_ps_page *ps_page;
705 struct sk_buff *skb;
706 unsigned int i, j;
707
708 i = rx_ring->next_to_use;
709 buffer_info = &rx_ring->buffer_info[i];
710
711 while (cleaned_count--) {
712 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
713
714 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 715 ps_page = &buffer_info->ps_pages[j];
716 if (j >= adapter->rx_ps_pages) {
717 /* all unused desc entries get hw null ptr */
af667a29
BA		 718 rx_desc->read.buffer_addr[j + 1] =
719 ~cpu_to_le64(0);
47f44e40
AK		 720 continue;
721 }
722 if (!ps_page->page) {
c2fed996 723 ps_page->page = alloc_page(gfp);
bc7f75fa 724 if (!ps_page->page) {
47f44e40
AK		 725 adapter->alloc_rx_buff_failed++;
726 goto no_buffers;
727 }
0be3f55f
NN		 728 ps_page->dma = dma_map_page(&pdev->dev,
729 ps_page->page,
730 0, PAGE_SIZE,
731 DMA_FROM_DEVICE);
732 if (dma_mapping_error(&pdev->dev,
733 ps_page->dma)) {
47f44e40 734 dev_err(&adapter->pdev->dev,
af667a29 735 "Rx DMA page map failed\n");
47f44e40
AK		 736 adapter->rx_dma_failed++;
737 goto no_buffers;
bc7f75fa 738 }
bc7f75fa 739 }
e921eb1a 740 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 741 * didn't change because each write-back
742 * erases this info.
743 */
af667a29
BA		 744 rx_desc->read.buffer_addr[j + 1] =
745 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 746 }
747
e5fe2541 748 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
c2fed996 749 gfp);
bc7f75fa
AK		 750
751 if (!skb) {
752 adapter->alloc_rx_buff_failed++;
753 break;
754 }
755
bc7f75fa 756 buffer_info->skb = skb;
0be3f55f 757 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 758 adapter->rx_ps_bsize0,
0be3f55f
NN		 759 DMA_FROM_DEVICE);
760 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 761 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 762 adapter->rx_dma_failed++;
763 /* cleanup skb */
764 dev_kfree_skb_any(skb);
765 buffer_info->skb = NULL;
766 break;
767 }
768
769 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
770
50849d79 771 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 772 /* Force memory writes to complete before letting h/w
50849d79
TH		 773 * know there are new descriptors to fetch. (Only
774 * applicable for weak-ordered memory model archs,
775 * such as IA-64).
776 */
777 wmb();
c6e7f51e 778 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 779 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 780 else
c5083cf6 781 writel(i << 1, rx_ring->tail);
50849d79
TH		 782 }
783
bc7f75fa
AK		 784 i++;
785 if (i == rx_ring->count)
786 i = 0;
787 buffer_info = &rx_ring->buffer_info[i];
788 }
789
790no_buffers:
50849d79 791 rx_ring->next_to_use = i;
bc7f75fa
AK		 792}
793
97ac8cae
BA		 794/**
795 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 796 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 797 * @cleaned_count: number of buffers to allocate this pass
798 **/
799
55aa6985 800static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 801 int cleaned_count, gfp_t gfp)
97ac8cae 802{
55aa6985 803 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 804 struct net_device *netdev = adapter->netdev;
805 struct pci_dev *pdev = adapter->pdev;
5f450212 806 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 807 struct e1000_buffer *buffer_info;
808 struct sk_buff *skb;
809 unsigned int i;
2a2293b9 810 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 811
812 i = rx_ring->next_to_use;
813 buffer_info = &rx_ring->buffer_info[i];
814
815 while (cleaned_count--) {
816 skb = buffer_info->skb;
817 if (skb) {
818 skb_trim(skb, 0);
819 goto check_page;
820 }
821
c2fed996 822 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 823 if (unlikely(!skb)) {
824 /* Better luck next round */
825 adapter->alloc_rx_buff_failed++;
826 break;
827 }
828
97ac8cae
BA		 829 buffer_info->skb = skb;
830check_page:
831 /* allocate a new page if necessary */
832 if (!buffer_info->page) {
c2fed996 833 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 834 if (unlikely(!buffer_info->page)) {
835 adapter->alloc_rx_buff_failed++;
836 break;
837 }
838 }
839
37287fae 840 if (!buffer_info->dma) {
0be3f55f 841 buffer_info->dma = dma_map_page(&pdev->dev,
f0ff4398
BA		 842 buffer_info->page, 0,
843 PAGE_SIZE,
0be3f55f 844 DMA_FROM_DEVICE);
37287fae
CP		 845 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
846 adapter->alloc_rx_buff_failed++;
847 break;
848 }
849 }
97ac8cae 850
5f450212
BA		 851 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
852 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 853
854 if (unlikely(++i == rx_ring->count))
855 i = 0;
856 buffer_info = &rx_ring->buffer_info[i];
857 }
858
859 if (likely(rx_ring->next_to_use != i)) {
860 rx_ring->next_to_use = i;
861 if (unlikely(i-- == 0))
862 i = (rx_ring->count - 1);
863
864 /* Force memory writes to complete before letting h/w
865 * know there are new descriptors to fetch. (Only
866 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 867 * such as IA-64).
868 */
97ac8cae 869 wmb();
c6e7f51e 870 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 871 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 872 else
c5083cf6 873 writel(i, rx_ring->tail);
97ac8cae
BA		 874 }
875}
876
70495a50
BA		 877static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
878 struct sk_buff *skb)
879{
880 if (netdev->features & NETIF_F_RXHASH)
e25909bc 881 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
70495a50
BA		 882}
883
bc7f75fa 884/**
55aa6985
BA		 885 * e1000_clean_rx_irq - Send received data up the network stack
886 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 887 *
888 * the return value indicates whether actual cleaning was done, there
889 * is no guarantee that everything was cleaned
890 **/
55aa6985
BA		 891static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
892 int work_to_do)
bc7f75fa 893{
55aa6985 894 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 895 struct net_device *netdev = adapter->netdev;
896 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 897 struct e1000_hw *hw = &adapter->hw;
5f450212 898 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 899 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 900 u32 length, staterr;
bc7f75fa
AK		 901 unsigned int i;
902 int cleaned_count = 0;
3db1cd5c 903 bool cleaned = false;
bc7f75fa
AK		 904 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
905
906 i = rx_ring->next_to_clean;
5f450212
BA		 907 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
908 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 909 buffer_info = &rx_ring->buffer_info[i];
910
5f450212 911 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 912 struct sk_buff *skb;
bc7f75fa
AK		 913
914 if (*work_done >= work_to_do)
915 break;
916 (*work_done)++;
2d0bb1c1 917 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 918
bc7f75fa
AK		 919 skb = buffer_info->skb;
920 buffer_info->skb = NULL;
921
922 prefetch(skb->data - NET_IP_ALIGN);
923
924 i++;
925 if (i == rx_ring->count)
926 i = 0;
5f450212 927 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 928 prefetch(next_rxd);
929
930 next_buffer = &rx_ring->buffer_info[i];
931
3db1cd5c 932 cleaned = true;
bc7f75fa 933 cleaned_count++;
e5fe2541
BA		 934 dma_unmap_single(&pdev->dev, buffer_info->dma,
935 adapter->rx_buffer_len, DMA_FROM_DEVICE);
bc7f75fa
AK		 936 buffer_info->dma = 0;
937
5f450212 938 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 939
e921eb1a 940 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 941 * packet, if that's the case we need to toss it. In fact, we
942 * need to toss every packet with the EOP bit clear and the
943 * next frame that _does_ have the EOP bit set, as it is by
944 * definition only a frame fragment
945 */
5f450212 946 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 947 adapter->flags2 |= FLAG2_IS_DISCARDING;
948
949 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 950 /* All receives must fit into a single buffer */
3bb99fe2 951 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 952 /* recycle */
953 buffer_info->skb = skb;
5f450212 954 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 955 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 956 goto next_desc;
957 }
958
cf955e6c
BG		 959 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
960 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 961 /* recycle */
962 buffer_info->skb = skb;
963 goto next_desc;
964 }
965
eb7c3adb 966 /* adjust length to remove Ethernet CRC */
0184039a
BG		 967 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
968 /* If configured to store CRC, don't subtract FCS,
969 * but keep the FCS bytes out of the total_rx_bytes
970 * counter
971 */
972 if (netdev->features & NETIF_F_RXFCS)
973 total_rx_bytes -= 4;
974 else
975 length -= 4;
976 }
eb7c3adb 977
bc7f75fa
AK		 978 total_rx_bytes += length;
979 total_rx_packets++;
980
e921eb1a 981 /* code added for copybreak, this should improve
bc7f75fa 982 * performance for small packets with large amounts
ad68076e
BA		 983 * of reassembly being done in the stack
984 */
bc7f75fa
AK		 985 if (length < copybreak) {
986 struct sk_buff *new_skb =
89d71a66 987 netdev_alloc_skb_ip_align(netdev, length);
bc7f75fa 988 if (new_skb) {
808ff676
BA		 989 skb_copy_to_linear_data_offset(new_skb,
990 -NET_IP_ALIGN,
991 (skb->data -
992 NET_IP_ALIGN),
993 (length +
994 NET_IP_ALIGN));
bc7f75fa
AK		 995 /* save the skb in buffer_info as good */
996 buffer_info->skb = skb;
997 skb = new_skb;
998 }
999 /* else just continue with the old one */
1000 }
1001 /* end copybreak code */
1002 skb_put(skb, length);
1003
1004 /* Receive Checksum Offload */
2e1706f2 1005 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1006
70495a50
BA		 1007 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1008
5f450212
BA		 1009 e1000_receive_skb(adapter, netdev, skb, staterr,
1010 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1011
1012next_desc:
5f450212 1013 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1014
1015 /* return some buffers to hardware, one at a time is too slow */
1016 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1017 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1018 GFP_ATOMIC);
bc7f75fa
AK		 1019 cleaned_count = 0;
1020 }
1021
1022 /* use prefetched values */
1023 rx_desc = next_rxd;
1024 buffer_info = next_buffer;
5f450212
BA		 1025
1026 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1027 }
1028 rx_ring->next_to_clean = i;
1029
1030 cleaned_count = e1000_desc_unused(rx_ring);
1031 if (cleaned_count)
55aa6985 1032 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1033
bc7f75fa 1034 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1035 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1036 return cleaned;
1037}
1038
55aa6985
BA		 1039static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1040 struct e1000_buffer *buffer_info)
bc7f75fa 1041{
55aa6985
BA		 1042 struct e1000_adapter *adapter = tx_ring->adapter;
1043
03b1320d
AD		 1044 if (buffer_info->dma) {
1045 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1046 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1047 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1048 else
0be3f55f
NN		 1049 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1050 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1051 buffer_info->dma = 0;
1052 }
bc7f75fa
AK		 1053 if (buffer_info->skb) {
1054 dev_kfree_skb_any(buffer_info->skb);
1055 buffer_info->skb = NULL;
1056 }
1b7719c4 1057 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1058}
1059
41cec6f1 1060static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1061{
41cec6f1 1062 struct e1000_adapter *adapter = container_of(work,
f0ff4398
BA		 1063 struct e1000_adapter,
1064 print_hang_task);
09357b00 1065 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1066 struct e1000_ring *tx_ring = adapter->tx_ring;
1067 unsigned int i = tx_ring->next_to_clean;
1068 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1069 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1070 struct e1000_hw *hw = &adapter->hw;
1071 u16 phy_status, phy_1000t_status, phy_ext_status;
1072 u16 pci_status;
1073
615b32af
JB		 1074 if (test_bit(__E1000_DOWN, &adapter->state))
1075 return;
1076
e5fe2541 1077 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1078 /* May be block on write-back, flush and detect again
09357b00
JK		 1079 * flush pending descriptor writebacks to memory
1080 */
1081 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1082 /* execute the writes immediately */
1083 e1e_flush();
e921eb1a 1084 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1085 * the write is successful
1086 */
1087 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1088 /* execute the writes immediately */
1089 e1e_flush();
09357b00
JK		 1090 adapter->tx_hang_recheck = true;
1091 return;
1092 }
09357b00 1093 adapter->tx_hang_recheck = false;
d9554e96
DE		 1094
1095 if (er32(TDH(0)) == er32(TDT(0))) {
1096 e_dbg("false hang detected, ignoring\n");
1097 return;
1098 }
1099
1100 /* Real hang detected */
09357b00
JK		 1101 netif_stop_queue(netdev);
1102
c2ade1a4
BA		 1103 e1e_rphy(hw, MII_BMSR, &phy_status);
1104 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1105 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
bc7f75fa 1106
41cec6f1
BA		 1107 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1108
1109 /* detected Hardware unit hang */
1110 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1111 " TDH <%x>\n"
1112 " TDT <%x>\n"
1113 " next_to_use <%x>\n"
1114 " next_to_clean <%x>\n"
1115 "buffer_info[next_to_clean]:\n"
1116 " time_stamp <%lx>\n"
1117 " next_to_watch <%x>\n"
1118 " jiffies <%lx>\n"
41cec6f1
BA		 1119 " next_to_watch.status <%x>\n"
1120 "MAC Status <%x>\n"
1121 "PHY Status <%x>\n"
1122 "PHY 1000BASE-T Status <%x>\n"
1123 "PHY Extended Status <%x>\n"
1124 "PCI Status <%x>\n",
e5fe2541
BA		 1125 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1126 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1127 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1128 phy_status, phy_1000t_status, phy_ext_status, pci_status);
7c0427ee 1129
d9554e96
DE		 1130 e1000e_dump(adapter);
1131
7c0427ee
BA		 1132 /* Suggest workaround for known h/w issue */
1133 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1134 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1135}
1136
b67e1913
BA		 1137/**
1138 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1139 * @work: pointer to work struct
1140 *
1141 * This work function polls the TSYNCTXCTL valid bit to determine when a
1142 * timestamp has been taken for the current stored skb. The timestamp must
1143 * be for this skb because only one such packet is allowed in the queue.
1144 */
1145static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1146{
1147 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1148 tx_hwtstamp_work);
1149 struct e1000_hw *hw = &adapter->hw;
1150
b67e1913
BA		 1151 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1152 struct skb_shared_hwtstamps shhwtstamps;
1153 u64 txstmp;
1154
1155 txstmp = er32(TXSTMPL);
1156 txstmp |= (u64)er32(TXSTMPH) << 32;
1157
1158 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1159
1160 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1161 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1162 adapter->tx_hwtstamp_skb = NULL;
59c871c5
JK		 1163 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1164 + adapter->tx_timeout_factor * HZ)) {
1165 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1166 adapter->tx_hwtstamp_skb = NULL;
1167 adapter->tx_hwtstamp_timeouts++;
1168 e_warn("clearing Tx timestamp hang");
b67e1913
BA		 1169 } else {
1170 /* reschedule to check later */
1171 schedule_work(&adapter->tx_hwtstamp_work);
1172 }
1173}
1174
bc7f75fa
AK		 1175/**
1176 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1177 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1178 *
1179 * the return value indicates whether actual cleaning was done, there
1180 * is no guarantee that everything was cleaned
1181 **/
55aa6985 1182static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1183{
55aa6985 1184 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1185 struct net_device *netdev = adapter->netdev;
1186 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1187 struct e1000_tx_desc *tx_desc, *eop_desc;
1188 struct e1000_buffer *buffer_info;
1189 unsigned int i, eop;
1190 unsigned int count = 0;
bc7f75fa 1191 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1192 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1193
1194 i = tx_ring->next_to_clean;
1195 eop = tx_ring->buffer_info[i].next_to_watch;
1196 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1197
12d04a3c
AD		 1198 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1199 (count < tx_ring->count)) {
a86043c2 1200 bool cleaned = false;
e80bd1d1 1201 rmb(); /* read buffer_info after eop_desc */
a86043c2 1202 for (; !cleaned; count++) {
bc7f75fa
AK		 1203 tx_desc = E1000_TX_DESC(*tx_ring, i);
1204 buffer_info = &tx_ring->buffer_info[i];
1205 cleaned = (i == eop);
1206
1207 if (cleaned) {
9ed318d5
TH		 1208 total_tx_packets += buffer_info->segs;
1209 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1210 if (buffer_info->skb) {
1211 bytes_compl += buffer_info->skb->len;
1212 pkts_compl++;
1213 }
bc7f75fa
AK		 1214 }
1215
55aa6985 1216 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1217 tx_desc->upper.data = 0;
1218
1219 i++;
1220 if (i == tx_ring->count)
1221 i = 0;
1222 }
1223
dac87619
TL		 1224 if (i == tx_ring->next_to_use)
1225 break;
bc7f75fa
AK		 1226 eop = tx_ring->buffer_info[i].next_to_watch;
1227 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1228 }
1229
1230 tx_ring->next_to_clean = i;
1231
3f0cfa3b
TH		 1232 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1233
bc7f75fa 1234#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1235 if (count && netif_carrier_ok(netdev) &&
1236 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1237 /* Make sure that anybody stopping the queue after this
1238 * sees the new next_to_clean.
1239 */
1240 smp_mb();
1241
1242 if (netif_queue_stopped(netdev) &&
1243 !(test_bit(__E1000_DOWN, &adapter->state))) {
1244 netif_wake_queue(netdev);
1245 ++adapter->restart_queue;
1246 }
1247 }
1248
1249 if (adapter->detect_tx_hung) {
e921eb1a 1250 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1251 * check with the clearing of time_stamp and movement of i
1252 */
3db1cd5c 1253 adapter->detect_tx_hung = false;
12d04a3c
AD		 1254 if (tx_ring->buffer_info[i].time_stamp &&
1255 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1256 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1257 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1258 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1259 else
1260 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1261 }
1262 adapter->total_tx_bytes += total_tx_bytes;
1263 adapter->total_tx_packets += total_tx_packets;
807540ba 1264 return count < tx_ring->count;
bc7f75fa
AK		 1265}
1266
bc7f75fa
AK		 1267/**
1268 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1269 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1270 *
1271 * the return value indicates whether actual cleaning was done, there
1272 * is no guarantee that everything was cleaned
1273 **/
55aa6985
BA		 1274static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1275 int work_to_do)
bc7f75fa 1276{
55aa6985 1277 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1278 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1279 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1280 struct net_device *netdev = adapter->netdev;
1281 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1282 struct e1000_buffer *buffer_info, *next_buffer;
1283 struct e1000_ps_page *ps_page;
1284 struct sk_buff *skb;
1285 unsigned int i, j;
1286 u32 length, staterr;
1287 int cleaned_count = 0;
3db1cd5c 1288 bool cleaned = false;
bc7f75fa
AK		 1289 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1290
1291 i = rx_ring->next_to_clean;
1292 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1293 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1294 buffer_info = &rx_ring->buffer_info[i];
1295
1296 while (staterr & E1000_RXD_STAT_DD) {
1297 if (*work_done >= work_to_do)
1298 break;
1299 (*work_done)++;
1300 skb = buffer_info->skb;
2d0bb1c1 1301 rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1302
1303 /* in the packet split case this is header only */
1304 prefetch(skb->data - NET_IP_ALIGN);
1305
1306 i++;
1307 if (i == rx_ring->count)
1308 i = 0;
1309 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1310 prefetch(next_rxd);
1311
1312 next_buffer = &rx_ring->buffer_info[i];
1313
3db1cd5c 1314 cleaned = true;
bc7f75fa 1315 cleaned_count++;
0be3f55f 1316 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1317 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1318 buffer_info->dma = 0;
1319
af667a29 1320 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1321 if (!(staterr & E1000_RXD_STAT_EOP))
1322 adapter->flags2 |= FLAG2_IS_DISCARDING;
1323
1324 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1325 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1326 dev_kfree_skb_irq(skb);
b94b5028
JB		 1327 if (staterr & E1000_RXD_STAT_EOP)
1328 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1329 goto next_desc;
1330 }
1331
cf955e6c
BG		 1332 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1333 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1334 dev_kfree_skb_irq(skb);
1335 goto next_desc;
1336 }
1337
1338 length = le16_to_cpu(rx_desc->wb.middle.length0);
1339
1340 if (!length) {
ef456f85 1341 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1342 dev_kfree_skb_irq(skb);
1343 goto next_desc;
1344 }
1345
1346 /* Good Receive */
1347 skb_put(skb, length);
1348
1349 {
e921eb1a 1350 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1351 * it more efficient than reusing j
1352 */
1353 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1354
e921eb1a 1355 /* page alloc/put takes too long and effects small
0e15df49
BA		 1356 * packet throughput, so unsplit small packets and
1357 * save the alloc/put only valid in softirq (napi)
1358 * context to call kmap_*
ad68076e 1359 */
0e15df49
BA		 1360 if (l1 && (l1 <= copybreak) &&
1361 ((length + l1) <= adapter->rx_ps_bsize0)) {
1362 u8 *vaddr;
1363
1364 ps_page = &buffer_info->ps_pages[0];
1365
e921eb1a 1366 /* there is no documentation about how to call
0e15df49
BA		 1367 * kmap_atomic, so we can't hold the mapping
1368 * very long
1369 */
1370 dma_sync_single_for_cpu(&pdev->dev,
1371 ps_page->dma,
1372 PAGE_SIZE,
1373 DMA_FROM_DEVICE);
9f393834 1374 vaddr = kmap_atomic(ps_page->page);
0e15df49 1375 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1376 kunmap_atomic(vaddr);
0e15df49
BA		 1377 dma_sync_single_for_device(&pdev->dev,
1378 ps_page->dma,
1379 PAGE_SIZE,
1380 DMA_FROM_DEVICE);
1381
1382 /* remove the CRC */
0184039a
BG		 1383 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1384 if (!(netdev->features & NETIF_F_RXFCS))
1385 l1 -= 4;
1386 }
0e15df49
BA		 1387
1388 skb_put(skb, l1);
1389 goto copydone;
e80bd1d1 1390 } /* if */
bc7f75fa
AK		 1391 }
1392
1393 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1394 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1395 if (!length)
1396 break;
1397
47f44e40 1398 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1399 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1400 DMA_FROM_DEVICE);
bc7f75fa
AK		 1401 ps_page->dma = 0;
1402 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1403 ps_page->page = NULL;
1404 skb->len += length;
1405 skb->data_len += length;
98a045d7 1406 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1407 }
1408
eb7c3adb
JK		 1409 /* strip the ethernet crc, problem is we're using pages now so
1410 * this whole operation can get a little cpu intensive
1411 */
0184039a
BG		 1412 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1413 if (!(netdev->features & NETIF_F_RXFCS))
1414 pskb_trim(skb, skb->len - 4);
1415 }
eb7c3adb 1416
bc7f75fa
AK		 1417copydone:
1418 total_rx_bytes += skb->len;
1419 total_rx_packets++;
1420
2e1706f2 1421 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1422
70495a50
BA		 1423 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1424
bc7f75fa 1425 if (rx_desc->wb.upper.header_status &
17e813ec 1426 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
bc7f75fa
AK		 1427 adapter->rx_hdr_split++;
1428
b67e1913
BA		 1429 e1000_receive_skb(adapter, netdev, skb, staterr,
1430 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1431
1432next_desc:
1433 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1434 buffer_info->skb = NULL;
1435
1436 /* return some buffers to hardware, one at a time is too slow */
1437 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1438 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1439 GFP_ATOMIC);
bc7f75fa
AK		 1440 cleaned_count = 0;
1441 }
1442
1443 /* use prefetched values */
1444 rx_desc = next_rxd;
1445 buffer_info = next_buffer;
1446
1447 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1448 }
1449 rx_ring->next_to_clean = i;
1450
1451 cleaned_count = e1000_desc_unused(rx_ring);
1452 if (cleaned_count)
55aa6985 1453 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1454
bc7f75fa 1455 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1456 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1457 return cleaned;
1458}
1459
97ac8cae
BA		 1460/**
1461 * e1000_consume_page - helper function
1462 **/
1463static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
66501f56 1464 u16 length)
97ac8cae
BA		 1465{
1466 bi->page = NULL;
1467 skb->len += length;
1468 skb->data_len += length;
98a045d7 1469 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1470}
1471
1472/**
1473 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1474 * @adapter: board private structure
1475 *
1476 * the return value indicates whether actual cleaning was done, there
1477 * is no guarantee that everything was cleaned
1478 **/
55aa6985
BA		 1479static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1480 int work_to_do)
97ac8cae 1481{
55aa6985 1482 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1483 struct net_device *netdev = adapter->netdev;
1484 struct pci_dev *pdev = adapter->pdev;
5f450212 1485 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1486 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1487 u32 length, staterr;
97ac8cae
BA		 1488 unsigned int i;
1489 int cleaned_count = 0;
1490 bool cleaned = false;
362e20ca 1491 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
17e813ec 1492 struct skb_shared_info *shinfo;
97ac8cae
BA		 1493
1494 i = rx_ring->next_to_clean;
5f450212
BA		 1495 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1496 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1497 buffer_info = &rx_ring->buffer_info[i];
1498
5f450212 1499 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1500 struct sk_buff *skb;
97ac8cae
BA		 1501
1502 if (*work_done >= work_to_do)
1503 break;
1504 (*work_done)++;
2d0bb1c1 1505 rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1506
97ac8cae
BA		 1507 skb = buffer_info->skb;
1508 buffer_info->skb = NULL;
1509
1510 ++i;
1511 if (i == rx_ring->count)
1512 i = 0;
5f450212 1513 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1514 prefetch(next_rxd);
1515
1516 next_buffer = &rx_ring->buffer_info[i];
1517
1518 cleaned = true;
1519 cleaned_count++;
0be3f55f
NN		 1520 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1521 DMA_FROM_DEVICE);
97ac8cae
BA		 1522 buffer_info->dma = 0;
1523
5f450212 1524 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1525
1526 /* errors is only valid for DD + EOP descriptors */
5f450212 1527 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1528 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1529 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1530 /* recycle both page and skb */
1531 buffer_info->skb = skb;
1532 /* an error means any chain goes out the window too */
1533 if (rx_ring->rx_skb_top)
1534 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1535 rx_ring->rx_skb_top = NULL;
1536 goto next_desc;
97ac8cae 1537 }
f0f1a172 1538#define rxtop (rx_ring->rx_skb_top)
5f450212 1539 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1540 /* this descriptor is only the beginning (or middle) */
1541 if (!rxtop) {
1542 /* this is the beginning of a chain */
1543 rxtop = skb;
1544 skb_fill_page_desc(rxtop, 0, buffer_info->page,
f0ff4398 1545 0, length);
97ac8cae
BA		 1546 } else {
1547 /* this is the middle of a chain */
17e813ec
BA		 1548 shinfo = skb_shinfo(rxtop);
1549 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1550 buffer_info->page, 0,
1551 length);
97ac8cae
BA		 1552 /* re-use the skb, only consumed the page */
1553 buffer_info->skb = skb;
1554 }
1555 e1000_consume_page(buffer_info, rxtop, length);
1556 goto next_desc;
1557 } else {
1558 if (rxtop) {
1559 /* end of the chain */
17e813ec
BA		 1560 shinfo = skb_shinfo(rxtop);
1561 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1562 buffer_info->page, 0,
1563 length);
97ac8cae 1564 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1565 * page
1566 */
97ac8cae
BA		 1567 buffer_info->skb = skb;
1568 skb = rxtop;
1569 rxtop = NULL;
1570 e1000_consume_page(buffer_info, skb, length);
1571 } else {
1572 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1573 * copybreak to save the put_page/alloc_page
1574 */
97ac8cae
BA		 1575 if (length <= copybreak &&
1576 skb_tailroom(skb) >= length) {
1577 u8 *vaddr;
4679026d 1578 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1579 memcpy(skb_tail_pointer(skb), vaddr,
1580 length);
4679026d 1581 kunmap_atomic(vaddr);
97ac8cae 1582 /* re-use the page, so don't erase
e921eb1a
BA		 1583 * buffer_info->page
1584 */
97ac8cae
BA		 1585 skb_put(skb, length);
1586 } else {
1587 skb_fill_page_desc(skb, 0,
f0ff4398
BA		 1588 buffer_info->page, 0,
1589 length);
97ac8cae 1590 e1000_consume_page(buffer_info, skb,
f0ff4398 1591 length);
97ac8cae
BA		 1592 }
1593 }
1594 }
1595
2e1706f2
BA		 1596 /* Receive Checksum Offload */
1597 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1598
70495a50
BA		 1599 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1600
97ac8cae
BA		 1601 /* probably a little skewed due to removing CRC */
1602 total_rx_bytes += skb->len;
1603 total_rx_packets++;
1604
1605 /* eth type trans needs skb->data to point to something */
1606 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1607 e_err("pskb_may_pull failed.\n");
ef5ab89c 1608 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1609 goto next_desc;
1610 }
1611
5f450212
BA		 1612 e1000_receive_skb(adapter, netdev, skb, staterr,
1613 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1614
1615next_desc:
5f450212 1616 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1617
1618 /* return some buffers to hardware, one at a time is too slow */
1619 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1620 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1621 GFP_ATOMIC);
97ac8cae
BA		 1622 cleaned_count = 0;
1623 }
1624
1625 /* use prefetched values */
1626 rx_desc = next_rxd;
1627 buffer_info = next_buffer;
5f450212
BA		 1628
1629 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1630 }
1631 rx_ring->next_to_clean = i;
1632
1633 cleaned_count = e1000_desc_unused(rx_ring);
1634 if (cleaned_count)
55aa6985 1635 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1636
1637 adapter->total_rx_bytes += total_rx_bytes;
1638 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1639 return cleaned;
1640}
1641
bc7f75fa
AK		 1642/**
1643 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1644 * @rx_ring: Rx descriptor ring
bc7f75fa 1645 **/
55aa6985 1646static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1647{
55aa6985 1648 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1649 struct e1000_buffer *buffer_info;
1650 struct e1000_ps_page *ps_page;
1651 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1652 unsigned int i, j;
1653
1654 /* Free all the Rx ring sk_buffs */
1655 for (i = 0; i < rx_ring->count; i++) {
1656 buffer_info = &rx_ring->buffer_info[i];
1657 if (buffer_info->dma) {
1658 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1659 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1660 adapter->rx_buffer_len,
0be3f55f 1661 DMA_FROM_DEVICE);
97ac8cae 1662 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1663 dma_unmap_page(&pdev->dev, buffer_info->dma,
f0ff4398 1664 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa 1665 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1666 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1667 adapter->rx_ps_bsize0,
0be3f55f 1668 DMA_FROM_DEVICE);
bc7f75fa
AK		 1669 buffer_info->dma = 0;
1670 }
1671
97ac8cae
BA		 1672 if (buffer_info->page) {
1673 put_page(buffer_info->page);
1674 buffer_info->page = NULL;
1675 }
1676
bc7f75fa
AK		 1677 if (buffer_info->skb) {
1678 dev_kfree_skb(buffer_info->skb);
1679 buffer_info->skb = NULL;
1680 }
1681
1682 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1683 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1684 if (!ps_page->page)
1685 break;
0be3f55f
NN		 1686 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1687 DMA_FROM_DEVICE);
bc7f75fa
AK		 1688 ps_page->dma = 0;
1689 put_page(ps_page->page);
1690 ps_page->page = NULL;
1691 }
1692 }
1693
1694 /* there also may be some cached data from a chained receive */
1695 if (rx_ring->rx_skb_top) {
1696 dev_kfree_skb(rx_ring->rx_skb_top);
1697 rx_ring->rx_skb_top = NULL;
1698 }
1699
bc7f75fa
AK		 1700 /* Zero out the descriptor ring */
1701 memset(rx_ring->desc, 0, rx_ring->size);
1702
1703 rx_ring->next_to_clean = 0;
1704 rx_ring->next_to_use = 0;
b94b5028 1705 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa 1706
c5083cf6 1707 writel(0, rx_ring->head);
b485dbae 1708 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
bdc125f7
BA		 1709 e1000e_update_rdt_wa(rx_ring, 0);
1710 else
1711 writel(0, rx_ring->tail);
bc7f75fa
AK		 1712}
1713
a8f88ff5
JB		 1714static void e1000e_downshift_workaround(struct work_struct *work)
1715{
1716 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 1717 struct e1000_adapter,
1718 downshift_task);
a8f88ff5 1719
615b32af
JB		 1720 if (test_bit(__E1000_DOWN, &adapter->state))
1721 return;
1722
a8f88ff5
JB		 1723 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1724}
1725
bc7f75fa
AK		 1726/**
1727 * e1000_intr_msi - Interrupt Handler
1728 * @irq: interrupt number
1729 * @data: pointer to a network interface device structure
1730 **/
8bb62869 1731static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
bc7f75fa
AK		 1732{
1733 struct net_device *netdev = data;
1734 struct e1000_adapter *adapter = netdev_priv(netdev);
1735 struct e1000_hw *hw = &adapter->hw;
1736 u32 icr = er32(ICR);
1737
e921eb1a 1738 /* read ICR disables interrupts using IAM */
573cca8c 1739 if (icr & E1000_ICR_LSC) {
f92518dd 1740 hw->mac.get_link_status = true;
e921eb1a 1741 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1742 * disconnect (LSC) before accessing any PHY registers
1743 */
bc7f75fa
AK		 1744 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1745 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1746 schedule_work(&adapter->downshift_task);
bc7f75fa 1747
e921eb1a 1748 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1749 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1750 * adapter in watchdog
1751 */
bc7f75fa
AK		 1752 if (netif_carrier_ok(netdev) &&
1753 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1754 /* disable receives */
1755 u32 rctl = er32(RCTL);
1756 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1757 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1758 }
1759 /* guard against interrupt when we're going down */
1760 if (!test_bit(__E1000_DOWN, &adapter->state))
1761 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1762 }
1763
94fb848b
BA		 1764 /* Reset on uncorrectable ECC error */
1765 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1766 u32 pbeccsts = er32(PBECCSTS);
1767
1768 adapter->corr_errors +=
1769 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1770 adapter->uncorr_errors +=
1771 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1772 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1773
1774 /* Do the reset outside of interrupt context */
1775 schedule_work(&adapter->reset_task);
1776
1777 /* return immediately since reset is imminent */
1778 return IRQ_HANDLED;
1779 }
1780
288379f0 1781 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1782 adapter->total_tx_bytes = 0;
1783 adapter->total_tx_packets = 0;
1784 adapter->total_rx_bytes = 0;
1785 adapter->total_rx_packets = 0;
288379f0 1786 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1787 }
1788
1789 return IRQ_HANDLED;
1790}
1791
1792/**
1793 * e1000_intr - Interrupt Handler
1794 * @irq: interrupt number
1795 * @data: pointer to a network interface device structure
1796 **/
8bb62869 1797static irqreturn_t e1000_intr(int __always_unused irq, void *data)
bc7f75fa
AK		 1798{
1799 struct net_device *netdev = data;
1800 struct e1000_adapter *adapter = netdev_priv(netdev);
1801 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1802 u32 rctl, icr = er32(ICR);
4662e82b 1803
a68ea775 1804 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
e80bd1d1 1805 return IRQ_NONE; /* Not our interrupt */
bc7f75fa 1806
e921eb1a 1807 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1808 * not set, then the adapter didn't send an interrupt
1809 */
bc7f75fa
AK		 1810 if (!(icr & E1000_ICR_INT_ASSERTED))
1811 return IRQ_NONE;
1812
e921eb1a 1813 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1814 * interrupts are masked. No need for the
1815 * IMC write
1816 */
bc7f75fa 1817
573cca8c 1818 if (icr & E1000_ICR_LSC) {
f92518dd 1819 hw->mac.get_link_status = true;
e921eb1a 1820 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1821 * disconnect (LSC) before accessing any PHY registers
1822 */
bc7f75fa
AK		 1823 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1824 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1825 schedule_work(&adapter->downshift_task);
bc7f75fa 1826
e921eb1a 1827 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1828 * For packet buffer work-around on link down event;
1829 * disable receives here in the ISR and
1830 * reset adapter in watchdog
1831 */
1832 if (netif_carrier_ok(netdev) &&
1833 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1834 /* disable receives */
1835 rctl = er32(RCTL);
1836 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1837 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1838 }
1839 /* guard against interrupt when we're going down */
1840 if (!test_bit(__E1000_DOWN, &adapter->state))
1841 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1842 }
1843
94fb848b
BA		 1844 /* Reset on uncorrectable ECC error */
1845 if ((icr & E1000_ICR_ECCER) && (hw->mac.type == e1000_pch_lpt)) {
1846 u32 pbeccsts = er32(PBECCSTS);
1847
1848 adapter->corr_errors +=
1849 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1850 adapter->uncorr_errors +=
1851 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1852 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1853
1854 /* Do the reset outside of interrupt context */
1855 schedule_work(&adapter->reset_task);
1856
1857 /* return immediately since reset is imminent */
1858 return IRQ_HANDLED;
1859 }
1860
288379f0 1861 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1862 adapter->total_tx_bytes = 0;
1863 adapter->total_tx_packets = 0;
1864 adapter->total_rx_bytes = 0;
1865 adapter->total_rx_packets = 0;
288379f0 1866 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1867 }
1868
1869 return IRQ_HANDLED;
1870}
1871
8bb62869 1872static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
4662e82b
BA		 1873{
1874 struct net_device *netdev = data;
1875 struct e1000_adapter *adapter = netdev_priv(netdev);
1876 struct e1000_hw *hw = &adapter->hw;
1877 u32 icr = er32(ICR);
1878
1879 if (!(icr & E1000_ICR_INT_ASSERTED)) {
a3c69fef
JB		 1880 if (!test_bit(__E1000_DOWN, &adapter->state))
1881 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1882 return IRQ_NONE;
1883 }
1884
1885 if (icr & adapter->eiac_mask)
1886 ew32(ICS, (icr & adapter->eiac_mask));
1887
1888 if (icr & E1000_ICR_OTHER) {
1889 if (!(icr & E1000_ICR_LSC))
1890 goto no_link_interrupt;
f92518dd 1891 hw->mac.get_link_status = true;
4662e82b
BA		 1892 /* guard against interrupt when we're going down */
1893 if (!test_bit(__E1000_DOWN, &adapter->state))
1894 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1895 }
1896
1897no_link_interrupt:
a3c69fef
JB		 1898 if (!test_bit(__E1000_DOWN, &adapter->state))
1899 ew32(IMS, E1000_IMS_LSC | E1000_IMS_OTHER);
4662e82b
BA		 1900
1901 return IRQ_HANDLED;
1902}
1903
8bb62869 1904static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
4662e82b
BA		 1905{
1906 struct net_device *netdev = data;
1907 struct e1000_adapter *adapter = netdev_priv(netdev);
1908 struct e1000_hw *hw = &adapter->hw;
1909 struct e1000_ring *tx_ring = adapter->tx_ring;
1910
4662e82b
BA		 1911 adapter->total_tx_bytes = 0;
1912 adapter->total_tx_packets = 0;
1913
55aa6985 1914 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1915 /* Ring was not completely cleaned, so fire another interrupt */
1916 ew32(ICS, tx_ring->ims_val);
1917
1918 return IRQ_HANDLED;
1919}
1920
8bb62869 1921static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
4662e82b
BA		 1922{
1923 struct net_device *netdev = data;
1924 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1925 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1926
1927 /* Write the ITR value calculated at the end of the
1928 * previous interrupt.
1929 */
55aa6985
BA		 1930 if (rx_ring->set_itr) {
1931 writel(1000000000 / (rx_ring->itr_val * 256),
1932 rx_ring->itr_register);
1933 rx_ring->set_itr = 0;
4662e82b
BA		 1934 }
1935
288379f0 1936 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1937 adapter->total_rx_bytes = 0;
1938 adapter->total_rx_packets = 0;
288379f0 1939 __napi_schedule(&adapter->napi);
4662e82b
BA		 1940 }
1941 return IRQ_HANDLED;
1942}
1943
1944/**
1945 * e1000_configure_msix - Configure MSI-X hardware
1946 *
1947 * e1000_configure_msix sets up the hardware to properly
1948 * generate MSI-X interrupts.
1949 **/
1950static void e1000_configure_msix(struct e1000_adapter *adapter)
1951{
1952 struct e1000_hw *hw = &adapter->hw;
1953 struct e1000_ring *rx_ring = adapter->rx_ring;
1954 struct e1000_ring *tx_ring = adapter->tx_ring;
1955 int vector = 0;
1956 u32 ctrl_ext, ivar = 0;
1957
1958 adapter->eiac_mask = 0;
1959
1960 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1961 if (hw->mac.type == e1000_82574) {
1962 u32 rfctl = er32(RFCTL);
1963 rfctl |= E1000_RFCTL_ACK_DIS;
1964 ew32(RFCTL, rfctl);
1965 }
1966
4662e82b
BA		 1967 /* Configure Rx vector */
1968 rx_ring->ims_val = E1000_IMS_RXQ0;
1969 adapter->eiac_mask |= rx_ring->ims_val;
1970 if (rx_ring->itr_val)
1971 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1972 rx_ring->itr_register);
4662e82b 1973 else
c5083cf6 1974 writel(1, rx_ring->itr_register);
4662e82b
BA		 1975 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1976
1977 /* Configure Tx vector */
1978 tx_ring->ims_val = E1000_IMS_TXQ0;
1979 vector++;
1980 if (tx_ring->itr_val)
1981 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 1982 tx_ring->itr_register);
4662e82b 1983 else
c5083cf6 1984 writel(1, tx_ring->itr_register);
4662e82b
BA		 1985 adapter->eiac_mask |= tx_ring->ims_val;
1986 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
1987
1988 /* set vector for Other Causes, e.g. link changes */
1989 vector++;
1990 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
1991 if (rx_ring->itr_val)
1992 writel(1000000000 / (rx_ring->itr_val * 256),
1993 hw->hw_addr + E1000_EITR_82574(vector));
1994 else
1995 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
1996
1997 /* Cause Tx interrupts on every write back */
1998 ivar |= (1 << 31);
1999
2000 ew32(IVAR, ivar);
2001
2002 /* enable MSI-X PBA support */
2003 ctrl_ext = er32(CTRL_EXT);
2004 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR;
2005
2006 /* Auto-Mask Other interrupts upon ICR read */
4662e82b
BA		 2007 ew32(IAM, ~E1000_EIAC_MASK_82574 | E1000_IMS_OTHER);
2008 ctrl_ext |= E1000_CTRL_EXT_EIAME;
2009 ew32(CTRL_EXT, ctrl_ext);
2010 e1e_flush();
2011}
2012
2013void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2014{
2015 if (adapter->msix_entries) {
2016 pci_disable_msix(adapter->pdev);
2017 kfree(adapter->msix_entries);
2018 adapter->msix_entries = NULL;
2019 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2020 pci_disable_msi(adapter->pdev);
2021 adapter->flags &= ~FLAG_MSI_ENABLED;
2022 }
4662e82b
BA		 2023}
2024
2025/**
2026 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2027 *
2028 * Attempt to configure interrupts using the best available
2029 * capabilities of the hardware and kernel.
2030 **/
2031void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2032{
2033 int err;
8e86acd7 2034 int i;
4662e82b
BA		 2035
2036 switch (adapter->int_mode) {
2037 case E1000E_INT_MODE_MSIX:
2038 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2039 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2040 adapter->msix_entries = kcalloc(adapter->num_vectors,
17e813ec
BA		 2041 sizeof(struct
2042 msix_entry),
2043 GFP_KERNEL);
4662e82b 2044 if (adapter->msix_entries) {
0cc7c959
AG		 2045 struct e1000_adapter *a = adapter;
2046
8e86acd7 2047 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2048 adapter->msix_entries[i].entry = i;
2049
0cc7c959
AG		 2050 err = pci_enable_msix_range(a->pdev,
2051 a->msix_entries,
2052 a->num_vectors,
2053 a->num_vectors);
2054 if (err > 0)
4662e82b
BA		 2055 return;
2056 }
2057 /* MSI-X failed, so fall through and try MSI */
ef456f85 2058 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2059 e1000e_reset_interrupt_capability(adapter);
2060 }
2061 adapter->int_mode = E1000E_INT_MODE_MSI;
2062 /* Fall through */
2063 case E1000E_INT_MODE_MSI:
2064 if (!pci_enable_msi(adapter->pdev)) {
2065 adapter->flags |= FLAG_MSI_ENABLED;
2066 } else {
2067 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2068 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2069 }
2070 /* Fall through */
2071 case E1000E_INT_MODE_LEGACY:
2072 /* Don't do anything; this is the system default */
2073 break;
2074 }
8e86acd7
JK		 2075
2076 /* store the number of vectors being used */
2077 adapter->num_vectors = 1;
4662e82b
BA		 2078}
2079
2080/**
2081 * e1000_request_msix - Initialize MSI-X interrupts
2082 *
2083 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2084 * kernel.
2085 **/
2086static int e1000_request_msix(struct e1000_adapter *adapter)
2087{
2088 struct net_device *netdev = adapter->netdev;
2089 int err = 0, vector = 0;
2090
2091 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2092 snprintf(adapter->rx_ring->name,
2093 sizeof(adapter->rx_ring->name) - 1,
2094 "%s-rx-0", netdev->name);
4662e82b
BA		 2095 else
2096 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2097 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2098 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2099 netdev);
2100 if (err)
5015e53a 2101 return err;
c5083cf6
BA		 2102 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2103 E1000_EITR_82574(vector);
4662e82b
BA		 2104 adapter->rx_ring->itr_val = adapter->itr;
2105 vector++;
2106
2107 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2108 snprintf(adapter->tx_ring->name,
2109 sizeof(adapter->tx_ring->name) - 1,
2110 "%s-tx-0", netdev->name);
4662e82b
BA		 2111 else
2112 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2113 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2114 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2115 netdev);
2116 if (err)
5015e53a 2117 return err;
c5083cf6
BA		 2118 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2119 E1000_EITR_82574(vector);
4662e82b
BA		 2120 adapter->tx_ring->itr_val = adapter->itr;
2121 vector++;
2122
2123 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2124 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2125 if (err)
5015e53a 2126 return err;
4662e82b
BA		 2127
2128 e1000_configure_msix(adapter);
5015e53a 2129
4662e82b 2130 return 0;
4662e82b
BA		 2131}
2132
f8d59f78
BA		 2133/**
2134 * e1000_request_irq - initialize interrupts
2135 *
2136 * Attempts to configure interrupts using the best available
2137 * capabilities of the hardware and kernel.
2138 **/
bc7f75fa
AK		 2139static int e1000_request_irq(struct e1000_adapter *adapter)
2140{
2141 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2142 int err;
2143
4662e82b
BA		 2144 if (adapter->msix_entries) {
2145 err = e1000_request_msix(adapter);
2146 if (!err)
2147 return err;
2148 /* fall back to MSI */
2149 e1000e_reset_interrupt_capability(adapter);
2150 adapter->int_mode = E1000E_INT_MODE_MSI;
2151 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2152 }
4662e82b 2153 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2154 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2155 netdev->name, netdev);
2156 if (!err)
2157 return err;
bc7f75fa 2158
4662e82b
BA		 2159 /* fall back to legacy interrupt */
2160 e1000e_reset_interrupt_capability(adapter);
2161 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2162 }
2163
a0607fd3 2164 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2165 netdev->name, netdev);
2166 if (err)
2167 e_err("Unable to allocate interrupt, Error: %d\n", err);
2168
bc7f75fa
AK		 2169 return err;
2170}
2171
2172static void e1000_free_irq(struct e1000_adapter *adapter)
2173{
2174 struct net_device *netdev = adapter->netdev;
2175
4662e82b
BA		 2176 if (adapter->msix_entries) {
2177 int vector = 0;
2178
2179 free_irq(adapter->msix_entries[vector].vector, netdev);
2180 vector++;
2181
2182 free_irq(adapter->msix_entries[vector].vector, netdev);
2183 vector++;
2184
2185 /* Other Causes interrupt vector */
2186 free_irq(adapter->msix_entries[vector].vector, netdev);
2187 return;
bc7f75fa 2188 }
4662e82b
BA		 2189
2190 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2191}
2192
2193/**
2194 * e1000_irq_disable - Mask off interrupt generation on the NIC
2195 **/
2196static void e1000_irq_disable(struct e1000_adapter *adapter)
2197{
2198 struct e1000_hw *hw = &adapter->hw;
2199
bc7f75fa 2200 ew32(IMC, ~0);
4662e82b
BA		 2201 if (adapter->msix_entries)
2202 ew32(EIAC_82574, 0);
bc7f75fa 2203 e1e_flush();
8e86acd7
JK		 2204
2205 if (adapter->msix_entries) {
2206 int i;
2207 for (i = 0; i < adapter->num_vectors; i++)
2208 synchronize_irq(adapter->msix_entries[i].vector);
2209 } else {
2210 synchronize_irq(adapter->pdev->irq);
2211 }
bc7f75fa
AK		 2212}
2213
2214/**
2215 * e1000_irq_enable - Enable default interrupt generation settings
2216 **/
2217static void e1000_irq_enable(struct e1000_adapter *adapter)
2218{
2219 struct e1000_hw *hw = &adapter->hw;
2220
4662e82b
BA		 2221 if (adapter->msix_entries) {
2222 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
2223 ew32(IMS, adapter->eiac_mask | E1000_IMS_OTHER | E1000_IMS_LSC);
94fb848b
BA		 2224 } else if (hw->mac.type == e1000_pch_lpt) {
2225 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2226 } else {
2227 ew32(IMS, IMS_ENABLE_MASK);
2228 }
74ef9c39 2229 e1e_flush();
bc7f75fa
AK		 2230}
2231
2232/**
31dbe5b4 2233 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2234 * @adapter: address of board private structure
2235 *
31dbe5b4 2236 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2237 * For ASF and Pass Through versions of f/w this means that
2238 * the driver is loaded. For AMT version (only with 82573)
2239 * of the f/w this means that the network i/f is open.
2240 **/
31dbe5b4 2241void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2242{
2243 struct e1000_hw *hw = &adapter->hw;
2244 u32 ctrl_ext;
2245 u32 swsm;
2246
2247 /* Let firmware know the driver has taken over */
2248 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2249 swsm = er32(SWSM);
2250 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2251 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2252 ctrl_ext = er32(CTRL_EXT);
ad68076e 2253 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2254 }
2255}
2256
2257/**
31dbe5b4 2258 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2259 * @adapter: address of board private structure
2260 *
31dbe5b4 2261 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2262 * For ASF and Pass Through versions of f/w this means that the
2263 * driver is no longer loaded. For AMT version (only with 82573) i
2264 * of the f/w this means that the network i/f is closed.
2265 *
2266 **/
31dbe5b4 2267void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2268{
2269 struct e1000_hw *hw = &adapter->hw;
2270 u32 ctrl_ext;
2271 u32 swsm;
2272
2273 /* Let firmware taken over control of h/w */
2274 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2275 swsm = er32(SWSM);
2276 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2277 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2278 ctrl_ext = er32(CTRL_EXT);
ad68076e 2279 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2280 }
2281}
2282
bc7f75fa 2283/**
49ce9c2c 2284 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2285 **/
2286static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2287 struct e1000_ring *ring)
2288{
2289 struct pci_dev *pdev = adapter->pdev;
2290
2291 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2292 GFP_KERNEL);
2293 if (!ring->desc)
2294 return -ENOMEM;
2295
2296 return 0;
2297}
2298
2299/**
2300 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2301 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2302 *
2303 * Return 0 on success, negative on failure
2304 **/
55aa6985 2305int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2306{
55aa6985 2307 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2308 int err = -ENOMEM, size;
2309
2310 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2311 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2312 if (!tx_ring->buffer_info)
2313 goto err;
bc7f75fa
AK		 2314
2315 /* round up to nearest 4K */
2316 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2317 tx_ring->size = ALIGN(tx_ring->size, 4096);
2318
2319 err = e1000_alloc_ring_dma(adapter, tx_ring);
2320 if (err)
2321 goto err;
2322
2323 tx_ring->next_to_use = 0;
2324 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2325
2326 return 0;
2327err:
2328 vfree(tx_ring->buffer_info);
44defeb3 2329 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2330 return err;
2331}
2332
2333/**
2334 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2335 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2336 *
2337 * Returns 0 on success, negative on failure
2338 **/
55aa6985 2339int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2340{
55aa6985 2341 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2342 struct e1000_buffer *buffer_info;
2343 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2344
2345 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2346 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2347 if (!rx_ring->buffer_info)
2348 goto err;
bc7f75fa 2349
47f44e40
AK		 2350 for (i = 0; i < rx_ring->count; i++) {
2351 buffer_info = &rx_ring->buffer_info[i];
2352 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2353 sizeof(struct e1000_ps_page),
2354 GFP_KERNEL);
2355 if (!buffer_info->ps_pages)
2356 goto err_pages;
2357 }
bc7f75fa
AK		 2358
2359 desc_len = sizeof(union e1000_rx_desc_packet_split);
2360
2361 /* Round up to nearest 4K */
2362 rx_ring->size = rx_ring->count * desc_len;
2363 rx_ring->size = ALIGN(rx_ring->size, 4096);
2364
2365 err = e1000_alloc_ring_dma(adapter, rx_ring);
2366 if (err)
47f44e40 2367 goto err_pages;
bc7f75fa
AK		 2368
2369 rx_ring->next_to_clean = 0;
2370 rx_ring->next_to_use = 0;
2371 rx_ring->rx_skb_top = NULL;
2372
2373 return 0;
47f44e40
AK		 2374
2375err_pages:
2376 for (i = 0; i < rx_ring->count; i++) {
2377 buffer_info = &rx_ring->buffer_info[i];
2378 kfree(buffer_info->ps_pages);
2379 }
bc7f75fa
AK		 2380err:
2381 vfree(rx_ring->buffer_info);
e9262447 2382 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2383 return err;
2384}
2385
2386/**
2387 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2388 * @tx_ring: Tx descriptor ring
bc7f75fa 2389 **/
55aa6985 2390static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2391{
55aa6985 2392 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2393 struct e1000_buffer *buffer_info;
2394 unsigned long size;
2395 unsigned int i;
2396
2397 for (i = 0; i < tx_ring->count; i++) {
2398 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2399 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2400 }
2401
3f0cfa3b 2402 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2403 size = sizeof(struct e1000_buffer) * tx_ring->count;
2404 memset(tx_ring->buffer_info, 0, size);
2405
2406 memset(tx_ring->desc, 0, tx_ring->size);
2407
2408 tx_ring->next_to_use = 0;
2409 tx_ring->next_to_clean = 0;
2410
c5083cf6 2411 writel(0, tx_ring->head);
b485dbae 2412 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
bdc125f7
BA		 2413 e1000e_update_tdt_wa(tx_ring, 0);
2414 else
2415 writel(0, tx_ring->tail);
bc7f75fa
AK		 2416}
2417
2418/**
2419 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2420 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2421 *
2422 * Free all transmit software resources
2423 **/
55aa6985 2424void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2425{
55aa6985 2426 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2427 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2428
55aa6985 2429 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2430
2431 vfree(tx_ring->buffer_info);
2432 tx_ring->buffer_info = NULL;
2433
2434 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2435 tx_ring->dma);
2436 tx_ring->desc = NULL;
2437}
2438
2439/**
2440 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2441 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2442 *
2443 * Free all receive software resources
2444 **/
55aa6985 2445void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2446{
55aa6985 2447 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2448 struct pci_dev *pdev = adapter->pdev;
47f44e40 2449 int i;
bc7f75fa 2450
55aa6985 2451 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2452
b1cdfead 2453 for (i = 0; i < rx_ring->count; i++)
47f44e40 2454 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2455
bc7f75fa
AK		 2456 vfree(rx_ring->buffer_info);
2457 rx_ring->buffer_info = NULL;
2458
bc7f75fa
AK		 2459 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2460 rx_ring->dma);
2461 rx_ring->desc = NULL;
2462}
2463
2464/**
2465 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2466 * @adapter: pointer to adapter
2467 * @itr_setting: current adapter->itr
2468 * @packets: the number of packets during this measurement interval
2469 * @bytes: the number of bytes during this measurement interval
2470 *
bc7f75fa
AK		 2471 * Stores a new ITR value based on packets and byte
2472 * counts during the last interrupt. The advantage of per interrupt
2473 * computation is faster updates and more accurate ITR for the current
2474 * traffic pattern. Constants in this function were computed
2475 * based on theoretical maximum wire speed and thresholds were set based
2476 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2477 * while increasing bulk throughput. This functionality is controlled
2478 * by the InterruptThrottleRate module parameter.
bc7f75fa 2479 **/
8bb62869 2480static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
bc7f75fa
AK		 2481{
2482 unsigned int retval = itr_setting;
2483
2484 if (packets == 0)
5015e53a 2485 return itr_setting;
bc7f75fa
AK		 2486
2487 switch (itr_setting) {
2488 case lowest_latency:
2489 /* handle TSO and jumbo frames */
362e20ca 2490 if (bytes / packets > 8000)
bc7f75fa 2491 retval = bulk_latency;
b1cdfead 2492 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2493 retval = low_latency;
bc7f75fa 2494 break;
e80bd1d1 2495 case low_latency: /* 50 usec aka 20000 ints/s */
bc7f75fa
AK		 2496 if (bytes > 10000) {
2497 /* this if handles the TSO accounting */
362e20ca 2498 if (bytes / packets > 8000)
bc7f75fa 2499 retval = bulk_latency;
362e20ca 2500 else if ((packets < 10) || ((bytes / packets) > 1200))
bc7f75fa 2501 retval = bulk_latency;
b1cdfead 2502 else if ((packets > 35))
bc7f75fa 2503 retval = lowest_latency;
362e20ca 2504 } else if (bytes / packets > 2000) {
bc7f75fa
AK		 2505 retval = bulk_latency;
2506 } else if (packets <= 2 && bytes < 512) {
2507 retval = lowest_latency;
2508 }
2509 break;
e80bd1d1 2510 case bulk_latency: /* 250 usec aka 4000 ints/s */
bc7f75fa 2511 if (bytes > 25000) {
b1cdfead 2512 if (packets > 35)
bc7f75fa 2513 retval = low_latency;
bc7f75fa
AK		 2514 } else if (bytes < 6000) {
2515 retval = low_latency;
2516 }
2517 break;
2518 }
2519
bc7f75fa
AK		 2520 return retval;
2521}
2522
2523static void e1000_set_itr(struct e1000_adapter *adapter)
2524{
bc7f75fa
AK		 2525 u16 current_itr;
2526 u32 new_itr = adapter->itr;
2527
2528 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2529 if (adapter->link_speed != SPEED_1000) {
2530 current_itr = 0;
2531 new_itr = 4000;
2532 goto set_itr_now;
2533 }
2534
828bac87
BA		 2535 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2536 new_itr = 0;
2537 goto set_itr_now;
2538 }
2539
8bb62869
BA		 2540 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2541 adapter->total_tx_packets,
2542 adapter->total_tx_bytes);
bc7f75fa
AK		 2543 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2544 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2545 adapter->tx_itr = low_latency;
2546
8bb62869
BA		 2547 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2548 adapter->total_rx_packets,
2549 adapter->total_rx_bytes);
bc7f75fa
AK		 2550 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2551 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2552 adapter->rx_itr = low_latency;
2553
2554 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2555
bc7f75fa 2556 /* counts and packets in update_itr are dependent on these numbers */
33550cec 2557 switch (current_itr) {
bc7f75fa
AK		 2558 case lowest_latency:
2559 new_itr = 70000;
2560 break;
2561 case low_latency:
e80bd1d1 2562 new_itr = 20000; /* aka hwitr = ~200 */
bc7f75fa
AK		 2563 break;
2564 case bulk_latency:
2565 new_itr = 4000;
2566 break;
2567 default:
2568 break;
2569 }
2570
2571set_itr_now:
2572 if (new_itr != adapter->itr) {
e921eb1a 2573 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2574 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2575 * increasing
2576 */
bc7f75fa 2577 new_itr = new_itr > adapter->itr ?
f0ff4398 2578 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
bc7f75fa 2579 adapter->itr = new_itr;
4662e82b
BA		 2580 adapter->rx_ring->itr_val = new_itr;
2581 if (adapter->msix_entries)
2582 adapter->rx_ring->set_itr = 1;
2583 else
e3d14b08 2584 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2585 }
2586}
2587
22a4cca2
MV		 2588/**
2589 * e1000e_write_itr - write the ITR value to the appropriate registers
2590 * @adapter: address of board private structure
2591 * @itr: new ITR value to program
2592 *
2593 * e1000e_write_itr determines if the adapter is in MSI-X mode
2594 * and, if so, writes the EITR registers with the ITR value.
2595 * Otherwise, it writes the ITR value into the ITR register.
2596 **/
2597void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2598{
2599 struct e1000_hw *hw = &adapter->hw;
2600 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2601
2602 if (adapter->msix_entries) {
2603 int vector;
2604
2605 for (vector = 0; vector < adapter->num_vectors; vector++)
2606 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2607 } else {
2608 ew32(ITR, new_itr);
2609 }
2610}
2611
4662e82b
BA		 2612/**
2613 * e1000_alloc_queues - Allocate memory for all rings
2614 * @adapter: board private structure to initialize
2615 **/
9f9a12f8 2616static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2617{
55aa6985
BA		 2618 int size = sizeof(struct e1000_ring);
2619
2620 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2621 if (!adapter->tx_ring)
2622 goto err;
55aa6985
BA		 2623 adapter->tx_ring->count = adapter->tx_ring_count;
2624 adapter->tx_ring->adapter = adapter;
4662e82b 2625
55aa6985 2626 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2627 if (!adapter->rx_ring)
2628 goto err;
55aa6985
BA		 2629 adapter->rx_ring->count = adapter->rx_ring_count;
2630 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2631
2632 return 0;
2633err:
2634 e_err("Unable to allocate memory for queues\n");
2635 kfree(adapter->rx_ring);
2636 kfree(adapter->tx_ring);
2637 return -ENOMEM;
2638}
2639
bc7f75fa 2640/**
c58c8a78 2641 * e1000e_poll - NAPI Rx polling callback
ad68076e 2642 * @napi: struct associated with this polling callback
c58c8a78 2643 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2644 **/
c58c8a78 2645static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2646{
c58c8a78
BA		 2647 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2648 napi);
4662e82b 2649 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2650 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2651 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2652
4cf1653a 2653 adapter = netdev_priv(poll_dev);
bc7f75fa 2654
c58c8a78
BA		 2655 if (!adapter->msix_entries ||
2656 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2657 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2658
c58c8a78 2659 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2660
12d04a3c 2661 if (!tx_cleaned)
c58c8a78 2662 work_done = weight;
bc7f75fa 2663
c58c8a78
BA		 2664 /* If weight not fully consumed, exit the polling mode */
2665 if (work_done < weight) {
bc7f75fa
AK		 2666 if (adapter->itr_setting & 3)
2667 e1000_set_itr(adapter);
288379f0 2668 napi_complete(napi);
a3c69fef
JB		 2669 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2670 if (adapter->msix_entries)
2671 ew32(IMS, adapter->rx_ring->ims_val);
2672 else
2673 e1000_irq_enable(adapter);
2674 }
bc7f75fa
AK		 2675 }
2676
2677 return work_done;
2678}
2679
80d5c368 2680static int e1000_vlan_rx_add_vid(struct net_device *netdev,
603cdca9 2681 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2682{
2683 struct e1000_adapter *adapter = netdev_priv(netdev);
2684 struct e1000_hw *hw = &adapter->hw;
2685 u32 vfta, index;
2686
2687 /* don't update vlan cookie if already programmed */
2688 if ((adapter->hw.mng_cookie.status &
2689 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2690 (vid == adapter->mng_vlan_id))
8e586137 2691 return 0;
caaddaf8 2692
bc7f75fa 2693 /* add VID to filter table */
caaddaf8
BA		 2694 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2695 index = (vid >> 5) & 0x7F;
2696 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2697 vfta |= (1 << (vid & 0x1F));
2698 hw->mac.ops.write_vfta(hw, index, vfta);
2699 }
86d70e53
JK		 2700
2701 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2702
2703 return 0;
bc7f75fa
AK		 2704}
2705
80d5c368 2706static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
603cdca9 2707 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2708{
2709 struct e1000_adapter *adapter = netdev_priv(netdev);
2710 struct e1000_hw *hw = &adapter->hw;
2711 u32 vfta, index;
2712
bc7f75fa
AK		 2713 if ((adapter->hw.mng_cookie.status &
2714 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2715 (vid == adapter->mng_vlan_id)) {
2716 /* release control to f/w */
31dbe5b4 2717 e1000e_release_hw_control(adapter);
8e586137 2718 return 0;
bc7f75fa
AK		 2719 }
2720
2721 /* remove VID from filter table */
caaddaf8
BA		 2722 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2723 index = (vid >> 5) & 0x7F;
2724 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
2725 vfta &= ~(1 << (vid & 0x1F));
2726 hw->mac.ops.write_vfta(hw, index, vfta);
2727 }
86d70e53
JK		 2728
2729 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2730
2731 return 0;
bc7f75fa
AK		 2732}
2733
86d70e53
JK		 2734/**
2735 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2736 * @adapter: board private structure to initialize
2737 **/
2738static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2739{
2740 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2741 struct e1000_hw *hw = &adapter->hw;
2742 u32 rctl;
bc7f75fa 2743
86d70e53
JK		 2744 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2745 /* disable VLAN receive filtering */
2746 rctl = er32(RCTL);
2747 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2748 ew32(RCTL, rctl);
2749
2750 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
80d5c368
PM		 2751 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2752 adapter->mng_vlan_id);
86d70e53 2753 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2754 }
bc7f75fa
AK		 2755 }
2756}
2757
86d70e53
JK		 2758/**
2759 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2760 * @adapter: board private structure to initialize
2761 **/
2762static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2763{
2764 struct e1000_hw *hw = &adapter->hw;
2765 u32 rctl;
2766
2767 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2768 /* enable VLAN receive filtering */
2769 rctl = er32(RCTL);
2770 rctl |= E1000_RCTL_VFE;
2771 rctl &= ~E1000_RCTL_CFIEN;
2772 ew32(RCTL, rctl);
2773 }
2774}
bc7f75fa 2775
86d70e53
JK		 2776/**
2777 * e1000e_vlan_strip_enable - helper to disable HW VLAN stripping
2778 * @adapter: board private structure to initialize
2779 **/
2780static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2781{
bc7f75fa 2782 struct e1000_hw *hw = &adapter->hw;
86d70e53 2783 u32 ctrl;
bc7f75fa 2784
86d70e53
JK		 2785 /* disable VLAN tag insert/strip */
2786 ctrl = er32(CTRL);
2787 ctrl &= ~E1000_CTRL_VME;
2788 ew32(CTRL, ctrl);
2789}
bc7f75fa 2790
86d70e53
JK		 2791/**
2792 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2793 * @adapter: board private structure to initialize
2794 **/
2795static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2796{
2797 struct e1000_hw *hw = &adapter->hw;
2798 u32 ctrl;
bc7f75fa 2799
86d70e53
JK		 2800 /* enable VLAN tag insert/strip */
2801 ctrl = er32(CTRL);
2802 ctrl |= E1000_CTRL_VME;
2803 ew32(CTRL, ctrl);
2804}
bc7f75fa 2805
86d70e53
JK		 2806static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2807{
2808 struct net_device *netdev = adapter->netdev;
2809 u16 vid = adapter->hw.mng_cookie.vlan_id;
2810 u16 old_vid = adapter->mng_vlan_id;
2811
e5fe2541 2812 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
80d5c368 2813 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
86d70e53 2814 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2815 }
2816
86d70e53 2817 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
80d5c368 2818 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
bc7f75fa
AK		 2819}
2820
2821static void e1000_restore_vlan(struct e1000_adapter *adapter)
2822{
2823 u16 vid;
2824
80d5c368 2825 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
bc7f75fa 2826
86d70e53 2827 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 2828 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
bc7f75fa
AK		 2829}
2830
cd791618 2831static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2832{
2833 struct e1000_hw *hw = &adapter->hw;
cd791618 2834 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2835
2836 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2837 return;
2838
2839 manc = er32(MANC);
2840
e921eb1a 2841 /* enable receiving management packets to the host. this will probably
bc7f75fa 2842 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2843 * the packets will be handled on SMBUS
2844 */
bc7f75fa
AK		 2845 manc |= E1000_MANC_EN_MNG2HOST;
2846 manc2h = er32(MANC2H);
cd791618
BA		 2847
2848 switch (hw->mac.type) {
2849 default:
2850 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2851 break;
2852 case e1000_82574:
2853 case e1000_82583:
e921eb1a 2854 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2855 * if so, enable it.
2856 */
2857 for (i = 0, j = 0; i < 8; i++) {
2858 mdef = er32(MDEF(i));
2859
2860 /* Ignore filters with anything other than IPMI ports */
3b21b508 2861 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2862 continue;
2863
2864 /* Enable this decision filter in MANC2H */
2865 if (mdef)
2866 manc2h |= (1 << i);
2867
2868 j |= mdef;
2869 }
2870
2871 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2872 break;
2873
2874 /* Create new decision filter in an empty filter */
2875 for (i = 0, j = 0; i < 8; i++)
2876 if (er32(MDEF(i)) == 0) {
2877 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2878 E1000_MDEF_PORT_664));
2879 manc2h |= (1 << 1);
2880 j++;
2881 break;
2882 }
2883
2884 if (!j)
2885 e_warn("Unable to create IPMI pass-through filter\n");
2886 break;
2887 }
2888
bc7f75fa
AK		 2889 ew32(MANC2H, manc2h);
2890 ew32(MANC, manc);
2891}
2892
2893/**
af667a29 2894 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2895 * @adapter: board private structure
2896 *
2897 * Configure the Tx unit of the MAC after a reset.
2898 **/
2899static void e1000_configure_tx(struct e1000_adapter *adapter)
2900{
2901 struct e1000_hw *hw = &adapter->hw;
2902 struct e1000_ring *tx_ring = adapter->tx_ring;
2903 u64 tdba;
e7e834aa 2904 u32 tdlen, tctl, tarc;
bc7f75fa
AK		 2905
2906 /* Setup the HW Tx Head and Tail descriptor pointers */
2907 tdba = tx_ring->dma;
2908 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2909 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2910 ew32(TDBAH(0), (tdba >> 32));
2911 ew32(TDLEN(0), tdlen);
2912 ew32(TDH(0), 0);
2913 ew32(TDT(0), 0);
2914 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2915 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2916
bc7f75fa
AK		 2917 /* Set the Tx Interrupt Delay register */
2918 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2919 /* Tx irq moderation */
bc7f75fa
AK		 2920 ew32(TADV, adapter->tx_abs_int_delay);
2921
3a3b7586
JB		 2922 if (adapter->flags2 & FLAG2_DMA_BURST) {
2923 u32 txdctl = er32(TXDCTL(0));
2924 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2925 E1000_TXDCTL_WTHRESH);
e921eb1a 2926 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2927 * hardware to use the bus more efficiently in bursts, depends
2928 * on the tx_int_delay to be enabled,
8edc0e62 2929 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2930 * hthresh = 1 ==> prefetch when one or more available
2931 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2932 * BEWARE: this seems to work but should be considered first if
af667a29 2933 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2934 */
2935 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2936 ew32(TXDCTL(0), txdctl);
3a3b7586 2937 }
56032be7
BA		 2938 /* erratum work around: set txdctl the same for both queues */
2939 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2940
e7e834aa
DE		 2941 /* Program the Transmit Control Register */
2942 tctl = er32(TCTL);
2943 tctl &= ~E1000_TCTL_CT;
2944 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2945 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2946
bc7f75fa 2947 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2948 tarc = er32(TARC(0));
e921eb1a 2949 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2950 * gigabit link later
2951 */
bc7f75fa
AK		 2952#define SPEED_MODE_BIT (1 << 21)
2953 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2954 ew32(TARC(0), tarc);
bc7f75fa
AK		 2955 }
2956
2957 /* errata: program both queues to unweighted RR */
2958 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2959 tarc = er32(TARC(0));
bc7f75fa 2960 tarc |= 1;
e9ec2c0f
JK		 2961 ew32(TARC(0), tarc);
2962 tarc = er32(TARC(1));
bc7f75fa 2963 tarc |= 1;
e9ec2c0f 2964 ew32(TARC(1), tarc);
bc7f75fa
AK		 2965 }
2966
bc7f75fa
AK		 2967 /* Setup Transmit Descriptor Settings for eop descriptor */
2968 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2969
2970 /* only set IDE if we are delaying interrupts using the timers */
2971 if (adapter->tx_int_delay)
2972 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2973
2974 /* enable Report Status bit */
2975 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2976
e7e834aa
DE		 2977 ew32(TCTL, tctl);
2978
57cde763 2979 hw->mac.ops.config_collision_dist(hw);
bc7f75fa
AK		 2980}
2981
2982/**
2983 * e1000_setup_rctl - configure the receive control registers
2984 * @adapter: Board private structure
2985 **/
2986#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
2987 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
2988static void e1000_setup_rctl(struct e1000_adapter *adapter)
2989{
2990 struct e1000_hw *hw = &adapter->hw;
2991 u32 rctl, rfctl;
bc7f75fa
AK		 2992 u32 pages = 0;
2993
2fbe4526 2994 /* Workaround Si errata on PCHx - configure jumbo frame flow */
da1e2046
BA		 2995 if ((hw->mac.type >= e1000_pch2lan) &&
2996 (adapter->netdev->mtu > ETH_DATA_LEN) &&
2997 e1000_lv_jumbo_workaround_ich8lan(hw, true))
2998 e_dbg("failed to enable jumbo frame workaround mode\n");
a1ce6473 2999
bc7f75fa
AK		 3000 /* Program MC offset vector base */
3001 rctl = er32(RCTL);
3002 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3003 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
f0ff4398
BA		 3004 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3005 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
bc7f75fa
AK		 3006
3007 /* Do not Store bad packets */
3008 rctl &= ~E1000_RCTL_SBP;
3009
3010 /* Enable Long Packet receive */
3011 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3012 rctl &= ~E1000_RCTL_LPE;
3013 else
3014 rctl |= E1000_RCTL_LPE;
3015
eb7c3adb
JK		 3016 /* Some systems expect that the CRC is included in SMBUS traffic. The
3017 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3018 * host memory when this is enabled
3019 */
3020 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3021 rctl |= E1000_RCTL_SECRC;
5918bd88 3022
a4f58f54
BA		 3023 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3024 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3025 u16 phy_data;
3026
3027 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3028 phy_data &= 0xfff8;
3029 phy_data |= (1 << 2);
3030 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3031
3032 e1e_rphy(hw, 22, &phy_data);
3033 phy_data &= 0x0fff;
3034 phy_data |= (1 << 14);
3035 e1e_wphy(hw, 0x10, 0x2823);
3036 e1e_wphy(hw, 0x11, 0x0003);
3037 e1e_wphy(hw, 22, phy_data);
3038 }
3039
bc7f75fa
AK		 3040 /* Setup buffer sizes */
3041 rctl &= ~E1000_RCTL_SZ_4096;
3042 rctl |= E1000_RCTL_BSEX;
3043 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3044 case 2048:
3045 default:
3046 rctl |= E1000_RCTL_SZ_2048;
3047 rctl &= ~E1000_RCTL_BSEX;
3048 break;
3049 case 4096:
3050 rctl |= E1000_RCTL_SZ_4096;
3051 break;
3052 case 8192:
3053 rctl |= E1000_RCTL_SZ_8192;
3054 break;
3055 case 16384:
3056 rctl |= E1000_RCTL_SZ_16384;
3057 break;
3058 }
3059
5f450212
BA		 3060 /* Enable Extended Status in all Receive Descriptors */
3061 rfctl = er32(RFCTL);
3062 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3063 ew32(RFCTL, rfctl);
5f450212 3064
e921eb1a 3065 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3066 * header is placed in skb->data and the packet data is
3067 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3068 * In the case of a non-split, skb->data is linearly filled,
3069 * followed by the page buffers. Therefore, skb->data is
3070 * sized to hold the largest protocol header.
3071 *
3072 * allocations using alloc_page take too long for regular MTU
3073 * so only enable packet split for jumbo frames
3074 *
3075 * Using pages when the page size is greater than 16k wastes
3076 * a lot of memory, since we allocate 3 pages at all times
3077 * per packet.
3078 */
bc7f75fa 3079 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3080 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3081 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3082 else
3083 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3084
3085 if (adapter->rx_ps_pages) {
90da0669
BA		 3086 u32 psrctl = 0;
3087
140a7480
AK		 3088 /* Enable Packet split descriptors */
3089 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa 3090
e5fe2541 3091 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
bc7f75fa
AK		 3092
3093 switch (adapter->rx_ps_pages) {
3094 case 3:
e5fe2541
BA		 3095 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3096 /* fall-through */
bc7f75fa 3097 case 2:
e5fe2541
BA		 3098 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3099 /* fall-through */
bc7f75fa 3100 case 1:
e5fe2541 3101 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
bc7f75fa
AK		 3102 break;
3103 }
3104
3105 ew32(PSRCTL, psrctl);
3106 }
3107
cf955e6c
BG		 3108 /* This is useful for sniffing bad packets. */
3109 if (adapter->netdev->features & NETIF_F_RXALL) {
3110 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3111 * in e1000e_set_rx_mode
3112 */
e80bd1d1
BA		 3113 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3114 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3115 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
cf955e6c 3116
e80bd1d1
BA		 3117 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3118 E1000_RCTL_DPF | /* Allow filtered pause */
3119 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
cf955e6c
BG		 3120 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3121 * and that breaks VLANs.
3122 */
3123 }
3124
bc7f75fa 3125 ew32(RCTL, rctl);
318a94d6 3126 /* just started the receive unit, no need to restart */
12d43f7d 3127 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3128}
3129
3130/**
3131 * e1000_configure_rx - Configure Receive Unit after Reset
3132 * @adapter: board private structure
3133 *
3134 * Configure the Rx unit of the MAC after a reset.
3135 **/
3136static void e1000_configure_rx(struct e1000_adapter *adapter)
3137{
3138 struct e1000_hw *hw = &adapter->hw;
3139 struct e1000_ring *rx_ring = adapter->rx_ring;
3140 u64 rdba;
3141 u32 rdlen, rctl, rxcsum, ctrl_ext;
3142
3143 if (adapter->rx_ps_pages) {
3144 /* this is a 32 byte descriptor */
3145 rdlen = rx_ring->count *
af667a29 3146 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3147 adapter->clean_rx = e1000_clean_rx_irq_ps;
3148 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3149 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3150 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3151 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3152 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3153 } else {
5f450212 3154 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3155 adapter->clean_rx = e1000_clean_rx_irq;
3156 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3157 }
3158
3159 /* disable receives while setting up the descriptors */
3160 rctl = er32(RCTL);
7f99ae63
BA		 3161 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3162 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3163 e1e_flush();
1bba4386 3164 usleep_range(10000, 20000);
bc7f75fa 3165
3a3b7586 3166 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3167 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3168 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3169 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3170 * granularity = 01
3171 * wthresh = 04,
3172 * hthresh = 04,
3173 * pthresh = 0x20
3174 */
3175 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3176 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3177
e921eb1a 3178 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3179 * the value was not set by the user via module options
3180 */
3181 if (adapter->rx_int_delay == DEFAULT_RDTR)
3182 adapter->rx_int_delay = BURST_RDTR;
3183 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3184 adapter->rx_abs_int_delay = BURST_RADV;
3185 }
3186
bc7f75fa
AK		 3187 /* set the Receive Delay Timer Register */
3188 ew32(RDTR, adapter->rx_int_delay);
3189
3190 /* irq moderation */
3191 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3192 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3193 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3194
3195 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3196 /* Auto-Mask interrupts upon ICR access */
3197 ctrl_ext |= E1000_CTRL_EXT_IAME;
3198 ew32(IAM, 0xffffffff);
3199 ew32(CTRL_EXT, ctrl_ext);
3200 e1e_flush();
3201
e921eb1a 3202 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3203 * the Base and Length of the Rx Descriptor Ring
3204 */
bc7f75fa 3205 rdba = rx_ring->dma;
1e36052e
BA		 3206 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3207 ew32(RDBAH(0), (rdba >> 32));
3208 ew32(RDLEN(0), rdlen);
3209 ew32(RDH(0), 0);
3210 ew32(RDT(0), 0);
3211 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3212 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa
AK		 3213
3214 /* Enable Receive Checksum Offload for TCP and UDP */
3215 rxcsum = er32(RXCSUM);
2e1706f2 3216 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3217 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3218 else
bc7f75fa 3219 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3220 ew32(RXCSUM, rxcsum);
3221
3e35d991
BA		 3222 /* With jumbo frames, excessive C-state transition latencies result
3223 * in dropped transactions.
3224 */
3225 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3226 u32 lat =
3227 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3228 adapter->max_frame_size) * 8 / 1000;
3229
3230 if (adapter->flags & FLAG_IS_ICH) {
53ec5498
BA		 3231 u32 rxdctl = er32(RXDCTL(0));
3232 ew32(RXDCTL(0), rxdctl | 0x3);
53ec5498 3233 }
3e35d991
BA		 3234
3235 pm_qos_update_request(&adapter->netdev->pm_qos_req, lat);
3236 } else {
3237 pm_qos_update_request(&adapter->netdev->pm_qos_req,
3238 PM_QOS_DEFAULT_VALUE);
97ac8cae 3239 }
bc7f75fa
AK		 3240
3241 /* Enable Receives */
3242 ew32(RCTL, rctl);
3243}
3244
3245/**
ef9b965a
JB		 3246 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3247 * @netdev: network interface device structure
bc7f75fa 3248 *
ef9b965a
JB		 3249 * Writes multicast address list to the MTA hash table.
3250 * Returns: -ENOMEM on failure
3251 * 0 on no addresses written
3252 * X on writing X addresses to MTA
3253 */
3254static int e1000e_write_mc_addr_list(struct net_device *netdev)
3255{
3256 struct e1000_adapter *adapter = netdev_priv(netdev);
3257 struct e1000_hw *hw = &adapter->hw;
3258 struct netdev_hw_addr *ha;
3259 u8 *mta_list;
3260 int i;
3261
3262 if (netdev_mc_empty(netdev)) {
3263 /* nothing to program, so clear mc list */
3264 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3265 return 0;
3266 }
3267
3268 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3269 if (!mta_list)
3270 return -ENOMEM;
3271
3272 /* update_mc_addr_list expects a packed array of only addresses. */
3273 i = 0;
3274 netdev_for_each_mc_addr(ha, netdev)
f0ff4398 3275 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
ef9b965a
JB		 3276
3277 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3278 kfree(mta_list);
3279
3280 return netdev_mc_count(netdev);
3281}
3282
3283/**
3284 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3285 * @netdev: network interface device structure
bc7f75fa 3286 *
ef9b965a
JB		 3287 * Writes unicast address list to the RAR table.
3288 * Returns: -ENOMEM on failure/insufficient address space
3289 * 0 on no addresses written
3290 * X on writing X addresses to the RAR table
bc7f75fa 3291 **/
ef9b965a 3292static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3293{
ef9b965a
JB		 3294 struct e1000_adapter *adapter = netdev_priv(netdev);
3295 struct e1000_hw *hw = &adapter->hw;
3296 unsigned int rar_entries = hw->mac.rar_entry_count;
3297 int count = 0;
3298
3299 /* save a rar entry for our hardware address */
3300 rar_entries--;
3301
3302 /* save a rar entry for the LAA workaround */
3303 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3304 rar_entries--;
3305
3306 /* return ENOMEM indicating insufficient memory for addresses */
3307 if (netdev_uc_count(netdev) > rar_entries)
3308 return -ENOMEM;
3309
3310 if (!netdev_uc_empty(netdev) && rar_entries) {
3311 struct netdev_hw_addr *ha;
3312
e921eb1a 3313 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3314 * combining
3315 */
3316 netdev_for_each_uc_addr(ha, netdev) {
3317 if (!rar_entries)
3318 break;
69e1e019 3319 hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
ef9b965a
JB		 3320 count++;
3321 }
3322 }
3323
3324 /* zero out the remaining RAR entries not used above */
3325 for (; rar_entries > 0; rar_entries--) {
3326 ew32(RAH(rar_entries), 0);
3327 ew32(RAL(rar_entries), 0);
3328 }
3329 e1e_flush();
3330
3331 return count;
bc7f75fa
AK		 3332}
3333
3334/**
ef9b965a 3335 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3336 * @netdev: network interface device structure
3337 *
ef9b965a
JB		 3338 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3339 * address list or the network interface flags are updated. This routine is
3340 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3341 * promiscuous mode, and all-multi behavior.
3342 **/
ef9b965a 3343static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3344{
3345 struct e1000_adapter *adapter = netdev_priv(netdev);
3346 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3347 u32 rctl;
bc7f75fa 3348
63eb48f1
DE		 3349 if (pm_runtime_suspended(netdev->dev.parent))
3350 return;
3351
bc7f75fa 3352 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3353 rctl = er32(RCTL);
3354
ef9b965a
JB		 3355 /* clear the affected bits */
3356 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3357
bc7f75fa
AK		 3358 if (netdev->flags & IFF_PROMISC) {
3359 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3360 /* Do not hardware filter VLANs in promisc mode */
3361 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3362 } else {
ef9b965a 3363 int count;
3d3a1676 3364
746b9f02
PM		 3365 if (netdev->flags & IFF_ALLMULTI) {
3366 rctl |= E1000_RCTL_MPE;
746b9f02 3367 } else {
e921eb1a 3368 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3369 * then we should just turn on promiscuous mode so
3370 * that we can at least receive multicast traffic
3371 */
3372 count = e1000e_write_mc_addr_list(netdev);
3373 if (count < 0)
3374 rctl |= E1000_RCTL_MPE;
746b9f02 3375 }
86d70e53 3376 e1000e_vlan_filter_enable(adapter);
e921eb1a 3377 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3378 * sufficient space to store all the addresses then enable
3379 * unicast promiscuous mode
bc7f75fa 3380 */
ef9b965a
JB		 3381 count = e1000e_write_uc_addr_list(netdev);
3382 if (count < 0)
3383 rctl |= E1000_RCTL_UPE;
bc7f75fa 3384 }
86d70e53 3385
ef9b965a
JB		 3386 ew32(RCTL, rctl);
3387
f646968f 3388 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
86d70e53
JK		 3389 e1000e_vlan_strip_enable(adapter);
3390 else
3391 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3392}
3393
70495a50
BA		 3394static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3395{
3396 struct e1000_hw *hw = &adapter->hw;
3397 u32 mrqc, rxcsum;
3398 int i;
3399 static const u32 rsskey[10] = {
3400 0xda565a6d, 0xc20e5b25, 0x3d256741, 0xb08fa343, 0xcb2bcad0,
3401 0xb4307bae, 0xa32dcb77, 0x0cf23080, 0x3bb7426a, 0xfa01acbe
3402 };
3403
3404 /* Fill out hash function seed */
3405 for (i = 0; i < 10; i++)
3406 ew32(RSSRK(i), rsskey[i]);
3407
3408 /* Direct all traffic to queue 0 */
3409 for (i = 0; i < 32; i++)
3410 ew32(RETA(i), 0);
3411
e921eb1a 3412 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3413 * descriptor on writeback.
3414 */
3415 rxcsum = er32(RXCSUM);
3416 rxcsum |= E1000_RXCSUM_PCSD;
3417
3418 ew32(RXCSUM, rxcsum);
3419
3420 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3421 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3422 E1000_MRQC_RSS_FIELD_IPV6 |
3423 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3424 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3425
3426 ew32(MRQC, mrqc);
3427}
3428
b67e1913
BA		 3429/**
3430 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3431 * @adapter: board private structure
3432 * @timinca: pointer to returned time increment attributes
3433 *
3434 * Get attributes for incrementing the System Time Register SYSTIML/H at
3435 * the default base frequency, and set the cyclecounter shift value.
3436 **/
d89777bf 3437s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3438{
3439 struct e1000_hw *hw = &adapter->hw;
3440 u32 incvalue, incperiod, shift;
3441
3442 /* Make sure clock is enabled on I217 before checking the frequency */
3443 if ((hw->mac.type == e1000_pch_lpt) &&
3444 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3445 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3446 u32 fextnvm7 = er32(FEXTNVM7);
3447
3448 if (!(fextnvm7 & (1 << 0))) {
3449 ew32(FEXTNVM7, fextnvm7 | (1 << 0));
3450 e1e_flush();
3451 }
3452 }
3453
3454 switch (hw->mac.type) {
3455 case e1000_pch2lan:
3456 case e1000_pch_lpt:
3457 /* On I217, the clock frequency is 25MHz or 96MHz as
3458 * indicated by the System Clock Frequency Indication
3459 */
3460 if ((hw->mac.type != e1000_pch_lpt) ||
3461 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI)) {
3462 /* Stable 96MHz frequency */
3463 incperiod = INCPERIOD_96MHz;
3464 incvalue = INCVALUE_96MHz;
3465 shift = INCVALUE_SHIFT_96MHz;
3466 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
3467 break;
3468 }
3469 /* fall-through */
3470 case e1000_82574:
3471 case e1000_82583:
3472 /* Stable 25MHz frequency */
3473 incperiod = INCPERIOD_25MHz;
3474 incvalue = INCVALUE_25MHz;
3475 shift = INCVALUE_SHIFT_25MHz;
3476 adapter->cc.shift = shift;
3477 break;
3478 default:
3479 return -EINVAL;
3480 }
3481
3482 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3483 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3484
3485 return 0;
3486}
3487
3488/**
3489 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3490 * @adapter: board private structure
3491 *
3492 * Outgoing time stamping can be enabled and disabled. Play nice and
3493 * disable it when requested, although it shouldn't cause any overhead
3494 * when no packet needs it. At most one packet in the queue may be
3495 * marked for time stamping, otherwise it would be impossible to tell
3496 * for sure to which packet the hardware time stamp belongs.
3497 *
3498 * Incoming time stamping has to be configured via the hardware filters.
3499 * Not all combinations are supported, in particular event type has to be
3500 * specified. Matching the kind of event packet is not supported, with the
3501 * exception of "all V2 events regardless of level 2 or 4".
3502 **/
62d7e3a2
BH		 3503static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3504 struct hwtstamp_config *config)
b67e1913
BA		 3505{
3506 struct e1000_hw *hw = &adapter->hw;
b67e1913
BA		 3507 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3508 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3509 u32 rxmtrl = 0;
3510 u16 rxudp = 0;
3511 bool is_l4 = false;
3512 bool is_l2 = false;
b67e1913
BA		 3513 u32 regval;
3514 s32 ret_val;
3515
3516 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3517 return -EINVAL;
3518
3519 /* flags reserved for future extensions - must be zero */
3520 if (config->flags)
3521 return -EINVAL;
3522
3523 switch (config->tx_type) {
3524 case HWTSTAMP_TX_OFF:
3525 tsync_tx_ctl = 0;
3526 break;
3527 case HWTSTAMP_TX_ON:
3528 break;
3529 default:
3530 return -ERANGE;
3531 }
3532
3533 switch (config->rx_filter) {
3534 case HWTSTAMP_FILTER_NONE:
3535 tsync_rx_ctl = 0;
3536 break;
d89777bf
BA		 3537 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3538 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3539 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3540 is_l4 = true;
3541 break;
3542 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3543 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3544 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3545 is_l4 = true;
3546 break;
3547 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3548 /* Also time stamps V2 L2 Path Delay Request/Response */
3549 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3550 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3551 is_l2 = true;
3552 break;
3553 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3554 /* Also time stamps V2 L2 Path Delay Request/Response. */
3555 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3556 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3557 is_l2 = true;
3558 break;
3559 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3560 /* Hardware cannot filter just V2 L4 Sync messages;
3561 * fall-through to V2 (both L2 and L4) Sync.
3562 */
3563 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3564 /* Also time stamps V2 Path Delay Request/Response. */
3565 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3566 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3567 is_l2 = true;
3568 is_l4 = true;
3569 break;
3570 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3571 /* Hardware cannot filter just V2 L4 Delay Request messages;
3572 * fall-through to V2 (both L2 and L4) Delay Request.
3573 */
3574 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3575 /* Also time stamps V2 Path Delay Request/Response. */
3576 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3577 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3578 is_l2 = true;
3579 is_l4 = true;
3580 break;
3581 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3582 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3583 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3584 * fall-through to all V2 (both L2 and L4) Events.
3585 */
3586 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3587 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3588 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3589 is_l2 = true;
3590 is_l4 = true;
3591 break;
3592 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3593 /* For V1, the hardware can only filter Sync messages or
3594 * Delay Request messages but not both so fall-through to
3595 * time stamp all packets.
3596 */
b67e1913 3597 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3598 is_l2 = true;
3599 is_l4 = true;
b67e1913
BA		 3600 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3601 config->rx_filter = HWTSTAMP_FILTER_ALL;
3602 break;
3603 default:
3604 return -ERANGE;
3605 }
3606
62d7e3a2
BH		 3607 adapter->hwtstamp_config = *config;
3608
b67e1913
BA		 3609 /* enable/disable Tx h/w time stamping */
3610 regval = er32(TSYNCTXCTL);
3611 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3612 regval |= tsync_tx_ctl;
3613 ew32(TSYNCTXCTL, regval);
3614 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3615 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3616 e_err("Timesync Tx Control register not set as expected\n");
3617 return -EAGAIN;
3618 }
3619
3620 /* enable/disable Rx h/w time stamping */
3621 regval = er32(TSYNCRXCTL);
3622 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3623 regval |= tsync_rx_ctl;
3624 ew32(TSYNCRXCTL, regval);
3625 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3626 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3627 (regval & (E1000_TSYNCRXCTL_ENABLED |
3628 E1000_TSYNCRXCTL_TYPE_MASK))) {
3629 e_err("Timesync Rx Control register not set as expected\n");
3630 return -EAGAIN;
3631 }
3632
d89777bf
BA		 3633 /* L2: define ethertype filter for time stamped packets */
3634 if (is_l2)
3635 rxmtrl |= ETH_P_1588;
3636
3637 /* define which PTP packets get time stamped */
3638 ew32(RXMTRL, rxmtrl);
3639
3640 /* Filter by destination port */
3641 if (is_l4) {
3642 rxudp = PTP_EV_PORT;
3643 cpu_to_be16s(&rxudp);
3644 }
3645 ew32(RXUDP, rxudp);
3646
3647 e1e_flush();
3648
b67e1913 3649 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
70806a7f
BA		 3650 er32(RXSTMPH);
3651 er32(TXSTMPH);
b67e1913
BA		 3652
3653 /* Get and set the System Time Register SYSTIM base frequency */
3654 ret_val = e1000e_get_base_timinca(adapter, &regval);
3655 if (ret_val)
3656 return ret_val;
3657 ew32(TIMINCA, regval);
3658
3659 /* reset the ns time counter */
3660 timecounter_init(&adapter->tc, &adapter->cc,
3661 ktime_to_ns(ktime_get_real()));
3662
3663 return 0;
3664}
3665
bc7f75fa 3666/**
ad68076e 3667 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3668 * @adapter: private board structure
3669 **/
3670static void e1000_configure(struct e1000_adapter *adapter)
3671{
55aa6985
BA		 3672 struct e1000_ring *rx_ring = adapter->rx_ring;
3673
ef9b965a 3674 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3675
3676 e1000_restore_vlan(adapter);
cd791618 3677 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3678
3679 e1000_configure_tx(adapter);
70495a50
BA		 3680
3681 if (adapter->netdev->features & NETIF_F_RXHASH)
3682 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3683 e1000_setup_rctl(adapter);
3684 e1000_configure_rx(adapter);
55aa6985 3685 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3686}
3687
3688/**
3689 * e1000e_power_up_phy - restore link in case the phy was powered down
3690 * @adapter: address of board private structure
3691 *
3692 * The phy may be powered down to save power and turn off link when the
3693 * driver is unloaded and wake on lan is not enabled (among others)
3694 * *** this routine MUST be followed by a call to e1000e_reset ***
3695 **/
3696void e1000e_power_up_phy(struct e1000_adapter *adapter)
3697{
17f208de
BA		 3698 if (adapter->hw.phy.ops.power_up)
3699 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3700
3701 adapter->hw.mac.ops.setup_link(&adapter->hw);
3702}
3703
3704/**
3705 * e1000_power_down_phy - Power down the PHY
3706 *
17f208de
BA		 3707 * Power down the PHY so no link is implied when interface is down.
3708 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3709 */
3710static void e1000_power_down_phy(struct e1000_adapter *adapter)
3711{
17f208de
BA		 3712 if (adapter->hw.phy.ops.power_down)
3713 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3714}
3715
3716/**
3717 * e1000e_reset - bring the hardware into a known good state
3718 *
3719 * This function boots the hardware and enables some settings that
3720 * require a configuration cycle of the hardware - those cannot be
3721 * set/changed during runtime. After reset the device needs to be
ad68076e 3722 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3723 */
3724void e1000e_reset(struct e1000_adapter *adapter)
3725{
3726 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3727 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3728 struct e1000_hw *hw = &adapter->hw;
3729 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3730 u32 pba = adapter->pba;
bc7f75fa
AK		 3731 u16 hwm;
3732
ad68076e 3733 /* reset Packet Buffer Allocation to default */
318a94d6 3734 ew32(PBA, pba);
df762464 3735
318a94d6 3736 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
e921eb1a 3737 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3738 * large enough to accommodate two full transmit packets,
3739 * rounded up to the next 1KB and expressed in KB. Likewise,
3740 * the Rx FIFO should be large enough to accommodate at least
3741 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3742 * expressed in KB.
3743 */
df762464 3744 pba = er32(PBA);
bc7f75fa 3745 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3746 tx_space = pba >> 16;
bc7f75fa 3747 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3748 pba &= 0xffff;
e921eb1a 3749 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3750 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3751 */
3752 min_tx_space = (adapter->max_frame_size +
e5fe2541 3753 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
bc7f75fa
AK		 3754 min_tx_space = ALIGN(min_tx_space, 1024);
3755 min_tx_space >>= 10;
3756 /* software strips receive CRC, so leave room for it */
318a94d6 3757 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3758 min_rx_space = ALIGN(min_rx_space, 1024);
3759 min_rx_space >>= 10;
3760
e921eb1a 3761 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3762 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3763 * allocation, take space away from current Rx allocation
3764 */
df762464
AK		 3765 if ((tx_space < min_tx_space) &&
3766 ((min_tx_space - tx_space) < pba)) {
3767 pba -= min_tx_space - tx_space;
bc7f75fa 3768
e921eb1a 3769 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3770 * adjustment
ad68076e 3771 */
79d4e908 3772 if (pba < min_rx_space)
df762464 3773 pba = min_rx_space;
bc7f75fa 3774 }
df762464
AK		 3775
3776 ew32(PBA, pba);
bc7f75fa
AK		 3777 }
3778
e921eb1a 3779 /* flow control settings
ad68076e 3780 *
38eb394e 3781 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3782 * (or the size used for early receive) above it in the Rx FIFO.
3783 * Set it to the lower of:
3784 * - 90% of the Rx FIFO size, and
38eb394e 3785 * - the full Rx FIFO size minus one full frame
ad68076e 3786 */
d3738bb8
BA		 3787 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3788 fc->pause_time = 0xFFFF;
3789 else
3790 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3791 fc->send_xon = true;
d3738bb8
BA		 3792 fc->current_mode = fc->requested_mode;
3793
3794 switch (hw->mac.type) {
79d4e908
BA		 3795 case e1000_ich9lan:
3796 case e1000_ich10lan:
3797 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3798 pba = 14;
3799 ew32(PBA, pba);
3800 fc->high_water = 0x2800;
3801 fc->low_water = fc->high_water - 8;
3802 break;
3803 }
3804 /* fall-through */
d3738bb8 3805 default:
79d4e908
BA		 3806 hwm = min(((pba << 10) * 9 / 10),
3807 ((pba << 10) - adapter->max_frame_size));
d3738bb8 3808
e80bd1d1 3809 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
d3738bb8
BA		 3810 fc->low_water = fc->high_water - 8;
3811 break;
3812 case e1000_pchlan:
e921eb1a 3813 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 3814 * loads. If hangs persist, try disabling Tx flow control.
3815 */
3816 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3817 fc->high_water = 0x3500;
e80bd1d1 3818 fc->low_water = 0x1500;
38eb394e
BA		 3819 } else {
3820 fc->high_water = 0x5000;
e80bd1d1 3821 fc->low_water = 0x3000;
38eb394e 3822 }
a305595b 3823 fc->refresh_time = 0x1000;
d3738bb8
BA		 3824 break;
3825 case e1000_pch2lan:
2fbe4526 3826 case e1000_pch_lpt:
d3738bb8 3827 fc->refresh_time = 0x0400;
347b5201
BA		 3828
3829 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
3830 fc->high_water = 0x05C20;
3831 fc->low_water = 0x05048;
3832 fc->pause_time = 0x0650;
3833 break;
828bac87 3834 }
347b5201 3835
ce345e08
BA		 3836 pba = 14;
3837 ew32(PBA, pba);
347b5201
BA		 3838 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
3839 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 3840 break;
38eb394e 3841 }
bc7f75fa 3842
e921eb1a 3843 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 3844 * maximum size per Tx descriptor limited only to the transmit
3845 * allocation of the packet buffer minus 96 bytes with an upper
3846 * limit of 24KB due to receive synchronization limitations.
3847 */
3848 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
3849 24 << 10);
3850
e921eb1a 3851 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 3852 * fit in receive buffer.
828bac87
BA		 3853 */
3854 if (adapter->itr_setting & 0x3) {
79d4e908 3855 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 3856 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
3857 dev_info(&adapter->pdev->dev,
17e813ec 3858 "Interrupt Throttle Rate off\n");
828bac87 3859 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 3860 e1000e_write_itr(adapter, 0);
828bac87
BA		 3861 }
3862 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
3863 dev_info(&adapter->pdev->dev,
17e813ec 3864 "Interrupt Throttle Rate on\n");
828bac87
BA		 3865 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
3866 adapter->itr = 20000;
22a4cca2 3867 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 3868 }
3869 }
3870
bc7f75fa
AK		 3871 /* Allow time for pending master requests to run */
3872 mac->ops.reset_hw(hw);
97ac8cae 3873
e921eb1a 3874 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 3875 * that the network interface is in control
3876 */
c43bc57e 3877 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 3878 e1000e_get_hw_control(adapter);
97ac8cae 3879
bc7f75fa
AK		 3880 ew32(WUC, 0);
3881
3882 if (mac->ops.init_hw(hw))
44defeb3 3883 e_err("Hardware Error\n");
bc7f75fa
AK		 3884
3885 e1000_update_mng_vlan(adapter);
3886
3887 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
3888 ew32(VET, ETH_P_8021Q);
3889
3890 e1000e_reset_adaptive(hw);
31dbe5b4 3891
b67e1913 3892 /* initialize systim and reset the ns time counter */
62d7e3a2 3893 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
b67e1913 3894
d495bcb8
BA		 3895 /* Set EEE advertisement as appropriate */
3896 if (adapter->flags2 & FLAG2_HAS_EEE) {
3897 s32 ret_val;
3898 u16 adv_addr;
3899
3900 switch (hw->phy.type) {
3901 case e1000_phy_82579:
3902 adv_addr = I82579_EEE_ADVERTISEMENT;
3903 break;
3904 case e1000_phy_i217:
3905 adv_addr = I217_EEE_ADVERTISEMENT;
3906 break;
3907 default:
3908 dev_err(&adapter->pdev->dev,
3909 "Invalid PHY type setting EEE advertisement\n");
3910 return;
3911 }
3912
3913 ret_val = hw->phy.ops.acquire(hw);
3914 if (ret_val) {
3915 dev_err(&adapter->pdev->dev,
3916 "EEE advertisement - unable to acquire PHY\n");
3917 return;
3918 }
3919
3920 e1000_write_emi_reg_locked(hw, adv_addr,
3921 hw->dev_spec.ich8lan.eee_disable ?
3922 0 : adapter->eee_advert);
3923
3924 hw->phy.ops.release(hw);
3925 }
3926
31dbe5b4 3927 if (!netif_running(adapter->netdev) &&
28002099 3928 !test_bit(__E1000_TESTING, &adapter->state))
31dbe5b4 3929 e1000_power_down_phy(adapter);
31dbe5b4 3930
bc7f75fa
AK		 3931 e1000_get_phy_info(hw);
3932
918d7197
BA		 3933 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
3934 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 3935 u16 phy_data = 0;
e921eb1a 3936 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 3937 * the return value of this function because there is nothing
ad68076e
BA		 3938 * different we would do if it failed
3939 */
bc7f75fa
AK		 3940 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
3941 phy_data &= ~IGP02E1000_PM_SPD;
3942 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
3943 }
bc7f75fa
AK		 3944}
3945
3946int e1000e_up(struct e1000_adapter *adapter)
3947{
3948 struct e1000_hw *hw = &adapter->hw;
3949
3950 /* hardware has been reset, we need to reload some things */
3951 e1000_configure(adapter);
3952
3953 clear_bit(__E1000_DOWN, &adapter->state);
3954
4662e82b
BA		 3955 if (adapter->msix_entries)
3956 e1000_configure_msix(adapter);
bc7f75fa
AK		 3957 e1000_irq_enable(adapter);
3958
400484fa 3959 netif_start_queue(adapter->netdev);
4cb9be7a 3960
bc7f75fa 3961 /* fire a link change interrupt to start the watchdog */
52a9b231
BA		 3962 if (adapter->msix_entries)
3963 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
3964 else
3965 ew32(ICS, E1000_ICS_LSC);
3966
bc7f75fa
AK		 3967 return 0;
3968}
3969
713b3c9e
JB		 3970static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
3971{
3972 struct e1000_hw *hw = &adapter->hw;
3973
3974 if (!(adapter->flags2 & FLAG2_DMA_BURST))
3975 return;
3976
3977 /* flush pending descriptor writebacks to memory */
3978 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3979 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
3980
3981 /* execute the writes immediately */
3982 e1e_flush();
bf03085f 3983
e921eb1a 3984 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 3985 * write is successful
3986 */
3987 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
3988 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 3989
3990 /* execute the writes immediately */
3991 e1e_flush();
3992}
3993
67fd4fcb
JK		 3994static void e1000e_update_stats(struct e1000_adapter *adapter);
3995
28002099
DE		 3996/**
3997 * e1000e_down - quiesce the device and optionally reset the hardware
3998 * @adapter: board private structure
3999 * @reset: boolean flag to reset the hardware or not
4000 */
4001void e1000e_down(struct e1000_adapter *adapter, bool reset)
bc7f75fa
AK		 4002{
4003 struct net_device *netdev = adapter->netdev;
4004 struct e1000_hw *hw = &adapter->hw;
4005 u32 tctl, rctl;
4006
e921eb1a 4007 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 4008 * reschedule our watchdog timer
4009 */
bc7f75fa
AK		 4010 set_bit(__E1000_DOWN, &adapter->state);
4011
4012 /* disable receives in the hardware */
4013 rctl = er32(RCTL);
7f99ae63
BA		 4014 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4015 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 4016 /* flush and sleep below */
4017
4cb9be7a 4018 netif_stop_queue(netdev);
bc7f75fa
AK		 4019
4020 /* disable transmits in the hardware */
4021 tctl = er32(TCTL);
4022 tctl &= ~E1000_TCTL_EN;
4023 ew32(TCTL, tctl);
7f99ae63 4024
bc7f75fa
AK		 4025 /* flush both disables and wait for them to finish */
4026 e1e_flush();
1bba4386 4027 usleep_range(10000, 20000);
bc7f75fa 4028
bc7f75fa
AK		 4029 e1000_irq_disable(adapter);
4030
a3b87a4c
BA		 4031 napi_synchronize(&adapter->napi);
4032
bc7f75fa
AK		 4033 del_timer_sync(&adapter->watchdog_timer);
4034 del_timer_sync(&adapter->phy_info_timer);
4035
bc7f75fa 4036 netif_carrier_off(netdev);
67fd4fcb
JK		 4037
4038 spin_lock(&adapter->stats64_lock);
4039 e1000e_update_stats(adapter);
4040 spin_unlock(&adapter->stats64_lock);
4041
400484fa 4042 e1000e_flush_descriptors(adapter);
55aa6985
BA		 4043 e1000_clean_tx_ring(adapter->tx_ring);
4044 e1000_clean_rx_ring(adapter->rx_ring);
400484fa 4045
bc7f75fa
AK		 4046 adapter->link_speed = 0;
4047 adapter->link_duplex = 0;
4048
da1e2046
BA		 4049 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4050 if ((hw->mac.type >= e1000_pch2lan) &&
4051 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4052 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4053 e_dbg("failed to disable jumbo frame workaround mode\n");
4054
28002099 4055 if (reset && !pci_channel_offline(adapter->pdev))
52cc3086 4056 e1000e_reset(adapter);
bc7f75fa
AK		 4057}
4058
4059void e1000e_reinit_locked(struct e1000_adapter *adapter)
4060{
4061 might_sleep();
4062 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 4063 usleep_range(1000, 2000);
28002099 4064 e1000e_down(adapter, true);
bc7f75fa
AK		 4065 e1000e_up(adapter);
4066 clear_bit(__E1000_RESETTING, &adapter->state);
4067}
4068
b67e1913
BA		 4069/**
4070 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4071 * @cc: cyclecounter structure
4072 **/
4073static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4074{
4075 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4076 cc);
4077 struct e1000_hw *hw = &adapter->hw;
4078 cycle_t systim;
4079
4080 /* latch SYSTIMH on read of SYSTIML */
4081 systim = (cycle_t)er32(SYSTIML);
4082 systim |= (cycle_t)er32(SYSTIMH) << 32;
4083
4084 return systim;
4085}
4086
bc7f75fa
AK		 4087/**
4088 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4089 * @adapter: board private structure to initialize
4090 *
4091 * e1000_sw_init initializes the Adapter private data structure.
4092 * Fields are initialized based on PCI device information and
4093 * OS network device settings (MTU size).
4094 **/
9f9a12f8 4095static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4096{
bc7f75fa
AK		 4097 struct net_device *netdev = adapter->netdev;
4098
4099 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN;
4100 adapter->rx_ps_bsize0 = 128;
318a94d6
JK		 4101 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4102 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4103 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4104 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4105
67fd4fcb
JK		 4106 spin_lock_init(&adapter->stats64_lock);
4107
4662e82b 4108 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4109
4662e82b
BA		 4110 if (e1000_alloc_queues(adapter))
4111 return -ENOMEM;
bc7f75fa 4112
b67e1913
BA		 4113 /* Setup hardware time stamping cyclecounter */
4114 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4115 adapter->cc.read = e1000e_cyclecounter_read;
4116 adapter->cc.mask = CLOCKSOURCE_MASK(64);
4117 adapter->cc.mult = 1;
4118 /* cc.shift set in e1000e_get_base_tininca() */
4119
4120 spin_lock_init(&adapter->systim_lock);
4121 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4122 }
4123
bc7f75fa 4124 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4125 e1000_irq_disable(adapter);
4126
bc7f75fa
AK		 4127 set_bit(__E1000_DOWN, &adapter->state);
4128 return 0;
bc7f75fa
AK		 4129}
4130
f8d59f78
BA		 4131/**
4132 * e1000_intr_msi_test - Interrupt Handler
4133 * @irq: interrupt number
4134 * @data: pointer to a network interface device structure
4135 **/
8bb62869 4136static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
f8d59f78
BA		 4137{
4138 struct net_device *netdev = data;
4139 struct e1000_adapter *adapter = netdev_priv(netdev);
4140 struct e1000_hw *hw = &adapter->hw;
4141 u32 icr = er32(ICR);
4142
3bb99fe2 4143 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4144 if (icr & E1000_ICR_RXSEQ) {
4145 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4146 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4147 * interrupt is handled.
4148 */
f8d59f78
BA		 4149 wmb();
4150 }
4151
4152 return IRQ_HANDLED;
4153}
4154
4155/**
4156 * e1000_test_msi_interrupt - Returns 0 for successful test
4157 * @adapter: board private struct
4158 *
4159 * code flow taken from tg3.c
4160 **/
4161static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4162{
4163 struct net_device *netdev = adapter->netdev;
4164 struct e1000_hw *hw = &adapter->hw;
4165 int err;
4166
4167 /* poll_enable hasn't been called yet, so don't need disable */
4168 /* clear any pending events */
4169 er32(ICR);
4170
4171 /* free the real vector and request a test handler */
4172 e1000_free_irq(adapter);
4662e82b 4173 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4174
4175 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4176 * MSI irq handler will unset this flag
4177 */
f8d59f78
BA		 4178 adapter->flags |= FLAG_MSI_TEST_FAILED;
4179
4180 err = pci_enable_msi(adapter->pdev);
4181 if (err)
4182 goto msi_test_failed;
4183
a0607fd3 4184 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4185 netdev->name, netdev);
4186 if (err) {
4187 pci_disable_msi(adapter->pdev);
4188 goto msi_test_failed;
4189 }
4190
e921eb1a 4191 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4192 * interrupt.
4193 */
f8d59f78
BA		 4194 wmb();
4195
4196 e1000_irq_enable(adapter);
4197
4198 /* fire an unusual interrupt on the test handler */
4199 ew32(ICS, E1000_ICS_RXSEQ);
4200 e1e_flush();
569a3aff 4201 msleep(100);
f8d59f78
BA		 4202
4203 e1000_irq_disable(adapter);
4204
bc76329d 4205 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4206
4207 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4208 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4209 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4210 } else {
068e8a30 4211 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4212 }
f8d59f78
BA		 4213
4214 free_irq(adapter->pdev->irq, netdev);
4215 pci_disable_msi(adapter->pdev);
4216
f8d59f78 4217msi_test_failed:
4662e82b 4218 e1000e_set_interrupt_capability(adapter);
068e8a30 4219 return e1000_request_irq(adapter);
f8d59f78
BA		 4220}
4221
4222/**
4223 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4224 * @adapter: board private struct
4225 *
4226 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4227 **/
4228static int e1000_test_msi(struct e1000_adapter *adapter)
4229{
4230 int err;
4231 u16 pci_cmd;
4232
4233 if (!(adapter->flags & FLAG_MSI_ENABLED))
4234 return 0;
4235
4236 /* disable SERR in case the MSI write causes a master abort */
4237 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4238 if (pci_cmd & PCI_COMMAND_SERR)
4239 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4240 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4241
4242 err = e1000_test_msi_interrupt(adapter);
4243
36f2407f
DN		 4244 /* re-enable SERR */
4245 if (pci_cmd & PCI_COMMAND_SERR) {
4246 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4247 pci_cmd |= PCI_COMMAND_SERR;
4248 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4249 }
f8d59f78 4250
f8d59f78
BA		 4251 return err;
4252}
4253
bc7f75fa
AK		 4254/**
4255 * e1000_open - Called when a network interface is made active
4256 * @netdev: network interface device structure
4257 *
4258 * Returns 0 on success, negative value on failure
4259 *
4260 * The open entry point is called when a network interface is made
4261 * active by the system (IFF_UP). At this point all resources needed
4262 * for transmit and receive operations are allocated, the interrupt
4263 * handler is registered with the OS, the watchdog timer is started,
4264 * and the stack is notified that the interface is ready.
4265 **/
4266static int e1000_open(struct net_device *netdev)
4267{
4268 struct e1000_adapter *adapter = netdev_priv(netdev);
4269 struct e1000_hw *hw = &adapter->hw;
23606cf5 4270 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4271 int err;
4272
4273 /* disallow open during test */
4274 if (test_bit(__E1000_TESTING, &adapter->state))
4275 return -EBUSY;
4276
23606cf5
RW		 4277 pm_runtime_get_sync(&pdev->dev);
4278
9c563d20
JB		 4279 netif_carrier_off(netdev);
4280
bc7f75fa 4281 /* allocate transmit descriptors */
55aa6985 4282 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4283 if (err)
4284 goto err_setup_tx;
4285
4286 /* allocate receive descriptors */
55aa6985 4287 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4288 if (err)
4289 goto err_setup_rx;
4290
e921eb1a 4291 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4292 * interface is now open and reset the part to a known state.
4293 */
4294 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4295 e1000e_get_hw_control(adapter);
11b08be8
BA		 4296 e1000e_reset(adapter);
4297 }
4298
bc7f75fa
AK		 4299 e1000e_power_up_phy(adapter);
4300
4301 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
e5fe2541 4302 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
bc7f75fa
AK		 4303 e1000_update_mng_vlan(adapter);
4304
79d4e908 4305 /* DMA latency requirement to workaround jumbo issue */
3e35d991
BA		 4306 pm_qos_add_request(&adapter->netdev->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
4307 PM_QOS_DEFAULT_VALUE);
c128ec29 4308
e921eb1a 4309 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4310 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4311 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4312 * clean_rx handler before we do so.
4313 */
bc7f75fa
AK		 4314 e1000_configure(adapter);
4315
4316 err = e1000_request_irq(adapter);
4317 if (err)
4318 goto err_req_irq;
4319
e921eb1a 4320 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4321 * ignore e1000e MSI messages, which means we need to test our MSI
4322 * interrupt now
4323 */
4662e82b 4324 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4325 err = e1000_test_msi(adapter);
4326 if (err) {
4327 e_err("Interrupt allocation failed\n");
4328 goto err_req_irq;
4329 }
4330 }
4331
bc7f75fa
AK		 4332 /* From here on the code is the same as e1000e_up() */
4333 clear_bit(__E1000_DOWN, &adapter->state);
4334
4335 napi_enable(&adapter->napi);
4336
4337 e1000_irq_enable(adapter);
4338
09357b00 4339 adapter->tx_hang_recheck = false;
4cb9be7a 4340 netif_start_queue(netdev);
d55b53ff 4341
66148bab 4342 hw->mac.get_link_status = true;
23606cf5
RW		 4343 pm_runtime_put(&pdev->dev);
4344
bc7f75fa 4345 /* fire a link status change interrupt to start the watchdog */
52a9b231
BA		 4346 if (adapter->msix_entries)
4347 ew32(ICS, E1000_ICS_LSC | E1000_ICR_OTHER);
4348 else
4349 ew32(ICS, E1000_ICS_LSC);
bc7f75fa
AK		 4350
4351 return 0;
4352
4353err_req_irq:
31dbe5b4 4354 e1000e_release_hw_control(adapter);
bc7f75fa 4355 e1000_power_down_phy(adapter);
55aa6985 4356 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4357err_setup_rx:
55aa6985 4358 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4359err_setup_tx:
4360 e1000e_reset(adapter);
23606cf5 4361 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4362
4363 return err;
4364}
4365
4366/**
4367 * e1000_close - Disables a network interface
4368 * @netdev: network interface device structure
4369 *
4370 * Returns 0, this is not allowed to fail
4371 *
4372 * The close entry point is called when an interface is de-activated
4373 * by the OS. The hardware is still under the drivers control, but
4374 * needs to be disabled. A global MAC reset is issued to stop the
4375 * hardware, and all transmit and receive resources are freed.
4376 **/
4377static int e1000_close(struct net_device *netdev)
4378{
4379 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4380 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4381 int count = E1000_CHECK_RESET_COUNT;
4382
4383 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4384 usleep_range(10000, 20000);
bc7f75fa
AK		 4385
4386 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4387
4388 pm_runtime_get_sync(&pdev->dev);
4389
4390 if (!test_bit(__E1000_DOWN, &adapter->state)) {
28002099 4391 e1000e_down(adapter, true);
23606cf5 4392 e1000_free_irq(adapter);
63eb48f1
DE		 4393
4394 /* Link status message must follow this format */
4395 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
23606cf5 4396 }
a3b87a4c
BA		 4397
4398 napi_disable(&adapter->napi);
4399
55aa6985
BA		 4400 e1000e_free_tx_resources(adapter->tx_ring);
4401 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4402
e921eb1a 4403 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4404 * the same ID is registered on the host OS (let 8021q kill it)
4405 */
e5fe2541 4406 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
80d5c368
PM		 4407 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4408 adapter->mng_vlan_id);
bc7f75fa 4409
e921eb1a 4410 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4411 * interface is now closed
4412 */
31dbe5b4
BA		 4413 if ((adapter->flags & FLAG_HAS_AMT) &&
4414 !test_bit(__E1000_TESTING, &adapter->state))
4415 e1000e_release_hw_control(adapter);
bc7f75fa 4416
3e35d991 4417 pm_qos_remove_request(&adapter->netdev->pm_qos_req);
c128ec29 4418
23606cf5
RW		 4419 pm_runtime_put_sync(&pdev->dev);
4420
bc7f75fa
AK		 4421 return 0;
4422}
fc830b78 4423
bc7f75fa
AK		 4424/**
4425 * e1000_set_mac - Change the Ethernet Address of the NIC
4426 * @netdev: network interface device structure
4427 * @p: pointer to an address structure
4428 *
4429 * Returns 0 on success, negative on failure
4430 **/
4431static int e1000_set_mac(struct net_device *netdev, void *p)
4432{
4433 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4434 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4435 struct sockaddr *addr = p;
4436
4437 if (!is_valid_ether_addr(addr->sa_data))
4438 return -EADDRNOTAVAIL;
4439
4440 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4441 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4442
69e1e019 4443 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4444
4445 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4446 /* activate the work around */
4447 e1000e_set_laa_state_82571(&adapter->hw, 1);
4448
e921eb1a 4449 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4450 * between the time RAR[0] gets clobbered and the time it
4451 * gets fixed (in e1000_watchdog), the actual LAA is in one
4452 * of the RARs and no incoming packets directed to this port
4453 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4454 * RAR[14]
4455 */
69e1e019
BA		 4456 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4457 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4458 }
4459
4460 return 0;
4461}
4462
a8f88ff5
JB		 4463/**
4464 * e1000e_update_phy_task - work thread to update phy
4465 * @work: pointer to our work struct
4466 *
4467 * this worker thread exists because we must acquire a
4468 * semaphore to read the phy, which we could msleep while
4469 * waiting for it, and we can't msleep in a timer.
4470 **/
4471static void e1000e_update_phy_task(struct work_struct *work)
4472{
4473 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4474 struct e1000_adapter,
4475 update_phy_task);
a03206ed 4476 struct e1000_hw *hw = &adapter->hw;
615b32af
JB		 4477
4478 if (test_bit(__E1000_DOWN, &adapter->state))
4479 return;
4480
a03206ed
DE		 4481 e1000_get_phy_info(hw);
4482
4483 /* Enable EEE on 82579 after link up */
4484 if (hw->phy.type == e1000_phy_82579)
4485 e1000_set_eee_pchlan(hw);
a8f88ff5
JB		 4486}
4487
e921eb1a
BA		 4488/**
4489 * e1000_update_phy_info - timre call-back to update PHY info
4490 * @data: pointer to adapter cast into an unsigned long
4491 *
ad68076e
BA		 4492 * Need to wait a few seconds after link up to get diagnostic information from
4493 * the phy
e921eb1a 4494 **/
bc7f75fa
AK		 4495static void e1000_update_phy_info(unsigned long data)
4496{
53aa82da 4497 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
615b32af
JB		 4498
4499 if (test_bit(__E1000_DOWN, &adapter->state))
4500 return;
4501
a8f88ff5 4502 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4503}
4504
8c7bbb92
BA		 4505/**
4506 * e1000e_update_phy_stats - Update the PHY statistics counters
4507 * @adapter: board private structure
2b6b168d
BA		 4508 *
4509 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4510 **/
4511static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4512{
4513 struct e1000_hw *hw = &adapter->hw;
4514 s32 ret_val;
4515 u16 phy_data;
4516
4517 ret_val = hw->phy.ops.acquire(hw);
4518 if (ret_val)
4519 return;
4520
e921eb1a 4521 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4522 * If not, set to the page with the PHY status registers.
4523 */
2b6b168d 4524 hw->phy.addr = 1;
8c7bbb92
BA		 4525 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4526 &phy_data);
4527 if (ret_val)
4528 goto release;
2b6b168d
BA		 4529 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4530 ret_val = hw->phy.ops.set_page(hw,
4531 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4532 if (ret_val)
4533 goto release;
4534 }
4535
8c7bbb92 4536 /* Single Collision Count */
2b6b168d
BA		 4537 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4538 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4539 if (!ret_val)
4540 adapter->stats.scc += phy_data;
4541
4542 /* Excessive Collision Count */
2b6b168d
BA		 4543 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4544 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4545 if (!ret_val)
4546 adapter->stats.ecol += phy_data;
4547
4548 /* Multiple Collision Count */
2b6b168d
BA		 4549 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4550 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4551 if (!ret_val)
4552 adapter->stats.mcc += phy_data;
4553
4554 /* Late Collision Count */
2b6b168d
BA		 4555 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4556 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4557 if (!ret_val)
4558 adapter->stats.latecol += phy_data;
4559
4560 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4561 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4562 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4563 if (!ret_val)
4564 hw->mac.collision_delta = phy_data;
4565
4566 /* Defer Count */
2b6b168d
BA		 4567 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4568 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4569 if (!ret_val)
4570 adapter->stats.dc += phy_data;
4571
4572 /* Transmit with no CRS */
2b6b168d
BA		 4573 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4574 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4575 if (!ret_val)
4576 adapter->stats.tncrs += phy_data;
4577
4578release:
4579 hw->phy.ops.release(hw);
4580}
4581
bc7f75fa
AK		 4582/**
4583 * e1000e_update_stats - Update the board statistics counters
4584 * @adapter: board private structure
4585 **/
67fd4fcb 4586static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4587{
7274c20f 4588 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4589 struct e1000_hw *hw = &adapter->hw;
4590 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4591
e921eb1a 4592 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4593 * connection is down.
4594 */
4595 if (adapter->link_speed == 0)
4596 return;
4597 if (pci_channel_offline(pdev))
4598 return;
4599
bc7f75fa
AK		 4600 adapter->stats.crcerrs += er32(CRCERRS);
4601 adapter->stats.gprc += er32(GPRC);
7c25769f 4602 adapter->stats.gorc += er32(GORCL);
e80bd1d1 4603 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4604 adapter->stats.bprc += er32(BPRC);
4605 adapter->stats.mprc += er32(MPRC);
4606 adapter->stats.roc += er32(ROC);
4607
bc7f75fa 4608 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4609
4610 /* Half-duplex statistics */
4611 if (adapter->link_duplex == HALF_DUPLEX) {
4612 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4613 e1000e_update_phy_stats(adapter);
4614 } else {
4615 adapter->stats.scc += er32(SCC);
4616 adapter->stats.ecol += er32(ECOL);
4617 adapter->stats.mcc += er32(MCC);
4618 adapter->stats.latecol += er32(LATECOL);
4619 adapter->stats.dc += er32(DC);
4620
4621 hw->mac.collision_delta = er32(COLC);
4622
4623 if ((hw->mac.type != e1000_82574) &&
4624 (hw->mac.type != e1000_82583))
4625 adapter->stats.tncrs += er32(TNCRS);
4626 }
4627 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4628 }
8c7bbb92 4629
bc7f75fa
AK		 4630 adapter->stats.xonrxc += er32(XONRXC);
4631 adapter->stats.xontxc += er32(XONTXC);
4632 adapter->stats.xoffrxc += er32(XOFFRXC);
4633 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4634 adapter->stats.gptc += er32(GPTC);
7c25769f 4635 adapter->stats.gotc += er32(GOTCL);
e80bd1d1 4636 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4637 adapter->stats.rnbc += er32(RNBC);
4638 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4639
4640 adapter->stats.mptc += er32(MPTC);
4641 adapter->stats.bptc += er32(BPTC);
4642
4643 /* used for adaptive IFS */
4644
4645 hw->mac.tx_packet_delta = er32(TPT);
4646 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4647
4648 adapter->stats.algnerrc += er32(ALGNERRC);
4649 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4650 adapter->stats.cexterr += er32(CEXTERR);
4651 adapter->stats.tsctc += er32(TSCTC);
4652 adapter->stats.tsctfc += er32(TSCTFC);
4653
bc7f75fa 4654 /* Fill out the OS statistics structure */
7274c20f
AK		 4655 netdev->stats.multicast = adapter->stats.mprc;
4656 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4657
4658 /* Rx Errors */
4659
e921eb1a 4660 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4661 * our own version based on RUC and ROC
4662 */
7274c20f 4663 netdev->stats.rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 4664 adapter->stats.crcerrs + adapter->stats.algnerrc +
4665 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
7274c20f 4666 netdev->stats.rx_length_errors = adapter->stats.ruc +
f0ff4398 4667 adapter->stats.roc;
7274c20f
AK		 4668 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4669 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4670 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4671
4672 /* Tx Errors */
f0ff4398 4673 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
7274c20f
AK		 4674 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4675 netdev->stats.tx_window_errors = adapter->stats.latecol;
4676 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4677
4678 /* Tx Dropped needs to be maintained elsewhere */
4679
bc7f75fa
AK		 4680 /* Management Stats */
4681 adapter->stats.mgptc += er32(MGTPTC);
4682 adapter->stats.mgprc += er32(MGTPRC);
4683 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 4684
4685 /* Correctable ECC Errors */
4686 if (hw->mac.type == e1000_pch_lpt) {
4687 u32 pbeccsts = er32(PBECCSTS);
4688 adapter->corr_errors +=
4689 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4690 adapter->uncorr_errors +=
4691 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4692 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4693 }
bc7f75fa
AK		 4694}
4695
7c25769f
BA		 4696/**
4697 * e1000_phy_read_status - Update the PHY register status snapshot
4698 * @adapter: board private structure
4699 **/
4700static void e1000_phy_read_status(struct e1000_adapter *adapter)
4701{
4702 struct e1000_hw *hw = &adapter->hw;
4703 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f 4704
97390ab8
BA		 4705 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
4706 (er32(STATUS) & E1000_STATUS_LU) &&
7c25769f 4707 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4708 int ret_val;
4709
c2ade1a4
BA		 4710 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4711 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4712 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4713 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4714 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4715 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4716 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4717 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
7c25769f 4718 if (ret_val)
44defeb3 4719 e_warn("Error reading PHY register\n");
7c25769f 4720 } else {
e921eb1a 4721 /* Do not read PHY registers if link is not up
7c25769f
BA		 4722 * Set values to typical power-on defaults
4723 */
4724 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
4725 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
4726 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
4727 BMSR_ERCAP);
4728 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
4729 ADVERTISE_ALL | ADVERTISE_CSMA);
4730 phy->lpa = 0;
4731 phy->expansion = EXPANSION_ENABLENPAGE;
4732 phy->ctrl1000 = ADVERTISE_1000FULL;
4733 phy->stat1000 = 0;
4734 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
4735 }
7c25769f
BA		 4736}
4737
bc7f75fa
AK		 4738static void e1000_print_link_info(struct e1000_adapter *adapter)
4739{
bc7f75fa
AK		 4740 struct e1000_hw *hw = &adapter->hw;
4741 u32 ctrl = er32(CTRL);
4742
8f12fe86 4743 /* Link status message must follow this format for user tools */
7dbc1672
BA		 4744 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
4745 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 4746 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
4747 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
4748 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
4749 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 4750}
4751
0c6bdb30 4752static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 4753{
4754 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 4755 bool link_active = false;
318a94d6
JK		 4756 s32 ret_val = 0;
4757
e921eb1a 4758 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 4759 * Rx sequence error interrupt. get_link_status will stay
4760 * false until the check_for_link establishes link
4761 * for copper adapters ONLY
4762 */
4763 switch (hw->phy.media_type) {
4764 case e1000_media_type_copper:
4765 if (hw->mac.get_link_status) {
4766 ret_val = hw->mac.ops.check_for_link(hw);
4767 link_active = !hw->mac.get_link_status;
4768 } else {
3db1cd5c 4769 link_active = true;
318a94d6
JK		 4770 }
4771 break;
4772 case e1000_media_type_fiber:
4773 ret_val = hw->mac.ops.check_for_link(hw);
4774 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
4775 break;
4776 case e1000_media_type_internal_serdes:
4777 ret_val = hw->mac.ops.check_for_link(hw);
4778 link_active = adapter->hw.mac.serdes_has_link;
4779 break;
4780 default:
4781 case e1000_media_type_unknown:
4782 break;
4783 }
4784
4785 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
4786 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
4787 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 4788 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 4789 }
4790
4791 return link_active;
4792}
4793
4794static void e1000e_enable_receives(struct e1000_adapter *adapter)
4795{
4796 /* make sure the receive unit is started */
4797 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 4798 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 4799 struct e1000_hw *hw = &adapter->hw;
4800 u32 rctl = er32(RCTL);
4801 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 4802 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 4803 }
4804}
4805
ff10e13c
CW		 4806static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
4807{
4808 struct e1000_hw *hw = &adapter->hw;
4809
e921eb1a 4810 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 4811 * for hung state and reset, if two calls return true
4812 */
4813 if (e1000_check_phy_82574(hw))
4814 adapter->phy_hang_count++;
4815 else
4816 adapter->phy_hang_count = 0;
4817
4818 if (adapter->phy_hang_count > 1) {
4819 adapter->phy_hang_count = 0;
d9554e96 4820 e_dbg("PHY appears hung - resetting\n");
ff10e13c
CW		 4821 schedule_work(&adapter->reset_task);
4822 }
4823}
4824
bc7f75fa
AK		 4825/**
4826 * e1000_watchdog - Timer Call-back
4827 * @data: pointer to adapter cast into an unsigned long
4828 **/
4829static void e1000_watchdog(unsigned long data)
4830{
53aa82da 4831 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
bc7f75fa
AK		 4832
4833 /* Do the rest outside of interrupt context */
4834 schedule_work(&adapter->watchdog_task);
4835
4836 /* TODO: make this use queue_delayed_work() */
4837}
4838
4839static void e1000_watchdog_task(struct work_struct *work)
4840{
4841 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4842 struct e1000_adapter,
4843 watchdog_task);
bc7f75fa
AK		 4844 struct net_device *netdev = adapter->netdev;
4845 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 4846 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 4847 struct e1000_ring *tx_ring = adapter->tx_ring;
4848 struct e1000_hw *hw = &adapter->hw;
4849 u32 link, tctl;
bc7f75fa 4850
615b32af
JB		 4851 if (test_bit(__E1000_DOWN, &adapter->state))
4852 return;
4853
b405e8df 4854 link = e1000e_has_link(adapter);
318a94d6 4855 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 4856 /* Cancel scheduled suspend requests. */
4857 pm_runtime_resume(netdev->dev.parent);
4858
318a94d6 4859 e1000e_enable_receives(adapter);
bc7f75fa 4860 goto link_up;
bc7f75fa
AK		 4861 }
4862
4863 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
4864 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
4865 e1000_update_mng_vlan(adapter);
4866
bc7f75fa
AK		 4867 if (link) {
4868 if (!netif_carrier_ok(netdev)) {
3db1cd5c 4869 bool txb2b = true;
23606cf5
RW		 4870
4871 /* Cancel scheduled suspend requests. */
4872 pm_runtime_resume(netdev->dev.parent);
4873
318a94d6 4874 /* update snapshot of PHY registers on LSC */
7c25769f 4875 e1000_phy_read_status(adapter);
bc7f75fa 4876 mac->ops.get_link_up_info(&adapter->hw,
17e813ec
BA		 4877 &adapter->link_speed,
4878 &adapter->link_duplex);
bc7f75fa 4879 e1000_print_link_info(adapter);
e792cd91
KS		 4880
4881 /* check if SmartSpeed worked */
4882 e1000e_check_downshift(hw);
4883 if (phy->speed_downgraded)
4884 netdev_warn(netdev,
4885 "Link Speed was downgraded by SmartSpeed\n");
4886
e921eb1a 4887 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 4888 * if link has autonegotiated at 10/100 half
4889 */
4890 if ((hw->phy.type == e1000_phy_igp_3 ||
4891 hw->phy.type == e1000_phy_bm) &&
138953bb 4892 hw->mac.autoneg &&
f4187b56
BA		 4893 (adapter->link_speed == SPEED_10 ||
4894 adapter->link_speed == SPEED_100) &&
4895 (adapter->link_duplex == HALF_DUPLEX)) {
4896 u16 autoneg_exp;
4897
c2ade1a4 4898 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
f4187b56 4899
c2ade1a4 4900 if (!(autoneg_exp & EXPANSION_NWAY))
ef456f85 4901 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 4902 }
4903
f49c57e1 4904 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 4905 adapter->tx_timeout_factor = 1;
4906 switch (adapter->link_speed) {
4907 case SPEED_10:
3db1cd5c 4908 txb2b = false;
10f1b492 4909 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 4910 break;
4911 case SPEED_100:
3db1cd5c 4912 txb2b = false;
4c86e0b9 4913 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 4914 break;
4915 }
4916
e921eb1a 4917 /* workaround: re-program speed mode bit after
ad68076e
BA		 4918 * link-up event
4919 */
bc7f75fa
AK		 4920 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
4921 !txb2b) {
4922 u32 tarc0;
e9ec2c0f 4923 tarc0 = er32(TARC(0));
bc7f75fa 4924 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 4925 ew32(TARC(0), tarc0);
bc7f75fa
AK		 4926 }
4927
e921eb1a 4928 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 4929 * some hardware issues
4930 */
bc7f75fa
AK		 4931 if (!(adapter->flags & FLAG_TSO_FORCE)) {
4932 switch (adapter->link_speed) {
4933 case SPEED_10:
4934 case SPEED_100:
44defeb3 4935 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 4936 netdev->features &= ~NETIF_F_TSO;
4937 netdev->features &= ~NETIF_F_TSO6;
4938 break;
4939 case SPEED_1000:
4940 netdev->features |= NETIF_F_TSO;
4941 netdev->features |= NETIF_F_TSO6;
4942 break;
4943 default:
4944 /* oops */
4945 break;
4946 }
4947 }
4948
e921eb1a 4949 /* enable transmits in the hardware, need to do this
ad68076e
BA		 4950 * after setting TARC(0)
4951 */
bc7f75fa
AK		 4952 tctl = er32(TCTL);
4953 tctl |= E1000_TCTL_EN;
4954 ew32(TCTL, tctl);
4955
e921eb1a 4956 /* Perform any post-link-up configuration before
75eb0fad
BA		 4957 * reporting link up.
4958 */
4959 if (phy->ops.cfg_on_link_up)
4960 phy->ops.cfg_on_link_up(hw);
4961
bc7f75fa 4962 netif_carrier_on(netdev);
bc7f75fa
AK		 4963
4964 if (!test_bit(__E1000_DOWN, &adapter->state))
4965 mod_timer(&adapter->phy_info_timer,
4966 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 4967 }
4968 } else {
4969 if (netif_carrier_ok(netdev)) {
4970 adapter->link_speed = 0;
4971 adapter->link_duplex = 0;
8f12fe86 4972 /* Link status message must follow this format */
7dbc1672 4973 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 4974 netif_carrier_off(netdev);
bc7f75fa
AK		 4975 if (!test_bit(__E1000_DOWN, &adapter->state))
4976 mod_timer(&adapter->phy_info_timer,
4977 round_jiffies(jiffies + 2 * HZ));
4978
d9554e96
DE		 4979 /* 8000ES2LAN requires a Rx packet buffer work-around
4980 * on link down event; reset the controller to flush
4981 * the Rx packet buffer.
12d43f7d 4982 */
d9554e96 4983 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
12d43f7d 4984 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 4985 else
4986 pm_schedule_suspend(netdev->dev.parent,
17e813ec 4987 LINK_TIMEOUT);
bc7f75fa
AK		 4988 }
4989 }
4990
4991link_up:
67fd4fcb 4992 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 4993 e1000e_update_stats(adapter);
4994
4995 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
4996 adapter->tpt_old = adapter->stats.tpt;
4997 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
4998 adapter->colc_old = adapter->stats.colc;
4999
7c25769f
BA		 5000 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5001 adapter->gorc_old = adapter->stats.gorc;
5002 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5003 adapter->gotc_old = adapter->stats.gotc;
2084b114 5004 spin_unlock(&adapter->stats64_lock);
bc7f75fa 5005
d9554e96
DE		 5006 /* If the link is lost the controller stops DMA, but
5007 * if there is queued Tx work it cannot be done. So
5008 * reset the controller to flush the Tx packet buffers.
5009 */
5010 if (!netif_carrier_ok(netdev) &&
5011 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5012 adapter->flags |= FLAG_RESTART_NOW;
5013
5014 /* If reset is necessary, do it outside of interrupt context. */
12d43f7d 5015 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 5016 schedule_work(&adapter->reset_task);
5017 /* return immediately since reset is imminent */
5018 return;
bc7f75fa
AK		 5019 }
5020
12d43f7d
BA		 5021 e1000e_update_adaptive(&adapter->hw);
5022
eab2abf5
JB		 5023 /* Simple mode for Interrupt Throttle Rate (ITR) */
5024 if (adapter->itr_setting == 4) {
e921eb1a 5025 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 5026 * Total asymmetrical Tx or Rx gets ITR=8000;
5027 * everyone else is between 2000-8000.
5028 */
5029 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5030 u32 dif = (adapter->gotc > adapter->gorc ?
17e813ec
BA		 5031 adapter->gotc - adapter->gorc :
5032 adapter->gorc - adapter->gotc) / 10000;
eab2abf5
JB		 5033 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5034
22a4cca2 5035 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 5036 }
5037
ad68076e 5038 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 5039 if (adapter->msix_entries)
5040 ew32(ICS, adapter->rx_ring->ims_val);
5041 else
5042 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 5043
713b3c9e
JB		 5044 /* flush pending descriptors to memory before detecting Tx hang */
5045 e1000e_flush_descriptors(adapter);
5046
bc7f75fa 5047 /* Force detection of hung controller every watchdog period */
3db1cd5c 5048 adapter->detect_tx_hung = true;
bc7f75fa 5049
e921eb1a 5050 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 5051 * reset from the other port. Set the appropriate LAA in RAR[0]
5052 */
bc7f75fa 5053 if (e1000e_get_laa_state_82571(hw))
69e1e019 5054 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 5055
ff10e13c
CW		 5056 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5057 e1000e_check_82574_phy_workaround(adapter);
5058
b67e1913
BA		 5059 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5060 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5061 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5062 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5063 er32(RXSTMPH);
5064 adapter->rx_hwtstamp_cleared++;
5065 } else {
5066 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5067 }
5068 }
5069
bc7f75fa
AK		 5070 /* Reset the timer */
5071 if (!test_bit(__E1000_DOWN, &adapter->state))
5072 mod_timer(&adapter->watchdog_timer,
5073 round_jiffies(jiffies + 2 * HZ));
5074}
5075
5076#define E1000_TX_FLAGS_CSUM 0x00000001
5077#define E1000_TX_FLAGS_VLAN 0x00000002
5078#define E1000_TX_FLAGS_TSO 0x00000004
5079#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5080#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5081#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5082#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5083#define E1000_TX_FLAGS_VLAN_SHIFT 16
5084
55aa6985 5085static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5086{
bc7f75fa
AK		 5087 struct e1000_context_desc *context_desc;
5088 struct e1000_buffer *buffer_info;
5089 unsigned int i;
5090 u32 cmd_length = 0;
70443ae9 5091 u16 ipcse = 0, mss;
bc7f75fa 5092 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bc7f75fa 5093
3d5e33c9
BA		 5094 if (!skb_is_gso(skb))
5095 return 0;
bc7f75fa 5096
3d5e33c9 5097 if (skb_header_cloned(skb)) {
90da0669
BA		 5098 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5099
3d5e33c9
BA		 5100 if (err)
5101 return err;
bc7f75fa
AK		 5102 }
5103
3d5e33c9
BA		 5104 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5105 mss = skb_shinfo(skb)->gso_size;
5106 if (skb->protocol == htons(ETH_P_IP)) {
5107 struct iphdr *iph = ip_hdr(skb);
5108 iph->tot_len = 0;
5109 iph->check = 0;
5110 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
f0ff4398 5111 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5112 cmd_length = E1000_TXD_CMD_IP;
5113 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5114 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 5115 ipv6_hdr(skb)->payload_len = 0;
5116 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
f0ff4398
BA		 5117 &ipv6_hdr(skb)->daddr,
5118 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5119 ipcse = 0;
5120 }
5121 ipcss = skb_network_offset(skb);
5122 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5123 tucss = skb_transport_offset(skb);
5124 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5125
5126 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
f0ff4398 5127 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
3d5e33c9
BA		 5128
5129 i = tx_ring->next_to_use;
5130 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5131 buffer_info = &tx_ring->buffer_info[i];
5132
e80bd1d1
BA		 5133 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5134 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5135 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
3d5e33c9
BA		 5136 context_desc->upper_setup.tcp_fields.tucss = tucss;
5137 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5138 context_desc->upper_setup.tcp_fields.tucse = 0;
e80bd1d1 5139 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
3d5e33c9
BA		 5140 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5141 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5142
5143 buffer_info->time_stamp = jiffies;
5144 buffer_info->next_to_watch = i;
5145
5146 i++;
5147 if (i == tx_ring->count)
5148 i = 0;
5149 tx_ring->next_to_use = i;
5150
5151 return 1;
bc7f75fa
AK		 5152}
5153
55aa6985 5154static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb)
bc7f75fa 5155{
55aa6985 5156 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5157 struct e1000_context_desc *context_desc;
5158 struct e1000_buffer *buffer_info;
5159 unsigned int i;
5160 u8 css;
af807c82 5161 u32 cmd_len = E1000_TXD_CMD_DEXT;
5f66f208 5162 __be16 protocol;
bc7f75fa 5163
af807c82
DG		 5164 if (skb->ip_summed != CHECKSUM_PARTIAL)
5165 return 0;
bc7f75fa 5166
5f66f208
AJ		 5167 if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
5168 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
5169 else
5170 protocol = skb->protocol;
5171
3f518390 5172 switch (protocol) {
09640e63 5173 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5174 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5175 cmd_len |= E1000_TXD_CMD_TCP;
5176 break;
09640e63 5177 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5178 /* XXX not handling all IPV6 headers */
5179 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5180 cmd_len |= E1000_TXD_CMD_TCP;
5181 break;
5182 default:
5183 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5184 e_warn("checksum_partial proto=%x!\n",
5185 be16_to_cpu(protocol));
af807c82 5186 break;
bc7f75fa
AK		 5187 }
5188
0d0b1672 5189 css = skb_checksum_start_offset(skb);
af807c82
DG		 5190
5191 i = tx_ring->next_to_use;
5192 buffer_info = &tx_ring->buffer_info[i];
5193 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5194
5195 context_desc->lower_setup.ip_config = 0;
5196 context_desc->upper_setup.tcp_fields.tucss = css;
f0ff4398 5197 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
af807c82
DG		 5198 context_desc->upper_setup.tcp_fields.tucse = 0;
5199 context_desc->tcp_seg_setup.data = 0;
5200 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5201
5202 buffer_info->time_stamp = jiffies;
5203 buffer_info->next_to_watch = i;
5204
5205 i++;
5206 if (i == tx_ring->count)
5207 i = 0;
5208 tx_ring->next_to_use = i;
5209
5210 return 1;
bc7f75fa
AK		 5211}
5212
55aa6985
BA		 5213static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5214 unsigned int first, unsigned int max_per_txd,
d821a4c4 5215 unsigned int nr_frags)
bc7f75fa 5216{
55aa6985 5217 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5218 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5219 struct e1000_buffer *buffer_info;
8ddc951c 5220 unsigned int len = skb_headlen(skb);
03b1320d 5221 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5222 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5223
5224 i = tx_ring->next_to_use;
5225
5226 while (len) {
1b7719c4 5227 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5228 size = min(len, max_per_txd);
5229
bc7f75fa 5230 buffer_info->length = size;
bc7f75fa 5231 buffer_info->time_stamp = jiffies;
bc7f75fa 5232 buffer_info->next_to_watch = i;
0be3f55f
NN		 5233 buffer_info->dma = dma_map_single(&pdev->dev,
5234 skb->data + offset,
af667a29 5235 size, DMA_TO_DEVICE);
03b1320d 5236 buffer_info->mapped_as_page = false;
0be3f55f 5237 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5238 goto dma_error;
bc7f75fa
AK		 5239
5240 len -= size;
5241 offset += size;
03b1320d 5242 count++;
1b7719c4
AD		 5243
5244 if (len) {
5245 i++;
5246 if (i == tx_ring->count)
5247 i = 0;
5248 }
bc7f75fa
AK		 5249 }
5250
5251 for (f = 0; f < nr_frags; f++) {
9e903e08 5252 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5253
5254 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5255 len = skb_frag_size(frag);
877749bf 5256 offset = 0;
bc7f75fa
AK		 5257
5258 while (len) {
1b7719c4
AD		 5259 i++;
5260 if (i == tx_ring->count)
5261 i = 0;
5262
bc7f75fa
AK		 5263 buffer_info = &tx_ring->buffer_info[i];
5264 size = min(len, max_per_txd);
bc7f75fa
AK		 5265
5266 buffer_info->length = size;
5267 buffer_info->time_stamp = jiffies;
bc7f75fa 5268 buffer_info->next_to_watch = i;
877749bf 5269 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
17e813ec
BA		 5270 offset, size,
5271 DMA_TO_DEVICE);
03b1320d 5272 buffer_info->mapped_as_page = true;
0be3f55f 5273 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5274 goto dma_error;
bc7f75fa
AK		 5275
5276 len -= size;
5277 offset += size;
5278 count++;
bc7f75fa
AK		 5279 }
5280 }
5281
af667a29 5282 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5283 /* multiply data chunks by size of headers */
5284 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5285
bc7f75fa 5286 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5287 tx_ring->buffer_info[i].segs = segs;
5288 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5289 tx_ring->buffer_info[first].next_to_watch = i;
5290
5291 return count;
03b1320d
AD		 5292
5293dma_error:
af667a29 5294 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5295 buffer_info->dma = 0;
c1fa347f 5296 if (count)
03b1320d 5297 count--;
c1fa347f
RK		 5298
5299 while (count--) {
af667a29 5300 if (i == 0)
03b1320d 5301 i += tx_ring->count;
c1fa347f 5302 i--;
03b1320d 5303 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5304 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5305 }
5306
5307 return 0;
bc7f75fa
AK		 5308}
5309
55aa6985 5310static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5311{
55aa6985 5312 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5313 struct e1000_tx_desc *tx_desc = NULL;
5314 struct e1000_buffer *buffer_info;
5315 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5316 unsigned int i;
5317
5318 if (tx_flags & E1000_TX_FLAGS_TSO) {
5319 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
f0ff4398 5320 E1000_TXD_CMD_TSE;
bc7f75fa
AK		 5321 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5322
5323 if (tx_flags & E1000_TX_FLAGS_IPV4)
5324 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5325 }
5326
5327 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5328 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5329 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5330 }
5331
5332 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5333 txd_lower |= E1000_TXD_CMD_VLE;
5334 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5335 }
5336
943146de
BG		 5337 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5338 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5339
b67e1913
BA		 5340 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5341 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5342 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5343 }
5344
bc7f75fa
AK		 5345 i = tx_ring->next_to_use;
5346
36b973df 5347 do {
bc7f75fa
AK		 5348 buffer_info = &tx_ring->buffer_info[i];
5349 tx_desc = E1000_TX_DESC(*tx_ring, i);
5350 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
f0ff4398
BA		 5351 tx_desc->lower.data = cpu_to_le32(txd_lower |
5352 buffer_info->length);
bc7f75fa
AK		 5353 tx_desc->upper.data = cpu_to_le32(txd_upper);
5354
5355 i++;
5356 if (i == tx_ring->count)
5357 i = 0;
36b973df 5358 } while (--count > 0);
bc7f75fa
AK		 5359
5360 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5361
943146de
BG		 5362 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5363 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5364 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5365
e921eb1a 5366 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5367 * know there are new descriptors to fetch. (Only
5368 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5369 * such as IA-64).
5370 */
bc7f75fa
AK		 5371 wmb();
5372
5373 tx_ring->next_to_use = i;
c6e7f51e
BA		 5374
5375 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 5376 e1000e_update_tdt_wa(tx_ring, i);
c6e7f51e 5377 else
c5083cf6 5378 writel(i, tx_ring->tail);
c6e7f51e 5379
e921eb1a 5380 /* we need this if more than one processor can write to our tail
ad68076e
BA		 5381 * at a time, it synchronizes IO on IA64/Altix systems
5382 */
bc7f75fa
AK		 5383 mmiowb();
5384}
5385
5386#define MINIMUM_DHCP_PACKET_SIZE 282
5387static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5388 struct sk_buff *skb)
5389{
e80bd1d1 5390 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 5391 u16 length, offset;
5392
d60923c4
BA		 5393 if (vlan_tx_tag_present(skb) &&
5394 !((vlan_tx_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
5395 (adapter->hw.mng_cookie.status &
5396 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5397 return 0;
bc7f75fa
AK		 5398
5399 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5400 return 0;
5401
53aa82da 5402 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
bc7f75fa
AK		 5403 return 0;
5404
5405 {
362e20ca 5406 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
bc7f75fa
AK		 5407 struct udphdr *udp;
5408
5409 if (ip->protocol != IPPROTO_UDP)
5410 return 0;
5411
5412 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5413 if (ntohs(udp->dest) != 67)
5414 return 0;
5415
5416 offset = (u8 *)udp + 8 - skb->data;
5417 length = skb->len - offset;
5418 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5419 }
5420
5421 return 0;
5422}
5423
55aa6985 5424static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5425{
55aa6985 5426 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5427
55aa6985 5428 netif_stop_queue(adapter->netdev);
e921eb1a 5429 /* Herbert's original patch had:
bc7f75fa 5430 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5431 * but since that doesn't exist yet, just open code it.
5432 */
bc7f75fa
AK		 5433 smp_mb();
5434
e921eb1a 5435 /* We need to check again in a case another CPU has just
ad68076e
BA		 5436 * made room available.
5437 */
55aa6985 5438 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5439 return -EBUSY;
5440
5441 /* A reprieve! */
55aa6985 5442 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5443 ++adapter->restart_queue;
5444 return 0;
5445}
5446
55aa6985 5447static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5448{
d821a4c4
BA		 5449 BUG_ON(size > tx_ring->count);
5450
55aa6985 5451 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5452 return 0;
55aa6985 5453 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5454}
5455
3b29a56d
SH		 5456static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5457 struct net_device *netdev)
bc7f75fa
AK		 5458{
5459 struct e1000_adapter *adapter = netdev_priv(netdev);
5460 struct e1000_ring *tx_ring = adapter->tx_ring;
5461 unsigned int first;
bc7f75fa 5462 unsigned int tx_flags = 0;
e743d313 5463 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5464 unsigned int nr_frags;
5465 unsigned int mss;
bc7f75fa
AK		 5466 int count = 0;
5467 int tso;
5468 unsigned int f;
bc7f75fa
AK		 5469
5470 if (test_bit(__E1000_DOWN, &adapter->state)) {
5471 dev_kfree_skb_any(skb);
5472 return NETDEV_TX_OK;
5473 }
5474
5475 if (skb->len <= 0) {
5476 dev_kfree_skb_any(skb);
5477 return NETDEV_TX_OK;
5478 }
5479
e921eb1a 5480 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5481 * pad skb in order to meet this minimum size requirement
5482 */
5483 if (unlikely(skb->len < 17)) {
5484 if (skb_pad(skb, 17 - skb->len))
5485 return NETDEV_TX_OK;
5486 skb->len = 17;
5487 skb_set_tail_pointer(skb, 17);
5488 }
5489
bc7f75fa 5490 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5491 if (mss) {
5492 u8 hdr_len;
bc7f75fa 5493
e921eb1a 5494 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5495 * points to just header, pull a few bytes of payload from
5496 * frags into skb->data
5497 */
bc7f75fa 5498 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5499 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5500 * avoiding it could save a lot of cycles
5501 */
4e6c709c 5502 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5503 unsigned int pull_size;
5504
a2a5b323 5505 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5506 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5507 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5508 dev_kfree_skb_any(skb);
5509 return NETDEV_TX_OK;
5510 }
e743d313 5511 len = skb_headlen(skb);
bc7f75fa
AK		 5512 }
5513 }
5514
5515 /* reserve a descriptor for the offload context */
5516 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5517 count++;
5518 count++;
5519
d821a4c4 5520 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5521
5522 nr_frags = skb_shinfo(skb)->nr_frags;
5523 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5524 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5525 adapter->tx_fifo_limit);
bc7f75fa
AK		 5526
5527 if (adapter->hw.mac.tx_pkt_filtering)
5528 e1000_transfer_dhcp_info(adapter, skb);
5529
e921eb1a 5530 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5531 * head, otherwise try next time
5532 */
55aa6985 5533 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5534 return NETDEV_TX_BUSY;
bc7f75fa 5535
eab6d18d 5536 if (vlan_tx_tag_present(skb)) {
bc7f75fa
AK		 5537 tx_flags |= E1000_TX_FLAGS_VLAN;
5538 tx_flags |= (vlan_tx_tag_get(skb) << E1000_TX_FLAGS_VLAN_SHIFT);
5539 }
5540
5541 first = tx_ring->next_to_use;
5542
55aa6985 5543 tso = e1000_tso(tx_ring, skb);
bc7f75fa
AK		 5544 if (tso < 0) {
5545 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5546 return NETDEV_TX_OK;
5547 }
5548
5549 if (tso)
5550 tx_flags |= E1000_TX_FLAGS_TSO;
55aa6985 5551 else if (e1000_tx_csum(tx_ring, skb))
bc7f75fa
AK		 5552 tx_flags |= E1000_TX_FLAGS_CSUM;
5553
e921eb1a 5554 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5555 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5556 * no longer assume, we must.
5557 */
bc7f75fa
AK		 5558 if (skb->protocol == htons(ETH_P_IP))
5559 tx_flags |= E1000_TX_FLAGS_IPV4;
5560
943146de
BG		 5561 if (unlikely(skb->no_fcs))
5562 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5563
25985edc 5564 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5565 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5566 nr_frags);
1b7719c4 5567 if (count) {
b67e1913
BA		 5568 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5569 !adapter->tx_hwtstamp_skb)) {
5570 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5571 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5572 adapter->tx_hwtstamp_skb = skb_get(skb);
59c871c5 5573 adapter->tx_hwtstamp_start = jiffies;
b67e1913
BA		 5574 schedule_work(&adapter->tx_hwtstamp_work);
5575 } else {
5576 skb_tx_timestamp(skb);
5577 }
80be3129 5578
3f0cfa3b 5579 netdev_sent_queue(netdev, skb->len);
55aa6985 5580 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5581 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5582 e1000_maybe_stop_tx(tx_ring,
5583 (MAX_SKB_FRAGS *
5584 DIV_ROUND_UP(PAGE_SIZE,
5585 adapter->tx_fifo_limit) + 2));
1b7719c4 5586 } else {
bc7f75fa 5587 dev_kfree_skb_any(skb);
1b7719c4
AD		 5588 tx_ring->buffer_info[first].time_stamp = 0;
5589 tx_ring->next_to_use = first;
bc7f75fa
AK		 5590 }
5591
bc7f75fa
AK		 5592 return NETDEV_TX_OK;
5593}
5594
5595/**
5596 * e1000_tx_timeout - Respond to a Tx Hang
5597 * @netdev: network interface device structure
5598 **/
5599static void e1000_tx_timeout(struct net_device *netdev)
5600{
5601 struct e1000_adapter *adapter = netdev_priv(netdev);
5602
5603 /* Do the reset outside of interrupt context */
5604 adapter->tx_timeout_count++;
5605 schedule_work(&adapter->reset_task);
5606}
5607
5608static void e1000_reset_task(struct work_struct *work)
5609{
5610 struct e1000_adapter *adapter;
5611 adapter = container_of(work, struct e1000_adapter, reset_task);
5612
615b32af
JB		 5613 /* don't run the task if already down */
5614 if (test_bit(__E1000_DOWN, &adapter->state))
5615 return;
5616
12d43f7d 5617 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5618 e1000e_dump(adapter);
12d43f7d 5619 e_err("Reset adapter unexpectedly\n");
affa9dfb 5620 }
bc7f75fa
AK		 5621 e1000e_reinit_locked(adapter);
5622}
5623
5624/**
67fd4fcb 5625 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5626 * @netdev: network interface device structure
67fd4fcb 5627 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5628 *
5629 * Returns the address of the device statistics structure.
bc7f75fa 5630 **/
67fd4fcb 5631struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
66501f56 5632 struct rtnl_link_stats64 *stats)
bc7f75fa 5633{
67fd4fcb
JK		 5634 struct e1000_adapter *adapter = netdev_priv(netdev);
5635
5636 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5637 spin_lock(&adapter->stats64_lock);
5638 e1000e_update_stats(adapter);
5639 /* Fill out the OS statistics structure */
5640 stats->rx_bytes = adapter->stats.gorc;
5641 stats->rx_packets = adapter->stats.gprc;
5642 stats->tx_bytes = adapter->stats.gotc;
5643 stats->tx_packets = adapter->stats.gptc;
5644 stats->multicast = adapter->stats.mprc;
5645 stats->collisions = adapter->stats.colc;
5646
5647 /* Rx Errors */
5648
e921eb1a 5649 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5650 * our own version based on RUC and ROC
5651 */
5652 stats->rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 5653 adapter->stats.crcerrs + adapter->stats.algnerrc +
5654 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5655 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
67fd4fcb
JK		 5656 stats->rx_crc_errors = adapter->stats.crcerrs;
5657 stats->rx_frame_errors = adapter->stats.algnerrc;
5658 stats->rx_missed_errors = adapter->stats.mpc;
5659
5660 /* Tx Errors */
f0ff4398 5661 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
67fd4fcb
JK		 5662 stats->tx_aborted_errors = adapter->stats.ecol;
5663 stats->tx_window_errors = adapter->stats.latecol;
5664 stats->tx_carrier_errors = adapter->stats.tncrs;
5665
5666 /* Tx Dropped needs to be maintained elsewhere */
5667
5668 spin_unlock(&adapter->stats64_lock);
5669 return stats;
bc7f75fa
AK		 5670}
5671
5672/**
5673 * e1000_change_mtu - Change the Maximum Transfer Unit
5674 * @netdev: network interface device structure
5675 * @new_mtu: new value for maximum frame size
5676 *
5677 * Returns 0 on success, negative on failure
5678 **/
5679static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5680{
5681 struct e1000_adapter *adapter = netdev_priv(netdev);
5682 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5683
2adc55c9 5684 /* Jumbo frame support */
2e1706f2
BA		 5685 if ((max_frame > ETH_FRAME_LEN + ETH_FCS_LEN) &&
5686 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5687 e_err("Jumbo Frames not supported.\n");
5688 return -EINVAL;
bc7f75fa
AK		 5689 }
5690
2adc55c9
BA		 5691 /* Supported frame sizes */
5692 if ((new_mtu < ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN) ||
5693 (max_frame > adapter->max_hw_frame_size)) {
5694 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5695 return -EINVAL;
5696 }
5697
2fbe4526
BA		 5698 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5699 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5700 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5701 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5702 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5703 return -EINVAL;
5704 }
5705
bc7f75fa 5706 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5707 usleep_range(1000, 2000);
610c9928 5708 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5709 adapter->max_frame_size = max_frame;
610c9928
BA		 5710 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5711 netdev->mtu = new_mtu;
63eb48f1
DE		 5712
5713 pm_runtime_get_sync(netdev->dev.parent);
5714
bc7f75fa 5715 if (netif_running(netdev))
28002099 5716 e1000e_down(adapter, true);
bc7f75fa 5717
e921eb1a 5718 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5719 * means we reserve 2 more, this pushes us to allocate from the next
5720 * larger slab size.
ad68076e 5721 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 5722 * However with the new *_jumbo_rx* routines, jumbo receives will use
5723 * fragmented skbs
ad68076e 5724 */
bc7f75fa 5725
9926146b 5726 if (max_frame <= 2048)
bc7f75fa
AK		 5727 adapter->rx_buffer_len = 2048;
5728 else
5729 adapter->rx_buffer_len = 4096;
5730
5731 /* adjust allocation if LPE protects us, and we aren't using SBP */
5732 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
17e813ec 5733 (max_frame == ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN))
bc7f75fa 5734 adapter->rx_buffer_len = ETH_FRAME_LEN + VLAN_HLEN
17e813ec 5735 + ETH_FCS_LEN;
bc7f75fa 5736
bc7f75fa
AK		 5737 if (netif_running(netdev))
5738 e1000e_up(adapter);
5739 else
5740 e1000e_reset(adapter);
5741
63eb48f1
DE		 5742 pm_runtime_put_sync(netdev->dev.parent);
5743
bc7f75fa
AK		 5744 clear_bit(__E1000_RESETTING, &adapter->state);
5745
5746 return 0;
5747}
5748
5749static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
5750 int cmd)
5751{
5752 struct e1000_adapter *adapter = netdev_priv(netdev);
5753 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 5754
318a94d6 5755 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 5756 return -EOPNOTSUPP;
5757
5758 switch (cmd) {
5759 case SIOCGMIIPHY:
5760 data->phy_id = adapter->hw.phy.addr;
5761 break;
5762 case SIOCGMIIREG:
b16a002e
BA		 5763 e1000_phy_read_status(adapter);
5764
7c25769f
BA		 5765 switch (data->reg_num & 0x1F) {
5766 case MII_BMCR:
5767 data->val_out = adapter->phy_regs.bmcr;
5768 break;
5769 case MII_BMSR:
5770 data->val_out = adapter->phy_regs.bmsr;
5771 break;
5772 case MII_PHYSID1:
5773 data->val_out = (adapter->hw.phy.id >> 16);
5774 break;
5775 case MII_PHYSID2:
5776 data->val_out = (adapter->hw.phy.id & 0xFFFF);
5777 break;
5778 case MII_ADVERTISE:
5779 data->val_out = adapter->phy_regs.advertise;
5780 break;
5781 case MII_LPA:
5782 data->val_out = adapter->phy_regs.lpa;
5783 break;
5784 case MII_EXPANSION:
5785 data->val_out = adapter->phy_regs.expansion;
5786 break;
5787 case MII_CTRL1000:
5788 data->val_out = adapter->phy_regs.ctrl1000;
5789 break;
5790 case MII_STAT1000:
5791 data->val_out = adapter->phy_regs.stat1000;
5792 break;
5793 case MII_ESTATUS:
5794 data->val_out = adapter->phy_regs.estatus;
5795 break;
5796 default:
bc7f75fa
AK		 5797 return -EIO;
5798 }
bc7f75fa
AK		 5799 break;
5800 case SIOCSMIIREG:
5801 default:
5802 return -EOPNOTSUPP;
5803 }
5804 return 0;
5805}
5806
b67e1913
BA		 5807/**
5808 * e1000e_hwtstamp_ioctl - control hardware time stamping
5809 * @netdev: network interface device structure
5810 * @ifreq: interface request
5811 *
5812 * Outgoing time stamping can be enabled and disabled. Play nice and
5813 * disable it when requested, although it shouldn't cause any overhead
5814 * when no packet needs it. At most one packet in the queue may be
5815 * marked for time stamping, otherwise it would be impossible to tell
5816 * for sure to which packet the hardware time stamp belongs.
5817 *
5818 * Incoming time stamping has to be configured via the hardware filters.
5819 * Not all combinations are supported, in particular event type has to be
5820 * specified. Matching the kind of event packet is not supported, with the
5821 * exception of "all V2 events regardless of level 2 or 4".
5822 **/
4e8cff64 5823static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
b67e1913
BA		 5824{
5825 struct e1000_adapter *adapter = netdev_priv(netdev);
5826 struct hwtstamp_config config;
5827 int ret_val;
5828
5829 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
5830 return -EFAULT;
5831
62d7e3a2 5832 ret_val = e1000e_config_hwtstamp(adapter, &config);
b67e1913
BA		 5833 if (ret_val)
5834 return ret_val;
5835
d89777bf
BA		 5836 switch (config.rx_filter) {
5837 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
5838 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
5839 case HWTSTAMP_FILTER_PTP_V2_SYNC:
5840 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
5841 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
5842 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
5843 /* With V2 type filters which specify a Sync or Delay Request,
5844 * Path Delay Request/Response messages are also time stamped
5845 * by hardware so notify the caller the requested packets plus
5846 * some others are time stamped.
5847 */
5848 config.rx_filter = HWTSTAMP_FILTER_SOME;
5849 break;
5850 default:
5851 break;
5852 }
5853
b67e1913
BA		 5854 return copy_to_user(ifr->ifr_data, &config,
5855 sizeof(config)) ? -EFAULT : 0;
5856}
5857
4e8cff64
BH		 5858static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
5859{
5860 struct e1000_adapter *adapter = netdev_priv(netdev);
5861
5862 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
5863 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
5864}
5865
bc7f75fa
AK		 5866static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
5867{
5868 switch (cmd) {
5869 case SIOCGMIIPHY:
5870 case SIOCGMIIREG:
5871 case SIOCSMIIREG:
5872 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913 5873 case SIOCSHWTSTAMP:
4e8cff64
BH		 5874 return e1000e_hwtstamp_set(netdev, ifr);
5875 case SIOCGHWTSTAMP:
5876 return e1000e_hwtstamp_get(netdev, ifr);
bc7f75fa
AK		 5877 default:
5878 return -EOPNOTSUPP;
5879 }
5880}
5881
a4f58f54
BA		 5882static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
5883{
5884 struct e1000_hw *hw = &adapter->hw;
74f350ee 5885 u32 i, mac_reg, wuc;
2b6b168d 5886 u16 phy_reg, wuc_enable;
70806a7f 5887 int retval;
a4f58f54
BA		 5888
5889 /* copy MAC RARs to PHY RARs */
d3738bb8 5890 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 5891
2b6b168d
BA		 5892 retval = hw->phy.ops.acquire(hw);
5893 if (retval) {
5894 e_err("Could not acquire PHY\n");
5895 return retval;
5896 }
5897
5898 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
5899 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
5900 if (retval)
75ce1532 5901 goto release;
2b6b168d
BA		 5902
5903 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 5904 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
5905 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 5906 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
5907 (u16)(mac_reg & 0xFFFF));
5908 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
5909 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 5910 }
5911
5912 /* configure PHY Rx Control register */
2b6b168d 5913 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 5914 mac_reg = er32(RCTL);
5915 if (mac_reg & E1000_RCTL_UPE)
5916 phy_reg |= BM_RCTL_UPE;
5917 if (mac_reg & E1000_RCTL_MPE)
5918 phy_reg |= BM_RCTL_MPE;
5919 phy_reg &= ~(BM_RCTL_MO_MASK);
5920 if (mac_reg & E1000_RCTL_MO_3)
5921 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
17e813ec 5922 << BM_RCTL_MO_SHIFT);
a4f58f54
BA		 5923 if (mac_reg & E1000_RCTL_BAM)
5924 phy_reg |= BM_RCTL_BAM;
5925 if (mac_reg & E1000_RCTL_PMCF)
5926 phy_reg |= BM_RCTL_PMCF;
5927 mac_reg = er32(CTRL);
5928 if (mac_reg & E1000_CTRL_RFCE)
5929 phy_reg |= BM_RCTL_RFCE;
2b6b168d 5930 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54 5931
74f350ee
DE		 5932 wuc = E1000_WUC_PME_EN;
5933 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
5934 wuc |= E1000_WUC_APME;
5935
a4f58f54
BA		 5936 /* enable PHY wakeup in MAC register */
5937 ew32(WUFC, wufc);
74f350ee
DE		 5938 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
5939 E1000_WUC_PME_STATUS | wuc));
a4f58f54
BA		 5940
5941 /* configure and enable PHY wakeup in PHY registers */
2b6b168d 5942 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
74f350ee 5943 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
a4f58f54
BA		 5944
5945 /* activate PHY wakeup */
2b6b168d
BA		 5946 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
5947 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 5948 if (retval)
5949 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 5950release:
94d8186a 5951 hw->phy.ops.release(hw);
a4f58f54
BA		 5952
5953 return retval;
5954}
5955
28002099 5956static int e1000e_pm_freeze(struct device *dev)
bc7f75fa 5957{
28002099 5958 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
bc7f75fa 5959 struct e1000_adapter *adapter = netdev_priv(netdev);
bc7f75fa
AK		 5960
5961 netif_device_detach(netdev);
5962
5963 if (netif_running(netdev)) {
bb9e44d0
BA		 5964 int count = E1000_CHECK_RESET_COUNT;
5965
5966 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
5967 usleep_range(10000, 20000);
5968
bc7f75fa 5969 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
28002099
DE		 5970
5971 /* Quiesce the device without resetting the hardware */
5972 e1000e_down(adapter, false);
bc7f75fa
AK		 5973 e1000_free_irq(adapter);
5974 }
4662e82b 5975 e1000e_reset_interrupt_capability(adapter);
bc7f75fa 5976
28002099
DE		 5977 /* Allow time for pending master requests to run */
5978 e1000e_disable_pcie_master(&adapter->hw);
5979
5980 return 0;
5981}
5982
5983static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
5984{
5985 struct net_device *netdev = pci_get_drvdata(pdev);
5986 struct e1000_adapter *adapter = netdev_priv(netdev);
5987 struct e1000_hw *hw = &adapter->hw;
5988 u32 ctrl, ctrl_ext, rctl, status;
5989 /* Runtime suspend should only enable wakeup for link changes */
5990 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
5991 int retval = 0;
5992
bc7f75fa
AK		 5993 status = er32(STATUS);
5994 if (status & E1000_STATUS_LU)
5995 wufc &= ~E1000_WUFC_LNKC;
5996
5997 if (wufc) {
5998 e1000_setup_rctl(adapter);
ef9b965a 5999 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 6000
6001 /* turn on all-multi mode if wake on multicast is enabled */
6002 if (wufc & E1000_WUFC_MC) {
6003 rctl = er32(RCTL);
6004 rctl |= E1000_RCTL_MPE;
6005 ew32(RCTL, rctl);
6006 }
6007
6008 ctrl = er32(CTRL);
a4f58f54
BA		 6009 ctrl |= E1000_CTRL_ADVD3WUC;
6010 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6011 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 6012 ew32(CTRL, ctrl);
6013
318a94d6
JK		 6014 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6015 adapter->hw.phy.media_type ==
6016 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 6017 /* keep the laser running in D3 */
6018 ctrl_ext = er32(CTRL_EXT);
93a23f48 6019 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 6020 ew32(CTRL_EXT, ctrl_ext);
6021 }
6022
63eb48f1
DE		 6023 if (!runtime)
6024 e1000e_power_up_phy(adapter);
6025
97ac8cae 6026 if (adapter->flags & FLAG_IS_ICH)
99730e4c 6027 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 6028
82776a4b 6029 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 6030 /* enable wakeup by the PHY */
6031 retval = e1000_init_phy_wakeup(adapter, wufc);
6032 if (retval)
6033 return retval;
6034 } else {
6035 /* enable wakeup by the MAC */
6036 ew32(WUFC, wufc);
6037 ew32(WUC, E1000_WUC_PME_EN);
6038 }
bc7f75fa
AK		 6039 } else {
6040 ew32(WUC, 0);
6041 ew32(WUFC, 0);
28002099
DE		 6042
6043 e1000_power_down_phy(adapter);
bc7f75fa
AK		 6044 }
6045
74f350ee 6046 if (adapter->hw.phy.type == e1000_phy_igp_3) {
bc7f75fa 6047 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
74f350ee
DE		 6048 } else if (hw->mac.type == e1000_pch_lpt) {
6049 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6050 /* ULP does not support wake from unicast, multicast
6051 * or broadcast.
6052 */
6053 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6054
6055 if (retval)
6056 return retval;
6057 }
6058
bc7f75fa 6059
e921eb1a 6060 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6061 * would have already happened in close and is redundant.
6062 */
31dbe5b4 6063 e1000e_release_hw_control(adapter);
bc7f75fa 6064
24b41c97
DN		 6065 pci_clear_master(pdev);
6066
e921eb1a 6067 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 6068 * correctable error when the MAC transitions from D0 to D3. To
6069 * prevent this we need to mask off the correctable errors on the
6070 * downstream port of the pci-e switch.
e8c254c5
LZ		 6071 *
6072 * We don't have the associated upstream bridge while assigning
6073 * the PCI device into guest. For example, the KVM on power is
6074 * one of the cases.
005cbdfc
AD		 6075 */
6076 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6077 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 6078 u16 devctl;
6079
e8c254c5
LZ		 6080 if (!us_dev)
6081 return 0;
6082
f8c0fcac
JL		 6083 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6084 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6085 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6086
66148bab
KK		 6087 pci_save_state(pdev);
6088 pci_prepare_to_sleep(pdev);
005cbdfc 6089
f8c0fcac 6090 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6091 }
66148bab
KK		 6092
6093 return 0;
bc7f75fa
AK		 6094}
6095
13129d9b
CW		 6096/**
6097 * e1000e_disable_aspm - Disable ASPM states
6098 * @pdev: pointer to PCI device struct
6099 * @state: bit-mask of ASPM states to disable
6100 *
6101 * Some devices *must* have certain ASPM states disabled per hardware errata.
6102 **/
6103static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6f461f6c 6104{
13129d9b
CW		 6105 struct pci_dev *parent = pdev->bus->self;
6106 u16 aspm_dis_mask = 0;
6107 u16 pdev_aspmc, parent_aspmc;
6108
6109 switch (state) {
6110 case PCIE_LINK_STATE_L0S:
6111 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6112 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6113 /* fall-through - can't have L1 without L0s */
6114 case PCIE_LINK_STATE_L1:
6115 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6116 break;
6117 default:
6118 return;
6119 }
6120
6121 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6122 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6123
6124 if (parent) {
6125 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6126 &parent_aspmc);
6127 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6128 }
6129
6130 /* Nothing to do if the ASPM states to be disabled already are */
6131 if (!(pdev_aspmc & aspm_dis_mask) &&
6132 (!parent || !(parent_aspmc & aspm_dis_mask)))
6133 return;
6134
6135 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6136 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6137 "L0s" : "",
6138 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6139 "L1" : "");
6140
6141#ifdef CONFIG_PCIEASPM
9f728f53 6142 pci_disable_link_state_locked(pdev, state);
ffe0b2ff 6143
13129d9b
CW		 6144 /* Double-check ASPM control. If not disabled by the above, the
6145 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6146 * not enabled); override by writing PCI config space directly.
6147 */
6148 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6149 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6150
6151 if (!(aspm_dis_mask & pdev_aspmc))
6152 return;
6153#endif
ffe0b2ff 6154
e921eb1a 6155 /* Both device and parent should have the same ASPM setting.
6f461f6c 6156 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6157 */
13129d9b 6158 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6f461f6c 6159
13129d9b
CW		 6160 if (parent)
6161 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6162 aspm_dis_mask);
1eae4eb2
AK		 6163}
6164
aa338601 6165#ifdef CONFIG_PM
23606cf5 6166static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6167{
6168 struct net_device *netdev = pci_get_drvdata(pdev);
6169 struct e1000_adapter *adapter = netdev_priv(netdev);
6170 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6171 u16 aspm_disable_flag = 0;
bc7f75fa 6172
78cd29d5
BA		 6173 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6174 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6175 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6176 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6177 if (aspm_disable_flag)
6178 e1000e_disable_aspm(pdev, aspm_disable_flag);
6179
66148bab 6180 pci_set_master(pdev);
6e4f6f6b 6181
2fbe4526 6182 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6183 e1000_resume_workarounds_pchlan(&adapter->hw);
6184
bc7f75fa 6185 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6186
6187 /* report the system wakeup cause from S3/S4 */
6188 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6189 u16 phy_data;
6190
6191 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6192 if (phy_data) {
6193 e_info("PHY Wakeup cause - %s\n",
17e813ec
BA		 6194 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6195 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6196 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6197 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6198 phy_data & E1000_WUS_LNKC ?
6199 "Link Status Change" : "other");
a4f58f54
BA		 6200 }
6201 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6202 } else {
6203 u32 wus = er32(WUS);
6204 if (wus) {
6205 e_info("MAC Wakeup cause - %s\n",
17e813ec
BA		 6206 wus & E1000_WUS_EX ? "Unicast Packet" :
6207 wus & E1000_WUS_MC ? "Multicast Packet" :
6208 wus & E1000_WUS_BC ? "Broadcast Packet" :
6209 wus & E1000_WUS_MAG ? "Magic Packet" :
6210 wus & E1000_WUS_LNKC ? "Link Status Change" :
6211 "other");
a4f58f54
BA		 6212 }
6213 ew32(WUS, ~0);
6214 }
6215
bc7f75fa 6216 e1000e_reset(adapter);
bc7f75fa 6217
cd791618 6218 e1000_init_manageability_pt(adapter);
bc7f75fa 6219
e921eb1a 6220 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6221 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6222 * under the control of the driver.
6223 */
c43bc57e 6224 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6225 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6226
6227 return 0;
6228}
23606cf5 6229
28002099
DE		 6230static int e1000e_pm_thaw(struct device *dev)
6231{
6232 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6233 struct e1000_adapter *adapter = netdev_priv(netdev);
6234
6235 e1000e_set_interrupt_capability(adapter);
6236 if (netif_running(netdev)) {
6237 u32 err = e1000_request_irq(adapter);
6238
6239 if (err)
6240 return err;
6241
6242 e1000e_up(adapter);
6243 }
6244
6245 netif_device_attach(netdev);
6246
6247 return 0;
6248}
6249
38a529b5 6250#ifdef CONFIG_PM_SLEEP
28002099 6251static int e1000e_pm_suspend(struct device *dev)
a0340162
RW		 6252{
6253 struct pci_dev *pdev = to_pci_dev(dev);
a0340162 6254
28002099
DE		 6255 e1000e_pm_freeze(dev);
6256
66148bab 6257 return __e1000_shutdown(pdev, false);
a0340162
RW		 6258}
6259
28002099 6260static int e1000e_pm_resume(struct device *dev)
23606cf5
RW		 6261{
6262 struct pci_dev *pdev = to_pci_dev(dev);
28002099 6263 int rc;
23606cf5 6264
28002099
DE		 6265 rc = __e1000_resume(pdev);
6266 if (rc)
6267 return rc;
23606cf5 6268
28002099 6269 return e1000e_pm_thaw(dev);
23606cf5 6270}
38a529b5 6271#endif /* CONFIG_PM_SLEEP */
a0340162
RW		 6272
6273#ifdef CONFIG_PM_RUNTIME
63eb48f1 6274static int e1000e_pm_runtime_idle(struct device *dev)
a0340162
RW		 6275{
6276 struct pci_dev *pdev = to_pci_dev(dev);
6277 struct net_device *netdev = pci_get_drvdata(pdev);
6278 struct e1000_adapter *adapter = netdev_priv(netdev);
6279
63eb48f1
DE		 6280 if (!e1000e_has_link(adapter))
6281 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
a0340162 6282
63eb48f1 6283 return -EBUSY;
a0340162
RW		 6284}
6285
63eb48f1 6286static int e1000e_pm_runtime_resume(struct device *dev)
a0340162
RW		 6287{
6288 struct pci_dev *pdev = to_pci_dev(dev);
6289 struct net_device *netdev = pci_get_drvdata(pdev);
6290 struct e1000_adapter *adapter = netdev_priv(netdev);
63eb48f1 6291 int rc;
a0340162 6292
63eb48f1
DE		 6293 rc = __e1000_resume(pdev);
6294 if (rc)
6295 return rc;
a0340162 6296
63eb48f1
DE		 6297 if (netdev->flags & IFF_UP)
6298 rc = e1000e_up(adapter);
a0340162 6299
63eb48f1 6300 return rc;
a0340162 6301}
23606cf5 6302
63eb48f1 6303static int e1000e_pm_runtime_suspend(struct device *dev)
23606cf5
RW		 6304{
6305 struct pci_dev *pdev = to_pci_dev(dev);
6306 struct net_device *netdev = pci_get_drvdata(pdev);
6307 struct e1000_adapter *adapter = netdev_priv(netdev);
6308
63eb48f1
DE		 6309 if (netdev->flags & IFF_UP) {
6310 int count = E1000_CHECK_RESET_COUNT;
6311
6312 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6313 usleep_range(10000, 20000);
23606cf5 6314
63eb48f1
DE		 6315 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6316
6317 /* Down the device without resetting the hardware */
6318 e1000e_down(adapter, false);
6319 }
6320
6321 if (__e1000_shutdown(pdev, true)) {
6322 e1000e_pm_runtime_resume(dev);
6323 return -EBUSY;
6324 }
6325
6326 return 0;
23606cf5 6327}
a0340162 6328#endif /* CONFIG_PM_RUNTIME */
aa338601 6329#endif /* CONFIG_PM */
bc7f75fa
AK		 6330
6331static void e1000_shutdown(struct pci_dev *pdev)
6332{
28002099
DE		 6333 e1000e_pm_freeze(&pdev->dev);
6334
66148bab 6335 __e1000_shutdown(pdev, false);
bc7f75fa
AK		 6336}
6337
6338#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c 6339
8bb62869 6340static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
147b2c8c
DD		 6341{
6342 struct net_device *netdev = data;
6343 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6344
6345 if (adapter->msix_entries) {
90da0669
BA		 6346 int vector, msix_irq;
6347
147b2c8c
DD		 6348 vector = 0;
6349 msix_irq = adapter->msix_entries[vector].vector;
6350 disable_irq(msix_irq);
6351 e1000_intr_msix_rx(msix_irq, netdev);
6352 enable_irq(msix_irq);
6353
6354 vector++;
6355 msix_irq = adapter->msix_entries[vector].vector;
6356 disable_irq(msix_irq);
6357 e1000_intr_msix_tx(msix_irq, netdev);
6358 enable_irq(msix_irq);
6359
6360 vector++;
6361 msix_irq = adapter->msix_entries[vector].vector;
6362 disable_irq(msix_irq);
6363 e1000_msix_other(msix_irq, netdev);
6364 enable_irq(msix_irq);
6365 }
6366
6367 return IRQ_HANDLED;
6368}
6369
e921eb1a
BA		 6370/**
6371 * e1000_netpoll
6372 * @netdev: network interface device structure
6373 *
bc7f75fa
AK		 6374 * Polling 'interrupt' - used by things like netconsole to send skbs
6375 * without having to re-enable interrupts. It's not called while
6376 * the interrupt routine is executing.
6377 */
6378static void e1000_netpoll(struct net_device *netdev)
6379{
6380 struct e1000_adapter *adapter = netdev_priv(netdev);
6381
147b2c8c
DD		 6382 switch (adapter->int_mode) {
6383 case E1000E_INT_MODE_MSIX:
6384 e1000_intr_msix(adapter->pdev->irq, netdev);
6385 break;
6386 case E1000E_INT_MODE_MSI:
6387 disable_irq(adapter->pdev->irq);
6388 e1000_intr_msi(adapter->pdev->irq, netdev);
6389 enable_irq(adapter->pdev->irq);
6390 break;
e80bd1d1 6391 default: /* E1000E_INT_MODE_LEGACY */
147b2c8c
DD		 6392 disable_irq(adapter->pdev->irq);
6393 e1000_intr(adapter->pdev->irq, netdev);
6394 enable_irq(adapter->pdev->irq);
6395 break;
6396 }
bc7f75fa
AK		 6397}
6398#endif
6399
6400/**
6401 * e1000_io_error_detected - called when PCI error is detected
6402 * @pdev: Pointer to PCI device
6403 * @state: The current pci connection state
6404 *
6405 * This function is called after a PCI bus error affecting
6406 * this device has been detected.
6407 */
6408static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6409 pci_channel_state_t state)
6410{
6411 struct net_device *netdev = pci_get_drvdata(pdev);
6412 struct e1000_adapter *adapter = netdev_priv(netdev);
6413
6414 netif_device_detach(netdev);
6415
c93b5a76
MM		 6416 if (state == pci_channel_io_perm_failure)
6417 return PCI_ERS_RESULT_DISCONNECT;
6418
bc7f75fa 6419 if (netif_running(netdev))
28002099 6420 e1000e_down(adapter, true);
bc7f75fa
AK		 6421 pci_disable_device(pdev);
6422
6423 /* Request a slot slot reset. */
6424 return PCI_ERS_RESULT_NEED_RESET;
6425}
6426
6427/**
6428 * e1000_io_slot_reset - called after the pci bus has been reset.
6429 * @pdev: Pointer to PCI device
6430 *
6431 * Restart the card from scratch, as if from a cold-boot. Implementation
28002099 6432 * resembles the first-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6433 */
6434static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6435{
6436 struct net_device *netdev = pci_get_drvdata(pdev);
6437 struct e1000_adapter *adapter = netdev_priv(netdev);
6438 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6439 u16 aspm_disable_flag = 0;
6e4f6f6b 6440 int err;
111b9dc5 6441 pci_ers_result_t result;
bc7f75fa 6442
78cd29d5
BA		 6443 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6444 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6445 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6446 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6447 if (aspm_disable_flag)
6448 e1000e_disable_aspm(pdev, aspm_disable_flag);
6449
f0f422e5 6450 err = pci_enable_device_mem(pdev);
6e4f6f6b 6451 if (err) {
bc7f75fa
AK		 6452 dev_err(&pdev->dev,
6453 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6454 result = PCI_ERS_RESULT_DISCONNECT;
6455 } else {
23606cf5 6456 pdev->state_saved = true;
111b9dc5 6457 pci_restore_state(pdev);
66148bab 6458 pci_set_master(pdev);
bc7f75fa 6459
111b9dc5
JB		 6460 pci_enable_wake(pdev, PCI_D3hot, 0);
6461 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6462
111b9dc5
JB		 6463 e1000e_reset(adapter);
6464 ew32(WUS, ~0);
6465 result = PCI_ERS_RESULT_RECOVERED;
6466 }
bc7f75fa 6467
111b9dc5
JB		 6468 pci_cleanup_aer_uncorrect_error_status(pdev);
6469
6470 return result;
bc7f75fa
AK		 6471}
6472
6473/**
6474 * e1000_io_resume - called when traffic can start flowing again.
6475 * @pdev: Pointer to PCI device
6476 *
6477 * This callback is called when the error recovery driver tells us that
6478 * its OK to resume normal operation. Implementation resembles the
28002099 6479 * second-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6480 */
6481static void e1000_io_resume(struct pci_dev *pdev)
6482{
6483 struct net_device *netdev = pci_get_drvdata(pdev);
6484 struct e1000_adapter *adapter = netdev_priv(netdev);
6485
cd791618 6486 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 6487
6488 if (netif_running(netdev)) {
6489 if (e1000e_up(adapter)) {
6490 dev_err(&pdev->dev,
6491 "can't bring device back up after reset\n");
6492 return;
6493 }
6494 }
6495
6496 netif_device_attach(netdev);
6497
e921eb1a 6498 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6499 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6500 * under the control of the driver.
6501 */
c43bc57e 6502 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6503 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6504}
6505
6506static void e1000_print_device_info(struct e1000_adapter *adapter)
6507{
6508 struct e1000_hw *hw = &adapter->hw;
6509 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6510 u32 ret_val;
6511 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6512
6513 /* print bus type/speed/width info */
a5cc7642 6514 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6515 /* bus width */
6516 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
f0ff4398 6517 "Width x1"),
44defeb3 6518 /* MAC address */
7c510e4b 6519 netdev->dev_addr);
44defeb3
JK		 6520 e_info("Intel(R) PRO/%s Network Connection\n",
6521 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6522 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6523 E1000_PBANUM_LENGTH);
6524 if (ret_val)
f2315bf1 6525 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6526 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6527 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6528}
6529
10aa4c04
AK		 6530static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6531{
6532 struct e1000_hw *hw = &adapter->hw;
6533 int ret_val;
6534 u16 buf = 0;
6535
6536 if (hw->mac.type != e1000_82573)
6537 return;
6538
6539 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762
BA		 6540 le16_to_cpus(&buf);
6541 if (!ret_val && (!(buf & (1 << 0)))) {
10aa4c04 6542 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6543 dev_warn(&adapter->pdev->dev,
6544 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6545 }
10aa4c04
AK		 6546}
6547
c8f44aff 6548static int e1000_set_features(struct net_device *netdev,
70495a50 6549 netdev_features_t features)
dc221294
BA		 6550{
6551 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6552 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6553
6554 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6555 adapter->flags |= FLAG_TSO_FORCE;
6556
f646968f 6557 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
cf955e6c
BG		 6558 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6559 NETIF_F_RXALL)))
dc221294
BA		 6560 return 0;
6561
0184039a
BG		 6562 if (changed & NETIF_F_RXFCS) {
6563 if (features & NETIF_F_RXFCS) {
6564 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6565 } else {
6566 /* We need to take it back to defaults, which might mean
6567 * stripping is still disabled at the adapter level.
6568 */
6569 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6570 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6571 else
6572 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6573 }
6574 }
6575
70495a50
BA		 6576 netdev->features = features;
6577
dc221294
BA		 6578 if (netif_running(netdev))
6579 e1000e_reinit_locked(adapter);
6580 else
6581 e1000e_reset(adapter);
6582
6583 return 0;
6584}
6585
651c2466
SH		 6586static const struct net_device_ops e1000e_netdev_ops = {
6587 .ndo_open = e1000_open,
6588 .ndo_stop = e1000_close,
00829823 6589 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6590 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6591 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6592 .ndo_set_mac_address = e1000_set_mac,
6593 .ndo_change_mtu = e1000_change_mtu,
6594 .ndo_do_ioctl = e1000_ioctl,
6595 .ndo_tx_timeout = e1000_tx_timeout,
6596 .ndo_validate_addr = eth_validate_addr,
6597
651c2466
SH		 6598 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6599 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6600#ifdef CONFIG_NET_POLL_CONTROLLER
6601 .ndo_poll_controller = e1000_netpoll,
6602#endif
dc221294 6603 .ndo_set_features = e1000_set_features,
651c2466
SH		 6604};
6605
bc7f75fa
AK		 6606/**
6607 * e1000_probe - Device Initialization Routine
6608 * @pdev: PCI device information struct
6609 * @ent: entry in e1000_pci_tbl
6610 *
6611 * Returns 0 on success, negative on failure
6612 *
6613 * e1000_probe initializes an adapter identified by a pci_dev structure.
6614 * The OS initialization, configuring of the adapter private structure,
6615 * and a hardware reset occur.
6616 **/
1dd06ae8 6617static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 6618{
6619 struct net_device *netdev;
6620 struct e1000_adapter *adapter;
6621 struct e1000_hw *hw;
6622 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 6623 resource_size_t mmio_start, mmio_len;
6624 resource_size_t flash_start, flash_len;
bc7f75fa 6625 static int cards_found;
78cd29d5 6626 u16 aspm_disable_flag = 0;
17e813ec 6627 int bars, i, err, pci_using_dac;
bc7f75fa
AK		 6628 u16 eeprom_data = 0;
6629 u16 eeprom_apme_mask = E1000_EEPROM_APME;
6630
78cd29d5
BA		 6631 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
6632 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6633 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6634 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6635 if (aspm_disable_flag)
6636 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 6637
f0f422e5 6638 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 6639 if (err)
6640 return err;
6641
6642 pci_using_dac = 0;
718a39eb 6643 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 6644 if (!err) {
718a39eb 6645 pci_using_dac = 1;
bc7f75fa 6646 } else {
718a39eb 6647 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 6648 if (err) {
718a39eb
RK		 6649 dev_err(&pdev->dev,
6650 "No usable DMA configuration, aborting\n");
6651 goto err_dma;
bc7f75fa
AK		 6652 }
6653 }
6654
17e813ec
BA		 6655 bars = pci_select_bars(pdev, IORESOURCE_MEM);
6656 err = pci_request_selected_regions_exclusive(pdev, bars,
6657 e1000e_driver_name);
bc7f75fa
AK		 6658 if (err)
6659 goto err_pci_reg;
6660
68eac460 6661 /* AER (Advanced Error Reporting) hooks */
19d5afd4 6662 pci_enable_pcie_error_reporting(pdev);
68eac460 6663
bc7f75fa 6664 pci_set_master(pdev);
438b365a
BA		 6665 /* PCI config space info */
6666 err = pci_save_state(pdev);
6667 if (err)
6668 goto err_alloc_etherdev;
bc7f75fa
AK		 6669
6670 err = -ENOMEM;
6671 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
6672 if (!netdev)
6673 goto err_alloc_etherdev;
6674
bc7f75fa
AK		 6675 SET_NETDEV_DEV(netdev, &pdev->dev);
6676
f85e4dfa
TH		 6677 netdev->irq = pdev->irq;
6678
bc7f75fa
AK		 6679 pci_set_drvdata(pdev, netdev);
6680 adapter = netdev_priv(netdev);
6681 hw = &adapter->hw;
6682 adapter->netdev = netdev;
6683 adapter->pdev = pdev;
6684 adapter->ei = ei;
6685 adapter->pba = ei->pba;
6686 adapter->flags = ei->flags;
eb7c3adb 6687 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 6688 adapter->hw.adapter = adapter;
6689 adapter->hw.mac.type = ei->mac;
2adc55c9 6690 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 6691 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 6692
6693 mmio_start = pci_resource_start(pdev, 0);
6694 mmio_len = pci_resource_len(pdev, 0);
6695
6696 err = -EIO;
6697 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
6698 if (!adapter->hw.hw_addr)
6699 goto err_ioremap;
6700
6701 if ((adapter->flags & FLAG_HAS_FLASH) &&
6702 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
6703 flash_start = pci_resource_start(pdev, 1);
6704 flash_len = pci_resource_len(pdev, 1);
6705 adapter->hw.flash_address = ioremap(flash_start, flash_len);
6706 if (!adapter->hw.flash_address)
6707 goto err_flashmap;
6708 }
6709
d495bcb8
BA		 6710 /* Set default EEE advertisement */
6711 if (adapter->flags2 & FLAG2_HAS_EEE)
6712 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
6713
bc7f75fa 6714 /* construct the net_device struct */
e80bd1d1 6715 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 6716 e1000e_set_ethtool_ops(netdev);
e80bd1d1 6717 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 6718 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 6719 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 6720
6721 netdev->mem_start = mmio_start;
6722 netdev->mem_end = mmio_start + mmio_len;
6723
6724 adapter->bd_number = cards_found++;
6725
4662e82b
BA		 6726 e1000e_check_options(adapter);
6727
bc7f75fa
AK		 6728 /* setup adapter struct */
6729 err = e1000_sw_init(adapter);
6730 if (err)
6731 goto err_sw_init;
6732
bc7f75fa
AK		 6733 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
6734 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
6735 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
6736
69e3fd8c 6737 err = ei->get_variants(adapter);
bc7f75fa
AK		 6738 if (err)
6739 goto err_hw_init;
6740
4a770358
BA		 6741 if ((adapter->flags & FLAG_IS_ICH) &&
6742 (adapter->flags & FLAG_READ_ONLY_NVM))
6743 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
6744
bc7f75fa
AK		 6745 hw->mac.ops.get_bus_info(&adapter->hw);
6746
318a94d6 6747 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 6748
6749 /* Copper options */
318a94d6 6750 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 6751 adapter->hw.phy.mdix = AUTO_ALL_MODES;
6752 adapter->hw.phy.disable_polarity_correction = 0;
6753 adapter->hw.phy.ms_type = e1000_ms_hw_default;
6754 }
6755
470a5420 6756 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 6757 dev_info(&pdev->dev,
6758 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 6759
dc221294
BA		 6760 /* Set initial default active device features */
6761 netdev->features = (NETIF_F_SG |
f646968f
PM		 6762 NETIF_F_HW_VLAN_CTAG_RX |
6763 NETIF_F_HW_VLAN_CTAG_TX |
dc221294
BA		 6764 NETIF_F_TSO |
6765 NETIF_F_TSO6 |
70495a50 6766 NETIF_F_RXHASH |
dc221294
BA		 6767 NETIF_F_RXCSUM |
6768 NETIF_F_HW_CSUM);
6769
6770 /* Set user-changeable features (subset of all device features) */
6771 netdev->hw_features = netdev->features;
0184039a 6772 netdev->hw_features |= NETIF_F_RXFCS;
943146de 6773 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 6774 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 6775
6776 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
f646968f 6777 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
bc7f75fa 6778
dc221294
BA		 6779 netdev->vlan_features |= (NETIF_F_SG |
6780 NETIF_F_TSO |
6781 NETIF_F_TSO6 |
6782 NETIF_F_HW_CSUM);
a5136e23 6783
ef9b965a
JB		 6784 netdev->priv_flags |= IFF_UNICAST_FLT;
6785
7b872a55 6786 if (pci_using_dac) {
bc7f75fa 6787 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 6788 netdev->vlan_features |= NETIF_F_HIGHDMA;
6789 }
bc7f75fa 6790
bc7f75fa
AK		 6791 if (e1000e_enable_mng_pass_thru(&adapter->hw))
6792 adapter->flags |= FLAG_MNG_PT_ENABLED;
6793
e921eb1a 6794 /* before reading the NVM, reset the controller to
ad68076e
BA		 6795 * put the device in a known good starting state
6796 */
bc7f75fa
AK		 6797 adapter->hw.mac.ops.reset_hw(&adapter->hw);
6798
e921eb1a 6799 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 6800 * attempt. Let's give it a few tries
6801 */
6802 for (i = 0;; i++) {
6803 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
6804 break;
6805 if (i == 2) {
185095fb 6806 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 6807 err = -EIO;
6808 goto err_eeprom;
6809 }
6810 }
6811
10aa4c04
AK		 6812 e1000_eeprom_checks(adapter);
6813
608f8a0d 6814 /* copy the MAC address */
bc7f75fa 6815 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 6816 dev_err(&pdev->dev,
6817 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 6818
6819 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 6820
aaeb6cdf 6821 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 6822 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 6823 netdev->dev_addr);
bc7f75fa
AK		 6824 err = -EIO;
6825 goto err_eeprom;
6826 }
6827
6828 init_timer(&adapter->watchdog_timer);
c061b18d 6829 adapter->watchdog_timer.function = e1000_watchdog;
53aa82da 6830 adapter->watchdog_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6831
6832 init_timer(&adapter->phy_info_timer);
c061b18d 6833 adapter->phy_info_timer.function = e1000_update_phy_info;
53aa82da 6834 adapter->phy_info_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 6835
6836 INIT_WORK(&adapter->reset_task, e1000_reset_task);
6837 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 6838 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
6839 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 6840 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 6841
bc7f75fa
AK		 6842 /* Initialize link parameters. User can change them with ethtool */
6843 adapter->hw.mac.autoneg = 1;
3db1cd5c 6844 adapter->fc_autoneg = true;
5c48ef3e
BA		 6845 adapter->hw.fc.requested_mode = e1000_fc_default;
6846 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 6847 adapter->hw.phy.autoneg_advertised = 0x2f;
6848
e921eb1a 6849 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 6850 * the EEPROM, enable the ACPI Magic Packet filter
6851 */
6852 if (adapter->flags & FLAG_APME_IN_WUC) {
6853 /* APME bit in EEPROM is mapped to WUC.APME */
6854 eeprom_data = er32(WUC);
6855 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 6856 if ((hw->mac.type > e1000_ich10lan) &&
6857 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 6858 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 6859 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
6860 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
6861 (adapter->hw.bus.func == 1))
3d3a1676
BA		 6862 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_B,
6863 1, &eeprom_data);
bc7f75fa 6864 else
3d3a1676
BA		 6865 e1000_read_nvm(&adapter->hw, NVM_INIT_CONTROL3_PORT_A,
6866 1, &eeprom_data);
bc7f75fa
AK		 6867 }
6868
6869 /* fetch WoL from EEPROM */
6870 if (eeprom_data & eeprom_apme_mask)
6871 adapter->eeprom_wol |= E1000_WUFC_MAG;
6872
e921eb1a 6873 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 6874 * where the eeprom may be wrong or the board simply won't support
6875 * wake on lan on a particular port
6876 */
6877 if (!(adapter->flags & FLAG_HAS_WOL))
6878 adapter->eeprom_wol = 0;
6879
6880 /* initialize the wol settings based on the eeprom settings */
6881 adapter->wol = adapter->eeprom_wol;
66148bab
KK		 6882
6883 /* make sure adapter isn't asleep if manageability is enabled */
6884 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
6885 (hw->mac.ops.check_mng_mode(hw)))
6886 device_wakeup_enable(&pdev->dev);
bc7f75fa 6887
84527590
BA		 6888 /* save off EEPROM version number */
6889 e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
6890
bc7f75fa
AK		 6891 /* reset the hardware with the new settings */
6892 e1000e_reset(adapter);
6893
e921eb1a 6894 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6895 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6896 * under the control of the driver.
6897 */
c43bc57e 6898 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6899 e1000e_get_hw_control(adapter);
bc7f75fa 6900
f2315bf1 6901 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 6902 err = register_netdev(netdev);
6903 if (err)
6904 goto err_register;
6905
9c563d20
JB		 6906 /* carrier off reporting is important to ethtool even BEFORE open */
6907 netif_carrier_off(netdev);
6908
d89777bf
BA		 6909 /* init PTP hardware clock */
6910 e1000e_ptp_init(adapter);
6911
bc7f75fa
AK		 6912 e1000_print_device_info(adapter);
6913
f3ec4f87
AS		 6914 if (pci_dev_run_wake(pdev))
6915 pm_runtime_put_noidle(&pdev->dev);
23606cf5 6916
bc7f75fa
AK		 6917 return 0;
6918
6919err_register:
c43bc57e 6920 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6921 e1000e_release_hw_control(adapter);
bc7f75fa 6922err_eeprom:
470a5420 6923 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 6924 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 6925err_hw_init:
bc7f75fa
AK		 6926 kfree(adapter->tx_ring);
6927 kfree(adapter->rx_ring);
6928err_sw_init:
c43bc57e
JB		 6929 if (adapter->hw.flash_address)
6930 iounmap(adapter->hw.flash_address);
e82f54ba 6931 e1000e_reset_interrupt_capability(adapter);
c43bc57e 6932err_flashmap:
bc7f75fa
AK		 6933 iounmap(adapter->hw.hw_addr);
6934err_ioremap:
6935 free_netdev(netdev);
6936err_alloc_etherdev:
f0f422e5 6937 pci_release_selected_regions(pdev,
f0ff4398 6938 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 6939err_pci_reg:
6940err_dma:
6941 pci_disable_device(pdev);
6942 return err;
6943}
6944
6945/**
6946 * e1000_remove - Device Removal Routine
6947 * @pdev: PCI device information struct
6948 *
6949 * e1000_remove is called by the PCI subsystem to alert the driver
6950 * that it should release a PCI device. The could be caused by a
6951 * Hot-Plug event, or because the driver is going to be removed from
6952 * memory.
6953 **/
9f9a12f8 6954static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 6955{
6956 struct net_device *netdev = pci_get_drvdata(pdev);
6957 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 6958 bool down = test_bit(__E1000_DOWN, &adapter->state);
6959
d89777bf
BA		 6960 e1000e_ptp_remove(adapter);
6961
e921eb1a 6962 /* The timers may be rescheduled, so explicitly disable them
23f333a2 6963 * from being rescheduled.
ad68076e 6964 */
23606cf5
RW		 6965 if (!down)
6966 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 6967 del_timer_sync(&adapter->watchdog_timer);
6968 del_timer_sync(&adapter->phy_info_timer);
6969
41cec6f1
BA		 6970 cancel_work_sync(&adapter->reset_task);
6971 cancel_work_sync(&adapter->watchdog_task);
6972 cancel_work_sync(&adapter->downshift_task);
6973 cancel_work_sync(&adapter->update_phy_task);
6974 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 6975
b67e1913
BA		 6976 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
6977 cancel_work_sync(&adapter->tx_hwtstamp_work);
6978 if (adapter->tx_hwtstamp_skb) {
6979 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
6980 adapter->tx_hwtstamp_skb = NULL;
6981 }
6982 }
6983
23606cf5
RW		 6984 /* Don't lie to e1000_close() down the road. */
6985 if (!down)
6986 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 6987 unregister_netdev(netdev);
6988
f3ec4f87
AS		 6989 if (pci_dev_run_wake(pdev))
6990 pm_runtime_get_noresume(&pdev->dev);
23606cf5 6991
e921eb1a 6992 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6993 * would have already happened in close and is redundant.
6994 */
31dbe5b4 6995 e1000e_release_hw_control(adapter);
bc7f75fa 6996
4662e82b 6997 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 6998 kfree(adapter->tx_ring);
6999 kfree(adapter->rx_ring);
7000
7001 iounmap(adapter->hw.hw_addr);
7002 if (adapter->hw.flash_address)
7003 iounmap(adapter->hw.flash_address);
f0f422e5 7004 pci_release_selected_regions(pdev,
f0ff4398 7005 pci_select_bars(pdev, IORESOURCE_MEM));
bc7f75fa
AK		 7006
7007 free_netdev(netdev);
7008
111b9dc5 7009 /* AER disable */
19d5afd4 7010 pci_disable_pcie_error_reporting(pdev);
111b9dc5 7011
bc7f75fa
AK		 7012 pci_disable_device(pdev);
7013}
7014
7015/* PCI Error Recovery (ERS) */
3646f0e5 7016static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 7017 .error_detected = e1000_io_error_detected,
7018 .slot_reset = e1000_io_slot_reset,
7019 .resume = e1000_io_resume,
7020};
7021
a3aa1884 7022static DEFINE_PCI_DEVICE_TABLE(e1000_pci_tbl) = {
bc7f75fa
AK		 7023 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7024 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7025 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
c29c3ba5
BA		 7026 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7027 board_82571 },
bc7f75fa
AK		 7028 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7029 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 7030 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7031 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7032 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 7033
bc7f75fa
AK		 7034 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7035 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7036 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7037 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 7038
bc7f75fa
AK		 7039 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7040 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7041 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 7042
4662e82b 7043 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 7044 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 7045 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 7046
bc7f75fa
AK		 7047 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7048 board_80003es2lan },
7049 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7050 board_80003es2lan },
7051 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7052 board_80003es2lan },
7053 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7054 board_80003es2lan },
ad68076e 7055
bc7f75fa
AK		 7056 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7057 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7058 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7059 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7060 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7061 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7062 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 7063 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 7064
bc7f75fa
AK		 7065 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7066 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7067 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7068 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7069 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 7070 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 7071 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7072 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7073 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7074
7075 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7076 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7077 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 7078
f4187b56
BA		 7079 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7080 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 7081 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 7082
a4f58f54
BA		 7083 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7084 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7085 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7086 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7087
d3738bb8
BA		 7088 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7089 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7090
2fbe4526
BA		 7091 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7092 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 7093 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7094 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
91a3d82f
BA		 7095 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7096 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7097 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7098 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
2fbe4526 7099
f36bb6ca 7100 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 7101};
7102MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7103
23606cf5 7104static const struct dev_pm_ops e1000_pm_ops = {
72f72dcc 7105#ifdef CONFIG_PM_SLEEP
28002099
DE		 7106 .suspend = e1000e_pm_suspend,
7107 .resume = e1000e_pm_resume,
7108 .freeze = e1000e_pm_freeze,
7109 .thaw = e1000e_pm_thaw,
7110 .poweroff = e1000e_pm_suspend,
7111 .restore = e1000e_pm_resume,
72f72dcc 7112#endif
63eb48f1
DE		 7113 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7114 e1000e_pm_runtime_idle)
23606cf5
RW		 7115};
7116
bc7f75fa
AK		 7117/* PCI Device API Driver */
7118static struct pci_driver e1000_driver = {
7119 .name = e1000e_driver_name,
7120 .id_table = e1000_pci_tbl,
7121 .probe = e1000_probe,
9f9a12f8 7122 .remove = e1000_remove,
f36bb6ca
BA		 7123 .driver = {
7124 .pm = &e1000_pm_ops,
7125 },
bc7f75fa
AK		 7126 .shutdown = e1000_shutdown,
7127 .err_handler = &e1000_err_handler
7128};
7129
7130/**
7131 * e1000_init_module - Driver Registration Routine
7132 *
7133 * e1000_init_module is the first routine called when the driver is
7134 * loaded. All it does is register with the PCI subsystem.
7135 **/
7136static int __init e1000_init_module(void)
7137{
7138 int ret;
8544b9f7
BA		 7139 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7140 e1000e_driver_version);
e78b80b1 7141 pr_info("Copyright(c) 1999 - 2014 Intel Corporation.\n");
bc7f75fa 7142 ret = pci_register_driver(&e1000_driver);
53ec5498 7143
bc7f75fa
AK		 7144 return ret;
7145}
7146module_init(e1000_init_module);
7147
7148/**
7149 * e1000_exit_module - Driver Exit Cleanup Routine
7150 *
7151 * e1000_exit_module is called just before the driver is removed
7152 * from memory.
7153 **/
7154static void __exit e1000_exit_module(void)
7155{
7156 pci_unregister_driver(&e1000_driver);
7157}
7158module_exit(e1000_exit_module);
7159
bc7f75fa
AK		 7160MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7161MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7162MODULE_LICENSE("GPL");
7163MODULE_VERSION(DRV_VERSION);
7164
06c24b91 7165/* netdev.c */
Linux 6.x block layer and io_uring tree(s)