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igb: fix adjusting PTP timestamps for Tx/Rx latency
[linux-block.git] / drivers / net / ethernet / intel / e1000e / netdev.c
CommitLineData
e78b80b1 1/* Intel PRO/1000 Linux driver
529498cd 2 * Copyright(c) 1999 - 2015 Intel Corporation.
e78b80b1
DE		 3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * The full GNU General Public License is included in this distribution in
14 * the file called "COPYING".
15 *
16 * Contact Information:
17 * Linux NICS <linux.nics@intel.com>
18 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
19 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
20 */
bc7f75fa 21
8544b9f7
BA		 22#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
23
bc7f75fa
AK		 24#include <linux/module.h>
25#include <linux/types.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/vmalloc.h>
29#include <linux/pagemap.h>
30#include <linux/delay.h>
31#include <linux/netdevice.h>
9fb7a5f7 32#include <linux/interrupt.h>
bc7f75fa
AK		 33#include <linux/tcp.h>
34#include <linux/ipv6.h>
5a0e3ad6 35#include <linux/slab.h>
bc7f75fa
AK		 36#include <net/checksum.h>
37#include <net/ip6_checksum.h>
bc7f75fa
AK		 38#include <linux/ethtool.h>
39#include <linux/if_vlan.h>
40#include <linux/cpu.h>
41#include <linux/smp.h>
e8db0be1 42#include <linux/pm_qos.h>
23606cf5 43#include <linux/pm_runtime.h>
111b9dc5 44#include <linux/aer.h>
70c71606 45#include <linux/prefetch.h>
bc7f75fa
AK		 46
47#include "e1000.h"
48
b3ccf267 49#define DRV_EXTRAVERSION "-k"
c14c643b 50
d2d7d4e4 51#define DRV_VERSION "3.2.6" DRV_EXTRAVERSION
bc7f75fa
AK		 52char e1000e_driver_name[] = "e1000e";
53const char e1000e_driver_version[] = DRV_VERSION;
54
b3f4d599 55#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
56static int debug = -1;
57module_param(debug, int, 0);
58MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
59
bc7f75fa
AK		 60static const struct e1000_info *e1000_info_tbl[] = {
61 [board_82571] = &e1000_82571_info,
62 [board_82572] = &e1000_82572_info,
63 [board_82573] = &e1000_82573_info,
4662e82b 64 [board_82574] = &e1000_82574_info,
8c81c9c3 65 [board_82583] = &e1000_82583_info,
bc7f75fa
AK		 66 [board_80003es2lan] = &e1000_es2_info,
67 [board_ich8lan] = &e1000_ich8_info,
68 [board_ich9lan] = &e1000_ich9_info,
f4187b56 69 [board_ich10lan] = &e1000_ich10_info,
a4f58f54 70 [board_pchlan] = &e1000_pch_info,
d3738bb8 71 [board_pch2lan] = &e1000_pch2_info,
2fbe4526 72 [board_pch_lpt] = &e1000_pch_lpt_info,
79849ebc 73 [board_pch_spt] = &e1000_pch_spt_info,
bc7f75fa
AK		 74};
75
84f4ee90
TI		 76struct e1000_reg_info {
77 u32 ofs;
78 char *name;
79};
80
84f4ee90 81static const struct e1000_reg_info e1000_reg_info_tbl[] = {
84f4ee90
TI		 82 /* General Registers */
83 {E1000_CTRL, "CTRL"},
84 {E1000_STATUS, "STATUS"},
85 {E1000_CTRL_EXT, "CTRL_EXT"},
86
87 /* Interrupt Registers */
88 {E1000_ICR, "ICR"},
89
af667a29 90 /* Rx Registers */
84f4ee90 91 {E1000_RCTL, "RCTL"},
1e36052e
BA		 92 {E1000_RDLEN(0), "RDLEN"},
93 {E1000_RDH(0), "RDH"},
94 {E1000_RDT(0), "RDT"},
84f4ee90
TI		 95 {E1000_RDTR, "RDTR"},
96 {E1000_RXDCTL(0), "RXDCTL"},
97 {E1000_ERT, "ERT"},
1e36052e
BA		 98 {E1000_RDBAL(0), "RDBAL"},
99 {E1000_RDBAH(0), "RDBAH"},
84f4ee90
TI		 100 {E1000_RDFH, "RDFH"},
101 {E1000_RDFT, "RDFT"},
102 {E1000_RDFHS, "RDFHS"},
103 {E1000_RDFTS, "RDFTS"},
104 {E1000_RDFPC, "RDFPC"},
105
af667a29 106 /* Tx Registers */
84f4ee90 107 {E1000_TCTL, "TCTL"},
1e36052e
BA		 108 {E1000_TDBAL(0), "TDBAL"},
109 {E1000_TDBAH(0), "TDBAH"},
110 {E1000_TDLEN(0), "TDLEN"},
111 {E1000_TDH(0), "TDH"},
112 {E1000_TDT(0), "TDT"},
84f4ee90
TI		 113 {E1000_TIDV, "TIDV"},
114 {E1000_TXDCTL(0), "TXDCTL"},
115 {E1000_TADV, "TADV"},
116 {E1000_TARC(0), "TARC"},
117 {E1000_TDFH, "TDFH"},
118 {E1000_TDFT, "TDFT"},
119 {E1000_TDFHS, "TDFHS"},
120 {E1000_TDFTS, "TDFTS"},
121 {E1000_TDFPC, "TDFPC"},
122
123 /* List Terminator */
f36bb6ca 124 {0, NULL}
84f4ee90
TI		 125};
126
c6f3148c
AK		 127/**
128 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
129 * @hw: pointer to the HW structure
130 *
131 * When updating the MAC CSR registers, the Manageability Engine (ME) could
132 * be accessing the registers at the same time. Normally, this is handled in
133 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
134 * accesses later than it should which could result in the register to have
135 * an incorrect value. Workaround this by checking the FWSM register which
136 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
137 * and try again a number of times.
138 **/
139s32 __ew32_prepare(struct e1000_hw *hw)
140{
141 s32 i = E1000_ICH_FWSM_PCIM2PCI_COUNT;
142
143 while ((er32(FWSM) & E1000_ICH_FWSM_PCIM2PCI) && --i)
144 udelay(50);
145
146 return i;
147}
148
149void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
150{
151 if (hw->adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
152 __ew32_prepare(hw);
153
154 writel(val, hw->hw_addr + reg);
155}
156
e921eb1a 157/**
84f4ee90 158 * e1000_regdump - register printout routine
e921eb1a
BA		 159 * @hw: pointer to the HW structure
160 * @reginfo: pointer to the register info table
161 **/
84f4ee90
TI		 162static void e1000_regdump(struct e1000_hw *hw, struct e1000_reg_info *reginfo)
163{
164 int n = 0;
165 char rname[16];
166 u32 regs[8];
167
168 switch (reginfo->ofs) {
169 case E1000_RXDCTL(0):
170 for (n = 0; n < 2; n++)
171 regs[n] = __er32(hw, E1000_RXDCTL(n));
172 break;
173 case E1000_TXDCTL(0):
174 for (n = 0; n < 2; n++)
175 regs[n] = __er32(hw, E1000_TXDCTL(n));
176 break;
177 case E1000_TARC(0):
178 for (n = 0; n < 2; n++)
179 regs[n] = __er32(hw, E1000_TARC(n));
180 break;
181 default:
ef456f85
JK		 182 pr_info("%-15s %08x\n",
183 reginfo->name, __er32(hw, reginfo->ofs));
84f4ee90
TI		 184 return;
185 }
186
187 snprintf(rname, 16, "%s%s", reginfo->name, "[0-1]");
ef456f85 188 pr_info("%-15s %08x %08x\n", rname, regs[0], regs[1]);
84f4ee90
TI		 189}
190
f0c5dadf
ET		 191static void e1000e_dump_ps_pages(struct e1000_adapter *adapter,
192 struct e1000_buffer *bi)
193{
194 int i;
195 struct e1000_ps_page *ps_page;
196
197 for (i = 0; i < adapter->rx_ps_pages; i++) {
198 ps_page = &bi->ps_pages[i];
199
200 if (ps_page->page) {
201 pr_info("packet dump for ps_page %d:\n", i);
202 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
203 16, 1, page_address(ps_page->page),
204 PAGE_SIZE, true);
205 }
206 }
207}
208
e921eb1a 209/**
af667a29 210 * e1000e_dump - Print registers, Tx-ring and Rx-ring
e921eb1a
BA		 211 * @adapter: board private structure
212 **/
84f4ee90
TI		 213static void e1000e_dump(struct e1000_adapter *adapter)
214{
215 struct net_device *netdev = adapter->netdev;
216 struct e1000_hw *hw = &adapter->hw;
217 struct e1000_reg_info *reginfo;
218 struct e1000_ring *tx_ring = adapter->tx_ring;
219 struct e1000_tx_desc *tx_desc;
af667a29 220 struct my_u0 {
e885d762
BA		 221 __le64 a;
222 __le64 b;
af667a29 223 } *u0;
84f4ee90
TI		 224 struct e1000_buffer *buffer_info;
225 struct e1000_ring *rx_ring = adapter->rx_ring;
226 union e1000_rx_desc_packet_split *rx_desc_ps;
5f450212 227 union e1000_rx_desc_extended *rx_desc;
af667a29 228 struct my_u1 {
e885d762
BA		 229 __le64 a;
230 __le64 b;
231 __le64 c;
232 __le64 d;
af667a29 233 } *u1;
84f4ee90
TI		 234 u32 staterr;
235 int i = 0;
236
237 if (!netif_msg_hw(adapter))
238 return;
239
240 /* Print netdevice Info */
241 if (netdev) {
242 dev_info(&adapter->pdev->dev, "Net device Info\n");
ef456f85 243 pr_info("Device Name state trans_start last_rx\n");
e5fe2541 244 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name,
4d0e9657 245 netdev->state, dev_trans_start(netdev), netdev->last_rx);
84f4ee90
TI		 246 }
247
248 /* Print Registers */
249 dev_info(&adapter->pdev->dev, "Register Dump\n");
ef456f85 250 pr_info(" Register Name Value\n");
84f4ee90
TI		 251 for (reginfo = (struct e1000_reg_info *)e1000_reg_info_tbl;
252 reginfo->name; reginfo++) {
253 e1000_regdump(hw, reginfo);
254 }
255
af667a29 256 /* Print Tx Ring Summary */
84f4ee90 257 if (!netdev || !netif_running(netdev))
fe1e980f 258 return;
84f4ee90 259
af667a29 260 dev_info(&adapter->pdev->dev, "Tx Ring Summary\n");
ef456f85 261 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
84f4ee90 262 buffer_info = &tx_ring->buffer_info[tx_ring->next_to_clean];
ef456f85
JK		 263 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
264 0, tx_ring->next_to_use, tx_ring->next_to_clean,
265 (unsigned long long)buffer_info->dma,
266 buffer_info->length,
267 buffer_info->next_to_watch,
268 (unsigned long long)buffer_info->time_stamp);
84f4ee90 269
af667a29 270 /* Print Tx Ring */
84f4ee90
TI		 271 if (!netif_msg_tx_done(adapter))
272 goto rx_ring_summary;
273
af667a29 274 dev_info(&adapter->pdev->dev, "Tx Ring Dump\n");
84f4ee90
TI		 275
276 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
277 *
278 * Legacy Transmit Descriptor
279 * +--------------------------------------------------------------+
280 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
281 * +--------------------------------------------------------------+
282 * 8 | Special | CSS | Status | CMD | CSO | Length |
283 * +--------------------------------------------------------------+
284 * 63 48 47 36 35 32 31 24 23 16 15 0
285 *
286 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
287 * 63 48 47 40 39 32 31 16 15 8 7 0
288 * +----------------------------------------------------------------+
289 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
290 * +----------------------------------------------------------------+
291 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
292 * +----------------------------------------------------------------+
293 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
294 *
295 * Extended Data Descriptor (DTYP=0x1)
296 * +----------------------------------------------------------------+
297 * 0 | Buffer Address [63:0] |
298 * +----------------------------------------------------------------+
299 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
300 * +----------------------------------------------------------------+
301 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
302 */
ef456f85
JK		 303 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
304 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
305 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
84f4ee90 306 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
ef456f85 307 const char *next_desc;
84f4ee90
TI		 308 tx_desc = E1000_TX_DESC(*tx_ring, i);
309 buffer_info = &tx_ring->buffer_info[i];
310 u0 = (struct my_u0 *)tx_desc;
84f4ee90 311 if (i == tx_ring->next_to_use && i == tx_ring->next_to_clean)
ef456f85 312 next_desc = " NTC/U";
84f4ee90 313 else if (i == tx_ring->next_to_use)
ef456f85 314 next_desc = " NTU";
84f4ee90 315 else if (i == tx_ring->next_to_clean)
ef456f85 316 next_desc = " NTC";
84f4ee90 317 else
ef456f85
JK		 318 next_desc = "";
319 pr_info("T%c[0x%03X] %016llX %016llX %016llX %04X %3X %016llX %p%s\n",
18dd2392
JK		 320 (!(le64_to_cpu(u0->b) & BIT(29)) ? 'l' :
321 ((le64_to_cpu(u0->b) & BIT(20)) ? 'd' : 'c')),
ef456f85
JK		 322 i,
323 (unsigned long long)le64_to_cpu(u0->a),
324 (unsigned long long)le64_to_cpu(u0->b),
325 (unsigned long long)buffer_info->dma,
326 buffer_info->length, buffer_info->next_to_watch,
327 (unsigned long long)buffer_info->time_stamp,
328 buffer_info->skb, next_desc);
84f4ee90 329
f0c5dadf 330 if (netif_msg_pktdata(adapter) && buffer_info->skb)
84f4ee90 331 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_ADDRESS,
f0c5dadf
ET		 332 16, 1, buffer_info->skb->data,
333 buffer_info->skb->len, true);
84f4ee90
TI		 334 }
335
af667a29 336 /* Print Rx Ring Summary */
84f4ee90 337rx_ring_summary:
af667a29 338 dev_info(&adapter->pdev->dev, "Rx Ring Summary\n");
ef456f85
JK		 339 pr_info("Queue [NTU] [NTC]\n");
340 pr_info(" %5d %5X %5X\n",
341 0, rx_ring->next_to_use, rx_ring->next_to_clean);
84f4ee90 342
af667a29 343 /* Print Rx Ring */
84f4ee90 344 if (!netif_msg_rx_status(adapter))
fe1e980f 345 return;
84f4ee90 346
af667a29 347 dev_info(&adapter->pdev->dev, "Rx Ring Dump\n");
84f4ee90
TI		 348 switch (adapter->rx_ps_pages) {
349 case 1:
350 case 2:
351 case 3:
352 /* [Extended] Packet Split Receive Descriptor Format
353 *
354 * +-----------------------------------------------------+
355 * 0 | Buffer Address 0 [63:0] |
356 * +-----------------------------------------------------+
357 * 8 | Buffer Address 1 [63:0] |
358 * +-----------------------------------------------------+
359 * 16 | Buffer Address 2 [63:0] |
360 * +-----------------------------------------------------+
361 * 24 | Buffer Address 3 [63:0] |
362 * +-----------------------------------------------------+
363 */
ef456f85 364 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
84f4ee90
TI		 365 /* [Extended] Receive Descriptor (Write-Back) Format
366 *
367 * 63 48 47 32 31 13 12 8 7 4 3 0
368 * +------------------------------------------------------+
369 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
370 * | Checksum | Ident | | Queue | | Type |
371 * +------------------------------------------------------+
372 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
373 * +------------------------------------------------------+
374 * 63 48 47 32 31 20 19 0
375 */
ef456f85 376 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
84f4ee90 377 for (i = 0; i < rx_ring->count; i++) {
ef456f85 378 const char *next_desc;
84f4ee90
TI		 379 buffer_info = &rx_ring->buffer_info[i];
380 rx_desc_ps = E1000_RX_DESC_PS(*rx_ring, i);
381 u1 = (struct my_u1 *)rx_desc_ps;
382 staterr =
af667a29 383 le32_to_cpu(rx_desc_ps->wb.middle.status_error);
ef456f85
JK		 384
385 if (i == rx_ring->next_to_use)
386 next_desc = " NTU";
387 else if (i == rx_ring->next_to_clean)
388 next_desc = " NTC";
389 else
390 next_desc = "";
391
84f4ee90
TI		 392 if (staterr & E1000_RXD_STAT_DD) {
393 /* Descriptor Done */
ef456f85
JK		 394 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX ---------------- %p%s\n",
395 "RWB", i,
396 (unsigned long long)le64_to_cpu(u1->a),
397 (unsigned long long)le64_to_cpu(u1->b),
398 (unsigned long long)le64_to_cpu(u1->c),
399 (unsigned long long)le64_to_cpu(u1->d),
400 buffer_info->skb, next_desc);
84f4ee90 401 } else {
ef456f85
JK		 402 pr_info("%s[0x%03X] %016llX %016llX %016llX %016llX %016llX %p%s\n",
403 "R ", i,
404 (unsigned long long)le64_to_cpu(u1->a),
405 (unsigned long long)le64_to_cpu(u1->b),
406 (unsigned long long)le64_to_cpu(u1->c),
407 (unsigned long long)le64_to_cpu(u1->d),
408 (unsigned long long)buffer_info->dma,
409 buffer_info->skb, next_desc);
84f4ee90
TI		 410
411 if (netif_msg_pktdata(adapter))
f0c5dadf
ET		 412 e1000e_dump_ps_pages(adapter,
413 buffer_info);
84f4ee90 414 }
84f4ee90
TI		 415 }
416 break;
417 default:
418 case 0:
5f450212 419 /* Extended Receive Descriptor (Read) Format
84f4ee90 420 *
5f450212
BA		 421 * +-----------------------------------------------------+
422 * 0 | Buffer Address [63:0] |
423 * +-----------------------------------------------------+
424 * 8 | Reserved |
425 * +-----------------------------------------------------+
84f4ee90 426 */
ef456f85 427 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
5f450212
BA		 428 /* Extended Receive Descriptor (Write-Back) Format
429 *
430 * 63 48 47 32 31 24 23 4 3 0
431 * +------------------------------------------------------+
432 * | RSS Hash | | | |
433 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
434 * | Packet | IP | | | Type |
435 * | Checksum | Ident | | | |
436 * +------------------------------------------------------+
437 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
438 * +------------------------------------------------------+
439 * 63 48 47 32 31 20 19 0
440 */
ef456f85 441 pr_info("RWB[desc] [cs ipid mrq] [vt ln xe xs] [bi->skb] <-- Ext (Write-Back) format\n");
5f450212
BA		 442
443 for (i = 0; i < rx_ring->count; i++) {
ef456f85
JK		 444 const char *next_desc;
445
84f4ee90 446 buffer_info = &rx_ring->buffer_info[i];
5f450212
BA		 447 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
448 u1 = (struct my_u1 *)rx_desc;
449 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
ef456f85
JK		 450
451 if (i == rx_ring->next_to_use)
452 next_desc = " NTU";
453 else if (i == rx_ring->next_to_clean)
454 next_desc = " NTC";
455 else
456 next_desc = "";
457
5f450212
BA		 458 if (staterr & E1000_RXD_STAT_DD) {
459 /* Descriptor Done */
ef456f85
JK		 460 pr_info("%s[0x%03X] %016llX %016llX ---------------- %p%s\n",
461 "RWB", i,
462 (unsigned long long)le64_to_cpu(u1->a),
463 (unsigned long long)le64_to_cpu(u1->b),
464 buffer_info->skb, next_desc);
5f450212 465 } else {
ef456f85
JK		 466 pr_info("%s[0x%03X] %016llX %016llX %016llX %p%s\n",
467 "R ", i,
468 (unsigned long long)le64_to_cpu(u1->a),
469 (unsigned long long)le64_to_cpu(u1->b),
470 (unsigned long long)buffer_info->dma,
471 buffer_info->skb, next_desc);
5f450212 472
f0c5dadf
ET		 473 if (netif_msg_pktdata(adapter) &&
474 buffer_info->skb)
5f450212
BA		 475 print_hex_dump(KERN_INFO, "",
476 DUMP_PREFIX_ADDRESS, 16,
477 1,
f0c5dadf 478 buffer_info->skb->data,
5f450212
BA		 479 adapter->rx_buffer_len,
480 true);
481 }
84f4ee90
TI		 482 }
483 }
84f4ee90
TI		 484}
485
bc7f75fa
AK		 486/**
487 * e1000_desc_unused - calculate if we have unused descriptors
488 **/
489static int e1000_desc_unused(struct e1000_ring *ring)
490{
491 if (ring->next_to_clean > ring->next_to_use)
492 return ring->next_to_clean - ring->next_to_use - 1;
493
494 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
495}
496
b67e1913
BA		 497/**
498 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
499 * @adapter: board private structure
500 * @hwtstamps: time stamp structure to update
501 * @systim: unsigned 64bit system time value.
502 *
503 * Convert the system time value stored in the RX/TXSTMP registers into a
504 * hwtstamp which can be used by the upper level time stamping functions.
505 *
506 * The 'systim_lock' spinlock is used to protect the consistency of the
507 * system time value. This is needed because reading the 64 bit time
508 * value involves reading two 32 bit registers. The first read latches the
509 * value.
510 **/
511static void e1000e_systim_to_hwtstamp(struct e1000_adapter *adapter,
512 struct skb_shared_hwtstamps *hwtstamps,
513 u64 systim)
514{
515 u64 ns;
516 unsigned long flags;
517
518 spin_lock_irqsave(&adapter->systim_lock, flags);
519 ns = timecounter_cyc2time(&adapter->tc, systim);
520 spin_unlock_irqrestore(&adapter->systim_lock, flags);
521
522 memset(hwtstamps, 0, sizeof(*hwtstamps));
523 hwtstamps->hwtstamp = ns_to_ktime(ns);
524}
525
526/**
527 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
528 * @adapter: board private structure
529 * @status: descriptor extended error and status field
530 * @skb: particular skb to include time stamp
531 *
532 * If the time stamp is valid, convert it into the timecounter ns value
533 * and store that result into the shhwtstamps structure which is passed
534 * up the network stack.
535 **/
536static void e1000e_rx_hwtstamp(struct e1000_adapter *adapter, u32 status,
537 struct sk_buff *skb)
538{
539 struct e1000_hw *hw = &adapter->hw;
540 u64 rxstmp;
541
542 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP) ||
543 !(status & E1000_RXDEXT_STATERR_TST) ||
544 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
545 return;
546
547 /* The Rx time stamp registers contain the time stamp. No other
548 * received packet will be time stamped until the Rx time stamp
549 * registers are read. Because only one packet can be time stamped
550 * at a time, the register values must belong to this packet and
551 * therefore none of the other additional attributes need to be
552 * compared.
553 */
554 rxstmp = (u64)er32(RXSTMPL);
555 rxstmp |= (u64)er32(RXSTMPH) << 32;
556 e1000e_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), rxstmp);
557
558 adapter->flags2 &= ~FLAG2_CHECK_RX_HWTSTAMP;
559}
560
bc7f75fa 561/**
ad68076e 562 * e1000_receive_skb - helper function to handle Rx indications
bc7f75fa 563 * @adapter: board private structure
b67e1913 564 * @staterr: descriptor extended error and status field as written by hardware
bc7f75fa
AK		 565 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
566 * @skb: pointer to sk_buff to be indicated to stack
567 **/
568static void e1000_receive_skb(struct e1000_adapter *adapter,
af667a29 569 struct net_device *netdev, struct sk_buff *skb,
b67e1913 570 u32 staterr, __le16 vlan)
bc7f75fa 571{
86d70e53 572 u16 tag = le16_to_cpu(vlan);
b67e1913
BA		 573
574 e1000e_rx_hwtstamp(adapter, staterr, skb);
575
bc7f75fa
AK		 576 skb->protocol = eth_type_trans(skb, netdev);
577
b67e1913 578 if (staterr & E1000_RXD_STAT_VP)
86a9bad3 579 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), tag);
86d70e53
JK		 580
581 napi_gro_receive(&adapter->napi, skb);
bc7f75fa
AK		 582}
583
584/**
af667a29 585 * e1000_rx_checksum - Receive Checksum Offload
afd12939
BA		 586 * @adapter: board private structure
587 * @status_err: receive descriptor status and error fields
588 * @csum: receive descriptor csum field
589 * @sk_buff: socket buffer with received data
bc7f75fa
AK		 590 **/
591static void e1000_rx_checksum(struct e1000_adapter *adapter, u32 status_err,
2e1706f2 592 struct sk_buff *skb)
bc7f75fa
AK		 593{
594 u16 status = (u16)status_err;
595 u8 errors = (u8)(status_err >> 24);
bc8acf2c
ED		 596
597 skb_checksum_none_assert(skb);
bc7f75fa 598
afd12939
BA		 599 /* Rx checksum disabled */
600 if (!(adapter->netdev->features & NETIF_F_RXCSUM))
601 return;
602
bc7f75fa
AK		 603 /* Ignore Checksum bit is set */
604 if (status & E1000_RXD_STAT_IXSM)
605 return;
afd12939 606
2e1706f2
BA		 607 /* TCP/UDP checksum error bit or IP checksum error bit is set */
608 if (errors & (E1000_RXD_ERR_TCPE | E1000_RXD_ERR_IPE)) {
bc7f75fa
AK		 609 /* let the stack verify checksum errors */
610 adapter->hw_csum_err++;
611 return;
612 }
613
614 /* TCP/UDP Checksum has not been calculated */
615 if (!(status & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)))
616 return;
617
618 /* It must be a TCP or UDP packet with a valid checksum */
2e1706f2 619 skb->ip_summed = CHECKSUM_UNNECESSARY;
bc7f75fa
AK		 620 adapter->hw_csum_good++;
621}
622
55aa6985 623static void e1000e_update_rdt_wa(struct e1000_ring *rx_ring, unsigned int i)
c6e7f51e 624{
55aa6985 625 struct e1000_adapter *adapter = rx_ring->adapter;
c6e7f51e 626 struct e1000_hw *hw = &adapter->hw;
bdc125f7
BA		 627 s32 ret_val = __ew32_prepare(hw);
628
629 writel(i, rx_ring->tail);
c6e7f51e 630
bdc125f7 631 if (unlikely(!ret_val && (i != readl(rx_ring->tail)))) {
c6e7f51e 632 u32 rctl = er32(RCTL);
6cf08d1c 633
c6e7f51e
BA		 634 ew32(RCTL, rctl & ~E1000_RCTL_EN);
635 e_err("ME firmware caused invalid RDT - resetting\n");
636 schedule_work(&adapter->reset_task);
637 }
638}
639
55aa6985 640static void e1000e_update_tdt_wa(struct e1000_ring *tx_ring, unsigned int i)
c6e7f51e 641{
55aa6985 642 struct e1000_adapter *adapter = tx_ring->adapter;
c6e7f51e 643 struct e1000_hw *hw = &adapter->hw;
bdc125f7 644 s32 ret_val = __ew32_prepare(hw);
c6e7f51e 645
bdc125f7
BA		 646 writel(i, tx_ring->tail);
647
648 if (unlikely(!ret_val && (i != readl(tx_ring->tail)))) {
c6e7f51e 649 u32 tctl = er32(TCTL);
6cf08d1c 650
c6e7f51e
BA		 651 ew32(TCTL, tctl & ~E1000_TCTL_EN);
652 e_err("ME firmware caused invalid TDT - resetting\n");
653 schedule_work(&adapter->reset_task);
654 }
655}
656
bc7f75fa 657/**
5f450212 658 * e1000_alloc_rx_buffers - Replace used receive buffers
55aa6985 659 * @rx_ring: Rx descriptor ring
bc7f75fa 660 **/
55aa6985 661static void e1000_alloc_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 662 int cleaned_count, gfp_t gfp)
bc7f75fa 663{
55aa6985 664 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 665 struct net_device *netdev = adapter->netdev;
666 struct pci_dev *pdev = adapter->pdev;
5f450212 667 union e1000_rx_desc_extended *rx_desc;
bc7f75fa
AK		 668 struct e1000_buffer *buffer_info;
669 struct sk_buff *skb;
670 unsigned int i;
89d71a66 671 unsigned int bufsz = adapter->rx_buffer_len;
bc7f75fa
AK		 672
673 i = rx_ring->next_to_use;
674 buffer_info = &rx_ring->buffer_info[i];
675
676 while (cleaned_count--) {
677 skb = buffer_info->skb;
678 if (skb) {
679 skb_trim(skb, 0);
680 goto map_skb;
681 }
682
c2fed996 683 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
bc7f75fa
AK		 684 if (!skb) {
685 /* Better luck next round */
686 adapter->alloc_rx_buff_failed++;
687 break;
688 }
689
bc7f75fa
AK		 690 buffer_info->skb = skb;
691map_skb:
0be3f55f 692 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 693 adapter->rx_buffer_len,
0be3f55f
NN		 694 DMA_FROM_DEVICE);
695 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 696 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 697 adapter->rx_dma_failed++;
698 break;
699 }
700
5f450212
BA		 701 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
702 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
bc7f75fa 703
50849d79 704 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 705 /* Force memory writes to complete before letting h/w
50849d79
TH		 706 * know there are new descriptors to fetch. (Only
707 * applicable for weak-ordered memory model archs,
708 * such as IA-64).
709 */
710 wmb();
c6e7f51e 711 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 712 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 713 else
c5083cf6 714 writel(i, rx_ring->tail);
50849d79 715 }
bc7f75fa
AK		 716 i++;
717 if (i == rx_ring->count)
718 i = 0;
719 buffer_info = &rx_ring->buffer_info[i];
720 }
721
50849d79 722 rx_ring->next_to_use = i;
bc7f75fa
AK		 723}
724
725/**
726 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
55aa6985 727 * @rx_ring: Rx descriptor ring
bc7f75fa 728 **/
55aa6985 729static void e1000_alloc_rx_buffers_ps(struct e1000_ring *rx_ring,
c2fed996 730 int cleaned_count, gfp_t gfp)
bc7f75fa 731{
55aa6985 732 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 733 struct net_device *netdev = adapter->netdev;
734 struct pci_dev *pdev = adapter->pdev;
735 union e1000_rx_desc_packet_split *rx_desc;
bc7f75fa
AK		 736 struct e1000_buffer *buffer_info;
737 struct e1000_ps_page *ps_page;
738 struct sk_buff *skb;
739 unsigned int i, j;
740
741 i = rx_ring->next_to_use;
742 buffer_info = &rx_ring->buffer_info[i];
743
744 while (cleaned_count--) {
745 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
746
747 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40
AK		 748 ps_page = &buffer_info->ps_pages[j];
749 if (j >= adapter->rx_ps_pages) {
750 /* all unused desc entries get hw null ptr */
af667a29
BA		 751 rx_desc->read.buffer_addr[j + 1] =
752 ~cpu_to_le64(0);
47f44e40
AK		 753 continue;
754 }
755 if (!ps_page->page) {
c2fed996 756 ps_page->page = alloc_page(gfp);
bc7f75fa 757 if (!ps_page->page) {
47f44e40
AK		 758 adapter->alloc_rx_buff_failed++;
759 goto no_buffers;
760 }
0be3f55f
NN		 761 ps_page->dma = dma_map_page(&pdev->dev,
762 ps_page->page,
763 0, PAGE_SIZE,
764 DMA_FROM_DEVICE);
765 if (dma_mapping_error(&pdev->dev,
766 ps_page->dma)) {
47f44e40 767 dev_err(&adapter->pdev->dev,
af667a29 768 "Rx DMA page map failed\n");
47f44e40
AK		 769 adapter->rx_dma_failed++;
770 goto no_buffers;
bc7f75fa 771 }
bc7f75fa 772 }
e921eb1a 773 /* Refresh the desc even if buffer_addrs
47f44e40
AK		 774 * didn't change because each write-back
775 * erases this info.
776 */
af667a29
BA		 777 rx_desc->read.buffer_addr[j + 1] =
778 cpu_to_le64(ps_page->dma);
bc7f75fa
AK		 779 }
780
e5fe2541 781 skb = __netdev_alloc_skb_ip_align(netdev, adapter->rx_ps_bsize0,
c2fed996 782 gfp);
bc7f75fa
AK		 783
784 if (!skb) {
785 adapter->alloc_rx_buff_failed++;
786 break;
787 }
788
bc7f75fa 789 buffer_info->skb = skb;
0be3f55f 790 buffer_info->dma = dma_map_single(&pdev->dev, skb->data,
bc7f75fa 791 adapter->rx_ps_bsize0,
0be3f55f
NN		 792 DMA_FROM_DEVICE);
793 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
af667a29 794 dev_err(&pdev->dev, "Rx DMA map failed\n");
bc7f75fa
AK		 795 adapter->rx_dma_failed++;
796 /* cleanup skb */
797 dev_kfree_skb_any(skb);
798 buffer_info->skb = NULL;
799 break;
800 }
801
802 rx_desc->read.buffer_addr[0] = cpu_to_le64(buffer_info->dma);
803
50849d79 804 if (unlikely(!(i & (E1000_RX_BUFFER_WRITE - 1)))) {
e921eb1a 805 /* Force memory writes to complete before letting h/w
50849d79
TH		 806 * know there are new descriptors to fetch. (Only
807 * applicable for weak-ordered memory model archs,
808 * such as IA-64).
809 */
810 wmb();
c6e7f51e 811 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 812 e1000e_update_rdt_wa(rx_ring, i << 1);
c6e7f51e 813 else
c5083cf6 814 writel(i << 1, rx_ring->tail);
50849d79
TH		 815 }
816
bc7f75fa
AK		 817 i++;
818 if (i == rx_ring->count)
819 i = 0;
820 buffer_info = &rx_ring->buffer_info[i];
821 }
822
823no_buffers:
50849d79 824 rx_ring->next_to_use = i;
bc7f75fa
AK		 825}
826
97ac8cae
BA		 827/**
828 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
55aa6985 829 * @rx_ring: Rx descriptor ring
97ac8cae
BA		 830 * @cleaned_count: number of buffers to allocate this pass
831 **/
832
55aa6985 833static void e1000_alloc_jumbo_rx_buffers(struct e1000_ring *rx_ring,
c2fed996 834 int cleaned_count, gfp_t gfp)
97ac8cae 835{
55aa6985 836 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 837 struct net_device *netdev = adapter->netdev;
838 struct pci_dev *pdev = adapter->pdev;
5f450212 839 union e1000_rx_desc_extended *rx_desc;
97ac8cae
BA		 840 struct e1000_buffer *buffer_info;
841 struct sk_buff *skb;
842 unsigned int i;
2a2293b9 843 unsigned int bufsz = 256 - 16; /* for skb_reserve */
97ac8cae
BA		 844
845 i = rx_ring->next_to_use;
846 buffer_info = &rx_ring->buffer_info[i];
847
848 while (cleaned_count--) {
849 skb = buffer_info->skb;
850 if (skb) {
851 skb_trim(skb, 0);
852 goto check_page;
853 }
854
c2fed996 855 skb = __netdev_alloc_skb_ip_align(netdev, bufsz, gfp);
97ac8cae
BA		 856 if (unlikely(!skb)) {
857 /* Better luck next round */
858 adapter->alloc_rx_buff_failed++;
859 break;
860 }
861
97ac8cae
BA		 862 buffer_info->skb = skb;
863check_page:
864 /* allocate a new page if necessary */
865 if (!buffer_info->page) {
c2fed996 866 buffer_info->page = alloc_page(gfp);
97ac8cae
BA		 867 if (unlikely(!buffer_info->page)) {
868 adapter->alloc_rx_buff_failed++;
869 break;
870 }
871 }
872
37287fae 873 if (!buffer_info->dma) {
0be3f55f 874 buffer_info->dma = dma_map_page(&pdev->dev,
f0ff4398
BA		 875 buffer_info->page, 0,
876 PAGE_SIZE,
0be3f55f 877 DMA_FROM_DEVICE);
37287fae
CP		 878 if (dma_mapping_error(&pdev->dev, buffer_info->dma)) {
879 adapter->alloc_rx_buff_failed++;
880 break;
881 }
882 }
97ac8cae 883
5f450212
BA		 884 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
885 rx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
97ac8cae
BA		 886
887 if (unlikely(++i == rx_ring->count))
888 i = 0;
889 buffer_info = &rx_ring->buffer_info[i];
890 }
891
892 if (likely(rx_ring->next_to_use != i)) {
893 rx_ring->next_to_use = i;
894 if (unlikely(i-- == 0))
895 i = (rx_ring->count - 1);
896
897 /* Force memory writes to complete before letting h/w
898 * know there are new descriptors to fetch. (Only
899 * applicable for weak-ordered memory model archs,
e921eb1a
BA		 900 * such as IA-64).
901 */
97ac8cae 902 wmb();
c6e7f51e 903 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
55aa6985 904 e1000e_update_rdt_wa(rx_ring, i);
c6e7f51e 905 else
c5083cf6 906 writel(i, rx_ring->tail);
97ac8cae
BA		 907 }
908}
909
70495a50
BA		 910static inline void e1000_rx_hash(struct net_device *netdev, __le32 rss,
911 struct sk_buff *skb)
912{
913 if (netdev->features & NETIF_F_RXHASH)
e25909bc 914 skb_set_hash(skb, le32_to_cpu(rss), PKT_HASH_TYPE_L3);
70495a50
BA		 915}
916
bc7f75fa 917/**
55aa6985
BA		 918 * e1000_clean_rx_irq - Send received data up the network stack
919 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 920 *
921 * the return value indicates whether actual cleaning was done, there
922 * is no guarantee that everything was cleaned
923 **/
55aa6985
BA		 924static bool e1000_clean_rx_irq(struct e1000_ring *rx_ring, int *work_done,
925 int work_to_do)
bc7f75fa 926{
55aa6985 927 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 928 struct net_device *netdev = adapter->netdev;
929 struct pci_dev *pdev = adapter->pdev;
3bb99fe2 930 struct e1000_hw *hw = &adapter->hw;
5f450212 931 union e1000_rx_desc_extended *rx_desc, *next_rxd;
bc7f75fa 932 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 933 u32 length, staterr;
bc7f75fa
AK		 934 unsigned int i;
935 int cleaned_count = 0;
3db1cd5c 936 bool cleaned = false;
bc7f75fa
AK		 937 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
938
939 i = rx_ring->next_to_clean;
5f450212
BA		 940 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
941 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 942 buffer_info = &rx_ring->buffer_info[i];
943
5f450212 944 while (staterr & E1000_RXD_STAT_DD) {
bc7f75fa 945 struct sk_buff *skb;
bc7f75fa
AK		 946
947 if (*work_done >= work_to_do)
948 break;
949 (*work_done)++;
837a1dba 950 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa 951
bc7f75fa
AK		 952 skb = buffer_info->skb;
953 buffer_info->skb = NULL;
954
955 prefetch(skb->data - NET_IP_ALIGN);
956
957 i++;
958 if (i == rx_ring->count)
959 i = 0;
5f450212 960 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
bc7f75fa
AK		 961 prefetch(next_rxd);
962
963 next_buffer = &rx_ring->buffer_info[i];
964
3db1cd5c 965 cleaned = true;
bc7f75fa 966 cleaned_count++;
e5fe2541
BA		 967 dma_unmap_single(&pdev->dev, buffer_info->dma,
968 adapter->rx_buffer_len, DMA_FROM_DEVICE);
bc7f75fa
AK		 969 buffer_info->dma = 0;
970
5f450212 971 length = le16_to_cpu(rx_desc->wb.upper.length);
bc7f75fa 972
e921eb1a 973 /* !EOP means multiple descriptors were used to store a single
b94b5028
JB		 974 * packet, if that's the case we need to toss it. In fact, we
975 * need to toss every packet with the EOP bit clear and the
976 * next frame that _does_ have the EOP bit set, as it is by
977 * definition only a frame fragment
978 */
5f450212 979 if (unlikely(!(staterr & E1000_RXD_STAT_EOP)))
b94b5028
JB		 980 adapter->flags2 |= FLAG2_IS_DISCARDING;
981
982 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
bc7f75fa 983 /* All receives must fit into a single buffer */
3bb99fe2 984 e_dbg("Receive packet consumed multiple buffers\n");
bc7f75fa
AK		 985 /* recycle */
986 buffer_info->skb = skb;
5f450212 987 if (staterr & E1000_RXD_STAT_EOP)
b94b5028 988 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 989 goto next_desc;
990 }
991
cf955e6c
BG		 992 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
993 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 994 /* recycle */
995 buffer_info->skb = skb;
996 goto next_desc;
997 }
998
eb7c3adb 999 /* adjust length to remove Ethernet CRC */
0184039a
BG		 1000 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1001 /* If configured to store CRC, don't subtract FCS,
1002 * but keep the FCS bytes out of the total_rx_bytes
1003 * counter
1004 */
1005 if (netdev->features & NETIF_F_RXFCS)
1006 total_rx_bytes -= 4;
1007 else
1008 length -= 4;
1009 }
eb7c3adb 1010
bc7f75fa
AK		 1011 total_rx_bytes += length;
1012 total_rx_packets++;
1013
e921eb1a 1014 /* code added for copybreak, this should improve
bc7f75fa 1015 * performance for small packets with large amounts
ad68076e
BA		 1016 * of reassembly being done in the stack
1017 */
bc7f75fa
AK		 1018 if (length < copybreak) {
1019 struct sk_buff *new_skb =
67fd893e 1020 napi_alloc_skb(&adapter->napi, length);
bc7f75fa 1021 if (new_skb) {
808ff676
BA		 1022 skb_copy_to_linear_data_offset(new_skb,
1023 -NET_IP_ALIGN,
1024 (skb->data -
1025 NET_IP_ALIGN),
1026 (length +
1027 NET_IP_ALIGN));
bc7f75fa
AK		 1028 /* save the skb in buffer_info as good */
1029 buffer_info->skb = skb;
1030 skb = new_skb;
1031 }
1032 /* else just continue with the old one */
1033 }
1034 /* end copybreak code */
1035 skb_put(skb, length);
1036
1037 /* Receive Checksum Offload */
2e1706f2 1038 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1039
70495a50
BA		 1040 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1041
5f450212
BA		 1042 e1000_receive_skb(adapter, netdev, skb, staterr,
1043 rx_desc->wb.upper.vlan);
bc7f75fa
AK		 1044
1045next_desc:
5f450212 1046 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
bc7f75fa
AK		 1047
1048 /* return some buffers to hardware, one at a time is too slow */
1049 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1050 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1051 GFP_ATOMIC);
bc7f75fa
AK		 1052 cleaned_count = 0;
1053 }
1054
1055 /* use prefetched values */
1056 rx_desc = next_rxd;
1057 buffer_info = next_buffer;
5f450212
BA		 1058
1059 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
bc7f75fa
AK		 1060 }
1061 rx_ring->next_to_clean = i;
1062
1063 cleaned_count = e1000_desc_unused(rx_ring);
1064 if (cleaned_count)
55aa6985 1065 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1066
bc7f75fa 1067 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1068 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1069 return cleaned;
1070}
1071
55aa6985
BA		 1072static void e1000_put_txbuf(struct e1000_ring *tx_ring,
1073 struct e1000_buffer *buffer_info)
bc7f75fa 1074{
55aa6985
BA		 1075 struct e1000_adapter *adapter = tx_ring->adapter;
1076
03b1320d
AD		 1077 if (buffer_info->dma) {
1078 if (buffer_info->mapped_as_page)
0be3f55f
NN		 1079 dma_unmap_page(&adapter->pdev->dev, buffer_info->dma,
1080 buffer_info->length, DMA_TO_DEVICE);
03b1320d 1081 else
0be3f55f
NN		 1082 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1083 buffer_info->length, DMA_TO_DEVICE);
03b1320d
AD		 1084 buffer_info->dma = 0;
1085 }
bc7f75fa
AK		 1086 if (buffer_info->skb) {
1087 dev_kfree_skb_any(buffer_info->skb);
1088 buffer_info->skb = NULL;
1089 }
1b7719c4 1090 buffer_info->time_stamp = 0;
bc7f75fa
AK		 1091}
1092
41cec6f1 1093static void e1000_print_hw_hang(struct work_struct *work)
bc7f75fa 1094{
41cec6f1 1095 struct e1000_adapter *adapter = container_of(work,
f0ff4398
BA		 1096 struct e1000_adapter,
1097 print_hang_task);
09357b00 1098 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 1099 struct e1000_ring *tx_ring = adapter->tx_ring;
1100 unsigned int i = tx_ring->next_to_clean;
1101 unsigned int eop = tx_ring->buffer_info[i].next_to_watch;
1102 struct e1000_tx_desc *eop_desc = E1000_TX_DESC(*tx_ring, eop);
41cec6f1
BA		 1103 struct e1000_hw *hw = &adapter->hw;
1104 u16 phy_status, phy_1000t_status, phy_ext_status;
1105 u16 pci_status;
1106
615b32af
JB		 1107 if (test_bit(__E1000_DOWN, &adapter->state))
1108 return;
1109
e5fe2541 1110 if (!adapter->tx_hang_recheck && (adapter->flags2 & FLAG2_DMA_BURST)) {
e921eb1a 1111 /* May be block on write-back, flush and detect again
09357b00
JK		 1112 * flush pending descriptor writebacks to memory
1113 */
1114 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1115 /* execute the writes immediately */
1116 e1e_flush();
e921eb1a 1117 /* Due to rare timing issues, write to TIDV again to ensure
bf03085f
MV		 1118 * the write is successful
1119 */
1120 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
1121 /* execute the writes immediately */
1122 e1e_flush();
09357b00
JK		 1123 adapter->tx_hang_recheck = true;
1124 return;
1125 }
09357b00 1126 adapter->tx_hang_recheck = false;
d9554e96
DE		 1127
1128 if (er32(TDH(0)) == er32(TDT(0))) {
1129 e_dbg("false hang detected, ignoring\n");
1130 return;
1131 }
1132
1133 /* Real hang detected */
09357b00
JK		 1134 netif_stop_queue(netdev);
1135
c2ade1a4
BA		 1136 e1e_rphy(hw, MII_BMSR, &phy_status);
1137 e1e_rphy(hw, MII_STAT1000, &phy_1000t_status);
1138 e1e_rphy(hw, MII_ESTATUS, &phy_ext_status);
bc7f75fa 1139
41cec6f1
BA		 1140 pci_read_config_word(adapter->pdev, PCI_STATUS, &pci_status);
1141
1142 /* detected Hardware unit hang */
1143 e_err("Detected Hardware Unit Hang:\n"
44defeb3
JK		 1144 " TDH <%x>\n"
1145 " TDT <%x>\n"
1146 " next_to_use <%x>\n"
1147 " next_to_clean <%x>\n"
1148 "buffer_info[next_to_clean]:\n"
1149 " time_stamp <%lx>\n"
1150 " next_to_watch <%x>\n"
1151 " jiffies <%lx>\n"
41cec6f1
BA		 1152 " next_to_watch.status <%x>\n"
1153 "MAC Status <%x>\n"
1154 "PHY Status <%x>\n"
1155 "PHY 1000BASE-T Status <%x>\n"
1156 "PHY Extended Status <%x>\n"
1157 "PCI Status <%x>\n",
e5fe2541
BA		 1158 readl(tx_ring->head), readl(tx_ring->tail), tx_ring->next_to_use,
1159 tx_ring->next_to_clean, tx_ring->buffer_info[eop].time_stamp,
1160 eop, jiffies, eop_desc->upper.fields.status, er32(STATUS),
1161 phy_status, phy_1000t_status, phy_ext_status, pci_status);
7c0427ee 1162
d9554e96
DE		 1163 e1000e_dump(adapter);
1164
7c0427ee
BA		 1165 /* Suggest workaround for known h/w issue */
1166 if ((hw->mac.type == e1000_pchlan) && (er32(CTRL) & E1000_CTRL_TFCE))
1167 e_err("Try turning off Tx pause (flow control) via ethtool\n");
bc7f75fa
AK		 1168}
1169
b67e1913
BA		 1170/**
1171 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1172 * @work: pointer to work struct
1173 *
1174 * This work function polls the TSYNCTXCTL valid bit to determine when a
1175 * timestamp has been taken for the current stored skb. The timestamp must
1176 * be for this skb because only one such packet is allowed in the queue.
1177 */
1178static void e1000e_tx_hwtstamp_work(struct work_struct *work)
1179{
1180 struct e1000_adapter *adapter = container_of(work, struct e1000_adapter,
1181 tx_hwtstamp_work);
1182 struct e1000_hw *hw = &adapter->hw;
1183
b67e1913
BA		 1184 if (er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID) {
1185 struct skb_shared_hwtstamps shhwtstamps;
1186 u64 txstmp;
1187
1188 txstmp = er32(TXSTMPL);
1189 txstmp |= (u64)er32(TXSTMPH) << 32;
1190
1191 e1000e_systim_to_hwtstamp(adapter, &shhwtstamps, txstmp);
1192
1193 skb_tstamp_tx(adapter->tx_hwtstamp_skb, &shhwtstamps);
1194 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1195 adapter->tx_hwtstamp_skb = NULL;
59c871c5
JK		 1196 } else if (time_after(jiffies, adapter->tx_hwtstamp_start
1197 + adapter->tx_timeout_factor * HZ)) {
1198 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
1199 adapter->tx_hwtstamp_skb = NULL;
1200 adapter->tx_hwtstamp_timeouts++;
c5ffe7e1 1201 e_warn("clearing Tx timestamp hang\n");
b67e1913
BA		 1202 } else {
1203 /* reschedule to check later */
1204 schedule_work(&adapter->tx_hwtstamp_work);
1205 }
1206}
1207
bc7f75fa
AK		 1208/**
1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes
55aa6985 1210 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 1211 *
1212 * the return value indicates whether actual cleaning was done, there
1213 * is no guarantee that everything was cleaned
1214 **/
55aa6985 1215static bool e1000_clean_tx_irq(struct e1000_ring *tx_ring)
bc7f75fa 1216{
55aa6985 1217 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 1218 struct net_device *netdev = adapter->netdev;
1219 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1220 struct e1000_tx_desc *tx_desc, *eop_desc;
1221 struct e1000_buffer *buffer_info;
1222 unsigned int i, eop;
1223 unsigned int count = 0;
bc7f75fa 1224 unsigned int total_tx_bytes = 0, total_tx_packets = 0;
3f0cfa3b 1225 unsigned int bytes_compl = 0, pkts_compl = 0;
bc7f75fa
AK		 1226
1227 i = tx_ring->next_to_clean;
1228 eop = tx_ring->buffer_info[i].next_to_watch;
1229 eop_desc = E1000_TX_DESC(*tx_ring, eop);
1230
12d04a3c
AD		 1231 while ((eop_desc->upper.data & cpu_to_le32(E1000_TXD_STAT_DD)) &&
1232 (count < tx_ring->count)) {
a86043c2 1233 bool cleaned = false;
6cf08d1c 1234
837a1dba 1235 dma_rmb(); /* read buffer_info after eop_desc */
a86043c2 1236 for (; !cleaned; count++) {
bc7f75fa
AK		 1237 tx_desc = E1000_TX_DESC(*tx_ring, i);
1238 buffer_info = &tx_ring->buffer_info[i];
1239 cleaned = (i == eop);
1240
1241 if (cleaned) {
9ed318d5
TH		 1242 total_tx_packets += buffer_info->segs;
1243 total_tx_bytes += buffer_info->bytecount;
3f0cfa3b
TH		 1244 if (buffer_info->skb) {
1245 bytes_compl += buffer_info->skb->len;
1246 pkts_compl++;
1247 }
bc7f75fa
AK		 1248 }
1249
55aa6985 1250 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 1251 tx_desc->upper.data = 0;
1252
1253 i++;
1254 if (i == tx_ring->count)
1255 i = 0;
1256 }
1257
dac87619
TL		 1258 if (i == tx_ring->next_to_use)
1259 break;
bc7f75fa
AK		 1260 eop = tx_ring->buffer_info[i].next_to_watch;
1261 eop_desc = E1000_TX_DESC(*tx_ring, eop);
bc7f75fa
AK		 1262 }
1263
1264 tx_ring->next_to_clean = i;
1265
3f0cfa3b
TH		 1266 netdev_completed_queue(netdev, pkts_compl, bytes_compl);
1267
bc7f75fa 1268#define TX_WAKE_THRESHOLD 32
a86043c2
JB		 1269 if (count && netif_carrier_ok(netdev) &&
1270 e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) {
bc7f75fa
AK		 1271 /* Make sure that anybody stopping the queue after this
1272 * sees the new next_to_clean.
1273 */
1274 smp_mb();
1275
1276 if (netif_queue_stopped(netdev) &&
1277 !(test_bit(__E1000_DOWN, &adapter->state))) {
1278 netif_wake_queue(netdev);
1279 ++adapter->restart_queue;
1280 }
1281 }
1282
1283 if (adapter->detect_tx_hung) {
e921eb1a 1284 /* Detect a transmit hang in hardware, this serializes the
41cec6f1
BA		 1285 * check with the clearing of time_stamp and movement of i
1286 */
3db1cd5c 1287 adapter->detect_tx_hung = false;
12d04a3c
AD		 1288 if (tx_ring->buffer_info[i].time_stamp &&
1289 time_after(jiffies, tx_ring->buffer_info[i].time_stamp
8e95a202 1290 + (adapter->tx_timeout_factor * HZ)) &&
09357b00 1291 !(er32(STATUS) & E1000_STATUS_TXOFF))
41cec6f1 1292 schedule_work(&adapter->print_hang_task);
09357b00
JK		 1293 else
1294 adapter->tx_hang_recheck = false;
bc7f75fa
AK		 1295 }
1296 adapter->total_tx_bytes += total_tx_bytes;
1297 adapter->total_tx_packets += total_tx_packets;
807540ba 1298 return count < tx_ring->count;
bc7f75fa
AK		 1299}
1300
bc7f75fa
AK		 1301/**
1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
55aa6985 1303 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 1304 *
1305 * the return value indicates whether actual cleaning was done, there
1306 * is no guarantee that everything was cleaned
1307 **/
55aa6985
BA		 1308static bool e1000_clean_rx_irq_ps(struct e1000_ring *rx_ring, int *work_done,
1309 int work_to_do)
bc7f75fa 1310{
55aa6985 1311 struct e1000_adapter *adapter = rx_ring->adapter;
3bb99fe2 1312 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 1313 union e1000_rx_desc_packet_split *rx_desc, *next_rxd;
1314 struct net_device *netdev = adapter->netdev;
1315 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1316 struct e1000_buffer *buffer_info, *next_buffer;
1317 struct e1000_ps_page *ps_page;
1318 struct sk_buff *skb;
1319 unsigned int i, j;
1320 u32 length, staterr;
1321 int cleaned_count = 0;
3db1cd5c 1322 bool cleaned = false;
bc7f75fa
AK		 1323 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1324
1325 i = rx_ring->next_to_clean;
1326 rx_desc = E1000_RX_DESC_PS(*rx_ring, i);
1327 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1328 buffer_info = &rx_ring->buffer_info[i];
1329
1330 while (staterr & E1000_RXD_STAT_DD) {
1331 if (*work_done >= work_to_do)
1332 break;
1333 (*work_done)++;
1334 skb = buffer_info->skb;
837a1dba 1335 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
bc7f75fa
AK		 1336
1337 /* in the packet split case this is header only */
1338 prefetch(skb->data - NET_IP_ALIGN);
1339
1340 i++;
1341 if (i == rx_ring->count)
1342 i = 0;
1343 next_rxd = E1000_RX_DESC_PS(*rx_ring, i);
1344 prefetch(next_rxd);
1345
1346 next_buffer = &rx_ring->buffer_info[i];
1347
3db1cd5c 1348 cleaned = true;
bc7f75fa 1349 cleaned_count++;
0be3f55f 1350 dma_unmap_single(&pdev->dev, buffer_info->dma,
af667a29 1351 adapter->rx_ps_bsize0, DMA_FROM_DEVICE);
bc7f75fa
AK		 1352 buffer_info->dma = 0;
1353
af667a29 1354 /* see !EOP comment in other Rx routine */
b94b5028
JB		 1355 if (!(staterr & E1000_RXD_STAT_EOP))
1356 adapter->flags2 |= FLAG2_IS_DISCARDING;
1357
1358 if (adapter->flags2 & FLAG2_IS_DISCARDING) {
ef456f85 1359 e_dbg("Packet Split buffers didn't pick up the full packet\n");
bc7f75fa 1360 dev_kfree_skb_irq(skb);
b94b5028
JB		 1361 if (staterr & E1000_RXD_STAT_EOP)
1362 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1363 goto next_desc;
1364 }
1365
cf955e6c
BG		 1366 if (unlikely((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1367 !(netdev->features & NETIF_F_RXALL))) {
bc7f75fa
AK		 1368 dev_kfree_skb_irq(skb);
1369 goto next_desc;
1370 }
1371
1372 length = le16_to_cpu(rx_desc->wb.middle.length0);
1373
1374 if (!length) {
ef456f85 1375 e_dbg("Last part of the packet spanning multiple descriptors\n");
bc7f75fa
AK		 1376 dev_kfree_skb_irq(skb);
1377 goto next_desc;
1378 }
1379
1380 /* Good Receive */
1381 skb_put(skb, length);
1382
1383 {
e921eb1a 1384 /* this looks ugly, but it seems compiler issues make
0e15df49
BA		 1385 * it more efficient than reusing j
1386 */
1387 int l1 = le16_to_cpu(rx_desc->wb.upper.length[0]);
bc7f75fa 1388
e921eb1a 1389 /* page alloc/put takes too long and effects small
0e15df49
BA		 1390 * packet throughput, so unsplit small packets and
1391 * save the alloc/put only valid in softirq (napi)
1392 * context to call kmap_*
ad68076e 1393 */
0e15df49
BA		 1394 if (l1 && (l1 <= copybreak) &&
1395 ((length + l1) <= adapter->rx_ps_bsize0)) {
1396 u8 *vaddr;
1397
1398 ps_page = &buffer_info->ps_pages[0];
1399
e921eb1a 1400 /* there is no documentation about how to call
0e15df49
BA		 1401 * kmap_atomic, so we can't hold the mapping
1402 * very long
1403 */
1404 dma_sync_single_for_cpu(&pdev->dev,
1405 ps_page->dma,
1406 PAGE_SIZE,
1407 DMA_FROM_DEVICE);
9f393834 1408 vaddr = kmap_atomic(ps_page->page);
0e15df49 1409 memcpy(skb_tail_pointer(skb), vaddr, l1);
9f393834 1410 kunmap_atomic(vaddr);
0e15df49
BA		 1411 dma_sync_single_for_device(&pdev->dev,
1412 ps_page->dma,
1413 PAGE_SIZE,
1414 DMA_FROM_DEVICE);
1415
1416 /* remove the CRC */
0184039a
BG		 1417 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1418 if (!(netdev->features & NETIF_F_RXFCS))
1419 l1 -= 4;
1420 }
0e15df49
BA		 1421
1422 skb_put(skb, l1);
1423 goto copydone;
e80bd1d1 1424 } /* if */
bc7f75fa
AK		 1425 }
1426
1427 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
1428 length = le16_to_cpu(rx_desc->wb.upper.length[j]);
1429 if (!length)
1430 break;
1431
47f44e40 1432 ps_page = &buffer_info->ps_pages[j];
0be3f55f
NN		 1433 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1434 DMA_FROM_DEVICE);
bc7f75fa
AK		 1435 ps_page->dma = 0;
1436 skb_fill_page_desc(skb, j, ps_page->page, 0, length);
1437 ps_page->page = NULL;
1438 skb->len += length;
1439 skb->data_len += length;
98a045d7 1440 skb->truesize += PAGE_SIZE;
bc7f75fa
AK		 1441 }
1442
eb7c3adb
JK		 1443 /* strip the ethernet crc, problem is we're using pages now so
1444 * this whole operation can get a little cpu intensive
1445 */
0184039a
BG		 1446 if (!(adapter->flags2 & FLAG2_CRC_STRIPPING)) {
1447 if (!(netdev->features & NETIF_F_RXFCS))
1448 pskb_trim(skb, skb->len - 4);
1449 }
eb7c3adb 1450
bc7f75fa
AK		 1451copydone:
1452 total_rx_bytes += skb->len;
1453 total_rx_packets++;
1454
2e1706f2 1455 e1000_rx_checksum(adapter, staterr, skb);
bc7f75fa 1456
70495a50
BA		 1457 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1458
bc7f75fa 1459 if (rx_desc->wb.upper.header_status &
17e813ec 1460 cpu_to_le16(E1000_RXDPS_HDRSTAT_HDRSP))
bc7f75fa
AK		 1461 adapter->rx_hdr_split++;
1462
b67e1913
BA		 1463 e1000_receive_skb(adapter, netdev, skb, staterr,
1464 rx_desc->wb.middle.vlan);
bc7f75fa
AK		 1465
1466next_desc:
1467 rx_desc->wb.middle.status_error &= cpu_to_le32(~0xFF);
1468 buffer_info->skb = NULL;
1469
1470 /* return some buffers to hardware, one at a time is too slow */
1471 if (cleaned_count >= E1000_RX_BUFFER_WRITE) {
55aa6985 1472 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1473 GFP_ATOMIC);
bc7f75fa
AK		 1474 cleaned_count = 0;
1475 }
1476
1477 /* use prefetched values */
1478 rx_desc = next_rxd;
1479 buffer_info = next_buffer;
1480
1481 staterr = le32_to_cpu(rx_desc->wb.middle.status_error);
1482 }
1483 rx_ring->next_to_clean = i;
1484
1485 cleaned_count = e1000_desc_unused(rx_ring);
1486 if (cleaned_count)
55aa6985 1487 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
bc7f75fa 1488
bc7f75fa 1489 adapter->total_rx_bytes += total_rx_bytes;
7c25769f 1490 adapter->total_rx_packets += total_rx_packets;
bc7f75fa
AK		 1491 return cleaned;
1492}
1493
97ac8cae
BA		 1494/**
1495 * e1000_consume_page - helper function
1496 **/
1497static void e1000_consume_page(struct e1000_buffer *bi, struct sk_buff *skb,
66501f56 1498 u16 length)
97ac8cae
BA		 1499{
1500 bi->page = NULL;
1501 skb->len += length;
1502 skb->data_len += length;
98a045d7 1503 skb->truesize += PAGE_SIZE;
97ac8cae
BA		 1504}
1505
1506/**
1507 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1508 * @adapter: board private structure
1509 *
1510 * the return value indicates whether actual cleaning was done, there
1511 * is no guarantee that everything was cleaned
1512 **/
55aa6985
BA		 1513static bool e1000_clean_jumbo_rx_irq(struct e1000_ring *rx_ring, int *work_done,
1514 int work_to_do)
97ac8cae 1515{
55aa6985 1516 struct e1000_adapter *adapter = rx_ring->adapter;
97ac8cae
BA		 1517 struct net_device *netdev = adapter->netdev;
1518 struct pci_dev *pdev = adapter->pdev;
5f450212 1519 union e1000_rx_desc_extended *rx_desc, *next_rxd;
97ac8cae 1520 struct e1000_buffer *buffer_info, *next_buffer;
5f450212 1521 u32 length, staterr;
97ac8cae
BA		 1522 unsigned int i;
1523 int cleaned_count = 0;
1524 bool cleaned = false;
362e20ca 1525 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
17e813ec 1526 struct skb_shared_info *shinfo;
97ac8cae
BA		 1527
1528 i = rx_ring->next_to_clean;
5f450212
BA		 1529 rx_desc = E1000_RX_DESC_EXT(*rx_ring, i);
1530 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1531 buffer_info = &rx_ring->buffer_info[i];
1532
5f450212 1533 while (staterr & E1000_RXD_STAT_DD) {
97ac8cae 1534 struct sk_buff *skb;
97ac8cae
BA		 1535
1536 if (*work_done >= work_to_do)
1537 break;
1538 (*work_done)++;
837a1dba 1539 dma_rmb(); /* read descriptor and rx_buffer_info after status DD */
97ac8cae 1540
97ac8cae
BA		 1541 skb = buffer_info->skb;
1542 buffer_info->skb = NULL;
1543
1544 ++i;
1545 if (i == rx_ring->count)
1546 i = 0;
5f450212 1547 next_rxd = E1000_RX_DESC_EXT(*rx_ring, i);
97ac8cae
BA		 1548 prefetch(next_rxd);
1549
1550 next_buffer = &rx_ring->buffer_info[i];
1551
1552 cleaned = true;
1553 cleaned_count++;
0be3f55f
NN		 1554 dma_unmap_page(&pdev->dev, buffer_info->dma, PAGE_SIZE,
1555 DMA_FROM_DEVICE);
97ac8cae
BA		 1556 buffer_info->dma = 0;
1557
5f450212 1558 length = le16_to_cpu(rx_desc->wb.upper.length);
97ac8cae
BA		 1559
1560 /* errors is only valid for DD + EOP descriptors */
5f450212 1561 if (unlikely((staterr & E1000_RXD_STAT_EOP) &&
cf955e6c
BG		 1562 ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) &&
1563 !(netdev->features & NETIF_F_RXALL)))) {
5f450212
BA		 1564 /* recycle both page and skb */
1565 buffer_info->skb = skb;
1566 /* an error means any chain goes out the window too */
1567 if (rx_ring->rx_skb_top)
1568 dev_kfree_skb_irq(rx_ring->rx_skb_top);
1569 rx_ring->rx_skb_top = NULL;
1570 goto next_desc;
97ac8cae 1571 }
f0f1a172 1572#define rxtop (rx_ring->rx_skb_top)
5f450212 1573 if (!(staterr & E1000_RXD_STAT_EOP)) {
97ac8cae
BA		 1574 /* this descriptor is only the beginning (or middle) */
1575 if (!rxtop) {
1576 /* this is the beginning of a chain */
1577 rxtop = skb;
1578 skb_fill_page_desc(rxtop, 0, buffer_info->page,
f0ff4398 1579 0, length);
97ac8cae
BA		 1580 } else {
1581 /* this is the middle of a chain */
17e813ec
BA		 1582 shinfo = skb_shinfo(rxtop);
1583 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1584 buffer_info->page, 0,
1585 length);
97ac8cae
BA		 1586 /* re-use the skb, only consumed the page */
1587 buffer_info->skb = skb;
1588 }
1589 e1000_consume_page(buffer_info, rxtop, length);
1590 goto next_desc;
1591 } else {
1592 if (rxtop) {
1593 /* end of the chain */
17e813ec
BA		 1594 shinfo = skb_shinfo(rxtop);
1595 skb_fill_page_desc(rxtop, shinfo->nr_frags,
1596 buffer_info->page, 0,
1597 length);
97ac8cae 1598 /* re-use the current skb, we only consumed the
e921eb1a
BA		 1599 * page
1600 */
97ac8cae
BA		 1601 buffer_info->skb = skb;
1602 skb = rxtop;
1603 rxtop = NULL;
1604 e1000_consume_page(buffer_info, skb, length);
1605 } else {
1606 /* no chain, got EOP, this buf is the packet
e921eb1a
BA		 1607 * copybreak to save the put_page/alloc_page
1608 */
97ac8cae
BA		 1609 if (length <= copybreak &&
1610 skb_tailroom(skb) >= length) {
1611 u8 *vaddr;
4679026d 1612 vaddr = kmap_atomic(buffer_info->page);
97ac8cae
BA		 1613 memcpy(skb_tail_pointer(skb), vaddr,
1614 length);
4679026d 1615 kunmap_atomic(vaddr);
97ac8cae 1616 /* re-use the page, so don't erase
e921eb1a
BA		 1617 * buffer_info->page
1618 */
97ac8cae
BA		 1619 skb_put(skb, length);
1620 } else {
1621 skb_fill_page_desc(skb, 0,
f0ff4398
BA		 1622 buffer_info->page, 0,
1623 length);
97ac8cae 1624 e1000_consume_page(buffer_info, skb,
f0ff4398 1625 length);
97ac8cae
BA		 1626 }
1627 }
1628 }
1629
2e1706f2
BA		 1630 /* Receive Checksum Offload */
1631 e1000_rx_checksum(adapter, staterr, skb);
97ac8cae 1632
70495a50
BA		 1633 e1000_rx_hash(netdev, rx_desc->wb.lower.hi_dword.rss, skb);
1634
97ac8cae
BA		 1635 /* probably a little skewed due to removing CRC */
1636 total_rx_bytes += skb->len;
1637 total_rx_packets++;
1638
1639 /* eth type trans needs skb->data to point to something */
1640 if (!pskb_may_pull(skb, ETH_HLEN)) {
44defeb3 1641 e_err("pskb_may_pull failed.\n");
ef5ab89c 1642 dev_kfree_skb_irq(skb);
97ac8cae
BA		 1643 goto next_desc;
1644 }
1645
5f450212
BA		 1646 e1000_receive_skb(adapter, netdev, skb, staterr,
1647 rx_desc->wb.upper.vlan);
97ac8cae
BA		 1648
1649next_desc:
5f450212 1650 rx_desc->wb.upper.status_error &= cpu_to_le32(~0xFF);
97ac8cae
BA		 1651
1652 /* return some buffers to hardware, one at a time is too slow */
1653 if (unlikely(cleaned_count >= E1000_RX_BUFFER_WRITE)) {
55aa6985 1654 adapter->alloc_rx_buf(rx_ring, cleaned_count,
c2fed996 1655 GFP_ATOMIC);
97ac8cae
BA		 1656 cleaned_count = 0;
1657 }
1658
1659 /* use prefetched values */
1660 rx_desc = next_rxd;
1661 buffer_info = next_buffer;
5f450212
BA		 1662
1663 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
97ac8cae
BA		 1664 }
1665 rx_ring->next_to_clean = i;
1666
1667 cleaned_count = e1000_desc_unused(rx_ring);
1668 if (cleaned_count)
55aa6985 1669 adapter->alloc_rx_buf(rx_ring, cleaned_count, GFP_ATOMIC);
97ac8cae
BA		 1670
1671 adapter->total_rx_bytes += total_rx_bytes;
1672 adapter->total_rx_packets += total_rx_packets;
97ac8cae
BA		 1673 return cleaned;
1674}
1675
bc7f75fa
AK		 1676/**
1677 * e1000_clean_rx_ring - Free Rx Buffers per Queue
55aa6985 1678 * @rx_ring: Rx descriptor ring
bc7f75fa 1679 **/
55aa6985 1680static void e1000_clean_rx_ring(struct e1000_ring *rx_ring)
bc7f75fa 1681{
55aa6985 1682 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa
AK		 1683 struct e1000_buffer *buffer_info;
1684 struct e1000_ps_page *ps_page;
1685 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 1686 unsigned int i, j;
1687
1688 /* Free all the Rx ring sk_buffs */
1689 for (i = 0; i < rx_ring->count; i++) {
1690 buffer_info = &rx_ring->buffer_info[i];
1691 if (buffer_info->dma) {
1692 if (adapter->clean_rx == e1000_clean_rx_irq)
0be3f55f 1693 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1694 adapter->rx_buffer_len,
0be3f55f 1695 DMA_FROM_DEVICE);
97ac8cae 1696 else if (adapter->clean_rx == e1000_clean_jumbo_rx_irq)
0be3f55f 1697 dma_unmap_page(&pdev->dev, buffer_info->dma,
f0ff4398 1698 PAGE_SIZE, DMA_FROM_DEVICE);
bc7f75fa 1699 else if (adapter->clean_rx == e1000_clean_rx_irq_ps)
0be3f55f 1700 dma_unmap_single(&pdev->dev, buffer_info->dma,
bc7f75fa 1701 adapter->rx_ps_bsize0,
0be3f55f 1702 DMA_FROM_DEVICE);
bc7f75fa
AK		 1703 buffer_info->dma = 0;
1704 }
1705
97ac8cae
BA		 1706 if (buffer_info->page) {
1707 put_page(buffer_info->page);
1708 buffer_info->page = NULL;
1709 }
1710
bc7f75fa
AK		 1711 if (buffer_info->skb) {
1712 dev_kfree_skb(buffer_info->skb);
1713 buffer_info->skb = NULL;
1714 }
1715
1716 for (j = 0; j < PS_PAGE_BUFFERS; j++) {
47f44e40 1717 ps_page = &buffer_info->ps_pages[j];
bc7f75fa
AK		 1718 if (!ps_page->page)
1719 break;
0be3f55f
NN		 1720 dma_unmap_page(&pdev->dev, ps_page->dma, PAGE_SIZE,
1721 DMA_FROM_DEVICE);
bc7f75fa
AK		 1722 ps_page->dma = 0;
1723 put_page(ps_page->page);
1724 ps_page->page = NULL;
1725 }
1726 }
1727
1728 /* there also may be some cached data from a chained receive */
1729 if (rx_ring->rx_skb_top) {
1730 dev_kfree_skb(rx_ring->rx_skb_top);
1731 rx_ring->rx_skb_top = NULL;
1732 }
1733
bc7f75fa
AK		 1734 /* Zero out the descriptor ring */
1735 memset(rx_ring->desc, 0, rx_ring->size);
1736
1737 rx_ring->next_to_clean = 0;
1738 rx_ring->next_to_use = 0;
b94b5028 1739 adapter->flags2 &= ~FLAG2_IS_DISCARDING;
bc7f75fa
AK		 1740}
1741
a8f88ff5
JB		 1742static void e1000e_downshift_workaround(struct work_struct *work)
1743{
1744 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 1745 struct e1000_adapter,
1746 downshift_task);
a8f88ff5 1747
615b32af
JB		 1748 if (test_bit(__E1000_DOWN, &adapter->state))
1749 return;
1750
a8f88ff5
JB		 1751 e1000e_gig_downshift_workaround_ich8lan(&adapter->hw);
1752}
1753
bc7f75fa
AK		 1754/**
1755 * e1000_intr_msi - Interrupt Handler
1756 * @irq: interrupt number
1757 * @data: pointer to a network interface device structure
1758 **/
8bb62869 1759static irqreturn_t e1000_intr_msi(int __always_unused irq, void *data)
bc7f75fa
AK		 1760{
1761 struct net_device *netdev = data;
1762 struct e1000_adapter *adapter = netdev_priv(netdev);
1763 struct e1000_hw *hw = &adapter->hw;
1764 u32 icr = er32(ICR);
1765
e921eb1a 1766 /* read ICR disables interrupts using IAM */
573cca8c 1767 if (icr & E1000_ICR_LSC) {
f92518dd 1768 hw->mac.get_link_status = true;
e921eb1a 1769 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1770 * disconnect (LSC) before accessing any PHY registers
1771 */
bc7f75fa
AK		 1772 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1773 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1774 schedule_work(&adapter->downshift_task);
bc7f75fa 1775
e921eb1a 1776 /* 80003ES2LAN workaround-- For packet buffer work-around on
bc7f75fa 1777 * link down event; disable receives here in the ISR and reset
ad68076e
BA		 1778 * adapter in watchdog
1779 */
bc7f75fa
AK		 1780 if (netif_carrier_ok(netdev) &&
1781 adapter->flags & FLAG_RX_NEEDS_RESTART) {
1782 /* disable receives */
1783 u32 rctl = er32(RCTL);
6cf08d1c 1784
bc7f75fa 1785 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1786 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1787 }
1788 /* guard against interrupt when we're going down */
1789 if (!test_bit(__E1000_DOWN, &adapter->state))
1790 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1791 }
1792
94fb848b 1793 /* Reset on uncorrectable ECC error */
79849ebc
DE		 1794 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
1795 (hw->mac.type == e1000_pch_spt))) {
94fb848b
BA		 1796 u32 pbeccsts = er32(PBECCSTS);
1797
1798 adapter->corr_errors +=
1799 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1800 adapter->uncorr_errors +=
1801 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1802 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1803
1804 /* Do the reset outside of interrupt context */
1805 schedule_work(&adapter->reset_task);
1806
1807 /* return immediately since reset is imminent */
1808 return IRQ_HANDLED;
1809 }
1810
288379f0 1811 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1812 adapter->total_tx_bytes = 0;
1813 adapter->total_tx_packets = 0;
1814 adapter->total_rx_bytes = 0;
1815 adapter->total_rx_packets = 0;
288379f0 1816 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1817 }
1818
1819 return IRQ_HANDLED;
1820}
1821
1822/**
1823 * e1000_intr - Interrupt Handler
1824 * @irq: interrupt number
1825 * @data: pointer to a network interface device structure
1826 **/
8bb62869 1827static irqreturn_t e1000_intr(int __always_unused irq, void *data)
bc7f75fa
AK		 1828{
1829 struct net_device *netdev = data;
1830 struct e1000_adapter *adapter = netdev_priv(netdev);
1831 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 1832 u32 rctl, icr = er32(ICR);
4662e82b 1833
a68ea775 1834 if (!icr || test_bit(__E1000_DOWN, &adapter->state))
e80bd1d1 1835 return IRQ_NONE; /* Not our interrupt */
bc7f75fa 1836
e921eb1a 1837 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
ad68076e
BA		 1838 * not set, then the adapter didn't send an interrupt
1839 */
bc7f75fa
AK		 1840 if (!(icr & E1000_ICR_INT_ASSERTED))
1841 return IRQ_NONE;
1842
e921eb1a 1843 /* Interrupt Auto-Mask...upon reading ICR,
ad68076e
BA		 1844 * interrupts are masked. No need for the
1845 * IMC write
1846 */
bc7f75fa 1847
573cca8c 1848 if (icr & E1000_ICR_LSC) {
f92518dd 1849 hw->mac.get_link_status = true;
e921eb1a 1850 /* ICH8 workaround-- Call gig speed drop workaround on cable
ad68076e
BA		 1851 * disconnect (LSC) before accessing any PHY registers
1852 */
bc7f75fa
AK		 1853 if ((adapter->flags & FLAG_LSC_GIG_SPEED_DROP) &&
1854 (!(er32(STATUS) & E1000_STATUS_LU)))
a8f88ff5 1855 schedule_work(&adapter->downshift_task);
bc7f75fa 1856
e921eb1a 1857 /* 80003ES2LAN workaround--
bc7f75fa
AK		 1858 * For packet buffer work-around on link down event;
1859 * disable receives here in the ISR and
1860 * reset adapter in watchdog
1861 */
1862 if (netif_carrier_ok(netdev) &&
1863 (adapter->flags & FLAG_RX_NEEDS_RESTART)) {
1864 /* disable receives */
1865 rctl = er32(RCTL);
1866 ew32(RCTL, rctl & ~E1000_RCTL_EN);
12d43f7d 1867 adapter->flags |= FLAG_RESTART_NOW;
bc7f75fa
AK		 1868 }
1869 /* guard against interrupt when we're going down */
1870 if (!test_bit(__E1000_DOWN, &adapter->state))
1871 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1872 }
1873
94fb848b 1874 /* Reset on uncorrectable ECC error */
79849ebc
DE		 1875 if ((icr & E1000_ICR_ECCER) && ((hw->mac.type == e1000_pch_lpt) ||
1876 (hw->mac.type == e1000_pch_spt))) {
94fb848b
BA		 1877 u32 pbeccsts = er32(PBECCSTS);
1878
1879 adapter->corr_errors +=
1880 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
1881 adapter->uncorr_errors +=
1882 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
1883 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
1884
1885 /* Do the reset outside of interrupt context */
1886 schedule_work(&adapter->reset_task);
1887
1888 /* return immediately since reset is imminent */
1889 return IRQ_HANDLED;
1890 }
1891
288379f0 1892 if (napi_schedule_prep(&adapter->napi)) {
bc7f75fa
AK		 1893 adapter->total_tx_bytes = 0;
1894 adapter->total_tx_packets = 0;
1895 adapter->total_rx_bytes = 0;
1896 adapter->total_rx_packets = 0;
288379f0 1897 __napi_schedule(&adapter->napi);
bc7f75fa
AK		 1898 }
1899
1900 return IRQ_HANDLED;
1901}
1902
8bb62869 1903static irqreturn_t e1000_msix_other(int __always_unused irq, void *data)
4662e82b
BA		 1904{
1905 struct net_device *netdev = data;
1906 struct e1000_adapter *adapter = netdev_priv(netdev);
1907 struct e1000_hw *hw = &adapter->hw;
4662e82b 1908
16ecba59 1909 hw->mac.get_link_status = true;
4662e82b 1910
16ecba59
BP		 1911 /* guard against interrupt when we're going down */
1912 if (!test_bit(__E1000_DOWN, &adapter->state)) {
1913 mod_timer(&adapter->watchdog_timer, jiffies + 1);
1914 ew32(IMS, E1000_IMS_OTHER);
4662e82b
BA		 1915 }
1916
4662e82b
BA		 1917 return IRQ_HANDLED;
1918}
1919
8bb62869 1920static irqreturn_t e1000_intr_msix_tx(int __always_unused irq, void *data)
4662e82b
BA		 1921{
1922 struct net_device *netdev = data;
1923 struct e1000_adapter *adapter = netdev_priv(netdev);
1924 struct e1000_hw *hw = &adapter->hw;
1925 struct e1000_ring *tx_ring = adapter->tx_ring;
1926
4662e82b
BA		 1927 adapter->total_tx_bytes = 0;
1928 adapter->total_tx_packets = 0;
1929
55aa6985 1930 if (!e1000_clean_tx_irq(tx_ring))
4662e82b
BA		 1931 /* Ring was not completely cleaned, so fire another interrupt */
1932 ew32(ICS, tx_ring->ims_val);
1933
0a8047ac
BP		 1934 if (!test_bit(__E1000_DOWN, &adapter->state))
1935 ew32(IMS, adapter->tx_ring->ims_val);
1936
4662e82b
BA		 1937 return IRQ_HANDLED;
1938}
1939
8bb62869 1940static irqreturn_t e1000_intr_msix_rx(int __always_unused irq, void *data)
4662e82b
BA		 1941{
1942 struct net_device *netdev = data;
1943 struct e1000_adapter *adapter = netdev_priv(netdev);
55aa6985 1944 struct e1000_ring *rx_ring = adapter->rx_ring;
4662e82b
BA		 1945
1946 /* Write the ITR value calculated at the end of the
1947 * previous interrupt.
1948 */
55aa6985 1949 if (rx_ring->set_itr) {
b77ac46b
DF		 1950 u32 itr = rx_ring->itr_val ?
1951 1000000000 / (rx_ring->itr_val * 256) : 0;
1952
1953 writel(itr, rx_ring->itr_register);
55aa6985 1954 rx_ring->set_itr = 0;
4662e82b
BA		 1955 }
1956
288379f0 1957 if (napi_schedule_prep(&adapter->napi)) {
4662e82b
BA		 1958 adapter->total_rx_bytes = 0;
1959 adapter->total_rx_packets = 0;
288379f0 1960 __napi_schedule(&adapter->napi);
4662e82b
BA		 1961 }
1962 return IRQ_HANDLED;
1963}
1964
1965/**
1966 * e1000_configure_msix - Configure MSI-X hardware
1967 *
1968 * e1000_configure_msix sets up the hardware to properly
1969 * generate MSI-X interrupts.
1970 **/
1971static void e1000_configure_msix(struct e1000_adapter *adapter)
1972{
1973 struct e1000_hw *hw = &adapter->hw;
1974 struct e1000_ring *rx_ring = adapter->rx_ring;
1975 struct e1000_ring *tx_ring = adapter->tx_ring;
1976 int vector = 0;
1977 u32 ctrl_ext, ivar = 0;
1978
1979 adapter->eiac_mask = 0;
1980
1981 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1982 if (hw->mac.type == e1000_82574) {
1983 u32 rfctl = er32(RFCTL);
6cf08d1c 1984
4662e82b
BA		 1985 rfctl |= E1000_RFCTL_ACK_DIS;
1986 ew32(RFCTL, rfctl);
1987 }
1988
4662e82b
BA		 1989 /* Configure Rx vector */
1990 rx_ring->ims_val = E1000_IMS_RXQ0;
1991 adapter->eiac_mask |= rx_ring->ims_val;
1992 if (rx_ring->itr_val)
1993 writel(1000000000 / (rx_ring->itr_val * 256),
c5083cf6 1994 rx_ring->itr_register);
4662e82b 1995 else
c5083cf6 1996 writel(1, rx_ring->itr_register);
4662e82b
BA		 1997 ivar = E1000_IVAR_INT_ALLOC_VALID | vector;
1998
1999 /* Configure Tx vector */
2000 tx_ring->ims_val = E1000_IMS_TXQ0;
2001 vector++;
2002 if (tx_ring->itr_val)
2003 writel(1000000000 / (tx_ring->itr_val * 256),
c5083cf6 2004 tx_ring->itr_register);
4662e82b 2005 else
c5083cf6 2006 writel(1, tx_ring->itr_register);
4662e82b
BA		 2007 adapter->eiac_mask |= tx_ring->ims_val;
2008 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 8);
2009
2010 /* set vector for Other Causes, e.g. link changes */
2011 vector++;
2012 ivar |= ((E1000_IVAR_INT_ALLOC_VALID | vector) << 16);
2013 if (rx_ring->itr_val)
2014 writel(1000000000 / (rx_ring->itr_val * 256),
2015 hw->hw_addr + E1000_EITR_82574(vector));
2016 else
2017 writel(1, hw->hw_addr + E1000_EITR_82574(vector));
16ecba59 2018 adapter->eiac_mask |= E1000_IMS_OTHER;
4662e82b
BA		 2019
2020 /* Cause Tx interrupts on every write back */
18dd2392 2021 ivar |= BIT(31);
4662e82b
BA		 2022
2023 ew32(IVAR, ivar);
2024
2025 /* enable MSI-X PBA support */
0a8047ac
BP		 2026 ctrl_ext = er32(CTRL_EXT) & ~E1000_CTRL_EXT_IAME;
2027 ctrl_ext |= E1000_CTRL_EXT_PBA_CLR | E1000_CTRL_EXT_EIAME;
4662e82b
BA		 2028 ew32(CTRL_EXT, ctrl_ext);
2029 e1e_flush();
2030}
2031
2032void e1000e_reset_interrupt_capability(struct e1000_adapter *adapter)
2033{
2034 if (adapter->msix_entries) {
2035 pci_disable_msix(adapter->pdev);
2036 kfree(adapter->msix_entries);
2037 adapter->msix_entries = NULL;
2038 } else if (adapter->flags & FLAG_MSI_ENABLED) {
2039 pci_disable_msi(adapter->pdev);
2040 adapter->flags &= ~FLAG_MSI_ENABLED;
2041 }
4662e82b
BA		 2042}
2043
2044/**
2045 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2046 *
2047 * Attempt to configure interrupts using the best available
2048 * capabilities of the hardware and kernel.
2049 **/
2050void e1000e_set_interrupt_capability(struct e1000_adapter *adapter)
2051{
2052 int err;
8e86acd7 2053 int i;
4662e82b
BA		 2054
2055 switch (adapter->int_mode) {
2056 case E1000E_INT_MODE_MSIX:
2057 if (adapter->flags & FLAG_HAS_MSIX) {
8e86acd7
JK		 2058 adapter->num_vectors = 3; /* RxQ0, TxQ0 and other */
2059 adapter->msix_entries = kcalloc(adapter->num_vectors,
17e813ec
BA		 2060 sizeof(struct
2061 msix_entry),
2062 GFP_KERNEL);
4662e82b 2063 if (adapter->msix_entries) {
0cc7c959
AG		 2064 struct e1000_adapter *a = adapter;
2065
8e86acd7 2066 for (i = 0; i < adapter->num_vectors; i++)
4662e82b
BA		 2067 adapter->msix_entries[i].entry = i;
2068
0cc7c959
AG		 2069 err = pci_enable_msix_range(a->pdev,
2070 a->msix_entries,
2071 a->num_vectors,
2072 a->num_vectors);
2073 if (err > 0)
4662e82b
BA		 2074 return;
2075 }
2076 /* MSI-X failed, so fall through and try MSI */
ef456f85 2077 e_err("Failed to initialize MSI-X interrupts. Falling back to MSI interrupts.\n");
4662e82b
BA		 2078 e1000e_reset_interrupt_capability(adapter);
2079 }
2080 adapter->int_mode = E1000E_INT_MODE_MSI;
2081 /* Fall through */
2082 case E1000E_INT_MODE_MSI:
2083 if (!pci_enable_msi(adapter->pdev)) {
2084 adapter->flags |= FLAG_MSI_ENABLED;
2085 } else {
2086 adapter->int_mode = E1000E_INT_MODE_LEGACY;
ef456f85 2087 e_err("Failed to initialize MSI interrupts. Falling back to legacy interrupts.\n");
4662e82b
BA		 2088 }
2089 /* Fall through */
2090 case E1000E_INT_MODE_LEGACY:
2091 /* Don't do anything; this is the system default */
2092 break;
2093 }
8e86acd7
JK		 2094
2095 /* store the number of vectors being used */
2096 adapter->num_vectors = 1;
4662e82b
BA		 2097}
2098
2099/**
2100 * e1000_request_msix - Initialize MSI-X interrupts
2101 *
2102 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2103 * kernel.
2104 **/
2105static int e1000_request_msix(struct e1000_adapter *adapter)
2106{
2107 struct net_device *netdev = adapter->netdev;
2108 int err = 0, vector = 0;
2109
2110 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2111 snprintf(adapter->rx_ring->name,
2112 sizeof(adapter->rx_ring->name) - 1,
2113 "%s-rx-0", netdev->name);
4662e82b
BA		 2114 else
2115 memcpy(adapter->rx_ring->name, netdev->name, IFNAMSIZ);
2116 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2117 e1000_intr_msix_rx, 0, adapter->rx_ring->name,
4662e82b
BA		 2118 netdev);
2119 if (err)
5015e53a 2120 return err;
c5083cf6
BA		 2121 adapter->rx_ring->itr_register = adapter->hw.hw_addr +
2122 E1000_EITR_82574(vector);
4662e82b
BA		 2123 adapter->rx_ring->itr_val = adapter->itr;
2124 vector++;
2125
2126 if (strlen(netdev->name) < (IFNAMSIZ - 5))
79f5e840
BA		 2127 snprintf(adapter->tx_ring->name,
2128 sizeof(adapter->tx_ring->name) - 1,
2129 "%s-tx-0", netdev->name);
4662e82b
BA		 2130 else
2131 memcpy(adapter->tx_ring->name, netdev->name, IFNAMSIZ);
2132 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2133 e1000_intr_msix_tx, 0, adapter->tx_ring->name,
4662e82b
BA		 2134 netdev);
2135 if (err)
5015e53a 2136 return err;
c5083cf6
BA		 2137 adapter->tx_ring->itr_register = adapter->hw.hw_addr +
2138 E1000_EITR_82574(vector);
4662e82b
BA		 2139 adapter->tx_ring->itr_val = adapter->itr;
2140 vector++;
2141
2142 err = request_irq(adapter->msix_entries[vector].vector,
a0607fd3 2143 e1000_msix_other, 0, netdev->name, netdev);
4662e82b 2144 if (err)
5015e53a 2145 return err;
4662e82b
BA		 2146
2147 e1000_configure_msix(adapter);
5015e53a 2148
4662e82b 2149 return 0;
4662e82b
BA		 2150}
2151
f8d59f78
BA		 2152/**
2153 * e1000_request_irq - initialize interrupts
2154 *
2155 * Attempts to configure interrupts using the best available
2156 * capabilities of the hardware and kernel.
2157 **/
bc7f75fa
AK		 2158static int e1000_request_irq(struct e1000_adapter *adapter)
2159{
2160 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 2161 int err;
2162
4662e82b
BA		 2163 if (adapter->msix_entries) {
2164 err = e1000_request_msix(adapter);
2165 if (!err)
2166 return err;
2167 /* fall back to MSI */
2168 e1000e_reset_interrupt_capability(adapter);
2169 adapter->int_mode = E1000E_INT_MODE_MSI;
2170 e1000e_set_interrupt_capability(adapter);
bc7f75fa 2171 }
4662e82b 2172 if (adapter->flags & FLAG_MSI_ENABLED) {
a0607fd3 2173 err = request_irq(adapter->pdev->irq, e1000_intr_msi, 0,
4662e82b
BA		 2174 netdev->name, netdev);
2175 if (!err)
2176 return err;
bc7f75fa 2177
4662e82b
BA		 2178 /* fall back to legacy interrupt */
2179 e1000e_reset_interrupt_capability(adapter);
2180 adapter->int_mode = E1000E_INT_MODE_LEGACY;
bc7f75fa
AK		 2181 }
2182
a0607fd3 2183 err = request_irq(adapter->pdev->irq, e1000_intr, IRQF_SHARED,
4662e82b
BA		 2184 netdev->name, netdev);
2185 if (err)
2186 e_err("Unable to allocate interrupt, Error: %d\n", err);
2187
bc7f75fa
AK		 2188 return err;
2189}
2190
2191static void e1000_free_irq(struct e1000_adapter *adapter)
2192{
2193 struct net_device *netdev = adapter->netdev;
2194
4662e82b
BA		 2195 if (adapter->msix_entries) {
2196 int vector = 0;
2197
2198 free_irq(adapter->msix_entries[vector].vector, netdev);
2199 vector++;
2200
2201 free_irq(adapter->msix_entries[vector].vector, netdev);
2202 vector++;
2203
2204 /* Other Causes interrupt vector */
2205 free_irq(adapter->msix_entries[vector].vector, netdev);
2206 return;
bc7f75fa 2207 }
4662e82b
BA		 2208
2209 free_irq(adapter->pdev->irq, netdev);
bc7f75fa
AK		 2210}
2211
2212/**
2213 * e1000_irq_disable - Mask off interrupt generation on the NIC
2214 **/
2215static void e1000_irq_disable(struct e1000_adapter *adapter)
2216{
2217 struct e1000_hw *hw = &adapter->hw;
2218
bc7f75fa 2219 ew32(IMC, ~0);
4662e82b
BA		 2220 if (adapter->msix_entries)
2221 ew32(EIAC_82574, 0);
bc7f75fa 2222 e1e_flush();
8e86acd7
JK		 2223
2224 if (adapter->msix_entries) {
2225 int i;
6cf08d1c 2226
8e86acd7
JK		 2227 for (i = 0; i < adapter->num_vectors; i++)
2228 synchronize_irq(adapter->msix_entries[i].vector);
2229 } else {
2230 synchronize_irq(adapter->pdev->irq);
2231 }
bc7f75fa
AK		 2232}
2233
2234/**
2235 * e1000_irq_enable - Enable default interrupt generation settings
2236 **/
2237static void e1000_irq_enable(struct e1000_adapter *adapter)
2238{
2239 struct e1000_hw *hw = &adapter->hw;
2240
4662e82b
BA		 2241 if (adapter->msix_entries) {
2242 ew32(EIAC_82574, adapter->eiac_mask & E1000_EIAC_MASK_82574);
16ecba59 2243 ew32(IMS, adapter->eiac_mask | E1000_IMS_LSC);
79849ebc
DE		 2244 } else if ((hw->mac.type == e1000_pch_lpt) ||
2245 (hw->mac.type == e1000_pch_spt)) {
94fb848b 2246 ew32(IMS, IMS_ENABLE_MASK | E1000_IMS_ECCER);
4662e82b
BA		 2247 } else {
2248 ew32(IMS, IMS_ENABLE_MASK);
2249 }
74ef9c39 2250 e1e_flush();
bc7f75fa
AK		 2251}
2252
2253/**
31dbe5b4 2254 * e1000e_get_hw_control - get control of the h/w from f/w
bc7f75fa
AK		 2255 * @adapter: address of board private structure
2256 *
31dbe5b4 2257 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2258 * For ASF and Pass Through versions of f/w this means that
2259 * the driver is loaded. For AMT version (only with 82573)
2260 * of the f/w this means that the network i/f is open.
2261 **/
31dbe5b4 2262void e1000e_get_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2263{
2264 struct e1000_hw *hw = &adapter->hw;
2265 u32 ctrl_ext;
2266 u32 swsm;
2267
2268 /* Let firmware know the driver has taken over */
2269 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2270 swsm = er32(SWSM);
2271 ew32(SWSM, swsm | E1000_SWSM_DRV_LOAD);
2272 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2273 ctrl_ext = er32(CTRL_EXT);
ad68076e 2274 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2275 }
2276}
2277
2278/**
31dbe5b4 2279 * e1000e_release_hw_control - release control of the h/w to f/w
bc7f75fa
AK		 2280 * @adapter: address of board private structure
2281 *
31dbe5b4 2282 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
bc7f75fa
AK		 2283 * For ASF and Pass Through versions of f/w this means that the
2284 * driver is no longer loaded. For AMT version (only with 82573) i
2285 * of the f/w this means that the network i/f is closed.
2286 *
2287 **/
31dbe5b4 2288void e1000e_release_hw_control(struct e1000_adapter *adapter)
bc7f75fa
AK		 2289{
2290 struct e1000_hw *hw = &adapter->hw;
2291 u32 ctrl_ext;
2292 u32 swsm;
2293
2294 /* Let firmware taken over control of h/w */
2295 if (adapter->flags & FLAG_HAS_SWSM_ON_LOAD) {
2296 swsm = er32(SWSM);
2297 ew32(SWSM, swsm & ~E1000_SWSM_DRV_LOAD);
2298 } else if (adapter->flags & FLAG_HAS_CTRLEXT_ON_LOAD) {
2299 ctrl_ext = er32(CTRL_EXT);
ad68076e 2300 ew32(CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
bc7f75fa
AK		 2301 }
2302}
2303
bc7f75fa 2304/**
49ce9c2c 2305 * e1000_alloc_ring_dma - allocate memory for a ring structure
bc7f75fa
AK		 2306 **/
2307static int e1000_alloc_ring_dma(struct e1000_adapter *adapter,
2308 struct e1000_ring *ring)
2309{
2310 struct pci_dev *pdev = adapter->pdev;
2311
2312 ring->desc = dma_alloc_coherent(&pdev->dev, ring->size, &ring->dma,
2313 GFP_KERNEL);
2314 if (!ring->desc)
2315 return -ENOMEM;
2316
2317 return 0;
2318}
2319
2320/**
2321 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
55aa6985 2322 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2323 *
2324 * Return 0 on success, negative on failure
2325 **/
55aa6985 2326int e1000e_setup_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2327{
55aa6985 2328 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2329 int err = -ENOMEM, size;
2330
2331 size = sizeof(struct e1000_buffer) * tx_ring->count;
89bf67f1 2332 tx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2333 if (!tx_ring->buffer_info)
2334 goto err;
bc7f75fa
AK		 2335
2336 /* round up to nearest 4K */
2337 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc);
2338 tx_ring->size = ALIGN(tx_ring->size, 4096);
2339
2340 err = e1000_alloc_ring_dma(adapter, tx_ring);
2341 if (err)
2342 goto err;
2343
2344 tx_ring->next_to_use = 0;
2345 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2346
2347 return 0;
2348err:
2349 vfree(tx_ring->buffer_info);
44defeb3 2350 e_err("Unable to allocate memory for the transmit descriptor ring\n");
bc7f75fa
AK		 2351 return err;
2352}
2353
2354/**
2355 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
55aa6985 2356 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2357 *
2358 * Returns 0 on success, negative on failure
2359 **/
55aa6985 2360int e1000e_setup_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2361{
55aa6985 2362 struct e1000_adapter *adapter = rx_ring->adapter;
47f44e40
AK		 2363 struct e1000_buffer *buffer_info;
2364 int i, size, desc_len, err = -ENOMEM;
bc7f75fa
AK		 2365
2366 size = sizeof(struct e1000_buffer) * rx_ring->count;
89bf67f1 2367 rx_ring->buffer_info = vzalloc(size);
bc7f75fa
AK		 2368 if (!rx_ring->buffer_info)
2369 goto err;
bc7f75fa 2370
47f44e40
AK		 2371 for (i = 0; i < rx_ring->count; i++) {
2372 buffer_info = &rx_ring->buffer_info[i];
2373 buffer_info->ps_pages = kcalloc(PS_PAGE_BUFFERS,
2374 sizeof(struct e1000_ps_page),
2375 GFP_KERNEL);
2376 if (!buffer_info->ps_pages)
2377 goto err_pages;
2378 }
bc7f75fa
AK		 2379
2380 desc_len = sizeof(union e1000_rx_desc_packet_split);
2381
2382 /* Round up to nearest 4K */
2383 rx_ring->size = rx_ring->count * desc_len;
2384 rx_ring->size = ALIGN(rx_ring->size, 4096);
2385
2386 err = e1000_alloc_ring_dma(adapter, rx_ring);
2387 if (err)
47f44e40 2388 goto err_pages;
bc7f75fa
AK		 2389
2390 rx_ring->next_to_clean = 0;
2391 rx_ring->next_to_use = 0;
2392 rx_ring->rx_skb_top = NULL;
2393
2394 return 0;
47f44e40
AK		 2395
2396err_pages:
2397 for (i = 0; i < rx_ring->count; i++) {
2398 buffer_info = &rx_ring->buffer_info[i];
2399 kfree(buffer_info->ps_pages);
2400 }
bc7f75fa
AK		 2401err:
2402 vfree(rx_ring->buffer_info);
e9262447 2403 e_err("Unable to allocate memory for the receive descriptor ring\n");
bc7f75fa
AK		 2404 return err;
2405}
2406
2407/**
2408 * e1000_clean_tx_ring - Free Tx Buffers
55aa6985 2409 * @tx_ring: Tx descriptor ring
bc7f75fa 2410 **/
55aa6985 2411static void e1000_clean_tx_ring(struct e1000_ring *tx_ring)
bc7f75fa 2412{
55aa6985 2413 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 2414 struct e1000_buffer *buffer_info;
2415 unsigned long size;
2416 unsigned int i;
2417
2418 for (i = 0; i < tx_ring->count; i++) {
2419 buffer_info = &tx_ring->buffer_info[i];
55aa6985 2420 e1000_put_txbuf(tx_ring, buffer_info);
bc7f75fa
AK		 2421 }
2422
3f0cfa3b 2423 netdev_reset_queue(adapter->netdev);
bc7f75fa
AK		 2424 size = sizeof(struct e1000_buffer) * tx_ring->count;
2425 memset(tx_ring->buffer_info, 0, size);
2426
2427 memset(tx_ring->desc, 0, tx_ring->size);
2428
2429 tx_ring->next_to_use = 0;
2430 tx_ring->next_to_clean = 0;
bc7f75fa
AK		 2431}
2432
2433/**
2434 * e1000e_free_tx_resources - Free Tx Resources per Queue
55aa6985 2435 * @tx_ring: Tx descriptor ring
bc7f75fa
AK		 2436 *
2437 * Free all transmit software resources
2438 **/
55aa6985 2439void e1000e_free_tx_resources(struct e1000_ring *tx_ring)
bc7f75fa 2440{
55aa6985 2441 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 2442 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 2443
55aa6985 2444 e1000_clean_tx_ring(tx_ring);
bc7f75fa
AK		 2445
2446 vfree(tx_ring->buffer_info);
2447 tx_ring->buffer_info = NULL;
2448
2449 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
2450 tx_ring->dma);
2451 tx_ring->desc = NULL;
2452}
2453
2454/**
2455 * e1000e_free_rx_resources - Free Rx Resources
55aa6985 2456 * @rx_ring: Rx descriptor ring
bc7f75fa
AK		 2457 *
2458 * Free all receive software resources
2459 **/
55aa6985 2460void e1000e_free_rx_resources(struct e1000_ring *rx_ring)
bc7f75fa 2461{
55aa6985 2462 struct e1000_adapter *adapter = rx_ring->adapter;
bc7f75fa 2463 struct pci_dev *pdev = adapter->pdev;
47f44e40 2464 int i;
bc7f75fa 2465
55aa6985 2466 e1000_clean_rx_ring(rx_ring);
bc7f75fa 2467
b1cdfead 2468 for (i = 0; i < rx_ring->count; i++)
47f44e40 2469 kfree(rx_ring->buffer_info[i].ps_pages);
47f44e40 2470
bc7f75fa
AK		 2471 vfree(rx_ring->buffer_info);
2472 rx_ring->buffer_info = NULL;
2473
bc7f75fa
AK		 2474 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
2475 rx_ring->dma);
2476 rx_ring->desc = NULL;
2477}
2478
2479/**
2480 * e1000_update_itr - update the dynamic ITR value based on statistics
489815ce
AK		 2481 * @adapter: pointer to adapter
2482 * @itr_setting: current adapter->itr
2483 * @packets: the number of packets during this measurement interval
2484 * @bytes: the number of bytes during this measurement interval
2485 *
bc7f75fa
AK		 2486 * Stores a new ITR value based on packets and byte
2487 * counts during the last interrupt. The advantage of per interrupt
2488 * computation is faster updates and more accurate ITR for the current
2489 * traffic pattern. Constants in this function were computed
2490 * based on theoretical maximum wire speed and thresholds were set based
2491 * on testing data as well as attempting to minimize response time
4662e82b
BA		 2492 * while increasing bulk throughput. This functionality is controlled
2493 * by the InterruptThrottleRate module parameter.
bc7f75fa 2494 **/
8bb62869 2495static unsigned int e1000_update_itr(u16 itr_setting, int packets, int bytes)
bc7f75fa
AK		 2496{
2497 unsigned int retval = itr_setting;
2498
2499 if (packets == 0)
5015e53a 2500 return itr_setting;
bc7f75fa
AK		 2501
2502 switch (itr_setting) {
2503 case lowest_latency:
2504 /* handle TSO and jumbo frames */
362e20ca 2505 if (bytes / packets > 8000)
bc7f75fa 2506 retval = bulk_latency;
b1cdfead 2507 else if ((packets < 5) && (bytes > 512))
bc7f75fa 2508 retval = low_latency;
bc7f75fa 2509 break;
e80bd1d1 2510 case low_latency: /* 50 usec aka 20000 ints/s */
bc7f75fa
AK		 2511 if (bytes > 10000) {
2512 /* this if handles the TSO accounting */
362e20ca 2513 if (bytes / packets > 8000)
bc7f75fa 2514 retval = bulk_latency;
362e20ca 2515 else if ((packets < 10) || ((bytes / packets) > 1200))
bc7f75fa 2516 retval = bulk_latency;
b1cdfead 2517 else if ((packets > 35))
bc7f75fa 2518 retval = lowest_latency;
362e20ca 2519 } else if (bytes / packets > 2000) {
bc7f75fa
AK		 2520 retval = bulk_latency;
2521 } else if (packets <= 2 && bytes < 512) {
2522 retval = lowest_latency;
2523 }
2524 break;
e80bd1d1 2525 case bulk_latency: /* 250 usec aka 4000 ints/s */
bc7f75fa 2526 if (bytes > 25000) {
b1cdfead 2527 if (packets > 35)
bc7f75fa 2528 retval = low_latency;
bc7f75fa
AK		 2529 } else if (bytes < 6000) {
2530 retval = low_latency;
2531 }
2532 break;
2533 }
2534
bc7f75fa
AK		 2535 return retval;
2536}
2537
2538static void e1000_set_itr(struct e1000_adapter *adapter)
2539{
bc7f75fa
AK		 2540 u16 current_itr;
2541 u32 new_itr = adapter->itr;
2542
2543 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2544 if (adapter->link_speed != SPEED_1000) {
2545 current_itr = 0;
2546 new_itr = 4000;
2547 goto set_itr_now;
2548 }
2549
828bac87
BA		 2550 if (adapter->flags2 & FLAG2_DISABLE_AIM) {
2551 new_itr = 0;
2552 goto set_itr_now;
2553 }
2554
8bb62869
BA		 2555 adapter->tx_itr = e1000_update_itr(adapter->tx_itr,
2556 adapter->total_tx_packets,
2557 adapter->total_tx_bytes);
bc7f75fa
AK		 2558 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2559 if (adapter->itr_setting == 3 && adapter->tx_itr == lowest_latency)
2560 adapter->tx_itr = low_latency;
2561
8bb62869
BA		 2562 adapter->rx_itr = e1000_update_itr(adapter->rx_itr,
2563 adapter->total_rx_packets,
2564 adapter->total_rx_bytes);
bc7f75fa
AK		 2565 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2566 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2567 adapter->rx_itr = low_latency;
2568
2569 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2570
bc7f75fa 2571 /* counts and packets in update_itr are dependent on these numbers */
33550cec 2572 switch (current_itr) {
bc7f75fa
AK		 2573 case lowest_latency:
2574 new_itr = 70000;
2575 break;
2576 case low_latency:
e80bd1d1 2577 new_itr = 20000; /* aka hwitr = ~200 */
bc7f75fa
AK		 2578 break;
2579 case bulk_latency:
2580 new_itr = 4000;
2581 break;
2582 default:
2583 break;
2584 }
2585
2586set_itr_now:
2587 if (new_itr != adapter->itr) {
e921eb1a 2588 /* this attempts to bias the interrupt rate towards Bulk
bc7f75fa 2589 * by adding intermediate steps when interrupt rate is
ad68076e
BA		 2590 * increasing
2591 */
bc7f75fa 2592 new_itr = new_itr > adapter->itr ?
f0ff4398 2593 min(adapter->itr + (new_itr >> 2), new_itr) : new_itr;
bc7f75fa 2594 adapter->itr = new_itr;
4662e82b
BA		 2595 adapter->rx_ring->itr_val = new_itr;
2596 if (adapter->msix_entries)
2597 adapter->rx_ring->set_itr = 1;
2598 else
e3d14b08 2599 e1000e_write_itr(adapter, new_itr);
bc7f75fa
AK		 2600 }
2601}
2602
22a4cca2
MV		 2603/**
2604 * e1000e_write_itr - write the ITR value to the appropriate registers
2605 * @adapter: address of board private structure
2606 * @itr: new ITR value to program
2607 *
2608 * e1000e_write_itr determines if the adapter is in MSI-X mode
2609 * and, if so, writes the EITR registers with the ITR value.
2610 * Otherwise, it writes the ITR value into the ITR register.
2611 **/
2612void e1000e_write_itr(struct e1000_adapter *adapter, u32 itr)
2613{
2614 struct e1000_hw *hw = &adapter->hw;
2615 u32 new_itr = itr ? 1000000000 / (itr * 256) : 0;
2616
2617 if (adapter->msix_entries) {
2618 int vector;
2619
2620 for (vector = 0; vector < adapter->num_vectors; vector++)
2621 writel(new_itr, hw->hw_addr + E1000_EITR_82574(vector));
2622 } else {
2623 ew32(ITR, new_itr);
2624 }
2625}
2626
4662e82b
BA		 2627/**
2628 * e1000_alloc_queues - Allocate memory for all rings
2629 * @adapter: board private structure to initialize
2630 **/
9f9a12f8 2631static int e1000_alloc_queues(struct e1000_adapter *adapter)
4662e82b 2632{
55aa6985
BA		 2633 int size = sizeof(struct e1000_ring);
2634
2635 adapter->tx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2636 if (!adapter->tx_ring)
2637 goto err;
55aa6985
BA		 2638 adapter->tx_ring->count = adapter->tx_ring_count;
2639 adapter->tx_ring->adapter = adapter;
4662e82b 2640
55aa6985 2641 adapter->rx_ring = kzalloc(size, GFP_KERNEL);
4662e82b
BA		 2642 if (!adapter->rx_ring)
2643 goto err;
55aa6985
BA		 2644 adapter->rx_ring->count = adapter->rx_ring_count;
2645 adapter->rx_ring->adapter = adapter;
4662e82b
BA		 2646
2647 return 0;
2648err:
2649 e_err("Unable to allocate memory for queues\n");
2650 kfree(adapter->rx_ring);
2651 kfree(adapter->tx_ring);
2652 return -ENOMEM;
2653}
2654
bc7f75fa 2655/**
c58c8a78 2656 * e1000e_poll - NAPI Rx polling callback
ad68076e 2657 * @napi: struct associated with this polling callback
c58c8a78 2658 * @weight: number of packets driver is allowed to process this poll
bc7f75fa 2659 **/
c58c8a78 2660static int e1000e_poll(struct napi_struct *napi, int weight)
bc7f75fa 2661{
c58c8a78
BA		 2662 struct e1000_adapter *adapter = container_of(napi, struct e1000_adapter,
2663 napi);
4662e82b 2664 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 2665 struct net_device *poll_dev = adapter->netdev;
679e8a0f 2666 int tx_cleaned = 1, work_done = 0;
bc7f75fa 2667
4cf1653a 2668 adapter = netdev_priv(poll_dev);
bc7f75fa 2669
c58c8a78
BA		 2670 if (!adapter->msix_entries ||
2671 (adapter->rx_ring->ims_val & adapter->tx_ring->ims_val))
2672 tx_cleaned = e1000_clean_tx_irq(adapter->tx_ring);
4662e82b 2673
c58c8a78 2674 adapter->clean_rx(adapter->rx_ring, &work_done, weight);
d2c7ddd6 2675
12d04a3c 2676 if (!tx_cleaned)
c58c8a78 2677 work_done = weight;
bc7f75fa 2678
c58c8a78
BA		 2679 /* If weight not fully consumed, exit the polling mode */
2680 if (work_done < weight) {
bc7f75fa
AK		 2681 if (adapter->itr_setting & 3)
2682 e1000_set_itr(adapter);
32b3e08f 2683 napi_complete_done(napi, work_done);
a3c69fef
JB		 2684 if (!test_bit(__E1000_DOWN, &adapter->state)) {
2685 if (adapter->msix_entries)
2686 ew32(IMS, adapter->rx_ring->ims_val);
2687 else
2688 e1000_irq_enable(adapter);
2689 }
bc7f75fa
AK		 2690 }
2691
2692 return work_done;
2693}
2694
80d5c368 2695static int e1000_vlan_rx_add_vid(struct net_device *netdev,
603cdca9 2696 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2697{
2698 struct e1000_adapter *adapter = netdev_priv(netdev);
2699 struct e1000_hw *hw = &adapter->hw;
2700 u32 vfta, index;
2701
2702 /* don't update vlan cookie if already programmed */
2703 if ((adapter->hw.mng_cookie.status &
2704 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2705 (vid == adapter->mng_vlan_id))
8e586137 2706 return 0;
caaddaf8 2707
bc7f75fa 2708 /* add VID to filter table */
caaddaf8
BA		 2709 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2710 index = (vid >> 5) & 0x7F;
2711 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
18dd2392 2712 vfta |= BIT((vid & 0x1F));
caaddaf8
BA		 2713 hw->mac.ops.write_vfta(hw, index, vfta);
2714 }
86d70e53
JK		 2715
2716 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2717
2718 return 0;
bc7f75fa
AK		 2719}
2720
80d5c368 2721static int e1000_vlan_rx_kill_vid(struct net_device *netdev,
603cdca9 2722 __always_unused __be16 proto, u16 vid)
bc7f75fa
AK		 2723{
2724 struct e1000_adapter *adapter = netdev_priv(netdev);
2725 struct e1000_hw *hw = &adapter->hw;
2726 u32 vfta, index;
2727
bc7f75fa
AK		 2728 if ((adapter->hw.mng_cookie.status &
2729 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2730 (vid == adapter->mng_vlan_id)) {
2731 /* release control to f/w */
31dbe5b4 2732 e1000e_release_hw_control(adapter);
8e586137 2733 return 0;
bc7f75fa
AK		 2734 }
2735
2736 /* remove VID from filter table */
caaddaf8
BA		 2737 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2738 index = (vid >> 5) & 0x7F;
2739 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, index);
18dd2392 2740 vfta &= ~BIT((vid & 0x1F));
caaddaf8
BA		 2741 hw->mac.ops.write_vfta(hw, index, vfta);
2742 }
86d70e53
JK		 2743
2744 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2745
2746 return 0;
bc7f75fa
AK		 2747}
2748
86d70e53
JK		 2749/**
2750 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2751 * @adapter: board private structure to initialize
2752 **/
2753static void e1000e_vlan_filter_disable(struct e1000_adapter *adapter)
bc7f75fa
AK		 2754{
2755 struct net_device *netdev = adapter->netdev;
86d70e53
JK		 2756 struct e1000_hw *hw = &adapter->hw;
2757 u32 rctl;
bc7f75fa 2758
86d70e53
JK		 2759 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2760 /* disable VLAN receive filtering */
2761 rctl = er32(RCTL);
2762 rctl &= ~(E1000_RCTL_VFE | E1000_RCTL_CFIEN);
2763 ew32(RCTL, rctl);
2764
2765 if (adapter->mng_vlan_id != (u16)E1000_MNG_VLAN_NONE) {
80d5c368
PM		 2766 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
2767 adapter->mng_vlan_id);
86d70e53 2768 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
bc7f75fa 2769 }
bc7f75fa
AK		 2770 }
2771}
2772
86d70e53
JK		 2773/**
2774 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2775 * @adapter: board private structure to initialize
2776 **/
2777static void e1000e_vlan_filter_enable(struct e1000_adapter *adapter)
2778{
2779 struct e1000_hw *hw = &adapter->hw;
2780 u32 rctl;
2781
2782 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER) {
2783 /* enable VLAN receive filtering */
2784 rctl = er32(RCTL);
2785 rctl |= E1000_RCTL_VFE;
2786 rctl &= ~E1000_RCTL_CFIEN;
2787 ew32(RCTL, rctl);
2788 }
2789}
bc7f75fa 2790
86d70e53 2791/**
889ad456 2792 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
86d70e53
JK		 2793 * @adapter: board private structure to initialize
2794 **/
2795static void e1000e_vlan_strip_disable(struct e1000_adapter *adapter)
bc7f75fa 2796{
bc7f75fa 2797 struct e1000_hw *hw = &adapter->hw;
86d70e53 2798 u32 ctrl;
bc7f75fa 2799
86d70e53
JK		 2800 /* disable VLAN tag insert/strip */
2801 ctrl = er32(CTRL);
2802 ctrl &= ~E1000_CTRL_VME;
2803 ew32(CTRL, ctrl);
2804}
bc7f75fa 2805
86d70e53
JK		 2806/**
2807 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2808 * @adapter: board private structure to initialize
2809 **/
2810static void e1000e_vlan_strip_enable(struct e1000_adapter *adapter)
2811{
2812 struct e1000_hw *hw = &adapter->hw;
2813 u32 ctrl;
bc7f75fa 2814
86d70e53
JK		 2815 /* enable VLAN tag insert/strip */
2816 ctrl = er32(CTRL);
2817 ctrl |= E1000_CTRL_VME;
2818 ew32(CTRL, ctrl);
2819}
bc7f75fa 2820
86d70e53
JK		 2821static void e1000_update_mng_vlan(struct e1000_adapter *adapter)
2822{
2823 struct net_device *netdev = adapter->netdev;
2824 u16 vid = adapter->hw.mng_cookie.vlan_id;
2825 u16 old_vid = adapter->mng_vlan_id;
2826
e5fe2541 2827 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
80d5c368 2828 e1000_vlan_rx_add_vid(netdev, htons(ETH_P_8021Q), vid);
86d70e53 2829 adapter->mng_vlan_id = vid;
bc7f75fa
AK		 2830 }
2831
86d70e53 2832 if ((old_vid != (u16)E1000_MNG_VLAN_NONE) && (vid != old_vid))
80d5c368 2833 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q), old_vid);
bc7f75fa
AK		 2834}
2835
2836static void e1000_restore_vlan(struct e1000_adapter *adapter)
2837{
2838 u16 vid;
2839
80d5c368 2840 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
bc7f75fa 2841
86d70e53 2842 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 2843 e1000_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
bc7f75fa
AK		 2844}
2845
cd791618 2846static void e1000_init_manageability_pt(struct e1000_adapter *adapter)
bc7f75fa
AK		 2847{
2848 struct e1000_hw *hw = &adapter->hw;
cd791618 2849 u32 manc, manc2h, mdef, i, j;
bc7f75fa
AK		 2850
2851 if (!(adapter->flags & FLAG_MNG_PT_ENABLED))
2852 return;
2853
2854 manc = er32(MANC);
2855
e921eb1a 2856 /* enable receiving management packets to the host. this will probably
bc7f75fa 2857 * generate destination unreachable messages from the host OS, but
ad68076e
BA		 2858 * the packets will be handled on SMBUS
2859 */
bc7f75fa
AK		 2860 manc |= E1000_MANC_EN_MNG2HOST;
2861 manc2h = er32(MANC2H);
cd791618
BA		 2862
2863 switch (hw->mac.type) {
2864 default:
2865 manc2h |= (E1000_MANC2H_PORT_623 | E1000_MANC2H_PORT_664);
2866 break;
2867 case e1000_82574:
2868 case e1000_82583:
e921eb1a 2869 /* Check if IPMI pass-through decision filter already exists;
cd791618
BA		 2870 * if so, enable it.
2871 */
2872 for (i = 0, j = 0; i < 8; i++) {
2873 mdef = er32(MDEF(i));
2874
2875 /* Ignore filters with anything other than IPMI ports */
3b21b508 2876 if (mdef & ~(E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
cd791618
BA		 2877 continue;
2878
2879 /* Enable this decision filter in MANC2H */
2880 if (mdef)
18dd2392 2881 manc2h |= BIT(i);
cd791618
BA		 2882
2883 j |= mdef;
2884 }
2885
2886 if (j == (E1000_MDEF_PORT_623 | E1000_MDEF_PORT_664))
2887 break;
2888
2889 /* Create new decision filter in an empty filter */
2890 for (i = 0, j = 0; i < 8; i++)
2891 if (er32(MDEF(i)) == 0) {
2892 ew32(MDEF(i), (E1000_MDEF_PORT_623 |
2893 E1000_MDEF_PORT_664));
18dd2392 2894 manc2h |= BIT(1);
cd791618
BA		 2895 j++;
2896 break;
2897 }
2898
2899 if (!j)
2900 e_warn("Unable to create IPMI pass-through filter\n");
2901 break;
2902 }
2903
bc7f75fa
AK		 2904 ew32(MANC2H, manc2h);
2905 ew32(MANC, manc);
2906}
2907
2908/**
af667a29 2909 * e1000_configure_tx - Configure Transmit Unit after Reset
bc7f75fa
AK		 2910 * @adapter: board private structure
2911 *
2912 * Configure the Tx unit of the MAC after a reset.
2913 **/
2914static void e1000_configure_tx(struct e1000_adapter *adapter)
2915{
2916 struct e1000_hw *hw = &adapter->hw;
2917 struct e1000_ring *tx_ring = adapter->tx_ring;
2918 u64 tdba;
e7e834aa 2919 u32 tdlen, tctl, tarc;
bc7f75fa
AK		 2920
2921 /* Setup the HW Tx Head and Tail descriptor pointers */
2922 tdba = tx_ring->dma;
2923 tdlen = tx_ring->count * sizeof(struct e1000_tx_desc);
1e36052e
BA		 2924 ew32(TDBAL(0), (tdba & DMA_BIT_MASK(32)));
2925 ew32(TDBAH(0), (tdba >> 32));
2926 ew32(TDLEN(0), tdlen);
2927 ew32(TDH(0), 0);
2928 ew32(TDT(0), 0);
2929 tx_ring->head = adapter->hw.hw_addr + E1000_TDH(0);
2930 tx_ring->tail = adapter->hw.hw_addr + E1000_TDT(0);
bc7f75fa 2931
0845d45e
JJB		 2932 writel(0, tx_ring->head);
2933 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
2934 e1000e_update_tdt_wa(tx_ring, 0);
2935 else
2936 writel(0, tx_ring->tail);
2937
bc7f75fa
AK		 2938 /* Set the Tx Interrupt Delay register */
2939 ew32(TIDV, adapter->tx_int_delay);
ad68076e 2940 /* Tx irq moderation */
bc7f75fa
AK		 2941 ew32(TADV, adapter->tx_abs_int_delay);
2942
3a3b7586
JB		 2943 if (adapter->flags2 & FLAG2_DMA_BURST) {
2944 u32 txdctl = er32(TXDCTL(0));
6cf08d1c 2945
3a3b7586
JB		 2946 txdctl &= ~(E1000_TXDCTL_PTHRESH | E1000_TXDCTL_HTHRESH |
2947 E1000_TXDCTL_WTHRESH);
e921eb1a 2948 /* set up some performance related parameters to encourage the
3a3b7586
JB		 2949 * hardware to use the bus more efficiently in bursts, depends
2950 * on the tx_int_delay to be enabled,
8edc0e62 2951 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
3a3b7586
JB		 2952 * hthresh = 1 ==> prefetch when one or more available
2953 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2954 * BEWARE: this seems to work but should be considered first if
af667a29 2955 * there are Tx hangs or other Tx related bugs
3a3b7586
JB		 2956 */
2957 txdctl |= E1000_TXDCTL_DMA_BURST_ENABLE;
2958 ew32(TXDCTL(0), txdctl);
3a3b7586 2959 }
56032be7
BA		 2960 /* erratum work around: set txdctl the same for both queues */
2961 ew32(TXDCTL(1), er32(TXDCTL(0)));
3a3b7586 2962
e7e834aa
DE		 2963 /* Program the Transmit Control Register */
2964 tctl = er32(TCTL);
2965 tctl &= ~E1000_TCTL_CT;
2966 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
2967 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2968
bc7f75fa 2969 if (adapter->flags & FLAG_TARC_SPEED_MODE_BIT) {
e9ec2c0f 2970 tarc = er32(TARC(0));
e921eb1a 2971 /* set the speed mode bit, we'll clear it if we're not at
ad68076e
BA		 2972 * gigabit link later
2973 */
18dd2392 2974#define SPEED_MODE_BIT BIT(21)
bc7f75fa 2975 tarc |= SPEED_MODE_BIT;
e9ec2c0f 2976 ew32(TARC(0), tarc);
bc7f75fa
AK		 2977 }
2978
2979 /* errata: program both queues to unweighted RR */
2980 if (adapter->flags & FLAG_TARC_SET_BIT_ZERO) {
e9ec2c0f 2981 tarc = er32(TARC(0));
bc7f75fa 2982 tarc |= 1;
e9ec2c0f
JK		 2983 ew32(TARC(0), tarc);
2984 tarc = er32(TARC(1));
bc7f75fa 2985 tarc |= 1;
e9ec2c0f 2986 ew32(TARC(1), tarc);
bc7f75fa
AK		 2987 }
2988
bc7f75fa
AK		 2989 /* Setup Transmit Descriptor Settings for eop descriptor */
2990 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
2991
2992 /* only set IDE if we are delaying interrupts using the timers */
2993 if (adapter->tx_int_delay)
2994 adapter->txd_cmd |= E1000_TXD_CMD_IDE;
2995
2996 /* enable Report Status bit */
2997 adapter->txd_cmd |= E1000_TXD_CMD_RS;
2998
e7e834aa
DE		 2999 ew32(TCTL, tctl);
3000
57cde763 3001 hw->mac.ops.config_collision_dist(hw);
79849ebc
DE		 3002
3003 /* SPT Si errata workaround to avoid data corruption */
3004 if (hw->mac.type == e1000_pch_spt) {
3005 u32 reg_val;
3006
3007 reg_val = er32(IOSFPC);
3008 reg_val |= E1000_RCTL_RDMTS_HEX;
3009 ew32(IOSFPC, reg_val);
3010
3011 reg_val = er32(TARC(0));
3012 reg_val |= E1000_TARC0_CB_MULTIQ_3_REQ;
3013 ew32(TARC(0), reg_val);
3014 }
bc7f75fa
AK		 3015}
3016
3017/**
3018 * e1000_setup_rctl - configure the receive control registers
3019 * @adapter: Board private structure
3020 **/
3021#define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3022 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3023static void e1000_setup_rctl(struct e1000_adapter *adapter)
3024{
3025 struct e1000_hw *hw = &adapter->hw;
3026 u32 rctl, rfctl;
bc7f75fa
AK		 3027 u32 pages = 0;
3028
b20a7744
DE		 3029 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3030 * If jumbo frames not set, program related MAC/PHY registers
3031 * to h/w defaults
3032 */
3033 if (hw->mac.type >= e1000_pch2lan) {
3034 s32 ret_val;
3035
3036 if (adapter->netdev->mtu > ETH_DATA_LEN)
3037 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, true);
3038 else
3039 ret_val = e1000_lv_jumbo_workaround_ich8lan(hw, false);
3040
3041 if (ret_val)
3042 e_dbg("failed to enable|disable jumbo frame workaround mode\n");
3043 }
a1ce6473 3044
bc7f75fa
AK		 3045 /* Program MC offset vector base */
3046 rctl = er32(RCTL);
3047 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3048 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
f0ff4398
BA		 3049 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
3050 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
bc7f75fa
AK		 3051
3052 /* Do not Store bad packets */
3053 rctl &= ~E1000_RCTL_SBP;
3054
3055 /* Enable Long Packet receive */
3056 if (adapter->netdev->mtu <= ETH_DATA_LEN)
3057 rctl &= ~E1000_RCTL_LPE;
3058 else
3059 rctl |= E1000_RCTL_LPE;
3060
eb7c3adb
JK		 3061 /* Some systems expect that the CRC is included in SMBUS traffic. The
3062 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3063 * host memory when this is enabled
3064 */
3065 if (adapter->flags2 & FLAG2_CRC_STRIPPING)
3066 rctl |= E1000_RCTL_SECRC;
5918bd88 3067
a4f58f54
BA		 3068 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3069 if ((hw->phy.type == e1000_phy_82577) && (rctl & E1000_RCTL_LPE)) {
3070 u16 phy_data;
3071
3072 e1e_rphy(hw, PHY_REG(770, 26), &phy_data);
3073 phy_data &= 0xfff8;
18dd2392 3074 phy_data |= BIT(2);
a4f58f54
BA		 3075 e1e_wphy(hw, PHY_REG(770, 26), phy_data);
3076
3077 e1e_rphy(hw, 22, &phy_data);
3078 phy_data &= 0x0fff;
18dd2392 3079 phy_data |= BIT(14);
a4f58f54
BA		 3080 e1e_wphy(hw, 0x10, 0x2823);
3081 e1e_wphy(hw, 0x11, 0x0003);
3082 e1e_wphy(hw, 22, phy_data);
3083 }
3084
bc7f75fa
AK		 3085 /* Setup buffer sizes */
3086 rctl &= ~E1000_RCTL_SZ_4096;
3087 rctl |= E1000_RCTL_BSEX;
3088 switch (adapter->rx_buffer_len) {
bc7f75fa
AK		 3089 case 2048:
3090 default:
3091 rctl |= E1000_RCTL_SZ_2048;
3092 rctl &= ~E1000_RCTL_BSEX;
3093 break;
3094 case 4096:
3095 rctl |= E1000_RCTL_SZ_4096;
3096 break;
3097 case 8192:
3098 rctl |= E1000_RCTL_SZ_8192;
3099 break;
3100 case 16384:
3101 rctl |= E1000_RCTL_SZ_16384;
3102 break;
3103 }
3104
5f450212
BA		 3105 /* Enable Extended Status in all Receive Descriptors */
3106 rfctl = er32(RFCTL);
3107 rfctl |= E1000_RFCTL_EXTEN;
f6bd5577 3108 ew32(RFCTL, rfctl);
5f450212 3109
e921eb1a 3110 /* 82571 and greater support packet-split where the protocol
bc7f75fa
AK		 3111 * header is placed in skb->data and the packet data is
3112 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3113 * In the case of a non-split, skb->data is linearly filled,
3114 * followed by the page buffers. Therefore, skb->data is
3115 * sized to hold the largest protocol header.
3116 *
3117 * allocations using alloc_page take too long for regular MTU
3118 * so only enable packet split for jumbo frames
3119 *
3120 * Using pages when the page size is greater than 16k wastes
3121 * a lot of memory, since we allocate 3 pages at all times
3122 * per packet.
3123 */
bc7f75fa 3124 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
79d4e908 3125 if ((pages <= 3) && (PAGE_SIZE <= 16384) && (rctl & E1000_RCTL_LPE))
bc7f75fa 3126 adapter->rx_ps_pages = pages;
97ac8cae
BA		 3127 else
3128 adapter->rx_ps_pages = 0;
bc7f75fa
AK		 3129
3130 if (adapter->rx_ps_pages) {
90da0669
BA		 3131 u32 psrctl = 0;
3132
140a7480
AK		 3133 /* Enable Packet split descriptors */
3134 rctl |= E1000_RCTL_DTYP_PS;
bc7f75fa 3135
e5fe2541 3136 psrctl |= adapter->rx_ps_bsize0 >> E1000_PSRCTL_BSIZE0_SHIFT;
bc7f75fa
AK		 3137
3138 switch (adapter->rx_ps_pages) {
3139 case 3:
e5fe2541
BA		 3140 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE3_SHIFT;
3141 /* fall-through */
bc7f75fa 3142 case 2:
e5fe2541
BA		 3143 psrctl |= PAGE_SIZE << E1000_PSRCTL_BSIZE2_SHIFT;
3144 /* fall-through */
bc7f75fa 3145 case 1:
e5fe2541 3146 psrctl |= PAGE_SIZE >> E1000_PSRCTL_BSIZE1_SHIFT;
bc7f75fa
AK		 3147 break;
3148 }
3149
3150 ew32(PSRCTL, psrctl);
3151 }
3152
cf955e6c
BG		 3153 /* This is useful for sniffing bad packets. */
3154 if (adapter->netdev->features & NETIF_F_RXALL) {
3155 /* UPE and MPE will be handled by normal PROMISC logic
e921eb1a
BA		 3156 * in e1000e_set_rx_mode
3157 */
e80bd1d1
BA		 3158 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */
3159 E1000_RCTL_BAM | /* RX All Bcast Pkts */
3160 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */
cf955e6c 3161
e80bd1d1
BA		 3162 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */
3163 E1000_RCTL_DPF | /* Allow filtered pause */
3164 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */
cf955e6c
BG		 3165 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3166 * and that breaks VLANs.
3167 */
3168 }
3169
bc7f75fa 3170 ew32(RCTL, rctl);
318a94d6 3171 /* just started the receive unit, no need to restart */
12d43f7d 3172 adapter->flags &= ~FLAG_RESTART_NOW;
bc7f75fa
AK		 3173}
3174
3175/**
3176 * e1000_configure_rx - Configure Receive Unit after Reset
3177 * @adapter: board private structure
3178 *
3179 * Configure the Rx unit of the MAC after a reset.
3180 **/
3181static void e1000_configure_rx(struct e1000_adapter *adapter)
3182{
3183 struct e1000_hw *hw = &adapter->hw;
3184 struct e1000_ring *rx_ring = adapter->rx_ring;
3185 u64 rdba;
3186 u32 rdlen, rctl, rxcsum, ctrl_ext;
3187
3188 if (adapter->rx_ps_pages) {
3189 /* this is a 32 byte descriptor */
3190 rdlen = rx_ring->count *
af667a29 3191 sizeof(union e1000_rx_desc_packet_split);
bc7f75fa
AK		 3192 adapter->clean_rx = e1000_clean_rx_irq_ps;
3193 adapter->alloc_rx_buf = e1000_alloc_rx_buffers_ps;
97ac8cae 3194 } else if (adapter->netdev->mtu > ETH_FRAME_LEN + ETH_FCS_LEN) {
5f450212 3195 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
97ac8cae
BA		 3196 adapter->clean_rx = e1000_clean_jumbo_rx_irq;
3197 adapter->alloc_rx_buf = e1000_alloc_jumbo_rx_buffers;
bc7f75fa 3198 } else {
5f450212 3199 rdlen = rx_ring->count * sizeof(union e1000_rx_desc_extended);
bc7f75fa
AK		 3200 adapter->clean_rx = e1000_clean_rx_irq;
3201 adapter->alloc_rx_buf = e1000_alloc_rx_buffers;
3202 }
3203
3204 /* disable receives while setting up the descriptors */
3205 rctl = er32(RCTL);
7f99ae63
BA		 3206 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
3207 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa 3208 e1e_flush();
1bba4386 3209 usleep_range(10000, 20000);
bc7f75fa 3210
3a3b7586 3211 if (adapter->flags2 & FLAG2_DMA_BURST) {
e921eb1a 3212 /* set the writeback threshold (only takes effect if the RDTR
3a3b7586 3213 * is set). set GRAN=1 and write back up to 0x4 worth, and
af667a29 3214 * enable prefetching of 0x20 Rx descriptors
3a3b7586
JB		 3215 * granularity = 01
3216 * wthresh = 04,
3217 * hthresh = 04,
3218 * pthresh = 0x20
3219 */
3220 ew32(RXDCTL(0), E1000_RXDCTL_DMA_BURST_ENABLE);
3221 ew32(RXDCTL(1), E1000_RXDCTL_DMA_BURST_ENABLE);
3222
e921eb1a 3223 /* override the delay timers for enabling bursting, only if
3a3b7586
JB		 3224 * the value was not set by the user via module options
3225 */
3226 if (adapter->rx_int_delay == DEFAULT_RDTR)
3227 adapter->rx_int_delay = BURST_RDTR;
3228 if (adapter->rx_abs_int_delay == DEFAULT_RADV)
3229 adapter->rx_abs_int_delay = BURST_RADV;
3230 }
3231
bc7f75fa
AK		 3232 /* set the Receive Delay Timer Register */
3233 ew32(RDTR, adapter->rx_int_delay);
3234
3235 /* irq moderation */
3236 ew32(RADV, adapter->rx_abs_int_delay);
828bac87 3237 if ((adapter->itr_setting != 0) && (adapter->itr != 0))
22a4cca2 3238 e1000e_write_itr(adapter, adapter->itr);
bc7f75fa
AK		 3239
3240 ctrl_ext = er32(CTRL_EXT);
bc7f75fa
AK		 3241 /* Auto-Mask interrupts upon ICR access */
3242 ctrl_ext |= E1000_CTRL_EXT_IAME;
3243 ew32(IAM, 0xffffffff);
3244 ew32(CTRL_EXT, ctrl_ext);
3245 e1e_flush();
3246
e921eb1a 3247 /* Setup the HW Rx Head and Tail Descriptor Pointers and
ad68076e
BA		 3248 * the Base and Length of the Rx Descriptor Ring
3249 */
bc7f75fa 3250 rdba = rx_ring->dma;
1e36052e
BA		 3251 ew32(RDBAL(0), (rdba & DMA_BIT_MASK(32)));
3252 ew32(RDBAH(0), (rdba >> 32));
3253 ew32(RDLEN(0), rdlen);
3254 ew32(RDH(0), 0);
3255 ew32(RDT(0), 0);
3256 rx_ring->head = adapter->hw.hw_addr + E1000_RDH(0);
3257 rx_ring->tail = adapter->hw.hw_addr + E1000_RDT(0);
bc7f75fa 3258
0845d45e
JJB		 3259 writel(0, rx_ring->head);
3260 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
3261 e1000e_update_rdt_wa(rx_ring, 0);
3262 else
3263 writel(0, rx_ring->tail);
3264
bc7f75fa
AK		 3265 /* Enable Receive Checksum Offload for TCP and UDP */
3266 rxcsum = er32(RXCSUM);
2e1706f2 3267 if (adapter->netdev->features & NETIF_F_RXCSUM)
bc7f75fa 3268 rxcsum |= E1000_RXCSUM_TUOFL;
2e1706f2 3269 else
bc7f75fa 3270 rxcsum &= ~E1000_RXCSUM_TUOFL;
bc7f75fa
AK		 3271 ew32(RXCSUM, rxcsum);
3272
3e35d991
BA		 3273 /* With jumbo frames, excessive C-state transition latencies result
3274 * in dropped transactions.
3275 */
3276 if (adapter->netdev->mtu > ETH_DATA_LEN) {
3277 u32 lat =
3278 ((er32(PBA) & E1000_PBA_RXA_MASK) * 1024 -
3279 adapter->max_frame_size) * 8 / 1000;
3280
3281 if (adapter->flags & FLAG_IS_ICH) {
53ec5498 3282 u32 rxdctl = er32(RXDCTL(0));
6cf08d1c 3283
53ec5498 3284 ew32(RXDCTL(0), rxdctl | 0x3);
53ec5498 3285 }
3e35d991 3286
e2c65448 3287 pm_qos_update_request(&adapter->pm_qos_req, lat);
3e35d991 3288 } else {
e2c65448 3289 pm_qos_update_request(&adapter->pm_qos_req,
3e35d991 3290 PM_QOS_DEFAULT_VALUE);
97ac8cae 3291 }
bc7f75fa
AK		 3292
3293 /* Enable Receives */
3294 ew32(RCTL, rctl);
3295}
3296
3297/**
ef9b965a
JB		 3298 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3299 * @netdev: network interface device structure
bc7f75fa 3300 *
ef9b965a
JB		 3301 * Writes multicast address list to the MTA hash table.
3302 * Returns: -ENOMEM on failure
3303 * 0 on no addresses written
3304 * X on writing X addresses to MTA
3305 */
3306static int e1000e_write_mc_addr_list(struct net_device *netdev)
3307{
3308 struct e1000_adapter *adapter = netdev_priv(netdev);
3309 struct e1000_hw *hw = &adapter->hw;
3310 struct netdev_hw_addr *ha;
3311 u8 *mta_list;
3312 int i;
3313
3314 if (netdev_mc_empty(netdev)) {
3315 /* nothing to program, so clear mc list */
3316 hw->mac.ops.update_mc_addr_list(hw, NULL, 0);
3317 return 0;
3318 }
3319
3320 mta_list = kzalloc(netdev_mc_count(netdev) * ETH_ALEN, GFP_ATOMIC);
3321 if (!mta_list)
3322 return -ENOMEM;
3323
3324 /* update_mc_addr_list expects a packed array of only addresses. */
3325 i = 0;
3326 netdev_for_each_mc_addr(ha, netdev)
f0ff4398 3327 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
ef9b965a
JB		 3328
3329 hw->mac.ops.update_mc_addr_list(hw, mta_list, i);
3330 kfree(mta_list);
3331
3332 return netdev_mc_count(netdev);
3333}
3334
3335/**
3336 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3337 * @netdev: network interface device structure
bc7f75fa 3338 *
ef9b965a
JB		 3339 * Writes unicast address list to the RAR table.
3340 * Returns: -ENOMEM on failure/insufficient address space
3341 * 0 on no addresses written
3342 * X on writing X addresses to the RAR table
bc7f75fa 3343 **/
ef9b965a 3344static int e1000e_write_uc_addr_list(struct net_device *netdev)
bc7f75fa 3345{
ef9b965a
JB		 3346 struct e1000_adapter *adapter = netdev_priv(netdev);
3347 struct e1000_hw *hw = &adapter->hw;
b3e5bf1f 3348 unsigned int rar_entries;
ef9b965a
JB		 3349 int count = 0;
3350
b3e5bf1f
DE		 3351 rar_entries = hw->mac.ops.rar_get_count(hw);
3352
ef9b965a
JB		 3353 /* save a rar entry for our hardware address */
3354 rar_entries--;
3355
3356 /* save a rar entry for the LAA workaround */
3357 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA)
3358 rar_entries--;
3359
3360 /* return ENOMEM indicating insufficient memory for addresses */
3361 if (netdev_uc_count(netdev) > rar_entries)
3362 return -ENOMEM;
3363
3364 if (!netdev_uc_empty(netdev) && rar_entries) {
3365 struct netdev_hw_addr *ha;
3366
e921eb1a 3367 /* write the addresses in reverse order to avoid write
ef9b965a
JB		 3368 * combining
3369 */
3370 netdev_for_each_uc_addr(ha, netdev) {
847042a6 3371 int ret_val;
b3e5bf1f 3372
ef9b965a
JB		 3373 if (!rar_entries)
3374 break;
847042a6
BW		 3375 ret_val = hw->mac.ops.rar_set(hw, ha->addr, rar_entries--);
3376 if (ret_val < 0)
b3e5bf1f 3377 return -ENOMEM;
ef9b965a
JB		 3378 count++;
3379 }
3380 }
3381
3382 /* zero out the remaining RAR entries not used above */
3383 for (; rar_entries > 0; rar_entries--) {
3384 ew32(RAH(rar_entries), 0);
3385 ew32(RAL(rar_entries), 0);
3386 }
3387 e1e_flush();
3388
3389 return count;
bc7f75fa
AK		 3390}
3391
3392/**
ef9b965a 3393 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
bc7f75fa
AK		 3394 * @netdev: network interface device structure
3395 *
ef9b965a
JB		 3396 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3397 * address list or the network interface flags are updated. This routine is
3398 * responsible for configuring the hardware for proper unicast, multicast,
bc7f75fa
AK		 3399 * promiscuous mode, and all-multi behavior.
3400 **/
ef9b965a 3401static void e1000e_set_rx_mode(struct net_device *netdev)
bc7f75fa
AK		 3402{
3403 struct e1000_adapter *adapter = netdev_priv(netdev);
3404 struct e1000_hw *hw = &adapter->hw;
bc7f75fa 3405 u32 rctl;
bc7f75fa 3406
63eb48f1
DE		 3407 if (pm_runtime_suspended(netdev->dev.parent))
3408 return;
3409
bc7f75fa 3410 /* Check for Promiscuous and All Multicast modes */
bc7f75fa
AK		 3411 rctl = er32(RCTL);
3412
ef9b965a
JB		 3413 /* clear the affected bits */
3414 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
3415
bc7f75fa
AK		 3416 if (netdev->flags & IFF_PROMISC) {
3417 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
86d70e53
JK		 3418 /* Do not hardware filter VLANs in promisc mode */
3419 e1000e_vlan_filter_disable(adapter);
bc7f75fa 3420 } else {
ef9b965a 3421 int count;
3d3a1676 3422
746b9f02
PM		 3423 if (netdev->flags & IFF_ALLMULTI) {
3424 rctl |= E1000_RCTL_MPE;
746b9f02 3425 } else {
e921eb1a 3426 /* Write addresses to the MTA, if the attempt fails
ef9b965a
JB		 3427 * then we should just turn on promiscuous mode so
3428 * that we can at least receive multicast traffic
3429 */
3430 count = e1000e_write_mc_addr_list(netdev);
3431 if (count < 0)
3432 rctl |= E1000_RCTL_MPE;
746b9f02 3433 }
86d70e53 3434 e1000e_vlan_filter_enable(adapter);
e921eb1a 3435 /* Write addresses to available RAR registers, if there is not
ef9b965a
JB		 3436 * sufficient space to store all the addresses then enable
3437 * unicast promiscuous mode
bc7f75fa 3438 */
ef9b965a
JB		 3439 count = e1000e_write_uc_addr_list(netdev);
3440 if (count < 0)
3441 rctl |= E1000_RCTL_UPE;
bc7f75fa 3442 }
86d70e53 3443
ef9b965a
JB		 3444 ew32(RCTL, rctl);
3445
83808641 3446 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
86d70e53
JK		 3447 e1000e_vlan_strip_enable(adapter);
3448 else
3449 e1000e_vlan_strip_disable(adapter);
bc7f75fa
AK		 3450}
3451
70495a50
BA		 3452static void e1000e_setup_rss_hash(struct e1000_adapter *adapter)
3453{
3454 struct e1000_hw *hw = &adapter->hw;
3455 u32 mrqc, rxcsum;
5c8d19da 3456 u32 rss_key[10];
70495a50 3457 int i;
70495a50 3458
5c8d19da 3459 netdev_rss_key_fill(rss_key, sizeof(rss_key));
70495a50 3460 for (i = 0; i < 10; i++)
5c8d19da 3461 ew32(RSSRK(i), rss_key[i]);
70495a50
BA		 3462
3463 /* Direct all traffic to queue 0 */
3464 for (i = 0; i < 32; i++)
3465 ew32(RETA(i), 0);
3466
e921eb1a 3467 /* Disable raw packet checksumming so that RSS hash is placed in
70495a50
BA		 3468 * descriptor on writeback.
3469 */
3470 rxcsum = er32(RXCSUM);
3471 rxcsum |= E1000_RXCSUM_PCSD;
3472
3473 ew32(RXCSUM, rxcsum);
3474
3475 mrqc = (E1000_MRQC_RSS_FIELD_IPV4 |
3476 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3477 E1000_MRQC_RSS_FIELD_IPV6 |
3478 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3479 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3480
3481 ew32(MRQC, mrqc);
3482}
3483
b67e1913
BA		 3484/**
3485 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3486 * @adapter: board private structure
3487 * @timinca: pointer to returned time increment attributes
3488 *
3489 * Get attributes for incrementing the System Time Register SYSTIML/H at
3490 * the default base frequency, and set the cyclecounter shift value.
3491 **/
d89777bf 3492s32 e1000e_get_base_timinca(struct e1000_adapter *adapter, u32 *timinca)
b67e1913
BA		 3493{
3494 struct e1000_hw *hw = &adapter->hw;
3495 u32 incvalue, incperiod, shift;
3496
79849ebc
DE		 3497 /* Make sure clock is enabled on I217/I218/I219 before checking
3498 * the frequency
3499 */
3500 if (((hw->mac.type == e1000_pch_lpt) ||
3501 (hw->mac.type == e1000_pch_spt)) &&
b67e1913
BA		 3502 !(er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) &&
3503 !(er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_ENABLED)) {
3504 u32 fextnvm7 = er32(FEXTNVM7);
3505
18dd2392
JK		 3506 if (!(fextnvm7 & BIT(0))) {
3507 ew32(FEXTNVM7, fextnvm7 | BIT(0));
b67e1913
BA		 3508 e1e_flush();
3509 }
3510 }
3511
3512 switch (hw->mac.type) {
3513 case e1000_pch2lan:
3514 case e1000_pch_lpt:
83129b37 3515 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
b67e1913
BA		 3516 /* Stable 96MHz frequency */
3517 incperiod = INCPERIOD_96MHz;
3518 incvalue = INCVALUE_96MHz;
3519 shift = INCVALUE_SHIFT_96MHz;
3520 adapter->cc.shift = shift + INCPERIOD_SHIFT_96MHz;
83129b37
YL		 3521 } else {
3522 /* Stable 25MHz frequency */
3523 incperiod = INCPERIOD_25MHz;
3524 incvalue = INCVALUE_25MHz;
3525 shift = INCVALUE_SHIFT_25MHz;
3526 adapter->cc.shift = shift;
3527 }
3528 break;
3529 case e1000_pch_spt:
3530 if (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_SYSCFI) {
3531 /* Stable 24MHz frequency */
3532 incperiod = INCPERIOD_24MHz;
3533 incvalue = INCVALUE_24MHz;
3534 shift = INCVALUE_SHIFT_24MHz;
3535 adapter->cc.shift = shift;
b67e1913
BA		 3536 break;
3537 }
83129b37 3538 return -EINVAL;
b67e1913
BA		 3539 case e1000_82574:
3540 case e1000_82583:
3541 /* Stable 25MHz frequency */
3542 incperiod = INCPERIOD_25MHz;
3543 incvalue = INCVALUE_25MHz;
3544 shift = INCVALUE_SHIFT_25MHz;
3545 adapter->cc.shift = shift;
3546 break;
3547 default:
3548 return -EINVAL;
3549 }
3550
3551 *timinca = ((incperiod << E1000_TIMINCA_INCPERIOD_SHIFT) |
3552 ((incvalue << shift) & E1000_TIMINCA_INCVALUE_MASK));
3553
3554 return 0;
3555}
3556
3557/**
3558 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3559 * @adapter: board private structure
3560 *
3561 * Outgoing time stamping can be enabled and disabled. Play nice and
3562 * disable it when requested, although it shouldn't cause any overhead
3563 * when no packet needs it. At most one packet in the queue may be
3564 * marked for time stamping, otherwise it would be impossible to tell
3565 * for sure to which packet the hardware time stamp belongs.
3566 *
3567 * Incoming time stamping has to be configured via the hardware filters.
3568 * Not all combinations are supported, in particular event type has to be
3569 * specified. Matching the kind of event packet is not supported, with the
3570 * exception of "all V2 events regardless of level 2 or 4".
3571 **/
62d7e3a2
BH		 3572static int e1000e_config_hwtstamp(struct e1000_adapter *adapter,
3573 struct hwtstamp_config *config)
b67e1913
BA		 3574{
3575 struct e1000_hw *hw = &adapter->hw;
b67e1913
BA		 3576 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
3577 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
d89777bf
BA		 3578 u32 rxmtrl = 0;
3579 u16 rxudp = 0;
3580 bool is_l4 = false;
3581 bool is_l2 = false;
b67e1913 3582 u32 regval;
b67e1913
BA		 3583
3584 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3585 return -EINVAL;
3586
3587 /* flags reserved for future extensions - must be zero */
3588 if (config->flags)
3589 return -EINVAL;
3590
3591 switch (config->tx_type) {
3592 case HWTSTAMP_TX_OFF:
3593 tsync_tx_ctl = 0;
3594 break;
3595 case HWTSTAMP_TX_ON:
3596 break;
3597 default:
3598 return -ERANGE;
3599 }
3600
3601 switch (config->rx_filter) {
3602 case HWTSTAMP_FILTER_NONE:
3603 tsync_rx_ctl = 0;
3604 break;
d89777bf
BA		 3605 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3606 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3607 rxmtrl = E1000_RXMTRL_PTP_V1_SYNC_MESSAGE;
3608 is_l4 = true;
3609 break;
3610 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3611 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
3612 rxmtrl = E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE;
3613 is_l4 = true;
3614 break;
3615 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3616 /* Also time stamps V2 L2 Path Delay Request/Response */
3617 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3618 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3619 is_l2 = true;
3620 break;
3621 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3622 /* Also time stamps V2 L2 Path Delay Request/Response. */
3623 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_V2;
3624 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3625 is_l2 = true;
3626 break;
3627 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3628 /* Hardware cannot filter just V2 L4 Sync messages;
3629 * fall-through to V2 (both L2 and L4) Sync.
3630 */
3631 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3632 /* Also time stamps V2 Path Delay Request/Response. */
3633 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3634 rxmtrl = E1000_RXMTRL_PTP_V2_SYNC_MESSAGE;
3635 is_l2 = true;
3636 is_l4 = true;
3637 break;
3638 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3639 /* Hardware cannot filter just V2 L4 Delay Request messages;
3640 * fall-through to V2 (both L2 and L4) Delay Request.
3641 */
3642 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3643 /* Also time stamps V2 Path Delay Request/Response. */
3644 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
3645 rxmtrl = E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE;
3646 is_l2 = true;
3647 is_l4 = true;
3648 break;
3649 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3650 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3651 /* Hardware cannot filter just V2 L4 or L2 Event messages;
3652 * fall-through to all V2 (both L2 and L4) Events.
3653 */
3654 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3655 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
3656 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
3657 is_l2 = true;
3658 is_l4 = true;
3659 break;
3660 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3661 /* For V1, the hardware can only filter Sync messages or
3662 * Delay Request messages but not both so fall-through to
3663 * time stamp all packets.
3664 */
b67e1913 3665 case HWTSTAMP_FILTER_ALL:
d89777bf
BA		 3666 is_l2 = true;
3667 is_l4 = true;
b67e1913
BA		 3668 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
3669 config->rx_filter = HWTSTAMP_FILTER_ALL;
3670 break;
3671 default:
3672 return -ERANGE;
3673 }
3674
62d7e3a2
BH		 3675 adapter->hwtstamp_config = *config;
3676
b67e1913
BA		 3677 /* enable/disable Tx h/w time stamping */
3678 regval = er32(TSYNCTXCTL);
3679 regval &= ~E1000_TSYNCTXCTL_ENABLED;
3680 regval |= tsync_tx_ctl;
3681 ew32(TSYNCTXCTL, regval);
3682 if ((er32(TSYNCTXCTL) & E1000_TSYNCTXCTL_ENABLED) !=
3683 (regval & E1000_TSYNCTXCTL_ENABLED)) {
3684 e_err("Timesync Tx Control register not set as expected\n");
3685 return -EAGAIN;
3686 }
3687
3688 /* enable/disable Rx h/w time stamping */
3689 regval = er32(TSYNCRXCTL);
3690 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
3691 regval |= tsync_rx_ctl;
3692 ew32(TSYNCRXCTL, regval);
3693 if ((er32(TSYNCRXCTL) & (E1000_TSYNCRXCTL_ENABLED |
3694 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3695 (regval & (E1000_TSYNCRXCTL_ENABLED |
3696 E1000_TSYNCRXCTL_TYPE_MASK))) {
3697 e_err("Timesync Rx Control register not set as expected\n");
3698 return -EAGAIN;
3699 }
3700
d89777bf
BA		 3701 /* L2: define ethertype filter for time stamped packets */
3702 if (is_l2)
3703 rxmtrl |= ETH_P_1588;
3704
3705 /* define which PTP packets get time stamped */
3706 ew32(RXMTRL, rxmtrl);
3707
3708 /* Filter by destination port */
3709 if (is_l4) {
3710 rxudp = PTP_EV_PORT;
3711 cpu_to_be16s(&rxudp);
3712 }
3713 ew32(RXUDP, rxudp);
3714
3715 e1e_flush();
3716
b67e1913 3717 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
70806a7f
BA		 3718 er32(RXSTMPH);
3719 er32(TXSTMPH);
b67e1913 3720
b67e1913
BA		 3721 return 0;
3722}
3723
bc7f75fa 3724/**
ad68076e 3725 * e1000_configure - configure the hardware for Rx and Tx
bc7f75fa
AK		 3726 * @adapter: private board structure
3727 **/
3728static void e1000_configure(struct e1000_adapter *adapter)
3729{
55aa6985
BA		 3730 struct e1000_ring *rx_ring = adapter->rx_ring;
3731
ef9b965a 3732 e1000e_set_rx_mode(adapter->netdev);
bc7f75fa
AK		 3733
3734 e1000_restore_vlan(adapter);
cd791618 3735 e1000_init_manageability_pt(adapter);
bc7f75fa
AK		 3736
3737 e1000_configure_tx(adapter);
70495a50
BA		 3738
3739 if (adapter->netdev->features & NETIF_F_RXHASH)
3740 e1000e_setup_rss_hash(adapter);
bc7f75fa
AK		 3741 e1000_setup_rctl(adapter);
3742 e1000_configure_rx(adapter);
55aa6985 3743 adapter->alloc_rx_buf(rx_ring, e1000_desc_unused(rx_ring), GFP_KERNEL);
bc7f75fa
AK		 3744}
3745
3746/**
3747 * e1000e_power_up_phy - restore link in case the phy was powered down
3748 * @adapter: address of board private structure
3749 *
3750 * The phy may be powered down to save power and turn off link when the
3751 * driver is unloaded and wake on lan is not enabled (among others)
3752 * *** this routine MUST be followed by a call to e1000e_reset ***
3753 **/
3754void e1000e_power_up_phy(struct e1000_adapter *adapter)
3755{
17f208de
BA		 3756 if (adapter->hw.phy.ops.power_up)
3757 adapter->hw.phy.ops.power_up(&adapter->hw);
bc7f75fa
AK		 3758
3759 adapter->hw.mac.ops.setup_link(&adapter->hw);
3760}
3761
3762/**
3763 * e1000_power_down_phy - Power down the PHY
3764 *
17f208de
BA		 3765 * Power down the PHY so no link is implied when interface is down.
3766 * The PHY cannot be powered down if management or WoL is active.
bc7f75fa
AK		 3767 */
3768static void e1000_power_down_phy(struct e1000_adapter *adapter)
3769{
17f208de
BA		 3770 if (adapter->hw.phy.ops.power_down)
3771 adapter->hw.phy.ops.power_down(&adapter->hw);
bc7f75fa
AK		 3772}
3773
ad851fbb
YL		 3774/**
3775 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3776 *
3777 * We want to clear all pending descriptors from the TX ring.
3778 * zeroing happens when the HW reads the regs. We assign the ring itself as
3779 * the data of the next descriptor. We don't care about the data we are about
3780 * to reset the HW.
3781 */
3782static void e1000_flush_tx_ring(struct e1000_adapter *adapter)
3783{
3784 struct e1000_hw *hw = &adapter->hw;
3785 struct e1000_ring *tx_ring = adapter->tx_ring;
3786 struct e1000_tx_desc *tx_desc = NULL;
3787 u32 tdt, tctl, txd_lower = E1000_TXD_CMD_IFCS;
3788 u16 size = 512;
3789
3790 tctl = er32(TCTL);
3791 ew32(TCTL, tctl | E1000_TCTL_EN);
3792 tdt = er32(TDT(0));
3793 BUG_ON(tdt != tx_ring->next_to_use);
3794 tx_desc = E1000_TX_DESC(*tx_ring, tx_ring->next_to_use);
3795 tx_desc->buffer_addr = tx_ring->dma;
3796
3797 tx_desc->lower.data = cpu_to_le32(txd_lower | size);
3798 tx_desc->upper.data = 0;
3799 /* flush descriptors to memory before notifying the HW */
3800 wmb();
3801 tx_ring->next_to_use++;
3802 if (tx_ring->next_to_use == tx_ring->count)
3803 tx_ring->next_to_use = 0;
3804 ew32(TDT(0), tx_ring->next_to_use);
3805 mmiowb();
3806 usleep_range(200, 250);
3807}
3808
3809/**
3810 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3811 *
3812 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3813 */
3814static void e1000_flush_rx_ring(struct e1000_adapter *adapter)
3815{
3816 u32 rctl, rxdctl;
3817 struct e1000_hw *hw = &adapter->hw;
3818
3819 rctl = er32(RCTL);
3820 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3821 e1e_flush();
3822 usleep_range(100, 150);
3823
3824 rxdctl = er32(RXDCTL(0));
3825 /* zero the lower 14 bits (prefetch and host thresholds) */
3826 rxdctl &= 0xffffc000;
3827
3828 /* update thresholds: prefetch threshold to 31, host threshold to 1
3829 * and make sure the granularity is "descriptors" and not "cache lines"
3830 */
18dd2392 3831 rxdctl |= (0x1F | BIT(8) | E1000_RXDCTL_THRESH_UNIT_DESC);
ad851fbb
YL		 3832
3833 ew32(RXDCTL(0), rxdctl);
3834 /* momentarily enable the RX ring for the changes to take effect */
3835 ew32(RCTL, rctl | E1000_RCTL_EN);
3836 e1e_flush();
3837 usleep_range(100, 150);
3838 ew32(RCTL, rctl & ~E1000_RCTL_EN);
3839}
3840
3841/**
3842 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3843 *
3844 * In i219, the descriptor rings must be emptied before resetting the HW
3845 * or before changing the device state to D3 during runtime (runtime PM).
3846 *
3847 * Failure to do this will cause the HW to enter a unit hang state which can
3848 * only be released by PCI reset on the device
3849 *
3850 */
3851
3852static void e1000_flush_desc_rings(struct e1000_adapter *adapter)
3853{
ff917429 3854 u16 hang_state;
ad851fbb
YL		 3855 u32 fext_nvm11, tdlen;
3856 struct e1000_hw *hw = &adapter->hw;
3857
3858 /* First, disable MULR fix in FEXTNVM11 */
3859 fext_nvm11 = er32(FEXTNVM11);
3860 fext_nvm11 |= E1000_FEXTNVM11_DISABLE_MULR_FIX;
3861 ew32(FEXTNVM11, fext_nvm11);
3862 /* do nothing if we're not in faulty state, or if the queue is empty */
3863 tdlen = er32(TDLEN(0));
ff917429
YL		 3864 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3865 &hang_state);
3866 if (!(hang_state & FLUSH_DESC_REQUIRED) || !tdlen)
ad851fbb
YL		 3867 return;
3868 e1000_flush_tx_ring(adapter);
3869 /* recheck, maybe the fault is caused by the rx ring */
ff917429
YL		 3870 pci_read_config_word(adapter->pdev, PCICFG_DESC_RING_STATUS,
3871 &hang_state);
3872 if (hang_state & FLUSH_DESC_REQUIRED)
ad851fbb
YL		 3873 e1000_flush_rx_ring(adapter);
3874}
3875
aa524b66
JK		 3876/**
3877 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3878 * @adapter: board private structure
3879 *
3880 * When the MAC is reset, all hardware bits for timesync will be reset to the
3881 * default values. This function will restore the settings last in place.
3882 * Since the clock SYSTIME registers are reset, we will simply restore the
3883 * cyclecounter to the kernel real clock time.
3884 **/
3885static void e1000e_systim_reset(struct e1000_adapter *adapter)
3886{
3887 struct ptp_clock_info *info = &adapter->ptp_clock_info;
3888 struct e1000_hw *hw = &adapter->hw;
3889 unsigned long flags;
3890 u32 timinca;
3891 s32 ret_val;
3892
3893 if (!(adapter->flags & FLAG_HAS_HW_TIMESTAMP))
3894 return;
3895
3896 if (info->adjfreq) {
3897 /* restore the previous ptp frequency delta */
3898 ret_val = info->adjfreq(info, adapter->ptp_delta);
3899 } else {
3900 /* set the default base frequency if no adjustment possible */
3901 ret_val = e1000e_get_base_timinca(adapter, &timinca);
3902 if (!ret_val)
3903 ew32(TIMINCA, timinca);
3904 }
3905
3906 if (ret_val) {
3907 dev_warn(&adapter->pdev->dev,
3908 "Failed to restore TIMINCA clock rate delta: %d\n",
3909 ret_val);
3910 return;
3911 }
3912
3913 /* reset the systim ns time counter */
3914 spin_lock_irqsave(&adapter->systim_lock, flags);
3915 timecounter_init(&adapter->tc, &adapter->cc,
3916 ktime_to_ns(ktime_get_real()));
3917 spin_unlock_irqrestore(&adapter->systim_lock, flags);
3918
3919 /* restore the previous hwtstamp configuration settings */
3920 e1000e_config_hwtstamp(adapter, &adapter->hwtstamp_config);
3921}
3922
bc7f75fa
AK		 3923/**
3924 * e1000e_reset - bring the hardware into a known good state
3925 *
3926 * This function boots the hardware and enables some settings that
3927 * require a configuration cycle of the hardware - those cannot be
3928 * set/changed during runtime. After reset the device needs to be
ad68076e 3929 * properly configured for Rx, Tx etc.
bc7f75fa
AK		 3930 */
3931void e1000e_reset(struct e1000_adapter *adapter)
3932{
3933 struct e1000_mac_info *mac = &adapter->hw.mac;
318a94d6 3934 struct e1000_fc_info *fc = &adapter->hw.fc;
bc7f75fa
AK		 3935 struct e1000_hw *hw = &adapter->hw;
3936 u32 tx_space, min_tx_space, min_rx_space;
318a94d6 3937 u32 pba = adapter->pba;
bc7f75fa
AK		 3938 u16 hwm;
3939
ad68076e 3940 /* reset Packet Buffer Allocation to default */
318a94d6 3941 ew32(PBA, pba);
df762464 3942
8084b86d 3943 if (adapter->max_frame_size > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) {
e921eb1a 3944 /* To maintain wire speed transmits, the Tx FIFO should be
bc7f75fa
AK		 3945 * large enough to accommodate two full transmit packets,
3946 * rounded up to the next 1KB and expressed in KB. Likewise,
3947 * the Rx FIFO should be large enough to accommodate at least
3948 * one full receive packet and is similarly rounded up and
ad68076e
BA		 3949 * expressed in KB.
3950 */
df762464 3951 pba = er32(PBA);
bc7f75fa 3952 /* upper 16 bits has Tx packet buffer allocation size in KB */
df762464 3953 tx_space = pba >> 16;
bc7f75fa 3954 /* lower 16 bits has Rx packet buffer allocation size in KB */
df762464 3955 pba &= 0xffff;
e921eb1a 3956 /* the Tx fifo also stores 16 bytes of information about the Tx
ad68076e 3957 * but don't include ethernet FCS because hardware appends it
318a94d6
JK		 3958 */
3959 min_tx_space = (adapter->max_frame_size +
e5fe2541 3960 sizeof(struct e1000_tx_desc) - ETH_FCS_LEN) * 2;
bc7f75fa
AK		 3961 min_tx_space = ALIGN(min_tx_space, 1024);
3962 min_tx_space >>= 10;
3963 /* software strips receive CRC, so leave room for it */
318a94d6 3964 min_rx_space = adapter->max_frame_size;
bc7f75fa
AK		 3965 min_rx_space = ALIGN(min_rx_space, 1024);
3966 min_rx_space >>= 10;
3967
e921eb1a 3968 /* If current Tx allocation is less than the min Tx FIFO size,
bc7f75fa 3969 * and the min Tx FIFO size is less than the current Rx FIFO
ad68076e
BA		 3970 * allocation, take space away from current Rx allocation
3971 */
df762464
AK		 3972 if ((tx_space < min_tx_space) &&
3973 ((min_tx_space - tx_space) < pba)) {
3974 pba -= min_tx_space - tx_space;
bc7f75fa 3975
e921eb1a 3976 /* if short on Rx space, Rx wins and must trump Tx
419e551c 3977 * adjustment
ad68076e 3978 */
79d4e908 3979 if (pba < min_rx_space)
df762464 3980 pba = min_rx_space;
bc7f75fa 3981 }
df762464
AK		 3982
3983 ew32(PBA, pba);
bc7f75fa
AK		 3984 }
3985
e921eb1a 3986 /* flow control settings
ad68076e 3987 *
38eb394e 3988 * The high water mark must be low enough to fit one full frame
bc7f75fa
AK		 3989 * (or the size used for early receive) above it in the Rx FIFO.
3990 * Set it to the lower of:
3991 * - 90% of the Rx FIFO size, and
38eb394e 3992 * - the full Rx FIFO size minus one full frame
ad68076e 3993 */
d3738bb8
BA		 3994 if (adapter->flags & FLAG_DISABLE_FC_PAUSE_TIME)
3995 fc->pause_time = 0xFFFF;
3996 else
3997 fc->pause_time = E1000_FC_PAUSE_TIME;
b20caa80 3998 fc->send_xon = true;
d3738bb8
BA		 3999 fc->current_mode = fc->requested_mode;
4000
4001 switch (hw->mac.type) {
79d4e908
BA		 4002 case e1000_ich9lan:
4003 case e1000_ich10lan:
4004 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4005 pba = 14;
4006 ew32(PBA, pba);
4007 fc->high_water = 0x2800;
4008 fc->low_water = fc->high_water - 8;
4009 break;
4010 }
4011 /* fall-through */
d3738bb8 4012 default:
79d4e908
BA		 4013 hwm = min(((pba << 10) * 9 / 10),
4014 ((pba << 10) - adapter->max_frame_size));
d3738bb8 4015
e80bd1d1 4016 fc->high_water = hwm & E1000_FCRTH_RTH; /* 8-byte granularity */
d3738bb8
BA		 4017 fc->low_water = fc->high_water - 8;
4018 break;
4019 case e1000_pchlan:
e921eb1a 4020 /* Workaround PCH LOM adapter hangs with certain network
38eb394e
BA		 4021 * loads. If hangs persist, try disabling Tx flow control.
4022 */
4023 if (adapter->netdev->mtu > ETH_DATA_LEN) {
4024 fc->high_water = 0x3500;
e80bd1d1 4025 fc->low_water = 0x1500;
38eb394e
BA		 4026 } else {
4027 fc->high_water = 0x5000;
e80bd1d1 4028 fc->low_water = 0x3000;
38eb394e 4029 }
a305595b 4030 fc->refresh_time = 0x1000;
d3738bb8
BA		 4031 break;
4032 case e1000_pch2lan:
2fbe4526 4033 case e1000_pch_lpt:
79849ebc 4034 case e1000_pch_spt:
d3738bb8 4035 fc->refresh_time = 0x0400;
347b5201
BA		 4036
4037 if (adapter->netdev->mtu <= ETH_DATA_LEN) {
4038 fc->high_water = 0x05C20;
4039 fc->low_water = 0x05048;
4040 fc->pause_time = 0x0650;
4041 break;
828bac87 4042 }
347b5201 4043
ce345e08
BA		 4044 pba = 14;
4045 ew32(PBA, pba);
347b5201
BA		 4046 fc->high_water = ((pba << 10) * 9 / 10) & E1000_FCRTH_RTH;
4047 fc->low_water = ((pba << 10) * 8 / 10) & E1000_FCRTL_RTL;
d3738bb8 4048 break;
38eb394e 4049 }
bc7f75fa 4050
e921eb1a 4051 /* Alignment of Tx data is on an arbitrary byte boundary with the
d821a4c4
BA		 4052 * maximum size per Tx descriptor limited only to the transmit
4053 * allocation of the packet buffer minus 96 bytes with an upper
4054 * limit of 24KB due to receive synchronization limitations.
4055 */
4056 adapter->tx_fifo_limit = min_t(u32, ((er32(PBA) >> 16) << 10) - 96,
4057 24 << 10);
4058
e921eb1a 4059 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
79d4e908 4060 * fit in receive buffer.
828bac87
BA		 4061 */
4062 if (adapter->itr_setting & 0x3) {
79d4e908 4063 if ((adapter->max_frame_size * 2) > (pba << 10)) {
828bac87
BA		 4064 if (!(adapter->flags2 & FLAG2_DISABLE_AIM)) {
4065 dev_info(&adapter->pdev->dev,
17e813ec 4066 "Interrupt Throttle Rate off\n");
828bac87 4067 adapter->flags2 |= FLAG2_DISABLE_AIM;
22a4cca2 4068 e1000e_write_itr(adapter, 0);
828bac87
BA		 4069 }
4070 } else if (adapter->flags2 & FLAG2_DISABLE_AIM) {
4071 dev_info(&adapter->pdev->dev,
17e813ec 4072 "Interrupt Throttle Rate on\n");
828bac87
BA		 4073 adapter->flags2 &= ~FLAG2_DISABLE_AIM;
4074 adapter->itr = 20000;
22a4cca2 4075 e1000e_write_itr(adapter, adapter->itr);
828bac87
BA		 4076 }
4077 }
4078
0ffc5646
YL		 4079 if (hw->mac.type == e1000_pch_spt)
4080 e1000_flush_desc_rings(adapter);
bc7f75fa
AK		 4081 /* Allow time for pending master requests to run */
4082 mac->ops.reset_hw(hw);
97ac8cae 4083
e921eb1a 4084 /* For parts with AMT enabled, let the firmware know
97ac8cae
BA		 4085 * that the network interface is in control
4086 */
c43bc57e 4087 if (adapter->flags & FLAG_HAS_AMT)
31dbe5b4 4088 e1000e_get_hw_control(adapter);
97ac8cae 4089
bc7f75fa
AK		 4090 ew32(WUC, 0);
4091
4092 if (mac->ops.init_hw(hw))
44defeb3 4093 e_err("Hardware Error\n");
bc7f75fa
AK		 4094
4095 e1000_update_mng_vlan(adapter);
4096
4097 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4098 ew32(VET, ETH_P_8021Q);
4099
4100 e1000e_reset_adaptive(hw);
31dbe5b4 4101
aa524b66
JK		 4102 /* restore systim and hwtstamp settings */
4103 e1000e_systim_reset(adapter);
b67e1913 4104
d495bcb8
BA		 4105 /* Set EEE advertisement as appropriate */
4106 if (adapter->flags2 & FLAG2_HAS_EEE) {
4107 s32 ret_val;
4108 u16 adv_addr;
4109
4110 switch (hw->phy.type) {
4111 case e1000_phy_82579:
4112 adv_addr = I82579_EEE_ADVERTISEMENT;
4113 break;
4114 case e1000_phy_i217:
4115 adv_addr = I217_EEE_ADVERTISEMENT;
4116 break;
4117 default:
4118 dev_err(&adapter->pdev->dev,
4119 "Invalid PHY type setting EEE advertisement\n");
4120 return;
4121 }
4122
4123 ret_val = hw->phy.ops.acquire(hw);
4124 if (ret_val) {
4125 dev_err(&adapter->pdev->dev,
4126 "EEE advertisement - unable to acquire PHY\n");
4127 return;
4128 }
4129
4130 e1000_write_emi_reg_locked(hw, adv_addr,
4131 hw->dev_spec.ich8lan.eee_disable ?
4132 0 : adapter->eee_advert);
4133
4134 hw->phy.ops.release(hw);
4135 }
4136
31dbe5b4 4137 if (!netif_running(adapter->netdev) &&
28002099 4138 !test_bit(__E1000_TESTING, &adapter->state))
31dbe5b4 4139 e1000_power_down_phy(adapter);
31dbe5b4 4140
bc7f75fa
AK		 4141 e1000_get_phy_info(hw);
4142
918d7197
BA		 4143 if ((adapter->flags & FLAG_HAS_SMART_POWER_DOWN) &&
4144 !(adapter->flags & FLAG_SMART_POWER_DOWN)) {
bc7f75fa 4145 u16 phy_data = 0;
e921eb1a 4146 /* speed up time to link by disabling smart power down, ignore
bc7f75fa 4147 * the return value of this function because there is nothing
ad68076e
BA		 4148 * different we would do if it failed
4149 */
bc7f75fa
AK		 4150 e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
4151 phy_data &= ~IGP02E1000_PM_SPD;
4152 e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
4153 }
ec945cfb
YL		 4154 if (hw->mac.type == e1000_pch_spt && adapter->int_mode == 0) {
4155 u32 reg;
4156
4157 /* Fextnvm7 @ 0xe4[2] = 1 */
4158 reg = er32(FEXTNVM7);
4159 reg |= E1000_FEXTNVM7_SIDE_CLK_UNGATE;
4160 ew32(FEXTNVM7, reg);
4161 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4162 reg = er32(FEXTNVM9);
4163 reg |= E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS |
4164 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4165 ew32(FEXTNVM9, reg);
4166 }
4167
bc7f75fa
AK		 4168}
4169
a61cfe4f
BP		 4170/**
4171 * e1000e_trigger_lsc - trigger an LSC interrupt
4172 * @adapter:
4173 *
4174 * Fire a link status change interrupt to start the watchdog.
4175 **/
4176static void e1000e_trigger_lsc(struct e1000_adapter *adapter)
bc7f75fa
AK		 4177{
4178 struct e1000_hw *hw = &adapter->hw;
4179
a61cfe4f
BP		 4180 if (adapter->msix_entries)
4181 ew32(ICS, E1000_ICS_OTHER);
4182 else
4183 ew32(ICS, E1000_ICS_LSC);
4184}
4185
4186void e1000e_up(struct e1000_adapter *adapter)
4187{
bc7f75fa
AK		 4188 /* hardware has been reset, we need to reload some things */
4189 e1000_configure(adapter);
4190
4191 clear_bit(__E1000_DOWN, &adapter->state);
4192
4662e82b
BA		 4193 if (adapter->msix_entries)
4194 e1000_configure_msix(adapter);
bc7f75fa
AK		 4195 e1000_irq_enable(adapter);
4196
400484fa 4197 netif_start_queue(adapter->netdev);
4cb9be7a 4198
a61cfe4f 4199 e1000e_trigger_lsc(adapter);
bc7f75fa
AK		 4200}
4201
713b3c9e
JB		 4202static void e1000e_flush_descriptors(struct e1000_adapter *adapter)
4203{
4204 struct e1000_hw *hw = &adapter->hw;
4205
4206 if (!(adapter->flags2 & FLAG2_DMA_BURST))
4207 return;
4208
4209 /* flush pending descriptor writebacks to memory */
4210 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4211 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
4212
4213 /* execute the writes immediately */
4214 e1e_flush();
bf03085f 4215
e921eb1a 4216 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
bf03085f
MV		 4217 * write is successful
4218 */
4219 ew32(TIDV, adapter->tx_int_delay | E1000_TIDV_FPD);
4220 ew32(RDTR, adapter->rx_int_delay | E1000_RDTR_FPD);
713b3c9e
JB		 4221
4222 /* execute the writes immediately */
4223 e1e_flush();
4224}
4225
67fd4fcb
JK		 4226static void e1000e_update_stats(struct e1000_adapter *adapter);
4227
28002099
DE		 4228/**
4229 * e1000e_down - quiesce the device and optionally reset the hardware
4230 * @adapter: board private structure
4231 * @reset: boolean flag to reset the hardware or not
4232 */
4233void e1000e_down(struct e1000_adapter *adapter, bool reset)
bc7f75fa
AK		 4234{
4235 struct net_device *netdev = adapter->netdev;
4236 struct e1000_hw *hw = &adapter->hw;
4237 u32 tctl, rctl;
4238
e921eb1a 4239 /* signal that we're down so the interrupt handler does not
ad68076e
BA		 4240 * reschedule our watchdog timer
4241 */
bc7f75fa
AK		 4242 set_bit(__E1000_DOWN, &adapter->state);
4243
a60a132e
ET		 4244 netif_carrier_off(netdev);
4245
bc7f75fa
AK		 4246 /* disable receives in the hardware */
4247 rctl = er32(RCTL);
7f99ae63
BA		 4248 if (!(adapter->flags2 & FLAG2_NO_DISABLE_RX))
4249 ew32(RCTL, rctl & ~E1000_RCTL_EN);
bc7f75fa
AK		 4250 /* flush and sleep below */
4251
4cb9be7a 4252 netif_stop_queue(netdev);
bc7f75fa
AK		 4253
4254 /* disable transmits in the hardware */
4255 tctl = er32(TCTL);
4256 tctl &= ~E1000_TCTL_EN;
4257 ew32(TCTL, tctl);
7f99ae63 4258
bc7f75fa
AK		 4259 /* flush both disables and wait for them to finish */
4260 e1e_flush();
1bba4386 4261 usleep_range(10000, 20000);
bc7f75fa 4262
bc7f75fa
AK		 4263 e1000_irq_disable(adapter);
4264
a3b87a4c
BA		 4265 napi_synchronize(&adapter->napi);
4266
bc7f75fa
AK		 4267 del_timer_sync(&adapter->watchdog_timer);
4268 del_timer_sync(&adapter->phy_info_timer);
4269
67fd4fcb
JK		 4270 spin_lock(&adapter->stats64_lock);
4271 e1000e_update_stats(adapter);
4272 spin_unlock(&adapter->stats64_lock);
4273
400484fa 4274 e1000e_flush_descriptors(adapter);
400484fa 4275
bc7f75fa
AK		 4276 adapter->link_speed = 0;
4277 adapter->link_duplex = 0;
4278
da1e2046
BA		 4279 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4280 if ((hw->mac.type >= e1000_pch2lan) &&
4281 (adapter->netdev->mtu > ETH_DATA_LEN) &&
4282 e1000_lv_jumbo_workaround_ich8lan(hw, false))
4283 e_dbg("failed to disable jumbo frame workaround mode\n");
4284
0ffc5646
YL		 4285 if (!pci_channel_offline(adapter->pdev)) {
4286 if (reset)
4287 e1000e_reset(adapter);
4288 else if (hw->mac.type == e1000_pch_spt)
4289 e1000_flush_desc_rings(adapter);
4290 }
4291 e1000_clean_tx_ring(adapter->tx_ring);
4292 e1000_clean_rx_ring(adapter->rx_ring);
bc7f75fa
AK		 4293}
4294
4295void e1000e_reinit_locked(struct e1000_adapter *adapter)
4296{
4297 might_sleep();
4298 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 4299 usleep_range(1000, 2000);
28002099 4300 e1000e_down(adapter, true);
bc7f75fa
AK		 4301 e1000e_up(adapter);
4302 clear_bit(__E1000_RESETTING, &adapter->state);
4303}
4304
b67e1913
BA		 4305/**
4306 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4307 * @cc: cyclecounter structure
4308 **/
4309static cycle_t e1000e_cyclecounter_read(const struct cyclecounter *cc)
4310{
4311 struct e1000_adapter *adapter = container_of(cc, struct e1000_adapter,
4312 cc);
4313 struct e1000_hw *hw = &adapter->hw;
ab507c9a 4314 u32 systimel, systimeh;
5e7ff970 4315 cycle_t systim, systim_next;
37b12910
RA		 4316 /* SYSTIMH latching upon SYSTIML read does not work well.
4317 * This means that if SYSTIML overflows after we read it but before
4318 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4319 * will experience a huge non linear increment in the systime value
4320 * to fix that we test for overflow and if true, we re-read systime.
83129b37 4321 */
ab507c9a 4322 systimel = er32(SYSTIML);
37b12910 4323 systimeh = er32(SYSTIMH);
ab507c9a
DV		 4324 /* Is systimel is so large that overflow is possible? */
4325 if (systimel >= (u32)0xffffffff - E1000_TIMINCA_INCVALUE_MASK) {
4326 u32 systimel_2 = er32(SYSTIML);
4327 if (systimel > systimel_2) {
4328 /* There was an overflow, read again SYSTIMH, and use
4329 * systimel_2
4330 */
4331 systimeh = er32(SYSTIMH);
4332 systimel = systimel_2;
4333 }
37b12910 4334 }
ab507c9a
DV		 4335 systim = (cycle_t)systimel;
4336 systim |= (cycle_t)systimeh << 32;
b67e1913 4337
5e7ff970 4338 if ((hw->mac.type == e1000_82574) || (hw->mac.type == e1000_82583)) {
fb5277f2
DV		 4339 u64 time_delta, rem, temp;
4340 u32 incvalue;
5e7ff970
TF		 4341 int i;
4342
4343 /* errata for 82574/82583 possible bad bits read from SYSTIMH/L
4344 * check to see that the time is incrementing at a reasonable
4345 * rate and is a multiple of incvalue
4346 */
4347 incvalue = er32(TIMINCA) & E1000_TIMINCA_INCVALUE_MASK;
4348 for (i = 0; i < E1000_MAX_82574_SYSTIM_REREADS; i++) {
4349 /* latch SYSTIMH on read of SYSTIML */
4350 systim_next = (cycle_t)er32(SYSTIML);
4351 systim_next |= (cycle_t)er32(SYSTIMH) << 32;
4352
4353 time_delta = systim_next - systim;
4354 temp = time_delta;
3d05b15b
DV		 4355 /* VMWare users have seen incvalue of zero, don't div / 0 */
4356 rem = incvalue ? do_div(temp, incvalue) : (time_delta != 0);
5e7ff970
TF		 4357
4358 systim = systim_next;
4359
4360 if ((time_delta < E1000_82574_SYSTIM_EPSILON) &&
4361 (rem == 0))
4362 break;
4363 }
4364 }
b67e1913
BA		 4365 return systim;
4366}
4367
bc7f75fa
AK		 4368/**
4369 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4370 * @adapter: board private structure to initialize
4371 *
4372 * e1000_sw_init initializes the Adapter private data structure.
4373 * Fields are initialized based on PCI device information and
4374 * OS network device settings (MTU size).
4375 **/
9f9a12f8 4376static int e1000_sw_init(struct e1000_adapter *adapter)
bc7f75fa 4377{
bc7f75fa
AK		 4378 struct net_device *netdev = adapter->netdev;
4379
8084b86d 4380 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
bc7f75fa 4381 adapter->rx_ps_bsize0 = 128;
8084b86d 4382 adapter->max_frame_size = netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
318a94d6 4383 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
55aa6985
BA		 4384 adapter->tx_ring_count = E1000_DEFAULT_TXD;
4385 adapter->rx_ring_count = E1000_DEFAULT_RXD;
bc7f75fa 4386
67fd4fcb
JK		 4387 spin_lock_init(&adapter->stats64_lock);
4388
4662e82b 4389 e1000e_set_interrupt_capability(adapter);
bc7f75fa 4390
4662e82b
BA		 4391 if (e1000_alloc_queues(adapter))
4392 return -ENOMEM;
bc7f75fa 4393
b67e1913
BA		 4394 /* Setup hardware time stamping cyclecounter */
4395 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
4396 adapter->cc.read = e1000e_cyclecounter_read;
4d045b4c 4397 adapter->cc.mask = CYCLECOUNTER_MASK(64);
b67e1913
BA		 4398 adapter->cc.mult = 1;
4399 /* cc.shift set in e1000e_get_base_tininca() */
4400
4401 spin_lock_init(&adapter->systim_lock);
4402 INIT_WORK(&adapter->tx_hwtstamp_work, e1000e_tx_hwtstamp_work);
4403 }
4404
bc7f75fa 4405 /* Explicitly disable IRQ since the NIC can be in any state. */
bc7f75fa
AK		 4406 e1000_irq_disable(adapter);
4407
bc7f75fa
AK		 4408 set_bit(__E1000_DOWN, &adapter->state);
4409 return 0;
bc7f75fa
AK		 4410}
4411
f8d59f78
BA		 4412/**
4413 * e1000_intr_msi_test - Interrupt Handler
4414 * @irq: interrupt number
4415 * @data: pointer to a network interface device structure
4416 **/
8bb62869 4417static irqreturn_t e1000_intr_msi_test(int __always_unused irq, void *data)
f8d59f78
BA		 4418{
4419 struct net_device *netdev = data;
4420 struct e1000_adapter *adapter = netdev_priv(netdev);
4421 struct e1000_hw *hw = &adapter->hw;
4422 u32 icr = er32(ICR);
4423
3bb99fe2 4424 e_dbg("icr is %08X\n", icr);
f8d59f78
BA		 4425 if (icr & E1000_ICR_RXSEQ) {
4426 adapter->flags &= ~FLAG_MSI_TEST_FAILED;
e921eb1a 4427 /* Force memory writes to complete before acknowledging the
bc76329d
BA		 4428 * interrupt is handled.
4429 */
f8d59f78
BA		 4430 wmb();
4431 }
4432
4433 return IRQ_HANDLED;
4434}
4435
4436/**
4437 * e1000_test_msi_interrupt - Returns 0 for successful test
4438 * @adapter: board private struct
4439 *
4440 * code flow taken from tg3.c
4441 **/
4442static int e1000_test_msi_interrupt(struct e1000_adapter *adapter)
4443{
4444 struct net_device *netdev = adapter->netdev;
4445 struct e1000_hw *hw = &adapter->hw;
4446 int err;
4447
4448 /* poll_enable hasn't been called yet, so don't need disable */
4449 /* clear any pending events */
4450 er32(ICR);
4451
4452 /* free the real vector and request a test handler */
4453 e1000_free_irq(adapter);
4662e82b 4454 e1000e_reset_interrupt_capability(adapter);
f8d59f78
BA		 4455
4456 /* Assume that the test fails, if it succeeds then the test
e921eb1a
BA		 4457 * MSI irq handler will unset this flag
4458 */
f8d59f78
BA		 4459 adapter->flags |= FLAG_MSI_TEST_FAILED;
4460
4461 err = pci_enable_msi(adapter->pdev);
4462 if (err)
4463 goto msi_test_failed;
4464
a0607fd3 4465 err = request_irq(adapter->pdev->irq, e1000_intr_msi_test, 0,
f8d59f78
BA		 4466 netdev->name, netdev);
4467 if (err) {
4468 pci_disable_msi(adapter->pdev);
4469 goto msi_test_failed;
4470 }
4471
e921eb1a 4472 /* Force memory writes to complete before enabling and firing an
bc76329d
BA		 4473 * interrupt.
4474 */
f8d59f78
BA		 4475 wmb();
4476
4477 e1000_irq_enable(adapter);
4478
4479 /* fire an unusual interrupt on the test handler */
4480 ew32(ICS, E1000_ICS_RXSEQ);
4481 e1e_flush();
569a3aff 4482 msleep(100);
f8d59f78
BA		 4483
4484 e1000_irq_disable(adapter);
4485
bc76329d 4486 rmb(); /* read flags after interrupt has been fired */
f8d59f78
BA		 4487
4488 if (adapter->flags & FLAG_MSI_TEST_FAILED) {
4662e82b 4489 adapter->int_mode = E1000E_INT_MODE_LEGACY;
068e8a30 4490 e_info("MSI interrupt test failed, using legacy interrupt.\n");
24b706b2 4491 } else {
068e8a30 4492 e_dbg("MSI interrupt test succeeded!\n");
24b706b2 4493 }
f8d59f78
BA		 4494
4495 free_irq(adapter->pdev->irq, netdev);
4496 pci_disable_msi(adapter->pdev);
4497
f8d59f78 4498msi_test_failed:
4662e82b 4499 e1000e_set_interrupt_capability(adapter);
068e8a30 4500 return e1000_request_irq(adapter);
f8d59f78
BA		 4501}
4502
4503/**
4504 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4505 * @adapter: board private struct
4506 *
4507 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4508 **/
4509static int e1000_test_msi(struct e1000_adapter *adapter)
4510{
4511 int err;
4512 u16 pci_cmd;
4513
4514 if (!(adapter->flags & FLAG_MSI_ENABLED))
4515 return 0;
4516
4517 /* disable SERR in case the MSI write causes a master abort */
4518 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
36f2407f
DN		 4519 if (pci_cmd & PCI_COMMAND_SERR)
4520 pci_write_config_word(adapter->pdev, PCI_COMMAND,
4521 pci_cmd & ~PCI_COMMAND_SERR);
f8d59f78
BA		 4522
4523 err = e1000_test_msi_interrupt(adapter);
4524
36f2407f
DN		 4525 /* re-enable SERR */
4526 if (pci_cmd & PCI_COMMAND_SERR) {
4527 pci_read_config_word(adapter->pdev, PCI_COMMAND, &pci_cmd);
4528 pci_cmd |= PCI_COMMAND_SERR;
4529 pci_write_config_word(adapter->pdev, PCI_COMMAND, pci_cmd);
4530 }
f8d59f78 4531
f8d59f78
BA		 4532 return err;
4533}
4534
bc7f75fa 4535/**
d5ea45da 4536 * e1000e_open - Called when a network interface is made active
bc7f75fa
AK		 4537 * @netdev: network interface device structure
4538 *
4539 * Returns 0 on success, negative value on failure
4540 *
4541 * The open entry point is called when a network interface is made
4542 * active by the system (IFF_UP). At this point all resources needed
4543 * for transmit and receive operations are allocated, the interrupt
4544 * handler is registered with the OS, the watchdog timer is started,
4545 * and the stack is notified that the interface is ready.
4546 **/
d5ea45da 4547int e1000e_open(struct net_device *netdev)
bc7f75fa
AK		 4548{
4549 struct e1000_adapter *adapter = netdev_priv(netdev);
4550 struct e1000_hw *hw = &adapter->hw;
23606cf5 4551 struct pci_dev *pdev = adapter->pdev;
bc7f75fa
AK		 4552 int err;
4553
4554 /* disallow open during test */
4555 if (test_bit(__E1000_TESTING, &adapter->state))
4556 return -EBUSY;
4557
23606cf5
RW		 4558 pm_runtime_get_sync(&pdev->dev);
4559
9c563d20
JB		 4560 netif_carrier_off(netdev);
4561
bc7f75fa 4562 /* allocate transmit descriptors */
55aa6985 4563 err = e1000e_setup_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4564 if (err)
4565 goto err_setup_tx;
4566
4567 /* allocate receive descriptors */
55aa6985 4568 err = e1000e_setup_rx_resources(adapter->rx_ring);
bc7f75fa
AK		 4569 if (err)
4570 goto err_setup_rx;
4571
e921eb1a 4572 /* If AMT is enabled, let the firmware know that the network
11b08be8
BA		 4573 * interface is now open and reset the part to a known state.
4574 */
4575 if (adapter->flags & FLAG_HAS_AMT) {
31dbe5b4 4576 e1000e_get_hw_control(adapter);
11b08be8
BA		 4577 e1000e_reset(adapter);
4578 }
4579
bc7f75fa
AK		 4580 e1000e_power_up_phy(adapter);
4581
4582 adapter->mng_vlan_id = E1000_MNG_VLAN_NONE;
e5fe2541 4583 if ((adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
bc7f75fa
AK		 4584 e1000_update_mng_vlan(adapter);
4585
79d4e908 4586 /* DMA latency requirement to workaround jumbo issue */
e2c65448 4587 pm_qos_add_request(&adapter->pm_qos_req, PM_QOS_CPU_DMA_LATENCY,
3e35d991 4588 PM_QOS_DEFAULT_VALUE);
c128ec29 4589
e921eb1a 4590 /* before we allocate an interrupt, we must be ready to handle it.
bc7f75fa
AK		 4591 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4592 * as soon as we call pci_request_irq, so we have to setup our
ad68076e
BA		 4593 * clean_rx handler before we do so.
4594 */
bc7f75fa
AK		 4595 e1000_configure(adapter);
4596
4597 err = e1000_request_irq(adapter);
4598 if (err)
4599 goto err_req_irq;
4600
e921eb1a 4601 /* Work around PCIe errata with MSI interrupts causing some chipsets to
f8d59f78
BA		 4602 * ignore e1000e MSI messages, which means we need to test our MSI
4603 * interrupt now
4604 */
4662e82b 4605 if (adapter->int_mode != E1000E_INT_MODE_LEGACY) {
f8d59f78
BA		 4606 err = e1000_test_msi(adapter);
4607 if (err) {
4608 e_err("Interrupt allocation failed\n");
4609 goto err_req_irq;
4610 }
4611 }
4612
bc7f75fa
AK		 4613 /* From here on the code is the same as e1000e_up() */
4614 clear_bit(__E1000_DOWN, &adapter->state);
4615
4616 napi_enable(&adapter->napi);
4617
4618 e1000_irq_enable(adapter);
4619
09357b00 4620 adapter->tx_hang_recheck = false;
4cb9be7a 4621 netif_start_queue(netdev);
d55b53ff 4622
66148bab 4623 hw->mac.get_link_status = true;
23606cf5
RW		 4624 pm_runtime_put(&pdev->dev);
4625
a61cfe4f 4626 e1000e_trigger_lsc(adapter);
bc7f75fa
AK		 4627
4628 return 0;
4629
4630err_req_irq:
7faae964 4631 pm_qos_remove_request(&adapter->pm_qos_req);
31dbe5b4 4632 e1000e_release_hw_control(adapter);
bc7f75fa 4633 e1000_power_down_phy(adapter);
55aa6985 4634 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4635err_setup_rx:
55aa6985 4636 e1000e_free_tx_resources(adapter->tx_ring);
bc7f75fa
AK		 4637err_setup_tx:
4638 e1000e_reset(adapter);
23606cf5 4639 pm_runtime_put_sync(&pdev->dev);
bc7f75fa
AK		 4640
4641 return err;
4642}
4643
4644/**
d5ea45da 4645 * e1000e_close - Disables a network interface
bc7f75fa
AK		 4646 * @netdev: network interface device structure
4647 *
4648 * Returns 0, this is not allowed to fail
4649 *
4650 * The close entry point is called when an interface is de-activated
4651 * by the OS. The hardware is still under the drivers control, but
4652 * needs to be disabled. A global MAC reset is issued to stop the
4653 * hardware, and all transmit and receive resources are freed.
4654 **/
d5ea45da 4655int e1000e_close(struct net_device *netdev)
bc7f75fa
AK		 4656{
4657 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5 4658 struct pci_dev *pdev = adapter->pdev;
bb9e44d0
BA		 4659 int count = E1000_CHECK_RESET_COUNT;
4660
4661 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
4662 usleep_range(10000, 20000);
bc7f75fa
AK		 4663
4664 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
23606cf5
RW		 4665
4666 pm_runtime_get_sync(&pdev->dev);
4667
4668 if (!test_bit(__E1000_DOWN, &adapter->state)) {
28002099 4669 e1000e_down(adapter, true);
23606cf5 4670 e1000_free_irq(adapter);
63eb48f1
DE		 4671
4672 /* Link status message must follow this format */
4673 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
23606cf5 4674 }
a3b87a4c
BA		 4675
4676 napi_disable(&adapter->napi);
4677
55aa6985
BA		 4678 e1000e_free_tx_resources(adapter->tx_ring);
4679 e1000e_free_rx_resources(adapter->rx_ring);
bc7f75fa 4680
e921eb1a 4681 /* kill manageability vlan ID if supported, but not if a vlan with
ad68076e
BA		 4682 * the same ID is registered on the host OS (let 8021q kill it)
4683 */
e5fe2541 4684 if (adapter->hw.mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN)
80d5c368
PM		 4685 e1000_vlan_rx_kill_vid(netdev, htons(ETH_P_8021Q),
4686 adapter->mng_vlan_id);
bc7f75fa 4687
e921eb1a 4688 /* If AMT is enabled, let the firmware know that the network
ad68076e
BA		 4689 * interface is now closed
4690 */
31dbe5b4
BA		 4691 if ((adapter->flags & FLAG_HAS_AMT) &&
4692 !test_bit(__E1000_TESTING, &adapter->state))
4693 e1000e_release_hw_control(adapter);
bc7f75fa 4694
e2c65448 4695 pm_qos_remove_request(&adapter->pm_qos_req);
c128ec29 4696
23606cf5
RW		 4697 pm_runtime_put_sync(&pdev->dev);
4698
bc7f75fa
AK		 4699 return 0;
4700}
fc830b78 4701
bc7f75fa
AK		 4702/**
4703 * e1000_set_mac - Change the Ethernet Address of the NIC
4704 * @netdev: network interface device structure
4705 * @p: pointer to an address structure
4706 *
4707 * Returns 0 on success, negative on failure
4708 **/
4709static int e1000_set_mac(struct net_device *netdev, void *p)
4710{
4711 struct e1000_adapter *adapter = netdev_priv(netdev);
69e1e019 4712 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 4713 struct sockaddr *addr = p;
4714
4715 if (!is_valid_ether_addr(addr->sa_data))
4716 return -EADDRNOTAVAIL;
4717
4718 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
4719 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
4720
69e1e019 4721 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
bc7f75fa
AK		 4722
4723 if (adapter->flags & FLAG_RESET_OVERWRITES_LAA) {
4724 /* activate the work around */
4725 e1000e_set_laa_state_82571(&adapter->hw, 1);
4726
e921eb1a 4727 /* Hold a copy of the LAA in RAR[14] This is done so that
bc7f75fa
AK		 4728 * between the time RAR[0] gets clobbered and the time it
4729 * gets fixed (in e1000_watchdog), the actual LAA is in one
4730 * of the RARs and no incoming packets directed to this port
4731 * are dropped. Eventually the LAA will be in RAR[0] and
ad68076e
BA		 4732 * RAR[14]
4733 */
69e1e019
BA		 4734 hw->mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr,
4735 adapter->hw.mac.rar_entry_count - 1);
bc7f75fa
AK		 4736 }
4737
4738 return 0;
4739}
4740
a8f88ff5
JB		 4741/**
4742 * e1000e_update_phy_task - work thread to update phy
4743 * @work: pointer to our work struct
4744 *
4745 * this worker thread exists because we must acquire a
4746 * semaphore to read the phy, which we could msleep while
4747 * waiting for it, and we can't msleep in a timer.
4748 **/
4749static void e1000e_update_phy_task(struct work_struct *work)
4750{
4751 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 4752 struct e1000_adapter,
4753 update_phy_task);
a03206ed 4754 struct e1000_hw *hw = &adapter->hw;
615b32af
JB		 4755
4756 if (test_bit(__E1000_DOWN, &adapter->state))
4757 return;
4758
a03206ed
DE		 4759 e1000_get_phy_info(hw);
4760
4761 /* Enable EEE on 82579 after link up */
50844bb7 4762 if (hw->phy.type >= e1000_phy_82579)
a03206ed 4763 e1000_set_eee_pchlan(hw);
a8f88ff5
JB		 4764}
4765
e921eb1a
BA		 4766/**
4767 * e1000_update_phy_info - timre call-back to update PHY info
4768 * @data: pointer to adapter cast into an unsigned long
4769 *
ad68076e
BA		 4770 * Need to wait a few seconds after link up to get diagnostic information from
4771 * the phy
e921eb1a 4772 **/
bc7f75fa
AK		 4773static void e1000_update_phy_info(unsigned long data)
4774{
53aa82da 4775 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
615b32af
JB		 4776
4777 if (test_bit(__E1000_DOWN, &adapter->state))
4778 return;
4779
a8f88ff5 4780 schedule_work(&adapter->update_phy_task);
bc7f75fa
AK		 4781}
4782
8c7bbb92
BA		 4783/**
4784 * e1000e_update_phy_stats - Update the PHY statistics counters
4785 * @adapter: board private structure
2b6b168d
BA		 4786 *
4787 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
8c7bbb92
BA		 4788 **/
4789static void e1000e_update_phy_stats(struct e1000_adapter *adapter)
4790{
4791 struct e1000_hw *hw = &adapter->hw;
4792 s32 ret_val;
4793 u16 phy_data;
4794
4795 ret_val = hw->phy.ops.acquire(hw);
4796 if (ret_val)
4797 return;
4798
e921eb1a 4799 /* A page set is expensive so check if already on desired page.
8c7bbb92
BA		 4800 * If not, set to the page with the PHY status registers.
4801 */
2b6b168d 4802 hw->phy.addr = 1;
8c7bbb92
BA		 4803 ret_val = e1000e_read_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT,
4804 &phy_data);
4805 if (ret_val)
4806 goto release;
2b6b168d
BA		 4807 if (phy_data != (HV_STATS_PAGE << IGP_PAGE_SHIFT)) {
4808 ret_val = hw->phy.ops.set_page(hw,
4809 HV_STATS_PAGE << IGP_PAGE_SHIFT);
8c7bbb92
BA		 4810 if (ret_val)
4811 goto release;
4812 }
4813
8c7bbb92 4814 /* Single Collision Count */
2b6b168d
BA		 4815 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
4816 ret_val = hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
8c7bbb92
BA		 4817 if (!ret_val)
4818 adapter->stats.scc += phy_data;
4819
4820 /* Excessive Collision Count */
2b6b168d
BA		 4821 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
4822 ret_val = hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
8c7bbb92
BA		 4823 if (!ret_val)
4824 adapter->stats.ecol += phy_data;
4825
4826 /* Multiple Collision Count */
2b6b168d
BA		 4827 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
4828 ret_val = hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
8c7bbb92
BA		 4829 if (!ret_val)
4830 adapter->stats.mcc += phy_data;
4831
4832 /* Late Collision Count */
2b6b168d
BA		 4833 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
4834 ret_val = hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
8c7bbb92
BA		 4835 if (!ret_val)
4836 adapter->stats.latecol += phy_data;
4837
4838 /* Collision Count - also used for adaptive IFS */
2b6b168d
BA		 4839 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
4840 ret_val = hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
8c7bbb92
BA		 4841 if (!ret_val)
4842 hw->mac.collision_delta = phy_data;
4843
4844 /* Defer Count */
2b6b168d
BA		 4845 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
4846 ret_val = hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
8c7bbb92
BA		 4847 if (!ret_val)
4848 adapter->stats.dc += phy_data;
4849
4850 /* Transmit with no CRS */
2b6b168d
BA		 4851 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
4852 ret_val = hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
8c7bbb92
BA		 4853 if (!ret_val)
4854 adapter->stats.tncrs += phy_data;
4855
4856release:
4857 hw->phy.ops.release(hw);
4858}
4859
bc7f75fa
AK		 4860/**
4861 * e1000e_update_stats - Update the board statistics counters
4862 * @adapter: board private structure
4863 **/
67fd4fcb 4864static void e1000e_update_stats(struct e1000_adapter *adapter)
bc7f75fa 4865{
7274c20f 4866 struct net_device *netdev = adapter->netdev;
bc7f75fa
AK		 4867 struct e1000_hw *hw = &adapter->hw;
4868 struct pci_dev *pdev = adapter->pdev;
bc7f75fa 4869
e921eb1a 4870 /* Prevent stats update while adapter is being reset, or if the pci
bc7f75fa
AK		 4871 * connection is down.
4872 */
4873 if (adapter->link_speed == 0)
4874 return;
4875 if (pci_channel_offline(pdev))
4876 return;
4877
bc7f75fa
AK		 4878 adapter->stats.crcerrs += er32(CRCERRS);
4879 adapter->stats.gprc += er32(GPRC);
7c25769f 4880 adapter->stats.gorc += er32(GORCL);
e80bd1d1 4881 er32(GORCH); /* Clear gorc */
bc7f75fa
AK		 4882 adapter->stats.bprc += er32(BPRC);
4883 adapter->stats.mprc += er32(MPRC);
4884 adapter->stats.roc += er32(ROC);
4885
bc7f75fa 4886 adapter->stats.mpc += er32(MPC);
8c7bbb92
BA		 4887
4888 /* Half-duplex statistics */
4889 if (adapter->link_duplex == HALF_DUPLEX) {
4890 if (adapter->flags2 & FLAG2_HAS_PHY_STATS) {
4891 e1000e_update_phy_stats(adapter);
4892 } else {
4893 adapter->stats.scc += er32(SCC);
4894 adapter->stats.ecol += er32(ECOL);
4895 adapter->stats.mcc += er32(MCC);
4896 adapter->stats.latecol += er32(LATECOL);
4897 adapter->stats.dc += er32(DC);
4898
4899 hw->mac.collision_delta = er32(COLC);
4900
4901 if ((hw->mac.type != e1000_82574) &&
4902 (hw->mac.type != e1000_82583))
4903 adapter->stats.tncrs += er32(TNCRS);
4904 }
4905 adapter->stats.colc += hw->mac.collision_delta;
a4f58f54 4906 }
8c7bbb92 4907
bc7f75fa
AK		 4908 adapter->stats.xonrxc += er32(XONRXC);
4909 adapter->stats.xontxc += er32(XONTXC);
4910 adapter->stats.xoffrxc += er32(XOFFRXC);
4911 adapter->stats.xofftxc += er32(XOFFTXC);
bc7f75fa 4912 adapter->stats.gptc += er32(GPTC);
7c25769f 4913 adapter->stats.gotc += er32(GOTCL);
e80bd1d1 4914 er32(GOTCH); /* Clear gotc */
bc7f75fa
AK		 4915 adapter->stats.rnbc += er32(RNBC);
4916 adapter->stats.ruc += er32(RUC);
bc7f75fa
AK		 4917
4918 adapter->stats.mptc += er32(MPTC);
4919 adapter->stats.bptc += er32(BPTC);
4920
4921 /* used for adaptive IFS */
4922
4923 hw->mac.tx_packet_delta = er32(TPT);
4924 adapter->stats.tpt += hw->mac.tx_packet_delta;
bc7f75fa
AK		 4925
4926 adapter->stats.algnerrc += er32(ALGNERRC);
4927 adapter->stats.rxerrc += er32(RXERRC);
bc7f75fa
AK		 4928 adapter->stats.cexterr += er32(CEXTERR);
4929 adapter->stats.tsctc += er32(TSCTC);
4930 adapter->stats.tsctfc += er32(TSCTFC);
4931
bc7f75fa 4932 /* Fill out the OS statistics structure */
7274c20f
AK		 4933 netdev->stats.multicast = adapter->stats.mprc;
4934 netdev->stats.collisions = adapter->stats.colc;
bc7f75fa
AK		 4935
4936 /* Rx Errors */
4937
e921eb1a 4938 /* RLEC on some newer hardware can be incorrect so build
ad68076e
BA		 4939 * our own version based on RUC and ROC
4940 */
7274c20f 4941 netdev->stats.rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 4942 adapter->stats.crcerrs + adapter->stats.algnerrc +
4943 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
7274c20f 4944 netdev->stats.rx_length_errors = adapter->stats.ruc +
f0ff4398 4945 adapter->stats.roc;
7274c20f
AK		 4946 netdev->stats.rx_crc_errors = adapter->stats.crcerrs;
4947 netdev->stats.rx_frame_errors = adapter->stats.algnerrc;
4948 netdev->stats.rx_missed_errors = adapter->stats.mpc;
bc7f75fa
AK		 4949
4950 /* Tx Errors */
f0ff4398 4951 netdev->stats.tx_errors = adapter->stats.ecol + adapter->stats.latecol;
7274c20f
AK		 4952 netdev->stats.tx_aborted_errors = adapter->stats.ecol;
4953 netdev->stats.tx_window_errors = adapter->stats.latecol;
4954 netdev->stats.tx_carrier_errors = adapter->stats.tncrs;
bc7f75fa
AK		 4955
4956 /* Tx Dropped needs to be maintained elsewhere */
4957
bc7f75fa
AK		 4958 /* Management Stats */
4959 adapter->stats.mgptc += er32(MGTPTC);
4960 adapter->stats.mgprc += er32(MGTPRC);
4961 adapter->stats.mgpdc += er32(MGTPDC);
94fb848b
BA		 4962
4963 /* Correctable ECC Errors */
79849ebc
DE		 4964 if ((hw->mac.type == e1000_pch_lpt) ||
4965 (hw->mac.type == e1000_pch_spt)) {
94fb848b 4966 u32 pbeccsts = er32(PBECCSTS);
6cf08d1c 4967
94fb848b
BA		 4968 adapter->corr_errors +=
4969 pbeccsts & E1000_PBECCSTS_CORR_ERR_CNT_MASK;
4970 adapter->uncorr_errors +=
4971 (pbeccsts & E1000_PBECCSTS_UNCORR_ERR_CNT_MASK) >>
4972 E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT;
4973 }
bc7f75fa
AK		 4974}
4975
7c25769f
BA		 4976/**
4977 * e1000_phy_read_status - Update the PHY register status snapshot
4978 * @adapter: board private structure
4979 **/
4980static void e1000_phy_read_status(struct e1000_adapter *adapter)
4981{
4982 struct e1000_hw *hw = &adapter->hw;
4983 struct e1000_phy_regs *phy = &adapter->phy_regs;
7c25769f 4984
97390ab8
BA		 4985 if (!pm_runtime_suspended((&adapter->pdev->dev)->parent) &&
4986 (er32(STATUS) & E1000_STATUS_LU) &&
7c25769f 4987 (adapter->hw.phy.media_type == e1000_media_type_copper)) {
90da0669
BA		 4988 int ret_val;
4989
c2ade1a4
BA		 4990 ret_val = e1e_rphy(hw, MII_BMCR, &phy->bmcr);
4991 ret_val |= e1e_rphy(hw, MII_BMSR, &phy->bmsr);
4992 ret_val |= e1e_rphy(hw, MII_ADVERTISE, &phy->advertise);
4993 ret_val |= e1e_rphy(hw, MII_LPA, &phy->lpa);
4994 ret_val |= e1e_rphy(hw, MII_EXPANSION, &phy->expansion);
4995 ret_val |= e1e_rphy(hw, MII_CTRL1000, &phy->ctrl1000);
4996 ret_val |= e1e_rphy(hw, MII_STAT1000, &phy->stat1000);
4997 ret_val |= e1e_rphy(hw, MII_ESTATUS, &phy->estatus);
7c25769f 4998 if (ret_val)
44defeb3 4999 e_warn("Error reading PHY register\n");
7c25769f 5000 } else {
e921eb1a 5001 /* Do not read PHY registers if link is not up
7c25769f
BA		 5002 * Set values to typical power-on defaults
5003 */
5004 phy->bmcr = (BMCR_SPEED1000 | BMCR_ANENABLE | BMCR_FULLDPLX);
5005 phy->bmsr = (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL |
5006 BMSR_10HALF | BMSR_ESTATEN | BMSR_ANEGCAPABLE |
5007 BMSR_ERCAP);
5008 phy->advertise = (ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP |
5009 ADVERTISE_ALL | ADVERTISE_CSMA);
5010 phy->lpa = 0;
5011 phy->expansion = EXPANSION_ENABLENPAGE;
5012 phy->ctrl1000 = ADVERTISE_1000FULL;
5013 phy->stat1000 = 0;
5014 phy->estatus = (ESTATUS_1000_TFULL | ESTATUS_1000_THALF);
5015 }
7c25769f
BA		 5016}
5017
bc7f75fa
AK		 5018static void e1000_print_link_info(struct e1000_adapter *adapter)
5019{
bc7f75fa
AK		 5020 struct e1000_hw *hw = &adapter->hw;
5021 u32 ctrl = er32(CTRL);
5022
8f12fe86 5023 /* Link status message must follow this format for user tools */
7dbc1672
BA		 5024 pr_info("%s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n",
5025 adapter->netdev->name, adapter->link_speed,
ef456f85
JK		 5026 adapter->link_duplex == FULL_DUPLEX ? "Full" : "Half",
5027 (ctrl & E1000_CTRL_TFCE) && (ctrl & E1000_CTRL_RFCE) ? "Rx/Tx" :
5028 (ctrl & E1000_CTRL_RFCE) ? "Rx" :
5029 (ctrl & E1000_CTRL_TFCE) ? "Tx" : "None");
bc7f75fa
AK		 5030}
5031
0c6bdb30 5032static bool e1000e_has_link(struct e1000_adapter *adapter)
318a94d6
JK		 5033{
5034 struct e1000_hw *hw = &adapter->hw;
3db1cd5c 5035 bool link_active = false;
318a94d6
JK		 5036 s32 ret_val = 0;
5037
e921eb1a 5038 /* get_link_status is set on LSC (link status) interrupt or
318a94d6
JK		 5039 * Rx sequence error interrupt. get_link_status will stay
5040 * false until the check_for_link establishes link
5041 * for copper adapters ONLY
5042 */
5043 switch (hw->phy.media_type) {
5044 case e1000_media_type_copper:
5045 if (hw->mac.get_link_status) {
5046 ret_val = hw->mac.ops.check_for_link(hw);
5047 link_active = !hw->mac.get_link_status;
5048 } else {
3db1cd5c 5049 link_active = true;
318a94d6
JK		 5050 }
5051 break;
5052 case e1000_media_type_fiber:
5053 ret_val = hw->mac.ops.check_for_link(hw);
5054 link_active = !!(er32(STATUS) & E1000_STATUS_LU);
5055 break;
5056 case e1000_media_type_internal_serdes:
5057 ret_val = hw->mac.ops.check_for_link(hw);
5058 link_active = adapter->hw.mac.serdes_has_link;
5059 break;
5060 default:
5061 case e1000_media_type_unknown:
5062 break;
5063 }
5064
5065 if ((ret_val == E1000_ERR_PHY) && (hw->phy.type == e1000_phy_igp_3) &&
5066 (er32(CTRL) & E1000_PHY_CTRL_GBE_DISABLE)) {
5067 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
44defeb3 5068 e_info("Gigabit has been disabled, downgrading speed\n");
318a94d6
JK		 5069 }
5070
5071 return link_active;
5072}
5073
5074static void e1000e_enable_receives(struct e1000_adapter *adapter)
5075{
5076 /* make sure the receive unit is started */
5077 if ((adapter->flags & FLAG_RX_NEEDS_RESTART) &&
12d43f7d 5078 (adapter->flags & FLAG_RESTART_NOW)) {
318a94d6
JK		 5079 struct e1000_hw *hw = &adapter->hw;
5080 u32 rctl = er32(RCTL);
6cf08d1c 5081
318a94d6 5082 ew32(RCTL, rctl | E1000_RCTL_EN);
12d43f7d 5083 adapter->flags &= ~FLAG_RESTART_NOW;
318a94d6
JK		 5084 }
5085}
5086
ff10e13c
CW		 5087static void e1000e_check_82574_phy_workaround(struct e1000_adapter *adapter)
5088{
5089 struct e1000_hw *hw = &adapter->hw;
5090
e921eb1a 5091 /* With 82574 controllers, PHY needs to be checked periodically
ff10e13c
CW		 5092 * for hung state and reset, if two calls return true
5093 */
5094 if (e1000_check_phy_82574(hw))
5095 adapter->phy_hang_count++;
5096 else
5097 adapter->phy_hang_count = 0;
5098
5099 if (adapter->phy_hang_count > 1) {
5100 adapter->phy_hang_count = 0;
d9554e96 5101 e_dbg("PHY appears hung - resetting\n");
ff10e13c
CW		 5102 schedule_work(&adapter->reset_task);
5103 }
5104}
5105
bc7f75fa
AK		 5106/**
5107 * e1000_watchdog - Timer Call-back
5108 * @data: pointer to adapter cast into an unsigned long
5109 **/
5110static void e1000_watchdog(unsigned long data)
5111{
53aa82da 5112 struct e1000_adapter *adapter = (struct e1000_adapter *)data;
bc7f75fa
AK		 5113
5114 /* Do the rest outside of interrupt context */
5115 schedule_work(&adapter->watchdog_task);
5116
5117 /* TODO: make this use queue_delayed_work() */
5118}
5119
5120static void e1000_watchdog_task(struct work_struct *work)
5121{
5122 struct e1000_adapter *adapter = container_of(work,
17e813ec
BA		 5123 struct e1000_adapter,
5124 watchdog_task);
bc7f75fa
AK		 5125 struct net_device *netdev = adapter->netdev;
5126 struct e1000_mac_info *mac = &adapter->hw.mac;
75eb0fad 5127 struct e1000_phy_info *phy = &adapter->hw.phy;
bc7f75fa
AK		 5128 struct e1000_ring *tx_ring = adapter->tx_ring;
5129 struct e1000_hw *hw = &adapter->hw;
5130 u32 link, tctl;
bc7f75fa 5131
615b32af
JB		 5132 if (test_bit(__E1000_DOWN, &adapter->state))
5133 return;
5134
b405e8df 5135 link = e1000e_has_link(adapter);
318a94d6 5136 if ((netif_carrier_ok(netdev)) && link) {
23606cf5
RW		 5137 /* Cancel scheduled suspend requests. */
5138 pm_runtime_resume(netdev->dev.parent);
5139
318a94d6 5140 e1000e_enable_receives(adapter);
bc7f75fa 5141 goto link_up;
bc7f75fa
AK		 5142 }
5143
5144 if ((e1000e_enable_tx_pkt_filtering(hw)) &&
5145 (adapter->mng_vlan_id != adapter->hw.mng_cookie.vlan_id))
5146 e1000_update_mng_vlan(adapter);
5147
bc7f75fa
AK		 5148 if (link) {
5149 if (!netif_carrier_ok(netdev)) {
3db1cd5c 5150 bool txb2b = true;
23606cf5
RW		 5151
5152 /* Cancel scheduled suspend requests. */
5153 pm_runtime_resume(netdev->dev.parent);
5154
318a94d6 5155 /* update snapshot of PHY registers on LSC */
7c25769f 5156 e1000_phy_read_status(adapter);
bc7f75fa 5157 mac->ops.get_link_up_info(&adapter->hw,
17e813ec
BA		 5158 &adapter->link_speed,
5159 &adapter->link_duplex);
bc7f75fa 5160 e1000_print_link_info(adapter);
e792cd91
KS		 5161
5162 /* check if SmartSpeed worked */
5163 e1000e_check_downshift(hw);
5164 if (phy->speed_downgraded)
5165 netdev_warn(netdev,
5166 "Link Speed was downgraded by SmartSpeed\n");
5167
e921eb1a 5168 /* On supported PHYs, check for duplex mismatch only
f4187b56
BA		 5169 * if link has autonegotiated at 10/100 half
5170 */
5171 if ((hw->phy.type == e1000_phy_igp_3 ||
5172 hw->phy.type == e1000_phy_bm) &&
138953bb 5173 hw->mac.autoneg &&
f4187b56
BA		 5174 (adapter->link_speed == SPEED_10 ||
5175 adapter->link_speed == SPEED_100) &&
5176 (adapter->link_duplex == HALF_DUPLEX)) {
5177 u16 autoneg_exp;
5178
c2ade1a4 5179 e1e_rphy(hw, MII_EXPANSION, &autoneg_exp);
f4187b56 5180
c2ade1a4 5181 if (!(autoneg_exp & EXPANSION_NWAY))
ef456f85 5182 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
f4187b56
BA		 5183 }
5184
f49c57e1 5185 /* adjust timeout factor according to speed/duplex */
bc7f75fa
AK		 5186 adapter->tx_timeout_factor = 1;
5187 switch (adapter->link_speed) {
5188 case SPEED_10:
3db1cd5c 5189 txb2b = false;
10f1b492 5190 adapter->tx_timeout_factor = 16;
bc7f75fa
AK		 5191 break;
5192 case SPEED_100:
3db1cd5c 5193 txb2b = false;
4c86e0b9 5194 adapter->tx_timeout_factor = 10;
bc7f75fa
AK		 5195 break;
5196 }
5197
e921eb1a 5198 /* workaround: re-program speed mode bit after
ad68076e
BA		 5199 * link-up event
5200 */
bc7f75fa
AK		 5201 if ((adapter->flags & FLAG_TARC_SPEED_MODE_BIT) &&
5202 !txb2b) {
5203 u32 tarc0;
6cf08d1c 5204
e9ec2c0f 5205 tarc0 = er32(TARC(0));
bc7f75fa 5206 tarc0 &= ~SPEED_MODE_BIT;
e9ec2c0f 5207 ew32(TARC(0), tarc0);
bc7f75fa
AK		 5208 }
5209
e921eb1a 5210 /* disable TSO for pcie and 10/100 speeds, to avoid
ad68076e
BA		 5211 * some hardware issues
5212 */
bc7f75fa
AK		 5213 if (!(adapter->flags & FLAG_TSO_FORCE)) {
5214 switch (adapter->link_speed) {
5215 case SPEED_10:
5216 case SPEED_100:
44defeb3 5217 e_info("10/100 speed: disabling TSO\n");
bc7f75fa
AK		 5218 netdev->features &= ~NETIF_F_TSO;
5219 netdev->features &= ~NETIF_F_TSO6;
5220 break;
5221 case SPEED_1000:
5222 netdev->features |= NETIF_F_TSO;
5223 netdev->features |= NETIF_F_TSO6;
5224 break;
5225 default:
5226 /* oops */
5227 break;
5228 }
5229 }
5230
e921eb1a 5231 /* enable transmits in the hardware, need to do this
ad68076e
BA		 5232 * after setting TARC(0)
5233 */
bc7f75fa
AK		 5234 tctl = er32(TCTL);
5235 tctl |= E1000_TCTL_EN;
5236 ew32(TCTL, tctl);
5237
e921eb1a 5238 /* Perform any post-link-up configuration before
75eb0fad
BA		 5239 * reporting link up.
5240 */
5241 if (phy->ops.cfg_on_link_up)
5242 phy->ops.cfg_on_link_up(hw);
5243
bc7f75fa 5244 netif_carrier_on(netdev);
bc7f75fa
AK		 5245
5246 if (!test_bit(__E1000_DOWN, &adapter->state))
5247 mod_timer(&adapter->phy_info_timer,
5248 round_jiffies(jiffies + 2 * HZ));
bc7f75fa
AK		 5249 }
5250 } else {
5251 if (netif_carrier_ok(netdev)) {
5252 adapter->link_speed = 0;
5253 adapter->link_duplex = 0;
8f12fe86 5254 /* Link status message must follow this format */
7dbc1672 5255 pr_info("%s NIC Link is Down\n", adapter->netdev->name);
bc7f75fa 5256 netif_carrier_off(netdev);
bc7f75fa
AK		 5257 if (!test_bit(__E1000_DOWN, &adapter->state))
5258 mod_timer(&adapter->phy_info_timer,
5259 round_jiffies(jiffies + 2 * HZ));
5260
d9554e96
DE		 5261 /* 8000ES2LAN requires a Rx packet buffer work-around
5262 * on link down event; reset the controller to flush
5263 * the Rx packet buffer.
12d43f7d 5264 */
d9554e96 5265 if (adapter->flags & FLAG_RX_NEEDS_RESTART)
12d43f7d 5266 adapter->flags |= FLAG_RESTART_NOW;
23606cf5
RW		 5267 else
5268 pm_schedule_suspend(netdev->dev.parent,
17e813ec 5269 LINK_TIMEOUT);
bc7f75fa
AK		 5270 }
5271 }
5272
5273link_up:
67fd4fcb 5274 spin_lock(&adapter->stats64_lock);
bc7f75fa
AK		 5275 e1000e_update_stats(adapter);
5276
5277 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
5278 adapter->tpt_old = adapter->stats.tpt;
5279 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
5280 adapter->colc_old = adapter->stats.colc;
5281
7c25769f
BA		 5282 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
5283 adapter->gorc_old = adapter->stats.gorc;
5284 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
5285 adapter->gotc_old = adapter->stats.gotc;
2084b114 5286 spin_unlock(&adapter->stats64_lock);
bc7f75fa 5287
d9554e96
DE		 5288 /* If the link is lost the controller stops DMA, but
5289 * if there is queued Tx work it cannot be done. So
5290 * reset the controller to flush the Tx packet buffers.
5291 */
5292 if (!netif_carrier_ok(netdev) &&
5293 (e1000_desc_unused(tx_ring) + 1 < tx_ring->count))
5294 adapter->flags |= FLAG_RESTART_NOW;
5295
5296 /* If reset is necessary, do it outside of interrupt context. */
12d43f7d 5297 if (adapter->flags & FLAG_RESTART_NOW) {
90da0669
BA		 5298 schedule_work(&adapter->reset_task);
5299 /* return immediately since reset is imminent */
5300 return;
bc7f75fa
AK		 5301 }
5302
12d43f7d
BA		 5303 e1000e_update_adaptive(&adapter->hw);
5304
eab2abf5
JB		 5305 /* Simple mode for Interrupt Throttle Rate (ITR) */
5306 if (adapter->itr_setting == 4) {
e921eb1a 5307 /* Symmetric Tx/Rx gets a reduced ITR=2000;
eab2abf5
JB		 5308 * Total asymmetrical Tx or Rx gets ITR=8000;
5309 * everyone else is between 2000-8000.
5310 */
5311 u32 goc = (adapter->gotc + adapter->gorc) / 10000;
5312 u32 dif = (adapter->gotc > adapter->gorc ?
17e813ec
BA		 5313 adapter->gotc - adapter->gorc :
5314 adapter->gorc - adapter->gotc) / 10000;
eab2abf5
JB		 5315 u32 itr = goc > 0 ? (dif * 6000 / goc + 2000) : 8000;
5316
22a4cca2 5317 e1000e_write_itr(adapter, itr);
eab2abf5
JB		 5318 }
5319
ad68076e 5320 /* Cause software interrupt to ensure Rx ring is cleaned */
4662e82b
BA		 5321 if (adapter->msix_entries)
5322 ew32(ICS, adapter->rx_ring->ims_val);
5323 else
5324 ew32(ICS, E1000_ICS_RXDMT0);
bc7f75fa 5325
713b3c9e
JB		 5326 /* flush pending descriptors to memory before detecting Tx hang */
5327 e1000e_flush_descriptors(adapter);
5328
bc7f75fa 5329 /* Force detection of hung controller every watchdog period */
3db1cd5c 5330 adapter->detect_tx_hung = true;
bc7f75fa 5331
e921eb1a 5332 /* With 82571 controllers, LAA may be overwritten due to controller
ad68076e
BA		 5333 * reset from the other port. Set the appropriate LAA in RAR[0]
5334 */
bc7f75fa 5335 if (e1000e_get_laa_state_82571(hw))
69e1e019 5336 hw->mac.ops.rar_set(hw, adapter->hw.mac.addr, 0);
bc7f75fa 5337
ff10e13c
CW		 5338 if (adapter->flags2 & FLAG2_CHECK_PHY_HANG)
5339 e1000e_check_82574_phy_workaround(adapter);
5340
b67e1913
BA		 5341 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5342 if (adapter->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE) {
5343 if ((adapter->flags2 & FLAG2_CHECK_RX_HWTSTAMP) &&
5344 (er32(TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) {
5345 er32(RXSTMPH);
5346 adapter->rx_hwtstamp_cleared++;
5347 } else {
5348 adapter->flags2 |= FLAG2_CHECK_RX_HWTSTAMP;
5349 }
5350 }
5351
bc7f75fa
AK		 5352 /* Reset the timer */
5353 if (!test_bit(__E1000_DOWN, &adapter->state))
5354 mod_timer(&adapter->watchdog_timer,
5355 round_jiffies(jiffies + 2 * HZ));
5356}
5357
5358#define E1000_TX_FLAGS_CSUM 0x00000001
5359#define E1000_TX_FLAGS_VLAN 0x00000002
5360#define E1000_TX_FLAGS_TSO 0x00000004
5361#define E1000_TX_FLAGS_IPV4 0x00000008
943146de 5362#define E1000_TX_FLAGS_NO_FCS 0x00000010
b67e1913 5363#define E1000_TX_FLAGS_HWTSTAMP 0x00000020
bc7f75fa
AK		 5364#define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5365#define E1000_TX_FLAGS_VLAN_SHIFT 16
5366
47ccd1ed
VY		 5367static int e1000_tso(struct e1000_ring *tx_ring, struct sk_buff *skb,
5368 __be16 protocol)
bc7f75fa 5369{
bc7f75fa
AK		 5370 struct e1000_context_desc *context_desc;
5371 struct e1000_buffer *buffer_info;
5372 unsigned int i;
5373 u32 cmd_length = 0;
70443ae9 5374 u16 ipcse = 0, mss;
bc7f75fa 5375 u8 ipcss, ipcso, tucss, tucso, hdr_len;
bcf1f57f 5376 int err;
bc7f75fa 5377
3d5e33c9
BA		 5378 if (!skb_is_gso(skb))
5379 return 0;
bc7f75fa 5380
bcf1f57f
FR		 5381 err = skb_cow_head(skb, 0);
5382 if (err < 0)
5383 return err;
bc7f75fa 5384
3d5e33c9
BA		 5385 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
5386 mss = skb_shinfo(skb)->gso_size;
47ccd1ed 5387 if (protocol == htons(ETH_P_IP)) {
3d5e33c9
BA		 5388 struct iphdr *iph = ip_hdr(skb);
5389 iph->tot_len = 0;
5390 iph->check = 0;
5391 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
f0ff4398 5392 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5393 cmd_length = E1000_TXD_CMD_IP;
5394 ipcse = skb_transport_offset(skb) - 1;
8e1e8a47 5395 } else if (skb_is_gso_v6(skb)) {
3d5e33c9
BA		 5396 ipv6_hdr(skb)->payload_len = 0;
5397 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
f0ff4398
BA		 5398 &ipv6_hdr(skb)->daddr,
5399 0, IPPROTO_TCP, 0);
3d5e33c9
BA		 5400 ipcse = 0;
5401 }
5402 ipcss = skb_network_offset(skb);
5403 ipcso = (void *)&(ip_hdr(skb)->check) - (void *)skb->data;
5404 tucss = skb_transport_offset(skb);
5405 tucso = (void *)&(tcp_hdr(skb)->check) - (void *)skb->data;
3d5e33c9
BA		 5406
5407 cmd_length |= (E1000_TXD_CMD_DEXT | E1000_TXD_CMD_TSE |
f0ff4398 5408 E1000_TXD_CMD_TCP | (skb->len - (hdr_len)));
3d5e33c9
BA		 5409
5410 i = tx_ring->next_to_use;
5411 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5412 buffer_info = &tx_ring->buffer_info[i];
5413
e80bd1d1
BA		 5414 context_desc->lower_setup.ip_fields.ipcss = ipcss;
5415 context_desc->lower_setup.ip_fields.ipcso = ipcso;
5416 context_desc->lower_setup.ip_fields.ipcse = cpu_to_le16(ipcse);
3d5e33c9
BA		 5417 context_desc->upper_setup.tcp_fields.tucss = tucss;
5418 context_desc->upper_setup.tcp_fields.tucso = tucso;
70443ae9 5419 context_desc->upper_setup.tcp_fields.tucse = 0;
e80bd1d1 5420 context_desc->tcp_seg_setup.fields.mss = cpu_to_le16(mss);
3d5e33c9
BA		 5421 context_desc->tcp_seg_setup.fields.hdr_len = hdr_len;
5422 context_desc->cmd_and_length = cpu_to_le32(cmd_length);
5423
5424 buffer_info->time_stamp = jiffies;
5425 buffer_info->next_to_watch = i;
5426
5427 i++;
5428 if (i == tx_ring->count)
5429 i = 0;
5430 tx_ring->next_to_use = i;
5431
5432 return 1;
bc7f75fa
AK		 5433}
5434
47ccd1ed
VY		 5435static bool e1000_tx_csum(struct e1000_ring *tx_ring, struct sk_buff *skb,
5436 __be16 protocol)
bc7f75fa 5437{
55aa6985 5438 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5439 struct e1000_context_desc *context_desc;
5440 struct e1000_buffer *buffer_info;
5441 unsigned int i;
5442 u8 css;
af807c82 5443 u32 cmd_len = E1000_TXD_CMD_DEXT;
bc7f75fa 5444
af807c82 5445 if (skb->ip_summed != CHECKSUM_PARTIAL)
3992c8ed 5446 return false;
bc7f75fa 5447
3f518390 5448 switch (protocol) {
09640e63 5449 case cpu_to_be16(ETH_P_IP):
af807c82
DG		 5450 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
5451 cmd_len |= E1000_TXD_CMD_TCP;
5452 break;
09640e63 5453 case cpu_to_be16(ETH_P_IPV6):
af807c82
DG		 5454 /* XXX not handling all IPV6 headers */
5455 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
5456 cmd_len |= E1000_TXD_CMD_TCP;
5457 break;
5458 default:
5459 if (unlikely(net_ratelimit()))
5f66f208
AJ		 5460 e_warn("checksum_partial proto=%x!\n",
5461 be16_to_cpu(protocol));
af807c82 5462 break;
bc7f75fa
AK		 5463 }
5464
0d0b1672 5465 css = skb_checksum_start_offset(skb);
af807c82
DG		 5466
5467 i = tx_ring->next_to_use;
5468 buffer_info = &tx_ring->buffer_info[i];
5469 context_desc = E1000_CONTEXT_DESC(*tx_ring, i);
5470
5471 context_desc->lower_setup.ip_config = 0;
5472 context_desc->upper_setup.tcp_fields.tucss = css;
f0ff4398 5473 context_desc->upper_setup.tcp_fields.tucso = css + skb->csum_offset;
af807c82
DG		 5474 context_desc->upper_setup.tcp_fields.tucse = 0;
5475 context_desc->tcp_seg_setup.data = 0;
5476 context_desc->cmd_and_length = cpu_to_le32(cmd_len);
5477
5478 buffer_info->time_stamp = jiffies;
5479 buffer_info->next_to_watch = i;
5480
5481 i++;
5482 if (i == tx_ring->count)
5483 i = 0;
5484 tx_ring->next_to_use = i;
5485
3992c8ed 5486 return true;
bc7f75fa
AK		 5487}
5488
55aa6985
BA		 5489static int e1000_tx_map(struct e1000_ring *tx_ring, struct sk_buff *skb,
5490 unsigned int first, unsigned int max_per_txd,
d821a4c4 5491 unsigned int nr_frags)
bc7f75fa 5492{
55aa6985 5493 struct e1000_adapter *adapter = tx_ring->adapter;
03b1320d 5494 struct pci_dev *pdev = adapter->pdev;
1b7719c4 5495 struct e1000_buffer *buffer_info;
8ddc951c 5496 unsigned int len = skb_headlen(skb);
03b1320d 5497 unsigned int offset = 0, size, count = 0, i;
9ed318d5 5498 unsigned int f, bytecount, segs;
bc7f75fa
AK		 5499
5500 i = tx_ring->next_to_use;
5501
5502 while (len) {
1b7719c4 5503 buffer_info = &tx_ring->buffer_info[i];
bc7f75fa
AK		 5504 size = min(len, max_per_txd);
5505
bc7f75fa 5506 buffer_info->length = size;
bc7f75fa 5507 buffer_info->time_stamp = jiffies;
bc7f75fa 5508 buffer_info->next_to_watch = i;
0be3f55f
NN		 5509 buffer_info->dma = dma_map_single(&pdev->dev,
5510 skb->data + offset,
af667a29 5511 size, DMA_TO_DEVICE);
03b1320d 5512 buffer_info->mapped_as_page = false;
0be3f55f 5513 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5514 goto dma_error;
bc7f75fa
AK		 5515
5516 len -= size;
5517 offset += size;
03b1320d 5518 count++;
1b7719c4
AD		 5519
5520 if (len) {
5521 i++;
5522 if (i == tx_ring->count)
5523 i = 0;
5524 }
bc7f75fa
AK		 5525 }
5526
5527 for (f = 0; f < nr_frags; f++) {
9e903e08 5528 const struct skb_frag_struct *frag;
bc7f75fa
AK		 5529
5530 frag = &skb_shinfo(skb)->frags[f];
9e903e08 5531 len = skb_frag_size(frag);
877749bf 5532 offset = 0;
bc7f75fa
AK		 5533
5534 while (len) {
1b7719c4
AD		 5535 i++;
5536 if (i == tx_ring->count)
5537 i = 0;
5538
bc7f75fa
AK		 5539 buffer_info = &tx_ring->buffer_info[i];
5540 size = min(len, max_per_txd);
bc7f75fa
AK		 5541
5542 buffer_info->length = size;
5543 buffer_info->time_stamp = jiffies;
bc7f75fa 5544 buffer_info->next_to_watch = i;
877749bf 5545 buffer_info->dma = skb_frag_dma_map(&pdev->dev, frag,
17e813ec
BA		 5546 offset, size,
5547 DMA_TO_DEVICE);
03b1320d 5548 buffer_info->mapped_as_page = true;
0be3f55f 5549 if (dma_mapping_error(&pdev->dev, buffer_info->dma))
03b1320d 5550 goto dma_error;
bc7f75fa
AK		 5551
5552 len -= size;
5553 offset += size;
5554 count++;
bc7f75fa
AK		 5555 }
5556 }
5557
af667a29 5558 segs = skb_shinfo(skb)->gso_segs ? : 1;
9ed318d5
TH		 5559 /* multiply data chunks by size of headers */
5560 bytecount = ((segs - 1) * skb_headlen(skb)) + skb->len;
5561
bc7f75fa 5562 tx_ring->buffer_info[i].skb = skb;
9ed318d5
TH		 5563 tx_ring->buffer_info[i].segs = segs;
5564 tx_ring->buffer_info[i].bytecount = bytecount;
bc7f75fa
AK		 5565 tx_ring->buffer_info[first].next_to_watch = i;
5566
5567 return count;
03b1320d
AD		 5568
5569dma_error:
af667a29 5570 dev_err(&pdev->dev, "Tx DMA map failed\n");
03b1320d 5571 buffer_info->dma = 0;
c1fa347f 5572 if (count)
03b1320d 5573 count--;
c1fa347f
RK		 5574
5575 while (count--) {
af667a29 5576 if (i == 0)
03b1320d 5577 i += tx_ring->count;
c1fa347f 5578 i--;
03b1320d 5579 buffer_info = &tx_ring->buffer_info[i];
55aa6985 5580 e1000_put_txbuf(tx_ring, buffer_info);
03b1320d
AD		 5581 }
5582
5583 return 0;
bc7f75fa
AK		 5584}
5585
55aa6985 5586static void e1000_tx_queue(struct e1000_ring *tx_ring, int tx_flags, int count)
bc7f75fa 5587{
55aa6985 5588 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa
AK		 5589 struct e1000_tx_desc *tx_desc = NULL;
5590 struct e1000_buffer *buffer_info;
5591 u32 txd_upper = 0, txd_lower = E1000_TXD_CMD_IFCS;
5592 unsigned int i;
5593
5594 if (tx_flags & E1000_TX_FLAGS_TSO) {
5595 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D |
f0ff4398 5596 E1000_TXD_CMD_TSE;
bc7f75fa
AK		 5597 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5598
5599 if (tx_flags & E1000_TX_FLAGS_IPV4)
5600 txd_upper |= E1000_TXD_POPTS_IXSM << 8;
5601 }
5602
5603 if (tx_flags & E1000_TX_FLAGS_CSUM) {
5604 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5605 txd_upper |= E1000_TXD_POPTS_TXSM << 8;
5606 }
5607
5608 if (tx_flags & E1000_TX_FLAGS_VLAN) {
5609 txd_lower |= E1000_TXD_CMD_VLE;
5610 txd_upper |= (tx_flags & E1000_TX_FLAGS_VLAN_MASK);
5611 }
5612
943146de
BG		 5613 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5614 txd_lower &= ~(E1000_TXD_CMD_IFCS);
5615
b67e1913
BA		 5616 if (unlikely(tx_flags & E1000_TX_FLAGS_HWTSTAMP)) {
5617 txd_lower |= E1000_TXD_CMD_DEXT | E1000_TXD_DTYP_D;
5618 txd_upper |= E1000_TXD_EXTCMD_TSTAMP;
5619 }
5620
bc7f75fa
AK		 5621 i = tx_ring->next_to_use;
5622
36b973df 5623 do {
bc7f75fa
AK		 5624 buffer_info = &tx_ring->buffer_info[i];
5625 tx_desc = E1000_TX_DESC(*tx_ring, i);
5626 tx_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
f0ff4398
BA		 5627 tx_desc->lower.data = cpu_to_le32(txd_lower |
5628 buffer_info->length);
bc7f75fa
AK		 5629 tx_desc->upper.data = cpu_to_le32(txd_upper);
5630
5631 i++;
5632 if (i == tx_ring->count)
5633 i = 0;
36b973df 5634 } while (--count > 0);
bc7f75fa
AK		 5635
5636 tx_desc->lower.data |= cpu_to_le32(adapter->txd_cmd);
5637
943146de
BG		 5638 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5639 if (unlikely(tx_flags & E1000_TX_FLAGS_NO_FCS))
5640 tx_desc->lower.data &= ~(cpu_to_le32(E1000_TXD_CMD_IFCS));
5641
e921eb1a 5642 /* Force memory writes to complete before letting h/w
bc7f75fa
AK		 5643 * know there are new descriptors to fetch. (Only
5644 * applicable for weak-ordered memory model archs,
ad68076e
BA		 5645 * such as IA-64).
5646 */
bc7f75fa
AK		 5647 wmb();
5648
5649 tx_ring->next_to_use = i;
bc7f75fa
AK		 5650}
5651
5652#define MINIMUM_DHCP_PACKET_SIZE 282
5653static int e1000_transfer_dhcp_info(struct e1000_adapter *adapter,
5654 struct sk_buff *skb)
5655{
e80bd1d1 5656 struct e1000_hw *hw = &adapter->hw;
bc7f75fa
AK		 5657 u16 length, offset;
5658
df8a39de
JP		 5659 if (skb_vlan_tag_present(skb) &&
5660 !((skb_vlan_tag_get(skb) == adapter->hw.mng_cookie.vlan_id) &&
d60923c4
BA		 5661 (adapter->hw.mng_cookie.status &
5662 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5663 return 0;
bc7f75fa
AK		 5664
5665 if (skb->len <= MINIMUM_DHCP_PACKET_SIZE)
5666 return 0;
5667
53aa82da 5668 if (((struct ethhdr *)skb->data)->h_proto != htons(ETH_P_IP))
bc7f75fa
AK		 5669 return 0;
5670
5671 {
362e20ca 5672 const struct iphdr *ip = (struct iphdr *)((u8 *)skb->data + 14);
bc7f75fa
AK		 5673 struct udphdr *udp;
5674
5675 if (ip->protocol != IPPROTO_UDP)
5676 return 0;
5677
5678 udp = (struct udphdr *)((u8 *)ip + (ip->ihl << 2));
5679 if (ntohs(udp->dest) != 67)
5680 return 0;
5681
5682 offset = (u8 *)udp + 8 - skb->data;
5683 length = skb->len - offset;
5684 return e1000e_mng_write_dhcp_info(hw, (u8 *)udp + 8, length);
5685 }
5686
5687 return 0;
5688}
5689
55aa6985 5690static int __e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5691{
55aa6985 5692 struct e1000_adapter *adapter = tx_ring->adapter;
bc7f75fa 5693
55aa6985 5694 netif_stop_queue(adapter->netdev);
e921eb1a 5695 /* Herbert's original patch had:
bc7f75fa 5696 * smp_mb__after_netif_stop_queue();
ad68076e
BA		 5697 * but since that doesn't exist yet, just open code it.
5698 */
bc7f75fa
AK		 5699 smp_mb();
5700
e921eb1a 5701 /* We need to check again in a case another CPU has just
ad68076e
BA		 5702 * made room available.
5703 */
55aa6985 5704 if (e1000_desc_unused(tx_ring) < size)
bc7f75fa
AK		 5705 return -EBUSY;
5706
5707 /* A reprieve! */
55aa6985 5708 netif_start_queue(adapter->netdev);
bc7f75fa
AK		 5709 ++adapter->restart_queue;
5710 return 0;
5711}
5712
55aa6985 5713static int e1000_maybe_stop_tx(struct e1000_ring *tx_ring, int size)
bc7f75fa 5714{
d821a4c4
BA		 5715 BUG_ON(size > tx_ring->count);
5716
55aa6985 5717 if (e1000_desc_unused(tx_ring) >= size)
bc7f75fa 5718 return 0;
55aa6985 5719 return __e1000_maybe_stop_tx(tx_ring, size);
bc7f75fa
AK		 5720}
5721
3b29a56d
SH		 5722static netdev_tx_t e1000_xmit_frame(struct sk_buff *skb,
5723 struct net_device *netdev)
bc7f75fa
AK		 5724{
5725 struct e1000_adapter *adapter = netdev_priv(netdev);
5726 struct e1000_ring *tx_ring = adapter->tx_ring;
5727 unsigned int first;
bc7f75fa 5728 unsigned int tx_flags = 0;
e743d313 5729 unsigned int len = skb_headlen(skb);
4e6c709c
AK		 5730 unsigned int nr_frags;
5731 unsigned int mss;
bc7f75fa
AK		 5732 int count = 0;
5733 int tso;
5734 unsigned int f;
47ccd1ed 5735 __be16 protocol = vlan_get_protocol(skb);
bc7f75fa
AK		 5736
5737 if (test_bit(__E1000_DOWN, &adapter->state)) {
5738 dev_kfree_skb_any(skb);
5739 return NETDEV_TX_OK;
5740 }
5741
5742 if (skb->len <= 0) {
5743 dev_kfree_skb_any(skb);
5744 return NETDEV_TX_OK;
5745 }
5746
e921eb1a 5747 /* The minimum packet size with TCTL.PSP set is 17 bytes so
6e97c170
TD		 5748 * pad skb in order to meet this minimum size requirement
5749 */
a94d9e22
AD		 5750 if (skb_put_padto(skb, 17))
5751 return NETDEV_TX_OK;
6e97c170 5752
bc7f75fa 5753 mss = skb_shinfo(skb)->gso_size;
bc7f75fa
AK		 5754 if (mss) {
5755 u8 hdr_len;
bc7f75fa 5756
e921eb1a 5757 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
ad68076e
BA		 5758 * points to just header, pull a few bytes of payload from
5759 * frags into skb->data
5760 */
bc7f75fa 5761 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
e921eb1a 5762 /* we do this workaround for ES2LAN, but it is un-necessary,
ad68076e
BA		 5763 * avoiding it could save a lot of cycles
5764 */
4e6c709c 5765 if (skb->data_len && (hdr_len == len)) {
bc7f75fa
AK		 5766 unsigned int pull_size;
5767
a2a5b323 5768 pull_size = min_t(unsigned int, 4, skb->data_len);
bc7f75fa 5769 if (!__pskb_pull_tail(skb, pull_size)) {
44defeb3 5770 e_err("__pskb_pull_tail failed.\n");
bc7f75fa
AK		 5771 dev_kfree_skb_any(skb);
5772 return NETDEV_TX_OK;
5773 }
e743d313 5774 len = skb_headlen(skb);
bc7f75fa
AK		 5775 }
5776 }
5777
5778 /* reserve a descriptor for the offload context */
5779 if ((mss) || (skb->ip_summed == CHECKSUM_PARTIAL))
5780 count++;
5781 count++;
5782
d821a4c4 5783 count += DIV_ROUND_UP(len, adapter->tx_fifo_limit);
bc7f75fa
AK		 5784
5785 nr_frags = skb_shinfo(skb)->nr_frags;
5786 for (f = 0; f < nr_frags; f++)
d821a4c4
BA		 5787 count += DIV_ROUND_UP(skb_frag_size(&skb_shinfo(skb)->frags[f]),
5788 adapter->tx_fifo_limit);
bc7f75fa
AK		 5789
5790 if (adapter->hw.mac.tx_pkt_filtering)
5791 e1000_transfer_dhcp_info(adapter, skb);
5792
e921eb1a 5793 /* need: count + 2 desc gap to keep tail from touching
ad68076e
BA		 5794 * head, otherwise try next time
5795 */
55aa6985 5796 if (e1000_maybe_stop_tx(tx_ring, count + 2))
bc7f75fa 5797 return NETDEV_TX_BUSY;
bc7f75fa 5798
df8a39de 5799 if (skb_vlan_tag_present(skb)) {
bc7f75fa 5800 tx_flags |= E1000_TX_FLAGS_VLAN;
df8a39de
JP		 5801 tx_flags |= (skb_vlan_tag_get(skb) <<
5802 E1000_TX_FLAGS_VLAN_SHIFT);
bc7f75fa
AK		 5803 }
5804
5805 first = tx_ring->next_to_use;
5806
47ccd1ed 5807 tso = e1000_tso(tx_ring, skb, protocol);
bc7f75fa
AK		 5808 if (tso < 0) {
5809 dev_kfree_skb_any(skb);
bc7f75fa
AK		 5810 return NETDEV_TX_OK;
5811 }
5812
5813 if (tso)
5814 tx_flags |= E1000_TX_FLAGS_TSO;
47ccd1ed 5815 else if (e1000_tx_csum(tx_ring, skb, protocol))
bc7f75fa
AK		 5816 tx_flags |= E1000_TX_FLAGS_CSUM;
5817
e921eb1a 5818 /* Old method was to assume IPv4 packet by default if TSO was enabled.
bc7f75fa 5819 * 82571 hardware supports TSO capabilities for IPv6 as well...
ad68076e
BA		 5820 * no longer assume, we must.
5821 */
47ccd1ed 5822 if (protocol == htons(ETH_P_IP))
bc7f75fa
AK		 5823 tx_flags |= E1000_TX_FLAGS_IPV4;
5824
943146de
BG		 5825 if (unlikely(skb->no_fcs))
5826 tx_flags |= E1000_TX_FLAGS_NO_FCS;
5827
25985edc 5828 /* if count is 0 then mapping error has occurred */
d821a4c4
BA		 5829 count = e1000_tx_map(tx_ring, skb, first, adapter->tx_fifo_limit,
5830 nr_frags);
1b7719c4 5831 if (count) {
6930895d
MK		 5832 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
5833 (adapter->flags & FLAG_HAS_HW_TIMESTAMP) &&
5834 !adapter->tx_hwtstamp_skb) {
b67e1913
BA		 5835 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
5836 tx_flags |= E1000_TX_FLAGS_HWTSTAMP;
5837 adapter->tx_hwtstamp_skb = skb_get(skb);
59c871c5 5838 adapter->tx_hwtstamp_start = jiffies;
b67e1913
BA		 5839 schedule_work(&adapter->tx_hwtstamp_work);
5840 } else {
5841 skb_tx_timestamp(skb);
5842 }
80be3129 5843
3f0cfa3b 5844 netdev_sent_queue(netdev, skb->len);
55aa6985 5845 e1000_tx_queue(tx_ring, tx_flags, count);
1b7719c4 5846 /* Make sure there is space in the ring for the next send. */
d821a4c4
BA		 5847 e1000_maybe_stop_tx(tx_ring,
5848 (MAX_SKB_FRAGS *
5849 DIV_ROUND_UP(PAGE_SIZE,
5850 adapter->tx_fifo_limit) + 2));
472f31f5
FW		 5851
5852 if (!skb->xmit_more ||
5853 netif_xmit_stopped(netdev_get_tx_queue(netdev, 0))) {
5854 if (adapter->flags2 & FLAG2_PCIM2PCI_ARBITER_WA)
5855 e1000e_update_tdt_wa(tx_ring,
5856 tx_ring->next_to_use);
5857 else
5858 writel(tx_ring->next_to_use, tx_ring->tail);
5859
5860 /* we need this if more than one processor can write
5861 * to our tail at a time, it synchronizes IO on
5862 *IA64/Altix systems
5863 */
5864 mmiowb();
5865 }
1b7719c4 5866 } else {
bc7f75fa 5867 dev_kfree_skb_any(skb);
1b7719c4
AD		 5868 tx_ring->buffer_info[first].time_stamp = 0;
5869 tx_ring->next_to_use = first;
bc7f75fa
AK		 5870 }
5871
bc7f75fa
AK		 5872 return NETDEV_TX_OK;
5873}
5874
5875/**
5876 * e1000_tx_timeout - Respond to a Tx Hang
5877 * @netdev: network interface device structure
5878 **/
5879static void e1000_tx_timeout(struct net_device *netdev)
5880{
5881 struct e1000_adapter *adapter = netdev_priv(netdev);
5882
5883 /* Do the reset outside of interrupt context */
5884 adapter->tx_timeout_count++;
5885 schedule_work(&adapter->reset_task);
5886}
5887
5888static void e1000_reset_task(struct work_struct *work)
5889{
5890 struct e1000_adapter *adapter;
5891 adapter = container_of(work, struct e1000_adapter, reset_task);
5892
615b32af
JB		 5893 /* don't run the task if already down */
5894 if (test_bit(__E1000_DOWN, &adapter->state))
5895 return;
5896
12d43f7d 5897 if (!(adapter->flags & FLAG_RESTART_NOW)) {
affa9dfb 5898 e1000e_dump(adapter);
12d43f7d 5899 e_err("Reset adapter unexpectedly\n");
affa9dfb 5900 }
bc7f75fa
AK		 5901 e1000e_reinit_locked(adapter);
5902}
5903
5904/**
67fd4fcb 5905 * e1000_get_stats64 - Get System Network Statistics
bc7f75fa 5906 * @netdev: network interface device structure
67fd4fcb 5907 * @stats: rtnl_link_stats64 pointer
bc7f75fa
AK		 5908 *
5909 * Returns the address of the device statistics structure.
bc7f75fa 5910 **/
67fd4fcb 5911struct rtnl_link_stats64 *e1000e_get_stats64(struct net_device *netdev,
66501f56 5912 struct rtnl_link_stats64 *stats)
bc7f75fa 5913{
67fd4fcb
JK		 5914 struct e1000_adapter *adapter = netdev_priv(netdev);
5915
5916 memset(stats, 0, sizeof(struct rtnl_link_stats64));
5917 spin_lock(&adapter->stats64_lock);
5918 e1000e_update_stats(adapter);
5919 /* Fill out the OS statistics structure */
5920 stats->rx_bytes = adapter->stats.gorc;
5921 stats->rx_packets = adapter->stats.gprc;
5922 stats->tx_bytes = adapter->stats.gotc;
5923 stats->tx_packets = adapter->stats.gptc;
5924 stats->multicast = adapter->stats.mprc;
5925 stats->collisions = adapter->stats.colc;
5926
5927 /* Rx Errors */
5928
e921eb1a 5929 /* RLEC on some newer hardware can be incorrect so build
67fd4fcb
JK		 5930 * our own version based on RUC and ROC
5931 */
5932 stats->rx_errors = adapter->stats.rxerrc +
f0ff4398
BA		 5933 adapter->stats.crcerrs + adapter->stats.algnerrc +
5934 adapter->stats.ruc + adapter->stats.roc + adapter->stats.cexterr;
5935 stats->rx_length_errors = adapter->stats.ruc + adapter->stats.roc;
67fd4fcb
JK		 5936 stats->rx_crc_errors = adapter->stats.crcerrs;
5937 stats->rx_frame_errors = adapter->stats.algnerrc;
5938 stats->rx_missed_errors = adapter->stats.mpc;
5939
5940 /* Tx Errors */
f0ff4398 5941 stats->tx_errors = adapter->stats.ecol + adapter->stats.latecol;
67fd4fcb
JK		 5942 stats->tx_aborted_errors = adapter->stats.ecol;
5943 stats->tx_window_errors = adapter->stats.latecol;
5944 stats->tx_carrier_errors = adapter->stats.tncrs;
5945
5946 /* Tx Dropped needs to be maintained elsewhere */
5947
5948 spin_unlock(&adapter->stats64_lock);
5949 return stats;
bc7f75fa
AK		 5950}
5951
5952/**
5953 * e1000_change_mtu - Change the Maximum Transfer Unit
5954 * @netdev: network interface device structure
5955 * @new_mtu: new value for maximum frame size
5956 *
5957 * Returns 0 on success, negative on failure
5958 **/
5959static int e1000_change_mtu(struct net_device *netdev, int new_mtu)
5960{
5961 struct e1000_adapter *adapter = netdev_priv(netdev);
8084b86d 5962 int max_frame = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
bc7f75fa 5963
2adc55c9 5964 /* Jumbo frame support */
8084b86d 5965 if ((max_frame > (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)) &&
2e1706f2
BA		 5966 !(adapter->flags & FLAG_HAS_JUMBO_FRAMES)) {
5967 e_err("Jumbo Frames not supported.\n");
5968 return -EINVAL;
bc7f75fa
AK		 5969 }
5970
2adc55c9 5971 /* Supported frame sizes */
8084b86d 5972 if ((new_mtu < (VLAN_ETH_ZLEN + ETH_FCS_LEN)) ||
2adc55c9
BA		 5973 (max_frame > adapter->max_hw_frame_size)) {
5974 e_err("Unsupported MTU setting\n");
bc7f75fa
AK		 5975 return -EINVAL;
5976 }
5977
2fbe4526
BA		 5978 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
5979 if ((adapter->hw.mac.type >= e1000_pch2lan) &&
a1ce6473
BA		 5980 !(adapter->flags2 & FLAG2_CRC_STRIPPING) &&
5981 (new_mtu > ETH_DATA_LEN)) {
2fbe4526 5982 e_err("Jumbo Frames not supported on this device when CRC stripping is disabled.\n");
a1ce6473
BA		 5983 return -EINVAL;
5984 }
5985
bc7f75fa 5986 while (test_and_set_bit(__E1000_RESETTING, &adapter->state))
1bba4386 5987 usleep_range(1000, 2000);
610c9928 5988 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
318a94d6 5989 adapter->max_frame_size = max_frame;
610c9928
BA		 5990 e_info("changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5991 netdev->mtu = new_mtu;
63eb48f1
DE		 5992
5993 pm_runtime_get_sync(netdev->dev.parent);
5994
bc7f75fa 5995 if (netif_running(netdev))
28002099 5996 e1000e_down(adapter, true);
bc7f75fa 5997
e921eb1a 5998 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
bc7f75fa
AK		 5999 * means we reserve 2 more, this pushes us to allocate from the next
6000 * larger slab size.
ad68076e 6001 * i.e. RXBUFFER_2048 --> size-4096 slab
97ac8cae
BA		 6002 * However with the new *_jumbo_rx* routines, jumbo receives will use
6003 * fragmented skbs
ad68076e 6004 */
bc7f75fa 6005
9926146b 6006 if (max_frame <= 2048)
bc7f75fa
AK		 6007 adapter->rx_buffer_len = 2048;
6008 else
6009 adapter->rx_buffer_len = 4096;
6010
6011 /* adjust allocation if LPE protects us, and we aren't using SBP */
8084b86d
AD		 6012 if (max_frame <= (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN))
6013 adapter->rx_buffer_len = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN;
bc7f75fa 6014
bc7f75fa
AK		 6015 if (netif_running(netdev))
6016 e1000e_up(adapter);
6017 else
6018 e1000e_reset(adapter);
6019
63eb48f1
DE		 6020 pm_runtime_put_sync(netdev->dev.parent);
6021
bc7f75fa
AK		 6022 clear_bit(__E1000_RESETTING, &adapter->state);
6023
6024 return 0;
6025}
6026
6027static int e1000_mii_ioctl(struct net_device *netdev, struct ifreq *ifr,
6028 int cmd)
6029{
6030 struct e1000_adapter *adapter = netdev_priv(netdev);
6031 struct mii_ioctl_data *data = if_mii(ifr);
bc7f75fa 6032
318a94d6 6033 if (adapter->hw.phy.media_type != e1000_media_type_copper)
bc7f75fa
AK		 6034 return -EOPNOTSUPP;
6035
6036 switch (cmd) {
6037 case SIOCGMIIPHY:
6038 data->phy_id = adapter->hw.phy.addr;
6039 break;
6040 case SIOCGMIIREG:
b16a002e
BA		 6041 e1000_phy_read_status(adapter);
6042
7c25769f
BA		 6043 switch (data->reg_num & 0x1F) {
6044 case MII_BMCR:
6045 data->val_out = adapter->phy_regs.bmcr;
6046 break;
6047 case MII_BMSR:
6048 data->val_out = adapter->phy_regs.bmsr;
6049 break;
6050 case MII_PHYSID1:
6051 data->val_out = (adapter->hw.phy.id >> 16);
6052 break;
6053 case MII_PHYSID2:
6054 data->val_out = (adapter->hw.phy.id & 0xFFFF);
6055 break;
6056 case MII_ADVERTISE:
6057 data->val_out = adapter->phy_regs.advertise;
6058 break;
6059 case MII_LPA:
6060 data->val_out = adapter->phy_regs.lpa;
6061 break;
6062 case MII_EXPANSION:
6063 data->val_out = adapter->phy_regs.expansion;
6064 break;
6065 case MII_CTRL1000:
6066 data->val_out = adapter->phy_regs.ctrl1000;
6067 break;
6068 case MII_STAT1000:
6069 data->val_out = adapter->phy_regs.stat1000;
6070 break;
6071 case MII_ESTATUS:
6072 data->val_out = adapter->phy_regs.estatus;
6073 break;
6074 default:
bc7f75fa
AK		 6075 return -EIO;
6076 }
bc7f75fa
AK		 6077 break;
6078 case SIOCSMIIREG:
6079 default:
6080 return -EOPNOTSUPP;
6081 }
6082 return 0;
6083}
6084
b67e1913
BA		 6085/**
6086 * e1000e_hwtstamp_ioctl - control hardware time stamping
6087 * @netdev: network interface device structure
6088 * @ifreq: interface request
6089 *
6090 * Outgoing time stamping can be enabled and disabled. Play nice and
6091 * disable it when requested, although it shouldn't cause any overhead
6092 * when no packet needs it. At most one packet in the queue may be
6093 * marked for time stamping, otherwise it would be impossible to tell
6094 * for sure to which packet the hardware time stamp belongs.
6095 *
6096 * Incoming time stamping has to be configured via the hardware filters.
6097 * Not all combinations are supported, in particular event type has to be
6098 * specified. Matching the kind of event packet is not supported, with the
6099 * exception of "all V2 events regardless of level 2 or 4".
6100 **/
4e8cff64 6101static int e1000e_hwtstamp_set(struct net_device *netdev, struct ifreq *ifr)
b67e1913
BA		 6102{
6103 struct e1000_adapter *adapter = netdev_priv(netdev);
6104 struct hwtstamp_config config;
6105 int ret_val;
6106
6107 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
6108 return -EFAULT;
6109
62d7e3a2 6110 ret_val = e1000e_config_hwtstamp(adapter, &config);
b67e1913
BA		 6111 if (ret_val)
6112 return ret_val;
6113
d89777bf
BA		 6114 switch (config.rx_filter) {
6115 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6116 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
6117 case HWTSTAMP_FILTER_PTP_V2_SYNC:
6118 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6119 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
6120 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6121 /* With V2 type filters which specify a Sync or Delay Request,
6122 * Path Delay Request/Response messages are also time stamped
6123 * by hardware so notify the caller the requested packets plus
6124 * some others are time stamped.
6125 */
6126 config.rx_filter = HWTSTAMP_FILTER_SOME;
6127 break;
6128 default:
6129 break;
6130 }
6131
b67e1913
BA		 6132 return copy_to_user(ifr->ifr_data, &config,
6133 sizeof(config)) ? -EFAULT : 0;
6134}
6135
4e8cff64
BH		 6136static int e1000e_hwtstamp_get(struct net_device *netdev, struct ifreq *ifr)
6137{
6138 struct e1000_adapter *adapter = netdev_priv(netdev);
6139
6140 return copy_to_user(ifr->ifr_data, &adapter->hwtstamp_config,
6141 sizeof(adapter->hwtstamp_config)) ? -EFAULT : 0;
6142}
6143
bc7f75fa
AK		 6144static int e1000_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
6145{
6146 switch (cmd) {
6147 case SIOCGMIIPHY:
6148 case SIOCGMIIREG:
6149 case SIOCSMIIREG:
6150 return e1000_mii_ioctl(netdev, ifr, cmd);
b67e1913 6151 case SIOCSHWTSTAMP:
4e8cff64
BH		 6152 return e1000e_hwtstamp_set(netdev, ifr);
6153 case SIOCGHWTSTAMP:
6154 return e1000e_hwtstamp_get(netdev, ifr);
bc7f75fa
AK		 6155 default:
6156 return -EOPNOTSUPP;
6157 }
6158}
6159
a4f58f54
BA		 6160static int e1000_init_phy_wakeup(struct e1000_adapter *adapter, u32 wufc)
6161{
6162 struct e1000_hw *hw = &adapter->hw;
74f350ee 6163 u32 i, mac_reg, wuc;
2b6b168d 6164 u16 phy_reg, wuc_enable;
70806a7f 6165 int retval;
a4f58f54
BA		 6166
6167 /* copy MAC RARs to PHY RARs */
d3738bb8 6168 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
a4f58f54 6169
2b6b168d
BA		 6170 retval = hw->phy.ops.acquire(hw);
6171 if (retval) {
6172 e_err("Could not acquire PHY\n");
6173 return retval;
6174 }
6175
6176 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6177 retval = e1000_enable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
6178 if (retval)
75ce1532 6179 goto release;
2b6b168d
BA		 6180
6181 /* copy MAC MTA to PHY MTA - only needed for pchlan */
a4f58f54
BA		 6182 for (i = 0; i < adapter->hw.mac.mta_reg_count; i++) {
6183 mac_reg = E1000_READ_REG_ARRAY(hw, E1000_MTA, i);
2b6b168d
BA		 6184 hw->phy.ops.write_reg_page(hw, BM_MTA(i),
6185 (u16)(mac_reg & 0xFFFF));
6186 hw->phy.ops.write_reg_page(hw, BM_MTA(i) + 1,
6187 (u16)((mac_reg >> 16) & 0xFFFF));
a4f58f54
BA		 6188 }
6189
6190 /* configure PHY Rx Control register */
2b6b168d 6191 hw->phy.ops.read_reg_page(&adapter->hw, BM_RCTL, &phy_reg);
a4f58f54
BA		 6192 mac_reg = er32(RCTL);
6193 if (mac_reg & E1000_RCTL_UPE)
6194 phy_reg |= BM_RCTL_UPE;
6195 if (mac_reg & E1000_RCTL_MPE)
6196 phy_reg |= BM_RCTL_MPE;
6197 phy_reg &= ~(BM_RCTL_MO_MASK);
6198 if (mac_reg & E1000_RCTL_MO_3)
6199 phy_reg |= (((mac_reg & E1000_RCTL_MO_3) >> E1000_RCTL_MO_SHIFT)
17e813ec 6200 << BM_RCTL_MO_SHIFT);
a4f58f54
BA		 6201 if (mac_reg & E1000_RCTL_BAM)
6202 phy_reg |= BM_RCTL_BAM;
6203 if (mac_reg & E1000_RCTL_PMCF)
6204 phy_reg |= BM_RCTL_PMCF;
6205 mac_reg = er32(CTRL);
6206 if (mac_reg & E1000_CTRL_RFCE)
6207 phy_reg |= BM_RCTL_RFCE;
2b6b168d 6208 hw->phy.ops.write_reg_page(&adapter->hw, BM_RCTL, phy_reg);
a4f58f54 6209
74f350ee
DE		 6210 wuc = E1000_WUC_PME_EN;
6211 if (wufc & (E1000_WUFC_MAG | E1000_WUFC_LNKC))
6212 wuc |= E1000_WUC_APME;
6213
a4f58f54
BA		 6214 /* enable PHY wakeup in MAC register */
6215 ew32(WUFC, wufc);
74f350ee
DE		 6216 ew32(WUC, (E1000_WUC_PHY_WAKE | E1000_WUC_APMPME |
6217 E1000_WUC_PME_STATUS | wuc));
a4f58f54
BA		 6218
6219 /* configure and enable PHY wakeup in PHY registers */
2b6b168d 6220 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUFC, wufc);
74f350ee 6221 hw->phy.ops.write_reg_page(&adapter->hw, BM_WUC, wuc);
a4f58f54
BA		 6222
6223 /* activate PHY wakeup */
2b6b168d
BA		 6224 wuc_enable |= BM_WUC_ENABLE_BIT | BM_WUC_HOST_WU_BIT;
6225 retval = e1000_disable_phy_wakeup_reg_access_bm(hw, &wuc_enable);
a4f58f54
BA		 6226 if (retval)
6227 e_err("Could not set PHY Host Wakeup bit\n");
75ce1532 6228release:
94d8186a 6229 hw->phy.ops.release(hw);
a4f58f54
BA		 6230
6231 return retval;
6232}
6233
2a7e19af
DE		 6234static void e1000e_flush_lpic(struct pci_dev *pdev)
6235{
6236 struct net_device *netdev = pci_get_drvdata(pdev);
6237 struct e1000_adapter *adapter = netdev_priv(netdev);
6238 struct e1000_hw *hw = &adapter->hw;
6239 u32 ret_val;
6240
6241 pm_runtime_get_sync(netdev->dev.parent);
6242
6243 ret_val = hw->phy.ops.acquire(hw);
6244 if (ret_val)
6245 goto fl_out;
6246
6247 pr_info("EEE TX LPI TIMER: %08X\n",
6248 er32(LPIC) >> E1000_LPIC_LPIET_SHIFT);
6249
6250 hw->phy.ops.release(hw);
6251
6252fl_out:
6253 pm_runtime_put_sync(netdev->dev.parent);
6254}
6255
28002099 6256static int e1000e_pm_freeze(struct device *dev)
bc7f75fa 6257{
28002099 6258 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
bc7f75fa 6259 struct e1000_adapter *adapter = netdev_priv(netdev);
bc7f75fa
AK		 6260
6261 netif_device_detach(netdev);
6262
6263 if (netif_running(netdev)) {
bb9e44d0
BA		 6264 int count = E1000_CHECK_RESET_COUNT;
6265
6266 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6267 usleep_range(10000, 20000);
6268
bc7f75fa 6269 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
28002099
DE		 6270
6271 /* Quiesce the device without resetting the hardware */
6272 e1000e_down(adapter, false);
bc7f75fa
AK		 6273 e1000_free_irq(adapter);
6274 }
4662e82b 6275 e1000e_reset_interrupt_capability(adapter);
bc7f75fa 6276
28002099
DE		 6277 /* Allow time for pending master requests to run */
6278 e1000e_disable_pcie_master(&adapter->hw);
6279
6280 return 0;
6281}
6282
6283static int __e1000_shutdown(struct pci_dev *pdev, bool runtime)
6284{
6285 struct net_device *netdev = pci_get_drvdata(pdev);
6286 struct e1000_adapter *adapter = netdev_priv(netdev);
6287 struct e1000_hw *hw = &adapter->hw;
6288 u32 ctrl, ctrl_ext, rctl, status;
6289 /* Runtime suspend should only enable wakeup for link changes */
6290 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol;
6291 int retval = 0;
6292
bc7f75fa
AK		 6293 status = er32(STATUS);
6294 if (status & E1000_STATUS_LU)
6295 wufc &= ~E1000_WUFC_LNKC;
6296
6297 if (wufc) {
6298 e1000_setup_rctl(adapter);
ef9b965a 6299 e1000e_set_rx_mode(netdev);
bc7f75fa
AK		 6300
6301 /* turn on all-multi mode if wake on multicast is enabled */
6302 if (wufc & E1000_WUFC_MC) {
6303 rctl = er32(RCTL);
6304 rctl |= E1000_RCTL_MPE;
6305 ew32(RCTL, rctl);
6306 }
6307
6308 ctrl = er32(CTRL);
a4f58f54
BA		 6309 ctrl |= E1000_CTRL_ADVD3WUC;
6310 if (!(adapter->flags2 & FLAG2_HAS_PHY_WAKEUP))
6311 ctrl |= E1000_CTRL_EN_PHY_PWR_MGMT;
bc7f75fa
AK		 6312 ew32(CTRL, ctrl);
6313
318a94d6
JK		 6314 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
6315 adapter->hw.phy.media_type ==
6316 e1000_media_type_internal_serdes) {
bc7f75fa
AK		 6317 /* keep the laser running in D3 */
6318 ctrl_ext = er32(CTRL_EXT);
93a23f48 6319 ctrl_ext |= E1000_CTRL_EXT_SDP3_DATA;
bc7f75fa
AK		 6320 ew32(CTRL_EXT, ctrl_ext);
6321 }
6322
63eb48f1
DE		 6323 if (!runtime)
6324 e1000e_power_up_phy(adapter);
6325
97ac8cae 6326 if (adapter->flags & FLAG_IS_ICH)
99730e4c 6327 e1000_suspend_workarounds_ich8lan(&adapter->hw);
97ac8cae 6328
82776a4b 6329 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
a4f58f54
BA		 6330 /* enable wakeup by the PHY */
6331 retval = e1000_init_phy_wakeup(adapter, wufc);
6332 if (retval)
6333 return retval;
6334 } else {
6335 /* enable wakeup by the MAC */
6336 ew32(WUFC, wufc);
6337 ew32(WUC, E1000_WUC_PME_EN);
6338 }
bc7f75fa
AK		 6339 } else {
6340 ew32(WUC, 0);
6341 ew32(WUFC, 0);
28002099
DE		 6342
6343 e1000_power_down_phy(adapter);
bc7f75fa
AK		 6344 }
6345
74f350ee 6346 if (adapter->hw.phy.type == e1000_phy_igp_3) {
bc7f75fa 6347 e1000e_igp3_phy_powerdown_workaround_ich8lan(&adapter->hw);
79849ebc
DE		 6348 } else if ((hw->mac.type == e1000_pch_lpt) ||
6349 (hw->mac.type == e1000_pch_spt)) {
74f350ee
DE		 6350 if (!(wufc & (E1000_WUFC_EX | E1000_WUFC_MC | E1000_WUFC_BC)))
6351 /* ULP does not support wake from unicast, multicast
6352 * or broadcast.
6353 */
6354 retval = e1000_enable_ulp_lpt_lp(hw, !runtime);
6355
6356 if (retval)
6357 return retval;
6358 }
6359
f5ac7445
RA		 6360 /* Ensure that the appropriate bits are set in LPI_CTRL
6361 * for EEE in Sx
6362 */
6363 if ((hw->phy.type >= e1000_phy_i217) &&
6364 adapter->eee_advert && hw->dev_spec.ich8lan.eee_lp_ability) {
6365 u16 lpi_ctrl = 0;
6366
6367 retval = hw->phy.ops.acquire(hw);
6368 if (!retval) {
6369 retval = e1e_rphy_locked(hw, I82579_LPI_CTRL,
6370 &lpi_ctrl);
6371 if (!retval) {
6372 if (adapter->eee_advert &
6373 hw->dev_spec.ich8lan.eee_lp_ability &
6374 I82579_EEE_100_SUPPORTED)
6375 lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE;
6376 if (adapter->eee_advert &
6377 hw->dev_spec.ich8lan.eee_lp_ability &
6378 I82579_EEE_1000_SUPPORTED)
6379 lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE;
6380
6381 retval = e1e_wphy_locked(hw, I82579_LPI_CTRL,
6382 lpi_ctrl);
6383 }
6384 }
6385 hw->phy.ops.release(hw);
6386 }
bc7f75fa 6387
e921eb1a 6388 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 6389 * would have already happened in close and is redundant.
6390 */
31dbe5b4 6391 e1000e_release_hw_control(adapter);
bc7f75fa 6392
24b41c97
DN		 6393 pci_clear_master(pdev);
6394
e921eb1a 6395 /* The pci-e switch on some quad port adapters will report a
005cbdfc
AD		 6396 * correctable error when the MAC transitions from D0 to D3. To
6397 * prevent this we need to mask off the correctable errors on the
6398 * downstream port of the pci-e switch.
e8c254c5
LZ		 6399 *
6400 * We don't have the associated upstream bridge while assigning
6401 * the PCI device into guest. For example, the KVM on power is
6402 * one of the cases.
005cbdfc
AD		 6403 */
6404 if (adapter->flags & FLAG_IS_QUAD_PORT) {
6405 struct pci_dev *us_dev = pdev->bus->self;
005cbdfc
AD		 6406 u16 devctl;
6407
e8c254c5
LZ		 6408 if (!us_dev)
6409 return 0;
6410
f8c0fcac
JL		 6411 pcie_capability_read_word(us_dev, PCI_EXP_DEVCTL, &devctl);
6412 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL,
6413 (devctl & ~PCI_EXP_DEVCTL_CERE));
005cbdfc 6414
66148bab
KK		 6415 pci_save_state(pdev);
6416 pci_prepare_to_sleep(pdev);
005cbdfc 6417
f8c0fcac 6418 pcie_capability_write_word(us_dev, PCI_EXP_DEVCTL, devctl);
005cbdfc 6419 }
66148bab
KK		 6420
6421 return 0;
bc7f75fa
AK		 6422}
6423
13129d9b 6424/**
beb0a152 6425 * __e1000e_disable_aspm - Disable ASPM states
13129d9b
CW		 6426 * @pdev: pointer to PCI device struct
6427 * @state: bit-mask of ASPM states to disable
beb0a152 6428 * @locked: indication if this context holds pci_bus_sem locked.
13129d9b
CW		 6429 *
6430 * Some devices *must* have certain ASPM states disabled per hardware errata.
6431 **/
beb0a152 6432static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state, int locked)
6f461f6c 6433{
13129d9b
CW		 6434 struct pci_dev *parent = pdev->bus->self;
6435 u16 aspm_dis_mask = 0;
6436 u16 pdev_aspmc, parent_aspmc;
6437
6438 switch (state) {
6439 case PCIE_LINK_STATE_L0S:
6440 case PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1:
6441 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L0S;
6442 /* fall-through - can't have L1 without L0s */
6443 case PCIE_LINK_STATE_L1:
6444 aspm_dis_mask |= PCI_EXP_LNKCTL_ASPM_L1;
6445 break;
6446 default:
6447 return;
6448 }
6449
6450 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6451 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6452
6453 if (parent) {
6454 pcie_capability_read_word(parent, PCI_EXP_LNKCTL,
6455 &parent_aspmc);
6456 parent_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6457 }
6458
6459 /* Nothing to do if the ASPM states to be disabled already are */
6460 if (!(pdev_aspmc & aspm_dis_mask) &&
6461 (!parent || !(parent_aspmc & aspm_dis_mask)))
6462 return;
6463
6464 dev_info(&pdev->dev, "Disabling ASPM %s %s\n",
6465 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L0S) ?
6466 "L0s" : "",
6467 (aspm_dis_mask & pdev_aspmc & PCI_EXP_LNKCTL_ASPM_L1) ?
6468 "L1" : "");
6469
6470#ifdef CONFIG_PCIEASPM
beb0a152
YL		 6471 if (locked)
6472 pci_disable_link_state_locked(pdev, state);
6473 else
6474 pci_disable_link_state(pdev, state);
ffe0b2ff 6475
13129d9b
CW		 6476 /* Double-check ASPM control. If not disabled by the above, the
6477 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6478 * not enabled); override by writing PCI config space directly.
6479 */
6480 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &pdev_aspmc);
6481 pdev_aspmc &= PCI_EXP_LNKCTL_ASPMC;
6482
6483 if (!(aspm_dis_mask & pdev_aspmc))
6484 return;
6485#endif
ffe0b2ff 6486
e921eb1a 6487 /* Both device and parent should have the same ASPM setting.
6f461f6c 6488 * Disable ASPM in downstream component first and then upstream.
1eae4eb2 6489 */
13129d9b 6490 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, aspm_dis_mask);
6f461f6c 6491
13129d9b
CW		 6492 if (parent)
6493 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
6494 aspm_dis_mask);
1eae4eb2
AK		 6495}
6496
beb0a152
YL		 6497/**
6498 * e1000e_disable_aspm - Disable ASPM states.
6499 * @pdev: pointer to PCI device struct
6500 * @state: bit-mask of ASPM states to disable
6501 *
6502 * This function acquires the pci_bus_sem!
6503 * Some devices *must* have certain ASPM states disabled per hardware errata.
6504 **/
6505static void e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
6506{
6507 __e1000e_disable_aspm(pdev, state, 0);
6508}
6509
6510/**
6511 * e1000e_disable_aspm_locked Disable ASPM states.
6512 * @pdev: pointer to PCI device struct
6513 * @state: bit-mask of ASPM states to disable
6514 *
6515 * This function must be called with pci_bus_sem acquired!
6516 * Some devices *must* have certain ASPM states disabled per hardware errata.
6517 **/
6518static void e1000e_disable_aspm_locked(struct pci_dev *pdev, u16 state)
6519{
6520 __e1000e_disable_aspm(pdev, state, 1);
6521}
6522
aa338601 6523#ifdef CONFIG_PM
23606cf5 6524static int __e1000_resume(struct pci_dev *pdev)
bc7f75fa
AK		 6525{
6526 struct net_device *netdev = pci_get_drvdata(pdev);
6527 struct e1000_adapter *adapter = netdev_priv(netdev);
6528 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6529 u16 aspm_disable_flag = 0;
bc7f75fa 6530
78cd29d5
BA		 6531 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6532 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6533 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
6534 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6535 if (aspm_disable_flag)
2758f9ed 6536 e1000e_disable_aspm(pdev, aspm_disable_flag);
78cd29d5 6537
66148bab 6538 pci_set_master(pdev);
6e4f6f6b 6539
2fbe4526 6540 if (hw->mac.type >= e1000_pch2lan)
99730e4c
BA		 6541 e1000_resume_workarounds_pchlan(&adapter->hw);
6542
bc7f75fa 6543 e1000e_power_up_phy(adapter);
a4f58f54
BA		 6544
6545 /* report the system wakeup cause from S3/S4 */
6546 if (adapter->flags2 & FLAG2_HAS_PHY_WAKEUP) {
6547 u16 phy_data;
6548
6549 e1e_rphy(&adapter->hw, BM_WUS, &phy_data);
6550 if (phy_data) {
6551 e_info("PHY Wakeup cause - %s\n",
17e813ec
BA		 6552 phy_data & E1000_WUS_EX ? "Unicast Packet" :
6553 phy_data & E1000_WUS_MC ? "Multicast Packet" :
6554 phy_data & E1000_WUS_BC ? "Broadcast Packet" :
6555 phy_data & E1000_WUS_MAG ? "Magic Packet" :
6556 phy_data & E1000_WUS_LNKC ?
6557 "Link Status Change" : "other");
a4f58f54
BA		 6558 }
6559 e1e_wphy(&adapter->hw, BM_WUS, ~0);
6560 } else {
6561 u32 wus = er32(WUS);
6cf08d1c 6562
a4f58f54
BA		 6563 if (wus) {
6564 e_info("MAC Wakeup cause - %s\n",
17e813ec
BA		 6565 wus & E1000_WUS_EX ? "Unicast Packet" :
6566 wus & E1000_WUS_MC ? "Multicast Packet" :
6567 wus & E1000_WUS_BC ? "Broadcast Packet" :
6568 wus & E1000_WUS_MAG ? "Magic Packet" :
6569 wus & E1000_WUS_LNKC ? "Link Status Change" :
6570 "other");
a4f58f54
BA		 6571 }
6572 ew32(WUS, ~0);
6573 }
6574
bc7f75fa 6575 e1000e_reset(adapter);
bc7f75fa 6576
cd791618 6577 e1000_init_manageability_pt(adapter);
bc7f75fa 6578
e921eb1a 6579 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6580 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6581 * under the control of the driver.
6582 */
c43bc57e 6583 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6584 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6585
6586 return 0;
6587}
23606cf5 6588
3e7986f6 6589#ifdef CONFIG_PM_SLEEP
28002099
DE		 6590static int e1000e_pm_thaw(struct device *dev)
6591{
6592 struct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));
6593 struct e1000_adapter *adapter = netdev_priv(netdev);
6594
6595 e1000e_set_interrupt_capability(adapter);
6596 if (netif_running(netdev)) {
6597 u32 err = e1000_request_irq(adapter);
6598
6599 if (err)
6600 return err;
6601
6602 e1000e_up(adapter);
6603 }
6604
6605 netif_device_attach(netdev);
6606
6607 return 0;
6608}
6609
28002099 6610static int e1000e_pm_suspend(struct device *dev)
a0340162
RW		 6611{
6612 struct pci_dev *pdev = to_pci_dev(dev);
a0340162 6613
2a7e19af
DE		 6614 e1000e_flush_lpic(pdev);
6615
28002099
DE		 6616 e1000e_pm_freeze(dev);
6617
66148bab 6618 return __e1000_shutdown(pdev, false);
a0340162
RW		 6619}
6620
28002099 6621static int e1000e_pm_resume(struct device *dev)
23606cf5
RW		 6622{
6623 struct pci_dev *pdev = to_pci_dev(dev);
28002099 6624 int rc;
23606cf5 6625
28002099
DE		 6626 rc = __e1000_resume(pdev);
6627 if (rc)
6628 return rc;
23606cf5 6629
28002099 6630 return e1000e_pm_thaw(dev);
23606cf5 6631}
38a529b5 6632#endif /* CONFIG_PM_SLEEP */
a0340162 6633
63eb48f1 6634static int e1000e_pm_runtime_idle(struct device *dev)
a0340162
RW		 6635{
6636 struct pci_dev *pdev = to_pci_dev(dev);
6637 struct net_device *netdev = pci_get_drvdata(pdev);
6638 struct e1000_adapter *adapter = netdev_priv(netdev);
2116bc25 6639 u16 eee_lp;
a0340162 6640
2116bc25
DE		 6641 eee_lp = adapter->hw.dev_spec.ich8lan.eee_lp_ability;
6642
6643 if (!e1000e_has_link(adapter)) {
6644 adapter->hw.dev_spec.ich8lan.eee_lp_ability = eee_lp;
63eb48f1 6645 pm_schedule_suspend(dev, 5 * MSEC_PER_SEC);
2116bc25 6646 }
a0340162 6647
63eb48f1 6648 return -EBUSY;
a0340162
RW		 6649}
6650
63eb48f1 6651static int e1000e_pm_runtime_resume(struct device *dev)
a0340162
RW		 6652{
6653 struct pci_dev *pdev = to_pci_dev(dev);
6654 struct net_device *netdev = pci_get_drvdata(pdev);
6655 struct e1000_adapter *adapter = netdev_priv(netdev);
63eb48f1 6656 int rc;
a0340162 6657
63eb48f1
DE		 6658 rc = __e1000_resume(pdev);
6659 if (rc)
6660 return rc;
a0340162 6661
63eb48f1 6662 if (netdev->flags & IFF_UP)
386164d9 6663 e1000e_up(adapter);
a0340162 6664
63eb48f1 6665 return rc;
a0340162 6666}
23606cf5 6667
63eb48f1 6668static int e1000e_pm_runtime_suspend(struct device *dev)
23606cf5
RW		 6669{
6670 struct pci_dev *pdev = to_pci_dev(dev);
6671 struct net_device *netdev = pci_get_drvdata(pdev);
6672 struct e1000_adapter *adapter = netdev_priv(netdev);
6673
63eb48f1
DE		 6674 if (netdev->flags & IFF_UP) {
6675 int count = E1000_CHECK_RESET_COUNT;
6676
6677 while (test_bit(__E1000_RESETTING, &adapter->state) && count--)
6678 usleep_range(10000, 20000);
23606cf5 6679
63eb48f1
DE		 6680 WARN_ON(test_bit(__E1000_RESETTING, &adapter->state));
6681
6682 /* Down the device without resetting the hardware */
6683 e1000e_down(adapter, false);
6684 }
6685
6686 if (__e1000_shutdown(pdev, true)) {
6687 e1000e_pm_runtime_resume(dev);
6688 return -EBUSY;
6689 }
6690
6691 return 0;
23606cf5 6692}
aa338601 6693#endif /* CONFIG_PM */
bc7f75fa
AK		 6694
6695static void e1000_shutdown(struct pci_dev *pdev)
6696{
2a7e19af
DE		 6697 e1000e_flush_lpic(pdev);
6698
28002099
DE		 6699 e1000e_pm_freeze(&pdev->dev);
6700
66148bab 6701 __e1000_shutdown(pdev, false);
bc7f75fa
AK		 6702}
6703
6704#ifdef CONFIG_NET_POLL_CONTROLLER
147b2c8c 6705
8bb62869 6706static irqreturn_t e1000_intr_msix(int __always_unused irq, void *data)
147b2c8c
DD		 6707{
6708 struct net_device *netdev = data;
6709 struct e1000_adapter *adapter = netdev_priv(netdev);
147b2c8c
DD		 6710
6711 if (adapter->msix_entries) {
90da0669
BA		 6712 int vector, msix_irq;
6713
147b2c8c
DD		 6714 vector = 0;
6715 msix_irq = adapter->msix_entries[vector].vector;
6716 disable_irq(msix_irq);
6717 e1000_intr_msix_rx(msix_irq, netdev);
6718 enable_irq(msix_irq);
6719
6720 vector++;
6721 msix_irq = adapter->msix_entries[vector].vector;
6722 disable_irq(msix_irq);
6723 e1000_intr_msix_tx(msix_irq, netdev);
6724 enable_irq(msix_irq);
6725
6726 vector++;
6727 msix_irq = adapter->msix_entries[vector].vector;
6728 disable_irq(msix_irq);
6729 e1000_msix_other(msix_irq, netdev);
6730 enable_irq(msix_irq);
6731 }
6732
6733 return IRQ_HANDLED;
6734}
6735
e921eb1a
BA		 6736/**
6737 * e1000_netpoll
6738 * @netdev: network interface device structure
6739 *
bc7f75fa
AK		 6740 * Polling 'interrupt' - used by things like netconsole to send skbs
6741 * without having to re-enable interrupts. It's not called while
6742 * the interrupt routine is executing.
6743 */
6744static void e1000_netpoll(struct net_device *netdev)
6745{
6746 struct e1000_adapter *adapter = netdev_priv(netdev);
6747
147b2c8c
DD		 6748 switch (adapter->int_mode) {
6749 case E1000E_INT_MODE_MSIX:
6750 e1000_intr_msix(adapter->pdev->irq, netdev);
6751 break;
6752 case E1000E_INT_MODE_MSI:
6753 disable_irq(adapter->pdev->irq);
6754 e1000_intr_msi(adapter->pdev->irq, netdev);
6755 enable_irq(adapter->pdev->irq);
6756 break;
e80bd1d1 6757 default: /* E1000E_INT_MODE_LEGACY */
147b2c8c
DD		 6758 disable_irq(adapter->pdev->irq);
6759 e1000_intr(adapter->pdev->irq, netdev);
6760 enable_irq(adapter->pdev->irq);
6761 break;
6762 }
bc7f75fa
AK		 6763}
6764#endif
6765
6766/**
6767 * e1000_io_error_detected - called when PCI error is detected
6768 * @pdev: Pointer to PCI device
6769 * @state: The current pci connection state
6770 *
6771 * This function is called after a PCI bus error affecting
6772 * this device has been detected.
6773 */
6774static pci_ers_result_t e1000_io_error_detected(struct pci_dev *pdev,
6775 pci_channel_state_t state)
6776{
6777 struct net_device *netdev = pci_get_drvdata(pdev);
6778 struct e1000_adapter *adapter = netdev_priv(netdev);
6779
6780 netif_device_detach(netdev);
6781
c93b5a76
MM		 6782 if (state == pci_channel_io_perm_failure)
6783 return PCI_ERS_RESULT_DISCONNECT;
6784
bc7f75fa 6785 if (netif_running(netdev))
28002099 6786 e1000e_down(adapter, true);
bc7f75fa
AK		 6787 pci_disable_device(pdev);
6788
6789 /* Request a slot slot reset. */
6790 return PCI_ERS_RESULT_NEED_RESET;
6791}
6792
6793/**
6794 * e1000_io_slot_reset - called after the pci bus has been reset.
6795 * @pdev: Pointer to PCI device
6796 *
6797 * Restart the card from scratch, as if from a cold-boot. Implementation
28002099 6798 * resembles the first-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6799 */
6800static pci_ers_result_t e1000_io_slot_reset(struct pci_dev *pdev)
6801{
6802 struct net_device *netdev = pci_get_drvdata(pdev);
6803 struct e1000_adapter *adapter = netdev_priv(netdev);
6804 struct e1000_hw *hw = &adapter->hw;
78cd29d5 6805 u16 aspm_disable_flag = 0;
6e4f6f6b 6806 int err;
111b9dc5 6807 pci_ers_result_t result;
bc7f75fa 6808
78cd29d5
BA		 6809 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L0S)
6810 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 6811 if (adapter->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 6812 aspm_disable_flag |= PCIE_LINK_STATE_L1;
6813 if (aspm_disable_flag)
2758f9ed 6814 e1000e_disable_aspm_locked(pdev, aspm_disable_flag);
78cd29d5 6815
f0f422e5 6816 err = pci_enable_device_mem(pdev);
6e4f6f6b 6817 if (err) {
bc7f75fa
AK		 6818 dev_err(&pdev->dev,
6819 "Cannot re-enable PCI device after reset.\n");
111b9dc5
JB		 6820 result = PCI_ERS_RESULT_DISCONNECT;
6821 } else {
23606cf5 6822 pdev->state_saved = true;
111b9dc5 6823 pci_restore_state(pdev);
66148bab 6824 pci_set_master(pdev);
bc7f75fa 6825
111b9dc5
JB		 6826 pci_enable_wake(pdev, PCI_D3hot, 0);
6827 pci_enable_wake(pdev, PCI_D3cold, 0);
bc7f75fa 6828
111b9dc5
JB		 6829 e1000e_reset(adapter);
6830 ew32(WUS, ~0);
6831 result = PCI_ERS_RESULT_RECOVERED;
6832 }
bc7f75fa 6833
111b9dc5
JB		 6834 pci_cleanup_aer_uncorrect_error_status(pdev);
6835
6836 return result;
bc7f75fa
AK		 6837}
6838
6839/**
6840 * e1000_io_resume - called when traffic can start flowing again.
6841 * @pdev: Pointer to PCI device
6842 *
6843 * This callback is called when the error recovery driver tells us that
6844 * its OK to resume normal operation. Implementation resembles the
28002099 6845 * second-half of the e1000e_pm_resume routine.
bc7f75fa
AK		 6846 */
6847static void e1000_io_resume(struct pci_dev *pdev)
6848{
6849 struct net_device *netdev = pci_get_drvdata(pdev);
6850 struct e1000_adapter *adapter = netdev_priv(netdev);
6851
cd791618 6852 e1000_init_manageability_pt(adapter);
bc7f75fa 6853
386164d9
AD		 6854 if (netif_running(netdev))
6855 e1000e_up(adapter);
bc7f75fa
AK		 6856
6857 netif_device_attach(netdev);
6858
e921eb1a 6859 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 6860 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 6861 * under the control of the driver.
6862 */
c43bc57e 6863 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 6864 e1000e_get_hw_control(adapter);
bc7f75fa
AK		 6865}
6866
6867static void e1000_print_device_info(struct e1000_adapter *adapter)
6868{
6869 struct e1000_hw *hw = &adapter->hw;
6870 struct net_device *netdev = adapter->netdev;
073287c0
BA		 6871 u32 ret_val;
6872 u8 pba_str[E1000_PBANUM_LENGTH];
bc7f75fa
AK		 6873
6874 /* print bus type/speed/width info */
a5cc7642 6875 e_info("(PCI Express:2.5GT/s:%s) %pM\n",
44defeb3
JK		 6876 /* bus width */
6877 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
f0ff4398 6878 "Width x1"),
44defeb3 6879 /* MAC address */
7c510e4b 6880 netdev->dev_addr);
44defeb3
JK		 6881 e_info("Intel(R) PRO/%s Network Connection\n",
6882 (hw->phy.type == e1000_phy_ife) ? "10/100" : "1000");
073287c0
BA		 6883 ret_val = e1000_read_pba_string_generic(hw, pba_str,
6884 E1000_PBANUM_LENGTH);
6885 if (ret_val)
f2315bf1 6886 strlcpy((char *)pba_str, "Unknown", sizeof(pba_str));
073287c0
BA		 6887 e_info("MAC: %d, PHY: %d, PBA No: %s\n",
6888 hw->mac.type, hw->phy.type, pba_str);
bc7f75fa
AK		 6889}
6890
10aa4c04
AK		 6891static void e1000_eeprom_checks(struct e1000_adapter *adapter)
6892{
6893 struct e1000_hw *hw = &adapter->hw;
6894 int ret_val;
6895 u16 buf = 0;
6896
6897 if (hw->mac.type != e1000_82573)
6898 return;
6899
6900 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &buf);
e885d762 6901 le16_to_cpus(&buf);
18dd2392 6902 if (!ret_val && (!(buf & BIT(0)))) {
10aa4c04 6903 /* Deep Smart Power Down (DSPD) */
6c2a9efa
FP		 6904 dev_warn(&adapter->pdev->dev,
6905 "Warning: detected DSPD enabled in EEPROM\n");
10aa4c04 6906 }
10aa4c04
AK		 6907}
6908
55e7fe5b
AD		 6909static netdev_features_t e1000_fix_features(struct net_device *netdev,
6910 netdev_features_t features)
6911{
6912 struct e1000_adapter *adapter = netdev_priv(netdev);
6913 struct e1000_hw *hw = &adapter->hw;
6914
6915 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6916 if ((hw->mac.type >= e1000_pch2lan) && (netdev->mtu > ETH_DATA_LEN))
6917 features &= ~NETIF_F_RXFCS;
6918
83808641
JW		 6919 /* Since there is no support for separate Rx/Tx vlan accel
6920 * enable/disable make sure Tx flag is always in same state as Rx.
6921 */
6922 if (features & NETIF_F_HW_VLAN_CTAG_RX)
6923 features |= NETIF_F_HW_VLAN_CTAG_TX;
6924 else
6925 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
6926
55e7fe5b
AD		 6927 return features;
6928}
6929
c8f44aff 6930static int e1000_set_features(struct net_device *netdev,
70495a50 6931 netdev_features_t features)
dc221294
BA		 6932{
6933 struct e1000_adapter *adapter = netdev_priv(netdev);
c8f44aff 6934 netdev_features_t changed = features ^ netdev->features;
dc221294
BA		 6935
6936 if (changed & (NETIF_F_TSO | NETIF_F_TSO6))
6937 adapter->flags |= FLAG_TSO_FORCE;
6938
f646968f 6939 if (!(changed & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
cf955e6c
BG		 6940 NETIF_F_RXCSUM | NETIF_F_RXHASH | NETIF_F_RXFCS |
6941 NETIF_F_RXALL)))
dc221294
BA		 6942 return 0;
6943
0184039a
BG		 6944 if (changed & NETIF_F_RXFCS) {
6945 if (features & NETIF_F_RXFCS) {
6946 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6947 } else {
6948 /* We need to take it back to defaults, which might mean
6949 * stripping is still disabled at the adapter level.
6950 */
6951 if (adapter->flags2 & FLAG2_DFLT_CRC_STRIPPING)
6952 adapter->flags2 |= FLAG2_CRC_STRIPPING;
6953 else
6954 adapter->flags2 &= ~FLAG2_CRC_STRIPPING;
6955 }
6956 }
6957
70495a50
BA		 6958 netdev->features = features;
6959
dc221294
BA		 6960 if (netif_running(netdev))
6961 e1000e_reinit_locked(adapter);
6962 else
6963 e1000e_reset(adapter);
6964
6965 return 0;
6966}
6967
651c2466 6968static const struct net_device_ops e1000e_netdev_ops = {
d5ea45da
SA		 6969 .ndo_open = e1000e_open,
6970 .ndo_stop = e1000e_close,
00829823 6971 .ndo_start_xmit = e1000_xmit_frame,
67fd4fcb 6972 .ndo_get_stats64 = e1000e_get_stats64,
ef9b965a 6973 .ndo_set_rx_mode = e1000e_set_rx_mode,
651c2466
SH		 6974 .ndo_set_mac_address = e1000_set_mac,
6975 .ndo_change_mtu = e1000_change_mtu,
6976 .ndo_do_ioctl = e1000_ioctl,
6977 .ndo_tx_timeout = e1000_tx_timeout,
6978 .ndo_validate_addr = eth_validate_addr,
6979
651c2466
SH		 6980 .ndo_vlan_rx_add_vid = e1000_vlan_rx_add_vid,
6981 .ndo_vlan_rx_kill_vid = e1000_vlan_rx_kill_vid,
6982#ifdef CONFIG_NET_POLL_CONTROLLER
6983 .ndo_poll_controller = e1000_netpoll,
6984#endif
dc221294 6985 .ndo_set_features = e1000_set_features,
55e7fe5b 6986 .ndo_fix_features = e1000_fix_features,
f2701b18 6987 .ndo_features_check = passthru_features_check,
651c2466
SH		 6988};
6989
bc7f75fa
AK		 6990/**
6991 * e1000_probe - Device Initialization Routine
6992 * @pdev: PCI device information struct
6993 * @ent: entry in e1000_pci_tbl
6994 *
6995 * Returns 0 on success, negative on failure
6996 *
6997 * e1000_probe initializes an adapter identified by a pci_dev structure.
6998 * The OS initialization, configuring of the adapter private structure,
6999 * and a hardware reset occur.
7000 **/
1dd06ae8 7001static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
bc7f75fa
AK		 7002{
7003 struct net_device *netdev;
7004 struct e1000_adapter *adapter;
7005 struct e1000_hw *hw;
7006 const struct e1000_info *ei = e1000_info_tbl[ent->driver_data];
f47e81fc
BB		 7007 resource_size_t mmio_start, mmio_len;
7008 resource_size_t flash_start, flash_len;
bc7f75fa 7009 static int cards_found;
78cd29d5 7010 u16 aspm_disable_flag = 0;
17e813ec 7011 int bars, i, err, pci_using_dac;
bc7f75fa
AK		 7012 u16 eeprom_data = 0;
7013 u16 eeprom_apme_mask = E1000_EEPROM_APME;
847042a6 7014 s32 ret_val = 0;
bc7f75fa 7015
78cd29d5
BA		 7016 if (ei->flags2 & FLAG2_DISABLE_ASPM_L0S)
7017 aspm_disable_flag = PCIE_LINK_STATE_L0S;
6f461f6c 7018 if (ei->flags2 & FLAG2_DISABLE_ASPM_L1)
78cd29d5
BA		 7019 aspm_disable_flag |= PCIE_LINK_STATE_L1;
7020 if (aspm_disable_flag)
7021 e1000e_disable_aspm(pdev, aspm_disable_flag);
6e4f6f6b 7022
f0f422e5 7023 err = pci_enable_device_mem(pdev);
bc7f75fa
AK		 7024 if (err)
7025 return err;
7026
7027 pci_using_dac = 0;
718a39eb 7028 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
bc7f75fa 7029 if (!err) {
718a39eb 7030 pci_using_dac = 1;
bc7f75fa 7031 } else {
718a39eb 7032 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
bc7f75fa 7033 if (err) {
718a39eb
RK		 7034 dev_err(&pdev->dev,
7035 "No usable DMA configuration, aborting\n");
7036 goto err_dma;
bc7f75fa
AK		 7037 }
7038 }
7039
17e813ec
BA		 7040 bars = pci_select_bars(pdev, IORESOURCE_MEM);
7041 err = pci_request_selected_regions_exclusive(pdev, bars,
7042 e1000e_driver_name);
bc7f75fa
AK		 7043 if (err)
7044 goto err_pci_reg;
7045
68eac460 7046 /* AER (Advanced Error Reporting) hooks */
19d5afd4 7047 pci_enable_pcie_error_reporting(pdev);
68eac460 7048
bc7f75fa 7049 pci_set_master(pdev);
438b365a
BA		 7050 /* PCI config space info */
7051 err = pci_save_state(pdev);
7052 if (err)
7053 goto err_alloc_etherdev;
bc7f75fa
AK		 7054
7055 err = -ENOMEM;
7056 netdev = alloc_etherdev(sizeof(struct e1000_adapter));
7057 if (!netdev)
7058 goto err_alloc_etherdev;
7059
bc7f75fa
AK		 7060 SET_NETDEV_DEV(netdev, &pdev->dev);
7061
f85e4dfa
TH		 7062 netdev->irq = pdev->irq;
7063
bc7f75fa
AK		 7064 pci_set_drvdata(pdev, netdev);
7065 adapter = netdev_priv(netdev);
7066 hw = &adapter->hw;
7067 adapter->netdev = netdev;
7068 adapter->pdev = pdev;
7069 adapter->ei = ei;
7070 adapter->pba = ei->pba;
7071 adapter->flags = ei->flags;
eb7c3adb 7072 adapter->flags2 = ei->flags2;
bc7f75fa
AK		 7073 adapter->hw.adapter = adapter;
7074 adapter->hw.mac.type = ei->mac;
2adc55c9 7075 adapter->max_hw_frame_size = ei->max_hw_frame_size;
b3f4d599 7076 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
bc7f75fa
AK		 7077
7078 mmio_start = pci_resource_start(pdev, 0);
7079 mmio_len = pci_resource_len(pdev, 0);
7080
7081 err = -EIO;
7082 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
7083 if (!adapter->hw.hw_addr)
7084 goto err_ioremap;
7085
7086 if ((adapter->flags & FLAG_HAS_FLASH) &&
1103a631
YL		 7087 (pci_resource_flags(pdev, 1) & IORESOURCE_MEM) &&
7088 (hw->mac.type < e1000_pch_spt)) {
bc7f75fa
AK		 7089 flash_start = pci_resource_start(pdev, 1);
7090 flash_len = pci_resource_len(pdev, 1);
7091 adapter->hw.flash_address = ioremap(flash_start, flash_len);
7092 if (!adapter->hw.flash_address)
7093 goto err_flashmap;
7094 }
7095
d495bcb8
BA		 7096 /* Set default EEE advertisement */
7097 if (adapter->flags2 & FLAG2_HAS_EEE)
7098 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T;
7099
bc7f75fa 7100 /* construct the net_device struct */
e80bd1d1 7101 netdev->netdev_ops = &e1000e_netdev_ops;
bc7f75fa 7102 e1000e_set_ethtool_ops(netdev);
e80bd1d1 7103 netdev->watchdog_timeo = 5 * HZ;
c58c8a78 7104 netif_napi_add(netdev, &adapter->napi, e1000e_poll, 64);
f2315bf1 7105 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
bc7f75fa
AK		 7106
7107 netdev->mem_start = mmio_start;
7108 netdev->mem_end = mmio_start + mmio_len;
7109
7110 adapter->bd_number = cards_found++;
7111
4662e82b
BA		 7112 e1000e_check_options(adapter);
7113
bc7f75fa
AK		 7114 /* setup adapter struct */
7115 err = e1000_sw_init(adapter);
7116 if (err)
7117 goto err_sw_init;
7118
bc7f75fa
AK		 7119 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
7120 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
7121 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
7122
69e3fd8c 7123 err = ei->get_variants(adapter);
bc7f75fa
AK		 7124 if (err)
7125 goto err_hw_init;
7126
4a770358 7127 if ((adapter->flags & FLAG_IS_ICH) &&
152c0a97
YL		 7128 (adapter->flags & FLAG_READ_ONLY_NVM) &&
7129 (hw->mac.type < e1000_pch_spt))
4a770358
BA		 7130 e1000e_write_protect_nvm_ich8lan(&adapter->hw);
7131
bc7f75fa
AK		 7132 hw->mac.ops.get_bus_info(&adapter->hw);
7133
318a94d6 7134 adapter->hw.phy.autoneg_wait_to_complete = 0;
bc7f75fa
AK		 7135
7136 /* Copper options */
318a94d6 7137 if (adapter->hw.phy.media_type == e1000_media_type_copper) {
bc7f75fa
AK		 7138 adapter->hw.phy.mdix = AUTO_ALL_MODES;
7139 adapter->hw.phy.disable_polarity_correction = 0;
7140 adapter->hw.phy.ms_type = e1000_ms_hw_default;
7141 }
7142
470a5420 7143 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
185095fb
BA		 7144 dev_info(&pdev->dev,
7145 "PHY reset is blocked due to SOL/IDER session.\n");
bc7f75fa 7146
dc221294
BA		 7147 /* Set initial default active device features */
7148 netdev->features = (NETIF_F_SG |
f646968f
PM		 7149 NETIF_F_HW_VLAN_CTAG_RX |
7150 NETIF_F_HW_VLAN_CTAG_TX |
dc221294
BA		 7151 NETIF_F_TSO |
7152 NETIF_F_TSO6 |
70495a50 7153 NETIF_F_RXHASH |
dc221294
BA		 7154 NETIF_F_RXCSUM |
7155 NETIF_F_HW_CSUM);
7156
7157 /* Set user-changeable features (subset of all device features) */
7158 netdev->hw_features = netdev->features;
0184039a 7159 netdev->hw_features |= NETIF_F_RXFCS;
943146de 7160 netdev->priv_flags |= IFF_SUPP_NOFCS;
cf955e6c 7161 netdev->hw_features |= NETIF_F_RXALL;
bc7f75fa
AK		 7162
7163 if (adapter->flags & FLAG_HAS_HW_VLAN_FILTER)
f646968f 7164 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
bc7f75fa 7165
dc221294
BA		 7166 netdev->vlan_features |= (NETIF_F_SG |
7167 NETIF_F_TSO |
7168 NETIF_F_TSO6 |
7169 NETIF_F_HW_CSUM);
a5136e23 7170
ef9b965a
JB		 7171 netdev->priv_flags |= IFF_UNICAST_FLT;
7172
7b872a55 7173 if (pci_using_dac) {
bc7f75fa 7174 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7175 netdev->vlan_features |= NETIF_F_HIGHDMA;
7176 }
bc7f75fa 7177
bc7f75fa
AK		 7178 if (e1000e_enable_mng_pass_thru(&adapter->hw))
7179 adapter->flags |= FLAG_MNG_PT_ENABLED;
7180
e921eb1a 7181 /* before reading the NVM, reset the controller to
ad68076e
BA		 7182 * put the device in a known good starting state
7183 */
bc7f75fa
AK		 7184 adapter->hw.mac.ops.reset_hw(&adapter->hw);
7185
e921eb1a 7186 /* systems with ASPM and others may see the checksum fail on the first
bc7f75fa
AK		 7187 * attempt. Let's give it a few tries
7188 */
7189 for (i = 0;; i++) {
7190 if (e1000_validate_nvm_checksum(&adapter->hw) >= 0)
7191 break;
7192 if (i == 2) {
185095fb 7193 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
bc7f75fa
AK		 7194 err = -EIO;
7195 goto err_eeprom;
7196 }
7197 }
7198
10aa4c04
AK		 7199 e1000_eeprom_checks(adapter);
7200
608f8a0d 7201 /* copy the MAC address */
bc7f75fa 7202 if (e1000e_read_mac_addr(&adapter->hw))
185095fb
BA		 7203 dev_err(&pdev->dev,
7204 "NVM Read Error while reading MAC address\n");
bc7f75fa
AK		 7205
7206 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
bc7f75fa 7207
aaeb6cdf 7208 if (!is_valid_ether_addr(netdev->dev_addr)) {
185095fb 7209 dev_err(&pdev->dev, "Invalid MAC Address: %pM\n",
aaeb6cdf 7210 netdev->dev_addr);
bc7f75fa
AK		 7211 err = -EIO;
7212 goto err_eeprom;
7213 }
7214
7215 init_timer(&adapter->watchdog_timer);
c061b18d 7216 adapter->watchdog_timer.function = e1000_watchdog;
53aa82da 7217 adapter->watchdog_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 7218
7219 init_timer(&adapter->phy_info_timer);
c061b18d 7220 adapter->phy_info_timer.function = e1000_update_phy_info;
53aa82da 7221 adapter->phy_info_timer.data = (unsigned long)adapter;
bc7f75fa
AK		 7222
7223 INIT_WORK(&adapter->reset_task, e1000_reset_task);
7224 INIT_WORK(&adapter->watchdog_task, e1000_watchdog_task);
a8f88ff5
JB		 7225 INIT_WORK(&adapter->downshift_task, e1000e_downshift_workaround);
7226 INIT_WORK(&adapter->update_phy_task, e1000e_update_phy_task);
41cec6f1 7227 INIT_WORK(&adapter->print_hang_task, e1000_print_hw_hang);
bc7f75fa 7228
bc7f75fa
AK		 7229 /* Initialize link parameters. User can change them with ethtool */
7230 adapter->hw.mac.autoneg = 1;
3db1cd5c 7231 adapter->fc_autoneg = true;
5c48ef3e
BA		 7232 adapter->hw.fc.requested_mode = e1000_fc_default;
7233 adapter->hw.fc.current_mode = e1000_fc_default;
bc7f75fa
AK		 7234 adapter->hw.phy.autoneg_advertised = 0x2f;
7235
e921eb1a 7236 /* Initial Wake on LAN setting - If APM wake is enabled in
bc7f75fa
AK		 7237 * the EEPROM, enable the ACPI Magic Packet filter
7238 */
7239 if (adapter->flags & FLAG_APME_IN_WUC) {
7240 /* APME bit in EEPROM is mapped to WUC.APME */
7241 eeprom_data = er32(WUC);
7242 eeprom_apme_mask = E1000_WUC_APME;
4def99bb
BA		 7243 if ((hw->mac.type > e1000_ich10lan) &&
7244 (eeprom_data & E1000_WUC_PHY_WAKE))
a4f58f54 7245 adapter->flags2 |= FLAG2_HAS_PHY_WAKEUP;
bc7f75fa
AK		 7246 } else if (adapter->flags & FLAG_APME_IN_CTRL3) {
7247 if (adapter->flags & FLAG_APME_CHECK_PORT_B &&
7248 (adapter->hw.bus.func == 1))
847042a6 7249 ret_val = e1000_read_nvm(&adapter->hw,
491a04d2
DE		 7250 NVM_INIT_CONTROL3_PORT_B,
7251 1, &eeprom_data);
bc7f75fa 7252 else
847042a6 7253 ret_val = e1000_read_nvm(&adapter->hw,
491a04d2
DE		 7254 NVM_INIT_CONTROL3_PORT_A,
7255 1, &eeprom_data);
bc7f75fa
AK		 7256 }
7257
7258 /* fetch WoL from EEPROM */
847042a6
BW		 7259 if (ret_val)
7260 e_dbg("NVM read error getting WoL initial values: %d\n", ret_val);
491a04d2 7261 else if (eeprom_data & eeprom_apme_mask)
bc7f75fa
AK		 7262 adapter->eeprom_wol |= E1000_WUFC_MAG;
7263
e921eb1a 7264 /* now that we have the eeprom settings, apply the special cases
bc7f75fa
AK		 7265 * where the eeprom may be wrong or the board simply won't support
7266 * wake on lan on a particular port
7267 */
7268 if (!(adapter->flags & FLAG_HAS_WOL))
7269 adapter->eeprom_wol = 0;
7270
7271 /* initialize the wol settings based on the eeprom settings */
7272 adapter->wol = adapter->eeprom_wol;
66148bab
KK		 7273
7274 /* make sure adapter isn't asleep if manageability is enabled */
7275 if (adapter->wol || (adapter->flags & FLAG_MNG_PT_ENABLED) ||
7276 (hw->mac.ops.check_mng_mode(hw)))
7277 device_wakeup_enable(&pdev->dev);
bc7f75fa 7278
84527590 7279 /* save off EEPROM version number */
847042a6 7280 ret_val = e1000_read_nvm(&adapter->hw, 5, 1, &adapter->eeprom_vers);
491a04d2 7281
847042a6
BW		 7282 if (ret_val) {
7283 e_dbg("NVM read error getting EEPROM version: %d\n", ret_val);
491a04d2
DE		 7284 adapter->eeprom_vers = 0;
7285 }
84527590 7286
aa524b66
JK		 7287 /* init PTP hardware clock */
7288 e1000e_ptp_init(adapter);
7289
bc7f75fa
AK		 7290 /* reset the hardware with the new settings */
7291 e1000e_reset(adapter);
7292
e921eb1a 7293 /* If the controller has AMT, do not set DRV_LOAD until the interface
bc7f75fa 7294 * is up. For all other cases, let the f/w know that the h/w is now
ad68076e
BA		 7295 * under the control of the driver.
7296 */
c43bc57e 7297 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 7298 e1000e_get_hw_control(adapter);
bc7f75fa 7299
f2315bf1 7300 strlcpy(netdev->name, "eth%d", sizeof(netdev->name));
bc7f75fa
AK		 7301 err = register_netdev(netdev);
7302 if (err)
7303 goto err_register;
7304
9c563d20
JB		 7305 /* carrier off reporting is important to ethtool even BEFORE open */
7306 netif_carrier_off(netdev);
7307
bc7f75fa
AK		 7308 e1000_print_device_info(adapter);
7309
f3ec4f87
AS		 7310 if (pci_dev_run_wake(pdev))
7311 pm_runtime_put_noidle(&pdev->dev);
23606cf5 7312
bc7f75fa
AK		 7313 return 0;
7314
7315err_register:
c43bc57e 7316 if (!(adapter->flags & FLAG_HAS_AMT))
31dbe5b4 7317 e1000e_release_hw_control(adapter);
bc7f75fa 7318err_eeprom:
470a5420 7319 if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
bc7f75fa 7320 e1000_phy_hw_reset(&adapter->hw);
c43bc57e 7321err_hw_init:
bc7f75fa
AK		 7322 kfree(adapter->tx_ring);
7323 kfree(adapter->rx_ring);
7324err_sw_init:
1103a631 7325 if ((adapter->hw.flash_address) && (hw->mac.type < e1000_pch_spt))
c43bc57e 7326 iounmap(adapter->hw.flash_address);
e82f54ba 7327 e1000e_reset_interrupt_capability(adapter);
c43bc57e 7328err_flashmap:
bc7f75fa
AK		 7329 iounmap(adapter->hw.hw_addr);
7330err_ioremap:
7331 free_netdev(netdev);
7332err_alloc_etherdev:
56d766d6 7333 pci_release_mem_regions(pdev);
bc7f75fa
AK		 7334err_pci_reg:
7335err_dma:
7336 pci_disable_device(pdev);
7337 return err;
7338}
7339
7340/**
7341 * e1000_remove - Device Removal Routine
7342 * @pdev: PCI device information struct
7343 *
7344 * e1000_remove is called by the PCI subsystem to alert the driver
7345 * that it should release a PCI device. The could be caused by a
7346 * Hot-Plug event, or because the driver is going to be removed from
7347 * memory.
7348 **/
9f9a12f8 7349static void e1000_remove(struct pci_dev *pdev)
bc7f75fa
AK		 7350{
7351 struct net_device *netdev = pci_get_drvdata(pdev);
7352 struct e1000_adapter *adapter = netdev_priv(netdev);
23606cf5
RW		 7353 bool down = test_bit(__E1000_DOWN, &adapter->state);
7354
d89777bf
BA		 7355 e1000e_ptp_remove(adapter);
7356
e921eb1a 7357 /* The timers may be rescheduled, so explicitly disable them
23f333a2 7358 * from being rescheduled.
ad68076e 7359 */
23606cf5
RW		 7360 if (!down)
7361 set_bit(__E1000_DOWN, &adapter->state);
bc7f75fa
AK		 7362 del_timer_sync(&adapter->watchdog_timer);
7363 del_timer_sync(&adapter->phy_info_timer);
7364
41cec6f1
BA		 7365 cancel_work_sync(&adapter->reset_task);
7366 cancel_work_sync(&adapter->watchdog_task);
7367 cancel_work_sync(&adapter->downshift_task);
7368 cancel_work_sync(&adapter->update_phy_task);
7369 cancel_work_sync(&adapter->print_hang_task);
bc7f75fa 7370
b67e1913
BA		 7371 if (adapter->flags & FLAG_HAS_HW_TIMESTAMP) {
7372 cancel_work_sync(&adapter->tx_hwtstamp_work);
7373 if (adapter->tx_hwtstamp_skb) {
7374 dev_kfree_skb_any(adapter->tx_hwtstamp_skb);
7375 adapter->tx_hwtstamp_skb = NULL;
7376 }
7377 }
7378
23606cf5
RW		 7379 /* Don't lie to e1000_close() down the road. */
7380 if (!down)
7381 clear_bit(__E1000_DOWN, &adapter->state);
17f208de
BA		 7382 unregister_netdev(netdev);
7383
f3ec4f87
AS		 7384 if (pci_dev_run_wake(pdev))
7385 pm_runtime_get_noresume(&pdev->dev);
23606cf5 7386
e921eb1a 7387 /* Release control of h/w to f/w. If f/w is AMT enabled, this
ad68076e
BA		 7388 * would have already happened in close and is redundant.
7389 */
31dbe5b4 7390 e1000e_release_hw_control(adapter);
bc7f75fa 7391
4662e82b 7392 e1000e_reset_interrupt_capability(adapter);
bc7f75fa
AK		 7393 kfree(adapter->tx_ring);
7394 kfree(adapter->rx_ring);
7395
7396 iounmap(adapter->hw.hw_addr);
1103a631
YL		 7397 if ((adapter->hw.flash_address) &&
7398 (adapter->hw.mac.type < e1000_pch_spt))
bc7f75fa 7399 iounmap(adapter->hw.flash_address);
56d766d6 7400 pci_release_mem_regions(pdev);
bc7f75fa
AK		 7401
7402 free_netdev(netdev);
7403
111b9dc5 7404 /* AER disable */
19d5afd4 7405 pci_disable_pcie_error_reporting(pdev);
111b9dc5 7406
bc7f75fa
AK		 7407 pci_disable_device(pdev);
7408}
7409
7410/* PCI Error Recovery (ERS) */
3646f0e5 7411static const struct pci_error_handlers e1000_err_handler = {
bc7f75fa
AK		 7412 .error_detected = e1000_io_error_detected,
7413 .slot_reset = e1000_io_slot_reset,
7414 .resume = e1000_io_resume,
7415};
7416
0e8e842b 7417static const struct pci_device_id e1000_pci_tbl[] = {
bc7f75fa
AK		 7418 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_COPPER), board_82571 },
7419 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_FIBER), board_82571 },
7420 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER), board_82571 },
c29c3ba5
BA		 7421 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_COPPER_LP),
7422 board_82571 },
bc7f75fa
AK		 7423 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_QUAD_FIBER), board_82571 },
7424 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES), board_82571 },
040babf9
AK		 7425 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_DUAL), board_82571 },
7426 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571EB_SERDES_QUAD), board_82571 },
7427 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82571PT_QUAD_COPPER), board_82571 },
ad68076e 7428
bc7f75fa
AK		 7429 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI), board_82572 },
7430 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_COPPER), board_82572 },
7431 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_FIBER), board_82572 },
7432 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82572EI_SERDES), board_82572 },
ad68076e 7433
bc7f75fa
AK		 7434 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E), board_82573 },
7435 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573E_IAMT), board_82573 },
7436 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82573L), board_82573 },
ad68076e 7437
4662e82b 7438 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574L), board_82574 },
bef28b11 7439 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82574LA), board_82574 },
8c81c9c3 7440 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82583V), board_82583 },
4662e82b 7441
bc7f75fa
AK		 7442 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_DPT),
7443 board_80003es2lan },
7444 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_COPPER_SPT),
7445 board_80003es2lan },
7446 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_DPT),
7447 board_80003es2lan },
7448 { PCI_VDEVICE(INTEL, E1000_DEV_ID_80003ES2LAN_SERDES_SPT),
7449 board_80003es2lan },
ad68076e 7450
bc7f75fa
AK		 7451 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE), board_ich8lan },
7452 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_G), board_ich8lan },
7453 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IFE_GT), board_ich8lan },
7454 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_AMT), board_ich8lan },
7455 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_C), board_ich8lan },
7456 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M), board_ich8lan },
7457 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_IGP_M_AMT), board_ich8lan },
9e135a2e 7458 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH8_82567V_3), board_ich8lan },
ad68076e 7459
bc7f75fa
AK		 7460 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE), board_ich9lan },
7461 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_G), board_ich9lan },
7462 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IFE_GT), board_ich9lan },
7463 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_AMT), board_ich9lan },
7464 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_C), board_ich9lan },
2f15f9d6 7465 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_BM), board_ich9lan },
97ac8cae
BA		 7466 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M), board_ich9lan },
7467 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_AMT), board_ich9lan },
7468 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH9_IGP_M_V), board_ich9lan },
7469
7470 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LM), board_ich9lan },
7471 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_LF), board_ich9lan },
7472 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_R_BM_V), board_ich9lan },
bc7f75fa 7473
f4187b56
BA		 7474 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LM), board_ich10lan },
7475 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_LF), board_ich10lan },
10df0b91 7476 { PCI_VDEVICE(INTEL, E1000_DEV_ID_ICH10_D_BM_V), board_ich10lan },
f4187b56 7477
a4f58f54
BA		 7478 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LM), board_pchlan },
7479 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_M_HV_LC), board_pchlan },
7480 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DM), board_pchlan },
7481 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_D_HV_DC), board_pchlan },
7482
d3738bb8
BA		 7483 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_LM), board_pch2lan },
7484 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH2_LV_V), board_pch2lan },
7485
2fbe4526
BA		 7486 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_LM), board_pch_lpt },
7487 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPT_I217_V), board_pch_lpt },
16e310ae
BA		 7488 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_LM), board_pch_lpt },
7489 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LPTLP_I218_V), board_pch_lpt },
91a3d82f
BA		 7490 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM2), board_pch_lpt },
7491 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V2), board_pch_lpt },
7492 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_LM3), board_pch_lpt },
7493 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_I218_V3), board_pch_lpt },
79849ebc
DE		 7494 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM), board_pch_spt },
7495 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V), board_pch_spt },
7496 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM2), board_pch_spt },
7497 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V2), board_pch_spt },
f3ed935d 7498 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_LBG_I219_LM3), board_pch_spt },
9cd34b3a
RA		 7499 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM4), board_pch_spt },
7500 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
7501 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
7502 { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
2fbe4526 7503
f36bb6ca 7504 { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
bc7f75fa
AK		 7505};
7506MODULE_DEVICE_TABLE(pci, e1000_pci_tbl);
7507
23606cf5 7508static const struct dev_pm_ops e1000_pm_ops = {
72f72dcc 7509#ifdef CONFIG_PM_SLEEP
28002099
DE		 7510 .suspend = e1000e_pm_suspend,
7511 .resume = e1000e_pm_resume,
7512 .freeze = e1000e_pm_freeze,
7513 .thaw = e1000e_pm_thaw,
7514 .poweroff = e1000e_pm_suspend,
7515 .restore = e1000e_pm_resume,
72f72dcc 7516#endif
63eb48f1
DE		 7517 SET_RUNTIME_PM_OPS(e1000e_pm_runtime_suspend, e1000e_pm_runtime_resume,
7518 e1000e_pm_runtime_idle)
23606cf5
RW		 7519};
7520
bc7f75fa
AK		 7521/* PCI Device API Driver */
7522static struct pci_driver e1000_driver = {
7523 .name = e1000e_driver_name,
7524 .id_table = e1000_pci_tbl,
7525 .probe = e1000_probe,
9f9a12f8 7526 .remove = e1000_remove,
f36bb6ca
BA		 7527 .driver = {
7528 .pm = &e1000_pm_ops,
7529 },
bc7f75fa
AK		 7530 .shutdown = e1000_shutdown,
7531 .err_handler = &e1000_err_handler
7532};
7533
7534/**
7535 * e1000_init_module - Driver Registration Routine
7536 *
7537 * e1000_init_module is the first routine called when the driver is
7538 * loaded. All it does is register with the PCI subsystem.
7539 **/
7540static int __init e1000_init_module(void)
7541{
8544b9f7
BA		 7542 pr_info("Intel(R) PRO/1000 Network Driver - %s\n",
7543 e1000e_driver_version);
529498cd 7544 pr_info("Copyright(c) 1999 - 2015 Intel Corporation.\n");
53ec5498 7545
5a5e889c 7546 return pci_register_driver(&e1000_driver);
bc7f75fa
AK		 7547}
7548module_init(e1000_init_module);
7549
7550/**
7551 * e1000_exit_module - Driver Exit Cleanup Routine
7552 *
7553 * e1000_exit_module is called just before the driver is removed
7554 * from memory.
7555 **/
7556static void __exit e1000_exit_module(void)
7557{
7558 pci_unregister_driver(&e1000_driver);
7559}
7560module_exit(e1000_exit_module);
7561
bc7f75fa
AK		 7562MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
7563MODULE_DESCRIPTION("Intel(R) PRO/1000 Network Driver");
7564MODULE_LICENSE("GPL");
7565MODULE_VERSION(DRV_VERSION);
7566
06c24b91 7567/* netdev.c */
Linux 6.x block layer and io_uring tree(s)