Commit | Line | Data |
---|---|---|
ae06c70b | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
51dce24b | 2 | /* Copyright(c) 1999 - 2018 Intel Corporation. */ |
1b41db37 BA |
3 | |
4 | #ifndef _E1000E_ICH8LAN_H_ | |
5 | #define _E1000E_ICH8LAN_H_ | |
6 | ||
7 | #define ICH_FLASH_GFPREG 0x0000 | |
8 | #define ICH_FLASH_HSFSTS 0x0004 | |
9 | #define ICH_FLASH_HSFCTL 0x0006 | |
10 | #define ICH_FLASH_FADDR 0x0008 | |
11 | #define ICH_FLASH_FDATA0 0x0010 | |
12 | #define ICH_FLASH_PR0 0x0074 | |
13 | ||
14 | /* Requires up to 10 seconds when MNG might be accessing part. */ | |
15 | #define ICH_FLASH_READ_COMMAND_TIMEOUT 10000000 | |
16 | #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 | |
17 | #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 | |
18 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF | |
19 | #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 | |
20 | ||
21 | #define ICH_CYCLE_READ 0 | |
22 | #define ICH_CYCLE_WRITE 2 | |
23 | #define ICH_CYCLE_ERASE 3 | |
24 | ||
25 | #define FLASH_GFPREG_BASE_MASK 0x1FFF | |
26 | #define FLASH_SECTOR_ADDR_SHIFT 12 | |
27 | ||
28 | #define ICH_FLASH_SEG_SIZE_256 256 | |
29 | #define ICH_FLASH_SEG_SIZE_4K 4096 | |
30 | #define ICH_FLASH_SEG_SIZE_8K 8192 | |
31 | #define ICH_FLASH_SEG_SIZE_64K 65536 | |
32 | ||
33 | #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ | |
34 | /* FW established a valid mode */ | |
35 | #define E1000_ICH_FWSM_FW_VALID 0x00008000 | |
36 | #define E1000_ICH_FWSM_PCIM2PCI 0x01000000 /* ME PCIm-to-PCI active */ | |
37 | #define E1000_ICH_FWSM_PCIM2PCI_COUNT 2000 | |
38 | ||
39 | #define E1000_ICH_MNG_IAMT_MODE 0x2 | |
40 | ||
41 | #define E1000_FWSM_WLOCK_MAC_MASK 0x0380 | |
42 | #define E1000_FWSM_WLOCK_MAC_SHIFT 7 | |
74f350ee | 43 | #define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */ |
ef407b86 | 44 | #define E1000_EXFWSM_DPG_EXIT_DONE 0x00000001 |
1b41db37 BA |
45 | |
46 | /* Shared Receive Address Registers */ | |
47 | #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) | |
48 | #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) | |
49 | ||
74f350ee | 50 | #define E1000_H2ME 0x05B50 /* Host to ME */ |
3e55d231 SN |
51 | #define E1000_H2ME_START_DPG 0x00000001 /* indicate the ME of DPG */ |
52 | #define E1000_H2ME_EXIT_DPG 0x00000002 /* indicate the ME exit DPG */ | |
74f350ee DE |
53 | #define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */ |
54 | #define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */ | |
55 | ||
1b41db37 BA |
56 | #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ |
57 | (ID_LED_OFF1_OFF2 << 8) | \ | |
58 | (ID_LED_OFF1_ON2 << 4) | \ | |
59 | (ID_LED_DEF1_DEF2)) | |
60 | ||
942c7112 JK |
61 | #define E1000_ICH_NVM_SIG_WORD 0x13u |
62 | #define E1000_ICH_NVM_SIG_MASK 0xC000u | |
63 | #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0u | |
64 | #define E1000_ICH_NVM_SIG_VALUE 0x80u | |
1b41db37 BA |
65 | |
66 | #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 | |
67 | ||
74f350ee DE |
68 | /* FEXT register bit definition */ |
69 | #define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004 | |
70 | ||
1b41db37 BA |
71 | #define E1000_FEXTNVM_SW_CONFIG 1 |
72 | #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */ | |
73 | ||
74 | #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 | |
75 | #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 | |
76 | ||
77 | #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 | |
78 | #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 | |
79 | #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 | |
80 | ||
e08f626b | 81 | #define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 |
e0236ad9 | 82 | #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200 |
79849ebc DE |
83 | #define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000 |
84 | /* bit for disabling packet buffer read */ | |
85 | #define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000 | |
ec945cfb | 86 | #define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004 |
74f350ee | 87 | #define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020 |
ec945cfb YL |
88 | #define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800 |
89 | #define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000 | |
90 | #define E1000_FEXTNVM11_DISABLE_PB_READ 0x00000200 | |
ad851fbb YL |
91 | #define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000 |
92 | ||
93 | /* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */ | |
d5828915 | 94 | #define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000 |
74f350ee | 95 | |
79849ebc DE |
96 | #define K1_ENTRY_LATENCY 0 |
97 | #define K1_MIN_TIME 1 | |
98 | #define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field */ | |
99 | #define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs */ | |
100 | #define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */ | |
c0f4b163 SN |
101 | #define E1000_TARC0_CB_MULTIQ_3_REQ 0x30000000 |
102 | #define E1000_TARC0_CB_MULTIQ_2_REQ 0x20000000 | |
1b41db37 BA |
103 | #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL |
104 | ||
105 | #define E1000_ICH_RAR_ENTRIES 7 | |
96dee024 | 106 | #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ |
1b41db37 BA |
107 | #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ |
108 | ||
109 | #define PHY_PAGE_SHIFT 5 | |
110 | #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ | |
111 | ((reg) & MAX_PHY_REG_ADDRESS)) | |
112 | #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ | |
113 | #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ | |
114 | ||
115 | #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 | |
116 | #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 | |
117 | #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 | |
118 | ||
119 | /* PHY Wakeup Registers and defines */ | |
120 | #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17) | |
121 | #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0) | |
122 | #define BM_WUC PHY_REG(BM_WUC_PAGE, 1) | |
123 | #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2) | |
124 | #define BM_WUS PHY_REG(BM_WUC_PAGE, 3) | |
125 | #define BM_RAR_L(_i) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2))) | |
126 | #define BM_RAR_M(_i) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2))) | |
127 | #define BM_RAR_H(_i) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2))) | |
128 | #define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2))) | |
129 | #define BM_MTA(_i) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1))) | |
130 | ||
131 | #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */ | |
132 | #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */ | |
133 | #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */ | |
134 | #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */ | |
135 | #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */ | |
136 | #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */ | |
137 | #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */ | |
138 | ||
139 | #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ | |
140 | #define HV_MUX_DATA_CTRL PHY_REG(776, 16) | |
141 | #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 | |
142 | #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 | |
143 | #define HV_STATS_PAGE 778 | |
144 | /* Half-duplex collision counts */ | |
145 | #define HV_SCC_UPPER PHY_REG(HV_STATS_PAGE, 16) /* Single Collision */ | |
146 | #define HV_SCC_LOWER PHY_REG(HV_STATS_PAGE, 17) | |
147 | #define HV_ECOL_UPPER PHY_REG(HV_STATS_PAGE, 18) /* Excessive Coll. */ | |
148 | #define HV_ECOL_LOWER PHY_REG(HV_STATS_PAGE, 19) | |
149 | #define HV_MCC_UPPER PHY_REG(HV_STATS_PAGE, 20) /* Multiple Collision */ | |
150 | #define HV_MCC_LOWER PHY_REG(HV_STATS_PAGE, 21) | |
151 | #define HV_LATECOL_UPPER PHY_REG(HV_STATS_PAGE, 23) /* Late Collision */ | |
152 | #define HV_LATECOL_LOWER PHY_REG(HV_STATS_PAGE, 24) | |
153 | #define HV_COLC_UPPER PHY_REG(HV_STATS_PAGE, 25) /* Collision */ | |
154 | #define HV_COLC_LOWER PHY_REG(HV_STATS_PAGE, 26) | |
155 | #define HV_DC_UPPER PHY_REG(HV_STATS_PAGE, 27) /* Defer Count */ | |
156 | #define HV_DC_LOWER PHY_REG(HV_STATS_PAGE, 28) | |
157 | #define HV_TNCRS_UPPER PHY_REG(HV_STATS_PAGE, 29) /* Tx with no CRS */ | |
158 | #define HV_TNCRS_LOWER PHY_REG(HV_STATS_PAGE, 30) | |
159 | ||
160 | #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ | |
161 | ||
162 | #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ | |
163 | #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ | |
164 | ||
165 | /* SMBus Control Phy Register */ | |
166 | #define CV_SMB_CTRL PHY_REG(769, 23) | |
167 | #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 | |
168 | ||
74f350ee DE |
169 | /* I218 Ultra Low Power Configuration 1 Register */ |
170 | #define I218_ULP_CONFIG1 PHY_REG(779, 16) | |
171 | #define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */ | |
172 | #define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */ | |
173 | #define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */ | |
174 | #define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */ | |
175 | #define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */ | |
176 | #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */ | |
c5c6d077 RA |
177 | /* enable ULP even if when phy powered down via lanphypc */ |
178 | #define I218_ULP_CONFIG1_EN_ULP_LANPHYPC 0x0400 | |
179 | /* disable clear of sticky ULP on PERST */ | |
180 | #define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800 | |
74f350ee DE |
181 | #define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */ |
182 | ||
1b41db37 BA |
183 | /* SMBus Address Phy Register */ |
184 | #define HV_SMB_ADDR PHY_REG(768, 26) | |
185 | #define HV_SMB_ADDR_MASK 0x007F | |
186 | #define HV_SMB_ADDR_PEC_EN 0x0200 | |
187 | #define HV_SMB_ADDR_VALID 0x0080 | |
188 | #define HV_SMB_ADDR_FREQ_MASK 0x1100 | |
189 | #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8 | |
190 | #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 | |
191 | ||
192 | /* Strapping Option Register - RO */ | |
193 | #define E1000_STRAP 0x0000C | |
194 | #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 | |
195 | #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 | |
196 | #define E1000_STRAP_SMT_FREQ_MASK 0x00003000 | |
197 | #define E1000_STRAP_SMT_FREQ_SHIFT 12 | |
198 | ||
199 | /* OEM Bits Phy Register */ | |
200 | #define HV_OEM_BITS PHY_REG(768, 25) | |
201 | #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ | |
202 | #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ | |
203 | #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ | |
204 | ||
205 | /* KMRN Mode Control */ | |
206 | #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) | |
207 | #define HV_KMRN_MDIO_SLOW 0x0400 | |
208 | ||
209 | /* KMRN FIFO Control and Status */ | |
210 | #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) | |
211 | #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 | |
212 | #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 | |
213 | ||
214 | /* PHY Power Management Control */ | |
215 | #define HV_PM_CTRL PHY_REG(770, 17) | |
e5e9a2ec | 216 | #define HV_PM_CTRL_K1_CLK_REQ 0x200 |
74f350ee | 217 | #define HV_PM_CTRL_K1_ENABLE 0x4000 |
1b41db37 | 218 | |
74f31299 RA |
219 | #define I217_PLL_CLOCK_GATE_REG PHY_REG(772, 28) |
220 | #define I217_PLL_CLOCK_GATE_MASK 0x07FF | |
221 | ||
1b41db37 BA |
222 | #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in ms */ |
223 | ||
e0236ad9 BA |
224 | /* Inband Control */ |
225 | #define I217_INBAND_CTRL PHY_REG(770, 18) | |
226 | #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00 | |
227 | #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8 | |
228 | ||
b4c1e6bf DE |
229 | /* Low Power Idle GPIO Control */ |
230 | #define I217_LPI_GPIO_CTRL PHY_REG(772, 18) | |
231 | #define I217_LPI_GPIO_CTRL_AUTO_EN_LPI 0x0800 | |
232 | ||
1b41db37 BA |
233 | /* PHY Low Power Idle Control */ |
234 | #define I82579_LPI_CTRL PHY_REG(772, 20) | |
235 | #define I82579_LPI_CTRL_100_ENABLE 0x2000 | |
236 | #define I82579_LPI_CTRL_1000_ENABLE 0x4000 | |
237 | #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 | |
238 | #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 | |
239 | ||
240 | /* Extended Management Interface (EMI) Registers */ | |
241 | #define I82579_EMI_ADDR 0x10 | |
242 | #define I82579_EMI_DATA 0x11 | |
243 | #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ | |
244 | #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ | |
245 | #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ | |
246 | #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ | |
772d05c5 | 247 | #define I82579_RX_CONFIG 0x3412 /* Receive configuration */ |
7142a55c | 248 | #define I82579_LPI_PLL_SHUT 0x4412 /* LPI PLL Shut Enable */ |
d495bcb8 | 249 | #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */ |
1b41db37 BA |
250 | #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ |
251 | #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ | |
252 | #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ | |
253 | #define I82579_EEE_100_SUPPORTED (1 << 1) /* 100BaseTx EEE */ | |
254 | #define I82579_EEE_1000_SUPPORTED (1 << 2) /* 1000BaseTx EEE */ | |
7142a55c | 255 | #define I82579_LPI_100_PLL_SHUT (1 << 2) /* 100M LPI PLL Shut Enabled */ |
1b41db37 BA |
256 | #define I217_EEE_PCS_STATUS 0x9401 /* IEEE MMD Register 3.1 */ |
257 | #define I217_EEE_CAPABILITY 0x8000 /* IEEE MMD Register 3.20 */ | |
258 | #define I217_EEE_ADVERTISEMENT 0x8001 /* IEEE MMD Register 7.60 */ | |
259 | #define I217_EEE_LP_ABILITY 0x8002 /* IEEE MMD Register 7.61 */ | |
fbb9ab10 | 260 | #define I217_RX_CONFIG 0xB20C /* Receive configuration */ |
1b41db37 BA |
261 | |
262 | #define E1000_EEE_RX_LPI_RCVD 0x0400 /* Tx LP idle received */ | |
263 | #define E1000_EEE_TX_LPI_RCVD 0x0800 /* Rx LP idle received */ | |
264 | ||
265 | /* Intel Rapid Start Technology Support */ | |
266 | #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) | |
267 | #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 | |
268 | #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28) | |
269 | #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000 | |
270 | #define I217_CGFREG PHY_REG(772, 29) | |
271 | #define I217_CGFREG_ENABLE_MTA_RESET 0x0002 | |
272 | #define I217_MEMPWR PHY_REG(772, 26) | |
273 | #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 | |
274 | ||
275 | /* Receive Address Initial CRC Calculation */ | |
276 | #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) | |
277 | ||
278 | /* Latency Tolerance Reporting */ | |
279 | #define E1000_LTRV 0x000F8 | |
44a13a5d | 280 | #define E1000_LTRV_VALUE_MASK 0x000003FF |
1b41db37 BA |
281 | #define E1000_LTRV_SCALE_MAX 5 |
282 | #define E1000_LTRV_SCALE_FACTOR 5 | |
44a13a5d SN |
283 | #define E1000_LTRV_SCALE_SHIFT 10 |
284 | #define E1000_LTRV_SCALE_MASK 0x00001C00 | |
1b41db37 BA |
285 | #define E1000_LTRV_REQ_SHIFT 15 |
286 | #define E1000_LTRV_NOSNOOP_SHIFT 16 | |
287 | #define E1000_LTRV_SEND (1 << 30) | |
288 | ||
289 | /* Proprietary Latency Tolerance Reporting PCI Capability */ | |
290 | #define E1000_PCI_LTR_CAP_LPT 0xA8 | |
291 | ||
639e298f SN |
292 | /* Don't gate wake DMA clock */ |
293 | #define E1000_FFLT_DBG_DONT_GATE_WAKE_DMA_CLK 0x1000 | |
294 | ||
1b41db37 BA |
295 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw); |
296 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, | |
297 | bool state); | |
298 | void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); | |
299 | void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw); | |
300 | void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw); | |
301 | void e1000_resume_workarounds_pchlan(struct e1000_hw *hw); | |
302 | s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); | |
303 | void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); | |
304 | s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); | |
305 | s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); | |
d495bcb8 | 306 | s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data); |
a03206ed | 307 | s32 e1000_set_eee_pchlan(struct e1000_hw *hw); |
74f350ee | 308 | s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx); |
1b41db37 | 309 | #endif /* _E1000E_ICH8LAN_H_ */ |