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bc7f75fa AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel PRO/1000 Linux driver | |
f5e261e6 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
bc7f75fa AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
23 | Linux NICS <linux.nics@intel.com> | |
24 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
25 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
26 | ||
27 | *******************************************************************************/ | |
28 | ||
e921eb1a | 29 | /* 82562G 10/100 Network Connection |
bc7f75fa AK |
30 | * 82562G-2 10/100 Network Connection |
31 | * 82562GT 10/100 Network Connection | |
32 | * 82562GT-2 10/100 Network Connection | |
33 | * 82562V 10/100 Network Connection | |
34 | * 82562V-2 10/100 Network Connection | |
35 | * 82566DC-2 Gigabit Network Connection | |
36 | * 82566DC Gigabit Network Connection | |
37 | * 82566DM-2 Gigabit Network Connection | |
38 | * 82566DM Gigabit Network Connection | |
39 | * 82566MC Gigabit Network Connection | |
40 | * 82566MM Gigabit Network Connection | |
97ac8cae BA |
41 | * 82567LM Gigabit Network Connection |
42 | * 82567LF Gigabit Network Connection | |
1605927f | 43 | * 82567V Gigabit Network Connection |
97ac8cae BA |
44 | * 82567LM-2 Gigabit Network Connection |
45 | * 82567LF-2 Gigabit Network Connection | |
46 | * 82567V-2 Gigabit Network Connection | |
f4187b56 BA |
47 | * 82567LF-3 Gigabit Network Connection |
48 | * 82567LM-3 Gigabit Network Connection | |
2f15f9d6 | 49 | * 82567LM-4 Gigabit Network Connection |
a4f58f54 BA |
50 | * 82577LM Gigabit Network Connection |
51 | * 82577LC Gigabit Network Connection | |
52 | * 82578DM Gigabit Network Connection | |
53 | * 82578DC Gigabit Network Connection | |
d3738bb8 BA |
54 | * 82579LM Gigabit Network Connection |
55 | * 82579V Gigabit Network Connection | |
bc7f75fa AK |
56 | */ |
57 | ||
bc7f75fa AK |
58 | #include "e1000.h" |
59 | ||
60 | #define ICH_FLASH_GFPREG 0x0000 | |
61 | #define ICH_FLASH_HSFSTS 0x0004 | |
62 | #define ICH_FLASH_HSFCTL 0x0006 | |
63 | #define ICH_FLASH_FADDR 0x0008 | |
64 | #define ICH_FLASH_FDATA0 0x0010 | |
4a770358 | 65 | #define ICH_FLASH_PR0 0x0074 |
bc7f75fa AK |
66 | |
67 | #define ICH_FLASH_READ_COMMAND_TIMEOUT 500 | |
68 | #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500 | |
69 | #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000 | |
70 | #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF | |
71 | #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 | |
72 | ||
73 | #define ICH_CYCLE_READ 0 | |
74 | #define ICH_CYCLE_WRITE 2 | |
75 | #define ICH_CYCLE_ERASE 3 | |
76 | ||
77 | #define FLASH_GFPREG_BASE_MASK 0x1FFF | |
78 | #define FLASH_SECTOR_ADDR_SHIFT 12 | |
79 | ||
80 | #define ICH_FLASH_SEG_SIZE_256 256 | |
81 | #define ICH_FLASH_SEG_SIZE_4K 4096 | |
82 | #define ICH_FLASH_SEG_SIZE_8K 8192 | |
83 | #define ICH_FLASH_SEG_SIZE_64K 65536 | |
84 | ||
85 | ||
86 | #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */ | |
6dfaa769 BA |
87 | /* FW established a valid mode */ |
88 | #define E1000_ICH_FWSM_FW_VALID 0x00008000 | |
bc7f75fa AK |
89 | |
90 | #define E1000_ICH_MNG_IAMT_MODE 0x2 | |
91 | ||
92 | #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ | |
93 | (ID_LED_DEF1_OFF2 << 8) | \ | |
94 | (ID_LED_DEF1_ON2 << 4) | \ | |
95 | (ID_LED_DEF1_DEF2)) | |
96 | ||
97 | #define E1000_ICH_NVM_SIG_WORD 0x13 | |
98 | #define E1000_ICH_NVM_SIG_MASK 0xC000 | |
e243455d BA |
99 | #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 |
100 | #define E1000_ICH_NVM_SIG_VALUE 0x80 | |
bc7f75fa AK |
101 | |
102 | #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 | |
103 | ||
104 | #define E1000_FEXTNVM_SW_CONFIG 1 | |
105 | #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ | |
106 | ||
62bc813e BA |
107 | #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 |
108 | #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 | |
109 | ||
831bd2e6 BA |
110 | #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 |
111 | #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 | |
112 | #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 | |
113 | ||
bc7f75fa AK |
114 | #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL |
115 | ||
116 | #define E1000_ICH_RAR_ENTRIES 7 | |
69e1e019 | 117 | #define E1000_PCH2_RAR_ENTRIES 5 /* RAR[0], SHRA[0-3] */ |
2fbe4526 | 118 | #define E1000_PCH_LPT_RAR_ENTRIES 12 /* RAR[0], SHRA[0-10] */ |
bc7f75fa AK |
119 | |
120 | #define PHY_PAGE_SHIFT 5 | |
121 | #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ | |
122 | ((reg) & MAX_PHY_REG_ADDRESS)) | |
123 | #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */ | |
124 | #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */ | |
125 | ||
126 | #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 | |
127 | #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300 | |
128 | #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 | |
129 | ||
a4f58f54 BA |
130 | #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */ |
131 | ||
53ac5a88 BA |
132 | #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */ |
133 | ||
2fbe4526 BA |
134 | /* SMBus Control Phy Register */ |
135 | #define CV_SMB_CTRL PHY_REG(769, 23) | |
136 | #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 | |
137 | ||
f523d211 BA |
138 | /* SMBus Address Phy Register */ |
139 | #define HV_SMB_ADDR PHY_REG(768, 26) | |
8395ae83 | 140 | #define HV_SMB_ADDR_MASK 0x007F |
f523d211 BA |
141 | #define HV_SMB_ADDR_PEC_EN 0x0200 |
142 | #define HV_SMB_ADDR_VALID 0x0080 | |
2fbe4526 BA |
143 | #define HV_SMB_ADDR_FREQ_MASK 0x1100 |
144 | #define HV_SMB_ADDR_FREQ_LOW_SHIFT 8 | |
145 | #define HV_SMB_ADDR_FREQ_HIGH_SHIFT 12 | |
f523d211 | 146 | |
d3738bb8 BA |
147 | /* PHY Power Management Control */ |
148 | #define HV_PM_CTRL PHY_REG(770, 17) | |
36ceeb43 | 149 | #define HV_PM_CTRL_PLL_STOP_IN_K1_GIGA 0x100 |
d3738bb8 | 150 | |
2fbe4526 | 151 | /* Intel Rapid Start Technology Support */ |
6d7407bf | 152 | #define I217_PROXY_CTRL BM_PHY_REG(BM_WUC_PAGE, 70) |
2fbe4526 BA |
153 | #define I217_PROXY_CTRL_AUTO_DISABLE 0x0080 |
154 | #define I217_SxCTRL PHY_REG(BM_PORT_CTRL_PAGE, 28) | |
6d7407bf | 155 | #define I217_SxCTRL_ENABLE_LPI_RESET 0x1000 |
2fbe4526 | 156 | #define I217_CGFREG PHY_REG(772, 29) |
6d7407bf | 157 | #define I217_CGFREG_ENABLE_MTA_RESET 0x0002 |
2fbe4526 | 158 | #define I217_MEMPWR PHY_REG(772, 26) |
6d7407bf | 159 | #define I217_MEMPWR_DISABLE_SMB_RELEASE 0x0010 |
1effb45c | 160 | |
f523d211 BA |
161 | /* Strapping Option Register - RO */ |
162 | #define E1000_STRAP 0x0000C | |
163 | #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 | |
164 | #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17 | |
2fbe4526 BA |
165 | #define E1000_STRAP_SMT_FREQ_MASK 0x00003000 |
166 | #define E1000_STRAP_SMT_FREQ_SHIFT 12 | |
f523d211 | 167 | |
fa2ce13c BA |
168 | /* OEM Bits Phy Register */ |
169 | #define HV_OEM_BITS PHY_REG(768, 25) | |
170 | #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ | |
f523d211 | 171 | #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ |
fa2ce13c BA |
172 | #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ |
173 | ||
1d5846b9 BA |
174 | #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ |
175 | #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ | |
176 | ||
fddaa1af BA |
177 | /* KMRN Mode Control */ |
178 | #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) | |
179 | #define HV_KMRN_MDIO_SLOW 0x0400 | |
180 | ||
1d2101a7 BA |
181 | /* KMRN FIFO Control and Status */ |
182 | #define HV_KMRN_FIFO_CTRLSTA PHY_REG(770, 16) | |
183 | #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK 0x7000 | |
184 | #define HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT 12 | |
185 | ||
bc7f75fa AK |
186 | /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ |
187 | /* Offset 04h HSFSTS */ | |
188 | union ich8_hws_flash_status { | |
189 | struct ich8_hsfsts { | |
190 | u16 flcdone :1; /* bit 0 Flash Cycle Done */ | |
191 | u16 flcerr :1; /* bit 1 Flash Cycle Error */ | |
192 | u16 dael :1; /* bit 2 Direct Access error Log */ | |
193 | u16 berasesz :2; /* bit 4:3 Sector Erase Size */ | |
194 | u16 flcinprog :1; /* bit 5 flash cycle in Progress */ | |
195 | u16 reserved1 :2; /* bit 13:6 Reserved */ | |
196 | u16 reserved2 :6; /* bit 13:6 Reserved */ | |
197 | u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */ | |
198 | u16 flockdn :1; /* bit 15 Flash Config Lock-Down */ | |
199 | } hsf_status; | |
200 | u16 regval; | |
201 | }; | |
202 | ||
203 | /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */ | |
204 | /* Offset 06h FLCTL */ | |
205 | union ich8_hws_flash_ctrl { | |
206 | struct ich8_hsflctl { | |
207 | u16 flcgo :1; /* 0 Flash Cycle Go */ | |
208 | u16 flcycle :2; /* 2:1 Flash Cycle */ | |
209 | u16 reserved :5; /* 7:3 Reserved */ | |
210 | u16 fldbcount :2; /* 9:8 Flash Data Byte Count */ | |
211 | u16 flockdn :6; /* 15:10 Reserved */ | |
212 | } hsf_ctrl; | |
213 | u16 regval; | |
214 | }; | |
215 | ||
216 | /* ICH Flash Region Access Permissions */ | |
217 | union ich8_hws_flash_regacc { | |
218 | struct ich8_flracc { | |
219 | u32 grra :8; /* 0:7 GbE region Read Access */ | |
220 | u32 grwa :8; /* 8:15 GbE region Write Access */ | |
221 | u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */ | |
222 | u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */ | |
223 | } hsf_flregacc; | |
224 | u16 regval; | |
225 | }; | |
226 | ||
4a770358 BA |
227 | /* ICH Flash Protected Region */ |
228 | union ich8_flash_protected_range { | |
229 | struct ich8_pr { | |
230 | u32 base:13; /* 0:12 Protected Range Base */ | |
231 | u32 reserved1:2; /* 13:14 Reserved */ | |
232 | u32 rpe:1; /* 15 Read Protection Enable */ | |
233 | u32 limit:13; /* 16:28 Protected Range Limit */ | |
234 | u32 reserved2:2; /* 29:30 Reserved */ | |
235 | u32 wpe:1; /* 31 Write Protection Enable */ | |
236 | } range; | |
237 | u32 regval; | |
238 | }; | |
239 | ||
bc7f75fa AK |
240 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw); |
241 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw); | |
242 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw); | |
bc7f75fa AK |
243 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank); |
244 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |
245 | u32 offset, u8 byte); | |
f4187b56 BA |
246 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, |
247 | u8 *data); | |
bc7f75fa AK |
248 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, |
249 | u16 *data); | |
250 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
251 | u8 size, u16 *data); | |
252 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw); | |
253 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw); | |
f4187b56 | 254 | static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw); |
a4f58f54 BA |
255 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw); |
256 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw); | |
257 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw); | |
258 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw); | |
259 | static s32 e1000_setup_led_pchlan(struct e1000_hw *hw); | |
260 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw); | |
261 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw); | |
262 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw); | |
fa2ce13c | 263 | static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); |
17f208de | 264 | static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw); |
f523d211 | 265 | static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw); |
1d5846b9 | 266 | static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link); |
fddaa1af | 267 | static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw); |
eb7700dc BA |
268 | static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw); |
269 | static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); | |
69e1e019 | 270 | static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); |
2fbe4526 | 271 | static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); |
831bd2e6 | 272 | static s32 e1000_k1_workaround_lv(struct e1000_hw *hw); |
605c82ba | 273 | static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate); |
bc7f75fa AK |
274 | |
275 | static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg) | |
276 | { | |
277 | return readw(hw->flash_address + reg); | |
278 | } | |
279 | ||
280 | static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg) | |
281 | { | |
282 | return readl(hw->flash_address + reg); | |
283 | } | |
284 | ||
285 | static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val) | |
286 | { | |
287 | writew(val, hw->flash_address + reg); | |
288 | } | |
289 | ||
290 | static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val) | |
291 | { | |
292 | writel(val, hw->flash_address + reg); | |
293 | } | |
294 | ||
295 | #define er16flash(reg) __er16flash(hw, (reg)) | |
296 | #define er32flash(reg) __er32flash(hw, (reg)) | |
0e15df49 BA |
297 | #define ew16flash(reg, val) __ew16flash(hw, (reg), (val)) |
298 | #define ew32flash(reg, val) __ew32flash(hw, (reg), (val)) | |
bc7f75fa | 299 | |
cb17aab9 BA |
300 | /** |
301 | * e1000_phy_is_accessible_pchlan - Check if able to access PHY registers | |
302 | * @hw: pointer to the HW structure | |
303 | * | |
304 | * Test access to the PHY registers by reading the PHY ID registers. If | |
305 | * the PHY ID is already known (e.g. resume path) compare it with known ID, | |
306 | * otherwise assume the read PHY ID is correct if it is valid. | |
307 | * | |
308 | * Assumes the sw/fw/hw semaphore is already acquired. | |
309 | **/ | |
310 | static bool e1000_phy_is_accessible_pchlan(struct e1000_hw *hw) | |
99730e4c | 311 | { |
a52359b5 BA |
312 | u16 phy_reg = 0; |
313 | u32 phy_id = 0; | |
314 | s32 ret_val; | |
315 | u16 retry_count; | |
316 | ||
317 | for (retry_count = 0; retry_count < 2; retry_count++) { | |
318 | ret_val = e1e_rphy_locked(hw, PHY_ID1, &phy_reg); | |
319 | if (ret_val || (phy_reg == 0xFFFF)) | |
320 | continue; | |
321 | phy_id = (u32)(phy_reg << 16); | |
322 | ||
323 | ret_val = e1e_rphy_locked(hw, PHY_ID2, &phy_reg); | |
324 | if (ret_val || (phy_reg == 0xFFFF)) { | |
325 | phy_id = 0; | |
326 | continue; | |
327 | } | |
328 | phy_id |= (u32)(phy_reg & PHY_REVISION_MASK); | |
329 | break; | |
330 | } | |
cb17aab9 BA |
331 | |
332 | if (hw->phy.id) { | |
333 | if (hw->phy.id == phy_id) | |
334 | return true; | |
a52359b5 BA |
335 | } else if (phy_id) { |
336 | hw->phy.id = phy_id; | |
337 | hw->phy.revision = (u32)(phy_reg & ~PHY_REVISION_MASK); | |
cb17aab9 BA |
338 | return true; |
339 | } | |
340 | ||
e921eb1a | 341 | /* In case the PHY needs to be in mdio slow mode, |
a52359b5 BA |
342 | * set slow mode and try to get the PHY id again. |
343 | */ | |
344 | hw->phy.ops.release(hw); | |
345 | ret_val = e1000_set_mdio_slow_mode_hv(hw); | |
346 | if (!ret_val) | |
347 | ret_val = e1000e_get_phy_id(hw); | |
348 | hw->phy.ops.acquire(hw); | |
349 | ||
350 | return !ret_val; | |
cb17aab9 BA |
351 | } |
352 | ||
353 | /** | |
354 | * e1000_init_phy_workarounds_pchlan - PHY initialization workarounds | |
355 | * @hw: pointer to the HW structure | |
356 | * | |
357 | * Workarounds/flow necessary for PHY initialization during driver load | |
358 | * and resume paths. | |
359 | **/ | |
360 | static s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) | |
361 | { | |
362 | u32 mac_reg, fwsm = er32(FWSM); | |
363 | s32 ret_val; | |
2fbe4526 | 364 | u16 phy_reg; |
cb17aab9 BA |
365 | |
366 | ret_val = hw->phy.ops.acquire(hw); | |
367 | if (ret_val) { | |
368 | e_dbg("Failed to initialize PHY flow\n"); | |
369 | return ret_val; | |
370 | } | |
371 | ||
e921eb1a | 372 | /* The MAC-PHY interconnect may be in SMBus mode. If the PHY is |
cb17aab9 BA |
373 | * inaccessible and resetting the PHY is not blocked, toggle the |
374 | * LANPHYPC Value bit to force the interconnect to PCIe mode. | |
375 | */ | |
376 | switch (hw->mac.type) { | |
2fbe4526 BA |
377 | case e1000_pch_lpt: |
378 | if (e1000_phy_is_accessible_pchlan(hw)) | |
379 | break; | |
380 | ||
e921eb1a | 381 | /* Before toggling LANPHYPC, see if PHY is accessible by |
2fbe4526 BA |
382 | * forcing MAC to SMBus mode first. |
383 | */ | |
384 | mac_reg = er32(CTRL_EXT); | |
385 | mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS; | |
386 | ew32(CTRL_EXT, mac_reg); | |
387 | ||
388 | /* fall-through */ | |
cb17aab9 | 389 | case e1000_pch2lan: |
e921eb1a | 390 | /* Gate automatic PHY configuration by hardware on |
cb17aab9 BA |
391 | * non-managed 82579 |
392 | */ | |
2fbe4526 BA |
393 | if ((hw->mac.type == e1000_pch2lan) && |
394 | !(fwsm & E1000_ICH_FWSM_FW_VALID)) | |
cb17aab9 BA |
395 | e1000_gate_hw_phy_config_ich8lan(hw, true); |
396 | ||
2fbe4526 BA |
397 | if (e1000_phy_is_accessible_pchlan(hw)) { |
398 | if (hw->mac.type == e1000_pch_lpt) { | |
399 | /* Unforce SMBus mode in PHY */ | |
400 | e1e_rphy_locked(hw, CV_SMB_CTRL, &phy_reg); | |
401 | phy_reg &= ~CV_SMB_CTRL_FORCE_SMBUS; | |
402 | e1e_wphy_locked(hw, CV_SMB_CTRL, phy_reg); | |
403 | ||
404 | /* Unforce SMBus mode in MAC */ | |
405 | mac_reg = er32(CTRL_EXT); | |
406 | mac_reg &= ~E1000_CTRL_EXT_FORCE_SMBUS; | |
407 | ew32(CTRL_EXT, mac_reg); | |
408 | } | |
cb17aab9 | 409 | break; |
2fbe4526 | 410 | } |
cb17aab9 BA |
411 | |
412 | /* fall-through */ | |
413 | case e1000_pchlan: | |
414 | if ((hw->mac.type == e1000_pchlan) && | |
415 | (fwsm & E1000_ICH_FWSM_FW_VALID)) | |
416 | break; | |
417 | ||
418 | if (hw->phy.ops.check_reset_block(hw)) { | |
419 | e_dbg("Required LANPHYPC toggle blocked by ME\n"); | |
420 | break; | |
421 | } | |
422 | ||
423 | e_dbg("Toggling LANPHYPC\n"); | |
424 | ||
425 | /* Set Phy Config Counter to 50msec */ | |
426 | mac_reg = er32(FEXTNVM3); | |
427 | mac_reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; | |
428 | mac_reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; | |
429 | ew32(FEXTNVM3, mac_reg); | |
430 | ||
431 | /* Toggle LANPHYPC Value bit */ | |
432 | mac_reg = er32(CTRL); | |
433 | mac_reg |= E1000_CTRL_LANPHYPC_OVERRIDE; | |
434 | mac_reg &= ~E1000_CTRL_LANPHYPC_VALUE; | |
435 | ew32(CTRL, mac_reg); | |
436 | e1e_flush(); | |
437 | udelay(10); | |
438 | mac_reg &= ~E1000_CTRL_LANPHYPC_OVERRIDE; | |
439 | ew32(CTRL, mac_reg); | |
440 | e1e_flush(); | |
2fbe4526 BA |
441 | if (hw->mac.type < e1000_pch_lpt) { |
442 | msleep(50); | |
443 | } else { | |
444 | u16 count = 20; | |
445 | do { | |
446 | usleep_range(5000, 10000); | |
447 | } while (!(er32(CTRL_EXT) & | |
448 | E1000_CTRL_EXT_LPCD) && count--); | |
449 | } | |
cb17aab9 BA |
450 | break; |
451 | default: | |
452 | break; | |
453 | } | |
454 | ||
455 | hw->phy.ops.release(hw); | |
456 | ||
e921eb1a | 457 | /* Reset the PHY before any access to it. Doing so, ensures |
cb17aab9 BA |
458 | * that the PHY is in a known good state before we read/write |
459 | * PHY registers. The generic reset is sufficient here, | |
460 | * because we haven't determined the PHY type yet. | |
461 | */ | |
462 | ret_val = e1000e_phy_hw_reset_generic(hw); | |
463 | ||
464 | /* Ungate automatic PHY configuration on non-managed 82579 */ | |
465 | if ((hw->mac.type == e1000_pch2lan) && | |
466 | !(fwsm & E1000_ICH_FWSM_FW_VALID)) { | |
467 | usleep_range(10000, 20000); | |
468 | e1000_gate_hw_phy_config_ich8lan(hw, false); | |
469 | } | |
470 | ||
471 | return ret_val; | |
99730e4c BA |
472 | } |
473 | ||
a4f58f54 BA |
474 | /** |
475 | * e1000_init_phy_params_pchlan - Initialize PHY function pointers | |
476 | * @hw: pointer to the HW structure | |
477 | * | |
478 | * Initialize family-specific PHY parameters and function pointers. | |
479 | **/ | |
480 | static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw) | |
481 | { | |
482 | struct e1000_phy_info *phy = &hw->phy; | |
483 | s32 ret_val = 0; | |
484 | ||
485 | phy->addr = 1; | |
486 | phy->reset_delay_us = 100; | |
487 | ||
2b6b168d | 488 | phy->ops.set_page = e1000_set_page_igp; |
94d8186a BA |
489 | phy->ops.read_reg = e1000_read_phy_reg_hv; |
490 | phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked; | |
2b6b168d | 491 | phy->ops.read_reg_page = e1000_read_phy_reg_page_hv; |
fa2ce13c BA |
492 | phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan; |
493 | phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan; | |
94d8186a BA |
494 | phy->ops.write_reg = e1000_write_phy_reg_hv; |
495 | phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked; | |
2b6b168d | 496 | phy->ops.write_reg_page = e1000_write_phy_reg_page_hv; |
17f208de BA |
497 | phy->ops.power_up = e1000_power_up_phy_copper; |
498 | phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; | |
a4f58f54 BA |
499 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; |
500 | ||
cb17aab9 | 501 | phy->id = e1000_phy_unknown; |
627c8a04 | 502 | |
cb17aab9 BA |
503 | ret_val = e1000_init_phy_workarounds_pchlan(hw); |
504 | if (ret_val) | |
505 | return ret_val; | |
605c82ba | 506 | |
cb17aab9 BA |
507 | if (phy->id == e1000_phy_unknown) |
508 | switch (hw->mac.type) { | |
509 | default: | |
510 | ret_val = e1000e_get_phy_id(hw); | |
511 | if (ret_val) | |
512 | return ret_val; | |
513 | if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK)) | |
514 | break; | |
515 | /* fall-through */ | |
516 | case e1000_pch2lan: | |
2fbe4526 | 517 | case e1000_pch_lpt: |
e921eb1a | 518 | /* In case the PHY needs to be in mdio slow mode, |
cb17aab9 BA |
519 | * set slow mode and try to get the PHY id again. |
520 | */ | |
521 | ret_val = e1000_set_mdio_slow_mode_hv(hw); | |
522 | if (ret_val) | |
523 | return ret_val; | |
524 | ret_val = e1000e_get_phy_id(hw); | |
525 | if (ret_val) | |
526 | return ret_val; | |
664dc878 | 527 | break; |
cb17aab9 | 528 | } |
a4f58f54 BA |
529 | phy->type = e1000e_get_phy_type_from_id(phy->id); |
530 | ||
0be84010 BA |
531 | switch (phy->type) { |
532 | case e1000_phy_82577: | |
d3738bb8 | 533 | case e1000_phy_82579: |
2fbe4526 | 534 | case e1000_phy_i217: |
a4f58f54 BA |
535 | phy->ops.check_polarity = e1000_check_polarity_82577; |
536 | phy->ops.force_speed_duplex = | |
6cc7aaed | 537 | e1000_phy_force_speed_duplex_82577; |
0be84010 | 538 | phy->ops.get_cable_length = e1000_get_cable_length_82577; |
94d8186a BA |
539 | phy->ops.get_info = e1000_get_phy_info_82577; |
540 | phy->ops.commit = e1000e_phy_sw_reset; | |
eab50ffb | 541 | break; |
0be84010 BA |
542 | case e1000_phy_82578: |
543 | phy->ops.check_polarity = e1000_check_polarity_m88; | |
544 | phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; | |
545 | phy->ops.get_cable_length = e1000e_get_cable_length_m88; | |
546 | phy->ops.get_info = e1000e_get_phy_info_m88; | |
547 | break; | |
548 | default: | |
549 | ret_val = -E1000_ERR_PHY; | |
550 | break; | |
a4f58f54 BA |
551 | } |
552 | ||
553 | return ret_val; | |
554 | } | |
555 | ||
bc7f75fa AK |
556 | /** |
557 | * e1000_init_phy_params_ich8lan - Initialize PHY function pointers | |
558 | * @hw: pointer to the HW structure | |
559 | * | |
560 | * Initialize family-specific PHY parameters and function pointers. | |
561 | **/ | |
562 | static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw) | |
563 | { | |
564 | struct e1000_phy_info *phy = &hw->phy; | |
565 | s32 ret_val; | |
566 | u16 i = 0; | |
567 | ||
568 | phy->addr = 1; | |
569 | phy->reset_delay_us = 100; | |
570 | ||
17f208de BA |
571 | phy->ops.power_up = e1000_power_up_phy_copper; |
572 | phy->ops.power_down = e1000_power_down_phy_copper_ich8lan; | |
573 | ||
e921eb1a | 574 | /* We may need to do this twice - once for IGP and if that fails, |
97ac8cae BA |
575 | * we'll set BM func pointers and try again |
576 | */ | |
577 | ret_val = e1000e_determine_phy_address(hw); | |
578 | if (ret_val) { | |
94d8186a BA |
579 | phy->ops.write_reg = e1000e_write_phy_reg_bm; |
580 | phy->ops.read_reg = e1000e_read_phy_reg_bm; | |
97ac8cae | 581 | ret_val = e1000e_determine_phy_address(hw); |
9b71b419 BA |
582 | if (ret_val) { |
583 | e_dbg("Cannot determine PHY addr. Erroring out\n"); | |
97ac8cae | 584 | return ret_val; |
9b71b419 | 585 | } |
97ac8cae BA |
586 | } |
587 | ||
bc7f75fa AK |
588 | phy->id = 0; |
589 | while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) && | |
590 | (i++ < 100)) { | |
1bba4386 | 591 | usleep_range(1000, 2000); |
bc7f75fa AK |
592 | ret_val = e1000e_get_phy_id(hw); |
593 | if (ret_val) | |
594 | return ret_val; | |
595 | } | |
596 | ||
597 | /* Verify phy id */ | |
598 | switch (phy->id) { | |
599 | case IGP03E1000_E_PHY_ID: | |
600 | phy->type = e1000_phy_igp_3; | |
601 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
94d8186a BA |
602 | phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked; |
603 | phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked; | |
0be84010 BA |
604 | phy->ops.get_info = e1000e_get_phy_info_igp; |
605 | phy->ops.check_polarity = e1000_check_polarity_igp; | |
606 | phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp; | |
bc7f75fa AK |
607 | break; |
608 | case IFE_E_PHY_ID: | |
609 | case IFE_PLUS_E_PHY_ID: | |
610 | case IFE_C_E_PHY_ID: | |
611 | phy->type = e1000_phy_ife; | |
612 | phy->autoneg_mask = E1000_ALL_NOT_GIG; | |
0be84010 BA |
613 | phy->ops.get_info = e1000_get_phy_info_ife; |
614 | phy->ops.check_polarity = e1000_check_polarity_ife; | |
615 | phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife; | |
bc7f75fa | 616 | break; |
97ac8cae BA |
617 | case BME1000_E_PHY_ID: |
618 | phy->type = e1000_phy_bm; | |
619 | phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; | |
94d8186a BA |
620 | phy->ops.read_reg = e1000e_read_phy_reg_bm; |
621 | phy->ops.write_reg = e1000e_write_phy_reg_bm; | |
622 | phy->ops.commit = e1000e_phy_sw_reset; | |
0be84010 BA |
623 | phy->ops.get_info = e1000e_get_phy_info_m88; |
624 | phy->ops.check_polarity = e1000_check_polarity_m88; | |
625 | phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88; | |
97ac8cae | 626 | break; |
bc7f75fa AK |
627 | default: |
628 | return -E1000_ERR_PHY; | |
629 | break; | |
630 | } | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
635 | /** | |
636 | * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers | |
637 | * @hw: pointer to the HW structure | |
638 | * | |
639 | * Initialize family-specific NVM parameters and function | |
640 | * pointers. | |
641 | **/ | |
642 | static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) | |
643 | { | |
644 | struct e1000_nvm_info *nvm = &hw->nvm; | |
645 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
148675a7 | 646 | u32 gfpreg, sector_base_addr, sector_end_addr; |
bc7f75fa AK |
647 | u16 i; |
648 | ||
ad68076e | 649 | /* Can't read flash registers if the register set isn't mapped. */ |
bc7f75fa | 650 | if (!hw->flash_address) { |
3bb99fe2 | 651 | e_dbg("ERROR: Flash registers not mapped\n"); |
bc7f75fa AK |
652 | return -E1000_ERR_CONFIG; |
653 | } | |
654 | ||
655 | nvm->type = e1000_nvm_flash_sw; | |
656 | ||
657 | gfpreg = er32flash(ICH_FLASH_GFPREG); | |
658 | ||
e921eb1a | 659 | /* sector_X_addr is a "sector"-aligned address (4096 bytes) |
bc7f75fa | 660 | * Add 1 to sector_end_addr since this sector is included in |
ad68076e BA |
661 | * the overall size. |
662 | */ | |
bc7f75fa AK |
663 | sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK; |
664 | sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1; | |
665 | ||
666 | /* flash_base_addr is byte-aligned */ | |
667 | nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT; | |
668 | ||
e921eb1a | 669 | /* find total size of the NVM, then cut in half since the total |
ad68076e BA |
670 | * size represents two separate NVM banks. |
671 | */ | |
bc7f75fa AK |
672 | nvm->flash_bank_size = (sector_end_addr - sector_base_addr) |
673 | << FLASH_SECTOR_ADDR_SHIFT; | |
674 | nvm->flash_bank_size /= 2; | |
675 | /* Adjust to word count */ | |
676 | nvm->flash_bank_size /= sizeof(u16); | |
677 | ||
678 | nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS; | |
679 | ||
680 | /* Clear shadow ram */ | |
681 | for (i = 0; i < nvm->word_size; i++) { | |
564ea9bb | 682 | dev_spec->shadow_ram[i].modified = false; |
bc7f75fa AK |
683 | dev_spec->shadow_ram[i].value = 0xFFFF; |
684 | } | |
685 | ||
686 | return 0; | |
687 | } | |
688 | ||
689 | /** | |
690 | * e1000_init_mac_params_ich8lan - Initialize MAC function pointers | |
691 | * @hw: pointer to the HW structure | |
692 | * | |
693 | * Initialize family-specific MAC parameters and function | |
694 | * pointers. | |
695 | **/ | |
ec34c170 | 696 | static s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) |
bc7f75fa | 697 | { |
bc7f75fa AK |
698 | struct e1000_mac_info *mac = &hw->mac; |
699 | ||
700 | /* Set media type function pointer */ | |
318a94d6 | 701 | hw->phy.media_type = e1000_media_type_copper; |
bc7f75fa AK |
702 | |
703 | /* Set mta register count */ | |
704 | mac->mta_reg_count = 32; | |
705 | /* Set rar entry count */ | |
706 | mac->rar_entry_count = E1000_ICH_RAR_ENTRIES; | |
707 | if (mac->type == e1000_ich8lan) | |
708 | mac->rar_entry_count--; | |
a65a4a0d BA |
709 | /* FWSM register */ |
710 | mac->has_fwsm = true; | |
711 | /* ARC subsystem not supported */ | |
712 | mac->arc_subsystem_valid = false; | |
f464ba87 BA |
713 | /* Adaptive IFS supported */ |
714 | mac->adaptive_ifs = true; | |
bc7f75fa | 715 | |
2fbe4526 | 716 | /* LED and other operations */ |
a4f58f54 BA |
717 | switch (mac->type) { |
718 | case e1000_ich8lan: | |
719 | case e1000_ich9lan: | |
720 | case e1000_ich10lan: | |
eb7700dc BA |
721 | /* check management mode */ |
722 | mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan; | |
a4f58f54 | 723 | /* ID LED init */ |
d1964eb1 | 724 | mac->ops.id_led_init = e1000e_id_led_init_generic; |
dbf80dcb BA |
725 | /* blink LED */ |
726 | mac->ops.blink_led = e1000e_blink_led_generic; | |
a4f58f54 BA |
727 | /* setup LED */ |
728 | mac->ops.setup_led = e1000e_setup_led_generic; | |
729 | /* cleanup LED */ | |
730 | mac->ops.cleanup_led = e1000_cleanup_led_ich8lan; | |
731 | /* turn on/off LED */ | |
732 | mac->ops.led_on = e1000_led_on_ich8lan; | |
733 | mac->ops.led_off = e1000_led_off_ich8lan; | |
734 | break; | |
d3738bb8 | 735 | case e1000_pch2lan: |
69e1e019 BA |
736 | mac->rar_entry_count = E1000_PCH2_RAR_ENTRIES; |
737 | mac->ops.rar_set = e1000_rar_set_pch2lan; | |
738 | /* fall-through */ | |
2fbe4526 | 739 | case e1000_pch_lpt: |
69e1e019 | 740 | case e1000_pchlan: |
eb7700dc BA |
741 | /* check management mode */ |
742 | mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; | |
a4f58f54 BA |
743 | /* ID LED init */ |
744 | mac->ops.id_led_init = e1000_id_led_init_pchlan; | |
745 | /* setup LED */ | |
746 | mac->ops.setup_led = e1000_setup_led_pchlan; | |
747 | /* cleanup LED */ | |
748 | mac->ops.cleanup_led = e1000_cleanup_led_pchlan; | |
749 | /* turn on/off LED */ | |
750 | mac->ops.led_on = e1000_led_on_pchlan; | |
751 | mac->ops.led_off = e1000_led_off_pchlan; | |
752 | break; | |
753 | default: | |
754 | break; | |
755 | } | |
756 | ||
2fbe4526 BA |
757 | if (mac->type == e1000_pch_lpt) { |
758 | mac->rar_entry_count = E1000_PCH_LPT_RAR_ENTRIES; | |
759 | mac->ops.rar_set = e1000_rar_set_pch_lpt; | |
760 | } | |
761 | ||
bc7f75fa AK |
762 | /* Enable PCS Lock-loss workaround for ICH8 */ |
763 | if (mac->type == e1000_ich8lan) | |
564ea9bb | 764 | e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true); |
bc7f75fa | 765 | |
e921eb1a | 766 | /* Gate automatic PHY configuration by hardware on managed |
2fbe4526 BA |
767 | * 82579 and i217 |
768 | */ | |
769 | if ((mac->type == e1000_pch2lan || mac->type == e1000_pch_lpt) && | |
605c82ba BA |
770 | (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) |
771 | e1000_gate_hw_phy_config_ich8lan(hw, true); | |
d3738bb8 | 772 | |
bc7f75fa AK |
773 | return 0; |
774 | } | |
775 | ||
4ddc48a9 BA |
776 | /** |
777 | * __e1000_access_emi_reg_locked - Read/write EMI register | |
778 | * @hw: pointer to the HW structure | |
779 | * @addr: EMI address to program | |
780 | * @data: pointer to value to read/write from/to the EMI address | |
781 | * @read: boolean flag to indicate read or write | |
782 | * | |
783 | * This helper function assumes the SW/FW/HW Semaphore is already acquired. | |
784 | **/ | |
785 | static s32 __e1000_access_emi_reg_locked(struct e1000_hw *hw, u16 address, | |
786 | u16 *data, bool read) | |
787 | { | |
788 | s32 ret_val = 0; | |
789 | ||
790 | ret_val = e1e_wphy_locked(hw, I82579_EMI_ADDR, address); | |
791 | if (ret_val) | |
792 | return ret_val; | |
793 | ||
794 | if (read) | |
795 | ret_val = e1e_rphy_locked(hw, I82579_EMI_DATA, data); | |
796 | else | |
797 | ret_val = e1e_wphy_locked(hw, I82579_EMI_DATA, *data); | |
798 | ||
799 | return ret_val; | |
800 | } | |
801 | ||
802 | /** | |
803 | * e1000_read_emi_reg_locked - Read Extended Management Interface register | |
804 | * @hw: pointer to the HW structure | |
805 | * @addr: EMI address to program | |
806 | * @data: value to be read from the EMI address | |
807 | * | |
808 | * Assumes the SW/FW/HW Semaphore is already acquired. | |
809 | **/ | |
203e4151 | 810 | s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data) |
4ddc48a9 BA |
811 | { |
812 | return __e1000_access_emi_reg_locked(hw, addr, data, true); | |
813 | } | |
814 | ||
815 | /** | |
816 | * e1000_write_emi_reg_locked - Write Extended Management Interface register | |
817 | * @hw: pointer to the HW structure | |
818 | * @addr: EMI address to program | |
819 | * @data: value to be written to the EMI address | |
820 | * | |
821 | * Assumes the SW/FW/HW Semaphore is already acquired. | |
822 | **/ | |
823 | static s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data) | |
824 | { | |
825 | return __e1000_access_emi_reg_locked(hw, addr, &data, false); | |
826 | } | |
827 | ||
e52997f9 BA |
828 | /** |
829 | * e1000_set_eee_pchlan - Enable/disable EEE support | |
830 | * @hw: pointer to the HW structure | |
831 | * | |
3d4d5755 BA |
832 | * Enable/disable EEE based on setting in dev_spec structure, the duplex of |
833 | * the link and the EEE capabilities of the link partner. The LPI Control | |
834 | * register bits will remain set only if/when link is up. | |
e52997f9 BA |
835 | **/ |
836 | static s32 e1000_set_eee_pchlan(struct e1000_hw *hw) | |
837 | { | |
2fbe4526 | 838 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
3d4d5755 BA |
839 | s32 ret_val; |
840 | u16 lpi_ctrl; | |
e52997f9 | 841 | |
2fbe4526 BA |
842 | if ((hw->phy.type != e1000_phy_82579) && |
843 | (hw->phy.type != e1000_phy_i217)) | |
5015e53a | 844 | return 0; |
e52997f9 | 845 | |
3d4d5755 | 846 | ret_val = hw->phy.ops.acquire(hw); |
e52997f9 | 847 | if (ret_val) |
5015e53a | 848 | return ret_val; |
e52997f9 | 849 | |
3d4d5755 | 850 | ret_val = e1e_rphy_locked(hw, I82579_LPI_CTRL, &lpi_ctrl); |
2fbe4526 | 851 | if (ret_val) |
3d4d5755 BA |
852 | goto release; |
853 | ||
854 | /* Clear bits that enable EEE in various speeds */ | |
855 | lpi_ctrl &= ~I82579_LPI_CTRL_ENABLE_MASK; | |
856 | ||
857 | /* Enable EEE if not disabled by user */ | |
858 | if (!dev_spec->eee_disable) { | |
859 | u16 lpa, pcs_status, data; | |
2fbe4526 | 860 | |
2fbe4526 | 861 | /* Save off link partner's EEE ability */ |
3d4d5755 BA |
862 | switch (hw->phy.type) { |
863 | case e1000_phy_82579: | |
864 | lpa = I82579_EEE_LP_ABILITY; | |
865 | pcs_status = I82579_EEE_PCS_STATUS; | |
866 | break; | |
867 | case e1000_phy_i217: | |
868 | lpa = I217_EEE_LP_ABILITY; | |
869 | pcs_status = I217_EEE_PCS_STATUS; | |
870 | break; | |
871 | default: | |
872 | ret_val = -E1000_ERR_PHY; | |
873 | goto release; | |
874 | } | |
875 | ret_val = e1000_read_emi_reg_locked(hw, lpa, | |
4ddc48a9 | 876 | &dev_spec->eee_lp_ability); |
2fbe4526 BA |
877 | if (ret_val) |
878 | goto release; | |
2fbe4526 | 879 | |
3d4d5755 BA |
880 | /* Enable EEE only for speeds in which the link partner is |
881 | * EEE capable. | |
2fbe4526 | 882 | */ |
3d4d5755 BA |
883 | if (dev_spec->eee_lp_ability & I82579_EEE_1000_SUPPORTED) |
884 | lpi_ctrl |= I82579_LPI_CTRL_1000_ENABLE; | |
885 | ||
886 | if (dev_spec->eee_lp_ability & I82579_EEE_100_SUPPORTED) { | |
887 | e1e_rphy_locked(hw, PHY_LP_ABILITY, &data); | |
888 | if (data & NWAY_LPAR_100TX_FD_CAPS) | |
889 | lpi_ctrl |= I82579_LPI_CTRL_100_ENABLE; | |
890 | else | |
891 | /* EEE is not supported in 100Half, so ignore | |
892 | * partner's EEE in 100 ability if full-duplex | |
893 | * is not advertised. | |
894 | */ | |
895 | dev_spec->eee_lp_ability &= | |
896 | ~I82579_EEE_100_SUPPORTED; | |
897 | } | |
898 | ||
899 | /* R/Clr IEEE MMD 3.1 bits 11:10 - Tx/Rx LPI Received */ | |
900 | ret_val = e1000_read_emi_reg_locked(hw, pcs_status, &data); | |
901 | if (ret_val) | |
902 | goto release; | |
2fbe4526 BA |
903 | } |
904 | ||
3d4d5755 BA |
905 | ret_val = e1e_wphy_locked(hw, I82579_LPI_CTRL, lpi_ctrl); |
906 | release: | |
907 | hw->phy.ops.release(hw); | |
908 | ||
909 | return ret_val; | |
e52997f9 BA |
910 | } |
911 | ||
7d3cabbc BA |
912 | /** |
913 | * e1000_check_for_copper_link_ich8lan - Check for link (Copper) | |
914 | * @hw: pointer to the HW structure | |
915 | * | |
916 | * Checks to see of the link status of the hardware has changed. If a | |
917 | * change in link status has been detected, then we read the PHY registers | |
918 | * to get the current speed/duplex if link exists. | |
919 | **/ | |
920 | static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw) | |
921 | { | |
922 | struct e1000_mac_info *mac = &hw->mac; | |
923 | s32 ret_val; | |
924 | bool link; | |
1d2101a7 | 925 | u16 phy_reg; |
7d3cabbc | 926 | |
e921eb1a | 927 | /* We only want to go out to the PHY registers to see if Auto-Neg |
7d3cabbc BA |
928 | * has completed and/or if our link status has changed. The |
929 | * get_link_status flag is set upon receiving a Link Status | |
930 | * Change or Rx Sequence Error interrupt. | |
931 | */ | |
5015e53a BA |
932 | if (!mac->get_link_status) |
933 | return 0; | |
7d3cabbc | 934 | |
e921eb1a | 935 | /* First we want to see if the MII Status Register reports |
7d3cabbc BA |
936 | * link. If so, then we want to get the current speed/duplex |
937 | * of the PHY. | |
938 | */ | |
939 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); | |
940 | if (ret_val) | |
5015e53a | 941 | return ret_val; |
7d3cabbc | 942 | |
1d5846b9 BA |
943 | if (hw->mac.type == e1000_pchlan) { |
944 | ret_val = e1000_k1_gig_workaround_hv(hw, link); | |
945 | if (ret_val) | |
5015e53a | 946 | return ret_val; |
1d5846b9 BA |
947 | } |
948 | ||
2fbe4526 BA |
949 | /* Clear link partner's EEE ability */ |
950 | hw->dev_spec.ich8lan.eee_lp_ability = 0; | |
951 | ||
7d3cabbc | 952 | if (!link) |
5015e53a | 953 | return 0; /* No link detected */ |
7d3cabbc BA |
954 | |
955 | mac->get_link_status = false; | |
956 | ||
1d2101a7 BA |
957 | switch (hw->mac.type) { |
958 | case e1000_pch2lan: | |
831bd2e6 BA |
959 | ret_val = e1000_k1_workaround_lv(hw); |
960 | if (ret_val) | |
5015e53a | 961 | return ret_val; |
1d2101a7 BA |
962 | /* fall-thru */ |
963 | case e1000_pchlan: | |
964 | if (hw->phy.type == e1000_phy_82578) { | |
965 | ret_val = e1000_link_stall_workaround_hv(hw); | |
966 | if (ret_val) | |
5015e53a | 967 | return ret_val; |
1d2101a7 BA |
968 | } |
969 | ||
e921eb1a | 970 | /* Workaround for PCHx parts in half-duplex: |
1d2101a7 BA |
971 | * Set the number of preambles removed from the packet |
972 | * when it is passed from the PHY to the MAC to prevent | |
973 | * the MAC from misinterpreting the packet type. | |
974 | */ | |
975 | e1e_rphy(hw, HV_KMRN_FIFO_CTRLSTA, &phy_reg); | |
976 | phy_reg &= ~HV_KMRN_FIFO_CTRLSTA_PREAMBLE_MASK; | |
977 | ||
978 | if ((er32(STATUS) & E1000_STATUS_FD) != E1000_STATUS_FD) | |
979 | phy_reg |= (1 << HV_KMRN_FIFO_CTRLSTA_PREAMBLE_SHIFT); | |
980 | ||
981 | e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, phy_reg); | |
982 | break; | |
983 | default: | |
984 | break; | |
831bd2e6 BA |
985 | } |
986 | ||
e921eb1a | 987 | /* Check if there was DownShift, must be checked |
7d3cabbc BA |
988 | * immediately after link-up |
989 | */ | |
990 | e1000e_check_downshift(hw); | |
991 | ||
e52997f9 BA |
992 | /* Enable/Disable EEE after link up */ |
993 | ret_val = e1000_set_eee_pchlan(hw); | |
994 | if (ret_val) | |
5015e53a | 995 | return ret_val; |
e52997f9 | 996 | |
e921eb1a | 997 | /* If we are forcing speed/duplex, then we simply return since |
7d3cabbc BA |
998 | * we have already determined whether we have link or not. |
999 | */ | |
5015e53a BA |
1000 | if (!mac->autoneg) |
1001 | return -E1000_ERR_CONFIG; | |
7d3cabbc | 1002 | |
e921eb1a | 1003 | /* Auto-Neg is enabled. Auto Speed Detection takes care |
7d3cabbc BA |
1004 | * of MAC speed/duplex configuration. So we only need to |
1005 | * configure Collision Distance in the MAC. | |
1006 | */ | |
57cde763 | 1007 | mac->ops.config_collision_dist(hw); |
7d3cabbc | 1008 | |
e921eb1a | 1009 | /* Configure Flow Control now that Auto-Neg has completed. |
7d3cabbc BA |
1010 | * First, we need to restore the desired flow control |
1011 | * settings because we may have had to re-autoneg with a | |
1012 | * different link partner. | |
1013 | */ | |
1014 | ret_val = e1000e_config_fc_after_link_up(hw); | |
1015 | if (ret_val) | |
3bb99fe2 | 1016 | e_dbg("Error configuring flow control\n"); |
7d3cabbc | 1017 | |
7d3cabbc BA |
1018 | return ret_val; |
1019 | } | |
1020 | ||
69e3fd8c | 1021 | static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter) |
bc7f75fa AK |
1022 | { |
1023 | struct e1000_hw *hw = &adapter->hw; | |
1024 | s32 rc; | |
1025 | ||
ec34c170 | 1026 | rc = e1000_init_mac_params_ich8lan(hw); |
bc7f75fa AK |
1027 | if (rc) |
1028 | return rc; | |
1029 | ||
1030 | rc = e1000_init_nvm_params_ich8lan(hw); | |
1031 | if (rc) | |
1032 | return rc; | |
1033 | ||
d3738bb8 BA |
1034 | switch (hw->mac.type) { |
1035 | case e1000_ich8lan: | |
1036 | case e1000_ich9lan: | |
1037 | case e1000_ich10lan: | |
a4f58f54 | 1038 | rc = e1000_init_phy_params_ich8lan(hw); |
d3738bb8 BA |
1039 | break; |
1040 | case e1000_pchlan: | |
1041 | case e1000_pch2lan: | |
2fbe4526 | 1042 | case e1000_pch_lpt: |
d3738bb8 BA |
1043 | rc = e1000_init_phy_params_pchlan(hw); |
1044 | break; | |
1045 | default: | |
1046 | break; | |
1047 | } | |
bc7f75fa AK |
1048 | if (rc) |
1049 | return rc; | |
1050 | ||
e921eb1a | 1051 | /* Disable Jumbo Frame support on parts with Intel 10/100 PHY or |
23e4f061 BA |
1052 | * on parts with MACsec enabled in NVM (reflected in CTRL_EXT). |
1053 | */ | |
1054 | if ((adapter->hw.phy.type == e1000_phy_ife) || | |
1055 | ((adapter->hw.mac.type >= e1000_pch2lan) && | |
1056 | (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) { | |
2adc55c9 BA |
1057 | adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES; |
1058 | adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN; | |
dbf80dcb BA |
1059 | |
1060 | hw->mac.ops.blink_led = NULL; | |
2adc55c9 BA |
1061 | } |
1062 | ||
bc7f75fa | 1063 | if ((adapter->hw.mac.type == e1000_ich8lan) && |
462d5994 | 1064 | (adapter->hw.phy.type != e1000_phy_ife)) |
bc7f75fa AK |
1065 | adapter->flags |= FLAG_LSC_GIG_SPEED_DROP; |
1066 | ||
c6e7f51e BA |
1067 | /* Enable workaround for 82579 w/ ME enabled */ |
1068 | if ((adapter->hw.mac.type == e1000_pch2lan) && | |
1069 | (er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) | |
1070 | adapter->flags2 |= FLAG2_PCIM2PCI_ARBITER_WA; | |
1071 | ||
5a86f28f BA |
1072 | /* Disable EEE by default until IEEE802.3az spec is finalized */ |
1073 | if (adapter->flags2 & FLAG2_HAS_EEE) | |
1074 | adapter->hw.dev_spec.ich8lan.eee_disable = true; | |
1075 | ||
bc7f75fa AK |
1076 | return 0; |
1077 | } | |
1078 | ||
717d438d | 1079 | static DEFINE_MUTEX(nvm_mutex); |
717d438d | 1080 | |
ca15df58 BA |
1081 | /** |
1082 | * e1000_acquire_nvm_ich8lan - Acquire NVM mutex | |
1083 | * @hw: pointer to the HW structure | |
1084 | * | |
1085 | * Acquires the mutex for performing NVM operations. | |
1086 | **/ | |
1087 | static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw) | |
1088 | { | |
1089 | mutex_lock(&nvm_mutex); | |
1090 | ||
1091 | return 0; | |
1092 | } | |
1093 | ||
1094 | /** | |
1095 | * e1000_release_nvm_ich8lan - Release NVM mutex | |
1096 | * @hw: pointer to the HW structure | |
1097 | * | |
1098 | * Releases the mutex used while performing NVM operations. | |
1099 | **/ | |
1100 | static void e1000_release_nvm_ich8lan(struct e1000_hw *hw) | |
1101 | { | |
1102 | mutex_unlock(&nvm_mutex); | |
ca15df58 BA |
1103 | } |
1104 | ||
bc7f75fa AK |
1105 | /** |
1106 | * e1000_acquire_swflag_ich8lan - Acquire software control flag | |
1107 | * @hw: pointer to the HW structure | |
1108 | * | |
ca15df58 BA |
1109 | * Acquires the software control flag for performing PHY and select |
1110 | * MAC CSR accesses. | |
bc7f75fa AK |
1111 | **/ |
1112 | static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw) | |
1113 | { | |
373a88d7 BA |
1114 | u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT; |
1115 | s32 ret_val = 0; | |
bc7f75fa | 1116 | |
a90b412c BA |
1117 | if (test_and_set_bit(__E1000_ACCESS_SHARED_RESOURCE, |
1118 | &hw->adapter->state)) { | |
34c9ef8b | 1119 | e_dbg("contention for Phy access\n"); |
a90b412c BA |
1120 | return -E1000_ERR_PHY; |
1121 | } | |
717d438d | 1122 | |
bc7f75fa AK |
1123 | while (timeout) { |
1124 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
373a88d7 BA |
1125 | if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)) |
1126 | break; | |
bc7f75fa | 1127 | |
373a88d7 BA |
1128 | mdelay(1); |
1129 | timeout--; | |
1130 | } | |
1131 | ||
1132 | if (!timeout) { | |
a90b412c | 1133 | e_dbg("SW has already locked the resource.\n"); |
373a88d7 BA |
1134 | ret_val = -E1000_ERR_CONFIG; |
1135 | goto out; | |
1136 | } | |
1137 | ||
53ac5a88 | 1138 | timeout = SW_FLAG_TIMEOUT; |
373a88d7 BA |
1139 | |
1140 | extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG; | |
1141 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
1142 | ||
1143 | while (timeout) { | |
1144 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
1145 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) | |
1146 | break; | |
a4f58f54 | 1147 | |
bc7f75fa AK |
1148 | mdelay(1); |
1149 | timeout--; | |
1150 | } | |
1151 | ||
1152 | if (!timeout) { | |
434f1392 | 1153 | e_dbg("Failed to acquire the semaphore, FW or HW has it: FWSM=0x%8.8x EXTCNF_CTRL=0x%8.8x)\n", |
a90b412c | 1154 | er32(FWSM), extcnf_ctrl); |
2e2e8d53 BA |
1155 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; |
1156 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
373a88d7 BA |
1157 | ret_val = -E1000_ERR_CONFIG; |
1158 | goto out; | |
bc7f75fa AK |
1159 | } |
1160 | ||
373a88d7 BA |
1161 | out: |
1162 | if (ret_val) | |
a90b412c | 1163 | clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); |
373a88d7 BA |
1164 | |
1165 | return ret_val; | |
bc7f75fa AK |
1166 | } |
1167 | ||
1168 | /** | |
1169 | * e1000_release_swflag_ich8lan - Release software control flag | |
1170 | * @hw: pointer to the HW structure | |
1171 | * | |
ca15df58 BA |
1172 | * Releases the software control flag for performing PHY and select |
1173 | * MAC CSR accesses. | |
bc7f75fa AK |
1174 | **/ |
1175 | static void e1000_release_swflag_ich8lan(struct e1000_hw *hw) | |
1176 | { | |
1177 | u32 extcnf_ctrl; | |
1178 | ||
1179 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
c5caf482 BA |
1180 | |
1181 | if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) { | |
1182 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG; | |
1183 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
1184 | } else { | |
1185 | e_dbg("Semaphore unexpectedly released by sw/fw/hw\n"); | |
1186 | } | |
717d438d | 1187 | |
a90b412c | 1188 | clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); |
bc7f75fa AK |
1189 | } |
1190 | ||
4662e82b BA |
1191 | /** |
1192 | * e1000_check_mng_mode_ich8lan - Checks management mode | |
1193 | * @hw: pointer to the HW structure | |
1194 | * | |
eb7700dc | 1195 | * This checks if the adapter has any manageability enabled. |
4662e82b BA |
1196 | * This is a function pointer entry point only called by read/write |
1197 | * routines for the PHY and NVM parts. | |
1198 | **/ | |
1199 | static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw) | |
1200 | { | |
a708dd88 BA |
1201 | u32 fwsm; |
1202 | ||
1203 | fwsm = er32(FWSM); | |
eb7700dc BA |
1204 | return (fwsm & E1000_ICH_FWSM_FW_VALID) && |
1205 | ((fwsm & E1000_FWSM_MODE_MASK) == | |
1206 | (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); | |
1207 | } | |
4662e82b | 1208 | |
eb7700dc BA |
1209 | /** |
1210 | * e1000_check_mng_mode_pchlan - Checks management mode | |
1211 | * @hw: pointer to the HW structure | |
1212 | * | |
1213 | * This checks if the adapter has iAMT enabled. | |
1214 | * This is a function pointer entry point only called by read/write | |
1215 | * routines for the PHY and NVM parts. | |
1216 | **/ | |
1217 | static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw) | |
1218 | { | |
1219 | u32 fwsm; | |
1220 | ||
1221 | fwsm = er32(FWSM); | |
1222 | return (fwsm & E1000_ICH_FWSM_FW_VALID) && | |
1223 | (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT)); | |
4662e82b BA |
1224 | } |
1225 | ||
69e1e019 BA |
1226 | /** |
1227 | * e1000_rar_set_pch2lan - Set receive address register | |
1228 | * @hw: pointer to the HW structure | |
1229 | * @addr: pointer to the receive address | |
1230 | * @index: receive address array register | |
1231 | * | |
1232 | * Sets the receive address array register at index to the address passed | |
1233 | * in by addr. For 82579, RAR[0] is the base address register that is to | |
1234 | * contain the MAC address but RAR[1-6] are reserved for manageability (ME). | |
1235 | * Use SHRA[0-3] in place of those reserved for ME. | |
1236 | **/ | |
1237 | static void e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index) | |
1238 | { | |
1239 | u32 rar_low, rar_high; | |
1240 | ||
e921eb1a | 1241 | /* HW expects these in little endian so we reverse the byte order |
69e1e019 BA |
1242 | * from network order (big endian) to little endian |
1243 | */ | |
1244 | rar_low = ((u32)addr[0] | | |
1245 | ((u32)addr[1] << 8) | | |
1246 | ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); | |
1247 | ||
1248 | rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); | |
1249 | ||
1250 | /* If MAC address zero, no need to set the AV bit */ | |
1251 | if (rar_low || rar_high) | |
1252 | rar_high |= E1000_RAH_AV; | |
1253 | ||
1254 | if (index == 0) { | |
1255 | ew32(RAL(index), rar_low); | |
1256 | e1e_flush(); | |
1257 | ew32(RAH(index), rar_high); | |
1258 | e1e_flush(); | |
1259 | return; | |
1260 | } | |
1261 | ||
1262 | if (index < hw->mac.rar_entry_count) { | |
1263 | s32 ret_val; | |
1264 | ||
1265 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1266 | if (ret_val) | |
1267 | goto out; | |
1268 | ||
1269 | ew32(SHRAL(index - 1), rar_low); | |
1270 | e1e_flush(); | |
1271 | ew32(SHRAH(index - 1), rar_high); | |
1272 | e1e_flush(); | |
1273 | ||
1274 | e1000_release_swflag_ich8lan(hw); | |
1275 | ||
1276 | /* verify the register updates */ | |
1277 | if ((er32(SHRAL(index - 1)) == rar_low) && | |
1278 | (er32(SHRAH(index - 1)) == rar_high)) | |
1279 | return; | |
1280 | ||
1281 | e_dbg("SHRA[%d] might be locked by ME - FWSM=0x%8.8x\n", | |
1282 | (index - 1), er32(FWSM)); | |
1283 | } | |
1284 | ||
1285 | out: | |
1286 | e_dbg("Failed to write receive address at index %d\n", index); | |
1287 | } | |
1288 | ||
2fbe4526 BA |
1289 | /** |
1290 | * e1000_rar_set_pch_lpt - Set receive address registers | |
1291 | * @hw: pointer to the HW structure | |
1292 | * @addr: pointer to the receive address | |
1293 | * @index: receive address array register | |
1294 | * | |
1295 | * Sets the receive address register array at index to the address passed | |
1296 | * in by addr. For LPT, RAR[0] is the base address register that is to | |
1297 | * contain the MAC address. SHRA[0-10] are the shared receive address | |
1298 | * registers that are shared between the Host and manageability engine (ME). | |
1299 | **/ | |
1300 | static void e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) | |
1301 | { | |
1302 | u32 rar_low, rar_high; | |
1303 | u32 wlock_mac; | |
1304 | ||
e921eb1a | 1305 | /* HW expects these in little endian so we reverse the byte order |
2fbe4526 BA |
1306 | * from network order (big endian) to little endian |
1307 | */ | |
1308 | rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | | |
1309 | ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); | |
1310 | ||
1311 | rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); | |
1312 | ||
1313 | /* If MAC address zero, no need to set the AV bit */ | |
1314 | if (rar_low || rar_high) | |
1315 | rar_high |= E1000_RAH_AV; | |
1316 | ||
1317 | if (index == 0) { | |
1318 | ew32(RAL(index), rar_low); | |
1319 | e1e_flush(); | |
1320 | ew32(RAH(index), rar_high); | |
1321 | e1e_flush(); | |
1322 | return; | |
1323 | } | |
1324 | ||
e921eb1a | 1325 | /* The manageability engine (ME) can lock certain SHRAR registers that |
2fbe4526 BA |
1326 | * it is using - those registers are unavailable for use. |
1327 | */ | |
1328 | if (index < hw->mac.rar_entry_count) { | |
1329 | wlock_mac = er32(FWSM) & E1000_FWSM_WLOCK_MAC_MASK; | |
1330 | wlock_mac >>= E1000_FWSM_WLOCK_MAC_SHIFT; | |
1331 | ||
1332 | /* Check if all SHRAR registers are locked */ | |
1333 | if (wlock_mac == 1) | |
1334 | goto out; | |
1335 | ||
1336 | if ((wlock_mac == 0) || (index <= wlock_mac)) { | |
1337 | s32 ret_val; | |
1338 | ||
1339 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
1340 | ||
1341 | if (ret_val) | |
1342 | goto out; | |
1343 | ||
1344 | ew32(SHRAL_PCH_LPT(index - 1), rar_low); | |
1345 | e1e_flush(); | |
1346 | ew32(SHRAH_PCH_LPT(index - 1), rar_high); | |
1347 | e1e_flush(); | |
1348 | ||
1349 | e1000_release_swflag_ich8lan(hw); | |
1350 | ||
1351 | /* verify the register updates */ | |
1352 | if ((er32(SHRAL_PCH_LPT(index - 1)) == rar_low) && | |
1353 | (er32(SHRAH_PCH_LPT(index - 1)) == rar_high)) | |
1354 | return; | |
1355 | } | |
1356 | } | |
1357 | ||
1358 | out: | |
1359 | e_dbg("Failed to write receive address at index %d\n", index); | |
1360 | } | |
1361 | ||
bc7f75fa AK |
1362 | /** |
1363 | * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked | |
1364 | * @hw: pointer to the HW structure | |
1365 | * | |
1366 | * Checks if firmware is blocking the reset of the PHY. | |
1367 | * This is a function pointer entry point only called by | |
1368 | * reset routines. | |
1369 | **/ | |
1370 | static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw) | |
1371 | { | |
1372 | u32 fwsm; | |
1373 | ||
1374 | fwsm = er32(FWSM); | |
1375 | ||
1376 | return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET; | |
1377 | } | |
1378 | ||
8395ae83 BA |
1379 | /** |
1380 | * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states | |
1381 | * @hw: pointer to the HW structure | |
1382 | * | |
1383 | * Assumes semaphore already acquired. | |
1384 | * | |
1385 | **/ | |
1386 | static s32 e1000_write_smbus_addr(struct e1000_hw *hw) | |
1387 | { | |
1388 | u16 phy_data; | |
1389 | u32 strap = er32(STRAP); | |
2fbe4526 BA |
1390 | u32 freq = (strap & E1000_STRAP_SMT_FREQ_MASK) >> |
1391 | E1000_STRAP_SMT_FREQ_SHIFT; | |
8395ae83 BA |
1392 | s32 ret_val = 0; |
1393 | ||
1394 | strap &= E1000_STRAP_SMBUS_ADDRESS_MASK; | |
1395 | ||
1396 | ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data); | |
1397 | if (ret_val) | |
5015e53a | 1398 | return ret_val; |
8395ae83 BA |
1399 | |
1400 | phy_data &= ~HV_SMB_ADDR_MASK; | |
1401 | phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT); | |
1402 | phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID; | |
8395ae83 | 1403 | |
2fbe4526 BA |
1404 | if (hw->phy.type == e1000_phy_i217) { |
1405 | /* Restore SMBus frequency */ | |
1406 | if (freq--) { | |
1407 | phy_data &= ~HV_SMB_ADDR_FREQ_MASK; | |
1408 | phy_data |= (freq & (1 << 0)) << | |
1409 | HV_SMB_ADDR_FREQ_LOW_SHIFT; | |
1410 | phy_data |= (freq & (1 << 1)) << | |
1411 | (HV_SMB_ADDR_FREQ_HIGH_SHIFT - 1); | |
1412 | } else { | |
1413 | e_dbg("Unsupported SMB frequency in PHY\n"); | |
1414 | } | |
1415 | } | |
1416 | ||
5015e53a | 1417 | return e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data); |
8395ae83 BA |
1418 | } |
1419 | ||
f523d211 BA |
1420 | /** |
1421 | * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration | |
1422 | * @hw: pointer to the HW structure | |
1423 | * | |
1424 | * SW should configure the LCD from the NVM extended configuration region | |
1425 | * as a workaround for certain parts. | |
1426 | **/ | |
1427 | static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw) | |
1428 | { | |
1429 | struct e1000_phy_info *phy = &hw->phy; | |
1430 | u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask; | |
8b802a7e | 1431 | s32 ret_val = 0; |
f523d211 BA |
1432 | u16 word_addr, reg_data, reg_addr, phy_page = 0; |
1433 | ||
e921eb1a | 1434 | /* Initialize the PHY from the NVM on ICH platforms. This |
f523d211 BA |
1435 | * is needed due to an issue where the NVM configuration is |
1436 | * not properly autoloaded after power transitions. | |
1437 | * Therefore, after each PHY reset, we will load the | |
1438 | * configuration data out of the NVM manually. | |
1439 | */ | |
3f0c16e8 BA |
1440 | switch (hw->mac.type) { |
1441 | case e1000_ich8lan: | |
1442 | if (phy->type != e1000_phy_igp_3) | |
1443 | return ret_val; | |
1444 | ||
5f3eed6f BA |
1445 | if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) || |
1446 | (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) { | |
3f0c16e8 BA |
1447 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG; |
1448 | break; | |
1449 | } | |
1450 | /* Fall-thru */ | |
1451 | case e1000_pchlan: | |
d3738bb8 | 1452 | case e1000_pch2lan: |
2fbe4526 | 1453 | case e1000_pch_lpt: |
8b802a7e | 1454 | sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M; |
3f0c16e8 BA |
1455 | break; |
1456 | default: | |
1457 | return ret_val; | |
1458 | } | |
1459 | ||
1460 | ret_val = hw->phy.ops.acquire(hw); | |
1461 | if (ret_val) | |
1462 | return ret_val; | |
8b802a7e BA |
1463 | |
1464 | data = er32(FEXTNVM); | |
1465 | if (!(data & sw_cfg_mask)) | |
75ce1532 | 1466 | goto release; |
f523d211 | 1467 | |
e921eb1a | 1468 | /* Make sure HW does not configure LCD from PHY |
8b802a7e BA |
1469 | * extended configuration before SW configuration |
1470 | */ | |
1471 | data = er32(EXTCNF_CTRL); | |
2fbe4526 BA |
1472 | if ((hw->mac.type < e1000_pch2lan) && |
1473 | (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)) | |
1474 | goto release; | |
8b802a7e BA |
1475 | |
1476 | cnf_size = er32(EXTCNF_SIZE); | |
1477 | cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK; | |
1478 | cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT; | |
1479 | if (!cnf_size) | |
75ce1532 | 1480 | goto release; |
8b802a7e BA |
1481 | |
1482 | cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK; | |
1483 | cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT; | |
1484 | ||
2fbe4526 BA |
1485 | if (((hw->mac.type == e1000_pchlan) && |
1486 | !(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)) || | |
1487 | (hw->mac.type > e1000_pchlan)) { | |
e921eb1a | 1488 | /* HW configures the SMBus address and LEDs when the |
8b802a7e BA |
1489 | * OEM and LCD Write Enable bits are set in the NVM. |
1490 | * When both NVM bits are cleared, SW will configure | |
1491 | * them instead. | |
f523d211 | 1492 | */ |
8395ae83 | 1493 | ret_val = e1000_write_smbus_addr(hw); |
8b802a7e | 1494 | if (ret_val) |
75ce1532 | 1495 | goto release; |
f523d211 | 1496 | |
8b802a7e BA |
1497 | data = er32(LEDCTL); |
1498 | ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG, | |
1499 | (u16)data); | |
1500 | if (ret_val) | |
75ce1532 | 1501 | goto release; |
8b802a7e | 1502 | } |
f523d211 | 1503 | |
8b802a7e BA |
1504 | /* Configure LCD from extended configuration region. */ |
1505 | ||
1506 | /* cnf_base_addr is in DWORD */ | |
1507 | word_addr = (u16)(cnf_base_addr << 1); | |
1508 | ||
1509 | for (i = 0; i < cnf_size; i++) { | |
1510 | ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1, | |
1511 | ®_data); | |
1512 | if (ret_val) | |
75ce1532 | 1513 | goto release; |
8b802a7e BA |
1514 | |
1515 | ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1), | |
1516 | 1, ®_addr); | |
1517 | if (ret_val) | |
75ce1532 | 1518 | goto release; |
8b802a7e BA |
1519 | |
1520 | /* Save off the PHY page for future writes. */ | |
1521 | if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) { | |
1522 | phy_page = reg_data; | |
1523 | continue; | |
f523d211 | 1524 | } |
8b802a7e BA |
1525 | |
1526 | reg_addr &= PHY_REG_MASK; | |
1527 | reg_addr |= phy_page; | |
1528 | ||
f1430d69 | 1529 | ret_val = e1e_wphy_locked(hw, (u32)reg_addr, reg_data); |
8b802a7e | 1530 | if (ret_val) |
75ce1532 | 1531 | goto release; |
f523d211 BA |
1532 | } |
1533 | ||
75ce1532 | 1534 | release: |
94d8186a | 1535 | hw->phy.ops.release(hw); |
f523d211 BA |
1536 | return ret_val; |
1537 | } | |
1538 | ||
1d5846b9 BA |
1539 | /** |
1540 | * e1000_k1_gig_workaround_hv - K1 Si workaround | |
1541 | * @hw: pointer to the HW structure | |
1542 | * @link: link up bool flag | |
1543 | * | |
1544 | * If K1 is enabled for 1Gbps, the MAC might stall when transitioning | |
1545 | * from a lower speed. This workaround disables K1 whenever link is at 1Gig | |
1546 | * If link is down, the function will restore the default K1 setting located | |
1547 | * in the NVM. | |
1548 | **/ | |
1549 | static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link) | |
1550 | { | |
1551 | s32 ret_val = 0; | |
1552 | u16 status_reg = 0; | |
1553 | bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled; | |
1554 | ||
1555 | if (hw->mac.type != e1000_pchlan) | |
5015e53a | 1556 | return 0; |
1d5846b9 BA |
1557 | |
1558 | /* Wrap the whole flow with the sw flag */ | |
94d8186a | 1559 | ret_val = hw->phy.ops.acquire(hw); |
1d5846b9 | 1560 | if (ret_val) |
5015e53a | 1561 | return ret_val; |
1d5846b9 BA |
1562 | |
1563 | /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */ | |
1564 | if (link) { | |
1565 | if (hw->phy.type == e1000_phy_82578) { | |
f1430d69 BA |
1566 | ret_val = e1e_rphy_locked(hw, BM_CS_STATUS, |
1567 | &status_reg); | |
1d5846b9 BA |
1568 | if (ret_val) |
1569 | goto release; | |
1570 | ||
1571 | status_reg &= BM_CS_STATUS_LINK_UP | | |
1572 | BM_CS_STATUS_RESOLVED | | |
1573 | BM_CS_STATUS_SPEED_MASK; | |
1574 | ||
1575 | if (status_reg == (BM_CS_STATUS_LINK_UP | | |
1576 | BM_CS_STATUS_RESOLVED | | |
1577 | BM_CS_STATUS_SPEED_1000)) | |
1578 | k1_enable = false; | |
1579 | } | |
1580 | ||
1581 | if (hw->phy.type == e1000_phy_82577) { | |
f1430d69 | 1582 | ret_val = e1e_rphy_locked(hw, HV_M_STATUS, &status_reg); |
1d5846b9 BA |
1583 | if (ret_val) |
1584 | goto release; | |
1585 | ||
1586 | status_reg &= HV_M_STATUS_LINK_UP | | |
1587 | HV_M_STATUS_AUTONEG_COMPLETE | | |
1588 | HV_M_STATUS_SPEED_MASK; | |
1589 | ||
1590 | if (status_reg == (HV_M_STATUS_LINK_UP | | |
1591 | HV_M_STATUS_AUTONEG_COMPLETE | | |
1592 | HV_M_STATUS_SPEED_1000)) | |
1593 | k1_enable = false; | |
1594 | } | |
1595 | ||
1596 | /* Link stall fix for link up */ | |
f1430d69 | 1597 | ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); |
1d5846b9 BA |
1598 | if (ret_val) |
1599 | goto release; | |
1600 | ||
1601 | } else { | |
1602 | /* Link stall fix for link down */ | |
f1430d69 | 1603 | ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); |
1d5846b9 BA |
1604 | if (ret_val) |
1605 | goto release; | |
1606 | } | |
1607 | ||
1608 | ret_val = e1000_configure_k1_ich8lan(hw, k1_enable); | |
1609 | ||
1610 | release: | |
94d8186a | 1611 | hw->phy.ops.release(hw); |
5015e53a | 1612 | |
1d5846b9 BA |
1613 | return ret_val; |
1614 | } | |
1615 | ||
1616 | /** | |
1617 | * e1000_configure_k1_ich8lan - Configure K1 power state | |
1618 | * @hw: pointer to the HW structure | |
1619 | * @enable: K1 state to configure | |
1620 | * | |
1621 | * Configure the K1 power state based on the provided parameter. | |
1622 | * Assumes semaphore already acquired. | |
1623 | * | |
1624 | * Success returns 0, Failure returns -E1000_ERR_PHY (-2) | |
1625 | **/ | |
bb436b20 | 1626 | s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable) |
1d5846b9 BA |
1627 | { |
1628 | s32 ret_val = 0; | |
1629 | u32 ctrl_reg = 0; | |
1630 | u32 ctrl_ext = 0; | |
1631 | u32 reg = 0; | |
1632 | u16 kmrn_reg = 0; | |
1633 | ||
3d3a1676 BA |
1634 | ret_val = e1000e_read_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, |
1635 | &kmrn_reg); | |
1d5846b9 | 1636 | if (ret_val) |
5015e53a | 1637 | return ret_val; |
1d5846b9 BA |
1638 | |
1639 | if (k1_enable) | |
1640 | kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE; | |
1641 | else | |
1642 | kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE; | |
1643 | ||
3d3a1676 BA |
1644 | ret_val = e1000e_write_kmrn_reg_locked(hw, E1000_KMRNCTRLSTA_K1_CONFIG, |
1645 | kmrn_reg); | |
1d5846b9 | 1646 | if (ret_val) |
5015e53a | 1647 | return ret_val; |
1d5846b9 BA |
1648 | |
1649 | udelay(20); | |
1650 | ctrl_ext = er32(CTRL_EXT); | |
1651 | ctrl_reg = er32(CTRL); | |
1652 | ||
1653 | reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); | |
1654 | reg |= E1000_CTRL_FRCSPD; | |
1655 | ew32(CTRL, reg); | |
1656 | ||
1657 | ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS); | |
945a5151 | 1658 | e1e_flush(); |
1d5846b9 BA |
1659 | udelay(20); |
1660 | ew32(CTRL, ctrl_reg); | |
1661 | ew32(CTRL_EXT, ctrl_ext); | |
945a5151 | 1662 | e1e_flush(); |
1d5846b9 BA |
1663 | udelay(20); |
1664 | ||
5015e53a | 1665 | return 0; |
1d5846b9 BA |
1666 | } |
1667 | ||
f523d211 BA |
1668 | /** |
1669 | * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration | |
1670 | * @hw: pointer to the HW structure | |
1671 | * @d0_state: boolean if entering d0 or d3 device state | |
1672 | * | |
1673 | * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are | |
1674 | * collectively called OEM bits. The OEM Write Enable bit and SW Config bit | |
1675 | * in NVM determines whether HW should configure LPLU and Gbe Disable. | |
1676 | **/ | |
1677 | static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state) | |
1678 | { | |
1679 | s32 ret_val = 0; | |
1680 | u32 mac_reg; | |
1681 | u16 oem_reg; | |
1682 | ||
2fbe4526 | 1683 | if (hw->mac.type < e1000_pchlan) |
f523d211 BA |
1684 | return ret_val; |
1685 | ||
94d8186a | 1686 | ret_val = hw->phy.ops.acquire(hw); |
f523d211 BA |
1687 | if (ret_val) |
1688 | return ret_val; | |
1689 | ||
2fbe4526 | 1690 | if (hw->mac.type == e1000_pchlan) { |
d3738bb8 BA |
1691 | mac_reg = er32(EXTCNF_CTRL); |
1692 | if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) | |
75ce1532 | 1693 | goto release; |
d3738bb8 | 1694 | } |
f523d211 BA |
1695 | |
1696 | mac_reg = er32(FEXTNVM); | |
1697 | if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M)) | |
75ce1532 | 1698 | goto release; |
f523d211 BA |
1699 | |
1700 | mac_reg = er32(PHY_CTRL); | |
1701 | ||
f1430d69 | 1702 | ret_val = e1e_rphy_locked(hw, HV_OEM_BITS, &oem_reg); |
f523d211 | 1703 | if (ret_val) |
75ce1532 | 1704 | goto release; |
f523d211 BA |
1705 | |
1706 | oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU); | |
1707 | ||
1708 | if (d0_state) { | |
1709 | if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE) | |
1710 | oem_reg |= HV_OEM_BITS_GBE_DIS; | |
1711 | ||
1712 | if (mac_reg & E1000_PHY_CTRL_D0A_LPLU) | |
1713 | oem_reg |= HV_OEM_BITS_LPLU; | |
1714 | } else { | |
03299e46 BA |
1715 | if (mac_reg & (E1000_PHY_CTRL_GBE_DISABLE | |
1716 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE)) | |
f523d211 BA |
1717 | oem_reg |= HV_OEM_BITS_GBE_DIS; |
1718 | ||
03299e46 BA |
1719 | if (mac_reg & (E1000_PHY_CTRL_D0A_LPLU | |
1720 | E1000_PHY_CTRL_NOND0A_LPLU)) | |
f523d211 BA |
1721 | oem_reg |= HV_OEM_BITS_LPLU; |
1722 | } | |
03299e46 | 1723 | |
92fe1733 BA |
1724 | /* Set Restart auto-neg to activate the bits */ |
1725 | if ((d0_state || (hw->mac.type != e1000_pchlan)) && | |
1726 | !hw->phy.ops.check_reset_block(hw)) | |
1727 | oem_reg |= HV_OEM_BITS_RESTART_AN; | |
1728 | ||
f1430d69 | 1729 | ret_val = e1e_wphy_locked(hw, HV_OEM_BITS, oem_reg); |
f523d211 | 1730 | |
75ce1532 | 1731 | release: |
94d8186a | 1732 | hw->phy.ops.release(hw); |
f523d211 BA |
1733 | |
1734 | return ret_val; | |
1735 | } | |
1736 | ||
1737 | ||
fddaa1af BA |
1738 | /** |
1739 | * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode | |
1740 | * @hw: pointer to the HW structure | |
1741 | **/ | |
1742 | static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw) | |
1743 | { | |
1744 | s32 ret_val; | |
1745 | u16 data; | |
1746 | ||
1747 | ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data); | |
1748 | if (ret_val) | |
1749 | return ret_val; | |
1750 | ||
1751 | data |= HV_KMRN_MDIO_SLOW; | |
1752 | ||
1753 | ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data); | |
1754 | ||
1755 | return ret_val; | |
1756 | } | |
1757 | ||
a4f58f54 BA |
1758 | /** |
1759 | * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be | |
1760 | * done after every PHY reset. | |
1761 | **/ | |
1762 | static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw) | |
1763 | { | |
1764 | s32 ret_val = 0; | |
baf86c9d | 1765 | u16 phy_data; |
a4f58f54 BA |
1766 | |
1767 | if (hw->mac.type != e1000_pchlan) | |
5015e53a | 1768 | return 0; |
a4f58f54 | 1769 | |
fddaa1af BA |
1770 | /* Set MDIO slow mode before any other MDIO access */ |
1771 | if (hw->phy.type == e1000_phy_82577) { | |
1772 | ret_val = e1000_set_mdio_slow_mode_hv(hw); | |
1773 | if (ret_val) | |
5015e53a | 1774 | return ret_val; |
fddaa1af BA |
1775 | } |
1776 | ||
a4f58f54 BA |
1777 | if (((hw->phy.type == e1000_phy_82577) && |
1778 | ((hw->phy.revision == 1) || (hw->phy.revision == 2))) || | |
1779 | ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) { | |
1780 | /* Disable generation of early preamble */ | |
1781 | ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); | |
1782 | if (ret_val) | |
1783 | return ret_val; | |
1784 | ||
1785 | /* Preamble tuning for SSC */ | |
1d2101a7 | 1786 | ret_val = e1e_wphy(hw, HV_KMRN_FIFO_CTRLSTA, 0xA204); |
a4f58f54 BA |
1787 | if (ret_val) |
1788 | return ret_val; | |
1789 | } | |
1790 | ||
1791 | if (hw->phy.type == e1000_phy_82578) { | |
e921eb1a | 1792 | /* Return registers to default by doing a soft reset then |
a4f58f54 BA |
1793 | * writing 0x3140 to the control register. |
1794 | */ | |
1795 | if (hw->phy.revision < 2) { | |
1796 | e1000e_phy_sw_reset(hw); | |
1797 | ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140); | |
1798 | } | |
1799 | } | |
1800 | ||
1801 | /* Select page 0 */ | |
94d8186a | 1802 | ret_val = hw->phy.ops.acquire(hw); |
a4f58f54 BA |
1803 | if (ret_val) |
1804 | return ret_val; | |
1d5846b9 | 1805 | |
a4f58f54 | 1806 | hw->phy.addr = 1; |
1d5846b9 | 1807 | ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0); |
baf86c9d | 1808 | hw->phy.ops.release(hw); |
1d5846b9 | 1809 | if (ret_val) |
5015e53a | 1810 | return ret_val; |
a4f58f54 | 1811 | |
e921eb1a | 1812 | /* Configure the K1 Si workaround during phy reset assuming there is |
1d5846b9 BA |
1813 | * link so that it disables K1 if link is in 1Gbps. |
1814 | */ | |
1815 | ret_val = e1000_k1_gig_workaround_hv(hw, true); | |
baf86c9d | 1816 | if (ret_val) |
5015e53a | 1817 | return ret_val; |
1d5846b9 | 1818 | |
baf86c9d BA |
1819 | /* Workaround for link disconnects on a busy hub in half duplex */ |
1820 | ret_val = hw->phy.ops.acquire(hw); | |
1821 | if (ret_val) | |
5015e53a | 1822 | return ret_val; |
f1430d69 | 1823 | ret_val = e1e_rphy_locked(hw, BM_PORT_GEN_CFG, &phy_data); |
baf86c9d BA |
1824 | if (ret_val) |
1825 | goto release; | |
f1430d69 | 1826 | ret_val = e1e_wphy_locked(hw, BM_PORT_GEN_CFG, phy_data & 0x00FF); |
651fb102 BA |
1827 | if (ret_val) |
1828 | goto release; | |
1829 | ||
1830 | /* set MSE higher to enable link to stay up when noise is high */ | |
1831 | ret_val = e1000_write_emi_reg_locked(hw, I82577_MSE_THRESHOLD, 0x0034); | |
baf86c9d BA |
1832 | release: |
1833 | hw->phy.ops.release(hw); | |
5015e53a | 1834 | |
a4f58f54 BA |
1835 | return ret_val; |
1836 | } | |
1837 | ||
d3738bb8 BA |
1838 | /** |
1839 | * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY | |
1840 | * @hw: pointer to the HW structure | |
1841 | **/ | |
1842 | void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) | |
1843 | { | |
1844 | u32 mac_reg; | |
2b6b168d BA |
1845 | u16 i, phy_reg = 0; |
1846 | s32 ret_val; | |
1847 | ||
1848 | ret_val = hw->phy.ops.acquire(hw); | |
1849 | if (ret_val) | |
1850 | return; | |
1851 | ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); | |
1852 | if (ret_val) | |
1853 | goto release; | |
d3738bb8 BA |
1854 | |
1855 | /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */ | |
1856 | for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { | |
1857 | mac_reg = er32(RAL(i)); | |
2b6b168d BA |
1858 | hw->phy.ops.write_reg_page(hw, BM_RAR_L(i), |
1859 | (u16)(mac_reg & 0xFFFF)); | |
1860 | hw->phy.ops.write_reg_page(hw, BM_RAR_M(i), | |
1861 | (u16)((mac_reg >> 16) & 0xFFFF)); | |
1862 | ||
d3738bb8 | 1863 | mac_reg = er32(RAH(i)); |
2b6b168d BA |
1864 | hw->phy.ops.write_reg_page(hw, BM_RAR_H(i), |
1865 | (u16)(mac_reg & 0xFFFF)); | |
1866 | hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i), | |
1867 | (u16)((mac_reg & E1000_RAH_AV) | |
1868 | >> 16)); | |
d3738bb8 | 1869 | } |
2b6b168d BA |
1870 | |
1871 | e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); | |
1872 | ||
1873 | release: | |
1874 | hw->phy.ops.release(hw); | |
d3738bb8 BA |
1875 | } |
1876 | ||
d3738bb8 BA |
1877 | /** |
1878 | * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation | |
1879 | * with 82579 PHY | |
1880 | * @hw: pointer to the HW structure | |
1881 | * @enable: flag to enable/disable workaround when enabling/disabling jumbos | |
1882 | **/ | |
1883 | s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) | |
1884 | { | |
1885 | s32 ret_val = 0; | |
1886 | u16 phy_reg, data; | |
1887 | u32 mac_reg; | |
1888 | u16 i; | |
1889 | ||
2fbe4526 | 1890 | if (hw->mac.type < e1000_pch2lan) |
5015e53a | 1891 | return 0; |
d3738bb8 BA |
1892 | |
1893 | /* disable Rx path while enabling/disabling workaround */ | |
1894 | e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); | |
1895 | ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14)); | |
1896 | if (ret_val) | |
5015e53a | 1897 | return ret_val; |
d3738bb8 BA |
1898 | |
1899 | if (enable) { | |
e921eb1a | 1900 | /* Write Rx addresses (rar_entry_count for RAL/H, +4 for |
d3738bb8 BA |
1901 | * SHRAL/H) and initial CRC values to the MAC |
1902 | */ | |
1903 | for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) { | |
1904 | u8 mac_addr[ETH_ALEN] = {0}; | |
1905 | u32 addr_high, addr_low; | |
1906 | ||
1907 | addr_high = er32(RAH(i)); | |
1908 | if (!(addr_high & E1000_RAH_AV)) | |
1909 | continue; | |
1910 | addr_low = er32(RAL(i)); | |
1911 | mac_addr[0] = (addr_low & 0xFF); | |
1912 | mac_addr[1] = ((addr_low >> 8) & 0xFF); | |
1913 | mac_addr[2] = ((addr_low >> 16) & 0xFF); | |
1914 | mac_addr[3] = ((addr_low >> 24) & 0xFF); | |
1915 | mac_addr[4] = (addr_high & 0xFF); | |
1916 | mac_addr[5] = ((addr_high >> 8) & 0xFF); | |
1917 | ||
fe46f58f | 1918 | ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr)); |
d3738bb8 BA |
1919 | } |
1920 | ||
1921 | /* Write Rx addresses to the PHY */ | |
1922 | e1000_copy_rx_addrs_to_phy_ich8lan(hw); | |
1923 | ||
1924 | /* Enable jumbo frame workaround in the MAC */ | |
1925 | mac_reg = er32(FFLT_DBG); | |
1926 | mac_reg &= ~(1 << 14); | |
1927 | mac_reg |= (7 << 15); | |
1928 | ew32(FFLT_DBG, mac_reg); | |
1929 | ||
1930 | mac_reg = er32(RCTL); | |
1931 | mac_reg |= E1000_RCTL_SECRC; | |
1932 | ew32(RCTL, mac_reg); | |
1933 | ||
1934 | ret_val = e1000e_read_kmrn_reg(hw, | |
1935 | E1000_KMRNCTRLSTA_CTRL_OFFSET, | |
1936 | &data); | |
1937 | if (ret_val) | |
5015e53a | 1938 | return ret_val; |
d3738bb8 BA |
1939 | ret_val = e1000e_write_kmrn_reg(hw, |
1940 | E1000_KMRNCTRLSTA_CTRL_OFFSET, | |
1941 | data | (1 << 0)); | |
1942 | if (ret_val) | |
5015e53a | 1943 | return ret_val; |
d3738bb8 BA |
1944 | ret_val = e1000e_read_kmrn_reg(hw, |
1945 | E1000_KMRNCTRLSTA_HD_CTRL, | |
1946 | &data); | |
1947 | if (ret_val) | |
5015e53a | 1948 | return ret_val; |
d3738bb8 BA |
1949 | data &= ~(0xF << 8); |
1950 | data |= (0xB << 8); | |
1951 | ret_val = e1000e_write_kmrn_reg(hw, | |
1952 | E1000_KMRNCTRLSTA_HD_CTRL, | |
1953 | data); | |
1954 | if (ret_val) | |
5015e53a | 1955 | return ret_val; |
d3738bb8 BA |
1956 | |
1957 | /* Enable jumbo frame workaround in the PHY */ | |
d3738bb8 BA |
1958 | e1e_rphy(hw, PHY_REG(769, 23), &data); |
1959 | data &= ~(0x7F << 5); | |
1960 | data |= (0x37 << 5); | |
1961 | ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); | |
1962 | if (ret_val) | |
5015e53a | 1963 | return ret_val; |
d3738bb8 BA |
1964 | e1e_rphy(hw, PHY_REG(769, 16), &data); |
1965 | data &= ~(1 << 13); | |
d3738bb8 BA |
1966 | ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); |
1967 | if (ret_val) | |
5015e53a | 1968 | return ret_val; |
d3738bb8 BA |
1969 | e1e_rphy(hw, PHY_REG(776, 20), &data); |
1970 | data &= ~(0x3FF << 2); | |
1971 | data |= (0x1A << 2); | |
1972 | ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); | |
1973 | if (ret_val) | |
5015e53a | 1974 | return ret_val; |
b64e9dd5 | 1975 | ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xF100); |
d3738bb8 | 1976 | if (ret_val) |
5015e53a | 1977 | return ret_val; |
d3738bb8 BA |
1978 | e1e_rphy(hw, HV_PM_CTRL, &data); |
1979 | ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10)); | |
1980 | if (ret_val) | |
5015e53a | 1981 | return ret_val; |
d3738bb8 BA |
1982 | } else { |
1983 | /* Write MAC register values back to h/w defaults */ | |
1984 | mac_reg = er32(FFLT_DBG); | |
1985 | mac_reg &= ~(0xF << 14); | |
1986 | ew32(FFLT_DBG, mac_reg); | |
1987 | ||
1988 | mac_reg = er32(RCTL); | |
1989 | mac_reg &= ~E1000_RCTL_SECRC; | |
a1ce6473 | 1990 | ew32(RCTL, mac_reg); |
d3738bb8 BA |
1991 | |
1992 | ret_val = e1000e_read_kmrn_reg(hw, | |
1993 | E1000_KMRNCTRLSTA_CTRL_OFFSET, | |
1994 | &data); | |
1995 | if (ret_val) | |
5015e53a | 1996 | return ret_val; |
d3738bb8 BA |
1997 | ret_val = e1000e_write_kmrn_reg(hw, |
1998 | E1000_KMRNCTRLSTA_CTRL_OFFSET, | |
1999 | data & ~(1 << 0)); | |
2000 | if (ret_val) | |
5015e53a | 2001 | return ret_val; |
d3738bb8 BA |
2002 | ret_val = e1000e_read_kmrn_reg(hw, |
2003 | E1000_KMRNCTRLSTA_HD_CTRL, | |
2004 | &data); | |
2005 | if (ret_val) | |
5015e53a | 2006 | return ret_val; |
d3738bb8 BA |
2007 | data &= ~(0xF << 8); |
2008 | data |= (0xB << 8); | |
2009 | ret_val = e1000e_write_kmrn_reg(hw, | |
2010 | E1000_KMRNCTRLSTA_HD_CTRL, | |
2011 | data); | |
2012 | if (ret_val) | |
5015e53a | 2013 | return ret_val; |
d3738bb8 BA |
2014 | |
2015 | /* Write PHY register values back to h/w defaults */ | |
d3738bb8 BA |
2016 | e1e_rphy(hw, PHY_REG(769, 23), &data); |
2017 | data &= ~(0x7F << 5); | |
2018 | ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); | |
2019 | if (ret_val) | |
5015e53a | 2020 | return ret_val; |
d3738bb8 | 2021 | e1e_rphy(hw, PHY_REG(769, 16), &data); |
d3738bb8 BA |
2022 | data |= (1 << 13); |
2023 | ret_val = e1e_wphy(hw, PHY_REG(769, 16), data); | |
2024 | if (ret_val) | |
5015e53a | 2025 | return ret_val; |
d3738bb8 BA |
2026 | e1e_rphy(hw, PHY_REG(776, 20), &data); |
2027 | data &= ~(0x3FF << 2); | |
2028 | data |= (0x8 << 2); | |
2029 | ret_val = e1e_wphy(hw, PHY_REG(776, 20), data); | |
2030 | if (ret_val) | |
5015e53a | 2031 | return ret_val; |
d3738bb8 BA |
2032 | ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00); |
2033 | if (ret_val) | |
5015e53a | 2034 | return ret_val; |
d3738bb8 BA |
2035 | e1e_rphy(hw, HV_PM_CTRL, &data); |
2036 | ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10)); | |
2037 | if (ret_val) | |
5015e53a | 2038 | return ret_val; |
d3738bb8 BA |
2039 | } |
2040 | ||
2041 | /* re-enable Rx path after enabling/disabling workaround */ | |
5015e53a | 2042 | return e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14)); |
d3738bb8 BA |
2043 | } |
2044 | ||
2045 | /** | |
2046 | * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be | |
2047 | * done after every PHY reset. | |
2048 | **/ | |
2049 | static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw) | |
2050 | { | |
2051 | s32 ret_val = 0; | |
2052 | ||
2053 | if (hw->mac.type != e1000_pch2lan) | |
5015e53a | 2054 | return 0; |
d3738bb8 BA |
2055 | |
2056 | /* Set MDIO slow mode before any other MDIO access */ | |
2057 | ret_val = e1000_set_mdio_slow_mode_hv(hw); | |
8e5ab42d BA |
2058 | if (ret_val) |
2059 | return ret_val; | |
d3738bb8 | 2060 | |
4d24136c BA |
2061 | ret_val = hw->phy.ops.acquire(hw); |
2062 | if (ret_val) | |
5015e53a | 2063 | return ret_val; |
4d24136c | 2064 | /* set MSE higher to enable link to stay up when noise is high */ |
4ddc48a9 | 2065 | ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_THRESHOLD, 0x0034); |
4d24136c BA |
2066 | if (ret_val) |
2067 | goto release; | |
2068 | /* drop link after 5 times MSE threshold was reached */ | |
4ddc48a9 | 2069 | ret_val = e1000_write_emi_reg_locked(hw, I82579_MSE_LINK_DOWN, 0x0005); |
4d24136c BA |
2070 | release: |
2071 | hw->phy.ops.release(hw); | |
2072 | ||
d3738bb8 BA |
2073 | return ret_val; |
2074 | } | |
2075 | ||
831bd2e6 BA |
2076 | /** |
2077 | * e1000_k1_gig_workaround_lv - K1 Si workaround | |
2078 | * @hw: pointer to the HW structure | |
2079 | * | |
2080 | * Workaround to set the K1 beacon duration for 82579 parts | |
2081 | **/ | |
2082 | static s32 e1000_k1_workaround_lv(struct e1000_hw *hw) | |
2083 | { | |
2084 | s32 ret_val = 0; | |
2085 | u16 status_reg = 0; | |
2086 | u32 mac_reg; | |
0ed013e2 | 2087 | u16 phy_reg; |
831bd2e6 BA |
2088 | |
2089 | if (hw->mac.type != e1000_pch2lan) | |
5015e53a | 2090 | return 0; |
831bd2e6 BA |
2091 | |
2092 | /* Set K1 beacon duration based on 1Gbps speed or otherwise */ | |
2093 | ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg); | |
2094 | if (ret_val) | |
5015e53a | 2095 | return ret_val; |
831bd2e6 BA |
2096 | |
2097 | if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) | |
2098 | == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) { | |
2099 | mac_reg = er32(FEXTNVM4); | |
2100 | mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK; | |
2101 | ||
0ed013e2 BA |
2102 | ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg); |
2103 | if (ret_val) | |
5015e53a | 2104 | return ret_val; |
0ed013e2 BA |
2105 | |
2106 | if (status_reg & HV_M_STATUS_SPEED_1000) { | |
36ceeb43 BA |
2107 | u16 pm_phy_reg; |
2108 | ||
831bd2e6 | 2109 | mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC; |
0ed013e2 | 2110 | phy_reg &= ~I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; |
36ceeb43 BA |
2111 | /* LV 1G Packet drop issue wa */ |
2112 | ret_val = e1e_rphy(hw, HV_PM_CTRL, &pm_phy_reg); | |
2113 | if (ret_val) | |
2114 | return ret_val; | |
2115 | pm_phy_reg &= ~HV_PM_CTRL_PLL_STOP_IN_K1_GIGA; | |
2116 | ret_val = e1e_wphy(hw, HV_PM_CTRL, pm_phy_reg); | |
2117 | if (ret_val) | |
2118 | return ret_val; | |
0ed013e2 | 2119 | } else { |
831bd2e6 | 2120 | mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC; |
0ed013e2 BA |
2121 | phy_reg |= I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT; |
2122 | } | |
831bd2e6 | 2123 | ew32(FEXTNVM4, mac_reg); |
0ed013e2 | 2124 | ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg); |
831bd2e6 BA |
2125 | } |
2126 | ||
831bd2e6 BA |
2127 | return ret_val; |
2128 | } | |
2129 | ||
605c82ba BA |
2130 | /** |
2131 | * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware | |
2132 | * @hw: pointer to the HW structure | |
2133 | * @gate: boolean set to true to gate, false to ungate | |
2134 | * | |
2135 | * Gate/ungate the automatic PHY configuration via hardware; perform | |
2136 | * the configuration via software instead. | |
2137 | **/ | |
2138 | static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) | |
2139 | { | |
2140 | u32 extcnf_ctrl; | |
2141 | ||
2fbe4526 | 2142 | if (hw->mac.type < e1000_pch2lan) |
605c82ba BA |
2143 | return; |
2144 | ||
2145 | extcnf_ctrl = er32(EXTCNF_CTRL); | |
2146 | ||
2147 | if (gate) | |
2148 | extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG; | |
2149 | else | |
2150 | extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG; | |
2151 | ||
2152 | ew32(EXTCNF_CTRL, extcnf_ctrl); | |
605c82ba BA |
2153 | } |
2154 | ||
fc0c7760 BA |
2155 | /** |
2156 | * e1000_lan_init_done_ich8lan - Check for PHY config completion | |
2157 | * @hw: pointer to the HW structure | |
2158 | * | |
2159 | * Check the appropriate indication the MAC has finished configuring the | |
2160 | * PHY after a software reset. | |
2161 | **/ | |
2162 | static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw) | |
2163 | { | |
2164 | u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT; | |
2165 | ||
2166 | /* Wait for basic configuration completes before proceeding */ | |
2167 | do { | |
2168 | data = er32(STATUS); | |
2169 | data &= E1000_STATUS_LAN_INIT_DONE; | |
2170 | udelay(100); | |
2171 | } while ((!data) && --loop); | |
2172 | ||
e921eb1a | 2173 | /* If basic configuration is incomplete before the above loop |
fc0c7760 BA |
2174 | * count reaches 0, loading the configuration from NVM will |
2175 | * leave the PHY in a bad state possibly resulting in no link. | |
2176 | */ | |
2177 | if (loop == 0) | |
3bb99fe2 | 2178 | e_dbg("LAN_INIT_DONE not set, increase timeout\n"); |
fc0c7760 BA |
2179 | |
2180 | /* Clear the Init Done bit for the next init event */ | |
2181 | data = er32(STATUS); | |
2182 | data &= ~E1000_STATUS_LAN_INIT_DONE; | |
2183 | ew32(STATUS, data); | |
2184 | } | |
2185 | ||
bc7f75fa | 2186 | /** |
e98cac44 | 2187 | * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset |
bc7f75fa | 2188 | * @hw: pointer to the HW structure |
bc7f75fa | 2189 | **/ |
e98cac44 | 2190 | static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw) |
bc7f75fa | 2191 | { |
f523d211 BA |
2192 | s32 ret_val = 0; |
2193 | u16 reg; | |
bc7f75fa | 2194 | |
44abd5c1 | 2195 | if (hw->phy.ops.check_reset_block(hw)) |
5015e53a | 2196 | return 0; |
fc0c7760 | 2197 | |
5f3eed6f | 2198 | /* Allow time for h/w to get to quiescent state after reset */ |
1bba4386 | 2199 | usleep_range(10000, 20000); |
5f3eed6f | 2200 | |
fddaa1af | 2201 | /* Perform any necessary post-reset workarounds */ |
e98cac44 BA |
2202 | switch (hw->mac.type) { |
2203 | case e1000_pchlan: | |
a4f58f54 BA |
2204 | ret_val = e1000_hv_phy_workarounds_ich8lan(hw); |
2205 | if (ret_val) | |
5015e53a | 2206 | return ret_val; |
e98cac44 | 2207 | break; |
d3738bb8 BA |
2208 | case e1000_pch2lan: |
2209 | ret_val = e1000_lv_phy_workarounds_ich8lan(hw); | |
2210 | if (ret_val) | |
5015e53a | 2211 | return ret_val; |
d3738bb8 | 2212 | break; |
e98cac44 BA |
2213 | default: |
2214 | break; | |
a4f58f54 BA |
2215 | } |
2216 | ||
3ebfc7c9 BA |
2217 | /* Clear the host wakeup bit after lcd reset */ |
2218 | if (hw->mac.type >= e1000_pchlan) { | |
2219 | e1e_rphy(hw, BM_PORT_GEN_CFG, ®); | |
2220 | reg &= ~BM_WUC_HOST_WU_BIT; | |
2221 | e1e_wphy(hw, BM_PORT_GEN_CFG, reg); | |
2222 | } | |
db2932ec | 2223 | |
f523d211 BA |
2224 | /* Configure the LCD with the extended configuration region in NVM */ |
2225 | ret_val = e1000_sw_lcd_config_ich8lan(hw); | |
2226 | if (ret_val) | |
5015e53a | 2227 | return ret_val; |
bc7f75fa | 2228 | |
f523d211 | 2229 | /* Configure the LCD with the OEM bits in NVM */ |
e98cac44 | 2230 | ret_val = e1000_oem_bits_config_ich8lan(hw, true); |
bc7f75fa | 2231 | |
1effb45c BA |
2232 | if (hw->mac.type == e1000_pch2lan) { |
2233 | /* Ungate automatic PHY configuration on non-managed 82579 */ | |
2234 | if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { | |
1bba4386 | 2235 | usleep_range(10000, 20000); |
1effb45c BA |
2236 | e1000_gate_hw_phy_config_ich8lan(hw, false); |
2237 | } | |
2238 | ||
2239 | /* Set EEE LPI Update Timer to 200usec */ | |
2240 | ret_val = hw->phy.ops.acquire(hw); | |
2241 | if (ret_val) | |
5015e53a | 2242 | return ret_val; |
4ddc48a9 BA |
2243 | ret_val = e1000_write_emi_reg_locked(hw, |
2244 | I82579_LPI_UPDATE_TIMER, | |
2245 | 0x1387); | |
1effb45c | 2246 | hw->phy.ops.release(hw); |
605c82ba BA |
2247 | } |
2248 | ||
e98cac44 BA |
2249 | return ret_val; |
2250 | } | |
2251 | ||
2252 | /** | |
2253 | * e1000_phy_hw_reset_ich8lan - Performs a PHY reset | |
2254 | * @hw: pointer to the HW structure | |
2255 | * | |
2256 | * Resets the PHY | |
2257 | * This is a function pointer entry point called by drivers | |
2258 | * or other shared routines. | |
2259 | **/ | |
2260 | static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw) | |
2261 | { | |
2262 | s32 ret_val = 0; | |
2263 | ||
605c82ba BA |
2264 | /* Gate automatic PHY configuration by hardware on non-managed 82579 */ |
2265 | if ((hw->mac.type == e1000_pch2lan) && | |
2266 | !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) | |
2267 | e1000_gate_hw_phy_config_ich8lan(hw, true); | |
2268 | ||
e98cac44 BA |
2269 | ret_val = e1000e_phy_hw_reset_generic(hw); |
2270 | if (ret_val) | |
5015e53a | 2271 | return ret_val; |
e98cac44 | 2272 | |
5015e53a | 2273 | return e1000_post_phy_reset_ich8lan(hw); |
bc7f75fa AK |
2274 | } |
2275 | ||
fa2ce13c BA |
2276 | /** |
2277 | * e1000_set_lplu_state_pchlan - Set Low Power Link Up state | |
2278 | * @hw: pointer to the HW structure | |
2279 | * @active: true to enable LPLU, false to disable | |
2280 | * | |
2281 | * Sets the LPLU state according to the active flag. For PCH, if OEM write | |
2282 | * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set | |
2283 | * the phy speed. This function will manually set the LPLU bit and restart | |
2284 | * auto-neg as hw would do. D3 and D0 LPLU will call the same function | |
2285 | * since it configures the same bit. | |
2286 | **/ | |
2287 | static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active) | |
2288 | { | |
2289 | s32 ret_val = 0; | |
2290 | u16 oem_reg; | |
2291 | ||
2292 | ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg); | |
2293 | if (ret_val) | |
5015e53a | 2294 | return ret_val; |
fa2ce13c BA |
2295 | |
2296 | if (active) | |
2297 | oem_reg |= HV_OEM_BITS_LPLU; | |
2298 | else | |
2299 | oem_reg &= ~HV_OEM_BITS_LPLU; | |
2300 | ||
44abd5c1 | 2301 | if (!hw->phy.ops.check_reset_block(hw)) |
464c85e3 BA |
2302 | oem_reg |= HV_OEM_BITS_RESTART_AN; |
2303 | ||
5015e53a | 2304 | return e1e_wphy(hw, HV_OEM_BITS, oem_reg); |
fa2ce13c BA |
2305 | } |
2306 | ||
bc7f75fa AK |
2307 | /** |
2308 | * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state | |
2309 | * @hw: pointer to the HW structure | |
564ea9bb | 2310 | * @active: true to enable LPLU, false to disable |
bc7f75fa AK |
2311 | * |
2312 | * Sets the LPLU D0 state according to the active flag. When | |
2313 | * activating LPLU this function also disables smart speed | |
2314 | * and vice versa. LPLU will not be activated unless the | |
2315 | * device autonegotiation advertisement meets standards of | |
2316 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
2317 | * This is a function pointer entry point only called by | |
2318 | * PHY setup routines. | |
2319 | **/ | |
2320 | static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |
2321 | { | |
2322 | struct e1000_phy_info *phy = &hw->phy; | |
2323 | u32 phy_ctrl; | |
2324 | s32 ret_val = 0; | |
2325 | u16 data; | |
2326 | ||
97ac8cae | 2327 | if (phy->type == e1000_phy_ife) |
82607255 | 2328 | return 0; |
bc7f75fa AK |
2329 | |
2330 | phy_ctrl = er32(PHY_CTRL); | |
2331 | ||
2332 | if (active) { | |
2333 | phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; | |
2334 | ew32(PHY_CTRL, phy_ctrl); | |
2335 | ||
60f1292f BA |
2336 | if (phy->type != e1000_phy_igp_3) |
2337 | return 0; | |
2338 | ||
e921eb1a | 2339 | /* Call gig speed drop workaround on LPLU before accessing |
ad68076e BA |
2340 | * any PHY registers |
2341 | */ | |
60f1292f | 2342 | if (hw->mac.type == e1000_ich8lan) |
bc7f75fa AK |
2343 | e1000e_gig_downshift_workaround_ich8lan(hw); |
2344 | ||
2345 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
2346 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); | |
2347 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2348 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); | |
2349 | if (ret_val) | |
2350 | return ret_val; | |
2351 | } else { | |
2352 | phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; | |
2353 | ew32(PHY_CTRL, phy_ctrl); | |
2354 | ||
60f1292f BA |
2355 | if (phy->type != e1000_phy_igp_3) |
2356 | return 0; | |
2357 | ||
e921eb1a | 2358 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
bc7f75fa AK |
2359 | * during Dx states where the power conservation is most |
2360 | * important. During driver activity we should enable | |
ad68076e BA |
2361 | * SmartSpeed, so performance is maintained. |
2362 | */ | |
bc7f75fa AK |
2363 | if (phy->smart_speed == e1000_smart_speed_on) { |
2364 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 2365 | &data); |
bc7f75fa AK |
2366 | if (ret_val) |
2367 | return ret_val; | |
2368 | ||
2369 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
2370 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 2371 | data); |
bc7f75fa AK |
2372 | if (ret_val) |
2373 | return ret_val; | |
2374 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
2375 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 2376 | &data); |
bc7f75fa AK |
2377 | if (ret_val) |
2378 | return ret_val; | |
2379 | ||
2380 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
2381 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, | |
ad68076e | 2382 | data); |
bc7f75fa AK |
2383 | if (ret_val) |
2384 | return ret_val; | |
2385 | } | |
2386 | } | |
2387 | ||
2388 | return 0; | |
2389 | } | |
2390 | ||
2391 | /** | |
2392 | * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state | |
2393 | * @hw: pointer to the HW structure | |
564ea9bb | 2394 | * @active: true to enable LPLU, false to disable |
bc7f75fa AK |
2395 | * |
2396 | * Sets the LPLU D3 state according to the active flag. When | |
2397 | * activating LPLU this function also disables smart speed | |
2398 | * and vice versa. LPLU will not be activated unless the | |
2399 | * device autonegotiation advertisement meets standards of | |
2400 | * either 10 or 10/100 or 10/100/1000 at all duplexes. | |
2401 | * This is a function pointer entry point only called by | |
2402 | * PHY setup routines. | |
2403 | **/ | |
2404 | static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active) | |
2405 | { | |
2406 | struct e1000_phy_info *phy = &hw->phy; | |
2407 | u32 phy_ctrl; | |
d7eb3384 | 2408 | s32 ret_val = 0; |
bc7f75fa AK |
2409 | u16 data; |
2410 | ||
2411 | phy_ctrl = er32(PHY_CTRL); | |
2412 | ||
2413 | if (!active) { | |
2414 | phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; | |
2415 | ew32(PHY_CTRL, phy_ctrl); | |
60f1292f BA |
2416 | |
2417 | if (phy->type != e1000_phy_igp_3) | |
2418 | return 0; | |
2419 | ||
e921eb1a | 2420 | /* LPLU and SmartSpeed are mutually exclusive. LPLU is used |
bc7f75fa AK |
2421 | * during Dx states where the power conservation is most |
2422 | * important. During driver activity we should enable | |
ad68076e BA |
2423 | * SmartSpeed, so performance is maintained. |
2424 | */ | |
bc7f75fa | 2425 | if (phy->smart_speed == e1000_smart_speed_on) { |
ad68076e BA |
2426 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
2427 | &data); | |
bc7f75fa AK |
2428 | if (ret_val) |
2429 | return ret_val; | |
2430 | ||
2431 | data |= IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e BA |
2432 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
2433 | data); | |
bc7f75fa AK |
2434 | if (ret_val) |
2435 | return ret_val; | |
2436 | } else if (phy->smart_speed == e1000_smart_speed_off) { | |
ad68076e BA |
2437 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
2438 | &data); | |
bc7f75fa AK |
2439 | if (ret_val) |
2440 | return ret_val; | |
2441 | ||
2442 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e BA |
2443 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, |
2444 | data); | |
bc7f75fa AK |
2445 | if (ret_val) |
2446 | return ret_val; | |
2447 | } | |
2448 | } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || | |
2449 | (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || | |
2450 | (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { | |
2451 | phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; | |
2452 | ew32(PHY_CTRL, phy_ctrl); | |
2453 | ||
60f1292f BA |
2454 | if (phy->type != e1000_phy_igp_3) |
2455 | return 0; | |
2456 | ||
e921eb1a | 2457 | /* Call gig speed drop workaround on LPLU before accessing |
ad68076e BA |
2458 | * any PHY registers |
2459 | */ | |
60f1292f | 2460 | if (hw->mac.type == e1000_ich8lan) |
bc7f75fa AK |
2461 | e1000e_gig_downshift_workaround_ich8lan(hw); |
2462 | ||
2463 | /* When LPLU is enabled, we should disable SmartSpeed */ | |
ad68076e | 2464 | ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data); |
bc7f75fa AK |
2465 | if (ret_val) |
2466 | return ret_val; | |
2467 | ||
2468 | data &= ~IGP01E1000_PSCFR_SMART_SPEED; | |
ad68076e | 2469 | ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data); |
bc7f75fa AK |
2470 | } |
2471 | ||
d7eb3384 | 2472 | return ret_val; |
bc7f75fa AK |
2473 | } |
2474 | ||
f4187b56 BA |
2475 | /** |
2476 | * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1 | |
2477 | * @hw: pointer to the HW structure | |
2478 | * @bank: pointer to the variable that returns the active bank | |
2479 | * | |
2480 | * Reads signature byte from the NVM using the flash access registers. | |
e243455d | 2481 | * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank. |
f4187b56 BA |
2482 | **/ |
2483 | static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank) | |
2484 | { | |
e243455d | 2485 | u32 eecd; |
f4187b56 | 2486 | struct e1000_nvm_info *nvm = &hw->nvm; |
f4187b56 BA |
2487 | u32 bank1_offset = nvm->flash_bank_size * sizeof(u16); |
2488 | u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1; | |
e243455d | 2489 | u8 sig_byte = 0; |
f71dde6a | 2490 | s32 ret_val; |
f4187b56 | 2491 | |
e243455d BA |
2492 | switch (hw->mac.type) { |
2493 | case e1000_ich8lan: | |
2494 | case e1000_ich9lan: | |
2495 | eecd = er32(EECD); | |
2496 | if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) == | |
2497 | E1000_EECD_SEC1VAL_VALID_MASK) { | |
2498 | if (eecd & E1000_EECD_SEC1VAL) | |
2499 | *bank = 1; | |
2500 | else | |
2501 | *bank = 0; | |
2502 | ||
2503 | return 0; | |
2504 | } | |
434f1392 | 2505 | e_dbg("Unable to determine valid NVM bank via EEC - reading flash signature\n"); |
e243455d BA |
2506 | /* fall-thru */ |
2507 | default: | |
2508 | /* set bank to 0 in case flash read fails */ | |
2509 | *bank = 0; | |
2510 | ||
2511 | /* Check bank 0 */ | |
2512 | ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset, | |
2513 | &sig_byte); | |
2514 | if (ret_val) | |
2515 | return ret_val; | |
2516 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == | |
2517 | E1000_ICH_NVM_SIG_VALUE) { | |
f4187b56 | 2518 | *bank = 0; |
e243455d BA |
2519 | return 0; |
2520 | } | |
f4187b56 | 2521 | |
e243455d BA |
2522 | /* Check bank 1 */ |
2523 | ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset + | |
2524 | bank1_offset, | |
2525 | &sig_byte); | |
2526 | if (ret_val) | |
2527 | return ret_val; | |
2528 | if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) == | |
2529 | E1000_ICH_NVM_SIG_VALUE) { | |
2530 | *bank = 1; | |
2531 | return 0; | |
f4187b56 | 2532 | } |
e243455d | 2533 | |
3bb99fe2 | 2534 | e_dbg("ERROR: No valid NVM bank present\n"); |
e243455d | 2535 | return -E1000_ERR_NVM; |
f4187b56 | 2536 | } |
f4187b56 BA |
2537 | } |
2538 | ||
bc7f75fa AK |
2539 | /** |
2540 | * e1000_read_nvm_ich8lan - Read word(s) from the NVM | |
2541 | * @hw: pointer to the HW structure | |
2542 | * @offset: The offset (in bytes) of the word(s) to read. | |
2543 | * @words: Size of data to read in words | |
2544 | * @data: Pointer to the word(s) to read at offset. | |
2545 | * | |
2546 | * Reads a word(s) from the NVM using the flash access registers. | |
2547 | **/ | |
2548 | static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |
2549 | u16 *data) | |
2550 | { | |
2551 | struct e1000_nvm_info *nvm = &hw->nvm; | |
2552 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
2553 | u32 act_offset; | |
148675a7 | 2554 | s32 ret_val = 0; |
f4187b56 | 2555 | u32 bank = 0; |
bc7f75fa AK |
2556 | u16 i, word; |
2557 | ||
2558 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | |
2559 | (words == 0)) { | |
3bb99fe2 | 2560 | e_dbg("nvm parameter(s) out of bounds\n"); |
ca15df58 BA |
2561 | ret_val = -E1000_ERR_NVM; |
2562 | goto out; | |
bc7f75fa AK |
2563 | } |
2564 | ||
94d8186a | 2565 | nvm->ops.acquire(hw); |
bc7f75fa | 2566 | |
f4187b56 | 2567 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
148675a7 | 2568 | if (ret_val) { |
3bb99fe2 | 2569 | e_dbg("Could not detect valid bank, assuming bank 0\n"); |
148675a7 BA |
2570 | bank = 0; |
2571 | } | |
f4187b56 BA |
2572 | |
2573 | act_offset = (bank) ? nvm->flash_bank_size : 0; | |
bc7f75fa AK |
2574 | act_offset += offset; |
2575 | ||
148675a7 | 2576 | ret_val = 0; |
bc7f75fa | 2577 | for (i = 0; i < words; i++) { |
b9e06f70 | 2578 | if (dev_spec->shadow_ram[offset+i].modified) { |
bc7f75fa AK |
2579 | data[i] = dev_spec->shadow_ram[offset+i].value; |
2580 | } else { | |
2581 | ret_val = e1000_read_flash_word_ich8lan(hw, | |
2582 | act_offset + i, | |
2583 | &word); | |
2584 | if (ret_val) | |
2585 | break; | |
2586 | data[i] = word; | |
2587 | } | |
2588 | } | |
2589 | ||
94d8186a | 2590 | nvm->ops.release(hw); |
bc7f75fa | 2591 | |
e243455d BA |
2592 | out: |
2593 | if (ret_val) | |
3bb99fe2 | 2594 | e_dbg("NVM read error: %d\n", ret_val); |
e243455d | 2595 | |
bc7f75fa AK |
2596 | return ret_val; |
2597 | } | |
2598 | ||
2599 | /** | |
2600 | * e1000_flash_cycle_init_ich8lan - Initialize flash | |
2601 | * @hw: pointer to the HW structure | |
2602 | * | |
2603 | * This function does initial flash setup so that a new read/write/erase cycle | |
2604 | * can be started. | |
2605 | **/ | |
2606 | static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw) | |
2607 | { | |
2608 | union ich8_hws_flash_status hsfsts; | |
2609 | s32 ret_val = -E1000_ERR_NVM; | |
bc7f75fa AK |
2610 | |
2611 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
2612 | ||
2613 | /* Check if the flash descriptor is valid */ | |
04499ec4 | 2614 | if (!hsfsts.hsf_status.fldesvalid) { |
434f1392 | 2615 | e_dbg("Flash descriptor invalid. SW Sequencing must be used.\n"); |
bc7f75fa AK |
2616 | return -E1000_ERR_NVM; |
2617 | } | |
2618 | ||
2619 | /* Clear FCERR and DAEL in hw status by writing 1 */ | |
2620 | hsfsts.hsf_status.flcerr = 1; | |
2621 | hsfsts.hsf_status.dael = 1; | |
2622 | ||
2623 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
2624 | ||
e921eb1a | 2625 | /* Either we should have a hardware SPI cycle in progress |
bc7f75fa AK |
2626 | * bit to check against, in order to start a new cycle or |
2627 | * FDONE bit should be changed in the hardware so that it | |
489815ce | 2628 | * is 1 after hardware reset, which can then be used as an |
bc7f75fa AK |
2629 | * indication whether a cycle is in progress or has been |
2630 | * completed. | |
2631 | */ | |
2632 | ||
04499ec4 | 2633 | if (!hsfsts.hsf_status.flcinprog) { |
e921eb1a | 2634 | /* There is no cycle running at present, |
5ff5b664 | 2635 | * so we can start a cycle. |
ad68076e BA |
2636 | * Begin by setting Flash Cycle Done. |
2637 | */ | |
bc7f75fa AK |
2638 | hsfsts.hsf_status.flcdone = 1; |
2639 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
2640 | ret_val = 0; | |
2641 | } else { | |
f71dde6a | 2642 | s32 i; |
90da0669 | 2643 | |
e921eb1a | 2644 | /* Otherwise poll for sometime so the current |
ad68076e BA |
2645 | * cycle has a chance to end before giving up. |
2646 | */ | |
bc7f75fa | 2647 | for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) { |
c8243ee0 | 2648 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
04499ec4 | 2649 | if (!hsfsts.hsf_status.flcinprog) { |
bc7f75fa AK |
2650 | ret_val = 0; |
2651 | break; | |
2652 | } | |
2653 | udelay(1); | |
2654 | } | |
9e2d7657 | 2655 | if (!ret_val) { |
e921eb1a | 2656 | /* Successful in waiting for previous cycle to timeout, |
ad68076e BA |
2657 | * now set the Flash Cycle Done. |
2658 | */ | |
bc7f75fa AK |
2659 | hsfsts.hsf_status.flcdone = 1; |
2660 | ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
2661 | } else { | |
2c73e1fe | 2662 | e_dbg("Flash controller busy, cannot get access\n"); |
bc7f75fa AK |
2663 | } |
2664 | } | |
2665 | ||
2666 | return ret_val; | |
2667 | } | |
2668 | ||
2669 | /** | |
2670 | * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase) | |
2671 | * @hw: pointer to the HW structure | |
2672 | * @timeout: maximum time to wait for completion | |
2673 | * | |
2674 | * This function starts a flash cycle and waits for its completion. | |
2675 | **/ | |
2676 | static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout) | |
2677 | { | |
2678 | union ich8_hws_flash_ctrl hsflctl; | |
2679 | union ich8_hws_flash_status hsfsts; | |
bc7f75fa AK |
2680 | u32 i = 0; |
2681 | ||
2682 | /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */ | |
2683 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
2684 | hsflctl.hsf_ctrl.flcgo = 1; | |
2685 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
2686 | ||
2687 | /* wait till FDONE bit is set to 1 */ | |
2688 | do { | |
2689 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
04499ec4 | 2690 | if (hsfsts.hsf_status.flcdone) |
bc7f75fa AK |
2691 | break; |
2692 | udelay(1); | |
2693 | } while (i++ < timeout); | |
2694 | ||
04499ec4 | 2695 | if (hsfsts.hsf_status.flcdone && !hsfsts.hsf_status.flcerr) |
bc7f75fa AK |
2696 | return 0; |
2697 | ||
55920b5e | 2698 | return -E1000_ERR_NVM; |
bc7f75fa AK |
2699 | } |
2700 | ||
2701 | /** | |
2702 | * e1000_read_flash_word_ich8lan - Read word from flash | |
2703 | * @hw: pointer to the HW structure | |
2704 | * @offset: offset to data location | |
2705 | * @data: pointer to the location for storing the data | |
2706 | * | |
2707 | * Reads the flash word at offset into data. Offset is converted | |
2708 | * to bytes before read. | |
2709 | **/ | |
2710 | static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset, | |
2711 | u16 *data) | |
2712 | { | |
2713 | /* Must convert offset into bytes. */ | |
2714 | offset <<= 1; | |
2715 | ||
2716 | return e1000_read_flash_data_ich8lan(hw, offset, 2, data); | |
2717 | } | |
2718 | ||
f4187b56 BA |
2719 | /** |
2720 | * e1000_read_flash_byte_ich8lan - Read byte from flash | |
2721 | * @hw: pointer to the HW structure | |
2722 | * @offset: The offset of the byte to read. | |
2723 | * @data: Pointer to a byte to store the value read. | |
2724 | * | |
2725 | * Reads a single byte from the NVM using the flash access registers. | |
2726 | **/ | |
2727 | static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | |
2728 | u8 *data) | |
2729 | { | |
2730 | s32 ret_val; | |
2731 | u16 word = 0; | |
2732 | ||
2733 | ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word); | |
2734 | if (ret_val) | |
2735 | return ret_val; | |
2736 | ||
2737 | *data = (u8)word; | |
2738 | ||
2739 | return 0; | |
2740 | } | |
2741 | ||
bc7f75fa AK |
2742 | /** |
2743 | * e1000_read_flash_data_ich8lan - Read byte or word from NVM | |
2744 | * @hw: pointer to the HW structure | |
2745 | * @offset: The offset (in bytes) of the byte or word to read. | |
2746 | * @size: Size of data to read, 1=byte 2=word | |
2747 | * @data: Pointer to the word to store the value read. | |
2748 | * | |
2749 | * Reads a byte or word from the NVM using the flash access registers. | |
2750 | **/ | |
2751 | static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
2752 | u8 size, u16 *data) | |
2753 | { | |
2754 | union ich8_hws_flash_status hsfsts; | |
2755 | union ich8_hws_flash_ctrl hsflctl; | |
2756 | u32 flash_linear_addr; | |
2757 | u32 flash_data = 0; | |
2758 | s32 ret_val = -E1000_ERR_NVM; | |
2759 | u8 count = 0; | |
2760 | ||
2761 | if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK) | |
2762 | return -E1000_ERR_NVM; | |
2763 | ||
2764 | flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + | |
2765 | hw->nvm.flash_base_addr; | |
2766 | ||
2767 | do { | |
2768 | udelay(1); | |
2769 | /* Steps */ | |
2770 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
9e2d7657 | 2771 | if (ret_val) |
bc7f75fa AK |
2772 | break; |
2773 | ||
2774 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
2775 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | |
2776 | hsflctl.hsf_ctrl.fldbcount = size - 1; | |
2777 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ; | |
2778 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
2779 | ||
2780 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
2781 | ||
2782 | ret_val = e1000_flash_cycle_ich8lan(hw, | |
2783 | ICH_FLASH_READ_COMMAND_TIMEOUT); | |
2784 | ||
e921eb1a | 2785 | /* Check if FCERR is set to 1, if set to 1, clear it |
bc7f75fa AK |
2786 | * and try the whole sequence a few more times, else |
2787 | * read in (shift in) the Flash Data0, the order is | |
ad68076e BA |
2788 | * least significant byte first msb to lsb |
2789 | */ | |
9e2d7657 | 2790 | if (!ret_val) { |
bc7f75fa | 2791 | flash_data = er32flash(ICH_FLASH_FDATA0); |
b1cdfead | 2792 | if (size == 1) |
bc7f75fa | 2793 | *data = (u8)(flash_data & 0x000000FF); |
b1cdfead | 2794 | else if (size == 2) |
bc7f75fa | 2795 | *data = (u16)(flash_data & 0x0000FFFF); |
bc7f75fa AK |
2796 | break; |
2797 | } else { | |
e921eb1a | 2798 | /* If we've gotten here, then things are probably |
bc7f75fa AK |
2799 | * completely hosed, but if the error condition is |
2800 | * detected, it won't hurt to give it another try... | |
2801 | * ICH_FLASH_CYCLE_REPEAT_COUNT times. | |
2802 | */ | |
2803 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
04499ec4 | 2804 | if (hsfsts.hsf_status.flcerr) { |
bc7f75fa AK |
2805 | /* Repeat for some time before giving up. */ |
2806 | continue; | |
04499ec4 | 2807 | } else if (!hsfsts.hsf_status.flcdone) { |
434f1392 | 2808 | e_dbg("Timeout error - flash cycle did not complete.\n"); |
bc7f75fa AK |
2809 | break; |
2810 | } | |
2811 | } | |
2812 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
2813 | ||
2814 | return ret_val; | |
2815 | } | |
2816 | ||
2817 | /** | |
2818 | * e1000_write_nvm_ich8lan - Write word(s) to the NVM | |
2819 | * @hw: pointer to the HW structure | |
2820 | * @offset: The offset (in bytes) of the word(s) to write. | |
2821 | * @words: Size of data to write in words | |
2822 | * @data: Pointer to the word(s) to write at offset. | |
2823 | * | |
2824 | * Writes a byte or word to the NVM using the flash access registers. | |
2825 | **/ | |
2826 | static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words, | |
2827 | u16 *data) | |
2828 | { | |
2829 | struct e1000_nvm_info *nvm = &hw->nvm; | |
2830 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
bc7f75fa AK |
2831 | u16 i; |
2832 | ||
2833 | if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) || | |
2834 | (words == 0)) { | |
3bb99fe2 | 2835 | e_dbg("nvm parameter(s) out of bounds\n"); |
bc7f75fa AK |
2836 | return -E1000_ERR_NVM; |
2837 | } | |
2838 | ||
94d8186a | 2839 | nvm->ops.acquire(hw); |
ca15df58 | 2840 | |
bc7f75fa | 2841 | for (i = 0; i < words; i++) { |
564ea9bb | 2842 | dev_spec->shadow_ram[offset+i].modified = true; |
bc7f75fa AK |
2843 | dev_spec->shadow_ram[offset+i].value = data[i]; |
2844 | } | |
2845 | ||
94d8186a | 2846 | nvm->ops.release(hw); |
ca15df58 | 2847 | |
bc7f75fa AK |
2848 | return 0; |
2849 | } | |
2850 | ||
2851 | /** | |
2852 | * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM | |
2853 | * @hw: pointer to the HW structure | |
2854 | * | |
2855 | * The NVM checksum is updated by calling the generic update_nvm_checksum, | |
2856 | * which writes the checksum to the shadow ram. The changes in the shadow | |
2857 | * ram are then committed to the EEPROM by processing each bank at a time | |
2858 | * checking for the modified bit and writing only the pending changes. | |
489815ce | 2859 | * After a successful commit, the shadow ram is cleared and is ready for |
bc7f75fa AK |
2860 | * future writes. |
2861 | **/ | |
2862 | static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw) | |
2863 | { | |
2864 | struct e1000_nvm_info *nvm = &hw->nvm; | |
2865 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
f4187b56 | 2866 | u32 i, act_offset, new_bank_offset, old_bank_offset, bank; |
bc7f75fa AK |
2867 | s32 ret_val; |
2868 | u16 data; | |
2869 | ||
2870 | ret_val = e1000e_update_nvm_checksum_generic(hw); | |
2871 | if (ret_val) | |
e243455d | 2872 | goto out; |
bc7f75fa AK |
2873 | |
2874 | if (nvm->type != e1000_nvm_flash_sw) | |
e243455d | 2875 | goto out; |
bc7f75fa | 2876 | |
94d8186a | 2877 | nvm->ops.acquire(hw); |
bc7f75fa | 2878 | |
e921eb1a | 2879 | /* We're writing to the opposite bank so if we're on bank 1, |
bc7f75fa | 2880 | * write to bank 0 etc. We also need to erase the segment that |
ad68076e BA |
2881 | * is going to be written |
2882 | */ | |
f4187b56 | 2883 | ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank); |
e243455d | 2884 | if (ret_val) { |
3bb99fe2 | 2885 | e_dbg("Could not detect valid bank, assuming bank 0\n"); |
148675a7 | 2886 | bank = 0; |
e243455d | 2887 | } |
f4187b56 BA |
2888 | |
2889 | if (bank == 0) { | |
bc7f75fa AK |
2890 | new_bank_offset = nvm->flash_bank_size; |
2891 | old_bank_offset = 0; | |
e243455d | 2892 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 1); |
9c5e209d BA |
2893 | if (ret_val) |
2894 | goto release; | |
bc7f75fa AK |
2895 | } else { |
2896 | old_bank_offset = nvm->flash_bank_size; | |
2897 | new_bank_offset = 0; | |
e243455d | 2898 | ret_val = e1000_erase_flash_bank_ich8lan(hw, 0); |
9c5e209d BA |
2899 | if (ret_val) |
2900 | goto release; | |
bc7f75fa AK |
2901 | } |
2902 | ||
2903 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { | |
e921eb1a | 2904 | /* Determine whether to write the value stored |
bc7f75fa | 2905 | * in the other NVM bank or a modified value stored |
ad68076e BA |
2906 | * in the shadow RAM |
2907 | */ | |
bc7f75fa AK |
2908 | if (dev_spec->shadow_ram[i].modified) { |
2909 | data = dev_spec->shadow_ram[i].value; | |
2910 | } else { | |
e243455d BA |
2911 | ret_val = e1000_read_flash_word_ich8lan(hw, i + |
2912 | old_bank_offset, | |
2913 | &data); | |
2914 | if (ret_val) | |
2915 | break; | |
bc7f75fa AK |
2916 | } |
2917 | ||
e921eb1a | 2918 | /* If the word is 0x13, then make sure the signature bits |
bc7f75fa AK |
2919 | * (15:14) are 11b until the commit has completed. |
2920 | * This will allow us to write 10b which indicates the | |
2921 | * signature is valid. We want to do this after the write | |
2922 | * has completed so that we don't mark the segment valid | |
ad68076e BA |
2923 | * while the write is still in progress |
2924 | */ | |
bc7f75fa AK |
2925 | if (i == E1000_ICH_NVM_SIG_WORD) |
2926 | data |= E1000_ICH_NVM_SIG_MASK; | |
2927 | ||
2928 | /* Convert offset to bytes. */ | |
2929 | act_offset = (i + new_bank_offset) << 1; | |
2930 | ||
2931 | udelay(100); | |
2932 | /* Write the bytes to the new bank. */ | |
2933 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
2934 | act_offset, | |
2935 | (u8)data); | |
2936 | if (ret_val) | |
2937 | break; | |
2938 | ||
2939 | udelay(100); | |
2940 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
2941 | act_offset + 1, | |
2942 | (u8)(data >> 8)); | |
2943 | if (ret_val) | |
2944 | break; | |
2945 | } | |
2946 | ||
e921eb1a | 2947 | /* Don't bother writing the segment valid bits if sector |
ad68076e BA |
2948 | * programming failed. |
2949 | */ | |
bc7f75fa | 2950 | if (ret_val) { |
4a770358 | 2951 | /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */ |
3bb99fe2 | 2952 | e_dbg("Flash commit failed.\n"); |
9c5e209d | 2953 | goto release; |
bc7f75fa AK |
2954 | } |
2955 | ||
e921eb1a | 2956 | /* Finally validate the new segment by setting bit 15:14 |
bc7f75fa AK |
2957 | * to 10b in word 0x13 , this can be done without an |
2958 | * erase as well since these bits are 11 to start with | |
ad68076e BA |
2959 | * and we need to change bit 14 to 0b |
2960 | */ | |
bc7f75fa | 2961 | act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD; |
e243455d | 2962 | ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data); |
9c5e209d BA |
2963 | if (ret_val) |
2964 | goto release; | |
2965 | ||
bc7f75fa AK |
2966 | data &= 0xBFFF; |
2967 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, | |
2968 | act_offset * 2 + 1, | |
2969 | (u8)(data >> 8)); | |
9c5e209d BA |
2970 | if (ret_val) |
2971 | goto release; | |
bc7f75fa | 2972 | |
e921eb1a | 2973 | /* And invalidate the previously valid segment by setting |
bc7f75fa AK |
2974 | * its signature word (0x13) high_byte to 0b. This can be |
2975 | * done without an erase because flash erase sets all bits | |
ad68076e BA |
2976 | * to 1's. We can write 1's to 0's without an erase |
2977 | */ | |
bc7f75fa AK |
2978 | act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1; |
2979 | ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0); | |
9c5e209d BA |
2980 | if (ret_val) |
2981 | goto release; | |
bc7f75fa AK |
2982 | |
2983 | /* Great! Everything worked, we can now clear the cached entries. */ | |
2984 | for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) { | |
564ea9bb | 2985 | dev_spec->shadow_ram[i].modified = false; |
bc7f75fa AK |
2986 | dev_spec->shadow_ram[i].value = 0xFFFF; |
2987 | } | |
2988 | ||
9c5e209d | 2989 | release: |
94d8186a | 2990 | nvm->ops.release(hw); |
bc7f75fa | 2991 | |
e921eb1a | 2992 | /* Reload the EEPROM, or else modifications will not appear |
bc7f75fa AK |
2993 | * until after the next adapter reset. |
2994 | */ | |
9c5e209d | 2995 | if (!ret_val) { |
e85e3639 | 2996 | nvm->ops.reload(hw); |
1bba4386 | 2997 | usleep_range(10000, 20000); |
9c5e209d | 2998 | } |
bc7f75fa | 2999 | |
e243455d BA |
3000 | out: |
3001 | if (ret_val) | |
3bb99fe2 | 3002 | e_dbg("NVM update error: %d\n", ret_val); |
e243455d | 3003 | |
bc7f75fa AK |
3004 | return ret_val; |
3005 | } | |
3006 | ||
3007 | /** | |
3008 | * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum | |
3009 | * @hw: pointer to the HW structure | |
3010 | * | |
3011 | * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19. | |
3012 | * If the bit is 0, that the EEPROM had been modified, but the checksum was not | |
3013 | * calculated, in which case we need to calculate the checksum and set bit 6. | |
3014 | **/ | |
3015 | static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw) | |
3016 | { | |
3017 | s32 ret_val; | |
3018 | u16 data; | |
1cc7a3a1 BA |
3019 | u16 word; |
3020 | u16 valid_csum_mask; | |
bc7f75fa | 3021 | |
1cc7a3a1 BA |
3022 | /* Read NVM and check Invalid Image CSUM bit. If this bit is 0, |
3023 | * the checksum needs to be fixed. This bit is an indication that | |
3024 | * the NVM was prepared by OEM software and did not calculate | |
3025 | * the checksum...a likely scenario. | |
bc7f75fa | 3026 | */ |
1cc7a3a1 BA |
3027 | switch (hw->mac.type) { |
3028 | case e1000_pch_lpt: | |
3029 | word = NVM_COMPAT; | |
3030 | valid_csum_mask = NVM_COMPAT_VALID_CSUM; | |
3031 | break; | |
3032 | default: | |
3033 | word = NVM_FUTURE_INIT_WORD1; | |
3034 | valid_csum_mask = NVM_FUTURE_INIT_WORD1_VALID_CSUM; | |
3035 | break; | |
3036 | } | |
3037 | ||
3038 | ret_val = e1000_read_nvm(hw, word, 1, &data); | |
bc7f75fa AK |
3039 | if (ret_val) |
3040 | return ret_val; | |
3041 | ||
1cc7a3a1 BA |
3042 | if (!(data & valid_csum_mask)) { |
3043 | data |= valid_csum_mask; | |
3044 | ret_val = e1000_write_nvm(hw, word, 1, &data); | |
bc7f75fa AK |
3045 | if (ret_val) |
3046 | return ret_val; | |
3047 | ret_val = e1000e_update_nvm_checksum(hw); | |
3048 | if (ret_val) | |
3049 | return ret_val; | |
3050 | } | |
3051 | ||
3052 | return e1000e_validate_nvm_checksum_generic(hw); | |
3053 | } | |
3054 | ||
4a770358 BA |
3055 | /** |
3056 | * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only | |
3057 | * @hw: pointer to the HW structure | |
3058 | * | |
3059 | * To prevent malicious write/erase of the NVM, set it to be read-only | |
3060 | * so that the hardware ignores all write/erase cycles of the NVM via | |
3061 | * the flash control registers. The shadow-ram copy of the NVM will | |
3062 | * still be updated, however any updates to this copy will not stick | |
3063 | * across driver reloads. | |
3064 | **/ | |
3065 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw) | |
3066 | { | |
ca15df58 | 3067 | struct e1000_nvm_info *nvm = &hw->nvm; |
4a770358 BA |
3068 | union ich8_flash_protected_range pr0; |
3069 | union ich8_hws_flash_status hsfsts; | |
3070 | u32 gfpreg; | |
4a770358 | 3071 | |
94d8186a | 3072 | nvm->ops.acquire(hw); |
4a770358 BA |
3073 | |
3074 | gfpreg = er32flash(ICH_FLASH_GFPREG); | |
3075 | ||
3076 | /* Write-protect GbE Sector of NVM */ | |
3077 | pr0.regval = er32flash(ICH_FLASH_PR0); | |
3078 | pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK; | |
3079 | pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK); | |
3080 | pr0.range.wpe = true; | |
3081 | ew32flash(ICH_FLASH_PR0, pr0.regval); | |
3082 | ||
e921eb1a | 3083 | /* Lock down a subset of GbE Flash Control Registers, e.g. |
4a770358 BA |
3084 | * PR0 to prevent the write-protection from being lifted. |
3085 | * Once FLOCKDN is set, the registers protected by it cannot | |
3086 | * be written until FLOCKDN is cleared by a hardware reset. | |
3087 | */ | |
3088 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
3089 | hsfsts.hsf_status.flockdn = true; | |
3090 | ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval); | |
3091 | ||
94d8186a | 3092 | nvm->ops.release(hw); |
4a770358 BA |
3093 | } |
3094 | ||
bc7f75fa AK |
3095 | /** |
3096 | * e1000_write_flash_data_ich8lan - Writes bytes to the NVM | |
3097 | * @hw: pointer to the HW structure | |
3098 | * @offset: The offset (in bytes) of the byte/word to read. | |
3099 | * @size: Size of data to read, 1=byte 2=word | |
3100 | * @data: The byte(s) to write to the NVM. | |
3101 | * | |
3102 | * Writes one/two bytes to the NVM using the flash access registers. | |
3103 | **/ | |
3104 | static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset, | |
3105 | u8 size, u16 data) | |
3106 | { | |
3107 | union ich8_hws_flash_status hsfsts; | |
3108 | union ich8_hws_flash_ctrl hsflctl; | |
3109 | u32 flash_linear_addr; | |
3110 | u32 flash_data = 0; | |
3111 | s32 ret_val; | |
3112 | u8 count = 0; | |
3113 | ||
3114 | if (size < 1 || size > 2 || data > size * 0xff || | |
3115 | offset > ICH_FLASH_LINEAR_ADDR_MASK) | |
3116 | return -E1000_ERR_NVM; | |
3117 | ||
3118 | flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) + | |
3119 | hw->nvm.flash_base_addr; | |
3120 | ||
3121 | do { | |
3122 | udelay(1); | |
3123 | /* Steps */ | |
3124 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
3125 | if (ret_val) | |
3126 | break; | |
3127 | ||
3128 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); | |
3129 | /* 0b/1b corresponds to 1 or 2 byte size, respectively. */ | |
3130 | hsflctl.hsf_ctrl.fldbcount = size -1; | |
3131 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE; | |
3132 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
3133 | ||
3134 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
3135 | ||
3136 | if (size == 1) | |
3137 | flash_data = (u32)data & 0x00FF; | |
3138 | else | |
3139 | flash_data = (u32)data; | |
3140 | ||
3141 | ew32flash(ICH_FLASH_FDATA0, flash_data); | |
3142 | ||
e921eb1a | 3143 | /* check if FCERR is set to 1 , if set to 1, clear it |
ad68076e BA |
3144 | * and try the whole sequence a few more times else done |
3145 | */ | |
bc7f75fa AK |
3146 | ret_val = e1000_flash_cycle_ich8lan(hw, |
3147 | ICH_FLASH_WRITE_COMMAND_TIMEOUT); | |
3148 | if (!ret_val) | |
3149 | break; | |
3150 | ||
e921eb1a | 3151 | /* If we're here, then things are most likely |
bc7f75fa AK |
3152 | * completely hosed, but if the error condition |
3153 | * is detected, it won't hurt to give it another | |
3154 | * try...ICH_FLASH_CYCLE_REPEAT_COUNT times. | |
3155 | */ | |
3156 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
04499ec4 | 3157 | if (hsfsts.hsf_status.flcerr) |
bc7f75fa AK |
3158 | /* Repeat for some time before giving up. */ |
3159 | continue; | |
04499ec4 | 3160 | if (!hsfsts.hsf_status.flcdone) { |
434f1392 | 3161 | e_dbg("Timeout error - flash cycle did not complete.\n"); |
bc7f75fa AK |
3162 | break; |
3163 | } | |
3164 | } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
3165 | ||
3166 | return ret_val; | |
3167 | } | |
3168 | ||
3169 | /** | |
3170 | * e1000_write_flash_byte_ich8lan - Write a single byte to NVM | |
3171 | * @hw: pointer to the HW structure | |
3172 | * @offset: The index of the byte to read. | |
3173 | * @data: The byte to write to the NVM. | |
3174 | * | |
3175 | * Writes a single byte to the NVM using the flash access registers. | |
3176 | **/ | |
3177 | static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset, | |
3178 | u8 data) | |
3179 | { | |
3180 | u16 word = (u16)data; | |
3181 | ||
3182 | return e1000_write_flash_data_ich8lan(hw, offset, 1, word); | |
3183 | } | |
3184 | ||
3185 | /** | |
3186 | * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM | |
3187 | * @hw: pointer to the HW structure | |
3188 | * @offset: The offset of the byte to write. | |
3189 | * @byte: The byte to write to the NVM. | |
3190 | * | |
3191 | * Writes a single byte to the NVM using the flash access registers. | |
3192 | * Goes through a retry algorithm before giving up. | |
3193 | **/ | |
3194 | static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw, | |
3195 | u32 offset, u8 byte) | |
3196 | { | |
3197 | s32 ret_val; | |
3198 | u16 program_retries; | |
3199 | ||
3200 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | |
3201 | if (!ret_val) | |
3202 | return ret_val; | |
3203 | ||
3204 | for (program_retries = 0; program_retries < 100; program_retries++) { | |
3bb99fe2 | 3205 | e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset); |
bc7f75fa AK |
3206 | udelay(100); |
3207 | ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte); | |
3208 | if (!ret_val) | |
3209 | break; | |
3210 | } | |
3211 | if (program_retries == 100) | |
3212 | return -E1000_ERR_NVM; | |
3213 | ||
3214 | return 0; | |
3215 | } | |
3216 | ||
3217 | /** | |
3218 | * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM | |
3219 | * @hw: pointer to the HW structure | |
3220 | * @bank: 0 for first bank, 1 for second bank, etc. | |
3221 | * | |
3222 | * Erases the bank specified. Each bank is a 4k block. Banks are 0 based. | |
3223 | * bank N is 4096 * N + flash_reg_addr. | |
3224 | **/ | |
3225 | static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank) | |
3226 | { | |
3227 | struct e1000_nvm_info *nvm = &hw->nvm; | |
3228 | union ich8_hws_flash_status hsfsts; | |
3229 | union ich8_hws_flash_ctrl hsflctl; | |
3230 | u32 flash_linear_addr; | |
3231 | /* bank size is in 16bit words - adjust to bytes */ | |
3232 | u32 flash_bank_size = nvm->flash_bank_size * 2; | |
3233 | s32 ret_val; | |
3234 | s32 count = 0; | |
a708dd88 | 3235 | s32 j, iteration, sector_size; |
bc7f75fa AK |
3236 | |
3237 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); | |
3238 | ||
e921eb1a | 3239 | /* Determine HW Sector size: Read BERASE bits of hw flash status |
ad68076e BA |
3240 | * register |
3241 | * 00: The Hw sector is 256 bytes, hence we need to erase 16 | |
bc7f75fa AK |
3242 | * consecutive sectors. The start index for the nth Hw sector |
3243 | * can be calculated as = bank * 4096 + n * 256 | |
3244 | * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector. | |
3245 | * The start index for the nth Hw sector can be calculated | |
3246 | * as = bank * 4096 | |
3247 | * 10: The Hw sector is 8K bytes, nth sector = bank * 8192 | |
3248 | * (ich9 only, otherwise error condition) | |
3249 | * 11: The Hw sector is 64K bytes, nth sector = bank * 65536 | |
3250 | */ | |
3251 | switch (hsfsts.hsf_status.berasesz) { | |
3252 | case 0: | |
3253 | /* Hw sector size 256 */ | |
3254 | sector_size = ICH_FLASH_SEG_SIZE_256; | |
3255 | iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256; | |
3256 | break; | |
3257 | case 1: | |
3258 | sector_size = ICH_FLASH_SEG_SIZE_4K; | |
28c9195a | 3259 | iteration = 1; |
bc7f75fa AK |
3260 | break; |
3261 | case 2: | |
148675a7 BA |
3262 | sector_size = ICH_FLASH_SEG_SIZE_8K; |
3263 | iteration = 1; | |
bc7f75fa AK |
3264 | break; |
3265 | case 3: | |
3266 | sector_size = ICH_FLASH_SEG_SIZE_64K; | |
28c9195a | 3267 | iteration = 1; |
bc7f75fa AK |
3268 | break; |
3269 | default: | |
3270 | return -E1000_ERR_NVM; | |
3271 | } | |
3272 | ||
3273 | /* Start with the base address, then add the sector offset. */ | |
3274 | flash_linear_addr = hw->nvm.flash_base_addr; | |
148675a7 | 3275 | flash_linear_addr += (bank) ? flash_bank_size : 0; |
bc7f75fa AK |
3276 | |
3277 | for (j = 0; j < iteration ; j++) { | |
3278 | do { | |
3279 | /* Steps */ | |
3280 | ret_val = e1000_flash_cycle_init_ich8lan(hw); | |
3281 | if (ret_val) | |
3282 | return ret_val; | |
3283 | ||
e921eb1a | 3284 | /* Write a value 11 (block Erase) in Flash |
ad68076e BA |
3285 | * Cycle field in hw flash control |
3286 | */ | |
bc7f75fa AK |
3287 | hsflctl.regval = er16flash(ICH_FLASH_HSFCTL); |
3288 | hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE; | |
3289 | ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval); | |
3290 | ||
e921eb1a | 3291 | /* Write the last 24 bits of an index within the |
bc7f75fa AK |
3292 | * block into Flash Linear address field in Flash |
3293 | * Address. | |
3294 | */ | |
3295 | flash_linear_addr += (j * sector_size); | |
3296 | ew32flash(ICH_FLASH_FADDR, flash_linear_addr); | |
3297 | ||
3298 | ret_val = e1000_flash_cycle_ich8lan(hw, | |
3299 | ICH_FLASH_ERASE_COMMAND_TIMEOUT); | |
9e2d7657 | 3300 | if (!ret_val) |
bc7f75fa AK |
3301 | break; |
3302 | ||
e921eb1a | 3303 | /* Check if FCERR is set to 1. If 1, |
bc7f75fa | 3304 | * clear it and try the whole sequence |
ad68076e BA |
3305 | * a few more times else Done |
3306 | */ | |
bc7f75fa | 3307 | hsfsts.regval = er16flash(ICH_FLASH_HSFSTS); |
04499ec4 | 3308 | if (hsfsts.hsf_status.flcerr) |
ad68076e | 3309 | /* repeat for some time before giving up */ |
bc7f75fa | 3310 | continue; |
04499ec4 | 3311 | else if (!hsfsts.hsf_status.flcdone) |
bc7f75fa AK |
3312 | return ret_val; |
3313 | } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT); | |
3314 | } | |
3315 | ||
3316 | return 0; | |
3317 | } | |
3318 | ||
3319 | /** | |
3320 | * e1000_valid_led_default_ich8lan - Set the default LED settings | |
3321 | * @hw: pointer to the HW structure | |
3322 | * @data: Pointer to the LED settings | |
3323 | * | |
3324 | * Reads the LED default settings from the NVM to data. If the NVM LED | |
3325 | * settings is all 0's or F's, set the LED default to a valid LED default | |
3326 | * setting. | |
3327 | **/ | |
3328 | static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data) | |
3329 | { | |
3330 | s32 ret_val; | |
3331 | ||
3332 | ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); | |
3333 | if (ret_val) { | |
3bb99fe2 | 3334 | e_dbg("NVM Read Error\n"); |
bc7f75fa AK |
3335 | return ret_val; |
3336 | } | |
3337 | ||
3338 | if (*data == ID_LED_RESERVED_0000 || | |
3339 | *data == ID_LED_RESERVED_FFFF) | |
3340 | *data = ID_LED_DEFAULT_ICH8LAN; | |
3341 | ||
3342 | return 0; | |
3343 | } | |
3344 | ||
a4f58f54 BA |
3345 | /** |
3346 | * e1000_id_led_init_pchlan - store LED configurations | |
3347 | * @hw: pointer to the HW structure | |
3348 | * | |
3349 | * PCH does not control LEDs via the LEDCTL register, rather it uses | |
3350 | * the PHY LED configuration register. | |
3351 | * | |
3352 | * PCH also does not have an "always on" or "always off" mode which | |
3353 | * complicates the ID feature. Instead of using the "on" mode to indicate | |
d1964eb1 | 3354 | * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init_generic()), |
a4f58f54 BA |
3355 | * use "link_up" mode. The LEDs will still ID on request if there is no |
3356 | * link based on logic in e1000_led_[on|off]_pchlan(). | |
3357 | **/ | |
3358 | static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw) | |
3359 | { | |
3360 | struct e1000_mac_info *mac = &hw->mac; | |
3361 | s32 ret_val; | |
3362 | const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP; | |
3363 | const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT; | |
3364 | u16 data, i, temp, shift; | |
3365 | ||
3366 | /* Get default ID LED modes */ | |
3367 | ret_val = hw->nvm.ops.valid_led_default(hw, &data); | |
3368 | if (ret_val) | |
5015e53a | 3369 | return ret_val; |
a4f58f54 BA |
3370 | |
3371 | mac->ledctl_default = er32(LEDCTL); | |
3372 | mac->ledctl_mode1 = mac->ledctl_default; | |
3373 | mac->ledctl_mode2 = mac->ledctl_default; | |
3374 | ||
3375 | for (i = 0; i < 4; i++) { | |
3376 | temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK; | |
3377 | shift = (i * 5); | |
3378 | switch (temp) { | |
3379 | case ID_LED_ON1_DEF2: | |
3380 | case ID_LED_ON1_ON2: | |
3381 | case ID_LED_ON1_OFF2: | |
3382 | mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); | |
3383 | mac->ledctl_mode1 |= (ledctl_on << shift); | |
3384 | break; | |
3385 | case ID_LED_OFF1_DEF2: | |
3386 | case ID_LED_OFF1_ON2: | |
3387 | case ID_LED_OFF1_OFF2: | |
3388 | mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift); | |
3389 | mac->ledctl_mode1 |= (ledctl_off << shift); | |
3390 | break; | |
3391 | default: | |
3392 | /* Do nothing */ | |
3393 | break; | |
3394 | } | |
3395 | switch (temp) { | |
3396 | case ID_LED_DEF1_ON2: | |
3397 | case ID_LED_ON1_ON2: | |
3398 | case ID_LED_OFF1_ON2: | |
3399 | mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); | |
3400 | mac->ledctl_mode2 |= (ledctl_on << shift); | |
3401 | break; | |
3402 | case ID_LED_DEF1_OFF2: | |
3403 | case ID_LED_ON1_OFF2: | |
3404 | case ID_LED_OFF1_OFF2: | |
3405 | mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift); | |
3406 | mac->ledctl_mode2 |= (ledctl_off << shift); | |
3407 | break; | |
3408 | default: | |
3409 | /* Do nothing */ | |
3410 | break; | |
3411 | } | |
3412 | } | |
3413 | ||
5015e53a | 3414 | return 0; |
a4f58f54 BA |
3415 | } |
3416 | ||
bc7f75fa AK |
3417 | /** |
3418 | * e1000_get_bus_info_ich8lan - Get/Set the bus type and width | |
3419 | * @hw: pointer to the HW structure | |
3420 | * | |
3421 | * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability | |
3422 | * register, so the the bus width is hard coded. | |
3423 | **/ | |
3424 | static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw) | |
3425 | { | |
3426 | struct e1000_bus_info *bus = &hw->bus; | |
3427 | s32 ret_val; | |
3428 | ||
3429 | ret_val = e1000e_get_bus_info_pcie(hw); | |
3430 | ||
e921eb1a | 3431 | /* ICH devices are "PCI Express"-ish. They have |
bc7f75fa AK |
3432 | * a configuration space, but do not contain |
3433 | * PCI Express Capability registers, so bus width | |
3434 | * must be hardcoded. | |
3435 | */ | |
3436 | if (bus->width == e1000_bus_width_unknown) | |
3437 | bus->width = e1000_bus_width_pcie_x1; | |
3438 | ||
3439 | return ret_val; | |
3440 | } | |
3441 | ||
3442 | /** | |
3443 | * e1000_reset_hw_ich8lan - Reset the hardware | |
3444 | * @hw: pointer to the HW structure | |
3445 | * | |
3446 | * Does a full reset of the hardware which includes a reset of the PHY and | |
3447 | * MAC. | |
3448 | **/ | |
3449 | static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) | |
3450 | { | |
1d5846b9 | 3451 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
62bc813e BA |
3452 | u16 kum_cfg; |
3453 | u32 ctrl, reg; | |
bc7f75fa AK |
3454 | s32 ret_val; |
3455 | ||
e921eb1a | 3456 | /* Prevent the PCI-E bus from sticking if there is no TLP connection |
bc7f75fa AK |
3457 | * on the last TLP read/write transaction when MAC is reset. |
3458 | */ | |
3459 | ret_val = e1000e_disable_pcie_master(hw); | |
e98cac44 | 3460 | if (ret_val) |
3bb99fe2 | 3461 | e_dbg("PCI-E Master disable polling has failed.\n"); |
bc7f75fa | 3462 | |
3bb99fe2 | 3463 | e_dbg("Masking off all interrupts\n"); |
bc7f75fa AK |
3464 | ew32(IMC, 0xffffffff); |
3465 | ||
e921eb1a | 3466 | /* Disable the Transmit and Receive units. Then delay to allow |
bc7f75fa AK |
3467 | * any pending transactions to complete before we hit the MAC |
3468 | * with the global reset. | |
3469 | */ | |
3470 | ew32(RCTL, 0); | |
3471 | ew32(TCTL, E1000_TCTL_PSP); | |
3472 | e1e_flush(); | |
3473 | ||
1bba4386 | 3474 | usleep_range(10000, 20000); |
bc7f75fa AK |
3475 | |
3476 | /* Workaround for ICH8 bit corruption issue in FIFO memory */ | |
3477 | if (hw->mac.type == e1000_ich8lan) { | |
3478 | /* Set Tx and Rx buffer allocation to 8k apiece. */ | |
3479 | ew32(PBA, E1000_PBA_8K); | |
3480 | /* Set Packet Buffer Size to 16k. */ | |
3481 | ew32(PBS, E1000_PBS_16K); | |
3482 | } | |
3483 | ||
1d5846b9 | 3484 | if (hw->mac.type == e1000_pchlan) { |
62bc813e BA |
3485 | /* Save the NVM K1 bit setting */ |
3486 | ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); | |
1d5846b9 BA |
3487 | if (ret_val) |
3488 | return ret_val; | |
3489 | ||
62bc813e | 3490 | if (kum_cfg & E1000_NVM_K1_ENABLE) |
1d5846b9 BA |
3491 | dev_spec->nvm_k1_enabled = true; |
3492 | else | |
3493 | dev_spec->nvm_k1_enabled = false; | |
3494 | } | |
3495 | ||
bc7f75fa AK |
3496 | ctrl = er32(CTRL); |
3497 | ||
44abd5c1 | 3498 | if (!hw->phy.ops.check_reset_block(hw)) { |
e921eb1a | 3499 | /* Full-chip reset requires MAC and PHY reset at the same |
bc7f75fa AK |
3500 | * time to make sure the interface between MAC and the |
3501 | * external PHY is reset. | |
3502 | */ | |
3503 | ctrl |= E1000_CTRL_PHY_RST; | |
605c82ba | 3504 | |
e921eb1a | 3505 | /* Gate automatic PHY configuration by hardware on |
605c82ba BA |
3506 | * non-managed 82579 |
3507 | */ | |
3508 | if ((hw->mac.type == e1000_pch2lan) && | |
3509 | !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) | |
3510 | e1000_gate_hw_phy_config_ich8lan(hw, true); | |
bc7f75fa AK |
3511 | } |
3512 | ret_val = e1000_acquire_swflag_ich8lan(hw); | |
3bb99fe2 | 3513 | e_dbg("Issuing a global reset to ich8lan\n"); |
bc7f75fa | 3514 | ew32(CTRL, (ctrl | E1000_CTRL_RST)); |
945a5151 | 3515 | /* cannot issue a flush here because it hangs the hardware */ |
bc7f75fa AK |
3516 | msleep(20); |
3517 | ||
62bc813e BA |
3518 | /* Set Phy Config Counter to 50msec */ |
3519 | if (hw->mac.type == e1000_pch2lan) { | |
3520 | reg = er32(FEXTNVM3); | |
3521 | reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; | |
3522 | reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; | |
3523 | ew32(FEXTNVM3, reg); | |
3524 | } | |
3525 | ||
fc0c7760 | 3526 | if (!ret_val) |
a90b412c | 3527 | clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); |
37f40239 | 3528 | |
e98cac44 | 3529 | if (ctrl & E1000_CTRL_PHY_RST) { |
fc0c7760 | 3530 | ret_val = hw->phy.ops.get_cfg_done(hw); |
e98cac44 | 3531 | if (ret_val) |
5015e53a | 3532 | return ret_val; |
fc0c7760 | 3533 | |
e98cac44 | 3534 | ret_val = e1000_post_phy_reset_ich8lan(hw); |
f523d211 | 3535 | if (ret_val) |
5015e53a | 3536 | return ret_val; |
f523d211 | 3537 | } |
e98cac44 | 3538 | |
e921eb1a | 3539 | /* For PCH, this write will make sure that any noise |
7d3cabbc BA |
3540 | * will be detected as a CRC error and be dropped rather than show up |
3541 | * as a bad packet to the DMA engine. | |
3542 | */ | |
3543 | if (hw->mac.type == e1000_pchlan) | |
3544 | ew32(CRC_OFFSET, 0x65656565); | |
3545 | ||
bc7f75fa | 3546 | ew32(IMC, 0xffffffff); |
dd93f95e | 3547 | er32(ICR); |
bc7f75fa | 3548 | |
62bc813e BA |
3549 | reg = er32(KABGTXD); |
3550 | reg |= E1000_KABGTXD_BGSQLBIAS; | |
3551 | ew32(KABGTXD, reg); | |
bc7f75fa | 3552 | |
5015e53a | 3553 | return 0; |
bc7f75fa AK |
3554 | } |
3555 | ||
3556 | /** | |
3557 | * e1000_init_hw_ich8lan - Initialize the hardware | |
3558 | * @hw: pointer to the HW structure | |
3559 | * | |
3560 | * Prepares the hardware for transmit and receive by doing the following: | |
3561 | * - initialize hardware bits | |
3562 | * - initialize LED identification | |
3563 | * - setup receive address registers | |
3564 | * - setup flow control | |
489815ce | 3565 | * - setup transmit descriptors |
bc7f75fa AK |
3566 | * - clear statistics |
3567 | **/ | |
3568 | static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw) | |
3569 | { | |
3570 | struct e1000_mac_info *mac = &hw->mac; | |
3571 | u32 ctrl_ext, txdctl, snoop; | |
3572 | s32 ret_val; | |
3573 | u16 i; | |
3574 | ||
3575 | e1000_initialize_hw_bits_ich8lan(hw); | |
3576 | ||
3577 | /* Initialize identification LED */ | |
a4f58f54 | 3578 | ret_val = mac->ops.id_led_init(hw); |
de39b752 | 3579 | if (ret_val) |
3bb99fe2 | 3580 | e_dbg("Error initializing identification LED\n"); |
de39b752 | 3581 | /* This is not fatal and we should not stop init due to this */ |
bc7f75fa AK |
3582 | |
3583 | /* Setup the receive address. */ | |
3584 | e1000e_init_rx_addrs(hw, mac->rar_entry_count); | |
3585 | ||
3586 | /* Zero out the Multicast HASH table */ | |
3bb99fe2 | 3587 | e_dbg("Zeroing the MTA\n"); |
bc7f75fa AK |
3588 | for (i = 0; i < mac->mta_reg_count; i++) |
3589 | E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); | |
3590 | ||
e921eb1a | 3591 | /* The 82578 Rx buffer will stall if wakeup is enabled in host and |
3ebfc7c9 | 3592 | * the ME. Disable wakeup by clearing the host wakeup bit. |
fc0c7760 BA |
3593 | * Reset the phy after disabling host wakeup to reset the Rx buffer. |
3594 | */ | |
3595 | if (hw->phy.type == e1000_phy_82578) { | |
3ebfc7c9 BA |
3596 | e1e_rphy(hw, BM_PORT_GEN_CFG, &i); |
3597 | i &= ~BM_WUC_HOST_WU_BIT; | |
3598 | e1e_wphy(hw, BM_PORT_GEN_CFG, i); | |
fc0c7760 BA |
3599 | ret_val = e1000_phy_hw_reset_ich8lan(hw); |
3600 | if (ret_val) | |
3601 | return ret_val; | |
3602 | } | |
3603 | ||
bc7f75fa | 3604 | /* Setup link and flow control */ |
1a46b40f | 3605 | ret_val = mac->ops.setup_link(hw); |
bc7f75fa AK |
3606 | |
3607 | /* Set the transmit descriptor write-back policy for both queues */ | |
e9ec2c0f | 3608 | txdctl = er32(TXDCTL(0)); |
bc7f75fa AK |
3609 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
3610 | E1000_TXDCTL_FULL_TX_DESC_WB; | |
3611 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | | |
3612 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; | |
e9ec2c0f JK |
3613 | ew32(TXDCTL(0), txdctl); |
3614 | txdctl = er32(TXDCTL(1)); | |
bc7f75fa AK |
3615 | txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | |
3616 | E1000_TXDCTL_FULL_TX_DESC_WB; | |
3617 | txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) | | |
3618 | E1000_TXDCTL_MAX_TX_DESC_PREFETCH; | |
e9ec2c0f | 3619 | ew32(TXDCTL(1), txdctl); |
bc7f75fa | 3620 | |
e921eb1a | 3621 | /* ICH8 has opposite polarity of no_snoop bits. |
ad68076e BA |
3622 | * By default, we should use snoop behavior. |
3623 | */ | |
bc7f75fa AK |
3624 | if (mac->type == e1000_ich8lan) |
3625 | snoop = PCIE_ICH8_SNOOP_ALL; | |
3626 | else | |
3627 | snoop = (u32) ~(PCIE_NO_SNOOP_ALL); | |
3628 | e1000e_set_pcie_no_snoop(hw, snoop); | |
3629 | ||
3630 | ctrl_ext = er32(CTRL_EXT); | |
3631 | ctrl_ext |= E1000_CTRL_EXT_RO_DIS; | |
3632 | ew32(CTRL_EXT, ctrl_ext); | |
3633 | ||
e921eb1a | 3634 | /* Clear all of the statistics registers (clear on read). It is |
bc7f75fa AK |
3635 | * important that we do this after we have tried to establish link |
3636 | * because the symbol error count will increment wildly if there | |
3637 | * is no link. | |
3638 | */ | |
3639 | e1000_clear_hw_cntrs_ich8lan(hw); | |
3640 | ||
e561a705 | 3641 | return ret_val; |
bc7f75fa AK |
3642 | } |
3643 | /** | |
3644 | * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits | |
3645 | * @hw: pointer to the HW structure | |
3646 | * | |
3647 | * Sets/Clears required hardware bits necessary for correctly setting up the | |
3648 | * hardware for transmit and receive. | |
3649 | **/ | |
3650 | static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw) | |
3651 | { | |
3652 | u32 reg; | |
3653 | ||
3654 | /* Extended Device Control */ | |
3655 | reg = er32(CTRL_EXT); | |
3656 | reg |= (1 << 22); | |
a4f58f54 BA |
3657 | /* Enable PHY low-power state when MAC is at D3 w/o WoL */ |
3658 | if (hw->mac.type >= e1000_pchlan) | |
3659 | reg |= E1000_CTRL_EXT_PHYPDEN; | |
bc7f75fa AK |
3660 | ew32(CTRL_EXT, reg); |
3661 | ||
3662 | /* Transmit Descriptor Control 0 */ | |
e9ec2c0f | 3663 | reg = er32(TXDCTL(0)); |
bc7f75fa | 3664 | reg |= (1 << 22); |
e9ec2c0f | 3665 | ew32(TXDCTL(0), reg); |
bc7f75fa AK |
3666 | |
3667 | /* Transmit Descriptor Control 1 */ | |
e9ec2c0f | 3668 | reg = er32(TXDCTL(1)); |
bc7f75fa | 3669 | reg |= (1 << 22); |
e9ec2c0f | 3670 | ew32(TXDCTL(1), reg); |
bc7f75fa AK |
3671 | |
3672 | /* Transmit Arbitration Control 0 */ | |
e9ec2c0f | 3673 | reg = er32(TARC(0)); |
bc7f75fa AK |
3674 | if (hw->mac.type == e1000_ich8lan) |
3675 | reg |= (1 << 28) | (1 << 29); | |
3676 | reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27); | |
e9ec2c0f | 3677 | ew32(TARC(0), reg); |
bc7f75fa AK |
3678 | |
3679 | /* Transmit Arbitration Control 1 */ | |
e9ec2c0f | 3680 | reg = er32(TARC(1)); |
bc7f75fa AK |
3681 | if (er32(TCTL) & E1000_TCTL_MULR) |
3682 | reg &= ~(1 << 28); | |
3683 | else | |
3684 | reg |= (1 << 28); | |
3685 | reg |= (1 << 24) | (1 << 26) | (1 << 30); | |
e9ec2c0f | 3686 | ew32(TARC(1), reg); |
bc7f75fa AK |
3687 | |
3688 | /* Device Status */ | |
3689 | if (hw->mac.type == e1000_ich8lan) { | |
3690 | reg = er32(STATUS); | |
3691 | reg &= ~(1 << 31); | |
3692 | ew32(STATUS, reg); | |
3693 | } | |
a80483d3 | 3694 | |
e921eb1a | 3695 | /* work-around descriptor data corruption issue during nfs v2 udp |
a80483d3 JB |
3696 | * traffic, just disable the nfs filtering capability |
3697 | */ | |
3698 | reg = er32(RFCTL); | |
3699 | reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS); | |
f6bd5577 | 3700 | |
e921eb1a | 3701 | /* Disable IPv6 extension header parsing because some malformed |
f6bd5577 MV |
3702 | * IPv6 headers can hang the Rx. |
3703 | */ | |
3704 | if (hw->mac.type == e1000_ich8lan) | |
3705 | reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS); | |
a80483d3 | 3706 | ew32(RFCTL, reg); |
bc7f75fa AK |
3707 | } |
3708 | ||
3709 | /** | |
3710 | * e1000_setup_link_ich8lan - Setup flow control and link settings | |
3711 | * @hw: pointer to the HW structure | |
3712 | * | |
3713 | * Determines which flow control settings to use, then configures flow | |
3714 | * control. Calls the appropriate media-specific link configuration | |
3715 | * function. Assuming the adapter has a valid link partner, a valid link | |
3716 | * should be established. Assumes the hardware has previously been reset | |
3717 | * and the transmitter and receiver are not enabled. | |
3718 | **/ | |
3719 | static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw) | |
3720 | { | |
bc7f75fa AK |
3721 | s32 ret_val; |
3722 | ||
44abd5c1 | 3723 | if (hw->phy.ops.check_reset_block(hw)) |
bc7f75fa AK |
3724 | return 0; |
3725 | ||
e921eb1a | 3726 | /* ICH parts do not have a word in the NVM to determine |
bc7f75fa AK |
3727 | * the default flow control setting, so we explicitly |
3728 | * set it to full. | |
3729 | */ | |
37289d9c BA |
3730 | if (hw->fc.requested_mode == e1000_fc_default) { |
3731 | /* Workaround h/w hang when Tx flow control enabled */ | |
3732 | if (hw->mac.type == e1000_pchlan) | |
3733 | hw->fc.requested_mode = e1000_fc_rx_pause; | |
3734 | else | |
3735 | hw->fc.requested_mode = e1000_fc_full; | |
3736 | } | |
bc7f75fa | 3737 | |
e921eb1a | 3738 | /* Save off the requested flow control mode for use later. Depending |
5c48ef3e BA |
3739 | * on the link partner's capabilities, we may or may not use this mode. |
3740 | */ | |
3741 | hw->fc.current_mode = hw->fc.requested_mode; | |
bc7f75fa | 3742 | |
3bb99fe2 | 3743 | e_dbg("After fix-ups FlowControl is now = %x\n", |
5c48ef3e | 3744 | hw->fc.current_mode); |
bc7f75fa AK |
3745 | |
3746 | /* Continue to configure the copper link. */ | |
944ce011 | 3747 | ret_val = hw->mac.ops.setup_physical_interface(hw); |
bc7f75fa AK |
3748 | if (ret_val) |
3749 | return ret_val; | |
3750 | ||
318a94d6 | 3751 | ew32(FCTTV, hw->fc.pause_time); |
a4f58f54 | 3752 | if ((hw->phy.type == e1000_phy_82578) || |
d3738bb8 | 3753 | (hw->phy.type == e1000_phy_82579) || |
2fbe4526 | 3754 | (hw->phy.type == e1000_phy_i217) || |
a4f58f54 | 3755 | (hw->phy.type == e1000_phy_82577)) { |
a305595b BA |
3756 | ew32(FCRTV_PCH, hw->fc.refresh_time); |
3757 | ||
482fed85 BA |
3758 | ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27), |
3759 | hw->fc.pause_time); | |
a4f58f54 BA |
3760 | if (ret_val) |
3761 | return ret_val; | |
3762 | } | |
bc7f75fa AK |
3763 | |
3764 | return e1000e_set_fc_watermarks(hw); | |
3765 | } | |
3766 | ||
3767 | /** | |
3768 | * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface | |
3769 | * @hw: pointer to the HW structure | |
3770 | * | |
3771 | * Configures the kumeran interface to the PHY to wait the appropriate time | |
3772 | * when polling the PHY, then call the generic setup_copper_link to finish | |
3773 | * configuring the copper link. | |
3774 | **/ | |
3775 | static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw) | |
3776 | { | |
3777 | u32 ctrl; | |
3778 | s32 ret_val; | |
3779 | u16 reg_data; | |
3780 | ||
3781 | ctrl = er32(CTRL); | |
3782 | ctrl |= E1000_CTRL_SLU; | |
3783 | ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); | |
3784 | ew32(CTRL, ctrl); | |
3785 | ||
e921eb1a | 3786 | /* Set the mac to wait the maximum time between each iteration |
bc7f75fa | 3787 | * and increase the max iterations when polling the phy; |
ad68076e BA |
3788 | * this fixes erroneous timeouts at 10Mbps. |
3789 | */ | |
07818950 | 3790 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF); |
bc7f75fa AK |
3791 | if (ret_val) |
3792 | return ret_val; | |
07818950 BA |
3793 | ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, |
3794 | ®_data); | |
bc7f75fa AK |
3795 | if (ret_val) |
3796 | return ret_val; | |
3797 | reg_data |= 0x3F; | |
07818950 BA |
3798 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM, |
3799 | reg_data); | |
bc7f75fa AK |
3800 | if (ret_val) |
3801 | return ret_val; | |
3802 | ||
a4f58f54 BA |
3803 | switch (hw->phy.type) { |
3804 | case e1000_phy_igp_3: | |
bc7f75fa AK |
3805 | ret_val = e1000e_copper_link_setup_igp(hw); |
3806 | if (ret_val) | |
3807 | return ret_val; | |
a4f58f54 BA |
3808 | break; |
3809 | case e1000_phy_bm: | |
3810 | case e1000_phy_82578: | |
97ac8cae BA |
3811 | ret_val = e1000e_copper_link_setup_m88(hw); |
3812 | if (ret_val) | |
3813 | return ret_val; | |
a4f58f54 BA |
3814 | break; |
3815 | case e1000_phy_82577: | |
d3738bb8 | 3816 | case e1000_phy_82579: |
2fbe4526 | 3817 | case e1000_phy_i217: |
a4f58f54 BA |
3818 | ret_val = e1000_copper_link_setup_82577(hw); |
3819 | if (ret_val) | |
3820 | return ret_val; | |
3821 | break; | |
3822 | case e1000_phy_ife: | |
482fed85 | 3823 | ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data); |
97ac8cae BA |
3824 | if (ret_val) |
3825 | return ret_val; | |
3826 | ||
3827 | reg_data &= ~IFE_PMC_AUTO_MDIX; | |
3828 | ||
3829 | switch (hw->phy.mdix) { | |
3830 | case 1: | |
3831 | reg_data &= ~IFE_PMC_FORCE_MDIX; | |
3832 | break; | |
3833 | case 2: | |
3834 | reg_data |= IFE_PMC_FORCE_MDIX; | |
3835 | break; | |
3836 | case 0: | |
3837 | default: | |
3838 | reg_data |= IFE_PMC_AUTO_MDIX; | |
3839 | break; | |
3840 | } | |
482fed85 | 3841 | ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data); |
97ac8cae BA |
3842 | if (ret_val) |
3843 | return ret_val; | |
a4f58f54 BA |
3844 | break; |
3845 | default: | |
3846 | break; | |
97ac8cae | 3847 | } |
3fa82936 | 3848 | |
bc7f75fa AK |
3849 | return e1000e_setup_copper_link(hw); |
3850 | } | |
3851 | ||
3852 | /** | |
3853 | * e1000_get_link_up_info_ich8lan - Get current link speed and duplex | |
3854 | * @hw: pointer to the HW structure | |
3855 | * @speed: pointer to store current link speed | |
3856 | * @duplex: pointer to store the current link duplex | |
3857 | * | |
ad68076e | 3858 | * Calls the generic get_speed_and_duplex to retrieve the current link |
bc7f75fa AK |
3859 | * information and then calls the Kumeran lock loss workaround for links at |
3860 | * gigabit speeds. | |
3861 | **/ | |
3862 | static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed, | |
3863 | u16 *duplex) | |
3864 | { | |
3865 | s32 ret_val; | |
3866 | ||
3867 | ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex); | |
3868 | if (ret_val) | |
3869 | return ret_val; | |
3870 | ||
3871 | if ((hw->mac.type == e1000_ich8lan) && | |
3872 | (hw->phy.type == e1000_phy_igp_3) && | |
3873 | (*speed == SPEED_1000)) { | |
3874 | ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw); | |
3875 | } | |
3876 | ||
3877 | return ret_val; | |
3878 | } | |
3879 | ||
3880 | /** | |
3881 | * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround | |
3882 | * @hw: pointer to the HW structure | |
3883 | * | |
3884 | * Work-around for 82566 Kumeran PCS lock loss: | |
3885 | * On link status change (i.e. PCI reset, speed change) and link is up and | |
3886 | * speed is gigabit- | |
3887 | * 0) if workaround is optionally disabled do nothing | |
3888 | * 1) wait 1ms for Kumeran link to come up | |
3889 | * 2) check Kumeran Diagnostic register PCS lock loss bit | |
3890 | * 3) if not set the link is locked (all is good), otherwise... | |
3891 | * 4) reset the PHY | |
3892 | * 5) repeat up to 10 times | |
3893 | * Note: this is only called for IGP3 copper when speed is 1gb. | |
3894 | **/ | |
3895 | static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw) | |
3896 | { | |
3897 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
3898 | u32 phy_ctrl; | |
3899 | s32 ret_val; | |
3900 | u16 i, data; | |
3901 | bool link; | |
3902 | ||
3903 | if (!dev_spec->kmrn_lock_loss_workaround_enabled) | |
3904 | return 0; | |
3905 | ||
e921eb1a | 3906 | /* Make sure link is up before proceeding. If not just return. |
bc7f75fa | 3907 | * Attempting this while link is negotiating fouled up link |
ad68076e BA |
3908 | * stability |
3909 | */ | |
bc7f75fa AK |
3910 | ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); |
3911 | if (!link) | |
3912 | return 0; | |
3913 | ||
3914 | for (i = 0; i < 10; i++) { | |
3915 | /* read once to clear */ | |
3916 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); | |
3917 | if (ret_val) | |
3918 | return ret_val; | |
3919 | /* and again to get new status */ | |
3920 | ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data); | |
3921 | if (ret_val) | |
3922 | return ret_val; | |
3923 | ||
3924 | /* check for PCS lock */ | |
3925 | if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS)) | |
3926 | return 0; | |
3927 | ||
3928 | /* Issue PHY reset */ | |
3929 | e1000_phy_hw_reset(hw); | |
3930 | mdelay(5); | |
3931 | } | |
3932 | /* Disable GigE link negotiation */ | |
3933 | phy_ctrl = er32(PHY_CTRL); | |
3934 | phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE | | |
3935 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
3936 | ew32(PHY_CTRL, phy_ctrl); | |
3937 | ||
e921eb1a | 3938 | /* Call gig speed drop workaround on Gig disable before accessing |
ad68076e BA |
3939 | * any PHY registers |
3940 | */ | |
bc7f75fa AK |
3941 | e1000e_gig_downshift_workaround_ich8lan(hw); |
3942 | ||
3943 | /* unable to acquire PCS lock */ | |
3944 | return -E1000_ERR_PHY; | |
3945 | } | |
3946 | ||
3947 | /** | |
6e3c8075 | 3948 | * e1000e_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state |
bc7f75fa | 3949 | * @hw: pointer to the HW structure |
489815ce | 3950 | * @state: boolean value used to set the current Kumeran workaround state |
bc7f75fa | 3951 | * |
564ea9bb BA |
3952 | * If ICH8, set the current Kumeran workaround state (enabled - true |
3953 | * /disabled - false). | |
bc7f75fa AK |
3954 | **/ |
3955 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, | |
3956 | bool state) | |
3957 | { | |
3958 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; | |
3959 | ||
3960 | if (hw->mac.type != e1000_ich8lan) { | |
3bb99fe2 | 3961 | e_dbg("Workaround applies to ICH8 only.\n"); |
bc7f75fa AK |
3962 | return; |
3963 | } | |
3964 | ||
3965 | dev_spec->kmrn_lock_loss_workaround_enabled = state; | |
3966 | } | |
3967 | ||
3968 | /** | |
3969 | * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3 | |
3970 | * @hw: pointer to the HW structure | |
3971 | * | |
3972 | * Workaround for 82566 power-down on D3 entry: | |
3973 | * 1) disable gigabit link | |
3974 | * 2) write VR power-down enable | |
3975 | * 3) read it back | |
3976 | * Continue if successful, else issue LCD reset and repeat | |
3977 | **/ | |
3978 | void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw) | |
3979 | { | |
3980 | u32 reg; | |
3981 | u16 data; | |
3982 | u8 retry = 0; | |
3983 | ||
3984 | if (hw->phy.type != e1000_phy_igp_3) | |
3985 | return; | |
3986 | ||
3987 | /* Try the workaround twice (if needed) */ | |
3988 | do { | |
3989 | /* Disable link */ | |
3990 | reg = er32(PHY_CTRL); | |
3991 | reg |= (E1000_PHY_CTRL_GBE_DISABLE | | |
3992 | E1000_PHY_CTRL_NOND0A_GBE_DISABLE); | |
3993 | ew32(PHY_CTRL, reg); | |
3994 | ||
e921eb1a | 3995 | /* Call gig speed drop workaround on Gig disable before |
ad68076e BA |
3996 | * accessing any PHY registers |
3997 | */ | |
bc7f75fa AK |
3998 | if (hw->mac.type == e1000_ich8lan) |
3999 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
4000 | ||
4001 | /* Write VR power-down enable */ | |
4002 | e1e_rphy(hw, IGP3_VR_CTRL, &data); | |
4003 | data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; | |
4004 | e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN); | |
4005 | ||
4006 | /* Read it back and test */ | |
4007 | e1e_rphy(hw, IGP3_VR_CTRL, &data); | |
4008 | data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK; | |
4009 | if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry) | |
4010 | break; | |
4011 | ||
4012 | /* Issue PHY reset and repeat at most one more time */ | |
4013 | reg = er32(CTRL); | |
4014 | ew32(CTRL, reg | E1000_CTRL_PHY_RST); | |
4015 | retry++; | |
4016 | } while (retry); | |
4017 | } | |
4018 | ||
4019 | /** | |
4020 | * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working | |
4021 | * @hw: pointer to the HW structure | |
4022 | * | |
4023 | * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC), | |
489815ce | 4024 | * LPLU, Gig disable, MDIC PHY reset): |
bc7f75fa AK |
4025 | * 1) Set Kumeran Near-end loopback |
4026 | * 2) Clear Kumeran Near-end loopback | |
462d5994 | 4027 | * Should only be called for ICH8[m] devices with any 1G Phy. |
bc7f75fa AK |
4028 | **/ |
4029 | void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw) | |
4030 | { | |
4031 | s32 ret_val; | |
4032 | u16 reg_data; | |
4033 | ||
462d5994 | 4034 | if ((hw->mac.type != e1000_ich8lan) || (hw->phy.type == e1000_phy_ife)) |
bc7f75fa AK |
4035 | return; |
4036 | ||
4037 | ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
4038 | ®_data); | |
4039 | if (ret_val) | |
4040 | return; | |
4041 | reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK; | |
4042 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
4043 | reg_data); | |
4044 | if (ret_val) | |
4045 | return; | |
4046 | reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK; | |
4047 | ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET, | |
4048 | reg_data); | |
4049 | } | |
4050 | ||
97ac8cae | 4051 | /** |
99730e4c | 4052 | * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx |
97ac8cae BA |
4053 | * @hw: pointer to the HW structure |
4054 | * | |
4055 | * During S0 to Sx transition, it is possible the link remains at gig | |
4056 | * instead of negotiating to a lower speed. Before going to Sx, set | |
c077a906 BA |
4057 | * 'Gig Disable' to force link speed negotiation to a lower speed based on |
4058 | * the LPLU setting in the NVM or custom setting. For PCH and newer parts, | |
4059 | * the OEM bits PHY register (LED, GbE disable and LPLU configurations) also | |
4060 | * needs to be written. | |
2fbe4526 BA |
4061 | * Parts that support (and are linked to a partner which support) EEE in |
4062 | * 100Mbps should disable LPLU since 100Mbps w/ EEE requires less power | |
4063 | * than 10Mbps w/o EEE. | |
97ac8cae | 4064 | **/ |
99730e4c | 4065 | void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw) |
97ac8cae | 4066 | { |
2fbe4526 | 4067 | struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; |
97ac8cae | 4068 | u32 phy_ctrl; |
8395ae83 | 4069 | s32 ret_val; |
97ac8cae | 4070 | |
17f085df | 4071 | phy_ctrl = er32(PHY_CTRL); |
c077a906 | 4072 | phy_ctrl |= E1000_PHY_CTRL_GBE_DISABLE; |
2fbe4526 BA |
4073 | if (hw->phy.type == e1000_phy_i217) { |
4074 | u16 phy_reg; | |
4075 | ||
4076 | ret_val = hw->phy.ops.acquire(hw); | |
4077 | if (ret_val) | |
4078 | goto out; | |
4079 | ||
4080 | if (!dev_spec->eee_disable) { | |
4081 | u16 eee_advert; | |
4082 | ||
4ddc48a9 BA |
4083 | ret_val = |
4084 | e1000_read_emi_reg_locked(hw, | |
4085 | I217_EEE_ADVERTISEMENT, | |
4086 | &eee_advert); | |
2fbe4526 BA |
4087 | if (ret_val) |
4088 | goto release; | |
2fbe4526 | 4089 | |
e921eb1a | 4090 | /* Disable LPLU if both link partners support 100BaseT |
2fbe4526 BA |
4091 | * EEE and 100Full is advertised on both ends of the |
4092 | * link. | |
4093 | */ | |
3d4d5755 | 4094 | if ((eee_advert & I82579_EEE_100_SUPPORTED) && |
2fbe4526 | 4095 | (dev_spec->eee_lp_ability & |
3d4d5755 | 4096 | I82579_EEE_100_SUPPORTED) && |
2fbe4526 BA |
4097 | (hw->phy.autoneg_advertised & ADVERTISE_100_FULL)) |
4098 | phy_ctrl &= ~(E1000_PHY_CTRL_D0A_LPLU | | |
4099 | E1000_PHY_CTRL_NOND0A_LPLU); | |
4100 | } | |
4101 | ||
e921eb1a | 4102 | /* For i217 Intel Rapid Start Technology support, |
2fbe4526 BA |
4103 | * when the system is going into Sx and no manageability engine |
4104 | * is present, the driver must configure proxy to reset only on | |
4105 | * power good. LPI (Low Power Idle) state must also reset only | |
4106 | * on power good, as well as the MTA (Multicast table array). | |
4107 | * The SMBus release must also be disabled on LCD reset. | |
4108 | */ | |
4109 | if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { | |
4110 | ||
4111 | /* Enable proxy to reset only on power good. */ | |
4112 | e1e_rphy_locked(hw, I217_PROXY_CTRL, &phy_reg); | |
4113 | phy_reg |= I217_PROXY_CTRL_AUTO_DISABLE; | |
4114 | e1e_wphy_locked(hw, I217_PROXY_CTRL, phy_reg); | |
4115 | ||
e921eb1a | 4116 | /* Set bit enable LPI (EEE) to reset only on |
2fbe4526 BA |
4117 | * power good. |
4118 | */ | |
4119 | e1e_rphy_locked(hw, I217_SxCTRL, &phy_reg); | |
6d7407bf | 4120 | phy_reg |= I217_SxCTRL_ENABLE_LPI_RESET; |
2fbe4526 BA |
4121 | e1e_wphy_locked(hw, I217_SxCTRL, phy_reg); |
4122 | ||
4123 | /* Disable the SMB release on LCD reset. */ | |
4124 | e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); | |
6d7407bf | 4125 | phy_reg &= ~I217_MEMPWR_DISABLE_SMB_RELEASE; |
2fbe4526 BA |
4126 | e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); |
4127 | } | |
4128 | ||
e921eb1a | 4129 | /* Enable MTA to reset for Intel Rapid Start Technology |
2fbe4526 BA |
4130 | * Support |
4131 | */ | |
4132 | e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); | |
6d7407bf | 4133 | phy_reg |= I217_CGFREG_ENABLE_MTA_RESET; |
2fbe4526 BA |
4134 | e1e_wphy_locked(hw, I217_CGFREG, phy_reg); |
4135 | ||
4136 | release: | |
4137 | hw->phy.ops.release(hw); | |
4138 | } | |
4139 | out: | |
17f085df | 4140 | ew32(PHY_CTRL, phy_ctrl); |
a4f58f54 | 4141 | |
462d5994 BA |
4142 | if (hw->mac.type == e1000_ich8lan) |
4143 | e1000e_gig_downshift_workaround_ich8lan(hw); | |
4144 | ||
8395ae83 | 4145 | if (hw->mac.type >= e1000_pchlan) { |
ce54afd1 | 4146 | e1000_oem_bits_config_ich8lan(hw, false); |
92fe1733 BA |
4147 | |
4148 | /* Reset PHY to activate OEM bits on 82577/8 */ | |
4149 | if (hw->mac.type == e1000_pchlan) | |
4150 | e1000e_phy_hw_reset_generic(hw); | |
4151 | ||
8395ae83 BA |
4152 | ret_val = hw->phy.ops.acquire(hw); |
4153 | if (ret_val) | |
4154 | return; | |
4155 | e1000_write_smbus_addr(hw); | |
4156 | hw->phy.ops.release(hw); | |
4157 | } | |
97ac8cae BA |
4158 | } |
4159 | ||
99730e4c BA |
4160 | /** |
4161 | * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0 | |
4162 | * @hw: pointer to the HW structure | |
4163 | * | |
4164 | * During Sx to S0 transitions on non-managed devices or managed devices | |
4165 | * on which PHY resets are not blocked, if the PHY registers cannot be | |
4166 | * accessed properly by the s/w toggle the LANPHYPC value to power cycle | |
4167 | * the PHY. | |
2fbe4526 | 4168 | * On i217, setup Intel Rapid Start Technology. |
99730e4c BA |
4169 | **/ |
4170 | void e1000_resume_workarounds_pchlan(struct e1000_hw *hw) | |
4171 | { | |
90b82984 | 4172 | s32 ret_val; |
99730e4c | 4173 | |
cb17aab9 | 4174 | if (hw->mac.type < e1000_pch2lan) |
99730e4c BA |
4175 | return; |
4176 | ||
cb17aab9 | 4177 | ret_val = e1000_init_phy_workarounds_pchlan(hw); |
90b82984 | 4178 | if (ret_val) { |
cb17aab9 | 4179 | e_dbg("Failed to init PHY flow ret_val=%d\n", ret_val); |
90b82984 BA |
4180 | return; |
4181 | } | |
2fbe4526 | 4182 | |
e921eb1a | 4183 | /* For i217 Intel Rapid Start Technology support when the system |
2fbe4526 BA |
4184 | * is transitioning from Sx and no manageability engine is present |
4185 | * configure SMBus to restore on reset, disable proxy, and enable | |
4186 | * the reset on MTA (Multicast table array). | |
4187 | */ | |
4188 | if (hw->phy.type == e1000_phy_i217) { | |
4189 | u16 phy_reg; | |
4190 | ||
4191 | ret_val = hw->phy.ops.acquire(hw); | |
4192 | if (ret_val) { | |
4193 | e_dbg("Failed to setup iRST\n"); | |
4194 | return; | |
4195 | } | |
4196 | ||
4197 | if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) { | |
e921eb1a | 4198 | /* Restore clear on SMB if no manageability engine |
2fbe4526 BA |
4199 | * is present |
4200 | */ | |
4201 | ret_val = e1e_rphy_locked(hw, I217_MEMPWR, &phy_reg); | |
4202 | if (ret_val) | |
4203 | goto release; | |
6d7407bf | 4204 | phy_reg |= I217_MEMPWR_DISABLE_SMB_RELEASE; |
2fbe4526 BA |
4205 | e1e_wphy_locked(hw, I217_MEMPWR, phy_reg); |
4206 | ||
4207 | /* Disable Proxy */ | |
4208 | e1e_wphy_locked(hw, I217_PROXY_CTRL, 0); | |
4209 | } | |
4210 | /* Enable reset on MTA */ | |
4211 | ret_val = e1e_rphy_locked(hw, I217_CGFREG, &phy_reg); | |
4212 | if (ret_val) | |
4213 | goto release; | |
6d7407bf | 4214 | phy_reg &= ~I217_CGFREG_ENABLE_MTA_RESET; |
2fbe4526 BA |
4215 | e1e_wphy_locked(hw, I217_CGFREG, phy_reg); |
4216 | release: | |
4217 | if (ret_val) | |
4218 | e_dbg("Error %d in resume workarounds\n", ret_val); | |
4219 | hw->phy.ops.release(hw); | |
4220 | } | |
99730e4c BA |
4221 | } |
4222 | ||
bc7f75fa AK |
4223 | /** |
4224 | * e1000_cleanup_led_ich8lan - Restore the default LED operation | |
4225 | * @hw: pointer to the HW structure | |
4226 | * | |
4227 | * Return the LED back to the default configuration. | |
4228 | **/ | |
4229 | static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw) | |
4230 | { | |
4231 | if (hw->phy.type == e1000_phy_ife) | |
4232 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0); | |
4233 | ||
4234 | ew32(LEDCTL, hw->mac.ledctl_default); | |
4235 | return 0; | |
4236 | } | |
4237 | ||
4238 | /** | |
489815ce | 4239 | * e1000_led_on_ich8lan - Turn LEDs on |
bc7f75fa AK |
4240 | * @hw: pointer to the HW structure |
4241 | * | |
489815ce | 4242 | * Turn on the LEDs. |
bc7f75fa AK |
4243 | **/ |
4244 | static s32 e1000_led_on_ich8lan(struct e1000_hw *hw) | |
4245 | { | |
4246 | if (hw->phy.type == e1000_phy_ife) | |
4247 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
4248 | (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON)); | |
4249 | ||
4250 | ew32(LEDCTL, hw->mac.ledctl_mode2); | |
4251 | return 0; | |
4252 | } | |
4253 | ||
4254 | /** | |
489815ce | 4255 | * e1000_led_off_ich8lan - Turn LEDs off |
bc7f75fa AK |
4256 | * @hw: pointer to the HW structure |
4257 | * | |
489815ce | 4258 | * Turn off the LEDs. |
bc7f75fa AK |
4259 | **/ |
4260 | static s32 e1000_led_off_ich8lan(struct e1000_hw *hw) | |
4261 | { | |
4262 | if (hw->phy.type == e1000_phy_ife) | |
4263 | return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, | |
482fed85 BA |
4264 | (IFE_PSCL_PROBE_MODE | |
4265 | IFE_PSCL_PROBE_LEDS_OFF)); | |
bc7f75fa AK |
4266 | |
4267 | ew32(LEDCTL, hw->mac.ledctl_mode1); | |
4268 | return 0; | |
4269 | } | |
4270 | ||
a4f58f54 BA |
4271 | /** |
4272 | * e1000_setup_led_pchlan - Configures SW controllable LED | |
4273 | * @hw: pointer to the HW structure | |
4274 | * | |
4275 | * This prepares the SW controllable LED for use. | |
4276 | **/ | |
4277 | static s32 e1000_setup_led_pchlan(struct e1000_hw *hw) | |
4278 | { | |
482fed85 | 4279 | return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1); |
a4f58f54 BA |
4280 | } |
4281 | ||
4282 | /** | |
4283 | * e1000_cleanup_led_pchlan - Restore the default LED operation | |
4284 | * @hw: pointer to the HW structure | |
4285 | * | |
4286 | * Return the LED back to the default configuration. | |
4287 | **/ | |
4288 | static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw) | |
4289 | { | |
482fed85 | 4290 | return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default); |
a4f58f54 BA |
4291 | } |
4292 | ||
4293 | /** | |
4294 | * e1000_led_on_pchlan - Turn LEDs on | |
4295 | * @hw: pointer to the HW structure | |
4296 | * | |
4297 | * Turn on the LEDs. | |
4298 | **/ | |
4299 | static s32 e1000_led_on_pchlan(struct e1000_hw *hw) | |
4300 | { | |
4301 | u16 data = (u16)hw->mac.ledctl_mode2; | |
4302 | u32 i, led; | |
4303 | ||
e921eb1a | 4304 | /* If no link, then turn LED on by setting the invert bit |
a4f58f54 BA |
4305 | * for each LED that's mode is "link_up" in ledctl_mode2. |
4306 | */ | |
4307 | if (!(er32(STATUS) & E1000_STATUS_LU)) { | |
4308 | for (i = 0; i < 3; i++) { | |
4309 | led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; | |
4310 | if ((led & E1000_PHY_LED0_MODE_MASK) != | |
4311 | E1000_LEDCTL_MODE_LINK_UP) | |
4312 | continue; | |
4313 | if (led & E1000_PHY_LED0_IVRT) | |
4314 | data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); | |
4315 | else | |
4316 | data |= (E1000_PHY_LED0_IVRT << (i * 5)); | |
4317 | } | |
4318 | } | |
4319 | ||
482fed85 | 4320 | return e1e_wphy(hw, HV_LED_CONFIG, data); |
a4f58f54 BA |
4321 | } |
4322 | ||
4323 | /** | |
4324 | * e1000_led_off_pchlan - Turn LEDs off | |
4325 | * @hw: pointer to the HW structure | |
4326 | * | |
4327 | * Turn off the LEDs. | |
4328 | **/ | |
4329 | static s32 e1000_led_off_pchlan(struct e1000_hw *hw) | |
4330 | { | |
4331 | u16 data = (u16)hw->mac.ledctl_mode1; | |
4332 | u32 i, led; | |
4333 | ||
e921eb1a | 4334 | /* If no link, then turn LED off by clearing the invert bit |
a4f58f54 BA |
4335 | * for each LED that's mode is "link_up" in ledctl_mode1. |
4336 | */ | |
4337 | if (!(er32(STATUS) & E1000_STATUS_LU)) { | |
4338 | for (i = 0; i < 3; i++) { | |
4339 | led = (data >> (i * 5)) & E1000_PHY_LED0_MASK; | |
4340 | if ((led & E1000_PHY_LED0_MODE_MASK) != | |
4341 | E1000_LEDCTL_MODE_LINK_UP) | |
4342 | continue; | |
4343 | if (led & E1000_PHY_LED0_IVRT) | |
4344 | data &= ~(E1000_PHY_LED0_IVRT << (i * 5)); | |
4345 | else | |
4346 | data |= (E1000_PHY_LED0_IVRT << (i * 5)); | |
4347 | } | |
4348 | } | |
4349 | ||
482fed85 | 4350 | return e1e_wphy(hw, HV_LED_CONFIG, data); |
a4f58f54 BA |
4351 | } |
4352 | ||
f4187b56 | 4353 | /** |
e98cac44 | 4354 | * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset |
f4187b56 BA |
4355 | * @hw: pointer to the HW structure |
4356 | * | |
e98cac44 BA |
4357 | * Read appropriate register for the config done bit for completion status |
4358 | * and configure the PHY through s/w for EEPROM-less parts. | |
4359 | * | |
4360 | * NOTE: some silicon which is EEPROM-less will fail trying to read the | |
4361 | * config done bit, so only an error is logged and continues. If we were | |
4362 | * to return with error, EEPROM-less silicon would not be able to be reset | |
4363 | * or change link. | |
f4187b56 BA |
4364 | **/ |
4365 | static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw) | |
4366 | { | |
e98cac44 | 4367 | s32 ret_val = 0; |
f4187b56 | 4368 | u32 bank = 0; |
e98cac44 | 4369 | u32 status; |
f4187b56 | 4370 | |
e98cac44 | 4371 | e1000e_get_cfg_done(hw); |
fc0c7760 | 4372 | |
e98cac44 BA |
4373 | /* Wait for indication from h/w that it has completed basic config */ |
4374 | if (hw->mac.type >= e1000_ich10lan) { | |
4375 | e1000_lan_init_done_ich8lan(hw); | |
4376 | } else { | |
4377 | ret_val = e1000e_get_auto_rd_done(hw); | |
4378 | if (ret_val) { | |
e921eb1a | 4379 | /* When auto config read does not complete, do not |
e98cac44 BA |
4380 | * return with an error. This can happen in situations |
4381 | * where there is no eeprom and prevents getting link. | |
4382 | */ | |
4383 | e_dbg("Auto Read Done did not complete\n"); | |
4384 | ret_val = 0; | |
4385 | } | |
fc0c7760 BA |
4386 | } |
4387 | ||
e98cac44 BA |
4388 | /* Clear PHY Reset Asserted bit */ |
4389 | status = er32(STATUS); | |
4390 | if (status & E1000_STATUS_PHYRA) | |
4391 | ew32(STATUS, status & ~E1000_STATUS_PHYRA); | |
4392 | else | |
4393 | e_dbg("PHY Reset Asserted not set - needs delay\n"); | |
f4187b56 BA |
4394 | |
4395 | /* If EEPROM is not marked present, init the IGP 3 PHY manually */ | |
e98cac44 | 4396 | if (hw->mac.type <= e1000_ich9lan) { |
04499ec4 | 4397 | if (!(er32(EECD) & E1000_EECD_PRES) && |
f4187b56 BA |
4398 | (hw->phy.type == e1000_phy_igp_3)) { |
4399 | e1000e_phy_init_script_igp3(hw); | |
4400 | } | |
4401 | } else { | |
4402 | if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) { | |
4403 | /* Maybe we should do a basic PHY config */ | |
3bb99fe2 | 4404 | e_dbg("EEPROM not present\n"); |
e98cac44 | 4405 | ret_val = -E1000_ERR_CONFIG; |
f4187b56 BA |
4406 | } |
4407 | } | |
4408 | ||
e98cac44 | 4409 | return ret_val; |
f4187b56 BA |
4410 | } |
4411 | ||
17f208de BA |
4412 | /** |
4413 | * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down | |
4414 | * @hw: pointer to the HW structure | |
4415 | * | |
4416 | * In the case of a PHY power down to save power, or to turn off link during a | |
4417 | * driver unload, or wake on lan is not enabled, remove the link. | |
4418 | **/ | |
4419 | static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw) | |
4420 | { | |
4421 | /* If the management interface is not enabled, then power down */ | |
4422 | if (!(hw->mac.ops.check_mng_mode(hw) || | |
4423 | hw->phy.ops.check_reset_block(hw))) | |
4424 | e1000_power_down_phy_copper(hw); | |
17f208de BA |
4425 | } |
4426 | ||
bc7f75fa AK |
4427 | /** |
4428 | * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters | |
4429 | * @hw: pointer to the HW structure | |
4430 | * | |
4431 | * Clears hardware counters specific to the silicon family and calls | |
4432 | * clear_hw_cntrs_generic to clear all general purpose counters. | |
4433 | **/ | |
4434 | static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw) | |
4435 | { | |
a4f58f54 | 4436 | u16 phy_data; |
2b6b168d | 4437 | s32 ret_val; |
bc7f75fa AK |
4438 | |
4439 | e1000e_clear_hw_cntrs_base(hw); | |
4440 | ||
99673d9b BA |
4441 | er32(ALGNERRC); |
4442 | er32(RXERRC); | |
4443 | er32(TNCRS); | |
4444 | er32(CEXTERR); | |
4445 | er32(TSCTC); | |
4446 | er32(TSCTFC); | |
bc7f75fa | 4447 | |
99673d9b BA |
4448 | er32(MGTPRC); |
4449 | er32(MGTPDC); | |
4450 | er32(MGTPTC); | |
bc7f75fa | 4451 | |
99673d9b BA |
4452 | er32(IAC); |
4453 | er32(ICRXOC); | |
bc7f75fa | 4454 | |
a4f58f54 BA |
4455 | /* Clear PHY statistics registers */ |
4456 | if ((hw->phy.type == e1000_phy_82578) || | |
d3738bb8 | 4457 | (hw->phy.type == e1000_phy_82579) || |
2fbe4526 | 4458 | (hw->phy.type == e1000_phy_i217) || |
a4f58f54 | 4459 | (hw->phy.type == e1000_phy_82577)) { |
2b6b168d BA |
4460 | ret_val = hw->phy.ops.acquire(hw); |
4461 | if (ret_val) | |
4462 | return; | |
4463 | ret_val = hw->phy.ops.set_page(hw, | |
4464 | HV_STATS_PAGE << IGP_PAGE_SHIFT); | |
4465 | if (ret_val) | |
4466 | goto release; | |
4467 | hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data); | |
4468 | hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data); | |
4469 | hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data); | |
4470 | hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data); | |
4471 | hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data); | |
4472 | hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data); | |
4473 | hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data); | |
4474 | hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data); | |
4475 | hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data); | |
4476 | hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data); | |
4477 | hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data); | |
4478 | hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data); | |
4479 | hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data); | |
4480 | hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data); | |
4481 | release: | |
4482 | hw->phy.ops.release(hw); | |
a4f58f54 | 4483 | } |
bc7f75fa AK |
4484 | } |
4485 | ||
8ce9d6c7 | 4486 | static const struct e1000_mac_operations ich8_mac_ops = { |
eb7700dc | 4487 | /* check_mng_mode dependent on mac type */ |
7d3cabbc | 4488 | .check_for_link = e1000_check_for_copper_link_ich8lan, |
a4f58f54 | 4489 | /* cleanup_led dependent on mac type */ |
bc7f75fa AK |
4490 | .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan, |
4491 | .get_bus_info = e1000_get_bus_info_ich8lan, | |
f4d2dd4c | 4492 | .set_lan_id = e1000_set_lan_id_single_port, |
bc7f75fa | 4493 | .get_link_up_info = e1000_get_link_up_info_ich8lan, |
a4f58f54 BA |
4494 | /* led_on dependent on mac type */ |
4495 | /* led_off dependent on mac type */ | |
e2de3eb6 | 4496 | .update_mc_addr_list = e1000e_update_mc_addr_list_generic, |
bc7f75fa AK |
4497 | .reset_hw = e1000_reset_hw_ich8lan, |
4498 | .init_hw = e1000_init_hw_ich8lan, | |
4499 | .setup_link = e1000_setup_link_ich8lan, | |
4500 | .setup_physical_interface= e1000_setup_copper_link_ich8lan, | |
a4f58f54 | 4501 | /* id_led_init dependent on mac type */ |
57cde763 | 4502 | .config_collision_dist = e1000e_config_collision_dist_generic, |
69e1e019 | 4503 | .rar_set = e1000e_rar_set_generic, |
bc7f75fa AK |
4504 | }; |
4505 | ||
8ce9d6c7 | 4506 | static const struct e1000_phy_operations ich8_phy_ops = { |
94d8186a | 4507 | .acquire = e1000_acquire_swflag_ich8lan, |
bc7f75fa | 4508 | .check_reset_block = e1000_check_reset_block_ich8lan, |
94d8186a | 4509 | .commit = NULL, |
f4187b56 | 4510 | .get_cfg_done = e1000_get_cfg_done_ich8lan, |
bc7f75fa | 4511 | .get_cable_length = e1000e_get_cable_length_igp_2, |
94d8186a BA |
4512 | .read_reg = e1000e_read_phy_reg_igp, |
4513 | .release = e1000_release_swflag_ich8lan, | |
4514 | .reset = e1000_phy_hw_reset_ich8lan, | |
bc7f75fa AK |
4515 | .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan, |
4516 | .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan, | |
94d8186a | 4517 | .write_reg = e1000e_write_phy_reg_igp, |
bc7f75fa AK |
4518 | }; |
4519 | ||
8ce9d6c7 | 4520 | static const struct e1000_nvm_operations ich8_nvm_ops = { |
94d8186a BA |
4521 | .acquire = e1000_acquire_nvm_ich8lan, |
4522 | .read = e1000_read_nvm_ich8lan, | |
4523 | .release = e1000_release_nvm_ich8lan, | |
e85e3639 | 4524 | .reload = e1000e_reload_nvm_generic, |
94d8186a | 4525 | .update = e1000_update_nvm_checksum_ich8lan, |
bc7f75fa | 4526 | .valid_led_default = e1000_valid_led_default_ich8lan, |
94d8186a BA |
4527 | .validate = e1000_validate_nvm_checksum_ich8lan, |
4528 | .write = e1000_write_nvm_ich8lan, | |
bc7f75fa AK |
4529 | }; |
4530 | ||
8ce9d6c7 | 4531 | const struct e1000_info e1000_ich8_info = { |
bc7f75fa AK |
4532 | .mac = e1000_ich8lan, |
4533 | .flags = FLAG_HAS_WOL | |
97ac8cae | 4534 | | FLAG_IS_ICH |
bc7f75fa AK |
4535 | | FLAG_HAS_CTRLEXT_ON_LOAD |
4536 | | FLAG_HAS_AMT | |
4537 | | FLAG_HAS_FLASH | |
4538 | | FLAG_APME_IN_WUC, | |
4539 | .pba = 8, | |
2adc55c9 | 4540 | .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN, |
69e3fd8c | 4541 | .get_variants = e1000_get_variants_ich8lan, |
bc7f75fa AK |
4542 | .mac_ops = &ich8_mac_ops, |
4543 | .phy_ops = &ich8_phy_ops, | |
4544 | .nvm_ops = &ich8_nvm_ops, | |
4545 | }; | |
4546 | ||
8ce9d6c7 | 4547 | const struct e1000_info e1000_ich9_info = { |
bc7f75fa AK |
4548 | .mac = e1000_ich9lan, |
4549 | .flags = FLAG_HAS_JUMBO_FRAMES | |
97ac8cae | 4550 | | FLAG_IS_ICH |
bc7f75fa | 4551 | | FLAG_HAS_WOL |
bc7f75fa AK |
4552 | | FLAG_HAS_CTRLEXT_ON_LOAD |
4553 | | FLAG_HAS_AMT | |
bc7f75fa AK |
4554 | | FLAG_HAS_FLASH |
4555 | | FLAG_APME_IN_WUC, | |
7f1557e1 | 4556 | .pba = 18, |
2adc55c9 | 4557 | .max_hw_frame_size = DEFAULT_JUMBO, |
69e3fd8c | 4558 | .get_variants = e1000_get_variants_ich8lan, |
bc7f75fa AK |
4559 | .mac_ops = &ich8_mac_ops, |
4560 | .phy_ops = &ich8_phy_ops, | |
4561 | .nvm_ops = &ich8_nvm_ops, | |
4562 | }; | |
4563 | ||
8ce9d6c7 | 4564 | const struct e1000_info e1000_ich10_info = { |
f4187b56 BA |
4565 | .mac = e1000_ich10lan, |
4566 | .flags = FLAG_HAS_JUMBO_FRAMES | |
4567 | | FLAG_IS_ICH | |
4568 | | FLAG_HAS_WOL | |
f4187b56 BA |
4569 | | FLAG_HAS_CTRLEXT_ON_LOAD |
4570 | | FLAG_HAS_AMT | |
f4187b56 BA |
4571 | | FLAG_HAS_FLASH |
4572 | | FLAG_APME_IN_WUC, | |
7f1557e1 | 4573 | .pba = 18, |
2adc55c9 | 4574 | .max_hw_frame_size = DEFAULT_JUMBO, |
f4187b56 BA |
4575 | .get_variants = e1000_get_variants_ich8lan, |
4576 | .mac_ops = &ich8_mac_ops, | |
4577 | .phy_ops = &ich8_phy_ops, | |
4578 | .nvm_ops = &ich8_nvm_ops, | |
4579 | }; | |
a4f58f54 | 4580 | |
8ce9d6c7 | 4581 | const struct e1000_info e1000_pch_info = { |
a4f58f54 BA |
4582 | .mac = e1000_pchlan, |
4583 | .flags = FLAG_IS_ICH | |
4584 | | FLAG_HAS_WOL | |
a4f58f54 BA |
4585 | | FLAG_HAS_CTRLEXT_ON_LOAD |
4586 | | FLAG_HAS_AMT | |
4587 | | FLAG_HAS_FLASH | |
4588 | | FLAG_HAS_JUMBO_FRAMES | |
38eb394e | 4589 | | FLAG_DISABLE_FC_PAUSE_TIME /* errata */ |
a4f58f54 | 4590 | | FLAG_APME_IN_WUC, |
8c7bbb92 | 4591 | .flags2 = FLAG2_HAS_PHY_STATS, |
a4f58f54 BA |
4592 | .pba = 26, |
4593 | .max_hw_frame_size = 4096, | |
4594 | .get_variants = e1000_get_variants_ich8lan, | |
4595 | .mac_ops = &ich8_mac_ops, | |
4596 | .phy_ops = &ich8_phy_ops, | |
4597 | .nvm_ops = &ich8_nvm_ops, | |
4598 | }; | |
d3738bb8 | 4599 | |
8ce9d6c7 | 4600 | const struct e1000_info e1000_pch2_info = { |
d3738bb8 BA |
4601 | .mac = e1000_pch2lan, |
4602 | .flags = FLAG_IS_ICH | |
4603 | | FLAG_HAS_WOL | |
b67e1913 | 4604 | | FLAG_HAS_HW_TIMESTAMP |
d3738bb8 BA |
4605 | | FLAG_HAS_CTRLEXT_ON_LOAD |
4606 | | FLAG_HAS_AMT | |
4607 | | FLAG_HAS_FLASH | |
4608 | | FLAG_HAS_JUMBO_FRAMES | |
4609 | | FLAG_APME_IN_WUC, | |
e52997f9 BA |
4610 | .flags2 = FLAG2_HAS_PHY_STATS |
4611 | | FLAG2_HAS_EEE, | |
828bac87 | 4612 | .pba = 26, |
d3738bb8 BA |
4613 | .max_hw_frame_size = DEFAULT_JUMBO, |
4614 | .get_variants = e1000_get_variants_ich8lan, | |
4615 | .mac_ops = &ich8_mac_ops, | |
4616 | .phy_ops = &ich8_phy_ops, | |
4617 | .nvm_ops = &ich8_nvm_ops, | |
4618 | }; | |
2fbe4526 BA |
4619 | |
4620 | const struct e1000_info e1000_pch_lpt_info = { | |
4621 | .mac = e1000_pch_lpt, | |
4622 | .flags = FLAG_IS_ICH | |
4623 | | FLAG_HAS_WOL | |
b67e1913 | 4624 | | FLAG_HAS_HW_TIMESTAMP |
2fbe4526 BA |
4625 | | FLAG_HAS_CTRLEXT_ON_LOAD |
4626 | | FLAG_HAS_AMT | |
4627 | | FLAG_HAS_FLASH | |
4628 | | FLAG_HAS_JUMBO_FRAMES | |
4629 | | FLAG_APME_IN_WUC, | |
4630 | .flags2 = FLAG2_HAS_PHY_STATS | |
4631 | | FLAG2_HAS_EEE, | |
4632 | .pba = 26, | |
4633 | .max_hw_frame_size = DEFAULT_JUMBO, | |
4634 | .get_variants = e1000_get_variants_ich8lan, | |
4635 | .mac_ops = &ich8_mac_ops, | |
4636 | .phy_ops = &ich8_phy_ops, | |
4637 | .nvm_ops = &ich8_nvm_ops, | |
4638 | }; |