[linux-2.6-block.git] / drivers / net / ethernet / intel / e1000e / hw.h

/*******************************************************************************

  Intel PRO/1000 Linux driver
  Copyright(c) 1999 - 2013 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  Linux NICS <linux.nics@intel.com>
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _E1000_HW_H_
#define _E1000_HW_H_

#include "regs.h"
#include "defines.h"

struct e1000_hw;

#define E1000_DEV_ID_82571EB_COPPER		0x105E
#define E1000_DEV_ID_82571EB_FIBER		0x105F
#define E1000_DEV_ID_82571EB_SERDES		0x1060
#define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
#define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
#define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
#define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
#define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
#define E1000_DEV_ID_82572EI_COPPER		0x107D
#define E1000_DEV_ID_82572EI_FIBER		0x107E
#define E1000_DEV_ID_82572EI_SERDES		0x107F
#define E1000_DEV_ID_82572EI			0x10B9
#define E1000_DEV_ID_82573E			0x108B
#define E1000_DEV_ID_82573E_IAMT		0x108C
#define E1000_DEV_ID_82573L			0x109A
#define E1000_DEV_ID_82574L			0x10D3
#define E1000_DEV_ID_82574LA			0x10F6
#define E1000_DEV_ID_82583V			0x150C
#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
#define E1000_DEV_ID_ICH8_82567V_3		0x1501
#define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
#define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
#define E1000_DEV_ID_ICH8_IGP_C			0x104B
#define E1000_DEV_ID_ICH8_IFE			0x104C
#define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
#define E1000_DEV_ID_ICH8_IFE_G			0x10C5
#define E1000_DEV_ID_ICH8_IGP_M			0x104D
#define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
#define E1000_DEV_ID_ICH9_BM			0x10E5
#define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
#define E1000_DEV_ID_ICH9_IGP_M			0x10BF
#define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
#define E1000_DEV_ID_ICH9_IGP_C			0x294C
#define E1000_DEV_ID_ICH9_IFE			0x10C0
#define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
#define E1000_DEV_ID_ICH9_IFE_G			0x10C2
#define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
#define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
#define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
#define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
#define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
#define E1000_DEV_ID_ICH10_D_BM_V		0x1525
#define E1000_DEV_ID_PCH_M_HV_LM		0x10EA
#define E1000_DEV_ID_PCH_M_HV_LC		0x10EB
#define E1000_DEV_ID_PCH_D_HV_DM		0x10EF
#define E1000_DEV_ID_PCH_D_HV_DC		0x10F0
#define E1000_DEV_ID_PCH2_LV_LM			0x1502
#define E1000_DEV_ID_PCH2_LV_V			0x1503
#define E1000_DEV_ID_PCH_LPT_I217_LM		0x153A
#define E1000_DEV_ID_PCH_LPT_I217_V		0x153B
#define E1000_DEV_ID_PCH_LPTLP_I218_LM		0x155A
#define E1000_DEV_ID_PCH_LPTLP_I218_V		0x1559

#define E1000_REVISION_4	4

#define E1000_FUNC_1		1

#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3

enum e1000_mac_type {
	e1000_82571,
	e1000_82572,
	e1000_82573,
	e1000_82574,
	e1000_82583,
	e1000_80003es2lan,
	e1000_ich8lan,
	e1000_ich9lan,
	e1000_ich10lan,
	e1000_pchlan,
	e1000_pch2lan,
	e1000_pch_lpt,
};

enum e1000_media_type {
	e1000_media_type_unknown = 0,
	e1000_media_type_copper = 1,
	e1000_media_type_fiber = 2,
	e1000_media_type_internal_serdes = 3,
	e1000_num_media_types
};

enum e1000_nvm_type {
	e1000_nvm_unknown = 0,
	e1000_nvm_none,
	e1000_nvm_eeprom_spi,
	e1000_nvm_flash_hw,
	e1000_nvm_flash_sw
};

enum e1000_nvm_override {
	e1000_nvm_override_none = 0,
	e1000_nvm_override_spi_small,
	e1000_nvm_override_spi_large
};

enum e1000_phy_type {
	e1000_phy_unknown = 0,
	e1000_phy_none,
	e1000_phy_m88,
	e1000_phy_igp,
	e1000_phy_igp_2,
	e1000_phy_gg82563,
	e1000_phy_igp_3,
	e1000_phy_ife,
	e1000_phy_bm,
	e1000_phy_82578,
	e1000_phy_82577,
	e1000_phy_82579,
	e1000_phy_i217,
};

enum e1000_bus_width {
	e1000_bus_width_unknown = 0,
	e1000_bus_width_pcie_x1,
	e1000_bus_width_pcie_x2,
	e1000_bus_width_pcie_x4 = 4,
	e1000_bus_width_32,
	e1000_bus_width_64,
	e1000_bus_width_reserved
};

enum e1000_1000t_rx_status {
	e1000_1000t_rx_status_not_ok = 0,
	e1000_1000t_rx_status_ok,
	e1000_1000t_rx_status_undefined = 0xFF
};

enum e1000_rev_polarity{
	e1000_rev_polarity_normal = 0,
	e1000_rev_polarity_reversed,
	e1000_rev_polarity_undefined = 0xFF
};

enum e1000_fc_mode {
	e1000_fc_none = 0,
	e1000_fc_rx_pause,
	e1000_fc_tx_pause,
	e1000_fc_full,
	e1000_fc_default = 0xFF
};

enum e1000_ms_type {
	e1000_ms_hw_default = 0,
	e1000_ms_force_master,
	e1000_ms_force_slave,
	e1000_ms_auto
};

enum e1000_smart_speed {
	e1000_smart_speed_default = 0,
	e1000_smart_speed_on,
	e1000_smart_speed_off
};

enum e1000_serdes_link_state {
	e1000_serdes_link_down = 0,
	e1000_serdes_link_autoneg_progress,
	e1000_serdes_link_autoneg_complete,
	e1000_serdes_link_forced_up
};

/* Receive Descriptor - Extended */
union e1000_rx_desc_extended {
	struct {
		__le64 buffer_addr;
		__le64 reserved;
	} read;
	struct {
		struct {
			__le32 mrq;	      /* Multiple Rx Queues */
			union {
				__le32 rss;	    /* RSS Hash */
				struct {
					__le16 ip_id;  /* IP id */
					__le16 csum;   /* Packet Checksum */
				} csum_ip;
			} hi_dword;
		} lower;
		struct {
			__le32 status_error;     /* ext status/error */
			__le16 length;
			__le16 vlan;	     /* VLAN tag */
		} upper;
	} wb;  /* writeback */
};

#define MAX_PS_BUFFERS 4
/* Receive Descriptor - Packet Split */
union e1000_rx_desc_packet_split {
	struct {
		/* one buffer for protocol header(s), three data buffers */
		__le64 buffer_addr[MAX_PS_BUFFERS];
	} read;
	struct {
		struct {
			__le32 mrq;	      /* Multiple Rx Queues */
			union {
				__le32 rss;	      /* RSS Hash */
				struct {
					__le16 ip_id;    /* IP id */
					__le16 csum;     /* Packet Checksum */
				} csum_ip;
			} hi_dword;
		} lower;
		struct {
			__le32 status_error;     /* ext status/error */
			__le16 length0;	  /* length of buffer 0 */
			__le16 vlan;	     /* VLAN tag */
		} middle;
		struct {
			__le16 header_status;
			__le16 length[3];	/* length of buffers 1-3 */
		} upper;
		__le64 reserved;
	} wb; /* writeback */
};

/* Transmit Descriptor */
struct e1000_tx_desc {
	__le64 buffer_addr;      /* Address of the descriptor's data buffer */
	union {
		__le32 data;
		struct {
			__le16 length;    /* Data buffer length */
			u8 cso;	/* Checksum offset */
			u8 cmd;	/* Descriptor control */
		} flags;
	} lower;
	union {
		__le32 data;
		struct {
			u8 status;     /* Descriptor status */
			u8 css;	/* Checksum start */
			__le16 special;
		} fields;
	} upper;
};

/* Offload Context Descriptor */
struct e1000_context_desc {
	union {
		__le32 ip_config;
		struct {
			u8 ipcss;      /* IP checksum start */
			u8 ipcso;      /* IP checksum offset */
			__le16 ipcse;     /* IP checksum end */
		} ip_fields;
	} lower_setup;
	union {
		__le32 tcp_config;
		struct {
			u8 tucss;      /* TCP checksum start */
			u8 tucso;      /* TCP checksum offset */
			__le16 tucse;     /* TCP checksum end */
		} tcp_fields;
	} upper_setup;
	__le32 cmd_and_length;
	union {
		__le32 data;
		struct {
			u8 status;     /* Descriptor status */
			u8 hdr_len;    /* Header length */
			__le16 mss;       /* Maximum segment size */
		} fields;
	} tcp_seg_setup;
};

/* Offload data descriptor */
struct e1000_data_desc {
	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
	union {
		__le32 data;
		struct {
			__le16 length;    /* Data buffer length */
			u8 typ_len_ext;
			u8 cmd;
		} flags;
	} lower;
	union {
		__le32 data;
		struct {
			u8 status;     /* Descriptor status */
			u8 popts;      /* Packet Options */
			__le16 special;
		} fields;
	} upper;
};

/* Statistics counters collected by the MAC */
struct e1000_hw_stats {
	u64 crcerrs;
	u64 algnerrc;
	u64 symerrs;
	u64 rxerrc;
	u64 mpc;
	u64 scc;
	u64 ecol;
	u64 mcc;
	u64 latecol;
	u64 colc;
	u64 dc;
	u64 tncrs;
	u64 sec;
	u64 cexterr;
	u64 rlec;
	u64 xonrxc;
	u64 xontxc;
	u64 xoffrxc;
	u64 xofftxc;
	u64 fcruc;
	u64 prc64;
	u64 prc127;
	u64 prc255;
	u64 prc511;
	u64 prc1023;
	u64 prc1522;
	u64 gprc;
	u64 bprc;
	u64 mprc;
	u64 gptc;
	u64 gorc;
	u64 gotc;
	u64 rnbc;
	u64 ruc;
	u64 rfc;
	u64 roc;
	u64 rjc;
	u64 mgprc;
	u64 mgpdc;
	u64 mgptc;
	u64 tor;
	u64 tot;
	u64 tpr;
	u64 tpt;
	u64 ptc64;
	u64 ptc127;
	u64 ptc255;
	u64 ptc511;
	u64 ptc1023;
	u64 ptc1522;
	u64 mptc;
	u64 bptc;
	u64 tsctc;
	u64 tsctfc;
	u64 iac;
	u64 icrxptc;
	u64 icrxatc;
	u64 ictxptc;
	u64 ictxatc;
	u64 ictxqec;
	u64 ictxqmtc;
	u64 icrxdmtc;
	u64 icrxoc;
};

struct e1000_phy_stats {
	u32 idle_errors;
	u32 receive_errors;
};

struct e1000_host_mng_dhcp_cookie {
	u32 signature;
	u8  status;
	u8  reserved0;
	u16 vlan_id;
	u32 reserved1;
	u16 reserved2;
	u8  reserved3;
	u8  checksum;
};

/* Host Interface "Rev 1" */
struct e1000_host_command_header {
	u8 command_id;
	u8 command_length;
	u8 command_options;
	u8 checksum;
};

#define E1000_HI_MAX_DATA_LENGTH	252
struct e1000_host_command_info {
	struct e1000_host_command_header command_header;
	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
};

/* Host Interface "Rev 2" */
struct e1000_host_mng_command_header {
	u8  command_id;
	u8  checksum;
	u16 reserved1;
	u16 reserved2;
	u16 command_length;
};

#define E1000_HI_MAX_MNG_DATA_LENGTH	0x6F8
struct e1000_host_mng_command_info {
	struct e1000_host_mng_command_header command_header;
	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
};

#include "mac.h"
#include "phy.h"
#include "nvm.h"
#include "manage.h"

/* Function pointers for the MAC. */
struct e1000_mac_operations {
	s32  (*id_led_init)(struct e1000_hw *);
	s32  (*blink_led)(struct e1000_hw *);
	bool (*check_mng_mode)(struct e1000_hw *);
	s32  (*check_for_link)(struct e1000_hw *);
	s32  (*cleanup_led)(struct e1000_hw *);
	void (*clear_hw_cntrs)(struct e1000_hw *);
	void (*clear_vfta)(struct e1000_hw *);
	s32  (*get_bus_info)(struct e1000_hw *);
	void (*set_lan_id)(struct e1000_hw *);
	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
	s32  (*led_on)(struct e1000_hw *);
	s32  (*led_off)(struct e1000_hw *);
	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
	s32  (*reset_hw)(struct e1000_hw *);
	s32  (*init_hw)(struct e1000_hw *);
	s32  (*setup_link)(struct e1000_hw *);
	s32  (*setup_physical_interface)(struct e1000_hw *);
	s32  (*setup_led)(struct e1000_hw *);
	void (*write_vfta)(struct e1000_hw *, u32, u32);
	void (*config_collision_dist)(struct e1000_hw *);
	void (*rar_set)(struct e1000_hw *, u8 *, u32);
	s32  (*read_mac_addr)(struct e1000_hw *);
};

/* When to use various PHY register access functions:
 *
 *                 Func   Caller
 *   Function      Does   Does    When to use
 *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 *   X_reg_locked  P,A    L       for multiple accesses of different regs
 *                                on different pages
 *   X_reg_page    A      L,P     for multiple accesses of different regs
 *                                on the same page
 *
 * Where X=[read|write], L=locking, P=sets page, A=register access
 *
 */
struct e1000_phy_operations {
	s32  (*acquire)(struct e1000_hw *);
	s32  (*cfg_on_link_up)(struct e1000_hw *);
	s32  (*check_polarity)(struct e1000_hw *);
	s32  (*check_reset_block)(struct e1000_hw *);
	s32  (*commit)(struct e1000_hw *);
	s32  (*force_speed_duplex)(struct e1000_hw *);
	s32  (*get_cfg_done)(struct e1000_hw *hw);
	s32  (*get_cable_length)(struct e1000_hw *);
	s32  (*get_info)(struct e1000_hw *);
	s32  (*set_page)(struct e1000_hw *, u16);
	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
	void (*release)(struct e1000_hw *);
	s32  (*reset)(struct e1000_hw *);
	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
	s32  (*write_reg)(struct e1000_hw *, u32, u16);
	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
	void (*power_up)(struct e1000_hw *);
	void (*power_down)(struct e1000_hw *);
};

/* Function pointers for the NVM. */
struct e1000_nvm_operations {
	s32  (*acquire)(struct e1000_hw *);
	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
	void (*release)(struct e1000_hw *);
	void (*reload)(struct e1000_hw *);
	s32  (*update)(struct e1000_hw *);
	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
	s32  (*validate)(struct e1000_hw *);
	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
};

struct e1000_mac_info {
	struct e1000_mac_operations ops;
	u8 addr[ETH_ALEN];
	u8 perm_addr[ETH_ALEN];

	enum e1000_mac_type type;

	u32 collision_delta;
	u32 ledctl_default;
	u32 ledctl_mode1;
	u32 ledctl_mode2;
	u32 mc_filter_type;
	u32 tx_packet_delta;
	u32 txcw;

	u16 current_ifs_val;
	u16 ifs_max_val;
	u16 ifs_min_val;
	u16 ifs_ratio;
	u16 ifs_step_size;
	u16 mta_reg_count;

	/* Maximum size of the MTA register table in all supported adapters */
	#define MAX_MTA_REG 128
	u32 mta_shadow[MAX_MTA_REG];
	u16 rar_entry_count;

	u8  forced_speed_duplex;

	bool adaptive_ifs;
	bool has_fwsm;
	bool arc_subsystem_valid;
	bool autoneg;
	bool autoneg_failed;
	bool get_link_status;
	bool in_ifs_mode;
	bool serdes_has_link;
	bool tx_pkt_filtering;
	enum e1000_serdes_link_state serdes_link_state;
};

struct e1000_phy_info {
	struct e1000_phy_operations ops;

	enum e1000_phy_type type;

	enum e1000_1000t_rx_status local_rx;
	enum e1000_1000t_rx_status remote_rx;
	enum e1000_ms_type ms_type;
	enum e1000_ms_type original_ms_type;
	enum e1000_rev_polarity cable_polarity;
	enum e1000_smart_speed smart_speed;

	u32 addr;
	u32 id;
	u32 reset_delay_us; /* in usec */
	u32 revision;

	enum e1000_media_type media_type;

	u16 autoneg_advertised;
	u16 autoneg_mask;
	u16 cable_length;
	u16 max_cable_length;
	u16 min_cable_length;

	u8 mdix;

	bool disable_polarity_correction;
	bool is_mdix;
	bool polarity_correction;
	bool speed_downgraded;
	bool autoneg_wait_to_complete;
};

struct e1000_nvm_info {
	struct e1000_nvm_operations ops;

	enum e1000_nvm_type type;
	enum e1000_nvm_override override;

	u32 flash_bank_size;
	u32 flash_base_addr;

	u16 word_size;
	u16 delay_usec;
	u16 address_bits;
	u16 opcode_bits;
	u16 page_size;
};

struct e1000_bus_info {
	enum e1000_bus_width width;

	u16 func;
};

struct e1000_fc_info {
	u32 high_water;          /* Flow control high-water mark */
	u32 low_water;           /* Flow control low-water mark */
	u16 pause_time;          /* Flow control pause timer */
	u16 refresh_time;        /* Flow control refresh timer */
	bool send_xon;           /* Flow control send XON */
	bool strict_ieee;        /* Strict IEEE mode */
	enum e1000_fc_mode current_mode; /* FC mode in effect */
	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
};

struct e1000_dev_spec_82571 {
	bool laa_is_present;
	u32 smb_counter;
};

struct e1000_dev_spec_80003es2lan {
	bool  mdic_wa_enable;
};

struct e1000_shadow_ram {
	u16  value;
	bool modified;
};

#define E1000_ICH8_SHADOW_RAM_WORDS		2048

struct e1000_dev_spec_ich8lan {
	bool kmrn_lock_loss_workaround_enabled;
	struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
	bool nvm_k1_enabled;
	bool eee_disable;
	u16 eee_lp_ability;
};

struct e1000_hw {
	struct e1000_adapter *adapter;

	void __iomem *hw_addr;
	void __iomem *flash_address;

	struct e1000_mac_info  mac;
	struct e1000_fc_info   fc;
	struct e1000_phy_info  phy;
	struct e1000_nvm_info  nvm;
	struct e1000_bus_info  bus;
	struct e1000_host_mng_dhcp_cookie mng_cookie;

	union {
		struct e1000_dev_spec_82571	e82571;
		struct e1000_dev_spec_80003es2lan e80003es2lan;
		struct e1000_dev_spec_ich8lan	ich8lan;
	} dev_spec;
};

#include "82571.h"
#include "80003es2lan.h"
#include "ich8lan.h"

#endif
Commit	Line	Data
bc7f75fa AK	1	/*******************************************************************************
	2
	3	Intel PRO/1000 Linux driver
bf67044b	4	Copyright(c) 1999 - 2013 Intel Corporation.
bc7f75fa AK	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	Linux NICS <linux.nics@intel.com>
	24	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	26
	27	*******************************************************************************/
	28
	29	#ifndef _E1000_HW_H_
	30	#define _E1000_HW_H_
	31
c556d607	32	#include "regs.h"
a9bb6290	33	#include "defines.h"
bc7f75fa AK	34
bc7f75fa AK	35	struct e1000_hw;
bc7f75fa	36
bc7f75fa AK	37	#define E1000_DEV_ID_82571EB_COPPER 0x105E
	38	#define E1000_DEV_ID_82571EB_FIBER 0x105F
	39	#define E1000_DEV_ID_82571EB_SERDES 0x1060
	40	#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
040babf9	41	#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
bc7f75fa AK	42	#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
bc7f75fa AK	43	#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
040babf9 AK	44	#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
040babf9 AK	45	#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
bc7f75fa AK	46	#define E1000_DEV_ID_82572EI_COPPER 0x107D
	47	#define E1000_DEV_ID_82572EI_FIBER 0x107E
	48	#define E1000_DEV_ID_82572EI_SERDES 0x107F
	49	#define E1000_DEV_ID_82572EI 0x10B9
	50	#define E1000_DEV_ID_82573E 0x108B
	51	#define E1000_DEV_ID_82573E_IAMT 0x108C
	52	#define E1000_DEV_ID_82573L 0x109A
4662e82b	53	#define E1000_DEV_ID_82574L 0x10D3
bef28b11	54	#define E1000_DEV_ID_82574LA 0x10F6
a9bb6290	55	#define E1000_DEV_ID_82583V 0x150C
bc7f75fa AK	56	#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
	57	#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
	58	#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
	59	#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
9e135a2e	60	#define E1000_DEV_ID_ICH8_82567V_3 0x1501
bc7f75fa AK	61	#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
	62	#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
	63	#define E1000_DEV_ID_ICH8_IGP_C 0x104B
	64	#define E1000_DEV_ID_ICH8_IFE 0x104C
	65	#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
	66	#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
	67	#define E1000_DEV_ID_ICH8_IGP_M 0x104D
	68	#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
2f15f9d6	69	#define E1000_DEV_ID_ICH9_BM 0x10E5
97ac8cae BA	70	#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
	71	#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
	72	#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
bc7f75fa AK	73	#define E1000_DEV_ID_ICH9_IGP_C 0x294C
	74	#define E1000_DEV_ID_ICH9_IFE 0x10C0
	75	#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
	76	#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
97ac8cae BA	77	#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
	78	#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
	79	#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
f4187b56 BA	80	#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
f4187b56 BA	81	#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
10df0b91	82	#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
a4f58f54 BA	83	#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
	84	#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
	85	#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
	86	#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
d3738bb8 BA	87	#define E1000_DEV_ID_PCH2_LV_LM 0x1502
d3738bb8 BA	88	#define E1000_DEV_ID_PCH2_LV_V 0x1503
2fbe4526 BA	89	#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
2fbe4526 BA	90	#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
16e310ae BA	91	#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
16e310ae BA	92	#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
bc7f75fa	93
a9bb6290	94	#define E1000_REVISION_4 4
4662e82b	95
a9bb6290	96	#define E1000_FUNC_1 1
bc7f75fa	97
a9bb6290 BA	98	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
a9bb6290 BA	99	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
608f8a0d	100
bc7f75fa AK	101	enum e1000_mac_type {
	102	e1000_82571,
	103	e1000_82572,
	104	e1000_82573,
4662e82b	105	e1000_82574,
8c81c9c3	106	e1000_82583,
bc7f75fa AK	107	e1000_80003es2lan,
	108	e1000_ich8lan,
	109	e1000_ich9lan,
f4187b56	110	e1000_ich10lan,
a4f58f54	111	e1000_pchlan,
d3738bb8	112	e1000_pch2lan,
2fbe4526	113	e1000_pch_lpt,
bc7f75fa AK	114	};
	115
	116	enum e1000_media_type {
	117	e1000_media_type_unknown = 0,
	118	e1000_media_type_copper = 1,
	119	e1000_media_type_fiber = 2,
	120	e1000_media_type_internal_serdes = 3,
	121	e1000_num_media_types
	122	};
	123
	124	enum e1000_nvm_type {
	125	e1000_nvm_unknown = 0,
	126	e1000_nvm_none,
	127	e1000_nvm_eeprom_spi,
	128	e1000_nvm_flash_hw,
	129	e1000_nvm_flash_sw
	130	};
	131
	132	enum e1000_nvm_override {
	133	e1000_nvm_override_none = 0,
	134	e1000_nvm_override_spi_small,
	135	e1000_nvm_override_spi_large
	136	};
	137
	138	enum e1000_phy_type {
	139	e1000_phy_unknown = 0,
	140	e1000_phy_none,
	141	e1000_phy_m88,
	142	e1000_phy_igp,
	143	e1000_phy_igp_2,
	144	e1000_phy_gg82563,
	145	e1000_phy_igp_3,
	146	e1000_phy_ife,
97ac8cae	147	e1000_phy_bm,
a4f58f54 BA	148	e1000_phy_82578,
a4f58f54 BA	149	e1000_phy_82577,
d3738bb8	150	e1000_phy_82579,
2fbe4526	151	e1000_phy_i217,
bc7f75fa AK	152	};
	153
	154	enum e1000_bus_width {
	155	e1000_bus_width_unknown = 0,
	156	e1000_bus_width_pcie_x1,
	157	e1000_bus_width_pcie_x2,
	158	e1000_bus_width_pcie_x4 = 4,
	159	e1000_bus_width_32,
	160	e1000_bus_width_64,
	161	e1000_bus_width_reserved
	162	};
	163
	164	enum e1000_1000t_rx_status {
	165	e1000_1000t_rx_status_not_ok = 0,
	166	e1000_1000t_rx_status_ok,
	167	e1000_1000t_rx_status_undefined = 0xFF
	168	};
	169
	170	enum e1000_rev_polarity{
	171	e1000_rev_polarity_normal = 0,
	172	e1000_rev_polarity_reversed,
	173	e1000_rev_polarity_undefined = 0xFF
	174	};
	175
5c48ef3e	176	enum e1000_fc_mode {
bc7f75fa AK	177	e1000_fc_none = 0,
	178	e1000_fc_rx_pause,
	179	e1000_fc_tx_pause,
	180	e1000_fc_full,
	181	e1000_fc_default = 0xFF
	182	};
	183
	184	enum e1000_ms_type {
	185	e1000_ms_hw_default = 0,
	186	e1000_ms_force_master,
	187	e1000_ms_force_slave,
	188	e1000_ms_auto
	189	};
	190
	191	enum e1000_smart_speed {
	192	e1000_smart_speed_default = 0,
	193	e1000_smart_speed_on,
	194	e1000_smart_speed_off
	195	};
	196
c9523379	197	enum e1000_serdes_link_state {
	198	e1000_serdes_link_down = 0,
	199	e1000_serdes_link_autoneg_progress,
	200	e1000_serdes_link_autoneg_complete,
	201	e1000_serdes_link_forced_up
	202	};
	203
bc7f75fa AK	204	/* Receive Descriptor - Extended */
	205	union e1000_rx_desc_extended {
	206	struct {
a39fe742 AV	207	__le64 buffer_addr;
a39fe742 AV	208	__le64 reserved;
bc7f75fa AK	209	} read;
	210	struct {
	211	struct {
a39fe742	212	__le32 mrq; /* Multiple Rx Queues */
bc7f75fa	213	union {
a39fe742	214	__le32 rss; /* RSS Hash */
bc7f75fa	215	struct {
a39fe742 AV	216	__le16 ip_id; /* IP id */
a39fe742 AV	217	__le16 csum; /* Packet Checksum */
bc7f75fa AK	218	} csum_ip;
	219	} hi_dword;
	220	} lower;
	221	struct {
a39fe742 AV	222	__le32 status_error; /* ext status/error */
	223	__le16 length;
	224	__le16 vlan; /* VLAN tag */
bc7f75fa AK	225	} upper;
	226	} wb; /* writeback */
	227	};
	228
	229	#define MAX_PS_BUFFERS 4
	230	/* Receive Descriptor - Packet Split */
	231	union e1000_rx_desc_packet_split {
	232	struct {
	233	/* one buffer for protocol header(s), three data buffers */
a39fe742	234	__le64 buffer_addr[MAX_PS_BUFFERS];
bc7f75fa AK	235	} read;
	236	struct {
	237	struct {
a39fe742	238	__le32 mrq; /* Multiple Rx Queues */
bc7f75fa	239	union {
a39fe742	240	__le32 rss; /* RSS Hash */
bc7f75fa	241	struct {
a39fe742 AV	242	__le16 ip_id; /* IP id */
a39fe742 AV	243	__le16 csum; /* Packet Checksum */
bc7f75fa AK	244	} csum_ip;
	245	} hi_dword;
	246	} lower;
	247	struct {
a39fe742 AV	248	__le32 status_error; /* ext status/error */
	249	__le16 length0; /* length of buffer 0 */
	250	__le16 vlan; /* VLAN tag */
bc7f75fa AK	251	} middle;
bc7f75fa AK	252	struct {
a39fe742 AV	253	__le16 header_status;
a39fe742 AV	254	__le16 length[3]; /* length of buffers 1-3 */
bc7f75fa	255	} upper;
a39fe742	256	__le64 reserved;
bc7f75fa AK	257	} wb; /* writeback */
	258	};
	259
	260	/* Transmit Descriptor */
	261	struct e1000_tx_desc {
a39fe742	262	__le64 buffer_addr; /* Address of the descriptor's data buffer */
bc7f75fa	263	union {
a39fe742	264	__le32 data;
bc7f75fa	265	struct {
a39fe742	266	__le16 length; /* Data buffer length */
bc7f75fa AK	267	u8 cso; /* Checksum offset */
	268	u8 cmd; /* Descriptor control */
	269	} flags;
	270	} lower;
	271	union {
a39fe742	272	__le32 data;
bc7f75fa AK	273	struct {
	274	u8 status; /* Descriptor status */
	275	u8 css; /* Checksum start */
a39fe742	276	__le16 special;
bc7f75fa AK	277	} fields;
	278	} upper;
	279	};
	280
	281	/* Offload Context Descriptor */
	282	struct e1000_context_desc {
	283	union {
a39fe742	284	__le32 ip_config;
bc7f75fa AK	285	struct {
	286	u8 ipcss; /* IP checksum start */
	287	u8 ipcso; /* IP checksum offset */
a39fe742	288	__le16 ipcse; /* IP checksum end */
bc7f75fa AK	289	} ip_fields;
	290	} lower_setup;
	291	union {
a39fe742	292	__le32 tcp_config;
bc7f75fa AK	293	struct {
	294	u8 tucss; /* TCP checksum start */
	295	u8 tucso; /* TCP checksum offset */
a39fe742	296	__le16 tucse; /* TCP checksum end */
bc7f75fa AK	297	} tcp_fields;
bc7f75fa AK	298	} upper_setup;
a39fe742	299	__le32 cmd_and_length;
bc7f75fa	300	union {
a39fe742	301	__le32 data;
bc7f75fa AK	302	struct {
	303	u8 status; /* Descriptor status */
	304	u8 hdr_len; /* Header length */
a39fe742	305	__le16 mss; /* Maximum segment size */
bc7f75fa AK	306	} fields;
	307	} tcp_seg_setup;
	308	};
	309
	310	/* Offload data descriptor */
	311	struct e1000_data_desc {
a39fe742	312	__le64 buffer_addr; /* Address of the descriptor's buffer address */
bc7f75fa	313	union {
a39fe742	314	__le32 data;
bc7f75fa	315	struct {
a39fe742	316	__le16 length; /* Data buffer length */
bc7f75fa AK	317	u8 typ_len_ext;
	318	u8 cmd;
	319	} flags;
	320	} lower;
	321	union {
a39fe742	322	__le32 data;
bc7f75fa AK	323	struct {
	324	u8 status; /* Descriptor status */
	325	u8 popts; /* Packet Options */
a9bb6290	326	__le16 special;
bc7f75fa AK	327	} fields;
	328	} upper;
	329	};
	330
	331	/* Statistics counters collected by the MAC */
	332	struct e1000_hw_stats {
	333	u64 crcerrs;
	334	u64 algnerrc;
	335	u64 symerrs;
	336	u64 rxerrc;
	337	u64 mpc;
	338	u64 scc;
	339	u64 ecol;
	340	u64 mcc;
	341	u64 latecol;
	342	u64 colc;
	343	u64 dc;
	344	u64 tncrs;
	345	u64 sec;
	346	u64 cexterr;
	347	u64 rlec;
	348	u64 xonrxc;
	349	u64 xontxc;
	350	u64 xoffrxc;
	351	u64 xofftxc;
	352	u64 fcruc;
	353	u64 prc64;
	354	u64 prc127;
	355	u64 prc255;
	356	u64 prc511;
	357	u64 prc1023;
	358	u64 prc1522;
	359	u64 gprc;
	360	u64 bprc;
	361	u64 mprc;
	362	u64 gptc;
7c25769f BA	363	u64 gorc;
7c25769f BA	364	u64 gotc;
bc7f75fa AK	365	u64 rnbc;
	366	u64 ruc;
	367	u64 rfc;
	368	u64 roc;
	369	u64 rjc;
	370	u64 mgprc;
	371	u64 mgpdc;
	372	u64 mgptc;
7c25769f BA	373	u64 tor;
7c25769f BA	374	u64 tot;
bc7f75fa AK	375	u64 tpr;
	376	u64 tpt;
	377	u64 ptc64;
	378	u64 ptc127;
	379	u64 ptc255;
	380	u64 ptc511;
	381	u64 ptc1023;
	382	u64 ptc1522;
	383	u64 mptc;
	384	u64 bptc;
	385	u64 tsctc;
	386	u64 tsctfc;
	387	u64 iac;
	388	u64 icrxptc;
	389	u64 icrxatc;
	390	u64 ictxptc;
	391	u64 ictxatc;
	392	u64 ictxqec;
	393	u64 ictxqmtc;
	394	u64 icrxdmtc;
	395	u64 icrxoc;
	396	};
	397
	398	struct e1000_phy_stats {
	399	u32 idle_errors;
	400	u32 receive_errors;
	401	};
	402
	403	struct e1000_host_mng_dhcp_cookie {
	404	u32 signature;
	405	u8 status;
	406	u8 reserved0;
	407	u16 vlan_id;
	408	u32 reserved1;
	409	u16 reserved2;
	410	u8 reserved3;
	411	u8 checksum;
	412	};
	413
	414	/* Host Interface "Rev 1" */
	415	struct e1000_host_command_header {
	416	u8 command_id;
	417	u8 command_length;
	418	u8 command_options;
	419	u8 checksum;
	420	};
	421
a9bb6290	422	#define E1000_HI_MAX_DATA_LENGTH 252
bc7f75fa AK	423	struct e1000_host_command_info {
	424	struct e1000_host_command_header command_header;
	425	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
	426	};
	427
	428	/* Host Interface "Rev 2" */
	429	struct e1000_host_mng_command_header {
	430	u8 command_id;
	431	u8 checksum;
	432	u16 reserved1;
	433	u16 reserved2;
	434	u16 command_length;
	435	};
	436
a9bb6290	437	#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
bc7f75fa AK	438	struct e1000_host_mng_command_info {
	439	struct e1000_host_mng_command_header command_header;
	440	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
	441	};
	442
bdfe2da6	443	#include "mac.h"
93b9f8bf	444	#include "phy.h"
d2263113	445	#include "nvm.h"
948f97ac	446	#include "manage.h"
bdfe2da6	447
a9bb6290	448	/* Function pointers for the MAC. */
bc7f75fa	449	struct e1000_mac_operations {
a4f58f54	450	s32 (id_led_init)(struct e1000_hw );
dbf80dcb	451	s32 (blink_led)(struct e1000_hw );
4662e82b	452	bool (check_mng_mode)(struct e1000_hw );
bc7f75fa AK	453	s32 (check_for_link)(struct e1000_hw );
	454	s32 (cleanup_led)(struct e1000_hw );
	455	void (clear_hw_cntrs)(struct e1000_hw );
caaddaf8	456	void (clear_vfta)(struct e1000_hw );
bc7f75fa	457	s32 (get_bus_info)(struct e1000_hw );
f4d2dd4c	458	void (set_lan_id)(struct e1000_hw );
bc7f75fa AK	459	s32 (get_link_up_info)(struct e1000_hw , u16 , u16 );
	460	s32 (led_on)(struct e1000_hw );
	461	s32 (led_off)(struct e1000_hw );
ab8932f3	462	void (update_mc_addr_list)(struct e1000_hw , u8 *, u32);
bc7f75fa AK	463	s32 (reset_hw)(struct e1000_hw );
	464	s32 (init_hw)(struct e1000_hw );
	465	s32 (setup_link)(struct e1000_hw );
	466	s32 (setup_physical_interface)(struct e1000_hw );
a4f58f54	467	s32 (setup_led)(struct e1000_hw );
caaddaf8	468	void (write_vfta)(struct e1000_hw , u32, u32);
57cde763	469	void (config_collision_dist)(struct e1000_hw );
69e1e019	470	void (rar_set)(struct e1000_hw , u8 *, u32);
608f8a0d	471	s32 (read_mac_addr)(struct e1000_hw );
bc7f75fa AK	472	};
bc7f75fa AK	473
e921eb1a	474	/* When to use various PHY register access functions:
2b6b168d BA	475	*
	476	* Func Caller
	477	* Function Does Does When to use
	478	* ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	479	* X_reg L,P,A n/a for simple PHY reg accesses
	480	* X_reg_locked P,A L for multiple accesses of different regs
	481	* on different pages
	482	* X_reg_page A L,P for multiple accesses of different regs
	483	* on the same page
	484	*
	485	* Where X=[read\|write], L=locking, P=sets page, A=register access
	486	*
	487	*/
bc7f75fa	488	struct e1000_phy_operations {
94d8186a BA	489	s32 (acquire)(struct e1000_hw );
94d8186a BA	490	s32 (cfg_on_link_up)(struct e1000_hw );
a4f58f54	491	s32 (check_polarity)(struct e1000_hw );
bc7f75fa	492	s32 (check_reset_block)(struct e1000_hw );
94d8186a	493	s32 (commit)(struct e1000_hw );
bc7f75fa AK	494	s32 (force_speed_duplex)(struct e1000_hw );
	495	s32 (get_cfg_done)(struct e1000_hw hw);
	496	s32 (get_cable_length)(struct e1000_hw );
94d8186a	497	s32 (get_info)(struct e1000_hw );
2b6b168d	498	s32 (set_page)(struct e1000_hw , u16);
94d8186a BA	499	s32 (read_reg)(struct e1000_hw , u32, u16 *);
94d8186a BA	500	s32 (read_reg_locked)(struct e1000_hw , u32, u16 *);
2b6b168d	501	s32 (read_reg_page)(struct e1000_hw , u32, u16 *);
94d8186a BA	502	void (release)(struct e1000_hw );
94d8186a BA	503	s32 (reset)(struct e1000_hw );
bc7f75fa AK	504	s32 (set_d0_lplu_state)(struct e1000_hw , bool);
bc7f75fa AK	505	s32 (set_d3_lplu_state)(struct e1000_hw , bool);
94d8186a BA	506	s32 (write_reg)(struct e1000_hw , u32, u16);
94d8186a BA	507	s32 (write_reg_locked)(struct e1000_hw , u32, u16);
2b6b168d	508	s32 (write_reg_page)(struct e1000_hw , u32, u16);
17f208de BA	509	void (power_up)(struct e1000_hw );
17f208de BA	510	void (power_down)(struct e1000_hw );
bc7f75fa AK	511	};
	512
	513	/* Function pointers for the NVM. */
	514	struct e1000_nvm_operations {
94d8186a BA	515	s32 (acquire)(struct e1000_hw );
	516	s32 (read)(struct e1000_hw , u16, u16, u16 *);
	517	void (release)(struct e1000_hw );
e85e3639	518	void (reload)(struct e1000_hw );
94d8186a	519	s32 (update)(struct e1000_hw );
bc7f75fa	520	s32 (valid_led_default)(struct e1000_hw , u16 *);
94d8186a BA	521	s32 (validate)(struct e1000_hw );
94d8186a BA	522	s32 (write)(struct e1000_hw , u16, u16, u16 *);
bc7f75fa AK	523	};
	524
	525	struct e1000_mac_info {
	526	struct e1000_mac_operations ops;
d8d5f8ae BA	527	u8 addr[ETH_ALEN];
d8d5f8ae BA	528	u8 perm_addr[ETH_ALEN];
bc7f75fa AK	529
bc7f75fa AK	530	enum e1000_mac_type type;
bc7f75fa AK	531
	532	u32 collision_delta;
	533	u32 ledctl_default;
	534	u32 ledctl_mode1;
	535	u32 ledctl_mode2;
bc7f75fa	536	u32 mc_filter_type;
bc7f75fa AK	537	u32 tx_packet_delta;
	538	u32 txcw;
	539
	540	u16 current_ifs_val;
	541	u16 ifs_max_val;
	542	u16 ifs_min_val;
	543	u16 ifs_ratio;
	544	u16 ifs_step_size;
	545	u16 mta_reg_count;
ab8932f3 BA	546
	547	/* Maximum size of the MTA register table in all supported adapters */
	548	#define MAX_MTA_REG 128
	549	u32 mta_shadow[MAX_MTA_REG];
bc7f75fa	550	u16 rar_entry_count;
bc7f75fa AK	551
	552	u8 forced_speed_duplex;
	553
f464ba87	554	bool adaptive_ifs;
a65a4a0d	555	bool has_fwsm;
bc7f75fa AK	556	bool arc_subsystem_valid;
	557	bool autoneg;
	558	bool autoneg_failed;
	559	bool get_link_status;
	560	bool in_ifs_mode;
	561	bool serdes_has_link;
	562	bool tx_pkt_filtering;
c9523379	563	enum e1000_serdes_link_state serdes_link_state;
bc7f75fa AK	564	};
	565
	566	struct e1000_phy_info {
	567	struct e1000_phy_operations ops;
	568
	569	enum e1000_phy_type type;
	570
	571	enum e1000_1000t_rx_status local_rx;
	572	enum e1000_1000t_rx_status remote_rx;
	573	enum e1000_ms_type ms_type;
	574	enum e1000_ms_type original_ms_type;
	575	enum e1000_rev_polarity cable_polarity;
	576	enum e1000_smart_speed smart_speed;
	577
	578	u32 addr;
	579	u32 id;
	580	u32 reset_delay_us; /* in usec */
	581	u32 revision;
	582
318a94d6 JK	583	enum e1000_media_type media_type;
318a94d6 JK	584
bc7f75fa AK	585	u16 autoneg_advertised;
	586	u16 autoneg_mask;
	587	u16 cable_length;
	588	u16 max_cable_length;
	589	u16 min_cable_length;
	590
	591	u8 mdix;
	592
	593	bool disable_polarity_correction;
	594	bool is_mdix;
	595	bool polarity_correction;
	596	bool speed_downgraded;
318a94d6	597	bool autoneg_wait_to_complete;
bc7f75fa AK	598	};
	599
	600	struct e1000_nvm_info {
	601	struct e1000_nvm_operations ops;
	602
	603	enum e1000_nvm_type type;
	604	enum e1000_nvm_override override;
	605
	606	u32 flash_bank_size;
	607	u32 flash_base_addr;
	608
	609	u16 word_size;
	610	u16 delay_usec;
	611	u16 address_bits;
	612	u16 opcode_bits;
	613	u16 page_size;
	614	};
	615
	616	struct e1000_bus_info {
	617	enum e1000_bus_width width;
	618
	619	u16 func;
	620	};
	621
318a94d6 JK	622	struct e1000_fc_info {
	623	u32 high_water; /* Flow control high-water mark */
	624	u32 low_water; /* Flow control low-water mark */
	625	u16 pause_time; /* Flow control pause timer */
a305595b	626	u16 refresh_time; /* Flow control refresh timer */
318a94d6 JK	627	bool send_xon; /* Flow control send XON */
318a94d6 JK	628	bool strict_ieee; /* Strict IEEE mode */
5c48ef3e BA	629	enum e1000_fc_mode current_mode; /* FC mode in effect */
5c48ef3e BA	630	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
318a94d6 JK	631	};
318a94d6 JK	632
bc7f75fa AK	633	struct e1000_dev_spec_82571 {
bc7f75fa AK	634	bool laa_is_present;
23a2d1b2	635	u32 smb_counter;
bc7f75fa AK	636	};
bc7f75fa AK	637
3421eecd BA	638	struct e1000_dev_spec_80003es2lan {
	639	bool mdic_wa_enable;
	640	};
	641
bc7f75fa AK	642	struct e1000_shadow_ram {
	643	u16 value;
	644	bool modified;
	645	};
	646
	647	#define E1000_ICH8_SHADOW_RAM_WORDS 2048
	648
	649	struct e1000_dev_spec_ich8lan {
	650	bool kmrn_lock_loss_workaround_enabled;
	651	struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
1d5846b9	652	bool nvm_k1_enabled;
e52997f9	653	bool eee_disable;
2fbe4526	654	u16 eee_lp_ability;
bc7f75fa AK	655	};
	656
	657	struct e1000_hw {
	658	struct e1000_adapter *adapter;
	659
c5083cf6 BA	660	void __iomem *hw_addr;
c5083cf6 BA	661	void __iomem *flash_address;
bc7f75fa AK	662
bc7f75fa AK	663	struct e1000_mac_info mac;
318a94d6	664	struct e1000_fc_info fc;
bc7f75fa AK	665	struct e1000_phy_info phy;
	666	struct e1000_nvm_info nvm;
	667	struct e1000_bus_info bus;
	668	struct e1000_host_mng_dhcp_cookie mng_cookie;
	669
	670	union {
	671	struct e1000_dev_spec_82571 e82571;
3421eecd	672	struct e1000_dev_spec_80003es2lan e80003es2lan;
bc7f75fa AK	673	struct e1000_dev_spec_ich8lan ich8lan;
bc7f75fa AK	674	} dev_spec;
bc7f75fa AK	675	};
bc7f75fa AK	676
f25701df	677	#include "82571.h"
21b5a6f8	678	#include "80003es2lan.h"
1b41db37	679	#include "ich8lan.h"
f25701df	680
bc7f75fa	681	#endif