[linux-2.6-block.git] / drivers / net / ethernet / intel / e1000e / hw.h

/* Intel PRO/1000 Linux driver
 * Copyright(c) 1999 - 2014 Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in
 * the file called "COPYING".
 *
 * Contact Information:
 * Linux NICS <linux.nics@intel.com>
 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 */

#ifndef _E1000_HW_H_
#define _E1000_HW_H_

#include "regs.h"
#include "defines.h"

struct e1000_hw;

#define E1000_DEV_ID_82571EB_COPPER		0x105E
#define E1000_DEV_ID_82571EB_FIBER		0x105F
#define E1000_DEV_ID_82571EB_SERDES		0x1060
#define E1000_DEV_ID_82571EB_QUAD_COPPER	0x10A4
#define E1000_DEV_ID_82571PT_QUAD_COPPER	0x10D5
#define E1000_DEV_ID_82571EB_QUAD_FIBER		0x10A5
#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP	0x10BC
#define E1000_DEV_ID_82571EB_SERDES_DUAL	0x10D9
#define E1000_DEV_ID_82571EB_SERDES_QUAD	0x10DA
#define E1000_DEV_ID_82572EI_COPPER		0x107D
#define E1000_DEV_ID_82572EI_FIBER		0x107E
#define E1000_DEV_ID_82572EI_SERDES		0x107F
#define E1000_DEV_ID_82572EI			0x10B9
#define E1000_DEV_ID_82573E			0x108B
#define E1000_DEV_ID_82573E_IAMT		0x108C
#define E1000_DEV_ID_82573L			0x109A
#define E1000_DEV_ID_82574L			0x10D3
#define E1000_DEV_ID_82574LA			0x10F6
#define E1000_DEV_ID_82583V			0x150C
#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT	0x1096
#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT	0x1098
#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT	0x10BA
#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT	0x10BB
#define E1000_DEV_ID_ICH8_82567V_3		0x1501
#define E1000_DEV_ID_ICH8_IGP_M_AMT		0x1049
#define E1000_DEV_ID_ICH8_IGP_AMT		0x104A
#define E1000_DEV_ID_ICH8_IGP_C			0x104B
#define E1000_DEV_ID_ICH8_IFE			0x104C
#define E1000_DEV_ID_ICH8_IFE_GT		0x10C4
#define E1000_DEV_ID_ICH8_IFE_G			0x10C5
#define E1000_DEV_ID_ICH8_IGP_M			0x104D
#define E1000_DEV_ID_ICH9_IGP_AMT		0x10BD
#define E1000_DEV_ID_ICH9_BM			0x10E5
#define E1000_DEV_ID_ICH9_IGP_M_AMT		0x10F5
#define E1000_DEV_ID_ICH9_IGP_M			0x10BF
#define E1000_DEV_ID_ICH9_IGP_M_V		0x10CB
#define E1000_DEV_ID_ICH9_IGP_C			0x294C
#define E1000_DEV_ID_ICH9_IFE			0x10C0
#define E1000_DEV_ID_ICH9_IFE_GT		0x10C3
#define E1000_DEV_ID_ICH9_IFE_G			0x10C2
#define E1000_DEV_ID_ICH10_R_BM_LM		0x10CC
#define E1000_DEV_ID_ICH10_R_BM_LF		0x10CD
#define E1000_DEV_ID_ICH10_R_BM_V		0x10CE
#define E1000_DEV_ID_ICH10_D_BM_LM		0x10DE
#define E1000_DEV_ID_ICH10_D_BM_LF		0x10DF
#define E1000_DEV_ID_ICH10_D_BM_V		0x1525
#define E1000_DEV_ID_PCH_M_HV_LM		0x10EA
#define E1000_DEV_ID_PCH_M_HV_LC		0x10EB
#define E1000_DEV_ID_PCH_D_HV_DM		0x10EF
#define E1000_DEV_ID_PCH_D_HV_DC		0x10F0
#define E1000_DEV_ID_PCH2_LV_LM			0x1502
#define E1000_DEV_ID_PCH2_LV_V			0x1503
#define E1000_DEV_ID_PCH_LPT_I217_LM		0x153A
#define E1000_DEV_ID_PCH_LPT_I217_V		0x153B
#define E1000_DEV_ID_PCH_LPTLP_I218_LM		0x155A
#define E1000_DEV_ID_PCH_LPTLP_I218_V		0x1559
#define E1000_DEV_ID_PCH_I218_LM2		0x15A0
#define E1000_DEV_ID_PCH_I218_V2		0x15A1
#define E1000_DEV_ID_PCH_I218_LM3		0x15A2	/* Wildcat Point PCH */
#define E1000_DEV_ID_PCH_I218_V3		0x15A3	/* Wildcat Point PCH */

#define E1000_REVISION_4	4

#define E1000_FUNC_1		1

#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0	0
#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1	3

enum e1000_mac_type {
	e1000_82571,
	e1000_82572,
	e1000_82573,
	e1000_82574,
	e1000_82583,
	e1000_80003es2lan,
	e1000_ich8lan,
	e1000_ich9lan,
	e1000_ich10lan,
	e1000_pchlan,
	e1000_pch2lan,
	e1000_pch_lpt,
};

enum e1000_media_type {
	e1000_media_type_unknown = 0,
	e1000_media_type_copper = 1,
	e1000_media_type_fiber = 2,
	e1000_media_type_internal_serdes = 3,
	e1000_num_media_types
};

enum e1000_nvm_type {
	e1000_nvm_unknown = 0,
	e1000_nvm_none,
	e1000_nvm_eeprom_spi,
	e1000_nvm_flash_hw,
	e1000_nvm_flash_sw
};

enum e1000_nvm_override {
	e1000_nvm_override_none = 0,
	e1000_nvm_override_spi_small,
	e1000_nvm_override_spi_large
};

enum e1000_phy_type {
	e1000_phy_unknown = 0,
	e1000_phy_none,
	e1000_phy_m88,
	e1000_phy_igp,
	e1000_phy_igp_2,
	e1000_phy_gg82563,
	e1000_phy_igp_3,
	e1000_phy_ife,
	e1000_phy_bm,
	e1000_phy_82578,
	e1000_phy_82577,
	e1000_phy_82579,
	e1000_phy_i217,
};

enum e1000_bus_width {
	e1000_bus_width_unknown = 0,
	e1000_bus_width_pcie_x1,
	e1000_bus_width_pcie_x2,
	e1000_bus_width_pcie_x4 = 4,
	e1000_bus_width_32,
	e1000_bus_width_64,
	e1000_bus_width_reserved
};

enum e1000_1000t_rx_status {
	e1000_1000t_rx_status_not_ok = 0,
	e1000_1000t_rx_status_ok,
	e1000_1000t_rx_status_undefined = 0xFF
};

enum e1000_rev_polarity {
	e1000_rev_polarity_normal = 0,
	e1000_rev_polarity_reversed,
	e1000_rev_polarity_undefined = 0xFF
};

enum e1000_fc_mode {
	e1000_fc_none = 0,
	e1000_fc_rx_pause,
	e1000_fc_tx_pause,
	e1000_fc_full,
	e1000_fc_default = 0xFF
};

enum e1000_ms_type {
	e1000_ms_hw_default = 0,
	e1000_ms_force_master,
	e1000_ms_force_slave,
	e1000_ms_auto
};

enum e1000_smart_speed {
	e1000_smart_speed_default = 0,
	e1000_smart_speed_on,
	e1000_smart_speed_off
};

enum e1000_serdes_link_state {
	e1000_serdes_link_down = 0,
	e1000_serdes_link_autoneg_progress,
	e1000_serdes_link_autoneg_complete,
	e1000_serdes_link_forced_up
};

/* Receive Descriptor - Extended */
union e1000_rx_desc_extended {
	struct {
		__le64 buffer_addr;
		__le64 reserved;
	} read;
	struct {
		struct {
			__le32 mrq;	      /* Multiple Rx Queues */
			union {
				__le32 rss;	    /* RSS Hash */
				struct {
					__le16 ip_id;  /* IP id */
					__le16 csum;   /* Packet Checksum */
				} csum_ip;
			} hi_dword;
		} lower;
		struct {
			__le32 status_error;     /* ext status/error */
			__le16 length;
			__le16 vlan;	     /* VLAN tag */
		} upper;
	} wb;  /* writeback */
};

#define MAX_PS_BUFFERS 4

/* Number of packet split data buffers (not including the header buffer) */
#define PS_PAGE_BUFFERS	(MAX_PS_BUFFERS - 1)

/* Receive Descriptor - Packet Split */
union e1000_rx_desc_packet_split {
	struct {
		/* one buffer for protocol header(s), three data buffers */
		__le64 buffer_addr[MAX_PS_BUFFERS];
	} read;
	struct {
		struct {
			__le32 mrq;	      /* Multiple Rx Queues */
			union {
				__le32 rss;	      /* RSS Hash */
				struct {
					__le16 ip_id;    /* IP id */
					__le16 csum;     /* Packet Checksum */
				} csum_ip;
			} hi_dword;
		} lower;
		struct {
			__le32 status_error;     /* ext status/error */
			__le16 length0;	  /* length of buffer 0 */
			__le16 vlan;	     /* VLAN tag */
		} middle;
		struct {
			__le16 header_status;
			/* length of buffers 1-3 */
			__le16 length[PS_PAGE_BUFFERS];
		} upper;
		__le64 reserved;
	} wb; /* writeback */
};

/* Transmit Descriptor */
struct e1000_tx_desc {
	__le64 buffer_addr;      /* Address of the descriptor's data buffer */
	union {
		__le32 data;
		struct {
			__le16 length;    /* Data buffer length */
			u8 cso;	/* Checksum offset */
			u8 cmd;	/* Descriptor control */
		} flags;
	} lower;
	union {
		__le32 data;
		struct {
			u8 status;     /* Descriptor status */
			u8 css;	/* Checksum start */
			__le16 special;
		} fields;
	} upper;
};

/* Offload Context Descriptor */
struct e1000_context_desc {
	union {
		__le32 ip_config;
		struct {
			u8 ipcss;      /* IP checksum start */
			u8 ipcso;      /* IP checksum offset */
			__le16 ipcse;     /* IP checksum end */
		} ip_fields;
	} lower_setup;
	union {
		__le32 tcp_config;
		struct {
			u8 tucss;      /* TCP checksum start */
			u8 tucso;      /* TCP checksum offset */
			__le16 tucse;     /* TCP checksum end */
		} tcp_fields;
	} upper_setup;
	__le32 cmd_and_length;
	union {
		__le32 data;
		struct {
			u8 status;     /* Descriptor status */
			u8 hdr_len;    /* Header length */
			__le16 mss;       /* Maximum segment size */
		} fields;
	} tcp_seg_setup;
};

/* Offload data descriptor */
struct e1000_data_desc {
	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
	union {
		__le32 data;
		struct {
			__le16 length;    /* Data buffer length */
			u8 typ_len_ext;
			u8 cmd;
		} flags;
	} lower;
	union {
		__le32 data;
		struct {
			u8 status;     /* Descriptor status */
			u8 popts;      /* Packet Options */
			__le16 special;
		} fields;
	} upper;
};

/* Statistics counters collected by the MAC */
struct e1000_hw_stats {
	u64 crcerrs;
	u64 algnerrc;
	u64 symerrs;
	u64 rxerrc;
	u64 mpc;
	u64 scc;
	u64 ecol;
	u64 mcc;
	u64 latecol;
	u64 colc;
	u64 dc;
	u64 tncrs;
	u64 sec;
	u64 cexterr;
	u64 rlec;
	u64 xonrxc;
	u64 xontxc;
	u64 xoffrxc;
	u64 xofftxc;
	u64 fcruc;
	u64 prc64;
	u64 prc127;
	u64 prc255;
	u64 prc511;
	u64 prc1023;
	u64 prc1522;
	u64 gprc;
	u64 bprc;
	u64 mprc;
	u64 gptc;
	u64 gorc;
	u64 gotc;
	u64 rnbc;
	u64 ruc;
	u64 rfc;
	u64 roc;
	u64 rjc;
	u64 mgprc;
	u64 mgpdc;
	u64 mgptc;
	u64 tor;
	u64 tot;
	u64 tpr;
	u64 tpt;
	u64 ptc64;
	u64 ptc127;
	u64 ptc255;
	u64 ptc511;
	u64 ptc1023;
	u64 ptc1522;
	u64 mptc;
	u64 bptc;
	u64 tsctc;
	u64 tsctfc;
	u64 iac;
	u64 icrxptc;
	u64 icrxatc;
	u64 ictxptc;
	u64 ictxatc;
	u64 ictxqec;
	u64 ictxqmtc;
	u64 icrxdmtc;
	u64 icrxoc;
};

struct e1000_phy_stats {
	u32 idle_errors;
	u32 receive_errors;
};

struct e1000_host_mng_dhcp_cookie {
	u32 signature;
	u8 status;
	u8 reserved0;
	u16 vlan_id;
	u32 reserved1;
	u16 reserved2;
	u8 reserved3;
	u8 checksum;
};

/* Host Interface "Rev 1" */
struct e1000_host_command_header {
	u8 command_id;
	u8 command_length;
	u8 command_options;
	u8 checksum;
};

#define E1000_HI_MAX_DATA_LENGTH	252
struct e1000_host_command_info {
	struct e1000_host_command_header command_header;
	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
};

/* Host Interface "Rev 2" */
struct e1000_host_mng_command_header {
	u8 command_id;
	u8 checksum;
	u16 reserved1;
	u16 reserved2;
	u16 command_length;
};

#define E1000_HI_MAX_MNG_DATA_LENGTH	0x6F8
struct e1000_host_mng_command_info {
	struct e1000_host_mng_command_header command_header;
	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
};

#include "mac.h"
#include "phy.h"
#include "nvm.h"
#include "manage.h"

/* Function pointers for the MAC. */
struct e1000_mac_operations {
	s32  (*id_led_init)(struct e1000_hw *);
	s32  (*blink_led)(struct e1000_hw *);
	bool (*check_mng_mode)(struct e1000_hw *);
	s32  (*check_for_link)(struct e1000_hw *);
	s32  (*cleanup_led)(struct e1000_hw *);
	void (*clear_hw_cntrs)(struct e1000_hw *);
	void (*clear_vfta)(struct e1000_hw *);
	s32  (*get_bus_info)(struct e1000_hw *);
	void (*set_lan_id)(struct e1000_hw *);
	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
	s32  (*led_on)(struct e1000_hw *);
	s32  (*led_off)(struct e1000_hw *);
	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
	s32  (*reset_hw)(struct e1000_hw *);
	s32  (*init_hw)(struct e1000_hw *);
	s32  (*setup_link)(struct e1000_hw *);
	s32  (*setup_physical_interface)(struct e1000_hw *);
	s32  (*setup_led)(struct e1000_hw *);
	void (*write_vfta)(struct e1000_hw *, u32, u32);
	void (*config_collision_dist)(struct e1000_hw *);
	void (*rar_set)(struct e1000_hw *, u8 *, u32);
	s32  (*read_mac_addr)(struct e1000_hw *);
};

/* When to use various PHY register access functions:
 *
 *                 Func   Caller
 *   Function      Does   Does    When to use
 *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 *   X_reg_locked  P,A    L       for multiple accesses of different regs
 *                                on different pages
 *   X_reg_page    A      L,P     for multiple accesses of different regs
 *                                on the same page
 *
 * Where X=[read|write], L=locking, P=sets page, A=register access
 *
 */
struct e1000_phy_operations {
	s32  (*acquire)(struct e1000_hw *);
	s32  (*cfg_on_link_up)(struct e1000_hw *);
	s32  (*check_polarity)(struct e1000_hw *);
	s32  (*check_reset_block)(struct e1000_hw *);
	s32  (*commit)(struct e1000_hw *);
	s32  (*force_speed_duplex)(struct e1000_hw *);
	s32  (*get_cfg_done)(struct e1000_hw *hw);
	s32  (*get_cable_length)(struct e1000_hw *);
	s32  (*get_info)(struct e1000_hw *);
	s32  (*set_page)(struct e1000_hw *, u16);
	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
	s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
	void (*release)(struct e1000_hw *);
	s32  (*reset)(struct e1000_hw *);
	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
	s32  (*write_reg)(struct e1000_hw *, u32, u16);
	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
	s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
	void (*power_up)(struct e1000_hw *);
	void (*power_down)(struct e1000_hw *);
};

/* Function pointers for the NVM. */
struct e1000_nvm_operations {
	s32  (*acquire)(struct e1000_hw *);
	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
	void (*release)(struct e1000_hw *);
	void (*reload)(struct e1000_hw *);
	s32  (*update)(struct e1000_hw *);
	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
	s32  (*validate)(struct e1000_hw *);
	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
};

struct e1000_mac_info {
	struct e1000_mac_operations ops;
	u8 addr[ETH_ALEN];
	u8 perm_addr[ETH_ALEN];

	enum e1000_mac_type type;

	u32 collision_delta;
	u32 ledctl_default;
	u32 ledctl_mode1;
	u32 ledctl_mode2;
	u32 mc_filter_type;
	u32 tx_packet_delta;
	u32 txcw;

	u16 current_ifs_val;
	u16 ifs_max_val;
	u16 ifs_min_val;
	u16 ifs_ratio;
	u16 ifs_step_size;
	u16 mta_reg_count;

	/* Maximum size of the MTA register table in all supported adapters */
#define MAX_MTA_REG 128
	u32 mta_shadow[MAX_MTA_REG];
	u16 rar_entry_count;

	u8 forced_speed_duplex;

	bool adaptive_ifs;
	bool has_fwsm;
	bool arc_subsystem_valid;
	bool autoneg;
	bool autoneg_failed;
	bool get_link_status;
	bool in_ifs_mode;
	bool serdes_has_link;
	bool tx_pkt_filtering;
	enum e1000_serdes_link_state serdes_link_state;
};

struct e1000_phy_info {
	struct e1000_phy_operations ops;

	enum e1000_phy_type type;

	enum e1000_1000t_rx_status local_rx;
	enum e1000_1000t_rx_status remote_rx;
	enum e1000_ms_type ms_type;
	enum e1000_ms_type original_ms_type;
	enum e1000_rev_polarity cable_polarity;
	enum e1000_smart_speed smart_speed;

	u32 addr;
	u32 id;
	u32 reset_delay_us;	/* in usec */
	u32 revision;

	enum e1000_media_type media_type;

	u16 autoneg_advertised;
	u16 autoneg_mask;
	u16 cable_length;
	u16 max_cable_length;
	u16 min_cable_length;

	u8 mdix;

	bool disable_polarity_correction;
	bool is_mdix;
	bool polarity_correction;
	bool speed_downgraded;
	bool autoneg_wait_to_complete;
};

struct e1000_nvm_info {
	struct e1000_nvm_operations ops;

	enum e1000_nvm_type type;
	enum e1000_nvm_override override;

	u32 flash_bank_size;
	u32 flash_base_addr;

	u16 word_size;
	u16 delay_usec;
	u16 address_bits;
	u16 opcode_bits;
	u16 page_size;
};

struct e1000_bus_info {
	enum e1000_bus_width width;

	u16 func;
};

struct e1000_fc_info {
	u32 high_water;          /* Flow control high-water mark */
	u32 low_water;           /* Flow control low-water mark */
	u16 pause_time;          /* Flow control pause timer */
	u16 refresh_time;        /* Flow control refresh timer */
	bool send_xon;           /* Flow control send XON */
	bool strict_ieee;        /* Strict IEEE mode */
	enum e1000_fc_mode current_mode; /* FC mode in effect */
	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
};

struct e1000_dev_spec_82571 {
	bool laa_is_present;
	u32 smb_counter;
};

struct e1000_dev_spec_80003es2lan {
	bool mdic_wa_enable;
};

struct e1000_shadow_ram {
	u16 value;
	bool modified;
};

#define E1000_ICH8_SHADOW_RAM_WORDS		2048

/* I218 PHY Ultra Low Power (ULP) states */
enum e1000_ulp_state {
	e1000_ulp_state_unknown,
	e1000_ulp_state_off,
	e1000_ulp_state_on,
};

struct e1000_dev_spec_ich8lan {
	bool kmrn_lock_loss_workaround_enabled;
	struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
	bool nvm_k1_enabled;
	bool eee_disable;
	u16 eee_lp_ability;
	enum e1000_ulp_state ulp_state;
};

struct e1000_hw {
	struct e1000_adapter *adapter;

	void __iomem *hw_addr;
	void __iomem *flash_address;

	struct e1000_mac_info mac;
	struct e1000_fc_info fc;
	struct e1000_phy_info phy;
	struct e1000_nvm_info nvm;
	struct e1000_bus_info bus;
	struct e1000_host_mng_dhcp_cookie mng_cookie;

	union {
		struct e1000_dev_spec_82571 e82571;
		struct e1000_dev_spec_80003es2lan e80003es2lan;
		struct e1000_dev_spec_ich8lan ich8lan;
	} dev_spec;
};

#include "82571.h"
#include "80003es2lan.h"
#include "ich8lan.h"

#endif
Commit	Line	Data
e78b80b1 DE	1	/* Intel PRO/1000 Linux driver
	2	* Copyright(c) 1999 - 2014 Intel Corporation.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* The full GNU General Public License is included in this distribution in
	14	* the file called "COPYING".
	15	*
	16	* Contact Information:
	17	* Linux NICS <linux.nics@intel.com>
	18	* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	19	* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	20	*/
bc7f75fa AK	21
	22	#ifndef _E1000_HW_H_
	23	#define _E1000_HW_H_
	24
c556d607	25	#include "regs.h"
a9bb6290	26	#include "defines.h"
bc7f75fa AK	27
bc7f75fa AK	28	struct e1000_hw;
bc7f75fa	29
bc7f75fa AK	30	#define E1000_DEV_ID_82571EB_COPPER 0x105E
	31	#define E1000_DEV_ID_82571EB_FIBER 0x105F
	32	#define E1000_DEV_ID_82571EB_SERDES 0x1060
	33	#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4
040babf9	34	#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5
bc7f75fa AK	35	#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5
bc7f75fa AK	36	#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
040babf9 AK	37	#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9
040babf9 AK	38	#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA
bc7f75fa AK	39	#define E1000_DEV_ID_82572EI_COPPER 0x107D
	40	#define E1000_DEV_ID_82572EI_FIBER 0x107E
	41	#define E1000_DEV_ID_82572EI_SERDES 0x107F
	42	#define E1000_DEV_ID_82572EI 0x10B9
	43	#define E1000_DEV_ID_82573E 0x108B
	44	#define E1000_DEV_ID_82573E_IAMT 0x108C
	45	#define E1000_DEV_ID_82573L 0x109A
4662e82b	46	#define E1000_DEV_ID_82574L 0x10D3
bef28b11	47	#define E1000_DEV_ID_82574LA 0x10F6
a9bb6290	48	#define E1000_DEV_ID_82583V 0x150C
bc7f75fa AK	49	#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
	50	#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
	51	#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
	52	#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
9e135a2e	53	#define E1000_DEV_ID_ICH8_82567V_3 0x1501
bc7f75fa AK	54	#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049
	55	#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A
	56	#define E1000_DEV_ID_ICH8_IGP_C 0x104B
	57	#define E1000_DEV_ID_ICH8_IFE 0x104C
	58	#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4
	59	#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
	60	#define E1000_DEV_ID_ICH8_IGP_M 0x104D
	61	#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD
2f15f9d6	62	#define E1000_DEV_ID_ICH9_BM 0x10E5
97ac8cae BA	63	#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5
	64	#define E1000_DEV_ID_ICH9_IGP_M 0x10BF
	65	#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB
bc7f75fa AK	66	#define E1000_DEV_ID_ICH9_IGP_C 0x294C
	67	#define E1000_DEV_ID_ICH9_IFE 0x10C0
	68	#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3
	69	#define E1000_DEV_ID_ICH9_IFE_G 0x10C2
97ac8cae BA	70	#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC
	71	#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD
	72	#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE
f4187b56 BA	73	#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE
f4187b56 BA	74	#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF
10df0b91	75	#define E1000_DEV_ID_ICH10_D_BM_V 0x1525
a4f58f54 BA	76	#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA
	77	#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB
	78	#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF
	79	#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0
d3738bb8 BA	80	#define E1000_DEV_ID_PCH2_LV_LM 0x1502
d3738bb8 BA	81	#define E1000_DEV_ID_PCH2_LV_V 0x1503
2fbe4526 BA	82	#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A
2fbe4526 BA	83	#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B
16e310ae BA	84	#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A
16e310ae BA	85	#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559
91a3d82f BA	86	#define E1000_DEV_ID_PCH_I218_LM2 0x15A0
	87	#define E1000_DEV_ID_PCH_I218_V2 0x15A1
	88	#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
	89	#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
bc7f75fa	90
a9bb6290	91	#define E1000_REVISION_4 4
4662e82b	92
a9bb6290	93	#define E1000_FUNC_1 1
bc7f75fa	94
a9bb6290 BA	95	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
a9bb6290 BA	96	#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
608f8a0d	97
bc7f75fa AK	98	enum e1000_mac_type {
	99	e1000_82571,
	100	e1000_82572,
	101	e1000_82573,
4662e82b	102	e1000_82574,
8c81c9c3	103	e1000_82583,
bc7f75fa AK	104	e1000_80003es2lan,
	105	e1000_ich8lan,
	106	e1000_ich9lan,
f4187b56	107	e1000_ich10lan,
a4f58f54	108	e1000_pchlan,
d3738bb8	109	e1000_pch2lan,
2fbe4526	110	e1000_pch_lpt,
bc7f75fa AK	111	};
	112
	113	enum e1000_media_type {
	114	e1000_media_type_unknown = 0,
	115	e1000_media_type_copper = 1,
	116	e1000_media_type_fiber = 2,
	117	e1000_media_type_internal_serdes = 3,
	118	e1000_num_media_types
	119	};
	120
	121	enum e1000_nvm_type {
	122	e1000_nvm_unknown = 0,
	123	e1000_nvm_none,
	124	e1000_nvm_eeprom_spi,
	125	e1000_nvm_flash_hw,
	126	e1000_nvm_flash_sw
	127	};
	128
	129	enum e1000_nvm_override {
	130	e1000_nvm_override_none = 0,
	131	e1000_nvm_override_spi_small,
	132	e1000_nvm_override_spi_large
	133	};
	134
	135	enum e1000_phy_type {
	136	e1000_phy_unknown = 0,
	137	e1000_phy_none,
	138	e1000_phy_m88,
	139	e1000_phy_igp,
	140	e1000_phy_igp_2,
	141	e1000_phy_gg82563,
	142	e1000_phy_igp_3,
	143	e1000_phy_ife,
97ac8cae	144	e1000_phy_bm,
a4f58f54 BA	145	e1000_phy_82578,
a4f58f54 BA	146	e1000_phy_82577,
d3738bb8	147	e1000_phy_82579,
2fbe4526	148	e1000_phy_i217,
bc7f75fa AK	149	};
	150
	151	enum e1000_bus_width {
	152	e1000_bus_width_unknown = 0,
	153	e1000_bus_width_pcie_x1,
	154	e1000_bus_width_pcie_x2,
	155	e1000_bus_width_pcie_x4 = 4,
	156	e1000_bus_width_32,
	157	e1000_bus_width_64,
	158	e1000_bus_width_reserved
	159	};
	160
	161	enum e1000_1000t_rx_status {
	162	e1000_1000t_rx_status_not_ok = 0,
	163	e1000_1000t_rx_status_ok,
	164	e1000_1000t_rx_status_undefined = 0xFF
	165	};
	166
362e20ca	167	enum e1000_rev_polarity {
bc7f75fa AK	168	e1000_rev_polarity_normal = 0,
	169	e1000_rev_polarity_reversed,
	170	e1000_rev_polarity_undefined = 0xFF
	171	};
	172
5c48ef3e	173	enum e1000_fc_mode {
bc7f75fa AK	174	e1000_fc_none = 0,
	175	e1000_fc_rx_pause,
	176	e1000_fc_tx_pause,
	177	e1000_fc_full,
	178	e1000_fc_default = 0xFF
	179	};
	180
	181	enum e1000_ms_type {
	182	e1000_ms_hw_default = 0,
	183	e1000_ms_force_master,
	184	e1000_ms_force_slave,
	185	e1000_ms_auto
	186	};
	187
	188	enum e1000_smart_speed {
	189	e1000_smart_speed_default = 0,
	190	e1000_smart_speed_on,
	191	e1000_smart_speed_off
	192	};
	193
c9523379	194	enum e1000_serdes_link_state {
	195	e1000_serdes_link_down = 0,
	196	e1000_serdes_link_autoneg_progress,
	197	e1000_serdes_link_autoneg_complete,
	198	e1000_serdes_link_forced_up
	199	};
	200
bc7f75fa AK	201	/* Receive Descriptor - Extended */
	202	union e1000_rx_desc_extended {
	203	struct {
a39fe742 AV	204	__le64 buffer_addr;
a39fe742 AV	205	__le64 reserved;
bc7f75fa AK	206	} read;
	207	struct {
	208	struct {
a39fe742	209	__le32 mrq; /* Multiple Rx Queues */
bc7f75fa	210	union {
a39fe742	211	__le32 rss; /* RSS Hash */
bc7f75fa	212	struct {
a39fe742 AV	213	__le16 ip_id; /* IP id */
a39fe742 AV	214	__le16 csum; /* Packet Checksum */
bc7f75fa AK	215	} csum_ip;
	216	} hi_dword;
	217	} lower;
	218	struct {
a39fe742 AV	219	__le32 status_error; /* ext status/error */
	220	__le16 length;
	221	__le16 vlan; /* VLAN tag */
bc7f75fa AK	222	} upper;
	223	} wb; /* writeback */
	224	};
	225
	226	#define MAX_PS_BUFFERS 4
c96ddb0b WY	227
c96ddb0b WY	228	/* Number of packet split data buffers (not including the header buffer) */
0cf04597 BA	229	#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
0cf04597 BA	230
bc7f75fa AK	231	/* Receive Descriptor - Packet Split */
	232	union e1000_rx_desc_packet_split {
	233	struct {
	234	/* one buffer for protocol header(s), three data buffers */
a39fe742	235	__le64 buffer_addr[MAX_PS_BUFFERS];
bc7f75fa AK	236	} read;
	237	struct {
	238	struct {
a39fe742	239	__le32 mrq; /* Multiple Rx Queues */
bc7f75fa	240	union {
a39fe742	241	__le32 rss; /* RSS Hash */
bc7f75fa	242	struct {
a39fe742 AV	243	__le16 ip_id; /* IP id */
a39fe742 AV	244	__le16 csum; /* Packet Checksum */
bc7f75fa AK	245	} csum_ip;
	246	} hi_dword;
	247	} lower;
	248	struct {
a39fe742 AV	249	__le32 status_error; /* ext status/error */
	250	__le16 length0; /* length of buffer 0 */
	251	__le16 vlan; /* VLAN tag */
bc7f75fa AK	252	} middle;
bc7f75fa AK	253	struct {
a39fe742	254	__le16 header_status;
c96ddb0b WY	255	/* length of buffers 1-3 */
c96ddb0b WY	256	__le16 length[PS_PAGE_BUFFERS];
bc7f75fa	257	} upper;
a39fe742	258	__le64 reserved;
bc7f75fa AK	259	} wb; /* writeback */
	260	};
	261
	262	/* Transmit Descriptor */
	263	struct e1000_tx_desc {
a39fe742	264	__le64 buffer_addr; /* Address of the descriptor's data buffer */
bc7f75fa	265	union {
a39fe742	266	__le32 data;
bc7f75fa	267	struct {
a39fe742	268	__le16 length; /* Data buffer length */
bc7f75fa AK	269	u8 cso; /* Checksum offset */
	270	u8 cmd; /* Descriptor control */
	271	} flags;
	272	} lower;
	273	union {
a39fe742	274	__le32 data;
bc7f75fa AK	275	struct {
	276	u8 status; /* Descriptor status */
	277	u8 css; /* Checksum start */
a39fe742	278	__le16 special;
bc7f75fa AK	279	} fields;
	280	} upper;
	281	};
	282
	283	/* Offload Context Descriptor */
	284	struct e1000_context_desc {
	285	union {
a39fe742	286	__le32 ip_config;
bc7f75fa AK	287	struct {
	288	u8 ipcss; /* IP checksum start */
	289	u8 ipcso; /* IP checksum offset */
a39fe742	290	__le16 ipcse; /* IP checksum end */
bc7f75fa AK	291	} ip_fields;
	292	} lower_setup;
	293	union {
a39fe742	294	__le32 tcp_config;
bc7f75fa AK	295	struct {
	296	u8 tucss; /* TCP checksum start */
	297	u8 tucso; /* TCP checksum offset */
a39fe742	298	__le16 tucse; /* TCP checksum end */
bc7f75fa AK	299	} tcp_fields;
bc7f75fa AK	300	} upper_setup;
a39fe742	301	__le32 cmd_and_length;
bc7f75fa	302	union {
a39fe742	303	__le32 data;
bc7f75fa AK	304	struct {
	305	u8 status; /* Descriptor status */
	306	u8 hdr_len; /* Header length */
a39fe742	307	__le16 mss; /* Maximum segment size */
bc7f75fa AK	308	} fields;
	309	} tcp_seg_setup;
	310	};
	311
	312	/* Offload data descriptor */
	313	struct e1000_data_desc {
a39fe742	314	__le64 buffer_addr; /* Address of the descriptor's buffer address */
bc7f75fa	315	union {
a39fe742	316	__le32 data;
bc7f75fa	317	struct {
a39fe742	318	__le16 length; /* Data buffer length */
bc7f75fa AK	319	u8 typ_len_ext;
	320	u8 cmd;
	321	} flags;
	322	} lower;
	323	union {
a39fe742	324	__le32 data;
bc7f75fa AK	325	struct {
	326	u8 status; /* Descriptor status */
	327	u8 popts; /* Packet Options */
a9bb6290	328	__le16 special;
bc7f75fa AK	329	} fields;
	330	} upper;
	331	};
	332
	333	/* Statistics counters collected by the MAC */
	334	struct e1000_hw_stats {
	335	u64 crcerrs;
	336	u64 algnerrc;
	337	u64 symerrs;
	338	u64 rxerrc;
	339	u64 mpc;
	340	u64 scc;
	341	u64 ecol;
	342	u64 mcc;
	343	u64 latecol;
	344	u64 colc;
	345	u64 dc;
	346	u64 tncrs;
	347	u64 sec;
	348	u64 cexterr;
	349	u64 rlec;
	350	u64 xonrxc;
	351	u64 xontxc;
	352	u64 xoffrxc;
	353	u64 xofftxc;
	354	u64 fcruc;
	355	u64 prc64;
	356	u64 prc127;
	357	u64 prc255;
	358	u64 prc511;
	359	u64 prc1023;
	360	u64 prc1522;
	361	u64 gprc;
	362	u64 bprc;
	363	u64 mprc;
	364	u64 gptc;
7c25769f BA	365	u64 gorc;
7c25769f BA	366	u64 gotc;
bc7f75fa AK	367	u64 rnbc;
	368	u64 ruc;
	369	u64 rfc;
	370	u64 roc;
	371	u64 rjc;
	372	u64 mgprc;
	373	u64 mgpdc;
	374	u64 mgptc;
7c25769f BA	375	u64 tor;
7c25769f BA	376	u64 tot;
bc7f75fa AK	377	u64 tpr;
	378	u64 tpt;
	379	u64 ptc64;
	380	u64 ptc127;
	381	u64 ptc255;
	382	u64 ptc511;
	383	u64 ptc1023;
	384	u64 ptc1522;
	385	u64 mptc;
	386	u64 bptc;
	387	u64 tsctc;
	388	u64 tsctfc;
	389	u64 iac;
	390	u64 icrxptc;
	391	u64 icrxatc;
	392	u64 ictxptc;
	393	u64 ictxatc;
	394	u64 ictxqec;
	395	u64 ictxqmtc;
	396	u64 icrxdmtc;
	397	u64 icrxoc;
	398	};
	399
	400	struct e1000_phy_stats {
	401	u32 idle_errors;
	402	u32 receive_errors;
	403	};
	404
	405	struct e1000_host_mng_dhcp_cookie {
	406	u32 signature;
e80bd1d1 BA	407	u8 status;
e80bd1d1 BA	408	u8 reserved0;
bc7f75fa AK	409	u16 vlan_id;
	410	u32 reserved1;
	411	u16 reserved2;
e80bd1d1 BA	412	u8 reserved3;
e80bd1d1 BA	413	u8 checksum;
bc7f75fa AK	414	};
	415
	416	/* Host Interface "Rev 1" */
	417	struct e1000_host_command_header {
	418	u8 command_id;
	419	u8 command_length;
	420	u8 command_options;
	421	u8 checksum;
	422	};
	423
a9bb6290	424	#define E1000_HI_MAX_DATA_LENGTH 252
bc7f75fa AK	425	struct e1000_host_command_info {
	426	struct e1000_host_command_header command_header;
	427	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
	428	};
	429
	430	/* Host Interface "Rev 2" */
	431	struct e1000_host_mng_command_header {
e80bd1d1 BA	432	u8 command_id;
e80bd1d1 BA	433	u8 checksum;
bc7f75fa AK	434	u16 reserved1;
	435	u16 reserved2;
	436	u16 command_length;
	437	};
	438
a9bb6290	439	#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
bc7f75fa AK	440	struct e1000_host_mng_command_info {
	441	struct e1000_host_mng_command_header command_header;
	442	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
	443	};
	444
bdfe2da6	445	#include "mac.h"
93b9f8bf	446	#include "phy.h"
d2263113	447	#include "nvm.h"
948f97ac	448	#include "manage.h"
bdfe2da6	449
a9bb6290	450	/* Function pointers for the MAC. */
bc7f75fa	451	struct e1000_mac_operations {
a4f58f54	452	s32 (id_led_init)(struct e1000_hw );
dbf80dcb	453	s32 (blink_led)(struct e1000_hw );
4662e82b	454	bool (check_mng_mode)(struct e1000_hw );
bc7f75fa AK	455	s32 (check_for_link)(struct e1000_hw );
	456	s32 (cleanup_led)(struct e1000_hw );
	457	void (clear_hw_cntrs)(struct e1000_hw );
caaddaf8	458	void (clear_vfta)(struct e1000_hw );
bc7f75fa	459	s32 (get_bus_info)(struct e1000_hw );
f4d2dd4c	460	void (set_lan_id)(struct e1000_hw );
bc7f75fa AK	461	s32 (get_link_up_info)(struct e1000_hw , u16 , u16 );
	462	s32 (led_on)(struct e1000_hw );
	463	s32 (led_off)(struct e1000_hw );
ab8932f3	464	void (update_mc_addr_list)(struct e1000_hw , u8 *, u32);
bc7f75fa AK	465	s32 (reset_hw)(struct e1000_hw );
	466	s32 (init_hw)(struct e1000_hw );
	467	s32 (setup_link)(struct e1000_hw );
	468	s32 (setup_physical_interface)(struct e1000_hw );
a4f58f54	469	s32 (setup_led)(struct e1000_hw );
caaddaf8	470	void (write_vfta)(struct e1000_hw , u32, u32);
57cde763	471	void (config_collision_dist)(struct e1000_hw );
69e1e019	472	void (rar_set)(struct e1000_hw , u8 *, u32);
608f8a0d	473	s32 (read_mac_addr)(struct e1000_hw );
bc7f75fa AK	474	};
bc7f75fa AK	475
e921eb1a	476	/* When to use various PHY register access functions:
2b6b168d BA	477	*
	478	* Func Caller
	479	* Function Does Does When to use
	480	* ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
	481	* X_reg L,P,A n/a for simple PHY reg accesses
	482	* X_reg_locked P,A L for multiple accesses of different regs
	483	* on different pages
	484	* X_reg_page A L,P for multiple accesses of different regs
	485	* on the same page
	486	*
	487	* Where X=[read\|write], L=locking, P=sets page, A=register access
	488	*
	489	*/
bc7f75fa	490	struct e1000_phy_operations {
94d8186a BA	491	s32 (acquire)(struct e1000_hw );
94d8186a BA	492	s32 (cfg_on_link_up)(struct e1000_hw );
a4f58f54	493	s32 (check_polarity)(struct e1000_hw );
bc7f75fa	494	s32 (check_reset_block)(struct e1000_hw );
94d8186a	495	s32 (commit)(struct e1000_hw );
bc7f75fa AK	496	s32 (force_speed_duplex)(struct e1000_hw );
	497	s32 (get_cfg_done)(struct e1000_hw hw);
	498	s32 (get_cable_length)(struct e1000_hw );
94d8186a	499	s32 (get_info)(struct e1000_hw );
2b6b168d	500	s32 (set_page)(struct e1000_hw , u16);
94d8186a BA	501	s32 (read_reg)(struct e1000_hw , u32, u16 *);
94d8186a BA	502	s32 (read_reg_locked)(struct e1000_hw , u32, u16 *);
2b6b168d	503	s32 (read_reg_page)(struct e1000_hw , u32, u16 *);
94d8186a BA	504	void (release)(struct e1000_hw );
94d8186a BA	505	s32 (reset)(struct e1000_hw );
bc7f75fa AK	506	s32 (set_d0_lplu_state)(struct e1000_hw , bool);
bc7f75fa AK	507	s32 (set_d3_lplu_state)(struct e1000_hw , bool);
94d8186a BA	508	s32 (write_reg)(struct e1000_hw , u32, u16);
94d8186a BA	509	s32 (write_reg_locked)(struct e1000_hw , u32, u16);
2b6b168d	510	s32 (write_reg_page)(struct e1000_hw , u32, u16);
17f208de BA	511	void (power_up)(struct e1000_hw );
17f208de BA	512	void (power_down)(struct e1000_hw );
bc7f75fa AK	513	};
	514
	515	/* Function pointers for the NVM. */
	516	struct e1000_nvm_operations {
94d8186a BA	517	s32 (acquire)(struct e1000_hw );
	518	s32 (read)(struct e1000_hw , u16, u16, u16 *);
	519	void (release)(struct e1000_hw );
e85e3639	520	void (reload)(struct e1000_hw );
94d8186a	521	s32 (update)(struct e1000_hw );
bc7f75fa	522	s32 (valid_led_default)(struct e1000_hw , u16 *);
94d8186a BA	523	s32 (validate)(struct e1000_hw );
94d8186a BA	524	s32 (write)(struct e1000_hw , u16, u16, u16 *);
bc7f75fa AK	525	};
	526
	527	struct e1000_mac_info {
	528	struct e1000_mac_operations ops;
d8d5f8ae BA	529	u8 addr[ETH_ALEN];
d8d5f8ae BA	530	u8 perm_addr[ETH_ALEN];
bc7f75fa AK	531
bc7f75fa AK	532	enum e1000_mac_type type;
bc7f75fa AK	533
	534	u32 collision_delta;
	535	u32 ledctl_default;
	536	u32 ledctl_mode1;
	537	u32 ledctl_mode2;
bc7f75fa	538	u32 mc_filter_type;
bc7f75fa AK	539	u32 tx_packet_delta;
	540	u32 txcw;
	541
	542	u16 current_ifs_val;
	543	u16 ifs_max_val;
	544	u16 ifs_min_val;
	545	u16 ifs_ratio;
	546	u16 ifs_step_size;
	547	u16 mta_reg_count;
ab8932f3 BA	548
ab8932f3 BA	549	/* Maximum size of the MTA register table in all supported adapters */
f0ff4398	550	#define MAX_MTA_REG 128
ab8932f3	551	u32 mta_shadow[MAX_MTA_REG];
bc7f75fa	552	u16 rar_entry_count;
bc7f75fa	553
e80bd1d1	554	u8 forced_speed_duplex;
bc7f75fa	555
f464ba87	556	bool adaptive_ifs;
a65a4a0d	557	bool has_fwsm;
bc7f75fa AK	558	bool arc_subsystem_valid;
	559	bool autoneg;
	560	bool autoneg_failed;
	561	bool get_link_status;
	562	bool in_ifs_mode;
	563	bool serdes_has_link;
	564	bool tx_pkt_filtering;
c9523379	565	enum e1000_serdes_link_state serdes_link_state;
bc7f75fa AK	566	};
	567
	568	struct e1000_phy_info {
	569	struct e1000_phy_operations ops;
	570
	571	enum e1000_phy_type type;
	572
	573	enum e1000_1000t_rx_status local_rx;
	574	enum e1000_1000t_rx_status remote_rx;
	575	enum e1000_ms_type ms_type;
	576	enum e1000_ms_type original_ms_type;
	577	enum e1000_rev_polarity cable_polarity;
	578	enum e1000_smart_speed smart_speed;
	579
	580	u32 addr;
	581	u32 id;
e80bd1d1	582	u32 reset_delay_us; /* in usec */
bc7f75fa AK	583	u32 revision;
bc7f75fa AK	584
318a94d6 JK	585	enum e1000_media_type media_type;
318a94d6 JK	586
bc7f75fa AK	587	u16 autoneg_advertised;
	588	u16 autoneg_mask;
	589	u16 cable_length;
	590	u16 max_cable_length;
	591	u16 min_cable_length;
	592
	593	u8 mdix;
	594
	595	bool disable_polarity_correction;
	596	bool is_mdix;
	597	bool polarity_correction;
	598	bool speed_downgraded;
318a94d6	599	bool autoneg_wait_to_complete;
bc7f75fa AK	600	};
	601
	602	struct e1000_nvm_info {
	603	struct e1000_nvm_operations ops;
	604
	605	enum e1000_nvm_type type;
	606	enum e1000_nvm_override override;
	607
	608	u32 flash_bank_size;
	609	u32 flash_base_addr;
	610
	611	u16 word_size;
	612	u16 delay_usec;
	613	u16 address_bits;
	614	u16 opcode_bits;
	615	u16 page_size;
	616	};
	617
	618	struct e1000_bus_info {
	619	enum e1000_bus_width width;
	620
	621	u16 func;
	622	};
	623
318a94d6 JK	624	struct e1000_fc_info {
	625	u32 high_water; /* Flow control high-water mark */
	626	u32 low_water; /* Flow control low-water mark */
	627	u16 pause_time; /* Flow control pause timer */
a305595b	628	u16 refresh_time; /* Flow control refresh timer */
318a94d6 JK	629	bool send_xon; /* Flow control send XON */
318a94d6 JK	630	bool strict_ieee; /* Strict IEEE mode */
5c48ef3e BA	631	enum e1000_fc_mode current_mode; /* FC mode in effect */
5c48ef3e BA	632	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
318a94d6 JK	633	};
318a94d6 JK	634
bc7f75fa AK	635	struct e1000_dev_spec_82571 {
bc7f75fa AK	636	bool laa_is_present;
23a2d1b2	637	u32 smb_counter;
bc7f75fa AK	638	};
bc7f75fa AK	639
3421eecd	640	struct e1000_dev_spec_80003es2lan {
e80bd1d1	641	bool mdic_wa_enable;
3421eecd BA	642	};
3421eecd BA	643
bc7f75fa	644	struct e1000_shadow_ram {
e80bd1d1	645	u16 value;
bc7f75fa AK	646	bool modified;
	647	};
	648
	649	#define E1000_ICH8_SHADOW_RAM_WORDS 2048
	650
74f350ee DE	651	/* I218 PHY Ultra Low Power (ULP) states */
	652	enum e1000_ulp_state {
	653	e1000_ulp_state_unknown,
	654	e1000_ulp_state_off,
	655	e1000_ulp_state_on,
	656	};
	657
bc7f75fa AK	658	struct e1000_dev_spec_ich8lan {
	659	bool kmrn_lock_loss_workaround_enabled;
	660	struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
1d5846b9	661	bool nvm_k1_enabled;
e52997f9	662	bool eee_disable;
2fbe4526	663	u16 eee_lp_ability;
74f350ee	664	enum e1000_ulp_state ulp_state;
bc7f75fa AK	665	};
	666
	667	struct e1000_hw {
	668	struct e1000_adapter *adapter;
	669
c5083cf6 BA	670	void __iomem *hw_addr;
c5083cf6 BA	671	void __iomem *flash_address;
bc7f75fa	672
e80bd1d1 BA	673	struct e1000_mac_info mac;
	674	struct e1000_fc_info fc;
	675	struct e1000_phy_info phy;
	676	struct e1000_nvm_info nvm;
	677	struct e1000_bus_info bus;
bc7f75fa AK	678	struct e1000_host_mng_dhcp_cookie mng_cookie;
	679
	680	union {
e80bd1d1	681	struct e1000_dev_spec_82571 e82571;
3421eecd	682	struct e1000_dev_spec_80003es2lan e80003es2lan;
e80bd1d1	683	struct e1000_dev_spec_ich8lan ich8lan;
bc7f75fa	684	} dev_spec;
bc7f75fa AK	685	};
bc7f75fa AK	686
f25701df	687	#include "82571.h"
21b5a6f8	688	#include "80003es2lan.h"
1b41db37	689	#include "ich8lan.h"
f25701df	690
bc7f75fa	691	#endif