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1 | /* Intel PRO/1000 Linux driver |
2 | * Copyright(c) 1999 - 2014 Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * The full GNU General Public License is included in this distribution in | |
14 | * the file called "COPYING". | |
15 | * | |
16 | * Contact Information: | |
17 | * Linux NICS <linux.nics@intel.com> | |
18 | * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> | |
19 | * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
20 | */ | |
21b5a6f8 BA |
21 | |
22 | #ifndef _E1000E_80003ES2LAN_H_ | |
23 | #define _E1000E_80003ES2LAN_H_ | |
24 | ||
25 | #define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00 | |
26 | #define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02 | |
27 | #define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10 | |
28 | #define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F | |
29 | ||
30 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008 | |
31 | #define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800 | |
32 | #define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010 | |
33 | ||
34 | #define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004 | |
35 | #define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000 | |
36 | #define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 | |
37 | ||
38 | #define E1000_KMRNCTRLSTA_OPMODE_MASK 0x000C | |
39 | #define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO 0x0004 | |
40 | ||
41 | #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gig Carry Extend Padding */ | |
42 | #define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000 | |
43 | ||
44 | #define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8 | |
45 | #define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9 | |
46 | ||
47 | /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ | |
48 | #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Dis */ | |
49 | #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 | |
50 | #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */ | |
51 | #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */ | |
52 | #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */ | |
53 | ||
54 | /* PHY Specific Control Register 2 (Page 0, Register 26) */ | |
55 | #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Neg */ | |
56 | ||
57 | /* MAC Specific Control Register (Page 2, Register 21) */ | |
58 | /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ | |
59 | #define GG82563_MSCR_TX_CLK_MASK 0x0007 | |
60 | #define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 | |
61 | #define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 | |
62 | #define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 | |
63 | ||
64 | #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ | |
65 | ||
66 | /* DSP Distance Register (Page 5, Register 26) | |
67 | * 0 = <50M | |
68 | * 1 = 50-80M | |
69 | * 2 = 80-100M | |
70 | * 3 = 110-140M | |
71 | * 4 = >140M | |
72 | */ | |
73 | #define GG82563_DSPD_CABLE_LENGTH 0x0007 | |
74 | ||
75 | /* Kumeran Mode Control Register (Page 193, Register 16) */ | |
76 | #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 | |
77 | ||
78 | /* Max number of times Kumeran read/write should be validated */ | |
79 | #define GG82563_MAX_KMRN_RETRY 0x5 | |
80 | ||
81 | /* Power Management Control Register (Page 193, Register 20) */ | |
82 | /* 1=Enable SERDES Electrical Idle */ | |
83 | #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 | |
84 | ||
85 | /* In-Band Control Register (Page 194, Register 18) */ | |
86 | #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */ | |
87 | ||
88 | #endif |