[linux-block.git] / drivers / net / ethernet / huawei / hinic / hinic_hw_dev.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Huawei HiNIC PCI Express Linux driver
 * Copyright(c) 2017 Huawei Technologies Co., Ltd
 */

#ifndef HINIC_HW_DEV_H
#define HINIC_HW_DEV_H

#include <linux/pci.h>
#include <linux/types.h>
#include <linux/bitops.h>

#include "hinic_hw_if.h"
#include "hinic_hw_eqs.h"
#include "hinic_hw_mgmt.h"
#include "hinic_hw_qp.h"
#include "hinic_hw_io.h"

#define HINIC_MAX_QPS   32

#define HINIC_MGMT_NUM_MSG_CMD  (HINIC_MGMT_MSG_CMD_MAX - \
				 HINIC_MGMT_MSG_CMD_BASE)

struct hinic_cap {
	u16     max_qps;
	u16     num_qps;
};

enum hinic_port_cmd {
	HINIC_PORT_CMD_CHANGE_MTU       = 2,

	HINIC_PORT_CMD_ADD_VLAN         = 3,
	HINIC_PORT_CMD_DEL_VLAN         = 4,

	HINIC_PORT_CMD_SET_MAC          = 9,
	HINIC_PORT_CMD_GET_MAC          = 10,
	HINIC_PORT_CMD_DEL_MAC          = 11,

	HINIC_PORT_CMD_SET_RX_MODE      = 12,

	HINIC_PORT_CMD_GET_LINK_STATE   = 24,

	HINIC_PORT_CMD_SET_LRO		= 25,

	HINIC_PORT_CMD_SET_RX_CSUM	= 26,

	HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 27,

	HINIC_PORT_CMD_GET_PORT_STATISTICS = 28,

	HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 29,

	HINIC_PORT_CMD_GET_VPORT_STAT	= 30,

	HINIC_PORT_CMD_CLEAN_VPORT_STAT	= 31,

	HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 37,

	HINIC_PORT_CMD_SET_PORT_STATE   = 41,

	HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 43,

	HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 44,

	HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 45,

	HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 46,

	HINIC_PORT_CMD_GET_RSS_CTX_TBL  = 47,

	HINIC_PORT_CMD_SET_RSS_CTX_TBL  = 48,

	HINIC_PORT_CMD_RSS_TEMP_MGR	= 49,

	HINIC_PORT_CMD_RSS_CFG		= 66,

	HINIC_PORT_CMD_FWCTXT_INIT      = 69,

	HINIC_PORT_CMD_GET_MGMT_VERSION = 88,

	HINIC_PORT_CMD_SET_FUNC_STATE   = 93,

	HINIC_PORT_CMD_GET_GLOBAL_QPN   = 102,

	HINIC_PORT_CMD_SET_TSO          = 112,

	HINIC_PORT_CMD_SET_RQ_IQ_MAP	= 115,

	HINIC_PORT_CMD_GET_CAP          = 170,

	HINIC_PORT_CMD_SET_LRO_TIMER	= 244,
};

enum hinic_ucode_cmd {
	HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT    = 0,
	HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,
	HINIC_UCODE_CMD_ARM_SQ,
	HINIC_UCODE_CMD_ARM_RQ,
	HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,
	HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,
	HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE,
	HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE,
	HINIC_UCODE_CMD_SET_IQ_ENABLE,
	HINIC_UCODE_CMD_SET_RQ_FLUSH            = 10
};

#define NIC_RSS_CMD_TEMP_ALLOC  0x01
#define NIC_RSS_CMD_TEMP_FREE   0x02

enum hinic_mgmt_msg_cmd {
	HINIC_MGMT_MSG_CMD_BASE         = 160,

	HINIC_MGMT_MSG_CMD_LINK_STATUS  = 160,

	HINIC_MGMT_MSG_CMD_MAX,
};

enum hinic_cb_state {
	HINIC_CB_ENABLED = BIT(0),
	HINIC_CB_RUNNING = BIT(1),
};

enum hinic_res_state {
	HINIC_RES_CLEAN         = 0,
	HINIC_RES_ACTIVE        = 1,
};

struct hinic_cmd_fw_ctxt {
	u8      status;
	u8      version;
	u8      rsvd0[6];

	u16     func_idx;
	u16     rx_buf_sz;

	u32     rsvd1;
};

struct hinic_cmd_hw_ioctxt {
	u8      status;
	u8      version;
	u8      rsvd0[6];

	u16     func_idx;

	u16     rsvd1;

	u8      set_cmdq_depth;
	u8      cmdq_depth;

	u8      lro_en;
	u8      rsvd3;
	u8      ppf_idx;
	u8      rsvd4;

	u16     rq_depth;
	u16     rx_buf_sz_idx;
	u16     sq_depth;
};

struct hinic_cmd_io_status {
	u8      status;
	u8      version;
	u8      rsvd0[6];

	u16     func_idx;
	u8      rsvd1;
	u8      rsvd2;
	u32     io_status;
};

struct hinic_cmd_clear_io_res {
	u8      status;
	u8      version;
	u8      rsvd0[6];

	u16     func_idx;
	u8      rsvd1;
	u8      rsvd2;
};

struct hinic_cmd_set_res_state {
	u8      status;
	u8      version;
	u8      rsvd0[6];

	u16     func_idx;
	u8      state;
	u8      rsvd1;
	u32     rsvd2;
};

struct hinic_cmd_base_qpn {
	u8      status;
	u8      version;
	u8      rsvd0[6];

	u16     func_idx;
	u16     qpn;
};

struct hinic_cmd_hw_ci {
	u8      status;
	u8      version;
	u8      rsvd0[6];

	u16     func_idx;

	u8      dma_attr_off;
	u8      pending_limit;
	u8      coalesc_timer;

	u8      msix_en;
	u16     msix_entry_idx;

	u32     sq_id;
	u32     rsvd1;
	u64     ci_addr;
};

struct hinic_hwdev {
	struct hinic_hwif               *hwif;
	struct msix_entry               *msix_entries;

	struct hinic_aeqs               aeqs;
	struct hinic_func_to_io         func_to_io;

	struct hinic_cap                nic_cap;
};

struct hinic_nic_cb {
	void    (*handler)(void *handle, void *buf_in,
			   u16 in_size, void *buf_out,
			   u16 *out_size);

	void            *handle;
	unsigned long   cb_state;
};

struct hinic_pfhwdev {
	struct hinic_hwdev              hwdev;

	struct hinic_pf_to_mgmt         pf_to_mgmt;

	struct hinic_nic_cb             nic_cb[HINIC_MGMT_NUM_MSG_CMD];
};

void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,
			     enum hinic_mgmt_msg_cmd cmd, void *handle,
			     void (*handler)(void *handle, void *buf_in,
					     u16 in_size, void *buf_out,
					     u16 *out_size));

void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,
			       enum hinic_mgmt_msg_cmd cmd);

int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,
		       void *buf_in, u16 in_size, void *buf_out,
		       u16 *out_size);

int hinic_hwdev_ifup(struct hinic_hwdev *hwdev);

void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev);

struct hinic_hwdev *hinic_init_hwdev(struct pci_dev *pdev);

void hinic_free_hwdev(struct hinic_hwdev *hwdev);

int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev);

int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev);

struct hinic_sq *hinic_hwdev_get_sq(struct hinic_hwdev *hwdev, int i);

struct hinic_rq *hinic_hwdev_get_rq(struct hinic_hwdev *hwdev, int i);

int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index);

int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,
			 u8 pending_limit, u8 coalesc_timer,
			 u8 lli_timer_cfg, u8 lli_credit_limit,
			 u8 resend_timer);

int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev *hwdev, struct hinic_sq *sq,
			       u8 pending_limit, u8 coalesc_timer);

void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index,
				enum hinic_msix_state flag);

#endif
Commit	Line	Data
2025cf9e	1	/* SPDX-License-Identifier: GPL-2.0-only */
51ba902a AK	2	/*
	3	* Huawei HiNIC PCI Express Linux driver
	4	* Copyright(c) 2017 Huawei Technologies Co., Ltd
51ba902a AK	5	*/
	6
	7	#ifndef HINIC_HW_DEV_H
	8	#define HINIC_HW_DEV_H
	9
	10	#include <linux/pci.h>
a5564e7e	11	#include <linux/types.h>
c4d06d2d	12	#include <linux/bitops.h>
51ba902a AK	13
51ba902a AK	14	#include "hinic_hw_if.h"
a5564e7e AK	15	#include "hinic_hw_eqs.h"
a5564e7e AK	16	#include "hinic_hw_mgmt.h"
c3e79baf AK	17	#include "hinic_hw_qp.h"
c3e79baf AK	18	#include "hinic_hw_io.h"
51ba902a AK	19
	20	#define HINIC_MAX_QPS 32
	21
c4d06d2d AK	22	#define HINIC_MGMT_NUM_MSG_CMD (HINIC_MGMT_MSG_CMD_MAX - \
	23	HINIC_MGMT_MSG_CMD_BASE)
	24
a5564e7e AK	25	struct hinic_cap {
	26	u16 max_qps;
	27	u16 num_qps;
	28	};
	29
25a3ba61 AK	30	enum hinic_port_cmd {
	31	HINIC_PORT_CMD_CHANGE_MTU = 2,
	32
	33	HINIC_PORT_CMD_ADD_VLAN = 3,
	34	HINIC_PORT_CMD_DEL_VLAN = 4,
	35
	36	HINIC_PORT_CMD_SET_MAC = 9,
	37	HINIC_PORT_CMD_GET_MAC = 10,
	38	HINIC_PORT_CMD_DEL_MAC = 11,
	39
	40	HINIC_PORT_CMD_SET_RX_MODE = 12,
	41
	42	HINIC_PORT_CMD_GET_LINK_STATE = 24,
	43
1e007181 XC	44	HINIC_PORT_CMD_SET_LRO = 25,
1e007181 XC	45
4a61abb1 XC	46	HINIC_PORT_CMD_SET_RX_CSUM = 26,
4a61abb1 XC	47
aebd17b7 XC	48	HINIC_PORT_CMD_SET_RX_VLAN_OFFLOAD = 27,
aebd17b7 XC	49
e54fbbdf XC	50	HINIC_PORT_CMD_GET_PORT_STATISTICS = 28,
	51
	52	HINIC_PORT_CMD_CLEAR_PORT_STATISTICS = 29,
	53
	54	HINIC_PORT_CMD_GET_VPORT_STAT = 30,
	55
	56	HINIC_PORT_CMD_CLEAN_VPORT_STAT = 31,
	57
4fdc51bb XC	58	HINIC_PORT_CMD_GET_RSS_TEMPLATE_INDIR_TBL = 37,
4fdc51bb XC	59
25a3ba61 AK	60	HINIC_PORT_CMD_SET_PORT_STATE = 41,
25a3ba61 AK	61
421e9526 XC	62	HINIC_PORT_CMD_SET_RSS_TEMPLATE_TBL = 43,
421e9526 XC	63
4fdc51bb XC	64	HINIC_PORT_CMD_GET_RSS_TEMPLATE_TBL = 44,
	65
	66	HINIC_PORT_CMD_SET_RSS_HASH_ENGINE = 45,
	67
	68	HINIC_PORT_CMD_GET_RSS_HASH_ENGINE = 46,
	69
	70	HINIC_PORT_CMD_GET_RSS_CTX_TBL = 47,
	71
	72	HINIC_PORT_CMD_SET_RSS_CTX_TBL = 48,
421e9526 XC	73
	74	HINIC_PORT_CMD_RSS_TEMP_MGR = 49,
	75
	76	HINIC_PORT_CMD_RSS_CFG = 66,
	77
25a3ba61 AK	78	HINIC_PORT_CMD_FWCTXT_INIT = 69,
25a3ba61 AK	79
61a582be XC	80	HINIC_PORT_CMD_GET_MGMT_VERSION = 88,
61a582be XC	81
25a3ba61 AK	82	HINIC_PORT_CMD_SET_FUNC_STATE = 93,
	83
	84	HINIC_PORT_CMD_GET_GLOBAL_QPN = 102,
	85
cc18a754 ZC	86	HINIC_PORT_CMD_SET_TSO = 112,
cc18a754 ZC	87
1e007181 XC	88	HINIC_PORT_CMD_SET_RQ_IQ_MAP = 115,
1e007181 XC	89
25a3ba61	90	HINIC_PORT_CMD_GET_CAP = 170,
1e007181 XC	91
1e007181 XC	92	HINIC_PORT_CMD_SET_LRO_TIMER = 244,
25a3ba61 AK	93	};
25a3ba61 AK	94
421e9526 XC	95	enum hinic_ucode_cmd {
	96	HINIC_UCODE_CMD_MODIFY_QUEUE_CONTEXT = 0,
	97	HINIC_UCODE_CMD_CLEAN_QUEUE_CONTEXT,
	98	HINIC_UCODE_CMD_ARM_SQ,
	99	HINIC_UCODE_CMD_ARM_RQ,
	100	HINIC_UCODE_CMD_SET_RSS_INDIR_TABLE,
	101	HINIC_UCODE_CMD_SET_RSS_CONTEXT_TABLE,
	102	HINIC_UCODE_CMD_GET_RSS_INDIR_TABLE,
	103	HINIC_UCODE_CMD_GET_RSS_CONTEXT_TABLE,
	104	HINIC_UCODE_CMD_SET_IQ_ENABLE,
	105	HINIC_UCODE_CMD_SET_RQ_FLUSH = 10
	106	};
	107
	108	#define NIC_RSS_CMD_TEMP_ALLOC 0x01
	109	#define NIC_RSS_CMD_TEMP_FREE 0x02
	110
c4d06d2d AK	111	enum hinic_mgmt_msg_cmd {
	112	HINIC_MGMT_MSG_CMD_BASE = 160,
	113
	114	HINIC_MGMT_MSG_CMD_LINK_STATUS = 160,
	115
	116	HINIC_MGMT_MSG_CMD_MAX,
	117	};
	118
	119	enum hinic_cb_state {
	120	HINIC_CB_ENABLED = BIT(0),
	121	HINIC_CB_RUNNING = BIT(1),
	122	};
	123
e2585ea7 AK	124	enum hinic_res_state {
	125	HINIC_RES_CLEAN = 0,
	126	HINIC_RES_ACTIVE = 1,
	127	};
	128
	129	struct hinic_cmd_fw_ctxt {
	130	u8 status;
	131	u8 version;
	132	u8 rsvd0[6];
	133
	134	u16 func_idx;
	135	u16 rx_buf_sz;
	136
	137	u32 rsvd1;
	138	};
	139
	140	struct hinic_cmd_hw_ioctxt {
	141	u8 status;
	142	u8 version;
	143	u8 rsvd0[6];
	144
	145	u16 func_idx;
	146
	147	u16 rsvd1;
	148
	149	u8 set_cmdq_depth;
	150	u8 cmdq_depth;
	151
1e007181	152	u8 lro_en;
e2585ea7	153	u8 rsvd3;
d2ed69ce	154	u8 ppf_idx;
e2585ea7	155	u8 rsvd4;
e2585ea7 AK	156
	157	u16 rq_depth;
	158	u16 rx_buf_sz_idx;
	159	u16 sq_depth;
	160	};
	161
	162	struct hinic_cmd_io_status {
	163	u8 status;
	164	u8 version;
	165	u8 rsvd0[6];
	166
	167	u16 func_idx;
	168	u8 rsvd1;
	169	u8 rsvd2;
	170	u32 io_status;
	171	};
	172
	173	struct hinic_cmd_clear_io_res {
	174	u8 status;
	175	u8 version;
	176	u8 rsvd0[6];
	177
	178	u16 func_idx;
	179	u8 rsvd1;
	180	u8 rsvd2;
	181	};
	182
	183	struct hinic_cmd_set_res_state {
	184	u8 status;
	185	u8 version;
	186	u8 rsvd0[6];
	187
	188	u16 func_idx;
	189	u8 state;
	190	u8 rsvd1;
	191	u32 rsvd2;
	192	};
	193
c3e79baf AK	194	struct hinic_cmd_base_qpn {
	195	u8 status;
	196	u8 version;
	197	u8 rsvd0[6];
	198
	199	u16 func_idx;
	200	u16 qpn;
	201	};
	202
00e57a6d AK	203	struct hinic_cmd_hw_ci {
	204	u8 status;
	205	u8 version;
	206	u8 rsvd0[6];
	207
	208	u16 func_idx;
	209
	210	u8 dma_attr_off;
	211	u8 pending_limit;
	212	u8 coalesc_timer;
	213
	214	u8 msix_en;
	215	u16 msix_entry_idx;
	216
	217	u32 sq_id;
	218	u32 rsvd1;
	219	u64 ci_addr;
	220	};
	221
51ba902a AK	222	struct hinic_hwdev {
	223	struct hinic_hwif *hwif;
	224	struct msix_entry *msix_entries;
a5564e7e AK	225
a5564e7e AK	226	struct hinic_aeqs aeqs;
c3e79baf	227	struct hinic_func_to_io func_to_io;
a5564e7e AK	228
a5564e7e AK	229	struct hinic_cap nic_cap;
51ba902a AK	230	};
51ba902a AK	231
c4d06d2d AK	232	struct hinic_nic_cb {
	233	void (handler)(void handle, void *buf_in,
	234	u16 in_size, void *buf_out,
	235	u16 *out_size);
	236
	237	void *handle;
	238	unsigned long cb_state;
	239	};
	240
51ba902a AK	241	struct hinic_pfhwdev {
	242	struct hinic_hwdev hwdev;
	243
a5564e7e	244	struct hinic_pf_to_mgmt pf_to_mgmt;
c4d06d2d AK	245
c4d06d2d AK	246	struct hinic_nic_cb nic_cb[HINIC_MGMT_NUM_MSG_CMD];
51ba902a AK	247	};
51ba902a AK	248
c4d06d2d AK	249	void hinic_hwdev_cb_register(struct hinic_hwdev *hwdev,
	250	enum hinic_mgmt_msg_cmd cmd, void *handle,
	251	void (handler)(void handle, void *buf_in,
	252	u16 in_size, void *buf_out,
	253	u16 *out_size));
	254
	255	void hinic_hwdev_cb_unregister(struct hinic_hwdev *hwdev,
	256	enum hinic_mgmt_msg_cmd cmd);
	257
25a3ba61 AK	258	int hinic_port_msg_cmd(struct hinic_hwdev *hwdev, enum hinic_port_cmd cmd,
	259	void buf_in, u16 in_size, void buf_out,
	260	u16 *out_size);
	261
c3e79baf AK	262	int hinic_hwdev_ifup(struct hinic_hwdev *hwdev);
	263
	264	void hinic_hwdev_ifdown(struct hinic_hwdev *hwdev);
	265
51ba902a AK	266	struct hinic_hwdev hinic_init_hwdev(struct pci_dev pdev);
	267
	268	void hinic_free_hwdev(struct hinic_hwdev *hwdev);
	269
421e9526 XC	270	int hinic_hwdev_max_num_qps(struct hinic_hwdev *hwdev);
421e9526 XC	271
51ba902a AK	272	int hinic_hwdev_num_qps(struct hinic_hwdev *hwdev);
51ba902a AK	273
c3e79baf AK	274	struct hinic_sq hinic_hwdev_get_sq(struct hinic_hwdev hwdev, int i);
	275
	276	struct hinic_rq hinic_hwdev_get_rq(struct hinic_hwdev hwdev, int i);
	277
e2585ea7 AK	278	int hinic_hwdev_msix_cnt_set(struct hinic_hwdev *hwdev, u16 msix_index);
	279
	280	int hinic_hwdev_msix_set(struct hinic_hwdev *hwdev, u16 msix_index,
	281	u8 pending_limit, u8 coalesc_timer,
	282	u8 lli_timer_cfg, u8 lli_credit_limit,
	283	u8 resend_timer);
	284
00e57a6d AK	285	int hinic_hwdev_hw_ci_addr_set(struct hinic_hwdev hwdev, struct hinic_sq sq,
	286	u8 pending_limit, u8 coalesc_timer);
	287
905b464a XC	288	void hinic_hwdev_set_msix_state(struct hinic_hwdev *hwdev, u16 msix_index,
	289	enum hinic_msix_state flag);
	290
51ba902a	291	#endif