[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns_mdio.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 */

#include <linux/acpi.h>
#include <linux/errno.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/netdevice.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>

#define MDIO_DRV_NAME "Hi-HNS_MDIO"
#define MDIO_BUS_NAME "Hisilicon MII Bus"

#define MDIO_TIMEOUT			1000000

struct hns_mdio_sc_reg {
	u16 mdio_clk_en;
	u16 mdio_clk_dis;
	u16 mdio_reset_req;
	u16 mdio_reset_dreq;
	u16 mdio_clk_st;
	u16 mdio_reset_st;
};

struct hns_mdio_device {
	u8 __iomem *vbase;		/* mdio reg base address */
	struct regmap *subctrl_vbase;
	struct hns_mdio_sc_reg sc_reg;
};

/* mdio reg */
#define MDIO_COMMAND_REG		0x0
#define MDIO_ADDR_REG			0x4
#define MDIO_WDATA_REG			0x8
#define MDIO_RDATA_REG			0xc
#define MDIO_STA_REG			0x10

/* cfg phy bit map */
#define MDIO_CMD_DEVAD_M	0x1f
#define MDIO_CMD_DEVAD_S	0
#define MDIO_CMD_PRTAD_M	0x1f
#define MDIO_CMD_PRTAD_S	5
#define MDIO_CMD_OP_S		10
#define MDIO_CMD_ST_S		12
#define MDIO_CMD_START_B	14

#define MDIO_ADDR_DATA_M	0xffff
#define MDIO_ADDR_DATA_S	0

#define MDIO_WDATA_DATA_M	0xffff
#define MDIO_WDATA_DATA_S	0

#define MDIO_RDATA_DATA_M	0xffff
#define MDIO_RDATA_DATA_S	0

#define MDIO_STATE_STA_B	0

enum mdio_st_clause {
	MDIO_ST_CLAUSE_45 = 0,
	MDIO_ST_CLAUSE_22
};

enum mdio_c22_op_seq {
	MDIO_C22_WRITE = 1,
	MDIO_C22_READ = 2
};

enum mdio_c45_op_seq {
	MDIO_C45_WRITE_ADDR = 0,
	MDIO_C45_WRITE_DATA,
	MDIO_C45_READ_INCREMENT,
	MDIO_C45_READ
};

/* peri subctrl reg */
#define MDIO_SC_CLK_EN		0x338
#define MDIO_SC_CLK_DIS		0x33C
#define MDIO_SC_RESET_REQ	0xA38
#define MDIO_SC_RESET_DREQ	0xA3C
#define MDIO_SC_CLK_ST		0x531C
#define MDIO_SC_RESET_ST	0x5A1C

static void mdio_write_reg(u8 __iomem *base, u32 reg, u32 value)
{
	writel_relaxed(value, base + reg);
}

#define MDIO_WRITE_REG(a, reg, value) \
	mdio_write_reg((a)->vbase, (reg), (value))

static u32 mdio_read_reg(u8 __iomem *base, u32 reg)
{
	return readl_relaxed(base + reg);
}

#define mdio_set_field(origin, mask, shift, val) \
	do { \
		(origin) &= (~((mask) << (shift))); \
		(origin) |= (((val) & (mask)) << (shift)); \
	} while (0)

#define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))

static void mdio_set_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift,
			       u32 val)
{
	u32 origin = mdio_read_reg(base, reg);

	mdio_set_field(origin, mask, shift, val);
	mdio_write_reg(base, reg, origin);
}

#define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
	mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))

static u32 mdio_get_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift)
{
	u32 origin;

	origin = mdio_read_reg(base, reg);
	return mdio_get_field(origin, mask, shift);
}

#define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
		mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))

#define MDIO_GET_REG_BIT(dev, reg, bit) \
		mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))

#define MDIO_CHECK_SET_ST	1
#define MDIO_CHECK_CLR_ST	0

static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev,
				 u32 cfg_reg, u32 set_val,
				 u32 st_reg, u32 st_msk, u8 check_st)
{
	u32 time_cnt;
	u32 reg_value;
	int ret;

	regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);

	for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) {
		ret = regmap_read(mdio_dev->subctrl_vbase, st_reg, &reg_value);
		if (ret)
			return ret;

		reg_value &= st_msk;
		if ((!!check_st) == (!!reg_value))
			break;
	}

	if ((!!check_st) != (!!reg_value))
		return -EBUSY;

	return 0;
}

static int hns_mdio_wait_ready(struct mii_bus *bus)
{
	struct hns_mdio_device *mdio_dev = bus->priv;
	u32 cmd_reg_value;
	int i;

	/* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
	/* after that can do read or write*/
	for (i = 0; i < MDIO_TIMEOUT; i++) {
		cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev,
						 MDIO_COMMAND_REG,
						 MDIO_CMD_START_B);
		if (!cmd_reg_value)
			break;
	}
	if ((i == MDIO_TIMEOUT) && cmd_reg_value)
		return -ETIMEDOUT;

	return 0;
}

static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev,
			       u8 is_c45, u8 op, u8 phy_id, u16 cmd)
{
	u32 cmd_reg_value;
	u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22;

	cmd_reg_value = st << MDIO_CMD_ST_S;
	cmd_reg_value |= op << MDIO_CMD_OP_S;
	cmd_reg_value |=
		(phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S;
	cmd_reg_value |= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S;
	cmd_reg_value |= 1 << MDIO_CMD_START_B;

	MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value);
}

/**
 * hns_mdio_write - access phy register
 * @bus: mdio bus
 * @phy_id: phy id
 * @regnum: register num
 * @value: register value
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_write(struct mii_bus *bus,
			  int phy_id, int regnum, u16 data)
{
	int ret;
	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
	u8 devad = ((regnum >> 16) & 0x1f);
	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	u16 reg = (u16)(regnum & 0xffff);
	u8 op;
	u16 cmd_reg_cfg;

	dev_dbg(&bus->dev, "mdio write %s,base is %p\n",
		bus->id, mdio_dev->vbase);
	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
		phy_id, is_c45, devad, reg, data);

	/* wait for ready */
	ret = hns_mdio_wait_ready(bus);
	if (ret) {
		dev_err(&bus->dev, "MDIO bus is busy\n");
		return ret;
	}

	if (!is_c45) {
		cmd_reg_cfg = reg;
		op = MDIO_C22_WRITE;
	} else {
		/* config the cmd-reg to write addr*/
		MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
				   MDIO_ADDR_DATA_S, reg);

		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C45_WRITE_ADDR, phy_id, devad);

		/* check for read or write opt is finished */
		ret = hns_mdio_wait_ready(bus);
		if (ret) {
			dev_err(&bus->dev, "MDIO bus is busy\n");
			return ret;
		}

		/* config the data needed writing */
		cmd_reg_cfg = devad;
		op = MDIO_C45_WRITE_DATA;
	}

	MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M,
			   MDIO_WDATA_DATA_S, data);

	hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg);

	return 0;
}

/**
 * hns_mdio_read - access phy register
 * @bus: mdio bus
 * @phy_id: phy id
 * @regnum: register num
 * @value: register value
 *
 * Return phy register value
 */
static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
{
	int ret;
	u16 reg_val = 0;
	u8 devad = ((regnum >> 16) & 0x1f);
	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	u16 reg = (u16)(regnum & 0xffff);
	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;

	dev_dbg(&bus->dev, "mdio read %s,base is %p\n",
		bus->id, mdio_dev->vbase);
	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
		phy_id, is_c45, devad, reg);

	/* Step 1: wait for ready */
	ret = hns_mdio_wait_ready(bus);
	if (ret) {
		dev_err(&bus->dev, "MDIO bus is busy\n");
		return ret;
	}

	if (!is_c45) {
		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C22_READ, phy_id, reg);
	} else {
		MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
				   MDIO_ADDR_DATA_S, reg);

		/* Step 2; config the cmd-reg to write addr*/
		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C45_WRITE_ADDR, phy_id, devad);

		/* Step 3: check for read or write opt is finished */
		ret = hns_mdio_wait_ready(bus);
		if (ret) {
			dev_err(&bus->dev, "MDIO bus is busy\n");
			return ret;
		}

		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C45_READ, phy_id, devad);
	}

	/* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
	/* check for read or write opt is finished */
	ret = hns_mdio_wait_ready(bus);
	if (ret) {
		dev_err(&bus->dev, "MDIO bus is busy\n");
		return ret;
	}

	reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);
	if (reg_val) {
		dev_err(&bus->dev, " ERROR! MDIO Read failed!\n");
		return -EBUSY;
	}

	/* Step 6; get out data*/
	reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,
					  MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S);

	return reg_val;
}

/**
 * hns_mdio_reset - reset mdio bus
 * @bus: mdio bus
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_reset(struct mii_bus *bus)
{
	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
	const struct hns_mdio_sc_reg *sc_reg;
	int ret;

	if (dev_of_node(bus->parent)) {
		if (!mdio_dev->subctrl_vbase) {
			dev_err(&bus->dev, "mdio sys ctl reg has not maped\n");
			return -ENODEV;
		}

		sc_reg = &mdio_dev->sc_reg;
		/* 1. reset req, and read reset st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_req,
					    0x1, sc_reg->mdio_reset_st, 0x1,
					    MDIO_CHECK_SET_ST);
		if (ret) {
			dev_err(&bus->dev, "MDIO reset fail\n");
			return ret;
		}

		/* 2. dis clk, and read clk st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_dis,
					    0x1, sc_reg->mdio_clk_st, 0x1,
					    MDIO_CHECK_CLR_ST);
		if (ret) {
			dev_err(&bus->dev, "MDIO dis clk fail\n");
			return ret;
		}

		/* 3. reset dreq, and read reset st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_dreq,
					    0x1, sc_reg->mdio_reset_st, 0x1,
					    MDIO_CHECK_CLR_ST);
		if (ret) {
			dev_err(&bus->dev, "MDIO dis clk fail\n");
			return ret;
		}

		/* 4. en clk, and read clk st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_en,
					    0x1, sc_reg->mdio_clk_st, 0x1,
					    MDIO_CHECK_SET_ST);
		if (ret)
			dev_err(&bus->dev, "MDIO en clk fail\n");
	} else if (is_acpi_node(bus->parent->fwnode)) {
		acpi_status s;

		s = acpi_evaluate_object(ACPI_HANDLE(bus->parent),
					 "_RST", NULL, NULL);
		if (ACPI_FAILURE(s)) {
			dev_err(&bus->dev, "Reset failed, return:%#x\n", s);
			ret = -EBUSY;
		} else {
			ret = 0;
		}
	} else {
		dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n");
		ret = -ENXIO;
	}
	return ret;
}

/**
 * hns_mdio_probe - probe mdio device
 * @pdev: mdio platform device
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_probe(struct platform_device *pdev)
{
	struct hns_mdio_device *mdio_dev;
	struct mii_bus *new_bus;
	int ret = -ENODEV;

	if (!pdev) {
		dev_err(NULL, "pdev is NULL!\r\n");
		return -ENODEV;
	}

	mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL);
	if (!mdio_dev)
		return -ENOMEM;

	new_bus = devm_mdiobus_alloc(&pdev->dev);
	if (!new_bus) {
		dev_err(&pdev->dev, "mdiobus_alloc fail!\n");
		return -ENOMEM;
	}

	new_bus->name = MDIO_BUS_NAME;
	new_bus->read = hns_mdio_read;
	new_bus->write = hns_mdio_write;
	new_bus->reset = hns_mdio_reset;
	new_bus->priv = mdio_dev;
	new_bus->parent = &pdev->dev;

	mdio_dev->vbase = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(mdio_dev->vbase)) {
		ret = PTR_ERR(mdio_dev->vbase);
		return ret;
	}

	platform_set_drvdata(pdev, new_bus);
	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii",
		 dev_name(&pdev->dev));
	if (dev_of_node(&pdev->dev)) {
		struct of_phandle_args reg_args;

		ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
						       "subctrl-vbase",
						       4,
						       0,
						       &reg_args);
		if (!ret) {
			mdio_dev->subctrl_vbase =
				syscon_node_to_regmap(reg_args.np);
			if (IS_ERR(mdio_dev->subctrl_vbase)) {
				dev_warn(&pdev->dev, "syscon_node_to_regmap error\n");
				mdio_dev->subctrl_vbase = NULL;
			} else {
				if (reg_args.args_count == 4) {
					mdio_dev->sc_reg.mdio_clk_en =
						(u16)reg_args.args[0];
					mdio_dev->sc_reg.mdio_clk_dis =
						(u16)reg_args.args[0] + 4;
					mdio_dev->sc_reg.mdio_reset_req =
						(u16)reg_args.args[1];
					mdio_dev->sc_reg.mdio_reset_dreq =
						(u16)reg_args.args[1] + 4;
					mdio_dev->sc_reg.mdio_clk_st =
						(u16)reg_args.args[2];
					mdio_dev->sc_reg.mdio_reset_st =
						(u16)reg_args.args[3];
				} else {
					/* for compatible */
					mdio_dev->sc_reg.mdio_clk_en =
						MDIO_SC_CLK_EN;
					mdio_dev->sc_reg.mdio_clk_dis =
						MDIO_SC_CLK_DIS;
					mdio_dev->sc_reg.mdio_reset_req =
						MDIO_SC_RESET_REQ;
					mdio_dev->sc_reg.mdio_reset_dreq =
						MDIO_SC_RESET_DREQ;
					mdio_dev->sc_reg.mdio_clk_st =
						MDIO_SC_CLK_ST;
					mdio_dev->sc_reg.mdio_reset_st =
						MDIO_SC_RESET_ST;
				}
			}
		} else {
			dev_warn(&pdev->dev, "find syscon ret = %#x\n", ret);
			mdio_dev->subctrl_vbase = NULL;
		}

		ret = of_mdiobus_register(new_bus, pdev->dev.of_node);
	} else if (is_acpi_node(pdev->dev.fwnode)) {
		/* Clear all the IRQ properties */
		memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR);

		/* Mask out all PHYs from auto probing. */
		new_bus->phy_mask = ~0;

		/* Register the MDIO bus */
		ret = mdiobus_register(new_bus);
	} else {
		dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n");
		ret = -ENXIO;
	}

	if (ret) {
		dev_err(&pdev->dev, "Cannot register as MDIO bus!\n");
		platform_set_drvdata(pdev, NULL);
		return ret;
	}

	return 0;
}

/**
 * hns_mdio_remove - remove mdio device
 * @pdev: mdio platform device
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_remove(struct platform_device *pdev)
{
	struct mii_bus *bus;

	bus = platform_get_drvdata(pdev);

	mdiobus_unregister(bus);
	platform_set_drvdata(pdev, NULL);
	return 0;
}

static const struct of_device_id hns_mdio_match[] = {
	{.compatible = "hisilicon,mdio"},
	{.compatible = "hisilicon,hns-mdio"},
	{}
};
MODULE_DEVICE_TABLE(of, hns_mdio_match);

static const struct acpi_device_id hns_mdio_acpi_match[] = {
	{ "HISI0141", 0 },
	{ },
};
MODULE_DEVICE_TABLE(acpi, hns_mdio_acpi_match);

static struct platform_driver hns_mdio_driver = {
	.probe = hns_mdio_probe,
	.remove = hns_mdio_remove,
	.driver = {
		   .name = MDIO_DRV_NAME,
		   .of_match_table = hns_mdio_match,
		   .acpi_match_table = ACPI_PTR(hns_mdio_acpi_match),
		   },
};

module_platform_driver(hns_mdio_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
MODULE_ALIAS("platform:" MDIO_DRV_NAME);
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
5b904d39	2	/*
5b904d39	3	* Copyright (c) 2014-2015 Hisilicon Limited.
5b904d39	4	*/
5b904d39	5
8a99ff5a	6	#include <linux/acpi.h>
5b904d39	7	#include <linux/errno.h>
	8	#include <linux/etherdevice.h>
	9	#include <linux/init.h>
	10	#include <linux/kernel.h>
c7fc9eb7	11	#include <linux/mfd/syscon.h>
5b904d39	12	#include <linux/module.h>
	13	#include <linux/mutex.h>
	14	#include <linux/netdevice.h>
	15	#include <linux/of_address.h>
	16	#include <linux/of.h>
	17	#include <linux/of_mdio.h>
	18	#include <linux/of_platform.h>
	19	#include <linux/phy.h>
	20	#include <linux/platform_device.h>
c7fc9eb7	21	#include <linux/regmap.h>
5b904d39	22
	23	#define MDIO_DRV_NAME "Hi-HNS_MDIO"
	24	#define MDIO_BUS_NAME "Hisilicon MII Bus"
5b904d39	25
	26	#define MDIO_TIMEOUT 1000000
	27
b15dc292 KY	28	struct hns_mdio_sc_reg {
	29	u16 mdio_clk_en;
	30	u16 mdio_clk_dis;
	31	u16 mdio_reset_req;
	32	u16 mdio_reset_dreq;
	33	u16 mdio_clk_st;
	34	u16 mdio_reset_st;
	35	};
	36
5b904d39	37	struct hns_mdio_device {
15400663	38	u8 __iomem vbase; / mdio reg base address */
c7fc9eb7	39	struct regmap *subctrl_vbase;
b15dc292	40	struct hns_mdio_sc_reg sc_reg;
5b904d39	41	};
	42
	43	/* mdio reg */
	44	#define MDIO_COMMAND_REG 0x0
	45	#define MDIO_ADDR_REG 0x4
	46	#define MDIO_WDATA_REG 0x8
	47	#define MDIO_RDATA_REG 0xc
	48	#define MDIO_STA_REG 0x10
	49
	50	/* cfg phy bit map */
	51	#define MDIO_CMD_DEVAD_M 0x1f
	52	#define MDIO_CMD_DEVAD_S 0
	53	#define MDIO_CMD_PRTAD_M 0x1f
	54	#define MDIO_CMD_PRTAD_S 5
5b904d39	55	#define MDIO_CMD_OP_S 10
5b904d39	56	#define MDIO_CMD_ST_S 12
	57	#define MDIO_CMD_START_B 14
	58
	59	#define MDIO_ADDR_DATA_M 0xffff
	60	#define MDIO_ADDR_DATA_S 0
	61
	62	#define MDIO_WDATA_DATA_M 0xffff
	63	#define MDIO_WDATA_DATA_S 0
	64
	65	#define MDIO_RDATA_DATA_M 0xffff
	66	#define MDIO_RDATA_DATA_S 0
	67
	68	#define MDIO_STATE_STA_B 0
	69
	70	enum mdio_st_clause {
	71	MDIO_ST_CLAUSE_45 = 0,
	72	MDIO_ST_CLAUSE_22
	73	};
	74
	75	enum mdio_c22_op_seq {
	76	MDIO_C22_WRITE = 1,
	77	MDIO_C22_READ = 2
	78	};
	79
	80	enum mdio_c45_op_seq {
	81	MDIO_C45_WRITE_ADDR = 0,
	82	MDIO_C45_WRITE_DATA,
	83	MDIO_C45_READ_INCREMENT,
	84	MDIO_C45_READ
	85	};
	86
	87	/* peri subctrl reg */
	88	#define MDIO_SC_CLK_EN 0x338
	89	#define MDIO_SC_CLK_DIS 0x33C
	90	#define MDIO_SC_RESET_REQ 0xA38
	91	#define MDIO_SC_RESET_DREQ 0xA3C
5b904d39	92	#define MDIO_SC_CLK_ST 0x531C
	93	#define MDIO_SC_RESET_ST 0x5A1C
	94
15400663	95	static void mdio_write_reg(u8 __iomem *base, u32 reg, u32 value)
5b904d39	96	{
15400663	97	writel_relaxed(value, base + reg);
5b904d39	98	}
	99
	100	#define MDIO_WRITE_REG(a, reg, value) \
	101	mdio_write_reg((a)->vbase, (reg), (value))
	102
15400663	103	static u32 mdio_read_reg(u8 __iomem *base, u32 reg)
5b904d39	104	{
15400663	105	return readl_relaxed(base + reg);
5b904d39	106	}
	107
	108	#define mdio_set_field(origin, mask, shift, val) \
	109	do { \
	110	(origin) &= (~((mask) << (shift))); \
	111	(origin) \|= (((val) & (mask)) << (shift)); \
	112	} while (0)
	113
	114	#define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))
	115
15400663	116	static void mdio_set_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift,
5b904d39	117	u32 val)
	118	{
	119	u32 origin = mdio_read_reg(base, reg);
	120
	121	mdio_set_field(origin, mask, shift, val);
	122	mdio_write_reg(base, reg, origin);
	123	}
	124
	125	#define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
	126	mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))
	127
15400663	128	static u32 mdio_get_reg_field(u8 __iomem *base, u32 reg, u32 mask, u32 shift)
5b904d39	129	{
	130	u32 origin;
	131
	132	origin = mdio_read_reg(base, reg);
	133	return mdio_get_field(origin, mask, shift);
	134	}
	135
	136	#define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
	137	mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))
	138
	139	#define MDIO_GET_REG_BIT(dev, reg, bit) \
	140	mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))
	141
	142	#define MDIO_CHECK_SET_ST 1
	143	#define MDIO_CHECK_CLR_ST 0
	144
	145	static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev,
	146	u32 cfg_reg, u32 set_val,
	147	u32 st_reg, u32 st_msk, u8 check_st)
	148	{
	149	u32 time_cnt;
	150	u32 reg_value;
53de429f	151	int ret;
5b904d39	152
c7fc9eb7	153	regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);
5b904d39	154
5b904d39	155	for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) {
53de429f Y	156	ret = regmap_read(mdio_dev->subctrl_vbase, st_reg, &reg_value);
	157	if (ret)
	158	return ret;
	159
5b904d39	160	reg_value &= st_msk;
	161	if ((!!check_st) == (!!reg_value))
	162	break;
	163	}
	164
	165	if ((!!check_st) != (!!reg_value))
	166	return -EBUSY;
	167
	168	return 0;
	169	}
	170
	171	static int hns_mdio_wait_ready(struct mii_bus *bus)
	172	{
	173	struct hns_mdio_device *mdio_dev = bus->priv;
d592a4a4	174	u32 cmd_reg_value;
5b904d39	175	int i;
5b904d39	176
	177	/* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
	178	/* after that can do read or write*/
d592a4a4	179	for (i = 0; i < MDIO_TIMEOUT; i++) {
5b904d39	180	cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev,
	181	MDIO_COMMAND_REG,
	182	MDIO_CMD_START_B);
d592a4a4 KY	183	if (!cmd_reg_value)
d592a4a4 KY	184	break;
5b904d39	185	}
d592a4a4 KY	186	if ((i == MDIO_TIMEOUT) && cmd_reg_value)
d592a4a4 KY	187	return -ETIMEDOUT;
5b904d39	188
	189	return 0;
	190	}
	191
	192	static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev,
	193	u8 is_c45, u8 op, u8 phy_id, u16 cmd)
	194	{
	195	u32 cmd_reg_value;
	196	u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22;
	197
	198	cmd_reg_value = st << MDIO_CMD_ST_S;
	199	cmd_reg_value \|= op << MDIO_CMD_OP_S;
	200	cmd_reg_value \|=
	201	(phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S;
	202	cmd_reg_value \|= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S;
	203	cmd_reg_value \|= 1 << MDIO_CMD_START_B;
	204
	205	MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value);
	206	}
	207
	208	/**
	209	* hns_mdio_write - access phy register
	210	* @bus: mdio bus
	211	* @phy_id: phy id
	212	* @regnum: register num
	213	* @value: register value
	214	*
	215	* Return 0 on success, negative on failure
	216	*/
	217	static int hns_mdio_write(struct mii_bus *bus,
	218	int phy_id, int regnum, u16 data)
	219	{
	220	int ret;
	221	struct hns_mdio_device mdio_dev = (struct hns_mdio_device )bus->priv;
	222	u8 devad = ((regnum >> 16) & 0x1f);
	223	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	224	u16 reg = (u16)(regnum & 0xffff);
	225	u8 op;
	226	u16 cmd_reg_cfg;
	227
	228	dev_dbg(&bus->dev, "mdio write %s,base is %p\n",
	229	bus->id, mdio_dev->vbase);
	230	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
	231	phy_id, is_c45, devad, reg, data);
	232
	233	/* wait for ready */
	234	ret = hns_mdio_wait_ready(bus);
	235	if (ret) {
	236	dev_err(&bus->dev, "MDIO bus is busy\n");
	237	return ret;
	238	}
	239
	240	if (!is_c45) {
	241	cmd_reg_cfg = reg;
	242	op = MDIO_C22_WRITE;
	243	} else {
	244	/* config the cmd-reg to write addr*/
	245	MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
	246	MDIO_ADDR_DATA_S, reg);
	247
	248	hns_mdio_cmd_write(mdio_dev, is_c45,
	249	MDIO_C45_WRITE_ADDR, phy_id, devad);
	250
	251	/* check for read or write opt is finished */
252	ret = hns_mdio_wait_ready(bus);
253	if (ret) {
254	dev_err(&bus->dev, "MDIO bus is busy\n");
255	return ret;
256	}
257
258	/* config the data needed writing */
259	cmd_reg_cfg = devad;
ebe8d359	260	op = MDIO_C45_WRITE_DATA;
5b904d39	261	}
	262
	263	MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M,
	264	MDIO_WDATA_DATA_S, data);
	265
	266	hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg);
	267
	268	return 0;
	269	}
	270
	271	/**
	272	* hns_mdio_read - access phy register
	273	* @bus: mdio bus
	274	* @phy_id: phy id
	275	* @regnum: register num
	276	* @value: register value
	277	*
	278	* Return phy register value
	279	*/
	280	static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
	281	{
	282	int ret;
	283	u16 reg_val = 0;
	284	u8 devad = ((regnum >> 16) & 0x1f);
	285	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	286	u16 reg = (u16)(regnum & 0xffff);
	287	struct hns_mdio_device mdio_dev = (struct hns_mdio_device )bus->priv;
	288
	289	dev_dbg(&bus->dev, "mdio read %s,base is %p\n",
	290	bus->id, mdio_dev->vbase);
	291	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
	292	phy_id, is_c45, devad, reg);
	293
	294	/* Step 1: wait for ready */
	295	ret = hns_mdio_wait_ready(bus);
	296	if (ret) {
	297	dev_err(&bus->dev, "MDIO bus is busy\n");
	298	return ret;
	299	}
	300
	301	if (!is_c45) {
	302	hns_mdio_cmd_write(mdio_dev, is_c45,
	303	MDIO_C22_READ, phy_id, reg);
	304	} else {
	305	MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
	306	MDIO_ADDR_DATA_S, reg);
	307
	308	/* Step 2; config the cmd-reg to write addr*/
	309	hns_mdio_cmd_write(mdio_dev, is_c45,
	310	MDIO_C45_WRITE_ADDR, phy_id, devad);
	311
	312	/* Step 3: check for read or write opt is finished */
	313	ret = hns_mdio_wait_ready(bus);
	314	if (ret) {
	315	dev_err(&bus->dev, "MDIO bus is busy\n");
	316	return ret;
	317	}
	318
	319	hns_mdio_cmd_write(mdio_dev, is_c45,
cec8abba	320	MDIO_C45_READ, phy_id, devad);
5b904d39	321	}
	322
	323	/* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
	324	/* check for read or write opt is finished */
	325	ret = hns_mdio_wait_ready(bus);
	326	if (ret) {
	327	dev_err(&bus->dev, "MDIO bus is busy\n");
	328	return ret;
	329	}
	330
	331	reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);
	332	if (reg_val) {
	333	dev_err(&bus->dev, " ERROR! MDIO Read failed!\n");
	334	return -EBUSY;
	335	}
	336
	337	/* Step 6; get out data*/
	338	reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,
	339	MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S);
	340
	341	return reg_val;
	342	}
	343
	344	/**
	345	* hns_mdio_reset - reset mdio bus
	346	* @bus: mdio bus
	347	*
	348	* Return 0 on success, negative on failure
	349	*/
	350	static int hns_mdio_reset(struct mii_bus *bus)
	351	{
	352	struct hns_mdio_device mdio_dev = (struct hns_mdio_device )bus->priv;
b15dc292	353	const struct hns_mdio_sc_reg *sc_reg;
5b904d39	354	int ret;
5b904d39	355
8a99ff5a KY	356	if (dev_of_node(bus->parent)) {
	357	if (!mdio_dev->subctrl_vbase) {
	358	dev_err(&bus->dev, "mdio sys ctl reg has not maped\n");
	359	return -ENODEV;
	360	}
16a9f361	361
b15dc292	362	sc_reg = &mdio_dev->sc_reg;
8a99ff5a	363	/* 1. reset req, and read reset st check */
b15dc292 KY	364	ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_req,
b15dc292 KY	365	0x1, sc_reg->mdio_reset_st, 0x1,
8a99ff5a KY	366	MDIO_CHECK_SET_ST);
	367	if (ret) {
	368	dev_err(&bus->dev, "MDIO reset fail\n");
	369	return ret;
	370	}
5b904d39	371
8a99ff5a	372	/* 2. dis clk, and read clk st check */
b15dc292 KY	373	ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_dis,
b15dc292 KY	374	0x1, sc_reg->mdio_clk_st, 0x1,
8a99ff5a KY	375	MDIO_CHECK_CLR_ST);
	376	if (ret) {
	377	dev_err(&bus->dev, "MDIO dis clk fail\n");
	378	return ret;
	379	}
5b904d39	380
8a99ff5a	381	/* 3. reset dreq, and read reset st check */
b15dc292 KY	382	ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_reset_dreq,
b15dc292 KY	383	0x1, sc_reg->mdio_reset_st, 0x1,
8a99ff5a KY	384	MDIO_CHECK_CLR_ST);
	385	if (ret) {
	386	dev_err(&bus->dev, "MDIO dis clk fail\n");
	387	return ret;
	388	}
5b904d39	389
8a99ff5a	390	/* 4. en clk, and read clk st check */
b15dc292 KY	391	ret = mdio_sc_cfg_reg_write(mdio_dev, sc_reg->mdio_clk_en,
b15dc292 KY	392	0x1, sc_reg->mdio_clk_st, 0x1,
8a99ff5a KY	393	MDIO_CHECK_SET_ST);
	394	if (ret)
	395	dev_err(&bus->dev, "MDIO en clk fail\n");
	396	} else if (is_acpi_node(bus->parent->fwnode)) {
	397	acpi_status s;
	398
	399	s = acpi_evaluate_object(ACPI_HANDLE(bus->parent),
	400	"_RST", NULL, NULL);
	401	if (ACPI_FAILURE(s)) {
	402	dev_err(&bus->dev, "Reset failed, return:%#x\n", s);
	403	ret = -EBUSY;
	404	} else {
	405	ret = 0;
	406	}
	407	} else {
	408	dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n");
	409	ret = -ENXIO;
5b904d39	410	}
5b904d39	411	return ret;
	412	}
	413
5b904d39	414	/**
	415	* hns_mdio_probe - probe mdio device
	416	* @pdev: mdio platform device
	417	*
	418	* Return 0 on success, negative on failure
	419	*/
	420	static int hns_mdio_probe(struct platform_device *pdev)
	421	{
5b904d39	422	struct hns_mdio_device *mdio_dev;
5b904d39	423	struct mii_bus *new_bus;
16a9f361	424	int ret = -ENODEV;
5b904d39	425
	426	if (!pdev) {
	427	dev_err(NULL, "pdev is NULL!\r\n");
	428	return -ENODEV;
	429	}
16a9f361	430
5b904d39	431	mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL);
	432	if (!mdio_dev)
	433	return -ENOMEM;
	434
	435	new_bus = devm_mdiobus_alloc(&pdev->dev);
	436	if (!new_bus) {
	437	dev_err(&pdev->dev, "mdiobus_alloc fail!\n");
	438	return -ENOMEM;
	439	}
	440
	441	new_bus->name = MDIO_BUS_NAME;
	442	new_bus->read = hns_mdio_read;
	443	new_bus->write = hns_mdio_write;
	444	new_bus->reset = hns_mdio_reset;
	445	new_bus->priv = mdio_dev;
16a9f361	446	new_bus->parent = &pdev->dev;
5b904d39	447
56170ba3	448	mdio_dev->vbase = devm_platform_ioremap_resource(pdev, 0);
5b904d39	449	if (IS_ERR(mdio_dev->vbase)) {
	450	ret = PTR_ERR(mdio_dev->vbase);
	451	return ret;
	452	}
	453
5b904d39	454	platform_set_drvdata(pdev, new_bus);
16a9f361 KY	455	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii",
	456	dev_name(&pdev->dev));
	457	if (dev_of_node(&pdev->dev)) {
b15dc292 KY	458	struct of_phandle_args reg_args;
	459
	460	ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
	461	"subctrl-vbase",
	462	4,
	463	0,
	464	&reg_args);
	465	if (!ret) {
	466	mdio_dev->subctrl_vbase =
	467	syscon_node_to_regmap(reg_args.np);
	468	if (IS_ERR(mdio_dev->subctrl_vbase)) {
	469	dev_warn(&pdev->dev, "syscon_node_to_regmap error\n");
	470	mdio_dev->subctrl_vbase = NULL;
	471	} else {
	472	if (reg_args.args_count == 4) {
	473	mdio_dev->sc_reg.mdio_clk_en =
	474	(u16)reg_args.args[0];
	475	mdio_dev->sc_reg.mdio_clk_dis =
	476	(u16)reg_args.args[0] + 4;
	477	mdio_dev->sc_reg.mdio_reset_req =
	478	(u16)reg_args.args[1];
	479	mdio_dev->sc_reg.mdio_reset_dreq =
	480	(u16)reg_args.args[1] + 4;
	481	mdio_dev->sc_reg.mdio_clk_st =
	482	(u16)reg_args.args[2];
	483	mdio_dev->sc_reg.mdio_reset_st =
	484	(u16)reg_args.args[3];
	485	} else {
	486	/* for compatible */
	487	mdio_dev->sc_reg.mdio_clk_en =
	488	MDIO_SC_CLK_EN;
	489	mdio_dev->sc_reg.mdio_clk_dis =
	490	MDIO_SC_CLK_DIS;
	491	mdio_dev->sc_reg.mdio_reset_req =
	492	MDIO_SC_RESET_REQ;
	493	mdio_dev->sc_reg.mdio_reset_dreq =
	494	MDIO_SC_RESET_DREQ;
	495	mdio_dev->sc_reg.mdio_clk_st =
	496	MDIO_SC_CLK_ST;
	497	mdio_dev->sc_reg.mdio_reset_st =
	498	MDIO_SC_RESET_ST;
	499	}
	500	}
	501	} else {
	502	dev_warn(&pdev->dev, "find syscon ret = %#x\n", ret);
16a9f361 KY	503	mdio_dev->subctrl_vbase = NULL;
16a9f361 KY	504	}
b15dc292	505
16a9f361	506	ret = of_mdiobus_register(new_bus, pdev->dev.of_node);
8a99ff5a KY	507	} else if (is_acpi_node(pdev->dev.fwnode)) {
	508	/* Clear all the IRQ properties */
	509	memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR);
	510
	511	/* Mask out all PHYs from auto probing. */
	512	new_bus->phy_mask = ~0;
	513
	514	/* Register the MDIO bus */
	515	ret = mdiobus_register(new_bus);
	516	} else {
	517	dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n");
	518	ret = -ENXIO;
16a9f361	519	}
5b904d39	520
5b904d39	521	if (ret) {
	522	dev_err(&pdev->dev, "Cannot register as MDIO bus!\n");
	523	platform_set_drvdata(pdev, NULL);
	524	return ret;
	525	}
	526
	527	return 0;
	528	}
	529
	530	/**
	531	* hns_mdio_remove - remove mdio device
	532	* @pdev: mdio platform device
	533	*
	534	* Return 0 on success, negative on failure
	535	*/
	536	static int hns_mdio_remove(struct platform_device *pdev)
	537	{
	538	struct mii_bus *bus;
	539
	540	bus = platform_get_drvdata(pdev);
	541
	542	mdiobus_unregister(bus);
	543	platform_set_drvdata(pdev, NULL);
	544	return 0;
	545	}
	546
	547	static const struct of_device_id hns_mdio_match[] = {
	548	{.compatible = "hisilicon,mdio"},
	549	{.compatible = "hisilicon,hns-mdio"},
	550	{}
	551	};
af40097e	552	MODULE_DEVICE_TABLE(of, hns_mdio_match);
5b904d39	553
8a99ff5a KY	554	static const struct acpi_device_id hns_mdio_acpi_match[] = {
	555	{ "HISI0141", 0 },
	556	{ },
	557	};
	558	MODULE_DEVICE_TABLE(acpi, hns_mdio_acpi_match);
	559
5b904d39	560	static struct platform_driver hns_mdio_driver = {
	561	.probe = hns_mdio_probe,
	562	.remove = hns_mdio_remove,
	563	.driver = {
	564	.name = MDIO_DRV_NAME,
	565	.of_match_table = hns_mdio_match,
8a99ff5a	566	.acpi_match_table = ACPI_PTR(hns_mdio_acpi_match),
5b904d39	567	},
	568	};
	569
	570	module_platform_driver(hns_mdio_driver);
	571
	572	MODULE_LICENSE("GPL");
	573	MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
	574	MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
	575	MODULE_ALIAS("platform:" MDIO_DRV_NAME);