[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns_mdio.c

/*
 * Copyright (c) 2014-2015 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include <linux/acpi.h>
#include <linux/errno.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/netdevice.h>
#include <linux/of_address.h>
#include <linux/of.h>
#include <linux/of_mdio.h>
#include <linux/of_platform.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/spinlock_types.h>

#define MDIO_DRV_NAME "Hi-HNS_MDIO"
#define MDIO_BUS_NAME "Hisilicon MII Bus"
#define MDIO_DRV_VERSION "1.3.0"
#define MDIO_COPYRIGHT "Copyright(c) 2015 Huawei Corporation."
#define MDIO_DRV_STRING MDIO_BUS_NAME
#define MDIO_DEFAULT_DEVICE_DESCR MDIO_BUS_NAME

#define MDIO_CTL_DEV_ADDR(x)	(x & 0x1f)
#define MDIO_CTL_PORT_ADDR(x)	((x & 0x1f) << 5)

#define MDIO_TIMEOUT			1000000

struct hns_mdio_device {
	void *vbase;		/* mdio reg base address */
	struct regmap *subctrl_vbase;
};

/* mdio reg */
#define MDIO_COMMAND_REG		0x0
#define MDIO_ADDR_REG			0x4
#define MDIO_WDATA_REG			0x8
#define MDIO_RDATA_REG			0xc
#define MDIO_STA_REG			0x10

/* cfg phy bit map */
#define MDIO_CMD_DEVAD_M	0x1f
#define MDIO_CMD_DEVAD_S	0
#define MDIO_CMD_PRTAD_M	0x1f
#define MDIO_CMD_PRTAD_S	5
#define MDIO_CMD_OP_M		0x3
#define MDIO_CMD_OP_S		10
#define MDIO_CMD_ST_M		0x3
#define MDIO_CMD_ST_S		12
#define MDIO_CMD_START_B	14

#define MDIO_ADDR_DATA_M	0xffff
#define MDIO_ADDR_DATA_S	0

#define MDIO_WDATA_DATA_M	0xffff
#define MDIO_WDATA_DATA_S	0

#define MDIO_RDATA_DATA_M	0xffff
#define MDIO_RDATA_DATA_S	0

#define MDIO_STATE_STA_B	0

enum mdio_st_clause {
	MDIO_ST_CLAUSE_45 = 0,
	MDIO_ST_CLAUSE_22
};

enum mdio_c22_op_seq {
	MDIO_C22_WRITE = 1,
	MDIO_C22_READ = 2
};

enum mdio_c45_op_seq {
	MDIO_C45_WRITE_ADDR = 0,
	MDIO_C45_WRITE_DATA,
	MDIO_C45_READ_INCREMENT,
	MDIO_C45_READ
};

/* peri subctrl reg */
#define MDIO_SC_CLK_EN		0x338
#define MDIO_SC_CLK_DIS		0x33C
#define MDIO_SC_RESET_REQ	0xA38
#define MDIO_SC_RESET_DREQ	0xA3C
#define MDIO_SC_CTRL		0x2010
#define MDIO_SC_CLK_ST		0x531C
#define MDIO_SC_RESET_ST	0x5A1C

static void mdio_write_reg(void *base, u32 reg, u32 value)
{
	u8 __iomem *reg_addr = (u8 __iomem *)base;

	writel_relaxed(value, reg_addr + reg);
}

#define MDIO_WRITE_REG(a, reg, value) \
	mdio_write_reg((a)->vbase, (reg), (value))

static u32 mdio_read_reg(void *base, u32 reg)
{
	u8 __iomem *reg_addr = (u8 __iomem *)base;

	return readl_relaxed(reg_addr + reg);
}

#define mdio_set_field(origin, mask, shift, val) \
	do { \
		(origin) &= (~((mask) << (shift))); \
		(origin) |= (((val) & (mask)) << (shift)); \
	} while (0)

#define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))

static void mdio_set_reg_field(void *base, u32 reg, u32 mask, u32 shift,
			       u32 val)
{
	u32 origin = mdio_read_reg(base, reg);

	mdio_set_field(origin, mask, shift, val);
	mdio_write_reg(base, reg, origin);
}

#define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
	mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))

static u32 mdio_get_reg_field(void *base, u32 reg, u32 mask, u32 shift)
{
	u32 origin;

	origin = mdio_read_reg(base, reg);
	return mdio_get_field(origin, mask, shift);
}

#define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
		mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))

#define MDIO_GET_REG_BIT(dev, reg, bit) \
		mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))

#define MDIO_CHECK_SET_ST	1
#define MDIO_CHECK_CLR_ST	0

static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev,
				 u32 cfg_reg, u32 set_val,
				 u32 st_reg, u32 st_msk, u8 check_st)
{
	u32 time_cnt;
	u32 reg_value;

	regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);

	for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) {
		regmap_read(mdio_dev->subctrl_vbase, st_reg, &reg_value);
		reg_value &= st_msk;
		if ((!!check_st) == (!!reg_value))
			break;
	}

	if ((!!check_st) != (!!reg_value))
		return -EBUSY;

	return 0;
}

static int hns_mdio_wait_ready(struct mii_bus *bus)
{
	struct hns_mdio_device *mdio_dev = bus->priv;
	int i;
	u32 cmd_reg_value = 1;

	/* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
	/* after that can do read or write*/
	for (i = 0; cmd_reg_value; i++) {
		cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev,
						 MDIO_COMMAND_REG,
						 MDIO_CMD_START_B);
		if (i == MDIO_TIMEOUT)
			return -ETIMEDOUT;
	}

	return 0;
}

static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev,
			       u8 is_c45, u8 op, u8 phy_id, u16 cmd)
{
	u32 cmd_reg_value;
	u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22;

	cmd_reg_value = st << MDIO_CMD_ST_S;
	cmd_reg_value |= op << MDIO_CMD_OP_S;
	cmd_reg_value |=
		(phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S;
	cmd_reg_value |= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S;
	cmd_reg_value |= 1 << MDIO_CMD_START_B;

	MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value);
}

/**
 * hns_mdio_write - access phy register
 * @bus: mdio bus
 * @phy_id: phy id
 * @regnum: register num
 * @value: register value
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_write(struct mii_bus *bus,
			  int phy_id, int regnum, u16 data)
{
	int ret;
	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
	u8 devad = ((regnum >> 16) & 0x1f);
	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	u16 reg = (u16)(regnum & 0xffff);
	u8 op;
	u16 cmd_reg_cfg;

	dev_dbg(&bus->dev, "mdio write %s,base is %p\n",
		bus->id, mdio_dev->vbase);
	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
		phy_id, is_c45, devad, reg, data);

	/* wait for ready */
	ret = hns_mdio_wait_ready(bus);
	if (ret) {
		dev_err(&bus->dev, "MDIO bus is busy\n");
		return ret;
	}

	if (!is_c45) {
		cmd_reg_cfg = reg;
		op = MDIO_C22_WRITE;
	} else {
		/* config the cmd-reg to write addr*/
		MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
				   MDIO_ADDR_DATA_S, reg);

		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C45_WRITE_ADDR, phy_id, devad);

		/* check for read or write opt is finished */
		ret = hns_mdio_wait_ready(bus);
		if (ret) {
			dev_err(&bus->dev, "MDIO bus is busy\n");
			return ret;
		}

		/* config the data needed writing */
		cmd_reg_cfg = devad;
		op = MDIO_C45_WRITE_ADDR;
	}

	MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M,
			   MDIO_WDATA_DATA_S, data);

	hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg);

	return 0;
}

/**
 * hns_mdio_read - access phy register
 * @bus: mdio bus
 * @phy_id: phy id
 * @regnum: register num
 * @value: register value
 *
 * Return phy register value
 */
static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
{
	int ret;
	u16 reg_val = 0;
	u8 devad = ((regnum >> 16) & 0x1f);
	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	u16 reg = (u16)(regnum & 0xffff);
	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;

	dev_dbg(&bus->dev, "mdio read %s,base is %p\n",
		bus->id, mdio_dev->vbase);
	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
		phy_id, is_c45, devad, reg);

	/* Step 1: wait for ready */
	ret = hns_mdio_wait_ready(bus);
	if (ret) {
		dev_err(&bus->dev, "MDIO bus is busy\n");
		return ret;
	}

	if (!is_c45) {
		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C22_READ, phy_id, reg);
	} else {
		MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
				   MDIO_ADDR_DATA_S, reg);

		/* Step 2; config the cmd-reg to write addr*/
		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C45_WRITE_ADDR, phy_id, devad);

		/* Step 3: check for read or write opt is finished */
		ret = hns_mdio_wait_ready(bus);
		if (ret) {
			dev_err(&bus->dev, "MDIO bus is busy\n");
			return ret;
		}

		hns_mdio_cmd_write(mdio_dev, is_c45,
				   MDIO_C45_WRITE_ADDR, phy_id, devad);
	}

	/* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
	/* check for read or write opt is finished */
	ret = hns_mdio_wait_ready(bus);
	if (ret) {
		dev_err(&bus->dev, "MDIO bus is busy\n");
		return ret;
	}

	reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);
	if (reg_val) {
		dev_err(&bus->dev, " ERROR! MDIO Read failed!\n");
		return -EBUSY;
	}

	/* Step 6; get out data*/
	reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,
					  MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S);

	return reg_val;
}

/**
 * hns_mdio_reset - reset mdio bus
 * @bus: mdio bus
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_reset(struct mii_bus *bus)
{
	struct hns_mdio_device *mdio_dev = (struct hns_mdio_device *)bus->priv;
	int ret;

	if (dev_of_node(bus->parent)) {
		if (!mdio_dev->subctrl_vbase) {
			dev_err(&bus->dev, "mdio sys ctl reg has not maped\n");
			return -ENODEV;
		}

		/* 1. reset req, and read reset st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, MDIO_SC_RESET_REQ, 0x1,
					    MDIO_SC_RESET_ST, 0x1,
					    MDIO_CHECK_SET_ST);
		if (ret) {
			dev_err(&bus->dev, "MDIO reset fail\n");
			return ret;
		}

		/* 2. dis clk, and read clk st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, MDIO_SC_CLK_DIS,
					    0x1, MDIO_SC_CLK_ST, 0x1,
					    MDIO_CHECK_CLR_ST);
		if (ret) {
			dev_err(&bus->dev, "MDIO dis clk fail\n");
			return ret;
		}

		/* 3. reset dreq, and read reset st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, MDIO_SC_RESET_DREQ, 0x1,
					    MDIO_SC_RESET_ST, 0x1,
					    MDIO_CHECK_CLR_ST);
		if (ret) {
			dev_err(&bus->dev, "MDIO dis clk fail\n");
			return ret;
		}

		/* 4. en clk, and read clk st check */
		ret = mdio_sc_cfg_reg_write(mdio_dev, MDIO_SC_CLK_EN,
					    0x1, MDIO_SC_CLK_ST, 0x1,
					    MDIO_CHECK_SET_ST);
		if (ret)
			dev_err(&bus->dev, "MDIO en clk fail\n");
	} else if (is_acpi_node(bus->parent->fwnode)) {
		acpi_status s;

		s = acpi_evaluate_object(ACPI_HANDLE(bus->parent),
					 "_RST", NULL, NULL);
		if (ACPI_FAILURE(s)) {
			dev_err(&bus->dev, "Reset failed, return:%#x\n", s);
			ret = -EBUSY;
		} else {
			ret = 0;
		}
	} else {
		dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n");
		ret = -ENXIO;
	}
	return ret;
}

/**
 * hns_mdio_probe - probe mdio device
 * @pdev: mdio platform device
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_probe(struct platform_device *pdev)
{
	struct hns_mdio_device *mdio_dev;
	struct mii_bus *new_bus;
	struct resource *res;
	int ret = -ENODEV;

	if (!pdev) {
		dev_err(NULL, "pdev is NULL!\r\n");
		return -ENODEV;
	}

	mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL);
	if (!mdio_dev)
		return -ENOMEM;

	new_bus = devm_mdiobus_alloc(&pdev->dev);
	if (!new_bus) {
		dev_err(&pdev->dev, "mdiobus_alloc fail!\n");
		return -ENOMEM;
	}

	new_bus->name = MDIO_BUS_NAME;
	new_bus->read = hns_mdio_read;
	new_bus->write = hns_mdio_write;
	new_bus->reset = hns_mdio_reset;
	new_bus->priv = mdio_dev;
	new_bus->parent = &pdev->dev;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	mdio_dev->vbase = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(mdio_dev->vbase)) {
		ret = PTR_ERR(mdio_dev->vbase);
		return ret;
	}

	platform_set_drvdata(pdev, new_bus);
	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii",
		 dev_name(&pdev->dev));
	if (dev_of_node(&pdev->dev)) {
		mdio_dev->subctrl_vbase = syscon_node_to_regmap(
			of_parse_phandle(pdev->dev.of_node,
					 "subctrl-vbase", 0));
		if (IS_ERR(mdio_dev->subctrl_vbase)) {
			dev_warn(&pdev->dev, "no syscon hisilicon,peri-c-subctrl\n");
			mdio_dev->subctrl_vbase = NULL;
		}
		ret = of_mdiobus_register(new_bus, pdev->dev.of_node);
	} else if (is_acpi_node(pdev->dev.fwnode)) {
		/* Clear all the IRQ properties */
		memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR);

		/* Mask out all PHYs from auto probing. */
		new_bus->phy_mask = ~0;

		/* Register the MDIO bus */
		ret = mdiobus_register(new_bus);
	} else {
		dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n");
		ret = -ENXIO;
	}

	if (ret) {
		dev_err(&pdev->dev, "Cannot register as MDIO bus!\n");
		platform_set_drvdata(pdev, NULL);
		return ret;
	}

	return 0;
}

/**
 * hns_mdio_remove - remove mdio device
 * @pdev: mdio platform device
 *
 * Return 0 on success, negative on failure
 */
static int hns_mdio_remove(struct platform_device *pdev)
{
	struct mii_bus *bus;

	bus = platform_get_drvdata(pdev);

	mdiobus_unregister(bus);
	platform_set_drvdata(pdev, NULL);
	return 0;
}

static const struct of_device_id hns_mdio_match[] = {
	{.compatible = "hisilicon,mdio"},
	{.compatible = "hisilicon,hns-mdio"},
	{}
};

static const struct acpi_device_id hns_mdio_acpi_match[] = {
	{ "HISI0141", 0 },
	{ },
};
MODULE_DEVICE_TABLE(acpi, hns_mdio_acpi_match);

static struct platform_driver hns_mdio_driver = {
	.probe = hns_mdio_probe,
	.remove = hns_mdio_remove,
	.driver = {
		   .name = MDIO_DRV_NAME,
		   .of_match_table = hns_mdio_match,
		   .acpi_match_table = ACPI_PTR(hns_mdio_acpi_match),
		   },
};

module_platform_driver(hns_mdio_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
MODULE_ALIAS("platform:" MDIO_DRV_NAME);
Commit	Line	Data
5b904d39	1	/*
	2	* Copyright (c) 2014-2015 Hisilicon Limited.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
8a99ff5a	10	#include <linux/acpi.h>
5b904d39	11	#include <linux/errno.h>
	12	#include <linux/etherdevice.h>
	13	#include <linux/init.h>
	14	#include <linux/kernel.h>
c7fc9eb7	15	#include <linux/mfd/syscon.h>
5b904d39	16	#include <linux/module.h>
	17	#include <linux/mutex.h>
	18	#include <linux/netdevice.h>
	19	#include <linux/of_address.h>
	20	#include <linux/of.h>
	21	#include <linux/of_mdio.h>
	22	#include <linux/of_platform.h>
	23	#include <linux/phy.h>
	24	#include <linux/platform_device.h>
c7fc9eb7	25	#include <linux/regmap.h>
5b904d39	26	#include <linux/spinlock_types.h>
	27
	28	#define MDIO_DRV_NAME "Hi-HNS_MDIO"
	29	#define MDIO_BUS_NAME "Hisilicon MII Bus"
	30	#define MDIO_DRV_VERSION "1.3.0"
	31	#define MDIO_COPYRIGHT "Copyright(c) 2015 Huawei Corporation."
	32	#define MDIO_DRV_STRING MDIO_BUS_NAME
	33	#define MDIO_DEFAULT_DEVICE_DESCR MDIO_BUS_NAME
	34
	35	#define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
	36	#define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
	37
	38	#define MDIO_TIMEOUT 1000000
	39
	40	struct hns_mdio_device {
	41	void vbase; / mdio reg base address */
c7fc9eb7	42	struct regmap *subctrl_vbase;
5b904d39	43	};
	44
	45	/* mdio reg */
	46	#define MDIO_COMMAND_REG 0x0
	47	#define MDIO_ADDR_REG 0x4
	48	#define MDIO_WDATA_REG 0x8
	49	#define MDIO_RDATA_REG 0xc
	50	#define MDIO_STA_REG 0x10
	51
	52	/* cfg phy bit map */
	53	#define MDIO_CMD_DEVAD_M 0x1f
	54	#define MDIO_CMD_DEVAD_S 0
	55	#define MDIO_CMD_PRTAD_M 0x1f
	56	#define MDIO_CMD_PRTAD_S 5
	57	#define MDIO_CMD_OP_M 0x3
	58	#define MDIO_CMD_OP_S 10
	59	#define MDIO_CMD_ST_M 0x3
	60	#define MDIO_CMD_ST_S 12
	61	#define MDIO_CMD_START_B 14
	62
	63	#define MDIO_ADDR_DATA_M 0xffff
	64	#define MDIO_ADDR_DATA_S 0
	65
	66	#define MDIO_WDATA_DATA_M 0xffff
	67	#define MDIO_WDATA_DATA_S 0
	68
	69	#define MDIO_RDATA_DATA_M 0xffff
	70	#define MDIO_RDATA_DATA_S 0
	71
	72	#define MDIO_STATE_STA_B 0
	73
	74	enum mdio_st_clause {
	75	MDIO_ST_CLAUSE_45 = 0,
	76	MDIO_ST_CLAUSE_22
	77	};
	78
	79	enum mdio_c22_op_seq {
	80	MDIO_C22_WRITE = 1,
	81	MDIO_C22_READ = 2
	82	};
	83
	84	enum mdio_c45_op_seq {
	85	MDIO_C45_WRITE_ADDR = 0,
	86	MDIO_C45_WRITE_DATA,
	87	MDIO_C45_READ_INCREMENT,
	88	MDIO_C45_READ
	89	};
	90
	91	/* peri subctrl reg */
	92	#define MDIO_SC_CLK_EN 0x338
	93	#define MDIO_SC_CLK_DIS 0x33C
	94	#define MDIO_SC_RESET_REQ 0xA38
	95	#define MDIO_SC_RESET_DREQ 0xA3C
	96	#define MDIO_SC_CTRL 0x2010
	97	#define MDIO_SC_CLK_ST 0x531C
	98	#define MDIO_SC_RESET_ST 0x5A1C
	99
	100	static void mdio_write_reg(void *base, u32 reg, u32 value)
	101	{
	102	u8 __iomem reg_addr = (u8 __iomem )base;
	103
	104	writel_relaxed(value, reg_addr + reg);
	105	}
	106
107	#define MDIO_WRITE_REG(a, reg, value) \
108	mdio_write_reg((a)->vbase, (reg), (value))
109
110	static u32 mdio_read_reg(void *base, u32 reg)
111	{
112	u8 __iomem reg_addr = (u8 __iomem )base;
113
114	return readl_relaxed(reg_addr + reg);
115	}
116
117	#define mdio_set_field(origin, mask, shift, val) \
118	do { \
119	(origin) &= (~((mask) << (shift))); \
120	(origin) \|= (((val) & (mask)) << (shift)); \
121	} while (0)
122
123	#define mdio_get_field(origin, mask, shift) (((origin) >> (shift)) & (mask))
124
125	static void mdio_set_reg_field(void *base, u32 reg, u32 mask, u32 shift,
126	u32 val)
127	{
128	u32 origin = mdio_read_reg(base, reg);
129
130	mdio_set_field(origin, mask, shift, val);
131	mdio_write_reg(base, reg, origin);
132	}
133
134	#define MDIO_SET_REG_FIELD(dev, reg, mask, shift, val) \
135	mdio_set_reg_field((dev)->vbase, (reg), (mask), (shift), (val))
136
137	static u32 mdio_get_reg_field(void *base, u32 reg, u32 mask, u32 shift)
138	{
139	u32 origin;
140
141	origin = mdio_read_reg(base, reg);
142	return mdio_get_field(origin, mask, shift);
143	}
144
145	#define MDIO_GET_REG_FIELD(dev, reg, mask, shift) \
146	mdio_get_reg_field((dev)->vbase, (reg), (mask), (shift))
147
148	#define MDIO_GET_REG_BIT(dev, reg, bit) \
149	mdio_get_reg_field((dev)->vbase, (reg), 0x1ull, (bit))
150
151	#define MDIO_CHECK_SET_ST 1
152	#define MDIO_CHECK_CLR_ST 0
153
154	static int mdio_sc_cfg_reg_write(struct hns_mdio_device *mdio_dev,
155	u32 cfg_reg, u32 set_val,
156	u32 st_reg, u32 st_msk, u8 check_st)
157	{
158	u32 time_cnt;
159	u32 reg_value;
160
c7fc9eb7	161	regmap_write(mdio_dev->subctrl_vbase, cfg_reg, set_val);
5b904d39	162
5b904d39	163	for (time_cnt = MDIO_TIMEOUT; time_cnt; time_cnt--) {
c7fc9eb7	164	regmap_read(mdio_dev->subctrl_vbase, st_reg, &reg_value);
5b904d39	165	reg_value &= st_msk;
	166	if ((!!check_st) == (!!reg_value))
	167	break;
	168	}
	169
	170	if ((!!check_st) != (!!reg_value))
	171	return -EBUSY;
	172
	173	return 0;
	174	}
	175
	176	static int hns_mdio_wait_ready(struct mii_bus *bus)
	177	{
	178	struct hns_mdio_device *mdio_dev = bus->priv;
	179	int i;
	180	u32 cmd_reg_value = 1;
	181
	182	/* waitting for MDIO_COMMAND_REG 's mdio_start==0 */
	183	/* after that can do read or write*/
	184	for (i = 0; cmd_reg_value; i++) {
	185	cmd_reg_value = MDIO_GET_REG_BIT(mdio_dev,
	186	MDIO_COMMAND_REG,
	187	MDIO_CMD_START_B);
	188	if (i == MDIO_TIMEOUT)
	189	return -ETIMEDOUT;
	190	}
	191
	192	return 0;
	193	}
	194
	195	static void hns_mdio_cmd_write(struct hns_mdio_device *mdio_dev,
	196	u8 is_c45, u8 op, u8 phy_id, u16 cmd)
	197	{
	198	u32 cmd_reg_value;
	199	u8 st = is_c45 ? MDIO_ST_CLAUSE_45 : MDIO_ST_CLAUSE_22;
	200
	201	cmd_reg_value = st << MDIO_CMD_ST_S;
	202	cmd_reg_value \|= op << MDIO_CMD_OP_S;
	203	cmd_reg_value \|=
	204	(phy_id & MDIO_CMD_PRTAD_M) << MDIO_CMD_PRTAD_S;
	205	cmd_reg_value \|= (cmd & MDIO_CMD_DEVAD_M) << MDIO_CMD_DEVAD_S;
	206	cmd_reg_value \|= 1 << MDIO_CMD_START_B;
	207
	208	MDIO_WRITE_REG(mdio_dev, MDIO_COMMAND_REG, cmd_reg_value);
	209	}
	210
	211	/**
	212	* hns_mdio_write - access phy register
	213	* @bus: mdio bus
	214	* @phy_id: phy id
	215	* @regnum: register num
	216	* @value: register value
	217	*
	218	* Return 0 on success, negative on failure
	219	*/
	220	static int hns_mdio_write(struct mii_bus *bus,
	221	int phy_id, int regnum, u16 data)
	222	{
	223	int ret;
	224	struct hns_mdio_device mdio_dev = (struct hns_mdio_device )bus->priv;
	225	u8 devad = ((regnum >> 16) & 0x1f);
	226	u8 is_c45 = !!(regnum & MII_ADDR_C45);
	227	u16 reg = (u16)(regnum & 0xffff);
	228	u8 op;
229	u16 cmd_reg_cfg;
230
231	dev_dbg(&bus->dev, "mdio write %s,base is %p\n",
232	bus->id, mdio_dev->vbase);
233	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x, write data=%d\n",
234	phy_id, is_c45, devad, reg, data);
235
236	/* wait for ready */
237	ret = hns_mdio_wait_ready(bus);
238	if (ret) {
239	dev_err(&bus->dev, "MDIO bus is busy\n");
240	return ret;
241	}
242
243	if (!is_c45) {
244	cmd_reg_cfg = reg;
245	op = MDIO_C22_WRITE;
246	} else {
247	/* config the cmd-reg to write addr*/
248	MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
249	MDIO_ADDR_DATA_S, reg);
250
251	hns_mdio_cmd_write(mdio_dev, is_c45,
252	MDIO_C45_WRITE_ADDR, phy_id, devad);
253
254	/* check for read or write opt is finished */
255	ret = hns_mdio_wait_ready(bus);
256	if (ret) {
257	dev_err(&bus->dev, "MDIO bus is busy\n");
258	return ret;
259	}
260
261	/* config the data needed writing */
262	cmd_reg_cfg = devad;
263	op = MDIO_C45_WRITE_ADDR;
264	}
265
266	MDIO_SET_REG_FIELD(mdio_dev, MDIO_WDATA_REG, MDIO_WDATA_DATA_M,
267	MDIO_WDATA_DATA_S, data);
268
269	hns_mdio_cmd_write(mdio_dev, is_c45, op, phy_id, cmd_reg_cfg);
270
271	return 0;
272	}
273
274	/**
275	* hns_mdio_read - access phy register
276	* @bus: mdio bus
277	* @phy_id: phy id
278	* @regnum: register num
279	* @value: register value
280	*
281	* Return phy register value
282	*/
283	static int hns_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
284	{
285	int ret;
286	u16 reg_val = 0;
287	u8 devad = ((regnum >> 16) & 0x1f);
288	u8 is_c45 = !!(regnum & MII_ADDR_C45);
289	u16 reg = (u16)(regnum & 0xffff);
290	struct hns_mdio_device mdio_dev = (struct hns_mdio_device )bus->priv;
291
292	dev_dbg(&bus->dev, "mdio read %s,base is %p\n",
293	bus->id, mdio_dev->vbase);
294	dev_dbg(&bus->dev, "phy id=%d, is_c45=%d, devad=%d, reg=%#x!\n",
295	phy_id, is_c45, devad, reg);
296
297	/* Step 1: wait for ready */
298	ret = hns_mdio_wait_ready(bus);
299	if (ret) {
300	dev_err(&bus->dev, "MDIO bus is busy\n");
301	return ret;
302	}
303
304	if (!is_c45) {
305	hns_mdio_cmd_write(mdio_dev, is_c45,
306	MDIO_C22_READ, phy_id, reg);
307	} else {
308	MDIO_SET_REG_FIELD(mdio_dev, MDIO_ADDR_REG, MDIO_ADDR_DATA_M,
309	MDIO_ADDR_DATA_S, reg);
310
311	/* Step 2; config the cmd-reg to write addr*/
312	hns_mdio_cmd_write(mdio_dev, is_c45,
313	MDIO_C45_WRITE_ADDR, phy_id, devad);
314
315	/* Step 3: check for read or write opt is finished */
316	ret = hns_mdio_wait_ready(bus);
317	if (ret) {
318	dev_err(&bus->dev, "MDIO bus is busy\n");
319	return ret;
320	}
321
322	hns_mdio_cmd_write(mdio_dev, is_c45,
323	MDIO_C45_WRITE_ADDR, phy_id, devad);
324	}
325
326	/* Step 5: waitting for MDIO_COMMAND_REG 's mdio_start==0,*/
327	/* check for read or write opt is finished */
328	ret = hns_mdio_wait_ready(bus);
329	if (ret) {
330	dev_err(&bus->dev, "MDIO bus is busy\n");
331	return ret;
332	}
333
334	reg_val = MDIO_GET_REG_BIT(mdio_dev, MDIO_STA_REG, MDIO_STATE_STA_B);
335	if (reg_val) {
336	dev_err(&bus->dev, " ERROR! MDIO Read failed!\n");
337	return -EBUSY;
338	}
339
340	/* Step 6; get out data*/
341	reg_val = (u16)MDIO_GET_REG_FIELD(mdio_dev, MDIO_RDATA_REG,
342	MDIO_RDATA_DATA_M, MDIO_RDATA_DATA_S);
343
344	return reg_val;
345	}
346
347	/**
348	* hns_mdio_reset - reset mdio bus
349	* @bus: mdio bus
350	*
351	* Return 0 on success, negative on failure
352	*/
353	static int hns_mdio_reset(struct mii_bus *bus)
354	{
355	struct hns_mdio_device mdio_dev = (struct hns_mdio_device )bus->priv;
356	int ret;
357
8a99ff5a KY	358	if (dev_of_node(bus->parent)) {
	359	if (!mdio_dev->subctrl_vbase) {
	360	dev_err(&bus->dev, "mdio sys ctl reg has not maped\n");
	361	return -ENODEV;
	362	}
16a9f361	363
8a99ff5a KY	364	/* 1. reset req, and read reset st check */
	365	ret = mdio_sc_cfg_reg_write(mdio_dev, MDIO_SC_RESET_REQ, 0x1,
	366	MDIO_SC_RESET_ST, 0x1,
	367	MDIO_CHECK_SET_ST);
	368	if (ret) {
	369	dev_err(&bus->dev, "MDIO reset fail\n");
	370	return ret;
	371	}
5b904d39	372
8a99ff5a KY	373	/* 2. dis clk, and read clk st check */
	374	ret = mdio_sc_cfg_reg_write(mdio_dev, MDIO_SC_CLK_DIS,
	375	0x1, MDIO_SC_CLK_ST, 0x1,
	376	MDIO_CHECK_CLR_ST);
	377	if (ret) {
	378	dev_err(&bus->dev, "MDIO dis clk fail\n");
	379	return ret;
	380	}
5b904d39	381
8a99ff5a KY	382	/* 3. reset dreq, and read reset st check */
	383	ret = mdio_sc_cfg_reg_write(mdio_dev, MDIO_SC_RESET_DREQ, 0x1,
	384	MDIO_SC_RESET_ST, 0x1,
	385	MDIO_CHECK_CLR_ST);
	386	if (ret) {
	387	dev_err(&bus->dev, "MDIO dis clk fail\n");
	388	return ret;
	389	}
5b904d39	390
8a99ff5a KY	391	/* 4. en clk, and read clk st check */
	392	ret = mdio_sc_cfg_reg_write(mdio_dev, MDIO_SC_CLK_EN,
	393	0x1, MDIO_SC_CLK_ST, 0x1,
	394	MDIO_CHECK_SET_ST);
	395	if (ret)
	396	dev_err(&bus->dev, "MDIO en clk fail\n");
	397	} else if (is_acpi_node(bus->parent->fwnode)) {
	398	acpi_status s;
	399
	400	s = acpi_evaluate_object(ACPI_HANDLE(bus->parent),
	401	"_RST", NULL, NULL);
	402	if (ACPI_FAILURE(s)) {
	403	dev_err(&bus->dev, "Reset failed, return:%#x\n", s);
	404	ret = -EBUSY;
	405	} else {
	406	ret = 0;
	407	}
	408	} else {
	409	dev_err(&bus->dev, "Can not get cfg data from DT or ACPI\n");
	410	ret = -ENXIO;
5b904d39	411	}
5b904d39	412	return ret;
	413	}
	414
5b904d39	415	/**
	416	* hns_mdio_probe - probe mdio device
	417	* @pdev: mdio platform device
	418	*
	419	* Return 0 on success, negative on failure
	420	*/
	421	static int hns_mdio_probe(struct platform_device *pdev)
	422	{
5b904d39	423	struct hns_mdio_device *mdio_dev;
	424	struct mii_bus *new_bus;
	425	struct resource *res;
16a9f361	426	int ret = -ENODEV;
5b904d39	427
	428	if (!pdev) {
	429	dev_err(NULL, "pdev is NULL!\r\n");
	430	return -ENODEV;
	431	}
16a9f361	432
5b904d39	433	mdio_dev = devm_kzalloc(&pdev->dev, sizeof(*mdio_dev), GFP_KERNEL);
	434	if (!mdio_dev)
	435	return -ENOMEM;
	436
	437	new_bus = devm_mdiobus_alloc(&pdev->dev);
	438	if (!new_bus) {
	439	dev_err(&pdev->dev, "mdiobus_alloc fail!\n");
	440	return -ENOMEM;
	441	}
	442
	443	new_bus->name = MDIO_BUS_NAME;
	444	new_bus->read = hns_mdio_read;
	445	new_bus->write = hns_mdio_write;
	446	new_bus->reset = hns_mdio_reset;
	447	new_bus->priv = mdio_dev;
16a9f361	448	new_bus->parent = &pdev->dev;
5b904d39	449
	450	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	451	mdio_dev->vbase = devm_ioremap_resource(&pdev->dev, res);
	452	if (IS_ERR(mdio_dev->vbase)) {
	453	ret = PTR_ERR(mdio_dev->vbase);
	454	return ret;
	455	}
	456
5b904d39	457	platform_set_drvdata(pdev, new_bus);
16a9f361 KY	458	snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%s", "Mii",
	459	dev_name(&pdev->dev));
	460	if (dev_of_node(&pdev->dev)) {
	461	mdio_dev->subctrl_vbase = syscon_node_to_regmap(
	462	of_parse_phandle(pdev->dev.of_node,
	463	"subctrl-vbase", 0));
	464	if (IS_ERR(mdio_dev->subctrl_vbase)) {
	465	dev_warn(&pdev->dev, "no syscon hisilicon,peri-c-subctrl\n");
	466	mdio_dev->subctrl_vbase = NULL;
	467	}
	468	ret = of_mdiobus_register(new_bus, pdev->dev.of_node);
8a99ff5a KY	469	} else if (is_acpi_node(pdev->dev.fwnode)) {
	470	/* Clear all the IRQ properties */
	471	memset(new_bus->irq, PHY_POLL, 4 * PHY_MAX_ADDR);
	472
	473	/* Mask out all PHYs from auto probing. */
	474	new_bus->phy_mask = ~0;
	475
	476	/* Register the MDIO bus */
	477	ret = mdiobus_register(new_bus);
	478	} else {
	479	dev_err(&pdev->dev, "Can not get cfg data from DT or ACPI\n");
	480	ret = -ENXIO;
16a9f361	481	}
5b904d39	482
5b904d39	483	if (ret) {
	484	dev_err(&pdev->dev, "Cannot register as MDIO bus!\n");
	485	platform_set_drvdata(pdev, NULL);
	486	return ret;
	487	}
	488
	489	return 0;
	490	}
	491
	492	/**
	493	* hns_mdio_remove - remove mdio device
	494	* @pdev: mdio platform device
	495	*
	496	* Return 0 on success, negative on failure
	497	*/
	498	static int hns_mdio_remove(struct platform_device *pdev)
	499	{
	500	struct mii_bus *bus;
	501
	502	bus = platform_get_drvdata(pdev);
	503
	504	mdiobus_unregister(bus);
	505	platform_set_drvdata(pdev, NULL);
	506	return 0;
	507	}
	508
	509	static const struct of_device_id hns_mdio_match[] = {
	510	{.compatible = "hisilicon,mdio"},
	511	{.compatible = "hisilicon,hns-mdio"},
	512	{}
	513	};
	514
8a99ff5a KY	515	static const struct acpi_device_id hns_mdio_acpi_match[] = {
	516	{ "HISI0141", 0 },
	517	{ },
	518	};
	519	MODULE_DEVICE_TABLE(acpi, hns_mdio_acpi_match);
	520
5b904d39	521	static struct platform_driver hns_mdio_driver = {
	522	.probe = hns_mdio_probe,
	523	.remove = hns_mdio_remove,
	524	.driver = {
	525	.name = MDIO_DRV_NAME,
	526	.of_match_table = hns_mdio_match,
8a99ff5a	527	.acpi_match_table = ACPI_PTR(hns_mdio_acpi_match),
5b904d39	528	},
	529	};
	530
	531	module_platform_driver(hns_mdio_driver);
	532
	533	MODULE_LICENSE("GPL");
	534	MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
	535	MODULE_DESCRIPTION("Hisilicon HNS MDIO driver");
	536	MODULE_ALIAS("platform:" MDIO_DRV_NAME);