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net: hns3: Modify hns3_get_max_available_channels
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3vf / hclgevf_main.c
CommitLineData
e2cb1dec
SM		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
3
4#include <linux/etherdevice.h>
6988eb2a 5#include <net/rtnetlink.h>
e2cb1dec
SM		 6#include "hclgevf_cmd.h"
7#include "hclgevf_main.h"
8#include "hclge_mbx.h"
9#include "hnae3.h"
10
11#define HCLGEVF_NAME "hclgevf"
12
7a01c897
SM		 13static int hclgevf_init_hdev(struct hclgevf_dev *hdev);
14static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev);
e2cb1dec
SM		 15static struct hnae3_ae_algo ae_algovf;
16
17static const struct pci_device_id ae_algovf_pci_tbl[] = {
18 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_VF), 0},
19 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF), 0},
20 /* required last entry */
21 {0, }
22};
23
2f550a46
YL		 24MODULE_DEVICE_TABLE(pci, ae_algovf_pci_tbl);
25
e2cb1dec
SM		 26static inline struct hclgevf_dev *hclgevf_ae_get_hdev(
27 struct hnae3_handle *handle)
28{
29 return container_of(handle, struct hclgevf_dev, nic);
30}
31
32static int hclgevf_tqps_update_stats(struct hnae3_handle *handle)
33{
b4f1d303 34 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
e2cb1dec 35 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
e2cb1dec
SM		 36 struct hclgevf_desc desc;
37 struct hclgevf_tqp *tqp;
38 int status;
39 int i;
40
b4f1d303
JS		 41 for (i = 0; i < kinfo->num_tqps; i++) {
42 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
e2cb1dec
SM		 43 hclgevf_cmd_setup_basic_desc(&desc,
44 HCLGEVF_OPC_QUERY_RX_STATUS,
45 true);
46
47 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
48 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
49 if (status) {
50 dev_err(&hdev->pdev->dev,
51 "Query tqp stat fail, status = %d,queue = %d\n",
52 status, i);
53 return status;
54 }
55 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
cf72fa63 56 le32_to_cpu(desc.data[1]);
e2cb1dec
SM		 57
58 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_TX_STATUS,
59 true);
60
61 desc.data[0] = cpu_to_le32(tqp->index & 0x1ff);
62 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
63 if (status) {
64 dev_err(&hdev->pdev->dev,
65 "Query tqp stat fail, status = %d,queue = %d\n",
66 status, i);
67 return status;
68 }
69 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
cf72fa63 70 le32_to_cpu(desc.data[1]);
e2cb1dec
SM		 71 }
72
73 return 0;
74}
75
76static u64 *hclgevf_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
77{
78 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
e2cb1dec
SM		 79 struct hclgevf_tqp *tqp;
80 u64 *buff = data;
81 int i;
82
b4f1d303
JS		 83 for (i = 0; i < kinfo->num_tqps; i++) {
84 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
e2cb1dec
SM		 85 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
86 }
87 for (i = 0; i < kinfo->num_tqps; i++) {
b4f1d303 88 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
e2cb1dec
SM		 89 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
90 }
91
92 return buff;
93}
94
95static int hclgevf_tqps_get_sset_count(struct hnae3_handle *handle, int strset)
96{
b4f1d303 97 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
e2cb1dec 98
b4f1d303 99 return kinfo->num_tqps * 2;
e2cb1dec
SM		 100}
101
102static u8 *hclgevf_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
103{
b4f1d303 104 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
e2cb1dec
SM		 105 u8 *buff = data;
106 int i = 0;
107
b4f1d303
JS		 108 for (i = 0; i < kinfo->num_tqps; i++) {
109 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
110 struct hclgevf_tqp, q);
0c218123 111 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
e2cb1dec
SM		 112 tqp->index);
113 buff += ETH_GSTRING_LEN;
114 }
115
b4f1d303
JS		 116 for (i = 0; i < kinfo->num_tqps; i++) {
117 struct hclgevf_tqp *tqp = container_of(kinfo->tqp[i],
118 struct hclgevf_tqp, q);
0c218123 119 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
e2cb1dec
SM		 120 tqp->index);
121 buff += ETH_GSTRING_LEN;
122 }
123
124 return buff;
125}
126
127static void hclgevf_update_stats(struct hnae3_handle *handle,
128 struct net_device_stats *net_stats)
129{
130 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
131 int status;
132
133 status = hclgevf_tqps_update_stats(handle);
134 if (status)
135 dev_err(&hdev->pdev->dev,
136 "VF update of TQPS stats fail, status = %d.\n",
137 status);
138}
139
140static int hclgevf_get_sset_count(struct hnae3_handle *handle, int strset)
141{
142 if (strset == ETH_SS_TEST)
143 return -EOPNOTSUPP;
144 else if (strset == ETH_SS_STATS)
145 return hclgevf_tqps_get_sset_count(handle, strset);
146
147 return 0;
148}
149
150static void hclgevf_get_strings(struct hnae3_handle *handle, u32 strset,
151 u8 *data)
152{
153 u8 *p = (char *)data;
154
155 if (strset == ETH_SS_STATS)
156 p = hclgevf_tqps_get_strings(handle, p);
157}
158
159static void hclgevf_get_stats(struct hnae3_handle *handle, u64 *data)
160{
161 hclgevf_tqps_get_stats(handle, data);
162}
163
164static int hclgevf_get_tc_info(struct hclgevf_dev *hdev)
165{
166 u8 resp_msg;
167 int status;
168
169 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_TCINFO, 0, NULL, 0,
170 true, &resp_msg, sizeof(u8));
171 if (status) {
172 dev_err(&hdev->pdev->dev,
173 "VF request to get TC info from PF failed %d",
174 status);
175 return status;
176 }
177
178 hdev->hw_tc_map = resp_msg;
179
180 return 0;
181}
182
6cee6fc3 183static int hclgevf_get_queue_info(struct hclgevf_dev *hdev)
e2cb1dec
SM		 184{
185#define HCLGEVF_TQPS_RSS_INFO_LEN 8
186 u8 resp_msg[HCLGEVF_TQPS_RSS_INFO_LEN];
187 int status;
188
189 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_QINFO, 0, NULL, 0,
190 true, resp_msg,
191 HCLGEVF_TQPS_RSS_INFO_LEN);
192 if (status) {
193 dev_err(&hdev->pdev->dev,
194 "VF request to get tqp info from PF failed %d",
195 status);
196 return status;
197 }
198
199 memcpy(&hdev->num_tqps, &resp_msg[0], sizeof(u16));
200 memcpy(&hdev->rss_size_max, &resp_msg[2], sizeof(u16));
201 memcpy(&hdev->num_desc, &resp_msg[4], sizeof(u16));
202 memcpy(&hdev->rx_buf_len, &resp_msg[6], sizeof(u16));
203
204 return 0;
205}
206
e2cb1dec
SM		 207static int hclgevf_alloc_tqps(struct hclgevf_dev *hdev)
208{
209 struct hclgevf_tqp *tqp;
210 int i;
211
7a01c897
SM		 212 /* if this is on going reset then we need to re-allocate the TPQs
213 * since we cannot assume we would get same number of TPQs back from PF
214 */
215 if (hclgevf_dev_ongoing_reset(hdev))
216 devm_kfree(&hdev->pdev->dev, hdev->htqp);
217
e2cb1dec
SM		 218 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
219 sizeof(struct hclgevf_tqp), GFP_KERNEL);
220 if (!hdev->htqp)
221 return -ENOMEM;
222
223 tqp = hdev->htqp;
224
225 for (i = 0; i < hdev->num_tqps; i++) {
226 tqp->dev = &hdev->pdev->dev;
227 tqp->index = i;
228
229 tqp->q.ae_algo = &ae_algovf;
230 tqp->q.buf_size = hdev->rx_buf_len;
231 tqp->q.desc_num = hdev->num_desc;
232 tqp->q.io_base = hdev->hw.io_base + HCLGEVF_TQP_REG_OFFSET +
233 i * HCLGEVF_TQP_REG_SIZE;
234
235 tqp++;
236 }
237
238 return 0;
239}
240
241static int hclgevf_knic_setup(struct hclgevf_dev *hdev)
242{
243 struct hnae3_handle *nic = &hdev->nic;
244 struct hnae3_knic_private_info *kinfo;
245 u16 new_tqps = hdev->num_tqps;
246 int i;
247
248 kinfo = &nic->kinfo;
249 kinfo->num_tc = 0;
250 kinfo->num_desc = hdev->num_desc;
251 kinfo->rx_buf_len = hdev->rx_buf_len;
252 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++)
253 if (hdev->hw_tc_map & BIT(i))
254 kinfo->num_tc++;
255
256 kinfo->rss_size
257 = min_t(u16, hdev->rss_size_max, new_tqps / kinfo->num_tc);
258 new_tqps = kinfo->rss_size * kinfo->num_tc;
259 kinfo->num_tqps = min(new_tqps, hdev->num_tqps);
260
7a01c897
SM		 261 /* if this is on going reset then we need to re-allocate the hnae queues
262 * as well since number of TPQs from PF might have changed.
263 */
264 if (hclgevf_dev_ongoing_reset(hdev))
265 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
266
e2cb1dec
SM		 267 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
268 sizeof(struct hnae3_queue *), GFP_KERNEL);
269 if (!kinfo->tqp)
270 return -ENOMEM;
271
272 for (i = 0; i < kinfo->num_tqps; i++) {
273 hdev->htqp[i].q.handle = &hdev->nic;
274 hdev->htqp[i].q.tqp_index = i;
275 kinfo->tqp[i] = &hdev->htqp[i].q;
276 }
277
278 return 0;
279}
280
281static void hclgevf_request_link_info(struct hclgevf_dev *hdev)
282{
283 int status;
284 u8 resp_msg;
285
286 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_GET_LINK_STATUS, 0, NULL,
287 0, false, &resp_msg, sizeof(u8));
288 if (status)
289 dev_err(&hdev->pdev->dev,
290 "VF failed to fetch link status(%d) from PF", status);
291}
292
293void hclgevf_update_link_status(struct hclgevf_dev *hdev, int link_state)
294{
295 struct hnae3_handle *handle = &hdev->nic;
296 struct hnae3_client *client;
297
298 client = handle->client;
299
582d37bb
PL		 300 link_state =
301 test_bit(HCLGEVF_STATE_DOWN, &hdev->state) ? 0 : link_state;
302
e2cb1dec
SM		 303 if (link_state != hdev->hw.mac.link) {
304 client->ops->link_status_change(handle, !!link_state);
305 hdev->hw.mac.link = link_state;
306 }
307}
308
309static int hclgevf_set_handle_info(struct hclgevf_dev *hdev)
310{
311 struct hnae3_handle *nic = &hdev->nic;
312 int ret;
313
314 nic->ae_algo = &ae_algovf;
315 nic->pdev = hdev->pdev;
316 nic->numa_node_mask = hdev->numa_node_mask;
424eb834 317 nic->flags |= HNAE3_SUPPORT_VF;
e2cb1dec
SM		 318
319 if (hdev->ae_dev->dev_type != HNAE3_DEV_KNIC) {
320 dev_err(&hdev->pdev->dev, "unsupported device type %d\n",
321 hdev->ae_dev->dev_type);
322 return -EINVAL;
323 }
324
325 ret = hclgevf_knic_setup(hdev);
326 if (ret)
327 dev_err(&hdev->pdev->dev, "VF knic setup failed %d\n",
328 ret);
329 return ret;
330}
331
332static void hclgevf_free_vector(struct hclgevf_dev *hdev, int vector_id)
333{
36cbbdf6
PL		 334 if (hdev->vector_status[vector_id] == HCLGEVF_INVALID_VPORT) {
335 dev_warn(&hdev->pdev->dev,
336 "vector(vector_id %d) has been freed.\n", vector_id);
337 return;
338 }
339
e2cb1dec
SM		 340 hdev->vector_status[vector_id] = HCLGEVF_INVALID_VPORT;
341 hdev->num_msi_left += 1;
342 hdev->num_msi_used -= 1;
343}
344
345static int hclgevf_get_vector(struct hnae3_handle *handle, u16 vector_num,
346 struct hnae3_vector_info *vector_info)
347{
348 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
349 struct hnae3_vector_info *vector = vector_info;
350 int alloc = 0;
351 int i, j;
352
353 vector_num = min(hdev->num_msi_left, vector_num);
354
355 for (j = 0; j < vector_num; j++) {
356 for (i = HCLGEVF_MISC_VECTOR_NUM + 1; i < hdev->num_msi; i++) {
357 if (hdev->vector_status[i] == HCLGEVF_INVALID_VPORT) {
358 vector->vector = pci_irq_vector(hdev->pdev, i);
359 vector->io_addr = hdev->hw.io_base +
360 HCLGEVF_VECTOR_REG_BASE +
361 (i - 1) * HCLGEVF_VECTOR_REG_OFFSET;
362 hdev->vector_status[i] = 0;
363 hdev->vector_irq[i] = vector->vector;
364
365 vector++;
366 alloc++;
367
368 break;
369 }
370 }
371 }
372 hdev->num_msi_left -= alloc;
373 hdev->num_msi_used += alloc;
374
375 return alloc;
376}
377
378static int hclgevf_get_vector_index(struct hclgevf_dev *hdev, int vector)
379{
380 int i;
381
382 for (i = 0; i < hdev->num_msi; i++)
383 if (vector == hdev->vector_irq[i])
384 return i;
385
386 return -EINVAL;
387}
388
389static u32 hclgevf_get_rss_key_size(struct hnae3_handle *handle)
390{
391 return HCLGEVF_RSS_KEY_SIZE;
392}
393
394static u32 hclgevf_get_rss_indir_size(struct hnae3_handle *handle)
395{
396 return HCLGEVF_RSS_IND_TBL_SIZE;
397}
398
399static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
400{
401 const u8 *indir = hdev->rss_cfg.rss_indirection_tbl;
402 struct hclgevf_rss_indirection_table_cmd *req;
403 struct hclgevf_desc desc;
404 int status;
405 int i, j;
406
407 req = (struct hclgevf_rss_indirection_table_cmd *)desc.data;
408
409 for (i = 0; i < HCLGEVF_RSS_CFG_TBL_NUM; i++) {
410 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
411 false);
412 req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE;
413 req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK;
414 for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
415 req->rss_result[j] =
416 indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
417
418 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
419 if (status) {
420 dev_err(&hdev->pdev->dev,
421 "VF failed(=%d) to set RSS indirection table\n",
422 status);
423 return status;
424 }
425 }
426
427 return 0;
428}
429
430static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev, u16 rss_size)
431{
432 struct hclgevf_rss_tc_mode_cmd *req;
433 u16 tc_offset[HCLGEVF_MAX_TC_NUM];
434 u16 tc_valid[HCLGEVF_MAX_TC_NUM];
435 u16 tc_size[HCLGEVF_MAX_TC_NUM];
436 struct hclgevf_desc desc;
437 u16 roundup_size;
438 int status;
439 int i;
440
441 req = (struct hclgevf_rss_tc_mode_cmd *)desc.data;
442
443 roundup_size = roundup_pow_of_two(rss_size);
444 roundup_size = ilog2(roundup_size);
445
446 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
447 tc_valid[i] = !!(hdev->hw_tc_map & BIT(i));
448 tc_size[i] = roundup_size;
449 tc_offset[i] = rss_size * i;
450 }
451
452 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
453 for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
e4e87715
PL		 454 hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B,
455 (tc_valid[i] & 0x1));
456 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M,
457 HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
458 hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M,
459 HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
e2cb1dec
SM		 460 }
461 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
462 if (status)
463 dev_err(&hdev->pdev->dev,
464 "VF failed(=%d) to set rss tc mode\n", status);
465
466 return status;
467}
468
469static int hclgevf_get_rss_hw_cfg(struct hnae3_handle *handle, u8 *hash,
470 u8 *key)
471{
472 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
473 struct hclgevf_rss_config_cmd *req;
474 int lkup_times = key ? 3 : 1;
475 struct hclgevf_desc desc;
476 int key_offset;
477 int key_size;
478 int status;
479
480 req = (struct hclgevf_rss_config_cmd *)desc.data;
481 lkup_times = (lkup_times == 3) ? 3 : ((hash) ? 1 : 0);
482
483 for (key_offset = 0; key_offset < lkup_times; key_offset++) {
484 hclgevf_cmd_setup_basic_desc(&desc,
485 HCLGEVF_OPC_RSS_GENERIC_CONFIG,
486 true);
487 req->hash_config |= (key_offset << HCLGEVF_RSS_HASH_KEY_OFFSET);
488
489 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
490 if (status) {
491 dev_err(&hdev->pdev->dev,
492 "failed to get hardware RSS cfg, status = %d\n",
493 status);
494 return status;
495 }
496
497 if (key_offset == 2)
498 key_size =
499 HCLGEVF_RSS_KEY_SIZE - HCLGEVF_RSS_HASH_KEY_NUM * 2;
500 else
501 key_size = HCLGEVF_RSS_HASH_KEY_NUM;
502
503 if (key)
504 memcpy(key + key_offset * HCLGEVF_RSS_HASH_KEY_NUM,
505 req->hash_key,
506 key_size);
507 }
508
509 if (hash) {
510 if ((req->hash_config & 0xf) == HCLGEVF_RSS_HASH_ALGO_TOEPLITZ)
511 *hash = ETH_RSS_HASH_TOP;
512 else
513 *hash = ETH_RSS_HASH_UNKNOWN;
514 }
515
516 return 0;
517}
518
519static int hclgevf_get_rss(struct hnae3_handle *handle, u32 *indir, u8 *key,
520 u8 *hfunc)
521{
522 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
523 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
524 int i;
525
526 if (indir)
527 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
528 indir[i] = rss_cfg->rss_indirection_tbl[i];
529
530 return hclgevf_get_rss_hw_cfg(handle, hfunc, key);
531}
532
533static int hclgevf_set_rss(struct hnae3_handle *handle, const u32 *indir,
534 const u8 *key, const u8 hfunc)
535{
536 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
537 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
538 int i;
539
540 /* update the shadow RSS table with user specified qids */
541 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
542 rss_cfg->rss_indirection_tbl[i] = indir[i];
543
544 /* update the hardware */
545 return hclgevf_set_rss_indir_table(hdev);
546}
547
548static int hclgevf_get_tc_size(struct hnae3_handle *handle)
549{
550 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
551 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
552
553 return rss_cfg->rss_size;
554}
555
556static int hclgevf_bind_ring_to_vector(struct hnae3_handle *handle, bool en,
b204bc74 557 int vector_id,
e2cb1dec
SM		 558 struct hnae3_ring_chain_node *ring_chain)
559{
e2cb1dec
SM		 560 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
561 struct hnae3_ring_chain_node *node;
562 struct hclge_mbx_vf_to_pf_cmd *req;
563 struct hclgevf_desc desc;
b204bc74 564 int i = 0;
e2cb1dec
SM		 565 int status;
566 u8 type;
567
568 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
e2cb1dec 569
e2cb1dec 570 for (node = ring_chain; node; node = node->next) {
5d02a58d
YL		 571 int idx_offset = HCLGE_MBX_RING_MAP_BASIC_MSG_NUM +
572 HCLGE_MBX_RING_NODE_VARIABLE_NUM * i;
573
574 if (i == 0) {
575 hclgevf_cmd_setup_basic_desc(&desc,
576 HCLGEVF_OPC_MBX_VF_TO_PF,
577 false);
578 type = en ?
579 HCLGE_MBX_MAP_RING_TO_VECTOR :
580 HCLGE_MBX_UNMAP_RING_TO_VECTOR;
581 req->msg[0] = type;
582 req->msg[1] = vector_id;
583 }
584
585 req->msg[idx_offset] =
e4e87715 586 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B);
5d02a58d 587 req->msg[idx_offset + 1] = node->tqp_index;
e4e87715
PL		 588 req->msg[idx_offset + 2] = hnae3_get_field(node->int_gl_idx,
589 HNAE3_RING_GL_IDX_M,
590 HNAE3_RING_GL_IDX_S);
5d02a58d
YL		 591
592 i++;
593 if ((i == (HCLGE_MBX_VF_MSG_DATA_NUM -
594 HCLGE_MBX_RING_MAP_BASIC_MSG_NUM) /
595 HCLGE_MBX_RING_NODE_VARIABLE_NUM) ||
596 !node->next) {
e2cb1dec
SM		 597 req->msg[2] = i;
598
599 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
600 if (status) {
601 dev_err(&hdev->pdev->dev,
602 "Map TQP fail, status is %d.\n",
603 status);
604 return status;
605 }
606 i = 0;
607 hclgevf_cmd_setup_basic_desc(&desc,
608 HCLGEVF_OPC_MBX_VF_TO_PF,
609 false);
610 req->msg[0] = type;
611 req->msg[1] = vector_id;
612 }
613 }
614
e2cb1dec
SM		 615 return 0;
616}
617
618static int hclgevf_map_ring_to_vector(struct hnae3_handle *handle, int vector,
619 struct hnae3_ring_chain_node *ring_chain)
620{
b204bc74
PL		 621 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
622 int vector_id;
623
624 vector_id = hclgevf_get_vector_index(hdev, vector);
625 if (vector_id < 0) {
626 dev_err(&handle->pdev->dev,
627 "Get vector index fail. ret =%d\n", vector_id);
628 return vector_id;
629 }
630
631 return hclgevf_bind_ring_to_vector(handle, true, vector_id, ring_chain);
e2cb1dec
SM		 632}
633
634static int hclgevf_unmap_ring_from_vector(
635 struct hnae3_handle *handle,
636 int vector,
637 struct hnae3_ring_chain_node *ring_chain)
638{
639 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
640 int ret, vector_id;
641
642 vector_id = hclgevf_get_vector_index(hdev, vector);
643 if (vector_id < 0) {
644 dev_err(&handle->pdev->dev,
645 "Get vector index fail. ret =%d\n", vector_id);
646 return vector_id;
647 }
648
b204bc74 649 ret = hclgevf_bind_ring_to_vector(handle, false, vector_id, ring_chain);
0d3e6631 650 if (ret)
e2cb1dec
SM		 651 dev_err(&handle->pdev->dev,
652 "Unmap ring from vector fail. vector=%d, ret =%d\n",
653 vector_id,
654 ret);
0d3e6631
YL		 655
656 return ret;
657}
658
659static int hclgevf_put_vector(struct hnae3_handle *handle, int vector)
660{
661 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
03718db9
YL		 662 int vector_id;
663
664 vector_id = hclgevf_get_vector_index(hdev, vector);
665 if (vector_id < 0) {
666 dev_err(&handle->pdev->dev,
667 "hclgevf_put_vector get vector index fail. ret =%d\n",
668 vector_id);
669 return vector_id;
670 }
e2cb1dec 671
03718db9 672 hclgevf_free_vector(hdev, vector_id);
e2cb1dec
SM		 673
674 return 0;
675}
676
3b75c3df
PL		 677static int hclgevf_cmd_set_promisc_mode(struct hclgevf_dev *hdev,
678 bool en_uc_pmc, bool en_mc_pmc)
e2cb1dec
SM		 679{
680 struct hclge_mbx_vf_to_pf_cmd *req;
681 struct hclgevf_desc desc;
682 int status;
683
684 req = (struct hclge_mbx_vf_to_pf_cmd *)desc.data;
685
686 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_MBX_VF_TO_PF, false);
687 req->msg[0] = HCLGE_MBX_SET_PROMISC_MODE;
3b75c3df
PL		 688 req->msg[1] = en_uc_pmc ? 1 : 0;
689 req->msg[2] = en_mc_pmc ? 1 : 0;
e2cb1dec
SM		 690
691 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
692 if (status)
693 dev_err(&hdev->pdev->dev,
694 "Set promisc mode fail, status is %d.\n", status);
695
696 return status;
697}
698
3b75c3df
PL		 699static void hclgevf_set_promisc_mode(struct hnae3_handle *handle,
700 bool en_uc_pmc, bool en_mc_pmc)
e2cb1dec
SM		 701{
702 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
703
3b75c3df 704 hclgevf_cmd_set_promisc_mode(hdev, en_uc_pmc, en_mc_pmc);
e2cb1dec
SM		 705}
706
707static int hclgevf_tqp_enable(struct hclgevf_dev *hdev, int tqp_id,
708 int stream_id, bool enable)
709{
710 struct hclgevf_cfg_com_tqp_queue_cmd *req;
711 struct hclgevf_desc desc;
712 int status;
713
714 req = (struct hclgevf_cfg_com_tqp_queue_cmd *)desc.data;
715
716 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_CFG_COM_TQP_QUEUE,
717 false);
718 req->tqp_id = cpu_to_le16(tqp_id & HCLGEVF_RING_ID_MASK);
719 req->stream_id = cpu_to_le16(stream_id);
720 req->enable |= enable << HCLGEVF_TQP_ENABLE_B;
721
722 status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
723 if (status)
724 dev_err(&hdev->pdev->dev,
725 "TQP enable fail, status =%d.\n", status);
726
727 return status;
728}
729
730static int hclgevf_get_queue_id(struct hnae3_queue *queue)
731{
732 struct hclgevf_tqp *tqp = container_of(queue, struct hclgevf_tqp, q);
733
734 return tqp->index;
735}
736
737static void hclgevf_reset_tqp_stats(struct hnae3_handle *handle)
738{
b4f1d303 739 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
e2cb1dec
SM		 740 struct hclgevf_tqp *tqp;
741 int i;
742
b4f1d303
JS		 743 for (i = 0; i < kinfo->num_tqps; i++) {
744 tqp = container_of(kinfo->tqp[i], struct hclgevf_tqp, q);
e2cb1dec
SM		 745 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
746 }
747}
748
3a678b58
XW		 749static int hclgevf_cfg_func_mta_type(struct hclgevf_dev *hdev)
750{
751 u8 resp_msg = HCLGEVF_MTA_TYPE_SEL_MAX;
752 int ret;
753
754 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
755 HCLGE_MBX_MAC_VLAN_MTA_TYPE_READ,
756 NULL, 0, true, &resp_msg, sizeof(u8));
757
758 if (ret) {
759 dev_err(&hdev->pdev->dev,
760 "Read mta type fail, ret=%d.\n", ret);
761 return ret;
762 }
763
764 if (resp_msg > HCLGEVF_MTA_TYPE_SEL_MAX) {
765 dev_err(&hdev->pdev->dev,
766 "Read mta type invalid, resp=%d.\n", resp_msg);
767 return -EINVAL;
768 }
769
770 hdev->mta_mac_sel_type = resp_msg;
771
772 return 0;
773}
774
775static u16 hclgevf_get_mac_addr_to_mta_index(struct hclgevf_dev *hdev,
776 const u8 *addr)
777{
778 u32 rsh = HCLGEVF_MTA_TYPE_SEL_MAX - hdev->mta_mac_sel_type;
779 u16 high_val = addr[1] | (addr[0] << 8);
780
781 return (high_val >> rsh) & 0xfff;
782}
783
784static int hclgevf_do_update_mta_status(struct hclgevf_dev *hdev,
785 unsigned long *status)
786{
787#define HCLGEVF_MTA_STATUS_MSG_SIZE 13
788#define HCLGEVF_MTA_STATUS_MSG_BITS \
789 (HCLGEVF_MTA_STATUS_MSG_SIZE * BITS_PER_BYTE)
790#define HCLGEVF_MTA_STATUS_MSG_END_BITS \
791 (HCLGEVF_MTA_TBL_SIZE % HCLGEVF_MTA_STATUS_MSG_BITS)
792 u16 tbl_cnt;
793 u16 tbl_idx;
794 u8 msg_cnt;
795 u8 msg_idx;
796 int ret;
797
798 msg_cnt = DIV_ROUND_UP(HCLGEVF_MTA_TBL_SIZE,
799 HCLGEVF_MTA_STATUS_MSG_BITS);
800 tbl_idx = 0;
801 msg_idx = 0;
802 while (msg_cnt--) {
803 u8 msg[HCLGEVF_MTA_STATUS_MSG_SIZE + 1];
804 u8 *p = &msg[1];
805 u8 msg_ofs;
806 u8 msg_bit;
807
808 memset(msg, 0, sizeof(msg));
809
810 /* set index field */
811 msg[0] = 0x7F & msg_idx;
812
813 /* set end flag field */
814 if (msg_cnt == 0) {
815 msg[0] |= 0x80;
816 tbl_cnt = HCLGEVF_MTA_STATUS_MSG_END_BITS;
817 } else {
818 tbl_cnt = HCLGEVF_MTA_STATUS_MSG_BITS;
819 }
820
821 /* set status field */
822 msg_ofs = 0;
823 msg_bit = 0;
824 while (tbl_cnt--) {
825 if (test_bit(tbl_idx, status))
826 p[msg_ofs] |= BIT(msg_bit);
827
828 tbl_idx++;
829
830 msg_bit++;
831 if (msg_bit == BITS_PER_BYTE) {
832 msg_bit = 0;
833 msg_ofs++;
834 }
835 }
836
837 ret = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
838 HCLGE_MBX_MAC_VLAN_MTA_STATUS_UPDATE,
839 msg, sizeof(msg), false, NULL, 0);
840 if (ret)
841 break;
842
843 msg_idx++;
844 }
845
846 return ret;
847}
848
849static int hclgevf_update_mta_status(struct hnae3_handle *handle)
850{
851 unsigned long mta_status[BITS_TO_LONGS(HCLGEVF_MTA_TBL_SIZE)];
852 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
853 struct net_device *netdev = hdev->nic.kinfo.netdev;
854 struct netdev_hw_addr *ha;
855 u16 tbl_idx;
856
857 /* clear status */
858 memset(mta_status, 0, sizeof(mta_status));
859
860 /* update status from mc addr list */
861 netdev_for_each_mc_addr(ha, netdev) {
862 tbl_idx = hclgevf_get_mac_addr_to_mta_index(hdev, ha->addr);
863 set_bit(tbl_idx, mta_status);
864 }
865
866 return hclgevf_do_update_mta_status(hdev, mta_status);
867}
868
e2cb1dec
SM		 869static void hclgevf_get_mac_addr(struct hnae3_handle *handle, u8 *p)
870{
871 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
872
873 ether_addr_copy(p, hdev->hw.mac.mac_addr);
874}
875
59098055
FL		 876static int hclgevf_set_mac_addr(struct hnae3_handle *handle, void *p,
877 bool is_first)
e2cb1dec
SM		 878{
879 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
880 u8 *old_mac_addr = (u8 *)hdev->hw.mac.mac_addr;
881 u8 *new_mac_addr = (u8 *)p;
882 u8 msg_data[ETH_ALEN * 2];
59098055 883 u16 subcode;
e2cb1dec
SM		 884 int status;
885
886 ether_addr_copy(msg_data, new_mac_addr);
887 ether_addr_copy(&msg_data[ETH_ALEN], old_mac_addr);
888
59098055
FL		 889 subcode = is_first ? HCLGE_MBX_MAC_VLAN_UC_ADD :
890 HCLGE_MBX_MAC_VLAN_UC_MODIFY;
891
e2cb1dec 892 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
59098055 893 subcode, msg_data, ETH_ALEN * 2,
2097fdef 894 true, NULL, 0);
e2cb1dec
SM		 895 if (!status)
896 ether_addr_copy(hdev->hw.mac.mac_addr, new_mac_addr);
897
898 return status;
899}
900
901static int hclgevf_add_uc_addr(struct hnae3_handle *handle,
902 const unsigned char *addr)
903{
904 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
905
906 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
907 HCLGE_MBX_MAC_VLAN_UC_ADD,
908 addr, ETH_ALEN, false, NULL, 0);
909}
910
911static int hclgevf_rm_uc_addr(struct hnae3_handle *handle,
912 const unsigned char *addr)
913{
914 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
915
916 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_UNICAST,
917 HCLGE_MBX_MAC_VLAN_UC_REMOVE,
918 addr, ETH_ALEN, false, NULL, 0);
919}
920
921static int hclgevf_add_mc_addr(struct hnae3_handle *handle,
922 const unsigned char *addr)
923{
924 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
925
926 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
927 HCLGE_MBX_MAC_VLAN_MC_ADD,
928 addr, ETH_ALEN, false, NULL, 0);
929}
930
931static int hclgevf_rm_mc_addr(struct hnae3_handle *handle,
932 const unsigned char *addr)
933{
934 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
935
936 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_MULTICAST,
937 HCLGE_MBX_MAC_VLAN_MC_REMOVE,
938 addr, ETH_ALEN, false, NULL, 0);
939}
940
941static int hclgevf_set_vlan_filter(struct hnae3_handle *handle,
942 __be16 proto, u16 vlan_id,
943 bool is_kill)
944{
945#define HCLGEVF_VLAN_MBX_MSG_LEN 5
946 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
947 u8 msg_data[HCLGEVF_VLAN_MBX_MSG_LEN];
948
949 if (vlan_id > 4095)
950 return -EINVAL;
951
952 if (proto != htons(ETH_P_8021Q))
953 return -EPROTONOSUPPORT;
954
955 msg_data[0] = is_kill;
956 memcpy(&msg_data[1], &vlan_id, sizeof(vlan_id));
957 memcpy(&msg_data[3], &proto, sizeof(proto));
958 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
959 HCLGE_MBX_VLAN_FILTER, msg_data,
960 HCLGEVF_VLAN_MBX_MSG_LEN, false, NULL, 0);
961}
962
b2641e2a
YL		 963static int hclgevf_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
964{
965 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
966 u8 msg_data;
967
968 msg_data = enable ? 1 : 0;
969 return hclgevf_send_mbx_msg(hdev, HCLGE_MBX_SET_VLAN,
970 HCLGE_MBX_VLAN_RX_OFF_CFG, &msg_data,
971 1, false, NULL, 0);
972}
973
e2cb1dec
SM		 974static void hclgevf_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
975{
976 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
977 u8 msg_data[2];
1a426f8b 978 int ret;
e2cb1dec
SM		 979
980 memcpy(&msg_data[0], &queue_id, sizeof(queue_id));
981
1a426f8b
PL		 982 /* disable vf queue before send queue reset msg to PF */
983 ret = hclgevf_tqp_enable(hdev, queue_id, 0, false);
984 if (ret)
985 return;
986
987 hclgevf_send_mbx_msg(hdev, HCLGE_MBX_QUEUE_RESET, 0, msg_data,
988 2, true, NULL, 0);
e2cb1dec
SM		 989}
990
6988eb2a
SM		 991static int hclgevf_notify_client(struct hclgevf_dev *hdev,
992 enum hnae3_reset_notify_type type)
993{
994 struct hnae3_client *client = hdev->nic_client;
995 struct hnae3_handle *handle = &hdev->nic;
996
997 if (!client->ops->reset_notify)
998 return -EOPNOTSUPP;
999
1000 return client->ops->reset_notify(handle, type);
1001}
1002
1003static int hclgevf_reset_wait(struct hclgevf_dev *hdev)
1004{
1005#define HCLGEVF_RESET_WAIT_MS 500
1006#define HCLGEVF_RESET_WAIT_CNT 20
1007 u32 val, cnt = 0;
1008
1009 /* wait to check the hardware reset completion status */
1010 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING);
e4e87715
PL		 1011 while (hnae3_get_bit(val, HCLGEVF_FUN_RST_ING_B) &&
1012 (cnt < HCLGEVF_RESET_WAIT_CNT)) {
6988eb2a
SM		 1013 msleep(HCLGEVF_RESET_WAIT_MS);
1014 val = hclgevf_read_dev(&hdev->hw, HCLGEVF_FUN_RST_ING);
1015 cnt++;
1016 }
1017
1018 /* hardware completion status should be available by this time */
1019 if (cnt >= HCLGEVF_RESET_WAIT_CNT) {
1020 dev_warn(&hdev->pdev->dev,
1021 "could'nt get reset done status from h/w, timeout!\n");
1022 return -EBUSY;
1023 }
1024
1025 /* we will wait a bit more to let reset of the stack to complete. This
1026 * might happen in case reset assertion was made by PF. Yes, this also
1027 * means we might end up waiting bit more even for VF reset.
1028 */
1029 msleep(5000);
1030
1031 return 0;
1032}
1033
1034static int hclgevf_reset_stack(struct hclgevf_dev *hdev)
1035{
7a01c897
SM		 1036 int ret;
1037
6988eb2a
SM		 1038 /* uninitialize the nic client */
1039 hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1040
7a01c897
SM		 1041 /* re-initialize the hclge device */
1042 ret = hclgevf_init_hdev(hdev);
1043 if (ret) {
1044 dev_err(&hdev->pdev->dev,
1045 "hclge device re-init failed, VF is disabled!\n");
1046 return ret;
1047 }
6988eb2a
SM		 1048
1049 /* bring up the nic client again */
1050 hclgevf_notify_client(hdev, HNAE3_INIT_CLIENT);
1051
1052 return 0;
1053}
1054
1055static int hclgevf_reset(struct hclgevf_dev *hdev)
1056{
1057 int ret;
1058
1059 rtnl_lock();
1060
1061 /* bring down the nic to stop any ongoing TX/RX */
1062 hclgevf_notify_client(hdev, HNAE3_DOWN_CLIENT);
1063
1064 /* check if VF could successfully fetch the hardware reset completion
1065 * status from the hardware
1066 */
1067 ret = hclgevf_reset_wait(hdev);
1068 if (ret) {
1069 /* can't do much in this situation, will disable VF */
1070 dev_err(&hdev->pdev->dev,
1071 "VF failed(=%d) to fetch H/W reset completion status\n",
1072 ret);
1073
1074 dev_warn(&hdev->pdev->dev, "VF reset failed, disabling VF!\n");
1075 hclgevf_notify_client(hdev, HNAE3_UNINIT_CLIENT);
1076
1077 rtnl_unlock();
1078 return ret;
1079 }
1080
1081 /* now, re-initialize the nic client and ae device*/
1082 ret = hclgevf_reset_stack(hdev);
1083 if (ret)
1084 dev_err(&hdev->pdev->dev, "failed to reset VF stack\n");
1085
1086 /* bring up the nic to enable TX/RX again */
1087 hclgevf_notify_client(hdev, HNAE3_UP_CLIENT);
1088
1089 rtnl_unlock();
1090
1091 return ret;
1092}
1093
a8dedb65
SM		 1094static int hclgevf_do_reset(struct hclgevf_dev *hdev)
1095{
1096 int status;
1097 u8 respmsg;
1098
1099 status = hclgevf_send_mbx_msg(hdev, HCLGE_MBX_RESET, 0, NULL,
1100 0, false, &respmsg, sizeof(u8));
1101 if (status)
1102 dev_err(&hdev->pdev->dev,
1103 "VF reset request to PF failed(=%d)\n", status);
1104
1105 return status;
1106}
1107
6d4c3981
SM		 1108static void hclgevf_reset_event(struct hnae3_handle *handle)
1109{
1110 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1111
1112 dev_info(&hdev->pdev->dev, "received reset request from VF enet\n");
1113
1114 handle->reset_level = HNAE3_VF_RESET;
1115
436667d2
SM		 1116 /* reset of this VF requested */
1117 set_bit(HCLGEVF_RESET_REQUESTED, &hdev->reset_state);
1118 hclgevf_reset_task_schedule(hdev);
6d4c3981
SM		 1119
1120 handle->last_reset_time = jiffies;
1121}
1122
e2cb1dec
SM		 1123static u32 hclgevf_get_fw_version(struct hnae3_handle *handle)
1124{
1125 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1126
1127 return hdev->fw_version;
1128}
1129
1130static void hclgevf_get_misc_vector(struct hclgevf_dev *hdev)
1131{
1132 struct hclgevf_misc_vector *vector = &hdev->misc_vector;
1133
1134 vector->vector_irq = pci_irq_vector(hdev->pdev,
1135 HCLGEVF_MISC_VECTOR_NUM);
1136 vector->addr = hdev->hw.io_base + HCLGEVF_MISC_VECTOR_REG_BASE;
1137 /* vector status always valid for Vector 0 */
1138 hdev->vector_status[HCLGEVF_MISC_VECTOR_NUM] = 0;
1139 hdev->vector_irq[HCLGEVF_MISC_VECTOR_NUM] = vector->vector_irq;
1140
1141 hdev->num_msi_left -= 1;
1142 hdev->num_msi_used += 1;
1143}
1144
35a1e503
SM		 1145void hclgevf_reset_task_schedule(struct hclgevf_dev *hdev)
1146{
1147 if (!test_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state) &&
1148 !test_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state)) {
1149 set_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1150 schedule_work(&hdev->rst_service_task);
1151 }
1152}
1153
07a0556a 1154void hclgevf_mbx_task_schedule(struct hclgevf_dev *hdev)
e2cb1dec 1155{
07a0556a
SM		 1156 if (!test_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state) &&
1157 !test_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state)) {
1158 set_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
e2cb1dec 1159 schedule_work(&hdev->mbx_service_task);
07a0556a 1160 }
e2cb1dec
SM		 1161}
1162
1163static void hclgevf_task_schedule(struct hclgevf_dev *hdev)
1164{
1165 if (!test_bit(HCLGEVF_STATE_DOWN, &hdev->state) &&
1166 !test_and_set_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state))
1167 schedule_work(&hdev->service_task);
1168}
1169
436667d2
SM		 1170static void hclgevf_deferred_task_schedule(struct hclgevf_dev *hdev)
1171{
07a0556a
SM		 1172 /* if we have any pending mailbox event then schedule the mbx task */
1173 if (hdev->mbx_event_pending)
1174 hclgevf_mbx_task_schedule(hdev);
1175
436667d2
SM		 1176 if (test_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state))
1177 hclgevf_reset_task_schedule(hdev);
1178}
1179
e2cb1dec
SM		 1180static void hclgevf_service_timer(struct timer_list *t)
1181{
1182 struct hclgevf_dev *hdev = from_timer(hdev, t, service_timer);
1183
1184 mod_timer(&hdev->service_timer, jiffies + 5 * HZ);
1185
1186 hclgevf_task_schedule(hdev);
1187}
1188
35a1e503
SM		 1189static void hclgevf_reset_service_task(struct work_struct *work)
1190{
1191 struct hclgevf_dev *hdev =
1192 container_of(work, struct hclgevf_dev, rst_service_task);
a8dedb65 1193 int ret;
35a1e503
SM		 1194
1195 if (test_and_set_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state))
1196 return;
1197
1198 clear_bit(HCLGEVF_STATE_RST_SERVICE_SCHED, &hdev->state);
1199
436667d2
SM		 1200 if (test_and_clear_bit(HCLGEVF_RESET_PENDING,
1201 &hdev->reset_state)) {
1202 /* PF has initmated that it is about to reset the hardware.
1203 * We now have to poll & check if harware has actually completed
1204 * the reset sequence. On hardware reset completion, VF needs to
1205 * reset the client and ae device.
1206 */
1207 hdev->reset_attempts = 0;
1208
6988eb2a
SM		 1209 ret = hclgevf_reset(hdev);
1210 if (ret)
1211 dev_err(&hdev->pdev->dev, "VF stack reset failed.\n");
436667d2
SM		 1212 } else if (test_and_clear_bit(HCLGEVF_RESET_REQUESTED,
1213 &hdev->reset_state)) {
1214 /* we could be here when either of below happens:
1215 * 1. reset was initiated due to watchdog timeout due to
1216 * a. IMP was earlier reset and our TX got choked down and
1217 * which resulted in watchdog reacting and inducing VF
1218 * reset. This also means our cmdq would be unreliable.
1219 * b. problem in TX due to other lower layer(example link
1220 * layer not functioning properly etc.)
1221 * 2. VF reset might have been initiated due to some config
1222 * change.
1223 *
1224 * NOTE: Theres no clear way to detect above cases than to react
1225 * to the response of PF for this reset request. PF will ack the
1226 * 1b and 2. cases but we will not get any intimation about 1a
1227 * from PF as cmdq would be in unreliable state i.e. mailbox
1228 * communication between PF and VF would be broken.
1229 */
1230
1231 /* if we are never geting into pending state it means either:
1232 * 1. PF is not receiving our request which could be due to IMP
1233 * reset
1234 * 2. PF is screwed
1235 * We cannot do much for 2. but to check first we can try reset
1236 * our PCIe + stack and see if it alleviates the problem.
1237 */
1238 if (hdev->reset_attempts > 3) {
1239 /* prepare for full reset of stack + pcie interface */
1240 hdev->nic.reset_level = HNAE3_VF_FULL_RESET;
1241
1242 /* "defer" schedule the reset task again */
1243 set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
1244 } else {
1245 hdev->reset_attempts++;
1246
1247 /* request PF for resetting this VF via mailbox */
a8dedb65
SM		 1248 ret = hclgevf_do_reset(hdev);
1249 if (ret)
1250 dev_warn(&hdev->pdev->dev,
1251 "VF rst fail, stack will call\n");
436667d2
SM		 1252 }
1253 }
35a1e503
SM		 1254
1255 clear_bit(HCLGEVF_STATE_RST_HANDLING, &hdev->state);
1256}
1257
e2cb1dec
SM		 1258static void hclgevf_mailbox_service_task(struct work_struct *work)
1259{
1260 struct hclgevf_dev *hdev;
1261
1262 hdev = container_of(work, struct hclgevf_dev, mbx_service_task);
1263
1264 if (test_and_set_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state))
1265 return;
1266
1267 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1268
07a0556a 1269 hclgevf_mbx_async_handler(hdev);
e2cb1dec
SM		 1270
1271 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1272}
1273
1274static void hclgevf_service_task(struct work_struct *work)
1275{
1276 struct hclgevf_dev *hdev;
1277
1278 hdev = container_of(work, struct hclgevf_dev, service_task);
1279
1280 /* request the link status from the PF. PF would be able to tell VF
1281 * about such updates in future so we might remove this later
1282 */
1283 hclgevf_request_link_info(hdev);
1284
436667d2
SM		 1285 hclgevf_deferred_task_schedule(hdev);
1286
e2cb1dec
SM		 1287 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1288}
1289
1290static void hclgevf_clear_event_cause(struct hclgevf_dev *hdev, u32 regclr)
1291{
1292 hclgevf_write_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_SRC_REG, regclr);
1293}
1294
1295static bool hclgevf_check_event_cause(struct hclgevf_dev *hdev, u32 *clearval)
1296{
1297 u32 cmdq_src_reg;
1298
1299 /* fetch the events from their corresponding regs */
1300 cmdq_src_reg = hclgevf_read_dev(&hdev->hw,
1301 HCLGEVF_VECTOR0_CMDQ_SRC_REG);
1302
1303 /* check for vector0 mailbox(=CMDQ RX) event source */
1304 if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
1305 cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
1306 *clearval = cmdq_src_reg;
1307 return true;
1308 }
1309
1310 dev_dbg(&hdev->pdev->dev, "vector 0 interrupt from unknown source\n");
1311
1312 return false;
1313}
1314
1315static void hclgevf_enable_vector(struct hclgevf_misc_vector *vector, bool en)
1316{
1317 writel(en ? 1 : 0, vector->addr);
1318}
1319
1320static irqreturn_t hclgevf_misc_irq_handle(int irq, void *data)
1321{
1322 struct hclgevf_dev *hdev = data;
1323 u32 clearval;
1324
1325 hclgevf_enable_vector(&hdev->misc_vector, false);
1326 if (!hclgevf_check_event_cause(hdev, &clearval))
1327 goto skip_sched;
1328
07a0556a 1329 hclgevf_mbx_handler(hdev);
e2cb1dec
SM		 1330
1331 hclgevf_clear_event_cause(hdev, clearval);
1332
1333skip_sched:
1334 hclgevf_enable_vector(&hdev->misc_vector, true);
1335
1336 return IRQ_HANDLED;
1337}
1338
1339static int hclgevf_configure(struct hclgevf_dev *hdev)
1340{
1341 int ret;
1342
c136b884
PL		 1343 hdev->hw.mac.media_type = HNAE3_MEDIA_TYPE_NONE;
1344
e2cb1dec 1345 /* get queue configuration from PF */
6cee6fc3 1346 ret = hclgevf_get_queue_info(hdev);
e2cb1dec
SM		 1347 if (ret)
1348 return ret;
1349 /* get tc configuration from PF */
1350 return hclgevf_get_tc_info(hdev);
1351}
1352
7a01c897
SM		 1353static int hclgevf_alloc_hdev(struct hnae3_ae_dev *ae_dev)
1354{
1355 struct pci_dev *pdev = ae_dev->pdev;
1356 struct hclgevf_dev *hdev = ae_dev->priv;
1357
1358 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
1359 if (!hdev)
1360 return -ENOMEM;
1361
1362 hdev->pdev = pdev;
1363 hdev->ae_dev = ae_dev;
1364 ae_dev->priv = hdev;
1365
1366 return 0;
1367}
1368
e2cb1dec
SM		 1369static int hclgevf_init_roce_base_info(struct hclgevf_dev *hdev)
1370{
1371 struct hnae3_handle *roce = &hdev->roce;
1372 struct hnae3_handle *nic = &hdev->nic;
1373
07acf909 1374 roce->rinfo.num_vectors = hdev->num_roce_msix;
e2cb1dec
SM		 1375
1376 if (hdev->num_msi_left < roce->rinfo.num_vectors ||
1377 hdev->num_msi_left == 0)
1378 return -EINVAL;
1379
07acf909 1380 roce->rinfo.base_vector = hdev->roce_base_vector;
e2cb1dec
SM		 1381
1382 roce->rinfo.netdev = nic->kinfo.netdev;
1383 roce->rinfo.roce_io_base = hdev->hw.io_base;
1384
1385 roce->pdev = nic->pdev;
1386 roce->ae_algo = nic->ae_algo;
1387 roce->numa_node_mask = nic->numa_node_mask;
1388
1389 return 0;
1390}
1391
1392static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
1393{
1394 struct hclgevf_rss_cfg *rss_cfg = &hdev->rss_cfg;
1395 int i, ret;
1396
1397 rss_cfg->rss_size = hdev->rss_size_max;
1398
1399 /* Initialize RSS indirect table for each vport */
1400 for (i = 0; i < HCLGEVF_RSS_IND_TBL_SIZE; i++)
1401 rss_cfg->rss_indirection_tbl[i] = i % hdev->rss_size_max;
1402
1403 ret = hclgevf_set_rss_indir_table(hdev);
1404 if (ret)
1405 return ret;
1406
1407 return hclgevf_set_rss_tc_mode(hdev, hdev->rss_size_max);
1408}
1409
1410static int hclgevf_init_vlan_config(struct hclgevf_dev *hdev)
1411{
1412 /* other vlan config(like, VLAN TX/RX offload) would also be added
1413 * here later
1414 */
1415 return hclgevf_set_vlan_filter(&hdev->nic, htons(ETH_P_8021Q), 0,
1416 false);
1417}
1418
1419static int hclgevf_ae_start(struct hnae3_handle *handle)
1420{
b4f1d303 1421 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
e2cb1dec
SM		 1422 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1423 int i, queue_id;
1424
b4f1d303 1425 for (i = 0; i < kinfo->num_tqps; i++) {
e2cb1dec 1426 /* ring enable */
b4f1d303 1427 queue_id = hclgevf_get_queue_id(kinfo->tqp[i]);
e2cb1dec
SM		 1428 if (queue_id < 0) {
1429 dev_warn(&hdev->pdev->dev,
1430 "Get invalid queue id, ignore it\n");
1431 continue;
1432 }
1433
1434 hclgevf_tqp_enable(hdev, queue_id, 0, true);
1435 }
1436
1437 /* reset tqp stats */
1438 hclgevf_reset_tqp_stats(handle);
1439
1440 hclgevf_request_link_info(hdev);
1441
1442 clear_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1443 mod_timer(&hdev->service_timer, jiffies + HZ);
1444
1445 return 0;
1446}
1447
1448static void hclgevf_ae_stop(struct hnae3_handle *handle)
1449{
b4f1d303 1450 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
e2cb1dec
SM		 1451 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1452 int i, queue_id;
1453
2f7e4896
FL		 1454 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1455
b4f1d303 1456 for (i = 0; i < kinfo->num_tqps; i++) {
e2cb1dec 1457 /* Ring disable */
b4f1d303 1458 queue_id = hclgevf_get_queue_id(kinfo->tqp[i]);
e2cb1dec
SM		 1459 if (queue_id < 0) {
1460 dev_warn(&hdev->pdev->dev,
1461 "Get invalid queue id, ignore it\n");
1462 continue;
1463 }
1464
1465 hclgevf_tqp_enable(hdev, queue_id, 0, false);
1466 }
1467
1468 /* reset tqp stats */
1469 hclgevf_reset_tqp_stats(handle);
8cc6c1f7
FL		 1470 del_timer_sync(&hdev->service_timer);
1471 cancel_work_sync(&hdev->service_task);
f5be7967 1472 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
8cc6c1f7 1473 hclgevf_update_link_status(hdev, 0);
e2cb1dec
SM		 1474}
1475
1476static void hclgevf_state_init(struct hclgevf_dev *hdev)
1477{
7a01c897
SM		 1478 /* if this is on going reset then skip this initialization */
1479 if (hclgevf_dev_ongoing_reset(hdev))
1480 return;
1481
e2cb1dec
SM		 1482 /* setup tasks for the MBX */
1483 INIT_WORK(&hdev->mbx_service_task, hclgevf_mailbox_service_task);
1484 clear_bit(HCLGEVF_STATE_MBX_SERVICE_SCHED, &hdev->state);
1485 clear_bit(HCLGEVF_STATE_MBX_HANDLING, &hdev->state);
1486
1487 /* setup tasks for service timer */
1488 timer_setup(&hdev->service_timer, hclgevf_service_timer, 0);
1489
1490 INIT_WORK(&hdev->service_task, hclgevf_service_task);
1491 clear_bit(HCLGEVF_STATE_SERVICE_SCHED, &hdev->state);
1492
35a1e503
SM		 1493 INIT_WORK(&hdev->rst_service_task, hclgevf_reset_service_task);
1494
e2cb1dec
SM		 1495 mutex_init(&hdev->mbx_resp.mbx_mutex);
1496
1497 /* bring the device down */
1498 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1499}
1500
1501static void hclgevf_state_uninit(struct hclgevf_dev *hdev)
1502{
1503 set_bit(HCLGEVF_STATE_DOWN, &hdev->state);
1504
1505 if (hdev->service_timer.function)
1506 del_timer_sync(&hdev->service_timer);
1507 if (hdev->service_task.func)
1508 cancel_work_sync(&hdev->service_task);
1509 if (hdev->mbx_service_task.func)
1510 cancel_work_sync(&hdev->mbx_service_task);
35a1e503
SM		 1511 if (hdev->rst_service_task.func)
1512 cancel_work_sync(&hdev->rst_service_task);
e2cb1dec
SM		 1513
1514 mutex_destroy(&hdev->mbx_resp.mbx_mutex);
1515}
1516
1517static int hclgevf_init_msi(struct hclgevf_dev *hdev)
1518{
1519 struct pci_dev *pdev = hdev->pdev;
1520 int vectors;
1521 int i;
1522
7a01c897
SM		 1523 /* if this is on going reset then skip this initialization */
1524 if (hclgevf_dev_ongoing_reset(hdev))
1525 return 0;
1526
07acf909
JS		 1527 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B))
1528 vectors = pci_alloc_irq_vectors(pdev,
1529 hdev->roce_base_msix_offset + 1,
1530 hdev->num_msi,
1531 PCI_IRQ_MSIX);
1532 else
1533 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1534 PCI_IRQ_MSI | PCI_IRQ_MSIX);
e2cb1dec 1535
e2cb1dec
SM		 1536 if (vectors < 0) {
1537 dev_err(&pdev->dev,
1538 "failed(%d) to allocate MSI/MSI-X vectors\n",
1539 vectors);
1540 return vectors;
1541 }
1542 if (vectors < hdev->num_msi)
1543 dev_warn(&hdev->pdev->dev,
1544 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1545 hdev->num_msi, vectors);
1546
1547 hdev->num_msi = vectors;
1548 hdev->num_msi_left = vectors;
1549 hdev->base_msi_vector = pdev->irq;
07acf909 1550 hdev->roce_base_vector = pdev->irq + hdev->roce_base_msix_offset;
e2cb1dec
SM		 1551
1552 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1553 sizeof(u16), GFP_KERNEL);
1554 if (!hdev->vector_status) {
1555 pci_free_irq_vectors(pdev);
1556 return -ENOMEM;
1557 }
1558
1559 for (i = 0; i < hdev->num_msi; i++)
1560 hdev->vector_status[i] = HCLGEVF_INVALID_VPORT;
1561
1562 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1563 sizeof(int), GFP_KERNEL);
1564 if (!hdev->vector_irq) {
1565 pci_free_irq_vectors(pdev);
1566 return -ENOMEM;
1567 }
1568
1569 return 0;
1570}
1571
1572static void hclgevf_uninit_msi(struct hclgevf_dev *hdev)
1573{
1574 struct pci_dev *pdev = hdev->pdev;
1575
1576 pci_free_irq_vectors(pdev);
1577}
1578
1579static int hclgevf_misc_irq_init(struct hclgevf_dev *hdev)
1580{
1581 int ret = 0;
1582
7a01c897
SM		 1583 /* if this is on going reset then skip this initialization */
1584 if (hclgevf_dev_ongoing_reset(hdev))
1585 return 0;
1586
e2cb1dec
SM		 1587 hclgevf_get_misc_vector(hdev);
1588
1589 ret = request_irq(hdev->misc_vector.vector_irq, hclgevf_misc_irq_handle,
1590 0, "hclgevf_cmd", hdev);
1591 if (ret) {
1592 dev_err(&hdev->pdev->dev, "VF failed to request misc irq(%d)\n",
1593 hdev->misc_vector.vector_irq);
1594 return ret;
1595 }
1596
1819e409
XW		 1597 hclgevf_clear_event_cause(hdev, 0);
1598
e2cb1dec
SM		 1599 /* enable misc. vector(vector 0) */
1600 hclgevf_enable_vector(&hdev->misc_vector, true);
1601
1602 return ret;
1603}
1604
1605static void hclgevf_misc_irq_uninit(struct hclgevf_dev *hdev)
1606{
1607 /* disable misc vector(vector 0) */
1608 hclgevf_enable_vector(&hdev->misc_vector, false);
1819e409 1609 synchronize_irq(hdev->misc_vector.vector_irq);
e2cb1dec
SM		 1610 free_irq(hdev->misc_vector.vector_irq, hdev);
1611 hclgevf_free_vector(hdev, 0);
1612}
1613
e718a93f
PL		 1614static int hclgevf_init_client_instance(struct hnae3_client *client,
1615 struct hnae3_ae_dev *ae_dev)
e2cb1dec 1616{
e718a93f 1617 struct hclgevf_dev *hdev = ae_dev->priv;
e2cb1dec
SM		 1618 int ret;
1619
1620 switch (client->type) {
1621 case HNAE3_CLIENT_KNIC:
1622 hdev->nic_client = client;
1623 hdev->nic.client = client;
1624
1625 ret = client->ops->init_instance(&hdev->nic);
1626 if (ret)
49dd8054 1627 goto clear_nic;
e2cb1dec 1628
d9f28fc2
JS		 1629 hnae3_set_client_init_flag(client, ae_dev, 1);
1630
e2cb1dec
SM		 1631 if (hdev->roce_client && hnae3_dev_roce_supported(hdev)) {
1632 struct hnae3_client *rc = hdev->roce_client;
1633
1634 ret = hclgevf_init_roce_base_info(hdev);
1635 if (ret)
49dd8054 1636 goto clear_roce;
e2cb1dec
SM		 1637 ret = rc->ops->init_instance(&hdev->roce);
1638 if (ret)
49dd8054 1639 goto clear_roce;
d9f28fc2
JS		 1640
1641 hnae3_set_client_init_flag(hdev->roce_client, ae_dev,
1642 1);
e2cb1dec
SM		 1643 }
1644 break;
1645 case HNAE3_CLIENT_UNIC:
1646 hdev->nic_client = client;
1647 hdev->nic.client = client;
1648
1649 ret = client->ops->init_instance(&hdev->nic);
1650 if (ret)
49dd8054 1651 goto clear_nic;
d9f28fc2
JS		 1652
1653 hnae3_set_client_init_flag(client, ae_dev, 1);
e2cb1dec
SM		 1654 break;
1655 case HNAE3_CLIENT_ROCE:
544a7bcd
LO		 1656 if (hnae3_dev_roce_supported(hdev)) {
1657 hdev->roce_client = client;
1658 hdev->roce.client = client;
1659 }
e2cb1dec 1660
544a7bcd 1661 if (hdev->roce_client && hdev->nic_client) {
e2cb1dec
SM		 1662 ret = hclgevf_init_roce_base_info(hdev);
1663 if (ret)
49dd8054 1664 goto clear_roce;
e2cb1dec
SM		 1665
1666 ret = client->ops->init_instance(&hdev->roce);
1667 if (ret)
49dd8054 1668 goto clear_roce;
e2cb1dec 1669 }
d9f28fc2
JS		 1670
1671 hnae3_set_client_init_flag(client, ae_dev, 1);
fa7a4bd5
JS		 1672 break;
1673 default:
1674 return -EINVAL;
e2cb1dec
SM		 1675 }
1676
1677 return 0;
49dd8054
JS		 1678
1679clear_nic:
1680 hdev->nic_client = NULL;
1681 hdev->nic.client = NULL;
1682 return ret;
1683clear_roce:
1684 hdev->roce_client = NULL;
1685 hdev->roce.client = NULL;
1686 return ret;
e2cb1dec
SM		 1687}
1688
e718a93f
PL		 1689static void hclgevf_uninit_client_instance(struct hnae3_client *client,
1690 struct hnae3_ae_dev *ae_dev)
e2cb1dec 1691{
e718a93f
PL		 1692 struct hclgevf_dev *hdev = ae_dev->priv;
1693
e2cb1dec 1694 /* un-init roce, if it exists */
49dd8054 1695 if (hdev->roce_client) {
e2cb1dec 1696 hdev->roce_client->ops->uninit_instance(&hdev->roce, 0);
49dd8054
JS		 1697 hdev->roce_client = NULL;
1698 hdev->roce.client = NULL;
1699 }
e2cb1dec
SM		 1700
1701 /* un-init nic/unic, if this was not called by roce client */
49dd8054
JS		 1702 if (client->ops->uninit_instance && hdev->nic_client &&
1703 client->type != HNAE3_CLIENT_ROCE) {
e2cb1dec 1704 client->ops->uninit_instance(&hdev->nic, 0);
49dd8054
JS		 1705 hdev->nic_client = NULL;
1706 hdev->nic.client = NULL;
1707 }
e2cb1dec
SM		 1708}
1709
e2cb1dec
SM		 1710static int hclgevf_pci_init(struct hclgevf_dev *hdev)
1711{
1712 struct pci_dev *pdev = hdev->pdev;
1713 struct hclgevf_hw *hw;
1714 int ret;
1715
7a01c897
SM		 1716 /* check if we need to skip initialization of pci. This will happen if
1717 * device is undergoing VF reset. Otherwise, we would need to
1718 * re-initialize pci interface again i.e. when device is not going
1719 * through *any* reset or actually undergoing full reset.
1720 */
1721 if (hclgevf_dev_ongoing_reset(hdev))
1722 return 0;
1723
e2cb1dec
SM		 1724 ret = pci_enable_device(pdev);
1725 if (ret) {
1726 dev_err(&pdev->dev, "failed to enable PCI device\n");
3e249d3b 1727 return ret;
e2cb1dec
SM		 1728 }
1729
1730 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1731 if (ret) {
1732 dev_err(&pdev->dev, "can't set consistent PCI DMA, exiting");
1733 goto err_disable_device;
1734 }
1735
1736 ret = pci_request_regions(pdev, HCLGEVF_DRIVER_NAME);
1737 if (ret) {
1738 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
1739 goto err_disable_device;
1740 }
1741
1742 pci_set_master(pdev);
1743 hw = &hdev->hw;
1744 hw->hdev = hdev;
2e1ea493 1745 hw->io_base = pci_iomap(pdev, 2, 0);
e2cb1dec
SM		 1746 if (!hw->io_base) {
1747 dev_err(&pdev->dev, "can't map configuration register space\n");
1748 ret = -ENOMEM;
1749 goto err_clr_master;
1750 }
1751
1752 return 0;
1753
1754err_clr_master:
1755 pci_clear_master(pdev);
1756 pci_release_regions(pdev);
1757err_disable_device:
1758 pci_disable_device(pdev);
3e249d3b 1759
e2cb1dec
SM		 1760 return ret;
1761}
1762
1763static void hclgevf_pci_uninit(struct hclgevf_dev *hdev)
1764{
1765 struct pci_dev *pdev = hdev->pdev;
1766
1767 pci_iounmap(pdev, hdev->hw.io_base);
1768 pci_clear_master(pdev);
1769 pci_release_regions(pdev);
1770 pci_disable_device(pdev);
e2cb1dec
SM		 1771}
1772
07acf909
JS		 1773static int hclgevf_query_vf_resource(struct hclgevf_dev *hdev)
1774{
1775 struct hclgevf_query_res_cmd *req;
1776 struct hclgevf_desc desc;
1777 int ret;
1778
1779 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_VF_RSRC, true);
1780 ret = hclgevf_cmd_send(&hdev->hw, &desc, 1);
1781 if (ret) {
1782 dev_err(&hdev->pdev->dev,
1783 "query vf resource failed, ret = %d.\n", ret);
1784 return ret;
1785 }
1786
1787 req = (struct hclgevf_query_res_cmd *)desc.data;
1788
1789 if (hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)) {
1790 hdev->roce_base_msix_offset =
1791 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
1792 HCLGEVF_MSIX_OFT_ROCEE_M,
1793 HCLGEVF_MSIX_OFT_ROCEE_S);
1794 hdev->num_roce_msix =
1795 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
1796 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
1797
1798 /* VF should have NIC vectors and Roce vectors, NIC vectors
1799 * are queued before Roce vectors. The offset is fixed to 64.
1800 */
1801 hdev->num_msi = hdev->num_roce_msix +
1802 hdev->roce_base_msix_offset;
1803 } else {
1804 hdev->num_msi =
1805 hnae3_get_field(__le16_to_cpu(req->vf_intr_vector_number),
1806 HCLGEVF_VEC_NUM_M, HCLGEVF_VEC_NUM_S);
1807 }
1808
1809 return 0;
1810}
1811
7a01c897 1812static int hclgevf_init_hdev(struct hclgevf_dev *hdev)
e2cb1dec 1813{
7a01c897 1814 struct pci_dev *pdev = hdev->pdev;
e2cb1dec
SM		 1815 int ret;
1816
7a01c897
SM		 1817 /* check if device is on-going full reset(i.e. pcie as well) */
1818 if (hclgevf_dev_ongoing_full_reset(hdev)) {
1819 dev_warn(&pdev->dev, "device is going full reset\n");
1820 hclgevf_uninit_hdev(hdev);
1821 }
e2cb1dec
SM		 1822
1823 ret = hclgevf_pci_init(hdev);
1824 if (ret) {
1825 dev_err(&pdev->dev, "PCI initialization failed\n");
1826 return ret;
1827 }
1828
07acf909
JS		 1829 ret = hclgevf_cmd_init(hdev);
1830 if (ret)
1831 goto err_cmd_init;
1832
1833 /* Get vf resource */
1834 ret = hclgevf_query_vf_resource(hdev);
1835 if (ret) {
1836 dev_err(&hdev->pdev->dev,
1837 "Query vf status error, ret = %d.\n", ret);
1838 goto err_query_vf;
1839 }
1840
e2cb1dec
SM		 1841 ret = hclgevf_init_msi(hdev);
1842 if (ret) {
1843 dev_err(&pdev->dev, "failed(%d) to init MSI/MSI-X\n", ret);
07acf909 1844 goto err_query_vf;
e2cb1dec
SM		 1845 }
1846
1847 hclgevf_state_init(hdev);
1848
1849 ret = hclgevf_misc_irq_init(hdev);
1850 if (ret) {
1851 dev_err(&pdev->dev, "failed(%d) to init Misc IRQ(vector0)\n",
1852 ret);
1853 goto err_misc_irq_init;
1854 }
1855
e2cb1dec
SM		 1856 ret = hclgevf_configure(hdev);
1857 if (ret) {
1858 dev_err(&pdev->dev, "failed(%d) to fetch configuration\n", ret);
1859 goto err_config;
1860 }
1861
1862 ret = hclgevf_alloc_tqps(hdev);
1863 if (ret) {
1864 dev_err(&pdev->dev, "failed(%d) to allocate TQPs\n", ret);
1865 goto err_config;
1866 }
1867
1868 ret = hclgevf_set_handle_info(hdev);
1869 if (ret) {
1870 dev_err(&pdev->dev, "failed(%d) to set handle info\n", ret);
1871 goto err_config;
1872 }
1873
3a678b58
XW		 1874 /* Initialize mta type for this VF */
1875 ret = hclgevf_cfg_func_mta_type(hdev);
e2cb1dec
SM		 1876 if (ret) {
1877 dev_err(&hdev->pdev->dev,
3a678b58 1878 "failed(%d) to initialize MTA type\n", ret);
e2cb1dec
SM		 1879 goto err_config;
1880 }
1881
1882 /* Initialize RSS for this VF */
1883 ret = hclgevf_rss_init_hw(hdev);
1884 if (ret) {
1885 dev_err(&hdev->pdev->dev,
1886 "failed(%d) to initialize RSS\n", ret);
1887 goto err_config;
1888 }
1889
1890 ret = hclgevf_init_vlan_config(hdev);
1891 if (ret) {
1892 dev_err(&hdev->pdev->dev,
1893 "failed(%d) to initialize VLAN config\n", ret);
1894 goto err_config;
1895 }
1896
1897 pr_info("finished initializing %s driver\n", HCLGEVF_DRIVER_NAME);
1898
1899 return 0;
1900
1901err_config:
e2cb1dec
SM		 1902 hclgevf_misc_irq_uninit(hdev);
1903err_misc_irq_init:
1904 hclgevf_state_uninit(hdev);
1905 hclgevf_uninit_msi(hdev);
07acf909
JS		 1906err_query_vf:
1907 hclgevf_cmd_uninit(hdev);
1908err_cmd_init:
e2cb1dec
SM		 1909 hclgevf_pci_uninit(hdev);
1910 return ret;
1911}
1912
7a01c897 1913static void hclgevf_uninit_hdev(struct hclgevf_dev *hdev)
e2cb1dec 1914{
e2cb1dec 1915 hclgevf_state_uninit(hdev);
eddf0462
YL		 1916 hclgevf_misc_irq_uninit(hdev);
1917 hclgevf_cmd_uninit(hdev);
e2cb1dec
SM		 1918 hclgevf_uninit_msi(hdev);
1919 hclgevf_pci_uninit(hdev);
7a01c897
SM		 1920}
1921
1922static int hclgevf_init_ae_dev(struct hnae3_ae_dev *ae_dev)
1923{
1924 struct pci_dev *pdev = ae_dev->pdev;
1925 int ret;
1926
1927 ret = hclgevf_alloc_hdev(ae_dev);
1928 if (ret) {
1929 dev_err(&pdev->dev, "hclge device allocation failed\n");
1930 return ret;
1931 }
1932
1933 ret = hclgevf_init_hdev(ae_dev->priv);
1934 if (ret)
1935 dev_err(&pdev->dev, "hclge device initialization failed\n");
1936
1937 return ret;
1938}
1939
1940static void hclgevf_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
1941{
1942 struct hclgevf_dev *hdev = ae_dev->priv;
1943
1944 hclgevf_uninit_hdev(hdev);
e2cb1dec
SM		 1945 ae_dev->priv = NULL;
1946}
1947
849e4607
PL		 1948static u32 hclgevf_get_max_channels(struct hclgevf_dev *hdev)
1949{
1950 struct hnae3_handle *nic = &hdev->nic;
1951 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1952
1953 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
1954}
1955
1956/**
1957 * hclgevf_get_channels - Get the current channels enabled and max supported.
1958 * @handle: hardware information for network interface
1959 * @ch: ethtool channels structure
1960 *
1961 * We don't support separate tx and rx queues as channels. The other count
1962 * represents how many queues are being used for control. max_combined counts
1963 * how many queue pairs we can support. They may not be mapped 1 to 1 with
1964 * q_vectors since we support a lot more queue pairs than q_vectors.
1965 **/
1966static void hclgevf_get_channels(struct hnae3_handle *handle,
1967 struct ethtool_channels *ch)
1968{
1969 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1970
1971 ch->max_combined = hclgevf_get_max_channels(hdev);
1972 ch->other_count = 0;
1973 ch->max_other = 0;
1974 ch->combined_count = hdev->num_tqps;
1975}
1976
cc719218 1977static void hclgevf_get_tqps_and_rss_info(struct hnae3_handle *handle,
0d43bf45 1978 u16 *alloc_tqps, u16 *max_rss_size)
cc719218
PL		 1979{
1980 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1981
0d43bf45 1982 *alloc_tqps = hdev->num_tqps;
cc719218
PL		 1983 *max_rss_size = hdev->rss_size_max;
1984}
1985
175ec96b
FL		 1986static int hclgevf_get_status(struct hnae3_handle *handle)
1987{
1988 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1989
1990 return hdev->hw.mac.link;
1991}
1992
4a152de9
FL		 1993static void hclgevf_get_ksettings_an_result(struct hnae3_handle *handle,
1994 u8 *auto_neg, u32 *speed,
1995 u8 *duplex)
1996{
1997 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
1998
1999 if (speed)
2000 *speed = hdev->hw.mac.speed;
2001 if (duplex)
2002 *duplex = hdev->hw.mac.duplex;
2003 if (auto_neg)
2004 *auto_neg = AUTONEG_DISABLE;
2005}
2006
2007void hclgevf_update_speed_duplex(struct hclgevf_dev *hdev, u32 speed,
2008 u8 duplex)
2009{
2010 hdev->hw.mac.speed = speed;
2011 hdev->hw.mac.duplex = duplex;
2012}
2013
c136b884
PL		 2014static void hclgevf_get_media_type(struct hnae3_handle *handle,
2015 u8 *media_type)
2016{
2017 struct hclgevf_dev *hdev = hclgevf_ae_get_hdev(handle);
2018 if (media_type)
2019 *media_type = hdev->hw.mac.media_type;
2020}
2021
e2cb1dec
SM		 2022static const struct hnae3_ae_ops hclgevf_ops = {
2023 .init_ae_dev = hclgevf_init_ae_dev,
2024 .uninit_ae_dev = hclgevf_uninit_ae_dev,
e718a93f
PL		 2025 .init_client_instance = hclgevf_init_client_instance,
2026 .uninit_client_instance = hclgevf_uninit_client_instance,
e2cb1dec
SM		 2027 .start = hclgevf_ae_start,
2028 .stop = hclgevf_ae_stop,
2029 .map_ring_to_vector = hclgevf_map_ring_to_vector,
2030 .unmap_ring_from_vector = hclgevf_unmap_ring_from_vector,
2031 .get_vector = hclgevf_get_vector,
0d3e6631 2032 .put_vector = hclgevf_put_vector,
e2cb1dec
SM		 2033 .reset_queue = hclgevf_reset_tqp,
2034 .set_promisc_mode = hclgevf_set_promisc_mode,
2035 .get_mac_addr = hclgevf_get_mac_addr,
2036 .set_mac_addr = hclgevf_set_mac_addr,
2037 .add_uc_addr = hclgevf_add_uc_addr,
2038 .rm_uc_addr = hclgevf_rm_uc_addr,
2039 .add_mc_addr = hclgevf_add_mc_addr,
2040 .rm_mc_addr = hclgevf_rm_mc_addr,
3a678b58 2041 .update_mta_status = hclgevf_update_mta_status,
e2cb1dec
SM		 2042 .get_stats = hclgevf_get_stats,
2043 .update_stats = hclgevf_update_stats,
2044 .get_strings = hclgevf_get_strings,
2045 .get_sset_count = hclgevf_get_sset_count,
2046 .get_rss_key_size = hclgevf_get_rss_key_size,
2047 .get_rss_indir_size = hclgevf_get_rss_indir_size,
2048 .get_rss = hclgevf_get_rss,
2049 .set_rss = hclgevf_set_rss,
2050 .get_tc_size = hclgevf_get_tc_size,
2051 .get_fw_version = hclgevf_get_fw_version,
2052 .set_vlan_filter = hclgevf_set_vlan_filter,
b2641e2a 2053 .enable_hw_strip_rxvtag = hclgevf_en_hw_strip_rxvtag,
6d4c3981 2054 .reset_event = hclgevf_reset_event,
849e4607 2055 .get_channels = hclgevf_get_channels,
cc719218 2056 .get_tqps_and_rss_info = hclgevf_get_tqps_and_rss_info,
175ec96b 2057 .get_status = hclgevf_get_status,
4a152de9 2058 .get_ksettings_an_result = hclgevf_get_ksettings_an_result,
c136b884 2059 .get_media_type = hclgevf_get_media_type,
e2cb1dec
SM		 2060};
2061
2062static struct hnae3_ae_algo ae_algovf = {
2063 .ops = &hclgevf_ops,
e2cb1dec
SM		 2064 .pdev_id_table = ae_algovf_pci_tbl,
2065};
2066
2067static int hclgevf_init(void)
2068{
2069 pr_info("%s is initializing\n", HCLGEVF_NAME);
2070
854cf33a
FL		 2071 hnae3_register_ae_algo(&ae_algovf);
2072
2073 return 0;
e2cb1dec
SM		 2074}
2075
2076static void hclgevf_exit(void)
2077{
2078 hnae3_unregister_ae_algo(&ae_algovf);
2079}
2080module_init(hclgevf_init);
2081module_exit(hclgevf_exit);
2082
2083MODULE_LICENSE("GPL");
2084MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
2085MODULE_DESCRIPTION("HCLGEVF Driver");
2086MODULE_VERSION(HCLGEVF_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)