projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: hns3: add support for configuring bandwidth of VF on the host
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_tm.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
84844054
S		 3
4#include <linux/etherdevice.h>
5
6#include "hclge_cmd.h"
7#include "hclge_main.h"
8#include "hclge_tm.h"
9
10enum hclge_shaper_level {
11 HCLGE_SHAPER_LVL_PRI = 0,
12 HCLGE_SHAPER_LVL_PG = 1,
13 HCLGE_SHAPER_LVL_PORT = 2,
14 HCLGE_SHAPER_LVL_QSET = 3,
15 HCLGE_SHAPER_LVL_CNT = 4,
16 HCLGE_SHAPER_LVL_VF = 0,
17 HCLGE_SHAPER_LVL_PF = 1,
18};
19
64fd2300
PL		 20#define HCLGE_TM_PFC_PKT_GET_CMD_NUM 3
21#define HCLGE_TM_PFC_NUM_GET_PER_CMD 3
22
3a7d5958
PL		 23#define HCLGE_SHAPER_BS_U_DEF 5
24#define HCLGE_SHAPER_BS_S_DEF 20
84844054
S		 25
26#define HCLGE_ETHER_MAX_RATE 100000
27
28/* hclge_shaper_para_calc: calculate ir parameter for the shaper
29 * @ir: Rate to be config, its unit is Mbps
30 * @shaper_level: the shaper level. eg: port, pg, priority, queueset
31 * @ir_b: IR_B parameter of IR shaper
32 * @ir_u: IR_U parameter of IR shaper
33 * @ir_s: IR_S parameter of IR shaper
34 *
35 * the formula:
36 *
37 * IR_b * (2 ^ IR_u) * 8
38 * IR(Mbps) = ------------------------- * CLOCK(1000Mbps)
39 * Tick * (2 ^ IR_s)
40 *
41 * @return: 0: calculate sucessful, negative: fail
42 */
43static int hclge_shaper_para_calc(u32 ir, u8 shaper_level,
44 u8 *ir_b, u8 *ir_u, u8 *ir_s)
45{
b37ce587
YM		 46#define DIVISOR_CLK (1000 * 8)
47#define DIVISOR_IR_B_126 (126 * DIVISOR_CLK)
48
3ea7af9e 49 static const u16 tick_array[HCLGE_SHAPER_LVL_CNT] = {
84844054
S		 50 6 * 256, /* Prioriy level */
51 6 * 32, /* Prioriy group level */
52 6 * 8, /* Port level */
53 6 * 256 /* Qset level */
54 };
9b2f3477
WL		 55 u8 ir_u_calc = 0;
56 u8 ir_s_calc = 0;
84844054
S		 57 u32 ir_calc;
58 u32 tick;
59
60 /* Calc tick */
04f25edb
YL		 61 if (shaper_level >= HCLGE_SHAPER_LVL_CNT ||
62 ir > HCLGE_ETHER_MAX_RATE)
84844054
S		 63 return -EINVAL;
64
65 tick = tick_array[shaper_level];
66
67 /**
68 * Calc the speed if ir_b = 126, ir_u = 0 and ir_s = 0
69 * the formula is changed to:
70 * 126 * 1 * 8
71 * ir_calc = ---------------- * 1000
72 * tick * 1
73 */
b37ce587 74 ir_calc = (DIVISOR_IR_B_126 + (tick >> 1) - 1) / tick;
84844054
S		 75
76 if (ir_calc == ir) {
77 *ir_b = 126;
78 *ir_u = 0;
79 *ir_s = 0;
80
81 return 0;
82 } else if (ir_calc > ir) {
83 /* Increasing the denominator to select ir_s value */
1a92497d 84 while (ir_calc >= ir && ir) {
84844054 85 ir_s_calc++;
b37ce587 86 ir_calc = DIVISOR_IR_B_126 / (tick * (1 << ir_s_calc));
84844054
S		 87 }
88
1a92497d
YL		 89 *ir_b = (ir * tick * (1 << ir_s_calc) + (DIVISOR_CLK >> 1)) /
90 DIVISOR_CLK;
84844054
S		 91 } else {
92 /* Increasing the numerator to select ir_u value */
93 u32 numerator;
94
95 while (ir_calc < ir) {
96 ir_u_calc++;
b37ce587 97 numerator = DIVISOR_IR_B_126 * (1 << ir_u_calc);
84844054
S		 98 ir_calc = (numerator + (tick >> 1)) / tick;
99 }
100
101 if (ir_calc == ir) {
102 *ir_b = 126;
103 } else {
1a92497d 104 u32 denominator = DIVISOR_CLK * (1 << --ir_u_calc);
84844054
S		 105 *ir_b = (ir * tick + (denominator >> 1)) / denominator;
106 }
107 }
108
109 *ir_u = ir_u_calc;
110 *ir_s = ir_s_calc;
111
112 return 0;
113}
114
64fd2300
PL		 115static int hclge_pfc_stats_get(struct hclge_dev *hdev,
116 enum hclge_opcode_type opcode, u64 *stats)
117{
118 struct hclge_desc desc[HCLGE_TM_PFC_PKT_GET_CMD_NUM];
119 int ret, i, j;
120
121 if (!(opcode == HCLGE_OPC_QUERY_PFC_RX_PKT_CNT ||
122 opcode == HCLGE_OPC_QUERY_PFC_TX_PKT_CNT))
123 return -EINVAL;
124
63cbf7a9 125 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM - 1; i++) {
64fd2300 126 hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
63cbf7a9 127 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
64fd2300
PL		 128 }
129
63cbf7a9
YM		 130 hclge_cmd_setup_basic_desc(&desc[i], opcode, true);
131
64fd2300 132 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_TM_PFC_PKT_GET_CMD_NUM);
20670328 133 if (ret)
64fd2300 134 return ret;
64fd2300
PL		 135
136 for (i = 0; i < HCLGE_TM_PFC_PKT_GET_CMD_NUM; i++) {
137 struct hclge_pfc_stats_cmd *pfc_stats =
138 (struct hclge_pfc_stats_cmd *)desc[i].data;
139
140 for (j = 0; j < HCLGE_TM_PFC_NUM_GET_PER_CMD; j++) {
141 u32 index = i * HCLGE_TM_PFC_PKT_GET_CMD_NUM + j;
142
143 if (index < HCLGE_MAX_TC_NUM)
144 stats[index] =
145 le64_to_cpu(pfc_stats->pkt_num[j]);
146 }
147 }
148 return 0;
149}
150
151int hclge_pfc_rx_stats_get(struct hclge_dev *hdev, u64 *stats)
152{
153 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_RX_PKT_CNT, stats);
154}
155
156int hclge_pfc_tx_stats_get(struct hclge_dev *hdev, u64 *stats)
157{
158 return hclge_pfc_stats_get(hdev, HCLGE_OPC_QUERY_PFC_TX_PKT_CNT, stats);
159}
160
61387774 161int hclge_mac_pause_en_cfg(struct hclge_dev *hdev, bool tx, bool rx)
84844054
S		 162{
163 struct hclge_desc desc;
164
165 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PAUSE_EN, false);
166
167 desc.data[0] = cpu_to_le32((tx ? HCLGE_TX_MAC_PAUSE_EN_MSK : 0) |
168 (rx ? HCLGE_RX_MAC_PAUSE_EN_MSK : 0));
169
170 return hclge_cmd_send(&hdev->hw, &desc, 1);
171}
172
9dc2145d
YL		 173static int hclge_pfc_pause_en_cfg(struct hclge_dev *hdev, u8 tx_rx_bitmap,
174 u8 pfc_bitmap)
175{
176 struct hclge_desc desc;
d0d72bac 177 struct hclge_pfc_en_cmd *pfc = (struct hclge_pfc_en_cmd *)desc.data;
9dc2145d
YL		 178
179 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PFC_PAUSE_EN, false);
180
181 pfc->tx_rx_en_bitmap = tx_rx_bitmap;
182 pfc->pri_en_bitmap = pfc_bitmap;
183
184 return hclge_cmd_send(&hdev->hw, &desc, 1);
185}
186
e98d7183
FL		 187static int hclge_pause_param_cfg(struct hclge_dev *hdev, const u8 *addr,
188 u8 pause_trans_gap, u16 pause_trans_time)
18838d0c
FL		 189{
190 struct hclge_cfg_pause_param_cmd *pause_param;
191 struct hclge_desc desc;
192
d0d72bac 193 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
18838d0c
FL		 194
195 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, false);
196
197 ether_addr_copy(pause_param->mac_addr, addr);
cd2086bf 198 ether_addr_copy(pause_param->mac_addr_extra, addr);
18838d0c
FL		 199 pause_param->pause_trans_gap = pause_trans_gap;
200 pause_param->pause_trans_time = cpu_to_le16(pause_trans_time);
201
202 return hclge_cmd_send(&hdev->hw, &desc, 1);
203}
204
e98d7183 205int hclge_pause_addr_cfg(struct hclge_dev *hdev, const u8 *mac_addr)
18838d0c
FL		 206{
207 struct hclge_cfg_pause_param_cmd *pause_param;
208 struct hclge_desc desc;
209 u16 trans_time;
210 u8 trans_gap;
211 int ret;
212
d0d72bac 213 pause_param = (struct hclge_cfg_pause_param_cmd *)desc.data;
18838d0c
FL		 214
215 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_MAC_PARA, true);
216
217 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
218 if (ret)
219 return ret;
220
221 trans_gap = pause_param->pause_trans_gap;
222 trans_time = le16_to_cpu(pause_param->pause_trans_time);
223
9b2f3477 224 return hclge_pause_param_cfg(hdev, mac_addr, trans_gap, trans_time);
18838d0c
FL		 225}
226
84844054
S		 227static int hclge_fill_pri_array(struct hclge_dev *hdev, u8 *pri, u8 pri_id)
228{
229 u8 tc;
230
c5795c53 231 tc = hdev->tm_info.prio_tc[pri_id];
84844054
S		 232
233 if (tc >= hdev->tm_info.num_tc)
234 return -EINVAL;
235
236 /**
237 * the register for priority has four bytes, the first bytes includes
238 * priority0 and priority1, the higher 4bit stands for priority1
239 * while the lower 4bit stands for priority0, as below:
240 * first byte: | pri_1 | pri_0 |
241 * second byte: | pri_3 | pri_2 |
242 * third byte: | pri_5 | pri_4 |
243 * fourth byte: | pri_7 | pri_6 |
244 */
245 pri[pri_id >> 1] |= tc << ((pri_id & 1) * 4);
246
247 return 0;
248}
249
250static int hclge_up_to_tc_map(struct hclge_dev *hdev)
251{
252 struct hclge_desc desc;
253 u8 *pri = (u8 *)desc.data;
254 u8 pri_id;
255 int ret;
256
257 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_PRI_TO_TC_MAPPING, false);
258
c5795c53 259 for (pri_id = 0; pri_id < HNAE3_MAX_USER_PRIO; pri_id++) {
84844054
S		 260 ret = hclge_fill_pri_array(hdev, pri, pri_id);
261 if (ret)
262 return ret;
263 }
264
265 return hclge_cmd_send(&hdev->hw, &desc, 1);
266}
267
268static int hclge_tm_pg_to_pri_map_cfg(struct hclge_dev *hdev,
269 u8 pg_id, u8 pri_bit_map)
270{
271 struct hclge_pg_to_pri_link_cmd *map;
272 struct hclge_desc desc;
273
274 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_TO_PRI_LINK, false);
275
276 map = (struct hclge_pg_to_pri_link_cmd *)desc.data;
277
278 map->pg_id = pg_id;
279 map->pri_bit_map = pri_bit_map;
280
281 return hclge_cmd_send(&hdev->hw, &desc, 1);
282}
283
284static int hclge_tm_qs_to_pri_map_cfg(struct hclge_dev *hdev,
285 u16 qs_id, u8 pri)
286{
287 struct hclge_qs_to_pri_link_cmd *map;
288 struct hclge_desc desc;
289
290 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_TO_PRI_LINK, false);
291
292 map = (struct hclge_qs_to_pri_link_cmd *)desc.data;
293
294 map->qs_id = cpu_to_le16(qs_id);
295 map->priority = pri;
296 map->link_vld = HCLGE_TM_QS_PRI_LINK_VLD_MSK;
297
298 return hclge_cmd_send(&hdev->hw, &desc, 1);
299}
300
301static int hclge_tm_q_to_qs_map_cfg(struct hclge_dev *hdev,
32c7fbc8 302 u16 q_id, u16 qs_id)
84844054
S		 303{
304 struct hclge_nq_to_qs_link_cmd *map;
305 struct hclge_desc desc;
306
307 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_NQ_TO_QS_LINK, false);
308
309 map = (struct hclge_nq_to_qs_link_cmd *)desc.data;
310
311 map->nq_id = cpu_to_le16(q_id);
312 map->qset_id = cpu_to_le16(qs_id | HCLGE_TM_Q_QS_LINK_VLD_MSK);
313
314 return hclge_cmd_send(&hdev->hw, &desc, 1);
315}
316
317static int hclge_tm_pg_weight_cfg(struct hclge_dev *hdev, u8 pg_id,
318 u8 dwrr)
319{
320 struct hclge_pg_weight_cmd *weight;
321 struct hclge_desc desc;
322
323 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_WEIGHT, false);
324
325 weight = (struct hclge_pg_weight_cmd *)desc.data;
326
327 weight->pg_id = pg_id;
328 weight->dwrr = dwrr;
329
330 return hclge_cmd_send(&hdev->hw, &desc, 1);
331}
332
333static int hclge_tm_pri_weight_cfg(struct hclge_dev *hdev, u8 pri_id,
334 u8 dwrr)
335{
336 struct hclge_priority_weight_cmd *weight;
337 struct hclge_desc desc;
338
339 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_WEIGHT, false);
340
341 weight = (struct hclge_priority_weight_cmd *)desc.data;
342
343 weight->pri_id = pri_id;
344 weight->dwrr = dwrr;
345
346 return hclge_cmd_send(&hdev->hw, &desc, 1);
347}
348
349static int hclge_tm_qs_weight_cfg(struct hclge_dev *hdev, u16 qs_id,
350 u8 dwrr)
351{
352 struct hclge_qs_weight_cmd *weight;
353 struct hclge_desc desc;
354
355 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_WEIGHT, false);
356
357 weight = (struct hclge_qs_weight_cmd *)desc.data;
358
359 weight->qs_id = cpu_to_le16(qs_id);
360 weight->dwrr = dwrr;
361
362 return hclge_cmd_send(&hdev->hw, &desc, 1);
363}
364
63cbf7a9
YM		 365static u32 hclge_tm_get_shapping_para(u8 ir_b, u8 ir_u, u8 ir_s,
366 u8 bs_b, u8 bs_s)
367{
368 u32 shapping_para = 0;
369
370 hclge_tm_set_field(shapping_para, IR_B, ir_b);
371 hclge_tm_set_field(shapping_para, IR_U, ir_u);
372 hclge_tm_set_field(shapping_para, IR_S, ir_s);
373 hclge_tm_set_field(shapping_para, BS_B, bs_b);
374 hclge_tm_set_field(shapping_para, BS_S, bs_s);
375
376 return shapping_para;
377}
378
84844054
S		 379static int hclge_tm_pg_shapping_cfg(struct hclge_dev *hdev,
380 enum hclge_shap_bucket bucket, u8 pg_id,
63cbf7a9 381 u32 shapping_para)
84844054
S		 382{
383 struct hclge_pg_shapping_cmd *shap_cfg_cmd;
384 enum hclge_opcode_type opcode;
385 struct hclge_desc desc;
386
387 opcode = bucket ? HCLGE_OPC_TM_PG_P_SHAPPING :
9b2f3477 388 HCLGE_OPC_TM_PG_C_SHAPPING;
84844054
S		 389 hclge_cmd_setup_basic_desc(&desc, opcode, false);
390
391 shap_cfg_cmd = (struct hclge_pg_shapping_cmd *)desc.data;
392
393 shap_cfg_cmd->pg_id = pg_id;
394
a90bb9a5 395 shap_cfg_cmd->pg_shapping_para = cpu_to_le32(shapping_para);
84844054
S		 396
397 return hclge_cmd_send(&hdev->hw, &desc, 1);
398}
399
0a5677d3
YL		 400static int hclge_tm_port_shaper_cfg(struct hclge_dev *hdev)
401{
402 struct hclge_port_shapping_cmd *shap_cfg_cmd;
403 struct hclge_desc desc;
0a5677d3 404 u8 ir_u, ir_b, ir_s;
cdd332ac 405 u32 shapping_para;
0a5677d3
YL		 406 int ret;
407
d9ea1562 408 ret = hclge_shaper_para_calc(hdev->hw.mac.speed,
0a5677d3
YL		 409 HCLGE_SHAPER_LVL_PORT,
410 &ir_b, &ir_u, &ir_s);
411 if (ret)
412 return ret;
413
414 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PORT_SHAPPING, false);
415 shap_cfg_cmd = (struct hclge_port_shapping_cmd *)desc.data;
416
63cbf7a9
YM		 417 shapping_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
418 HCLGE_SHAPER_BS_U_DEF,
419 HCLGE_SHAPER_BS_S_DEF);
0a5677d3
YL		 420
421 shap_cfg_cmd->port_shapping_para = cpu_to_le32(shapping_para);
422
423 return hclge_cmd_send(&hdev->hw, &desc, 1);
424}
425
84844054
S		 426static int hclge_tm_pri_shapping_cfg(struct hclge_dev *hdev,
427 enum hclge_shap_bucket bucket, u8 pri_id,
63cbf7a9 428 u32 shapping_para)
84844054
S		 429{
430 struct hclge_pri_shapping_cmd *shap_cfg_cmd;
431 enum hclge_opcode_type opcode;
432 struct hclge_desc desc;
433
434 opcode = bucket ? HCLGE_OPC_TM_PRI_P_SHAPPING :
9b2f3477 435 HCLGE_OPC_TM_PRI_C_SHAPPING;
84844054
S		 436
437 hclge_cmd_setup_basic_desc(&desc, opcode, false);
438
439 shap_cfg_cmd = (struct hclge_pri_shapping_cmd *)desc.data;
440
441 shap_cfg_cmd->pri_id = pri_id;
442
a90bb9a5 443 shap_cfg_cmd->pri_shapping_para = cpu_to_le32(shapping_para);
84844054
S		 444
445 return hclge_cmd_send(&hdev->hw, &desc, 1);
446}
447
448static int hclge_tm_pg_schd_mode_cfg(struct hclge_dev *hdev, u8 pg_id)
449{
450 struct hclge_desc desc;
451
452 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PG_SCH_MODE_CFG, false);
453
454 if (hdev->tm_info.pg_info[pg_id].pg_sch_mode == HCLGE_SCH_MODE_DWRR)
455 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
456 else
457 desc.data[1] = 0;
458
459 desc.data[0] = cpu_to_le32(pg_id);
460
461 return hclge_cmd_send(&hdev->hw, &desc, 1);
462}
463
464static int hclge_tm_pri_schd_mode_cfg(struct hclge_dev *hdev, u8 pri_id)
465{
466 struct hclge_desc desc;
467
468 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_PRI_SCH_MODE_CFG, false);
469
470 if (hdev->tm_info.tc_info[pri_id].tc_sch_mode == HCLGE_SCH_MODE_DWRR)
471 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
472 else
473 desc.data[1] = 0;
474
475 desc.data[0] = cpu_to_le32(pri_id);
476
477 return hclge_cmd_send(&hdev->hw, &desc, 1);
478}
479
cc9bb43a 480static int hclge_tm_qs_schd_mode_cfg(struct hclge_dev *hdev, u16 qs_id, u8 mode)
84844054
S		 481{
482 struct hclge_desc desc;
483
484 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_QS_SCH_MODE_CFG, false);
485
cc9bb43a 486 if (mode == HCLGE_SCH_MODE_DWRR)
84844054
S		 487 desc.data[1] = cpu_to_le32(HCLGE_TM_TX_SCHD_DWRR_MSK);
488 else
489 desc.data[1] = 0;
490
491 desc.data[0] = cpu_to_le32(qs_id);
492
493 return hclge_cmd_send(&hdev->hw, &desc, 1);
494}
495
67bf2541
YL		 496static int hclge_tm_qs_bp_cfg(struct hclge_dev *hdev, u8 tc, u8 grp_id,
497 u32 bit_map)
84844054
S		 498{
499 struct hclge_bp_to_qs_map_cmd *bp_to_qs_map_cmd;
500 struct hclge_desc desc;
501
502 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TM_BP_TO_QSET_MAPPING,
503 false);
504
505 bp_to_qs_map_cmd = (struct hclge_bp_to_qs_map_cmd *)desc.data;
506
507 bp_to_qs_map_cmd->tc_id = tc;
67bf2541
YL		 508 bp_to_qs_map_cmd->qs_group_id = grp_id;
509 bp_to_qs_map_cmd->qs_bit_map = cpu_to_le32(bit_map);
84844054
S		 510
511 return hclge_cmd_send(&hdev->hw, &desc, 1);
512}
513
ee9e4424
YL		 514int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate)
515{
516 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
517 struct hclge_qs_shapping_cmd *shap_cfg_cmd;
518 struct hclge_dev *hdev = vport->back;
519 struct hclge_desc desc;
520 u8 ir_b, ir_u, ir_s;
521 u32 shaper_para;
522 int ret, i;
523
524 if (!max_tx_rate)
525 max_tx_rate = HCLGE_ETHER_MAX_RATE;
526
527 ret = hclge_shaper_para_calc(max_tx_rate, HCLGE_SHAPER_LVL_QSET,
528 &ir_b, &ir_u, &ir_s);
529 if (ret)
530 return ret;
531
532 shaper_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
533 HCLGE_SHAPER_BS_U_DEF,
534 HCLGE_SHAPER_BS_S_DEF);
535
536 for (i = 0; i < kinfo->num_tc; i++) {
537 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QCN_SHAPPING_CFG,
538 false);
539
540 shap_cfg_cmd = (struct hclge_qs_shapping_cmd *)desc.data;
541 shap_cfg_cmd->qs_id = cpu_to_le16(vport->qs_offset + i);
542 shap_cfg_cmd->qs_shapping_para = cpu_to_le32(shaper_para);
543
544 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
545 if (ret) {
546 dev_err(&hdev->pdev->dev,
547 "vf%d, qs%u failed to set tx_rate:%d, ret=%d\n",
548 vport->vport_id, shap_cfg_cmd->qs_id,
549 max_tx_rate, ret);
550 return ret;
551 }
552 }
553
554 return 0;
555}
556
84844054
S		 557static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
558{
559 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
560 struct hclge_dev *hdev = vport->back;
672ad0ed 561 u16 max_rss_size;
84844054
S		 562 u8 i;
563
de67a690
YL		 564 /* TC configuration is shared by PF/VF in one port, only allow
565 * one tc for VF for simplicity. VF's vport_id is non zero.
566 */
567 kinfo->num_tc = vport->vport_id ? 1 :
568 min_t(u16, vport->alloc_tqps, hdev->tm_info.num_tc);
569 vport->qs_offset = (vport->vport_id ? hdev->tm_info.num_tc : 0) +
570 (vport->vport_id ? (vport->vport_id - 1) : 0);
571
672ad0ed
HT		 572 max_rss_size = min_t(u16, hdev->rss_size_max,
573 vport->alloc_tqps / kinfo->num_tc);
574
9b2f3477 575 /* Set to user value, no larger than max_rss_size. */
672ad0ed
HT		 576 if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
577 kinfo->req_rss_size <= max_rss_size) {
578 dev_info(&hdev->pdev->dev, "rss changes from %d to %d\n",
579 kinfo->rss_size, kinfo->req_rss_size);
580 kinfo->rss_size = kinfo->req_rss_size;
581 } else if (kinfo->rss_size > max_rss_size ||
582 (!kinfo->req_rss_size && kinfo->rss_size < max_rss_size)) {
9b2f3477 583 /* Set to the maximum specification value (max_rss_size). */
672ad0ed
HT		 584 dev_info(&hdev->pdev->dev, "rss changes from %d to %d\n",
585 kinfo->rss_size, max_rss_size);
586 kinfo->rss_size = max_rss_size;
587 }
588
589 kinfo->num_tqps = kinfo->num_tc * kinfo->rss_size;
84844054 590 vport->dwrr = 100; /* 100 percent as init */
68ece54e 591 vport->alloc_rss_size = kinfo->rss_size;
de67a690 592 vport->bw_limit = hdev->tm_info.pg_info[0].bw_limit;
84844054 593
af958827 594 for (i = 0; i < HNAE3_MAX_TC; i++) {
de67a690 595 if (hdev->hw_tc_map & BIT(i) && i < kinfo->num_tc) {
84844054
S		 596 kinfo->tc_info[i].enable = true;
597 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
598 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
599 kinfo->tc_info[i].tc = i;
84844054
S		 600 } else {
601 /* Set to default queue if TC is disable */
602 kinfo->tc_info[i].enable = false;
603 kinfo->tc_info[i].tqp_offset = 0;
604 kinfo->tc_info[i].tqp_count = 1;
605 kinfo->tc_info[i].tc = 0;
84844054
S		 606 }
607 }
c5795c53
YL		 608
609 memcpy(kinfo->prio_tc, hdev->tm_info.prio_tc,
610 FIELD_SIZEOF(struct hnae3_knic_private_info, prio_tc));
84844054
S		 611}
612
613static void hclge_tm_vport_info_update(struct hclge_dev *hdev)
614{
615 struct hclge_vport *vport = hdev->vport;
616 u32 i;
617
618 for (i = 0; i < hdev->num_alloc_vport; i++) {
619 hclge_tm_vport_tc_info_update(vport);
620
621 vport++;
622 }
623}
624
625static void hclge_tm_tc_info_init(struct hclge_dev *hdev)
626{
627 u8 i;
628
629 for (i = 0; i < hdev->tm_info.num_tc; i++) {
630 hdev->tm_info.tc_info[i].tc_id = i;
631 hdev->tm_info.tc_info[i].tc_sch_mode = HCLGE_SCH_MODE_DWRR;
84844054
S		 632 hdev->tm_info.tc_info[i].pgid = 0;
633 hdev->tm_info.tc_info[i].bw_limit =
634 hdev->tm_info.pg_info[0].bw_limit;
635 }
636
c5795c53
YL		 637 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++)
638 hdev->tm_info.prio_tc[i] =
639 (i >= hdev->tm_info.num_tc) ? 0 : i;
640
ae179b2f
YL		 641 /* DCB is enabled if we have more than 1 TC or pfc_en is
642 * non-zero.
643 */
644 if (hdev->tm_info.num_tc > 1 || hdev->tm_info.pfc_en)
7979a223
YL		 645 hdev->flag |= HCLGE_FLAG_DCB_ENABLE;
646 else
647 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
84844054
S		 648}
649
650static void hclge_tm_pg_info_init(struct hclge_dev *hdev)
651{
b37ce587
YM		 652#define BW_PERCENT 100
653
84844054
S		 654 u8 i;
655
656 for (i = 0; i < hdev->tm_info.num_pg; i++) {
657 int k;
658
b37ce587 659 hdev->tm_info.pg_dwrr[i] = i ? 0 : BW_PERCENT;
84844054
S		 660
661 hdev->tm_info.pg_info[i].pg_id = i;
662 hdev->tm_info.pg_info[i].pg_sch_mode = HCLGE_SCH_MODE_DWRR;
663
664 hdev->tm_info.pg_info[i].bw_limit = HCLGE_ETHER_MAX_RATE;
665
666 if (i != 0)
667 continue;
668
669 hdev->tm_info.pg_info[i].tc_bit_map = hdev->hw_tc_map;
670 for (k = 0; k < hdev->tm_info.num_tc; k++)
b37ce587 671 hdev->tm_info.pg_info[i].tc_dwrr[k] = BW_PERCENT;
84844054
S		 672 }
673}
674
7979a223
YL		 675static void hclge_pfc_info_init(struct hclge_dev *hdev)
676{
677 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE)) {
678 if (hdev->fc_mode_last_time == HCLGE_FC_PFC)
679 dev_warn(&hdev->pdev->dev,
680 "DCB is disable, but last mode is FC_PFC\n");
681
682 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
683 } else if (hdev->tm_info.fc_mode != HCLGE_FC_PFC) {
684 /* fc_mode_last_time record the last fc_mode when
685 * DCB is enabled, so that fc_mode can be set to
686 * the correct value when DCB is disabled.
687 */
688 hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
689 hdev->tm_info.fc_mode = HCLGE_FC_PFC;
690 }
691}
692
b6872fd3 693static void hclge_tm_schd_info_init(struct hclge_dev *hdev)
84844054 694{
84844054
S		 695 hclge_tm_pg_info_init(hdev);
696
697 hclge_tm_tc_info_init(hdev);
698
699 hclge_tm_vport_info_update(hdev);
700
7979a223 701 hclge_pfc_info_init(hdev);
84844054
S		 702}
703
704static int hclge_tm_pg_to_pri_map(struct hclge_dev *hdev)
705{
706 int ret;
707 u32 i;
708
709 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
710 return 0;
711
712 for (i = 0; i < hdev->tm_info.num_pg; i++) {
713 /* Cfg mapping */
714 ret = hclge_tm_pg_to_pri_map_cfg(
715 hdev, i, hdev->tm_info.pg_info[i].tc_bit_map);
716 if (ret)
717 return ret;
718 }
719
720 return 0;
721}
722
723static int hclge_tm_pg_shaper_cfg(struct hclge_dev *hdev)
724{
725 u8 ir_u, ir_b, ir_s;
63cbf7a9 726 u32 shaper_para;
84844054
S		 727 int ret;
728 u32 i;
729
730 /* Cfg pg schd */
731 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
732 return 0;
733
734 /* Pg to pri */
735 for (i = 0; i < hdev->tm_info.num_pg; i++) {
736 /* Calc shaper para */
737 ret = hclge_shaper_para_calc(
738 hdev->tm_info.pg_info[i].bw_limit,
739 HCLGE_SHAPER_LVL_PG,
740 &ir_b, &ir_u, &ir_s);
741 if (ret)
742 return ret;
743
63cbf7a9
YM		 744 shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
745 HCLGE_SHAPER_BS_U_DEF,
746 HCLGE_SHAPER_BS_S_DEF);
84844054
S		 747 ret = hclge_tm_pg_shapping_cfg(hdev,
748 HCLGE_TM_SHAP_C_BUCKET, i,
63cbf7a9 749 shaper_para);
84844054
S		 750 if (ret)
751 return ret;
752
63cbf7a9
YM		 753 shaper_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
754 HCLGE_SHAPER_BS_U_DEF,
755 HCLGE_SHAPER_BS_S_DEF);
84844054
S		 756 ret = hclge_tm_pg_shapping_cfg(hdev,
757 HCLGE_TM_SHAP_P_BUCKET, i,
63cbf7a9 758 shaper_para);
84844054
S		 759 if (ret)
760 return ret;
761 }
762
763 return 0;
764}
765
766static int hclge_tm_pg_dwrr_cfg(struct hclge_dev *hdev)
767{
768 int ret;
769 u32 i;
770
771 /* cfg pg schd */
772 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE)
773 return 0;
774
775 /* pg to prio */
776 for (i = 0; i < hdev->tm_info.num_pg; i++) {
777 /* Cfg dwrr */
9b2f3477 778 ret = hclge_tm_pg_weight_cfg(hdev, i, hdev->tm_info.pg_dwrr[i]);
84844054
S		 779 if (ret)
780 return ret;
781 }
782
783 return 0;
784}
785
786static int hclge_vport_q_to_qs_map(struct hclge_dev *hdev,
787 struct hclge_vport *vport)
788{
789 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
790 struct hnae3_queue **tqp = kinfo->tqp;
791 struct hnae3_tc_info *v_tc_info;
792 u32 i, j;
793 int ret;
794
795 for (i = 0; i < kinfo->num_tc; i++) {
796 v_tc_info = &kinfo->tc_info[i];
797 for (j = 0; j < v_tc_info->tqp_count; j++) {
798 struct hnae3_queue *q = tqp[v_tc_info->tqp_offset + j];
799
800 ret = hclge_tm_q_to_qs_map_cfg(hdev,
801 hclge_get_queue_id(q),
802 vport->qs_offset + i);
803 if (ret)
804 return ret;
805 }
806 }
807
808 return 0;
809}
810
811static int hclge_tm_pri_q_qs_cfg(struct hclge_dev *hdev)
812{
813 struct hclge_vport *vport = hdev->vport;
814 int ret;
cc9bb43a 815 u32 i, k;
84844054
S		 816
817 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
818 /* Cfg qs -> pri mapping, one by one mapping */
de67a690
YL		 819 for (k = 0; k < hdev->num_alloc_vport; k++) {
820 struct hnae3_knic_private_info *kinfo =
821 &vport[k].nic.kinfo;
822
823 for (i = 0; i < kinfo->num_tc; i++) {
cc9bb43a
YL		 824 ret = hclge_tm_qs_to_pri_map_cfg(
825 hdev, vport[k].qs_offset + i, i);
826 if (ret)
827 return ret;
828 }
de67a690 829 }
84844054 830 } else if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE) {
84844054
S		 831 /* Cfg qs -> pri mapping, qs = tc, pri = vf, 8 qs -> 1 pri */
832 for (k = 0; k < hdev->num_alloc_vport; k++)
833 for (i = 0; i < HNAE3_MAX_TC; i++) {
834 ret = hclge_tm_qs_to_pri_map_cfg(
835 hdev, vport[k].qs_offset + i, k);
836 if (ret)
837 return ret;
838 }
839 } else {
840 return -EINVAL;
841 }
842
843 /* Cfg q -> qs mapping */
844 for (i = 0; i < hdev->num_alloc_vport; i++) {
845 ret = hclge_vport_q_to_qs_map(hdev, vport);
846 if (ret)
847 return ret;
848
849 vport++;
850 }
851
852 return 0;
853}
854
855static int hclge_tm_pri_tc_base_shaper_cfg(struct hclge_dev *hdev)
856{
857 u8 ir_u, ir_b, ir_s;
63cbf7a9 858 u32 shaper_para;
84844054
S		 859 int ret;
860 u32 i;
861
862 for (i = 0; i < hdev->tm_info.num_tc; i++) {
863 ret = hclge_shaper_para_calc(
864 hdev->tm_info.tc_info[i].bw_limit,
865 HCLGE_SHAPER_LVL_PRI,
866 &ir_b, &ir_u, &ir_s);
867 if (ret)
868 return ret;
869
63cbf7a9
YM		 870 shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
871 HCLGE_SHAPER_BS_U_DEF,
872 HCLGE_SHAPER_BS_S_DEF);
873 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET, i,
874 shaper_para);
84844054
S		 875 if (ret)
876 return ret;
877
63cbf7a9
YM		 878 shaper_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
879 HCLGE_SHAPER_BS_U_DEF,
880 HCLGE_SHAPER_BS_S_DEF);
881 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET, i,
882 shaper_para);
84844054
S		 883 if (ret)
884 return ret;
885 }
886
887 return 0;
888}
889
890static int hclge_tm_pri_vnet_base_shaper_pri_cfg(struct hclge_vport *vport)
891{
892 struct hclge_dev *hdev = vport->back;
893 u8 ir_u, ir_b, ir_s;
63cbf7a9 894 u32 shaper_para;
84844054
S		 895 int ret;
896
897 ret = hclge_shaper_para_calc(vport->bw_limit, HCLGE_SHAPER_LVL_VF,
898 &ir_b, &ir_u, &ir_s);
899 if (ret)
900 return ret;
901
63cbf7a9
YM		 902 shaper_para = hclge_tm_get_shapping_para(0, 0, 0,
903 HCLGE_SHAPER_BS_U_DEF,
904 HCLGE_SHAPER_BS_S_DEF);
84844054 905 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_C_BUCKET,
63cbf7a9 906 vport->vport_id, shaper_para);
84844054
S		 907 if (ret)
908 return ret;
909
63cbf7a9
YM		 910 shaper_para = hclge_tm_get_shapping_para(ir_b, ir_u, ir_s,
911 HCLGE_SHAPER_BS_U_DEF,
912 HCLGE_SHAPER_BS_S_DEF);
84844054 913 ret = hclge_tm_pri_shapping_cfg(hdev, HCLGE_TM_SHAP_P_BUCKET,
63cbf7a9 914 vport->vport_id, shaper_para);
84844054
S		 915 if (ret)
916 return ret;
917
918 return 0;
919}
920
921static int hclge_tm_pri_vnet_base_shaper_qs_cfg(struct hclge_vport *vport)
922{
923 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
924 struct hclge_dev *hdev = vport->back;
84844054
S		 925 u8 ir_u, ir_b, ir_s;
926 u32 i;
927 int ret;
928
929 for (i = 0; i < kinfo->num_tc; i++) {
84844054
S		 930 ret = hclge_shaper_para_calc(
931 hdev->tm_info.tc_info[i].bw_limit,
932 HCLGE_SHAPER_LVL_QSET,
933 &ir_b, &ir_u, &ir_s);
934 if (ret)
935 return ret;
936 }
937
938 return 0;
939}
940
941static int hclge_tm_pri_vnet_base_shaper_cfg(struct hclge_dev *hdev)
942{
943 struct hclge_vport *vport = hdev->vport;
944 int ret;
945 u32 i;
946
947 /* Need config vport shaper */
948 for (i = 0; i < hdev->num_alloc_vport; i++) {
949 ret = hclge_tm_pri_vnet_base_shaper_pri_cfg(vport);
950 if (ret)
951 return ret;
952
953 ret = hclge_tm_pri_vnet_base_shaper_qs_cfg(vport);
954 if (ret)
955 return ret;
956
957 vport++;
958 }
959
960 return 0;
961}
962
963static int hclge_tm_pri_shaper_cfg(struct hclge_dev *hdev)
964{
965 int ret;
966
967 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
968 ret = hclge_tm_pri_tc_base_shaper_cfg(hdev);
969 if (ret)
970 return ret;
971 } else {
972 ret = hclge_tm_pri_vnet_base_shaper_cfg(hdev);
973 if (ret)
974 return ret;
975 }
976
977 return 0;
978}
979
980static int hclge_tm_pri_tc_base_dwrr_cfg(struct hclge_dev *hdev)
981{
cc9bb43a 982 struct hclge_vport *vport = hdev->vport;
84844054
S		 983 struct hclge_pg_info *pg_info;
984 u8 dwrr;
985 int ret;
cc9bb43a 986 u32 i, k;
84844054
S		 987
988 for (i = 0; i < hdev->tm_info.num_tc; i++) {
989 pg_info =
990 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
991 dwrr = pg_info->tc_dwrr[i];
992
993 ret = hclge_tm_pri_weight_cfg(hdev, i, dwrr);
994 if (ret)
995 return ret;
996
cc9bb43a
YL		 997 for (k = 0; k < hdev->num_alloc_vport; k++) {
998 ret = hclge_tm_qs_weight_cfg(
999 hdev, vport[k].qs_offset + i,
1000 vport[k].dwrr);
1001 if (ret)
1002 return ret;
1003 }
84844054
S		 1004 }
1005
1006 return 0;
1007}
1008
330baff5
YL		 1009static int hclge_tm_ets_tc_dwrr_cfg(struct hclge_dev *hdev)
1010{
1011#define DEFAULT_TC_WEIGHT 1
1012#define DEFAULT_TC_OFFSET 14
1013
1014 struct hclge_ets_tc_weight_cmd *ets_weight;
1015 struct hclge_desc desc;
ebaf1908 1016 unsigned int i;
330baff5
YL		 1017
1018 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ETS_TC_WEIGHT, false);
1019 ets_weight = (struct hclge_ets_tc_weight_cmd *)desc.data;
1020
1021 for (i = 0; i < HNAE3_MAX_TC; i++) {
1022 struct hclge_pg_info *pg_info;
1023
1024 ets_weight->tc_weight[i] = DEFAULT_TC_WEIGHT;
1025
1026 if (!(hdev->hw_tc_map & BIT(i)))
1027 continue;
1028
1029 pg_info =
1030 &hdev->tm_info.pg_info[hdev->tm_info.tc_info[i].pgid];
1031 ets_weight->tc_weight[i] = pg_info->tc_dwrr[i];
1032 }
1033
1034 ets_weight->weight_offset = DEFAULT_TC_OFFSET;
1035
1036 return hclge_cmd_send(&hdev->hw, &desc, 1);
1037}
1038
84844054
S		 1039static int hclge_tm_pri_vnet_base_dwrr_pri_cfg(struct hclge_vport *vport)
1040{
1041 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1042 struct hclge_dev *hdev = vport->back;
1043 int ret;
1044 u8 i;
1045
1046 /* Vf dwrr */
1047 ret = hclge_tm_pri_weight_cfg(hdev, vport->vport_id, vport->dwrr);
1048 if (ret)
1049 return ret;
1050
1051 /* Qset dwrr */
1052 for (i = 0; i < kinfo->num_tc; i++) {
1053 ret = hclge_tm_qs_weight_cfg(
1054 hdev, vport->qs_offset + i,
1055 hdev->tm_info.pg_info[0].tc_dwrr[i]);
1056 if (ret)
1057 return ret;
1058 }
1059
1060 return 0;
1061}
1062
1063static int hclge_tm_pri_vnet_base_dwrr_cfg(struct hclge_dev *hdev)
1064{
1065 struct hclge_vport *vport = hdev->vport;
1066 int ret;
1067 u32 i;
1068
1069 for (i = 0; i < hdev->num_alloc_vport; i++) {
1070 ret = hclge_tm_pri_vnet_base_dwrr_pri_cfg(vport);
1071 if (ret)
1072 return ret;
1073
1074 vport++;
1075 }
1076
1077 return 0;
1078}
1079
1080static int hclge_tm_pri_dwrr_cfg(struct hclge_dev *hdev)
1081{
1082 int ret;
1083
1084 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1085 ret = hclge_tm_pri_tc_base_dwrr_cfg(hdev);
1086 if (ret)
1087 return ret;
330baff5
YL		 1088
1089 if (!hnae3_dev_dcb_supported(hdev))
1090 return 0;
1091
1092 ret = hclge_tm_ets_tc_dwrr_cfg(hdev);
1093 if (ret == -EOPNOTSUPP) {
1094 dev_warn(&hdev->pdev->dev,
1095 "fw %08x does't support ets tc weight cmd\n",
1096 hdev->fw_version);
1097 ret = 0;
1098 }
1099
1100 return ret;
84844054
S		 1101 } else {
1102 ret = hclge_tm_pri_vnet_base_dwrr_cfg(hdev);
1103 if (ret)
1104 return ret;
1105 }
1106
1107 return 0;
1108}
1109
9e5157ba 1110static int hclge_tm_map_cfg(struct hclge_dev *hdev)
84844054
S		 1111{
1112 int ret;
1113
77f255c1
YL		 1114 ret = hclge_up_to_tc_map(hdev);
1115 if (ret)
1116 return ret;
1117
84844054
S		 1118 ret = hclge_tm_pg_to_pri_map(hdev);
1119 if (ret)
1120 return ret;
1121
1122 return hclge_tm_pri_q_qs_cfg(hdev);
1123}
1124
1125static int hclge_tm_shaper_cfg(struct hclge_dev *hdev)
1126{
1127 int ret;
1128
0a5677d3
YL		 1129 ret = hclge_tm_port_shaper_cfg(hdev);
1130 if (ret)
1131 return ret;
1132
84844054
S		 1133 ret = hclge_tm_pg_shaper_cfg(hdev);
1134 if (ret)
1135 return ret;
1136
1137 return hclge_tm_pri_shaper_cfg(hdev);
1138}
1139
1140int hclge_tm_dwrr_cfg(struct hclge_dev *hdev)
1141{
1142 int ret;
1143
1144 ret = hclge_tm_pg_dwrr_cfg(hdev);
1145 if (ret)
1146 return ret;
1147
1148 return hclge_tm_pri_dwrr_cfg(hdev);
1149}
1150
1151static int hclge_tm_lvl2_schd_mode_cfg(struct hclge_dev *hdev)
1152{
1153 int ret;
1154 u8 i;
1155
1156 /* Only being config on TC-Based scheduler mode */
1157 if (hdev->tx_sch_mode == HCLGE_FLAG_VNET_BASE_SCH_MODE)
1158 return 0;
1159
1160 for (i = 0; i < hdev->tm_info.num_pg; i++) {
1161 ret = hclge_tm_pg_schd_mode_cfg(hdev, i);
1162 if (ret)
1163 return ret;
1164 }
1165
1166 return 0;
1167}
1168
1169static int hclge_tm_schd_mode_vnet_base_cfg(struct hclge_vport *vport)
1170{
1171 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
1172 struct hclge_dev *hdev = vport->back;
1173 int ret;
1174 u8 i;
1175
04f25edb
YL		 1176 if (vport->vport_id >= HNAE3_MAX_TC)
1177 return -EINVAL;
1178
84844054
S		 1179 ret = hclge_tm_pri_schd_mode_cfg(hdev, vport->vport_id);
1180 if (ret)
1181 return ret;
1182
1183 for (i = 0; i < kinfo->num_tc; i++) {
cc9bb43a
YL		 1184 u8 sch_mode = hdev->tm_info.tc_info[i].tc_sch_mode;
1185
1186 ret = hclge_tm_qs_schd_mode_cfg(hdev, vport->qs_offset + i,
1187 sch_mode);
84844054
S		 1188 if (ret)
1189 return ret;
1190 }
1191
1192 return 0;
1193}
1194
1195static int hclge_tm_lvl34_schd_mode_cfg(struct hclge_dev *hdev)
1196{
1197 struct hclge_vport *vport = hdev->vport;
1198 int ret;
cc9bb43a 1199 u8 i, k;
84844054
S		 1200
1201 if (hdev->tx_sch_mode == HCLGE_FLAG_TC_BASE_SCH_MODE) {
1202 for (i = 0; i < hdev->tm_info.num_tc; i++) {
1203 ret = hclge_tm_pri_schd_mode_cfg(hdev, i);
1204 if (ret)
1205 return ret;
1206
cc9bb43a
YL		 1207 for (k = 0; k < hdev->num_alloc_vport; k++) {
1208 ret = hclge_tm_qs_schd_mode_cfg(
1209 hdev, vport[k].qs_offset + i,
1210 HCLGE_SCH_MODE_DWRR);
1211 if (ret)
1212 return ret;
1213 }
84844054
S		 1214 }
1215 } else {
1216 for (i = 0; i < hdev->num_alloc_vport; i++) {
1217 ret = hclge_tm_schd_mode_vnet_base_cfg(vport);
1218 if (ret)
1219 return ret;
1220
1221 vport++;
1222 }
1223 }
1224
1225 return 0;
1226}
1227
9e5157ba 1228static int hclge_tm_schd_mode_hw(struct hclge_dev *hdev)
84844054
S		 1229{
1230 int ret;
1231
1232 ret = hclge_tm_lvl2_schd_mode_cfg(hdev);
1233 if (ret)
1234 return ret;
1235
1236 return hclge_tm_lvl34_schd_mode_cfg(hdev);
1237}
1238
9e5157ba 1239int hclge_tm_schd_setup_hw(struct hclge_dev *hdev)
84844054
S		 1240{
1241 int ret;
1242
1243 /* Cfg tm mapping */
1244 ret = hclge_tm_map_cfg(hdev);
1245 if (ret)
1246 return ret;
1247
1248 /* Cfg tm shaper */
1249 ret = hclge_tm_shaper_cfg(hdev);
1250 if (ret)
1251 return ret;
1252
1253 /* Cfg dwrr */
1254 ret = hclge_tm_dwrr_cfg(hdev);
1255 if (ret)
1256 return ret;
1257
1258 /* Cfg schd mode for each level schd */
1259 return hclge_tm_schd_mode_hw(hdev);
1260}
1261
e98d7183 1262static int hclge_pause_param_setup_hw(struct hclge_dev *hdev)
18838d0c
FL		 1263{
1264 struct hclge_mac *mac = &hdev->hw.mac;
1265
e98d7183 1266 return hclge_pause_param_cfg(hdev, mac->mac_addr,
9b2f3477
WL		 1267 HCLGE_DEFAULT_PAUSE_TRANS_GAP,
1268 HCLGE_DEFAULT_PAUSE_TRANS_TIME);
18838d0c
FL		 1269}
1270
9dc2145d
YL		 1271static int hclge_pfc_setup_hw(struct hclge_dev *hdev)
1272{
1273 u8 enable_bitmap = 0;
1274
1275 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
1276 enable_bitmap = HCLGE_TX_MAC_PAUSE_EN_MSK |
1277 HCLGE_RX_MAC_PAUSE_EN_MSK;
1278
1279 return hclge_pfc_pause_en_cfg(hdev, enable_bitmap,
d3ad430a 1280 hdev->tm_info.pfc_en);
9dc2145d
YL		 1281}
1282
67bf2541
YL		 1283/* Each Tc has a 1024 queue sets to backpress, it divides to
1284 * 32 group, each group contains 32 queue sets, which can be
1285 * represented by u32 bitmap.
1286 */
1287static int hclge_bp_setup_hw(struct hclge_dev *hdev, u8 tc)
1288{
e8ccbb7d 1289 int i;
67bf2541
YL		 1290
1291 for (i = 0; i < HCLGE_BP_GRP_NUM; i++) {
e8ccbb7d
YL		 1292 u32 qs_bitmap = 0;
1293 int k, ret;
67bf2541
YL		 1294
1295 for (k = 0; k < hdev->num_alloc_vport; k++) {
e8ccbb7d 1296 struct hclge_vport *vport = &hdev->vport[k];
67bf2541
YL		 1297 u16 qs_id = vport->qs_offset + tc;
1298 u8 grp, sub_grp;
1299
e4e87715
PL		 1300 grp = hnae3_get_field(qs_id, HCLGE_BP_GRP_ID_M,
1301 HCLGE_BP_GRP_ID_S);
1302 sub_grp = hnae3_get_field(qs_id, HCLGE_BP_SUB_GRP_ID_M,
1303 HCLGE_BP_SUB_GRP_ID_S);
67bf2541
YL		 1304 if (i == grp)
1305 qs_bitmap |= (1 << sub_grp);
67bf2541
YL		 1306 }
1307
1308 ret = hclge_tm_qs_bp_cfg(hdev, tc, i, qs_bitmap);
1309 if (ret)
1310 return ret;
1311 }
1312
1313 return 0;
1314}
1315
9dc2145d
YL		 1316static int hclge_mac_pause_setup_hw(struct hclge_dev *hdev)
1317{
1318 bool tx_en, rx_en;
1319
1320 switch (hdev->tm_info.fc_mode) {
1321 case HCLGE_FC_NONE:
1322 tx_en = false;
1323 rx_en = false;
1324 break;
1325 case HCLGE_FC_RX_PAUSE:
1326 tx_en = false;
1327 rx_en = true;
1328 break;
1329 case HCLGE_FC_TX_PAUSE:
1330 tx_en = true;
1331 rx_en = false;
1332 break;
1333 case HCLGE_FC_FULL:
1334 tx_en = true;
1335 rx_en = true;
1336 break;
6d0ec65c
YL		 1337 case HCLGE_FC_PFC:
1338 tx_en = false;
1339 rx_en = false;
1340 break;
9dc2145d
YL		 1341 default:
1342 tx_en = true;
1343 rx_en = true;
1344 }
1345
1346 return hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
1347}
1348
73fc9c48
HT		 1349static int hclge_tm_bp_setup(struct hclge_dev *hdev)
1350{
1351 int ret = 0;
1352 int i;
1353
1354 for (i = 0; i < hdev->tm_info.num_tc; i++) {
1355 ret = hclge_bp_setup_hw(hdev, i);
1356 if (ret)
1357 return ret;
1358 }
1359
1360 return ret;
1361}
1362
44e59e37 1363int hclge_pause_setup_hw(struct hclge_dev *hdev, bool init)
84844054 1364{
84844054 1365 int ret;
84844054 1366
e98d7183
FL		 1367 ret = hclge_pause_param_setup_hw(hdev);
1368 if (ret)
1369 return ret;
18838d0c 1370
6d0ec65c
YL		 1371 ret = hclge_mac_pause_setup_hw(hdev);
1372 if (ret)
1373 return ret;
84844054 1374
9dc2145d 1375 /* Only DCB-supported dev supports qset back pressure and pfc cmd */
2daf4a65
YL		 1376 if (!hnae3_dev_dcb_supported(hdev))
1377 return 0;
1378
44e59e37
YL		 1379 /* GE MAC does not support PFC, when driver is initializing and MAC
1380 * is in GE Mode, ignore the error here, otherwise initialization
1381 * will fail.
1382 */
9dc2145d 1383 ret = hclge_pfc_setup_hw(hdev);
44e59e37
YL		 1384 if (init && ret == -EOPNOTSUPP)
1385 dev_warn(&hdev->pdev->dev, "GE MAC does not support pfc\n");
fba2efda
HT		 1386 else if (ret) {
1387 dev_err(&hdev->pdev->dev, "config pfc failed! ret = %d\n",
1388 ret);
44e59e37 1389 return ret;
fba2efda 1390 }
9dc2145d 1391
73fc9c48 1392 return hclge_tm_bp_setup(hdev);
77f255c1
YL		 1393}
1394
e432abfb 1395void hclge_tm_prio_tc_info_update(struct hclge_dev *hdev, u8 *prio_tc)
77f255c1
YL		 1396{
1397 struct hclge_vport *vport = hdev->vport;
1398 struct hnae3_knic_private_info *kinfo;
1399 u32 i, k;
1400
1401 for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
77f255c1
YL		 1402 hdev->tm_info.prio_tc[i] = prio_tc[i];
1403
1404 for (k = 0; k < hdev->num_alloc_vport; k++) {
1405 kinfo = &vport[k].nic.kinfo;
1406 kinfo->prio_tc[i] = prio_tc[i];
1407 }
1408 }
77f255c1
YL		 1409}
1410
e432abfb 1411void hclge_tm_schd_info_update(struct hclge_dev *hdev, u8 num_tc)
77f255c1 1412{
9b2f3477
WL		 1413 u8 bit_map = 0;
1414 u8 i;
77f255c1
YL		 1415
1416 hdev->tm_info.num_tc = num_tc;
1417
1418 for (i = 0; i < hdev->tm_info.num_tc; i++)
1419 bit_map |= BIT(i);
1420
1421 if (!bit_map) {
1422 bit_map = 1;
1423 hdev->tm_info.num_tc = 1;
1424 }
1425
1426 hdev->hw_tc_map = bit_map;
1427
1428 hclge_tm_schd_info_init(hdev);
84844054
S		 1429}
1430
ae179b2f
YL		 1431void hclge_tm_pfc_info_update(struct hclge_dev *hdev)
1432{
1433 /* DCB is enabled if we have more than 1 TC or pfc_en is
1434 * non-zero.
1435 */
1436 if (hdev->tm_info.num_tc > 1 || hdev->tm_info.pfc_en)
1437 hdev->flag |= HCLGE_FLAG_DCB_ENABLE;
1438 else
1439 hdev->flag &= ~HCLGE_FLAG_DCB_ENABLE;
1440
1441 hclge_pfc_info_init(hdev);
1442}
1443
44e59e37 1444int hclge_tm_init_hw(struct hclge_dev *hdev, bool init)
84844054
S		 1445{
1446 int ret;
1447
1448 if ((hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE) &&
1449 (hdev->tx_sch_mode != HCLGE_FLAG_VNET_BASE_SCH_MODE))
1450 return -ENOTSUPP;
1451
1452 ret = hclge_tm_schd_setup_hw(hdev);
1453 if (ret)
1454 return ret;
1455
44e59e37 1456 ret = hclge_pause_setup_hw(hdev, init);
84844054
S		 1457 if (ret)
1458 return ret;
1459
1460 return 0;
1461}
1462
1463int hclge_tm_schd_init(struct hclge_dev *hdev)
1464{
7979a223
YL		 1465 /* fc_mode is HCLGE_FC_FULL on reset */
1466 hdev->tm_info.fc_mode = HCLGE_FC_FULL;
1467 hdev->fc_mode_last_time = hdev->tm_info.fc_mode;
84844054 1468
b6872fd3
YL		 1469 if (hdev->tx_sch_mode != HCLGE_FLAG_TC_BASE_SCH_MODE &&
1470 hdev->tm_info.num_pg != 1)
1471 return -EINVAL;
1472
1473 hclge_tm_schd_info_init(hdev);
84844054 1474
44e59e37 1475 return hclge_tm_init_hw(hdev, true);
84844054 1476}
672ad0ed
HT		 1477
1478int hclge_tm_vport_map_update(struct hclge_dev *hdev)
1479{
1480 struct hclge_vport *vport = hdev->vport;
1481 int ret;
1482
1483 hclge_tm_vport_tc_info_update(vport);
1484
1485 ret = hclge_vport_q_to_qs_map(hdev, vport);
1486 if (ret)
1487 return ret;
1488
1489 if (!(hdev->flag & HCLGE_FLAG_DCB_ENABLE))
1490 return 0;
1491
1492 return hclge_tm_bp_setup(hdev);
1493}
Linux 6.x block layer and io_uring tree(s)