Commit | Line | Data |
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2ef17216 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
d71d8381 | 2 | // Copyright (c) 2016-2017 Hisilicon Limited. |
46a3df9f S |
3 | |
4 | #ifndef __HCLGE_MAIN_H | |
5 | #define __HCLGE_MAIN_H | |
6 | #include <linux/fs.h> | |
7 | #include <linux/types.h> | |
8 | #include <linux/phy.h> | |
dc8131d8 | 9 | #include <linux/if_vlan.h> |
a6345787 | 10 | #include <linux/kfifo.h> |
dc8131d8 | 11 | |
46a3df9f S |
12 | #include "hclge_cmd.h" |
13 | #include "hnae3.h" | |
14 | ||
3c7624d8 | 15 | #define HCLGE_MOD_VERSION "1.0" |
46a3df9f S |
16 | #define HCLGE_DRIVER_NAME "hclge" |
17 | ||
39932473 JS |
18 | #define HCLGE_MAX_PF_NUM 8 |
19 | ||
d174ea75 | 20 | #define HCLGE_RD_FIRST_STATS_NUM 2 |
21 | #define HCLGE_RD_OTHER_STATS_NUM 4 | |
22 | ||
46a3df9f S |
23 | #define HCLGE_INVALID_VPORT 0xffff |
24 | ||
46a3df9f S |
25 | #define HCLGE_PF_CFG_BLOCK_SIZE 32 |
26 | #define HCLGE_PF_CFG_DESC_NUM \ | |
27 | (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES) | |
28 | ||
29 | #define HCLGE_VECTOR_REG_BASE 0x20000 | |
466b0c00 | 30 | #define HCLGE_MISC_VECTOR_REG_BASE 0x20400 |
46a3df9f S |
31 | |
32 | #define HCLGE_VECTOR_REG_OFFSET 0x4 | |
33 | #define HCLGE_VECTOR_VF_OFFSET 0x100000 | |
34 | ||
ea4750ca JS |
35 | #define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000 |
36 | #define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004 | |
37 | #define HCLGE_CMDQ_TX_DEPTH_REG 0x27008 | |
38 | #define HCLGE_CMDQ_TX_TAIL_REG 0x27010 | |
39 | #define HCLGE_CMDQ_TX_HEAD_REG 0x27014 | |
40 | #define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018 | |
41 | #define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C | |
42 | #define HCLGE_CMDQ_RX_DEPTH_REG 0x27020 | |
43 | #define HCLGE_CMDQ_RX_TAIL_REG 0x27024 | |
44 | #define HCLGE_CMDQ_RX_HEAD_REG 0x27028 | |
45 | #define HCLGE_CMDQ_INTR_SRC_REG 0x27100 | |
46 | #define HCLGE_CMDQ_INTR_STS_REG 0x27104 | |
47 | #define HCLGE_CMDQ_INTR_EN_REG 0x27108 | |
48 | #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C | |
49 | ||
50 | /* bar registers for common func */ | |
51 | #define HCLGE_VECTOR0_OTER_EN_REG 0x20600 | |
52 | #define HCLGE_RAS_OTHER_STS_REG 0x20B00 | |
53 | #define HCLGE_FUNC_RESET_STS_REG 0x20C00 | |
54 | #define HCLGE_GRO_EN_REG 0x28000 | |
55 | ||
56 | /* bar registers for rcb */ | |
57 | #define HCLGE_RING_RX_ADDR_L_REG 0x80000 | |
58 | #define HCLGE_RING_RX_ADDR_H_REG 0x80004 | |
59 | #define HCLGE_RING_RX_BD_NUM_REG 0x80008 | |
60 | #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C | |
61 | #define HCLGE_RING_RX_MERGE_EN_REG 0x80014 | |
62 | #define HCLGE_RING_RX_TAIL_REG 0x80018 | |
63 | #define HCLGE_RING_RX_HEAD_REG 0x8001C | |
64 | #define HCLGE_RING_RX_FBD_NUM_REG 0x80020 | |
65 | #define HCLGE_RING_RX_OFFSET_REG 0x80024 | |
66 | #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028 | |
67 | #define HCLGE_RING_RX_STASH_REG 0x80030 | |
68 | #define HCLGE_RING_RX_BD_ERR_REG 0x80034 | |
69 | #define HCLGE_RING_TX_ADDR_L_REG 0x80040 | |
70 | #define HCLGE_RING_TX_ADDR_H_REG 0x80044 | |
71 | #define HCLGE_RING_TX_BD_NUM_REG 0x80048 | |
72 | #define HCLGE_RING_TX_PRIORITY_REG 0x8004C | |
73 | #define HCLGE_RING_TX_TC_REG 0x80050 | |
74 | #define HCLGE_RING_TX_MERGE_EN_REG 0x80054 | |
75 | #define HCLGE_RING_TX_TAIL_REG 0x80058 | |
76 | #define HCLGE_RING_TX_HEAD_REG 0x8005C | |
77 | #define HCLGE_RING_TX_FBD_NUM_REG 0x80060 | |
78 | #define HCLGE_RING_TX_OFFSET_REG 0x80064 | |
79 | #define HCLGE_RING_TX_EBD_NUM_REG 0x80068 | |
80 | #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070 | |
81 | #define HCLGE_RING_TX_BD_ERR_REG 0x80074 | |
82 | #define HCLGE_RING_EN_REG 0x80090 | |
83 | ||
84 | /* bar registers for tqp interrupt */ | |
85 | #define HCLGE_TQP_INTR_CTRL_REG 0x20000 | |
86 | #define HCLGE_TQP_INTR_GL0_REG 0x20100 | |
87 | #define HCLGE_TQP_INTR_GL1_REG 0x20200 | |
88 | #define HCLGE_TQP_INTR_GL2_REG 0x20300 | |
89 | #define HCLGE_TQP_INTR_RL_REG 0x20900 | |
90 | ||
46a3df9f | 91 | #define HCLGE_RSS_IND_TBL_SIZE 512 |
5392902d | 92 | #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0) |
46a3df9f S |
93 | #define HCLGE_RSS_KEY_SIZE 40 |
94 | #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0 | |
95 | #define HCLGE_RSS_HASH_ALGO_SIMPLE 1 | |
96 | #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2 | |
c79301d8 | 97 | #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0) |
46a3df9f S |
98 | #define HCLGE_RSS_CFG_TBL_NUM \ |
99 | (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE) | |
100 | ||
f7db940a L |
101 | #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0) |
102 | #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0) | |
103 | #define HCLGE_D_PORT_BIT BIT(0) | |
104 | #define HCLGE_S_PORT_BIT BIT(1) | |
105 | #define HCLGE_D_IP_BIT BIT(2) | |
106 | #define HCLGE_S_IP_BIT BIT(3) | |
107 | #define HCLGE_V_TAG_BIT BIT(4) | |
108 | ||
46a3df9f S |
109 | #define HCLGE_RSS_TC_SIZE_0 1 |
110 | #define HCLGE_RSS_TC_SIZE_1 2 | |
111 | #define HCLGE_RSS_TC_SIZE_2 4 | |
112 | #define HCLGE_RSS_TC_SIZE_3 8 | |
113 | #define HCLGE_RSS_TC_SIZE_4 16 | |
114 | #define HCLGE_RSS_TC_SIZE_5 32 | |
115 | #define HCLGE_RSS_TC_SIZE_6 64 | |
116 | #define HCLGE_RSS_TC_SIZE_7 128 | |
117 | ||
39932473 JS |
118 | #define HCLGE_UMV_TBL_SIZE 3072 |
119 | #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \ | |
120 | (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM) | |
121 | ||
e8df45c2 | 122 | #define HCLGE_TQP_RESET_TRY_TIMES 200 |
46a3df9f S |
123 | |
124 | #define HCLGE_PHY_PAGE_MDIX 0 | |
125 | #define HCLGE_PHY_PAGE_COPPER 0 | |
126 | ||
127 | /* Page Selection Reg. */ | |
128 | #define HCLGE_PHY_PAGE_REG 22 | |
129 | ||
130 | /* Copper Specific Control Register */ | |
131 | #define HCLGE_PHY_CSC_REG 16 | |
132 | ||
133 | /* Copper Specific Status Register */ | |
134 | #define HCLGE_PHY_CSS_REG 17 | |
135 | ||
a10829c4 | 136 | #define HCLGE_PHY_MDIX_CTRL_S 5 |
5392902d | 137 | #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5) |
46a3df9f | 138 | |
a10829c4 JS |
139 | #define HCLGE_PHY_MDIX_STATUS_B 6 |
140 | #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11 | |
46a3df9f | 141 | |
9027d043 GL |
142 | #define HCLGE_GET_DFX_REG_TYPE_CNT 4 |
143 | ||
5f6ea83f PL |
144 | /* Factor used to calculate offset and bitmap of VF num */ |
145 | #define HCLGE_VF_NUM_PER_CMD 64 | |
5f6ea83f | 146 | |
11732868 JS |
147 | enum HLCGE_PORT_TYPE { |
148 | HOST_PORT, | |
149 | NETWORK_PORT | |
150 | }; | |
151 | ||
dd2956ea YM |
152 | #define PF_VPORT_ID 0 |
153 | ||
11732868 JS |
154 | #define HCLGE_PF_ID_S 0 |
155 | #define HCLGE_PF_ID_M GENMASK(2, 0) | |
156 | #define HCLGE_VF_ID_S 3 | |
157 | #define HCLGE_VF_ID_M GENMASK(10, 3) | |
158 | #define HCLGE_PORT_TYPE_B 11 | |
159 | #define HCLGE_NETWORK_PORT_ID_S 0 | |
160 | #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0) | |
161 | ||
4ed340ab | 162 | /* Reset related Registers */ |
6dd22bbc | 163 | #define HCLGE_PF_OTHER_INT_REG 0x20600 |
4ed340ab | 164 | #define HCLGE_MISC_RESET_STS_REG 0x20700 |
9ca8d1a7 | 165 | #define HCLGE_MISC_VECTOR_INT_STS 0x20800 |
4ed340ab | 166 | #define HCLGE_GLOBAL_RESET_REG 0x20A00 |
f8a91784 JS |
167 | #define HCLGE_GLOBAL_RESET_BIT 0 |
168 | #define HCLGE_CORE_RESET_BIT 1 | |
65e41e7e | 169 | #define HCLGE_IMP_RESET_BIT 2 |
74e78d6b | 170 | #define HCLGE_RESET_INT_M GENMASK(7, 5) |
4ed340ab L |
171 | #define HCLGE_FUN_RST_ING 0x20C00 |
172 | #define HCLGE_FUN_RST_ING_B 0 | |
173 | ||
174 | /* Vector0 register bits define */ | |
175 | #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5 | |
176 | #define HCLGE_VECTOR0_CORERESET_INT_B 6 | |
177 | #define HCLGE_VECTOR0_IMPRESET_INT_B 7 | |
178 | ||
c1a81619 SM |
179 | /* Vector0 interrupt CMDQ event source register(RW) */ |
180 | #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100 | |
181 | /* CMDQ register bits for RX event(=MBX event) */ | |
182 | #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1 | |
183 | ||
6dd22bbc | 184 | #define HCLGE_VECTOR0_IMP_RESET_INT_B 1 |
a83d2961 WL |
185 | #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U |
186 | #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U | |
6dd22bbc | 187 | |
2866ccb2 | 188 | #define HCLGE_MAC_DEFAULT_FRAME \ |
a0b43717 | 189 | (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN) |
2866ccb2 FL |
190 | #define HCLGE_MAC_MIN_FRAME 64 |
191 | #define HCLGE_MAC_MAX_FRAME 9728 | |
192 | ||
0979aa0b FL |
193 | #define HCLGE_SUPPORT_1G_BIT BIT(0) |
194 | #define HCLGE_SUPPORT_10G_BIT BIT(1) | |
195 | #define HCLGE_SUPPORT_25G_BIT BIT(2) | |
196 | #define HCLGE_SUPPORT_50G_BIT BIT(3) | |
197 | #define HCLGE_SUPPORT_100G_BIT BIT(4) | |
88d10bd6 JS |
198 | /* to be compatible with exsit board */ |
199 | #define HCLGE_SUPPORT_40G_BIT BIT(5) | |
f18635d5 JS |
200 | #define HCLGE_SUPPORT_100M_BIT BIT(6) |
201 | #define HCLGE_SUPPORT_10M_BIT BIT(7) | |
202 | #define HCLGE_SUPPORT_GE \ | |
203 | (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT) | |
0979aa0b | 204 | |
46a3df9f S |
205 | enum HCLGE_DEV_STATE { |
206 | HCLGE_STATE_REINITING, | |
207 | HCLGE_STATE_DOWN, | |
208 | HCLGE_STATE_DISABLED, | |
209 | HCLGE_STATE_REMOVING, | |
bd9109c9 | 210 | HCLGE_STATE_NIC_REGISTERED, |
2a0bfc36 | 211 | HCLGE_STATE_ROCE_REGISTERED, |
46a3df9f | 212 | HCLGE_STATE_SERVICE_INITED, |
cb1b9f77 SM |
213 | HCLGE_STATE_RST_SERVICE_SCHED, |
214 | HCLGE_STATE_RST_HANDLING, | |
c1a81619 | 215 | HCLGE_STATE_MBX_SERVICE_SCHED, |
46a3df9f | 216 | HCLGE_STATE_MBX_HANDLING, |
c5f65480 | 217 | HCLGE_STATE_STATISTICS_UPDATING, |
8d40854f | 218 | HCLGE_STATE_CMD_DISABLE, |
1c6dfe6f | 219 | HCLGE_STATE_LINK_UPDATING, |
c631c696 | 220 | HCLGE_STATE_PROMISC_CHANGED, |
d5432455 | 221 | HCLGE_STATE_RST_FAIL, |
46a3df9f S |
222 | HCLGE_STATE_MAX |
223 | }; | |
224 | ||
ca1d7669 SM |
225 | enum hclge_evt_cause { |
226 | HCLGE_VECTOR0_EVENT_RST, | |
227 | HCLGE_VECTOR0_EVENT_MBX, | |
f6162d44 | 228 | HCLGE_VECTOR0_EVENT_ERR, |
ca1d7669 SM |
229 | HCLGE_VECTOR0_EVENT_OTHER, |
230 | }; | |
231 | ||
46a3df9f | 232 | enum HCLGE_MAC_SPEED { |
5d497936 | 233 | HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */ |
46a3df9f S |
234 | HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */ |
235 | HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */ | |
236 | HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */ | |
237 | HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */ | |
238 | HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */ | |
239 | HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */ | |
240 | HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */ | |
241 | HCLGE_MAC_SPEED_100G = 100000 /* 100000 Mbps = 100 Gbps */ | |
242 | }; | |
243 | ||
244 | enum HCLGE_MAC_DUPLEX { | |
245 | HCLGE_MAC_HALF, | |
246 | HCLGE_MAC_FULL | |
247 | }; | |
248 | ||
88d10bd6 JS |
249 | #define QUERY_SFP_SPEED 0 |
250 | #define QUERY_ACTIVE_SPEED 1 | |
251 | ||
46a3df9f | 252 | struct hclge_mac { |
ded45d40 | 253 | u8 mac_id; |
46a3df9f S |
254 | u8 phy_addr; |
255 | u8 flag; | |
88d10bd6 | 256 | u8 media_type; /* port media type, e.g. fibre/copper/backplane */ |
46a3df9f S |
257 | u8 mac_addr[ETH_ALEN]; |
258 | u8 autoneg; | |
259 | u8 duplex; | |
88d10bd6 JS |
260 | u8 support_autoneg; |
261 | u8 speed_type; /* 0: sfp speed, 1: active speed */ | |
46a3df9f | 262 | u32 speed; |
ee9e4424 | 263 | u32 max_speed; |
88d10bd6 JS |
264 | u32 speed_ability; /* speed ability supported by current media */ |
265 | u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */ | |
7e6ec914 JS |
266 | u32 fec_mode; /* active fec mode */ |
267 | u32 user_fec_mode; | |
268 | u32 fec_ability; | |
269 | int link; /* store the link status of mac & phy (if phy exit) */ | |
46a3df9f S |
270 | struct phy_device *phydev; |
271 | struct mii_bus *mdio_bus; | |
272 | phy_interface_t phy_if; | |
0979aa0b FL |
273 | __ETHTOOL_DECLARE_LINK_MODE_MASK(supported); |
274 | __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising); | |
46a3df9f S |
275 | }; |
276 | ||
277 | struct hclge_hw { | |
278 | void __iomem *io_base; | |
279 | struct hclge_mac mac; | |
280 | int num_vec; | |
281 | struct hclge_cmq cmq; | |
46a3df9f S |
282 | }; |
283 | ||
284 | /* TQP stats */ | |
285 | struct hlcge_tqp_stats { | |
286 | /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */ | |
287 | u64 rcb_tx_ring_pktnum_rcd; /* 32bit */ | |
288 | /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */ | |
289 | u64 rcb_rx_ring_pktnum_rcd; /* 32bit */ | |
290 | }; | |
291 | ||
292 | struct hclge_tqp { | |
fdace1bc JS |
293 | /* copy of device pointer from pci_dev, |
294 | * used when perform DMA mapping | |
295 | */ | |
296 | struct device *dev; | |
46a3df9f S |
297 | struct hnae3_queue q; |
298 | struct hlcge_tqp_stats tqp_stats; | |
299 | u16 index; /* Global index in a NIC controller */ | |
300 | ||
301 | bool alloced; | |
302 | }; | |
303 | ||
304 | enum hclge_fc_mode { | |
305 | HCLGE_FC_NONE, | |
306 | HCLGE_FC_RX_PAUSE, | |
307 | HCLGE_FC_TX_PAUSE, | |
308 | HCLGE_FC_FULL, | |
309 | HCLGE_FC_PFC, | |
310 | HCLGE_FC_DEFAULT | |
311 | }; | |
312 | ||
ed8fb4b2 JS |
313 | enum hclge_link_fail_code { |
314 | HCLGE_LF_NORMAL, | |
315 | HCLGE_LF_REF_CLOCK_LOST, | |
316 | HCLGE_LF_XSFP_TX_DISABLE, | |
317 | HCLGE_LF_XSFP_ABSENT, | |
318 | }; | |
319 | ||
fac24df7 JS |
320 | #define HCLGE_LINK_STATUS_DOWN 0 |
321 | #define HCLGE_LINK_STATUS_UP 1 | |
322 | ||
46a3df9f S |
323 | #define HCLGE_PG_NUM 4 |
324 | #define HCLGE_SCH_MODE_SP 0 | |
325 | #define HCLGE_SCH_MODE_DWRR 1 | |
326 | struct hclge_pg_info { | |
327 | u8 pg_id; | |
328 | u8 pg_sch_mode; /* 0: sp; 1: dwrr */ | |
329 | u8 tc_bit_map; | |
330 | u32 bw_limit; | |
331 | u8 tc_dwrr[HNAE3_MAX_TC]; | |
332 | }; | |
333 | ||
334 | struct hclge_tc_info { | |
335 | u8 tc_id; | |
336 | u8 tc_sch_mode; /* 0: sp; 1: dwrr */ | |
46a3df9f S |
337 | u8 pgid; |
338 | u32 bw_limit; | |
339 | }; | |
340 | ||
341 | struct hclge_cfg { | |
342 | u8 vmdq_vport_num; | |
343 | u8 tc_num; | |
344 | u16 tqp_desc_num; | |
345 | u16 rx_buf_len; | |
0e7a40cd | 346 | u16 rss_size_max; |
46a3df9f S |
347 | u8 phy_addr; |
348 | u8 media_type; | |
349 | u8 mac_addr[ETH_ALEN]; | |
350 | u8 default_speed; | |
351 | u32 numa_node_map; | |
0979aa0b | 352 | u8 speed_ability; |
39932473 | 353 | u16 umv_space; |
46a3df9f S |
354 | }; |
355 | ||
356 | struct hclge_tm_info { | |
357 | u8 num_tc; | |
358 | u8 num_pg; /* It must be 1 if vNET-Base schd */ | |
359 | u8 pg_dwrr[HCLGE_PG_NUM]; | |
c5795c53 | 360 | u8 prio_tc[HNAE3_MAX_USER_PRIO]; |
46a3df9f S |
361 | struct hclge_pg_info pg_info[HCLGE_PG_NUM]; |
362 | struct hclge_tc_info tc_info[HNAE3_MAX_TC]; | |
363 | enum hclge_fc_mode fc_mode; | |
364 | u8 hw_pfc_map; /* Allow for packet drop or not on this TC */ | |
d3ad430a | 365 | u8 pfc_en; /* PFC enabled or not for user priority */ |
46a3df9f S |
366 | }; |
367 | ||
368 | struct hclge_comm_stats_str { | |
369 | char desc[ETH_GSTRING_LEN]; | |
370 | unsigned long offset; | |
371 | }; | |
372 | ||
46a3df9f S |
373 | /* mac stats ,opcode id: 0x0032 */ |
374 | struct hclge_mac_stats { | |
375 | u64 mac_tx_mac_pause_num; | |
376 | u64 mac_rx_mac_pause_num; | |
377 | u64 mac_tx_pfc_pri0_pkt_num; | |
378 | u64 mac_tx_pfc_pri1_pkt_num; | |
379 | u64 mac_tx_pfc_pri2_pkt_num; | |
380 | u64 mac_tx_pfc_pri3_pkt_num; | |
381 | u64 mac_tx_pfc_pri4_pkt_num; | |
382 | u64 mac_tx_pfc_pri5_pkt_num; | |
383 | u64 mac_tx_pfc_pri6_pkt_num; | |
384 | u64 mac_tx_pfc_pri7_pkt_num; | |
385 | u64 mac_rx_pfc_pri0_pkt_num; | |
386 | u64 mac_rx_pfc_pri1_pkt_num; | |
387 | u64 mac_rx_pfc_pri2_pkt_num; | |
388 | u64 mac_rx_pfc_pri3_pkt_num; | |
389 | u64 mac_rx_pfc_pri4_pkt_num; | |
390 | u64 mac_rx_pfc_pri5_pkt_num; | |
391 | u64 mac_rx_pfc_pri6_pkt_num; | |
392 | u64 mac_rx_pfc_pri7_pkt_num; | |
393 | u64 mac_tx_total_pkt_num; | |
394 | u64 mac_tx_total_oct_num; | |
395 | u64 mac_tx_good_pkt_num; | |
396 | u64 mac_tx_bad_pkt_num; | |
397 | u64 mac_tx_good_oct_num; | |
398 | u64 mac_tx_bad_oct_num; | |
399 | u64 mac_tx_uni_pkt_num; | |
400 | u64 mac_tx_multi_pkt_num; | |
401 | u64 mac_tx_broad_pkt_num; | |
402 | u64 mac_tx_undersize_pkt_num; | |
200a88c6 | 403 | u64 mac_tx_oversize_pkt_num; |
46a3df9f S |
404 | u64 mac_tx_64_oct_pkt_num; |
405 | u64 mac_tx_65_127_oct_pkt_num; | |
406 | u64 mac_tx_128_255_oct_pkt_num; | |
407 | u64 mac_tx_256_511_oct_pkt_num; | |
408 | u64 mac_tx_512_1023_oct_pkt_num; | |
409 | u64 mac_tx_1024_1518_oct_pkt_num; | |
91f384f6 JS |
410 | u64 mac_tx_1519_2047_oct_pkt_num; |
411 | u64 mac_tx_2048_4095_oct_pkt_num; | |
412 | u64 mac_tx_4096_8191_oct_pkt_num; | |
dbecc779 XW |
413 | u64 rsv0; |
414 | u64 mac_tx_8192_9216_oct_pkt_num; | |
415 | u64 mac_tx_9217_12287_oct_pkt_num; | |
91f384f6 JS |
416 | u64 mac_tx_12288_16383_oct_pkt_num; |
417 | u64 mac_tx_1519_max_good_oct_pkt_num; | |
418 | u64 mac_tx_1519_max_bad_oct_pkt_num; | |
419 | ||
46a3df9f S |
420 | u64 mac_rx_total_pkt_num; |
421 | u64 mac_rx_total_oct_num; | |
422 | u64 mac_rx_good_pkt_num; | |
423 | u64 mac_rx_bad_pkt_num; | |
424 | u64 mac_rx_good_oct_num; | |
425 | u64 mac_rx_bad_oct_num; | |
426 | u64 mac_rx_uni_pkt_num; | |
427 | u64 mac_rx_multi_pkt_num; | |
428 | u64 mac_rx_broad_pkt_num; | |
429 | u64 mac_rx_undersize_pkt_num; | |
200a88c6 | 430 | u64 mac_rx_oversize_pkt_num; |
46a3df9f S |
431 | u64 mac_rx_64_oct_pkt_num; |
432 | u64 mac_rx_65_127_oct_pkt_num; | |
433 | u64 mac_rx_128_255_oct_pkt_num; | |
434 | u64 mac_rx_256_511_oct_pkt_num; | |
435 | u64 mac_rx_512_1023_oct_pkt_num; | |
436 | u64 mac_rx_1024_1518_oct_pkt_num; | |
91f384f6 JS |
437 | u64 mac_rx_1519_2047_oct_pkt_num; |
438 | u64 mac_rx_2048_4095_oct_pkt_num; | |
439 | u64 mac_rx_4096_8191_oct_pkt_num; | |
dbecc779 XW |
440 | u64 rsv1; |
441 | u64 mac_rx_8192_9216_oct_pkt_num; | |
442 | u64 mac_rx_9217_12287_oct_pkt_num; | |
91f384f6 JS |
443 | u64 mac_rx_12288_16383_oct_pkt_num; |
444 | u64 mac_rx_1519_max_good_oct_pkt_num; | |
445 | u64 mac_rx_1519_max_bad_oct_pkt_num; | |
46a3df9f | 446 | |
a6c51c26 JS |
447 | u64 mac_tx_fragment_pkt_num; |
448 | u64 mac_tx_undermin_pkt_num; | |
449 | u64 mac_tx_jabber_pkt_num; | |
450 | u64 mac_tx_err_all_pkt_num; | |
451 | u64 mac_tx_from_app_good_pkt_num; | |
452 | u64 mac_tx_from_app_bad_pkt_num; | |
453 | u64 mac_rx_fragment_pkt_num; | |
454 | u64 mac_rx_undermin_pkt_num; | |
455 | u64 mac_rx_jabber_pkt_num; | |
456 | u64 mac_rx_fcs_err_pkt_num; | |
457 | u64 mac_rx_send_app_good_pkt_num; | |
458 | u64 mac_rx_send_app_bad_pkt_num; | |
d174ea75 | 459 | u64 mac_tx_pfc_pause_pkt_num; |
460 | u64 mac_rx_pfc_pause_pkt_num; | |
461 | u64 mac_tx_ctrl_pkt_num; | |
462 | u64 mac_rx_ctrl_pkt_num; | |
46a3df9f S |
463 | }; |
464 | ||
1c6dfe6f | 465 | #define HCLGE_STATS_TIMER_INTERVAL 300UL |
46a3df9f | 466 | |
5f6ea83f PL |
467 | struct hclge_vlan_type_cfg { |
468 | u16 rx_ot_fst_vlan_type; | |
469 | u16 rx_ot_sec_vlan_type; | |
470 | u16 rx_in_fst_vlan_type; | |
471 | u16 rx_in_sec_vlan_type; | |
472 | u16 tx_ot_vlan_type; | |
473 | u16 tx_in_vlan_type; | |
474 | }; | |
475 | ||
d695964d JS |
476 | enum HCLGE_FD_MODE { |
477 | HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1, | |
478 | HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2, | |
479 | HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1, | |
480 | HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2, | |
481 | }; | |
482 | ||
483 | enum HCLGE_FD_KEY_TYPE { | |
484 | HCLGE_FD_KEY_BASE_ON_PTYPE, | |
485 | HCLGE_FD_KEY_BASE_ON_TUPLE, | |
486 | }; | |
487 | ||
488 | enum HCLGE_FD_STAGE { | |
489 | HCLGE_FD_STAGE_1, | |
490 | HCLGE_FD_STAGE_2, | |
e91e388c | 491 | MAX_STAGE_NUM, |
d695964d JS |
492 | }; |
493 | ||
494 | /* OUTER_XXX indicates tuples in tunnel header of tunnel packet | |
495 | * INNER_XXX indicate tuples in tunneled header of tunnel packet or | |
496 | * tuples of non-tunnel packet | |
497 | */ | |
498 | enum HCLGE_FD_TUPLE { | |
499 | OUTER_DST_MAC, | |
500 | OUTER_SRC_MAC, | |
501 | OUTER_VLAN_TAG_FST, | |
502 | OUTER_VLAN_TAG_SEC, | |
503 | OUTER_ETH_TYPE, | |
504 | OUTER_L2_RSV, | |
505 | OUTER_IP_TOS, | |
506 | OUTER_IP_PROTO, | |
507 | OUTER_SRC_IP, | |
508 | OUTER_DST_IP, | |
509 | OUTER_L3_RSV, | |
510 | OUTER_SRC_PORT, | |
511 | OUTER_DST_PORT, | |
512 | OUTER_L4_RSV, | |
513 | OUTER_TUN_VNI, | |
514 | OUTER_TUN_FLOW_ID, | |
515 | INNER_DST_MAC, | |
516 | INNER_SRC_MAC, | |
517 | INNER_VLAN_TAG_FST, | |
518 | INNER_VLAN_TAG_SEC, | |
519 | INNER_ETH_TYPE, | |
520 | INNER_L2_RSV, | |
521 | INNER_IP_TOS, | |
522 | INNER_IP_PROTO, | |
523 | INNER_SRC_IP, | |
524 | INNER_DST_IP, | |
525 | INNER_L3_RSV, | |
526 | INNER_SRC_PORT, | |
527 | INNER_DST_PORT, | |
528 | INNER_L4_RSV, | |
529 | MAX_TUPLE, | |
530 | }; | |
531 | ||
532 | enum HCLGE_FD_META_DATA { | |
533 | PACKET_TYPE_ID, | |
534 | IP_FRAGEMENT, | |
535 | ROCE_TYPE, | |
536 | NEXT_KEY, | |
537 | VLAN_NUMBER, | |
538 | SRC_VPORT, | |
539 | DST_VPORT, | |
540 | TUNNEL_PACKET, | |
541 | MAX_META_DATA, | |
542 | }; | |
543 | ||
544 | struct key_info { | |
545 | u8 key_type; | |
e91e388c | 546 | u8 key_length; /* use bit as unit */ |
d695964d JS |
547 | }; |
548 | ||
d695964d JS |
549 | #define MAX_KEY_LENGTH 400 |
550 | #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4) | |
551 | #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4) | |
552 | #define MAX_META_DATA_LENGTH 32 | |
553 | ||
44122887 JS |
554 | /* assigned by firmware, the real filter number for each pf may be less */ |
555 | #define MAX_FD_FILTER_NUM 4096 | |
1c6dfe6f | 556 | #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL |
44122887 JS |
557 | |
558 | enum HCLGE_FD_ACTIVE_RULE_TYPE { | |
559 | HCLGE_FD_RULE_NONE, | |
560 | HCLGE_FD_ARFS_ACTIVE, | |
561 | HCLGE_FD_EP_ACTIVE, | |
562 | }; | |
563 | ||
d695964d JS |
564 | enum HCLGE_FD_PACKET_TYPE { |
565 | NIC_PACKET, | |
566 | ROCE_PACKET, | |
567 | }; | |
568 | ||
11732868 JS |
569 | enum HCLGE_FD_ACTION { |
570 | HCLGE_FD_ACTION_ACCEPT_PACKET, | |
571 | HCLGE_FD_ACTION_DROP_PACKET, | |
572 | }; | |
573 | ||
d695964d JS |
574 | struct hclge_fd_key_cfg { |
575 | u8 key_sel; | |
576 | u8 inner_sipv6_word_en; | |
577 | u8 inner_dipv6_word_en; | |
578 | u8 outer_sipv6_word_en; | |
579 | u8 outer_dipv6_word_en; | |
580 | u32 tuple_active; | |
581 | u32 meta_data_active; | |
582 | }; | |
583 | ||
584 | struct hclge_fd_cfg { | |
585 | u8 fd_mode; | |
e91e388c | 586 | u16 max_key_length; /* use bit as unit */ |
e91e388c JS |
587 | u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */ |
588 | u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */ | |
589 | struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM]; | |
d695964d JS |
590 | }; |
591 | ||
e91e388c JS |
592 | #define IPV4_INDEX 3 |
593 | #define IPV6_SIZE 4 | |
11732868 | 594 | struct hclge_fd_rule_tuples { |
e91e388c JS |
595 | u8 src_mac[ETH_ALEN]; |
596 | u8 dst_mac[ETH_ALEN]; | |
597 | /* Be compatible for ip address of both ipv4 and ipv6. | |
598 | * For ipv4 address, we store it in src/dst_ip[3]. | |
599 | */ | |
600 | u32 src_ip[IPV6_SIZE]; | |
601 | u32 dst_ip[IPV6_SIZE]; | |
11732868 JS |
602 | u16 src_port; |
603 | u16 dst_port; | |
604 | u16 vlan_tag1; | |
605 | u16 ether_proto; | |
606 | u8 ip_tos; | |
607 | u8 ip_proto; | |
608 | }; | |
609 | ||
610 | struct hclge_fd_rule { | |
611 | struct hlist_node rule_node; | |
612 | struct hclge_fd_rule_tuples tuples; | |
613 | struct hclge_fd_rule_tuples tuples_mask; | |
614 | u32 unused_tuple; | |
615 | u32 flow_type; | |
616 | u8 action; | |
617 | u16 vf_id; | |
618 | u16 queue_id; | |
619 | u16 location; | |
d93ed94f | 620 | u16 flow_id; /* only used for arfs */ |
44122887 | 621 | enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type; |
11732868 JS |
622 | }; |
623 | ||
624 | struct hclge_fd_ad_data { | |
625 | u16 ad_id; | |
626 | u8 drop_packet; | |
627 | u8 forward_to_direct_queue; | |
628 | u16 queue_id; | |
629 | u8 use_counter; | |
630 | u8 counter_id; | |
631 | u8 use_next_stage; | |
632 | u8 write_rule_id_to_bd; | |
633 | u8 next_input_key; | |
634 | u16 rule_id; | |
635 | }; | |
636 | ||
ee4bcd3b JS |
637 | enum HCLGE_MAC_NODE_STATE { |
638 | HCLGE_MAC_TO_ADD, | |
639 | HCLGE_MAC_TO_DEL, | |
640 | HCLGE_MAC_ACTIVE | |
641 | }; | |
642 | ||
643 | struct hclge_mac_node { | |
6dd86902 | 644 | struct list_head node; |
ee4bcd3b | 645 | enum HCLGE_MAC_NODE_STATE state; |
6dd86902 | 646 | u8 mac_addr[ETH_ALEN]; |
647 | }; | |
648 | ||
649 | enum HCLGE_MAC_ADDR_TYPE { | |
650 | HCLGE_MAC_ADDR_UC, | |
651 | HCLGE_MAC_ADDR_MC | |
652 | }; | |
653 | ||
c6075b19 | 654 | struct hclge_vport_vlan_cfg { |
655 | struct list_head node; | |
656 | int hd_tbl_status; | |
657 | u16 vlan_id; | |
658 | }; | |
659 | ||
f02eb82d HT |
660 | struct hclge_rst_stats { |
661 | u32 reset_done_cnt; /* the number of reset has completed */ | |
662 | u32 hw_reset_done_cnt; /* the number of HW reset has completed */ | |
663 | u32 pf_rst_cnt; /* the number of PF reset */ | |
664 | u32 flr_rst_cnt; /* the number of FLR */ | |
f02eb82d HT |
665 | u32 global_rst_cnt; /* the number of GLOBAL */ |
666 | u32 imp_rst_cnt; /* the number of IMP reset */ | |
667 | u32 reset_cnt; /* the number of reset */ | |
0ecf1f7b | 668 | u32 reset_fail_cnt; /* the number of reset fail */ |
f02eb82d HT |
669 | }; |
670 | ||
a6345787 WL |
671 | /* time and register status when mac tunnel interruption occur */ |
672 | struct hclge_mac_tnl_stats { | |
673 | u64 time; | |
674 | u32 status; | |
675 | }; | |
676 | ||
b37ce587 | 677 | #define HCLGE_RESET_INTERVAL (10 * HZ) |
7cf9c069 | 678 | #define HCLGE_WAIT_RESET_DONE 100 |
b37ce587 | 679 | |
ebaf1908 WL |
680 | #pragma pack(1) |
681 | struct hclge_vf_vlan_cfg { | |
682 | u8 mbx_cmd; | |
683 | u8 subcode; | |
684 | u8 is_kill; | |
685 | u16 vlan; | |
686 | u16 proto; | |
687 | }; | |
688 | ||
689 | #pragma pack() | |
690 | ||
11732868 JS |
691 | /* For each bit of TCAM entry, it uses a pair of 'x' and |
692 | * 'y' to indicate which value to match, like below: | |
693 | * ---------------------------------- | |
694 | * | bit x | bit y | search value | | |
695 | * ---------------------------------- | |
696 | * | 0 | 0 | always hit | | |
697 | * ---------------------------------- | |
698 | * | 1 | 0 | match '0' | | |
699 | * ---------------------------------- | |
700 | * | 0 | 1 | match '1' | | |
701 | * ---------------------------------- | |
702 | * | 1 | 1 | invalid | | |
703 | * ---------------------------------- | |
704 | * Then for input key(k) and mask(v), we can calculate the value by | |
705 | * the formulae: | |
706 | * x = (~k) & v | |
707 | * y = (k ^ ~v) & k | |
708 | */ | |
709 | #define calc_x(x, k, v) ((x) = (~(k) & (v))) | |
710 | #define calc_y(y, k, v) \ | |
711 | do { \ | |
712 | const typeof(k) _k_ = (k); \ | |
713 | const typeof(v) _v_ = (v); \ | |
714 | (y) = (_k_ ^ ~_v_) & (_k_); \ | |
715 | } while (0) | |
716 | ||
a6345787 | 717 | #define HCLGE_MAC_TNL_LOG_SIZE 8 |
dc8131d8 | 718 | #define HCLGE_VPORT_NUM 256 |
46a3df9f S |
719 | struct hclge_dev { |
720 | struct pci_dev *pdev; | |
721 | struct hnae3_ae_dev *ae_dev; | |
722 | struct hclge_hw hw; | |
466b0c00 | 723 | struct hclge_misc_vector misc_vector; |
1c6dfe6f | 724 | struct hclge_mac_stats mac_stats; |
46a3df9f | 725 | unsigned long state; |
6b9a97ee | 726 | unsigned long flr_state; |
0742ed7c | 727 | unsigned long last_reset_time; |
46a3df9f | 728 | |
4ed340ab | 729 | enum hnae3_reset_type reset_type; |
0742ed7c | 730 | enum hnae3_reset_type reset_level; |
720bd583 | 731 | unsigned long default_reset_request; |
cb1b9f77 | 732 | unsigned long reset_request; /* reset has been requested */ |
ca1d7669 | 733 | unsigned long reset_pending; /* client rst is pending to be served */ |
f02eb82d | 734 | struct hclge_rst_stats rst_stats; |
8627bded | 735 | struct semaphore reset_sem; /* protect reset process */ |
46a3df9f S |
736 | u32 fw_version; |
737 | u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */ | |
738 | u16 num_tqps; /* Num task queue pairs of this PF */ | |
739 | u16 num_req_vfs; /* Num VFs requested for this PF */ | |
740 | ||
fdace1bc | 741 | u16 base_tqp_pid; /* Base task tqp physical id of this PF */ |
46a3df9f S |
742 | u16 alloc_rss_size; /* Allocated RSS task queue */ |
743 | u16 rss_size_max; /* HW defined max RSS task queue */ | |
744 | ||
fdace1bc | 745 | u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */ |
46a3df9f S |
746 | u16 num_alloc_vport; /* Num vports this driver supports */ |
747 | u32 numa_node_mask; | |
748 | u16 rx_buf_len; | |
c0425944 PL |
749 | u16 num_tx_desc; /* desc num of per tx queue */ |
750 | u16 num_rx_desc; /* desc num of per rx queue */ | |
46a3df9f S |
751 | u8 hw_tc_map; |
752 | u8 tc_num_last_time; | |
753 | enum hclge_fc_mode fc_mode_last_time; | |
5d497936 | 754 | u8 support_sfp_query; |
46a3df9f S |
755 | |
756 | #define HCLGE_FLAG_TC_BASE_SCH_MODE 1 | |
757 | #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2 | |
758 | u8 tx_sch_mode; | |
cacde272 YL |
759 | u8 tc_max; |
760 | u8 pfc_max; | |
46a3df9f S |
761 | |
762 | u8 default_up; | |
cacde272 | 763 | u8 dcbx_cap; |
46a3df9f S |
764 | struct hclge_tm_info tm_info; |
765 | ||
766 | u16 num_msi; | |
767 | u16 num_msi_left; | |
768 | u16 num_msi_used; | |
375dd5e4 | 769 | u16 roce_base_msix_offset; |
46a3df9f | 770 | u32 base_msi_vector; |
46a3df9f | 771 | u16 *vector_status; |
887c3820 | 772 | int *vector_irq; |
580a05f9 | 773 | u16 num_nic_msi; /* Num of nic vectors for this PF */ |
887c3820 SM |
774 | u16 num_roce_msi; /* Num of roce vectors for this PF */ |
775 | int roce_base_vector; | |
46a3df9f | 776 | |
46a3df9f S |
777 | unsigned long service_timer_period; |
778 | unsigned long service_timer_previous; | |
65e41e7e | 779 | struct timer_list reset_timer; |
7be1b9f3 | 780 | struct delayed_work service_task; |
46a3df9f S |
781 | |
782 | bool cur_promisc; | |
783 | int num_alloc_vfs; /* Actual number of VFs allocated */ | |
784 | ||
785 | struct hclge_tqp *htqp; | |
786 | struct hclge_vport *vport; | |
787 | ||
788 | struct dentry *hclge_dbgfs; | |
789 | ||
790 | struct hnae3_client *nic_client; | |
791 | struct hnae3_client *roce_client; | |
792 | ||
887c3820 SM |
793 | #define HCLGE_FLAG_MAIN BIT(0) |
794 | #define HCLGE_FLAG_DCB_CAPABLE BIT(1) | |
795 | #define HCLGE_FLAG_DCB_ENABLE BIT(2) | |
796 | #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3) | |
46a3df9f S |
797 | u32 flag; |
798 | ||
799 | u32 pkt_buf_size; /* Total pf buf size for tx/rx */ | |
368686be YL |
800 | u32 tx_buf_size; /* Tx buffer size for each TC */ |
801 | u32 dv_buf_size; /* Dv buffer size for each TC */ | |
802 | ||
46a3df9f | 803 | u32 mps; /* Max packet size */ |
818f1675 YL |
804 | /* vport_lock protect resource shared by vports */ |
805 | struct mutex vport_lock; | |
46a3df9f | 806 | |
5f6ea83f | 807 | struct hclge_vlan_type_cfg vlan_type_cfg; |
716aaac1 | 808 | |
dc8131d8 | 809 | unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)]; |
81a9255e | 810 | unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; |
d695964d | 811 | |
ee4bcd3b JS |
812 | unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)]; |
813 | ||
d695964d | 814 | struct hclge_fd_cfg fd_cfg; |
dd74f815 | 815 | struct hlist_head fd_rule_list; |
44122887 | 816 | spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */ |
dd74f815 | 817 | u16 hclge_fd_rule_num; |
1c6dfe6f YL |
818 | unsigned long serv_processed_cnt; |
819 | unsigned long last_serv_processed; | |
44122887 JS |
820 | unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)]; |
821 | enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type; | |
9abeb7d8 | 822 | u8 fd_en; |
39932473 JS |
823 | |
824 | u16 wanted_umv_size; | |
825 | /* max available unicast mac vlan space */ | |
826 | u16 max_umv_size; | |
827 | /* private unicast mac vlan space, it's same for PF and its VFs */ | |
828 | u16 priv_umv_size; | |
829 | /* unicast mac vlan space shared by PF and its VFs */ | |
830 | u16 share_umv_size; | |
6dd86902 | 831 | |
a6345787 WL |
832 | DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats, |
833 | HCLGE_MAC_TNL_LOG_SIZE); | |
08125454 YL |
834 | |
835 | /* affinity mask and notify for misc interrupt */ | |
836 | cpumask_t affinity_mask; | |
837 | struct irq_affinity_notify affinity_notify; | |
5f6ea83f PL |
838 | }; |
839 | ||
840 | /* VPort level vlan tag configuration for TX direction */ | |
841 | struct hclge_tx_vtag_cfg { | |
dcb35cce PL |
842 | bool accept_tag1; /* Whether accept tag1 packet from host */ |
843 | bool accept_untag1; /* Whether accept untag1 packet from host */ | |
844 | bool accept_tag2; | |
845 | bool accept_untag2; | |
5f6ea83f PL |
846 | bool insert_tag1_en; /* Whether insert inner vlan tag */ |
847 | bool insert_tag2_en; /* Whether insert outer vlan tag */ | |
848 | u16 default_tag1; /* The default inner vlan tag to insert */ | |
849 | u16 default_tag2; /* The default outer vlan tag to insert */ | |
850 | }; | |
851 | ||
852 | /* VPort level vlan tag configuration for RX direction */ | |
853 | struct hclge_rx_vtag_cfg { | |
741fca16 JS |
854 | u8 rx_vlan_offload_en; /* Whether enable rx vlan offload */ |
855 | u8 strip_tag1_en; /* Whether strip inner vlan tag */ | |
856 | u8 strip_tag2_en; /* Whether strip outer vlan tag */ | |
857 | u8 vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */ | |
858 | u8 vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */ | |
46a3df9f S |
859 | }; |
860 | ||
6f2af429 YL |
861 | struct hclge_rss_tuple_cfg { |
862 | u8 ipv4_tcp_en; | |
863 | u8 ipv4_udp_en; | |
864 | u8 ipv4_sctp_en; | |
865 | u8 ipv4_fragment_en; | |
866 | u8 ipv6_tcp_en; | |
867 | u8 ipv6_udp_en; | |
868 | u8 ipv6_sctp_en; | |
869 | u8 ipv6_fragment_en; | |
870 | }; | |
871 | ||
a6d818e3 YL |
872 | enum HCLGE_VPORT_STATE { |
873 | HCLGE_VPORT_STATE_ALIVE, | |
ee4bcd3b | 874 | HCLGE_VPORT_STATE_MAC_TBL_CHANGE, |
a6d818e3 YL |
875 | HCLGE_VPORT_STATE_MAX |
876 | }; | |
877 | ||
741fca16 JS |
878 | struct hclge_vlan_info { |
879 | u16 vlan_proto; /* so far support 802.1Q only */ | |
880 | u16 qos; | |
881 | u16 vlan_tag; | |
882 | }; | |
883 | ||
884 | struct hclge_port_base_vlan_config { | |
885 | u16 state; | |
886 | struct hclge_vlan_info vlan_info; | |
887 | }; | |
888 | ||
6430f744 YM |
889 | struct hclge_vf_info { |
890 | int link_state; | |
891 | u8 mac[ETH_ALEN]; | |
22044f95 | 892 | u32 spoofchk; |
ee9e4424 | 893 | u32 max_tx_rate; |
e196ec75 JS |
894 | u32 trusted; |
895 | u16 promisc_enable; | |
6430f744 YM |
896 | }; |
897 | ||
46a3df9f S |
898 | struct hclge_vport { |
899 | u16 alloc_tqps; /* Allocated Tx/Rx queues */ | |
900 | ||
901 | u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */ | |
902 | /* User configured lookup table entries */ | |
903 | u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE]; | |
89523cfa | 904 | int rss_algo; /* User configured hash algorithm */ |
6f2af429 YL |
905 | /* User configured rss tuple sets */ |
906 | struct hclge_rss_tuple_cfg rss_tuple_sets; | |
89523cfa | 907 | |
68ece54e | 908 | u16 alloc_rss_size; |
46a3df9f S |
909 | |
910 | u16 qs_offset; | |
2566f106 | 911 | u32 bw_limit; /* VSI BW Limit (0 = disabled) */ |
46a3df9f S |
912 | u8 dwrr; |
913 | ||
fe4144d4 | 914 | unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)]; |
741fca16 | 915 | struct hclge_port_base_vlan_config port_base_vlan_cfg; |
5f6ea83f PL |
916 | struct hclge_tx_vtag_cfg txvlan_cfg; |
917 | struct hclge_rx_vtag_cfg rxvlan_cfg; | |
918 | ||
39932473 JS |
919 | u16 used_umv_num; |
920 | ||
ebaf1908 | 921 | u16 vport_id; |
46a3df9f S |
922 | struct hclge_dev *back; /* Back reference to associated dev */ |
923 | struct hnae3_handle nic; | |
924 | struct hnae3_handle roce; | |
a6d818e3 YL |
925 | |
926 | unsigned long state; | |
927 | unsigned long last_active_jiffies; | |
818f1675 | 928 | u32 mps; /* Max packet size */ |
6430f744 | 929 | struct hclge_vf_info vf_info; |
6dd86902 | 930 | |
c631c696 JS |
931 | u8 overflow_promisc_flags; |
932 | u8 last_promisc_flags; | |
933 | ||
ee4bcd3b | 934 | spinlock_t mac_list_lock; /* protect mac address need to add/detele */ |
6dd86902 | 935 | struct list_head uc_mac_list; /* Store VF unicast table */ |
936 | struct list_head mc_mac_list; /* Store VF multicast table */ | |
c6075b19 | 937 | struct list_head vlan_list; /* Store VF vlan table */ |
46a3df9f S |
938 | }; |
939 | ||
e196ec75 JS |
940 | int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc, |
941 | bool en_mc_pmc, bool en_bc_pmc); | |
46a3df9f S |
942 | int hclge_add_uc_addr_common(struct hclge_vport *vport, |
943 | const unsigned char *addr); | |
944 | int hclge_rm_uc_addr_common(struct hclge_vport *vport, | |
945 | const unsigned char *addr); | |
946 | int hclge_add_mc_addr_common(struct hclge_vport *vport, | |
947 | const unsigned char *addr); | |
948 | int hclge_rm_mc_addr_common(struct hclge_vport *vport, | |
949 | const unsigned char *addr); | |
950 | ||
46a3df9f | 951 | struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle); |
84e095d6 SM |
952 | int hclge_bind_ring_with_vector(struct hclge_vport *vport, |
953 | int vector_id, bool en, | |
954 | struct hnae3_ring_chain_node *ring_chain); | |
955 | ||
46a3df9f S |
956 | static inline int hclge_get_queue_id(struct hnae3_queue *queue) |
957 | { | |
958 | struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q); | |
959 | ||
960 | return tqp->index; | |
961 | } | |
962 | ||
6dd22bbc HT |
963 | static inline bool hclge_is_reset_pending(struct hclge_dev *hdev) |
964 | { | |
965 | return !!hdev->reset_pending; | |
966 | } | |
967 | ||
dea846e8 | 968 | int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport); |
46a3df9f | 969 | int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex); |
dc8131d8 YL |
970 | int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, |
971 | u16 vlan_id, bool is_kill); | |
b2641e2a | 972 | int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable); |
77f255c1 YL |
973 | |
974 | int hclge_buffer_alloc(struct hclge_dev *hdev); | |
975 | int hclge_rss_init_hw(struct hclge_dev *hdev); | |
268f5dfa | 976 | void hclge_rss_indir_init_cfg(struct hclge_dev *hdev); |
dde1a86e SM |
977 | |
978 | void hclge_mbx_handler(struct hclge_dev *hdev); | |
7fa6be4f | 979 | int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id); |
1a426f8b | 980 | void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id); |
1770a7a3 | 981 | int hclge_cfg_flowctrl(struct hclge_dev *hdev); |
2bfbd35d | 982 | int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id); |
a6d818e3 YL |
983 | int hclge_vport_start(struct hclge_vport *vport); |
984 | void hclge_vport_stop(struct hclge_vport *vport); | |
818f1675 | 985 | int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu); |
ebaf1908 | 986 | int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf); |
0c29d191 | 987 | u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id); |
af013903 HT |
988 | int hclge_notify_client(struct hclge_dev *hdev, |
989 | enum hnae3_reset_notify_type type); | |
ee4bcd3b JS |
990 | int hclge_update_mac_list(struct hclge_vport *vport, |
991 | enum HCLGE_MAC_NODE_STATE state, | |
992 | enum HCLGE_MAC_ADDR_TYPE mac_type, | |
993 | const unsigned char *addr); | |
994 | int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport, | |
995 | const u8 *old_addr, const u8 *new_addr); | |
6dd86902 | 996 | void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list, |
997 | enum HCLGE_MAC_ADDR_TYPE mac_type); | |
c6075b19 | 998 | void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list); |
999 | void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev); | |
ee4bcd3b | 1000 | void hclge_restore_mac_table_common(struct hclge_vport *vport); |
039ba863 | 1001 | void hclge_restore_vport_vlan_table(struct hclge_vport *vport); |
21e043cd JS |
1002 | int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state, |
1003 | struct hclge_vlan_info *vlan_info); | |
92f11ea1 JS |
1004 | int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid, |
1005 | u16 state, u16 vlan_tag, u16 qos, | |
1006 | u16 vlan_proto); | |
ed8fb4b2 | 1007 | void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time); |
ddb54554 GH |
1008 | int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, |
1009 | struct hclge_desc *desc); | |
a83d2961 WL |
1010 | void hclge_report_hw_error(struct hclge_dev *hdev, |
1011 | enum hnae3_hw_error_type type); | |
e196ec75 | 1012 | void hclge_inform_vf_promisc_info(struct hclge_vport *vport); |
3d77d0cb | 1013 | void hclge_dbg_dump_rst_info(struct hclge_dev *hdev); |
46a3df9f | 1014 | #endif |