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net: hns3: Rename mac loopback to app loopback
[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
46a3df9f
S		 3
4#include <linux/acpi.h>
5#include <linux/device.h>
6#include <linux/etherdevice.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/pci.h>
13#include <linux/platform_device.h>
2866ccb2 14#include <linux/if_vlan.h>
f2f432f2 15#include <net/rtnetlink.h>
46a3df9f 16#include "hclge_cmd.h"
cacde272 17#include "hclge_dcb.h"
46a3df9f 18#include "hclge_main.h"
dde1a86e 19#include "hclge_mbx.h"
46a3df9f
S		 20#include "hclge_mdio.h"
21#include "hclge_tm.h"
22#include "hnae3.h"
23
24#define HCLGE_NAME "hclge"
25#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
26#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
46a3df9f 27
46a3df9f
S		 28static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
29 enum hclge_mta_dmac_sel_type mta_mac_sel,
30 bool enable);
f9fd82a9 31static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 32static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 33static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 34
35static struct hnae3_ae_algo ae_algo;
36
37static const struct pci_device_id ae_algo_pci_tbl[] = {
38 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
39 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 45 /* required last entry */
46a3df9f
S		 46 {0, }
47};
48
2f550a46
YL		 49MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
50
46a3df9f 51static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
eb66d503 52 "App Loopback test",
46a3df9f
S		 53 "Serdes Loopback test",
54 "Phy Loopback test"
55};
56
46a3df9f
S		 57static const struct hclge_comm_stats_str g_mac_stats_string[] = {
58 {"mac_tx_mac_pause_num",
59 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
60 {"mac_rx_mac_pause_num",
61 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
62 {"mac_tx_pfc_pri0_pkt_num",
63 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
64 {"mac_tx_pfc_pri1_pkt_num",
65 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
66 {"mac_tx_pfc_pri2_pkt_num",
67 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
68 {"mac_tx_pfc_pri3_pkt_num",
69 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
70 {"mac_tx_pfc_pri4_pkt_num",
71 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
72 {"mac_tx_pfc_pri5_pkt_num",
73 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
74 {"mac_tx_pfc_pri6_pkt_num",
75 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
76 {"mac_tx_pfc_pri7_pkt_num",
77 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
78 {"mac_rx_pfc_pri0_pkt_num",
79 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
80 {"mac_rx_pfc_pri1_pkt_num",
81 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
82 {"mac_rx_pfc_pri2_pkt_num",
83 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
84 {"mac_rx_pfc_pri3_pkt_num",
85 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
86 {"mac_rx_pfc_pri4_pkt_num",
87 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
88 {"mac_rx_pfc_pri5_pkt_num",
89 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
90 {"mac_rx_pfc_pri6_pkt_num",
91 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
92 {"mac_rx_pfc_pri7_pkt_num",
93 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
94 {"mac_tx_total_pkt_num",
95 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
96 {"mac_tx_total_oct_num",
97 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
98 {"mac_tx_good_pkt_num",
99 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
100 {"mac_tx_bad_pkt_num",
101 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
102 {"mac_tx_good_oct_num",
103 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
104 {"mac_tx_bad_oct_num",
105 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
106 {"mac_tx_uni_pkt_num",
107 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
108 {"mac_tx_multi_pkt_num",
109 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
110 {"mac_tx_broad_pkt_num",
111 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
112 {"mac_tx_undersize_pkt_num",
113 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
200a88c6
JS		 114 {"mac_tx_oversize_pkt_num",
115 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 116 {"mac_tx_64_oct_pkt_num",
117 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
118 {"mac_tx_65_127_oct_pkt_num",
119 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
120 {"mac_tx_128_255_oct_pkt_num",
121 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
122 {"mac_tx_256_511_oct_pkt_num",
123 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
124 {"mac_tx_512_1023_oct_pkt_num",
125 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
126 {"mac_tx_1024_1518_oct_pkt_num",
127 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
91f384f6
JS		 128 {"mac_tx_1519_2047_oct_pkt_num",
129 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
130 {"mac_tx_2048_4095_oct_pkt_num",
131 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
132 {"mac_tx_4096_8191_oct_pkt_num",
133 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
91f384f6
JS		 134 {"mac_tx_8192_9216_oct_pkt_num",
135 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
136 {"mac_tx_9217_12287_oct_pkt_num",
137 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
138 {"mac_tx_12288_16383_oct_pkt_num",
139 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
140 {"mac_tx_1519_max_good_pkt_num",
141 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
142 {"mac_tx_1519_max_bad_pkt_num",
143 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 144 {"mac_rx_total_pkt_num",
145 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
146 {"mac_rx_total_oct_num",
147 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
148 {"mac_rx_good_pkt_num",
149 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
150 {"mac_rx_bad_pkt_num",
151 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
152 {"mac_rx_good_oct_num",
153 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
154 {"mac_rx_bad_oct_num",
155 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
156 {"mac_rx_uni_pkt_num",
157 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
158 {"mac_rx_multi_pkt_num",
159 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
160 {"mac_rx_broad_pkt_num",
161 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
162 {"mac_rx_undersize_pkt_num",
163 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
200a88c6
JS		 164 {"mac_rx_oversize_pkt_num",
165 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 166 {"mac_rx_64_oct_pkt_num",
167 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
168 {"mac_rx_65_127_oct_pkt_num",
169 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
170 {"mac_rx_128_255_oct_pkt_num",
171 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
172 {"mac_rx_256_511_oct_pkt_num",
173 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
174 {"mac_rx_512_1023_oct_pkt_num",
175 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
176 {"mac_rx_1024_1518_oct_pkt_num",
177 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
91f384f6
JS		 178 {"mac_rx_1519_2047_oct_pkt_num",
179 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
180 {"mac_rx_2048_4095_oct_pkt_num",
181 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
182 {"mac_rx_4096_8191_oct_pkt_num",
183 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
91f384f6
JS		 184 {"mac_rx_8192_9216_oct_pkt_num",
185 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
186 {"mac_rx_9217_12287_oct_pkt_num",
187 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
188 {"mac_rx_12288_16383_oct_pkt_num",
189 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
190 {"mac_rx_1519_max_good_pkt_num",
191 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
192 {"mac_rx_1519_max_bad_pkt_num",
193 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 194
a6c51c26
JS		 195 {"mac_tx_fragment_pkt_num",
196 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
197 {"mac_tx_undermin_pkt_num",
198 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
199 {"mac_tx_jabber_pkt_num",
200 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
201 {"mac_tx_err_all_pkt_num",
202 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
203 {"mac_tx_from_app_good_pkt_num",
204 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
205 {"mac_tx_from_app_bad_pkt_num",
206 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
207 {"mac_rx_fragment_pkt_num",
208 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
209 {"mac_rx_undermin_pkt_num",
210 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
211 {"mac_rx_jabber_pkt_num",
212 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
213 {"mac_rx_fcs_err_pkt_num",
214 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
215 {"mac_rx_send_app_good_pkt_num",
216 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
217 {"mac_rx_send_app_bad_pkt_num",
218 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 219};
220
f5aac71c
FL		 221static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
222 {
223 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
224 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
225 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
226 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
227 .i_port_bitmap = 0x1,
228 },
229};
230
46a3df9f
S		 231static int hclge_mac_update_stats(struct hclge_dev *hdev)
232{
91f384f6 233#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 234#define HCLGE_RTN_DATA_NUM 4
235
236 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
237 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 238 __le64 *desc_data;
46a3df9f
S		 239 int i, k, n;
240 int ret;
241
242 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
243 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
244 if (ret) {
245 dev_err(&hdev->pdev->dev,
246 "Get MAC pkt stats fail, status = %d.\n", ret);
247
248 return ret;
249 }
250
251 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
252 if (unlikely(i == 0)) {
a90bb9a5 253 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 254 n = HCLGE_RTN_DATA_NUM - 2;
255 } else {
a90bb9a5 256 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 257 n = HCLGE_RTN_DATA_NUM;
258 }
259 for (k = 0; k < n; k++) {
a90bb9a5 260 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 261 desc_data++;
262 }
263 }
264
265 return 0;
266}
267
268static int hclge_tqps_update_stats(struct hnae3_handle *handle)
269{
270 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
271 struct hclge_vport *vport = hclge_get_vport(handle);
272 struct hclge_dev *hdev = vport->back;
273 struct hnae3_queue *queue;
274 struct hclge_desc desc[1];
275 struct hclge_tqp *tqp;
276 int ret, i;
277
278 for (i = 0; i < kinfo->num_tqps; i++) {
279 queue = handle->kinfo.tqp[i];
280 tqp = container_of(queue, struct hclge_tqp, q);
281 /* command : HCLGE_OPC_QUERY_IGU_STAT */
282 hclge_cmd_setup_basic_desc(&desc[0],
283 HCLGE_OPC_QUERY_RX_STATUS,
284 true);
285
a90bb9a5 286 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 287 ret = hclge_cmd_send(&hdev->hw, desc, 1);
288 if (ret) {
289 dev_err(&hdev->pdev->dev,
290 "Query tqp stat fail, status = %d,queue = %d\n",
291 ret, i);
292 return ret;
293 }
294 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
cf72fa63 295 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 296 }
297
298 for (i = 0; i < kinfo->num_tqps; i++) {
299 queue = handle->kinfo.tqp[i];
300 tqp = container_of(queue, struct hclge_tqp, q);
301 /* command : HCLGE_OPC_QUERY_IGU_STAT */
302 hclge_cmd_setup_basic_desc(&desc[0],
303 HCLGE_OPC_QUERY_TX_STATUS,
304 true);
305
a90bb9a5 306 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 307 ret = hclge_cmd_send(&hdev->hw, desc, 1);
308 if (ret) {
309 dev_err(&hdev->pdev->dev,
310 "Query tqp stat fail, status = %d,queue = %d\n",
311 ret, i);
312 return ret;
313 }
314 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
cf72fa63 315 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 316 }
317
318 return 0;
319}
320
321static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
322{
323 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
324 struct hclge_tqp *tqp;
325 u64 *buff = data;
326 int i;
327
328 for (i = 0; i < kinfo->num_tqps; i++) {
329 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 330 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 331 }
332
333 for (i = 0; i < kinfo->num_tqps; i++) {
334 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 335 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 336 }
337
338 return buff;
339}
340
341static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
342{
343 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
344
345 return kinfo->num_tqps * (2);
346}
347
348static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
349{
350 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
351 u8 *buff = data;
352 int i = 0;
353
354 for (i = 0; i < kinfo->num_tqps; i++) {
355 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
356 struct hclge_tqp, q);
0c218123 357 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
46a3df9f
S		 358 tqp->index);
359 buff = buff + ETH_GSTRING_LEN;
360 }
361
362 for (i = 0; i < kinfo->num_tqps; i++) {
363 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
364 struct hclge_tqp, q);
0c218123 365 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
46a3df9f
S		 366 tqp->index);
367 buff = buff + ETH_GSTRING_LEN;
368 }
369
370 return buff;
371}
372
373static u64 *hclge_comm_get_stats(void *comm_stats,
374 const struct hclge_comm_stats_str strs[],
375 int size, u64 *data)
376{
377 u64 *buf = data;
378 u32 i;
379
380 for (i = 0; i < size; i++)
381 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
382
383 return buf + size;
384}
385
386static u8 *hclge_comm_get_strings(u32 stringset,
387 const struct hclge_comm_stats_str strs[],
388 int size, u8 *data)
389{
390 char *buff = (char *)data;
391 u32 i;
392
393 if (stringset != ETH_SS_STATS)
394 return buff;
395
396 for (i = 0; i < size; i++) {
397 snprintf(buff, ETH_GSTRING_LEN,
398 strs[i].desc);
399 buff = buff + ETH_GSTRING_LEN;
400 }
401
402 return (u8 *)buff;
403}
404
405static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
406 struct net_device_stats *net_stats)
407{
408 net_stats->tx_dropped = 0;
200a88c6 409 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 410 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
a6c51c26 411 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 412
413 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
414 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
415
a6c51c26 416 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 417 net_stats->rx_length_errors =
418 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
419 net_stats->rx_length_errors +=
200a88c6 420 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 421 net_stats->rx_over_errors =
200a88c6 422 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 423}
424
425static void hclge_update_stats_for_all(struct hclge_dev *hdev)
426{
427 struct hnae3_handle *handle;
428 int status;
429
430 handle = &hdev->vport[0].nic;
431 if (handle->client) {
432 status = hclge_tqps_update_stats(handle);
433 if (status) {
434 dev_err(&hdev->pdev->dev,
435 "Update TQPS stats fail, status = %d.\n",
436 status);
437 }
438 }
439
440 status = hclge_mac_update_stats(hdev);
441 if (status)
442 dev_err(&hdev->pdev->dev,
443 "Update MAC stats fail, status = %d.\n", status);
444
46a3df9f
S		 445 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
446}
447
448static void hclge_update_stats(struct hnae3_handle *handle,
449 struct net_device_stats *net_stats)
450{
451 struct hclge_vport *vport = hclge_get_vport(handle);
452 struct hclge_dev *hdev = vport->back;
453 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
454 int status;
455
c5f65480
JS		 456 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
457 return;
458
46a3df9f
S		 459 status = hclge_mac_update_stats(hdev);
460 if (status)
461 dev_err(&hdev->pdev->dev,
462 "Update MAC stats fail, status = %d.\n",
463 status);
464
46a3df9f
S		 465 status = hclge_tqps_update_stats(handle);
466 if (status)
467 dev_err(&hdev->pdev->dev,
468 "Update TQPS stats fail, status = %d.\n",
469 status);
470
471 hclge_update_netstat(hw_stats, net_stats);
c5f65480
JS		 472
473 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 474}
475
476static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
477{
478#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
479
480 struct hclge_vport *vport = hclge_get_vport(handle);
481 struct hclge_dev *hdev = vport->back;
482 int count = 0;
483
484 /* Loopback test support rules:
485 * mac: only GE mode support
486 * serdes: all mac mode will support include GE/XGE/LGE/CGE
487 * phy: only support when phy device exist on board
488 */
489 if (stringset == ETH_SS_TEST) {
490 /* clear loopback bit flags at first */
491 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
492 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
493 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
494 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
495 count += 1;
eb66d503 496 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
46a3df9f 497 }
5fd50ac3
PL		 498
499 count++;
500 handle->flags |= HNAE3_SUPPORT_SERDES_LOOPBACK;
46a3df9f
S		 501 } else if (stringset == ETH_SS_STATS) {
502 count = ARRAY_SIZE(g_mac_stats_string) +
46a3df9f
S		 503 hclge_tqps_get_sset_count(handle, stringset);
504 }
505
506 return count;
507}
508
509static void hclge_get_strings(struct hnae3_handle *handle,
510 u32 stringset,
511 u8 *data)
512{
513 u8 *p = (char *)data;
514 int size;
515
516 if (stringset == ETH_SS_STATS) {
517 size = ARRAY_SIZE(g_mac_stats_string);
518 p = hclge_comm_get_strings(stringset,
519 g_mac_stats_string,
520 size,
521 p);
46a3df9f
S		 522 p = hclge_tqps_get_strings(handle, p);
523 } else if (stringset == ETH_SS_TEST) {
eb66d503 524 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
46a3df9f 525 memcpy(p,
eb66d503 526 hns3_nic_test_strs[HNAE3_LOOP_APP],
46a3df9f
S		 527 ETH_GSTRING_LEN);
528 p += ETH_GSTRING_LEN;
529 }
530 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
531 memcpy(p,
a7b687b3 532 hns3_nic_test_strs[HNAE3_LOOP_SERDES],
46a3df9f
S		 533 ETH_GSTRING_LEN);
534 p += ETH_GSTRING_LEN;
535 }
536 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
537 memcpy(p,
a7b687b3 538 hns3_nic_test_strs[HNAE3_LOOP_PHY],
46a3df9f
S		 539 ETH_GSTRING_LEN);
540 p += ETH_GSTRING_LEN;
541 }
542 }
543}
544
545static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
546{
547 struct hclge_vport *vport = hclge_get_vport(handle);
548 struct hclge_dev *hdev = vport->back;
549 u64 *p;
550
551 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
552 g_mac_stats_string,
553 ARRAY_SIZE(g_mac_stats_string),
554 data);
46a3df9f
S		 555 p = hclge_tqps_get_stats(handle, p);
556}
557
558static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 559 struct hclge_func_status_cmd *status)
46a3df9f
S		 560{
561 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
562 return -EINVAL;
563
564 /* Set the pf to main pf */
565 if (status->pf_state & HCLGE_PF_STATE_MAIN)
566 hdev->flag |= HCLGE_FLAG_MAIN;
567 else
568 hdev->flag &= ~HCLGE_FLAG_MAIN;
569
46a3df9f
S		 570 return 0;
571}
572
573static int hclge_query_function_status(struct hclge_dev *hdev)
574{
d44f9b63 575 struct hclge_func_status_cmd *req;
46a3df9f
S		 576 struct hclge_desc desc;
577 int timeout = 0;
578 int ret;
579
580 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 581 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 582
583 do {
584 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
585 if (ret) {
586 dev_err(&hdev->pdev->dev,
587 "query function status failed %d.\n",
588 ret);
589
590 return ret;
591 }
592
593 /* Check pf reset is done */
594 if (req->pf_state)
595 break;
596 usleep_range(1000, 2000);
597 } while (timeout++ < 5);
598
599 ret = hclge_parse_func_status(hdev, req);
600
601 return ret;
602}
603
604static int hclge_query_pf_resource(struct hclge_dev *hdev)
605{
d44f9b63 606 struct hclge_pf_res_cmd *req;
46a3df9f
S		 607 struct hclge_desc desc;
608 int ret;
609
610 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
611 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
612 if (ret) {
613 dev_err(&hdev->pdev->dev,
614 "query pf resource failed %d.\n", ret);
615 return ret;
616 }
617
d44f9b63 618 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 619 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
620 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
621
e92a0843 622 if (hnae3_dev_roce_supported(hdev)) {
375dd5e4
JS		 623 hdev->roce_base_msix_offset =
624 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
625 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
887c3820 626 hdev->num_roce_msi =
e4e87715
PL		 627 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
628 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 629
630 /* PF should have NIC vectors and Roce vectors,
631 * NIC vectors are queued before Roce vectors.
632 */
375dd5e4
JS		 633 hdev->num_msi = hdev->num_roce_msi +
634 hdev->roce_base_msix_offset;
46a3df9f
S		 635 } else {
636 hdev->num_msi =
e4e87715
PL		 637 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
638 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 639 }
640
641 return 0;
642}
643
644static int hclge_parse_speed(int speed_cmd, int *speed)
645{
646 switch (speed_cmd) {
647 case 6:
648 *speed = HCLGE_MAC_SPEED_10M;
649 break;
650 case 7:
651 *speed = HCLGE_MAC_SPEED_100M;
652 break;
653 case 0:
654 *speed = HCLGE_MAC_SPEED_1G;
655 break;
656 case 1:
657 *speed = HCLGE_MAC_SPEED_10G;
658 break;
659 case 2:
660 *speed = HCLGE_MAC_SPEED_25G;
661 break;
662 case 3:
663 *speed = HCLGE_MAC_SPEED_40G;
664 break;
665 case 4:
666 *speed = HCLGE_MAC_SPEED_50G;
667 break;
668 case 5:
669 *speed = HCLGE_MAC_SPEED_100G;
670 break;
671 default:
672 return -EINVAL;
673 }
674
675 return 0;
676}
677
0979aa0b
FL		 678static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
679 u8 speed_ability)
680{
681 unsigned long *supported = hdev->hw.mac.supported;
682
683 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
684 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
685 supported);
686
687 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
688 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
689 supported);
690
691 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
692 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
693 supported);
694
695 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
696 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
697 supported);
698
699 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
700 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
701 supported);
702
703 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
704 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
705}
706
707static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
708{
709 u8 media_type = hdev->hw.mac.media_type;
710
711 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
712 return;
713
714 hclge_parse_fiber_link_mode(hdev, speed_ability);
715}
716
46a3df9f
S		 717static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
718{
d44f9b63 719 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 720 u64 mac_addr_tmp_high;
721 u64 mac_addr_tmp;
722 int i;
723
d44f9b63 724 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 725
726 /* get the configuration */
e4e87715
PL		 727 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
728 HCLGE_CFG_VMDQ_M,
729 HCLGE_CFG_VMDQ_S);
730 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
731 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
732 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
733 HCLGE_CFG_TQP_DESC_N_M,
734 HCLGE_CFG_TQP_DESC_N_S);
735
736 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
737 HCLGE_CFG_PHY_ADDR_M,
738 HCLGE_CFG_PHY_ADDR_S);
739 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
740 HCLGE_CFG_MEDIA_TP_M,
741 HCLGE_CFG_MEDIA_TP_S);
742 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
743 HCLGE_CFG_RX_BUF_LEN_M,
744 HCLGE_CFG_RX_BUF_LEN_S);
46a3df9f
S		 745 /* get mac_address */
746 mac_addr_tmp = __le32_to_cpu(req->param[2]);
e4e87715
PL		 747 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
748 HCLGE_CFG_MAC_ADDR_H_M,
749 HCLGE_CFG_MAC_ADDR_H_S);
46a3df9f
S		 750
751 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
752
e4e87715
PL		 753 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
754 HCLGE_CFG_DEFAULT_SPEED_M,
755 HCLGE_CFG_DEFAULT_SPEED_S);
756 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
757 HCLGE_CFG_RSS_SIZE_M,
758 HCLGE_CFG_RSS_SIZE_S);
0e7a40cd 759
46a3df9f
S		 760 for (i = 0; i < ETH_ALEN; i++)
761 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
762
d44f9b63 763 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 764 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
0979aa0b 765
e4e87715
PL		 766 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
767 HCLGE_CFG_SPEED_ABILITY_M,
768 HCLGE_CFG_SPEED_ABILITY_S);
46a3df9f
S		 769}
770
771/* hclge_get_cfg: query the static parameter from flash
772 * @hdev: pointer to struct hclge_dev
773 * @hcfg: the config structure to be getted
774 */
775static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
776{
777 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 778 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 779 int i, ret;
780
781 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 782 u32 offset = 0;
783
d44f9b63 784 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 785 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
786 true);
e4e87715
PL		 787 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
788 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
46a3df9f 789 /* Len should be united by 4 bytes when send to hardware */
e4e87715
PL		 790 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
791 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 792 req->offset = cpu_to_le32(offset);
46a3df9f
S		 793 }
794
795 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
796 if (ret) {
3f639907 797 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
46a3df9f
S		 798 return ret;
799 }
800
801 hclge_parse_cfg(hcfg, desc);
3f639907 802
46a3df9f
S		 803 return 0;
804}
805
806static int hclge_get_cap(struct hclge_dev *hdev)
807{
808 int ret;
809
810 ret = hclge_query_function_status(hdev);
811 if (ret) {
812 dev_err(&hdev->pdev->dev,
813 "query function status error %d.\n", ret);
814 return ret;
815 }
816
817 /* get pf resource */
818 ret = hclge_query_pf_resource(hdev);
3f639907
JS		 819 if (ret)
820 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
46a3df9f 821
3f639907 822 return ret;
46a3df9f
S		 823}
824
825static int hclge_configure(struct hclge_dev *hdev)
826{
827 struct hclge_cfg cfg;
828 int ret, i;
829
830 ret = hclge_get_cfg(hdev, &cfg);
831 if (ret) {
832 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
833 return ret;
834 }
835
836 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
837 hdev->base_tqp_pid = 0;
0e7a40cd 838 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 839 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 840 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 841 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 842 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 843 hdev->num_desc = cfg.tqp_desc_num;
844 hdev->tm_info.num_pg = 1;
cacde272 845 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 846 hdev->tm_info.hw_pfc_map = 0;
847
848 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
849 if (ret) {
850 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
851 return ret;
852 }
853
0979aa0b
FL		 854 hclge_parse_link_mode(hdev, cfg.speed_ability);
855
cacde272
YL		 856 if ((hdev->tc_max > HNAE3_MAX_TC) ||
857 (hdev->tc_max < 1)) {
46a3df9f 858 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 859 hdev->tc_max);
860 hdev->tc_max = 1;
46a3df9f
S		 861 }
862
cacde272
YL		 863 /* Dev does not support DCB */
864 if (!hnae3_dev_dcb_supported(hdev)) {
865 hdev->tc_max = 1;
866 hdev->pfc_max = 0;
867 } else {
868 hdev->pfc_max = hdev->tc_max;
869 }
870
871 hdev->tm_info.num_tc = hdev->tc_max;
872
46a3df9f 873 /* Currently not support uncontiuous tc */
cacde272 874 for (i = 0; i < hdev->tm_info.num_tc; i++)
e4e87715 875 hnae3_set_bit(hdev->hw_tc_map, i, 1);
46a3df9f 876
71b83869 877 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 878
879 return ret;
880}
881
882static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
883 int tso_mss_max)
884{
d44f9b63 885 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 886 struct hclge_desc desc;
a90bb9a5 887 u16 tso_mss;
46a3df9f
S		 888
889 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
890
d44f9b63 891 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 892
893 tso_mss = 0;
e4e87715
PL		 894 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
895 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 896 req->tso_mss_min = cpu_to_le16(tso_mss);
897
898 tso_mss = 0;
e4e87715
PL		 899 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
900 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 901 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 902
903 return hclge_cmd_send(&hdev->hw, &desc, 1);
904}
905
906static int hclge_alloc_tqps(struct hclge_dev *hdev)
907{
908 struct hclge_tqp *tqp;
909 int i;
910
911 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
912 sizeof(struct hclge_tqp), GFP_KERNEL);
913 if (!hdev->htqp)
914 return -ENOMEM;
915
916 tqp = hdev->htqp;
917
918 for (i = 0; i < hdev->num_tqps; i++) {
919 tqp->dev = &hdev->pdev->dev;
920 tqp->index = i;
921
922 tqp->q.ae_algo = &ae_algo;
923 tqp->q.buf_size = hdev->rx_buf_len;
924 tqp->q.desc_num = hdev->num_desc;
925 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
926 i * HCLGE_TQP_REG_SIZE;
927
928 tqp++;
929 }
930
931 return 0;
932}
933
934static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
935 u16 tqp_pid, u16 tqp_vid, bool is_pf)
936{
d44f9b63 937 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 938 struct hclge_desc desc;
939 int ret;
940
941 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
942
d44f9b63 943 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 944 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 945 req->tqp_vf = func_id;
46a3df9f
S		 946 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
947 1 << HCLGE_TQP_MAP_EN_B;
948 req->tqp_vid = cpu_to_le16(tqp_vid);
949
950 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907
JS		 951 if (ret)
952 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
46a3df9f 953
3f639907 954 return ret;
46a3df9f
S		 955}
956
128b900d 957static int hclge_assign_tqp(struct hclge_vport *vport)
46a3df9f 958{
128b900d 959 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
46a3df9f 960 struct hclge_dev *hdev = vport->back;
7df7dad6 961 int i, alloced;
46a3df9f
S		 962
963 for (i = 0, alloced = 0; i < hdev->num_tqps &&
128b900d 964 alloced < kinfo->num_tqps; i++) {
46a3df9f
S		 965 if (!hdev->htqp[i].alloced) {
966 hdev->htqp[i].q.handle = &vport->nic;
967 hdev->htqp[i].q.tqp_index = alloced;
128b900d
YL		 968 hdev->htqp[i].q.desc_num = kinfo->num_desc;
969 kinfo->tqp[alloced] = &hdev->htqp[i].q;
46a3df9f 970 hdev->htqp[i].alloced = true;
46a3df9f
S		 971 alloced++;
972 }
973 }
128b900d 974 vport->alloc_tqps = kinfo->num_tqps;
46a3df9f
S		 975
976 return 0;
977}
978
128b900d
YL		 979static int hclge_knic_setup(struct hclge_vport *vport,
980 u16 num_tqps, u16 num_desc)
46a3df9f
S		 981{
982 struct hnae3_handle *nic = &vport->nic;
983 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
984 struct hclge_dev *hdev = vport->back;
985 int i, ret;
986
128b900d 987 kinfo->num_desc = num_desc;
46a3df9f
S		 988 kinfo->rx_buf_len = hdev->rx_buf_len;
989 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
990 kinfo->rss_size
991 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
992 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
993
994 for (i = 0; i < HNAE3_MAX_TC; i++) {
995 if (hdev->hw_tc_map & BIT(i)) {
996 kinfo->tc_info[i].enable = true;
997 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
998 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
999 kinfo->tc_info[i].tc = i;
1000 } else {
1001 /* Set to default queue if TC is disable */
1002 kinfo->tc_info[i].enable = false;
1003 kinfo->tc_info[i].tqp_offset = 0;
1004 kinfo->tc_info[i].tqp_count = 1;
1005 kinfo->tc_info[i].tc = 0;
1006 }
1007 }
1008
1009 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1010 sizeof(struct hnae3_queue *), GFP_KERNEL);
1011 if (!kinfo->tqp)
1012 return -ENOMEM;
1013
128b900d 1014 ret = hclge_assign_tqp(vport);
3f639907 1015 if (ret)
46a3df9f 1016 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
46a3df9f 1017
3f639907 1018 return ret;
46a3df9f
S		 1019}
1020
7df7dad6
L		 1021static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1022 struct hclge_vport *vport)
1023{
1024 struct hnae3_handle *nic = &vport->nic;
1025 struct hnae3_knic_private_info *kinfo;
1026 u16 i;
1027
1028 kinfo = &nic->kinfo;
1029 for (i = 0; i < kinfo->num_tqps; i++) {
1030 struct hclge_tqp *q =
1031 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1032 bool is_pf;
1033 int ret;
1034
1035 is_pf = !(vport->vport_id);
1036 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1037 i, is_pf);
1038 if (ret)
1039 return ret;
1040 }
1041
1042 return 0;
1043}
1044
1045static int hclge_map_tqp(struct hclge_dev *hdev)
1046{
1047 struct hclge_vport *vport = hdev->vport;
1048 u16 i, num_vport;
1049
1050 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1051 for (i = 0; i < num_vport; i++) {
1052 int ret;
1053
1054 ret = hclge_map_tqp_to_vport(hdev, vport);
1055 if (ret)
1056 return ret;
1057
1058 vport++;
1059 }
1060
1061 return 0;
1062}
1063
46a3df9f
S		 1064static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1065{
1066 /* this would be initialized later */
1067}
1068
1069static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1070{
1071 struct hnae3_handle *nic = &vport->nic;
1072 struct hclge_dev *hdev = vport->back;
1073 int ret;
1074
1075 nic->pdev = hdev->pdev;
1076 nic->ae_algo = &ae_algo;
1077 nic->numa_node_mask = hdev->numa_node_mask;
1078
1079 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
128b900d 1080 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
46a3df9f
S		 1081 if (ret) {
1082 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1083 ret);
1084 return ret;
1085 }
1086 } else {
1087 hclge_unic_setup(vport, num_tqps);
1088 }
1089
1090 return 0;
1091}
1092
1093static int hclge_alloc_vport(struct hclge_dev *hdev)
1094{
1095 struct pci_dev *pdev = hdev->pdev;
1096 struct hclge_vport *vport;
1097 u32 tqp_main_vport;
1098 u32 tqp_per_vport;
1099 int num_vport, i;
1100 int ret;
1101
1102 /* We need to alloc a vport for main NIC of PF */
1103 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1104
38e62046
HT		 1105 if (hdev->num_tqps < num_vport) {
1106 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1107 hdev->num_tqps, num_vport);
1108 return -EINVAL;
1109 }
46a3df9f
S		 1110
1111 /* Alloc the same number of TQPs for every vport */
1112 tqp_per_vport = hdev->num_tqps / num_vport;
1113 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1114
1115 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1116 GFP_KERNEL);
1117 if (!vport)
1118 return -ENOMEM;
1119
1120 hdev->vport = vport;
1121 hdev->num_alloc_vport = num_vport;
1122
2312e050
FL		 1123 if (IS_ENABLED(CONFIG_PCI_IOV))
1124 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1125
1126 for (i = 0; i < num_vport; i++) {
1127 vport->back = hdev;
1128 vport->vport_id = i;
1129
1130 if (i == 0)
1131 ret = hclge_vport_setup(vport, tqp_main_vport);
1132 else
1133 ret = hclge_vport_setup(vport, tqp_per_vport);
1134 if (ret) {
1135 dev_err(&pdev->dev,
1136 "vport setup failed for vport %d, %d\n",
1137 i, ret);
1138 return ret;
1139 }
1140
1141 vport++;
1142 }
1143
1144 return 0;
1145}
1146
acf61ecd
YL		 1147static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1148 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1149{
1150/* TX buffer size is unit by 128 byte */
1151#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1152#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1153 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1154 struct hclge_desc desc;
1155 int ret;
1156 u8 i;
1157
d44f9b63 1158 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1159
1160 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1161 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1162 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1163
46a3df9f
S		 1164 req->tx_pkt_buff[i] =
1165 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1166 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1167 }
46a3df9f
S		 1168
1169 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1170 if (ret)
46a3df9f
S		 1171 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1172 ret);
46a3df9f 1173
3f639907 1174 return ret;
46a3df9f
S		 1175}
1176
acf61ecd
YL		 1177static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1178 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1179{
acf61ecd 1180 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f 1181
3f639907
JS		 1182 if (ret)
1183 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
46a3df9f 1184
3f639907 1185 return ret;
46a3df9f
S		 1186}
1187
1188static int hclge_get_tc_num(struct hclge_dev *hdev)
1189{
1190 int i, cnt = 0;
1191
1192 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1193 if (hdev->hw_tc_map & BIT(i))
1194 cnt++;
1195 return cnt;
1196}
1197
1198static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1199{
1200 int i, cnt = 0;
1201
1202 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1203 if (hdev->hw_tc_map & BIT(i) &&
1204 hdev->tm_info.hw_pfc_map & BIT(i))
1205 cnt++;
1206 return cnt;
1207}
1208
1209/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1210static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1211 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1212{
1213 struct hclge_priv_buf *priv;
1214 int i, cnt = 0;
1215
1216 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1217 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1218 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1219 priv->enable)
1220 cnt++;
1221 }
1222
1223 return cnt;
1224}
1225
1226/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1227static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1228 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1229{
1230 struct hclge_priv_buf *priv;
1231 int i, cnt = 0;
1232
1233 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1234 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1235 if (hdev->hw_tc_map & BIT(i) &&
1236 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1237 priv->enable)
1238 cnt++;
1239 }
1240
1241 return cnt;
1242}
1243
acf61ecd 1244static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1245{
1246 struct hclge_priv_buf *priv;
1247 u32 rx_priv = 0;
1248 int i;
1249
1250 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1251 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1252 if (priv->enable)
1253 rx_priv += priv->buf_size;
1254 }
1255 return rx_priv;
1256}
1257
acf61ecd 1258static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1259{
1260 u32 i, total_tx_size = 0;
1261
1262 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1263 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1264
1265 return total_tx_size;
1266}
1267
acf61ecd
YL		 1268static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1269 struct hclge_pkt_buf_alloc *buf_alloc,
1270 u32 rx_all)
46a3df9f
S		 1271{
1272 u32 shared_buf_min, shared_buf_tc, shared_std;
1273 int tc_num, pfc_enable_num;
1274 u32 shared_buf;
1275 u32 rx_priv;
1276 int i;
1277
1278 tc_num = hclge_get_tc_num(hdev);
1279 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1280
d221df4e
YL		 1281 if (hnae3_dev_dcb_supported(hdev))
1282 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1283 else
1284 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1285
46a3df9f
S		 1286 shared_buf_tc = pfc_enable_num * hdev->mps +
1287 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1288 hdev->mps;
1289 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1290
acf61ecd 1291 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1292 if (rx_all <= rx_priv + shared_std)
1293 return false;
1294
1295 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1296 buf_alloc->s_buf.buf_size = shared_buf;
1297 buf_alloc->s_buf.self.high = shared_buf;
1298 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1299
1300 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1301 if ((hdev->hw_tc_map & BIT(i)) &&
1302 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1303 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1304 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1305 } else {
acf61ecd
YL		 1306 buf_alloc->s_buf.tc_thrd[i].low = 0;
1307 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1308 }
1309 }
1310
1311 return true;
1312}
1313
acf61ecd
YL		 1314static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1315 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1316{
1317 u32 i, total_size;
1318
1319 total_size = hdev->pkt_buf_size;
1320
1321 /* alloc tx buffer for all enabled tc */
1322 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1323 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1324
1325 if (total_size < HCLGE_DEFAULT_TX_BUF)
1326 return -ENOMEM;
1327
1328 if (hdev->hw_tc_map & BIT(i))
1329 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1330 else
1331 priv->tx_buf_size = 0;
1332
1333 total_size -= priv->tx_buf_size;
1334 }
1335
1336 return 0;
1337}
1338
46a3df9f
S		 1339/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1340 * @hdev: pointer to struct hclge_dev
acf61ecd 1341 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1342 * @return: 0: calculate sucessful, negative: fail
1343 */
1db9b1bf
YL		 1344static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1345 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1346{
9ffe79a9 1347 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1348 int no_pfc_priv_num, pfc_priv_num;
1349 struct hclge_priv_buf *priv;
1350 int i;
1351
acf61ecd 1352 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1353
d602a525
YL		 1354 /* When DCB is not supported, rx private
1355 * buffer is not allocated.
1356 */
1357 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1358 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1359 return -ENOMEM;
1360
1361 return 0;
1362 }
1363
46a3df9f
S		 1364 /* step 1, try to alloc private buffer for all enabled tc */
1365 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1366 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1367 if (hdev->hw_tc_map & BIT(i)) {
1368 priv->enable = 1;
1369 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1370 priv->wl.low = hdev->mps;
1371 priv->wl.high = priv->wl.low + hdev->mps;
1372 priv->buf_size = priv->wl.high +
1373 HCLGE_DEFAULT_DV;
1374 } else {
1375 priv->wl.low = 0;
1376 priv->wl.high = 2 * hdev->mps;
1377 priv->buf_size = priv->wl.high;
1378 }
bb1fe9ea
YL		 1379 } else {
1380 priv->enable = 0;
1381 priv->wl.low = 0;
1382 priv->wl.high = 0;
1383 priv->buf_size = 0;
46a3df9f
S		 1384 }
1385 }
1386
acf61ecd 1387 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1388 return 0;
1389
1390 /* step 2, try to decrease the buffer size of
1391 * no pfc TC's private buffer
1392 */
1393 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1394 priv = &buf_alloc->priv_buf[i];
46a3df9f 1395
bb1fe9ea
YL		 1396 priv->enable = 0;
1397 priv->wl.low = 0;
1398 priv->wl.high = 0;
1399 priv->buf_size = 0;
1400
1401 if (!(hdev->hw_tc_map & BIT(i)))
1402 continue;
1403
1404 priv->enable = 1;
46a3df9f
S		 1405
1406 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1407 priv->wl.low = 128;
1408 priv->wl.high = priv->wl.low + hdev->mps;
1409 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1410 } else {
1411 priv->wl.low = 0;
1412 priv->wl.high = hdev->mps;
1413 priv->buf_size = priv->wl.high;
1414 }
1415 }
1416
acf61ecd 1417 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1418 return 0;
1419
1420 /* step 3, try to reduce the number of pfc disabled TCs,
1421 * which have private buffer
1422 */
1423 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1424 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1425
1426 /* let the last to be cleared first */
1427 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1428 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1429
1430 if (hdev->hw_tc_map & BIT(i) &&
1431 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1432 /* Clear the no pfc TC private buffer */
1433 priv->wl.low = 0;
1434 priv->wl.high = 0;
1435 priv->buf_size = 0;
1436 priv->enable = 0;
1437 no_pfc_priv_num--;
1438 }
1439
acf61ecd 1440 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1441 no_pfc_priv_num == 0)
1442 break;
1443 }
1444
acf61ecd 1445 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1446 return 0;
1447
1448 /* step 4, try to reduce the number of pfc enabled TCs
1449 * which have private buffer.
1450 */
acf61ecd 1451 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1452
1453 /* let the last to be cleared first */
1454 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1455 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1456
1457 if (hdev->hw_tc_map & BIT(i) &&
1458 hdev->tm_info.hw_pfc_map & BIT(i)) {
1459 /* Reduce the number of pfc TC with private buffer */
1460 priv->wl.low = 0;
1461 priv->enable = 0;
1462 priv->wl.high = 0;
1463 priv->buf_size = 0;
1464 pfc_priv_num--;
1465 }
1466
acf61ecd 1467 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1468 pfc_priv_num == 0)
1469 break;
1470 }
acf61ecd 1471 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1472 return 0;
1473
1474 return -ENOMEM;
1475}
1476
acf61ecd
YL		 1477static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1478 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1479{
d44f9b63 1480 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1481 struct hclge_desc desc;
1482 int ret;
1483 int i;
1484
1485 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1486 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1487
1488 /* Alloc private buffer TCs */
1489 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1490 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1491
1492 req->buf_num[i] =
1493 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1494 req->buf_num[i] |=
5bca3b94 1495 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1496 }
1497
b8c8bf47 1498 req->shared_buf =
acf61ecd 1499 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1500 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1501
46a3df9f 1502 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1503 if (ret)
46a3df9f
S		 1504 dev_err(&hdev->pdev->dev,
1505 "rx private buffer alloc cmd failed %d\n", ret);
46a3df9f 1506
3f639907 1507 return ret;
46a3df9f
S		 1508}
1509
acf61ecd
YL		 1510static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1511 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1512{
1513 struct hclge_rx_priv_wl_buf *req;
1514 struct hclge_priv_buf *priv;
1515 struct hclge_desc desc[2];
1516 int i, j;
1517 int ret;
1518
1519 for (i = 0; i < 2; i++) {
1520 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1521 false);
1522 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1523
1524 /* The first descriptor set the NEXT bit to 1 */
1525 if (i == 0)
1526 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1527 else
1528 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1529
1530 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1531 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1532
1533 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1534 req->tc_wl[j].high =
1535 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1536 req->tc_wl[j].high |=
3738287c 1537 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1538 req->tc_wl[j].low =
1539 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1540 req->tc_wl[j].low |=
3738287c 1541 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1542 }
1543 }
1544
1545 /* Send 2 descriptor at one time */
1546 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3f639907 1547 if (ret)
46a3df9f
S		 1548 dev_err(&hdev->pdev->dev,
1549 "rx private waterline config cmd failed %d\n",
1550 ret);
3f639907 1551 return ret;
46a3df9f
S		 1552}
1553
acf61ecd
YL		 1554static int hclge_common_thrd_config(struct hclge_dev *hdev,
1555 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1556{
acf61ecd 1557 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1558 struct hclge_rx_com_thrd *req;
1559 struct hclge_desc desc[2];
1560 struct hclge_tc_thrd *tc;
1561 int i, j;
1562 int ret;
1563
1564 for (i = 0; i < 2; i++) {
1565 hclge_cmd_setup_basic_desc(&desc[i],
1566 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1567 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1568
1569 /* The first descriptor set the NEXT bit to 1 */
1570 if (i == 0)
1571 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1572 else
1573 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1574
1575 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1576 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1577
1578 req->com_thrd[j].high =
1579 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1580 req->com_thrd[j].high |=
3738287c 1581 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1582 req->com_thrd[j].low =
1583 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1584 req->com_thrd[j].low |=
3738287c 1585 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1586 }
1587 }
1588
1589 /* Send 2 descriptors at one time */
1590 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3f639907 1591 if (ret)
46a3df9f
S		 1592 dev_err(&hdev->pdev->dev,
1593 "common threshold config cmd failed %d\n", ret);
3f639907 1594 return ret;
46a3df9f
S		 1595}
1596
acf61ecd
YL		 1597static int hclge_common_wl_config(struct hclge_dev *hdev,
1598 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1599{
acf61ecd 1600 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1601 struct hclge_rx_com_wl *req;
1602 struct hclge_desc desc;
1603 int ret;
1604
1605 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1606
1607 req = (struct hclge_rx_com_wl *)desc.data;
1608 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
3738287c 1609 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1610
1611 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
3738287c 1612 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1613
1614 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1615 if (ret)
46a3df9f
S		 1616 dev_err(&hdev->pdev->dev,
1617 "common waterline config cmd failed %d\n", ret);
46a3df9f 1618
3f639907 1619 return ret;
46a3df9f
S		 1620}
1621
1622int hclge_buffer_alloc(struct hclge_dev *hdev)
1623{
acf61ecd 1624 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1625 int ret;
1626
acf61ecd
YL		 1627 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1628 if (!pkt_buf)
46a3df9f
S		 1629 return -ENOMEM;
1630
acf61ecd 1631 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1632 if (ret) {
1633 dev_err(&hdev->pdev->dev,
1634 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1635 goto out;
9ffe79a9
YL		 1636 }
1637
acf61ecd 1638 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1639 if (ret) {
1640 dev_err(&hdev->pdev->dev,
1641 "could not alloc tx buffers %d\n", ret);
acf61ecd 1642 goto out;
46a3df9f
S		 1643 }
1644
acf61ecd 1645 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1646 if (ret) {
1647 dev_err(&hdev->pdev->dev,
1648 "could not calc rx priv buffer size for all TCs %d\n",
1649 ret);
acf61ecd 1650 goto out;
46a3df9f
S		 1651 }
1652
acf61ecd 1653 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1654 if (ret) {
1655 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1656 ret);
acf61ecd 1657 goto out;
46a3df9f
S		 1658 }
1659
2daf4a65 1660 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1661 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1662 if (ret) {
1663 dev_err(&hdev->pdev->dev,
1664 "could not configure rx private waterline %d\n",
1665 ret);
acf61ecd 1666 goto out;
2daf4a65 1667 }
46a3df9f 1668
acf61ecd 1669 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1670 if (ret) {
1671 dev_err(&hdev->pdev->dev,
1672 "could not configure common threshold %d\n",
1673 ret);
acf61ecd 1674 goto out;
2daf4a65 1675 }
46a3df9f
S		 1676 }
1677
acf61ecd
YL		 1678 ret = hclge_common_wl_config(hdev, pkt_buf);
1679 if (ret)
46a3df9f
S		 1680 dev_err(&hdev->pdev->dev,
1681 "could not configure common waterline %d\n", ret);
46a3df9f 1682
acf61ecd
YL		 1683out:
1684 kfree(pkt_buf);
1685 return ret;
46a3df9f
S		 1686}
1687
1688static int hclge_init_roce_base_info(struct hclge_vport *vport)
1689{
1690 struct hnae3_handle *roce = &vport->roce;
1691 struct hnae3_handle *nic = &vport->nic;
1692
887c3820 1693 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 1694
1695 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1696 vport->back->num_msi_left == 0)
1697 return -EINVAL;
1698
1699 roce->rinfo.base_vector = vport->back->roce_base_vector;
1700
1701 roce->rinfo.netdev = nic->kinfo.netdev;
1702 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1703
1704 roce->pdev = nic->pdev;
1705 roce->ae_algo = nic->ae_algo;
1706 roce->numa_node_mask = nic->numa_node_mask;
1707
1708 return 0;
1709}
1710
887c3820 1711static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 1712{
1713 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 1714 int vectors;
1715 int i;
46a3df9f 1716
887c3820
SM		 1717 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1718 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1719 if (vectors < 0) {
1720 dev_err(&pdev->dev,
1721 "failed(%d) to allocate MSI/MSI-X vectors\n",
1722 vectors);
1723 return vectors;
46a3df9f 1724 }
887c3820
SM		 1725 if (vectors < hdev->num_msi)
1726 dev_warn(&hdev->pdev->dev,
1727 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1728 hdev->num_msi, vectors);
46a3df9f 1729
887c3820
SM		 1730 hdev->num_msi = vectors;
1731 hdev->num_msi_left = vectors;
1732 hdev->base_msi_vector = pdev->irq;
46a3df9f 1733 hdev->roce_base_vector = hdev->base_msi_vector +
375dd5e4 1734 hdev->roce_base_msix_offset;
46a3df9f 1735
46a3df9f
S		 1736 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1737 sizeof(u16), GFP_KERNEL);
887c3820
SM		 1738 if (!hdev->vector_status) {
1739 pci_free_irq_vectors(pdev);
46a3df9f 1740 return -ENOMEM;
887c3820 1741 }
46a3df9f
S		 1742
1743 for (i = 0; i < hdev->num_msi; i++)
1744 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1745
887c3820
SM		 1746 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1747 sizeof(int), GFP_KERNEL);
1748 if (!hdev->vector_irq) {
1749 pci_free_irq_vectors(pdev);
1750 return -ENOMEM;
46a3df9f 1751 }
46a3df9f
S		 1752
1753 return 0;
1754}
1755
2d03eacc 1756static u8 hclge_check_speed_dup(u8 duplex, int speed)
46a3df9f 1757{
46a3df9f 1758
2d03eacc
YL		 1759 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
1760 duplex = HCLGE_MAC_FULL;
46a3df9f 1761
2d03eacc 1762 return duplex;
46a3df9f
S		 1763}
1764
2d03eacc
YL		 1765static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1766 u8 duplex)
46a3df9f 1767{
d44f9b63 1768 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 1769 struct hclge_desc desc;
1770 int ret;
1771
d44f9b63 1772 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 1773
1774 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1775
e4e87715 1776 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
46a3df9f
S		 1777
1778 switch (speed) {
1779 case HCLGE_MAC_SPEED_10M:
e4e87715
PL		 1780 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1781 HCLGE_CFG_SPEED_S, 6);
46a3df9f
S		 1782 break;
1783 case HCLGE_MAC_SPEED_100M:
e4e87715
PL		 1784 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1785 HCLGE_CFG_SPEED_S, 7);
46a3df9f
S		 1786 break;
1787 case HCLGE_MAC_SPEED_1G:
e4e87715
PL		 1788 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1789 HCLGE_CFG_SPEED_S, 0);
46a3df9f
S		 1790 break;
1791 case HCLGE_MAC_SPEED_10G:
e4e87715
PL		 1792 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1793 HCLGE_CFG_SPEED_S, 1);
46a3df9f
S		 1794 break;
1795 case HCLGE_MAC_SPEED_25G:
e4e87715
PL		 1796 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1797 HCLGE_CFG_SPEED_S, 2);
46a3df9f
S		 1798 break;
1799 case HCLGE_MAC_SPEED_40G:
e4e87715
PL		 1800 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1801 HCLGE_CFG_SPEED_S, 3);
46a3df9f
S		 1802 break;
1803 case HCLGE_MAC_SPEED_50G:
e4e87715
PL		 1804 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1805 HCLGE_CFG_SPEED_S, 4);
46a3df9f
S		 1806 break;
1807 case HCLGE_MAC_SPEED_100G:
e4e87715
PL		 1808 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1809 HCLGE_CFG_SPEED_S, 5);
46a3df9f
S		 1810 break;
1811 default:
d7629e74 1812 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 1813 return -EINVAL;
1814 }
1815
e4e87715
PL		 1816 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1817 1);
46a3df9f
S		 1818
1819 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1820 if (ret) {
1821 dev_err(&hdev->pdev->dev,
1822 "mac speed/duplex config cmd failed %d.\n", ret);
1823 return ret;
1824 }
1825
2d03eacc
YL		 1826 return 0;
1827}
1828
1829int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1830{
1831 int ret;
1832
1833 duplex = hclge_check_speed_dup(duplex, speed);
1834 if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
1835 return 0;
1836
1837 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
1838 if (ret)
1839 return ret;
1840
1841 hdev->hw.mac.speed = speed;
1842 hdev->hw.mac.duplex = duplex;
46a3df9f
S		 1843
1844 return 0;
1845}
1846
1847static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1848 u8 duplex)
1849{
1850 struct hclge_vport *vport = hclge_get_vport(handle);
1851 struct hclge_dev *hdev = vport->back;
1852
1853 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1854}
1855
1856static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
1857 u8 *duplex)
1858{
d44f9b63 1859 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 1860 struct hclge_desc desc;
1861 int speed_tmp;
1862 int ret;
1863
d44f9b63 1864 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 1865
1866 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
1867 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1868 if (ret) {
1869 dev_err(&hdev->pdev->dev,
1870 "mac speed/autoneg/duplex query cmd failed %d\n",
1871 ret);
1872 return ret;
1873 }
1874
e4e87715
PL		 1875 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
1876 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
1877 HCLGE_QUERY_SPEED_S);
46a3df9f
S		 1878
1879 ret = hclge_parse_speed(speed_tmp, speed);
3f639907 1880 if (ret)
46a3df9f
S		 1881 dev_err(&hdev->pdev->dev,
1882 "could not parse speed(=%d), %d\n", speed_tmp, ret);
46a3df9f 1883
3f639907 1884 return ret;
46a3df9f
S		 1885}
1886
46a3df9f
S		 1887static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
1888{
d44f9b63 1889 struct hclge_config_auto_neg_cmd *req;
46a3df9f 1890 struct hclge_desc desc;
a90bb9a5 1891 u32 flag = 0;
46a3df9f
S		 1892 int ret;
1893
1894 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
1895
d44f9b63 1896 req = (struct hclge_config_auto_neg_cmd *)desc.data;
e4e87715 1897 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
a90bb9a5 1898 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 1899
1900 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1901 if (ret)
46a3df9f
S		 1902 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
1903 ret);
46a3df9f 1904
3f639907 1905 return ret;
46a3df9f
S		 1906}
1907
1908static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
1909{
1910 struct hclge_vport *vport = hclge_get_vport(handle);
1911 struct hclge_dev *hdev = vport->back;
1912
1913 return hclge_set_autoneg_en(hdev, enable);
1914}
1915
1916static int hclge_get_autoneg(struct hnae3_handle *handle)
1917{
1918 struct hclge_vport *vport = hclge_get_vport(handle);
1919 struct hclge_dev *hdev = vport->back;
27b5bf49
FL		 1920 struct phy_device *phydev = hdev->hw.mac.phydev;
1921
1922 if (phydev)
1923 return phydev->autoneg;
46a3df9f
S		 1924
1925 return hdev->hw.mac.autoneg;
1926}
1927
7564094c
PL		 1928static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
1929 bool mask_vlan,
1930 u8 *mac_mask)
1931{
1932 struct hclge_mac_vlan_mask_entry_cmd *req;
1933 struct hclge_desc desc;
1934 int status;
1935
1936 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
1937 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
1938
e4e87715
PL		 1939 hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
1940 mask_vlan ? 1 : 0);
7564094c
PL		 1941 ether_addr_copy(req->mac_mask, mac_mask);
1942
1943 status = hclge_cmd_send(&hdev->hw, &desc, 1);
1944 if (status)
1945 dev_err(&hdev->pdev->dev,
1946 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
1947 status);
1948
1949 return status;
1950}
1951
46a3df9f
S		 1952static int hclge_mac_init(struct hclge_dev *hdev)
1953{
f9fd82a9
FL		 1954 struct hnae3_handle *handle = &hdev->vport[0].nic;
1955 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 1956 struct hclge_mac *mac = &hdev->hw.mac;
7564094c 1957 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
40cca1c5 1958 struct hclge_vport *vport;
f9fd82a9 1959 int mtu;
46a3df9f 1960 int ret;
40cca1c5 1961 int i;
46a3df9f 1962
2d03eacc
YL		 1963 hdev->hw.mac.duplex = HCLGE_MAC_FULL;
1964 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
1965 hdev->hw.mac.duplex);
46a3df9f
S		 1966 if (ret) {
1967 dev_err(&hdev->pdev->dev,
1968 "Config mac speed dup fail ret=%d\n", ret);
1969 return ret;
1970 }
1971
1972 mac->link = 0;
1973
46a3df9f 1974 /* Initialize the MTA table work mode */
46a3df9f
S		 1975 hdev->enable_mta = true;
1976 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
1977
1978 ret = hclge_set_mta_filter_mode(hdev,
1979 hdev->mta_mac_sel_type,
1980 hdev->enable_mta);
1981 if (ret) {
1982 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
1983 ret);
1984 return ret;
1985 }
1986
40cca1c5
XW		 1987 for (i = 0; i < hdev->num_alloc_vport; i++) {
1988 vport = &hdev->vport[i];
1989 vport->accept_mta_mc = false;
1990
1991 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
1992 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
1993 if (ret) {
1994 dev_err(&hdev->pdev->dev,
1995 "set mta filter mode fail ret=%d\n", ret);
1996 return ret;
1997 }
7564094c
PL		 1998 }
1999
2000 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
f9fd82a9 2001 if (ret) {
7564094c
PL		 2002 dev_err(&hdev->pdev->dev,
2003 "set default mac_vlan_mask fail ret=%d\n", ret);
f9fd82a9
FL		 2004 return ret;
2005 }
7564094c 2006
f9fd82a9
FL		 2007 if (netdev)
2008 mtu = netdev->mtu;
2009 else
2010 mtu = ETH_DATA_LEN;
2011
2012 ret = hclge_set_mtu(handle, mtu);
3f639907 2013 if (ret)
f9fd82a9
FL		 2014 dev_err(&hdev->pdev->dev,
2015 "set mtu failed ret=%d\n", ret);
f9fd82a9 2016
3f639907 2017 return ret;
46a3df9f
S		 2018}
2019
c1a81619
SM		 2020static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2021{
2022 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2023 schedule_work(&hdev->mbx_service_task);
2024}
2025
cb1b9f77
SM		 2026static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2027{
2028 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2029 schedule_work(&hdev->rst_service_task);
2030}
2031
46a3df9f
S		 2032static void hclge_task_schedule(struct hclge_dev *hdev)
2033{
2034 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2035 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2036 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2037 (void)schedule_work(&hdev->service_task);
2038}
2039
2040static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2041{
d44f9b63 2042 struct hclge_link_status_cmd *req;
46a3df9f
S		 2043 struct hclge_desc desc;
2044 int link_status;
2045 int ret;
2046
2047 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2048 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2049 if (ret) {
2050 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2051 ret);
2052 return ret;
2053 }
2054
d44f9b63 2055 req = (struct hclge_link_status_cmd *)desc.data;
c79301d8 2056 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
46a3df9f
S		 2057
2058 return !!link_status;
2059}
2060
2061static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2062{
2063 int mac_state;
2064 int link_stat;
2065
582d37bb
PL		 2066 if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2067 return 0;
2068
46a3df9f
S		 2069 mac_state = hclge_get_mac_link_status(hdev);
2070
2071 if (hdev->hw.mac.phydev) {
fd813314 2072 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
46a3df9f
S		 2073 link_stat = mac_state &
2074 hdev->hw.mac.phydev->link;
2075 else
2076 link_stat = 0;
2077
2078 } else {
2079 link_stat = mac_state;
2080 }
2081
2082 return !!link_stat;
2083}
2084
2085static void hclge_update_link_status(struct hclge_dev *hdev)
2086{
2087 struct hnae3_client *client = hdev->nic_client;
2088 struct hnae3_handle *handle;
2089 int state;
2090 int i;
2091
2092 if (!client)
2093 return;
2094 state = hclge_get_mac_phy_link(hdev);
2095 if (state != hdev->hw.mac.link) {
2096 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2097 handle = &hdev->vport[i].nic;
2098 client->ops->link_status_change(handle, state);
2099 }
2100 hdev->hw.mac.link = state;
2101 }
2102}
2103
2104static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2105{
2106 struct hclge_mac mac = hdev->hw.mac;
2107 u8 duplex;
2108 int speed;
2109 int ret;
2110
2111 /* get the speed and duplex as autoneg'result from mac cmd when phy
2112 * doesn't exit.
2113 */
c040366b 2114 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2115 return 0;
2116
2117 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2118 if (ret) {
2119 dev_err(&hdev->pdev->dev,
2120 "mac autoneg/speed/duplex query failed %d\n", ret);
2121 return ret;
2122 }
2123
2d03eacc
YL		 2124 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2125 if (ret) {
2126 dev_err(&hdev->pdev->dev,
2127 "mac speed/duplex config failed %d\n", ret);
2128 return ret;
46a3df9f
S		 2129 }
2130
2131 return 0;
2132}
2133
2134static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2135{
2136 struct hclge_vport *vport = hclge_get_vport(handle);
2137 struct hclge_dev *hdev = vport->back;
2138
2139 return hclge_update_speed_duplex(hdev);
2140}
2141
2142static int hclge_get_status(struct hnae3_handle *handle)
2143{
2144 struct hclge_vport *vport = hclge_get_vport(handle);
2145 struct hclge_dev *hdev = vport->back;
2146
2147 hclge_update_link_status(hdev);
2148
2149 return hdev->hw.mac.link;
2150}
2151
d039ef68 2152static void hclge_service_timer(struct timer_list *t)
46a3df9f 2153{
d039ef68 2154 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2155
d039ef68 2156 mod_timer(&hdev->service_timer, jiffies + HZ);
c5f65480 2157 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2158 hclge_task_schedule(hdev);
2159}
2160
2161static void hclge_service_complete(struct hclge_dev *hdev)
2162{
2163 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2164
2165 /* Flush memory before next watchdog */
2166 smp_mb__before_atomic();
2167 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2168}
2169
ca1d7669
SM		 2170static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2171{
2172 u32 rst_src_reg;
c1a81619 2173 u32 cmdq_src_reg;
ca1d7669
SM		 2174
2175 /* fetch the events from their corresponding regs */
9ca8d1a7 2176 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
c1a81619
SM		 2177 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2178
2179 /* Assumption: If by any chance reset and mailbox events are reported
2180 * together then we will only process reset event in this go and will
2181 * defer the processing of the mailbox events. Since, we would have not
2182 * cleared RX CMDQ event this time we would receive again another
2183 * interrupt from H/W just for the mailbox.
2184 */
ca1d7669
SM		 2185
2186 /* check for vector0 reset event sources */
2187 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
8d40854f 2188 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
ca1d7669
SM		 2189 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2190 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2191 return HCLGE_VECTOR0_EVENT_RST;
2192 }
2193
2194 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
8d40854f 2195 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
ca1d7669
SM		 2196 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2197 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2198 return HCLGE_VECTOR0_EVENT_RST;
2199 }
2200
2201 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2202 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2203 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2204 return HCLGE_VECTOR0_EVENT_RST;
2205 }
2206
c1a81619
SM		 2207 /* check for vector0 mailbox(=CMDQ RX) event source */
2208 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2209 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2210 *clearval = cmdq_src_reg;
2211 return HCLGE_VECTOR0_EVENT_MBX;
2212 }
ca1d7669
SM		 2213
2214 return HCLGE_VECTOR0_EVENT_OTHER;
2215}
2216
2217static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2218 u32 regclr)
2219{
c1a81619
SM		 2220 switch (event_type) {
2221 case HCLGE_VECTOR0_EVENT_RST:
ca1d7669 2222 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
c1a81619
SM		 2223 break;
2224 case HCLGE_VECTOR0_EVENT_MBX:
2225 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2226 break;
fa7a4bd5
JS		 2227 default:
2228 break;
c1a81619 2229 }
ca1d7669
SM		 2230}
2231
8e52a602
XW		 2232static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2233{
2234 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2235 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2236 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2237 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2238 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2239}
2240
466b0c00
L		 2241static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2242{
2243 writel(enable ? 1 : 0, vector->addr);
2244}
2245
2246static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2247{
2248 struct hclge_dev *hdev = data;
ca1d7669
SM		 2249 u32 event_cause;
2250 u32 clearval;
466b0c00
L		 2251
2252 hclge_enable_vector(&hdev->misc_vector, false);
ca1d7669
SM		 2253 event_cause = hclge_check_event_cause(hdev, &clearval);
2254
c1a81619 2255 /* vector 0 interrupt is shared with reset and mailbox source events.*/
ca1d7669
SM		 2256 switch (event_cause) {
2257 case HCLGE_VECTOR0_EVENT_RST:
cb1b9f77 2258 hclge_reset_task_schedule(hdev);
ca1d7669 2259 break;
c1a81619
SM		 2260 case HCLGE_VECTOR0_EVENT_MBX:
2261 /* If we are here then,
2262 * 1. Either we are not handling any mbx task and we are not
2263 * scheduled as well
2264 * OR
2265 * 2. We could be handling a mbx task but nothing more is
2266 * scheduled.
2267 * In both cases, we should schedule mbx task as there are more
2268 * mbx messages reported by this interrupt.
2269 */
2270 hclge_mbx_task_schedule(hdev);
f0ad97ac 2271 break;
ca1d7669 2272 default:
f0ad97ac
YL		 2273 dev_warn(&hdev->pdev->dev,
2274 "received unknown or unhandled event of vector0\n");
ca1d7669
SM		 2275 break;
2276 }
2277
cd8c5c26
YL		 2278 /* clear the source of interrupt if it is not cause by reset */
2279 if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2280 hclge_clear_event_cause(hdev, event_cause, clearval);
2281 hclge_enable_vector(&hdev->misc_vector, true);
2282 }
466b0c00
L		 2283
2284 return IRQ_HANDLED;
2285}
2286
2287static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2288{
36cbbdf6
PL		 2289 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2290 dev_warn(&hdev->pdev->dev,
2291 "vector(vector_id %d) has been freed.\n", vector_id);
2292 return;
2293 }
2294
466b0c00
L		 2295 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2296 hdev->num_msi_left += 1;
2297 hdev->num_msi_used -= 1;
2298}
2299
2300static void hclge_get_misc_vector(struct hclge_dev *hdev)
2301{
2302 struct hclge_misc_vector *vector = &hdev->misc_vector;
2303
2304 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2305
2306 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2307 hdev->vector_status[0] = 0;
2308
2309 hdev->num_msi_left -= 1;
2310 hdev->num_msi_used += 1;
2311}
2312
2313static int hclge_misc_irq_init(struct hclge_dev *hdev)
2314{
2315 int ret;
2316
2317 hclge_get_misc_vector(hdev);
2318
ca1d7669
SM		 2319 /* this would be explicitly freed in the end */
2320 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2321 0, "hclge_misc", hdev);
466b0c00
L		 2322 if (ret) {
2323 hclge_free_vector(hdev, 0);
2324 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2325 hdev->misc_vector.vector_irq);
2326 }
2327
2328 return ret;
2329}
2330
ca1d7669
SM		 2331static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2332{
2333 free_irq(hdev->misc_vector.vector_irq, hdev);
2334 hclge_free_vector(hdev, 0);
2335}
2336
4ed340ab
L		 2337static int hclge_notify_client(struct hclge_dev *hdev,
2338 enum hnae3_reset_notify_type type)
2339{
2340 struct hnae3_client *client = hdev->nic_client;
2341 u16 i;
2342
2343 if (!client->ops->reset_notify)
2344 return -EOPNOTSUPP;
2345
2346 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2347 struct hnae3_handle *handle = &hdev->vport[i].nic;
2348 int ret;
2349
2350 ret = client->ops->reset_notify(handle, type);
2351 if (ret)
2352 return ret;
2353 }
2354
2355 return 0;
2356}
2357
2358static int hclge_reset_wait(struct hclge_dev *hdev)
2359{
2360#define HCLGE_RESET_WATI_MS 100
2361#define HCLGE_RESET_WAIT_CNT 5
2362 u32 val, reg, reg_bit;
2363 u32 cnt = 0;
2364
2365 switch (hdev->reset_type) {
2366 case HNAE3_GLOBAL_RESET:
2367 reg = HCLGE_GLOBAL_RESET_REG;
2368 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2369 break;
2370 case HNAE3_CORE_RESET:
2371 reg = HCLGE_GLOBAL_RESET_REG;
2372 reg_bit = HCLGE_CORE_RESET_BIT;
2373 break;
2374 case HNAE3_FUNC_RESET:
2375 reg = HCLGE_FUN_RST_ING;
2376 reg_bit = HCLGE_FUN_RST_ING_B;
2377 break;
2378 default:
2379 dev_err(&hdev->pdev->dev,
2380 "Wait for unsupported reset type: %d\n",
2381 hdev->reset_type);
2382 return -EINVAL;
2383 }
2384
2385 val = hclge_read_dev(&hdev->hw, reg);
e4e87715 2386 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
4ed340ab
L		 2387 msleep(HCLGE_RESET_WATI_MS);
2388 val = hclge_read_dev(&hdev->hw, reg);
2389 cnt++;
2390 }
2391
4ed340ab
L		 2392 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2393 dev_warn(&hdev->pdev->dev,
2394 "Wait for reset timeout: %d\n", hdev->reset_type);
2395 return -EBUSY;
2396 }
2397
2398 return 0;
2399}
2400
2bfbd35d 2401int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2402{
2403 struct hclge_desc desc;
2404 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2405 int ret;
2406
2407 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
e4e87715 2408 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4ed340ab
L		 2409 req->fun_reset_vfid = func_id;
2410
2411 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2412 if (ret)
2413 dev_err(&hdev->pdev->dev,
2414 "send function reset cmd fail, status =%d\n", ret);
2415
2416 return ret;
2417}
2418
f2f432f2 2419static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2420{
2421 struct pci_dev *pdev = hdev->pdev;
2422 u32 val;
2423
f2f432f2 2424 switch (hdev->reset_type) {
4ed340ab
L		 2425 case HNAE3_GLOBAL_RESET:
2426 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e4e87715 2427 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4ed340ab
L		 2428 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2429 dev_info(&pdev->dev, "Global Reset requested\n");
2430 break;
2431 case HNAE3_CORE_RESET:
2432 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e4e87715 2433 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
4ed340ab
L		 2434 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2435 dev_info(&pdev->dev, "Core Reset requested\n");
2436 break;
2437 case HNAE3_FUNC_RESET:
2438 dev_info(&pdev->dev, "PF Reset requested\n");
2439 hclge_func_reset_cmd(hdev, 0);
cb1b9f77
SM		 2440 /* schedule again to check later */
2441 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2442 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2443 break;
2444 default:
2445 dev_warn(&pdev->dev,
f2f432f2 2446 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2447 break;
2448 }
2449}
2450
f2f432f2
SM		 2451static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2452 unsigned long *addr)
2453{
2454 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2455
2456 /* return the highest priority reset level amongst all */
2457 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2458 rst_level = HNAE3_GLOBAL_RESET;
2459 else if (test_bit(HNAE3_CORE_RESET, addr))
2460 rst_level = HNAE3_CORE_RESET;
2461 else if (test_bit(HNAE3_IMP_RESET, addr))
2462 rst_level = HNAE3_IMP_RESET;
2463 else if (test_bit(HNAE3_FUNC_RESET, addr))
2464 rst_level = HNAE3_FUNC_RESET;
2465
2466 /* now, clear all other resets */
2467 clear_bit(HNAE3_GLOBAL_RESET, addr);
2468 clear_bit(HNAE3_CORE_RESET, addr);
2469 clear_bit(HNAE3_IMP_RESET, addr);
2470 clear_bit(HNAE3_FUNC_RESET, addr);
2471
2472 return rst_level;
2473}
2474
cd8c5c26
YL		 2475static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2476{
2477 u32 clearval = 0;
2478
2479 switch (hdev->reset_type) {
2480 case HNAE3_IMP_RESET:
2481 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2482 break;
2483 case HNAE3_GLOBAL_RESET:
2484 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2485 break;
2486 case HNAE3_CORE_RESET:
2487 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2488 break;
2489 default:
cd8c5c26
YL		 2490 break;
2491 }
2492
2493 if (!clearval)
2494 return;
2495
2496 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2497 hclge_enable_vector(&hdev->misc_vector, true);
2498}
2499
f2f432f2
SM		 2500static void hclge_reset(struct hclge_dev *hdev)
2501{
9de0b86f
HT		 2502 struct hnae3_handle *handle;
2503
f2f432f2 2504 /* perform reset of the stack & ae device for a client */
9de0b86f 2505 handle = &hdev->vport[0].nic;
6d4fab39 2506 rtnl_lock();
f2f432f2
SM		 2507 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2508
2509 if (!hclge_reset_wait(hdev)) {
f2f432f2
SM		 2510 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2511 hclge_reset_ae_dev(hdev->ae_dev);
2512 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
cd8c5c26
YL		 2513
2514 hclge_clear_reset_cause(hdev);
f2f432f2
SM		 2515 } else {
2516 /* schedule again to check pending resets later */
2517 set_bit(hdev->reset_type, &hdev->reset_pending);
2518 hclge_reset_task_schedule(hdev);
2519 }
2520
2521 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
9de0b86f 2522 handle->last_reset_time = jiffies;
6d4fab39 2523 rtnl_unlock();
f2f432f2
SM		 2524}
2525
6d4c3981 2526static void hclge_reset_event(struct hnae3_handle *handle)
4ed340ab
L		 2527{
2528 struct hclge_vport *vport = hclge_get_vport(handle);
2529 struct hclge_dev *hdev = vport->back;
2530
6d4c3981
SM		 2531 /* check if this is a new reset request and we are not here just because
2532 * last reset attempt did not succeed and watchdog hit us again. We will
2533 * know this if last reset request did not occur very recently (watchdog
2534 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2535 * In case of new request we reset the "reset level" to PF reset.
9de0b86f
HT		 2536 * And if it is a repeat reset request of the most recent one then we
2537 * want to make sure we throttle the reset request. Therefore, we will
2538 * not allow it again before 3*HZ times.
6d4c3981 2539 */
9de0b86f
HT		 2540 if (time_before(jiffies, (handle->last_reset_time + 3 * HZ)))
2541 return;
2542 else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
6d4c3981 2543 handle->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2544
6d4c3981
SM		 2545 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2546 handle->reset_level);
2547
2548 /* request reset & schedule reset task */
2549 set_bit(handle->reset_level, &hdev->reset_request);
2550 hclge_reset_task_schedule(hdev);
2551
2552 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2553 handle->reset_level++;
4ed340ab
L		 2554}
2555
2556static void hclge_reset_subtask(struct hclge_dev *hdev)
2557{
f2f432f2
SM		 2558 /* check if there is any ongoing reset in the hardware. This status can
2559 * be checked from reset_pending. If there is then, we need to wait for
2560 * hardware to complete reset.
2561 * a. If we are able to figure out in reasonable time that hardware
2562 * has fully resetted then, we can proceed with driver, client
2563 * reset.
2564 * b. else, we can come back later to check this status so re-sched
2565 * now.
2566 */
2567 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2568 if (hdev->reset_type != HNAE3_NONE_RESET)
2569 hclge_reset(hdev);
4ed340ab 2570
f2f432f2
SM		 2571 /* check if we got any *new* reset requests to be honored */
2572 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2573 if (hdev->reset_type != HNAE3_NONE_RESET)
2574 hclge_do_reset(hdev);
4ed340ab 2575
4ed340ab
L		 2576 hdev->reset_type = HNAE3_NONE_RESET;
2577}
2578
cb1b9f77 2579static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2580{
cb1b9f77
SM		 2581 struct hclge_dev *hdev =
2582 container_of(work, struct hclge_dev, rst_service_task);
2583
2584 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2585 return;
2586
2587 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2588
4ed340ab 2589 hclge_reset_subtask(hdev);
cb1b9f77
SM		 2590
2591 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2592}
2593
c1a81619
SM		 2594static void hclge_mailbox_service_task(struct work_struct *work)
2595{
2596 struct hclge_dev *hdev =
2597 container_of(work, struct hclge_dev, mbx_service_task);
2598
2599 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2600 return;
2601
2602 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2603
2604 hclge_mbx_handler(hdev);
2605
2606 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2607}
2608
46a3df9f
S		 2609static void hclge_service_task(struct work_struct *work)
2610{
2611 struct hclge_dev *hdev =
2612 container_of(work, struct hclge_dev, service_task);
2613
c5f65480
JS		 2614 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2615 hclge_update_stats_for_all(hdev);
2616 hdev->hw_stats.stats_timer = 0;
2617 }
2618
46a3df9f
S		 2619 hclge_update_speed_duplex(hdev);
2620 hclge_update_link_status(hdev);
46a3df9f
S		 2621 hclge_service_complete(hdev);
2622}
2623
46a3df9f
S		 2624struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2625{
2626 /* VF handle has no client */
2627 if (!handle->client)
2628 return container_of(handle, struct hclge_vport, nic);
2629 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2630 return container_of(handle, struct hclge_vport, roce);
2631 else
2632 return container_of(handle, struct hclge_vport, nic);
2633}
2634
2635static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2636 struct hnae3_vector_info *vector_info)
2637{
2638 struct hclge_vport *vport = hclge_get_vport(handle);
2639 struct hnae3_vector_info *vector = vector_info;
2640 struct hclge_dev *hdev = vport->back;
2641 int alloc = 0;
2642 int i, j;
2643
2644 vector_num = min(hdev->num_msi_left, vector_num);
2645
2646 for (j = 0; j < vector_num; j++) {
2647 for (i = 1; i < hdev->num_msi; i++) {
2648 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2649 vector->vector = pci_irq_vector(hdev->pdev, i);
2650 vector->io_addr = hdev->hw.io_base +
2651 HCLGE_VECTOR_REG_BASE +
2652 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2653 vport->vport_id *
2654 HCLGE_VECTOR_VF_OFFSET;
2655 hdev->vector_status[i] = vport->vport_id;
887c3820 2656 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2657
2658 vector++;
2659 alloc++;
2660
2661 break;
2662 }
2663 }
2664 }
2665 hdev->num_msi_left -= alloc;
2666 hdev->num_msi_used += alloc;
2667
2668 return alloc;
2669}
2670
2671static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2672{
2673 int i;
2674
887c3820
SM		 2675 for (i = 0; i < hdev->num_msi; i++)
2676 if (vector == hdev->vector_irq[i])
2677 return i;
2678
46a3df9f
S		 2679 return -EINVAL;
2680}
2681
0d3e6631
YL		 2682static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2683{
2684 struct hclge_vport *vport = hclge_get_vport(handle);
2685 struct hclge_dev *hdev = vport->back;
2686 int vector_id;
2687
2688 vector_id = hclge_get_vector_index(hdev, vector);
2689 if (vector_id < 0) {
2690 dev_err(&hdev->pdev->dev,
2691 "Get vector index fail. vector_id =%d\n", vector_id);
2692 return vector_id;
2693 }
2694
2695 hclge_free_vector(hdev, vector_id);
2696
2697 return 0;
2698}
2699
46a3df9f
S		 2700static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2701{
2702 return HCLGE_RSS_KEY_SIZE;
2703}
2704
2705static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2706{
2707 return HCLGE_RSS_IND_TBL_SIZE;
2708}
2709
46a3df9f
S		 2710static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2711 const u8 hfunc, const u8 *key)
2712{
d44f9b63 2713 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2714 struct hclge_desc desc;
2715 int key_offset;
2716 int key_size;
2717 int ret;
2718
d44f9b63 2719 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2720
2721 for (key_offset = 0; key_offset < 3; key_offset++) {
2722 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2723 false);
2724
2725 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2726 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2727
2728 if (key_offset == 2)
2729 key_size =
2730 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2731 else
2732 key_size = HCLGE_RSS_HASH_KEY_NUM;
2733
2734 memcpy(req->hash_key,
2735 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2736
2737 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2738 if (ret) {
2739 dev_err(&hdev->pdev->dev,
2740 "Configure RSS config fail, status = %d\n",
2741 ret);
2742 return ret;
2743 }
2744 }
2745 return 0;
2746}
2747
89523cfa 2748static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 2749{
d44f9b63 2750 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 2751 struct hclge_desc desc;
2752 int i, j;
2753 int ret;
2754
d44f9b63 2755 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 2756
2757 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2758 hclge_cmd_setup_basic_desc
2759 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2760
a90bb9a5
YL		 2761 req->start_table_index =
2762 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2763 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 2764
2765 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2766 req->rss_result[j] =
2767 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2768
2769 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2770 if (ret) {
2771 dev_err(&hdev->pdev->dev,
2772 "Configure rss indir table fail,status = %d\n",
2773 ret);
2774 return ret;
2775 }
2776 }
2777 return 0;
2778}
2779
2780static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2781 u16 *tc_size, u16 *tc_offset)
2782{
d44f9b63 2783 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 2784 struct hclge_desc desc;
2785 int ret;
2786 int i;
2787
2788 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 2789 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 2790
2791 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 2792 u16 mode = 0;
2793
e4e87715
PL		 2794 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2795 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
2796 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2797 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
2798 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 2799
2800 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 2801 }
2802
2803 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 2804 if (ret)
46a3df9f
S		 2805 dev_err(&hdev->pdev->dev,
2806 "Configure rss tc mode fail, status = %d\n", ret);
46a3df9f 2807
3f639907 2808 return ret;
46a3df9f
S		 2809}
2810
2811static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2812{
d44f9b63 2813 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 2814 struct hclge_desc desc;
2815 int ret;
2816
2817 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2818
d44f9b63 2819 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429
YL		 2820
2821 /* Get the tuple cfg from pf */
2822 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
2823 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
2824 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
2825 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
2826 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
2827 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
2828 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
2829 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
46a3df9f 2830 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 2831 if (ret)
46a3df9f
S		 2832 dev_err(&hdev->pdev->dev,
2833 "Configure rss input fail, status = %d\n", ret);
3f639907 2834 return ret;
46a3df9f
S		 2835}
2836
2837static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2838 u8 *key, u8 *hfunc)
2839{
2840 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 2841 int i;
2842
2843 /* Get hash algorithm */
2844 if (hfunc)
89523cfa 2845 *hfunc = vport->rss_algo;
46a3df9f
S		 2846
2847 /* Get the RSS Key required by the user */
2848 if (key)
2849 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2850
2851 /* Get indirect table */
2852 if (indir)
2853 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2854 indir[i] = vport->rss_indirection_tbl[i];
2855
2856 return 0;
2857}
2858
2859static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2860 const u8 *key, const u8 hfunc)
2861{
2862 struct hclge_vport *vport = hclge_get_vport(handle);
2863 struct hclge_dev *hdev = vport->back;
2864 u8 hash_algo;
2865 int ret, i;
2866
2867 /* Set the RSS Hash Key if specififed by the user */
2868 if (key) {
46a3df9f
S		 2869
2870 if (hfunc == ETH_RSS_HASH_TOP ||
2871 hfunc == ETH_RSS_HASH_NO_CHANGE)
2872 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2873 else
2874 return -EINVAL;
2875 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2876 if (ret)
2877 return ret;
89523cfa
YL		 2878
2879 /* Update the shadow RSS key with user specified qids */
2880 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2881 vport->rss_algo = hash_algo;
46a3df9f
S		 2882 }
2883
2884 /* Update the shadow RSS table with user specified qids */
2885 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2886 vport->rss_indirection_tbl[i] = indir[i];
2887
2888 /* Update the hardware */
89523cfa 2889 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 2890}
2891
f7db940a
L		 2892static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
2893{
2894 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
2895
2896 if (nfc->data & RXH_L4_B_2_3)
2897 hash_sets |= HCLGE_D_PORT_BIT;
2898 else
2899 hash_sets &= ~HCLGE_D_PORT_BIT;
2900
2901 if (nfc->data & RXH_IP_SRC)
2902 hash_sets |= HCLGE_S_IP_BIT;
2903 else
2904 hash_sets &= ~HCLGE_S_IP_BIT;
2905
2906 if (nfc->data & RXH_IP_DST)
2907 hash_sets |= HCLGE_D_IP_BIT;
2908 else
2909 hash_sets &= ~HCLGE_D_IP_BIT;
2910
2911 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
2912 hash_sets |= HCLGE_V_TAG_BIT;
2913
2914 return hash_sets;
2915}
2916
2917static int hclge_set_rss_tuple(struct hnae3_handle *handle,
2918 struct ethtool_rxnfc *nfc)
2919{
2920 struct hclge_vport *vport = hclge_get_vport(handle);
2921 struct hclge_dev *hdev = vport->back;
2922 struct hclge_rss_input_tuple_cmd *req;
2923 struct hclge_desc desc;
2924 u8 tuple_sets;
2925 int ret;
2926
2927 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2928 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2929 return -EINVAL;
2930
2931 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429 2932 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 2933
6f2af429
YL		 2934 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
2935 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
2936 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
2937 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
2938 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
2939 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
2940 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
2941 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 2942
2943 tuple_sets = hclge_get_rss_hash_bits(nfc);
2944 switch (nfc->flow_type) {
2945 case TCP_V4_FLOW:
2946 req->ipv4_tcp_en = tuple_sets;
2947 break;
2948 case TCP_V6_FLOW:
2949 req->ipv6_tcp_en = tuple_sets;
2950 break;
2951 case UDP_V4_FLOW:
2952 req->ipv4_udp_en = tuple_sets;
2953 break;
2954 case UDP_V6_FLOW:
2955 req->ipv6_udp_en = tuple_sets;
2956 break;
2957 case SCTP_V4_FLOW:
2958 req->ipv4_sctp_en = tuple_sets;
2959 break;
2960 case SCTP_V6_FLOW:
2961 if ((nfc->data & RXH_L4_B_0_1) ||
2962 (nfc->data & RXH_L4_B_2_3))
2963 return -EINVAL;
2964
2965 req->ipv6_sctp_en = tuple_sets;
2966 break;
2967 case IPV4_FLOW:
2968 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2969 break;
2970 case IPV6_FLOW:
2971 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2972 break;
2973 default:
2974 return -EINVAL;
2975 }
2976
2977 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6f2af429 2978 if (ret) {
f7db940a
L		 2979 dev_err(&hdev->pdev->dev,
2980 "Set rss tuple fail, status = %d\n", ret);
6f2af429
YL		 2981 return ret;
2982 }
f7db940a 2983
6f2af429
YL		 2984 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
2985 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
2986 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
2987 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
2988 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
2989 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
2990 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
2991 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
2992 return 0;
f7db940a
L		 2993}
2994
07d29954
L		 2995static int hclge_get_rss_tuple(struct hnae3_handle *handle,
2996 struct ethtool_rxnfc *nfc)
2997{
2998 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 2999 u8 tuple_sets;
07d29954
L		 3000
3001 nfc->data = 0;
3002
07d29954
L		 3003 switch (nfc->flow_type) {
3004 case TCP_V4_FLOW:
6f2af429 3005 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3006 break;
3007 case UDP_V4_FLOW:
6f2af429 3008 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3009 break;
3010 case TCP_V6_FLOW:
6f2af429 3011 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3012 break;
3013 case UDP_V6_FLOW:
6f2af429 3014 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3015 break;
3016 case SCTP_V4_FLOW:
6f2af429 3017 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3018 break;
3019 case SCTP_V6_FLOW:
6f2af429 3020 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3021 break;
3022 case IPV4_FLOW:
3023 case IPV6_FLOW:
3024 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3025 break;
3026 default:
3027 return -EINVAL;
3028 }
3029
3030 if (!tuple_sets)
3031 return 0;
3032
3033 if (tuple_sets & HCLGE_D_PORT_BIT)
3034 nfc->data |= RXH_L4_B_2_3;
3035 if (tuple_sets & HCLGE_S_PORT_BIT)
3036 nfc->data |= RXH_L4_B_0_1;
3037 if (tuple_sets & HCLGE_D_IP_BIT)
3038 nfc->data |= RXH_IP_DST;
3039 if (tuple_sets & HCLGE_S_IP_BIT)
3040 nfc->data |= RXH_IP_SRC;
3041
3042 return 0;
3043}
3044
46a3df9f
S		 3045static int hclge_get_tc_size(struct hnae3_handle *handle)
3046{
3047 struct hclge_vport *vport = hclge_get_vport(handle);
3048 struct hclge_dev *hdev = vport->back;
3049
3050 return hdev->rss_size_max;
3051}
3052
77f255c1 3053int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3054{
46a3df9f 3055 struct hclge_vport *vport = hdev->vport;
268f5dfa
YL		 3056 u8 *rss_indir = vport[0].rss_indirection_tbl;
3057 u16 rss_size = vport[0].alloc_rss_size;
3058 u8 *key = vport[0].rss_hash_key;
3059 u8 hfunc = vport[0].rss_algo;
46a3df9f 3060 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3061 u16 tc_valid[HCLGE_MAX_TC_NUM];
3062 u16 tc_size[HCLGE_MAX_TC_NUM];
268f5dfa
YL		 3063 u16 roundup_size;
3064 int i, ret;
68ece54e 3065
46a3df9f
S		 3066 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3067 if (ret)
268f5dfa 3068 return ret;
46a3df9f 3069
46a3df9f
S		 3070 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3071 if (ret)
268f5dfa 3072 return ret;
46a3df9f
S		 3073
3074 ret = hclge_set_rss_input_tuple(hdev);
3075 if (ret)
268f5dfa 3076 return ret;
46a3df9f 3077
68ece54e
YL		 3078 /* Each TC have the same queue size, and tc_size set to hardware is
3079 * the log2 of roundup power of two of rss_size, the acutal queue
3080 * size is limited by indirection table.
3081 */
3082 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3083 dev_err(&hdev->pdev->dev,
3084 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3085 rss_size);
268f5dfa 3086 return -EINVAL;
68ece54e
YL		 3087 }
3088
3089 roundup_size = roundup_pow_of_two(rss_size);
3090 roundup_size = ilog2(roundup_size);
3091
46a3df9f 3092 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3093 tc_valid[i] = 0;
46a3df9f 3094
68ece54e
YL		 3095 if (!(hdev->hw_tc_map & BIT(i)))
3096 continue;
3097
3098 tc_valid[i] = 1;
3099 tc_size[i] = roundup_size;
3100 tc_offset[i] = rss_size * i;
46a3df9f 3101 }
68ece54e 3102
268f5dfa
YL		 3103 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3104}
46a3df9f 3105
268f5dfa
YL		 3106void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3107{
3108 struct hclge_vport *vport = hdev->vport;
3109 int i, j;
46a3df9f 3110
268f5dfa
YL		 3111 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3112 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3113 vport[j].rss_indirection_tbl[i] =
3114 i % vport[j].alloc_rss_size;
3115 }
3116}
3117
3118static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3119{
3120 struct hclge_vport *vport = hdev->vport;
3121 int i;
3122
268f5dfa
YL		 3123 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3124 vport[i].rss_tuple_sets.ipv4_tcp_en =
3125 HCLGE_RSS_INPUT_TUPLE_OTHER;
3126 vport[i].rss_tuple_sets.ipv4_udp_en =
3127 HCLGE_RSS_INPUT_TUPLE_OTHER;
3128 vport[i].rss_tuple_sets.ipv4_sctp_en =
3129 HCLGE_RSS_INPUT_TUPLE_SCTP;
3130 vport[i].rss_tuple_sets.ipv4_fragment_en =
3131 HCLGE_RSS_INPUT_TUPLE_OTHER;
3132 vport[i].rss_tuple_sets.ipv6_tcp_en =
3133 HCLGE_RSS_INPUT_TUPLE_OTHER;
3134 vport[i].rss_tuple_sets.ipv6_udp_en =
3135 HCLGE_RSS_INPUT_TUPLE_OTHER;
3136 vport[i].rss_tuple_sets.ipv6_sctp_en =
3137 HCLGE_RSS_INPUT_TUPLE_SCTP;
3138 vport[i].rss_tuple_sets.ipv6_fragment_en =
3139 HCLGE_RSS_INPUT_TUPLE_OTHER;
3140
3141 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
ea739c90
FL		 3142
3143 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
268f5dfa
YL		 3144 }
3145
3146 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3147}
3148
84e095d6
SM		 3149int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3150 int vector_id, bool en,
3151 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3152{
3153 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3154 struct hnae3_ring_chain_node *node;
3155 struct hclge_desc desc;
84e095d6
SM		 3156 struct hclge_ctrl_vector_chain_cmd *req
3157 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3158 enum hclge_cmd_status status;
3159 enum hclge_opcode_type op;
3160 u16 tqp_type_and_id;
46a3df9f
S		 3161 int i;
3162
84e095d6
SM		 3163 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3164 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3165 req->int_vector_id = vector_id;
3166
3167 i = 0;
3168 for (node = ring_chain; node; node = node->next) {
84e095d6 3169 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
e4e87715
PL		 3170 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3171 HCLGE_INT_TYPE_S,
3172 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3173 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3174 HCLGE_TQP_ID_S, node->tqp_index);
3175 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3176 HCLGE_INT_GL_IDX_S,
3177 hnae3_get_field(node->int_gl_idx,
3178 HNAE3_RING_GL_IDX_M,
3179 HNAE3_RING_GL_IDX_S));
84e095d6 3180 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3181 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3182 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
84e095d6 3183 req->vfid = vport->vport_id;
46a3df9f 3184
84e095d6
SM		 3185 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3186 if (status) {
46a3df9f
S		 3187 dev_err(&hdev->pdev->dev,
3188 "Map TQP fail, status is %d.\n",
84e095d6
SM		 3189 status);
3190 return -EIO;
46a3df9f
S		 3191 }
3192 i = 0;
3193
3194 hclge_cmd_setup_basic_desc(&desc,
84e095d6 3195 op,
46a3df9f
S		 3196 false);
3197 req->int_vector_id = vector_id;
3198 }
3199 }
3200
3201 if (i > 0) {
3202 req->int_cause_num = i;
84e095d6
SM		 3203 req->vfid = vport->vport_id;
3204 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3205 if (status) {
46a3df9f 3206 dev_err(&hdev->pdev->dev,
84e095d6
SM		 3207 "Map TQP fail, status is %d.\n", status);
3208 return -EIO;
46a3df9f
S		 3209 }
3210 }
3211
3212 return 0;
3213}
3214
84e095d6
SM		 3215static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3216 int vector,
3217 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3218{
3219 struct hclge_vport *vport = hclge_get_vport(handle);
3220 struct hclge_dev *hdev = vport->back;
3221 int vector_id;
3222
3223 vector_id = hclge_get_vector_index(hdev, vector);
3224 if (vector_id < 0) {
3225 dev_err(&hdev->pdev->dev,
84e095d6 3226 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3227 return vector_id;
3228 }
3229
84e095d6 3230 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3231}
3232
84e095d6
SM		 3233static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3234 int vector,
3235 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3236{
3237 struct hclge_vport *vport = hclge_get_vport(handle);
3238 struct hclge_dev *hdev = vport->back;
84e095d6 3239 int vector_id, ret;
46a3df9f 3240
b50ae26c
PL		 3241 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3242 return 0;
3243
46a3df9f
S		 3244 vector_id = hclge_get_vector_index(hdev, vector);
3245 if (vector_id < 0) {
3246 dev_err(&handle->pdev->dev,
3247 "Get vector index fail. ret =%d\n", vector_id);
3248 return vector_id;
3249 }
3250
84e095d6 3251 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
0d3e6631 3252 if (ret)
84e095d6
SM		 3253 dev_err(&handle->pdev->dev,
3254 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3255 vector_id,
3256 ret);
46a3df9f 3257
0d3e6631 3258 return ret;
46a3df9f
S		 3259}
3260
3261int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3262 struct hclge_promisc_param *param)
3263{
d44f9b63 3264 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3265 struct hclge_desc desc;
3266 int ret;
3267
3268 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3269
d44f9b63 3270 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3271 req->vf_id = param->vf_id;
96c0e861
PL		 3272
3273 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3274 * pdev revision(0x20), new revision support them. The
3275 * value of this two fields will not return error when driver
3276 * send command to fireware in revision(0x20).
3277 */
3278 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3279 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3280
3281 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3282 if (ret)
46a3df9f
S		 3283 dev_err(&hdev->pdev->dev,
3284 "Set promisc mode fail, status is %d.\n", ret);
3f639907
JS		 3285
3286 return ret;
46a3df9f
S		 3287}
3288
3289void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3290 bool en_mc, bool en_bc, int vport_id)
3291{
3292 if (!param)
3293 return;
3294
3295 memset(param, 0, sizeof(struct hclge_promisc_param));
3296 if (en_uc)
3297 param->enable = HCLGE_PROMISC_EN_UC;
3298 if (en_mc)
3299 param->enable |= HCLGE_PROMISC_EN_MC;
3300 if (en_bc)
3301 param->enable |= HCLGE_PROMISC_EN_BC;
3302 param->vf_id = vport_id;
3303}
3304
3b75c3df
PL		 3305static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3306 bool en_mc_pmc)
46a3df9f
S		 3307{
3308 struct hclge_vport *vport = hclge_get_vport(handle);
3309 struct hclge_dev *hdev = vport->back;
3310 struct hclge_promisc_param param;
3311
3b75c3df
PL		 3312 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3313 vport->vport_id);
46a3df9f
S		 3314 hclge_cmd_set_promisc_mode(hdev, &param);
3315}
3316
3317static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3318{
3319 struct hclge_desc desc;
d44f9b63
YL		 3320 struct hclge_config_mac_mode_cmd *req =
3321 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3322 u32 loop_en = 0;
46a3df9f
S		 3323 int ret;
3324
3325 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
e4e87715
PL		 3326 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3327 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3328 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3329 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3330 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3331 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3332 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3333 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3334 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3335 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3336 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3337 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3338 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3339 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
a90bb9a5 3340 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3341
3342 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3343 if (ret)
3344 dev_err(&hdev->pdev->dev,
3345 "mac enable fail, ret =%d.\n", ret);
3346}
3347
eb66d503 3348static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 3349{
c39c4d98 3350 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 3351 struct hclge_desc desc;
3352 u32 loop_en;
3353 int ret;
3354
e4d68dae
YL		 3355 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3356 /* 1 Read out the MAC mode config at first */
3357 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3358 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3359 if (ret) {
3360 dev_err(&hdev->pdev->dev,
3361 "mac loopback get fail, ret =%d.\n", ret);
3362 return ret;
3363 }
c39c4d98 3364
e4d68dae
YL		 3365 /* 2 Then setup the loopback flag */
3366 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
e4e87715 3367 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
0f29fc23
YL		 3368 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0);
3369 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0);
e4d68dae
YL		 3370
3371 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 3372
e4d68dae
YL		 3373 /* 3 Config mac work mode with loopback flag
3374 * and its original configure parameters
3375 */
3376 hclge_cmd_reuse_desc(&desc, false);
3377 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3378 if (ret)
3379 dev_err(&hdev->pdev->dev,
3380 "mac loopback set fail, ret =%d.\n", ret);
3381 return ret;
3382}
c39c4d98 3383
5fd50ac3
PL		 3384static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en)
3385{
3386#define HCLGE_SERDES_RETRY_MS 10
3387#define HCLGE_SERDES_RETRY_NUM 100
3388 struct hclge_serdes_lb_cmd *req;
3389 struct hclge_desc desc;
3390 int ret, i = 0;
3391
d0d72bac 3392 req = (struct hclge_serdes_lb_cmd *)desc.data;
5fd50ac3
PL		 3393 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
3394
3395 if (en) {
3396 req->enable = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3397 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3398 } else {
3399 req->mask = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3400 }
3401
3402 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3403 if (ret) {
3404 dev_err(&hdev->pdev->dev,
3405 "serdes loopback set fail, ret = %d\n", ret);
3406 return ret;
3407 }
3408
3409 do {
3410 msleep(HCLGE_SERDES_RETRY_MS);
3411 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
3412 true);
3413 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3414 if (ret) {
3415 dev_err(&hdev->pdev->dev,
3416 "serdes loopback get, ret = %d\n", ret);
3417 return ret;
3418 }
3419 } while (++i < HCLGE_SERDES_RETRY_NUM &&
3420 !(req->result & HCLGE_CMD_SERDES_DONE_B));
3421
3422 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
3423 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
3424 return -EBUSY;
3425 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
3426 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
3427 return -EIO;
3428 }
3429
0f29fc23 3430 hclge_cfg_mac_mode(hdev, en);
5fd50ac3
PL		 3431 return 0;
3432}
3433
0f29fc23
YL		 3434static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3435 int stream_id, bool enable)
3436{
3437 struct hclge_desc desc;
3438 struct hclge_cfg_com_tqp_queue_cmd *req =
3439 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
3440 int ret;
3441
3442 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3443 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3444 req->stream_id = cpu_to_le16(stream_id);
3445 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3446
3447 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3448 if (ret)
3449 dev_err(&hdev->pdev->dev,
3450 "Tqp enable fail, status =%d.\n", ret);
3451 return ret;
3452}
3453
e4d68dae
YL		 3454static int hclge_set_loopback(struct hnae3_handle *handle,
3455 enum hnae3_loop loop_mode, bool en)
3456{
3457 struct hclge_vport *vport = hclge_get_vport(handle);
3458 struct hclge_dev *hdev = vport->back;
0f29fc23 3459 int i, ret;
e4d68dae
YL		 3460
3461 switch (loop_mode) {
eb66d503
FL		 3462 case HNAE3_LOOP_APP:
3463 ret = hclge_set_app_loopback(hdev, en);
c39c4d98 3464 break;
a7b687b3 3465 case HNAE3_LOOP_SERDES:
5fd50ac3
PL		 3466 ret = hclge_set_serdes_loopback(hdev, en);
3467 break;
c39c4d98
YL		 3468 default:
3469 ret = -ENOTSUPP;
3470 dev_err(&hdev->pdev->dev,
3471 "loop_mode %d is not supported\n", loop_mode);
3472 break;
3473 }
3474
0f29fc23
YL		 3475 for (i = 0; i < vport->alloc_tqps; i++) {
3476 ret = hclge_tqp_enable(hdev, i, 0, en);
3477 if (ret)
3478 return ret;
3479 }
46a3df9f 3480
0f29fc23 3481 return 0;
46a3df9f
S		 3482}
3483
3484static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3485{
3486 struct hclge_vport *vport = hclge_get_vport(handle);
3487 struct hnae3_queue *queue;
3488 struct hclge_tqp *tqp;
3489 int i;
3490
3491 for (i = 0; i < vport->alloc_tqps; i++) {
3492 queue = handle->kinfo.tqp[i];
3493 tqp = container_of(queue, struct hclge_tqp, q);
3494 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3495 }
3496}
3497
3498static int hclge_ae_start(struct hnae3_handle *handle)
3499{
3500 struct hclge_vport *vport = hclge_get_vport(handle);
3501 struct hclge_dev *hdev = vport->back;
b01b7cf1 3502 int i;
46a3df9f 3503
814e0274
PL		 3504 for (i = 0; i < vport->alloc_tqps; i++)
3505 hclge_tqp_enable(hdev, i, 0, true);
46a3df9f 3506
46a3df9f
S		 3507 /* mac enable */
3508 hclge_cfg_mac_mode(hdev, true);
3509 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3510 mod_timer(&hdev->service_timer, jiffies + HZ);
be8d8cdb 3511 hdev->hw.mac.link = 0;
46a3df9f 3512
b50ae26c
PL		 3513 /* reset tqp stats */
3514 hclge_reset_tqp_stats(handle);
3515
b01b7cf1 3516 hclge_mac_start_phy(hdev);
46a3df9f 3517
46a3df9f
S		 3518 return 0;
3519}
3520
3521static void hclge_ae_stop(struct hnae3_handle *handle)
3522{
3523 struct hclge_vport *vport = hclge_get_vport(handle);
3524 struct hclge_dev *hdev = vport->back;
814e0274 3525 int i;
46a3df9f 3526
2f7e4896
FL		 3527 set_bit(HCLGE_STATE_DOWN, &hdev->state);
3528
b50ae26c
PL		 3529 del_timer_sync(&hdev->service_timer);
3530 cancel_work_sync(&hdev->service_task);
f5be7967 3531 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
b50ae26c 3532
9617f668
YL		 3533 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3534 hclge_mac_stop_phy(hdev);
b50ae26c 3535 return;
9617f668 3536 }
b50ae26c 3537
814e0274
PL		 3538 for (i = 0; i < vport->alloc_tqps; i++)
3539 hclge_tqp_enable(hdev, i, 0, false);
46a3df9f 3540
46a3df9f
S		 3541 /* Mac disable */
3542 hclge_cfg_mac_mode(hdev, false);
3543
3544 hclge_mac_stop_phy(hdev);
3545
3546 /* reset tqp stats */
3547 hclge_reset_tqp_stats(handle);
f30dfddc
FL		 3548 del_timer_sync(&hdev->service_timer);
3549 cancel_work_sync(&hdev->service_task);
3550 hclge_update_link_status(hdev);
46a3df9f
S		 3551}
3552
3553static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3554 u16 cmdq_resp, u8 resp_code,
3555 enum hclge_mac_vlan_tbl_opcode op)
3556{
3557 struct hclge_dev *hdev = vport->back;
3558 int return_status = -EIO;
3559
3560 if (cmdq_resp) {
3561 dev_err(&hdev->pdev->dev,
3562 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3563 cmdq_resp);
3564 return -EIO;
3565 }
3566
3567 if (op == HCLGE_MAC_VLAN_ADD) {
3568 if ((!resp_code) || (resp_code == 1)) {
3569 return_status = 0;
3570 } else if (resp_code == 2) {
eefd00a5 3571 return_status = -ENOSPC;
46a3df9f
S		 3572 dev_err(&hdev->pdev->dev,
3573 "add mac addr failed for uc_overflow.\n");
3574 } else if (resp_code == 3) {
eefd00a5 3575 return_status = -ENOSPC;
46a3df9f
S		 3576 dev_err(&hdev->pdev->dev,
3577 "add mac addr failed for mc_overflow.\n");
3578 } else {
3579 dev_err(&hdev->pdev->dev,
3580 "add mac addr failed for undefined, code=%d.\n",
3581 resp_code);
3582 }
3583 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3584 if (!resp_code) {
3585 return_status = 0;
3586 } else if (resp_code == 1) {
eefd00a5 3587 return_status = -ENOENT;
46a3df9f
S		 3588 dev_dbg(&hdev->pdev->dev,
3589 "remove mac addr failed for miss.\n");
3590 } else {
3591 dev_err(&hdev->pdev->dev,
3592 "remove mac addr failed for undefined, code=%d.\n",
3593 resp_code);
3594 }
3595 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3596 if (!resp_code) {
3597 return_status = 0;
3598 } else if (resp_code == 1) {
eefd00a5 3599 return_status = -ENOENT;
46a3df9f
S		 3600 dev_dbg(&hdev->pdev->dev,
3601 "lookup mac addr failed for miss.\n");
3602 } else {
3603 dev_err(&hdev->pdev->dev,
3604 "lookup mac addr failed for undefined, code=%d.\n",
3605 resp_code);
3606 }
3607 } else {
eefd00a5 3608 return_status = -EINVAL;
46a3df9f
S		 3609 dev_err(&hdev->pdev->dev,
3610 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3611 op);
3612 }
3613
3614 return return_status;
3615}
3616
3617static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3618{
3619 int word_num;
3620 int bit_num;
3621
3622 if (vfid > 255 || vfid < 0)
3623 return -EIO;
3624
3625 if (vfid >= 0 && vfid <= 191) {
3626 word_num = vfid / 32;
3627 bit_num = vfid % 32;
3628 if (clr)
a90bb9a5 3629 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3630 else
a90bb9a5 3631 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3632 } else {
3633 word_num = (vfid - 192) / 32;
3634 bit_num = vfid % 32;
3635 if (clr)
a90bb9a5 3636 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3637 else
a90bb9a5 3638 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3639 }
3640
3641 return 0;
3642}
3643
3644static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3645{
3646#define HCLGE_DESC_NUMBER 3
3647#define HCLGE_FUNC_NUMBER_PER_DESC 6
3648 int i, j;
3649
6c39d527 3650 for (i = 1; i < HCLGE_DESC_NUMBER; i++)
46a3df9f
S		 3651 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3652 if (desc[i].data[j])
3653 return false;
3654
3655 return true;
3656}
3657
d44f9b63 3658static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3659 const u8 *addr)
3660{
3661 const unsigned char *mac_addr = addr;
3662 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3663 (mac_addr[0]) | (mac_addr[1] << 8);
3664 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3665
3666 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3667 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3668}
3669
1db9b1bf
YL		 3670static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3671 const u8 *addr)
46a3df9f
S		 3672{
3673 u16 high_val = addr[1] | (addr[0] << 8);
3674 struct hclge_dev *hdev = vport->back;
3675 u32 rsh = 4 - hdev->mta_mac_sel_type;
3676 u16 ret_val = (high_val >> rsh) & 0xfff;
3677
3678 return ret_val;
3679}
3680
3681static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3682 enum hclge_mta_dmac_sel_type mta_mac_sel,
3683 bool enable)
3684{
d44f9b63 3685 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3686 struct hclge_desc desc;
3687 int ret;
3688
d44f9b63 3689 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3690 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3691
e4e87715
PL		 3692 hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3693 enable);
3694 hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3695 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
46a3df9f
S		 3696
3697 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3698 if (ret)
46a3df9f
S		 3699 dev_err(&hdev->pdev->dev,
3700 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3701 ret);
46a3df9f 3702
3f639907 3703 return ret;
46a3df9f
S		 3704}
3705
3706int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3707 u8 func_id,
3708 bool enable)
3709{
d44f9b63 3710 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3711 struct hclge_desc desc;
3712 int ret;
3713
d44f9b63 3714 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3715 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3716
e4e87715
PL		 3717 hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3718 enable);
46a3df9f
S		 3719 req->function_id = func_id;
3720
3721 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3722 if (ret)
46a3df9f
S		 3723 dev_err(&hdev->pdev->dev,
3724 "Config func_id enable failed for cmd_send, ret =%d.\n",
3725 ret);
46a3df9f 3726
3f639907 3727 return ret;
46a3df9f
S		 3728}
3729
3730static int hclge_set_mta_table_item(struct hclge_vport *vport,
3731 u16 idx,
3732 bool enable)
3733{
3734 struct hclge_dev *hdev = vport->back;
d44f9b63 3735 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 3736 struct hclge_desc desc;
a90bb9a5 3737 u16 item_idx = 0;
46a3df9f
S		 3738 int ret;
3739
d44f9b63 3740 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f 3741 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
e4e87715 3742 hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
46a3df9f 3743
e4e87715
PL		 3744 hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3745 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 3746 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 3747
3748 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3749 if (ret) {
3750 dev_err(&hdev->pdev->dev,
3751 "Config mta table item failed for cmd_send, ret =%d.\n",
3752 ret);
3753 return ret;
3754 }
3755
40cca1c5
XW		 3756 if (enable)
3757 set_bit(idx, vport->mta_shadow);
3758 else
3759 clear_bit(idx, vport->mta_shadow);
3760
46a3df9f
S		 3761 return 0;
3762}
3763
40cca1c5
XW		 3764static int hclge_update_mta_status(struct hnae3_handle *handle)
3765{
3766 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
3767 struct hclge_vport *vport = hclge_get_vport(handle);
3768 struct net_device *netdev = handle->kinfo.netdev;
3769 struct netdev_hw_addr *ha;
3770 u16 tbl_idx;
3771
3772 memset(mta_status, 0, sizeof(mta_status));
3773
3774 /* update mta_status from mc addr list */
3775 netdev_for_each_mc_addr(ha, netdev) {
3776 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
3777 set_bit(tbl_idx, mta_status);
3778 }
3779
3780 return hclge_update_mta_status_common(vport, mta_status,
3781 0, HCLGE_MTA_TBL_SIZE, true);
3782}
3783
3784int hclge_update_mta_status_common(struct hclge_vport *vport,
3785 unsigned long *status,
3786 u16 idx,
3787 u16 count,
3788 bool update_filter)
3789{
3790 struct hclge_dev *hdev = vport->back;
3791 u16 update_max = idx + count;
3792 u16 check_max;
3793 int ret = 0;
3794 bool used;
3795 u16 i;
3796
3797 /* setup mta check range */
3798 if (update_filter) {
3799 i = 0;
3800 check_max = HCLGE_MTA_TBL_SIZE;
3801 } else {
3802 i = idx;
3803 check_max = update_max;
3804 }
3805
3806 used = false;
3807 /* check and update all mta item */
3808 for (; i < check_max; i++) {
3809 /* ignore unused item */
3810 if (!test_bit(i, vport->mta_shadow))
3811 continue;
3812
3813 /* if i in update range then update it */
3814 if (i >= idx && i < update_max)
3815 if (!test_bit(i - idx, status))
3816 hclge_set_mta_table_item(vport, i, false);
3817
3818 if (!used && test_bit(i, vport->mta_shadow))
3819 used = true;
3820 }
3821
3822 /* no longer use mta, disable it */
3823 if (vport->accept_mta_mc && update_filter && !used) {
3824 ret = hclge_cfg_func_mta_filter(hdev,
3825 vport->vport_id,
3826 false);
3827 if (ret)
3828 dev_err(&hdev->pdev->dev,
3829 "disable func mta filter fail ret=%d\n",
3830 ret);
3831 else
3832 vport->accept_mta_mc = false;
3833 }
3834
3835 return ret;
3836}
3837
46a3df9f 3838static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3839 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 3840{
3841 struct hclge_dev *hdev = vport->back;
3842 struct hclge_desc desc;
3843 u8 resp_code;
a90bb9a5 3844 u16 retval;
46a3df9f
S		 3845 int ret;
3846
3847 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3848
d44f9b63 3849 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3850
3851 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3852 if (ret) {
3853 dev_err(&hdev->pdev->dev,
3854 "del mac addr failed for cmd_send, ret =%d.\n",
3855 ret);
3856 return ret;
3857 }
a90bb9a5
YL		 3858 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3859 retval = le16_to_cpu(desc.retval);
46a3df9f 3860
a90bb9a5 3861 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3862 HCLGE_MAC_VLAN_REMOVE);
3863}
3864
3865static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3866 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3867 struct hclge_desc *desc,
3868 bool is_mc)
3869{
3870 struct hclge_dev *hdev = vport->back;
3871 u8 resp_code;
a90bb9a5 3872 u16 retval;
46a3df9f
S		 3873 int ret;
3874
3875 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3876 if (is_mc) {
3877 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3878 memcpy(desc[0].data,
3879 req,
d44f9b63 3880 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3881 hclge_cmd_setup_basic_desc(&desc[1],
3882 HCLGE_OPC_MAC_VLAN_ADD,
3883 true);
3884 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3885 hclge_cmd_setup_basic_desc(&desc[2],
3886 HCLGE_OPC_MAC_VLAN_ADD,
3887 true);
3888 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3889 } else {
3890 memcpy(desc[0].data,
3891 req,
d44f9b63 3892 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3893 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3894 }
3895 if (ret) {
3896 dev_err(&hdev->pdev->dev,
3897 "lookup mac addr failed for cmd_send, ret =%d.\n",
3898 ret);
3899 return ret;
3900 }
a90bb9a5
YL		 3901 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3902 retval = le16_to_cpu(desc[0].retval);
46a3df9f 3903
a90bb9a5 3904 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3905 HCLGE_MAC_VLAN_LKUP);
3906}
3907
3908static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3909 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3910 struct hclge_desc *mc_desc)
3911{
3912 struct hclge_dev *hdev = vport->back;
3913 int cfg_status;
3914 u8 resp_code;
a90bb9a5 3915 u16 retval;
46a3df9f
S		 3916 int ret;
3917
3918 if (!mc_desc) {
3919 struct hclge_desc desc;
3920
3921 hclge_cmd_setup_basic_desc(&desc,
3922 HCLGE_OPC_MAC_VLAN_ADD,
3923 false);
d44f9b63
YL		 3924 memcpy(desc.data, req,
3925 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3926 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 3927 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3928 retval = le16_to_cpu(desc.retval);
3929
3930 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3931 resp_code,
3932 HCLGE_MAC_VLAN_ADD);
3933 } else {
c3b6f755 3934 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 3935 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3936 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 3937 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3938 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 3939 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3940 memcpy(mc_desc[0].data, req,
d44f9b63 3941 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3942 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 3943 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
3944 retval = le16_to_cpu(mc_desc[0].retval);
3945
3946 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3947 resp_code,
3948 HCLGE_MAC_VLAN_ADD);
3949 }
3950
3951 if (ret) {
3952 dev_err(&hdev->pdev->dev,
3953 "add mac addr failed for cmd_send, ret =%d.\n",
3954 ret);
3955 return ret;
3956 }
3957
3958 return cfg_status;
3959}
3960
3961static int hclge_add_uc_addr(struct hnae3_handle *handle,
3962 const unsigned char *addr)
3963{
3964 struct hclge_vport *vport = hclge_get_vport(handle);
3965
3966 return hclge_add_uc_addr_common(vport, addr);
3967}
3968
3969int hclge_add_uc_addr_common(struct hclge_vport *vport,
3970 const unsigned char *addr)
3971{
3972 struct hclge_dev *hdev = vport->back;
d44f9b63 3973 struct hclge_mac_vlan_tbl_entry_cmd req;
d07b6bb4 3974 struct hclge_desc desc;
a90bb9a5 3975 u16 egress_port = 0;
aa7a795e 3976 int ret;
46a3df9f
S		 3977
3978 /* mac addr check */
3979 if (is_zero_ether_addr(addr) ||
3980 is_broadcast_ether_addr(addr) ||
3981 is_multicast_ether_addr(addr)) {
3982 dev_err(&hdev->pdev->dev,
3983 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3984 addr,
3985 is_zero_ether_addr(addr),
3986 is_broadcast_ether_addr(addr),
3987 is_multicast_ether_addr(addr));
3988 return -EINVAL;
3989 }
3990
3991 memset(&req, 0, sizeof(req));
e4e87715 3992 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
a90bb9a5 3993
e4e87715
PL		 3994 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
3995 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5
YL		 3996
3997 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 3998
3999 hclge_prepare_mac_addr(&req, addr);
4000
d07b6bb4
JS		 4001 /* Lookup the mac address in the mac_vlan table, and add
4002 * it if the entry is inexistent. Repeated unicast entry
4003 * is not allowed in the mac vlan table.
4004 */
4005 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4006 if (ret == -ENOENT)
4007 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4008
4009 /* check if we just hit the duplicate */
4010 if (!ret)
4011 ret = -EINVAL;
4012
4013 dev_err(&hdev->pdev->dev,
4014 "PF failed to add unicast entry(%pM) in the MAC table\n",
4015 addr);
46a3df9f 4016
aa7a795e 4017 return ret;
46a3df9f
S		 4018}
4019
4020static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4021 const unsigned char *addr)
4022{
4023 struct hclge_vport *vport = hclge_get_vport(handle);
4024
4025 return hclge_rm_uc_addr_common(vport, addr);
4026}
4027
4028int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4029 const unsigned char *addr)
4030{
4031 struct hclge_dev *hdev = vport->back;
d44f9b63 4032 struct hclge_mac_vlan_tbl_entry_cmd req;
aa7a795e 4033 int ret;
46a3df9f
S		 4034
4035 /* mac addr check */
4036 if (is_zero_ether_addr(addr) ||
4037 is_broadcast_ether_addr(addr) ||
4038 is_multicast_ether_addr(addr)) {
4039 dev_dbg(&hdev->pdev->dev,
4040 "Remove mac err! invalid mac:%pM.\n",
4041 addr);
4042 return -EINVAL;
4043 }
4044
4045 memset(&req, 0, sizeof(req));
e4e87715
PL		 4046 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4047 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f 4048 hclge_prepare_mac_addr(&req, addr);
aa7a795e 4049 ret = hclge_remove_mac_vlan_tbl(vport, &req);
46a3df9f 4050
aa7a795e 4051 return ret;
46a3df9f
S		 4052}
4053
4054static int hclge_add_mc_addr(struct hnae3_handle *handle,
4055 const unsigned char *addr)
4056{
4057 struct hclge_vport *vport = hclge_get_vport(handle);
4058
a10829c4 4059 return hclge_add_mc_addr_common(vport, addr);
46a3df9f
S		 4060}
4061
4062int hclge_add_mc_addr_common(struct hclge_vport *vport,
4063 const unsigned char *addr)
4064{
4065 struct hclge_dev *hdev = vport->back;
d44f9b63 4066 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4067 struct hclge_desc desc[3];
4068 u16 tbl_idx;
4069 int status;
4070
4071 /* mac addr check */
4072 if (!is_multicast_ether_addr(addr)) {
4073 dev_err(&hdev->pdev->dev,
4074 "Add mc mac err! invalid mac:%pM.\n",
4075 addr);
4076 return -EINVAL;
4077 }
4078 memset(&req, 0, sizeof(req));
e4e87715
PL		 4079 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4080 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4081 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
fd5f9da3 4082 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 4083 hclge_prepare_mac_addr(&req, addr);
4084 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4085 if (!status) {
4086 /* This mac addr exist, update VFID for it */
4087 hclge_update_desc_vfid(desc, vport->vport_id, false);
4088 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4089 } else {
4090 /* This mac addr do not exist, add new entry for it */
4091 memset(desc[0].data, 0, sizeof(desc[0].data));
4092 memset(desc[1].data, 0, sizeof(desc[0].data));
4093 memset(desc[2].data, 0, sizeof(desc[0].data));
4094 hclge_update_desc_vfid(desc, vport->vport_id, false);
4095 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4096 }
4097
40cca1c5
XW		 4098 /* If mc mac vlan table is full, use MTA table */
4099 if (status == -ENOSPC) {
4100 if (!vport->accept_mta_mc) {
4101 status = hclge_cfg_func_mta_filter(hdev,
4102 vport->vport_id,
4103 true);
4104 if (status) {
4105 dev_err(&hdev->pdev->dev,
4106 "set mta filter mode fail ret=%d\n",
4107 status);
4108 return status;
4109 }
4110 vport->accept_mta_mc = true;
4111 }
4112
4113 /* Set MTA table for this MAC address */
4114 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4115 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4116 }
46a3df9f
S		 4117
4118 return status;
4119}
4120
4121static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4122 const unsigned char *addr)
4123{
4124 struct hclge_vport *vport = hclge_get_vport(handle);
4125
4126 return hclge_rm_mc_addr_common(vport, addr);
4127}
4128
4129int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4130 const unsigned char *addr)
4131{
4132 struct hclge_dev *hdev = vport->back;
d44f9b63 4133 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4134 enum hclge_cmd_status status;
4135 struct hclge_desc desc[3];
46a3df9f
S		 4136
4137 /* mac addr check */
4138 if (!is_multicast_ether_addr(addr)) {
4139 dev_dbg(&hdev->pdev->dev,
4140 "Remove mc mac err! invalid mac:%pM.\n",
4141 addr);
4142 return -EINVAL;
4143 }
4144
4145 memset(&req, 0, sizeof(req));
e4e87715
PL		 4146 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4147 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4148 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
fd5f9da3 4149 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 4150 hclge_prepare_mac_addr(&req, addr);
4151 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4152 if (!status) {
4153 /* This mac addr exist, remove this handle's VFID for it */
4154 hclge_update_desc_vfid(desc, vport->vport_id, true);
4155
4156 if (hclge_is_all_function_id_zero(desc))
4157 /* All the vfid is zero, so need to delete this entry */
4158 status = hclge_remove_mac_vlan_tbl(vport, &req);
4159 else
4160 /* Not all the vfid is zero, update the vfid */
4161 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4162
4163 } else {
40cca1c5
XW		 4164 /* Maybe this mac address is in mta table, but it cannot be
4165 * deleted here because an entry of mta represents an address
4166 * range rather than a specific address. the delete action to
4167 * all entries will take effect in update_mta_status called by
4168 * hns3_nic_set_rx_mode.
4169 */
4170 status = 0;
46a3df9f
S		 4171 }
4172
46a3df9f
S		 4173 return status;
4174}
4175
f5aac71c
FL		 4176static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4177 u16 cmdq_resp, u8 resp_code)
4178{
4179#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4180#define HCLGE_ETHERTYPE_ALREADY_ADD 1
4181#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4182#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4183
4184 int return_status;
4185
4186 if (cmdq_resp) {
4187 dev_err(&hdev->pdev->dev,
4188 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4189 cmdq_resp);
4190 return -EIO;
4191 }
4192
4193 switch (resp_code) {
4194 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4195 case HCLGE_ETHERTYPE_ALREADY_ADD:
4196 return_status = 0;
4197 break;
4198 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4199 dev_err(&hdev->pdev->dev,
4200 "add mac ethertype failed for manager table overflow.\n");
4201 return_status = -EIO;
4202 break;
4203 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4204 dev_err(&hdev->pdev->dev,
4205 "add mac ethertype failed for key conflict.\n");
4206 return_status = -EIO;
4207 break;
4208 default:
4209 dev_err(&hdev->pdev->dev,
4210 "add mac ethertype failed for undefined, code=%d.\n",
4211 resp_code);
4212 return_status = -EIO;
4213 }
4214
4215 return return_status;
4216}
4217
4218static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4219 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4220{
4221 struct hclge_desc desc;
4222 u8 resp_code;
4223 u16 retval;
4224 int ret;
4225
4226 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4227 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4228
4229 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4230 if (ret) {
4231 dev_err(&hdev->pdev->dev,
4232 "add mac ethertype failed for cmd_send, ret =%d.\n",
4233 ret);
4234 return ret;
4235 }
4236
4237 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4238 retval = le16_to_cpu(desc.retval);
4239
4240 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4241}
4242
4243static int init_mgr_tbl(struct hclge_dev *hdev)
4244{
4245 int ret;
4246 int i;
4247
4248 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4249 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4250 if (ret) {
4251 dev_err(&hdev->pdev->dev,
4252 "add mac ethertype failed, ret =%d.\n",
4253 ret);
4254 return ret;
4255 }
4256 }
4257
4258 return 0;
4259}
4260
46a3df9f
S		 4261static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4262{
4263 struct hclge_vport *vport = hclge_get_vport(handle);
4264 struct hclge_dev *hdev = vport->back;
4265
4266 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4267}
4268
59098055
FL		 4269static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4270 bool is_first)
46a3df9f
S		 4271{
4272 const unsigned char *new_addr = (const unsigned char *)p;
4273 struct hclge_vport *vport = hclge_get_vport(handle);
4274 struct hclge_dev *hdev = vport->back;
18838d0c 4275 int ret;
46a3df9f
S		 4276
4277 /* mac addr check */
4278 if (is_zero_ether_addr(new_addr) ||
4279 is_broadcast_ether_addr(new_addr) ||
4280 is_multicast_ether_addr(new_addr)) {
4281 dev_err(&hdev->pdev->dev,
4282 "Change uc mac err! invalid mac:%p.\n",
4283 new_addr);
4284 return -EINVAL;
4285 }
4286
59098055 4287 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 4288 dev_warn(&hdev->pdev->dev,
59098055 4289 "remove old uc mac address fail.\n");
46a3df9f 4290
18838d0c
FL		 4291 ret = hclge_add_uc_addr(handle, new_addr);
4292 if (ret) {
4293 dev_err(&hdev->pdev->dev,
4294 "add uc mac address fail, ret =%d.\n",
4295 ret);
4296
59098055
FL		 4297 if (!is_first &&
4298 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 4299 dev_err(&hdev->pdev->dev,
59098055 4300 "restore uc mac address fail.\n");
18838d0c
FL		 4301
4302 return -EIO;
46a3df9f
S		 4303 }
4304
e98d7183 4305 ret = hclge_pause_addr_cfg(hdev, new_addr);
18838d0c
FL		 4306 if (ret) {
4307 dev_err(&hdev->pdev->dev,
4308 "configure mac pause address fail, ret =%d.\n",
4309 ret);
4310 return -EIO;
4311 }
4312
4313 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4314
4315 return 0;
46a3df9f
S		 4316}
4317
26483246
XW		 4318static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
4319 int cmd)
4320{
4321 struct hclge_vport *vport = hclge_get_vport(handle);
4322 struct hclge_dev *hdev = vport->back;
4323
4324 if (!hdev->hw.mac.phydev)
4325 return -EOPNOTSUPP;
4326
4327 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
4328}
4329
46a3df9f
S		 4330static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4331 bool filter_en)
4332{
d44f9b63 4333 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4334 struct hclge_desc desc;
4335 int ret;
4336
4337 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4338
d44f9b63 4339 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4340 req->vlan_type = vlan_type;
4341 req->vlan_fe = filter_en;
4342
4343 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 4344 if (ret)
46a3df9f
S		 4345 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4346 ret);
46a3df9f 4347
3f639907 4348 return ret;
46a3df9f
S		 4349}
4350
391b5e93
JS		 4351#define HCLGE_FILTER_TYPE_VF 0
4352#define HCLGE_FILTER_TYPE_PORT 1
4353
4354static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4355{
4356 struct hclge_vport *vport = hclge_get_vport(handle);
4357 struct hclge_dev *hdev = vport->back;
4358
4359 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4360}
4361
dc8131d8
YL		 4362static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4363 bool is_kill, u16 vlan, u8 qos,
4364 __be16 proto)
46a3df9f
S		 4365{
4366#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4367 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4368 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4369 struct hclge_desc desc[2];
4370 u8 vf_byte_val;
4371 u8 vf_byte_off;
4372 int ret;
4373
4374 hclge_cmd_setup_basic_desc(&desc[0],
4375 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4376 hclge_cmd_setup_basic_desc(&desc[1],
4377 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4378
4379 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4380
4381 vf_byte_off = vfid / 8;
4382 vf_byte_val = 1 << (vfid % 8);
4383
d44f9b63
YL		 4384 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4385 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4386
a90bb9a5 4387 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4388 req0->vlan_cfg = is_kill;
4389
4390 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4391 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4392 else
4393 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4394
4395 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4396 if (ret) {
4397 dev_err(&hdev->pdev->dev,
4398 "Send vf vlan command fail, ret =%d.\n",
4399 ret);
4400 return ret;
4401 }
4402
4403 if (!is_kill) {
6c251711 4404#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 4405 if (!req0->resp_code || req0->resp_code == 1)
4406 return 0;
4407
6c251711
YL		 4408 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4409 dev_warn(&hdev->pdev->dev,
4410 "vf vlan table is full, vf vlan filter is disabled\n");
4411 return 0;
4412 }
4413
46a3df9f
S		 4414 dev_err(&hdev->pdev->dev,
4415 "Add vf vlan filter fail, ret =%d.\n",
4416 req0->resp_code);
4417 } else {
41dafea2 4418#define HCLGE_VF_VLAN_DEL_NO_FOUND 1
46a3df9f
S		 4419 if (!req0->resp_code)
4420 return 0;
4421
41dafea2
YL		 4422 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
4423 dev_warn(&hdev->pdev->dev,
4424 "vlan %d filter is not in vf vlan table\n",
4425 vlan);
4426 return 0;
4427 }
4428
46a3df9f
S		 4429 dev_err(&hdev->pdev->dev,
4430 "Kill vf vlan filter fail, ret =%d.\n",
4431 req0->resp_code);
4432 }
4433
4434 return -EIO;
4435}
4436
dc8131d8
YL		 4437static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4438 u16 vlan_id, bool is_kill)
46a3df9f 4439{
d44f9b63 4440 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4441 struct hclge_desc desc;
4442 u8 vlan_offset_byte_val;
4443 u8 vlan_offset_byte;
4444 u8 vlan_offset_160;
4445 int ret;
4446
4447 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4448
4449 vlan_offset_160 = vlan_id / 160;
4450 vlan_offset_byte = (vlan_id % 160) / 8;
4451 vlan_offset_byte_val = 1 << (vlan_id % 8);
4452
d44f9b63 4453 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4454 req->vlan_offset = vlan_offset_160;
4455 req->vlan_cfg = is_kill;
4456 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4457
4458 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
dc8131d8
YL		 4459 if (ret)
4460 dev_err(&hdev->pdev->dev,
4461 "port vlan command, send fail, ret =%d.\n", ret);
4462 return ret;
4463}
4464
4465static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4466 u16 vport_id, u16 vlan_id, u8 qos,
4467 bool is_kill)
4468{
4469 u16 vport_idx, vport_num = 0;
4470 int ret;
4471
daaa8521
YL		 4472 if (is_kill && !vlan_id)
4473 return 0;
4474
dc8131d8
YL		 4475 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4476 0, proto);
46a3df9f
S		 4477 if (ret) {
4478 dev_err(&hdev->pdev->dev,
dc8131d8
YL		 4479 "Set %d vport vlan filter config fail, ret =%d.\n",
4480 vport_id, ret);
46a3df9f
S		 4481 return ret;
4482 }
4483
dc8131d8
YL		 4484 /* vlan 0 may be added twice when 8021q module is enabled */
4485 if (!is_kill && !vlan_id &&
4486 test_bit(vport_id, hdev->vlan_table[vlan_id]))
4487 return 0;
4488
4489 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 4490 dev_err(&hdev->pdev->dev,
dc8131d8
YL		 4491 "Add port vlan failed, vport %d is already in vlan %d\n",
4492 vport_id, vlan_id);
4493 return -EINVAL;
46a3df9f
S		 4494 }
4495
dc8131d8
YL		 4496 if (is_kill &&
4497 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4498 dev_err(&hdev->pdev->dev,
4499 "Delete port vlan failed, vport %d is not in vlan %d\n",
4500 vport_id, vlan_id);
4501 return -EINVAL;
4502 }
4503
54e97d11 4504 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
dc8131d8
YL		 4505 vport_num++;
4506
4507 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4508 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4509 is_kill);
4510
4511 return ret;
4512}
4513
4514int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4515 u16 vlan_id, bool is_kill)
4516{
4517 struct hclge_vport *vport = hclge_get_vport(handle);
4518 struct hclge_dev *hdev = vport->back;
4519
4520 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4521 0, is_kill);
46a3df9f
S		 4522}
4523
4524static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4525 u16 vlan, u8 qos, __be16 proto)
4526{
4527 struct hclge_vport *vport = hclge_get_vport(handle);
4528 struct hclge_dev *hdev = vport->back;
4529
4530 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4531 return -EINVAL;
4532 if (proto != htons(ETH_P_8021Q))
4533 return -EPROTONOSUPPORT;
4534
dc8131d8 4535 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 4536}
4537
5f6ea83f
PL		 4538static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4539{
4540 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4541 struct hclge_vport_vtag_tx_cfg_cmd *req;
4542 struct hclge_dev *hdev = vport->back;
4543 struct hclge_desc desc;
4544 int status;
4545
4546 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4547
4548 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4549 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4550 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
e4e87715
PL		 4551 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
4552 vcfg->accept_tag1 ? 1 : 0);
4553 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
4554 vcfg->accept_untag1 ? 1 : 0);
4555 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
4556 vcfg->accept_tag2 ? 1 : 0);
4557 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
4558 vcfg->accept_untag2 ? 1 : 0);
4559 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4560 vcfg->insert_tag1_en ? 1 : 0);
4561 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4562 vcfg->insert_tag2_en ? 1 : 0);
4563 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
5f6ea83f
PL		 4564
4565 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4566 req->vf_bitmap[req->vf_offset] =
4567 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4568
4569 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4570 if (status)
4571 dev_err(&hdev->pdev->dev,
4572 "Send port txvlan cfg command fail, ret =%d\n",
4573 status);
4574
4575 return status;
4576}
4577
4578static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4579{
4580 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4581 struct hclge_vport_vtag_rx_cfg_cmd *req;
4582 struct hclge_dev *hdev = vport->back;
4583 struct hclge_desc desc;
4584 int status;
4585
4586 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4587
4588 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
e4e87715
PL		 4589 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4590 vcfg->strip_tag1_en ? 1 : 0);
4591 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4592 vcfg->strip_tag2_en ? 1 : 0);
4593 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4594 vcfg->vlan1_vlan_prionly ? 1 : 0);
4595 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4596 vcfg->vlan2_vlan_prionly ? 1 : 0);
5f6ea83f
PL		 4597
4598 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4599 req->vf_bitmap[req->vf_offset] =
4600 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4601
4602 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4603 if (status)
4604 dev_err(&hdev->pdev->dev,
4605 "Send port rxvlan cfg command fail, ret =%d\n",
4606 status);
4607
4608 return status;
4609}
4610
4611static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4612{
4613 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4614 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4615 struct hclge_desc desc;
4616 int status;
4617
4618 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4619 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4620 rx_req->ot_fst_vlan_type =
4621 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4622 rx_req->ot_sec_vlan_type =
4623 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4624 rx_req->in_fst_vlan_type =
4625 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4626 rx_req->in_sec_vlan_type =
4627 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4628
4629 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4630 if (status) {
4631 dev_err(&hdev->pdev->dev,
4632 "Send rxvlan protocol type command fail, ret =%d\n",
4633 status);
4634 return status;
4635 }
4636
4637 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4638
d0d72bac 4639 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
5f6ea83f
PL		 4640 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4641 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4642
4643 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4644 if (status)
4645 dev_err(&hdev->pdev->dev,
4646 "Send txvlan protocol type command fail, ret =%d\n",
4647 status);
4648
4649 return status;
4650}
4651
46a3df9f
S		 4652static int hclge_init_vlan_config(struct hclge_dev *hdev)
4653{
5f6ea83f
PL		 4654#define HCLGE_DEF_VLAN_TYPE 0x8100
4655
5e43aef8 4656 struct hnae3_handle *handle;
5f6ea83f 4657 struct hclge_vport *vport;
46a3df9f 4658 int ret;
5f6ea83f
PL		 4659 int i;
4660
4661 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4662 if (ret)
4663 return ret;
46a3df9f 4664
5f6ea83f 4665 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
46a3df9f
S		 4666 if (ret)
4667 return ret;
4668
5f6ea83f
PL		 4669 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4670 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4671 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4672 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4673 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4674 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4675
4676 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 4677 if (ret)
4678 return ret;
46a3df9f 4679
5f6ea83f
PL		 4680 for (i = 0; i < hdev->num_alloc_vport; i++) {
4681 vport = &hdev->vport[i];
dcb35cce
PL		 4682 vport->txvlan_cfg.accept_tag1 = true;
4683 vport->txvlan_cfg.accept_untag1 = true;
4684
4685 /* accept_tag2 and accept_untag2 are not supported on
4686 * pdev revision(0x20), new revision support them. The
4687 * value of this two fields will not return error when driver
4688 * send command to fireware in revision(0x20).
4689 * This two fields can not configured by user.
4690 */
4691 vport->txvlan_cfg.accept_tag2 = true;
4692 vport->txvlan_cfg.accept_untag2 = true;
4693
5f6ea83f
PL		 4694 vport->txvlan_cfg.insert_tag1_en = false;
4695 vport->txvlan_cfg.insert_tag2_en = false;
4696 vport->txvlan_cfg.default_tag1 = 0;
4697 vport->txvlan_cfg.default_tag2 = 0;
4698
4699 ret = hclge_set_vlan_tx_offload_cfg(vport);
4700 if (ret)
4701 return ret;
4702
4703 vport->rxvlan_cfg.strip_tag1_en = false;
4704 vport->rxvlan_cfg.strip_tag2_en = true;
4705 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4706 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4707
4708 ret = hclge_set_vlan_rx_offload_cfg(vport);
4709 if (ret)
4710 return ret;
4711 }
4712
5e43aef8 4713 handle = &hdev->vport[0].nic;
dc8131d8 4714 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4715}
4716
b2641e2a 4717int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
052ece6d
PL		 4718{
4719 struct hclge_vport *vport = hclge_get_vport(handle);
4720
4721 vport->rxvlan_cfg.strip_tag1_en = false;
4722 vport->rxvlan_cfg.strip_tag2_en = enable;
4723 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4724 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4725
4726 return hclge_set_vlan_rx_offload_cfg(vport);
4727}
4728
dd72140c 4729static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 4730{
d44f9b63 4731 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 4732 struct hclge_desc desc;
2866ccb2 4733 int max_frm_size;
46a3df9f
S		 4734 int ret;
4735
2866ccb2
FL		 4736 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4737
4738 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4739 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 4740 return -EINVAL;
4741
2866ccb2
FL		 4742 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
4743
46a3df9f
S		 4744 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4745
d44f9b63 4746 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
2866ccb2 4747 req->max_frm_size = cpu_to_le16(max_frm_size);
8fc7346c 4748 req->min_frm_size = HCLGE_MAC_MIN_FRAME;
46a3df9f
S		 4749
4750 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 4751 if (ret)
46a3df9f 4752 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
3f639907
JS		 4753 else
4754 hdev->mps = max_frm_size;
2866ccb2 4755
3f639907 4756 return ret;
46a3df9f
S		 4757}
4758
dd72140c
FL		 4759static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4760{
4761 struct hclge_vport *vport = hclge_get_vport(handle);
4762 struct hclge_dev *hdev = vport->back;
4763 int ret;
4764
4765 ret = hclge_set_mac_mtu(hdev, new_mtu);
4766 if (ret) {
4767 dev_err(&hdev->pdev->dev,
4768 "Change mtu fail, ret =%d\n", ret);
4769 return ret;
4770 }
4771
4772 ret = hclge_buffer_alloc(hdev);
4773 if (ret)
4774 dev_err(&hdev->pdev->dev,
4775 "Allocate buffer fail, ret =%d\n", ret);
4776
4777 return ret;
4778}
4779
46a3df9f
S		 4780static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4781 bool enable)
4782{
d44f9b63 4783 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4784 struct hclge_desc desc;
4785 int ret;
4786
4787 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4788
d44f9b63 4789 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f 4790 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
e4e87715 4791 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
46a3df9f
S		 4792
4793 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4794 if (ret) {
4795 dev_err(&hdev->pdev->dev,
4796 "Send tqp reset cmd error, status =%d\n", ret);
4797 return ret;
4798 }
4799
4800 return 0;
4801}
4802
4803static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4804{
d44f9b63 4805 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4806 struct hclge_desc desc;
4807 int ret;
4808
4809 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4810
d44f9b63 4811 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4812 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4813
4814 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4815 if (ret) {
4816 dev_err(&hdev->pdev->dev,
4817 "Get reset status error, status =%d\n", ret);
4818 return ret;
4819 }
4820
e4e87715 4821 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
46a3df9f
S		 4822}
4823
814e0274
PL		 4824static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
4825 u16 queue_id)
4826{
4827 struct hnae3_queue *queue;
4828 struct hclge_tqp *tqp;
4829
4830 queue = handle->kinfo.tqp[queue_id];
4831 tqp = container_of(queue, struct hclge_tqp, q);
4832
4833 return tqp->index;
4834}
4835
84e095d6 4836void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 4837{
4838 struct hclge_vport *vport = hclge_get_vport(handle);
4839 struct hclge_dev *hdev = vport->back;
4840 int reset_try_times = 0;
4841 int reset_status;
814e0274 4842 u16 queue_gid;
46a3df9f
S		 4843 int ret;
4844
b50ae26c
PL		 4845 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
4846 return;
4847
814e0274
PL		 4848 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
4849
46a3df9f
S		 4850 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4851 if (ret) {
4852 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4853 return;
4854 }
4855
814e0274 4856 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f
S		 4857 if (ret) {
4858 dev_warn(&hdev->pdev->dev,
4859 "Send reset tqp cmd fail, ret = %d\n", ret);
4860 return;
4861 }
4862
4863 reset_try_times = 0;
4864 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4865 /* Wait for tqp hw reset */
4866 msleep(20);
814e0274 4867 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 4868 if (reset_status)
4869 break;
4870 }
4871
4872 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4873 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4874 return;
4875 }
4876
814e0274 4877 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
46a3df9f
S		 4878 if (ret) {
4879 dev_warn(&hdev->pdev->dev,
4880 "Deassert the soft reset fail, ret = %d\n", ret);
4881 return;
4882 }
4883}
4884
1a426f8b
PL		 4885void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
4886{
4887 struct hclge_dev *hdev = vport->back;
4888 int reset_try_times = 0;
4889 int reset_status;
4890 u16 queue_gid;
4891 int ret;
4892
4893 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
4894
4895 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
4896 if (ret) {
4897 dev_warn(&hdev->pdev->dev,
4898 "Send reset tqp cmd fail, ret = %d\n", ret);
4899 return;
4900 }
4901
4902 reset_try_times = 0;
4903 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4904 /* Wait for tqp hw reset */
4905 msleep(20);
4906 reset_status = hclge_get_reset_status(hdev, queue_gid);
4907 if (reset_status)
4908 break;
4909 }
4910
4911 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4912 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4913 return;
4914 }
4915
4916 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
4917 if (ret)
4918 dev_warn(&hdev->pdev->dev,
4919 "Deassert the soft reset fail, ret = %d\n", ret);
4920}
4921
46a3df9f
S		 4922static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4923{
4924 struct hclge_vport *vport = hclge_get_vport(handle);
4925 struct hclge_dev *hdev = vport->back;
4926
4927 return hdev->fw_version;
4928}
4929
61387774
PL		 4930static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4931{
4932 struct phy_device *phydev = hdev->hw.mac.phydev;
4933
4934 if (!phydev)
4935 return;
4936
70814e81 4937 phy_set_asym_pause(phydev, rx_en, tx_en);
61387774
PL		 4938}
4939
4940static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4941{
61387774
PL		 4942 int ret;
4943
4944 if (rx_en && tx_en)
40173a2e 4945 hdev->fc_mode_last_time = HCLGE_FC_FULL;
61387774 4946 else if (rx_en && !tx_en)
40173a2e 4947 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
61387774 4948 else if (!rx_en && tx_en)
40173a2e 4949 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
61387774 4950 else
40173a2e 4951 hdev->fc_mode_last_time = HCLGE_FC_NONE;
61387774 4952
40173a2e 4953 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
61387774 4954 return 0;
61387774
PL		 4955
4956 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
4957 if (ret) {
4958 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
4959 ret);
4960 return ret;
4961 }
4962
40173a2e 4963 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
61387774
PL		 4964
4965 return 0;
4966}
4967
1770a7a3
PL		 4968int hclge_cfg_flowctrl(struct hclge_dev *hdev)
4969{
4970 struct phy_device *phydev = hdev->hw.mac.phydev;
4971 u16 remote_advertising = 0;
4972 u16 local_advertising = 0;
4973 u32 rx_pause, tx_pause;
4974 u8 flowctl;
4975
4976 if (!phydev->link || !phydev->autoneg)
4977 return 0;
4978
4979 if (phydev->advertising & ADVERTISED_Pause)
4980 local_advertising = ADVERTISE_PAUSE_CAP;
4981
4982 if (phydev->advertising & ADVERTISED_Asym_Pause)
4983 local_advertising |= ADVERTISE_PAUSE_ASYM;
4984
4985 if (phydev->pause)
4986 remote_advertising = LPA_PAUSE_CAP;
4987
4988 if (phydev->asym_pause)
4989 remote_advertising |= LPA_PAUSE_ASYM;
4990
4991 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
4992 remote_advertising);
4993 tx_pause = flowctl & FLOW_CTRL_TX;
4994 rx_pause = flowctl & FLOW_CTRL_RX;
4995
4996 if (phydev->duplex == HCLGE_MAC_HALF) {
4997 tx_pause = 0;
4998 rx_pause = 0;
4999 }
5000
5001 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5002}
5003
46a3df9f
S		 5004static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5005 u32 *rx_en, u32 *tx_en)
5006{
5007 struct hclge_vport *vport = hclge_get_vport(handle);
5008 struct hclge_dev *hdev = vport->back;
5009
5010 *auto_neg = hclge_get_autoneg(handle);
5011
5012 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5013 *rx_en = 0;
5014 *tx_en = 0;
5015 return;
5016 }
5017
5018 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5019 *rx_en = 1;
5020 *tx_en = 0;
5021 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5022 *tx_en = 1;
5023 *rx_en = 0;
5024 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5025 *rx_en = 1;
5026 *tx_en = 1;
5027 } else {
5028 *rx_en = 0;
5029 *tx_en = 0;
5030 }
5031}
5032
61387774
PL		 5033static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5034 u32 rx_en, u32 tx_en)
5035{
5036 struct hclge_vport *vport = hclge_get_vport(handle);
5037 struct hclge_dev *hdev = vport->back;
5038 struct phy_device *phydev = hdev->hw.mac.phydev;
5039 u32 fc_autoneg;
5040
61387774
PL		 5041 fc_autoneg = hclge_get_autoneg(handle);
5042 if (auto_neg != fc_autoneg) {
5043 dev_info(&hdev->pdev->dev,
5044 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5045 return -EOPNOTSUPP;
5046 }
5047
5048 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5049 dev_info(&hdev->pdev->dev,
5050 "Priority flow control enabled. Cannot set link flow control.\n");
5051 return -EOPNOTSUPP;
5052 }
5053
5054 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5055
5056 if (!fc_autoneg)
5057 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5058
0c963e8c
FL		 5059 /* Only support flow control negotiation for netdev with
5060 * phy attached for now.
5061 */
5062 if (!phydev)
5063 return -EOPNOTSUPP;
5064
61387774
PL		 5065 return phy_start_aneg(phydev);
5066}
5067
46a3df9f
S		 5068static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5069 u8 *auto_neg, u32 *speed, u8 *duplex)
5070{
5071 struct hclge_vport *vport = hclge_get_vport(handle);
5072 struct hclge_dev *hdev = vport->back;
5073
5074 if (speed)
5075 *speed = hdev->hw.mac.speed;
5076 if (duplex)
5077 *duplex = hdev->hw.mac.duplex;
5078 if (auto_neg)
5079 *auto_neg = hdev->hw.mac.autoneg;
5080}
5081
5082static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5083{
5084 struct hclge_vport *vport = hclge_get_vport(handle);
5085 struct hclge_dev *hdev = vport->back;
5086
5087 if (media_type)
5088 *media_type = hdev->hw.mac.media_type;
5089}
5090
5091static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5092 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5093{
5094 struct hclge_vport *vport = hclge_get_vport(handle);
5095 struct hclge_dev *hdev = vport->back;
5096 struct phy_device *phydev = hdev->hw.mac.phydev;
5097 int mdix_ctrl, mdix, retval, is_resolved;
5098
5099 if (!phydev) {
5100 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5101 *tp_mdix = ETH_TP_MDI_INVALID;
5102 return;
5103 }
5104
5105 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5106
5107 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
e4e87715
PL		 5108 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5109 HCLGE_PHY_MDIX_CTRL_S);
46a3df9f
S		 5110
5111 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
e4e87715
PL		 5112 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5113 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
46a3df9f
S		 5114
5115 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5116
5117 switch (mdix_ctrl) {
5118 case 0x0:
5119 *tp_mdix_ctrl = ETH_TP_MDI;
5120 break;
5121 case 0x1:
5122 *tp_mdix_ctrl = ETH_TP_MDI_X;
5123 break;
5124 case 0x3:
5125 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5126 break;
5127 default:
5128 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5129 break;
5130 }
5131
5132 if (!is_resolved)
5133 *tp_mdix = ETH_TP_MDI_INVALID;
5134 else if (mdix)
5135 *tp_mdix = ETH_TP_MDI_X;
5136 else
5137 *tp_mdix = ETH_TP_MDI;
5138}
5139
b01b7cf1
FL		 5140static int hclge_init_instance_hw(struct hclge_dev *hdev)
5141{
5142 return hclge_mac_connect_phy(hdev);
5143}
5144
5145static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
5146{
5147 hclge_mac_disconnect_phy(hdev);
5148}
5149
46a3df9f
S		 5150static int hclge_init_client_instance(struct hnae3_client *client,
5151 struct hnae3_ae_dev *ae_dev)
5152{
5153 struct hclge_dev *hdev = ae_dev->priv;
5154 struct hclge_vport *vport;
5155 int i, ret;
5156
5157 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5158 vport = &hdev->vport[i];
5159
5160 switch (client->type) {
5161 case HNAE3_CLIENT_KNIC:
5162
5163 hdev->nic_client = client;
5164 vport->nic.client = client;
5165 ret = client->ops->init_instance(&vport->nic);
5166 if (ret)
49dd8054 5167 goto clear_nic;
46a3df9f 5168
b01b7cf1
FL		 5169 ret = hclge_init_instance_hw(hdev);
5170 if (ret) {
5171 client->ops->uninit_instance(&vport->nic,
5172 0);
49dd8054 5173 goto clear_nic;
b01b7cf1
FL		 5174 }
5175
d9f28fc2
JS		 5176 hnae3_set_client_init_flag(client, ae_dev, 1);
5177
46a3df9f 5178 if (hdev->roce_client &&
e92a0843 5179 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5180 struct hnae3_client *rc = hdev->roce_client;
5181
5182 ret = hclge_init_roce_base_info(vport);
5183 if (ret)
49dd8054 5184 goto clear_roce;
46a3df9f
S		 5185
5186 ret = rc->ops->init_instance(&vport->roce);
5187 if (ret)
49dd8054 5188 goto clear_roce;
d9f28fc2
JS		 5189
5190 hnae3_set_client_init_flag(hdev->roce_client,
5191 ae_dev, 1);
46a3df9f
S		 5192 }
5193
5194 break;
5195 case HNAE3_CLIENT_UNIC:
5196 hdev->nic_client = client;
5197 vport->nic.client = client;
5198
5199 ret = client->ops->init_instance(&vport->nic);
5200 if (ret)
49dd8054 5201 goto clear_nic;
46a3df9f 5202
d9f28fc2
JS		 5203 hnae3_set_client_init_flag(client, ae_dev, 1);
5204
46a3df9f
S		 5205 break;
5206 case HNAE3_CLIENT_ROCE:
e92a0843 5207 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5208 hdev->roce_client = client;
5209 vport->roce.client = client;
5210 }
5211
3a46f34d 5212 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 5213 ret = hclge_init_roce_base_info(vport);
5214 if (ret)
49dd8054 5215 goto clear_roce;
46a3df9f
S		 5216
5217 ret = client->ops->init_instance(&vport->roce);
5218 if (ret)
49dd8054 5219 goto clear_roce;
d9f28fc2
JS		 5220
5221 hnae3_set_client_init_flag(client, ae_dev, 1);
46a3df9f 5222 }
fa7a4bd5
JS		 5223
5224 break;
5225 default:
5226 return -EINVAL;
46a3df9f
S		 5227 }
5228 }
5229
5230 return 0;
49dd8054
JS		 5231
5232clear_nic:
5233 hdev->nic_client = NULL;
5234 vport->nic.client = NULL;
5235 return ret;
5236clear_roce:
5237 hdev->roce_client = NULL;
5238 vport->roce.client = NULL;
5239 return ret;
46a3df9f
S		 5240}
5241
5242static void hclge_uninit_client_instance(struct hnae3_client *client,
5243 struct hnae3_ae_dev *ae_dev)
5244{
5245 struct hclge_dev *hdev = ae_dev->priv;
5246 struct hclge_vport *vport;
5247 int i;
5248
5249 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5250 vport = &hdev->vport[i];
a17dcf3f 5251 if (hdev->roce_client) {
46a3df9f
S		 5252 hdev->roce_client->ops->uninit_instance(&vport->roce,
5253 0);
a17dcf3f
L		 5254 hdev->roce_client = NULL;
5255 vport->roce.client = NULL;
5256 }
46a3df9f
S		 5257 if (client->type == HNAE3_CLIENT_ROCE)
5258 return;
49dd8054 5259 if (hdev->nic_client && client->ops->uninit_instance) {
b01b7cf1 5260 hclge_uninit_instance_hw(hdev);
46a3df9f 5261 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 5262 hdev->nic_client = NULL;
5263 vport->nic.client = NULL;
5264 }
46a3df9f
S		 5265 }
5266}
5267
5268static int hclge_pci_init(struct hclge_dev *hdev)
5269{
5270 struct pci_dev *pdev = hdev->pdev;
5271 struct hclge_hw *hw;
5272 int ret;
5273
5274 ret = pci_enable_device(pdev);
5275 if (ret) {
5276 dev_err(&pdev->dev, "failed to enable PCI device\n");
3e249d3b 5277 return ret;
46a3df9f
S		 5278 }
5279
5280 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5281 if (ret) {
5282 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5283 if (ret) {
5284 dev_err(&pdev->dev,
5285 "can't set consistent PCI DMA");
5286 goto err_disable_device;
5287 }
5288 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5289 }
5290
5291 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5292 if (ret) {
5293 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5294 goto err_disable_device;
5295 }
5296
5297 pci_set_master(pdev);
5298 hw = &hdev->hw;
46a3df9f
S		 5299 hw->io_base = pcim_iomap(pdev, 2, 0);
5300 if (!hw->io_base) {
5301 dev_err(&pdev->dev, "Can't map configuration register space\n");
5302 ret = -ENOMEM;
5303 goto err_clr_master;
5304 }
5305
709eb41a
L		 5306 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5307
46a3df9f
S		 5308 return 0;
5309err_clr_master:
5310 pci_clear_master(pdev);
5311 pci_release_regions(pdev);
5312err_disable_device:
5313 pci_disable_device(pdev);
46a3df9f
S		 5314
5315 return ret;
5316}
5317
5318static void hclge_pci_uninit(struct hclge_dev *hdev)
5319{
5320 struct pci_dev *pdev = hdev->pdev;
5321
6a814413 5322 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 5323 pci_free_irq_vectors(pdev);
46a3df9f
S		 5324 pci_clear_master(pdev);
5325 pci_release_mem_regions(pdev);
5326 pci_disable_device(pdev);
5327}
5328
48569cda
PL		 5329static void hclge_state_init(struct hclge_dev *hdev)
5330{
5331 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5332 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5333 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5334 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5335 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5336 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5337}
5338
5339static void hclge_state_uninit(struct hclge_dev *hdev)
5340{
5341 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5342
5343 if (hdev->service_timer.function)
5344 del_timer_sync(&hdev->service_timer);
5345 if (hdev->service_task.func)
5346 cancel_work_sync(&hdev->service_task);
5347 if (hdev->rst_service_task.func)
5348 cancel_work_sync(&hdev->rst_service_task);
5349 if (hdev->mbx_service_task.func)
5350 cancel_work_sync(&hdev->mbx_service_task);
5351}
5352
46a3df9f
S		 5353static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5354{
5355 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 5356 struct hclge_dev *hdev;
5357 int ret;
5358
5359 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5360 if (!hdev) {
5361 ret = -ENOMEM;
ffd5656e 5362 goto out;
46a3df9f
S		 5363 }
5364
46a3df9f
S		 5365 hdev->pdev = pdev;
5366 hdev->ae_dev = ae_dev;
4ed340ab 5367 hdev->reset_type = HNAE3_NONE_RESET;
46a3df9f
S		 5368 ae_dev->priv = hdev;
5369
46a3df9f
S		 5370 ret = hclge_pci_init(hdev);
5371 if (ret) {
5372 dev_err(&pdev->dev, "PCI init failed\n");
ffd5656e 5373 goto out;
46a3df9f
S		 5374 }
5375
3efb960f
L		 5376 /* Firmware command queue initialize */
5377 ret = hclge_cmd_queue_init(hdev);
5378 if (ret) {
5379 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
ffd5656e 5380 goto err_pci_uninit;
3efb960f
L		 5381 }
5382
5383 /* Firmware command initialize */
46a3df9f
S		 5384 ret = hclge_cmd_init(hdev);
5385 if (ret)
ffd5656e 5386 goto err_cmd_uninit;
46a3df9f
S		 5387
5388 ret = hclge_get_cap(hdev);
5389 if (ret) {
e00e2197
CIK		 5390 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5391 ret);
ffd5656e 5392 goto err_cmd_uninit;
46a3df9f
S		 5393 }
5394
5395 ret = hclge_configure(hdev);
5396 if (ret) {
5397 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
ffd5656e 5398 goto err_cmd_uninit;
46a3df9f
S		 5399 }
5400
887c3820 5401 ret = hclge_init_msi(hdev);
46a3df9f 5402 if (ret) {
887c3820 5403 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
ffd5656e 5404 goto err_cmd_uninit;
46a3df9f
S		 5405 }
5406
466b0c00
L		 5407 ret = hclge_misc_irq_init(hdev);
5408 if (ret) {
5409 dev_err(&pdev->dev,
5410 "Misc IRQ(vector0) init error, ret = %d.\n",
5411 ret);
ffd5656e 5412 goto err_msi_uninit;
466b0c00
L		 5413 }
5414
46a3df9f
S		 5415 ret = hclge_alloc_tqps(hdev);
5416 if (ret) {
5417 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
ffd5656e 5418 goto err_msi_irq_uninit;
46a3df9f
S		 5419 }
5420
5421 ret = hclge_alloc_vport(hdev);
5422 if (ret) {
5423 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
ffd5656e 5424 goto err_msi_irq_uninit;
46a3df9f
S		 5425 }
5426
7df7dad6
L		 5427 ret = hclge_map_tqp(hdev);
5428 if (ret) {
5429 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
2312e050 5430 goto err_msi_irq_uninit;
7df7dad6
L		 5431 }
5432
c5ef83cb
HT		 5433 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5434 ret = hclge_mac_mdio_config(hdev);
5435 if (ret) {
5436 dev_err(&hdev->pdev->dev,
5437 "mdio config fail ret=%d\n", ret);
2312e050 5438 goto err_msi_irq_uninit;
c5ef83cb 5439 }
cf9cca2d 5440 }
5441
46a3df9f
S		 5442 ret = hclge_mac_init(hdev);
5443 if (ret) {
5444 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
ffd5656e 5445 goto err_mdiobus_unreg;
46a3df9f 5446 }
46a3df9f
S		 5447
5448 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5449 if (ret) {
5450 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
ffd5656e 5451 goto err_mdiobus_unreg;
46a3df9f
S		 5452 }
5453
46a3df9f
S		 5454 ret = hclge_init_vlan_config(hdev);
5455 if (ret) {
5456 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
ffd5656e 5457 goto err_mdiobus_unreg;
46a3df9f
S		 5458 }
5459
5460 ret = hclge_tm_schd_init(hdev);
5461 if (ret) {
5462 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
ffd5656e 5463 goto err_mdiobus_unreg;
68ece54e
YL		 5464 }
5465
268f5dfa 5466 hclge_rss_init_cfg(hdev);
68ece54e
YL		 5467 ret = hclge_rss_init_hw(hdev);
5468 if (ret) {
5469 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
ffd5656e 5470 goto err_mdiobus_unreg;
46a3df9f
S		 5471 }
5472
f5aac71c
FL		 5473 ret = init_mgr_tbl(hdev);
5474 if (ret) {
5475 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
ffd5656e 5476 goto err_mdiobus_unreg;
f5aac71c
FL		 5477 }
5478
cacde272
YL		 5479 hclge_dcb_ops_set(hdev);
5480
d039ef68 5481 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 5482 INIT_WORK(&hdev->service_task, hclge_service_task);
cb1b9f77 5483 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
c1a81619 5484 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 5485
8e52a602
XW		 5486 hclge_clear_all_event_cause(hdev);
5487
466b0c00
L		 5488 /* Enable MISC vector(vector0) */
5489 hclge_enable_vector(&hdev->misc_vector, true);
5490
48569cda 5491 hclge_state_init(hdev);
46a3df9f
S		 5492
5493 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5494 return 0;
5495
ffd5656e
HT		 5496err_mdiobus_unreg:
5497 if (hdev->hw.mac.phydev)
5498 mdiobus_unregister(hdev->hw.mac.mdio_bus);
ffd5656e
HT		 5499err_msi_irq_uninit:
5500 hclge_misc_irq_uninit(hdev);
5501err_msi_uninit:
5502 pci_free_irq_vectors(pdev);
5503err_cmd_uninit:
5504 hclge_destroy_cmd_queue(&hdev->hw);
5505err_pci_uninit:
6a814413 5506 pcim_iounmap(pdev, hdev->hw.io_base);
ffd5656e 5507 pci_clear_master(pdev);
46a3df9f 5508 pci_release_regions(pdev);
ffd5656e 5509 pci_disable_device(pdev);
ffd5656e 5510out:
46a3df9f
S		 5511 return ret;
5512}
5513
c6dc5213 5514static void hclge_stats_clear(struct hclge_dev *hdev)
5515{
5516 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5517}
5518
4ed340ab
L		 5519static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5520{
5521 struct hclge_dev *hdev = ae_dev->priv;
5522 struct pci_dev *pdev = ae_dev->pdev;
5523 int ret;
5524
5525 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5526
c6dc5213 5527 hclge_stats_clear(hdev);
dc8131d8 5528 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 5529
4ed340ab
L		 5530 ret = hclge_cmd_init(hdev);
5531 if (ret) {
5532 dev_err(&pdev->dev, "Cmd queue init failed\n");
5533 return ret;
5534 }
5535
5536 ret = hclge_get_cap(hdev);
5537 if (ret) {
5538 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5539 ret);
5540 return ret;
5541 }
5542
5543 ret = hclge_configure(hdev);
5544 if (ret) {
5545 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5546 return ret;
5547 }
5548
5549 ret = hclge_map_tqp(hdev);
5550 if (ret) {
5551 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5552 return ret;
5553 }
5554
5555 ret = hclge_mac_init(hdev);
5556 if (ret) {
5557 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5558 return ret;
5559 }
5560
4ed340ab
L		 5561 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5562 if (ret) {
5563 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5564 return ret;
5565 }
5566
5567 ret = hclge_init_vlan_config(hdev);
5568 if (ret) {
5569 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5570 return ret;
5571 }
5572
f31c1ba6 5573 ret = hclge_tm_init_hw(hdev);
4ed340ab 5574 if (ret) {
f31c1ba6 5575 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 5576 return ret;
5577 }
5578
5579 ret = hclge_rss_init_hw(hdev);
5580 if (ret) {
5581 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5582 return ret;
5583 }
5584
4ed340ab
L		 5585 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5586 HCLGE_DRIVER_NAME);
5587
5588 return 0;
5589}
5590
46a3df9f
S		 5591static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5592{
5593 struct hclge_dev *hdev = ae_dev->priv;
5594 struct hclge_mac *mac = &hdev->hw.mac;
5595
48569cda 5596 hclge_state_uninit(hdev);
46a3df9f
S		 5597
5598 if (mac->phydev)
5599 mdiobus_unregister(mac->mdio_bus);
5600
466b0c00
L		 5601 /* Disable MISC vector(vector0) */
5602 hclge_enable_vector(&hdev->misc_vector, false);
8e52a602
XW		 5603 synchronize_irq(hdev->misc_vector.vector_irq);
5604
46a3df9f 5605 hclge_destroy_cmd_queue(&hdev->hw);
ca1d7669 5606 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5607 hclge_pci_uninit(hdev);
5608 ae_dev->priv = NULL;
5609}
5610
482d2e9c
PL		 5611static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5612{
5613 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5614 struct hclge_vport *vport = hclge_get_vport(handle);
5615 struct hclge_dev *hdev = vport->back;
5616
5617 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5618}
5619
5620static void hclge_get_channels(struct hnae3_handle *handle,
5621 struct ethtool_channels *ch)
5622{
5623 struct hclge_vport *vport = hclge_get_vport(handle);
5624
5625 ch->max_combined = hclge_get_max_channels(handle);
5626 ch->other_count = 1;
5627 ch->max_other = 1;
5628 ch->combined_count = vport->alloc_tqps;
5629}
5630
09f2af64
PL		 5631static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
5632 u16 *free_tqps, u16 *max_rss_size)
5633{
5634 struct hclge_vport *vport = hclge_get_vport(handle);
5635 struct hclge_dev *hdev = vport->back;
5636 u16 temp_tqps = 0;
5637 int i;
5638
5639 for (i = 0; i < hdev->num_tqps; i++) {
5640 if (!hdev->htqp[i].alloced)
5641 temp_tqps++;
5642 }
5643 *free_tqps = temp_tqps;
5644 *max_rss_size = hdev->rss_size_max;
5645}
5646
5647static void hclge_release_tqp(struct hclge_vport *vport)
5648{
5649 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5650 struct hclge_dev *hdev = vport->back;
5651 int i;
5652
5653 for (i = 0; i < kinfo->num_tqps; i++) {
5654 struct hclge_tqp *tqp =
5655 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5656
5657 tqp->q.handle = NULL;
5658 tqp->q.tqp_index = 0;
5659 tqp->alloced = false;
5660 }
5661
5662 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5663 kinfo->tqp = NULL;
5664}
5665
5666static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5667{
5668 struct hclge_vport *vport = hclge_get_vport(handle);
5669 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5670 struct hclge_dev *hdev = vport->back;
5671 int cur_rss_size = kinfo->rss_size;
5672 int cur_tqps = kinfo->num_tqps;
5673 u16 tc_offset[HCLGE_MAX_TC_NUM];
5674 u16 tc_valid[HCLGE_MAX_TC_NUM];
5675 u16 tc_size[HCLGE_MAX_TC_NUM];
5676 u16 roundup_size;
5677 u32 *rss_indir;
5678 int ret, i;
5679
fdace1bc 5680 /* Free old tqps, and reallocate with new tqp number when nic setup */
09f2af64
PL		 5681 hclge_release_tqp(vport);
5682
128b900d 5683 ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc);
09f2af64
PL		 5684 if (ret) {
5685 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5686 return ret;
5687 }
5688
5689 ret = hclge_map_tqp_to_vport(hdev, vport);
5690 if (ret) {
5691 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5692 return ret;
5693 }
5694
5695 ret = hclge_tm_schd_init(hdev);
5696 if (ret) {
5697 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5698 return ret;
5699 }
5700
5701 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5702 roundup_size = ilog2(roundup_size);
5703 /* Set the RSS TC mode according to the new RSS size */
5704 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5705 tc_valid[i] = 0;
5706
5707 if (!(hdev->hw_tc_map & BIT(i)))
5708 continue;
5709
5710 tc_valid[i] = 1;
5711 tc_size[i] = roundup_size;
5712 tc_offset[i] = kinfo->rss_size * i;
5713 }
5714 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5715 if (ret)
5716 return ret;
5717
5718 /* Reinitializes the rss indirect table according to the new RSS size */
5719 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5720 if (!rss_indir)
5721 return -ENOMEM;
5722
5723 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5724 rss_indir[i] = i % kinfo->rss_size;
5725
5726 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5727 if (ret)
5728 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5729 ret);
5730
5731 kfree(rss_indir);
5732
5733 if (!ret)
5734 dev_info(&hdev->pdev->dev,
5735 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5736 cur_rss_size, kinfo->rss_size,
5737 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5738
5739 return ret;
5740}
5741
77b34110
FL		 5742static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5743 u32 *regs_num_64_bit)
5744{
5745 struct hclge_desc desc;
5746 u32 total_num;
5747 int ret;
5748
5749 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5750 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5751 if (ret) {
5752 dev_err(&hdev->pdev->dev,
5753 "Query register number cmd failed, ret = %d.\n", ret);
5754 return ret;
5755 }
5756
5757 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
5758 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
5759
5760 total_num = *regs_num_32_bit + *regs_num_64_bit;
5761 if (!total_num)
5762 return -EINVAL;
5763
5764 return 0;
5765}
5766
5767static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5768 void *data)
5769{
5770#define HCLGE_32_BIT_REG_RTN_DATANUM 8
5771
5772 struct hclge_desc *desc;
5773 u32 *reg_val = data;
5774 __le32 *desc_data;
5775 int cmd_num;
5776 int i, k, n;
5777 int ret;
5778
5779 if (regs_num == 0)
5780 return 0;
5781
5782 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
5783 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5784 if (!desc)
5785 return -ENOMEM;
5786
5787 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
5788 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5789 if (ret) {
5790 dev_err(&hdev->pdev->dev,
5791 "Query 32 bit register cmd failed, ret = %d.\n", ret);
5792 kfree(desc);
5793 return ret;
5794 }
5795
5796 for (i = 0; i < cmd_num; i++) {
5797 if (i == 0) {
5798 desc_data = (__le32 *)(&desc[i].data[0]);
5799 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
5800 } else {
5801 desc_data = (__le32 *)(&desc[i]);
5802 n = HCLGE_32_BIT_REG_RTN_DATANUM;
5803 }
5804 for (k = 0; k < n; k++) {
5805 *reg_val++ = le32_to_cpu(*desc_data++);
5806
5807 regs_num--;
5808 if (!regs_num)
5809 break;
5810 }
5811 }
5812
5813 kfree(desc);
5814 return 0;
5815}
5816
5817static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5818 void *data)
5819{
5820#define HCLGE_64_BIT_REG_RTN_DATANUM 4
5821
5822 struct hclge_desc *desc;
5823 u64 *reg_val = data;
5824 __le64 *desc_data;
5825 int cmd_num;
5826 int i, k, n;
5827 int ret;
5828
5829 if (regs_num == 0)
5830 return 0;
5831
5832 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
5833 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5834 if (!desc)
5835 return -ENOMEM;
5836
5837 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
5838 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5839 if (ret) {
5840 dev_err(&hdev->pdev->dev,
5841 "Query 64 bit register cmd failed, ret = %d.\n", ret);
5842 kfree(desc);
5843 return ret;
5844 }
5845
5846 for (i = 0; i < cmd_num; i++) {
5847 if (i == 0) {
5848 desc_data = (__le64 *)(&desc[i].data[0]);
5849 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
5850 } else {
5851 desc_data = (__le64 *)(&desc[i]);
5852 n = HCLGE_64_BIT_REG_RTN_DATANUM;
5853 }
5854 for (k = 0; k < n; k++) {
5855 *reg_val++ = le64_to_cpu(*desc_data++);
5856
5857 regs_num--;
5858 if (!regs_num)
5859 break;
5860 }
5861 }
5862
5863 kfree(desc);
5864 return 0;
5865}
5866
5867static int hclge_get_regs_len(struct hnae3_handle *handle)
5868{
5869 struct hclge_vport *vport = hclge_get_vport(handle);
5870 struct hclge_dev *hdev = vport->back;
5871 u32 regs_num_32_bit, regs_num_64_bit;
5872 int ret;
5873
5874 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5875 if (ret) {
5876 dev_err(&hdev->pdev->dev,
5877 "Get register number failed, ret = %d.\n", ret);
5878 return -EOPNOTSUPP;
5879 }
5880
5881 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
5882}
5883
5884static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
5885 void *data)
5886{
5887 struct hclge_vport *vport = hclge_get_vport(handle);
5888 struct hclge_dev *hdev = vport->back;
5889 u32 regs_num_32_bit, regs_num_64_bit;
5890 int ret;
5891
5892 *version = hdev->fw_version;
5893
5894 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5895 if (ret) {
5896 dev_err(&hdev->pdev->dev,
5897 "Get register number failed, ret = %d.\n", ret);
5898 return;
5899 }
5900
5901 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
5902 if (ret) {
5903 dev_err(&hdev->pdev->dev,
5904 "Get 32 bit register failed, ret = %d.\n", ret);
5905 return;
5906 }
5907
5908 data = (u32 *)data + regs_num_32_bit;
5909 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
5910 data);
5911 if (ret)
5912 dev_err(&hdev->pdev->dev,
5913 "Get 64 bit register failed, ret = %d.\n", ret);
5914}
5915
f6f75abc 5916static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
07f8e940
JS		 5917{
5918 struct hclge_set_led_state_cmd *req;
5919 struct hclge_desc desc;
5920 int ret;
5921
5922 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
5923
5924 req = (struct hclge_set_led_state_cmd *)desc.data;
e4e87715
PL		 5925 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
5926 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
07f8e940
JS		 5927
5928 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5929 if (ret)
5930 dev_err(&hdev->pdev->dev,
5931 "Send set led state cmd error, ret =%d\n", ret);
5932
5933 return ret;
5934}
5935
5936enum hclge_led_status {
5937 HCLGE_LED_OFF,
5938 HCLGE_LED_ON,
5939 HCLGE_LED_NO_CHANGE = 0xFF,
5940};
5941
5942static int hclge_set_led_id(struct hnae3_handle *handle,
5943 enum ethtool_phys_id_state status)
5944{
07f8e940
JS		 5945 struct hclge_vport *vport = hclge_get_vport(handle);
5946 struct hclge_dev *hdev = vport->back;
07f8e940
JS		 5947
5948 switch (status) {
5949 case ETHTOOL_ID_ACTIVE:
f6f75abc 5950 return hclge_set_led_status(hdev, HCLGE_LED_ON);
07f8e940 5951 case ETHTOOL_ID_INACTIVE:
f6f75abc 5952 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
07f8e940 5953 default:
f6f75abc 5954 return -EINVAL;
07f8e940 5955 }
07f8e940
JS		 5956}
5957
0979aa0b
FL		 5958static void hclge_get_link_mode(struct hnae3_handle *handle,
5959 unsigned long *supported,
5960 unsigned long *advertising)
5961{
5962 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
5963 struct hclge_vport *vport = hclge_get_vport(handle);
5964 struct hclge_dev *hdev = vport->back;
5965 unsigned int idx = 0;
5966
5967 for (; idx < size; idx++) {
5968 supported[idx] = hdev->hw.mac.supported[idx];
5969 advertising[idx] = hdev->hw.mac.advertising[idx];
5970 }
5971}
5972
46a3df9f
S		 5973static const struct hnae3_ae_ops hclge_ops = {
5974 .init_ae_dev = hclge_init_ae_dev,
5975 .uninit_ae_dev = hclge_uninit_ae_dev,
5976 .init_client_instance = hclge_init_client_instance,
5977 .uninit_client_instance = hclge_uninit_client_instance,
84e095d6
SM		 5978 .map_ring_to_vector = hclge_map_ring_to_vector,
5979 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 5980 .get_vector = hclge_get_vector,
0d3e6631 5981 .put_vector = hclge_put_vector,
46a3df9f 5982 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 5983 .set_loopback = hclge_set_loopback,
46a3df9f
S		 5984 .start = hclge_ae_start,
5985 .stop = hclge_ae_stop,
5986 .get_status = hclge_get_status,
5987 .get_ksettings_an_result = hclge_get_ksettings_an_result,
5988 .update_speed_duplex_h = hclge_update_speed_duplex_h,
5989 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
5990 .get_media_type = hclge_get_media_type,
5991 .get_rss_key_size = hclge_get_rss_key_size,
5992 .get_rss_indir_size = hclge_get_rss_indir_size,
5993 .get_rss = hclge_get_rss,
5994 .set_rss = hclge_set_rss,
f7db940a 5995 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 5996 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 5997 .get_tc_size = hclge_get_tc_size,
5998 .get_mac_addr = hclge_get_mac_addr,
5999 .set_mac_addr = hclge_set_mac_addr,
26483246 6000 .do_ioctl = hclge_do_ioctl,
46a3df9f
S		 6001 .add_uc_addr = hclge_add_uc_addr,
6002 .rm_uc_addr = hclge_rm_uc_addr,
6003 .add_mc_addr = hclge_add_mc_addr,
6004 .rm_mc_addr = hclge_rm_mc_addr,
40cca1c5 6005 .update_mta_status = hclge_update_mta_status,
46a3df9f
S		 6006 .set_autoneg = hclge_set_autoneg,
6007 .get_autoneg = hclge_get_autoneg,
6008 .get_pauseparam = hclge_get_pauseparam,
61387774 6009 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 6010 .set_mtu = hclge_set_mtu,
6011 .reset_queue = hclge_reset_tqp,
6012 .get_stats = hclge_get_stats,
6013 .update_stats = hclge_update_stats,
6014 .get_strings = hclge_get_strings,
6015 .get_sset_count = hclge_get_sset_count,
6016 .get_fw_version = hclge_get_fw_version,
6017 .get_mdix_mode = hclge_get_mdix_mode,
391b5e93 6018 .enable_vlan_filter = hclge_enable_vlan_filter,
dc8131d8 6019 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 6020 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
052ece6d 6021 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 6022 .reset_event = hclge_reset_event,
09f2af64
PL		 6023 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6024 .set_channels = hclge_set_channels,
482d2e9c 6025 .get_channels = hclge_get_channels,
77b34110
FL		 6026 .get_regs_len = hclge_get_regs_len,
6027 .get_regs = hclge_get_regs,
07f8e940 6028 .set_led_id = hclge_set_led_id,
0979aa0b 6029 .get_link_mode = hclge_get_link_mode,
46a3df9f
S		 6030};
6031
6032static struct hnae3_ae_algo ae_algo = {
6033 .ops = &hclge_ops,
46a3df9f
S		 6034 .pdev_id_table = ae_algo_pci_tbl,
6035};
6036
6037static int hclge_init(void)
6038{
6039 pr_info("%s is initializing\n", HCLGE_NAME);
6040
854cf33a
FL		 6041 hnae3_register_ae_algo(&ae_algo);
6042
6043 return 0;
46a3df9f
S		 6044}
6045
6046static void hclge_exit(void)
6047{
6048 hnae3_unregister_ae_algo(&ae_algo);
6049}
6050module_init(hclge_init);
6051module_exit(hclge_exit);
6052
6053MODULE_LICENSE("GPL");
6054MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6055MODULE_DESCRIPTION("HCLGE Driver");
6056MODULE_VERSION(HCLGE_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)