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net: hns3: Cleanup for ROCE capability flag in ae_dev
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
20
21#include "hclge_cmd.h"
22#include "hclge_main.h"
23#include "hclge_mdio.h"
24#include "hclge_tm.h"
25#include "hnae3.h"
26
27#define HCLGE_NAME "hclge"
28#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
29#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
30#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
31#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
32
33static int hclge_rss_init_hw(struct hclge_dev *hdev);
34static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
35 enum hclge_mta_dmac_sel_type mta_mac_sel,
36 bool enable);
37static int hclge_init_vlan_config(struct hclge_dev *hdev);
38
39static struct hnae3_ae_algo ae_algo;
40
41static const struct pci_device_id ae_algo_pci_tbl[] = {
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 49 /* required last entry */
46a3df9f
S		 50 {0, }
51};
52
53static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
54 "Mac Loopback test",
55 "Serdes Loopback test",
56 "Phy Loopback test"
57};
58
59static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
60 {"igu_rx_oversize_pkt",
61 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
62 {"igu_rx_undersize_pkt",
63 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
64 {"igu_rx_out_all_pkt",
65 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
66 {"igu_rx_uni_pkt",
67 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
68 {"igu_rx_multi_pkt",
69 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
70 {"igu_rx_broad_pkt",
71 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
72 {"egu_tx_out_all_pkt",
73 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
74 {"egu_tx_uni_pkt",
75 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
76 {"egu_tx_multi_pkt",
77 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
78 {"egu_tx_broad_pkt",
79 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
80 {"ssu_ppp_mac_key_num",
81 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
82 {"ssu_ppp_host_key_num",
83 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
84 {"ppp_ssu_mac_rlt_num",
85 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
86 {"ppp_ssu_host_rlt_num",
87 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
88 {"ssu_tx_in_num",
89 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
90 {"ssu_tx_out_num",
91 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
92 {"ssu_rx_in_num",
93 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
94 {"ssu_rx_out_num",
95 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
96};
97
98static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
99 {"igu_rx_err_pkt",
100 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
101 {"igu_rx_no_eof_pkt",
102 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
103 {"igu_rx_no_sof_pkt",
104 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
105 {"egu_tx_1588_pkt",
106 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
107 {"ssu_full_drop_num",
108 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
109 {"ssu_part_drop_num",
110 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
111 {"ppp_key_drop_num",
112 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
113 {"ppp_rlt_drop_num",
114 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
115 {"ssu_key_drop_num",
116 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
117 {"pkt_curr_buf_cnt",
118 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
119 {"qcn_fb_rcv_cnt",
120 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
121 {"qcn_fb_drop_cnt",
122 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
123 {"qcn_fb_invaild_cnt",
124 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
125 {"rx_packet_tc0_in_cnt",
126 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
127 {"rx_packet_tc1_in_cnt",
128 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
129 {"rx_packet_tc2_in_cnt",
130 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
131 {"rx_packet_tc3_in_cnt",
132 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
133 {"rx_packet_tc4_in_cnt",
134 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
135 {"rx_packet_tc5_in_cnt",
136 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
137 {"rx_packet_tc6_in_cnt",
138 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
139 {"rx_packet_tc7_in_cnt",
140 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
141 {"rx_packet_tc0_out_cnt",
142 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
143 {"rx_packet_tc1_out_cnt",
144 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
145 {"rx_packet_tc2_out_cnt",
146 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
147 {"rx_packet_tc3_out_cnt",
148 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
149 {"rx_packet_tc4_out_cnt",
150 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
151 {"rx_packet_tc5_out_cnt",
152 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
153 {"rx_packet_tc6_out_cnt",
154 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
155 {"rx_packet_tc7_out_cnt",
156 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
157 {"tx_packet_tc0_in_cnt",
158 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
159 {"tx_packet_tc1_in_cnt",
160 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
161 {"tx_packet_tc2_in_cnt",
162 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
163 {"tx_packet_tc3_in_cnt",
164 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
165 {"tx_packet_tc4_in_cnt",
166 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
167 {"tx_packet_tc5_in_cnt",
168 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
169 {"tx_packet_tc6_in_cnt",
170 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
171 {"tx_packet_tc7_in_cnt",
172 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
173 {"tx_packet_tc0_out_cnt",
174 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
175 {"tx_packet_tc1_out_cnt",
176 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
177 {"tx_packet_tc2_out_cnt",
178 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
179 {"tx_packet_tc3_out_cnt",
180 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
181 {"tx_packet_tc4_out_cnt",
182 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
183 {"tx_packet_tc5_out_cnt",
184 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
185 {"tx_packet_tc6_out_cnt",
186 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
187 {"tx_packet_tc7_out_cnt",
188 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
189 {"pkt_curr_buf_tc0_cnt",
190 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
191 {"pkt_curr_buf_tc1_cnt",
192 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
193 {"pkt_curr_buf_tc2_cnt",
194 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
195 {"pkt_curr_buf_tc3_cnt",
196 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
197 {"pkt_curr_buf_tc4_cnt",
198 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
199 {"pkt_curr_buf_tc5_cnt",
200 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
201 {"pkt_curr_buf_tc6_cnt",
202 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
203 {"pkt_curr_buf_tc7_cnt",
204 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
205 {"mb_uncopy_num",
206 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
207 {"lo_pri_unicast_rlt_drop_num",
208 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
209 {"hi_pri_multicast_rlt_drop_num",
210 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
211 {"lo_pri_multicast_rlt_drop_num",
212 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
213 {"rx_oq_drop_pkt_cnt",
214 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
215 {"tx_oq_drop_pkt_cnt",
216 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
217 {"nic_l2_err_drop_pkt_cnt",
218 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
219 {"roc_l2_err_drop_pkt_cnt",
220 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
221};
222
223static const struct hclge_comm_stats_str g_mac_stats_string[] = {
224 {"mac_tx_mac_pause_num",
225 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
226 {"mac_rx_mac_pause_num",
227 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
228 {"mac_tx_pfc_pri0_pkt_num",
229 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
230 {"mac_tx_pfc_pri1_pkt_num",
231 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
232 {"mac_tx_pfc_pri2_pkt_num",
233 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
234 {"mac_tx_pfc_pri3_pkt_num",
235 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
236 {"mac_tx_pfc_pri4_pkt_num",
237 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
238 {"mac_tx_pfc_pri5_pkt_num",
239 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
240 {"mac_tx_pfc_pri6_pkt_num",
241 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
242 {"mac_tx_pfc_pri7_pkt_num",
243 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
244 {"mac_rx_pfc_pri0_pkt_num",
245 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
246 {"mac_rx_pfc_pri1_pkt_num",
247 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
248 {"mac_rx_pfc_pri2_pkt_num",
249 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
250 {"mac_rx_pfc_pri3_pkt_num",
251 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
252 {"mac_rx_pfc_pri4_pkt_num",
253 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
254 {"mac_rx_pfc_pri5_pkt_num",
255 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
256 {"mac_rx_pfc_pri6_pkt_num",
257 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
258 {"mac_rx_pfc_pri7_pkt_num",
259 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
260 {"mac_tx_total_pkt_num",
261 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
262 {"mac_tx_total_oct_num",
263 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
264 {"mac_tx_good_pkt_num",
265 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
266 {"mac_tx_bad_pkt_num",
267 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
268 {"mac_tx_good_oct_num",
269 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
270 {"mac_tx_bad_oct_num",
271 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
272 {"mac_tx_uni_pkt_num",
273 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
274 {"mac_tx_multi_pkt_num",
275 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
276 {"mac_tx_broad_pkt_num",
277 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
278 {"mac_tx_undersize_pkt_num",
279 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
280 {"mac_tx_overrsize_pkt_num",
281 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
282 {"mac_tx_64_oct_pkt_num",
283 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
284 {"mac_tx_65_127_oct_pkt_num",
285 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
286 {"mac_tx_128_255_oct_pkt_num",
287 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
288 {"mac_tx_256_511_oct_pkt_num",
289 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
290 {"mac_tx_512_1023_oct_pkt_num",
291 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
292 {"mac_tx_1024_1518_oct_pkt_num",
293 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
294 {"mac_tx_1519_max_oct_pkt_num",
295 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
296 {"mac_rx_total_pkt_num",
297 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
298 {"mac_rx_total_oct_num",
299 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
300 {"mac_rx_good_pkt_num",
301 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
302 {"mac_rx_bad_pkt_num",
303 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
304 {"mac_rx_good_oct_num",
305 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
306 {"mac_rx_bad_oct_num",
307 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
308 {"mac_rx_uni_pkt_num",
309 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
310 {"mac_rx_multi_pkt_num",
311 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
312 {"mac_rx_broad_pkt_num",
313 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
314 {"mac_rx_undersize_pkt_num",
315 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
316 {"mac_rx_overrsize_pkt_num",
317 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
318 {"mac_rx_64_oct_pkt_num",
319 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
320 {"mac_rx_65_127_oct_pkt_num",
321 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
322 {"mac_rx_128_255_oct_pkt_num",
323 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
324 {"mac_rx_256_511_oct_pkt_num",
325 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
326 {"mac_rx_512_1023_oct_pkt_num",
327 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
328 {"mac_rx_1024_1518_oct_pkt_num",
329 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
330 {"mac_rx_1519_max_oct_pkt_num",
331 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
332
333 {"mac_trans_fragment_pkt_num",
334 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
335 {"mac_trans_undermin_pkt_num",
336 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
337 {"mac_trans_jabber_pkt_num",
338 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
339 {"mac_trans_err_all_pkt_num",
340 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
341 {"mac_trans_from_app_good_pkt_num",
342 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
343 {"mac_trans_from_app_bad_pkt_num",
344 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
345 {"mac_rcv_fragment_pkt_num",
346 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
347 {"mac_rcv_undermin_pkt_num",
348 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
349 {"mac_rcv_jabber_pkt_num",
350 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
351 {"mac_rcv_fcs_err_pkt_num",
352 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
353 {"mac_rcv_send_app_good_pkt_num",
354 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
355 {"mac_rcv_send_app_bad_pkt_num",
356 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
357};
358
359static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
360{
361#define HCLGE_64_BIT_CMD_NUM 5
362#define HCLGE_64_BIT_RTN_DATANUM 4
363 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
364 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
365 u64 *desc_data;
366 int i, k, n;
367 int ret;
368
369 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
370 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
371 if (ret) {
372 dev_err(&hdev->pdev->dev,
373 "Get 64 bit pkt stats fail, status = %d.\n", ret);
374 return ret;
375 }
376
377 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
378 if (unlikely(i == 0)) {
379 desc_data = (u64 *)(&desc[i].data[0]);
380 n = HCLGE_64_BIT_RTN_DATANUM - 1;
381 } else {
382 desc_data = (u64 *)(&desc[i]);
383 n = HCLGE_64_BIT_RTN_DATANUM;
384 }
385 for (k = 0; k < n; k++) {
386 *data++ += cpu_to_le64(*desc_data);
387 desc_data++;
388 }
389 }
390
391 return 0;
392}
393
394static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
395{
396 stats->pkt_curr_buf_cnt = 0;
397 stats->pkt_curr_buf_tc0_cnt = 0;
398 stats->pkt_curr_buf_tc1_cnt = 0;
399 stats->pkt_curr_buf_tc2_cnt = 0;
400 stats->pkt_curr_buf_tc3_cnt = 0;
401 stats->pkt_curr_buf_tc4_cnt = 0;
402 stats->pkt_curr_buf_tc5_cnt = 0;
403 stats->pkt_curr_buf_tc6_cnt = 0;
404 stats->pkt_curr_buf_tc7_cnt = 0;
405}
406
407static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
408{
409#define HCLGE_32_BIT_CMD_NUM 8
410#define HCLGE_32_BIT_RTN_DATANUM 8
411
412 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
413 struct hclge_32_bit_stats *all_32_bit_stats;
414 u32 *desc_data;
415 int i, k, n;
416 u64 *data;
417 int ret;
418
419 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
420 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
421
422 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
423 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
424 if (ret) {
425 dev_err(&hdev->pdev->dev,
426 "Get 32 bit pkt stats fail, status = %d.\n", ret);
427
428 return ret;
429 }
430
431 hclge_reset_partial_32bit_counter(all_32_bit_stats);
432 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
433 if (unlikely(i == 0)) {
434 all_32_bit_stats->igu_rx_err_pkt +=
435 cpu_to_le32(desc[i].data[0]);
436 all_32_bit_stats->igu_rx_no_eof_pkt +=
437 cpu_to_le32(desc[i].data[1] & 0xffff);
438 all_32_bit_stats->igu_rx_no_sof_pkt +=
439 cpu_to_le32((desc[i].data[1] >> 16) & 0xffff);
440
441 desc_data = (u32 *)(&desc[i].data[2]);
442 n = HCLGE_32_BIT_RTN_DATANUM - 4;
443 } else {
444 desc_data = (u32 *)(&desc[i]);
445 n = HCLGE_32_BIT_RTN_DATANUM;
446 }
447 for (k = 0; k < n; k++) {
448 *data++ += cpu_to_le32(*desc_data);
449 desc_data++;
450 }
451 }
452
453 return 0;
454}
455
456static int hclge_mac_update_stats(struct hclge_dev *hdev)
457{
458#define HCLGE_MAC_CMD_NUM 17
459#define HCLGE_RTN_DATA_NUM 4
460
461 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
462 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
463 u64 *desc_data;
464 int i, k, n;
465 int ret;
466
467 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
468 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
469 if (ret) {
470 dev_err(&hdev->pdev->dev,
471 "Get MAC pkt stats fail, status = %d.\n", ret);
472
473 return ret;
474 }
475
476 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
477 if (unlikely(i == 0)) {
478 desc_data = (u64 *)(&desc[i].data[0]);
479 n = HCLGE_RTN_DATA_NUM - 2;
480 } else {
481 desc_data = (u64 *)(&desc[i]);
482 n = HCLGE_RTN_DATA_NUM;
483 }
484 for (k = 0; k < n; k++) {
485 *data++ += cpu_to_le64(*desc_data);
486 desc_data++;
487 }
488 }
489
490 return 0;
491}
492
493static int hclge_tqps_update_stats(struct hnae3_handle *handle)
494{
495 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
496 struct hclge_vport *vport = hclge_get_vport(handle);
497 struct hclge_dev *hdev = vport->back;
498 struct hnae3_queue *queue;
499 struct hclge_desc desc[1];
500 struct hclge_tqp *tqp;
501 int ret, i;
502
503 for (i = 0; i < kinfo->num_tqps; i++) {
504 queue = handle->kinfo.tqp[i];
505 tqp = container_of(queue, struct hclge_tqp, q);
506 /* command : HCLGE_OPC_QUERY_IGU_STAT */
507 hclge_cmd_setup_basic_desc(&desc[0],
508 HCLGE_OPC_QUERY_RX_STATUS,
509 true);
510
511 desc[0].data[0] = (tqp->index & 0x1ff);
512 ret = hclge_cmd_send(&hdev->hw, desc, 1);
513 if (ret) {
514 dev_err(&hdev->pdev->dev,
515 "Query tqp stat fail, status = %d,queue = %d\n",
516 ret, i);
517 return ret;
518 }
519 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
520 cpu_to_le32(desc[0].data[4]);
521 }
522
523 for (i = 0; i < kinfo->num_tqps; i++) {
524 queue = handle->kinfo.tqp[i];
525 tqp = container_of(queue, struct hclge_tqp, q);
526 /* command : HCLGE_OPC_QUERY_IGU_STAT */
527 hclge_cmd_setup_basic_desc(&desc[0],
528 HCLGE_OPC_QUERY_TX_STATUS,
529 true);
530
531 desc[0].data[0] = (tqp->index & 0x1ff);
532 ret = hclge_cmd_send(&hdev->hw, desc, 1);
533 if (ret) {
534 dev_err(&hdev->pdev->dev,
535 "Query tqp stat fail, status = %d,queue = %d\n",
536 ret, i);
537 return ret;
538 }
539 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
540 cpu_to_le32(desc[0].data[4]);
541 }
542
543 return 0;
544}
545
546static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
547{
548 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
549 struct hclge_tqp *tqp;
550 u64 *buff = data;
551 int i;
552
553 for (i = 0; i < kinfo->num_tqps; i++) {
554 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
555 *buff++ = cpu_to_le64(tqp->tqp_stats.rcb_tx_ring_pktnum_rcd);
556 }
557
558 for (i = 0; i < kinfo->num_tqps; i++) {
559 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
560 *buff++ = cpu_to_le64(tqp->tqp_stats.rcb_rx_ring_pktnum_rcd);
561 }
562
563 return buff;
564}
565
566static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
567{
568 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
569
570 return kinfo->num_tqps * (2);
571}
572
573static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
574{
575 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
576 u8 *buff = data;
577 int i = 0;
578
579 for (i = 0; i < kinfo->num_tqps; i++) {
580 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
581 struct hclge_tqp, q);
582 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
583 tqp->index);
584 buff = buff + ETH_GSTRING_LEN;
585 }
586
587 for (i = 0; i < kinfo->num_tqps; i++) {
588 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
589 struct hclge_tqp, q);
590 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
591 tqp->index);
592 buff = buff + ETH_GSTRING_LEN;
593 }
594
595 return buff;
596}
597
598static u64 *hclge_comm_get_stats(void *comm_stats,
599 const struct hclge_comm_stats_str strs[],
600 int size, u64 *data)
601{
602 u64 *buf = data;
603 u32 i;
604
605 for (i = 0; i < size; i++)
606 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
607
608 return buf + size;
609}
610
611static u8 *hclge_comm_get_strings(u32 stringset,
612 const struct hclge_comm_stats_str strs[],
613 int size, u8 *data)
614{
615 char *buff = (char *)data;
616 u32 i;
617
618 if (stringset != ETH_SS_STATS)
619 return buff;
620
621 for (i = 0; i < size; i++) {
622 snprintf(buff, ETH_GSTRING_LEN,
623 strs[i].desc);
624 buff = buff + ETH_GSTRING_LEN;
625 }
626
627 return (u8 *)buff;
628}
629
630static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
631 struct net_device_stats *net_stats)
632{
633 net_stats->tx_dropped = 0;
634 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
635 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
636 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
637
638 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
639 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
640 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
641 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
642 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
643 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
644
645 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
646 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
647
648 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
649 net_stats->rx_length_errors =
650 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
651 net_stats->rx_length_errors +=
652 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
653 net_stats->rx_over_errors =
654 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
655}
656
657static void hclge_update_stats_for_all(struct hclge_dev *hdev)
658{
659 struct hnae3_handle *handle;
660 int status;
661
662 handle = &hdev->vport[0].nic;
663 if (handle->client) {
664 status = hclge_tqps_update_stats(handle);
665 if (status) {
666 dev_err(&hdev->pdev->dev,
667 "Update TQPS stats fail, status = %d.\n",
668 status);
669 }
670 }
671
672 status = hclge_mac_update_stats(hdev);
673 if (status)
674 dev_err(&hdev->pdev->dev,
675 "Update MAC stats fail, status = %d.\n", status);
676
677 status = hclge_32_bit_update_stats(hdev);
678 if (status)
679 dev_err(&hdev->pdev->dev,
680 "Update 32 bit stats fail, status = %d.\n",
681 status);
682
683 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
684}
685
686static void hclge_update_stats(struct hnae3_handle *handle,
687 struct net_device_stats *net_stats)
688{
689 struct hclge_vport *vport = hclge_get_vport(handle);
690 struct hclge_dev *hdev = vport->back;
691 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
692 int status;
693
694 status = hclge_mac_update_stats(hdev);
695 if (status)
696 dev_err(&hdev->pdev->dev,
697 "Update MAC stats fail, status = %d.\n",
698 status);
699
700 status = hclge_32_bit_update_stats(hdev);
701 if (status)
702 dev_err(&hdev->pdev->dev,
703 "Update 32 bit stats fail, status = %d.\n",
704 status);
705
706 status = hclge_64_bit_update_stats(hdev);
707 if (status)
708 dev_err(&hdev->pdev->dev,
709 "Update 64 bit stats fail, status = %d.\n",
710 status);
711
712 status = hclge_tqps_update_stats(handle);
713 if (status)
714 dev_err(&hdev->pdev->dev,
715 "Update TQPS stats fail, status = %d.\n",
716 status);
717
718 hclge_update_netstat(hw_stats, net_stats);
719}
720
721static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
722{
723#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
724
725 struct hclge_vport *vport = hclge_get_vport(handle);
726 struct hclge_dev *hdev = vport->back;
727 int count = 0;
728
729 /* Loopback test support rules:
730 * mac: only GE mode support
731 * serdes: all mac mode will support include GE/XGE/LGE/CGE
732 * phy: only support when phy device exist on board
733 */
734 if (stringset == ETH_SS_TEST) {
735 /* clear loopback bit flags at first */
736 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
737 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
738 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
739 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
740 count += 1;
741 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
742 } else {
743 count = -EOPNOTSUPP;
744 }
745 } else if (stringset == ETH_SS_STATS) {
746 count = ARRAY_SIZE(g_mac_stats_string) +
747 ARRAY_SIZE(g_all_32bit_stats_string) +
748 ARRAY_SIZE(g_all_64bit_stats_string) +
749 hclge_tqps_get_sset_count(handle, stringset);
750 }
751
752 return count;
753}
754
755static void hclge_get_strings(struct hnae3_handle *handle,
756 u32 stringset,
757 u8 *data)
758{
759 u8 *p = (char *)data;
760 int size;
761
762 if (stringset == ETH_SS_STATS) {
763 size = ARRAY_SIZE(g_mac_stats_string);
764 p = hclge_comm_get_strings(stringset,
765 g_mac_stats_string,
766 size,
767 p);
768 size = ARRAY_SIZE(g_all_32bit_stats_string);
769 p = hclge_comm_get_strings(stringset,
770 g_all_32bit_stats_string,
771 size,
772 p);
773 size = ARRAY_SIZE(g_all_64bit_stats_string);
774 p = hclge_comm_get_strings(stringset,
775 g_all_64bit_stats_string,
776 size,
777 p);
778 p = hclge_tqps_get_strings(handle, p);
779 } else if (stringset == ETH_SS_TEST) {
780 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
781 memcpy(p,
782 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
783 ETH_GSTRING_LEN);
784 p += ETH_GSTRING_LEN;
785 }
786 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
787 memcpy(p,
788 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
789 ETH_GSTRING_LEN);
790 p += ETH_GSTRING_LEN;
791 }
792 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
793 memcpy(p,
794 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
795 ETH_GSTRING_LEN);
796 p += ETH_GSTRING_LEN;
797 }
798 }
799}
800
801static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
802{
803 struct hclge_vport *vport = hclge_get_vport(handle);
804 struct hclge_dev *hdev = vport->back;
805 u64 *p;
806
807 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
808 g_mac_stats_string,
809 ARRAY_SIZE(g_mac_stats_string),
810 data);
811 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
812 g_all_32bit_stats_string,
813 ARRAY_SIZE(g_all_32bit_stats_string),
814 p);
815 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
816 g_all_64bit_stats_string,
817 ARRAY_SIZE(g_all_64bit_stats_string),
818 p);
819 p = hclge_tqps_get_stats(handle, p);
820}
821
822static int hclge_parse_func_status(struct hclge_dev *hdev,
823 struct hclge_func_status *status)
824{
825 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
826 return -EINVAL;
827
828 /* Set the pf to main pf */
829 if (status->pf_state & HCLGE_PF_STATE_MAIN)
830 hdev->flag |= HCLGE_FLAG_MAIN;
831 else
832 hdev->flag &= ~HCLGE_FLAG_MAIN;
833
834 hdev->num_req_vfs = status->vf_num / status->pf_num;
835 return 0;
836}
837
838static int hclge_query_function_status(struct hclge_dev *hdev)
839{
840 struct hclge_func_status *req;
841 struct hclge_desc desc;
842 int timeout = 0;
843 int ret;
844
845 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
846 req = (struct hclge_func_status *)desc.data;
847
848 do {
849 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
850 if (ret) {
851 dev_err(&hdev->pdev->dev,
852 "query function status failed %d.\n",
853 ret);
854
855 return ret;
856 }
857
858 /* Check pf reset is done */
859 if (req->pf_state)
860 break;
861 usleep_range(1000, 2000);
862 } while (timeout++ < 5);
863
864 ret = hclge_parse_func_status(hdev, req);
865
866 return ret;
867}
868
869static int hclge_query_pf_resource(struct hclge_dev *hdev)
870{
871 struct hclge_pf_res *req;
872 struct hclge_desc desc;
873 int ret;
874
875 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
876 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
877 if (ret) {
878 dev_err(&hdev->pdev->dev,
879 "query pf resource failed %d.\n", ret);
880 return ret;
881 }
882
883 req = (struct hclge_pf_res *)desc.data;
884 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
885 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
886
e92a0843 887 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 888 hdev->num_roce_msix =
889 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
890 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
891
892 /* PF should have NIC vectors and Roce vectors,
893 * NIC vectors are queued before Roce vectors.
894 */
895 hdev->num_msi = hdev->num_roce_msix + HCLGE_ROCE_VECTOR_OFFSET;
896 } else {
897 hdev->num_msi =
898 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
899 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
900 }
901
902 return 0;
903}
904
905static int hclge_parse_speed(int speed_cmd, int *speed)
906{
907 switch (speed_cmd) {
908 case 6:
909 *speed = HCLGE_MAC_SPEED_10M;
910 break;
911 case 7:
912 *speed = HCLGE_MAC_SPEED_100M;
913 break;
914 case 0:
915 *speed = HCLGE_MAC_SPEED_1G;
916 break;
917 case 1:
918 *speed = HCLGE_MAC_SPEED_10G;
919 break;
920 case 2:
921 *speed = HCLGE_MAC_SPEED_25G;
922 break;
923 case 3:
924 *speed = HCLGE_MAC_SPEED_40G;
925 break;
926 case 4:
927 *speed = HCLGE_MAC_SPEED_50G;
928 break;
929 case 5:
930 *speed = HCLGE_MAC_SPEED_100G;
931 break;
932 default:
933 return -EINVAL;
934 }
935
936 return 0;
937}
938
939static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
940{
941 struct hclge_cfg_param *req;
942 u64 mac_addr_tmp_high;
943 u64 mac_addr_tmp;
944 int i;
945
946 req = (struct hclge_cfg_param *)desc[0].data;
947
948 /* get the configuration */
949 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
950 HCLGE_CFG_VMDQ_M,
951 HCLGE_CFG_VMDQ_S);
952 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
953 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
954 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
955 HCLGE_CFG_TQP_DESC_N_M,
956 HCLGE_CFG_TQP_DESC_N_S);
957
958 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
959 HCLGE_CFG_PHY_ADDR_M,
960 HCLGE_CFG_PHY_ADDR_S);
961 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
962 HCLGE_CFG_MEDIA_TP_M,
963 HCLGE_CFG_MEDIA_TP_S);
964 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
965 HCLGE_CFG_RX_BUF_LEN_M,
966 HCLGE_CFG_RX_BUF_LEN_S);
967 /* get mac_address */
968 mac_addr_tmp = __le32_to_cpu(req->param[2]);
969 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
970 HCLGE_CFG_MAC_ADDR_H_M,
971 HCLGE_CFG_MAC_ADDR_H_S);
972
973 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
974
975 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
976 HCLGE_CFG_DEFAULT_SPEED_M,
977 HCLGE_CFG_DEFAULT_SPEED_S);
978 for (i = 0; i < ETH_ALEN; i++)
979 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
980
981 req = (struct hclge_cfg_param *)desc[1].data;
982 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
983}
984
985/* hclge_get_cfg: query the static parameter from flash
986 * @hdev: pointer to struct hclge_dev
987 * @hcfg: the config structure to be getted
988 */
989static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
990{
991 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
992 struct hclge_cfg_param *req;
993 int i, ret;
994
995 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
996 req = (struct hclge_cfg_param *)desc[i].data;
997 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
998 true);
999 hnae_set_field(req->offset, HCLGE_CFG_OFFSET_M,
1000 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1001 /* Len should be united by 4 bytes when send to hardware */
1002 hnae_set_field(req->offset, HCLGE_CFG_RD_LEN_M,
1003 HCLGE_CFG_RD_LEN_S,
1004 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
1005 req->offset = cpu_to_le32(req->offset);
1006 }
1007
1008 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1009 if (ret) {
1010 dev_err(&hdev->pdev->dev,
1011 "get config failed %d.\n", ret);
1012 return ret;
1013 }
1014
1015 hclge_parse_cfg(hcfg, desc);
1016 return 0;
1017}
1018
1019static int hclge_get_cap(struct hclge_dev *hdev)
1020{
1021 int ret;
1022
1023 ret = hclge_query_function_status(hdev);
1024 if (ret) {
1025 dev_err(&hdev->pdev->dev,
1026 "query function status error %d.\n", ret);
1027 return ret;
1028 }
1029
1030 /* get pf resource */
1031 ret = hclge_query_pf_resource(hdev);
1032 if (ret) {
1033 dev_err(&hdev->pdev->dev,
1034 "query pf resource error %d.\n", ret);
1035 return ret;
1036 }
1037
1038 return 0;
1039}
1040
1041static int hclge_configure(struct hclge_dev *hdev)
1042{
1043 struct hclge_cfg cfg;
1044 int ret, i;
1045
1046 ret = hclge_get_cfg(hdev, &cfg);
1047 if (ret) {
1048 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1049 return ret;
1050 }
1051
1052 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1053 hdev->base_tqp_pid = 0;
1054 hdev->rss_size_max = 1;
1055 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1056 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1057 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1058 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1059 hdev->num_desc = cfg.tqp_desc_num;
1060 hdev->tm_info.num_pg = 1;
1061 hdev->tm_info.num_tc = cfg.tc_num;
1062 hdev->tm_info.hw_pfc_map = 0;
1063
1064 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1065 if (ret) {
1066 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1067 return ret;
1068 }
1069
1070 if ((hdev->tm_info.num_tc > HNAE3_MAX_TC) ||
1071 (hdev->tm_info.num_tc < 1)) {
1072 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
1073 hdev->tm_info.num_tc);
1074 hdev->tm_info.num_tc = 1;
1075 }
1076
1077 /* Currently not support uncontiuous tc */
1078 for (i = 0; i < cfg.tc_num; i++)
1079 hnae_set_bit(hdev->hw_tc_map, i, 1);
1080
1081 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1082 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1083 else
1084 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1085
1086 return ret;
1087}
1088
1089static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1090 int tso_mss_max)
1091{
1092 struct hclge_cfg_tso_status *req;
1093 struct hclge_desc desc;
1094
1095 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1096
1097 req = (struct hclge_cfg_tso_status *)desc.data;
1098 hnae_set_field(req->tso_mss_min, HCLGE_TSO_MSS_MIN_M,
1099 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
1100 hnae_set_field(req->tso_mss_max, HCLGE_TSO_MSS_MIN_M,
1101 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
1102
1103 return hclge_cmd_send(&hdev->hw, &desc, 1);
1104}
1105
1106static int hclge_alloc_tqps(struct hclge_dev *hdev)
1107{
1108 struct hclge_tqp *tqp;
1109 int i;
1110
1111 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1112 sizeof(struct hclge_tqp), GFP_KERNEL);
1113 if (!hdev->htqp)
1114 return -ENOMEM;
1115
1116 tqp = hdev->htqp;
1117
1118 for (i = 0; i < hdev->num_tqps; i++) {
1119 tqp->dev = &hdev->pdev->dev;
1120 tqp->index = i;
1121
1122 tqp->q.ae_algo = &ae_algo;
1123 tqp->q.buf_size = hdev->rx_buf_len;
1124 tqp->q.desc_num = hdev->num_desc;
1125 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1126 i * HCLGE_TQP_REG_SIZE;
1127
1128 tqp++;
1129 }
1130
1131 return 0;
1132}
1133
1134static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1135 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1136{
1137 struct hclge_tqp_map *req;
1138 struct hclge_desc desc;
1139 int ret;
1140
1141 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1142
1143 req = (struct hclge_tqp_map *)desc.data;
1144 req->tqp_id = cpu_to_le16(tqp_pid);
1145 req->tqp_vf = cpu_to_le16(func_id);
1146 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1147 1 << HCLGE_TQP_MAP_EN_B;
1148 req->tqp_vid = cpu_to_le16(tqp_vid);
1149
1150 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1151 if (ret) {
1152 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1153 ret);
1154 return ret;
1155 }
1156
1157 return 0;
1158}
1159
1160static int hclge_assign_tqp(struct hclge_vport *vport,
1161 struct hnae3_queue **tqp, u16 num_tqps)
1162{
1163 struct hclge_dev *hdev = vport->back;
1164 int i, alloced, func_id, ret;
1165 bool is_pf;
1166
1167 func_id = vport->vport_id;
1168 is_pf = (vport->vport_id == 0) ? true : false;
1169
1170 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1171 alloced < num_tqps; i++) {
1172 if (!hdev->htqp[i].alloced) {
1173 hdev->htqp[i].q.handle = &vport->nic;
1174 hdev->htqp[i].q.tqp_index = alloced;
1175 tqp[alloced] = &hdev->htqp[i].q;
1176 hdev->htqp[i].alloced = true;
1177 ret = hclge_map_tqps_to_func(hdev, func_id,
1178 hdev->htqp[i].index,
1179 alloced, is_pf);
1180 if (ret)
1181 return ret;
1182
1183 alloced++;
1184 }
1185 }
1186 vport->alloc_tqps = num_tqps;
1187
1188 return 0;
1189}
1190
1191static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1192{
1193 struct hnae3_handle *nic = &vport->nic;
1194 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1195 struct hclge_dev *hdev = vport->back;
1196 int i, ret;
1197
1198 kinfo->num_desc = hdev->num_desc;
1199 kinfo->rx_buf_len = hdev->rx_buf_len;
1200 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1201 kinfo->rss_size
1202 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1203 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1204
1205 for (i = 0; i < HNAE3_MAX_TC; i++) {
1206 if (hdev->hw_tc_map & BIT(i)) {
1207 kinfo->tc_info[i].enable = true;
1208 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1209 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1210 kinfo->tc_info[i].tc = i;
1211 } else {
1212 /* Set to default queue if TC is disable */
1213 kinfo->tc_info[i].enable = false;
1214 kinfo->tc_info[i].tqp_offset = 0;
1215 kinfo->tc_info[i].tqp_count = 1;
1216 kinfo->tc_info[i].tc = 0;
1217 }
1218 }
1219
1220 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1221 sizeof(struct hnae3_queue *), GFP_KERNEL);
1222 if (!kinfo->tqp)
1223 return -ENOMEM;
1224
1225 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1226 if (ret) {
1227 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1228 return -EINVAL;
1229 }
1230
1231 return 0;
1232}
1233
1234static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1235{
1236 /* this would be initialized later */
1237}
1238
1239static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1240{
1241 struct hnae3_handle *nic = &vport->nic;
1242 struct hclge_dev *hdev = vport->back;
1243 int ret;
1244
1245 nic->pdev = hdev->pdev;
1246 nic->ae_algo = &ae_algo;
1247 nic->numa_node_mask = hdev->numa_node_mask;
1248
1249 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1250 ret = hclge_knic_setup(vport, num_tqps);
1251 if (ret) {
1252 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1253 ret);
1254 return ret;
1255 }
1256 } else {
1257 hclge_unic_setup(vport, num_tqps);
1258 }
1259
1260 return 0;
1261}
1262
1263static int hclge_alloc_vport(struct hclge_dev *hdev)
1264{
1265 struct pci_dev *pdev = hdev->pdev;
1266 struct hclge_vport *vport;
1267 u32 tqp_main_vport;
1268 u32 tqp_per_vport;
1269 int num_vport, i;
1270 int ret;
1271
1272 /* We need to alloc a vport for main NIC of PF */
1273 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1274
1275 if (hdev->num_tqps < num_vport)
1276 num_vport = hdev->num_tqps;
1277
1278 /* Alloc the same number of TQPs for every vport */
1279 tqp_per_vport = hdev->num_tqps / num_vport;
1280 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1281
1282 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1283 GFP_KERNEL);
1284 if (!vport)
1285 return -ENOMEM;
1286
1287 hdev->vport = vport;
1288 hdev->num_alloc_vport = num_vport;
1289
1290#ifdef CONFIG_PCI_IOV
1291 /* Enable SRIOV */
1292 if (hdev->num_req_vfs) {
1293 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1294 hdev->num_req_vfs);
1295 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1296 if (ret) {
1297 hdev->num_alloc_vfs = 0;
1298 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1299 ret);
1300 return ret;
1301 }
1302 }
1303 hdev->num_alloc_vfs = hdev->num_req_vfs;
1304#endif
1305
1306 for (i = 0; i < num_vport; i++) {
1307 vport->back = hdev;
1308 vport->vport_id = i;
1309
1310 if (i == 0)
1311 ret = hclge_vport_setup(vport, tqp_main_vport);
1312 else
1313 ret = hclge_vport_setup(vport, tqp_per_vport);
1314 if (ret) {
1315 dev_err(&pdev->dev,
1316 "vport setup failed for vport %d, %d\n",
1317 i, ret);
1318 return ret;
1319 }
1320
1321 vport++;
1322 }
1323
1324 return 0;
1325}
1326
1327static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, u16 buf_size)
1328{
1329/* TX buffer size is unit by 128 byte */
1330#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1331#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
1332 struct hclge_tx_buff_alloc *req;
1333 struct hclge_desc desc;
1334 int ret;
1335 u8 i;
1336
1337 req = (struct hclge_tx_buff_alloc *)desc.data;
1338
1339 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
1340 for (i = 0; i < HCLGE_TC_NUM; i++)
1341 req->tx_pkt_buff[i] =
1342 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1343 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
1344
1345 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1346 if (ret) {
1347 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1348 ret);
1349 return ret;
1350 }
1351
1352 return 0;
1353}
1354
1355static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, u32 buf_size)
1356{
1357 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_size);
1358
1359 if (ret) {
1360 dev_err(&hdev->pdev->dev,
1361 "tx buffer alloc failed %d\n", ret);
1362 return ret;
1363 }
1364
1365 return 0;
1366}
1367
1368static int hclge_get_tc_num(struct hclge_dev *hdev)
1369{
1370 int i, cnt = 0;
1371
1372 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1373 if (hdev->hw_tc_map & BIT(i))
1374 cnt++;
1375 return cnt;
1376}
1377
1378static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1379{
1380 int i, cnt = 0;
1381
1382 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1383 if (hdev->hw_tc_map & BIT(i) &&
1384 hdev->tm_info.hw_pfc_map & BIT(i))
1385 cnt++;
1386 return cnt;
1387}
1388
1389/* Get the number of pfc enabled TCs, which have private buffer */
1390static int hclge_get_pfc_priv_num(struct hclge_dev *hdev)
1391{
1392 struct hclge_priv_buf *priv;
1393 int i, cnt = 0;
1394
1395 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1396 priv = &hdev->priv_buf[i];
1397 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1398 priv->enable)
1399 cnt++;
1400 }
1401
1402 return cnt;
1403}
1404
1405/* Get the number of pfc disabled TCs, which have private buffer */
1406static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev)
1407{
1408 struct hclge_priv_buf *priv;
1409 int i, cnt = 0;
1410
1411 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1412 priv = &hdev->priv_buf[i];
1413 if (hdev->hw_tc_map & BIT(i) &&
1414 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1415 priv->enable)
1416 cnt++;
1417 }
1418
1419 return cnt;
1420}
1421
1422static u32 hclge_get_rx_priv_buff_alloced(struct hclge_dev *hdev)
1423{
1424 struct hclge_priv_buf *priv;
1425 u32 rx_priv = 0;
1426 int i;
1427
1428 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1429 priv = &hdev->priv_buf[i];
1430 if (priv->enable)
1431 rx_priv += priv->buf_size;
1432 }
1433 return rx_priv;
1434}
1435
1436static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, u32 rx_all)
1437{
1438 u32 shared_buf_min, shared_buf_tc, shared_std;
1439 int tc_num, pfc_enable_num;
1440 u32 shared_buf;
1441 u32 rx_priv;
1442 int i;
1443
1444 tc_num = hclge_get_tc_num(hdev);
1445 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1446
1447 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1448 shared_buf_tc = pfc_enable_num * hdev->mps +
1449 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1450 hdev->mps;
1451 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1452
1453 rx_priv = hclge_get_rx_priv_buff_alloced(hdev);
1454 if (rx_all <= rx_priv + shared_std)
1455 return false;
1456
1457 shared_buf = rx_all - rx_priv;
1458 hdev->s_buf.buf_size = shared_buf;
1459 hdev->s_buf.self.high = shared_buf;
1460 hdev->s_buf.self.low = 2 * hdev->mps;
1461
1462 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1463 if ((hdev->hw_tc_map & BIT(i)) &&
1464 (hdev->tm_info.hw_pfc_map & BIT(i))) {
1465 hdev->s_buf.tc_thrd[i].low = hdev->mps;
1466 hdev->s_buf.tc_thrd[i].high = 2 * hdev->mps;
1467 } else {
1468 hdev->s_buf.tc_thrd[i].low = 0;
1469 hdev->s_buf.tc_thrd[i].high = hdev->mps;
1470 }
1471 }
1472
1473 return true;
1474}
1475
1476/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1477 * @hdev: pointer to struct hclge_dev
1478 * @tx_size: the allocated tx buffer for all TCs
1479 * @return: 0: calculate sucessful, negative: fail
1480 */
1481int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size)
1482{
1483 u32 rx_all = hdev->pkt_buf_size - tx_size;
1484 int no_pfc_priv_num, pfc_priv_num;
1485 struct hclge_priv_buf *priv;
1486 int i;
1487
1488 /* step 1, try to alloc private buffer for all enabled tc */
1489 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1490 priv = &hdev->priv_buf[i];
1491 if (hdev->hw_tc_map & BIT(i)) {
1492 priv->enable = 1;
1493 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1494 priv->wl.low = hdev->mps;
1495 priv->wl.high = priv->wl.low + hdev->mps;
1496 priv->buf_size = priv->wl.high +
1497 HCLGE_DEFAULT_DV;
1498 } else {
1499 priv->wl.low = 0;
1500 priv->wl.high = 2 * hdev->mps;
1501 priv->buf_size = priv->wl.high;
1502 }
1503 }
1504 }
1505
1506 if (hclge_is_rx_buf_ok(hdev, rx_all))
1507 return 0;
1508
1509 /* step 2, try to decrease the buffer size of
1510 * no pfc TC's private buffer
1511 */
1512 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1513 priv = &hdev->priv_buf[i];
1514
1515 if (hdev->hw_tc_map & BIT(i))
1516 priv->enable = 1;
1517
1518 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1519 priv->wl.low = 128;
1520 priv->wl.high = priv->wl.low + hdev->mps;
1521 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1522 } else {
1523 priv->wl.low = 0;
1524 priv->wl.high = hdev->mps;
1525 priv->buf_size = priv->wl.high;
1526 }
1527 }
1528
1529 if (hclge_is_rx_buf_ok(hdev, rx_all))
1530 return 0;
1531
1532 /* step 3, try to reduce the number of pfc disabled TCs,
1533 * which have private buffer
1534 */
1535 /* get the total no pfc enable TC number, which have private buffer */
1536 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev);
1537
1538 /* let the last to be cleared first */
1539 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1540 priv = &hdev->priv_buf[i];
1541
1542 if (hdev->hw_tc_map & BIT(i) &&
1543 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1544 /* Clear the no pfc TC private buffer */
1545 priv->wl.low = 0;
1546 priv->wl.high = 0;
1547 priv->buf_size = 0;
1548 priv->enable = 0;
1549 no_pfc_priv_num--;
1550 }
1551
1552 if (hclge_is_rx_buf_ok(hdev, rx_all) ||
1553 no_pfc_priv_num == 0)
1554 break;
1555 }
1556
1557 if (hclge_is_rx_buf_ok(hdev, rx_all))
1558 return 0;
1559
1560 /* step 4, try to reduce the number of pfc enabled TCs
1561 * which have private buffer.
1562 */
1563 pfc_priv_num = hclge_get_pfc_priv_num(hdev);
1564
1565 /* let the last to be cleared first */
1566 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
1567 priv = &hdev->priv_buf[i];
1568
1569 if (hdev->hw_tc_map & BIT(i) &&
1570 hdev->tm_info.hw_pfc_map & BIT(i)) {
1571 /* Reduce the number of pfc TC with private buffer */
1572 priv->wl.low = 0;
1573 priv->enable = 0;
1574 priv->wl.high = 0;
1575 priv->buf_size = 0;
1576 pfc_priv_num--;
1577 }
1578
1579 if (hclge_is_rx_buf_ok(hdev, rx_all) ||
1580 pfc_priv_num == 0)
1581 break;
1582 }
1583 if (hclge_is_rx_buf_ok(hdev, rx_all))
1584 return 0;
1585
1586 return -ENOMEM;
1587}
1588
1589static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev)
1590{
1591 struct hclge_rx_priv_buff *req;
1592 struct hclge_desc desc;
1593 int ret;
1594 int i;
1595
1596 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
1597 req = (struct hclge_rx_priv_buff *)desc.data;
1598
1599 /* Alloc private buffer TCs */
1600 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1601 struct hclge_priv_buf *priv = &hdev->priv_buf[i];
1602
1603 req->buf_num[i] =
1604 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1605 req->buf_num[i] |=
1606 cpu_to_le16(true << HCLGE_TC0_PRI_BUF_EN_B);
1607 }
1608
1609 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1610 if (ret) {
1611 dev_err(&hdev->pdev->dev,
1612 "rx private buffer alloc cmd failed %d\n", ret);
1613 return ret;
1614 }
1615
1616 return 0;
1617}
1618
1619#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1620
1621static int hclge_rx_priv_wl_config(struct hclge_dev *hdev)
1622{
1623 struct hclge_rx_priv_wl_buf *req;
1624 struct hclge_priv_buf *priv;
1625 struct hclge_desc desc[2];
1626 int i, j;
1627 int ret;
1628
1629 for (i = 0; i < 2; i++) {
1630 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1631 false);
1632 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1633
1634 /* The first descriptor set the NEXT bit to 1 */
1635 if (i == 0)
1636 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1637 else
1638 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1639
1640 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1641 priv = &hdev->priv_buf[i * HCLGE_TC_NUM_ONE_DESC + j];
1642 req->tc_wl[j].high =
1643 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1644 req->tc_wl[j].high |=
1645 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1646 HCLGE_RX_PRIV_EN_B);
1647 req->tc_wl[j].low =
1648 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1649 req->tc_wl[j].low |=
1650 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1651 HCLGE_RX_PRIV_EN_B);
1652 }
1653 }
1654
1655 /* Send 2 descriptor at one time */
1656 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1657 if (ret) {
1658 dev_err(&hdev->pdev->dev,
1659 "rx private waterline config cmd failed %d\n",
1660 ret);
1661 return ret;
1662 }
1663 return 0;
1664}
1665
1666static int hclge_common_thrd_config(struct hclge_dev *hdev)
1667{
1668 struct hclge_shared_buf *s_buf = &hdev->s_buf;
1669 struct hclge_rx_com_thrd *req;
1670 struct hclge_desc desc[2];
1671 struct hclge_tc_thrd *tc;
1672 int i, j;
1673 int ret;
1674
1675 for (i = 0; i < 2; i++) {
1676 hclge_cmd_setup_basic_desc(&desc[i],
1677 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1678 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1679
1680 /* The first descriptor set the NEXT bit to 1 */
1681 if (i == 0)
1682 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1683 else
1684 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1685
1686 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1687 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1688
1689 req->com_thrd[j].high =
1690 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1691 req->com_thrd[j].high |=
1692 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1693 HCLGE_RX_PRIV_EN_B);
1694 req->com_thrd[j].low =
1695 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1696 req->com_thrd[j].low |=
1697 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1698 HCLGE_RX_PRIV_EN_B);
1699 }
1700 }
1701
1702 /* Send 2 descriptors at one time */
1703 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1704 if (ret) {
1705 dev_err(&hdev->pdev->dev,
1706 "common threshold config cmd failed %d\n", ret);
1707 return ret;
1708 }
1709 return 0;
1710}
1711
1712static int hclge_common_wl_config(struct hclge_dev *hdev)
1713{
1714 struct hclge_shared_buf *buf = &hdev->s_buf;
1715 struct hclge_rx_com_wl *req;
1716 struct hclge_desc desc;
1717 int ret;
1718
1719 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1720
1721 req = (struct hclge_rx_com_wl *)desc.data;
1722 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1723 req->com_wl.high |=
1724 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1725 HCLGE_RX_PRIV_EN_B);
1726
1727 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1728 req->com_wl.low |=
1729 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1730 HCLGE_RX_PRIV_EN_B);
1731
1732 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1733 if (ret) {
1734 dev_err(&hdev->pdev->dev,
1735 "common waterline config cmd failed %d\n", ret);
1736 return ret;
1737 }
1738
1739 return 0;
1740}
1741
1742int hclge_buffer_alloc(struct hclge_dev *hdev)
1743{
1744 u32 tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1745 int ret;
1746
1747 hdev->priv_buf = devm_kmalloc_array(&hdev->pdev->dev, HCLGE_MAX_TC_NUM,
1748 sizeof(struct hclge_priv_buf),
1749 GFP_KERNEL | __GFP_ZERO);
1750 if (!hdev->priv_buf)
1751 return -ENOMEM;
1752
1753 ret = hclge_tx_buffer_alloc(hdev, tx_buf_size);
1754 if (ret) {
1755 dev_err(&hdev->pdev->dev,
1756 "could not alloc tx buffers %d\n", ret);
1757 return ret;
1758 }
1759
1760 ret = hclge_rx_buffer_calc(hdev, tx_buf_size);
1761 if (ret) {
1762 dev_err(&hdev->pdev->dev,
1763 "could not calc rx priv buffer size for all TCs %d\n",
1764 ret);
1765 return ret;
1766 }
1767
1768 ret = hclge_rx_priv_buf_alloc(hdev);
1769 if (ret) {
1770 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1771 ret);
1772 return ret;
1773 }
1774
1775 ret = hclge_rx_priv_wl_config(hdev);
1776 if (ret) {
1777 dev_err(&hdev->pdev->dev,
1778 "could not configure rx private waterline %d\n", ret);
1779 return ret;
1780 }
1781
1782 ret = hclge_common_thrd_config(hdev);
1783 if (ret) {
1784 dev_err(&hdev->pdev->dev,
1785 "could not configure common threshold %d\n", ret);
1786 return ret;
1787 }
1788
1789 ret = hclge_common_wl_config(hdev);
1790 if (ret) {
1791 dev_err(&hdev->pdev->dev,
1792 "could not configure common waterline %d\n", ret);
1793 return ret;
1794 }
1795
1796 return 0;
1797}
1798
1799static int hclge_init_roce_base_info(struct hclge_vport *vport)
1800{
1801 struct hnae3_handle *roce = &vport->roce;
1802 struct hnae3_handle *nic = &vport->nic;
1803
1804 roce->rinfo.num_vectors = vport->back->num_roce_msix;
1805
1806 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1807 vport->back->num_msi_left == 0)
1808 return -EINVAL;
1809
1810 roce->rinfo.base_vector = vport->back->roce_base_vector;
1811
1812 roce->rinfo.netdev = nic->kinfo.netdev;
1813 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1814
1815 roce->pdev = nic->pdev;
1816 roce->ae_algo = nic->ae_algo;
1817 roce->numa_node_mask = nic->numa_node_mask;
1818
1819 return 0;
1820}
1821
1822static int hclge_init_msix(struct hclge_dev *hdev)
1823{
1824 struct pci_dev *pdev = hdev->pdev;
1825 int ret, i;
1826
1827 hdev->msix_entries = devm_kcalloc(&pdev->dev, hdev->num_msi,
1828 sizeof(struct msix_entry),
1829 GFP_KERNEL);
1830 if (!hdev->msix_entries)
1831 return -ENOMEM;
1832
1833 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1834 sizeof(u16), GFP_KERNEL);
1835 if (!hdev->vector_status)
1836 return -ENOMEM;
1837
1838 for (i = 0; i < hdev->num_msi; i++) {
1839 hdev->msix_entries[i].entry = i;
1840 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1841 }
1842
1843 hdev->num_msi_left = hdev->num_msi;
1844 hdev->base_msi_vector = hdev->pdev->irq;
1845 hdev->roce_base_vector = hdev->base_msi_vector +
1846 HCLGE_ROCE_VECTOR_OFFSET;
1847
1848 ret = pci_enable_msix_range(hdev->pdev, hdev->msix_entries,
1849 hdev->num_msi, hdev->num_msi);
1850 if (ret < 0) {
1851 dev_info(&hdev->pdev->dev,
1852 "MSI-X vector alloc failed: %d\n", ret);
1853 return ret;
1854 }
1855
1856 return 0;
1857}
1858
1859static int hclge_init_msi(struct hclge_dev *hdev)
1860{
1861 struct pci_dev *pdev = hdev->pdev;
1862 int vectors;
1863 int i;
1864
1865 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1866 sizeof(u16), GFP_KERNEL);
1867 if (!hdev->vector_status)
1868 return -ENOMEM;
1869
1870 for (i = 0; i < hdev->num_msi; i++)
1871 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1872
1873 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, PCI_IRQ_MSI);
1874 if (vectors < 0) {
1875 dev_err(&pdev->dev, "MSI vectors enable failed %d\n", vectors);
1876 return -EINVAL;
1877 }
1878 hdev->num_msi = vectors;
1879 hdev->num_msi_left = vectors;
1880 hdev->base_msi_vector = pdev->irq;
1881 hdev->roce_base_vector = hdev->base_msi_vector +
1882 HCLGE_ROCE_VECTOR_OFFSET;
1883
1884 return 0;
1885}
1886
1887static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
1888{
1889 struct hclge_mac *mac = &hdev->hw.mac;
1890
1891 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
1892 mac->duplex = (u8)duplex;
1893 else
1894 mac->duplex = HCLGE_MAC_FULL;
1895
1896 mac->speed = speed;
1897}
1898
1899int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1900{
1901 struct hclge_config_mac_speed_dup *req;
1902 struct hclge_desc desc;
1903 int ret;
1904
1905 req = (struct hclge_config_mac_speed_dup *)desc.data;
1906
1907 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1908
1909 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
1910
1911 switch (speed) {
1912 case HCLGE_MAC_SPEED_10M:
1913 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1914 HCLGE_CFG_SPEED_S, 6);
1915 break;
1916 case HCLGE_MAC_SPEED_100M:
1917 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1918 HCLGE_CFG_SPEED_S, 7);
1919 break;
1920 case HCLGE_MAC_SPEED_1G:
1921 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1922 HCLGE_CFG_SPEED_S, 0);
1923 break;
1924 case HCLGE_MAC_SPEED_10G:
1925 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1926 HCLGE_CFG_SPEED_S, 1);
1927 break;
1928 case HCLGE_MAC_SPEED_25G:
1929 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1930 HCLGE_CFG_SPEED_S, 2);
1931 break;
1932 case HCLGE_MAC_SPEED_40G:
1933 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1934 HCLGE_CFG_SPEED_S, 3);
1935 break;
1936 case HCLGE_MAC_SPEED_50G:
1937 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1938 HCLGE_CFG_SPEED_S, 4);
1939 break;
1940 case HCLGE_MAC_SPEED_100G:
1941 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1942 HCLGE_CFG_SPEED_S, 5);
1943 break;
1944 default:
d7629e74 1945 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 1946 return -EINVAL;
1947 }
1948
1949 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1950 1);
1951
1952 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1953 if (ret) {
1954 dev_err(&hdev->pdev->dev,
1955 "mac speed/duplex config cmd failed %d.\n", ret);
1956 return ret;
1957 }
1958
1959 hclge_check_speed_dup(hdev, duplex, speed);
1960
1961 return 0;
1962}
1963
1964static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1965 u8 duplex)
1966{
1967 struct hclge_vport *vport = hclge_get_vport(handle);
1968 struct hclge_dev *hdev = vport->back;
1969
1970 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1971}
1972
1973static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
1974 u8 *duplex)
1975{
1976 struct hclge_query_an_speed_dup *req;
1977 struct hclge_desc desc;
1978 int speed_tmp;
1979 int ret;
1980
1981 req = (struct hclge_query_an_speed_dup *)desc.data;
1982
1983 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
1984 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1985 if (ret) {
1986 dev_err(&hdev->pdev->dev,
1987 "mac speed/autoneg/duplex query cmd failed %d\n",
1988 ret);
1989 return ret;
1990 }
1991
1992 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
1993 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
1994 HCLGE_QUERY_SPEED_S);
1995
1996 ret = hclge_parse_speed(speed_tmp, speed);
1997 if (ret) {
1998 dev_err(&hdev->pdev->dev,
1999 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2000 return -EIO;
2001 }
2002
2003 return 0;
2004}
2005
2006static int hclge_query_autoneg_result(struct hclge_dev *hdev)
2007{
2008 struct hclge_mac *mac = &hdev->hw.mac;
2009 struct hclge_query_an_speed_dup *req;
2010 struct hclge_desc desc;
2011 int ret;
2012
2013 req = (struct hclge_query_an_speed_dup *)desc.data;
2014
2015 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2016 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2017 if (ret) {
2018 dev_err(&hdev->pdev->dev,
2019 "autoneg result query cmd failed %d.\n", ret);
2020 return ret;
2021 }
2022
2023 mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
2024
2025 return 0;
2026}
2027
2028static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2029{
2030 struct hclge_config_auto_neg *req;
2031 struct hclge_desc desc;
2032 int ret;
2033
2034 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2035
2036 req = (struct hclge_config_auto_neg *)desc.data;
2037 hnae_set_bit(req->cfg_an_cmd_flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2038
2039 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2040 if (ret) {
2041 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2042 ret);
2043 return ret;
2044 }
2045
2046 return 0;
2047}
2048
2049static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2050{
2051 struct hclge_vport *vport = hclge_get_vport(handle);
2052 struct hclge_dev *hdev = vport->back;
2053
2054 return hclge_set_autoneg_en(hdev, enable);
2055}
2056
2057static int hclge_get_autoneg(struct hnae3_handle *handle)
2058{
2059 struct hclge_vport *vport = hclge_get_vport(handle);
2060 struct hclge_dev *hdev = vport->back;
2061
2062 hclge_query_autoneg_result(hdev);
2063
2064 return hdev->hw.mac.autoneg;
2065}
2066
2067static int hclge_mac_init(struct hclge_dev *hdev)
2068{
2069 struct hclge_mac *mac = &hdev->hw.mac;
2070 int ret;
2071
2072 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2073 if (ret) {
2074 dev_err(&hdev->pdev->dev,
2075 "Config mac speed dup fail ret=%d\n", ret);
2076 return ret;
2077 }
2078
2079 mac->link = 0;
2080
2081 ret = hclge_mac_mdio_config(hdev);
2082 if (ret) {
2083 dev_warn(&hdev->pdev->dev,
2084 "mdio config fail ret=%d\n", ret);
2085 return ret;
2086 }
2087
2088 /* Initialize the MTA table work mode */
2089 hdev->accept_mta_mc = true;
2090 hdev->enable_mta = true;
2091 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2092
2093 ret = hclge_set_mta_filter_mode(hdev,
2094 hdev->mta_mac_sel_type,
2095 hdev->enable_mta);
2096 if (ret) {
2097 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2098 ret);
2099 return ret;
2100 }
2101
2102 return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2103}
2104
2105static void hclge_task_schedule(struct hclge_dev *hdev)
2106{
2107 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2108 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2109 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2110 (void)schedule_work(&hdev->service_task);
2111}
2112
2113static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2114{
2115 struct hclge_link_status *req;
2116 struct hclge_desc desc;
2117 int link_status;
2118 int ret;
2119
2120 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2121 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2122 if (ret) {
2123 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2124 ret);
2125 return ret;
2126 }
2127
2128 req = (struct hclge_link_status *)desc.data;
2129 link_status = req->status & HCLGE_LINK_STATUS;
2130
2131 return !!link_status;
2132}
2133
2134static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2135{
2136 int mac_state;
2137 int link_stat;
2138
2139 mac_state = hclge_get_mac_link_status(hdev);
2140
2141 if (hdev->hw.mac.phydev) {
2142 if (!genphy_read_status(hdev->hw.mac.phydev))
2143 link_stat = mac_state &
2144 hdev->hw.mac.phydev->link;
2145 else
2146 link_stat = 0;
2147
2148 } else {
2149 link_stat = mac_state;
2150 }
2151
2152 return !!link_stat;
2153}
2154
2155static void hclge_update_link_status(struct hclge_dev *hdev)
2156{
2157 struct hnae3_client *client = hdev->nic_client;
2158 struct hnae3_handle *handle;
2159 int state;
2160 int i;
2161
2162 if (!client)
2163 return;
2164 state = hclge_get_mac_phy_link(hdev);
2165 if (state != hdev->hw.mac.link) {
2166 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2167 handle = &hdev->vport[i].nic;
2168 client->ops->link_status_change(handle, state);
2169 }
2170 hdev->hw.mac.link = state;
2171 }
2172}
2173
2174static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2175{
2176 struct hclge_mac mac = hdev->hw.mac;
2177 u8 duplex;
2178 int speed;
2179 int ret;
2180
2181 /* get the speed and duplex as autoneg'result from mac cmd when phy
2182 * doesn't exit.
2183 */
2184 if (mac.phydev)
2185 return 0;
2186
2187 /* update mac->antoneg. */
2188 ret = hclge_query_autoneg_result(hdev);
2189 if (ret) {
2190 dev_err(&hdev->pdev->dev,
2191 "autoneg result query failed %d\n", ret);
2192 return ret;
2193 }
2194
2195 if (!mac.autoneg)
2196 return 0;
2197
2198 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2199 if (ret) {
2200 dev_err(&hdev->pdev->dev,
2201 "mac autoneg/speed/duplex query failed %d\n", ret);
2202 return ret;
2203 }
2204
2205 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2206 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2207 if (ret) {
2208 dev_err(&hdev->pdev->dev,
2209 "mac speed/duplex config failed %d\n", ret);
2210 return ret;
2211 }
2212 }
2213
2214 return 0;
2215}
2216
2217static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2218{
2219 struct hclge_vport *vport = hclge_get_vport(handle);
2220 struct hclge_dev *hdev = vport->back;
2221
2222 return hclge_update_speed_duplex(hdev);
2223}
2224
2225static int hclge_get_status(struct hnae3_handle *handle)
2226{
2227 struct hclge_vport *vport = hclge_get_vport(handle);
2228 struct hclge_dev *hdev = vport->back;
2229
2230 hclge_update_link_status(hdev);
2231
2232 return hdev->hw.mac.link;
2233}
2234
2235static void hclge_service_timer(unsigned long data)
2236{
2237 struct hclge_dev *hdev = (struct hclge_dev *)data;
2238 (void)mod_timer(&hdev->service_timer, jiffies + HZ);
2239
2240 hclge_task_schedule(hdev);
2241}
2242
2243static void hclge_service_complete(struct hclge_dev *hdev)
2244{
2245 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2246
2247 /* Flush memory before next watchdog */
2248 smp_mb__before_atomic();
2249 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2250}
2251
2252static void hclge_service_task(struct work_struct *work)
2253{
2254 struct hclge_dev *hdev =
2255 container_of(work, struct hclge_dev, service_task);
2256
2257 hclge_update_speed_duplex(hdev);
2258 hclge_update_link_status(hdev);
2259 hclge_update_stats_for_all(hdev);
2260 hclge_service_complete(hdev);
2261}
2262
2263static void hclge_disable_sriov(struct hclge_dev *hdev)
2264{
2a32ca13
AB		 2265 /* If our VFs are assigned we cannot shut down SR-IOV
2266 * without causing issues, so just leave the hardware
2267 * available but disabled
2268 */
2269 if (pci_vfs_assigned(hdev->pdev)) {
2270 dev_warn(&hdev->pdev->dev,
2271 "disabling driver while VFs are assigned\n");
2272 return;
2273 }
46a3df9f 2274
2a32ca13 2275 pci_disable_sriov(hdev->pdev);
46a3df9f
S		 2276}
2277
2278struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2279{
2280 /* VF handle has no client */
2281 if (!handle->client)
2282 return container_of(handle, struct hclge_vport, nic);
2283 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2284 return container_of(handle, struct hclge_vport, roce);
2285 else
2286 return container_of(handle, struct hclge_vport, nic);
2287}
2288
2289static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2290 struct hnae3_vector_info *vector_info)
2291{
2292 struct hclge_vport *vport = hclge_get_vport(handle);
2293 struct hnae3_vector_info *vector = vector_info;
2294 struct hclge_dev *hdev = vport->back;
2295 int alloc = 0;
2296 int i, j;
2297
2298 vector_num = min(hdev->num_msi_left, vector_num);
2299
2300 for (j = 0; j < vector_num; j++) {
2301 for (i = 1; i < hdev->num_msi; i++) {
2302 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2303 vector->vector = pci_irq_vector(hdev->pdev, i);
2304 vector->io_addr = hdev->hw.io_base +
2305 HCLGE_VECTOR_REG_BASE +
2306 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2307 vport->vport_id *
2308 HCLGE_VECTOR_VF_OFFSET;
2309 hdev->vector_status[i] = vport->vport_id;
2310
2311 vector++;
2312 alloc++;
2313
2314 break;
2315 }
2316 }
2317 }
2318 hdev->num_msi_left -= alloc;
2319 hdev->num_msi_used += alloc;
2320
2321 return alloc;
2322}
2323
2324static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2325{
2326 int i;
2327
2328 for (i = 0; i < hdev->num_msi; i++) {
2329 if (hdev->msix_entries) {
2330 if (vector == hdev->msix_entries[i].vector)
2331 return i;
2332 } else {
2333 if (vector == (hdev->base_msi_vector + i))
2334 return i;
2335 }
2336 }
2337 return -EINVAL;
2338}
2339
2340static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2341{
2342 return HCLGE_RSS_KEY_SIZE;
2343}
2344
2345static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2346{
2347 return HCLGE_RSS_IND_TBL_SIZE;
2348}
2349
2350static int hclge_get_rss_algo(struct hclge_dev *hdev)
2351{
2352 struct hclge_rss_config *req;
2353 struct hclge_desc desc;
2354 int rss_hash_algo;
2355 int ret;
2356
2357 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2358
2359 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2360 if (ret) {
2361 dev_err(&hdev->pdev->dev,
2362 "Get link status error, status =%d\n", ret);
2363 return ret;
2364 }
2365
2366 req = (struct hclge_rss_config *)desc.data;
2367 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2368
2369 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2370 return ETH_RSS_HASH_TOP;
2371
2372 return -EINVAL;
2373}
2374
2375static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2376 const u8 hfunc, const u8 *key)
2377{
2378 struct hclge_rss_config *req;
2379 struct hclge_desc desc;
2380 int key_offset;
2381 int key_size;
2382 int ret;
2383
2384 req = (struct hclge_rss_config *)desc.data;
2385
2386 for (key_offset = 0; key_offset < 3; key_offset++) {
2387 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2388 false);
2389
2390 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2391 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2392
2393 if (key_offset == 2)
2394 key_size =
2395 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2396 else
2397 key_size = HCLGE_RSS_HASH_KEY_NUM;
2398
2399 memcpy(req->hash_key,
2400 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2401
2402 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2403 if (ret) {
2404 dev_err(&hdev->pdev->dev,
2405 "Configure RSS config fail, status = %d\n",
2406 ret);
2407 return ret;
2408 }
2409 }
2410 return 0;
2411}
2412
2413static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2414{
2415 struct hclge_rss_indirection_table *req;
2416 struct hclge_desc desc;
2417 int i, j;
2418 int ret;
2419
2420 req = (struct hclge_rss_indirection_table *)desc.data;
2421
2422 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2423 hclge_cmd_setup_basic_desc
2424 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2425
2426 req->start_table_index = i * HCLGE_RSS_CFG_TBL_SIZE;
2427 req->rss_set_bitmap = HCLGE_RSS_SET_BITMAP_MSK;
2428
2429 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2430 req->rss_result[j] =
2431 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2432
2433 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2434 if (ret) {
2435 dev_err(&hdev->pdev->dev,
2436 "Configure rss indir table fail,status = %d\n",
2437 ret);
2438 return ret;
2439 }
2440 }
2441 return 0;
2442}
2443
2444static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2445 u16 *tc_size, u16 *tc_offset)
2446{
2447 struct hclge_rss_tc_mode *req;
2448 struct hclge_desc desc;
2449 int ret;
2450 int i;
2451
2452 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
2453 req = (struct hclge_rss_tc_mode *)desc.data;
2454
2455 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2456 hnae_set_bit(req->rss_tc_mode[i], HCLGE_RSS_TC_VALID_B,
2457 (tc_valid[i] & 0x1));
2458 hnae_set_field(req->rss_tc_mode[i], HCLGE_RSS_TC_SIZE_M,
2459 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2460 hnae_set_field(req->rss_tc_mode[i], HCLGE_RSS_TC_OFFSET_M,
2461 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
2462 }
2463
2464 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2465 if (ret) {
2466 dev_err(&hdev->pdev->dev,
2467 "Configure rss tc mode fail, status = %d\n", ret);
2468 return ret;
2469 }
2470
2471 return 0;
2472}
2473
2474static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2475{
2476#define HCLGE_RSS_INPUT_TUPLE_OTHER 0xf
2477#define HCLGE_RSS_INPUT_TUPLE_SCTP 0x1f
2478 struct hclge_rss_input_tuple *req;
2479 struct hclge_desc desc;
2480 int ret;
2481
2482 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2483
2484 req = (struct hclge_rss_input_tuple *)desc.data;
2485 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2486 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2487 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2488 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2489 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2490 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2491 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2492 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2493 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2494 if (ret) {
2495 dev_err(&hdev->pdev->dev,
2496 "Configure rss input fail, status = %d\n", ret);
2497 return ret;
2498 }
2499
2500 return 0;
2501}
2502
2503static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2504 u8 *key, u8 *hfunc)
2505{
2506 struct hclge_vport *vport = hclge_get_vport(handle);
2507 struct hclge_dev *hdev = vport->back;
2508 int i;
2509
2510 /* Get hash algorithm */
2511 if (hfunc)
2512 *hfunc = hclge_get_rss_algo(hdev);
2513
2514 /* Get the RSS Key required by the user */
2515 if (key)
2516 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2517
2518 /* Get indirect table */
2519 if (indir)
2520 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2521 indir[i] = vport->rss_indirection_tbl[i];
2522
2523 return 0;
2524}
2525
2526static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2527 const u8 *key, const u8 hfunc)
2528{
2529 struct hclge_vport *vport = hclge_get_vport(handle);
2530 struct hclge_dev *hdev = vport->back;
2531 u8 hash_algo;
2532 int ret, i;
2533
2534 /* Set the RSS Hash Key if specififed by the user */
2535 if (key) {
2536 /* Update the shadow RSS key with user specified qids */
2537 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2538
2539 if (hfunc == ETH_RSS_HASH_TOP ||
2540 hfunc == ETH_RSS_HASH_NO_CHANGE)
2541 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2542 else
2543 return -EINVAL;
2544 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2545 if (ret)
2546 return ret;
2547 }
2548
2549 /* Update the shadow RSS table with user specified qids */
2550 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2551 vport->rss_indirection_tbl[i] = indir[i];
2552
2553 /* Update the hardware */
2554 ret = hclge_set_rss_indir_table(hdev, indir);
2555 return ret;
2556}
2557
2558static int hclge_get_tc_size(struct hnae3_handle *handle)
2559{
2560 struct hclge_vport *vport = hclge_get_vport(handle);
2561 struct hclge_dev *hdev = vport->back;
2562
2563 return hdev->rss_size_max;
2564}
2565
2566static int hclge_rss_init_hw(struct hclge_dev *hdev)
2567{
2568 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2569 struct hclge_vport *vport = hdev->vport;
2570 u16 tc_offset[HCLGE_MAX_TC_NUM];
2571 u8 rss_key[HCLGE_RSS_KEY_SIZE];
2572 u16 tc_valid[HCLGE_MAX_TC_NUM];
2573 u16 tc_size[HCLGE_MAX_TC_NUM];
2574 u32 *rss_indir = NULL;
2575 const u8 *key;
2576 int i, ret, j;
2577
2578 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
2579 if (!rss_indir)
2580 return -ENOMEM;
2581
2582 /* Get default RSS key */
2583 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
2584
2585 /* Initialize RSS indirect table for each vport */
2586 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
2587 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
2588 vport[j].rss_indirection_tbl[i] =
2589 i % hdev->rss_size_max;
2590 rss_indir[i] = vport[j].rss_indirection_tbl[i];
2591 }
2592 }
2593 ret = hclge_set_rss_indir_table(hdev, rss_indir);
2594 if (ret)
2595 goto err;
2596
2597 key = rss_key;
2598 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
2599 if (ret)
2600 goto err;
2601
2602 ret = hclge_set_rss_input_tuple(hdev);
2603 if (ret)
2604 goto err;
2605
2606 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
2607 if (hdev->hw_tc_map & BIT(i))
2608 tc_valid[i] = 1;
2609 else
2610 tc_valid[i] = 0;
2611
2612 switch (hdev->rss_size_max) {
2613 case HCLGE_RSS_TC_SIZE_0:
2614 tc_size[i] = 0;
2615 break;
2616 case HCLGE_RSS_TC_SIZE_1:
2617 tc_size[i] = 1;
2618 break;
2619 case HCLGE_RSS_TC_SIZE_2:
2620 tc_size[i] = 2;
2621 break;
2622 case HCLGE_RSS_TC_SIZE_3:
2623 tc_size[i] = 3;
2624 break;
2625 case HCLGE_RSS_TC_SIZE_4:
2626 tc_size[i] = 4;
2627 break;
2628 case HCLGE_RSS_TC_SIZE_5:
2629 tc_size[i] = 5;
2630 break;
2631 case HCLGE_RSS_TC_SIZE_6:
2632 tc_size[i] = 6;
2633 break;
2634 case HCLGE_RSS_TC_SIZE_7:
2635 tc_size[i] = 7;
2636 break;
2637 default:
2638 break;
2639 }
2640 tc_offset[i] = hdev->rss_size_max * i;
2641 }
2642 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
2643
2644err:
2645 kfree(rss_indir);
2646
2647 return ret;
2648}
2649
2650int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,
2651 struct hnae3_ring_chain_node *ring_chain)
2652{
2653 struct hclge_dev *hdev = vport->back;
2654 struct hclge_ctrl_vector_chain *req;
2655 struct hnae3_ring_chain_node *node;
2656 struct hclge_desc desc;
2657 int ret;
2658 int i;
2659
2660 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ADD_RING_TO_VECTOR, false);
2661
2662 req = (struct hclge_ctrl_vector_chain *)desc.data;
2663 req->int_vector_id = vector_id;
2664
2665 i = 0;
2666 for (node = ring_chain; node; node = node->next) {
2667 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_TYPE_M,
2668 HCLGE_INT_TYPE_S,
2669 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2670 hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,
2671 HCLGE_TQP_ID_S, node->tqp_index);
0305b443
L		 2672 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,
2673 HCLGE_INT_GL_IDX_S,
2674 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
46a3df9f 2675 req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);
0305b443 2676 req->vfid = vport->vport_id;
46a3df9f
S		 2677
2678 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
2679 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
2680
2681 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2682 if (ret) {
2683 dev_err(&hdev->pdev->dev,
2684 "Map TQP fail, status is %d.\n",
2685 ret);
2686 return ret;
2687 }
2688 i = 0;
2689
2690 hclge_cmd_setup_basic_desc(&desc,
2691 HCLGE_OPC_ADD_RING_TO_VECTOR,
2692 false);
2693 req->int_vector_id = vector_id;
2694 }
2695 }
2696
2697 if (i > 0) {
2698 req->int_cause_num = i;
2699
2700 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2701 if (ret) {
2702 dev_err(&hdev->pdev->dev,
2703 "Map TQP fail, status is %d.\n", ret);
2704 return ret;
2705 }
2706 }
2707
2708 return 0;
2709}
2710
2711int hclge_map_handle_ring_to_vector(struct hnae3_handle *handle,
2712 int vector,
2713 struct hnae3_ring_chain_node *ring_chain)
2714{
2715 struct hclge_vport *vport = hclge_get_vport(handle);
2716 struct hclge_dev *hdev = vport->back;
2717 int vector_id;
2718
2719 vector_id = hclge_get_vector_index(hdev, vector);
2720 if (vector_id < 0) {
2721 dev_err(&hdev->pdev->dev,
2722 "Get vector index fail. ret =%d\n", vector_id);
2723 return vector_id;
2724 }
2725
2726 return hclge_map_vport_ring_to_vector(vport, vector_id, ring_chain);
2727}
2728
2729static int hclge_unmap_ring_from_vector(
2730 struct hnae3_handle *handle, int vector,
2731 struct hnae3_ring_chain_node *ring_chain)
2732{
2733 struct hclge_vport *vport = hclge_get_vport(handle);
2734 struct hclge_dev *hdev = vport->back;
2735 struct hclge_ctrl_vector_chain *req;
2736 struct hnae3_ring_chain_node *node;
2737 struct hclge_desc desc;
2738 int i, vector_id;
2739 int ret;
2740
2741 vector_id = hclge_get_vector_index(hdev, vector);
2742 if (vector_id < 0) {
2743 dev_err(&handle->pdev->dev,
2744 "Get vector index fail. ret =%d\n", vector_id);
2745 return vector_id;
2746 }
2747
2748 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_DEL_RING_TO_VECTOR, false);
2749
2750 req = (struct hclge_ctrl_vector_chain *)desc.data;
2751 req->int_vector_id = vector_id;
2752
2753 i = 0;
2754 for (node = ring_chain; node; node = node->next) {
2755 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_TYPE_M,
2756 HCLGE_INT_TYPE_S,
2757 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
2758 hnae_set_field(req->tqp_type_and_id[i], HCLGE_TQP_ID_M,
2759 HCLGE_TQP_ID_S, node->tqp_index);
0305b443
L		 2760 hnae_set_field(req->tqp_type_and_id[i], HCLGE_INT_GL_IDX_M,
2761 HCLGE_INT_GL_IDX_S,
2762 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
46a3df9f
S		 2763
2764 req->tqp_type_and_id[i] = cpu_to_le16(req->tqp_type_and_id[i]);
0305b443 2765 req->vfid = vport->vport_id;
46a3df9f
S		 2766
2767 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
2768 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
2769
2770 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2771 if (ret) {
2772 dev_err(&hdev->pdev->dev,
2773 "Unmap TQP fail, status is %d.\n",
2774 ret);
2775 return ret;
2776 }
2777 i = 0;
2778 hclge_cmd_setup_basic_desc(&desc,
c5b1b975 2779 HCLGE_OPC_DEL_RING_TO_VECTOR,
46a3df9f
S		 2780 false);
2781 req->int_vector_id = vector_id;
2782 }
2783 }
2784
2785 if (i > 0) {
2786 req->int_cause_num = i;
2787
2788 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2789 if (ret) {
2790 dev_err(&hdev->pdev->dev,
2791 "Unmap TQP fail, status is %d.\n", ret);
2792 return ret;
2793 }
2794 }
2795
2796 return 0;
2797}
2798
2799int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
2800 struct hclge_promisc_param *param)
2801{
2802 struct hclge_promisc_cfg *req;
2803 struct hclge_desc desc;
2804 int ret;
2805
2806 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
2807
2808 req = (struct hclge_promisc_cfg *)desc.data;
2809 req->vf_id = param->vf_id;
2810 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
2811
2812 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2813 if (ret) {
2814 dev_err(&hdev->pdev->dev,
2815 "Set promisc mode fail, status is %d.\n", ret);
2816 return ret;
2817 }
2818 return 0;
2819}
2820
2821void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
2822 bool en_mc, bool en_bc, int vport_id)
2823{
2824 if (!param)
2825 return;
2826
2827 memset(param, 0, sizeof(struct hclge_promisc_param));
2828 if (en_uc)
2829 param->enable = HCLGE_PROMISC_EN_UC;
2830 if (en_mc)
2831 param->enable |= HCLGE_PROMISC_EN_MC;
2832 if (en_bc)
2833 param->enable |= HCLGE_PROMISC_EN_BC;
2834 param->vf_id = vport_id;
2835}
2836
2837static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
2838{
2839 struct hclge_vport *vport = hclge_get_vport(handle);
2840 struct hclge_dev *hdev = vport->back;
2841 struct hclge_promisc_param param;
2842
2843 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
2844 hclge_cmd_set_promisc_mode(hdev, &param);
2845}
2846
2847static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
2848{
2849 struct hclge_desc desc;
2850 struct hclge_config_mac_mode *req =
2851 (struct hclge_config_mac_mode *)desc.data;
2852 int ret;
2853
2854 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
2855 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_TX_EN_B, enable);
2856 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_RX_EN_B, enable);
2857 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_PAD_TX_B, enable);
2858 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_PAD_RX_B, enable);
2859 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_1588_TX_B, 0);
2860 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_1588_RX_B, 0);
2861 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_APP_LP_B, 0);
2862 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_LINE_LP_B, 0);
2863 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_FCS_TX_B, enable);
2864 hnae_set_bit(req->txrx_pad_fcs_loop_en, HCLGE_MAC_RX_FCS_B, enable);
2865 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2866 HCLGE_MAC_RX_FCS_STRIP_B, enable);
2867 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2868 HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
2869 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2870 HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
2871 hnae_set_bit(req->txrx_pad_fcs_loop_en,
2872 HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
2873
2874 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2875 if (ret)
2876 dev_err(&hdev->pdev->dev,
2877 "mac enable fail, ret =%d.\n", ret);
2878}
2879
2880static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
2881 int stream_id, bool enable)
2882{
2883 struct hclge_desc desc;
2884 struct hclge_cfg_com_tqp_queue *req =
2885 (struct hclge_cfg_com_tqp_queue *)desc.data;
2886 int ret;
2887
2888 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
2889 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
2890 req->stream_id = cpu_to_le16(stream_id);
2891 req->enable |= enable << HCLGE_TQP_ENABLE_B;
2892
2893 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2894 if (ret)
2895 dev_err(&hdev->pdev->dev,
2896 "Tqp enable fail, status =%d.\n", ret);
2897 return ret;
2898}
2899
2900static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
2901{
2902 struct hclge_vport *vport = hclge_get_vport(handle);
2903 struct hnae3_queue *queue;
2904 struct hclge_tqp *tqp;
2905 int i;
2906
2907 for (i = 0; i < vport->alloc_tqps; i++) {
2908 queue = handle->kinfo.tqp[i];
2909 tqp = container_of(queue, struct hclge_tqp, q);
2910 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
2911 }
2912}
2913
2914static int hclge_ae_start(struct hnae3_handle *handle)
2915{
2916 struct hclge_vport *vport = hclge_get_vport(handle);
2917 struct hclge_dev *hdev = vport->back;
2918 int i, queue_id, ret;
2919
2920 for (i = 0; i < vport->alloc_tqps; i++) {
2921 /* todo clear interrupt */
2922 /* ring enable */
2923 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
2924 if (queue_id < 0) {
2925 dev_warn(&hdev->pdev->dev,
2926 "Get invalid queue id, ignore it\n");
2927 continue;
2928 }
2929
2930 hclge_tqp_enable(hdev, queue_id, 0, true);
2931 }
2932 /* mac enable */
2933 hclge_cfg_mac_mode(hdev, true);
2934 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
2935 (void)mod_timer(&hdev->service_timer, jiffies + HZ);
2936
2937 ret = hclge_mac_start_phy(hdev);
2938 if (ret)
2939 return ret;
2940
2941 /* reset tqp stats */
2942 hclge_reset_tqp_stats(handle);
2943
2944 return 0;
2945}
2946
2947static void hclge_ae_stop(struct hnae3_handle *handle)
2948{
2949 struct hclge_vport *vport = hclge_get_vport(handle);
2950 struct hclge_dev *hdev = vport->back;
2951 int i, queue_id;
2952
2953 for (i = 0; i < vport->alloc_tqps; i++) {
2954 /* Ring disable */
2955 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
2956 if (queue_id < 0) {
2957 dev_warn(&hdev->pdev->dev,
2958 "Get invalid queue id, ignore it\n");
2959 continue;
2960 }
2961
2962 hclge_tqp_enable(hdev, queue_id, 0, false);
2963 }
2964 /* Mac disable */
2965 hclge_cfg_mac_mode(hdev, false);
2966
2967 hclge_mac_stop_phy(hdev);
2968
2969 /* reset tqp stats */
2970 hclge_reset_tqp_stats(handle);
2971}
2972
2973static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
2974 u16 cmdq_resp, u8 resp_code,
2975 enum hclge_mac_vlan_tbl_opcode op)
2976{
2977 struct hclge_dev *hdev = vport->back;
2978 int return_status = -EIO;
2979
2980 if (cmdq_resp) {
2981 dev_err(&hdev->pdev->dev,
2982 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
2983 cmdq_resp);
2984 return -EIO;
2985 }
2986
2987 if (op == HCLGE_MAC_VLAN_ADD) {
2988 if ((!resp_code) || (resp_code == 1)) {
2989 return_status = 0;
2990 } else if (resp_code == 2) {
2991 return_status = -EIO;
2992 dev_err(&hdev->pdev->dev,
2993 "add mac addr failed for uc_overflow.\n");
2994 } else if (resp_code == 3) {
2995 return_status = -EIO;
2996 dev_err(&hdev->pdev->dev,
2997 "add mac addr failed for mc_overflow.\n");
2998 } else {
2999 dev_err(&hdev->pdev->dev,
3000 "add mac addr failed for undefined, code=%d.\n",
3001 resp_code);
3002 }
3003 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3004 if (!resp_code) {
3005 return_status = 0;
3006 } else if (resp_code == 1) {
3007 return_status = -EIO;
3008 dev_dbg(&hdev->pdev->dev,
3009 "remove mac addr failed for miss.\n");
3010 } else {
3011 dev_err(&hdev->pdev->dev,
3012 "remove mac addr failed for undefined, code=%d.\n",
3013 resp_code);
3014 }
3015 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3016 if (!resp_code) {
3017 return_status = 0;
3018 } else if (resp_code == 1) {
3019 return_status = -EIO;
3020 dev_dbg(&hdev->pdev->dev,
3021 "lookup mac addr failed for miss.\n");
3022 } else {
3023 dev_err(&hdev->pdev->dev,
3024 "lookup mac addr failed for undefined, code=%d.\n",
3025 resp_code);
3026 }
3027 } else {
3028 return_status = -EIO;
3029 dev_err(&hdev->pdev->dev,
3030 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3031 op);
3032 }
3033
3034 return return_status;
3035}
3036
3037static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3038{
3039 int word_num;
3040 int bit_num;
3041
3042 if (vfid > 255 || vfid < 0)
3043 return -EIO;
3044
3045 if (vfid >= 0 && vfid <= 191) {
3046 word_num = vfid / 32;
3047 bit_num = vfid % 32;
3048 if (clr)
3049 desc[1].data[word_num] &= ~(1 << bit_num);
3050 else
3051 desc[1].data[word_num] |= (1 << bit_num);
3052 } else {
3053 word_num = (vfid - 192) / 32;
3054 bit_num = vfid % 32;
3055 if (clr)
3056 desc[2].data[word_num] &= ~(1 << bit_num);
3057 else
3058 desc[2].data[word_num] |= (1 << bit_num);
3059 }
3060
3061 return 0;
3062}
3063
3064static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3065{
3066#define HCLGE_DESC_NUMBER 3
3067#define HCLGE_FUNC_NUMBER_PER_DESC 6
3068 int i, j;
3069
3070 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3071 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3072 if (desc[i].data[j])
3073 return false;
3074
3075 return true;
3076}
3077
3078static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry *new_req,
3079 const u8 *addr)
3080{
3081 const unsigned char *mac_addr = addr;
3082 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3083 (mac_addr[0]) | (mac_addr[1] << 8);
3084 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3085
3086 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3087 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3088}
3089
3090u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3091 const u8 *addr)
3092{
3093 u16 high_val = addr[1] | (addr[0] << 8);
3094 struct hclge_dev *hdev = vport->back;
3095 u32 rsh = 4 - hdev->mta_mac_sel_type;
3096 u16 ret_val = (high_val >> rsh) & 0xfff;
3097
3098 return ret_val;
3099}
3100
3101static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3102 enum hclge_mta_dmac_sel_type mta_mac_sel,
3103 bool enable)
3104{
3105 struct hclge_mta_filter_mode *req;
3106 struct hclge_desc desc;
3107 int ret;
3108
3109 req = (struct hclge_mta_filter_mode *)desc.data;
3110 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3111
3112 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3113 enable);
3114 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3115 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3116
3117 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3118 if (ret) {
3119 dev_err(&hdev->pdev->dev,
3120 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3121 ret);
3122 return ret;
3123 }
3124
3125 return 0;
3126}
3127
3128int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3129 u8 func_id,
3130 bool enable)
3131{
3132 struct hclge_cfg_func_mta_filter *req;
3133 struct hclge_desc desc;
3134 int ret;
3135
3136 req = (struct hclge_cfg_func_mta_filter *)desc.data;
3137 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3138
3139 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3140 enable);
3141 req->function_id = func_id;
3142
3143 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3144 if (ret) {
3145 dev_err(&hdev->pdev->dev,
3146 "Config func_id enable failed for cmd_send, ret =%d.\n",
3147 ret);
3148 return ret;
3149 }
3150
3151 return 0;
3152}
3153
3154static int hclge_set_mta_table_item(struct hclge_vport *vport,
3155 u16 idx,
3156 bool enable)
3157{
3158 struct hclge_dev *hdev = vport->back;
3159 struct hclge_cfg_func_mta_item *req;
3160 struct hclge_desc desc;
3161 int ret;
3162
3163 req = (struct hclge_cfg_func_mta_item *)desc.data;
3164 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3165 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3166
3167 hnae_set_field(req->item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3168 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
3169 req->item_idx = cpu_to_le16(req->item_idx);
3170
3171 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3172 if (ret) {
3173 dev_err(&hdev->pdev->dev,
3174 "Config mta table item failed for cmd_send, ret =%d.\n",
3175 ret);
3176 return ret;
3177 }
3178
3179 return 0;
3180}
3181
3182static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
3183 struct hclge_mac_vlan_tbl_entry *req)
3184{
3185 struct hclge_dev *hdev = vport->back;
3186 struct hclge_desc desc;
3187 u8 resp_code;
3188 int ret;
3189
3190 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3191
3192 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry));
3193
3194 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3195 if (ret) {
3196 dev_err(&hdev->pdev->dev,
3197 "del mac addr failed for cmd_send, ret =%d.\n",
3198 ret);
3199 return ret;
3200 }
3201 resp_code = (desc.data[0] >> 8) & 0xff;
3202
3203 return hclge_get_mac_vlan_cmd_status(vport, desc.retval, resp_code,
3204 HCLGE_MAC_VLAN_REMOVE);
3205}
3206
3207static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
3208 struct hclge_mac_vlan_tbl_entry *req,
3209 struct hclge_desc *desc,
3210 bool is_mc)
3211{
3212 struct hclge_dev *hdev = vport->back;
3213 u8 resp_code;
3214 int ret;
3215
3216 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3217 if (is_mc) {
3218 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3219 memcpy(desc[0].data,
3220 req,
3221 sizeof(struct hclge_mac_vlan_tbl_entry));
3222 hclge_cmd_setup_basic_desc(&desc[1],
3223 HCLGE_OPC_MAC_VLAN_ADD,
3224 true);
3225 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3226 hclge_cmd_setup_basic_desc(&desc[2],
3227 HCLGE_OPC_MAC_VLAN_ADD,
3228 true);
3229 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3230 } else {
3231 memcpy(desc[0].data,
3232 req,
3233 sizeof(struct hclge_mac_vlan_tbl_entry));
3234 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3235 }
3236 if (ret) {
3237 dev_err(&hdev->pdev->dev,
3238 "lookup mac addr failed for cmd_send, ret =%d.\n",
3239 ret);
3240 return ret;
3241 }
3242 resp_code = (desc[0].data[0] >> 8) & 0xff;
3243
3244 return hclge_get_mac_vlan_cmd_status(vport, desc[0].retval, resp_code,
3245 HCLGE_MAC_VLAN_LKUP);
3246}
3247
3248static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
3249 struct hclge_mac_vlan_tbl_entry *req,
3250 struct hclge_desc *mc_desc)
3251{
3252 struct hclge_dev *hdev = vport->back;
3253 int cfg_status;
3254 u8 resp_code;
3255 int ret;
3256
3257 if (!mc_desc) {
3258 struct hclge_desc desc;
3259
3260 hclge_cmd_setup_basic_desc(&desc,
3261 HCLGE_OPC_MAC_VLAN_ADD,
3262 false);
3263 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry));
3264 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3265 resp_code = (desc.data[0] >> 8) & 0xff;
3266 cfg_status = hclge_get_mac_vlan_cmd_status(vport, desc.retval,
3267 resp_code,
3268 HCLGE_MAC_VLAN_ADD);
3269 } else {
3270 mc_desc[0].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3271 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3272 mc_desc[1].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3273 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3274 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_WR);
3275 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3276 memcpy(mc_desc[0].data, req,
3277 sizeof(struct hclge_mac_vlan_tbl_entry));
3278 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
3279 resp_code = (mc_desc[0].data[0] >> 8) & 0xff;
3280 cfg_status = hclge_get_mac_vlan_cmd_status(vport,
3281 mc_desc[0].retval,
3282 resp_code,
3283 HCLGE_MAC_VLAN_ADD);
3284 }
3285
3286 if (ret) {
3287 dev_err(&hdev->pdev->dev,
3288 "add mac addr failed for cmd_send, ret =%d.\n",
3289 ret);
3290 return ret;
3291 }
3292
3293 return cfg_status;
3294}
3295
3296static int hclge_add_uc_addr(struct hnae3_handle *handle,
3297 const unsigned char *addr)
3298{
3299 struct hclge_vport *vport = hclge_get_vport(handle);
3300
3301 return hclge_add_uc_addr_common(vport, addr);
3302}
3303
3304int hclge_add_uc_addr_common(struct hclge_vport *vport,
3305 const unsigned char *addr)
3306{
3307 struct hclge_dev *hdev = vport->back;
3308 struct hclge_mac_vlan_tbl_entry req;
3309 enum hclge_cmd_status status;
3310
3311 /* mac addr check */
3312 if (is_zero_ether_addr(addr) ||
3313 is_broadcast_ether_addr(addr) ||
3314 is_multicast_ether_addr(addr)) {
3315 dev_err(&hdev->pdev->dev,
3316 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3317 addr,
3318 is_zero_ether_addr(addr),
3319 is_broadcast_ether_addr(addr),
3320 is_multicast_ether_addr(addr));
3321 return -EINVAL;
3322 }
3323
3324 memset(&req, 0, sizeof(req));
3325 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3326 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3327 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
3328 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3329 hnae_set_bit(req.egress_port,
3330 HCLGE_MAC_EPORT_SW_EN_B, 0);
3331 hnae_set_bit(req.egress_port,
3332 HCLGE_MAC_EPORT_TYPE_B, 0);
3333 hnae_set_field(req.egress_port, HCLGE_MAC_EPORT_VFID_M,
3334 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
3335 hnae_set_field(req.egress_port, HCLGE_MAC_EPORT_PFID_M,
3336 HCLGE_MAC_EPORT_PFID_S, 0);
3337 req.egress_port = cpu_to_le16(req.egress_port);
3338
3339 hclge_prepare_mac_addr(&req, addr);
3340
3341 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
3342
3343 return status;
3344}
3345
3346static int hclge_rm_uc_addr(struct hnae3_handle *handle,
3347 const unsigned char *addr)
3348{
3349 struct hclge_vport *vport = hclge_get_vport(handle);
3350
3351 return hclge_rm_uc_addr_common(vport, addr);
3352}
3353
3354int hclge_rm_uc_addr_common(struct hclge_vport *vport,
3355 const unsigned char *addr)
3356{
3357 struct hclge_dev *hdev = vport->back;
3358 struct hclge_mac_vlan_tbl_entry req;
3359 enum hclge_cmd_status status;
3360
3361 /* mac addr check */
3362 if (is_zero_ether_addr(addr) ||
3363 is_broadcast_ether_addr(addr) ||
3364 is_multicast_ether_addr(addr)) {
3365 dev_dbg(&hdev->pdev->dev,
3366 "Remove mac err! invalid mac:%pM.\n",
3367 addr);
3368 return -EINVAL;
3369 }
3370
3371 memset(&req, 0, sizeof(req));
3372 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3373 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3374 hclge_prepare_mac_addr(&req, addr);
3375 status = hclge_remove_mac_vlan_tbl(vport, &req);
3376
3377 return status;
3378}
3379
3380static int hclge_add_mc_addr(struct hnae3_handle *handle,
3381 const unsigned char *addr)
3382{
3383 struct hclge_vport *vport = hclge_get_vport(handle);
3384
3385 return hclge_add_mc_addr_common(vport, addr);
3386}
3387
3388int hclge_add_mc_addr_common(struct hclge_vport *vport,
3389 const unsigned char *addr)
3390{
3391 struct hclge_dev *hdev = vport->back;
3392 struct hclge_mac_vlan_tbl_entry req;
3393 struct hclge_desc desc[3];
3394 u16 tbl_idx;
3395 int status;
3396
3397 /* mac addr check */
3398 if (!is_multicast_ether_addr(addr)) {
3399 dev_err(&hdev->pdev->dev,
3400 "Add mc mac err! invalid mac:%pM.\n",
3401 addr);
3402 return -EINVAL;
3403 }
3404 memset(&req, 0, sizeof(req));
3405 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3406 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3407 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
3408 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3409 hclge_prepare_mac_addr(&req, addr);
3410 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
3411 if (!status) {
3412 /* This mac addr exist, update VFID for it */
3413 hclge_update_desc_vfid(desc, vport->vport_id, false);
3414 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3415 } else {
3416 /* This mac addr do not exist, add new entry for it */
3417 memset(desc[0].data, 0, sizeof(desc[0].data));
3418 memset(desc[1].data, 0, sizeof(desc[0].data));
3419 memset(desc[2].data, 0, sizeof(desc[0].data));
3420 hclge_update_desc_vfid(desc, vport->vport_id, false);
3421 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3422 }
3423
3424 /* Set MTA table for this MAC address */
3425 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
3426 status = hclge_set_mta_table_item(vport, tbl_idx, true);
3427
3428 return status;
3429}
3430
3431static int hclge_rm_mc_addr(struct hnae3_handle *handle,
3432 const unsigned char *addr)
3433{
3434 struct hclge_vport *vport = hclge_get_vport(handle);
3435
3436 return hclge_rm_mc_addr_common(vport, addr);
3437}
3438
3439int hclge_rm_mc_addr_common(struct hclge_vport *vport,
3440 const unsigned char *addr)
3441{
3442 struct hclge_dev *hdev = vport->back;
3443 struct hclge_mac_vlan_tbl_entry req;
3444 enum hclge_cmd_status status;
3445 struct hclge_desc desc[3];
3446 u16 tbl_idx;
3447
3448 /* mac addr check */
3449 if (!is_multicast_ether_addr(addr)) {
3450 dev_dbg(&hdev->pdev->dev,
3451 "Remove mc mac err! invalid mac:%pM.\n",
3452 addr);
3453 return -EINVAL;
3454 }
3455
3456 memset(&req, 0, sizeof(req));
3457 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3458 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3459 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
3460 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3461 hclge_prepare_mac_addr(&req, addr);
3462 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
3463 if (!status) {
3464 /* This mac addr exist, remove this handle's VFID for it */
3465 hclge_update_desc_vfid(desc, vport->vport_id, true);
3466
3467 if (hclge_is_all_function_id_zero(desc))
3468 /* All the vfid is zero, so need to delete this entry */
3469 status = hclge_remove_mac_vlan_tbl(vport, &req);
3470 else
3471 /* Not all the vfid is zero, update the vfid */
3472 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
3473
3474 } else {
3475 /* This mac addr do not exist, can't delete it */
3476 dev_err(&hdev->pdev->dev,
d7629e74 3477 "Rm multicast mac addr failed, ret = %d.\n",
46a3df9f
S		 3478 status);
3479 return -EIO;
3480 }
3481
3482 /* Set MTB table for this MAC address */
3483 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
3484 status = hclge_set_mta_table_item(vport, tbl_idx, false);
3485
3486 return status;
3487}
3488
3489static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
3490{
3491 struct hclge_vport *vport = hclge_get_vport(handle);
3492 struct hclge_dev *hdev = vport->back;
3493
3494 ether_addr_copy(p, hdev->hw.mac.mac_addr);
3495}
3496
3497static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
3498{
3499 const unsigned char *new_addr = (const unsigned char *)p;
3500 struct hclge_vport *vport = hclge_get_vport(handle);
3501 struct hclge_dev *hdev = vport->back;
3502
3503 /* mac addr check */
3504 if (is_zero_ether_addr(new_addr) ||
3505 is_broadcast_ether_addr(new_addr) ||
3506 is_multicast_ether_addr(new_addr)) {
3507 dev_err(&hdev->pdev->dev,
3508 "Change uc mac err! invalid mac:%p.\n",
3509 new_addr);
3510 return -EINVAL;
3511 }
3512
3513 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
3514
3515 if (!hclge_add_uc_addr(handle, new_addr)) {
3516 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
3517 return 0;
3518 }
3519
3520 return -EIO;
3521}
3522
3523static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
3524 bool filter_en)
3525{
3526 struct hclge_vlan_filter_ctrl *req;
3527 struct hclge_desc desc;
3528 int ret;
3529
3530 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
3531
3532 req = (struct hclge_vlan_filter_ctrl *)desc.data;
3533 req->vlan_type = vlan_type;
3534 req->vlan_fe = filter_en;
3535
3536 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3537 if (ret) {
3538 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
3539 ret);
3540 return ret;
3541 }
3542
3543 return 0;
3544}
3545
3546int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
3547 bool is_kill, u16 vlan, u8 qos, __be16 proto)
3548{
3549#define HCLGE_MAX_VF_BYTES 16
3550 struct hclge_vlan_filter_vf_cfg *req0;
3551 struct hclge_vlan_filter_vf_cfg *req1;
3552 struct hclge_desc desc[2];
3553 u8 vf_byte_val;
3554 u8 vf_byte_off;
3555 int ret;
3556
3557 hclge_cmd_setup_basic_desc(&desc[0],
3558 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
3559 hclge_cmd_setup_basic_desc(&desc[1],
3560 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
3561
3562 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3563
3564 vf_byte_off = vfid / 8;
3565 vf_byte_val = 1 << (vfid % 8);
3566
3567 req0 = (struct hclge_vlan_filter_vf_cfg *)desc[0].data;
3568 req1 = (struct hclge_vlan_filter_vf_cfg *)desc[1].data;
3569
3570 req0->vlan_id = vlan;
3571 req0->vlan_cfg = is_kill;
3572
3573 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
3574 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
3575 else
3576 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
3577
3578 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3579 if (ret) {
3580 dev_err(&hdev->pdev->dev,
3581 "Send vf vlan command fail, ret =%d.\n",
3582 ret);
3583 return ret;
3584 }
3585
3586 if (!is_kill) {
3587 if (!req0->resp_code || req0->resp_code == 1)
3588 return 0;
3589
3590 dev_err(&hdev->pdev->dev,
3591 "Add vf vlan filter fail, ret =%d.\n",
3592 req0->resp_code);
3593 } else {
3594 if (!req0->resp_code)
3595 return 0;
3596
3597 dev_err(&hdev->pdev->dev,
3598 "Kill vf vlan filter fail, ret =%d.\n",
3599 req0->resp_code);
3600 }
3601
3602 return -EIO;
3603}
3604
3605static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
3606 __be16 proto, u16 vlan_id,
3607 bool is_kill)
3608{
3609 struct hclge_vport *vport = hclge_get_vport(handle);
3610 struct hclge_dev *hdev = vport->back;
3611 struct hclge_vlan_filter_pf_cfg *req;
3612 struct hclge_desc desc;
3613 u8 vlan_offset_byte_val;
3614 u8 vlan_offset_byte;
3615 u8 vlan_offset_160;
3616 int ret;
3617
3618 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
3619
3620 vlan_offset_160 = vlan_id / 160;
3621 vlan_offset_byte = (vlan_id % 160) / 8;
3622 vlan_offset_byte_val = 1 << (vlan_id % 8);
3623
3624 req = (struct hclge_vlan_filter_pf_cfg *)desc.data;
3625 req->vlan_offset = vlan_offset_160;
3626 req->vlan_cfg = is_kill;
3627 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
3628
3629 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3630 if (ret) {
3631 dev_err(&hdev->pdev->dev,
3632 "port vlan command, send fail, ret =%d.\n",
3633 ret);
3634 return ret;
3635 }
3636
3637 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
3638 if (ret) {
3639 dev_err(&hdev->pdev->dev,
3640 "Set pf vlan filter config fail, ret =%d.\n",
3641 ret);
3642 return -EIO;
3643 }
3644
3645 return 0;
3646}
3647
3648static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
3649 u16 vlan, u8 qos, __be16 proto)
3650{
3651 struct hclge_vport *vport = hclge_get_vport(handle);
3652 struct hclge_dev *hdev = vport->back;
3653
3654 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
3655 return -EINVAL;
3656 if (proto != htons(ETH_P_8021Q))
3657 return -EPROTONOSUPPORT;
3658
3659 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
3660}
3661
3662static int hclge_init_vlan_config(struct hclge_dev *hdev)
3663{
3664#define HCLGE_VLAN_TYPE_VF_TABLE 0
3665#define HCLGE_VLAN_TYPE_PORT_TABLE 1
5e43aef8 3666 struct hnae3_handle *handle;
46a3df9f
S		 3667 int ret;
3668
3669 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,
3670 true);
3671 if (ret)
3672 return ret;
3673
3674 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,
3675 true);
5e43aef8
L		 3676 if (ret)
3677 return ret;
46a3df9f 3678
5e43aef8
L		 3679 handle = &hdev->vport[0].nic;
3680 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 3681}
3682
3683static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
3684{
3685 struct hclge_vport *vport = hclge_get_vport(handle);
3686 struct hclge_config_max_frm_size *req;
3687 struct hclge_dev *hdev = vport->back;
3688 struct hclge_desc desc;
3689 int ret;
3690
3691 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
3692 return -EINVAL;
3693
3694 hdev->mps = new_mtu;
3695 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
3696
3697 req = (struct hclge_config_max_frm_size *)desc.data;
3698 req->max_frm_size = cpu_to_le16(new_mtu);
3699
3700 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3701 if (ret) {
3702 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
3703 return ret;
3704 }
3705
3706 return 0;
3707}
3708
3709static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
3710 bool enable)
3711{
3712 struct hclge_reset_tqp_queue *req;
3713 struct hclge_desc desc;
3714 int ret;
3715
3716 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
3717
3718 req = (struct hclge_reset_tqp_queue *)desc.data;
3719 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
3720 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
3721
3722 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3723 if (ret) {
3724 dev_err(&hdev->pdev->dev,
3725 "Send tqp reset cmd error, status =%d\n", ret);
3726 return ret;
3727 }
3728
3729 return 0;
3730}
3731
3732static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
3733{
3734 struct hclge_reset_tqp_queue *req;
3735 struct hclge_desc desc;
3736 int ret;
3737
3738 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
3739
3740 req = (struct hclge_reset_tqp_queue *)desc.data;
3741 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
3742
3743 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3744 if (ret) {
3745 dev_err(&hdev->pdev->dev,
3746 "Get reset status error, status =%d\n", ret);
3747 return ret;
3748 }
3749
3750 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
3751}
3752
3753static void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
3754{
3755 struct hclge_vport *vport = hclge_get_vport(handle);
3756 struct hclge_dev *hdev = vport->back;
3757 int reset_try_times = 0;
3758 int reset_status;
3759 int ret;
3760
3761 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
3762 if (ret) {
3763 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
3764 return;
3765 }
3766
3767 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
3768 if (ret) {
3769 dev_warn(&hdev->pdev->dev,
3770 "Send reset tqp cmd fail, ret = %d\n", ret);
3771 return;
3772 }
3773
3774 reset_try_times = 0;
3775 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
3776 /* Wait for tqp hw reset */
3777 msleep(20);
3778 reset_status = hclge_get_reset_status(hdev, queue_id);
3779 if (reset_status)
3780 break;
3781 }
3782
3783 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
3784 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
3785 return;
3786 }
3787
3788 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
3789 if (ret) {
3790 dev_warn(&hdev->pdev->dev,
3791 "Deassert the soft reset fail, ret = %d\n", ret);
3792 return;
3793 }
3794}
3795
3796static u32 hclge_get_fw_version(struct hnae3_handle *handle)
3797{
3798 struct hclge_vport *vport = hclge_get_vport(handle);
3799 struct hclge_dev *hdev = vport->back;
3800
3801 return hdev->fw_version;
3802}
3803
3804static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
3805 u32 *rx_en, u32 *tx_en)
3806{
3807 struct hclge_vport *vport = hclge_get_vport(handle);
3808 struct hclge_dev *hdev = vport->back;
3809
3810 *auto_neg = hclge_get_autoneg(handle);
3811
3812 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
3813 *rx_en = 0;
3814 *tx_en = 0;
3815 return;
3816 }
3817
3818 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
3819 *rx_en = 1;
3820 *tx_en = 0;
3821 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
3822 *tx_en = 1;
3823 *rx_en = 0;
3824 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
3825 *rx_en = 1;
3826 *tx_en = 1;
3827 } else {
3828 *rx_en = 0;
3829 *tx_en = 0;
3830 }
3831}
3832
3833static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
3834 u8 *auto_neg, u32 *speed, u8 *duplex)
3835{
3836 struct hclge_vport *vport = hclge_get_vport(handle);
3837 struct hclge_dev *hdev = vport->back;
3838
3839 if (speed)
3840 *speed = hdev->hw.mac.speed;
3841 if (duplex)
3842 *duplex = hdev->hw.mac.duplex;
3843 if (auto_neg)
3844 *auto_neg = hdev->hw.mac.autoneg;
3845}
3846
3847static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
3848{
3849 struct hclge_vport *vport = hclge_get_vport(handle);
3850 struct hclge_dev *hdev = vport->back;
3851
3852 if (media_type)
3853 *media_type = hdev->hw.mac.media_type;
3854}
3855
3856static void hclge_get_mdix_mode(struct hnae3_handle *handle,
3857 u8 *tp_mdix_ctrl, u8 *tp_mdix)
3858{
3859 struct hclge_vport *vport = hclge_get_vport(handle);
3860 struct hclge_dev *hdev = vport->back;
3861 struct phy_device *phydev = hdev->hw.mac.phydev;
3862 int mdix_ctrl, mdix, retval, is_resolved;
3863
3864 if (!phydev) {
3865 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
3866 *tp_mdix = ETH_TP_MDI_INVALID;
3867 return;
3868 }
3869
3870 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
3871
3872 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
3873 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
3874 HCLGE_PHY_MDIX_CTRL_S);
3875
3876 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
3877 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
3878 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
3879
3880 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
3881
3882 switch (mdix_ctrl) {
3883 case 0x0:
3884 *tp_mdix_ctrl = ETH_TP_MDI;
3885 break;
3886 case 0x1:
3887 *tp_mdix_ctrl = ETH_TP_MDI_X;
3888 break;
3889 case 0x3:
3890 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
3891 break;
3892 default:
3893 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
3894 break;
3895 }
3896
3897 if (!is_resolved)
3898 *tp_mdix = ETH_TP_MDI_INVALID;
3899 else if (mdix)
3900 *tp_mdix = ETH_TP_MDI_X;
3901 else
3902 *tp_mdix = ETH_TP_MDI;
3903}
3904
3905static int hclge_init_client_instance(struct hnae3_client *client,
3906 struct hnae3_ae_dev *ae_dev)
3907{
3908 struct hclge_dev *hdev = ae_dev->priv;
3909 struct hclge_vport *vport;
3910 int i, ret;
3911
3912 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3913 vport = &hdev->vport[i];
3914
3915 switch (client->type) {
3916 case HNAE3_CLIENT_KNIC:
3917
3918 hdev->nic_client = client;
3919 vport->nic.client = client;
3920 ret = client->ops->init_instance(&vport->nic);
3921 if (ret)
3922 goto err;
3923
3924 if (hdev->roce_client &&
e92a0843 3925 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 3926 struct hnae3_client *rc = hdev->roce_client;
3927
3928 ret = hclge_init_roce_base_info(vport);
3929 if (ret)
3930 goto err;
3931
3932 ret = rc->ops->init_instance(&vport->roce);
3933 if (ret)
3934 goto err;
3935 }
3936
3937 break;
3938 case HNAE3_CLIENT_UNIC:
3939 hdev->nic_client = client;
3940 vport->nic.client = client;
3941
3942 ret = client->ops->init_instance(&vport->nic);
3943 if (ret)
3944 goto err;
3945
3946 break;
3947 case HNAE3_CLIENT_ROCE:
e92a0843 3948 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 3949 hdev->roce_client = client;
3950 vport->roce.client = client;
3951 }
3952
3953 if (hdev->roce_client) {
3954 ret = hclge_init_roce_base_info(vport);
3955 if (ret)
3956 goto err;
3957
3958 ret = client->ops->init_instance(&vport->roce);
3959 if (ret)
3960 goto err;
3961 }
3962 }
3963 }
3964
3965 return 0;
3966err:
3967 return ret;
3968}
3969
3970static void hclge_uninit_client_instance(struct hnae3_client *client,
3971 struct hnae3_ae_dev *ae_dev)
3972{
3973 struct hclge_dev *hdev = ae_dev->priv;
3974 struct hclge_vport *vport;
3975 int i;
3976
3977 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3978 vport = &hdev->vport[i];
3979 if (hdev->roce_client)
3980 hdev->roce_client->ops->uninit_instance(&vport->roce,
3981 0);
3982 if (client->type == HNAE3_CLIENT_ROCE)
3983 return;
3984 if (client->ops->uninit_instance)
3985 client->ops->uninit_instance(&vport->nic, 0);
3986 }
3987}
3988
3989static int hclge_pci_init(struct hclge_dev *hdev)
3990{
3991 struct pci_dev *pdev = hdev->pdev;
3992 struct hclge_hw *hw;
3993 int ret;
3994
3995 ret = pci_enable_device(pdev);
3996 if (ret) {
3997 dev_err(&pdev->dev, "failed to enable PCI device\n");
3998 goto err_no_drvdata;
3999 }
4000
4001 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4002 if (ret) {
4003 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4004 if (ret) {
4005 dev_err(&pdev->dev,
4006 "can't set consistent PCI DMA");
4007 goto err_disable_device;
4008 }
4009 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
4010 }
4011
4012 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
4013 if (ret) {
4014 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
4015 goto err_disable_device;
4016 }
4017
4018 pci_set_master(pdev);
4019 hw = &hdev->hw;
4020 hw->back = hdev;
4021 hw->io_base = pcim_iomap(pdev, 2, 0);
4022 if (!hw->io_base) {
4023 dev_err(&pdev->dev, "Can't map configuration register space\n");
4024 ret = -ENOMEM;
4025 goto err_clr_master;
4026 }
4027
4028 return 0;
4029err_clr_master:
4030 pci_clear_master(pdev);
4031 pci_release_regions(pdev);
4032err_disable_device:
4033 pci_disable_device(pdev);
4034err_no_drvdata:
4035 pci_set_drvdata(pdev, NULL);
4036
4037 return ret;
4038}
4039
4040static void hclge_pci_uninit(struct hclge_dev *hdev)
4041{
4042 struct pci_dev *pdev = hdev->pdev;
4043
4044 if (hdev->flag & HCLGE_FLAG_USE_MSIX) {
4045 pci_disable_msix(pdev);
4046 devm_kfree(&pdev->dev, hdev->msix_entries);
4047 hdev->msix_entries = NULL;
4048 } else {
4049 pci_disable_msi(pdev);
4050 }
4051
4052 pci_clear_master(pdev);
4053 pci_release_mem_regions(pdev);
4054 pci_disable_device(pdev);
4055}
4056
4057static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4058{
4059 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 4060 struct hclge_dev *hdev;
4061 int ret;
4062
4063 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
4064 if (!hdev) {
4065 ret = -ENOMEM;
4066 goto err_hclge_dev;
4067 }
4068
4069 hdev->flag |= HCLGE_FLAG_USE_MSIX;
4070 hdev->pdev = pdev;
4071 hdev->ae_dev = ae_dev;
4072 ae_dev->priv = hdev;
4073
46a3df9f
S		 4074 ret = hclge_pci_init(hdev);
4075 if (ret) {
4076 dev_err(&pdev->dev, "PCI init failed\n");
4077 goto err_pci_init;
4078 }
4079
4080 /* Command queue initialize */
4081 ret = hclge_cmd_init(hdev);
4082 if (ret)
4083 goto err_cmd_init;
4084
4085 ret = hclge_get_cap(hdev);
4086 if (ret) {
e00e2197
CIK		 4087 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4088 ret);
46a3df9f
S		 4089 return ret;
4090 }
4091
4092 ret = hclge_configure(hdev);
4093 if (ret) {
4094 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4095 return ret;
4096 }
4097
4098 if (hdev->flag & HCLGE_FLAG_USE_MSIX)
4099 ret = hclge_init_msix(hdev);
4100 else
4101 ret = hclge_init_msi(hdev);
4102 if (ret) {
4103 dev_err(&pdev->dev, "Init msix/msi error, ret = %d.\n", ret);
4104 return ret;
4105 }
4106
4107 ret = hclge_alloc_tqps(hdev);
4108 if (ret) {
4109 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
4110 return ret;
4111 }
4112
4113 ret = hclge_alloc_vport(hdev);
4114 if (ret) {
4115 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
4116 return ret;
4117 }
4118
4119 ret = hclge_mac_init(hdev);
4120 if (ret) {
4121 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4122 return ret;
4123 }
4124 ret = hclge_buffer_alloc(hdev);
4125 if (ret) {
4126 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4127 return ret;
4128 }
4129
4130 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4131 if (ret) {
4132 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4133 return ret;
4134 }
4135
4136 ret = hclge_rss_init_hw(hdev);
4137 if (ret) {
4138 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4139 return ret;
4140 }
4141
4142 ret = hclge_init_vlan_config(hdev);
4143 if (ret) {
4144 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4145 return ret;
4146 }
4147
4148 ret = hclge_tm_schd_init(hdev);
4149 if (ret) {
4150 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4151 return ret;
4152 }
4153
4154 setup_timer(&hdev->service_timer, hclge_service_timer,
4155 (unsigned long)hdev);
4156 INIT_WORK(&hdev->service_task, hclge_service_task);
4157
4158 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
4159 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4160
4161 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
4162 return 0;
4163
4164err_cmd_init:
4165 pci_release_regions(pdev);
4166err_pci_init:
4167 pci_set_drvdata(pdev, NULL);
4168err_hclge_dev:
4169 return ret;
4170}
4171
4172static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
4173{
4174 struct hclge_dev *hdev = ae_dev->priv;
4175 struct hclge_mac *mac = &hdev->hw.mac;
4176
4177 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4178
2a32ca13
AB		 4179 if (IS_ENABLED(CONFIG_PCI_IOV))
4180 hclge_disable_sriov(hdev);
46a3df9f
S		 4181
4182 if (hdev->service_timer.data)
4183 del_timer_sync(&hdev->service_timer);
4184 if (hdev->service_task.func)
4185 cancel_work_sync(&hdev->service_task);
4186
4187 if (mac->phydev)
4188 mdiobus_unregister(mac->mdio_bus);
4189
4190 hclge_destroy_cmd_queue(&hdev->hw);
4191 hclge_pci_uninit(hdev);
4192 ae_dev->priv = NULL;
4193}
4194
4195static const struct hnae3_ae_ops hclge_ops = {
4196 .init_ae_dev = hclge_init_ae_dev,
4197 .uninit_ae_dev = hclge_uninit_ae_dev,
4198 .init_client_instance = hclge_init_client_instance,
4199 .uninit_client_instance = hclge_uninit_client_instance,
4200 .map_ring_to_vector = hclge_map_handle_ring_to_vector,
4201 .unmap_ring_from_vector = hclge_unmap_ring_from_vector,
4202 .get_vector = hclge_get_vector,
4203 .set_promisc_mode = hclge_set_promisc_mode,
4204 .start = hclge_ae_start,
4205 .stop = hclge_ae_stop,
4206 .get_status = hclge_get_status,
4207 .get_ksettings_an_result = hclge_get_ksettings_an_result,
4208 .update_speed_duplex_h = hclge_update_speed_duplex_h,
4209 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
4210 .get_media_type = hclge_get_media_type,
4211 .get_rss_key_size = hclge_get_rss_key_size,
4212 .get_rss_indir_size = hclge_get_rss_indir_size,
4213 .get_rss = hclge_get_rss,
4214 .set_rss = hclge_set_rss,
4215 .get_tc_size = hclge_get_tc_size,
4216 .get_mac_addr = hclge_get_mac_addr,
4217 .set_mac_addr = hclge_set_mac_addr,
4218 .add_uc_addr = hclge_add_uc_addr,
4219 .rm_uc_addr = hclge_rm_uc_addr,
4220 .add_mc_addr = hclge_add_mc_addr,
4221 .rm_mc_addr = hclge_rm_mc_addr,
4222 .set_autoneg = hclge_set_autoneg,
4223 .get_autoneg = hclge_get_autoneg,
4224 .get_pauseparam = hclge_get_pauseparam,
4225 .set_mtu = hclge_set_mtu,
4226 .reset_queue = hclge_reset_tqp,
4227 .get_stats = hclge_get_stats,
4228 .update_stats = hclge_update_stats,
4229 .get_strings = hclge_get_strings,
4230 .get_sset_count = hclge_get_sset_count,
4231 .get_fw_version = hclge_get_fw_version,
4232 .get_mdix_mode = hclge_get_mdix_mode,
4233 .set_vlan_filter = hclge_set_port_vlan_filter,
4234 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
4235};
4236
4237static struct hnae3_ae_algo ae_algo = {
4238 .ops = &hclge_ops,
4239 .name = HCLGE_NAME,
4240 .pdev_id_table = ae_algo_pci_tbl,
4241};
4242
4243static int hclge_init(void)
4244{
4245 pr_info("%s is initializing\n", HCLGE_NAME);
4246
4247 return hnae3_register_ae_algo(&ae_algo);
4248}
4249
4250static void hclge_exit(void)
4251{
4252 hnae3_unregister_ae_algo(&ae_algo);
4253}
4254module_init(hclge_init);
4255module_exit(hclge_exit);
4256
4257MODULE_LICENSE("GPL");
4258MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
4259MODULE_DESCRIPTION("HCLGE Driver");
4260MODULE_VERSION(HCLGE_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)