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hns3: Fix the build.
[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
46a3df9f
S		 3
4#include <linux/acpi.h>
5#include <linux/device.h>
6#include <linux/etherdevice.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/pci.h>
13#include <linux/platform_device.h>
2866ccb2 14#include <linux/if_vlan.h>
f2f432f2 15#include <net/rtnetlink.h>
46a3df9f 16#include "hclge_cmd.h"
cacde272 17#include "hclge_dcb.h"
46a3df9f 18#include "hclge_main.h"
dde1a86e 19#include "hclge_mbx.h"
46a3df9f
S		 20#include "hclge_mdio.h"
21#include "hclge_tm.h"
22#include "hnae3.h"
23
24#define HCLGE_NAME "hclge"
25#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
26#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
46a3df9f 27
46a3df9f
S		 28static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
29 enum hclge_mta_dmac_sel_type mta_mac_sel,
30 bool enable);
f9fd82a9 31static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 32static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 33static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 34
35static struct hnae3_ae_algo ae_algo;
36
37static const struct pci_device_id ae_algo_pci_tbl[] = {
38 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
39 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 45 /* required last entry */
46a3df9f
S		 46 {0, }
47};
48
2f550a46
YL		 49MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
50
46a3df9f 51static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
eb66d503 52 "App Loopback test",
4dc13b96
FL		 53 "Serdes serial Loopback test",
54 "Serdes parallel Loopback test",
46a3df9f
S		 55 "Phy Loopback test"
56};
57
46a3df9f
S		 58static const struct hclge_comm_stats_str g_mac_stats_string[] = {
59 {"mac_tx_mac_pause_num",
60 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
61 {"mac_rx_mac_pause_num",
62 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
63 {"mac_tx_pfc_pri0_pkt_num",
64 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
65 {"mac_tx_pfc_pri1_pkt_num",
66 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
67 {"mac_tx_pfc_pri2_pkt_num",
68 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
69 {"mac_tx_pfc_pri3_pkt_num",
70 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
71 {"mac_tx_pfc_pri4_pkt_num",
72 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
73 {"mac_tx_pfc_pri5_pkt_num",
74 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
75 {"mac_tx_pfc_pri6_pkt_num",
76 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
77 {"mac_tx_pfc_pri7_pkt_num",
78 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
79 {"mac_rx_pfc_pri0_pkt_num",
80 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
81 {"mac_rx_pfc_pri1_pkt_num",
82 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
83 {"mac_rx_pfc_pri2_pkt_num",
84 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
85 {"mac_rx_pfc_pri3_pkt_num",
86 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
87 {"mac_rx_pfc_pri4_pkt_num",
88 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
89 {"mac_rx_pfc_pri5_pkt_num",
90 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
91 {"mac_rx_pfc_pri6_pkt_num",
92 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
93 {"mac_rx_pfc_pri7_pkt_num",
94 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
95 {"mac_tx_total_pkt_num",
96 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
97 {"mac_tx_total_oct_num",
98 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
99 {"mac_tx_good_pkt_num",
100 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
101 {"mac_tx_bad_pkt_num",
102 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
103 {"mac_tx_good_oct_num",
104 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
105 {"mac_tx_bad_oct_num",
106 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
107 {"mac_tx_uni_pkt_num",
108 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
109 {"mac_tx_multi_pkt_num",
110 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
111 {"mac_tx_broad_pkt_num",
112 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
113 {"mac_tx_undersize_pkt_num",
114 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
200a88c6
JS		 115 {"mac_tx_oversize_pkt_num",
116 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 117 {"mac_tx_64_oct_pkt_num",
118 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
119 {"mac_tx_65_127_oct_pkt_num",
120 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
121 {"mac_tx_128_255_oct_pkt_num",
122 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
123 {"mac_tx_256_511_oct_pkt_num",
124 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
125 {"mac_tx_512_1023_oct_pkt_num",
126 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
127 {"mac_tx_1024_1518_oct_pkt_num",
128 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
91f384f6
JS		 129 {"mac_tx_1519_2047_oct_pkt_num",
130 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
131 {"mac_tx_2048_4095_oct_pkt_num",
132 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
133 {"mac_tx_4096_8191_oct_pkt_num",
134 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
91f384f6
JS		 135 {"mac_tx_8192_9216_oct_pkt_num",
136 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
137 {"mac_tx_9217_12287_oct_pkt_num",
138 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
139 {"mac_tx_12288_16383_oct_pkt_num",
140 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
141 {"mac_tx_1519_max_good_pkt_num",
142 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
143 {"mac_tx_1519_max_bad_pkt_num",
144 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 145 {"mac_rx_total_pkt_num",
146 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
147 {"mac_rx_total_oct_num",
148 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
149 {"mac_rx_good_pkt_num",
150 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
151 {"mac_rx_bad_pkt_num",
152 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
153 {"mac_rx_good_oct_num",
154 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
155 {"mac_rx_bad_oct_num",
156 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
157 {"mac_rx_uni_pkt_num",
158 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
159 {"mac_rx_multi_pkt_num",
160 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
161 {"mac_rx_broad_pkt_num",
162 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
163 {"mac_rx_undersize_pkt_num",
164 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
200a88c6
JS		 165 {"mac_rx_oversize_pkt_num",
166 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 167 {"mac_rx_64_oct_pkt_num",
168 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
169 {"mac_rx_65_127_oct_pkt_num",
170 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
171 {"mac_rx_128_255_oct_pkt_num",
172 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
173 {"mac_rx_256_511_oct_pkt_num",
174 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
175 {"mac_rx_512_1023_oct_pkt_num",
176 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
177 {"mac_rx_1024_1518_oct_pkt_num",
178 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
91f384f6
JS		 179 {"mac_rx_1519_2047_oct_pkt_num",
180 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
181 {"mac_rx_2048_4095_oct_pkt_num",
182 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
183 {"mac_rx_4096_8191_oct_pkt_num",
184 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
91f384f6
JS		 185 {"mac_rx_8192_9216_oct_pkt_num",
186 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
187 {"mac_rx_9217_12287_oct_pkt_num",
188 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
189 {"mac_rx_12288_16383_oct_pkt_num",
190 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
191 {"mac_rx_1519_max_good_pkt_num",
192 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
193 {"mac_rx_1519_max_bad_pkt_num",
194 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 195
a6c51c26
JS		 196 {"mac_tx_fragment_pkt_num",
197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
198 {"mac_tx_undermin_pkt_num",
199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
200 {"mac_tx_jabber_pkt_num",
201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
202 {"mac_tx_err_all_pkt_num",
203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
204 {"mac_tx_from_app_good_pkt_num",
205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
206 {"mac_tx_from_app_bad_pkt_num",
207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
208 {"mac_rx_fragment_pkt_num",
209 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
210 {"mac_rx_undermin_pkt_num",
211 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
212 {"mac_rx_jabber_pkt_num",
213 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
214 {"mac_rx_fcs_err_pkt_num",
215 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
216 {"mac_rx_send_app_good_pkt_num",
217 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
218 {"mac_rx_send_app_bad_pkt_num",
219 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 220};
221
f5aac71c
FL		 222static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
223 {
224 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
225 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
226 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
227 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
228 .i_port_bitmap = 0x1,
229 },
230};
231
46a3df9f
S		 232static int hclge_mac_update_stats(struct hclge_dev *hdev)
233{
91f384f6 234#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 235#define HCLGE_RTN_DATA_NUM 4
236
237 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
238 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 239 __le64 *desc_data;
46a3df9f
S		 240 int i, k, n;
241 int ret;
242
243 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
244 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
245 if (ret) {
246 dev_err(&hdev->pdev->dev,
247 "Get MAC pkt stats fail, status = %d.\n", ret);
248
249 return ret;
250 }
251
252 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
253 if (unlikely(i == 0)) {
a90bb9a5 254 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 255 n = HCLGE_RTN_DATA_NUM - 2;
256 } else {
a90bb9a5 257 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 258 n = HCLGE_RTN_DATA_NUM;
259 }
260 for (k = 0; k < n; k++) {
a90bb9a5 261 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 262 desc_data++;
263 }
264 }
265
266 return 0;
267}
268
269static int hclge_tqps_update_stats(struct hnae3_handle *handle)
270{
271 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
272 struct hclge_vport *vport = hclge_get_vport(handle);
273 struct hclge_dev *hdev = vport->back;
274 struct hnae3_queue *queue;
275 struct hclge_desc desc[1];
276 struct hclge_tqp *tqp;
277 int ret, i;
278
279 for (i = 0; i < kinfo->num_tqps; i++) {
280 queue = handle->kinfo.tqp[i];
281 tqp = container_of(queue, struct hclge_tqp, q);
282 /* command : HCLGE_OPC_QUERY_IGU_STAT */
283 hclge_cmd_setup_basic_desc(&desc[0],
284 HCLGE_OPC_QUERY_RX_STATUS,
285 true);
286
a90bb9a5 287 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 288 ret = hclge_cmd_send(&hdev->hw, desc, 1);
289 if (ret) {
290 dev_err(&hdev->pdev->dev,
291 "Query tqp stat fail, status = %d,queue = %d\n",
292 ret, i);
293 return ret;
294 }
295 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
cf72fa63 296 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 297 }
298
299 for (i = 0; i < kinfo->num_tqps; i++) {
300 queue = handle->kinfo.tqp[i];
301 tqp = container_of(queue, struct hclge_tqp, q);
302 /* command : HCLGE_OPC_QUERY_IGU_STAT */
303 hclge_cmd_setup_basic_desc(&desc[0],
304 HCLGE_OPC_QUERY_TX_STATUS,
305 true);
306
a90bb9a5 307 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 308 ret = hclge_cmd_send(&hdev->hw, desc, 1);
309 if (ret) {
310 dev_err(&hdev->pdev->dev,
311 "Query tqp stat fail, status = %d,queue = %d\n",
312 ret, i);
313 return ret;
314 }
315 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
cf72fa63 316 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 317 }
318
319 return 0;
320}
321
322static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
323{
324 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
325 struct hclge_tqp *tqp;
326 u64 *buff = data;
327 int i;
328
329 for (i = 0; i < kinfo->num_tqps; i++) {
330 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 331 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 332 }
333
334 for (i = 0; i < kinfo->num_tqps; i++) {
335 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 336 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 337 }
338
339 return buff;
340}
341
342static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
343{
344 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
345
346 return kinfo->num_tqps * (2);
347}
348
349static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
350{
351 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
352 u8 *buff = data;
353 int i = 0;
354
355 for (i = 0; i < kinfo->num_tqps; i++) {
356 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
357 struct hclge_tqp, q);
0c218123 358 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
46a3df9f
S		 359 tqp->index);
360 buff = buff + ETH_GSTRING_LEN;
361 }
362
363 for (i = 0; i < kinfo->num_tqps; i++) {
364 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
365 struct hclge_tqp, q);
0c218123 366 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
46a3df9f
S		 367 tqp->index);
368 buff = buff + ETH_GSTRING_LEN;
369 }
370
371 return buff;
372}
373
374static u64 *hclge_comm_get_stats(void *comm_stats,
375 const struct hclge_comm_stats_str strs[],
376 int size, u64 *data)
377{
378 u64 *buf = data;
379 u32 i;
380
381 for (i = 0; i < size; i++)
382 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
383
384 return buf + size;
385}
386
387static u8 *hclge_comm_get_strings(u32 stringset,
388 const struct hclge_comm_stats_str strs[],
389 int size, u8 *data)
390{
391 char *buff = (char *)data;
392 u32 i;
393
394 if (stringset != ETH_SS_STATS)
395 return buff;
396
397 for (i = 0; i < size; i++) {
398 snprintf(buff, ETH_GSTRING_LEN,
399 strs[i].desc);
400 buff = buff + ETH_GSTRING_LEN;
401 }
402
403 return (u8 *)buff;
404}
405
406static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
407 struct net_device_stats *net_stats)
408{
409 net_stats->tx_dropped = 0;
200a88c6 410 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 411 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
a6c51c26 412 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 413
414 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
415 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
416
a6c51c26 417 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 418 net_stats->rx_length_errors =
419 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
420 net_stats->rx_length_errors +=
200a88c6 421 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 422 net_stats->rx_over_errors =
200a88c6 423 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 424}
425
426static void hclge_update_stats_for_all(struct hclge_dev *hdev)
427{
428 struct hnae3_handle *handle;
429 int status;
430
431 handle = &hdev->vport[0].nic;
432 if (handle->client) {
433 status = hclge_tqps_update_stats(handle);
434 if (status) {
435 dev_err(&hdev->pdev->dev,
436 "Update TQPS stats fail, status = %d.\n",
437 status);
438 }
439 }
440
441 status = hclge_mac_update_stats(hdev);
442 if (status)
443 dev_err(&hdev->pdev->dev,
444 "Update MAC stats fail, status = %d.\n", status);
445
46a3df9f
S		 446 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
447}
448
449static void hclge_update_stats(struct hnae3_handle *handle,
450 struct net_device_stats *net_stats)
451{
452 struct hclge_vport *vport = hclge_get_vport(handle);
453 struct hclge_dev *hdev = vport->back;
454 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
455 int status;
456
c5f65480
JS		 457 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
458 return;
459
46a3df9f
S		 460 status = hclge_mac_update_stats(hdev);
461 if (status)
462 dev_err(&hdev->pdev->dev,
463 "Update MAC stats fail, status = %d.\n",
464 status);
465
46a3df9f
S		 466 status = hclge_tqps_update_stats(handle);
467 if (status)
468 dev_err(&hdev->pdev->dev,
469 "Update TQPS stats fail, status = %d.\n",
470 status);
471
472 hclge_update_netstat(hw_stats, net_stats);
c5f65480
JS		 473
474 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 475}
476
477static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
478{
4dc13b96
FL		 479#define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\
480 HNAE3_SUPPORT_PHY_LOOPBACK |\
481 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\
482 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
46a3df9f
S		 483
484 struct hclge_vport *vport = hclge_get_vport(handle);
485 struct hclge_dev *hdev = vport->back;
486 int count = 0;
487
488 /* Loopback test support rules:
489 * mac: only GE mode support
490 * serdes: all mac mode will support include GE/XGE/LGE/CGE
491 * phy: only support when phy device exist on board
492 */
493 if (stringset == ETH_SS_TEST) {
494 /* clear loopback bit flags at first */
495 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
4dc13b96
FL		 496 if (hdev->pdev->revision >= HNAE3_REVISION_ID_21 ||
497 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
46a3df9f
S		 498 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
499 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
500 count += 1;
eb66d503 501 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
46a3df9f 502 }
5fd50ac3 503
4dc13b96
FL		 504 count += 2;
505 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
506 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
46a3df9f
S		 507 } else if (stringset == ETH_SS_STATS) {
508 count = ARRAY_SIZE(g_mac_stats_string) +
46a3df9f
S		 509 hclge_tqps_get_sset_count(handle, stringset);
510 }
511
512 return count;
513}
514
515static void hclge_get_strings(struct hnae3_handle *handle,
516 u32 stringset,
517 u8 *data)
518{
519 u8 *p = (char *)data;
520 int size;
521
522 if (stringset == ETH_SS_STATS) {
523 size = ARRAY_SIZE(g_mac_stats_string);
524 p = hclge_comm_get_strings(stringset,
525 g_mac_stats_string,
526 size,
527 p);
46a3df9f
S		 528 p = hclge_tqps_get_strings(handle, p);
529 } else if (stringset == ETH_SS_TEST) {
eb66d503 530 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
46a3df9f 531 memcpy(p,
eb66d503 532 hns3_nic_test_strs[HNAE3_LOOP_APP],
46a3df9f
S		 533 ETH_GSTRING_LEN);
534 p += ETH_GSTRING_LEN;
535 }
4dc13b96 536 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
46a3df9f 537 memcpy(p,
4dc13b96
FL		 538 hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
539 ETH_GSTRING_LEN);
540 p += ETH_GSTRING_LEN;
541 }
542 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
543 memcpy(p,
544 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
46a3df9f
S		 545 ETH_GSTRING_LEN);
546 p += ETH_GSTRING_LEN;
547 }
548 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
549 memcpy(p,
a7b687b3 550 hns3_nic_test_strs[HNAE3_LOOP_PHY],
46a3df9f
S		 551 ETH_GSTRING_LEN);
552 p += ETH_GSTRING_LEN;
553 }
554 }
555}
556
557static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
558{
559 struct hclge_vport *vport = hclge_get_vport(handle);
560 struct hclge_dev *hdev = vport->back;
561 u64 *p;
562
563 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
564 g_mac_stats_string,
565 ARRAY_SIZE(g_mac_stats_string),
566 data);
46a3df9f
S		 567 p = hclge_tqps_get_stats(handle, p);
568}
569
570static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 571 struct hclge_func_status_cmd *status)
46a3df9f
S		 572{
573 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
574 return -EINVAL;
575
576 /* Set the pf to main pf */
577 if (status->pf_state & HCLGE_PF_STATE_MAIN)
578 hdev->flag |= HCLGE_FLAG_MAIN;
579 else
580 hdev->flag &= ~HCLGE_FLAG_MAIN;
581
46a3df9f
S		 582 return 0;
583}
584
585static int hclge_query_function_status(struct hclge_dev *hdev)
586{
d44f9b63 587 struct hclge_func_status_cmd *req;
46a3df9f
S		 588 struct hclge_desc desc;
589 int timeout = 0;
590 int ret;
591
592 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 593 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 594
595 do {
596 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
597 if (ret) {
598 dev_err(&hdev->pdev->dev,
599 "query function status failed %d.\n",
600 ret);
601
602 return ret;
603 }
604
605 /* Check pf reset is done */
606 if (req->pf_state)
607 break;
608 usleep_range(1000, 2000);
609 } while (timeout++ < 5);
610
611 ret = hclge_parse_func_status(hdev, req);
612
613 return ret;
614}
615
616static int hclge_query_pf_resource(struct hclge_dev *hdev)
617{
d44f9b63 618 struct hclge_pf_res_cmd *req;
46a3df9f
S		 619 struct hclge_desc desc;
620 int ret;
621
622 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
623 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
624 if (ret) {
625 dev_err(&hdev->pdev->dev,
626 "query pf resource failed %d.\n", ret);
627 return ret;
628 }
629
d44f9b63 630 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 631 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
632 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
633
e92a0843 634 if (hnae3_dev_roce_supported(hdev)) {
375dd5e4
JS		 635 hdev->roce_base_msix_offset =
636 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
637 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
887c3820 638 hdev->num_roce_msi =
e4e87715
PL		 639 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
640 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 641
642 /* PF should have NIC vectors and Roce vectors,
643 * NIC vectors are queued before Roce vectors.
644 */
375dd5e4
JS		 645 hdev->num_msi = hdev->num_roce_msi +
646 hdev->roce_base_msix_offset;
46a3df9f
S		 647 } else {
648 hdev->num_msi =
e4e87715
PL		 649 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
650 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 651 }
652
653 return 0;
654}
655
656static int hclge_parse_speed(int speed_cmd, int *speed)
657{
658 switch (speed_cmd) {
659 case 6:
660 *speed = HCLGE_MAC_SPEED_10M;
661 break;
662 case 7:
663 *speed = HCLGE_MAC_SPEED_100M;
664 break;
665 case 0:
666 *speed = HCLGE_MAC_SPEED_1G;
667 break;
668 case 1:
669 *speed = HCLGE_MAC_SPEED_10G;
670 break;
671 case 2:
672 *speed = HCLGE_MAC_SPEED_25G;
673 break;
674 case 3:
675 *speed = HCLGE_MAC_SPEED_40G;
676 break;
677 case 4:
678 *speed = HCLGE_MAC_SPEED_50G;
679 break;
680 case 5:
681 *speed = HCLGE_MAC_SPEED_100G;
682 break;
683 default:
684 return -EINVAL;
685 }
686
687 return 0;
688}
689
0979aa0b
FL		 690static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
691 u8 speed_ability)
692{
693 unsigned long *supported = hdev->hw.mac.supported;
694
695 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
696 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
697 supported);
698
699 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
700 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
701 supported);
702
703 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
704 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
705 supported);
706
707 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
708 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
709 supported);
710
711 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
712 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
713 supported);
714
715 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
716 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
717}
718
719static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
720{
721 u8 media_type = hdev->hw.mac.media_type;
722
723 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
724 return;
725
726 hclge_parse_fiber_link_mode(hdev, speed_ability);
727}
728
46a3df9f
S		 729static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
730{
d44f9b63 731 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 732 u64 mac_addr_tmp_high;
733 u64 mac_addr_tmp;
734 int i;
735
d44f9b63 736 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 737
738 /* get the configuration */
e4e87715
PL		 739 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
740 HCLGE_CFG_VMDQ_M,
741 HCLGE_CFG_VMDQ_S);
742 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
743 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
744 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
745 HCLGE_CFG_TQP_DESC_N_M,
746 HCLGE_CFG_TQP_DESC_N_S);
747
748 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
749 HCLGE_CFG_PHY_ADDR_M,
750 HCLGE_CFG_PHY_ADDR_S);
751 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
752 HCLGE_CFG_MEDIA_TP_M,
753 HCLGE_CFG_MEDIA_TP_S);
754 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
755 HCLGE_CFG_RX_BUF_LEN_M,
756 HCLGE_CFG_RX_BUF_LEN_S);
46a3df9f
S		 757 /* get mac_address */
758 mac_addr_tmp = __le32_to_cpu(req->param[2]);
e4e87715
PL		 759 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
760 HCLGE_CFG_MAC_ADDR_H_M,
761 HCLGE_CFG_MAC_ADDR_H_S);
46a3df9f
S		 762
763 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
764
e4e87715
PL		 765 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
766 HCLGE_CFG_DEFAULT_SPEED_M,
767 HCLGE_CFG_DEFAULT_SPEED_S);
768 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
769 HCLGE_CFG_RSS_SIZE_M,
770 HCLGE_CFG_RSS_SIZE_S);
0e7a40cd 771
46a3df9f
S		 772 for (i = 0; i < ETH_ALEN; i++)
773 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
774
d44f9b63 775 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 776 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
0979aa0b 777
e4e87715
PL		 778 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
779 HCLGE_CFG_SPEED_ABILITY_M,
780 HCLGE_CFG_SPEED_ABILITY_S);
46a3df9f
S		 781}
782
783/* hclge_get_cfg: query the static parameter from flash
784 * @hdev: pointer to struct hclge_dev
785 * @hcfg: the config structure to be getted
786 */
787static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
788{
789 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 790 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 791 int i, ret;
792
793 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 794 u32 offset = 0;
795
d44f9b63 796 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 797 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
798 true);
e4e87715
PL		 799 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
800 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
46a3df9f 801 /* Len should be united by 4 bytes when send to hardware */
e4e87715
PL		 802 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
803 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 804 req->offset = cpu_to_le32(offset);
46a3df9f
S		 805 }
806
807 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
808 if (ret) {
3f639907 809 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
46a3df9f
S		 810 return ret;
811 }
812
813 hclge_parse_cfg(hcfg, desc);
3f639907 814
46a3df9f
S		 815 return 0;
816}
817
818static int hclge_get_cap(struct hclge_dev *hdev)
819{
820 int ret;
821
822 ret = hclge_query_function_status(hdev);
823 if (ret) {
824 dev_err(&hdev->pdev->dev,
825 "query function status error %d.\n", ret);
826 return ret;
827 }
828
829 /* get pf resource */
830 ret = hclge_query_pf_resource(hdev);
3f639907
JS		 831 if (ret)
832 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
46a3df9f 833
3f639907 834 return ret;
46a3df9f
S		 835}
836
837static int hclge_configure(struct hclge_dev *hdev)
838{
839 struct hclge_cfg cfg;
840 int ret, i;
841
842 ret = hclge_get_cfg(hdev, &cfg);
843 if (ret) {
844 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
845 return ret;
846 }
847
848 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
849 hdev->base_tqp_pid = 0;
0e7a40cd 850 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 851 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 852 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 853 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 854 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 855 hdev->num_desc = cfg.tqp_desc_num;
856 hdev->tm_info.num_pg = 1;
cacde272 857 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 858 hdev->tm_info.hw_pfc_map = 0;
859
860 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
861 if (ret) {
862 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
863 return ret;
864 }
865
0979aa0b
FL		 866 hclge_parse_link_mode(hdev, cfg.speed_ability);
867
cacde272
YL		 868 if ((hdev->tc_max > HNAE3_MAX_TC) ||
869 (hdev->tc_max < 1)) {
46a3df9f 870 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 871 hdev->tc_max);
872 hdev->tc_max = 1;
46a3df9f
S		 873 }
874
cacde272
YL		 875 /* Dev does not support DCB */
876 if (!hnae3_dev_dcb_supported(hdev)) {
877 hdev->tc_max = 1;
878 hdev->pfc_max = 0;
879 } else {
880 hdev->pfc_max = hdev->tc_max;
881 }
882
883 hdev->tm_info.num_tc = hdev->tc_max;
884
46a3df9f 885 /* Currently not support uncontiuous tc */
cacde272 886 for (i = 0; i < hdev->tm_info.num_tc; i++)
e4e87715 887 hnae3_set_bit(hdev->hw_tc_map, i, 1);
46a3df9f 888
71b83869 889 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 890
891 return ret;
892}
893
894static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
895 int tso_mss_max)
896{
d44f9b63 897 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 898 struct hclge_desc desc;
a90bb9a5 899 u16 tso_mss;
46a3df9f
S		 900
901 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
902
d44f9b63 903 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 904
905 tso_mss = 0;
e4e87715
PL		 906 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
907 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 908 req->tso_mss_min = cpu_to_le16(tso_mss);
909
910 tso_mss = 0;
e4e87715
PL		 911 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
912 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 913 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 914
915 return hclge_cmd_send(&hdev->hw, &desc, 1);
916}
917
918static int hclge_alloc_tqps(struct hclge_dev *hdev)
919{
920 struct hclge_tqp *tqp;
921 int i;
922
923 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
924 sizeof(struct hclge_tqp), GFP_KERNEL);
925 if (!hdev->htqp)
926 return -ENOMEM;
927
928 tqp = hdev->htqp;
929
930 for (i = 0; i < hdev->num_tqps; i++) {
931 tqp->dev = &hdev->pdev->dev;
932 tqp->index = i;
933
934 tqp->q.ae_algo = &ae_algo;
935 tqp->q.buf_size = hdev->rx_buf_len;
936 tqp->q.desc_num = hdev->num_desc;
937 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
938 i * HCLGE_TQP_REG_SIZE;
939
940 tqp++;
941 }
942
943 return 0;
944}
945
946static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
947 u16 tqp_pid, u16 tqp_vid, bool is_pf)
948{
d44f9b63 949 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 950 struct hclge_desc desc;
951 int ret;
952
953 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
954
d44f9b63 955 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 956 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 957 req->tqp_vf = func_id;
46a3df9f
S		 958 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
959 1 << HCLGE_TQP_MAP_EN_B;
960 req->tqp_vid = cpu_to_le16(tqp_vid);
961
962 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907
JS		 963 if (ret)
964 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
46a3df9f 965
3f639907 966 return ret;
46a3df9f
S		 967}
968
128b900d 969static int hclge_assign_tqp(struct hclge_vport *vport)
46a3df9f 970{
128b900d 971 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
46a3df9f 972 struct hclge_dev *hdev = vport->back;
7df7dad6 973 int i, alloced;
46a3df9f
S		 974
975 for (i = 0, alloced = 0; i < hdev->num_tqps &&
128b900d 976 alloced < kinfo->num_tqps; i++) {
46a3df9f
S		 977 if (!hdev->htqp[i].alloced) {
978 hdev->htqp[i].q.handle = &vport->nic;
979 hdev->htqp[i].q.tqp_index = alloced;
128b900d
YL		 980 hdev->htqp[i].q.desc_num = kinfo->num_desc;
981 kinfo->tqp[alloced] = &hdev->htqp[i].q;
46a3df9f 982 hdev->htqp[i].alloced = true;
46a3df9f
S		 983 alloced++;
984 }
985 }
128b900d 986 vport->alloc_tqps = kinfo->num_tqps;
46a3df9f
S		 987
988 return 0;
989}
990
128b900d
YL		 991static int hclge_knic_setup(struct hclge_vport *vport,
992 u16 num_tqps, u16 num_desc)
46a3df9f
S		 993{
994 struct hnae3_handle *nic = &vport->nic;
995 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
996 struct hclge_dev *hdev = vport->back;
997 int i, ret;
998
128b900d 999 kinfo->num_desc = num_desc;
46a3df9f
S		 1000 kinfo->rx_buf_len = hdev->rx_buf_len;
1001 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1002 kinfo->rss_size
1003 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1004 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1005
1006 for (i = 0; i < HNAE3_MAX_TC; i++) {
1007 if (hdev->hw_tc_map & BIT(i)) {
1008 kinfo->tc_info[i].enable = true;
1009 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1010 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1011 kinfo->tc_info[i].tc = i;
1012 } else {
1013 /* Set to default queue if TC is disable */
1014 kinfo->tc_info[i].enable = false;
1015 kinfo->tc_info[i].tqp_offset = 0;
1016 kinfo->tc_info[i].tqp_count = 1;
1017 kinfo->tc_info[i].tc = 0;
1018 }
1019 }
1020
1021 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1022 sizeof(struct hnae3_queue *), GFP_KERNEL);
1023 if (!kinfo->tqp)
1024 return -ENOMEM;
1025
128b900d 1026 ret = hclge_assign_tqp(vport);
3f639907 1027 if (ret)
46a3df9f 1028 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
46a3df9f 1029
3f639907 1030 return ret;
46a3df9f
S		 1031}
1032
7df7dad6
L		 1033static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1034 struct hclge_vport *vport)
1035{
1036 struct hnae3_handle *nic = &vport->nic;
1037 struct hnae3_knic_private_info *kinfo;
1038 u16 i;
1039
1040 kinfo = &nic->kinfo;
1041 for (i = 0; i < kinfo->num_tqps; i++) {
1042 struct hclge_tqp *q =
1043 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1044 bool is_pf;
1045 int ret;
1046
1047 is_pf = !(vport->vport_id);
1048 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1049 i, is_pf);
1050 if (ret)
1051 return ret;
1052 }
1053
1054 return 0;
1055}
1056
1057static int hclge_map_tqp(struct hclge_dev *hdev)
1058{
1059 struct hclge_vport *vport = hdev->vport;
1060 u16 i, num_vport;
1061
1062 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1063 for (i = 0; i < num_vport; i++) {
1064 int ret;
1065
1066 ret = hclge_map_tqp_to_vport(hdev, vport);
1067 if (ret)
1068 return ret;
1069
1070 vport++;
1071 }
1072
1073 return 0;
1074}
1075
46a3df9f
S		 1076static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1077{
1078 /* this would be initialized later */
1079}
1080
1081static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1082{
1083 struct hnae3_handle *nic = &vport->nic;
1084 struct hclge_dev *hdev = vport->back;
1085 int ret;
1086
1087 nic->pdev = hdev->pdev;
1088 nic->ae_algo = &ae_algo;
1089 nic->numa_node_mask = hdev->numa_node_mask;
1090
1091 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
128b900d 1092 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
46a3df9f
S		 1093 if (ret) {
1094 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1095 ret);
1096 return ret;
1097 }
1098 } else {
1099 hclge_unic_setup(vport, num_tqps);
1100 }
1101
1102 return 0;
1103}
1104
1105static int hclge_alloc_vport(struct hclge_dev *hdev)
1106{
1107 struct pci_dev *pdev = hdev->pdev;
1108 struct hclge_vport *vport;
1109 u32 tqp_main_vport;
1110 u32 tqp_per_vport;
1111 int num_vport, i;
1112 int ret;
1113
1114 /* We need to alloc a vport for main NIC of PF */
1115 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1116
38e62046
HT		 1117 if (hdev->num_tqps < num_vport) {
1118 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1119 hdev->num_tqps, num_vport);
1120 return -EINVAL;
1121 }
46a3df9f
S		 1122
1123 /* Alloc the same number of TQPs for every vport */
1124 tqp_per_vport = hdev->num_tqps / num_vport;
1125 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1126
1127 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1128 GFP_KERNEL);
1129 if (!vport)
1130 return -ENOMEM;
1131
1132 hdev->vport = vport;
1133 hdev->num_alloc_vport = num_vport;
1134
2312e050
FL		 1135 if (IS_ENABLED(CONFIG_PCI_IOV))
1136 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1137
1138 for (i = 0; i < num_vport; i++) {
1139 vport->back = hdev;
1140 vport->vport_id = i;
1141
1142 if (i == 0)
1143 ret = hclge_vport_setup(vport, tqp_main_vport);
1144 else
1145 ret = hclge_vport_setup(vport, tqp_per_vport);
1146 if (ret) {
1147 dev_err(&pdev->dev,
1148 "vport setup failed for vport %d, %d\n",
1149 i, ret);
1150 return ret;
1151 }
1152
1153 vport++;
1154 }
1155
1156 return 0;
1157}
1158
acf61ecd
YL		 1159static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1160 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1161{
1162/* TX buffer size is unit by 128 byte */
1163#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1164#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1165 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1166 struct hclge_desc desc;
1167 int ret;
1168 u8 i;
1169
d44f9b63 1170 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1171
1172 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1173 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1174 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1175
46a3df9f
S		 1176 req->tx_pkt_buff[i] =
1177 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1178 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1179 }
46a3df9f
S		 1180
1181 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1182 if (ret)
46a3df9f
S		 1183 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1184 ret);
46a3df9f 1185
3f639907 1186 return ret;
46a3df9f
S		 1187}
1188
acf61ecd
YL		 1189static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1190 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1191{
acf61ecd 1192 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f 1193
3f639907
JS		 1194 if (ret)
1195 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
46a3df9f 1196
3f639907 1197 return ret;
46a3df9f
S		 1198}
1199
1200static int hclge_get_tc_num(struct hclge_dev *hdev)
1201{
1202 int i, cnt = 0;
1203
1204 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1205 if (hdev->hw_tc_map & BIT(i))
1206 cnt++;
1207 return cnt;
1208}
1209
1210static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1211{
1212 int i, cnt = 0;
1213
1214 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1215 if (hdev->hw_tc_map & BIT(i) &&
1216 hdev->tm_info.hw_pfc_map & BIT(i))
1217 cnt++;
1218 return cnt;
1219}
1220
1221/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1222static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1223 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1224{
1225 struct hclge_priv_buf *priv;
1226 int i, cnt = 0;
1227
1228 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1229 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1230 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1231 priv->enable)
1232 cnt++;
1233 }
1234
1235 return cnt;
1236}
1237
1238/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1239static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1240 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1241{
1242 struct hclge_priv_buf *priv;
1243 int i, cnt = 0;
1244
1245 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1246 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1247 if (hdev->hw_tc_map & BIT(i) &&
1248 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1249 priv->enable)
1250 cnt++;
1251 }
1252
1253 return cnt;
1254}
1255
acf61ecd 1256static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1257{
1258 struct hclge_priv_buf *priv;
1259 u32 rx_priv = 0;
1260 int i;
1261
1262 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1263 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1264 if (priv->enable)
1265 rx_priv += priv->buf_size;
1266 }
1267 return rx_priv;
1268}
1269
acf61ecd 1270static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1271{
1272 u32 i, total_tx_size = 0;
1273
1274 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1275 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1276
1277 return total_tx_size;
1278}
1279
acf61ecd
YL		 1280static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1281 struct hclge_pkt_buf_alloc *buf_alloc,
1282 u32 rx_all)
46a3df9f
S		 1283{
1284 u32 shared_buf_min, shared_buf_tc, shared_std;
1285 int tc_num, pfc_enable_num;
1286 u32 shared_buf;
1287 u32 rx_priv;
1288 int i;
1289
1290 tc_num = hclge_get_tc_num(hdev);
1291 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1292
d221df4e
YL		 1293 if (hnae3_dev_dcb_supported(hdev))
1294 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1295 else
1296 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1297
46a3df9f
S		 1298 shared_buf_tc = pfc_enable_num * hdev->mps +
1299 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1300 hdev->mps;
1301 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1302
acf61ecd 1303 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1304 if (rx_all <= rx_priv + shared_std)
1305 return false;
1306
1307 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1308 buf_alloc->s_buf.buf_size = shared_buf;
1309 buf_alloc->s_buf.self.high = shared_buf;
1310 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1311
1312 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1313 if ((hdev->hw_tc_map & BIT(i)) &&
1314 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1315 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1316 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1317 } else {
acf61ecd
YL		 1318 buf_alloc->s_buf.tc_thrd[i].low = 0;
1319 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1320 }
1321 }
1322
1323 return true;
1324}
1325
acf61ecd
YL		 1326static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1327 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1328{
1329 u32 i, total_size;
1330
1331 total_size = hdev->pkt_buf_size;
1332
1333 /* alloc tx buffer for all enabled tc */
1334 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1335 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1336
1337 if (total_size < HCLGE_DEFAULT_TX_BUF)
1338 return -ENOMEM;
1339
1340 if (hdev->hw_tc_map & BIT(i))
1341 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1342 else
1343 priv->tx_buf_size = 0;
1344
1345 total_size -= priv->tx_buf_size;
1346 }
1347
1348 return 0;
1349}
1350
46a3df9f
S		 1351/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1352 * @hdev: pointer to struct hclge_dev
acf61ecd 1353 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1354 * @return: 0: calculate sucessful, negative: fail
1355 */
1db9b1bf
YL		 1356static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1357 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1358{
996ff918
YL		 1359#define HCLGE_BUF_SIZE_UNIT 128
1360 u32 rx_all = hdev->pkt_buf_size, aligned_mps;
46a3df9f
S		 1361 int no_pfc_priv_num, pfc_priv_num;
1362 struct hclge_priv_buf *priv;
1363 int i;
1364
996ff918 1365 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
acf61ecd 1366 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1367
d602a525
YL		 1368 /* When DCB is not supported, rx private
1369 * buffer is not allocated.
1370 */
1371 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1372 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1373 return -ENOMEM;
1374
1375 return 0;
1376 }
1377
46a3df9f
S		 1378 /* step 1, try to alloc private buffer for all enabled tc */
1379 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1380 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1381 if (hdev->hw_tc_map & BIT(i)) {
1382 priv->enable = 1;
1383 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
996ff918
YL		 1384 priv->wl.low = aligned_mps;
1385 priv->wl.high = priv->wl.low + aligned_mps;
46a3df9f
S		 1386 priv->buf_size = priv->wl.high +
1387 HCLGE_DEFAULT_DV;
1388 } else {
1389 priv->wl.low = 0;
996ff918 1390 priv->wl.high = 2 * aligned_mps;
46a3df9f
S		 1391 priv->buf_size = priv->wl.high;
1392 }
bb1fe9ea
YL		 1393 } else {
1394 priv->enable = 0;
1395 priv->wl.low = 0;
1396 priv->wl.high = 0;
1397 priv->buf_size = 0;
46a3df9f
S		 1398 }
1399 }
1400
acf61ecd 1401 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1402 return 0;
1403
1404 /* step 2, try to decrease the buffer size of
1405 * no pfc TC's private buffer
1406 */
1407 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1408 priv = &buf_alloc->priv_buf[i];
46a3df9f 1409
bb1fe9ea
YL		 1410 priv->enable = 0;
1411 priv->wl.low = 0;
1412 priv->wl.high = 0;
1413 priv->buf_size = 0;
1414
1415 if (!(hdev->hw_tc_map & BIT(i)))
1416 continue;
1417
1418 priv->enable = 1;
46a3df9f
S		 1419
1420 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1421 priv->wl.low = 128;
996ff918 1422 priv->wl.high = priv->wl.low + aligned_mps;
46a3df9f
S		 1423 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1424 } else {
1425 priv->wl.low = 0;
996ff918 1426 priv->wl.high = aligned_mps;
46a3df9f
S		 1427 priv->buf_size = priv->wl.high;
1428 }
1429 }
1430
acf61ecd 1431 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1432 return 0;
1433
1434 /* step 3, try to reduce the number of pfc disabled TCs,
1435 * which have private buffer
1436 */
1437 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1438 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1439
1440 /* let the last to be cleared first */
1441 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1442 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1443
1444 if (hdev->hw_tc_map & BIT(i) &&
1445 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1446 /* Clear the no pfc TC private buffer */
1447 priv->wl.low = 0;
1448 priv->wl.high = 0;
1449 priv->buf_size = 0;
1450 priv->enable = 0;
1451 no_pfc_priv_num--;
1452 }
1453
acf61ecd 1454 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1455 no_pfc_priv_num == 0)
1456 break;
1457 }
1458
acf61ecd 1459 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1460 return 0;
1461
1462 /* step 4, try to reduce the number of pfc enabled TCs
1463 * which have private buffer.
1464 */
acf61ecd 1465 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1466
1467 /* let the last to be cleared first */
1468 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1469 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1470
1471 if (hdev->hw_tc_map & BIT(i) &&
1472 hdev->tm_info.hw_pfc_map & BIT(i)) {
1473 /* Reduce the number of pfc TC with private buffer */
1474 priv->wl.low = 0;
1475 priv->enable = 0;
1476 priv->wl.high = 0;
1477 priv->buf_size = 0;
1478 pfc_priv_num--;
1479 }
1480
acf61ecd 1481 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1482 pfc_priv_num == 0)
1483 break;
1484 }
acf61ecd 1485 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1486 return 0;
1487
1488 return -ENOMEM;
1489}
1490
acf61ecd
YL		 1491static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1492 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1493{
d44f9b63 1494 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1495 struct hclge_desc desc;
1496 int ret;
1497 int i;
1498
1499 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1500 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1501
1502 /* Alloc private buffer TCs */
1503 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1504 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1505
1506 req->buf_num[i] =
1507 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1508 req->buf_num[i] |=
5bca3b94 1509 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1510 }
1511
b8c8bf47 1512 req->shared_buf =
acf61ecd 1513 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1514 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1515
46a3df9f 1516 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1517 if (ret)
46a3df9f
S		 1518 dev_err(&hdev->pdev->dev,
1519 "rx private buffer alloc cmd failed %d\n", ret);
46a3df9f 1520
3f639907 1521 return ret;
46a3df9f
S		 1522}
1523
acf61ecd
YL		 1524static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1525 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1526{
1527 struct hclge_rx_priv_wl_buf *req;
1528 struct hclge_priv_buf *priv;
1529 struct hclge_desc desc[2];
1530 int i, j;
1531 int ret;
1532
1533 for (i = 0; i < 2; i++) {
1534 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1535 false);
1536 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1537
1538 /* The first descriptor set the NEXT bit to 1 */
1539 if (i == 0)
1540 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1541 else
1542 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1543
1544 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1545 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1546
1547 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1548 req->tc_wl[j].high =
1549 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1550 req->tc_wl[j].high |=
3738287c 1551 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1552 req->tc_wl[j].low =
1553 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1554 req->tc_wl[j].low |=
3738287c 1555 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1556 }
1557 }
1558
1559 /* Send 2 descriptor at one time */
1560 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3f639907 1561 if (ret)
46a3df9f
S		 1562 dev_err(&hdev->pdev->dev,
1563 "rx private waterline config cmd failed %d\n",
1564 ret);
3f639907 1565 return ret;
46a3df9f
S		 1566}
1567
acf61ecd
YL		 1568static int hclge_common_thrd_config(struct hclge_dev *hdev,
1569 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1570{
acf61ecd 1571 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1572 struct hclge_rx_com_thrd *req;
1573 struct hclge_desc desc[2];
1574 struct hclge_tc_thrd *tc;
1575 int i, j;
1576 int ret;
1577
1578 for (i = 0; i < 2; i++) {
1579 hclge_cmd_setup_basic_desc(&desc[i],
1580 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1581 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1582
1583 /* The first descriptor set the NEXT bit to 1 */
1584 if (i == 0)
1585 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1586 else
1587 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1588
1589 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1590 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1591
1592 req->com_thrd[j].high =
1593 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1594 req->com_thrd[j].high |=
3738287c 1595 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1596 req->com_thrd[j].low =
1597 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1598 req->com_thrd[j].low |=
3738287c 1599 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1600 }
1601 }
1602
1603 /* Send 2 descriptors at one time */
1604 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3f639907 1605 if (ret)
46a3df9f
S		 1606 dev_err(&hdev->pdev->dev,
1607 "common threshold config cmd failed %d\n", ret);
3f639907 1608 return ret;
46a3df9f
S		 1609}
1610
acf61ecd
YL		 1611static int hclge_common_wl_config(struct hclge_dev *hdev,
1612 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1613{
acf61ecd 1614 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1615 struct hclge_rx_com_wl *req;
1616 struct hclge_desc desc;
1617 int ret;
1618
1619 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1620
1621 req = (struct hclge_rx_com_wl *)desc.data;
1622 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
3738287c 1623 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1624
1625 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
3738287c 1626 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1627
1628 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1629 if (ret)
46a3df9f
S		 1630 dev_err(&hdev->pdev->dev,
1631 "common waterline config cmd failed %d\n", ret);
46a3df9f 1632
3f639907 1633 return ret;
46a3df9f
S		 1634}
1635
1636int hclge_buffer_alloc(struct hclge_dev *hdev)
1637{
acf61ecd 1638 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1639 int ret;
1640
acf61ecd
YL		 1641 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1642 if (!pkt_buf)
46a3df9f
S		 1643 return -ENOMEM;
1644
acf61ecd 1645 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1646 if (ret) {
1647 dev_err(&hdev->pdev->dev,
1648 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1649 goto out;
9ffe79a9
YL		 1650 }
1651
acf61ecd 1652 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1653 if (ret) {
1654 dev_err(&hdev->pdev->dev,
1655 "could not alloc tx buffers %d\n", ret);
acf61ecd 1656 goto out;
46a3df9f
S		 1657 }
1658
acf61ecd 1659 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1660 if (ret) {
1661 dev_err(&hdev->pdev->dev,
1662 "could not calc rx priv buffer size for all TCs %d\n",
1663 ret);
acf61ecd 1664 goto out;
46a3df9f
S		 1665 }
1666
acf61ecd 1667 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1668 if (ret) {
1669 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1670 ret);
acf61ecd 1671 goto out;
46a3df9f
S		 1672 }
1673
2daf4a65 1674 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1675 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1676 if (ret) {
1677 dev_err(&hdev->pdev->dev,
1678 "could not configure rx private waterline %d\n",
1679 ret);
acf61ecd 1680 goto out;
2daf4a65 1681 }
46a3df9f 1682
acf61ecd 1683 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1684 if (ret) {
1685 dev_err(&hdev->pdev->dev,
1686 "could not configure common threshold %d\n",
1687 ret);
acf61ecd 1688 goto out;
2daf4a65 1689 }
46a3df9f
S		 1690 }
1691
acf61ecd
YL		 1692 ret = hclge_common_wl_config(hdev, pkt_buf);
1693 if (ret)
46a3df9f
S		 1694 dev_err(&hdev->pdev->dev,
1695 "could not configure common waterline %d\n", ret);
46a3df9f 1696
acf61ecd
YL		 1697out:
1698 kfree(pkt_buf);
1699 return ret;
46a3df9f
S		 1700}
1701
1702static int hclge_init_roce_base_info(struct hclge_vport *vport)
1703{
1704 struct hnae3_handle *roce = &vport->roce;
1705 struct hnae3_handle *nic = &vport->nic;
1706
887c3820 1707 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 1708
1709 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1710 vport->back->num_msi_left == 0)
1711 return -EINVAL;
1712
1713 roce->rinfo.base_vector = vport->back->roce_base_vector;
1714
1715 roce->rinfo.netdev = nic->kinfo.netdev;
1716 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1717
1718 roce->pdev = nic->pdev;
1719 roce->ae_algo = nic->ae_algo;
1720 roce->numa_node_mask = nic->numa_node_mask;
1721
1722 return 0;
1723}
1724
887c3820 1725static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 1726{
1727 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 1728 int vectors;
1729 int i;
46a3df9f 1730
887c3820
SM		 1731 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1732 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1733 if (vectors < 0) {
1734 dev_err(&pdev->dev,
1735 "failed(%d) to allocate MSI/MSI-X vectors\n",
1736 vectors);
1737 return vectors;
46a3df9f 1738 }
887c3820
SM		 1739 if (vectors < hdev->num_msi)
1740 dev_warn(&hdev->pdev->dev,
1741 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1742 hdev->num_msi, vectors);
46a3df9f 1743
887c3820
SM		 1744 hdev->num_msi = vectors;
1745 hdev->num_msi_left = vectors;
1746 hdev->base_msi_vector = pdev->irq;
46a3df9f 1747 hdev->roce_base_vector = hdev->base_msi_vector +
375dd5e4 1748 hdev->roce_base_msix_offset;
46a3df9f 1749
46a3df9f
S		 1750 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1751 sizeof(u16), GFP_KERNEL);
887c3820
SM		 1752 if (!hdev->vector_status) {
1753 pci_free_irq_vectors(pdev);
46a3df9f 1754 return -ENOMEM;
887c3820 1755 }
46a3df9f
S		 1756
1757 for (i = 0; i < hdev->num_msi; i++)
1758 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1759
887c3820
SM		 1760 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1761 sizeof(int), GFP_KERNEL);
1762 if (!hdev->vector_irq) {
1763 pci_free_irq_vectors(pdev);
1764 return -ENOMEM;
46a3df9f 1765 }
46a3df9f
S		 1766
1767 return 0;
1768}
1769
2d03eacc 1770static u8 hclge_check_speed_dup(u8 duplex, int speed)
46a3df9f 1771{
46a3df9f 1772
2d03eacc
YL		 1773 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
1774 duplex = HCLGE_MAC_FULL;
46a3df9f 1775
2d03eacc 1776 return duplex;
46a3df9f
S		 1777}
1778
2d03eacc
YL		 1779static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1780 u8 duplex)
46a3df9f 1781{
d44f9b63 1782 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 1783 struct hclge_desc desc;
1784 int ret;
1785
d44f9b63 1786 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 1787
1788 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1789
e4e87715 1790 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
46a3df9f
S		 1791
1792 switch (speed) {
1793 case HCLGE_MAC_SPEED_10M:
e4e87715
PL		 1794 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1795 HCLGE_CFG_SPEED_S, 6);
46a3df9f
S		 1796 break;
1797 case HCLGE_MAC_SPEED_100M:
e4e87715
PL		 1798 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1799 HCLGE_CFG_SPEED_S, 7);
46a3df9f
S		 1800 break;
1801 case HCLGE_MAC_SPEED_1G:
e4e87715
PL		 1802 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1803 HCLGE_CFG_SPEED_S, 0);
46a3df9f
S		 1804 break;
1805 case HCLGE_MAC_SPEED_10G:
e4e87715
PL		 1806 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1807 HCLGE_CFG_SPEED_S, 1);
46a3df9f
S		 1808 break;
1809 case HCLGE_MAC_SPEED_25G:
e4e87715
PL		 1810 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1811 HCLGE_CFG_SPEED_S, 2);
46a3df9f
S		 1812 break;
1813 case HCLGE_MAC_SPEED_40G:
e4e87715
PL		 1814 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1815 HCLGE_CFG_SPEED_S, 3);
46a3df9f
S		 1816 break;
1817 case HCLGE_MAC_SPEED_50G:
e4e87715
PL		 1818 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1819 HCLGE_CFG_SPEED_S, 4);
46a3df9f
S		 1820 break;
1821 case HCLGE_MAC_SPEED_100G:
e4e87715
PL		 1822 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1823 HCLGE_CFG_SPEED_S, 5);
46a3df9f
S		 1824 break;
1825 default:
d7629e74 1826 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 1827 return -EINVAL;
1828 }
1829
e4e87715
PL		 1830 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1831 1);
46a3df9f
S		 1832
1833 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1834 if (ret) {
1835 dev_err(&hdev->pdev->dev,
1836 "mac speed/duplex config cmd failed %d.\n", ret);
1837 return ret;
1838 }
1839
2d03eacc
YL		 1840 return 0;
1841}
1842
1843int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1844{
1845 int ret;
1846
1847 duplex = hclge_check_speed_dup(duplex, speed);
1848 if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
1849 return 0;
1850
1851 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
1852 if (ret)
1853 return ret;
1854
1855 hdev->hw.mac.speed = speed;
1856 hdev->hw.mac.duplex = duplex;
46a3df9f
S		 1857
1858 return 0;
1859}
1860
1861static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1862 u8 duplex)
1863{
1864 struct hclge_vport *vport = hclge_get_vport(handle);
1865 struct hclge_dev *hdev = vport->back;
1866
1867 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1868}
1869
1870static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
1871 u8 *duplex)
1872{
d44f9b63 1873 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 1874 struct hclge_desc desc;
1875 int speed_tmp;
1876 int ret;
1877
d44f9b63 1878 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 1879
1880 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
1881 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1882 if (ret) {
1883 dev_err(&hdev->pdev->dev,
1884 "mac speed/autoneg/duplex query cmd failed %d\n",
1885 ret);
1886 return ret;
1887 }
1888
e4e87715
PL		 1889 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
1890 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
1891 HCLGE_QUERY_SPEED_S);
46a3df9f
S		 1892
1893 ret = hclge_parse_speed(speed_tmp, speed);
3f639907 1894 if (ret)
46a3df9f
S		 1895 dev_err(&hdev->pdev->dev,
1896 "could not parse speed(=%d), %d\n", speed_tmp, ret);
46a3df9f 1897
3f639907 1898 return ret;
46a3df9f
S		 1899}
1900
46a3df9f
S		 1901static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
1902{
d44f9b63 1903 struct hclge_config_auto_neg_cmd *req;
46a3df9f 1904 struct hclge_desc desc;
a90bb9a5 1905 u32 flag = 0;
46a3df9f
S		 1906 int ret;
1907
1908 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
1909
d44f9b63 1910 req = (struct hclge_config_auto_neg_cmd *)desc.data;
e4e87715 1911 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
a90bb9a5 1912 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 1913
1914 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1915 if (ret)
46a3df9f
S		 1916 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
1917 ret);
46a3df9f 1918
3f639907 1919 return ret;
46a3df9f
S		 1920}
1921
1922static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
1923{
1924 struct hclge_vport *vport = hclge_get_vport(handle);
1925 struct hclge_dev *hdev = vport->back;
1926
1927 return hclge_set_autoneg_en(hdev, enable);
1928}
1929
1930static int hclge_get_autoneg(struct hnae3_handle *handle)
1931{
1932 struct hclge_vport *vport = hclge_get_vport(handle);
1933 struct hclge_dev *hdev = vport->back;
27b5bf49
FL		 1934 struct phy_device *phydev = hdev->hw.mac.phydev;
1935
1936 if (phydev)
1937 return phydev->autoneg;
46a3df9f
S		 1938
1939 return hdev->hw.mac.autoneg;
1940}
1941
7564094c
PL		 1942static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev,
1943 bool mask_vlan,
1944 u8 *mac_mask)
1945{
1946 struct hclge_mac_vlan_mask_entry_cmd *req;
1947 struct hclge_desc desc;
1948 int status;
1949
1950 req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data;
1951 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false);
1952
e4e87715
PL		 1953 hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B,
1954 mask_vlan ? 1 : 0);
7564094c
PL		 1955 ether_addr_copy(req->mac_mask, mac_mask);
1956
1957 status = hclge_cmd_send(&hdev->hw, &desc, 1);
1958 if (status)
1959 dev_err(&hdev->pdev->dev,
1960 "Config mac_vlan_mask failed for cmd_send, ret =%d\n",
1961 status);
1962
1963 return status;
1964}
1965
46a3df9f
S		 1966static int hclge_mac_init(struct hclge_dev *hdev)
1967{
f9fd82a9
FL		 1968 struct hnae3_handle *handle = &hdev->vport[0].nic;
1969 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 1970 struct hclge_mac *mac = &hdev->hw.mac;
7564094c 1971 u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
40cca1c5 1972 struct hclge_vport *vport;
f9fd82a9 1973 int mtu;
46a3df9f 1974 int ret;
40cca1c5 1975 int i;
46a3df9f 1976
2d03eacc
YL		 1977 hdev->hw.mac.duplex = HCLGE_MAC_FULL;
1978 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
1979 hdev->hw.mac.duplex);
46a3df9f
S		 1980 if (ret) {
1981 dev_err(&hdev->pdev->dev,
1982 "Config mac speed dup fail ret=%d\n", ret);
1983 return ret;
1984 }
1985
1986 mac->link = 0;
1987
46a3df9f 1988 /* Initialize the MTA table work mode */
46a3df9f
S		 1989 hdev->enable_mta = true;
1990 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
1991
1992 ret = hclge_set_mta_filter_mode(hdev,
1993 hdev->mta_mac_sel_type,
1994 hdev->enable_mta);
1995 if (ret) {
1996 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
1997 ret);
1998 return ret;
1999 }
2000
40cca1c5
XW		 2001 for (i = 0; i < hdev->num_alloc_vport; i++) {
2002 vport = &hdev->vport[i];
2003 vport->accept_mta_mc = false;
2004
2005 memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow));
2006 ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false);
2007 if (ret) {
2008 dev_err(&hdev->pdev->dev,
2009 "set mta filter mode fail ret=%d\n", ret);
2010 return ret;
2011 }
7564094c
PL		 2012 }
2013
2014 ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask);
f9fd82a9 2015 if (ret) {
7564094c
PL		 2016 dev_err(&hdev->pdev->dev,
2017 "set default mac_vlan_mask fail ret=%d\n", ret);
f9fd82a9
FL		 2018 return ret;
2019 }
7564094c 2020
f9fd82a9
FL		 2021 if (netdev)
2022 mtu = netdev->mtu;
2023 else
2024 mtu = ETH_DATA_LEN;
2025
2026 ret = hclge_set_mtu(handle, mtu);
3f639907 2027 if (ret)
f9fd82a9
FL		 2028 dev_err(&hdev->pdev->dev,
2029 "set mtu failed ret=%d\n", ret);
f9fd82a9 2030
3f639907 2031 return ret;
46a3df9f
S		 2032}
2033
c1a81619
SM		 2034static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
2035{
2036 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
2037 schedule_work(&hdev->mbx_service_task);
2038}
2039
cb1b9f77
SM		 2040static void hclge_reset_task_schedule(struct hclge_dev *hdev)
2041{
2042 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
2043 schedule_work(&hdev->rst_service_task);
2044}
2045
46a3df9f
S		 2046static void hclge_task_schedule(struct hclge_dev *hdev)
2047{
2048 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2049 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2050 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2051 (void)schedule_work(&hdev->service_task);
2052}
2053
2054static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2055{
d44f9b63 2056 struct hclge_link_status_cmd *req;
46a3df9f
S		 2057 struct hclge_desc desc;
2058 int link_status;
2059 int ret;
2060
2061 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2062 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2063 if (ret) {
2064 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2065 ret);
2066 return ret;
2067 }
2068
d44f9b63 2069 req = (struct hclge_link_status_cmd *)desc.data;
c79301d8 2070 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
46a3df9f
S		 2071
2072 return !!link_status;
2073}
2074
2075static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2076{
2077 int mac_state;
2078 int link_stat;
2079
582d37bb
PL		 2080 if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2081 return 0;
2082
46a3df9f
S		 2083 mac_state = hclge_get_mac_link_status(hdev);
2084
2085 if (hdev->hw.mac.phydev) {
fd813314 2086 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
46a3df9f
S		 2087 link_stat = mac_state &
2088 hdev->hw.mac.phydev->link;
2089 else
2090 link_stat = 0;
2091
2092 } else {
2093 link_stat = mac_state;
2094 }
2095
2096 return !!link_stat;
2097}
2098
2099static void hclge_update_link_status(struct hclge_dev *hdev)
2100{
2101 struct hnae3_client *client = hdev->nic_client;
2102 struct hnae3_handle *handle;
2103 int state;
2104 int i;
2105
2106 if (!client)
2107 return;
2108 state = hclge_get_mac_phy_link(hdev);
2109 if (state != hdev->hw.mac.link) {
2110 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2111 handle = &hdev->vport[i].nic;
2112 client->ops->link_status_change(handle, state);
2113 }
2114 hdev->hw.mac.link = state;
2115 }
2116}
2117
2118static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2119{
2120 struct hclge_mac mac = hdev->hw.mac;
2121 u8 duplex;
2122 int speed;
2123 int ret;
2124
2125 /* get the speed and duplex as autoneg'result from mac cmd when phy
2126 * doesn't exit.
2127 */
c040366b 2128 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2129 return 0;
2130
2131 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2132 if (ret) {
2133 dev_err(&hdev->pdev->dev,
2134 "mac autoneg/speed/duplex query failed %d\n", ret);
2135 return ret;
2136 }
2137
2d03eacc
YL		 2138 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2139 if (ret) {
2140 dev_err(&hdev->pdev->dev,
2141 "mac speed/duplex config failed %d\n", ret);
2142 return ret;
46a3df9f
S		 2143 }
2144
2145 return 0;
2146}
2147
2148static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2149{
2150 struct hclge_vport *vport = hclge_get_vport(handle);
2151 struct hclge_dev *hdev = vport->back;
2152
2153 return hclge_update_speed_duplex(hdev);
2154}
2155
2156static int hclge_get_status(struct hnae3_handle *handle)
2157{
2158 struct hclge_vport *vport = hclge_get_vport(handle);
2159 struct hclge_dev *hdev = vport->back;
2160
2161 hclge_update_link_status(hdev);
2162
2163 return hdev->hw.mac.link;
2164}
2165
d039ef68 2166static void hclge_service_timer(struct timer_list *t)
46a3df9f 2167{
d039ef68 2168 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2169
d039ef68 2170 mod_timer(&hdev->service_timer, jiffies + HZ);
c5f65480 2171 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2172 hclge_task_schedule(hdev);
2173}
2174
2175static void hclge_service_complete(struct hclge_dev *hdev)
2176{
2177 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2178
2179 /* Flush memory before next watchdog */
2180 smp_mb__before_atomic();
2181 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2182}
2183
ca1d7669
SM		 2184static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2185{
2186 u32 rst_src_reg;
c1a81619 2187 u32 cmdq_src_reg;
ca1d7669
SM		 2188
2189 /* fetch the events from their corresponding regs */
9ca8d1a7 2190 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
c1a81619
SM		 2191 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2192
2193 /* Assumption: If by any chance reset and mailbox events are reported
2194 * together then we will only process reset event in this go and will
2195 * defer the processing of the mailbox events. Since, we would have not
2196 * cleared RX CMDQ event this time we would receive again another
2197 * interrupt from H/W just for the mailbox.
2198 */
ca1d7669
SM		 2199
2200 /* check for vector0 reset event sources */
2201 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
8d40854f 2202 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
ca1d7669
SM		 2203 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2204 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2205 return HCLGE_VECTOR0_EVENT_RST;
2206 }
2207
2208 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
8d40854f 2209 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
ca1d7669
SM		 2210 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2211 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2212 return HCLGE_VECTOR0_EVENT_RST;
2213 }
2214
2215 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2216 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2217 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2218 return HCLGE_VECTOR0_EVENT_RST;
2219 }
2220
c1a81619
SM		 2221 /* check for vector0 mailbox(=CMDQ RX) event source */
2222 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2223 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2224 *clearval = cmdq_src_reg;
2225 return HCLGE_VECTOR0_EVENT_MBX;
2226 }
ca1d7669
SM		 2227
2228 return HCLGE_VECTOR0_EVENT_OTHER;
2229}
2230
2231static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2232 u32 regclr)
2233{
c1a81619
SM		 2234 switch (event_type) {
2235 case HCLGE_VECTOR0_EVENT_RST:
ca1d7669 2236 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
c1a81619
SM		 2237 break;
2238 case HCLGE_VECTOR0_EVENT_MBX:
2239 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2240 break;
fa7a4bd5
JS		 2241 default:
2242 break;
c1a81619 2243 }
ca1d7669
SM		 2244}
2245
8e52a602
XW		 2246static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2247{
2248 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2249 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2250 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2251 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2252 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2253}
2254
466b0c00
L		 2255static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2256{
2257 writel(enable ? 1 : 0, vector->addr);
2258}
2259
2260static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2261{
2262 struct hclge_dev *hdev = data;
ca1d7669
SM		 2263 u32 event_cause;
2264 u32 clearval;
466b0c00
L		 2265
2266 hclge_enable_vector(&hdev->misc_vector, false);
ca1d7669
SM		 2267 event_cause = hclge_check_event_cause(hdev, &clearval);
2268
c1a81619 2269 /* vector 0 interrupt is shared with reset and mailbox source events.*/
ca1d7669
SM		 2270 switch (event_cause) {
2271 case HCLGE_VECTOR0_EVENT_RST:
cb1b9f77 2272 hclge_reset_task_schedule(hdev);
ca1d7669 2273 break;
c1a81619
SM		 2274 case HCLGE_VECTOR0_EVENT_MBX:
2275 /* If we are here then,
2276 * 1. Either we are not handling any mbx task and we are not
2277 * scheduled as well
2278 * OR
2279 * 2. We could be handling a mbx task but nothing more is
2280 * scheduled.
2281 * In both cases, we should schedule mbx task as there are more
2282 * mbx messages reported by this interrupt.
2283 */
2284 hclge_mbx_task_schedule(hdev);
f0ad97ac 2285 break;
ca1d7669 2286 default:
f0ad97ac
YL		 2287 dev_warn(&hdev->pdev->dev,
2288 "received unknown or unhandled event of vector0\n");
ca1d7669
SM		 2289 break;
2290 }
2291
cd8c5c26
YL		 2292 /* clear the source of interrupt if it is not cause by reset */
2293 if (event_cause != HCLGE_VECTOR0_EVENT_RST) {
2294 hclge_clear_event_cause(hdev, event_cause, clearval);
2295 hclge_enable_vector(&hdev->misc_vector, true);
2296 }
466b0c00
L		 2297
2298 return IRQ_HANDLED;
2299}
2300
2301static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2302{
36cbbdf6
PL		 2303 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2304 dev_warn(&hdev->pdev->dev,
2305 "vector(vector_id %d) has been freed.\n", vector_id);
2306 return;
2307 }
2308
466b0c00
L		 2309 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2310 hdev->num_msi_left += 1;
2311 hdev->num_msi_used -= 1;
2312}
2313
2314static void hclge_get_misc_vector(struct hclge_dev *hdev)
2315{
2316 struct hclge_misc_vector *vector = &hdev->misc_vector;
2317
2318 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2319
2320 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2321 hdev->vector_status[0] = 0;
2322
2323 hdev->num_msi_left -= 1;
2324 hdev->num_msi_used += 1;
2325}
2326
2327static int hclge_misc_irq_init(struct hclge_dev *hdev)
2328{
2329 int ret;
2330
2331 hclge_get_misc_vector(hdev);
2332
ca1d7669
SM		 2333 /* this would be explicitly freed in the end */
2334 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2335 0, "hclge_misc", hdev);
466b0c00
L		 2336 if (ret) {
2337 hclge_free_vector(hdev, 0);
2338 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2339 hdev->misc_vector.vector_irq);
2340 }
2341
2342 return ret;
2343}
2344
ca1d7669
SM		 2345static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2346{
2347 free_irq(hdev->misc_vector.vector_irq, hdev);
2348 hclge_free_vector(hdev, 0);
2349}
2350
4ed340ab
L		 2351static int hclge_notify_client(struct hclge_dev *hdev,
2352 enum hnae3_reset_notify_type type)
2353{
2354 struct hnae3_client *client = hdev->nic_client;
2355 u16 i;
2356
2357 if (!client->ops->reset_notify)
2358 return -EOPNOTSUPP;
2359
2360 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2361 struct hnae3_handle *handle = &hdev->vport[i].nic;
2362 int ret;
2363
2364 ret = client->ops->reset_notify(handle, type);
2365 if (ret)
2366 return ret;
2367 }
2368
2369 return 0;
2370}
2371
2372static int hclge_reset_wait(struct hclge_dev *hdev)
2373{
2374#define HCLGE_RESET_WATI_MS 100
2375#define HCLGE_RESET_WAIT_CNT 5
2376 u32 val, reg, reg_bit;
2377 u32 cnt = 0;
2378
2379 switch (hdev->reset_type) {
2380 case HNAE3_GLOBAL_RESET:
2381 reg = HCLGE_GLOBAL_RESET_REG;
2382 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2383 break;
2384 case HNAE3_CORE_RESET:
2385 reg = HCLGE_GLOBAL_RESET_REG;
2386 reg_bit = HCLGE_CORE_RESET_BIT;
2387 break;
2388 case HNAE3_FUNC_RESET:
2389 reg = HCLGE_FUN_RST_ING;
2390 reg_bit = HCLGE_FUN_RST_ING_B;
2391 break;
2392 default:
2393 dev_err(&hdev->pdev->dev,
2394 "Wait for unsupported reset type: %d\n",
2395 hdev->reset_type);
2396 return -EINVAL;
2397 }
2398
2399 val = hclge_read_dev(&hdev->hw, reg);
e4e87715 2400 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
4ed340ab
L		 2401 msleep(HCLGE_RESET_WATI_MS);
2402 val = hclge_read_dev(&hdev->hw, reg);
2403 cnt++;
2404 }
2405
4ed340ab
L		 2406 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2407 dev_warn(&hdev->pdev->dev,
2408 "Wait for reset timeout: %d\n", hdev->reset_type);
2409 return -EBUSY;
2410 }
2411
2412 return 0;
2413}
2414
2bfbd35d 2415int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2416{
2417 struct hclge_desc desc;
2418 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2419 int ret;
2420
2421 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
e4e87715 2422 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4ed340ab
L		 2423 req->fun_reset_vfid = func_id;
2424
2425 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2426 if (ret)
2427 dev_err(&hdev->pdev->dev,
2428 "send function reset cmd fail, status =%d\n", ret);
2429
2430 return ret;
2431}
2432
f2f432f2 2433static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2434{
2435 struct pci_dev *pdev = hdev->pdev;
2436 u32 val;
2437
f2f432f2 2438 switch (hdev->reset_type) {
4ed340ab
L		 2439 case HNAE3_GLOBAL_RESET:
2440 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e4e87715 2441 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4ed340ab
L		 2442 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2443 dev_info(&pdev->dev, "Global Reset requested\n");
2444 break;
2445 case HNAE3_CORE_RESET:
2446 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e4e87715 2447 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
4ed340ab
L		 2448 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2449 dev_info(&pdev->dev, "Core Reset requested\n");
2450 break;
2451 case HNAE3_FUNC_RESET:
2452 dev_info(&pdev->dev, "PF Reset requested\n");
2453 hclge_func_reset_cmd(hdev, 0);
cb1b9f77
SM		 2454 /* schedule again to check later */
2455 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2456 hclge_reset_task_schedule(hdev);
4ed340ab
L		 2457 break;
2458 default:
2459 dev_warn(&pdev->dev,
f2f432f2 2460 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2461 break;
2462 }
2463}
2464
f2f432f2
SM		 2465static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2466 unsigned long *addr)
2467{
2468 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2469
2470 /* return the highest priority reset level amongst all */
2471 if (test_bit(HNAE3_GLOBAL_RESET, addr))
2472 rst_level = HNAE3_GLOBAL_RESET;
2473 else if (test_bit(HNAE3_CORE_RESET, addr))
2474 rst_level = HNAE3_CORE_RESET;
2475 else if (test_bit(HNAE3_IMP_RESET, addr))
2476 rst_level = HNAE3_IMP_RESET;
2477 else if (test_bit(HNAE3_FUNC_RESET, addr))
2478 rst_level = HNAE3_FUNC_RESET;
2479
2480 /* now, clear all other resets */
2481 clear_bit(HNAE3_GLOBAL_RESET, addr);
2482 clear_bit(HNAE3_CORE_RESET, addr);
2483 clear_bit(HNAE3_IMP_RESET, addr);
2484 clear_bit(HNAE3_FUNC_RESET, addr);
2485
2486 return rst_level;
2487}
2488
cd8c5c26
YL		 2489static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2490{
2491 u32 clearval = 0;
2492
2493 switch (hdev->reset_type) {
2494 case HNAE3_IMP_RESET:
2495 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2496 break;
2497 case HNAE3_GLOBAL_RESET:
2498 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2499 break;
2500 case HNAE3_CORE_RESET:
2501 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2502 break;
2503 default:
cd8c5c26
YL		 2504 break;
2505 }
2506
2507 if (!clearval)
2508 return;
2509
2510 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2511 hclge_enable_vector(&hdev->misc_vector, true);
2512}
2513
f2f432f2
SM		 2514static void hclge_reset(struct hclge_dev *hdev)
2515{
9de0b86f
HT		 2516 struct hnae3_handle *handle;
2517
f2f432f2 2518 /* perform reset of the stack & ae device for a client */
9de0b86f 2519 handle = &hdev->vport[0].nic;
6d4fab39 2520 rtnl_lock();
f2f432f2
SM		 2521 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2522
2523 if (!hclge_reset_wait(hdev)) {
f2f432f2
SM		 2524 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2525 hclge_reset_ae_dev(hdev->ae_dev);
2526 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
cd8c5c26
YL		 2527
2528 hclge_clear_reset_cause(hdev);
f2f432f2
SM		 2529 } else {
2530 /* schedule again to check pending resets later */
2531 set_bit(hdev->reset_type, &hdev->reset_pending);
2532 hclge_reset_task_schedule(hdev);
2533 }
2534
2535 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
9de0b86f 2536 handle->last_reset_time = jiffies;
6d4fab39 2537 rtnl_unlock();
f2f432f2
SM		 2538}
2539
6d4c3981 2540static void hclge_reset_event(struct hnae3_handle *handle)
4ed340ab
L		 2541{
2542 struct hclge_vport *vport = hclge_get_vport(handle);
2543 struct hclge_dev *hdev = vport->back;
2544
6d4c3981
SM		 2545 /* check if this is a new reset request and we are not here just because
2546 * last reset attempt did not succeed and watchdog hit us again. We will
2547 * know this if last reset request did not occur very recently (watchdog
2548 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2549 * In case of new request we reset the "reset level" to PF reset.
9de0b86f
HT		 2550 * And if it is a repeat reset request of the most recent one then we
2551 * want to make sure we throttle the reset request. Therefore, we will
2552 * not allow it again before 3*HZ times.
6d4c3981 2553 */
9de0b86f
HT		 2554 if (time_before(jiffies, (handle->last_reset_time + 3 * HZ)))
2555 return;
2556 else if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ)))
6d4c3981 2557 handle->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2558
6d4c3981
SM		 2559 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
2560 handle->reset_level);
2561
2562 /* request reset & schedule reset task */
2563 set_bit(handle->reset_level, &hdev->reset_request);
2564 hclge_reset_task_schedule(hdev);
2565
2566 if (handle->reset_level < HNAE3_GLOBAL_RESET)
2567 handle->reset_level++;
4ed340ab
L		 2568}
2569
2570static void hclge_reset_subtask(struct hclge_dev *hdev)
2571{
f2f432f2
SM		 2572 /* check if there is any ongoing reset in the hardware. This status can
2573 * be checked from reset_pending. If there is then, we need to wait for
2574 * hardware to complete reset.
2575 * a. If we are able to figure out in reasonable time that hardware
2576 * has fully resetted then, we can proceed with driver, client
2577 * reset.
2578 * b. else, we can come back later to check this status so re-sched
2579 * now.
2580 */
2581 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2582 if (hdev->reset_type != HNAE3_NONE_RESET)
2583 hclge_reset(hdev);
4ed340ab 2584
f2f432f2
SM		 2585 /* check if we got any *new* reset requests to be honored */
2586 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2587 if (hdev->reset_type != HNAE3_NONE_RESET)
2588 hclge_do_reset(hdev);
4ed340ab 2589
4ed340ab
L		 2590 hdev->reset_type = HNAE3_NONE_RESET;
2591}
2592
cb1b9f77 2593static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2594{
cb1b9f77
SM		 2595 struct hclge_dev *hdev =
2596 container_of(work, struct hclge_dev, rst_service_task);
2597
2598 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2599 return;
2600
2601 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2602
4ed340ab 2603 hclge_reset_subtask(hdev);
cb1b9f77
SM		 2604
2605 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2606}
2607
c1a81619
SM		 2608static void hclge_mailbox_service_task(struct work_struct *work)
2609{
2610 struct hclge_dev *hdev =
2611 container_of(work, struct hclge_dev, mbx_service_task);
2612
2613 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2614 return;
2615
2616 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2617
2618 hclge_mbx_handler(hdev);
2619
2620 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2621}
2622
46a3df9f
S		 2623static void hclge_service_task(struct work_struct *work)
2624{
2625 struct hclge_dev *hdev =
2626 container_of(work, struct hclge_dev, service_task);
2627
c5f65480
JS		 2628 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2629 hclge_update_stats_for_all(hdev);
2630 hdev->hw_stats.stats_timer = 0;
2631 }
2632
46a3df9f
S		 2633 hclge_update_speed_duplex(hdev);
2634 hclge_update_link_status(hdev);
46a3df9f
S		 2635 hclge_service_complete(hdev);
2636}
2637
46a3df9f
S		 2638struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2639{
2640 /* VF handle has no client */
2641 if (!handle->client)
2642 return container_of(handle, struct hclge_vport, nic);
2643 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2644 return container_of(handle, struct hclge_vport, roce);
2645 else
2646 return container_of(handle, struct hclge_vport, nic);
2647}
2648
2649static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2650 struct hnae3_vector_info *vector_info)
2651{
2652 struct hclge_vport *vport = hclge_get_vport(handle);
2653 struct hnae3_vector_info *vector = vector_info;
2654 struct hclge_dev *hdev = vport->back;
2655 int alloc = 0;
2656 int i, j;
2657
2658 vector_num = min(hdev->num_msi_left, vector_num);
2659
2660 for (j = 0; j < vector_num; j++) {
2661 for (i = 1; i < hdev->num_msi; i++) {
2662 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2663 vector->vector = pci_irq_vector(hdev->pdev, i);
2664 vector->io_addr = hdev->hw.io_base +
2665 HCLGE_VECTOR_REG_BASE +
2666 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2667 vport->vport_id *
2668 HCLGE_VECTOR_VF_OFFSET;
2669 hdev->vector_status[i] = vport->vport_id;
887c3820 2670 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2671
2672 vector++;
2673 alloc++;
2674
2675 break;
2676 }
2677 }
2678 }
2679 hdev->num_msi_left -= alloc;
2680 hdev->num_msi_used += alloc;
2681
2682 return alloc;
2683}
2684
2685static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2686{
2687 int i;
2688
887c3820
SM		 2689 for (i = 0; i < hdev->num_msi; i++)
2690 if (vector == hdev->vector_irq[i])
2691 return i;
2692
46a3df9f
S		 2693 return -EINVAL;
2694}
2695
0d3e6631
YL		 2696static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2697{
2698 struct hclge_vport *vport = hclge_get_vport(handle);
2699 struct hclge_dev *hdev = vport->back;
2700 int vector_id;
2701
2702 vector_id = hclge_get_vector_index(hdev, vector);
2703 if (vector_id < 0) {
2704 dev_err(&hdev->pdev->dev,
2705 "Get vector index fail. vector_id =%d\n", vector_id);
2706 return vector_id;
2707 }
2708
2709 hclge_free_vector(hdev, vector_id);
2710
2711 return 0;
2712}
2713
46a3df9f
S		 2714static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2715{
2716 return HCLGE_RSS_KEY_SIZE;
2717}
2718
2719static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2720{
2721 return HCLGE_RSS_IND_TBL_SIZE;
2722}
2723
46a3df9f
S		 2724static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2725 const u8 hfunc, const u8 *key)
2726{
d44f9b63 2727 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2728 struct hclge_desc desc;
2729 int key_offset;
2730 int key_size;
2731 int ret;
2732
d44f9b63 2733 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2734
2735 for (key_offset = 0; key_offset < 3; key_offset++) {
2736 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2737 false);
2738
2739 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2740 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2741
2742 if (key_offset == 2)
2743 key_size =
2744 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2745 else
2746 key_size = HCLGE_RSS_HASH_KEY_NUM;
2747
2748 memcpy(req->hash_key,
2749 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2750
2751 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2752 if (ret) {
2753 dev_err(&hdev->pdev->dev,
2754 "Configure RSS config fail, status = %d\n",
2755 ret);
2756 return ret;
2757 }
2758 }
2759 return 0;
2760}
2761
89523cfa 2762static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 2763{
d44f9b63 2764 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 2765 struct hclge_desc desc;
2766 int i, j;
2767 int ret;
2768
d44f9b63 2769 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 2770
2771 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2772 hclge_cmd_setup_basic_desc
2773 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2774
a90bb9a5
YL		 2775 req->start_table_index =
2776 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2777 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 2778
2779 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2780 req->rss_result[j] =
2781 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2782
2783 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2784 if (ret) {
2785 dev_err(&hdev->pdev->dev,
2786 "Configure rss indir table fail,status = %d\n",
2787 ret);
2788 return ret;
2789 }
2790 }
2791 return 0;
2792}
2793
2794static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2795 u16 *tc_size, u16 *tc_offset)
2796{
d44f9b63 2797 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 2798 struct hclge_desc desc;
2799 int ret;
2800 int i;
2801
2802 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 2803 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 2804
2805 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 2806 u16 mode = 0;
2807
e4e87715
PL		 2808 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2809 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
2810 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
2811 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
2812 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 2813
2814 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 2815 }
2816
2817 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 2818 if (ret)
46a3df9f
S		 2819 dev_err(&hdev->pdev->dev,
2820 "Configure rss tc mode fail, status = %d\n", ret);
46a3df9f 2821
3f639907 2822 return ret;
46a3df9f
S		 2823}
2824
2825static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2826{
d44f9b63 2827 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 2828 struct hclge_desc desc;
2829 int ret;
2830
2831 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2832
d44f9b63 2833 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429
YL		 2834
2835 /* Get the tuple cfg from pf */
2836 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
2837 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
2838 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
2839 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
2840 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
2841 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
2842 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
2843 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
46a3df9f 2844 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 2845 if (ret)
46a3df9f
S		 2846 dev_err(&hdev->pdev->dev,
2847 "Configure rss input fail, status = %d\n", ret);
3f639907 2848 return ret;
46a3df9f
S		 2849}
2850
2851static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2852 u8 *key, u8 *hfunc)
2853{
2854 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 2855 int i;
2856
2857 /* Get hash algorithm */
2858 if (hfunc)
89523cfa 2859 *hfunc = vport->rss_algo;
46a3df9f
S		 2860
2861 /* Get the RSS Key required by the user */
2862 if (key)
2863 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2864
2865 /* Get indirect table */
2866 if (indir)
2867 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2868 indir[i] = vport->rss_indirection_tbl[i];
2869
2870 return 0;
2871}
2872
2873static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2874 const u8 *key, const u8 hfunc)
2875{
2876 struct hclge_vport *vport = hclge_get_vport(handle);
2877 struct hclge_dev *hdev = vport->back;
2878 u8 hash_algo;
2879 int ret, i;
2880
2881 /* Set the RSS Hash Key if specififed by the user */
2882 if (key) {
46a3df9f
S		 2883
2884 if (hfunc == ETH_RSS_HASH_TOP ||
2885 hfunc == ETH_RSS_HASH_NO_CHANGE)
2886 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2887 else
2888 return -EINVAL;
2889 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2890 if (ret)
2891 return ret;
89523cfa
YL		 2892
2893 /* Update the shadow RSS key with user specified qids */
2894 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2895 vport->rss_algo = hash_algo;
46a3df9f
S		 2896 }
2897
2898 /* Update the shadow RSS table with user specified qids */
2899 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2900 vport->rss_indirection_tbl[i] = indir[i];
2901
2902 /* Update the hardware */
89523cfa 2903 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 2904}
2905
f7db940a
L		 2906static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
2907{
2908 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
2909
2910 if (nfc->data & RXH_L4_B_2_3)
2911 hash_sets |= HCLGE_D_PORT_BIT;
2912 else
2913 hash_sets &= ~HCLGE_D_PORT_BIT;
2914
2915 if (nfc->data & RXH_IP_SRC)
2916 hash_sets |= HCLGE_S_IP_BIT;
2917 else
2918 hash_sets &= ~HCLGE_S_IP_BIT;
2919
2920 if (nfc->data & RXH_IP_DST)
2921 hash_sets |= HCLGE_D_IP_BIT;
2922 else
2923 hash_sets &= ~HCLGE_D_IP_BIT;
2924
2925 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
2926 hash_sets |= HCLGE_V_TAG_BIT;
2927
2928 return hash_sets;
2929}
2930
2931static int hclge_set_rss_tuple(struct hnae3_handle *handle,
2932 struct ethtool_rxnfc *nfc)
2933{
2934 struct hclge_vport *vport = hclge_get_vport(handle);
2935 struct hclge_dev *hdev = vport->back;
2936 struct hclge_rss_input_tuple_cmd *req;
2937 struct hclge_desc desc;
2938 u8 tuple_sets;
2939 int ret;
2940
2941 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
2942 RXH_L4_B_0_1 | RXH_L4_B_2_3))
2943 return -EINVAL;
2944
2945 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429 2946 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 2947
6f2af429
YL		 2948 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
2949 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
2950 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
2951 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
2952 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
2953 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
2954 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
2955 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 2956
2957 tuple_sets = hclge_get_rss_hash_bits(nfc);
2958 switch (nfc->flow_type) {
2959 case TCP_V4_FLOW:
2960 req->ipv4_tcp_en = tuple_sets;
2961 break;
2962 case TCP_V6_FLOW:
2963 req->ipv6_tcp_en = tuple_sets;
2964 break;
2965 case UDP_V4_FLOW:
2966 req->ipv4_udp_en = tuple_sets;
2967 break;
2968 case UDP_V6_FLOW:
2969 req->ipv6_udp_en = tuple_sets;
2970 break;
2971 case SCTP_V4_FLOW:
2972 req->ipv4_sctp_en = tuple_sets;
2973 break;
2974 case SCTP_V6_FLOW:
2975 if ((nfc->data & RXH_L4_B_0_1) ||
2976 (nfc->data & RXH_L4_B_2_3))
2977 return -EINVAL;
2978
2979 req->ipv6_sctp_en = tuple_sets;
2980 break;
2981 case IPV4_FLOW:
2982 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2983 break;
2984 case IPV6_FLOW:
2985 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2986 break;
2987 default:
2988 return -EINVAL;
2989 }
2990
2991 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6f2af429 2992 if (ret) {
f7db940a
L		 2993 dev_err(&hdev->pdev->dev,
2994 "Set rss tuple fail, status = %d\n", ret);
6f2af429
YL		 2995 return ret;
2996 }
f7db940a 2997
6f2af429
YL		 2998 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
2999 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3000 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3001 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3002 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3003 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3004 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3005 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
3006 return 0;
f7db940a
L		 3007}
3008
07d29954
L		 3009static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3010 struct ethtool_rxnfc *nfc)
3011{
3012 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 3013 u8 tuple_sets;
07d29954
L		 3014
3015 nfc->data = 0;
3016
07d29954
L		 3017 switch (nfc->flow_type) {
3018 case TCP_V4_FLOW:
6f2af429 3019 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3020 break;
3021 case UDP_V4_FLOW:
6f2af429 3022 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3023 break;
3024 case TCP_V6_FLOW:
6f2af429 3025 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3026 break;
3027 case UDP_V6_FLOW:
6f2af429 3028 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3029 break;
3030 case SCTP_V4_FLOW:
6f2af429 3031 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3032 break;
3033 case SCTP_V6_FLOW:
6f2af429 3034 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3035 break;
3036 case IPV4_FLOW:
3037 case IPV6_FLOW:
3038 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3039 break;
3040 default:
3041 return -EINVAL;
3042 }
3043
3044 if (!tuple_sets)
3045 return 0;
3046
3047 if (tuple_sets & HCLGE_D_PORT_BIT)
3048 nfc->data |= RXH_L4_B_2_3;
3049 if (tuple_sets & HCLGE_S_PORT_BIT)
3050 nfc->data |= RXH_L4_B_0_1;
3051 if (tuple_sets & HCLGE_D_IP_BIT)
3052 nfc->data |= RXH_IP_DST;
3053 if (tuple_sets & HCLGE_S_IP_BIT)
3054 nfc->data |= RXH_IP_SRC;
3055
3056 return 0;
3057}
3058
46a3df9f
S		 3059static int hclge_get_tc_size(struct hnae3_handle *handle)
3060{
3061 struct hclge_vport *vport = hclge_get_vport(handle);
3062 struct hclge_dev *hdev = vport->back;
3063
3064 return hdev->rss_size_max;
3065}
3066
77f255c1 3067int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3068{
46a3df9f 3069 struct hclge_vport *vport = hdev->vport;
268f5dfa
YL		 3070 u8 *rss_indir = vport[0].rss_indirection_tbl;
3071 u16 rss_size = vport[0].alloc_rss_size;
3072 u8 *key = vport[0].rss_hash_key;
3073 u8 hfunc = vport[0].rss_algo;
46a3df9f 3074 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3075 u16 tc_valid[HCLGE_MAX_TC_NUM];
3076 u16 tc_size[HCLGE_MAX_TC_NUM];
268f5dfa
YL		 3077 u16 roundup_size;
3078 int i, ret;
68ece54e 3079
46a3df9f
S		 3080 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3081 if (ret)
268f5dfa 3082 return ret;
46a3df9f 3083
46a3df9f
S		 3084 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3085 if (ret)
268f5dfa 3086 return ret;
46a3df9f
S		 3087
3088 ret = hclge_set_rss_input_tuple(hdev);
3089 if (ret)
268f5dfa 3090 return ret;
46a3df9f 3091
68ece54e
YL		 3092 /* Each TC have the same queue size, and tc_size set to hardware is
3093 * the log2 of roundup power of two of rss_size, the acutal queue
3094 * size is limited by indirection table.
3095 */
3096 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3097 dev_err(&hdev->pdev->dev,
3098 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3099 rss_size);
268f5dfa 3100 return -EINVAL;
68ece54e
YL		 3101 }
3102
3103 roundup_size = roundup_pow_of_two(rss_size);
3104 roundup_size = ilog2(roundup_size);
3105
46a3df9f 3106 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3107 tc_valid[i] = 0;
46a3df9f 3108
68ece54e
YL		 3109 if (!(hdev->hw_tc_map & BIT(i)))
3110 continue;
3111
3112 tc_valid[i] = 1;
3113 tc_size[i] = roundup_size;
3114 tc_offset[i] = rss_size * i;
46a3df9f 3115 }
68ece54e 3116
268f5dfa
YL		 3117 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3118}
46a3df9f 3119
268f5dfa
YL		 3120void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3121{
3122 struct hclge_vport *vport = hdev->vport;
3123 int i, j;
46a3df9f 3124
268f5dfa
YL		 3125 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3126 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3127 vport[j].rss_indirection_tbl[i] =
3128 i % vport[j].alloc_rss_size;
3129 }
3130}
3131
3132static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3133{
3134 struct hclge_vport *vport = hdev->vport;
3135 int i;
3136
268f5dfa
YL		 3137 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3138 vport[i].rss_tuple_sets.ipv4_tcp_en =
3139 HCLGE_RSS_INPUT_TUPLE_OTHER;
3140 vport[i].rss_tuple_sets.ipv4_udp_en =
3141 HCLGE_RSS_INPUT_TUPLE_OTHER;
3142 vport[i].rss_tuple_sets.ipv4_sctp_en =
3143 HCLGE_RSS_INPUT_TUPLE_SCTP;
3144 vport[i].rss_tuple_sets.ipv4_fragment_en =
3145 HCLGE_RSS_INPUT_TUPLE_OTHER;
3146 vport[i].rss_tuple_sets.ipv6_tcp_en =
3147 HCLGE_RSS_INPUT_TUPLE_OTHER;
3148 vport[i].rss_tuple_sets.ipv6_udp_en =
3149 HCLGE_RSS_INPUT_TUPLE_OTHER;
3150 vport[i].rss_tuple_sets.ipv6_sctp_en =
3151 HCLGE_RSS_INPUT_TUPLE_SCTP;
3152 vport[i].rss_tuple_sets.ipv6_fragment_en =
3153 HCLGE_RSS_INPUT_TUPLE_OTHER;
3154
3155 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
ea739c90
FL		 3156
3157 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
268f5dfa
YL		 3158 }
3159
3160 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3161}
3162
84e095d6
SM		 3163int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3164 int vector_id, bool en,
3165 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3166{
3167 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3168 struct hnae3_ring_chain_node *node;
3169 struct hclge_desc desc;
84e095d6
SM		 3170 struct hclge_ctrl_vector_chain_cmd *req
3171 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3172 enum hclge_cmd_status status;
3173 enum hclge_opcode_type op;
3174 u16 tqp_type_and_id;
46a3df9f
S		 3175 int i;
3176
84e095d6
SM		 3177 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3178 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3179 req->int_vector_id = vector_id;
3180
3181 i = 0;
3182 for (node = ring_chain; node; node = node->next) {
84e095d6 3183 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
e4e87715
PL		 3184 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3185 HCLGE_INT_TYPE_S,
3186 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3187 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3188 HCLGE_TQP_ID_S, node->tqp_index);
3189 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3190 HCLGE_INT_GL_IDX_S,
3191 hnae3_get_field(node->int_gl_idx,
3192 HNAE3_RING_GL_IDX_M,
3193 HNAE3_RING_GL_IDX_S));
84e095d6 3194 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3195 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3196 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
84e095d6 3197 req->vfid = vport->vport_id;
46a3df9f 3198
84e095d6
SM		 3199 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3200 if (status) {
46a3df9f
S		 3201 dev_err(&hdev->pdev->dev,
3202 "Map TQP fail, status is %d.\n",
84e095d6
SM		 3203 status);
3204 return -EIO;
46a3df9f
S		 3205 }
3206 i = 0;
3207
3208 hclge_cmd_setup_basic_desc(&desc,
84e095d6 3209 op,
46a3df9f
S		 3210 false);
3211 req->int_vector_id = vector_id;
3212 }
3213 }
3214
3215 if (i > 0) {
3216 req->int_cause_num = i;
84e095d6
SM		 3217 req->vfid = vport->vport_id;
3218 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3219 if (status) {
46a3df9f 3220 dev_err(&hdev->pdev->dev,
84e095d6
SM		 3221 "Map TQP fail, status is %d.\n", status);
3222 return -EIO;
46a3df9f
S		 3223 }
3224 }
3225
3226 return 0;
3227}
3228
84e095d6
SM		 3229static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3230 int vector,
3231 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3232{
3233 struct hclge_vport *vport = hclge_get_vport(handle);
3234 struct hclge_dev *hdev = vport->back;
3235 int vector_id;
3236
3237 vector_id = hclge_get_vector_index(hdev, vector);
3238 if (vector_id < 0) {
3239 dev_err(&hdev->pdev->dev,
84e095d6 3240 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3241 return vector_id;
3242 }
3243
84e095d6 3244 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3245}
3246
84e095d6
SM		 3247static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3248 int vector,
3249 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3250{
3251 struct hclge_vport *vport = hclge_get_vport(handle);
3252 struct hclge_dev *hdev = vport->back;
84e095d6 3253 int vector_id, ret;
46a3df9f 3254
b50ae26c
PL		 3255 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3256 return 0;
3257
46a3df9f
S		 3258 vector_id = hclge_get_vector_index(hdev, vector);
3259 if (vector_id < 0) {
3260 dev_err(&handle->pdev->dev,
3261 "Get vector index fail. ret =%d\n", vector_id);
3262 return vector_id;
3263 }
3264
84e095d6 3265 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
0d3e6631 3266 if (ret)
84e095d6
SM		 3267 dev_err(&handle->pdev->dev,
3268 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3269 vector_id,
3270 ret);
46a3df9f 3271
0d3e6631 3272 return ret;
46a3df9f
S		 3273}
3274
3275int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3276 struct hclge_promisc_param *param)
3277{
d44f9b63 3278 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3279 struct hclge_desc desc;
3280 int ret;
3281
3282 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3283
d44f9b63 3284 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3285 req->vf_id = param->vf_id;
96c0e861
PL		 3286
3287 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3288 * pdev revision(0x20), new revision support them. The
3289 * value of this two fields will not return error when driver
3290 * send command to fireware in revision(0x20).
3291 */
3292 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3293 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3294
3295 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3296 if (ret)
46a3df9f
S		 3297 dev_err(&hdev->pdev->dev,
3298 "Set promisc mode fail, status is %d.\n", ret);
3f639907
JS		 3299
3300 return ret;
46a3df9f
S		 3301}
3302
3303void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3304 bool en_mc, bool en_bc, int vport_id)
3305{
3306 if (!param)
3307 return;
3308
3309 memset(param, 0, sizeof(struct hclge_promisc_param));
3310 if (en_uc)
3311 param->enable = HCLGE_PROMISC_EN_UC;
3312 if (en_mc)
3313 param->enable |= HCLGE_PROMISC_EN_MC;
3314 if (en_bc)
3315 param->enable |= HCLGE_PROMISC_EN_BC;
3316 param->vf_id = vport_id;
3317}
3318
3b75c3df
PL		 3319static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3320 bool en_mc_pmc)
46a3df9f
S		 3321{
3322 struct hclge_vport *vport = hclge_get_vport(handle);
3323 struct hclge_dev *hdev = vport->back;
3324 struct hclge_promisc_param param;
3325
3b75c3df
PL		 3326 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3327 vport->vport_id);
46a3df9f
S		 3328 hclge_cmd_set_promisc_mode(hdev, &param);
3329}
3330
3331static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3332{
3333 struct hclge_desc desc;
d44f9b63
YL		 3334 struct hclge_config_mac_mode_cmd *req =
3335 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3336 u32 loop_en = 0;
46a3df9f
S		 3337 int ret;
3338
3339 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
e4e87715
PL		 3340 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3341 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3342 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3343 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3344 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3345 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3346 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3347 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3348 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3349 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3350 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3351 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3352 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3353 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
a90bb9a5 3354 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3355
3356 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3357 if (ret)
3358 dev_err(&hdev->pdev->dev,
3359 "mac enable fail, ret =%d.\n", ret);
3360}
3361
eb66d503 3362static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 3363{
c39c4d98 3364 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 3365 struct hclge_desc desc;
3366 u32 loop_en;
3367 int ret;
3368
e4d68dae
YL		 3369 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3370 /* 1 Read out the MAC mode config at first */
3371 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
3372 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3373 if (ret) {
3374 dev_err(&hdev->pdev->dev,
3375 "mac loopback get fail, ret =%d.\n", ret);
3376 return ret;
3377 }
c39c4d98 3378
e4d68dae
YL		 3379 /* 2 Then setup the loopback flag */
3380 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
e4e87715 3381 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
0f29fc23
YL		 3382 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0);
3383 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0);
e4d68dae
YL		 3384
3385 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 3386
e4d68dae
YL		 3387 /* 3 Config mac work mode with loopback flag
3388 * and its original configure parameters
3389 */
3390 hclge_cmd_reuse_desc(&desc, false);
3391 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3392 if (ret)
3393 dev_err(&hdev->pdev->dev,
3394 "mac loopback set fail, ret =%d.\n", ret);
3395 return ret;
3396}
c39c4d98 3397
4dc13b96
FL		 3398static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en,
3399 enum hnae3_loop loop_mode)
5fd50ac3
PL		 3400{
3401#define HCLGE_SERDES_RETRY_MS 10
3402#define HCLGE_SERDES_RETRY_NUM 100
3403 struct hclge_serdes_lb_cmd *req;
3404 struct hclge_desc desc;
3405 int ret, i = 0;
4dc13b96 3406 u8 loop_mode_b;
5fd50ac3 3407
d0d72bac 3408 req = (struct hclge_serdes_lb_cmd *)desc.data;
5fd50ac3
PL		 3409 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
3410
4dc13b96
FL		 3411 switch (loop_mode) {
3412 case HNAE3_LOOP_SERIAL_SERDES:
3413 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
3414 break;
3415 case HNAE3_LOOP_PARALLEL_SERDES:
3416 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
3417 break;
3418 default:
3419 dev_err(&hdev->pdev->dev,
3420 "unsupported serdes loopback mode %d\n", loop_mode);
3421 return -ENOTSUPP;
3422 }
3423
5fd50ac3 3424 if (en) {
4dc13b96
FL		 3425 req->enable = loop_mode_b;
3426 req->mask = loop_mode_b;
5fd50ac3 3427 } else {
4dc13b96 3428 req->mask = loop_mode_b;
5fd50ac3
PL		 3429 }
3430
3431 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3432 if (ret) {
3433 dev_err(&hdev->pdev->dev,
3434 "serdes loopback set fail, ret = %d\n", ret);
3435 return ret;
3436 }
3437
3438 do {
3439 msleep(HCLGE_SERDES_RETRY_MS);
3440 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
3441 true);
3442 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3443 if (ret) {
3444 dev_err(&hdev->pdev->dev,
3445 "serdes loopback get, ret = %d\n", ret);
3446 return ret;
3447 }
3448 } while (++i < HCLGE_SERDES_RETRY_NUM &&
3449 !(req->result & HCLGE_CMD_SERDES_DONE_B));
3450
3451 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
3452 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
3453 return -EBUSY;
3454 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
3455 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
3456 return -EIO;
3457 }
3458
0f29fc23 3459 hclge_cfg_mac_mode(hdev, en);
5fd50ac3
PL		 3460 return 0;
3461}
3462
0f29fc23
YL		 3463static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3464 int stream_id, bool enable)
3465{
3466 struct hclge_desc desc;
3467 struct hclge_cfg_com_tqp_queue_cmd *req =
3468 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
3469 int ret;
3470
3471 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3472 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3473 req->stream_id = cpu_to_le16(stream_id);
3474 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3475
3476 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3477 if (ret)
3478 dev_err(&hdev->pdev->dev,
3479 "Tqp enable fail, status =%d.\n", ret);
3480 return ret;
3481}
3482
e4d68dae
YL		 3483static int hclge_set_loopback(struct hnae3_handle *handle,
3484 enum hnae3_loop loop_mode, bool en)
3485{
3486 struct hclge_vport *vport = hclge_get_vport(handle);
3487 struct hclge_dev *hdev = vport->back;
0f29fc23 3488 int i, ret;
e4d68dae
YL		 3489
3490 switch (loop_mode) {
eb66d503
FL		 3491 case HNAE3_LOOP_APP:
3492 ret = hclge_set_app_loopback(hdev, en);
c39c4d98 3493 break;
4dc13b96
FL		 3494 case HNAE3_LOOP_SERIAL_SERDES:
3495 case HNAE3_LOOP_PARALLEL_SERDES:
3496 ret = hclge_set_serdes_loopback(hdev, en, loop_mode);
5fd50ac3 3497 break;
c39c4d98
YL		 3498 default:
3499 ret = -ENOTSUPP;
3500 dev_err(&hdev->pdev->dev,
3501 "loop_mode %d is not supported\n", loop_mode);
3502 break;
3503 }
3504
0f29fc23
YL		 3505 for (i = 0; i < vport->alloc_tqps; i++) {
3506 ret = hclge_tqp_enable(hdev, i, 0, en);
3507 if (ret)
3508 return ret;
3509 }
46a3df9f 3510
0f29fc23 3511 return 0;
46a3df9f
S		 3512}
3513
3514static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3515{
3516 struct hclge_vport *vport = hclge_get_vport(handle);
3517 struct hnae3_queue *queue;
3518 struct hclge_tqp *tqp;
3519 int i;
3520
3521 for (i = 0; i < vport->alloc_tqps; i++) {
3522 queue = handle->kinfo.tqp[i];
3523 tqp = container_of(queue, struct hclge_tqp, q);
3524 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3525 }
3526}
3527
3528static int hclge_ae_start(struct hnae3_handle *handle)
3529{
3530 struct hclge_vport *vport = hclge_get_vport(handle);
3531 struct hclge_dev *hdev = vport->back;
b01b7cf1 3532 int i;
46a3df9f 3533
814e0274
PL		 3534 for (i = 0; i < vport->alloc_tqps; i++)
3535 hclge_tqp_enable(hdev, i, 0, true);
46a3df9f 3536
46a3df9f
S		 3537 /* mac enable */
3538 hclge_cfg_mac_mode(hdev, true);
3539 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3540 mod_timer(&hdev->service_timer, jiffies + HZ);
be8d8cdb 3541 hdev->hw.mac.link = 0;
46a3df9f 3542
b50ae26c
PL		 3543 /* reset tqp stats */
3544 hclge_reset_tqp_stats(handle);
3545
b01b7cf1 3546 hclge_mac_start_phy(hdev);
46a3df9f 3547
46a3df9f
S		 3548 return 0;
3549}
3550
3551static void hclge_ae_stop(struct hnae3_handle *handle)
3552{
3553 struct hclge_vport *vport = hclge_get_vport(handle);
3554 struct hclge_dev *hdev = vport->back;
814e0274 3555 int i;
46a3df9f 3556
2f7e4896
FL		 3557 set_bit(HCLGE_STATE_DOWN, &hdev->state);
3558
b50ae26c
PL		 3559 del_timer_sync(&hdev->service_timer);
3560 cancel_work_sync(&hdev->service_task);
f5be7967 3561 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
b50ae26c 3562
9617f668
YL		 3563 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) {
3564 hclge_mac_stop_phy(hdev);
b50ae26c 3565 return;
9617f668 3566 }
b50ae26c 3567
814e0274
PL		 3568 for (i = 0; i < vport->alloc_tqps; i++)
3569 hclge_tqp_enable(hdev, i, 0, false);
46a3df9f 3570
46a3df9f
S		 3571 /* Mac disable */
3572 hclge_cfg_mac_mode(hdev, false);
3573
3574 hclge_mac_stop_phy(hdev);
3575
3576 /* reset tqp stats */
3577 hclge_reset_tqp_stats(handle);
f30dfddc
FL		 3578 del_timer_sync(&hdev->service_timer);
3579 cancel_work_sync(&hdev->service_task);
3580 hclge_update_link_status(hdev);
46a3df9f
S		 3581}
3582
3583static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3584 u16 cmdq_resp, u8 resp_code,
3585 enum hclge_mac_vlan_tbl_opcode op)
3586{
3587 struct hclge_dev *hdev = vport->back;
3588 int return_status = -EIO;
3589
3590 if (cmdq_resp) {
3591 dev_err(&hdev->pdev->dev,
3592 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3593 cmdq_resp);
3594 return -EIO;
3595 }
3596
3597 if (op == HCLGE_MAC_VLAN_ADD) {
3598 if ((!resp_code) || (resp_code == 1)) {
3599 return_status = 0;
3600 } else if (resp_code == 2) {
eefd00a5 3601 return_status = -ENOSPC;
46a3df9f
S		 3602 dev_err(&hdev->pdev->dev,
3603 "add mac addr failed for uc_overflow.\n");
3604 } else if (resp_code == 3) {
eefd00a5 3605 return_status = -ENOSPC;
46a3df9f
S		 3606 dev_err(&hdev->pdev->dev,
3607 "add mac addr failed for mc_overflow.\n");
3608 } else {
3609 dev_err(&hdev->pdev->dev,
3610 "add mac addr failed for undefined, code=%d.\n",
3611 resp_code);
3612 }
3613 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3614 if (!resp_code) {
3615 return_status = 0;
3616 } else if (resp_code == 1) {
eefd00a5 3617 return_status = -ENOENT;
46a3df9f
S		 3618 dev_dbg(&hdev->pdev->dev,
3619 "remove mac addr failed for miss.\n");
3620 } else {
3621 dev_err(&hdev->pdev->dev,
3622 "remove mac addr failed for undefined, code=%d.\n",
3623 resp_code);
3624 }
3625 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3626 if (!resp_code) {
3627 return_status = 0;
3628 } else if (resp_code == 1) {
eefd00a5 3629 return_status = -ENOENT;
46a3df9f
S		 3630 dev_dbg(&hdev->pdev->dev,
3631 "lookup mac addr failed for miss.\n");
3632 } else {
3633 dev_err(&hdev->pdev->dev,
3634 "lookup mac addr failed for undefined, code=%d.\n",
3635 resp_code);
3636 }
3637 } else {
eefd00a5 3638 return_status = -EINVAL;
46a3df9f
S		 3639 dev_err(&hdev->pdev->dev,
3640 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3641 op);
3642 }
3643
3644 return return_status;
3645}
3646
3647static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3648{
3649 int word_num;
3650 int bit_num;
3651
3652 if (vfid > 255 || vfid < 0)
3653 return -EIO;
3654
3655 if (vfid >= 0 && vfid <= 191) {
3656 word_num = vfid / 32;
3657 bit_num = vfid % 32;
3658 if (clr)
a90bb9a5 3659 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3660 else
a90bb9a5 3661 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3662 } else {
3663 word_num = (vfid - 192) / 32;
3664 bit_num = vfid % 32;
3665 if (clr)
a90bb9a5 3666 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3667 else
a90bb9a5 3668 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3669 }
3670
3671 return 0;
3672}
3673
3674static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3675{
3676#define HCLGE_DESC_NUMBER 3
3677#define HCLGE_FUNC_NUMBER_PER_DESC 6
3678 int i, j;
3679
6c39d527 3680 for (i = 1; i < HCLGE_DESC_NUMBER; i++)
46a3df9f
S		 3681 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3682 if (desc[i].data[j])
3683 return false;
3684
3685 return true;
3686}
3687
d44f9b63 3688static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3689 const u8 *addr)
3690{
3691 const unsigned char *mac_addr = addr;
3692 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3693 (mac_addr[0]) | (mac_addr[1] << 8);
3694 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3695
3696 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3697 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3698}
3699
1db9b1bf
YL		 3700static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3701 const u8 *addr)
46a3df9f
S		 3702{
3703 u16 high_val = addr[1] | (addr[0] << 8);
3704 struct hclge_dev *hdev = vport->back;
3705 u32 rsh = 4 - hdev->mta_mac_sel_type;
3706 u16 ret_val = (high_val >> rsh) & 0xfff;
3707
3708 return ret_val;
3709}
3710
3711static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3712 enum hclge_mta_dmac_sel_type mta_mac_sel,
3713 bool enable)
3714{
d44f9b63 3715 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3716 struct hclge_desc desc;
3717 int ret;
3718
d44f9b63 3719 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3720 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3721
e4e87715
PL		 3722 hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3723 enable);
3724 hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3725 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
46a3df9f
S		 3726
3727 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3728 if (ret)
46a3df9f
S		 3729 dev_err(&hdev->pdev->dev,
3730 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3731 ret);
46a3df9f 3732
3f639907 3733 return ret;
46a3df9f
S		 3734}
3735
3736int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3737 u8 func_id,
3738 bool enable)
3739{
d44f9b63 3740 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3741 struct hclge_desc desc;
3742 int ret;
3743
d44f9b63 3744 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3745 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3746
e4e87715
PL		 3747 hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3748 enable);
46a3df9f
S		 3749 req->function_id = func_id;
3750
3751 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3752 if (ret)
46a3df9f
S		 3753 dev_err(&hdev->pdev->dev,
3754 "Config func_id enable failed for cmd_send, ret =%d.\n",
3755 ret);
46a3df9f 3756
3f639907 3757 return ret;
46a3df9f
S		 3758}
3759
3760static int hclge_set_mta_table_item(struct hclge_vport *vport,
3761 u16 idx,
3762 bool enable)
3763{
3764 struct hclge_dev *hdev = vport->back;
d44f9b63 3765 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 3766 struct hclge_desc desc;
a90bb9a5 3767 u16 item_idx = 0;
46a3df9f
S		 3768 int ret;
3769
d44f9b63 3770 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f 3771 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
e4e87715 3772 hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
46a3df9f 3773
e4e87715
PL		 3774 hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
3775 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 3776 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 3777
3778 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3779 if (ret) {
3780 dev_err(&hdev->pdev->dev,
3781 "Config mta table item failed for cmd_send, ret =%d.\n",
3782 ret);
3783 return ret;
3784 }
3785
40cca1c5
XW		 3786 if (enable)
3787 set_bit(idx, vport->mta_shadow);
3788 else
3789 clear_bit(idx, vport->mta_shadow);
3790
46a3df9f
S		 3791 return 0;
3792}
3793
40cca1c5
XW		 3794static int hclge_update_mta_status(struct hnae3_handle *handle)
3795{
3796 unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)];
3797 struct hclge_vport *vport = hclge_get_vport(handle);
3798 struct net_device *netdev = handle->kinfo.netdev;
3799 struct netdev_hw_addr *ha;
3800 u16 tbl_idx;
3801
3802 memset(mta_status, 0, sizeof(mta_status));
3803
3804 /* update mta_status from mc addr list */
3805 netdev_for_each_mc_addr(ha, netdev) {
3806 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr);
3807 set_bit(tbl_idx, mta_status);
3808 }
3809
3810 return hclge_update_mta_status_common(vport, mta_status,
3811 0, HCLGE_MTA_TBL_SIZE, true);
3812}
3813
3814int hclge_update_mta_status_common(struct hclge_vport *vport,
3815 unsigned long *status,
3816 u16 idx,
3817 u16 count,
3818 bool update_filter)
3819{
3820 struct hclge_dev *hdev = vport->back;
3821 u16 update_max = idx + count;
3822 u16 check_max;
3823 int ret = 0;
3824 bool used;
3825 u16 i;
3826
3827 /* setup mta check range */
3828 if (update_filter) {
3829 i = 0;
3830 check_max = HCLGE_MTA_TBL_SIZE;
3831 } else {
3832 i = idx;
3833 check_max = update_max;
3834 }
3835
3836 used = false;
3837 /* check and update all mta item */
3838 for (; i < check_max; i++) {
3839 /* ignore unused item */
3840 if (!test_bit(i, vport->mta_shadow))
3841 continue;
3842
3843 /* if i in update range then update it */
3844 if (i >= idx && i < update_max)
3845 if (!test_bit(i - idx, status))
3846 hclge_set_mta_table_item(vport, i, false);
3847
3848 if (!used && test_bit(i, vport->mta_shadow))
3849 used = true;
3850 }
3851
3852 /* no longer use mta, disable it */
3853 if (vport->accept_mta_mc && update_filter && !used) {
3854 ret = hclge_cfg_func_mta_filter(hdev,
3855 vport->vport_id,
3856 false);
3857 if (ret)
3858 dev_err(&hdev->pdev->dev,
3859 "disable func mta filter fail ret=%d\n",
3860 ret);
3861 else
3862 vport->accept_mta_mc = false;
3863 }
3864
3865 return ret;
3866}
3867
46a3df9f 3868static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3869 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 3870{
3871 struct hclge_dev *hdev = vport->back;
3872 struct hclge_desc desc;
3873 u8 resp_code;
a90bb9a5 3874 u16 retval;
46a3df9f
S		 3875 int ret;
3876
3877 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3878
d44f9b63 3879 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3880
3881 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3882 if (ret) {
3883 dev_err(&hdev->pdev->dev,
3884 "del mac addr failed for cmd_send, ret =%d.\n",
3885 ret);
3886 return ret;
3887 }
a90bb9a5
YL		 3888 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3889 retval = le16_to_cpu(desc.retval);
46a3df9f 3890
a90bb9a5 3891 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3892 HCLGE_MAC_VLAN_REMOVE);
3893}
3894
3895static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3896 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3897 struct hclge_desc *desc,
3898 bool is_mc)
3899{
3900 struct hclge_dev *hdev = vport->back;
3901 u8 resp_code;
a90bb9a5 3902 u16 retval;
46a3df9f
S		 3903 int ret;
3904
3905 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3906 if (is_mc) {
3907 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3908 memcpy(desc[0].data,
3909 req,
d44f9b63 3910 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3911 hclge_cmd_setup_basic_desc(&desc[1],
3912 HCLGE_OPC_MAC_VLAN_ADD,
3913 true);
3914 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3915 hclge_cmd_setup_basic_desc(&desc[2],
3916 HCLGE_OPC_MAC_VLAN_ADD,
3917 true);
3918 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3919 } else {
3920 memcpy(desc[0].data,
3921 req,
d44f9b63 3922 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3923 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3924 }
3925 if (ret) {
3926 dev_err(&hdev->pdev->dev,
3927 "lookup mac addr failed for cmd_send, ret =%d.\n",
3928 ret);
3929 return ret;
3930 }
a90bb9a5
YL		 3931 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3932 retval = le16_to_cpu(desc[0].retval);
46a3df9f 3933
a90bb9a5 3934 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3935 HCLGE_MAC_VLAN_LKUP);
3936}
3937
3938static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3939 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3940 struct hclge_desc *mc_desc)
3941{
3942 struct hclge_dev *hdev = vport->back;
3943 int cfg_status;
3944 u8 resp_code;
a90bb9a5 3945 u16 retval;
46a3df9f
S		 3946 int ret;
3947
3948 if (!mc_desc) {
3949 struct hclge_desc desc;
3950
3951 hclge_cmd_setup_basic_desc(&desc,
3952 HCLGE_OPC_MAC_VLAN_ADD,
3953 false);
d44f9b63
YL		 3954 memcpy(desc.data, req,
3955 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3956 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 3957 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3958 retval = le16_to_cpu(desc.retval);
3959
3960 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3961 resp_code,
3962 HCLGE_MAC_VLAN_ADD);
3963 } else {
c3b6f755 3964 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 3965 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3966 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 3967 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3968 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 3969 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3970 memcpy(mc_desc[0].data, req,
d44f9b63 3971 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3972 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 3973 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
3974 retval = le16_to_cpu(mc_desc[0].retval);
3975
3976 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3977 resp_code,
3978 HCLGE_MAC_VLAN_ADD);
3979 }
3980
3981 if (ret) {
3982 dev_err(&hdev->pdev->dev,
3983 "add mac addr failed for cmd_send, ret =%d.\n",
3984 ret);
3985 return ret;
3986 }
3987
3988 return cfg_status;
3989}
3990
3991static int hclge_add_uc_addr(struct hnae3_handle *handle,
3992 const unsigned char *addr)
3993{
3994 struct hclge_vport *vport = hclge_get_vport(handle);
3995
3996 return hclge_add_uc_addr_common(vport, addr);
3997}
3998
3999int hclge_add_uc_addr_common(struct hclge_vport *vport,
4000 const unsigned char *addr)
4001{
4002 struct hclge_dev *hdev = vport->back;
d44f9b63 4003 struct hclge_mac_vlan_tbl_entry_cmd req;
d07b6bb4 4004 struct hclge_desc desc;
a90bb9a5 4005 u16 egress_port = 0;
aa7a795e 4006 int ret;
46a3df9f
S		 4007
4008 /* mac addr check */
4009 if (is_zero_ether_addr(addr) ||
4010 is_broadcast_ether_addr(addr) ||
4011 is_multicast_ether_addr(addr)) {
4012 dev_err(&hdev->pdev->dev,
4013 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
4014 addr,
4015 is_zero_ether_addr(addr),
4016 is_broadcast_ether_addr(addr),
4017 is_multicast_ether_addr(addr));
4018 return -EINVAL;
4019 }
4020
4021 memset(&req, 0, sizeof(req));
e4e87715 4022 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
a90bb9a5 4023
e4e87715
PL		 4024 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
4025 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5
YL		 4026
4027 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 4028
4029 hclge_prepare_mac_addr(&req, addr);
4030
d07b6bb4
JS		 4031 /* Lookup the mac address in the mac_vlan table, and add
4032 * it if the entry is inexistent. Repeated unicast entry
4033 * is not allowed in the mac vlan table.
4034 */
4035 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
4036 if (ret == -ENOENT)
4037 return hclge_add_mac_vlan_tbl(vport, &req, NULL);
4038
4039 /* check if we just hit the duplicate */
4040 if (!ret)
4041 ret = -EINVAL;
4042
4043 dev_err(&hdev->pdev->dev,
4044 "PF failed to add unicast entry(%pM) in the MAC table\n",
4045 addr);
46a3df9f 4046
aa7a795e 4047 return ret;
46a3df9f
S		 4048}
4049
4050static int hclge_rm_uc_addr(struct hnae3_handle *handle,
4051 const unsigned char *addr)
4052{
4053 struct hclge_vport *vport = hclge_get_vport(handle);
4054
4055 return hclge_rm_uc_addr_common(vport, addr);
4056}
4057
4058int hclge_rm_uc_addr_common(struct hclge_vport *vport,
4059 const unsigned char *addr)
4060{
4061 struct hclge_dev *hdev = vport->back;
d44f9b63 4062 struct hclge_mac_vlan_tbl_entry_cmd req;
aa7a795e 4063 int ret;
46a3df9f
S		 4064
4065 /* mac addr check */
4066 if (is_zero_ether_addr(addr) ||
4067 is_broadcast_ether_addr(addr) ||
4068 is_multicast_ether_addr(addr)) {
4069 dev_dbg(&hdev->pdev->dev,
4070 "Remove mac err! invalid mac:%pM.\n",
4071 addr);
4072 return -EINVAL;
4073 }
4074
4075 memset(&req, 0, sizeof(req));
e4e87715
PL		 4076 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4077 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f 4078 hclge_prepare_mac_addr(&req, addr);
aa7a795e 4079 ret = hclge_remove_mac_vlan_tbl(vport, &req);
46a3df9f 4080
aa7a795e 4081 return ret;
46a3df9f
S		 4082}
4083
4084static int hclge_add_mc_addr(struct hnae3_handle *handle,
4085 const unsigned char *addr)
4086{
4087 struct hclge_vport *vport = hclge_get_vport(handle);
4088
a10829c4 4089 return hclge_add_mc_addr_common(vport, addr);
46a3df9f
S		 4090}
4091
4092int hclge_add_mc_addr_common(struct hclge_vport *vport,
4093 const unsigned char *addr)
4094{
4095 struct hclge_dev *hdev = vport->back;
d44f9b63 4096 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4097 struct hclge_desc desc[3];
4098 u16 tbl_idx;
4099 int status;
4100
4101 /* mac addr check */
4102 if (!is_multicast_ether_addr(addr)) {
4103 dev_err(&hdev->pdev->dev,
4104 "Add mc mac err! invalid mac:%pM.\n",
4105 addr);
4106 return -EINVAL;
4107 }
4108 memset(&req, 0, sizeof(req));
e4e87715
PL		 4109 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4110 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4111 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
fd5f9da3 4112 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 4113 hclge_prepare_mac_addr(&req, addr);
4114 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4115 if (!status) {
4116 /* This mac addr exist, update VFID for it */
4117 hclge_update_desc_vfid(desc, vport->vport_id, false);
4118 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4119 } else {
4120 /* This mac addr do not exist, add new entry for it */
4121 memset(desc[0].data, 0, sizeof(desc[0].data));
4122 memset(desc[1].data, 0, sizeof(desc[0].data));
4123 memset(desc[2].data, 0, sizeof(desc[0].data));
4124 hclge_update_desc_vfid(desc, vport->vport_id, false);
4125 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4126 }
4127
40cca1c5
XW		 4128 /* If mc mac vlan table is full, use MTA table */
4129 if (status == -ENOSPC) {
4130 if (!vport->accept_mta_mc) {
4131 status = hclge_cfg_func_mta_filter(hdev,
4132 vport->vport_id,
4133 true);
4134 if (status) {
4135 dev_err(&hdev->pdev->dev,
4136 "set mta filter mode fail ret=%d\n",
4137 status);
4138 return status;
4139 }
4140 vport->accept_mta_mc = true;
4141 }
4142
4143 /* Set MTA table for this MAC address */
4144 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4145 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4146 }
46a3df9f
S		 4147
4148 return status;
4149}
4150
4151static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4152 const unsigned char *addr)
4153{
4154 struct hclge_vport *vport = hclge_get_vport(handle);
4155
4156 return hclge_rm_mc_addr_common(vport, addr);
4157}
4158
4159int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4160 const unsigned char *addr)
4161{
4162 struct hclge_dev *hdev = vport->back;
d44f9b63 4163 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4164 enum hclge_cmd_status status;
4165 struct hclge_desc desc[3];
46a3df9f
S		 4166
4167 /* mac addr check */
4168 if (!is_multicast_ether_addr(addr)) {
4169 dev_dbg(&hdev->pdev->dev,
4170 "Remove mc mac err! invalid mac:%pM.\n",
4171 addr);
4172 return -EINVAL;
4173 }
4174
4175 memset(&req, 0, sizeof(req));
e4e87715
PL		 4176 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4177 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4178 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
fd5f9da3 4179 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 4180 hclge_prepare_mac_addr(&req, addr);
4181 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4182 if (!status) {
4183 /* This mac addr exist, remove this handle's VFID for it */
4184 hclge_update_desc_vfid(desc, vport->vport_id, true);
4185
4186 if (hclge_is_all_function_id_zero(desc))
4187 /* All the vfid is zero, so need to delete this entry */
4188 status = hclge_remove_mac_vlan_tbl(vport, &req);
4189 else
4190 /* Not all the vfid is zero, update the vfid */
4191 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4192
4193 } else {
40cca1c5
XW		 4194 /* Maybe this mac address is in mta table, but it cannot be
4195 * deleted here because an entry of mta represents an address
4196 * range rather than a specific address. the delete action to
4197 * all entries will take effect in update_mta_status called by
4198 * hns3_nic_set_rx_mode.
4199 */
4200 status = 0;
46a3df9f
S		 4201 }
4202
46a3df9f
S		 4203 return status;
4204}
4205
f5aac71c
FL		 4206static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
4207 u16 cmdq_resp, u8 resp_code)
4208{
4209#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
4210#define HCLGE_ETHERTYPE_ALREADY_ADD 1
4211#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
4212#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
4213
4214 int return_status;
4215
4216 if (cmdq_resp) {
4217 dev_err(&hdev->pdev->dev,
4218 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
4219 cmdq_resp);
4220 return -EIO;
4221 }
4222
4223 switch (resp_code) {
4224 case HCLGE_ETHERTYPE_SUCCESS_ADD:
4225 case HCLGE_ETHERTYPE_ALREADY_ADD:
4226 return_status = 0;
4227 break;
4228 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
4229 dev_err(&hdev->pdev->dev,
4230 "add mac ethertype failed for manager table overflow.\n");
4231 return_status = -EIO;
4232 break;
4233 case HCLGE_ETHERTYPE_KEY_CONFLICT:
4234 dev_err(&hdev->pdev->dev,
4235 "add mac ethertype failed for key conflict.\n");
4236 return_status = -EIO;
4237 break;
4238 default:
4239 dev_err(&hdev->pdev->dev,
4240 "add mac ethertype failed for undefined, code=%d.\n",
4241 resp_code);
4242 return_status = -EIO;
4243 }
4244
4245 return return_status;
4246}
4247
4248static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
4249 const struct hclge_mac_mgr_tbl_entry_cmd *req)
4250{
4251 struct hclge_desc desc;
4252 u8 resp_code;
4253 u16 retval;
4254 int ret;
4255
4256 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
4257 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
4258
4259 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4260 if (ret) {
4261 dev_err(&hdev->pdev->dev,
4262 "add mac ethertype failed for cmd_send, ret =%d.\n",
4263 ret);
4264 return ret;
4265 }
4266
4267 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
4268 retval = le16_to_cpu(desc.retval);
4269
4270 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
4271}
4272
4273static int init_mgr_tbl(struct hclge_dev *hdev)
4274{
4275 int ret;
4276 int i;
4277
4278 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
4279 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
4280 if (ret) {
4281 dev_err(&hdev->pdev->dev,
4282 "add mac ethertype failed, ret =%d.\n",
4283 ret);
4284 return ret;
4285 }
4286 }
4287
4288 return 0;
4289}
4290
46a3df9f
S		 4291static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4292{
4293 struct hclge_vport *vport = hclge_get_vport(handle);
4294 struct hclge_dev *hdev = vport->back;
4295
4296 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4297}
4298
59098055
FL		 4299static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
4300 bool is_first)
46a3df9f
S		 4301{
4302 const unsigned char *new_addr = (const unsigned char *)p;
4303 struct hclge_vport *vport = hclge_get_vport(handle);
4304 struct hclge_dev *hdev = vport->back;
18838d0c 4305 int ret;
46a3df9f
S		 4306
4307 /* mac addr check */
4308 if (is_zero_ether_addr(new_addr) ||
4309 is_broadcast_ether_addr(new_addr) ||
4310 is_multicast_ether_addr(new_addr)) {
4311 dev_err(&hdev->pdev->dev,
4312 "Change uc mac err! invalid mac:%p.\n",
4313 new_addr);
4314 return -EINVAL;
4315 }
4316
59098055 4317 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 4318 dev_warn(&hdev->pdev->dev,
59098055 4319 "remove old uc mac address fail.\n");
46a3df9f 4320
18838d0c
FL		 4321 ret = hclge_add_uc_addr(handle, new_addr);
4322 if (ret) {
4323 dev_err(&hdev->pdev->dev,
4324 "add uc mac address fail, ret =%d.\n",
4325 ret);
4326
59098055
FL		 4327 if (!is_first &&
4328 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 4329 dev_err(&hdev->pdev->dev,
59098055 4330 "restore uc mac address fail.\n");
18838d0c
FL		 4331
4332 return -EIO;
46a3df9f
S		 4333 }
4334
e98d7183 4335 ret = hclge_pause_addr_cfg(hdev, new_addr);
18838d0c
FL		 4336 if (ret) {
4337 dev_err(&hdev->pdev->dev,
4338 "configure mac pause address fail, ret =%d.\n",
4339 ret);
4340 return -EIO;
4341 }
4342
4343 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4344
4345 return 0;
46a3df9f
S		 4346}
4347
26483246
XW		 4348static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
4349 int cmd)
4350{
4351 struct hclge_vport *vport = hclge_get_vport(handle);
4352 struct hclge_dev *hdev = vport->back;
4353
4354 if (!hdev->hw.mac.phydev)
4355 return -EOPNOTSUPP;
4356
4357 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
4358}
4359
46a3df9f
S		 4360static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4361 bool filter_en)
4362{
d44f9b63 4363 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4364 struct hclge_desc desc;
4365 int ret;
4366
4367 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4368
d44f9b63 4369 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4370 req->vlan_type = vlan_type;
4371 req->vlan_fe = filter_en;
4372
4373 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 4374 if (ret)
46a3df9f
S		 4375 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4376 ret);
46a3df9f 4377
3f639907 4378 return ret;
46a3df9f
S		 4379}
4380
391b5e93
JS		 4381#define HCLGE_FILTER_TYPE_VF 0
4382#define HCLGE_FILTER_TYPE_PORT 1
4383
4384static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
4385{
4386 struct hclge_vport *vport = hclge_get_vport(handle);
4387 struct hclge_dev *hdev = vport->back;
4388
4389 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable);
4390}
4391
dc8131d8
YL		 4392static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4393 bool is_kill, u16 vlan, u8 qos,
4394 __be16 proto)
46a3df9f
S		 4395{
4396#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4397 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4398 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4399 struct hclge_desc desc[2];
4400 u8 vf_byte_val;
4401 u8 vf_byte_off;
4402 int ret;
4403
4404 hclge_cmd_setup_basic_desc(&desc[0],
4405 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4406 hclge_cmd_setup_basic_desc(&desc[1],
4407 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4408
4409 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4410
4411 vf_byte_off = vfid / 8;
4412 vf_byte_val = 1 << (vfid % 8);
4413
d44f9b63
YL		 4414 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4415 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4416
a90bb9a5 4417 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4418 req0->vlan_cfg = is_kill;
4419
4420 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4421 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4422 else
4423 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4424
4425 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4426 if (ret) {
4427 dev_err(&hdev->pdev->dev,
4428 "Send vf vlan command fail, ret =%d.\n",
4429 ret);
4430 return ret;
4431 }
4432
4433 if (!is_kill) {
6c251711 4434#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 4435 if (!req0->resp_code || req0->resp_code == 1)
4436 return 0;
4437
6c251711
YL		 4438 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
4439 dev_warn(&hdev->pdev->dev,
4440 "vf vlan table is full, vf vlan filter is disabled\n");
4441 return 0;
4442 }
4443
46a3df9f
S		 4444 dev_err(&hdev->pdev->dev,
4445 "Add vf vlan filter fail, ret =%d.\n",
4446 req0->resp_code);
4447 } else {
41dafea2 4448#define HCLGE_VF_VLAN_DEL_NO_FOUND 1
46a3df9f
S		 4449 if (!req0->resp_code)
4450 return 0;
4451
41dafea2
YL		 4452 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
4453 dev_warn(&hdev->pdev->dev,
4454 "vlan %d filter is not in vf vlan table\n",
4455 vlan);
4456 return 0;
4457 }
4458
46a3df9f
S		 4459 dev_err(&hdev->pdev->dev,
4460 "Kill vf vlan filter fail, ret =%d.\n",
4461 req0->resp_code);
4462 }
4463
4464 return -EIO;
4465}
4466
dc8131d8
YL		 4467static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
4468 u16 vlan_id, bool is_kill)
46a3df9f 4469{
d44f9b63 4470 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4471 struct hclge_desc desc;
4472 u8 vlan_offset_byte_val;
4473 u8 vlan_offset_byte;
4474 u8 vlan_offset_160;
4475 int ret;
4476
4477 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4478
4479 vlan_offset_160 = vlan_id / 160;
4480 vlan_offset_byte = (vlan_id % 160) / 8;
4481 vlan_offset_byte_val = 1 << (vlan_id % 8);
4482
d44f9b63 4483 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4484 req->vlan_offset = vlan_offset_160;
4485 req->vlan_cfg = is_kill;
4486 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4487
4488 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
dc8131d8
YL		 4489 if (ret)
4490 dev_err(&hdev->pdev->dev,
4491 "port vlan command, send fail, ret =%d.\n", ret);
4492 return ret;
4493}
4494
4495static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
4496 u16 vport_id, u16 vlan_id, u8 qos,
4497 bool is_kill)
4498{
4499 u16 vport_idx, vport_num = 0;
4500 int ret;
4501
daaa8521
YL		 4502 if (is_kill && !vlan_id)
4503 return 0;
4504
dc8131d8
YL		 4505 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
4506 0, proto);
46a3df9f
S		 4507 if (ret) {
4508 dev_err(&hdev->pdev->dev,
dc8131d8
YL		 4509 "Set %d vport vlan filter config fail, ret =%d.\n",
4510 vport_id, ret);
46a3df9f
S		 4511 return ret;
4512 }
4513
dc8131d8
YL		 4514 /* vlan 0 may be added twice when 8021q module is enabled */
4515 if (!is_kill && !vlan_id &&
4516 test_bit(vport_id, hdev->vlan_table[vlan_id]))
4517 return 0;
4518
4519 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 4520 dev_err(&hdev->pdev->dev,
dc8131d8
YL		 4521 "Add port vlan failed, vport %d is already in vlan %d\n",
4522 vport_id, vlan_id);
4523 return -EINVAL;
46a3df9f
S		 4524 }
4525
dc8131d8
YL		 4526 if (is_kill &&
4527 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
4528 dev_err(&hdev->pdev->dev,
4529 "Delete port vlan failed, vport %d is not in vlan %d\n",
4530 vport_id, vlan_id);
4531 return -EINVAL;
4532 }
4533
54e97d11 4534 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
dc8131d8
YL		 4535 vport_num++;
4536
4537 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
4538 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
4539 is_kill);
4540
4541 return ret;
4542}
4543
4544int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
4545 u16 vlan_id, bool is_kill)
4546{
4547 struct hclge_vport *vport = hclge_get_vport(handle);
4548 struct hclge_dev *hdev = vport->back;
4549
4550 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
4551 0, is_kill);
46a3df9f
S		 4552}
4553
4554static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4555 u16 vlan, u8 qos, __be16 proto)
4556{
4557 struct hclge_vport *vport = hclge_get_vport(handle);
4558 struct hclge_dev *hdev = vport->back;
4559
4560 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4561 return -EINVAL;
4562 if (proto != htons(ETH_P_8021Q))
4563 return -EPROTONOSUPPORT;
4564
dc8131d8 4565 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 4566}
4567
5f6ea83f
PL		 4568static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
4569{
4570 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
4571 struct hclge_vport_vtag_tx_cfg_cmd *req;
4572 struct hclge_dev *hdev = vport->back;
4573 struct hclge_desc desc;
4574 int status;
4575
4576 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
4577
4578 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
4579 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
4580 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
e4e87715
PL		 4581 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
4582 vcfg->accept_tag1 ? 1 : 0);
4583 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
4584 vcfg->accept_untag1 ? 1 : 0);
4585 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
4586 vcfg->accept_tag2 ? 1 : 0);
4587 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
4588 vcfg->accept_untag2 ? 1 : 0);
4589 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
4590 vcfg->insert_tag1_en ? 1 : 0);
4591 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
4592 vcfg->insert_tag2_en ? 1 : 0);
4593 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
5f6ea83f
PL		 4594
4595 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4596 req->vf_bitmap[req->vf_offset] =
4597 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4598
4599 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4600 if (status)
4601 dev_err(&hdev->pdev->dev,
4602 "Send port txvlan cfg command fail, ret =%d\n",
4603 status);
4604
4605 return status;
4606}
4607
4608static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
4609{
4610 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
4611 struct hclge_vport_vtag_rx_cfg_cmd *req;
4612 struct hclge_dev *hdev = vport->back;
4613 struct hclge_desc desc;
4614 int status;
4615
4616 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
4617
4618 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
e4e87715
PL		 4619 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
4620 vcfg->strip_tag1_en ? 1 : 0);
4621 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
4622 vcfg->strip_tag2_en ? 1 : 0);
4623 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
4624 vcfg->vlan1_vlan_prionly ? 1 : 0);
4625 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
4626 vcfg->vlan2_vlan_prionly ? 1 : 0);
5f6ea83f
PL		 4627
4628 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
4629 req->vf_bitmap[req->vf_offset] =
4630 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
4631
4632 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4633 if (status)
4634 dev_err(&hdev->pdev->dev,
4635 "Send port rxvlan cfg command fail, ret =%d\n",
4636 status);
4637
4638 return status;
4639}
4640
4641static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
4642{
4643 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
4644 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
4645 struct hclge_desc desc;
4646 int status;
4647
4648 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
4649 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
4650 rx_req->ot_fst_vlan_type =
4651 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
4652 rx_req->ot_sec_vlan_type =
4653 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
4654 rx_req->in_fst_vlan_type =
4655 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
4656 rx_req->in_sec_vlan_type =
4657 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
4658
4659 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4660 if (status) {
4661 dev_err(&hdev->pdev->dev,
4662 "Send rxvlan protocol type command fail, ret =%d\n",
4663 status);
4664 return status;
4665 }
4666
4667 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
4668
d0d72bac 4669 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
5f6ea83f
PL		 4670 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
4671 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
4672
4673 status = hclge_cmd_send(&hdev->hw, &desc, 1);
4674 if (status)
4675 dev_err(&hdev->pdev->dev,
4676 "Send txvlan protocol type command fail, ret =%d\n",
4677 status);
4678
4679 return status;
4680}
4681
46a3df9f
S		 4682static int hclge_init_vlan_config(struct hclge_dev *hdev)
4683{
5f6ea83f
PL		 4684#define HCLGE_DEF_VLAN_TYPE 0x8100
4685
5e43aef8 4686 struct hnae3_handle *handle;
5f6ea83f 4687 struct hclge_vport *vport;
46a3df9f 4688 int ret;
5f6ea83f
PL		 4689 int i;
4690
4691 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true);
4692 if (ret)
4693 return ret;
46a3df9f 4694
5f6ea83f 4695 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true);
46a3df9f
S		 4696 if (ret)
4697 return ret;
4698
5f6ea83f
PL		 4699 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4700 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4701 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
4702 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
4703 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
4704 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
4705
4706 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 4707 if (ret)
4708 return ret;
46a3df9f 4709
5f6ea83f
PL		 4710 for (i = 0; i < hdev->num_alloc_vport; i++) {
4711 vport = &hdev->vport[i];
dcb35cce
PL		 4712 vport->txvlan_cfg.accept_tag1 = true;
4713 vport->txvlan_cfg.accept_untag1 = true;
4714
4715 /* accept_tag2 and accept_untag2 are not supported on
4716 * pdev revision(0x20), new revision support them. The
4717 * value of this two fields will not return error when driver
4718 * send command to fireware in revision(0x20).
4719 * This two fields can not configured by user.
4720 */
4721 vport->txvlan_cfg.accept_tag2 = true;
4722 vport->txvlan_cfg.accept_untag2 = true;
4723
5f6ea83f
PL		 4724 vport->txvlan_cfg.insert_tag1_en = false;
4725 vport->txvlan_cfg.insert_tag2_en = false;
4726 vport->txvlan_cfg.default_tag1 = 0;
4727 vport->txvlan_cfg.default_tag2 = 0;
4728
4729 ret = hclge_set_vlan_tx_offload_cfg(vport);
4730 if (ret)
4731 return ret;
4732
4733 vport->rxvlan_cfg.strip_tag1_en = false;
4734 vport->rxvlan_cfg.strip_tag2_en = true;
4735 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4736 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4737
4738 ret = hclge_set_vlan_rx_offload_cfg(vport);
4739 if (ret)
4740 return ret;
4741 }
4742
5e43aef8 4743 handle = &hdev->vport[0].nic;
dc8131d8 4744 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4745}
4746
b2641e2a 4747int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
052ece6d
PL		 4748{
4749 struct hclge_vport *vport = hclge_get_vport(handle);
4750
4751 vport->rxvlan_cfg.strip_tag1_en = false;
4752 vport->rxvlan_cfg.strip_tag2_en = enable;
4753 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
4754 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
4755
4756 return hclge_set_vlan_rx_offload_cfg(vport);
4757}
4758
dd72140c 4759static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 4760{
d44f9b63 4761 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 4762 struct hclge_desc desc;
2866ccb2 4763 int max_frm_size;
46a3df9f
S		 4764 int ret;
4765
2866ccb2
FL		 4766 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4767
4768 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
4769 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 4770 return -EINVAL;
4771
2866ccb2
FL		 4772 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
4773
46a3df9f
S		 4774 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4775
d44f9b63 4776 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
2866ccb2 4777 req->max_frm_size = cpu_to_le16(max_frm_size);
8fc7346c 4778 req->min_frm_size = HCLGE_MAC_MIN_FRAME;
46a3df9f
S		 4779
4780 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 4781 if (ret)
46a3df9f 4782 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
3f639907
JS		 4783 else
4784 hdev->mps = max_frm_size;
2866ccb2 4785
3f639907 4786 return ret;
46a3df9f
S		 4787}
4788
dd72140c
FL		 4789static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4790{
4791 struct hclge_vport *vport = hclge_get_vport(handle);
4792 struct hclge_dev *hdev = vport->back;
4793 int ret;
4794
4795 ret = hclge_set_mac_mtu(hdev, new_mtu);
4796 if (ret) {
4797 dev_err(&hdev->pdev->dev,
4798 "Change mtu fail, ret =%d\n", ret);
4799 return ret;
4800 }
4801
4802 ret = hclge_buffer_alloc(hdev);
4803 if (ret)
4804 dev_err(&hdev->pdev->dev,
4805 "Allocate buffer fail, ret =%d\n", ret);
4806
4807 return ret;
4808}
4809
46a3df9f
S		 4810static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4811 bool enable)
4812{
d44f9b63 4813 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4814 struct hclge_desc desc;
4815 int ret;
4816
4817 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4818
d44f9b63 4819 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f 4820 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
e4e87715 4821 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
46a3df9f
S		 4822
4823 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4824 if (ret) {
4825 dev_err(&hdev->pdev->dev,
4826 "Send tqp reset cmd error, status =%d\n", ret);
4827 return ret;
4828 }
4829
4830 return 0;
4831}
4832
4833static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4834{
d44f9b63 4835 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4836 struct hclge_desc desc;
4837 int ret;
4838
4839 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4840
d44f9b63 4841 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4842 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4843
4844 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4845 if (ret) {
4846 dev_err(&hdev->pdev->dev,
4847 "Get reset status error, status =%d\n", ret);
4848 return ret;
4849 }
4850
e4e87715 4851 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
46a3df9f
S		 4852}
4853
814e0274
PL		 4854static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
4855 u16 queue_id)
4856{
4857 struct hnae3_queue *queue;
4858 struct hclge_tqp *tqp;
4859
4860 queue = handle->kinfo.tqp[queue_id];
4861 tqp = container_of(queue, struct hclge_tqp, q);
4862
4863 return tqp->index;
4864}
4865
84e095d6 4866void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 4867{
4868 struct hclge_vport *vport = hclge_get_vport(handle);
4869 struct hclge_dev *hdev = vport->back;
4870 int reset_try_times = 0;
4871 int reset_status;
814e0274 4872 u16 queue_gid;
46a3df9f
S		 4873 int ret;
4874
b50ae26c
PL		 4875 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
4876 return;
4877
814e0274
PL		 4878 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
4879
46a3df9f
S		 4880 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4881 if (ret) {
4882 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4883 return;
4884 }
4885
814e0274 4886 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f
S		 4887 if (ret) {
4888 dev_warn(&hdev->pdev->dev,
4889 "Send reset tqp cmd fail, ret = %d\n", ret);
4890 return;
4891 }
4892
4893 reset_try_times = 0;
4894 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4895 /* Wait for tqp hw reset */
4896 msleep(20);
814e0274 4897 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 4898 if (reset_status)
4899 break;
4900 }
4901
4902 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4903 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4904 return;
4905 }
4906
814e0274 4907 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
46a3df9f
S		 4908 if (ret) {
4909 dev_warn(&hdev->pdev->dev,
4910 "Deassert the soft reset fail, ret = %d\n", ret);
4911 return;
4912 }
4913}
4914
1a426f8b
PL		 4915void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
4916{
4917 struct hclge_dev *hdev = vport->back;
4918 int reset_try_times = 0;
4919 int reset_status;
4920 u16 queue_gid;
4921 int ret;
4922
4923 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
4924
4925 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
4926 if (ret) {
4927 dev_warn(&hdev->pdev->dev,
4928 "Send reset tqp cmd fail, ret = %d\n", ret);
4929 return;
4930 }
4931
4932 reset_try_times = 0;
4933 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4934 /* Wait for tqp hw reset */
4935 msleep(20);
4936 reset_status = hclge_get_reset_status(hdev, queue_gid);
4937 if (reset_status)
4938 break;
4939 }
4940
4941 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4942 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4943 return;
4944 }
4945
4946 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
4947 if (ret)
4948 dev_warn(&hdev->pdev->dev,
4949 "Deassert the soft reset fail, ret = %d\n", ret);
4950}
4951
46a3df9f
S		 4952static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4953{
4954 struct hclge_vport *vport = hclge_get_vport(handle);
4955 struct hclge_dev *hdev = vport->back;
4956
4957 return hdev->fw_version;
4958}
4959
61387774
PL		 4960static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4961{
4962 struct phy_device *phydev = hdev->hw.mac.phydev;
4963
4964 if (!phydev)
4965 return;
4966
70814e81 4967 phy_set_asym_pause(phydev, rx_en, tx_en);
61387774
PL		 4968}
4969
4970static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
4971{
61387774
PL		 4972 int ret;
4973
4974 if (rx_en && tx_en)
40173a2e 4975 hdev->fc_mode_last_time = HCLGE_FC_FULL;
61387774 4976 else if (rx_en && !tx_en)
40173a2e 4977 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
61387774 4978 else if (!rx_en && tx_en)
40173a2e 4979 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
61387774 4980 else
40173a2e 4981 hdev->fc_mode_last_time = HCLGE_FC_NONE;
61387774 4982
40173a2e 4983 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
61387774 4984 return 0;
61387774
PL		 4985
4986 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
4987 if (ret) {
4988 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
4989 ret);
4990 return ret;
4991 }
4992
40173a2e 4993 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
61387774
PL		 4994
4995 return 0;
4996}
4997
1770a7a3
PL		 4998int hclge_cfg_flowctrl(struct hclge_dev *hdev)
4999{
5000 struct phy_device *phydev = hdev->hw.mac.phydev;
5001 u16 remote_advertising = 0;
5002 u16 local_advertising = 0;
5003 u32 rx_pause, tx_pause;
5004 u8 flowctl;
5005
5006 if (!phydev->link || !phydev->autoneg)
5007 return 0;
5008
5009 if (phydev->advertising & ADVERTISED_Pause)
5010 local_advertising = ADVERTISE_PAUSE_CAP;
5011
5012 if (phydev->advertising & ADVERTISED_Asym_Pause)
5013 local_advertising |= ADVERTISE_PAUSE_ASYM;
5014
5015 if (phydev->pause)
5016 remote_advertising = LPA_PAUSE_CAP;
5017
5018 if (phydev->asym_pause)
5019 remote_advertising |= LPA_PAUSE_ASYM;
5020
5021 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
5022 remote_advertising);
5023 tx_pause = flowctl & FLOW_CTRL_TX;
5024 rx_pause = flowctl & FLOW_CTRL_RX;
5025
5026 if (phydev->duplex == HCLGE_MAC_HALF) {
5027 tx_pause = 0;
5028 rx_pause = 0;
5029 }
5030
5031 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
5032}
5033
46a3df9f
S		 5034static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
5035 u32 *rx_en, u32 *tx_en)
5036{
5037 struct hclge_vport *vport = hclge_get_vport(handle);
5038 struct hclge_dev *hdev = vport->back;
5039
5040 *auto_neg = hclge_get_autoneg(handle);
5041
5042 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5043 *rx_en = 0;
5044 *tx_en = 0;
5045 return;
5046 }
5047
5048 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
5049 *rx_en = 1;
5050 *tx_en = 0;
5051 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
5052 *tx_en = 1;
5053 *rx_en = 0;
5054 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
5055 *rx_en = 1;
5056 *tx_en = 1;
5057 } else {
5058 *rx_en = 0;
5059 *tx_en = 0;
5060 }
5061}
5062
61387774
PL		 5063static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
5064 u32 rx_en, u32 tx_en)
5065{
5066 struct hclge_vport *vport = hclge_get_vport(handle);
5067 struct hclge_dev *hdev = vport->back;
5068 struct phy_device *phydev = hdev->hw.mac.phydev;
5069 u32 fc_autoneg;
5070
61387774
PL		 5071 fc_autoneg = hclge_get_autoneg(handle);
5072 if (auto_neg != fc_autoneg) {
5073 dev_info(&hdev->pdev->dev,
5074 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
5075 return -EOPNOTSUPP;
5076 }
5077
5078 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
5079 dev_info(&hdev->pdev->dev,
5080 "Priority flow control enabled. Cannot set link flow control.\n");
5081 return -EOPNOTSUPP;
5082 }
5083
5084 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
5085
5086 if (!fc_autoneg)
5087 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
5088
0c963e8c
FL		 5089 /* Only support flow control negotiation for netdev with
5090 * phy attached for now.
5091 */
5092 if (!phydev)
5093 return -EOPNOTSUPP;
5094
61387774
PL		 5095 return phy_start_aneg(phydev);
5096}
5097
46a3df9f
S		 5098static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
5099 u8 *auto_neg, u32 *speed, u8 *duplex)
5100{
5101 struct hclge_vport *vport = hclge_get_vport(handle);
5102 struct hclge_dev *hdev = vport->back;
5103
5104 if (speed)
5105 *speed = hdev->hw.mac.speed;
5106 if (duplex)
5107 *duplex = hdev->hw.mac.duplex;
5108 if (auto_neg)
5109 *auto_neg = hdev->hw.mac.autoneg;
5110}
5111
5112static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
5113{
5114 struct hclge_vport *vport = hclge_get_vport(handle);
5115 struct hclge_dev *hdev = vport->back;
5116
5117 if (media_type)
5118 *media_type = hdev->hw.mac.media_type;
5119}
5120
5121static void hclge_get_mdix_mode(struct hnae3_handle *handle,
5122 u8 *tp_mdix_ctrl, u8 *tp_mdix)
5123{
5124 struct hclge_vport *vport = hclge_get_vport(handle);
5125 struct hclge_dev *hdev = vport->back;
5126 struct phy_device *phydev = hdev->hw.mac.phydev;
5127 int mdix_ctrl, mdix, retval, is_resolved;
5128
5129 if (!phydev) {
5130 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5131 *tp_mdix = ETH_TP_MDI_INVALID;
5132 return;
5133 }
5134
5135 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
5136
5137 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
e4e87715
PL		 5138 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
5139 HCLGE_PHY_MDIX_CTRL_S);
46a3df9f
S		 5140
5141 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
e4e87715
PL		 5142 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
5143 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
46a3df9f
S		 5144
5145 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
5146
5147 switch (mdix_ctrl) {
5148 case 0x0:
5149 *tp_mdix_ctrl = ETH_TP_MDI;
5150 break;
5151 case 0x1:
5152 *tp_mdix_ctrl = ETH_TP_MDI_X;
5153 break;
5154 case 0x3:
5155 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
5156 break;
5157 default:
5158 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
5159 break;
5160 }
5161
5162 if (!is_resolved)
5163 *tp_mdix = ETH_TP_MDI_INVALID;
5164 else if (mdix)
5165 *tp_mdix = ETH_TP_MDI_X;
5166 else
5167 *tp_mdix = ETH_TP_MDI;
5168}
5169
b01b7cf1
FL		 5170static int hclge_init_instance_hw(struct hclge_dev *hdev)
5171{
5172 return hclge_mac_connect_phy(hdev);
5173}
5174
5175static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
5176{
5177 hclge_mac_disconnect_phy(hdev);
5178}
5179
46a3df9f
S		 5180static int hclge_init_client_instance(struct hnae3_client *client,
5181 struct hnae3_ae_dev *ae_dev)
5182{
5183 struct hclge_dev *hdev = ae_dev->priv;
5184 struct hclge_vport *vport;
5185 int i, ret;
5186
5187 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5188 vport = &hdev->vport[i];
5189
5190 switch (client->type) {
5191 case HNAE3_CLIENT_KNIC:
5192
5193 hdev->nic_client = client;
5194 vport->nic.client = client;
5195 ret = client->ops->init_instance(&vport->nic);
5196 if (ret)
49dd8054 5197 goto clear_nic;
46a3df9f 5198
b01b7cf1
FL		 5199 ret = hclge_init_instance_hw(hdev);
5200 if (ret) {
5201 client->ops->uninit_instance(&vport->nic,
5202 0);
49dd8054 5203 goto clear_nic;
b01b7cf1
FL		 5204 }
5205
d9f28fc2
JS		 5206 hnae3_set_client_init_flag(client, ae_dev, 1);
5207
46a3df9f 5208 if (hdev->roce_client &&
e92a0843 5209 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5210 struct hnae3_client *rc = hdev->roce_client;
5211
5212 ret = hclge_init_roce_base_info(vport);
5213 if (ret)
49dd8054 5214 goto clear_roce;
46a3df9f
S		 5215
5216 ret = rc->ops->init_instance(&vport->roce);
5217 if (ret)
49dd8054 5218 goto clear_roce;
d9f28fc2
JS		 5219
5220 hnae3_set_client_init_flag(hdev->roce_client,
5221 ae_dev, 1);
46a3df9f
S		 5222 }
5223
5224 break;
5225 case HNAE3_CLIENT_UNIC:
5226 hdev->nic_client = client;
5227 vport->nic.client = client;
5228
5229 ret = client->ops->init_instance(&vport->nic);
5230 if (ret)
49dd8054 5231 goto clear_nic;
46a3df9f 5232
d9f28fc2
JS		 5233 hnae3_set_client_init_flag(client, ae_dev, 1);
5234
46a3df9f
S		 5235 break;
5236 case HNAE3_CLIENT_ROCE:
e92a0843 5237 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 5238 hdev->roce_client = client;
5239 vport->roce.client = client;
5240 }
5241
3a46f34d 5242 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 5243 ret = hclge_init_roce_base_info(vport);
5244 if (ret)
49dd8054 5245 goto clear_roce;
46a3df9f
S		 5246
5247 ret = client->ops->init_instance(&vport->roce);
5248 if (ret)
49dd8054 5249 goto clear_roce;
d9f28fc2
JS		 5250
5251 hnae3_set_client_init_flag(client, ae_dev, 1);
46a3df9f 5252 }
fa7a4bd5
JS		 5253
5254 break;
5255 default:
5256 return -EINVAL;
46a3df9f
S		 5257 }
5258 }
5259
5260 return 0;
49dd8054
JS		 5261
5262clear_nic:
5263 hdev->nic_client = NULL;
5264 vport->nic.client = NULL;
5265 return ret;
5266clear_roce:
5267 hdev->roce_client = NULL;
5268 vport->roce.client = NULL;
5269 return ret;
46a3df9f
S		 5270}
5271
5272static void hclge_uninit_client_instance(struct hnae3_client *client,
5273 struct hnae3_ae_dev *ae_dev)
5274{
5275 struct hclge_dev *hdev = ae_dev->priv;
5276 struct hclge_vport *vport;
5277 int i;
5278
5279 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
5280 vport = &hdev->vport[i];
a17dcf3f 5281 if (hdev->roce_client) {
46a3df9f
S		 5282 hdev->roce_client->ops->uninit_instance(&vport->roce,
5283 0);
a17dcf3f
L		 5284 hdev->roce_client = NULL;
5285 vport->roce.client = NULL;
5286 }
46a3df9f
S		 5287 if (client->type == HNAE3_CLIENT_ROCE)
5288 return;
49dd8054 5289 if (hdev->nic_client && client->ops->uninit_instance) {
b01b7cf1 5290 hclge_uninit_instance_hw(hdev);
46a3df9f 5291 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 5292 hdev->nic_client = NULL;
5293 vport->nic.client = NULL;
5294 }
46a3df9f
S		 5295 }
5296}
5297
5298static int hclge_pci_init(struct hclge_dev *hdev)
5299{
5300 struct pci_dev *pdev = hdev->pdev;
5301 struct hclge_hw *hw;
5302 int ret;
5303
5304 ret = pci_enable_device(pdev);
5305 if (ret) {
5306 dev_err(&pdev->dev, "failed to enable PCI device\n");
3e249d3b 5307 return ret;
46a3df9f
S		 5308 }
5309
5310 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
5311 if (ret) {
5312 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
5313 if (ret) {
5314 dev_err(&pdev->dev,
5315 "can't set consistent PCI DMA");
5316 goto err_disable_device;
5317 }
5318 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
5319 }
5320
5321 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
5322 if (ret) {
5323 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
5324 goto err_disable_device;
5325 }
5326
5327 pci_set_master(pdev);
5328 hw = &hdev->hw;
46a3df9f
S		 5329 hw->io_base = pcim_iomap(pdev, 2, 0);
5330 if (!hw->io_base) {
5331 dev_err(&pdev->dev, "Can't map configuration register space\n");
5332 ret = -ENOMEM;
5333 goto err_clr_master;
5334 }
5335
709eb41a
L		 5336 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
5337
46a3df9f
S		 5338 return 0;
5339err_clr_master:
5340 pci_clear_master(pdev);
5341 pci_release_regions(pdev);
5342err_disable_device:
5343 pci_disable_device(pdev);
46a3df9f
S		 5344
5345 return ret;
5346}
5347
5348static void hclge_pci_uninit(struct hclge_dev *hdev)
5349{
5350 struct pci_dev *pdev = hdev->pdev;
5351
6a814413 5352 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 5353 pci_free_irq_vectors(pdev);
46a3df9f
S		 5354 pci_clear_master(pdev);
5355 pci_release_mem_regions(pdev);
5356 pci_disable_device(pdev);
5357}
5358
48569cda
PL		 5359static void hclge_state_init(struct hclge_dev *hdev)
5360{
5361 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
5362 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5363 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
5364 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
5365 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
5366 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
5367}
5368
5369static void hclge_state_uninit(struct hclge_dev *hdev)
5370{
5371 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5372
5373 if (hdev->service_timer.function)
5374 del_timer_sync(&hdev->service_timer);
5375 if (hdev->service_task.func)
5376 cancel_work_sync(&hdev->service_task);
5377 if (hdev->rst_service_task.func)
5378 cancel_work_sync(&hdev->rst_service_task);
5379 if (hdev->mbx_service_task.func)
5380 cancel_work_sync(&hdev->mbx_service_task);
5381}
5382
46a3df9f
S		 5383static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
5384{
5385 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 5386 struct hclge_dev *hdev;
5387 int ret;
5388
5389 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
5390 if (!hdev) {
5391 ret = -ENOMEM;
ffd5656e 5392 goto out;
46a3df9f
S		 5393 }
5394
46a3df9f
S		 5395 hdev->pdev = pdev;
5396 hdev->ae_dev = ae_dev;
4ed340ab 5397 hdev->reset_type = HNAE3_NONE_RESET;
46a3df9f
S		 5398 ae_dev->priv = hdev;
5399
46a3df9f
S		 5400 ret = hclge_pci_init(hdev);
5401 if (ret) {
5402 dev_err(&pdev->dev, "PCI init failed\n");
ffd5656e 5403 goto out;
46a3df9f
S		 5404 }
5405
3efb960f
L		 5406 /* Firmware command queue initialize */
5407 ret = hclge_cmd_queue_init(hdev);
5408 if (ret) {
5409 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
ffd5656e 5410 goto err_pci_uninit;
3efb960f
L		 5411 }
5412
5413 /* Firmware command initialize */
46a3df9f
S		 5414 ret = hclge_cmd_init(hdev);
5415 if (ret)
ffd5656e 5416 goto err_cmd_uninit;
46a3df9f
S		 5417
5418 ret = hclge_get_cap(hdev);
5419 if (ret) {
e00e2197
CIK		 5420 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5421 ret);
ffd5656e 5422 goto err_cmd_uninit;
46a3df9f
S		 5423 }
5424
5425 ret = hclge_configure(hdev);
5426 if (ret) {
5427 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
ffd5656e 5428 goto err_cmd_uninit;
46a3df9f
S		 5429 }
5430
887c3820 5431 ret = hclge_init_msi(hdev);
46a3df9f 5432 if (ret) {
887c3820 5433 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
ffd5656e 5434 goto err_cmd_uninit;
46a3df9f
S		 5435 }
5436
466b0c00
L		 5437 ret = hclge_misc_irq_init(hdev);
5438 if (ret) {
5439 dev_err(&pdev->dev,
5440 "Misc IRQ(vector0) init error, ret = %d.\n",
5441 ret);
ffd5656e 5442 goto err_msi_uninit;
466b0c00
L		 5443 }
5444
46a3df9f
S		 5445 ret = hclge_alloc_tqps(hdev);
5446 if (ret) {
5447 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
ffd5656e 5448 goto err_msi_irq_uninit;
46a3df9f
S		 5449 }
5450
5451 ret = hclge_alloc_vport(hdev);
5452 if (ret) {
5453 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
ffd5656e 5454 goto err_msi_irq_uninit;
46a3df9f
S		 5455 }
5456
7df7dad6
L		 5457 ret = hclge_map_tqp(hdev);
5458 if (ret) {
5459 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
2312e050 5460 goto err_msi_irq_uninit;
7df7dad6
L		 5461 }
5462
c5ef83cb
HT		 5463 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
5464 ret = hclge_mac_mdio_config(hdev);
5465 if (ret) {
5466 dev_err(&hdev->pdev->dev,
5467 "mdio config fail ret=%d\n", ret);
2312e050 5468 goto err_msi_irq_uninit;
c5ef83cb 5469 }
cf9cca2d 5470 }
5471
46a3df9f
S		 5472 ret = hclge_mac_init(hdev);
5473 if (ret) {
5474 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
ffd5656e 5475 goto err_mdiobus_unreg;
46a3df9f 5476 }
46a3df9f
S		 5477
5478 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5479 if (ret) {
5480 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
ffd5656e 5481 goto err_mdiobus_unreg;
46a3df9f
S		 5482 }
5483
46a3df9f
S		 5484 ret = hclge_init_vlan_config(hdev);
5485 if (ret) {
5486 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
ffd5656e 5487 goto err_mdiobus_unreg;
46a3df9f
S		 5488 }
5489
5490 ret = hclge_tm_schd_init(hdev);
5491 if (ret) {
5492 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
ffd5656e 5493 goto err_mdiobus_unreg;
68ece54e
YL		 5494 }
5495
268f5dfa 5496 hclge_rss_init_cfg(hdev);
68ece54e
YL		 5497 ret = hclge_rss_init_hw(hdev);
5498 if (ret) {
5499 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
ffd5656e 5500 goto err_mdiobus_unreg;
46a3df9f
S		 5501 }
5502
f5aac71c
FL		 5503 ret = init_mgr_tbl(hdev);
5504 if (ret) {
5505 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
ffd5656e 5506 goto err_mdiobus_unreg;
f5aac71c
FL		 5507 }
5508
cacde272
YL		 5509 hclge_dcb_ops_set(hdev);
5510
d039ef68 5511 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f 5512 INIT_WORK(&hdev->service_task, hclge_service_task);
cb1b9f77 5513 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
c1a81619 5514 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 5515
8e52a602
XW		 5516 hclge_clear_all_event_cause(hdev);
5517
466b0c00
L		 5518 /* Enable MISC vector(vector0) */
5519 hclge_enable_vector(&hdev->misc_vector, true);
5520
48569cda 5521 hclge_state_init(hdev);
46a3df9f
S		 5522
5523 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
5524 return 0;
5525
ffd5656e
HT		 5526err_mdiobus_unreg:
5527 if (hdev->hw.mac.phydev)
5528 mdiobus_unregister(hdev->hw.mac.mdio_bus);
ffd5656e
HT		 5529err_msi_irq_uninit:
5530 hclge_misc_irq_uninit(hdev);
5531err_msi_uninit:
5532 pci_free_irq_vectors(pdev);
5533err_cmd_uninit:
5534 hclge_destroy_cmd_queue(&hdev->hw);
5535err_pci_uninit:
6a814413 5536 pcim_iounmap(pdev, hdev->hw.io_base);
ffd5656e 5537 pci_clear_master(pdev);
46a3df9f 5538 pci_release_regions(pdev);
ffd5656e 5539 pci_disable_device(pdev);
ffd5656e 5540out:
46a3df9f
S		 5541 return ret;
5542}
5543
c6dc5213 5544static void hclge_stats_clear(struct hclge_dev *hdev)
5545{
5546 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
5547}
5548
4ed340ab
L		 5549static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
5550{
5551 struct hclge_dev *hdev = ae_dev->priv;
5552 struct pci_dev *pdev = ae_dev->pdev;
5553 int ret;
5554
5555 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5556
c6dc5213 5557 hclge_stats_clear(hdev);
dc8131d8 5558 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 5559
4ed340ab
L		 5560 ret = hclge_cmd_init(hdev);
5561 if (ret) {
5562 dev_err(&pdev->dev, "Cmd queue init failed\n");
5563 return ret;
5564 }
5565
5566 ret = hclge_get_cap(hdev);
5567 if (ret) {
5568 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
5569 ret);
5570 return ret;
5571 }
5572
5573 ret = hclge_configure(hdev);
5574 if (ret) {
5575 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
5576 return ret;
5577 }
5578
5579 ret = hclge_map_tqp(hdev);
5580 if (ret) {
5581 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
5582 return ret;
5583 }
5584
5585 ret = hclge_mac_init(hdev);
5586 if (ret) {
5587 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
5588 return ret;
5589 }
5590
4ed340ab
L		 5591 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
5592 if (ret) {
5593 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
5594 return ret;
5595 }
5596
5597 ret = hclge_init_vlan_config(hdev);
5598 if (ret) {
5599 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
5600 return ret;
5601 }
5602
f31c1ba6 5603 ret = hclge_tm_init_hw(hdev);
4ed340ab 5604 if (ret) {
f31c1ba6 5605 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 5606 return ret;
5607 }
5608
5609 ret = hclge_rss_init_hw(hdev);
5610 if (ret) {
5611 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
5612 return ret;
5613 }
5614
4ed340ab
L		 5615 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
5616 HCLGE_DRIVER_NAME);
5617
5618 return 0;
5619}
5620
46a3df9f
S		 5621static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
5622{
5623 struct hclge_dev *hdev = ae_dev->priv;
5624 struct hclge_mac *mac = &hdev->hw.mac;
5625
48569cda 5626 hclge_state_uninit(hdev);
46a3df9f
S		 5627
5628 if (mac->phydev)
5629 mdiobus_unregister(mac->mdio_bus);
5630
466b0c00
L		 5631 /* Disable MISC vector(vector0) */
5632 hclge_enable_vector(&hdev->misc_vector, false);
8e52a602
XW		 5633 synchronize_irq(hdev->misc_vector.vector_irq);
5634
46a3df9f 5635 hclge_destroy_cmd_queue(&hdev->hw);
ca1d7669 5636 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 5637 hclge_pci_uninit(hdev);
5638 ae_dev->priv = NULL;
5639}
5640
482d2e9c
PL		 5641static u32 hclge_get_max_channels(struct hnae3_handle *handle)
5642{
5643 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
5644 struct hclge_vport *vport = hclge_get_vport(handle);
5645 struct hclge_dev *hdev = vport->back;
5646
5647 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
5648}
5649
5650static void hclge_get_channels(struct hnae3_handle *handle,
5651 struct ethtool_channels *ch)
5652{
5653 struct hclge_vport *vport = hclge_get_vport(handle);
5654
5655 ch->max_combined = hclge_get_max_channels(handle);
5656 ch->other_count = 1;
5657 ch->max_other = 1;
5658 ch->combined_count = vport->alloc_tqps;
5659}
5660
09f2af64 5661static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
0d43bf45 5662 u16 *alloc_tqps, u16 *max_rss_size)
09f2af64
PL		 5663{
5664 struct hclge_vport *vport = hclge_get_vport(handle);
5665 struct hclge_dev *hdev = vport->back;
09f2af64 5666
0d43bf45 5667 *alloc_tqps = vport->alloc_tqps;
09f2af64
PL		 5668 *max_rss_size = hdev->rss_size_max;
5669}
5670
5671static void hclge_release_tqp(struct hclge_vport *vport)
5672{
5673 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5674 struct hclge_dev *hdev = vport->back;
5675 int i;
5676
5677 for (i = 0; i < kinfo->num_tqps; i++) {
5678 struct hclge_tqp *tqp =
5679 container_of(kinfo->tqp[i], struct hclge_tqp, q);
5680
5681 tqp->q.handle = NULL;
5682 tqp->q.tqp_index = 0;
5683 tqp->alloced = false;
5684 }
5685
5686 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
5687 kinfo->tqp = NULL;
5688}
5689
5690static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
5691{
5692 struct hclge_vport *vport = hclge_get_vport(handle);
5693 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
5694 struct hclge_dev *hdev = vport->back;
5695 int cur_rss_size = kinfo->rss_size;
5696 int cur_tqps = kinfo->num_tqps;
5697 u16 tc_offset[HCLGE_MAX_TC_NUM];
5698 u16 tc_valid[HCLGE_MAX_TC_NUM];
5699 u16 tc_size[HCLGE_MAX_TC_NUM];
5700 u16 roundup_size;
5701 u32 *rss_indir;
5702 int ret, i;
5703
fdace1bc 5704 /* Free old tqps, and reallocate with new tqp number when nic setup */
09f2af64
PL		 5705 hclge_release_tqp(vport);
5706
128b900d 5707 ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc);
09f2af64
PL		 5708 if (ret) {
5709 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
5710 return ret;
5711 }
5712
5713 ret = hclge_map_tqp_to_vport(hdev, vport);
5714 if (ret) {
5715 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
5716 return ret;
5717 }
5718
5719 ret = hclge_tm_schd_init(hdev);
5720 if (ret) {
5721 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
5722 return ret;
5723 }
5724
5725 roundup_size = roundup_pow_of_two(kinfo->rss_size);
5726 roundup_size = ilog2(roundup_size);
5727 /* Set the RSS TC mode according to the new RSS size */
5728 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
5729 tc_valid[i] = 0;
5730
5731 if (!(hdev->hw_tc_map & BIT(i)))
5732 continue;
5733
5734 tc_valid[i] = 1;
5735 tc_size[i] = roundup_size;
5736 tc_offset[i] = kinfo->rss_size * i;
5737 }
5738 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
5739 if (ret)
5740 return ret;
5741
5742 /* Reinitializes the rss indirect table according to the new RSS size */
5743 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
5744 if (!rss_indir)
5745 return -ENOMEM;
5746
5747 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
5748 rss_indir[i] = i % kinfo->rss_size;
5749
5750 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
5751 if (ret)
5752 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
5753 ret);
5754
5755 kfree(rss_indir);
5756
5757 if (!ret)
5758 dev_info(&hdev->pdev->dev,
5759 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
5760 cur_rss_size, kinfo->rss_size,
5761 cur_tqps, kinfo->rss_size * kinfo->num_tc);
5762
5763 return ret;
5764}
5765
77b34110
FL		 5766static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
5767 u32 *regs_num_64_bit)
5768{
5769 struct hclge_desc desc;
5770 u32 total_num;
5771 int ret;
5772
5773 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
5774 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5775 if (ret) {
5776 dev_err(&hdev->pdev->dev,
5777 "Query register number cmd failed, ret = %d.\n", ret);
5778 return ret;
5779 }
5780
5781 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
5782 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
5783
5784 total_num = *regs_num_32_bit + *regs_num_64_bit;
5785 if (!total_num)
5786 return -EINVAL;
5787
5788 return 0;
5789}
5790
5791static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5792 void *data)
5793{
5794#define HCLGE_32_BIT_REG_RTN_DATANUM 8
5795
5796 struct hclge_desc *desc;
5797 u32 *reg_val = data;
5798 __le32 *desc_data;
5799 int cmd_num;
5800 int i, k, n;
5801 int ret;
5802
5803 if (regs_num == 0)
5804 return 0;
5805
5806 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
5807 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5808 if (!desc)
5809 return -ENOMEM;
5810
5811 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
5812 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5813 if (ret) {
5814 dev_err(&hdev->pdev->dev,
5815 "Query 32 bit register cmd failed, ret = %d.\n", ret);
5816 kfree(desc);
5817 return ret;
5818 }
5819
5820 for (i = 0; i < cmd_num; i++) {
5821 if (i == 0) {
5822 desc_data = (__le32 *)(&desc[i].data[0]);
5823 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
5824 } else {
5825 desc_data = (__le32 *)(&desc[i]);
5826 n = HCLGE_32_BIT_REG_RTN_DATANUM;
5827 }
5828 for (k = 0; k < n; k++) {
5829 *reg_val++ = le32_to_cpu(*desc_data++);
5830
5831 regs_num--;
5832 if (!regs_num)
5833 break;
5834 }
5835 }
5836
5837 kfree(desc);
5838 return 0;
5839}
5840
5841static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
5842 void *data)
5843{
5844#define HCLGE_64_BIT_REG_RTN_DATANUM 4
5845
5846 struct hclge_desc *desc;
5847 u64 *reg_val = data;
5848 __le64 *desc_data;
5849 int cmd_num;
5850 int i, k, n;
5851 int ret;
5852
5853 if (regs_num == 0)
5854 return 0;
5855
5856 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
5857 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
5858 if (!desc)
5859 return -ENOMEM;
5860
5861 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
5862 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
5863 if (ret) {
5864 dev_err(&hdev->pdev->dev,
5865 "Query 64 bit register cmd failed, ret = %d.\n", ret);
5866 kfree(desc);
5867 return ret;
5868 }
5869
5870 for (i = 0; i < cmd_num; i++) {
5871 if (i == 0) {
5872 desc_data = (__le64 *)(&desc[i].data[0]);
5873 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
5874 } else {
5875 desc_data = (__le64 *)(&desc[i]);
5876 n = HCLGE_64_BIT_REG_RTN_DATANUM;
5877 }
5878 for (k = 0; k < n; k++) {
5879 *reg_val++ = le64_to_cpu(*desc_data++);
5880
5881 regs_num--;
5882 if (!regs_num)
5883 break;
5884 }
5885 }
5886
5887 kfree(desc);
5888 return 0;
5889}
5890
5891static int hclge_get_regs_len(struct hnae3_handle *handle)
5892{
5893 struct hclge_vport *vport = hclge_get_vport(handle);
5894 struct hclge_dev *hdev = vport->back;
5895 u32 regs_num_32_bit, regs_num_64_bit;
5896 int ret;
5897
5898 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5899 if (ret) {
5900 dev_err(&hdev->pdev->dev,
5901 "Get register number failed, ret = %d.\n", ret);
5902 return -EOPNOTSUPP;
5903 }
5904
5905 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
5906}
5907
5908static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
5909 void *data)
5910{
5911 struct hclge_vport *vport = hclge_get_vport(handle);
5912 struct hclge_dev *hdev = vport->back;
5913 u32 regs_num_32_bit, regs_num_64_bit;
5914 int ret;
5915
5916 *version = hdev->fw_version;
5917
5918 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
5919 if (ret) {
5920 dev_err(&hdev->pdev->dev,
5921 "Get register number failed, ret = %d.\n", ret);
5922 return;
5923 }
5924
5925 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
5926 if (ret) {
5927 dev_err(&hdev->pdev->dev,
5928 "Get 32 bit register failed, ret = %d.\n", ret);
5929 return;
5930 }
5931
5932 data = (u32 *)data + regs_num_32_bit;
5933 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
5934 data);
5935 if (ret)
5936 dev_err(&hdev->pdev->dev,
5937 "Get 64 bit register failed, ret = %d.\n", ret);
5938}
5939
f6f75abc 5940static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
07f8e940
JS		 5941{
5942 struct hclge_set_led_state_cmd *req;
5943 struct hclge_desc desc;
5944 int ret;
5945
5946 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
5947
5948 req = (struct hclge_set_led_state_cmd *)desc.data;
e4e87715
PL		 5949 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
5950 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
07f8e940
JS		 5951
5952 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5953 if (ret)
5954 dev_err(&hdev->pdev->dev,
5955 "Send set led state cmd error, ret =%d\n", ret);
5956
5957 return ret;
5958}
5959
5960enum hclge_led_status {
5961 HCLGE_LED_OFF,
5962 HCLGE_LED_ON,
5963 HCLGE_LED_NO_CHANGE = 0xFF,
5964};
5965
5966static int hclge_set_led_id(struct hnae3_handle *handle,
5967 enum ethtool_phys_id_state status)
5968{
07f8e940
JS		 5969 struct hclge_vport *vport = hclge_get_vport(handle);
5970 struct hclge_dev *hdev = vport->back;
07f8e940
JS		 5971
5972 switch (status) {
5973 case ETHTOOL_ID_ACTIVE:
f6f75abc 5974 return hclge_set_led_status(hdev, HCLGE_LED_ON);
07f8e940 5975 case ETHTOOL_ID_INACTIVE:
f6f75abc 5976 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
07f8e940 5977 default:
f6f75abc 5978 return -EINVAL;
07f8e940 5979 }
07f8e940
JS		 5980}
5981
0979aa0b
FL		 5982static void hclge_get_link_mode(struct hnae3_handle *handle,
5983 unsigned long *supported,
5984 unsigned long *advertising)
5985{
5986 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
5987 struct hclge_vport *vport = hclge_get_vport(handle);
5988 struct hclge_dev *hdev = vport->back;
5989 unsigned int idx = 0;
5990
5991 for (; idx < size; idx++) {
5992 supported[idx] = hdev->hw.mac.supported[idx];
5993 advertising[idx] = hdev->hw.mac.advertising[idx];
5994 }
5995}
5996
46a3df9f
S		 5997static const struct hnae3_ae_ops hclge_ops = {
5998 .init_ae_dev = hclge_init_ae_dev,
5999 .uninit_ae_dev = hclge_uninit_ae_dev,
6000 .init_client_instance = hclge_init_client_instance,
6001 .uninit_client_instance = hclge_uninit_client_instance,
84e095d6
SM		 6002 .map_ring_to_vector = hclge_map_ring_to_vector,
6003 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 6004 .get_vector = hclge_get_vector,
0d3e6631 6005 .put_vector = hclge_put_vector,
46a3df9f 6006 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 6007 .set_loopback = hclge_set_loopback,
46a3df9f
S		 6008 .start = hclge_ae_start,
6009 .stop = hclge_ae_stop,
6010 .get_status = hclge_get_status,
6011 .get_ksettings_an_result = hclge_get_ksettings_an_result,
6012 .update_speed_duplex_h = hclge_update_speed_duplex_h,
6013 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
6014 .get_media_type = hclge_get_media_type,
6015 .get_rss_key_size = hclge_get_rss_key_size,
6016 .get_rss_indir_size = hclge_get_rss_indir_size,
6017 .get_rss = hclge_get_rss,
6018 .set_rss = hclge_set_rss,
f7db940a 6019 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 6020 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 6021 .get_tc_size = hclge_get_tc_size,
6022 .get_mac_addr = hclge_get_mac_addr,
6023 .set_mac_addr = hclge_set_mac_addr,
26483246 6024 .do_ioctl = hclge_do_ioctl,
46a3df9f
S		 6025 .add_uc_addr = hclge_add_uc_addr,
6026 .rm_uc_addr = hclge_rm_uc_addr,
6027 .add_mc_addr = hclge_add_mc_addr,
6028 .rm_mc_addr = hclge_rm_mc_addr,
40cca1c5 6029 .update_mta_status = hclge_update_mta_status,
46a3df9f
S		 6030 .set_autoneg = hclge_set_autoneg,
6031 .get_autoneg = hclge_get_autoneg,
6032 .get_pauseparam = hclge_get_pauseparam,
61387774 6033 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 6034 .set_mtu = hclge_set_mtu,
6035 .reset_queue = hclge_reset_tqp,
6036 .get_stats = hclge_get_stats,
6037 .update_stats = hclge_update_stats,
6038 .get_strings = hclge_get_strings,
6039 .get_sset_count = hclge_get_sset_count,
6040 .get_fw_version = hclge_get_fw_version,
6041 .get_mdix_mode = hclge_get_mdix_mode,
391b5e93 6042 .enable_vlan_filter = hclge_enable_vlan_filter,
dc8131d8 6043 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 6044 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
052ece6d 6045 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 6046 .reset_event = hclge_reset_event,
09f2af64
PL		 6047 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
6048 .set_channels = hclge_set_channels,
482d2e9c 6049 .get_channels = hclge_get_channels,
77b34110
FL		 6050 .get_regs_len = hclge_get_regs_len,
6051 .get_regs = hclge_get_regs,
07f8e940 6052 .set_led_id = hclge_set_led_id,
0979aa0b 6053 .get_link_mode = hclge_get_link_mode,
46a3df9f
S		 6054};
6055
6056static struct hnae3_ae_algo ae_algo = {
6057 .ops = &hclge_ops,
46a3df9f
S		 6058 .pdev_id_table = ae_algo_pci_tbl,
6059};
6060
6061static int hclge_init(void)
6062{
6063 pr_info("%s is initializing\n", HCLGE_NAME);
6064
854cf33a
FL		 6065 hnae3_register_ae_algo(&ae_algo);
6066
6067 return 0;
46a3df9f
S		 6068}
6069
6070static void hclge_exit(void)
6071{
6072 hnae3_unregister_ae_algo(&ae_algo);
6073}
6074module_init(hclge_init);
6075module_exit(hclge_exit);
6076
6077MODULE_LICENSE("GPL");
6078MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
6079MODULE_DESCRIPTION("HCLGE Driver");
6080MODULE_VERSION(HCLGE_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)