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net: hns3: Refactor of the reset interrupt handling logic
[linux-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
46a3df9f
S		 1/*
2 * Copyright (c) 2016-2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#include <linux/acpi.h>
11#include <linux/device.h>
12#include <linux/etherdevice.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/netdevice.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
20
21#include "hclge_cmd.h"
cacde272 22#include "hclge_dcb.h"
46a3df9f
S		 23#include "hclge_main.h"
24#include "hclge_mdio.h"
25#include "hclge_tm.h"
26#include "hnae3.h"
27
28#define HCLGE_NAME "hclge"
29#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
30#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
31#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
32#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
33
46a3df9f
S		 34static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
35 enum hclge_mta_dmac_sel_type mta_mac_sel,
36 bool enable);
37static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 38static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
46a3df9f
S		 39
40static struct hnae3_ae_algo ae_algo;
41
42static const struct pci_device_id ae_algo_pci_tbl[] = {
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
45 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
46 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
47 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
48 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
49 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 50 /* required last entry */
46a3df9f
S		 51 {0, }
52};
53
54static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
55 "Mac Loopback test",
56 "Serdes Loopback test",
57 "Phy Loopback test"
58};
59
60static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
61 {"igu_rx_oversize_pkt",
62 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
63 {"igu_rx_undersize_pkt",
64 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
65 {"igu_rx_out_all_pkt",
66 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
67 {"igu_rx_uni_pkt",
68 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
69 {"igu_rx_multi_pkt",
70 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
71 {"igu_rx_broad_pkt",
72 HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
73 {"egu_tx_out_all_pkt",
74 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
75 {"egu_tx_uni_pkt",
76 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
77 {"egu_tx_multi_pkt",
78 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
79 {"egu_tx_broad_pkt",
80 HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
81 {"ssu_ppp_mac_key_num",
82 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
83 {"ssu_ppp_host_key_num",
84 HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
85 {"ppp_ssu_mac_rlt_num",
86 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
87 {"ppp_ssu_host_rlt_num",
88 HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
89 {"ssu_tx_in_num",
90 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
91 {"ssu_tx_out_num",
92 HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
93 {"ssu_rx_in_num",
94 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
95 {"ssu_rx_out_num",
96 HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
97};
98
99static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
100 {"igu_rx_err_pkt",
101 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
102 {"igu_rx_no_eof_pkt",
103 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
104 {"igu_rx_no_sof_pkt",
105 HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
106 {"egu_tx_1588_pkt",
107 HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
108 {"ssu_full_drop_num",
109 HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
110 {"ssu_part_drop_num",
111 HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
112 {"ppp_key_drop_num",
113 HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
114 {"ppp_rlt_drop_num",
115 HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
116 {"ssu_key_drop_num",
117 HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
118 {"pkt_curr_buf_cnt",
119 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
120 {"qcn_fb_rcv_cnt",
121 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
122 {"qcn_fb_drop_cnt",
123 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
124 {"qcn_fb_invaild_cnt",
125 HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
126 {"rx_packet_tc0_in_cnt",
127 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
128 {"rx_packet_tc1_in_cnt",
129 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
130 {"rx_packet_tc2_in_cnt",
131 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
132 {"rx_packet_tc3_in_cnt",
133 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
134 {"rx_packet_tc4_in_cnt",
135 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
136 {"rx_packet_tc5_in_cnt",
137 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
138 {"rx_packet_tc6_in_cnt",
139 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
140 {"rx_packet_tc7_in_cnt",
141 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
142 {"rx_packet_tc0_out_cnt",
143 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
144 {"rx_packet_tc1_out_cnt",
145 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
146 {"rx_packet_tc2_out_cnt",
147 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
148 {"rx_packet_tc3_out_cnt",
149 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
150 {"rx_packet_tc4_out_cnt",
151 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
152 {"rx_packet_tc5_out_cnt",
153 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
154 {"rx_packet_tc6_out_cnt",
155 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
156 {"rx_packet_tc7_out_cnt",
157 HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
158 {"tx_packet_tc0_in_cnt",
159 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
160 {"tx_packet_tc1_in_cnt",
161 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
162 {"tx_packet_tc2_in_cnt",
163 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
164 {"tx_packet_tc3_in_cnt",
165 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
166 {"tx_packet_tc4_in_cnt",
167 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
168 {"tx_packet_tc5_in_cnt",
169 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
170 {"tx_packet_tc6_in_cnt",
171 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
172 {"tx_packet_tc7_in_cnt",
173 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
174 {"tx_packet_tc0_out_cnt",
175 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
176 {"tx_packet_tc1_out_cnt",
177 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
178 {"tx_packet_tc2_out_cnt",
179 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
180 {"tx_packet_tc3_out_cnt",
181 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
182 {"tx_packet_tc4_out_cnt",
183 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
184 {"tx_packet_tc5_out_cnt",
185 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
186 {"tx_packet_tc6_out_cnt",
187 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
188 {"tx_packet_tc7_out_cnt",
189 HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
190 {"pkt_curr_buf_tc0_cnt",
191 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
192 {"pkt_curr_buf_tc1_cnt",
193 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
194 {"pkt_curr_buf_tc2_cnt",
195 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
196 {"pkt_curr_buf_tc3_cnt",
197 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
198 {"pkt_curr_buf_tc4_cnt",
199 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
200 {"pkt_curr_buf_tc5_cnt",
201 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
202 {"pkt_curr_buf_tc6_cnt",
203 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
204 {"pkt_curr_buf_tc7_cnt",
205 HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
206 {"mb_uncopy_num",
207 HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
208 {"lo_pri_unicast_rlt_drop_num",
209 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
210 {"hi_pri_multicast_rlt_drop_num",
211 HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
212 {"lo_pri_multicast_rlt_drop_num",
213 HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
214 {"rx_oq_drop_pkt_cnt",
215 HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
216 {"tx_oq_drop_pkt_cnt",
217 HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
218 {"nic_l2_err_drop_pkt_cnt",
219 HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
220 {"roc_l2_err_drop_pkt_cnt",
221 HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
222};
223
224static const struct hclge_comm_stats_str g_mac_stats_string[] = {
225 {"mac_tx_mac_pause_num",
226 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
227 {"mac_rx_mac_pause_num",
228 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
229 {"mac_tx_pfc_pri0_pkt_num",
230 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
231 {"mac_tx_pfc_pri1_pkt_num",
232 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
233 {"mac_tx_pfc_pri2_pkt_num",
234 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
235 {"mac_tx_pfc_pri3_pkt_num",
236 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
237 {"mac_tx_pfc_pri4_pkt_num",
238 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
239 {"mac_tx_pfc_pri5_pkt_num",
240 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
241 {"mac_tx_pfc_pri6_pkt_num",
242 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
243 {"mac_tx_pfc_pri7_pkt_num",
244 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
245 {"mac_rx_pfc_pri0_pkt_num",
246 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
247 {"mac_rx_pfc_pri1_pkt_num",
248 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
249 {"mac_rx_pfc_pri2_pkt_num",
250 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
251 {"mac_rx_pfc_pri3_pkt_num",
252 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
253 {"mac_rx_pfc_pri4_pkt_num",
254 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
255 {"mac_rx_pfc_pri5_pkt_num",
256 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
257 {"mac_rx_pfc_pri6_pkt_num",
258 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
259 {"mac_rx_pfc_pri7_pkt_num",
260 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
261 {"mac_tx_total_pkt_num",
262 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
263 {"mac_tx_total_oct_num",
264 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
265 {"mac_tx_good_pkt_num",
266 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
267 {"mac_tx_bad_pkt_num",
268 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
269 {"mac_tx_good_oct_num",
270 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
271 {"mac_tx_bad_oct_num",
272 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
273 {"mac_tx_uni_pkt_num",
274 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
275 {"mac_tx_multi_pkt_num",
276 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
277 {"mac_tx_broad_pkt_num",
278 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
279 {"mac_tx_undersize_pkt_num",
280 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
281 {"mac_tx_overrsize_pkt_num",
282 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
283 {"mac_tx_64_oct_pkt_num",
284 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
285 {"mac_tx_65_127_oct_pkt_num",
286 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
287 {"mac_tx_128_255_oct_pkt_num",
288 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
289 {"mac_tx_256_511_oct_pkt_num",
290 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
291 {"mac_tx_512_1023_oct_pkt_num",
292 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
293 {"mac_tx_1024_1518_oct_pkt_num",
294 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
295 {"mac_tx_1519_max_oct_pkt_num",
296 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
297 {"mac_rx_total_pkt_num",
298 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
299 {"mac_rx_total_oct_num",
300 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
301 {"mac_rx_good_pkt_num",
302 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
303 {"mac_rx_bad_pkt_num",
304 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
305 {"mac_rx_good_oct_num",
306 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
307 {"mac_rx_bad_oct_num",
308 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
309 {"mac_rx_uni_pkt_num",
310 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
311 {"mac_rx_multi_pkt_num",
312 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
313 {"mac_rx_broad_pkt_num",
314 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
315 {"mac_rx_undersize_pkt_num",
316 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
317 {"mac_rx_overrsize_pkt_num",
318 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
319 {"mac_rx_64_oct_pkt_num",
320 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
321 {"mac_rx_65_127_oct_pkt_num",
322 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
323 {"mac_rx_128_255_oct_pkt_num",
324 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
325 {"mac_rx_256_511_oct_pkt_num",
326 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
327 {"mac_rx_512_1023_oct_pkt_num",
328 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
329 {"mac_rx_1024_1518_oct_pkt_num",
330 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
331 {"mac_rx_1519_max_oct_pkt_num",
332 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
333
334 {"mac_trans_fragment_pkt_num",
335 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
336 {"mac_trans_undermin_pkt_num",
337 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
338 {"mac_trans_jabber_pkt_num",
339 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
340 {"mac_trans_err_all_pkt_num",
341 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
342 {"mac_trans_from_app_good_pkt_num",
343 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
344 {"mac_trans_from_app_bad_pkt_num",
345 HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
346 {"mac_rcv_fragment_pkt_num",
347 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
348 {"mac_rcv_undermin_pkt_num",
349 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
350 {"mac_rcv_jabber_pkt_num",
351 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
352 {"mac_rcv_fcs_err_pkt_num",
353 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
354 {"mac_rcv_send_app_good_pkt_num",
355 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
356 {"mac_rcv_send_app_bad_pkt_num",
357 HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
358};
359
360static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
361{
362#define HCLGE_64_BIT_CMD_NUM 5
363#define HCLGE_64_BIT_RTN_DATANUM 4
364 u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
365 struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
a90bb9a5 366 __le64 *desc_data;
46a3df9f
S		 367 int i, k, n;
368 int ret;
369
370 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
371 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
372 if (ret) {
373 dev_err(&hdev->pdev->dev,
374 "Get 64 bit pkt stats fail, status = %d.\n", ret);
375 return ret;
376 }
377
378 for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
379 if (unlikely(i == 0)) {
a90bb9a5 380 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 381 n = HCLGE_64_BIT_RTN_DATANUM - 1;
382 } else {
a90bb9a5 383 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 384 n = HCLGE_64_BIT_RTN_DATANUM;
385 }
386 for (k = 0; k < n; k++) {
a90bb9a5 387 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 388 desc_data++;
389 }
390 }
391
392 return 0;
393}
394
395static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
396{
397 stats->pkt_curr_buf_cnt = 0;
398 stats->pkt_curr_buf_tc0_cnt = 0;
399 stats->pkt_curr_buf_tc1_cnt = 0;
400 stats->pkt_curr_buf_tc2_cnt = 0;
401 stats->pkt_curr_buf_tc3_cnt = 0;
402 stats->pkt_curr_buf_tc4_cnt = 0;
403 stats->pkt_curr_buf_tc5_cnt = 0;
404 stats->pkt_curr_buf_tc6_cnt = 0;
405 stats->pkt_curr_buf_tc7_cnt = 0;
406}
407
408static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
409{
410#define HCLGE_32_BIT_CMD_NUM 8
411#define HCLGE_32_BIT_RTN_DATANUM 8
412
413 struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
414 struct hclge_32_bit_stats *all_32_bit_stats;
a90bb9a5 415 __le32 *desc_data;
46a3df9f
S		 416 int i, k, n;
417 u64 *data;
418 int ret;
419
420 all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
421 data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
422
423 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
424 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
425 if (ret) {
426 dev_err(&hdev->pdev->dev,
427 "Get 32 bit pkt stats fail, status = %d.\n", ret);
428
429 return ret;
430 }
431
432 hclge_reset_partial_32bit_counter(all_32_bit_stats);
433 for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
434 if (unlikely(i == 0)) {
a90bb9a5
YL		 435 __le16 *desc_data_16bit;
436
46a3df9f 437 all_32_bit_stats->igu_rx_err_pkt +=
a90bb9a5
YL		 438 le32_to_cpu(desc[i].data[0]);
439
440 desc_data_16bit = (__le16 *)&desc[i].data[1];
46a3df9f 441 all_32_bit_stats->igu_rx_no_eof_pkt +=
a90bb9a5
YL		 442 le16_to_cpu(*desc_data_16bit);
443
444 desc_data_16bit++;
46a3df9f 445 all_32_bit_stats->igu_rx_no_sof_pkt +=
a90bb9a5 446 le16_to_cpu(*desc_data_16bit);
46a3df9f 447
a90bb9a5 448 desc_data = &desc[i].data[2];
46a3df9f
S		 449 n = HCLGE_32_BIT_RTN_DATANUM - 4;
450 } else {
a90bb9a5 451 desc_data = (__le32 *)&desc[i];
46a3df9f
S		 452 n = HCLGE_32_BIT_RTN_DATANUM;
453 }
454 for (k = 0; k < n; k++) {
a90bb9a5 455 *data++ += le32_to_cpu(*desc_data);
46a3df9f
S		 456 desc_data++;
457 }
458 }
459
460 return 0;
461}
462
463static int hclge_mac_update_stats(struct hclge_dev *hdev)
464{
465#define HCLGE_MAC_CMD_NUM 17
466#define HCLGE_RTN_DATA_NUM 4
467
468 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
469 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 470 __le64 *desc_data;
46a3df9f
S		 471 int i, k, n;
472 int ret;
473
474 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
475 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
476 if (ret) {
477 dev_err(&hdev->pdev->dev,
478 "Get MAC pkt stats fail, status = %d.\n", ret);
479
480 return ret;
481 }
482
483 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
484 if (unlikely(i == 0)) {
a90bb9a5 485 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 486 n = HCLGE_RTN_DATA_NUM - 2;
487 } else {
a90bb9a5 488 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 489 n = HCLGE_RTN_DATA_NUM;
490 }
491 for (k = 0; k < n; k++) {
a90bb9a5 492 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 493 desc_data++;
494 }
495 }
496
497 return 0;
498}
499
500static int hclge_tqps_update_stats(struct hnae3_handle *handle)
501{
502 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
503 struct hclge_vport *vport = hclge_get_vport(handle);
504 struct hclge_dev *hdev = vport->back;
505 struct hnae3_queue *queue;
506 struct hclge_desc desc[1];
507 struct hclge_tqp *tqp;
508 int ret, i;
509
510 for (i = 0; i < kinfo->num_tqps; i++) {
511 queue = handle->kinfo.tqp[i];
512 tqp = container_of(queue, struct hclge_tqp, q);
513 /* command : HCLGE_OPC_QUERY_IGU_STAT */
514 hclge_cmd_setup_basic_desc(&desc[0],
515 HCLGE_OPC_QUERY_RX_STATUS,
516 true);
517
a90bb9a5 518 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 519 ret = hclge_cmd_send(&hdev->hw, desc, 1);
520 if (ret) {
521 dev_err(&hdev->pdev->dev,
522 "Query tqp stat fail, status = %d,queue = %d\n",
523 ret, i);
524 return ret;
525 }
526 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
a90bb9a5 527 le32_to_cpu(desc[0].data[4]);
46a3df9f
S		 528 }
529
530 for (i = 0; i < kinfo->num_tqps; i++) {
531 queue = handle->kinfo.tqp[i];
532 tqp = container_of(queue, struct hclge_tqp, q);
533 /* command : HCLGE_OPC_QUERY_IGU_STAT */
534 hclge_cmd_setup_basic_desc(&desc[0],
535 HCLGE_OPC_QUERY_TX_STATUS,
536 true);
537
a90bb9a5 538 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 539 ret = hclge_cmd_send(&hdev->hw, desc, 1);
540 if (ret) {
541 dev_err(&hdev->pdev->dev,
542 "Query tqp stat fail, status = %d,queue = %d\n",
543 ret, i);
544 return ret;
545 }
546 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
a90bb9a5 547 le32_to_cpu(desc[0].data[4]);
46a3df9f
S		 548 }
549
550 return 0;
551}
552
553static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
554{
555 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
556 struct hclge_tqp *tqp;
557 u64 *buff = data;
558 int i;
559
560 for (i = 0; i < kinfo->num_tqps; i++) {
561 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 562 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 563 }
564
565 for (i = 0; i < kinfo->num_tqps; i++) {
566 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 567 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 568 }
569
570 return buff;
571}
572
573static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
574{
575 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
576
577 return kinfo->num_tqps * (2);
578}
579
580static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
581{
582 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
583 u8 *buff = data;
584 int i = 0;
585
586 for (i = 0; i < kinfo->num_tqps; i++) {
587 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
588 struct hclge_tqp, q);
589 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
590 tqp->index);
591 buff = buff + ETH_GSTRING_LEN;
592 }
593
594 for (i = 0; i < kinfo->num_tqps; i++) {
595 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
596 struct hclge_tqp, q);
597 snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
598 tqp->index);
599 buff = buff + ETH_GSTRING_LEN;
600 }
601
602 return buff;
603}
604
605static u64 *hclge_comm_get_stats(void *comm_stats,
606 const struct hclge_comm_stats_str strs[],
607 int size, u64 *data)
608{
609 u64 *buf = data;
610 u32 i;
611
612 for (i = 0; i < size; i++)
613 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
614
615 return buf + size;
616}
617
618static u8 *hclge_comm_get_strings(u32 stringset,
619 const struct hclge_comm_stats_str strs[],
620 int size, u8 *data)
621{
622 char *buff = (char *)data;
623 u32 i;
624
625 if (stringset != ETH_SS_STATS)
626 return buff;
627
628 for (i = 0; i < size; i++) {
629 snprintf(buff, ETH_GSTRING_LEN,
630 strs[i].desc);
631 buff = buff + ETH_GSTRING_LEN;
632 }
633
634 return (u8 *)buff;
635}
636
637static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
638 struct net_device_stats *net_stats)
639{
640 net_stats->tx_dropped = 0;
641 net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
642 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
643 net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
644
645 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
646 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
647 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
648 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
649 net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
650 net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
651
652 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
653 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
654
655 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
656 net_stats->rx_length_errors =
657 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
658 net_stats->rx_length_errors +=
659 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
660 net_stats->rx_over_errors =
661 hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
662}
663
664static void hclge_update_stats_for_all(struct hclge_dev *hdev)
665{
666 struct hnae3_handle *handle;
667 int status;
668
669 handle = &hdev->vport[0].nic;
670 if (handle->client) {
671 status = hclge_tqps_update_stats(handle);
672 if (status) {
673 dev_err(&hdev->pdev->dev,
674 "Update TQPS stats fail, status = %d.\n",
675 status);
676 }
677 }
678
679 status = hclge_mac_update_stats(hdev);
680 if (status)
681 dev_err(&hdev->pdev->dev,
682 "Update MAC stats fail, status = %d.\n", status);
683
684 status = hclge_32_bit_update_stats(hdev);
685 if (status)
686 dev_err(&hdev->pdev->dev,
687 "Update 32 bit stats fail, status = %d.\n",
688 status);
689
690 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
691}
692
693static void hclge_update_stats(struct hnae3_handle *handle,
694 struct net_device_stats *net_stats)
695{
696 struct hclge_vport *vport = hclge_get_vport(handle);
697 struct hclge_dev *hdev = vport->back;
698 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
699 int status;
700
701 status = hclge_mac_update_stats(hdev);
702 if (status)
703 dev_err(&hdev->pdev->dev,
704 "Update MAC stats fail, status = %d.\n",
705 status);
706
707 status = hclge_32_bit_update_stats(hdev);
708 if (status)
709 dev_err(&hdev->pdev->dev,
710 "Update 32 bit stats fail, status = %d.\n",
711 status);
712
713 status = hclge_64_bit_update_stats(hdev);
714 if (status)
715 dev_err(&hdev->pdev->dev,
716 "Update 64 bit stats fail, status = %d.\n",
717 status);
718
719 status = hclge_tqps_update_stats(handle);
720 if (status)
721 dev_err(&hdev->pdev->dev,
722 "Update TQPS stats fail, status = %d.\n",
723 status);
724
725 hclge_update_netstat(hw_stats, net_stats);
726}
727
728static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
729{
730#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
731
732 struct hclge_vport *vport = hclge_get_vport(handle);
733 struct hclge_dev *hdev = vport->back;
734 int count = 0;
735
736 /* Loopback test support rules:
737 * mac: only GE mode support
738 * serdes: all mac mode will support include GE/XGE/LGE/CGE
739 * phy: only support when phy device exist on board
740 */
741 if (stringset == ETH_SS_TEST) {
742 /* clear loopback bit flags at first */
743 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
744 if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
745 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
746 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
747 count += 1;
748 handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
749 } else {
750 count = -EOPNOTSUPP;
751 }
752 } else if (stringset == ETH_SS_STATS) {
753 count = ARRAY_SIZE(g_mac_stats_string) +
754 ARRAY_SIZE(g_all_32bit_stats_string) +
755 ARRAY_SIZE(g_all_64bit_stats_string) +
756 hclge_tqps_get_sset_count(handle, stringset);
757 }
758
759 return count;
760}
761
762static void hclge_get_strings(struct hnae3_handle *handle,
763 u32 stringset,
764 u8 *data)
765{
766 u8 *p = (char *)data;
767 int size;
768
769 if (stringset == ETH_SS_STATS) {
770 size = ARRAY_SIZE(g_mac_stats_string);
771 p = hclge_comm_get_strings(stringset,
772 g_mac_stats_string,
773 size,
774 p);
775 size = ARRAY_SIZE(g_all_32bit_stats_string);
776 p = hclge_comm_get_strings(stringset,
777 g_all_32bit_stats_string,
778 size,
779 p);
780 size = ARRAY_SIZE(g_all_64bit_stats_string);
781 p = hclge_comm_get_strings(stringset,
782 g_all_64bit_stats_string,
783 size,
784 p);
785 p = hclge_tqps_get_strings(handle, p);
786 } else if (stringset == ETH_SS_TEST) {
787 if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
788 memcpy(p,
789 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
790 ETH_GSTRING_LEN);
791 p += ETH_GSTRING_LEN;
792 }
793 if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
794 memcpy(p,
795 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
796 ETH_GSTRING_LEN);
797 p += ETH_GSTRING_LEN;
798 }
799 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
800 memcpy(p,
801 hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
802 ETH_GSTRING_LEN);
803 p += ETH_GSTRING_LEN;
804 }
805 }
806}
807
808static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
809{
810 struct hclge_vport *vport = hclge_get_vport(handle);
811 struct hclge_dev *hdev = vport->back;
812 u64 *p;
813
814 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
815 g_mac_stats_string,
816 ARRAY_SIZE(g_mac_stats_string),
817 data);
818 p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
819 g_all_32bit_stats_string,
820 ARRAY_SIZE(g_all_32bit_stats_string),
821 p);
822 p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
823 g_all_64bit_stats_string,
824 ARRAY_SIZE(g_all_64bit_stats_string),
825 p);
826 p = hclge_tqps_get_stats(handle, p);
827}
828
829static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 830 struct hclge_func_status_cmd *status)
46a3df9f
S		 831{
832 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
833 return -EINVAL;
834
835 /* Set the pf to main pf */
836 if (status->pf_state & HCLGE_PF_STATE_MAIN)
837 hdev->flag |= HCLGE_FLAG_MAIN;
838 else
839 hdev->flag &= ~HCLGE_FLAG_MAIN;
840
46a3df9f
S		 841 return 0;
842}
843
844static int hclge_query_function_status(struct hclge_dev *hdev)
845{
d44f9b63 846 struct hclge_func_status_cmd *req;
46a3df9f
S		 847 struct hclge_desc desc;
848 int timeout = 0;
849 int ret;
850
851 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 852 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 853
854 do {
855 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
856 if (ret) {
857 dev_err(&hdev->pdev->dev,
858 "query function status failed %d.\n",
859 ret);
860
861 return ret;
862 }
863
864 /* Check pf reset is done */
865 if (req->pf_state)
866 break;
867 usleep_range(1000, 2000);
868 } while (timeout++ < 5);
869
870 ret = hclge_parse_func_status(hdev, req);
871
872 return ret;
873}
874
875static int hclge_query_pf_resource(struct hclge_dev *hdev)
876{
d44f9b63 877 struct hclge_pf_res_cmd *req;
46a3df9f
S		 878 struct hclge_desc desc;
879 int ret;
880
881 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
882 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
883 if (ret) {
884 dev_err(&hdev->pdev->dev,
885 "query pf resource failed %d.\n", ret);
886 return ret;
887 }
888
d44f9b63 889 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 890 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
891 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
892
e92a0843 893 if (hnae3_dev_roce_supported(hdev)) {
887c3820 894 hdev->num_roce_msi =
46a3df9f
S		 895 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
896 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
897
898 /* PF should have NIC vectors and Roce vectors,
899 * NIC vectors are queued before Roce vectors.
900 */
887c3820 901 hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET;
46a3df9f
S		 902 } else {
903 hdev->num_msi =
904 hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
905 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
906 }
907
908 return 0;
909}
910
911static int hclge_parse_speed(int speed_cmd, int *speed)
912{
913 switch (speed_cmd) {
914 case 6:
915 *speed = HCLGE_MAC_SPEED_10M;
916 break;
917 case 7:
918 *speed = HCLGE_MAC_SPEED_100M;
919 break;
920 case 0:
921 *speed = HCLGE_MAC_SPEED_1G;
922 break;
923 case 1:
924 *speed = HCLGE_MAC_SPEED_10G;
925 break;
926 case 2:
927 *speed = HCLGE_MAC_SPEED_25G;
928 break;
929 case 3:
930 *speed = HCLGE_MAC_SPEED_40G;
931 break;
932 case 4:
933 *speed = HCLGE_MAC_SPEED_50G;
934 break;
935 case 5:
936 *speed = HCLGE_MAC_SPEED_100G;
937 break;
938 default:
939 return -EINVAL;
940 }
941
942 return 0;
943}
944
945static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
946{
d44f9b63 947 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 948 u64 mac_addr_tmp_high;
949 u64 mac_addr_tmp;
950 int i;
951
d44f9b63 952 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 953
954 /* get the configuration */
955 cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
956 HCLGE_CFG_VMDQ_M,
957 HCLGE_CFG_VMDQ_S);
958 cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
959 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
960 cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
961 HCLGE_CFG_TQP_DESC_N_M,
962 HCLGE_CFG_TQP_DESC_N_S);
963
964 cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
965 HCLGE_CFG_PHY_ADDR_M,
966 HCLGE_CFG_PHY_ADDR_S);
967 cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
968 HCLGE_CFG_MEDIA_TP_M,
969 HCLGE_CFG_MEDIA_TP_S);
970 cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
971 HCLGE_CFG_RX_BUF_LEN_M,
972 HCLGE_CFG_RX_BUF_LEN_S);
973 /* get mac_address */
974 mac_addr_tmp = __le32_to_cpu(req->param[2]);
975 mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
976 HCLGE_CFG_MAC_ADDR_H_M,
977 HCLGE_CFG_MAC_ADDR_H_S);
978
979 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
980
981 cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
982 HCLGE_CFG_DEFAULT_SPEED_M,
983 HCLGE_CFG_DEFAULT_SPEED_S);
984 for (i = 0; i < ETH_ALEN; i++)
985 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
986
d44f9b63 987 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f
S		 988 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
989}
990
991/* hclge_get_cfg: query the static parameter from flash
992 * @hdev: pointer to struct hclge_dev
993 * @hcfg: the config structure to be getted
994 */
995static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
996{
997 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 998 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 999 int i, ret;
1000
1001 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 1002 u32 offset = 0;
1003
d44f9b63 1004 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 1005 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
1006 true);
a90bb9a5 1007 hnae_set_field(offset, HCLGE_CFG_OFFSET_M,
46a3df9f
S		 1008 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
1009 /* Len should be united by 4 bytes when send to hardware */
a90bb9a5 1010 hnae_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
46a3df9f 1011 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 1012 req->offset = cpu_to_le32(offset);
46a3df9f
S		 1013 }
1014
1015 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
1016 if (ret) {
1017 dev_err(&hdev->pdev->dev,
1018 "get config failed %d.\n", ret);
1019 return ret;
1020 }
1021
1022 hclge_parse_cfg(hcfg, desc);
1023 return 0;
1024}
1025
1026static int hclge_get_cap(struct hclge_dev *hdev)
1027{
1028 int ret;
1029
1030 ret = hclge_query_function_status(hdev);
1031 if (ret) {
1032 dev_err(&hdev->pdev->dev,
1033 "query function status error %d.\n", ret);
1034 return ret;
1035 }
1036
1037 /* get pf resource */
1038 ret = hclge_query_pf_resource(hdev);
1039 if (ret) {
1040 dev_err(&hdev->pdev->dev,
1041 "query pf resource error %d.\n", ret);
1042 return ret;
1043 }
1044
1045 return 0;
1046}
1047
1048static int hclge_configure(struct hclge_dev *hdev)
1049{
1050 struct hclge_cfg cfg;
1051 int ret, i;
1052
1053 ret = hclge_get_cfg(hdev, &cfg);
1054 if (ret) {
1055 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
1056 return ret;
1057 }
1058
1059 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
1060 hdev->base_tqp_pid = 0;
1061 hdev->rss_size_max = 1;
1062 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 1063 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 1064 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 1065 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 1066 hdev->num_desc = cfg.tqp_desc_num;
1067 hdev->tm_info.num_pg = 1;
cacde272 1068 hdev->tc_max = cfg.tc_num;
46a3df9f
S		 1069 hdev->tm_info.hw_pfc_map = 0;
1070
1071 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
1072 if (ret) {
1073 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
1074 return ret;
1075 }
1076
cacde272
YL		 1077 if ((hdev->tc_max > HNAE3_MAX_TC) ||
1078 (hdev->tc_max < 1)) {
46a3df9f 1079 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 1080 hdev->tc_max);
1081 hdev->tc_max = 1;
46a3df9f
S		 1082 }
1083
cacde272
YL		 1084 /* Dev does not support DCB */
1085 if (!hnae3_dev_dcb_supported(hdev)) {
1086 hdev->tc_max = 1;
1087 hdev->pfc_max = 0;
1088 } else {
1089 hdev->pfc_max = hdev->tc_max;
1090 }
1091
1092 hdev->tm_info.num_tc = hdev->tc_max;
1093
46a3df9f 1094 /* Currently not support uncontiuous tc */
cacde272 1095 for (i = 0; i < hdev->tm_info.num_tc; i++)
46a3df9f
S		 1096 hnae_set_bit(hdev->hw_tc_map, i, 1);
1097
1098 if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
1099 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
1100 else
1101 hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
1102
1103 return ret;
1104}
1105
1106static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
1107 int tso_mss_max)
1108{
d44f9b63 1109 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 1110 struct hclge_desc desc;
a90bb9a5 1111 u16 tso_mss;
46a3df9f
S		 1112
1113 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
1114
d44f9b63 1115 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 1116
1117 tso_mss = 0;
1118 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1119 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 1120 req->tso_mss_min = cpu_to_le16(tso_mss);
1121
1122 tso_mss = 0;
1123 hnae_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
46a3df9f 1124 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 1125 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 1126
1127 return hclge_cmd_send(&hdev->hw, &desc, 1);
1128}
1129
1130static int hclge_alloc_tqps(struct hclge_dev *hdev)
1131{
1132 struct hclge_tqp *tqp;
1133 int i;
1134
1135 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
1136 sizeof(struct hclge_tqp), GFP_KERNEL);
1137 if (!hdev->htqp)
1138 return -ENOMEM;
1139
1140 tqp = hdev->htqp;
1141
1142 for (i = 0; i < hdev->num_tqps; i++) {
1143 tqp->dev = &hdev->pdev->dev;
1144 tqp->index = i;
1145
1146 tqp->q.ae_algo = &ae_algo;
1147 tqp->q.buf_size = hdev->rx_buf_len;
1148 tqp->q.desc_num = hdev->num_desc;
1149 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
1150 i * HCLGE_TQP_REG_SIZE;
1151
1152 tqp++;
1153 }
1154
1155 return 0;
1156}
1157
1158static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
1159 u16 tqp_pid, u16 tqp_vid, bool is_pf)
1160{
d44f9b63 1161 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 1162 struct hclge_desc desc;
1163 int ret;
1164
1165 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
1166
d44f9b63 1167 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 1168 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 1169 req->tqp_vf = func_id;
46a3df9f
S		 1170 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1171 1 << HCLGE_TQP_MAP_EN_B;
1172 req->tqp_vid = cpu_to_le16(tqp_vid);
1173
1174 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1175 if (ret) {
1176 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
1177 ret);
1178 return ret;
1179 }
1180
1181 return 0;
1182}
1183
1184static int hclge_assign_tqp(struct hclge_vport *vport,
1185 struct hnae3_queue **tqp, u16 num_tqps)
1186{
1187 struct hclge_dev *hdev = vport->back;
7df7dad6 1188 int i, alloced;
46a3df9f
S		 1189
1190 for (i = 0, alloced = 0; i < hdev->num_tqps &&
1191 alloced < num_tqps; i++) {
1192 if (!hdev->htqp[i].alloced) {
1193 hdev->htqp[i].q.handle = &vport->nic;
1194 hdev->htqp[i].q.tqp_index = alloced;
1195 tqp[alloced] = &hdev->htqp[i].q;
1196 hdev->htqp[i].alloced = true;
46a3df9f
S		 1197 alloced++;
1198 }
1199 }
1200 vport->alloc_tqps = num_tqps;
1201
1202 return 0;
1203}
1204
1205static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
1206{
1207 struct hnae3_handle *nic = &vport->nic;
1208 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1209 struct hclge_dev *hdev = vport->back;
1210 int i, ret;
1211
1212 kinfo->num_desc = hdev->num_desc;
1213 kinfo->rx_buf_len = hdev->rx_buf_len;
1214 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1215 kinfo->rss_size
1216 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1217 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1218
1219 for (i = 0; i < HNAE3_MAX_TC; i++) {
1220 if (hdev->hw_tc_map & BIT(i)) {
1221 kinfo->tc_info[i].enable = true;
1222 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1223 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1224 kinfo->tc_info[i].tc = i;
1225 } else {
1226 /* Set to default queue if TC is disable */
1227 kinfo->tc_info[i].enable = false;
1228 kinfo->tc_info[i].tqp_offset = 0;
1229 kinfo->tc_info[i].tqp_count = 1;
1230 kinfo->tc_info[i].tc = 0;
1231 }
1232 }
1233
1234 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1235 sizeof(struct hnae3_queue *), GFP_KERNEL);
1236 if (!kinfo->tqp)
1237 return -ENOMEM;
1238
1239 ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
1240 if (ret) {
1241 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
1242 return -EINVAL;
1243 }
1244
1245 return 0;
1246}
1247
7df7dad6
L		 1248static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1249 struct hclge_vport *vport)
1250{
1251 struct hnae3_handle *nic = &vport->nic;
1252 struct hnae3_knic_private_info *kinfo;
1253 u16 i;
1254
1255 kinfo = &nic->kinfo;
1256 for (i = 0; i < kinfo->num_tqps; i++) {
1257 struct hclge_tqp *q =
1258 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1259 bool is_pf;
1260 int ret;
1261
1262 is_pf = !(vport->vport_id);
1263 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1264 i, is_pf);
1265 if (ret)
1266 return ret;
1267 }
1268
1269 return 0;
1270}
1271
1272static int hclge_map_tqp(struct hclge_dev *hdev)
1273{
1274 struct hclge_vport *vport = hdev->vport;
1275 u16 i, num_vport;
1276
1277 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1278 for (i = 0; i < num_vport; i++) {
1279 int ret;
1280
1281 ret = hclge_map_tqp_to_vport(hdev, vport);
1282 if (ret)
1283 return ret;
1284
1285 vport++;
1286 }
1287
1288 return 0;
1289}
1290
46a3df9f
S		 1291static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1292{
1293 /* this would be initialized later */
1294}
1295
1296static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1297{
1298 struct hnae3_handle *nic = &vport->nic;
1299 struct hclge_dev *hdev = vport->back;
1300 int ret;
1301
1302 nic->pdev = hdev->pdev;
1303 nic->ae_algo = &ae_algo;
1304 nic->numa_node_mask = hdev->numa_node_mask;
1305
1306 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
1307 ret = hclge_knic_setup(vport, num_tqps);
1308 if (ret) {
1309 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1310 ret);
1311 return ret;
1312 }
1313 } else {
1314 hclge_unic_setup(vport, num_tqps);
1315 }
1316
1317 return 0;
1318}
1319
1320static int hclge_alloc_vport(struct hclge_dev *hdev)
1321{
1322 struct pci_dev *pdev = hdev->pdev;
1323 struct hclge_vport *vport;
1324 u32 tqp_main_vport;
1325 u32 tqp_per_vport;
1326 int num_vport, i;
1327 int ret;
1328
1329 /* We need to alloc a vport for main NIC of PF */
1330 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1331
1332 if (hdev->num_tqps < num_vport)
1333 num_vport = hdev->num_tqps;
1334
1335 /* Alloc the same number of TQPs for every vport */
1336 tqp_per_vport = hdev->num_tqps / num_vport;
1337 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1338
1339 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1340 GFP_KERNEL);
1341 if (!vport)
1342 return -ENOMEM;
1343
1344 hdev->vport = vport;
1345 hdev->num_alloc_vport = num_vport;
1346
1347#ifdef CONFIG_PCI_IOV
1348 /* Enable SRIOV */
1349 if (hdev->num_req_vfs) {
1350 dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
1351 hdev->num_req_vfs);
1352 ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
1353 if (ret) {
1354 hdev->num_alloc_vfs = 0;
1355 dev_err(&pdev->dev, "SRIOV enable failed %d\n",
1356 ret);
1357 return ret;
1358 }
1359 }
1360 hdev->num_alloc_vfs = hdev->num_req_vfs;
1361#endif
1362
1363 for (i = 0; i < num_vport; i++) {
1364 vport->back = hdev;
1365 vport->vport_id = i;
1366
1367 if (i == 0)
1368 ret = hclge_vport_setup(vport, tqp_main_vport);
1369 else
1370 ret = hclge_vport_setup(vport, tqp_per_vport);
1371 if (ret) {
1372 dev_err(&pdev->dev,
1373 "vport setup failed for vport %d, %d\n",
1374 i, ret);
1375 return ret;
1376 }
1377
1378 vport++;
1379 }
1380
1381 return 0;
1382}
1383
acf61ecd
YL		 1384static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1385 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1386{
1387/* TX buffer size is unit by 128 byte */
1388#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1389#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1390 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1391 struct hclge_desc desc;
1392 int ret;
1393 u8 i;
1394
d44f9b63 1395 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1396
1397 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1398 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1399 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1400
46a3df9f
S		 1401 req->tx_pkt_buff[i] =
1402 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1403 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1404 }
46a3df9f
S		 1405
1406 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1407 if (ret) {
1408 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1409 ret);
1410 return ret;
1411 }
1412
1413 return 0;
1414}
1415
acf61ecd
YL		 1416static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1417 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1418{
acf61ecd 1419 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f
S		 1420
1421 if (ret) {
1422 dev_err(&hdev->pdev->dev,
1423 "tx buffer alloc failed %d\n", ret);
1424 return ret;
1425 }
1426
1427 return 0;
1428}
1429
1430static int hclge_get_tc_num(struct hclge_dev *hdev)
1431{
1432 int i, cnt = 0;
1433
1434 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1435 if (hdev->hw_tc_map & BIT(i))
1436 cnt++;
1437 return cnt;
1438}
1439
1440static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1441{
1442 int i, cnt = 0;
1443
1444 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1445 if (hdev->hw_tc_map & BIT(i) &&
1446 hdev->tm_info.hw_pfc_map & BIT(i))
1447 cnt++;
1448 return cnt;
1449}
1450
1451/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1452static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1453 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1454{
1455 struct hclge_priv_buf *priv;
1456 int i, cnt = 0;
1457
1458 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1459 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1460 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1461 priv->enable)
1462 cnt++;
1463 }
1464
1465 return cnt;
1466}
1467
1468/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1469static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1470 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1471{
1472 struct hclge_priv_buf *priv;
1473 int i, cnt = 0;
1474
1475 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1476 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1477 if (hdev->hw_tc_map & BIT(i) &&
1478 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1479 priv->enable)
1480 cnt++;
1481 }
1482
1483 return cnt;
1484}
1485
acf61ecd 1486static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1487{
1488 struct hclge_priv_buf *priv;
1489 u32 rx_priv = 0;
1490 int i;
1491
1492 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1493 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1494 if (priv->enable)
1495 rx_priv += priv->buf_size;
1496 }
1497 return rx_priv;
1498}
1499
acf61ecd 1500static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1501{
1502 u32 i, total_tx_size = 0;
1503
1504 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1505 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1506
1507 return total_tx_size;
1508}
1509
acf61ecd
YL		 1510static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1511 struct hclge_pkt_buf_alloc *buf_alloc,
1512 u32 rx_all)
46a3df9f
S		 1513{
1514 u32 shared_buf_min, shared_buf_tc, shared_std;
1515 int tc_num, pfc_enable_num;
1516 u32 shared_buf;
1517 u32 rx_priv;
1518 int i;
1519
1520 tc_num = hclge_get_tc_num(hdev);
1521 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1522
d221df4e
YL		 1523 if (hnae3_dev_dcb_supported(hdev))
1524 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1525 else
1526 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1527
46a3df9f
S		 1528 shared_buf_tc = pfc_enable_num * hdev->mps +
1529 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1530 hdev->mps;
1531 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1532
acf61ecd 1533 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1534 if (rx_all <= rx_priv + shared_std)
1535 return false;
1536
1537 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1538 buf_alloc->s_buf.buf_size = shared_buf;
1539 buf_alloc->s_buf.self.high = shared_buf;
1540 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1541
1542 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1543 if ((hdev->hw_tc_map & BIT(i)) &&
1544 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1545 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1546 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1547 } else {
acf61ecd
YL		 1548 buf_alloc->s_buf.tc_thrd[i].low = 0;
1549 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1550 }
1551 }
1552
1553 return true;
1554}
1555
acf61ecd
YL		 1556static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1557 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1558{
1559 u32 i, total_size;
1560
1561 total_size = hdev->pkt_buf_size;
1562
1563 /* alloc tx buffer for all enabled tc */
1564 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1565 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1566
1567 if (total_size < HCLGE_DEFAULT_TX_BUF)
1568 return -ENOMEM;
1569
1570 if (hdev->hw_tc_map & BIT(i))
1571 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1572 else
1573 priv->tx_buf_size = 0;
1574
1575 total_size -= priv->tx_buf_size;
1576 }
1577
1578 return 0;
1579}
1580
46a3df9f
S		 1581/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1582 * @hdev: pointer to struct hclge_dev
acf61ecd 1583 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1584 * @return: 0: calculate sucessful, negative: fail
1585 */
1db9b1bf
YL		 1586static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1587 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1588{
9ffe79a9 1589 u32 rx_all = hdev->pkt_buf_size;
46a3df9f
S		 1590 int no_pfc_priv_num, pfc_priv_num;
1591 struct hclge_priv_buf *priv;
1592 int i;
1593
acf61ecd 1594 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1595
d602a525
YL		 1596 /* When DCB is not supported, rx private
1597 * buffer is not allocated.
1598 */
1599 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1600 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1601 return -ENOMEM;
1602
1603 return 0;
1604 }
1605
46a3df9f
S		 1606 /* step 1, try to alloc private buffer for all enabled tc */
1607 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1608 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1609 if (hdev->hw_tc_map & BIT(i)) {
1610 priv->enable = 1;
1611 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1612 priv->wl.low = hdev->mps;
1613 priv->wl.high = priv->wl.low + hdev->mps;
1614 priv->buf_size = priv->wl.high +
1615 HCLGE_DEFAULT_DV;
1616 } else {
1617 priv->wl.low = 0;
1618 priv->wl.high = 2 * hdev->mps;
1619 priv->buf_size = priv->wl.high;
1620 }
bb1fe9ea
YL		 1621 } else {
1622 priv->enable = 0;
1623 priv->wl.low = 0;
1624 priv->wl.high = 0;
1625 priv->buf_size = 0;
46a3df9f
S		 1626 }
1627 }
1628
acf61ecd 1629 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1630 return 0;
1631
1632 /* step 2, try to decrease the buffer size of
1633 * no pfc TC's private buffer
1634 */
1635 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1636 priv = &buf_alloc->priv_buf[i];
46a3df9f 1637
bb1fe9ea
YL		 1638 priv->enable = 0;
1639 priv->wl.low = 0;
1640 priv->wl.high = 0;
1641 priv->buf_size = 0;
1642
1643 if (!(hdev->hw_tc_map & BIT(i)))
1644 continue;
1645
1646 priv->enable = 1;
46a3df9f
S		 1647
1648 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1649 priv->wl.low = 128;
1650 priv->wl.high = priv->wl.low + hdev->mps;
1651 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1652 } else {
1653 priv->wl.low = 0;
1654 priv->wl.high = hdev->mps;
1655 priv->buf_size = priv->wl.high;
1656 }
1657 }
1658
acf61ecd 1659 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1660 return 0;
1661
1662 /* step 3, try to reduce the number of pfc disabled TCs,
1663 * which have private buffer
1664 */
1665 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1666 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1667
1668 /* let the last to be cleared first */
1669 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1670 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1671
1672 if (hdev->hw_tc_map & BIT(i) &&
1673 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1674 /* Clear the no pfc TC private buffer */
1675 priv->wl.low = 0;
1676 priv->wl.high = 0;
1677 priv->buf_size = 0;
1678 priv->enable = 0;
1679 no_pfc_priv_num--;
1680 }
1681
acf61ecd 1682 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1683 no_pfc_priv_num == 0)
1684 break;
1685 }
1686
acf61ecd 1687 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1688 return 0;
1689
1690 /* step 4, try to reduce the number of pfc enabled TCs
1691 * which have private buffer.
1692 */
acf61ecd 1693 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1694
1695 /* let the last to be cleared first */
1696 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1697 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1698
1699 if (hdev->hw_tc_map & BIT(i) &&
1700 hdev->tm_info.hw_pfc_map & BIT(i)) {
1701 /* Reduce the number of pfc TC with private buffer */
1702 priv->wl.low = 0;
1703 priv->enable = 0;
1704 priv->wl.high = 0;
1705 priv->buf_size = 0;
1706 pfc_priv_num--;
1707 }
1708
acf61ecd 1709 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1710 pfc_priv_num == 0)
1711 break;
1712 }
acf61ecd 1713 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1714 return 0;
1715
1716 return -ENOMEM;
1717}
1718
acf61ecd
YL		 1719static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1720 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1721{
d44f9b63 1722 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1723 struct hclge_desc desc;
1724 int ret;
1725 int i;
1726
1727 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1728 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1729
1730 /* Alloc private buffer TCs */
1731 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1732 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1733
1734 req->buf_num[i] =
1735 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1736 req->buf_num[i] |=
5bca3b94 1737 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1738 }
1739
b8c8bf47 1740 req->shared_buf =
acf61ecd 1741 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1742 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1743
46a3df9f
S		 1744 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1745 if (ret) {
1746 dev_err(&hdev->pdev->dev,
1747 "rx private buffer alloc cmd failed %d\n", ret);
1748 return ret;
1749 }
1750
1751 return 0;
1752}
1753
1754#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
1755
acf61ecd
YL		 1756static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1757 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1758{
1759 struct hclge_rx_priv_wl_buf *req;
1760 struct hclge_priv_buf *priv;
1761 struct hclge_desc desc[2];
1762 int i, j;
1763 int ret;
1764
1765 for (i = 0; i < 2; i++) {
1766 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1767 false);
1768 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1769
1770 /* The first descriptor set the NEXT bit to 1 */
1771 if (i == 0)
1772 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1773 else
1774 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1775
1776 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1777 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1778
1779 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1780 req->tc_wl[j].high =
1781 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1782 req->tc_wl[j].high |=
1783 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
1784 HCLGE_RX_PRIV_EN_B);
1785 req->tc_wl[j].low =
1786 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1787 req->tc_wl[j].low |=
1788 cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
1789 HCLGE_RX_PRIV_EN_B);
1790 }
1791 }
1792
1793 /* Send 2 descriptor at one time */
1794 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1795 if (ret) {
1796 dev_err(&hdev->pdev->dev,
1797 "rx private waterline config cmd failed %d\n",
1798 ret);
1799 return ret;
1800 }
1801 return 0;
1802}
1803
acf61ecd
YL		 1804static int hclge_common_thrd_config(struct hclge_dev *hdev,
1805 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1806{
acf61ecd 1807 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1808 struct hclge_rx_com_thrd *req;
1809 struct hclge_desc desc[2];
1810 struct hclge_tc_thrd *tc;
1811 int i, j;
1812 int ret;
1813
1814 for (i = 0; i < 2; i++) {
1815 hclge_cmd_setup_basic_desc(&desc[i],
1816 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1817 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1818
1819 /* The first descriptor set the NEXT bit to 1 */
1820 if (i == 0)
1821 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1822 else
1823 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1824
1825 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1826 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1827
1828 req->com_thrd[j].high =
1829 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1830 req->com_thrd[j].high |=
1831 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
1832 HCLGE_RX_PRIV_EN_B);
1833 req->com_thrd[j].low =
1834 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1835 req->com_thrd[j].low |=
1836 cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
1837 HCLGE_RX_PRIV_EN_B);
1838 }
1839 }
1840
1841 /* Send 2 descriptors at one time */
1842 ret = hclge_cmd_send(&hdev->hw, desc, 2);
1843 if (ret) {
1844 dev_err(&hdev->pdev->dev,
1845 "common threshold config cmd failed %d\n", ret);
1846 return ret;
1847 }
1848 return 0;
1849}
1850
acf61ecd
YL		 1851static int hclge_common_wl_config(struct hclge_dev *hdev,
1852 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1853{
acf61ecd 1854 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1855 struct hclge_rx_com_wl *req;
1856 struct hclge_desc desc;
1857 int ret;
1858
1859 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1860
1861 req = (struct hclge_rx_com_wl *)desc.data;
1862 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
1863 req->com_wl.high |=
1864 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
1865 HCLGE_RX_PRIV_EN_B);
1866
1867 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
1868 req->com_wl.low |=
1869 cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
1870 HCLGE_RX_PRIV_EN_B);
1871
1872 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1873 if (ret) {
1874 dev_err(&hdev->pdev->dev,
1875 "common waterline config cmd failed %d\n", ret);
1876 return ret;
1877 }
1878
1879 return 0;
1880}
1881
1882int hclge_buffer_alloc(struct hclge_dev *hdev)
1883{
acf61ecd 1884 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1885 int ret;
1886
acf61ecd
YL		 1887 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1888 if (!pkt_buf)
46a3df9f
S		 1889 return -ENOMEM;
1890
acf61ecd 1891 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1892 if (ret) {
1893 dev_err(&hdev->pdev->dev,
1894 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1895 goto out;
9ffe79a9
YL		 1896 }
1897
acf61ecd 1898 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1899 if (ret) {
1900 dev_err(&hdev->pdev->dev,
1901 "could not alloc tx buffers %d\n", ret);
acf61ecd 1902 goto out;
46a3df9f
S		 1903 }
1904
acf61ecd 1905 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1906 if (ret) {
1907 dev_err(&hdev->pdev->dev,
1908 "could not calc rx priv buffer size for all TCs %d\n",
1909 ret);
acf61ecd 1910 goto out;
46a3df9f
S		 1911 }
1912
acf61ecd 1913 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1914 if (ret) {
1915 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1916 ret);
acf61ecd 1917 goto out;
46a3df9f
S		 1918 }
1919
2daf4a65 1920 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1921 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1922 if (ret) {
1923 dev_err(&hdev->pdev->dev,
1924 "could not configure rx private waterline %d\n",
1925 ret);
acf61ecd 1926 goto out;
2daf4a65 1927 }
46a3df9f 1928
acf61ecd 1929 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1930 if (ret) {
1931 dev_err(&hdev->pdev->dev,
1932 "could not configure common threshold %d\n",
1933 ret);
acf61ecd 1934 goto out;
2daf4a65 1935 }
46a3df9f
S		 1936 }
1937
acf61ecd
YL		 1938 ret = hclge_common_wl_config(hdev, pkt_buf);
1939 if (ret)
46a3df9f
S		 1940 dev_err(&hdev->pdev->dev,
1941 "could not configure common waterline %d\n", ret);
46a3df9f 1942
acf61ecd
YL		 1943out:
1944 kfree(pkt_buf);
1945 return ret;
46a3df9f
S		 1946}
1947
1948static int hclge_init_roce_base_info(struct hclge_vport *vport)
1949{
1950 struct hnae3_handle *roce = &vport->roce;
1951 struct hnae3_handle *nic = &vport->nic;
1952
887c3820 1953 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 1954
1955 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1956 vport->back->num_msi_left == 0)
1957 return -EINVAL;
1958
1959 roce->rinfo.base_vector = vport->back->roce_base_vector;
1960
1961 roce->rinfo.netdev = nic->kinfo.netdev;
1962 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1963
1964 roce->pdev = nic->pdev;
1965 roce->ae_algo = nic->ae_algo;
1966 roce->numa_node_mask = nic->numa_node_mask;
1967
1968 return 0;
1969}
1970
887c3820 1971static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 1972{
1973 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 1974 int vectors;
1975 int i;
46a3df9f 1976
887c3820
SM		 1977 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1978 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1979 if (vectors < 0) {
1980 dev_err(&pdev->dev,
1981 "failed(%d) to allocate MSI/MSI-X vectors\n",
1982 vectors);
1983 return vectors;
46a3df9f 1984 }
887c3820
SM		 1985 if (vectors < hdev->num_msi)
1986 dev_warn(&hdev->pdev->dev,
1987 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1988 hdev->num_msi, vectors);
46a3df9f 1989
887c3820
SM		 1990 hdev->num_msi = vectors;
1991 hdev->num_msi_left = vectors;
1992 hdev->base_msi_vector = pdev->irq;
46a3df9f
S		 1993 hdev->roce_base_vector = hdev->base_msi_vector +
1994 HCLGE_ROCE_VECTOR_OFFSET;
1995
46a3df9f
S		 1996 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1997 sizeof(u16), GFP_KERNEL);
887c3820
SM		 1998 if (!hdev->vector_status) {
1999 pci_free_irq_vectors(pdev);
46a3df9f 2000 return -ENOMEM;
887c3820 2001 }
46a3df9f
S		 2002
2003 for (i = 0; i < hdev->num_msi; i++)
2004 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
2005
887c3820
SM		 2006 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
2007 sizeof(int), GFP_KERNEL);
2008 if (!hdev->vector_irq) {
2009 pci_free_irq_vectors(pdev);
2010 return -ENOMEM;
46a3df9f 2011 }
46a3df9f
S		 2012
2013 return 0;
2014}
2015
2016static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
2017{
2018 struct hclge_mac *mac = &hdev->hw.mac;
2019
2020 if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
2021 mac->duplex = (u8)duplex;
2022 else
2023 mac->duplex = HCLGE_MAC_FULL;
2024
2025 mac->speed = speed;
2026}
2027
2028int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
2029{
d44f9b63 2030 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 2031 struct hclge_desc desc;
2032 int ret;
2033
d44f9b63 2034 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 2035
2036 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
2037
2038 hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
2039
2040 switch (speed) {
2041 case HCLGE_MAC_SPEED_10M:
2042 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2043 HCLGE_CFG_SPEED_S, 6);
2044 break;
2045 case HCLGE_MAC_SPEED_100M:
2046 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2047 HCLGE_CFG_SPEED_S, 7);
2048 break;
2049 case HCLGE_MAC_SPEED_1G:
2050 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2051 HCLGE_CFG_SPEED_S, 0);
2052 break;
2053 case HCLGE_MAC_SPEED_10G:
2054 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2055 HCLGE_CFG_SPEED_S, 1);
2056 break;
2057 case HCLGE_MAC_SPEED_25G:
2058 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2059 HCLGE_CFG_SPEED_S, 2);
2060 break;
2061 case HCLGE_MAC_SPEED_40G:
2062 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2063 HCLGE_CFG_SPEED_S, 3);
2064 break;
2065 case HCLGE_MAC_SPEED_50G:
2066 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2067 HCLGE_CFG_SPEED_S, 4);
2068 break;
2069 case HCLGE_MAC_SPEED_100G:
2070 hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
2071 HCLGE_CFG_SPEED_S, 5);
2072 break;
2073 default:
d7629e74 2074 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 2075 return -EINVAL;
2076 }
2077
2078 hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
2079 1);
2080
2081 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2082 if (ret) {
2083 dev_err(&hdev->pdev->dev,
2084 "mac speed/duplex config cmd failed %d.\n", ret);
2085 return ret;
2086 }
2087
2088 hclge_check_speed_dup(hdev, duplex, speed);
2089
2090 return 0;
2091}
2092
2093static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
2094 u8 duplex)
2095{
2096 struct hclge_vport *vport = hclge_get_vport(handle);
2097 struct hclge_dev *hdev = vport->back;
2098
2099 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2100}
2101
2102static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
2103 u8 *duplex)
2104{
d44f9b63 2105 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2106 struct hclge_desc desc;
2107 int speed_tmp;
2108 int ret;
2109
d44f9b63 2110 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2111
2112 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2113 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2114 if (ret) {
2115 dev_err(&hdev->pdev->dev,
2116 "mac speed/autoneg/duplex query cmd failed %d\n",
2117 ret);
2118 return ret;
2119 }
2120
2121 *duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
2122 speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
2123 HCLGE_QUERY_SPEED_S);
2124
2125 ret = hclge_parse_speed(speed_tmp, speed);
2126 if (ret) {
2127 dev_err(&hdev->pdev->dev,
2128 "could not parse speed(=%d), %d\n", speed_tmp, ret);
2129 return -EIO;
2130 }
2131
2132 return 0;
2133}
2134
2135static int hclge_query_autoneg_result(struct hclge_dev *hdev)
2136{
2137 struct hclge_mac *mac = &hdev->hw.mac;
d44f9b63 2138 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 2139 struct hclge_desc desc;
2140 int ret;
2141
d44f9b63 2142 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 2143
2144 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
2145 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2146 if (ret) {
2147 dev_err(&hdev->pdev->dev,
2148 "autoneg result query cmd failed %d.\n", ret);
2149 return ret;
2150 }
2151
2152 mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
2153
2154 return 0;
2155}
2156
2157static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
2158{
d44f9b63 2159 struct hclge_config_auto_neg_cmd *req;
46a3df9f 2160 struct hclge_desc desc;
a90bb9a5 2161 u32 flag = 0;
46a3df9f
S		 2162 int ret;
2163
2164 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
2165
d44f9b63 2166 req = (struct hclge_config_auto_neg_cmd *)desc.data;
a90bb9a5
YL		 2167 hnae_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
2168 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 2169
2170 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2171 if (ret) {
2172 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
2173 ret);
2174 return ret;
2175 }
2176
2177 return 0;
2178}
2179
2180static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
2181{
2182 struct hclge_vport *vport = hclge_get_vport(handle);
2183 struct hclge_dev *hdev = vport->back;
2184
2185 return hclge_set_autoneg_en(hdev, enable);
2186}
2187
2188static int hclge_get_autoneg(struct hnae3_handle *handle)
2189{
2190 struct hclge_vport *vport = hclge_get_vport(handle);
2191 struct hclge_dev *hdev = vport->back;
2192
2193 hclge_query_autoneg_result(hdev);
2194
2195 return hdev->hw.mac.autoneg;
2196}
2197
2198static int hclge_mac_init(struct hclge_dev *hdev)
2199{
2200 struct hclge_mac *mac = &hdev->hw.mac;
2201 int ret;
2202
2203 ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
2204 if (ret) {
2205 dev_err(&hdev->pdev->dev,
2206 "Config mac speed dup fail ret=%d\n", ret);
2207 return ret;
2208 }
2209
2210 mac->link = 0;
2211
46a3df9f
S		 2212 /* Initialize the MTA table work mode */
2213 hdev->accept_mta_mc = true;
2214 hdev->enable_mta = true;
2215 hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
2216
2217 ret = hclge_set_mta_filter_mode(hdev,
2218 hdev->mta_mac_sel_type,
2219 hdev->enable_mta);
2220 if (ret) {
2221 dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
2222 ret);
2223 return ret;
2224 }
2225
2226 return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
2227}
2228
2229static void hclge_task_schedule(struct hclge_dev *hdev)
2230{
2231 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
2232 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
2233 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
2234 (void)schedule_work(&hdev->service_task);
2235}
2236
2237static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2238{
d44f9b63 2239 struct hclge_link_status_cmd *req;
46a3df9f
S		 2240 struct hclge_desc desc;
2241 int link_status;
2242 int ret;
2243
2244 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2245 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2246 if (ret) {
2247 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2248 ret);
2249 return ret;
2250 }
2251
d44f9b63 2252 req = (struct hclge_link_status_cmd *)desc.data;
46a3df9f
S		 2253 link_status = req->status & HCLGE_LINK_STATUS;
2254
2255 return !!link_status;
2256}
2257
2258static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2259{
2260 int mac_state;
2261 int link_stat;
2262
2263 mac_state = hclge_get_mac_link_status(hdev);
2264
2265 if (hdev->hw.mac.phydev) {
2266 if (!genphy_read_status(hdev->hw.mac.phydev))
2267 link_stat = mac_state &
2268 hdev->hw.mac.phydev->link;
2269 else
2270 link_stat = 0;
2271
2272 } else {
2273 link_stat = mac_state;
2274 }
2275
2276 return !!link_stat;
2277}
2278
2279static void hclge_update_link_status(struct hclge_dev *hdev)
2280{
2281 struct hnae3_client *client = hdev->nic_client;
2282 struct hnae3_handle *handle;
2283 int state;
2284 int i;
2285
2286 if (!client)
2287 return;
2288 state = hclge_get_mac_phy_link(hdev);
2289 if (state != hdev->hw.mac.link) {
2290 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2291 handle = &hdev->vport[i].nic;
2292 client->ops->link_status_change(handle, state);
2293 }
2294 hdev->hw.mac.link = state;
2295 }
2296}
2297
2298static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2299{
2300 struct hclge_mac mac = hdev->hw.mac;
2301 u8 duplex;
2302 int speed;
2303 int ret;
2304
2305 /* get the speed and duplex as autoneg'result from mac cmd when phy
2306 * doesn't exit.
2307 */
c040366b 2308 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2309 return 0;
2310
2311 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2312 if (ret) {
2313 dev_err(&hdev->pdev->dev,
2314 "mac autoneg/speed/duplex query failed %d\n", ret);
2315 return ret;
2316 }
2317
2318 if ((mac.speed != speed) || (mac.duplex != duplex)) {
2319 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2320 if (ret) {
2321 dev_err(&hdev->pdev->dev,
2322 "mac speed/duplex config failed %d\n", ret);
2323 return ret;
2324 }
2325 }
2326
2327 return 0;
2328}
2329
2330static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2331{
2332 struct hclge_vport *vport = hclge_get_vport(handle);
2333 struct hclge_dev *hdev = vport->back;
2334
2335 return hclge_update_speed_duplex(hdev);
2336}
2337
2338static int hclge_get_status(struct hnae3_handle *handle)
2339{
2340 struct hclge_vport *vport = hclge_get_vport(handle);
2341 struct hclge_dev *hdev = vport->back;
2342
2343 hclge_update_link_status(hdev);
2344
2345 return hdev->hw.mac.link;
2346}
2347
d039ef68 2348static void hclge_service_timer(struct timer_list *t)
46a3df9f 2349{
d039ef68 2350 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2351
d039ef68 2352 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 2353 hclge_task_schedule(hdev);
2354}
2355
2356static void hclge_service_complete(struct hclge_dev *hdev)
2357{
2358 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2359
2360 /* Flush memory before next watchdog */
2361 smp_mb__before_atomic();
2362 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2363}
2364
ca1d7669
SM		 2365static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2366{
2367 u32 rst_src_reg;
2368
2369 /* fetch the events from their corresponding regs */
2370 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG);
2371
2372 /* check for vector0 reset event sources */
2373 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
2374 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2375 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2376 return HCLGE_VECTOR0_EVENT_RST;
2377 }
2378
2379 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
2380 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2381 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2382 return HCLGE_VECTOR0_EVENT_RST;
2383 }
2384
2385 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2386 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2387 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2388 return HCLGE_VECTOR0_EVENT_RST;
2389 }
2390
2391 /* mailbox event sharing vector 0 interrupt would be placed here */
2392
2393 return HCLGE_VECTOR0_EVENT_OTHER;
2394}
2395
2396static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2397 u32 regclr)
2398{
2399 if (event_type == HCLGE_VECTOR0_EVENT_RST)
2400 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
2401
2402 /* mailbox event sharing vector 0 interrupt would be placed here */
2403}
2404
466b0c00
L		 2405static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2406{
2407 writel(enable ? 1 : 0, vector->addr);
2408}
2409
2410static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2411{
2412 struct hclge_dev *hdev = data;
ca1d7669
SM		 2413 u32 event_cause;
2414 u32 clearval;
466b0c00
L		 2415
2416 hclge_enable_vector(&hdev->misc_vector, false);
ca1d7669
SM		 2417 event_cause = hclge_check_event_cause(hdev, &clearval);
2418
2419 /* vector 0 interrupt is shared with reset and mailbox source events.
2420 * For now, we are not handling mailbox events.
2421 */
2422 switch (event_cause) {
2423 case HCLGE_VECTOR0_EVENT_RST:
2424 /* reset task to be scheduled here */
2425 break;
2426 default:
2427 dev_dbg(&hdev->pdev->dev,
2428 "received unknown or unhandled event of vector0\n");
2429 break;
2430 }
2431
2432 /* we should clear the source of interrupt */
2433 hclge_clear_event_cause(hdev, event_cause, clearval);
2434 hclge_enable_vector(&hdev->misc_vector, true);
466b0c00
L		 2435
2436 return IRQ_HANDLED;
2437}
2438
2439static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2440{
2441 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2442 hdev->num_msi_left += 1;
2443 hdev->num_msi_used -= 1;
2444}
2445
2446static void hclge_get_misc_vector(struct hclge_dev *hdev)
2447{
2448 struct hclge_misc_vector *vector = &hdev->misc_vector;
2449
2450 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2451
2452 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2453 hdev->vector_status[0] = 0;
2454
2455 hdev->num_msi_left -= 1;
2456 hdev->num_msi_used += 1;
2457}
2458
2459static int hclge_misc_irq_init(struct hclge_dev *hdev)
2460{
2461 int ret;
2462
2463 hclge_get_misc_vector(hdev);
2464
ca1d7669
SM		 2465 /* this would be explicitly freed in the end */
2466 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2467 0, "hclge_misc", hdev);
466b0c00
L		 2468 if (ret) {
2469 hclge_free_vector(hdev, 0);
2470 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2471 hdev->misc_vector.vector_irq);
2472 }
2473
2474 return ret;
2475}
2476
ca1d7669
SM		 2477static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2478{
2479 free_irq(hdev->misc_vector.vector_irq, hdev);
2480 hclge_free_vector(hdev, 0);
2481}
2482
4ed340ab
L		 2483static int hclge_notify_client(struct hclge_dev *hdev,
2484 enum hnae3_reset_notify_type type)
2485{
2486 struct hnae3_client *client = hdev->nic_client;
2487 u16 i;
2488
2489 if (!client->ops->reset_notify)
2490 return -EOPNOTSUPP;
2491
2492 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2493 struct hnae3_handle *handle = &hdev->vport[i].nic;
2494 int ret;
2495
2496 ret = client->ops->reset_notify(handle, type);
2497 if (ret)
2498 return ret;
2499 }
2500
2501 return 0;
2502}
2503
2504static int hclge_reset_wait(struct hclge_dev *hdev)
2505{
2506#define HCLGE_RESET_WATI_MS 100
2507#define HCLGE_RESET_WAIT_CNT 5
2508 u32 val, reg, reg_bit;
2509 u32 cnt = 0;
2510
2511 switch (hdev->reset_type) {
2512 case HNAE3_GLOBAL_RESET:
2513 reg = HCLGE_GLOBAL_RESET_REG;
2514 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2515 break;
2516 case HNAE3_CORE_RESET:
2517 reg = HCLGE_GLOBAL_RESET_REG;
2518 reg_bit = HCLGE_CORE_RESET_BIT;
2519 break;
2520 case HNAE3_FUNC_RESET:
2521 reg = HCLGE_FUN_RST_ING;
2522 reg_bit = HCLGE_FUN_RST_ING_B;
2523 break;
2524 default:
2525 dev_err(&hdev->pdev->dev,
2526 "Wait for unsupported reset type: %d\n",
2527 hdev->reset_type);
2528 return -EINVAL;
2529 }
2530
2531 val = hclge_read_dev(&hdev->hw, reg);
2532 while (hnae_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
2533 msleep(HCLGE_RESET_WATI_MS);
2534 val = hclge_read_dev(&hdev->hw, reg);
2535 cnt++;
2536 }
2537
4ed340ab
L		 2538 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2539 dev_warn(&hdev->pdev->dev,
2540 "Wait for reset timeout: %d\n", hdev->reset_type);
2541 return -EBUSY;
2542 }
2543
2544 return 0;
2545}
2546
2547static int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
2548{
2549 struct hclge_desc desc;
2550 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2551 int ret;
2552
2553 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
2554 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_MAC_B, 0);
2555 hnae_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
2556 req->fun_reset_vfid = func_id;
2557
2558 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2559 if (ret)
2560 dev_err(&hdev->pdev->dev,
2561 "send function reset cmd fail, status =%d\n", ret);
2562
2563 return ret;
2564}
2565
2566static void hclge_do_reset(struct hclge_dev *hdev, enum hnae3_reset_type type)
2567{
2568 struct pci_dev *pdev = hdev->pdev;
2569 u32 val;
2570
2571 switch (type) {
2572 case HNAE3_GLOBAL_RESET:
2573 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2574 hnae_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
2575 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2576 dev_info(&pdev->dev, "Global Reset requested\n");
2577 break;
2578 case HNAE3_CORE_RESET:
2579 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
2580 hnae_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
2581 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2582 dev_info(&pdev->dev, "Core Reset requested\n");
2583 break;
2584 case HNAE3_FUNC_RESET:
2585 dev_info(&pdev->dev, "PF Reset requested\n");
2586 hclge_func_reset_cmd(hdev, 0);
2587 break;
2588 default:
2589 dev_warn(&pdev->dev,
2590 "Unsupported reset type: %d\n", type);
2591 break;
2592 }
2593}
2594
4ed340ab
L		 2595static void hclge_reset_event(struct hnae3_handle *handle,
2596 enum hnae3_reset_type reset)
2597{
2598 struct hclge_vport *vport = hclge_get_vport(handle);
2599 struct hclge_dev *hdev = vport->back;
2600
2601 dev_info(&hdev->pdev->dev,
2602 "Receive reset event , reset_type is %d", reset);
2603
2604 switch (reset) {
2605 case HNAE3_FUNC_RESET:
2606 case HNAE3_CORE_RESET:
2607 case HNAE3_GLOBAL_RESET:
2608 if (test_bit(HCLGE_STATE_RESET_INT, &hdev->state)) {
2609 dev_err(&hdev->pdev->dev, "Already in reset state");
2610 return;
2611 }
2612 hdev->reset_type = reset;
2613 set_bit(HCLGE_STATE_RESET_INT, &hdev->state);
2614 set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2615 schedule_work(&hdev->service_task);
2616 break;
2617 default:
2618 dev_warn(&hdev->pdev->dev, "Unsupported reset event:%d", reset);
2619 break;
2620 }
2621}
2622
2623static void hclge_reset_subtask(struct hclge_dev *hdev)
2624{
2625 bool do_reset;
2626
2627 do_reset = hdev->reset_type != HNAE3_NONE_RESET;
2628
4ed340ab
L		 2629
2630 if (hdev->reset_type == HNAE3_NONE_RESET)
2631 return;
2632
2633 switch (hdev->reset_type) {
2634 case HNAE3_FUNC_RESET:
2635 case HNAE3_CORE_RESET:
2636 case HNAE3_GLOBAL_RESET:
2637 case HNAE3_IMP_RESET:
2638 hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2639
2640 if (do_reset)
2641 hclge_do_reset(hdev, hdev->reset_type);
2642 else
2643 set_bit(HCLGE_STATE_RESET_INT, &hdev->state);
2644
2645 if (!hclge_reset_wait(hdev)) {
2646 hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2647 hclge_reset_ae_dev(hdev->ae_dev);
2648 hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2649 clear_bit(HCLGE_STATE_RESET_INT, &hdev->state);
2650 }
2651 hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2652 break;
2653 default:
2654 dev_err(&hdev->pdev->dev, "Unsupported reset type:%d\n",
2655 hdev->reset_type);
2656 break;
2657 }
2658 hdev->reset_type = HNAE3_NONE_RESET;
2659}
2660
466b0c00
L		 2661static void hclge_misc_irq_service_task(struct hclge_dev *hdev)
2662{
4ed340ab 2663 hclge_reset_subtask(hdev);
466b0c00
L		 2664}
2665
46a3df9f
S		 2666static void hclge_service_task(struct work_struct *work)
2667{
2668 struct hclge_dev *hdev =
2669 container_of(work, struct hclge_dev, service_task);
2670
466b0c00 2671 hclge_misc_irq_service_task(hdev);
46a3df9f
S		 2672 hclge_update_speed_duplex(hdev);
2673 hclge_update_link_status(hdev);
2674 hclge_update_stats_for_all(hdev);
2675 hclge_service_complete(hdev);
2676}
2677
2678static void hclge_disable_sriov(struct hclge_dev *hdev)
2679{
2a32ca13
AB		 2680 /* If our VFs are assigned we cannot shut down SR-IOV
2681 * without causing issues, so just leave the hardware
2682 * available but disabled
2683 */
2684 if (pci_vfs_assigned(hdev->pdev)) {
2685 dev_warn(&hdev->pdev->dev,
2686 "disabling driver while VFs are assigned\n");
2687 return;
2688 }
46a3df9f 2689
2a32ca13 2690 pci_disable_sriov(hdev->pdev);
46a3df9f
S		 2691}
2692
2693struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2694{
2695 /* VF handle has no client */
2696 if (!handle->client)
2697 return container_of(handle, struct hclge_vport, nic);
2698 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2699 return container_of(handle, struct hclge_vport, roce);
2700 else
2701 return container_of(handle, struct hclge_vport, nic);
2702}
2703
2704static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2705 struct hnae3_vector_info *vector_info)
2706{
2707 struct hclge_vport *vport = hclge_get_vport(handle);
2708 struct hnae3_vector_info *vector = vector_info;
2709 struct hclge_dev *hdev = vport->back;
2710 int alloc = 0;
2711 int i, j;
2712
2713 vector_num = min(hdev->num_msi_left, vector_num);
2714
2715 for (j = 0; j < vector_num; j++) {
2716 for (i = 1; i < hdev->num_msi; i++) {
2717 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2718 vector->vector = pci_irq_vector(hdev->pdev, i);
2719 vector->io_addr = hdev->hw.io_base +
2720 HCLGE_VECTOR_REG_BASE +
2721 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2722 vport->vport_id *
2723 HCLGE_VECTOR_VF_OFFSET;
2724 hdev->vector_status[i] = vport->vport_id;
887c3820 2725 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2726
2727 vector++;
2728 alloc++;
2729
2730 break;
2731 }
2732 }
2733 }
2734 hdev->num_msi_left -= alloc;
2735 hdev->num_msi_used += alloc;
2736
2737 return alloc;
2738}
2739
2740static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2741{
2742 int i;
2743
887c3820
SM		 2744 for (i = 0; i < hdev->num_msi; i++)
2745 if (vector == hdev->vector_irq[i])
2746 return i;
2747
46a3df9f
S		 2748 return -EINVAL;
2749}
2750
2751static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2752{
2753 return HCLGE_RSS_KEY_SIZE;
2754}
2755
2756static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2757{
2758 return HCLGE_RSS_IND_TBL_SIZE;
2759}
2760
2761static int hclge_get_rss_algo(struct hclge_dev *hdev)
2762{
d44f9b63 2763 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2764 struct hclge_desc desc;
2765 int rss_hash_algo;
2766 int ret;
2767
2768 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
2769
2770 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2771 if (ret) {
2772 dev_err(&hdev->pdev->dev,
2773 "Get link status error, status =%d\n", ret);
2774 return ret;
2775 }
2776
d44f9b63 2777 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2778 rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
2779
2780 if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
2781 return ETH_RSS_HASH_TOP;
2782
2783 return -EINVAL;
2784}
2785
2786static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2787 const u8 hfunc, const u8 *key)
2788{
d44f9b63 2789 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2790 struct hclge_desc desc;
2791 int key_offset;
2792 int key_size;
2793 int ret;
2794
d44f9b63 2795 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 2796
2797 for (key_offset = 0; key_offset < 3; key_offset++) {
2798 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
2799 false);
2800
2801 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
2802 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
2803
2804 if (key_offset == 2)
2805 key_size =
2806 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
2807 else
2808 key_size = HCLGE_RSS_HASH_KEY_NUM;
2809
2810 memcpy(req->hash_key,
2811 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
2812
2813 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2814 if (ret) {
2815 dev_err(&hdev->pdev->dev,
2816 "Configure RSS config fail, status = %d\n",
2817 ret);
2818 return ret;
2819 }
2820 }
2821 return 0;
2822}
2823
2824static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
2825{
d44f9b63 2826 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 2827 struct hclge_desc desc;
2828 int i, j;
2829 int ret;
2830
d44f9b63 2831 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 2832
2833 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
2834 hclge_cmd_setup_basic_desc
2835 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
2836
a90bb9a5
YL		 2837 req->start_table_index =
2838 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
2839 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 2840
2841 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
2842 req->rss_result[j] =
2843 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
2844
2845 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2846 if (ret) {
2847 dev_err(&hdev->pdev->dev,
2848 "Configure rss indir table fail,status = %d\n",
2849 ret);
2850 return ret;
2851 }
2852 }
2853 return 0;
2854}
2855
2856static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
2857 u16 *tc_size, u16 *tc_offset)
2858{
d44f9b63 2859 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 2860 struct hclge_desc desc;
2861 int ret;
2862 int i;
2863
2864 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 2865 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 2866
2867 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 2868 u16 mode = 0;
2869
2870 hnae_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
2871 hnae_set_field(mode, HCLGE_RSS_TC_SIZE_M,
46a3df9f 2872 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
a90bb9a5 2873 hnae_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
46a3df9f 2874 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 2875
2876 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 2877 }
2878
2879 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2880 if (ret) {
2881 dev_err(&hdev->pdev->dev,
2882 "Configure rss tc mode fail, status = %d\n", ret);
2883 return ret;
2884 }
2885
2886 return 0;
2887}
2888
2889static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
2890{
d44f9b63 2891 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 2892 struct hclge_desc desc;
2893 int ret;
2894
2895 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
2896
d44f9b63 2897 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
46a3df9f
S		 2898 req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2899 req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2900 req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2901 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2902 req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2903 req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2904 req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
2905 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
2906 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2907 if (ret) {
2908 dev_err(&hdev->pdev->dev,
2909 "Configure rss input fail, status = %d\n", ret);
2910 return ret;
2911 }
2912
2913 return 0;
2914}
2915
2916static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
2917 u8 *key, u8 *hfunc)
2918{
2919 struct hclge_vport *vport = hclge_get_vport(handle);
2920 struct hclge_dev *hdev = vport->back;
2921 int i;
2922
2923 /* Get hash algorithm */
2924 if (hfunc)
2925 *hfunc = hclge_get_rss_algo(hdev);
2926
2927 /* Get the RSS Key required by the user */
2928 if (key)
2929 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
2930
2931 /* Get indirect table */
2932 if (indir)
2933 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2934 indir[i] = vport->rss_indirection_tbl[i];
2935
2936 return 0;
2937}
2938
2939static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
2940 const u8 *key, const u8 hfunc)
2941{
2942 struct hclge_vport *vport = hclge_get_vport(handle);
2943 struct hclge_dev *hdev = vport->back;
2944 u8 hash_algo;
2945 int ret, i;
2946
2947 /* Set the RSS Hash Key if specififed by the user */
2948 if (key) {
2949 /* Update the shadow RSS key with user specified qids */
2950 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
2951
2952 if (hfunc == ETH_RSS_HASH_TOP ||
2953 hfunc == ETH_RSS_HASH_NO_CHANGE)
2954 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
2955 else
2956 return -EINVAL;
2957 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
2958 if (ret)
2959 return ret;
2960 }
2961
2962 /* Update the shadow RSS table with user specified qids */
2963 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
2964 vport->rss_indirection_tbl[i] = indir[i];
2965
2966 /* Update the hardware */
2967 ret = hclge_set_rss_indir_table(hdev, indir);
2968 return ret;
2969}
2970
f7db940a
L		 2971static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
2972{
2973 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
2974
2975 if (nfc->data & RXH_L4_B_2_3)
2976 hash_sets |= HCLGE_D_PORT_BIT;
2977 else
2978 hash_sets &= ~HCLGE_D_PORT_BIT;
2979
2980 if (nfc->data & RXH_IP_SRC)
2981 hash_sets |= HCLGE_S_IP_BIT;
2982 else
2983 hash_sets &= ~HCLGE_S_IP_BIT;
2984
2985 if (nfc->data & RXH_IP_DST)
2986 hash_sets |= HCLGE_D_IP_BIT;
2987 else
2988 hash_sets &= ~HCLGE_D_IP_BIT;
2989
2990 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
2991 hash_sets |= HCLGE_V_TAG_BIT;
2992
2993 return hash_sets;
2994}
2995
2996static int hclge_set_rss_tuple(struct hnae3_handle *handle,
2997 struct ethtool_rxnfc *nfc)
2998{
2999 struct hclge_vport *vport = hclge_get_vport(handle);
3000 struct hclge_dev *hdev = vport->back;
3001 struct hclge_rss_input_tuple_cmd *req;
3002 struct hclge_desc desc;
3003 u8 tuple_sets;
3004 int ret;
3005
3006 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3007 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3008 return -EINVAL;
3009
3010 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3011 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3012 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3013 if (ret) {
3014 dev_err(&hdev->pdev->dev,
3015 "Read rss tuple fail, status = %d\n", ret);
3016 return ret;
3017 }
3018
3019 hclge_cmd_reuse_desc(&desc, false);
3020
3021 tuple_sets = hclge_get_rss_hash_bits(nfc);
3022 switch (nfc->flow_type) {
3023 case TCP_V4_FLOW:
3024 req->ipv4_tcp_en = tuple_sets;
3025 break;
3026 case TCP_V6_FLOW:
3027 req->ipv6_tcp_en = tuple_sets;
3028 break;
3029 case UDP_V4_FLOW:
3030 req->ipv4_udp_en = tuple_sets;
3031 break;
3032 case UDP_V6_FLOW:
3033 req->ipv6_udp_en = tuple_sets;
3034 break;
3035 case SCTP_V4_FLOW:
3036 req->ipv4_sctp_en = tuple_sets;
3037 break;
3038 case SCTP_V6_FLOW:
3039 if ((nfc->data & RXH_L4_B_0_1) ||
3040 (nfc->data & RXH_L4_B_2_3))
3041 return -EINVAL;
3042
3043 req->ipv6_sctp_en = tuple_sets;
3044 break;
3045 case IPV4_FLOW:
3046 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3047 break;
3048 case IPV6_FLOW:
3049 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3050 break;
3051 default:
3052 return -EINVAL;
3053 }
3054
3055 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3056 if (ret)
3057 dev_err(&hdev->pdev->dev,
3058 "Set rss tuple fail, status = %d\n", ret);
3059
3060 return ret;
3061}
3062
07d29954
L		 3063static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3064 struct ethtool_rxnfc *nfc)
3065{
3066 struct hclge_vport *vport = hclge_get_vport(handle);
3067 struct hclge_dev *hdev = vport->back;
3068 struct hclge_rss_input_tuple_cmd *req;
3069 struct hclge_desc desc;
3070 u8 tuple_sets;
3071 int ret;
3072
3073 nfc->data = 0;
3074
3075 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
3076 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, true);
3077 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3078 if (ret) {
3079 dev_err(&hdev->pdev->dev,
3080 "Read rss tuple fail, status = %d\n", ret);
3081 return ret;
3082 }
3083
3084 switch (nfc->flow_type) {
3085 case TCP_V4_FLOW:
3086 tuple_sets = req->ipv4_tcp_en;
3087 break;
3088 case UDP_V4_FLOW:
3089 tuple_sets = req->ipv4_udp_en;
3090 break;
3091 case TCP_V6_FLOW:
3092 tuple_sets = req->ipv6_tcp_en;
3093 break;
3094 case UDP_V6_FLOW:
3095 tuple_sets = req->ipv6_udp_en;
3096 break;
3097 case SCTP_V4_FLOW:
3098 tuple_sets = req->ipv4_sctp_en;
3099 break;
3100 case SCTP_V6_FLOW:
3101 tuple_sets = req->ipv6_sctp_en;
3102 break;
3103 case IPV4_FLOW:
3104 case IPV6_FLOW:
3105 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3106 break;
3107 default:
3108 return -EINVAL;
3109 }
3110
3111 if (!tuple_sets)
3112 return 0;
3113
3114 if (tuple_sets & HCLGE_D_PORT_BIT)
3115 nfc->data |= RXH_L4_B_2_3;
3116 if (tuple_sets & HCLGE_S_PORT_BIT)
3117 nfc->data |= RXH_L4_B_0_1;
3118 if (tuple_sets & HCLGE_D_IP_BIT)
3119 nfc->data |= RXH_IP_DST;
3120 if (tuple_sets & HCLGE_S_IP_BIT)
3121 nfc->data |= RXH_IP_SRC;
3122
3123 return 0;
3124}
3125
46a3df9f
S		 3126static int hclge_get_tc_size(struct hnae3_handle *handle)
3127{
3128 struct hclge_vport *vport = hclge_get_vport(handle);
3129 struct hclge_dev *hdev = vport->back;
3130
3131 return hdev->rss_size_max;
3132}
3133
77f255c1 3134int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f
S		 3135{
3136 const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
3137 struct hclge_vport *vport = hdev->vport;
3138 u16 tc_offset[HCLGE_MAX_TC_NUM];
3139 u8 rss_key[HCLGE_RSS_KEY_SIZE];
3140 u16 tc_valid[HCLGE_MAX_TC_NUM];
3141 u16 tc_size[HCLGE_MAX_TC_NUM];
3142 u32 *rss_indir = NULL;
68ece54e 3143 u16 rss_size = 0, roundup_size;
46a3df9f
S		 3144 const u8 *key;
3145 int i, ret, j;
3146
3147 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
3148 if (!rss_indir)
3149 return -ENOMEM;
3150
3151 /* Get default RSS key */
3152 netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
3153
3154 /* Initialize RSS indirect table for each vport */
3155 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3156 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
3157 vport[j].rss_indirection_tbl[i] =
68ece54e
YL		 3158 i % vport[j].alloc_rss_size;
3159
3160 /* vport 0 is for PF */
3161 if (j != 0)
3162 continue;
3163
3164 rss_size = vport[j].alloc_rss_size;
46a3df9f
S		 3165 rss_indir[i] = vport[j].rss_indirection_tbl[i];
3166 }
3167 }
3168 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3169 if (ret)
3170 goto err;
3171
3172 key = rss_key;
3173 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3174 if (ret)
3175 goto err;
3176
3177 ret = hclge_set_rss_input_tuple(hdev);
3178 if (ret)
3179 goto err;
3180
68ece54e
YL		 3181 /* Each TC have the same queue size, and tc_size set to hardware is
3182 * the log2 of roundup power of two of rss_size, the acutal queue
3183 * size is limited by indirection table.
3184 */
3185 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3186 dev_err(&hdev->pdev->dev,
3187 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3188 rss_size);
81359617
CJ		 3189 ret = -EINVAL;
3190 goto err;
68ece54e
YL		 3191 }
3192
3193 roundup_size = roundup_pow_of_two(rss_size);
3194 roundup_size = ilog2(roundup_size);
3195
46a3df9f 3196 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3197 tc_valid[i] = 0;
46a3df9f 3198
68ece54e
YL		 3199 if (!(hdev->hw_tc_map & BIT(i)))
3200 continue;
3201
3202 tc_valid[i] = 1;
3203 tc_size[i] = roundup_size;
3204 tc_offset[i] = rss_size * i;
46a3df9f 3205 }
68ece54e 3206
46a3df9f
S		 3207 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3208
3209err:
3210 kfree(rss_indir);
3211
3212 return ret;
3213}
3214
3215int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,
3216 struct hnae3_ring_chain_node *ring_chain)
3217{
3218 struct hclge_dev *hdev = vport->back;
d44f9b63 3219 struct hclge_ctrl_vector_chain_cmd *req;
46a3df9f
S		 3220 struct hnae3_ring_chain_node *node;
3221 struct hclge_desc desc;
3222 int ret;
3223 int i;
3224
3225 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ADD_RING_TO_VECTOR, false);
3226
d44f9b63 3227 req = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
46a3df9f
S		 3228 req->int_vector_id = vector_id;
3229
3230 i = 0;
3231 for (node = ring_chain; node; node = node->next) {
a90bb9a5
YL		 3232 u16 type_and_id = 0;
3233
3234 hnae_set_field(type_and_id, HCLGE_INT_TYPE_M, HCLGE_INT_TYPE_S,
46a3df9f 3235 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
a90bb9a5
YL		 3236 hnae_set_field(type_and_id, HCLGE_TQP_ID_M, HCLGE_TQP_ID_S,
3237 node->tqp_index);
3238 hnae_set_field(type_and_id, HCLGE_INT_GL_IDX_M,
0305b443
L		 3239 HCLGE_INT_GL_IDX_S,
3240 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
a90bb9a5 3241 req->tqp_type_and_id[i] = cpu_to_le16(type_and_id);
0305b443 3242 req->vfid = vport->vport_id;
46a3df9f
S		 3243
3244 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3245 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3246
3247 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3248 if (ret) {
3249 dev_err(&hdev->pdev->dev,
3250 "Map TQP fail, status is %d.\n",
3251 ret);
3252 return ret;
3253 }
3254 i = 0;
3255
3256 hclge_cmd_setup_basic_desc(&desc,
3257 HCLGE_OPC_ADD_RING_TO_VECTOR,
3258 false);
3259 req->int_vector_id = vector_id;
3260 }
3261 }
3262
3263 if (i > 0) {
3264 req->int_cause_num = i;
3265
3266 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3267 if (ret) {
3268 dev_err(&hdev->pdev->dev,
3269 "Map TQP fail, status is %d.\n", ret);
3270 return ret;
3271 }
3272 }
3273
3274 return 0;
3275}
3276
1db9b1bf
YL		 3277static int hclge_map_handle_ring_to_vector(
3278 struct hnae3_handle *handle, int vector,
3279 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3280{
3281 struct hclge_vport *vport = hclge_get_vport(handle);
3282 struct hclge_dev *hdev = vport->back;
3283 int vector_id;
3284
3285 vector_id = hclge_get_vector_index(hdev, vector);
3286 if (vector_id < 0) {
3287 dev_err(&hdev->pdev->dev,
3288 "Get vector index fail. ret =%d\n", vector_id);
3289 return vector_id;
3290 }
3291
3292 return hclge_map_vport_ring_to_vector(vport, vector_id, ring_chain);
3293}
3294
3295static int hclge_unmap_ring_from_vector(
3296 struct hnae3_handle *handle, int vector,
3297 struct hnae3_ring_chain_node *ring_chain)
3298{
3299 struct hclge_vport *vport = hclge_get_vport(handle);
3300 struct hclge_dev *hdev = vport->back;
d44f9b63 3301 struct hclge_ctrl_vector_chain_cmd *req;
46a3df9f
S		 3302 struct hnae3_ring_chain_node *node;
3303 struct hclge_desc desc;
3304 int i, vector_id;
3305 int ret;
3306
3307 vector_id = hclge_get_vector_index(hdev, vector);
3308 if (vector_id < 0) {
3309 dev_err(&handle->pdev->dev,
3310 "Get vector index fail. ret =%d\n", vector_id);
3311 return vector_id;
3312 }
3313
3314 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_DEL_RING_TO_VECTOR, false);
3315
d44f9b63 3316 req = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
46a3df9f
S		 3317 req->int_vector_id = vector_id;
3318
3319 i = 0;
3320 for (node = ring_chain; node; node = node->next) {
a90bb9a5
YL		 3321 u16 type_and_id = 0;
3322
3323 hnae_set_field(type_and_id, HCLGE_INT_TYPE_M, HCLGE_INT_TYPE_S,
46a3df9f 3324 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
a90bb9a5
YL		 3325 hnae_set_field(type_and_id, HCLGE_TQP_ID_M, HCLGE_TQP_ID_S,
3326 node->tqp_index);
3327 hnae_set_field(type_and_id, HCLGE_INT_GL_IDX_M,
0305b443
L		 3328 HCLGE_INT_GL_IDX_S,
3329 hnae_get_bit(node->flag, HNAE3_RING_TYPE_B));
46a3df9f 3330
a90bb9a5 3331 req->tqp_type_and_id[i] = cpu_to_le16(type_and_id);
0305b443 3332 req->vfid = vport->vport_id;
46a3df9f
S		 3333
3334 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3335 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
3336
3337 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3338 if (ret) {
3339 dev_err(&hdev->pdev->dev,
3340 "Unmap TQP fail, status is %d.\n",
3341 ret);
3342 return ret;
3343 }
3344 i = 0;
3345 hclge_cmd_setup_basic_desc(&desc,
c5b1b975 3346 HCLGE_OPC_DEL_RING_TO_VECTOR,
46a3df9f
S		 3347 false);
3348 req->int_vector_id = vector_id;
3349 }
3350 }
3351
3352 if (i > 0) {
3353 req->int_cause_num = i;
3354
3355 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3356 if (ret) {
3357 dev_err(&hdev->pdev->dev,
3358 "Unmap TQP fail, status is %d.\n", ret);
3359 return ret;
3360 }
3361 }
3362
3363 return 0;
3364}
3365
3366int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3367 struct hclge_promisc_param *param)
3368{
d44f9b63 3369 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3370 struct hclge_desc desc;
3371 int ret;
3372
3373 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3374
d44f9b63 3375 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f
S		 3376 req->vf_id = param->vf_id;
3377 req->flag = (param->enable << HCLGE_PROMISC_EN_B);
3378
3379 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3380 if (ret) {
3381 dev_err(&hdev->pdev->dev,
3382 "Set promisc mode fail, status is %d.\n", ret);
3383 return ret;
3384 }
3385 return 0;
3386}
3387
3388void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3389 bool en_mc, bool en_bc, int vport_id)
3390{
3391 if (!param)
3392 return;
3393
3394 memset(param, 0, sizeof(struct hclge_promisc_param));
3395 if (en_uc)
3396 param->enable = HCLGE_PROMISC_EN_UC;
3397 if (en_mc)
3398 param->enable |= HCLGE_PROMISC_EN_MC;
3399 if (en_bc)
3400 param->enable |= HCLGE_PROMISC_EN_BC;
3401 param->vf_id = vport_id;
3402}
3403
3404static void hclge_set_promisc_mode(struct hnae3_handle *handle, u32 en)
3405{
3406 struct hclge_vport *vport = hclge_get_vport(handle);
3407 struct hclge_dev *hdev = vport->back;
3408 struct hclge_promisc_param param;
3409
3410 hclge_promisc_param_init(&param, en, en, true, vport->vport_id);
3411 hclge_cmd_set_promisc_mode(hdev, &param);
3412}
3413
3414static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
3415{
3416 struct hclge_desc desc;
d44f9b63
YL		 3417 struct hclge_config_mac_mode_cmd *req =
3418 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 3419 u32 loop_en = 0;
46a3df9f
S		 3420 int ret;
3421
3422 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
a90bb9a5
YL		 3423 hnae_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
3424 hnae_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
3425 hnae_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
3426 hnae_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
3427 hnae_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
3428 hnae_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
3429 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3430 hnae_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
3431 hnae_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
3432 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
3433 hnae_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
3434 hnae_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
3435 hnae_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
3436 hnae_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
3437 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 3438
3439 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3440 if (ret)
3441 dev_err(&hdev->pdev->dev,
3442 "mac enable fail, ret =%d.\n", ret);
3443}
3444
c39c4d98
YL		 3445static int hclge_set_loopback(struct hnae3_handle *handle,
3446 enum hnae3_loop loop_mode, bool en)
3447{
3448 struct hclge_vport *vport = hclge_get_vport(handle);
3449 struct hclge_config_mac_mode_cmd *req;
3450 struct hclge_dev *hdev = vport->back;
3451 struct hclge_desc desc;
3452 u32 loop_en;
3453 int ret;
3454
3455 switch (loop_mode) {
3456 case HNAE3_MAC_INTER_LOOP_MAC:
3457 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
3458 /* 1 Read out the MAC mode config at first */
3459 hclge_cmd_setup_basic_desc(&desc,
3460 HCLGE_OPC_CONFIG_MAC_MODE,
3461 true);
3462 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3463 if (ret) {
3464 dev_err(&hdev->pdev->dev,
3465 "mac loopback get fail, ret =%d.\n",
3466 ret);
3467 return ret;
3468 }
3469
3470 /* 2 Then setup the loopback flag */
3471 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
3472 if (en)
3473 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 1);
3474 else
3475 hnae_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
3476
3477 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
3478
3479 /* 3 Config mac work mode with loopback flag
3480 * and its original configure parameters
3481 */
3482 hclge_cmd_reuse_desc(&desc, false);
3483 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3484 if (ret)
3485 dev_err(&hdev->pdev->dev,
3486 "mac loopback set fail, ret =%d.\n", ret);
3487 break;
3488 default:
3489 ret = -ENOTSUPP;
3490 dev_err(&hdev->pdev->dev,
3491 "loop_mode %d is not supported\n", loop_mode);
3492 break;
3493 }
3494
3495 return ret;
3496}
3497
46a3df9f
S		 3498static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
3499 int stream_id, bool enable)
3500{
3501 struct hclge_desc desc;
d44f9b63
YL		 3502 struct hclge_cfg_com_tqp_queue_cmd *req =
3503 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
46a3df9f
S		 3504 int ret;
3505
3506 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
3507 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
3508 req->stream_id = cpu_to_le16(stream_id);
3509 req->enable |= enable << HCLGE_TQP_ENABLE_B;
3510
3511 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3512 if (ret)
3513 dev_err(&hdev->pdev->dev,
3514 "Tqp enable fail, status =%d.\n", ret);
3515 return ret;
3516}
3517
3518static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
3519{
3520 struct hclge_vport *vport = hclge_get_vport(handle);
3521 struct hnae3_queue *queue;
3522 struct hclge_tqp *tqp;
3523 int i;
3524
3525 for (i = 0; i < vport->alloc_tqps; i++) {
3526 queue = handle->kinfo.tqp[i];
3527 tqp = container_of(queue, struct hclge_tqp, q);
3528 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
3529 }
3530}
3531
3532static int hclge_ae_start(struct hnae3_handle *handle)
3533{
3534 struct hclge_vport *vport = hclge_get_vport(handle);
3535 struct hclge_dev *hdev = vport->back;
3536 int i, queue_id, ret;
3537
3538 for (i = 0; i < vport->alloc_tqps; i++) {
3539 /* todo clear interrupt */
3540 /* ring enable */
3541 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3542 if (queue_id < 0) {
3543 dev_warn(&hdev->pdev->dev,
3544 "Get invalid queue id, ignore it\n");
3545 continue;
3546 }
3547
3548 hclge_tqp_enable(hdev, queue_id, 0, true);
3549 }
3550 /* mac enable */
3551 hclge_cfg_mac_mode(hdev, true);
3552 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 3553 mod_timer(&hdev->service_timer, jiffies + HZ);
46a3df9f
S		 3554
3555 ret = hclge_mac_start_phy(hdev);
3556 if (ret)
3557 return ret;
3558
3559 /* reset tqp stats */
3560 hclge_reset_tqp_stats(handle);
3561
3562 return 0;
3563}
3564
3565static void hclge_ae_stop(struct hnae3_handle *handle)
3566{
3567 struct hclge_vport *vport = hclge_get_vport(handle);
3568 struct hclge_dev *hdev = vport->back;
3569 int i, queue_id;
3570
3571 for (i = 0; i < vport->alloc_tqps; i++) {
3572 /* Ring disable */
3573 queue_id = hclge_get_queue_id(handle->kinfo.tqp[i]);
3574 if (queue_id < 0) {
3575 dev_warn(&hdev->pdev->dev,
3576 "Get invalid queue id, ignore it\n");
3577 continue;
3578 }
3579
3580 hclge_tqp_enable(hdev, queue_id, 0, false);
3581 }
3582 /* Mac disable */
3583 hclge_cfg_mac_mode(hdev, false);
3584
3585 hclge_mac_stop_phy(hdev);
3586
3587 /* reset tqp stats */
3588 hclge_reset_tqp_stats(handle);
3589}
3590
3591static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
3592 u16 cmdq_resp, u8 resp_code,
3593 enum hclge_mac_vlan_tbl_opcode op)
3594{
3595 struct hclge_dev *hdev = vport->back;
3596 int return_status = -EIO;
3597
3598 if (cmdq_resp) {
3599 dev_err(&hdev->pdev->dev,
3600 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
3601 cmdq_resp);
3602 return -EIO;
3603 }
3604
3605 if (op == HCLGE_MAC_VLAN_ADD) {
3606 if ((!resp_code) || (resp_code == 1)) {
3607 return_status = 0;
3608 } else if (resp_code == 2) {
3609 return_status = -EIO;
3610 dev_err(&hdev->pdev->dev,
3611 "add mac addr failed for uc_overflow.\n");
3612 } else if (resp_code == 3) {
3613 return_status = -EIO;
3614 dev_err(&hdev->pdev->dev,
3615 "add mac addr failed for mc_overflow.\n");
3616 } else {
3617 dev_err(&hdev->pdev->dev,
3618 "add mac addr failed for undefined, code=%d.\n",
3619 resp_code);
3620 }
3621 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
3622 if (!resp_code) {
3623 return_status = 0;
3624 } else if (resp_code == 1) {
3625 return_status = -EIO;
3626 dev_dbg(&hdev->pdev->dev,
3627 "remove mac addr failed for miss.\n");
3628 } else {
3629 dev_err(&hdev->pdev->dev,
3630 "remove mac addr failed for undefined, code=%d.\n",
3631 resp_code);
3632 }
3633 } else if (op == HCLGE_MAC_VLAN_LKUP) {
3634 if (!resp_code) {
3635 return_status = 0;
3636 } else if (resp_code == 1) {
3637 return_status = -EIO;
3638 dev_dbg(&hdev->pdev->dev,
3639 "lookup mac addr failed for miss.\n");
3640 } else {
3641 dev_err(&hdev->pdev->dev,
3642 "lookup mac addr failed for undefined, code=%d.\n",
3643 resp_code);
3644 }
3645 } else {
3646 return_status = -EIO;
3647 dev_err(&hdev->pdev->dev,
3648 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
3649 op);
3650 }
3651
3652 return return_status;
3653}
3654
3655static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
3656{
3657 int word_num;
3658 int bit_num;
3659
3660 if (vfid > 255 || vfid < 0)
3661 return -EIO;
3662
3663 if (vfid >= 0 && vfid <= 191) {
3664 word_num = vfid / 32;
3665 bit_num = vfid % 32;
3666 if (clr)
a90bb9a5 3667 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3668 else
a90bb9a5 3669 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3670 } else {
3671 word_num = (vfid - 192) / 32;
3672 bit_num = vfid % 32;
3673 if (clr)
a90bb9a5 3674 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 3675 else
a90bb9a5 3676 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 3677 }
3678
3679 return 0;
3680}
3681
3682static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
3683{
3684#define HCLGE_DESC_NUMBER 3
3685#define HCLGE_FUNC_NUMBER_PER_DESC 6
3686 int i, j;
3687
3688 for (i = 0; i < HCLGE_DESC_NUMBER; i++)
3689 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
3690 if (desc[i].data[j])
3691 return false;
3692
3693 return true;
3694}
3695
d44f9b63 3696static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 3697 const u8 *addr)
3698{
3699 const unsigned char *mac_addr = addr;
3700 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
3701 (mac_addr[0]) | (mac_addr[1] << 8);
3702 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
3703
3704 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
3705 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
3706}
3707
1db9b1bf
YL		 3708static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport,
3709 const u8 *addr)
46a3df9f
S		 3710{
3711 u16 high_val = addr[1] | (addr[0] << 8);
3712 struct hclge_dev *hdev = vport->back;
3713 u32 rsh = 4 - hdev->mta_mac_sel_type;
3714 u16 ret_val = (high_val >> rsh) & 0xfff;
3715
3716 return ret_val;
3717}
3718
3719static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
3720 enum hclge_mta_dmac_sel_type mta_mac_sel,
3721 bool enable)
3722{
d44f9b63 3723 struct hclge_mta_filter_mode_cmd *req;
46a3df9f
S		 3724 struct hclge_desc desc;
3725 int ret;
3726
d44f9b63 3727 req = (struct hclge_mta_filter_mode_cmd *)desc.data;
46a3df9f
S		 3728 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false);
3729
3730 hnae_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B,
3731 enable);
3732 hnae_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M,
3733 HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel);
3734
3735 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3736 if (ret) {
3737 dev_err(&hdev->pdev->dev,
3738 "Config mat filter mode failed for cmd_send, ret =%d.\n",
3739 ret);
3740 return ret;
3741 }
3742
3743 return 0;
3744}
3745
3746int hclge_cfg_func_mta_filter(struct hclge_dev *hdev,
3747 u8 func_id,
3748 bool enable)
3749{
d44f9b63 3750 struct hclge_cfg_func_mta_filter_cmd *req;
46a3df9f
S		 3751 struct hclge_desc desc;
3752 int ret;
3753
d44f9b63 3754 req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data;
46a3df9f
S		 3755 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false);
3756
3757 hnae_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B,
3758 enable);
3759 req->function_id = func_id;
3760
3761 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3762 if (ret) {
3763 dev_err(&hdev->pdev->dev,
3764 "Config func_id enable failed for cmd_send, ret =%d.\n",
3765 ret);
3766 return ret;
3767 }
3768
3769 return 0;
3770}
3771
3772static int hclge_set_mta_table_item(struct hclge_vport *vport,
3773 u16 idx,
3774 bool enable)
3775{
3776 struct hclge_dev *hdev = vport->back;
d44f9b63 3777 struct hclge_cfg_func_mta_item_cmd *req;
46a3df9f 3778 struct hclge_desc desc;
a90bb9a5 3779 u16 item_idx = 0;
46a3df9f
S		 3780 int ret;
3781
d44f9b63 3782 req = (struct hclge_cfg_func_mta_item_cmd *)desc.data;
46a3df9f
S		 3783 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false);
3784 hnae_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable);
3785
a90bb9a5 3786 hnae_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M,
46a3df9f 3787 HCLGE_CFG_MTA_ITEM_IDX_S, idx);
a90bb9a5 3788 req->item_idx = cpu_to_le16(item_idx);
46a3df9f
S		 3789
3790 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3791 if (ret) {
3792 dev_err(&hdev->pdev->dev,
3793 "Config mta table item failed for cmd_send, ret =%d.\n",
3794 ret);
3795 return ret;
3796 }
3797
3798 return 0;
3799}
3800
3801static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3802 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 3803{
3804 struct hclge_dev *hdev = vport->back;
3805 struct hclge_desc desc;
3806 u8 resp_code;
a90bb9a5 3807 u16 retval;
46a3df9f
S		 3808 int ret;
3809
3810 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
3811
d44f9b63 3812 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3813
3814 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3815 if (ret) {
3816 dev_err(&hdev->pdev->dev,
3817 "del mac addr failed for cmd_send, ret =%d.\n",
3818 ret);
3819 return ret;
3820 }
a90bb9a5
YL		 3821 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3822 retval = le16_to_cpu(desc.retval);
46a3df9f 3823
a90bb9a5 3824 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3825 HCLGE_MAC_VLAN_REMOVE);
3826}
3827
3828static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3829 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3830 struct hclge_desc *desc,
3831 bool is_mc)
3832{
3833 struct hclge_dev *hdev = vport->back;
3834 u8 resp_code;
a90bb9a5 3835 u16 retval;
46a3df9f
S		 3836 int ret;
3837
3838 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
3839 if (is_mc) {
3840 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3841 memcpy(desc[0].data,
3842 req,
d44f9b63 3843 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3844 hclge_cmd_setup_basic_desc(&desc[1],
3845 HCLGE_OPC_MAC_VLAN_ADD,
3846 true);
3847 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3848 hclge_cmd_setup_basic_desc(&desc[2],
3849 HCLGE_OPC_MAC_VLAN_ADD,
3850 true);
3851 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3852 } else {
3853 memcpy(desc[0].data,
3854 req,
d44f9b63 3855 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 3856 ret = hclge_cmd_send(&hdev->hw, desc, 1);
3857 }
3858 if (ret) {
3859 dev_err(&hdev->pdev->dev,
3860 "lookup mac addr failed for cmd_send, ret =%d.\n",
3861 ret);
3862 return ret;
3863 }
a90bb9a5
YL		 3864 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
3865 retval = le16_to_cpu(desc[0].retval);
46a3df9f 3866
a90bb9a5 3867 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 3868 HCLGE_MAC_VLAN_LKUP);
3869}
3870
3871static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 3872 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 3873 struct hclge_desc *mc_desc)
3874{
3875 struct hclge_dev *hdev = vport->back;
3876 int cfg_status;
3877 u8 resp_code;
a90bb9a5 3878 u16 retval;
46a3df9f
S		 3879 int ret;
3880
3881 if (!mc_desc) {
3882 struct hclge_desc desc;
3883
3884 hclge_cmd_setup_basic_desc(&desc,
3885 HCLGE_OPC_MAC_VLAN_ADD,
3886 false);
d44f9b63
YL		 3887 memcpy(desc.data, req,
3888 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3889 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 3890 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
3891 retval = le16_to_cpu(desc.retval);
3892
3893 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3894 resp_code,
3895 HCLGE_MAC_VLAN_ADD);
3896 } else {
c3b6f755 3897 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 3898 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3899 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 3900 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 3901 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 3902 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
3903 memcpy(mc_desc[0].data, req,
d44f9b63 3904 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 3905 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 3906 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
3907 retval = le16_to_cpu(mc_desc[0].retval);
3908
3909 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 3910 resp_code,
3911 HCLGE_MAC_VLAN_ADD);
3912 }
3913
3914 if (ret) {
3915 dev_err(&hdev->pdev->dev,
3916 "add mac addr failed for cmd_send, ret =%d.\n",
3917 ret);
3918 return ret;
3919 }
3920
3921 return cfg_status;
3922}
3923
3924static int hclge_add_uc_addr(struct hnae3_handle *handle,
3925 const unsigned char *addr)
3926{
3927 struct hclge_vport *vport = hclge_get_vport(handle);
3928
3929 return hclge_add_uc_addr_common(vport, addr);
3930}
3931
3932int hclge_add_uc_addr_common(struct hclge_vport *vport,
3933 const unsigned char *addr)
3934{
3935 struct hclge_dev *hdev = vport->back;
d44f9b63 3936 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f 3937 enum hclge_cmd_status status;
a90bb9a5 3938 u16 egress_port = 0;
46a3df9f
S		 3939
3940 /* mac addr check */
3941 if (is_zero_ether_addr(addr) ||
3942 is_broadcast_ether_addr(addr) ||
3943 is_multicast_ether_addr(addr)) {
3944 dev_err(&hdev->pdev->dev,
3945 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
3946 addr,
3947 is_zero_ether_addr(addr),
3948 is_broadcast_ether_addr(addr),
3949 is_multicast_ether_addr(addr));
3950 return -EINVAL;
3951 }
3952
3953 memset(&req, 0, sizeof(req));
3954 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
3955 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
3956 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 0);
3957 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
a90bb9a5
YL		 3958
3959 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_SW_EN_B, 0);
3960 hnae_set_bit(egress_port, HCLGE_MAC_EPORT_TYPE_B, 0);
3961 hnae_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
46a3df9f 3962 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5 3963 hnae_set_field(egress_port, HCLGE_MAC_EPORT_PFID_M,
46a3df9f 3964 HCLGE_MAC_EPORT_PFID_S, 0);
a90bb9a5
YL		 3965
3966 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 3967
3968 hclge_prepare_mac_addr(&req, addr);
3969
3970 status = hclge_add_mac_vlan_tbl(vport, &req, NULL);
3971
3972 return status;
3973}
3974
3975static int hclge_rm_uc_addr(struct hnae3_handle *handle,
3976 const unsigned char *addr)
3977{
3978 struct hclge_vport *vport = hclge_get_vport(handle);
3979
3980 return hclge_rm_uc_addr_common(vport, addr);
3981}
3982
3983int hclge_rm_uc_addr_common(struct hclge_vport *vport,
3984 const unsigned char *addr)
3985{
3986 struct hclge_dev *hdev = vport->back;
d44f9b63 3987 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 3988 enum hclge_cmd_status status;
3989
3990 /* mac addr check */
3991 if (is_zero_ether_addr(addr) ||
3992 is_broadcast_ether_addr(addr) ||
3993 is_multicast_ether_addr(addr)) {
3994 dev_dbg(&hdev->pdev->dev,
3995 "Remove mac err! invalid mac:%pM.\n",
3996 addr);
3997 return -EINVAL;
3998 }
3999
4000 memset(&req, 0, sizeof(req));
4001 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4002 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4003 hclge_prepare_mac_addr(&req, addr);
4004 status = hclge_remove_mac_vlan_tbl(vport, &req);
4005
4006 return status;
4007}
4008
4009static int hclge_add_mc_addr(struct hnae3_handle *handle,
4010 const unsigned char *addr)
4011{
4012 struct hclge_vport *vport = hclge_get_vport(handle);
4013
4014 return hclge_add_mc_addr_common(vport, addr);
4015}
4016
4017int hclge_add_mc_addr_common(struct hclge_vport *vport,
4018 const unsigned char *addr)
4019{
4020 struct hclge_dev *hdev = vport->back;
d44f9b63 4021 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4022 struct hclge_desc desc[3];
4023 u16 tbl_idx;
4024 int status;
4025
4026 /* mac addr check */
4027 if (!is_multicast_ether_addr(addr)) {
4028 dev_err(&hdev->pdev->dev,
4029 "Add mc mac err! invalid mac:%pM.\n",
4030 addr);
4031 return -EINVAL;
4032 }
4033 memset(&req, 0, sizeof(req));
4034 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4035 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4036 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4037 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4038 hclge_prepare_mac_addr(&req, addr);
4039 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4040 if (!status) {
4041 /* This mac addr exist, update VFID for it */
4042 hclge_update_desc_vfid(desc, vport->vport_id, false);
4043 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4044 } else {
4045 /* This mac addr do not exist, add new entry for it */
4046 memset(desc[0].data, 0, sizeof(desc[0].data));
4047 memset(desc[1].data, 0, sizeof(desc[0].data));
4048 memset(desc[2].data, 0, sizeof(desc[0].data));
4049 hclge_update_desc_vfid(desc, vport->vport_id, false);
4050 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4051 }
4052
4053 /* Set MTA table for this MAC address */
4054 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4055 status = hclge_set_mta_table_item(vport, tbl_idx, true);
4056
4057 return status;
4058}
4059
4060static int hclge_rm_mc_addr(struct hnae3_handle *handle,
4061 const unsigned char *addr)
4062{
4063 struct hclge_vport *vport = hclge_get_vport(handle);
4064
4065 return hclge_rm_mc_addr_common(vport, addr);
4066}
4067
4068int hclge_rm_mc_addr_common(struct hclge_vport *vport,
4069 const unsigned char *addr)
4070{
4071 struct hclge_dev *hdev = vport->back;
d44f9b63 4072 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 4073 enum hclge_cmd_status status;
4074 struct hclge_desc desc[3];
4075 u16 tbl_idx;
4076
4077 /* mac addr check */
4078 if (!is_multicast_ether_addr(addr)) {
4079 dev_dbg(&hdev->pdev->dev,
4080 "Remove mc mac err! invalid mac:%pM.\n",
4081 addr);
4082 return -EINVAL;
4083 }
4084
4085 memset(&req, 0, sizeof(req));
4086 hnae_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
4087 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4088 hnae_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
4089 hnae_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
4090 hclge_prepare_mac_addr(&req, addr);
4091 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
4092 if (!status) {
4093 /* This mac addr exist, remove this handle's VFID for it */
4094 hclge_update_desc_vfid(desc, vport->vport_id, true);
4095
4096 if (hclge_is_all_function_id_zero(desc))
4097 /* All the vfid is zero, so need to delete this entry */
4098 status = hclge_remove_mac_vlan_tbl(vport, &req);
4099 else
4100 /* Not all the vfid is zero, update the vfid */
4101 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
4102
4103 } else {
4104 /* This mac addr do not exist, can't delete it */
4105 dev_err(&hdev->pdev->dev,
d7629e74 4106 "Rm multicast mac addr failed, ret = %d.\n",
46a3df9f
S		 4107 status);
4108 return -EIO;
4109 }
4110
4111 /* Set MTB table for this MAC address */
4112 tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr);
4113 status = hclge_set_mta_table_item(vport, tbl_idx, false);
4114
4115 return status;
4116}
4117
4118static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
4119{
4120 struct hclge_vport *vport = hclge_get_vport(handle);
4121 struct hclge_dev *hdev = vport->back;
4122
4123 ether_addr_copy(p, hdev->hw.mac.mac_addr);
4124}
4125
4126static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p)
4127{
4128 const unsigned char *new_addr = (const unsigned char *)p;
4129 struct hclge_vport *vport = hclge_get_vport(handle);
4130 struct hclge_dev *hdev = vport->back;
4131
4132 /* mac addr check */
4133 if (is_zero_ether_addr(new_addr) ||
4134 is_broadcast_ether_addr(new_addr) ||
4135 is_multicast_ether_addr(new_addr)) {
4136 dev_err(&hdev->pdev->dev,
4137 "Change uc mac err! invalid mac:%p.\n",
4138 new_addr);
4139 return -EINVAL;
4140 }
4141
4142 hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr);
4143
4144 if (!hclge_add_uc_addr(handle, new_addr)) {
4145 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
4146 return 0;
4147 }
4148
4149 return -EIO;
4150}
4151
4152static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
4153 bool filter_en)
4154{
d44f9b63 4155 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 4156 struct hclge_desc desc;
4157 int ret;
4158
4159 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
4160
d44f9b63 4161 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f
S		 4162 req->vlan_type = vlan_type;
4163 req->vlan_fe = filter_en;
4164
4165 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4166 if (ret) {
4167 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
4168 ret);
4169 return ret;
4170 }
4171
4172 return 0;
4173}
4174
4175int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
4176 bool is_kill, u16 vlan, u8 qos, __be16 proto)
4177{
4178#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 4179 struct hclge_vlan_filter_vf_cfg_cmd *req0;
4180 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 4181 struct hclge_desc desc[2];
4182 u8 vf_byte_val;
4183 u8 vf_byte_off;
4184 int ret;
4185
4186 hclge_cmd_setup_basic_desc(&desc[0],
4187 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4188 hclge_cmd_setup_basic_desc(&desc[1],
4189 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
4190
4191 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
4192
4193 vf_byte_off = vfid / 8;
4194 vf_byte_val = 1 << (vfid % 8);
4195
d44f9b63
YL		 4196 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
4197 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 4198
a90bb9a5 4199 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 4200 req0->vlan_cfg = is_kill;
4201
4202 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
4203 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
4204 else
4205 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
4206
4207 ret = hclge_cmd_send(&hdev->hw, desc, 2);
4208 if (ret) {
4209 dev_err(&hdev->pdev->dev,
4210 "Send vf vlan command fail, ret =%d.\n",
4211 ret);
4212 return ret;
4213 }
4214
4215 if (!is_kill) {
4216 if (!req0->resp_code || req0->resp_code == 1)
4217 return 0;
4218
4219 dev_err(&hdev->pdev->dev,
4220 "Add vf vlan filter fail, ret =%d.\n",
4221 req0->resp_code);
4222 } else {
4223 if (!req0->resp_code)
4224 return 0;
4225
4226 dev_err(&hdev->pdev->dev,
4227 "Kill vf vlan filter fail, ret =%d.\n",
4228 req0->resp_code);
4229 }
4230
4231 return -EIO;
4232}
4233
4234static int hclge_set_port_vlan_filter(struct hnae3_handle *handle,
4235 __be16 proto, u16 vlan_id,
4236 bool is_kill)
4237{
4238 struct hclge_vport *vport = hclge_get_vport(handle);
4239 struct hclge_dev *hdev = vport->back;
d44f9b63 4240 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 4241 struct hclge_desc desc;
4242 u8 vlan_offset_byte_val;
4243 u8 vlan_offset_byte;
4244 u8 vlan_offset_160;
4245 int ret;
4246
4247 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
4248
4249 vlan_offset_160 = vlan_id / 160;
4250 vlan_offset_byte = (vlan_id % 160) / 8;
4251 vlan_offset_byte_val = 1 << (vlan_id % 8);
4252
d44f9b63 4253 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 4254 req->vlan_offset = vlan_offset_160;
4255 req->vlan_cfg = is_kill;
4256 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
4257
4258 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4259 if (ret) {
4260 dev_err(&hdev->pdev->dev,
4261 "port vlan command, send fail, ret =%d.\n",
4262 ret);
4263 return ret;
4264 }
4265
4266 ret = hclge_set_vf_vlan_common(hdev, 0, is_kill, vlan_id, 0, proto);
4267 if (ret) {
4268 dev_err(&hdev->pdev->dev,
4269 "Set pf vlan filter config fail, ret =%d.\n",
4270 ret);
4271 return -EIO;
4272 }
4273
4274 return 0;
4275}
4276
4277static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
4278 u16 vlan, u8 qos, __be16 proto)
4279{
4280 struct hclge_vport *vport = hclge_get_vport(handle);
4281 struct hclge_dev *hdev = vport->back;
4282
4283 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
4284 return -EINVAL;
4285 if (proto != htons(ETH_P_8021Q))
4286 return -EPROTONOSUPPORT;
4287
4288 return hclge_set_vf_vlan_common(hdev, vfid, false, vlan, qos, proto);
4289}
4290
4291static int hclge_init_vlan_config(struct hclge_dev *hdev)
4292{
4293#define HCLGE_VLAN_TYPE_VF_TABLE 0
4294#define HCLGE_VLAN_TYPE_PORT_TABLE 1
5e43aef8 4295 struct hnae3_handle *handle;
46a3df9f
S		 4296 int ret;
4297
4298 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_VF_TABLE,
4299 true);
4300 if (ret)
4301 return ret;
4302
4303 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_VLAN_TYPE_PORT_TABLE,
4304 true);
5e43aef8
L		 4305 if (ret)
4306 return ret;
46a3df9f 4307
5e43aef8
L		 4308 handle = &hdev->vport[0].nic;
4309 return hclge_set_port_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 4310}
4311
4312static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
4313{
4314 struct hclge_vport *vport = hclge_get_vport(handle);
d44f9b63 4315 struct hclge_config_max_frm_size_cmd *req;
46a3df9f
S		 4316 struct hclge_dev *hdev = vport->back;
4317 struct hclge_desc desc;
4318 int ret;
4319
4320 if ((new_mtu < HCLGE_MAC_MIN_MTU) || (new_mtu > HCLGE_MAC_MAX_MTU))
4321 return -EINVAL;
4322
4323 hdev->mps = new_mtu;
4324 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
4325
d44f9b63 4326 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
46a3df9f
S		 4327 req->max_frm_size = cpu_to_le16(new_mtu);
4328
4329 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4330 if (ret) {
4331 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
4332 return ret;
4333 }
4334
4335 return 0;
4336}
4337
4338static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
4339 bool enable)
4340{
d44f9b63 4341 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4342 struct hclge_desc desc;
4343 int ret;
4344
4345 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
4346
d44f9b63 4347 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4348 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4349 hnae_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
4350
4351 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4352 if (ret) {
4353 dev_err(&hdev->pdev->dev,
4354 "Send tqp reset cmd error, status =%d\n", ret);
4355 return ret;
4356 }
4357
4358 return 0;
4359}
4360
4361static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
4362{
d44f9b63 4363 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 4364 struct hclge_desc desc;
4365 int ret;
4366
4367 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
4368
d44f9b63 4369 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 4370 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
4371
4372 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4373 if (ret) {
4374 dev_err(&hdev->pdev->dev,
4375 "Get reset status error, status =%d\n", ret);
4376 return ret;
4377 }
4378
4379 return hnae_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
4380}
4381
4382static void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
4383{
4384 struct hclge_vport *vport = hclge_get_vport(handle);
4385 struct hclge_dev *hdev = vport->back;
4386 int reset_try_times = 0;
4387 int reset_status;
4388 int ret;
4389
4390 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
4391 if (ret) {
4392 dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
4393 return;
4394 }
4395
4396 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, true);
4397 if (ret) {
4398 dev_warn(&hdev->pdev->dev,
4399 "Send reset tqp cmd fail, ret = %d\n", ret);
4400 return;
4401 }
4402
4403 reset_try_times = 0;
4404 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
4405 /* Wait for tqp hw reset */
4406 msleep(20);
4407 reset_status = hclge_get_reset_status(hdev, queue_id);
4408 if (reset_status)
4409 break;
4410 }
4411
4412 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
4413 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
4414 return;
4415 }
4416
4417 ret = hclge_send_reset_tqp_cmd(hdev, queue_id, false);
4418 if (ret) {
4419 dev_warn(&hdev->pdev->dev,
4420 "Deassert the soft reset fail, ret = %d\n", ret);
4421 return;
4422 }
4423}
4424
4425static u32 hclge_get_fw_version(struct hnae3_handle *handle)
4426{
4427 struct hclge_vport *vport = hclge_get_vport(handle);
4428 struct hclge_dev *hdev = vport->back;
4429
4430 return hdev->fw_version;
4431}
4432
4433static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
4434 u32 *rx_en, u32 *tx_en)
4435{
4436 struct hclge_vport *vport = hclge_get_vport(handle);
4437 struct hclge_dev *hdev = vport->back;
4438
4439 *auto_neg = hclge_get_autoneg(handle);
4440
4441 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
4442 *rx_en = 0;
4443 *tx_en = 0;
4444 return;
4445 }
4446
4447 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
4448 *rx_en = 1;
4449 *tx_en = 0;
4450 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
4451 *tx_en = 1;
4452 *rx_en = 0;
4453 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
4454 *rx_en = 1;
4455 *tx_en = 1;
4456 } else {
4457 *rx_en = 0;
4458 *tx_en = 0;
4459 }
4460}
4461
4462static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
4463 u8 *auto_neg, u32 *speed, u8 *duplex)
4464{
4465 struct hclge_vport *vport = hclge_get_vport(handle);
4466 struct hclge_dev *hdev = vport->back;
4467
4468 if (speed)
4469 *speed = hdev->hw.mac.speed;
4470 if (duplex)
4471 *duplex = hdev->hw.mac.duplex;
4472 if (auto_neg)
4473 *auto_neg = hdev->hw.mac.autoneg;
4474}
4475
4476static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
4477{
4478 struct hclge_vport *vport = hclge_get_vport(handle);
4479 struct hclge_dev *hdev = vport->back;
4480
4481 if (media_type)
4482 *media_type = hdev->hw.mac.media_type;
4483}
4484
4485static void hclge_get_mdix_mode(struct hnae3_handle *handle,
4486 u8 *tp_mdix_ctrl, u8 *tp_mdix)
4487{
4488 struct hclge_vport *vport = hclge_get_vport(handle);
4489 struct hclge_dev *hdev = vport->back;
4490 struct phy_device *phydev = hdev->hw.mac.phydev;
4491 int mdix_ctrl, mdix, retval, is_resolved;
4492
4493 if (!phydev) {
4494 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4495 *tp_mdix = ETH_TP_MDI_INVALID;
4496 return;
4497 }
4498
4499 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
4500
4501 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
4502 mdix_ctrl = hnae_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
4503 HCLGE_PHY_MDIX_CTRL_S);
4504
4505 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
4506 mdix = hnae_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
4507 is_resolved = hnae_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
4508
4509 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
4510
4511 switch (mdix_ctrl) {
4512 case 0x0:
4513 *tp_mdix_ctrl = ETH_TP_MDI;
4514 break;
4515 case 0x1:
4516 *tp_mdix_ctrl = ETH_TP_MDI_X;
4517 break;
4518 case 0x3:
4519 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
4520 break;
4521 default:
4522 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
4523 break;
4524 }
4525
4526 if (!is_resolved)
4527 *tp_mdix = ETH_TP_MDI_INVALID;
4528 else if (mdix)
4529 *tp_mdix = ETH_TP_MDI_X;
4530 else
4531 *tp_mdix = ETH_TP_MDI;
4532}
4533
4534static int hclge_init_client_instance(struct hnae3_client *client,
4535 struct hnae3_ae_dev *ae_dev)
4536{
4537 struct hclge_dev *hdev = ae_dev->priv;
4538 struct hclge_vport *vport;
4539 int i, ret;
4540
4541 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4542 vport = &hdev->vport[i];
4543
4544 switch (client->type) {
4545 case HNAE3_CLIENT_KNIC:
4546
4547 hdev->nic_client = client;
4548 vport->nic.client = client;
4549 ret = client->ops->init_instance(&vport->nic);
4550 if (ret)
4551 goto err;
4552
4553 if (hdev->roce_client &&
e92a0843 4554 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4555 struct hnae3_client *rc = hdev->roce_client;
4556
4557 ret = hclge_init_roce_base_info(vport);
4558 if (ret)
4559 goto err;
4560
4561 ret = rc->ops->init_instance(&vport->roce);
4562 if (ret)
4563 goto err;
4564 }
4565
4566 break;
4567 case HNAE3_CLIENT_UNIC:
4568 hdev->nic_client = client;
4569 vport->nic.client = client;
4570
4571 ret = client->ops->init_instance(&vport->nic);
4572 if (ret)
4573 goto err;
4574
4575 break;
4576 case HNAE3_CLIENT_ROCE:
e92a0843 4577 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 4578 hdev->roce_client = client;
4579 vport->roce.client = client;
4580 }
4581
3a46f34d 4582 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 4583 ret = hclge_init_roce_base_info(vport);
4584 if (ret)
4585 goto err;
4586
4587 ret = client->ops->init_instance(&vport->roce);
4588 if (ret)
4589 goto err;
4590 }
4591 }
4592 }
4593
4594 return 0;
4595err:
4596 return ret;
4597}
4598
4599static void hclge_uninit_client_instance(struct hnae3_client *client,
4600 struct hnae3_ae_dev *ae_dev)
4601{
4602 struct hclge_dev *hdev = ae_dev->priv;
4603 struct hclge_vport *vport;
4604 int i;
4605
4606 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
4607 vport = &hdev->vport[i];
a17dcf3f 4608 if (hdev->roce_client) {
46a3df9f
S		 4609 hdev->roce_client->ops->uninit_instance(&vport->roce,
4610 0);
a17dcf3f
L		 4611 hdev->roce_client = NULL;
4612 vport->roce.client = NULL;
4613 }
46a3df9f
S		 4614 if (client->type == HNAE3_CLIENT_ROCE)
4615 return;
a17dcf3f 4616 if (client->ops->uninit_instance) {
46a3df9f 4617 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 4618 hdev->nic_client = NULL;
4619 vport->nic.client = NULL;
4620 }
46a3df9f
S		 4621 }
4622}
4623
4624static int hclge_pci_init(struct hclge_dev *hdev)
4625{
4626 struct pci_dev *pdev = hdev->pdev;
4627 struct hclge_hw *hw;
4628 int ret;
4629
4630 ret = pci_enable_device(pdev);
4631 if (ret) {
4632 dev_err(&pdev->dev, "failed to enable PCI device\n");
4633 goto err_no_drvdata;
4634 }
4635
4636 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
4637 if (ret) {
4638 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
4639 if (ret) {
4640 dev_err(&pdev->dev,
4641 "can't set consistent PCI DMA");
4642 goto err_disable_device;
4643 }
4644 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
4645 }
4646
4647 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
4648 if (ret) {
4649 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
4650 goto err_disable_device;
4651 }
4652
4653 pci_set_master(pdev);
4654 hw = &hdev->hw;
4655 hw->back = hdev;
4656 hw->io_base = pcim_iomap(pdev, 2, 0);
4657 if (!hw->io_base) {
4658 dev_err(&pdev->dev, "Can't map configuration register space\n");
4659 ret = -ENOMEM;
4660 goto err_clr_master;
4661 }
4662
709eb41a
L		 4663 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
4664
46a3df9f
S		 4665 return 0;
4666err_clr_master:
4667 pci_clear_master(pdev);
4668 pci_release_regions(pdev);
4669err_disable_device:
4670 pci_disable_device(pdev);
4671err_no_drvdata:
4672 pci_set_drvdata(pdev, NULL);
4673
4674 return ret;
4675}
4676
4677static void hclge_pci_uninit(struct hclge_dev *hdev)
4678{
4679 struct pci_dev *pdev = hdev->pdev;
4680
887c3820 4681 pci_free_irq_vectors(pdev);
46a3df9f
S		 4682 pci_clear_master(pdev);
4683 pci_release_mem_regions(pdev);
4684 pci_disable_device(pdev);
4685}
4686
4687static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
4688{
4689 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 4690 struct hclge_dev *hdev;
4691 int ret;
4692
4693 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
4694 if (!hdev) {
4695 ret = -ENOMEM;
4696 goto err_hclge_dev;
4697 }
4698
46a3df9f
S		 4699 hdev->pdev = pdev;
4700 hdev->ae_dev = ae_dev;
4ed340ab 4701 hdev->reset_type = HNAE3_NONE_RESET;
ca1d7669 4702 hdev->reset_pending = 0;
46a3df9f
S		 4703 ae_dev->priv = hdev;
4704
46a3df9f
S		 4705 ret = hclge_pci_init(hdev);
4706 if (ret) {
4707 dev_err(&pdev->dev, "PCI init failed\n");
4708 goto err_pci_init;
4709 }
4710
3efb960f
L		 4711 /* Firmware command queue initialize */
4712 ret = hclge_cmd_queue_init(hdev);
4713 if (ret) {
4714 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
4715 return ret;
4716 }
4717
4718 /* Firmware command initialize */
46a3df9f
S		 4719 ret = hclge_cmd_init(hdev);
4720 if (ret)
4721 goto err_cmd_init;
4722
4723 ret = hclge_get_cap(hdev);
4724 if (ret) {
e00e2197
CIK		 4725 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4726 ret);
46a3df9f
S		 4727 return ret;
4728 }
4729
4730 ret = hclge_configure(hdev);
4731 if (ret) {
4732 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4733 return ret;
4734 }
4735
887c3820 4736 ret = hclge_init_msi(hdev);
46a3df9f 4737 if (ret) {
887c3820 4738 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
46a3df9f
S		 4739 return ret;
4740 }
4741
466b0c00
L		 4742 ret = hclge_misc_irq_init(hdev);
4743 if (ret) {
4744 dev_err(&pdev->dev,
4745 "Misc IRQ(vector0) init error, ret = %d.\n",
4746 ret);
4747 return ret;
4748 }
4749
46a3df9f
S		 4750 ret = hclge_alloc_tqps(hdev);
4751 if (ret) {
4752 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
4753 return ret;
4754 }
4755
4756 ret = hclge_alloc_vport(hdev);
4757 if (ret) {
4758 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
4759 return ret;
4760 }
4761
7df7dad6
L		 4762 ret = hclge_map_tqp(hdev);
4763 if (ret) {
4764 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
4765 return ret;
4766 }
4767
cf9cca2d 4768 ret = hclge_mac_mdio_config(hdev);
4769 if (ret) {
4770 dev_warn(&hdev->pdev->dev,
4771 "mdio config fail ret=%d\n", ret);
4772 return ret;
4773 }
4774
46a3df9f
S		 4775 ret = hclge_mac_init(hdev);
4776 if (ret) {
4777 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4778 return ret;
4779 }
4780 ret = hclge_buffer_alloc(hdev);
4781 if (ret) {
4782 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4783 return ret;
4784 }
4785
4786 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4787 if (ret) {
4788 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4789 return ret;
4790 }
4791
46a3df9f
S		 4792 ret = hclge_init_vlan_config(hdev);
4793 if (ret) {
4794 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4795 return ret;
4796 }
4797
4798 ret = hclge_tm_schd_init(hdev);
4799 if (ret) {
4800 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4801 return ret;
68ece54e
YL		 4802 }
4803
4804 ret = hclge_rss_init_hw(hdev);
4805 if (ret) {
4806 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4807 return ret;
46a3df9f
S		 4808 }
4809
cacde272
YL		 4810 hclge_dcb_ops_set(hdev);
4811
d039ef68 4812 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
46a3df9f
S		 4813 INIT_WORK(&hdev->service_task, hclge_service_task);
4814
466b0c00
L		 4815 /* Enable MISC vector(vector0) */
4816 hclge_enable_vector(&hdev->misc_vector, true);
4817
46a3df9f
S		 4818 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
4819 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4820
4821 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
4822 return 0;
4823
4824err_cmd_init:
4825 pci_release_regions(pdev);
4826err_pci_init:
4827 pci_set_drvdata(pdev, NULL);
4828err_hclge_dev:
4829 return ret;
4830}
4831
c6dc5213 4832static void hclge_stats_clear(struct hclge_dev *hdev)
4833{
4834 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
4835}
4836
4ed340ab
L		 4837static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
4838{
4839 struct hclge_dev *hdev = ae_dev->priv;
4840 struct pci_dev *pdev = ae_dev->pdev;
4841 int ret;
4842
4843 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4844
c6dc5213 4845 hclge_stats_clear(hdev);
4846
4ed340ab
L		 4847 ret = hclge_cmd_init(hdev);
4848 if (ret) {
4849 dev_err(&pdev->dev, "Cmd queue init failed\n");
4850 return ret;
4851 }
4852
4853 ret = hclge_get_cap(hdev);
4854 if (ret) {
4855 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
4856 ret);
4857 return ret;
4858 }
4859
4860 ret = hclge_configure(hdev);
4861 if (ret) {
4862 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
4863 return ret;
4864 }
4865
4866 ret = hclge_map_tqp(hdev);
4867 if (ret) {
4868 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
4869 return ret;
4870 }
4871
4872 ret = hclge_mac_init(hdev);
4873 if (ret) {
4874 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
4875 return ret;
4876 }
4877
4878 ret = hclge_buffer_alloc(hdev);
4879 if (ret) {
4880 dev_err(&pdev->dev, "Buffer allocate fail, ret =%d\n", ret);
4881 return ret;
4882 }
4883
4884 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
4885 if (ret) {
4886 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
4887 return ret;
4888 }
4889
4890 ret = hclge_init_vlan_config(hdev);
4891 if (ret) {
4892 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
4893 return ret;
4894 }
4895
4896 ret = hclge_tm_schd_init(hdev);
4897 if (ret) {
4898 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
4899 return ret;
4900 }
4901
4902 ret = hclge_rss_init_hw(hdev);
4903 if (ret) {
4904 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
4905 return ret;
4906 }
4907
4908 /* Enable MISC vector(vector0) */
4909 hclge_enable_vector(&hdev->misc_vector, true);
4910
4911 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
4912 HCLGE_DRIVER_NAME);
4913
4914 return 0;
4915}
4916
46a3df9f
S		 4917static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
4918{
4919 struct hclge_dev *hdev = ae_dev->priv;
4920 struct hclge_mac *mac = &hdev->hw.mac;
4921
4922 set_bit(HCLGE_STATE_DOWN, &hdev->state);
4923
2a32ca13
AB		 4924 if (IS_ENABLED(CONFIG_PCI_IOV))
4925 hclge_disable_sriov(hdev);
46a3df9f 4926
d039ef68 4927 if (hdev->service_timer.function)
46a3df9f
S		 4928 del_timer_sync(&hdev->service_timer);
4929 if (hdev->service_task.func)
4930 cancel_work_sync(&hdev->service_task);
4931
4932 if (mac->phydev)
4933 mdiobus_unregister(mac->mdio_bus);
4934
466b0c00
L		 4935 /* Disable MISC vector(vector0) */
4936 hclge_enable_vector(&hdev->misc_vector, false);
46a3df9f 4937 hclge_destroy_cmd_queue(&hdev->hw);
ca1d7669 4938 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 4939 hclge_pci_uninit(hdev);
4940 ae_dev->priv = NULL;
4941}
4942
4943static const struct hnae3_ae_ops hclge_ops = {
4944 .init_ae_dev = hclge_init_ae_dev,
4945 .uninit_ae_dev = hclge_uninit_ae_dev,
4946 .init_client_instance = hclge_init_client_instance,
4947 .uninit_client_instance = hclge_uninit_client_instance,
4948 .map_ring_to_vector = hclge_map_handle_ring_to_vector,
4949 .unmap_ring_from_vector = hclge_unmap_ring_from_vector,
4950 .get_vector = hclge_get_vector,
4951 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 4952 .set_loopback = hclge_set_loopback,
46a3df9f
S		 4953 .start = hclge_ae_start,
4954 .stop = hclge_ae_stop,
4955 .get_status = hclge_get_status,
4956 .get_ksettings_an_result = hclge_get_ksettings_an_result,
4957 .update_speed_duplex_h = hclge_update_speed_duplex_h,
4958 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
4959 .get_media_type = hclge_get_media_type,
4960 .get_rss_key_size = hclge_get_rss_key_size,
4961 .get_rss_indir_size = hclge_get_rss_indir_size,
4962 .get_rss = hclge_get_rss,
4963 .set_rss = hclge_set_rss,
f7db940a 4964 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 4965 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 4966 .get_tc_size = hclge_get_tc_size,
4967 .get_mac_addr = hclge_get_mac_addr,
4968 .set_mac_addr = hclge_set_mac_addr,
4969 .add_uc_addr = hclge_add_uc_addr,
4970 .rm_uc_addr = hclge_rm_uc_addr,
4971 .add_mc_addr = hclge_add_mc_addr,
4972 .rm_mc_addr = hclge_rm_mc_addr,
4973 .set_autoneg = hclge_set_autoneg,
4974 .get_autoneg = hclge_get_autoneg,
4975 .get_pauseparam = hclge_get_pauseparam,
4976 .set_mtu = hclge_set_mtu,
4977 .reset_queue = hclge_reset_tqp,
4978 .get_stats = hclge_get_stats,
4979 .update_stats = hclge_update_stats,
4980 .get_strings = hclge_get_strings,
4981 .get_sset_count = hclge_get_sset_count,
4982 .get_fw_version = hclge_get_fw_version,
4983 .get_mdix_mode = hclge_get_mdix_mode,
4984 .set_vlan_filter = hclge_set_port_vlan_filter,
4985 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
4ed340ab 4986 .reset_event = hclge_reset_event,
46a3df9f
S		 4987};
4988
4989static struct hnae3_ae_algo ae_algo = {
4990 .ops = &hclge_ops,
4991 .name = HCLGE_NAME,
4992 .pdev_id_table = ae_algo_pci_tbl,
4993};
4994
4995static int hclge_init(void)
4996{
4997 pr_info("%s is initializing\n", HCLGE_NAME);
4998
4999 return hnae3_register_ae_algo(&ae_algo);
5000}
5001
5002static void hclge_exit(void)
5003{
5004 hnae3_unregister_ae_algo(&ae_algo);
5005}
5006module_init(hclge_init);
5007module_exit(hclge_exit);
5008
5009MODULE_LICENSE("GPL");
5010MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
5011MODULE_DESCRIPTION("HCLGE Driver");
5012MODULE_VERSION(HCLGE_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)