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net: phy: remove states PHY_STARTING and PHY_PENDING
[linux-2.6-block.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_main.c
CommitLineData
d71d8381
JS		 1// SPDX-License-Identifier: GPL-2.0+
2// Copyright (c) 2016-2017 Hisilicon Limited.
46a3df9f
S		 3
4#include <linux/acpi.h>
5#include <linux/device.h>
6#include <linux/etherdevice.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/netdevice.h>
12#include <linux/pci.h>
13#include <linux/platform_device.h>
2866ccb2 14#include <linux/if_vlan.h>
f2f432f2 15#include <net/rtnetlink.h>
46a3df9f 16#include "hclge_cmd.h"
cacde272 17#include "hclge_dcb.h"
46a3df9f 18#include "hclge_main.h"
dde1a86e 19#include "hclge_mbx.h"
46a3df9f
S		 20#include "hclge_mdio.h"
21#include "hclge_tm.h"
5a9f0eac 22#include "hclge_err.h"
46a3df9f
S		 23#include "hnae3.h"
24
25#define HCLGE_NAME "hclge"
26#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
27#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
46a3df9f 28
f9fd82a9 29static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu);
46a3df9f 30static int hclge_init_vlan_config(struct hclge_dev *hdev);
4ed340ab 31static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev);
39932473
JS		 32static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
33 u16 *allocated_size, bool is_alloc);
46a3df9f
S		 34
35static struct hnae3_ae_algo ae_algo;
36
37static const struct pci_device_id ae_algo_pci_tbl[] = {
38 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
39 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
40 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
41 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
42 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
43 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
44 {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
e92a0843 45 /* required last entry */
46a3df9f
S		 46 {0, }
47};
48
2f550a46
YL		 49MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl);
50
46a3df9f 51static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
eb66d503 52 "App Loopback test",
4dc13b96
FL		 53 "Serdes serial Loopback test",
54 "Serdes parallel Loopback test",
46a3df9f
S		 55 "Phy Loopback test"
56};
57
46a3df9f
S		 58static const struct hclge_comm_stats_str g_mac_stats_string[] = {
59 {"mac_tx_mac_pause_num",
60 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
61 {"mac_rx_mac_pause_num",
62 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
63 {"mac_tx_pfc_pri0_pkt_num",
64 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
65 {"mac_tx_pfc_pri1_pkt_num",
66 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
67 {"mac_tx_pfc_pri2_pkt_num",
68 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
69 {"mac_tx_pfc_pri3_pkt_num",
70 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
71 {"mac_tx_pfc_pri4_pkt_num",
72 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
73 {"mac_tx_pfc_pri5_pkt_num",
74 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
75 {"mac_tx_pfc_pri6_pkt_num",
76 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
77 {"mac_tx_pfc_pri7_pkt_num",
78 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
79 {"mac_rx_pfc_pri0_pkt_num",
80 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
81 {"mac_rx_pfc_pri1_pkt_num",
82 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
83 {"mac_rx_pfc_pri2_pkt_num",
84 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
85 {"mac_rx_pfc_pri3_pkt_num",
86 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
87 {"mac_rx_pfc_pri4_pkt_num",
88 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
89 {"mac_rx_pfc_pri5_pkt_num",
90 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
91 {"mac_rx_pfc_pri6_pkt_num",
92 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
93 {"mac_rx_pfc_pri7_pkt_num",
94 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
95 {"mac_tx_total_pkt_num",
96 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
97 {"mac_tx_total_oct_num",
98 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
99 {"mac_tx_good_pkt_num",
100 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
101 {"mac_tx_bad_pkt_num",
102 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
103 {"mac_tx_good_oct_num",
104 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
105 {"mac_tx_bad_oct_num",
106 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
107 {"mac_tx_uni_pkt_num",
108 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
109 {"mac_tx_multi_pkt_num",
110 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
111 {"mac_tx_broad_pkt_num",
112 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
113 {"mac_tx_undersize_pkt_num",
114 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
200a88c6
JS		 115 {"mac_tx_oversize_pkt_num",
116 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)},
46a3df9f
S		 117 {"mac_tx_64_oct_pkt_num",
118 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
119 {"mac_tx_65_127_oct_pkt_num",
120 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
121 {"mac_tx_128_255_oct_pkt_num",
122 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
123 {"mac_tx_256_511_oct_pkt_num",
124 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
125 {"mac_tx_512_1023_oct_pkt_num",
126 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
127 {"mac_tx_1024_1518_oct_pkt_num",
128 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
91f384f6
JS		 129 {"mac_tx_1519_2047_oct_pkt_num",
130 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)},
131 {"mac_tx_2048_4095_oct_pkt_num",
132 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)},
133 {"mac_tx_4096_8191_oct_pkt_num",
134 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)},
91f384f6
JS		 135 {"mac_tx_8192_9216_oct_pkt_num",
136 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)},
137 {"mac_tx_9217_12287_oct_pkt_num",
138 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)},
139 {"mac_tx_12288_16383_oct_pkt_num",
140 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)},
141 {"mac_tx_1519_max_good_pkt_num",
142 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)},
143 {"mac_tx_1519_max_bad_pkt_num",
144 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)},
46a3df9f
S		 145 {"mac_rx_total_pkt_num",
146 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
147 {"mac_rx_total_oct_num",
148 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
149 {"mac_rx_good_pkt_num",
150 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
151 {"mac_rx_bad_pkt_num",
152 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
153 {"mac_rx_good_oct_num",
154 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
155 {"mac_rx_bad_oct_num",
156 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
157 {"mac_rx_uni_pkt_num",
158 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
159 {"mac_rx_multi_pkt_num",
160 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
161 {"mac_rx_broad_pkt_num",
162 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
163 {"mac_rx_undersize_pkt_num",
164 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
200a88c6
JS		 165 {"mac_rx_oversize_pkt_num",
166 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)},
46a3df9f
S		 167 {"mac_rx_64_oct_pkt_num",
168 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
169 {"mac_rx_65_127_oct_pkt_num",
170 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
171 {"mac_rx_128_255_oct_pkt_num",
172 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
173 {"mac_rx_256_511_oct_pkt_num",
174 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
175 {"mac_rx_512_1023_oct_pkt_num",
176 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
177 {"mac_rx_1024_1518_oct_pkt_num",
178 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
91f384f6
JS		 179 {"mac_rx_1519_2047_oct_pkt_num",
180 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)},
181 {"mac_rx_2048_4095_oct_pkt_num",
182 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)},
183 {"mac_rx_4096_8191_oct_pkt_num",
184 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)},
91f384f6
JS		 185 {"mac_rx_8192_9216_oct_pkt_num",
186 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)},
187 {"mac_rx_9217_12287_oct_pkt_num",
188 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)},
189 {"mac_rx_12288_16383_oct_pkt_num",
190 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)},
191 {"mac_rx_1519_max_good_pkt_num",
192 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)},
193 {"mac_rx_1519_max_bad_pkt_num",
194 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)},
46a3df9f 195
a6c51c26
JS		 196 {"mac_tx_fragment_pkt_num",
197 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)},
198 {"mac_tx_undermin_pkt_num",
199 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)},
200 {"mac_tx_jabber_pkt_num",
201 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)},
202 {"mac_tx_err_all_pkt_num",
203 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)},
204 {"mac_tx_from_app_good_pkt_num",
205 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)},
206 {"mac_tx_from_app_bad_pkt_num",
207 HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)},
208 {"mac_rx_fragment_pkt_num",
209 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)},
210 {"mac_rx_undermin_pkt_num",
211 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)},
212 {"mac_rx_jabber_pkt_num",
213 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)},
214 {"mac_rx_fcs_err_pkt_num",
215 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)},
216 {"mac_rx_send_app_good_pkt_num",
217 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)},
218 {"mac_rx_send_app_bad_pkt_num",
219 HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)}
46a3df9f
S		 220};
221
f5aac71c
FL		 222static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = {
223 {
224 .flags = HCLGE_MAC_MGR_MASK_VLAN_B,
225 .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP),
226 .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)),
227 .mac_addr_lo16 = cpu_to_le16(htons(0x000E)),
228 .i_port_bitmap = 0x1,
229 },
230};
231
46a3df9f
S		 232static int hclge_mac_update_stats(struct hclge_dev *hdev)
233{
91f384f6 234#define HCLGE_MAC_CMD_NUM 21
46a3df9f
S		 235#define HCLGE_RTN_DATA_NUM 4
236
237 u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
238 struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
a90bb9a5 239 __le64 *desc_data;
46a3df9f
S		 240 int i, k, n;
241 int ret;
242
243 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
244 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
245 if (ret) {
246 dev_err(&hdev->pdev->dev,
247 "Get MAC pkt stats fail, status = %d.\n", ret);
248
249 return ret;
250 }
251
252 for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
253 if (unlikely(i == 0)) {
a90bb9a5 254 desc_data = (__le64 *)(&desc[i].data[0]);
46a3df9f
S		 255 n = HCLGE_RTN_DATA_NUM - 2;
256 } else {
a90bb9a5 257 desc_data = (__le64 *)(&desc[i]);
46a3df9f
S		 258 n = HCLGE_RTN_DATA_NUM;
259 }
260 for (k = 0; k < n; k++) {
a90bb9a5 261 *data++ += le64_to_cpu(*desc_data);
46a3df9f
S		 262 desc_data++;
263 }
264 }
265
266 return 0;
267}
268
269static int hclge_tqps_update_stats(struct hnae3_handle *handle)
270{
271 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
272 struct hclge_vport *vport = hclge_get_vport(handle);
273 struct hclge_dev *hdev = vport->back;
274 struct hnae3_queue *queue;
275 struct hclge_desc desc[1];
276 struct hclge_tqp *tqp;
277 int ret, i;
278
279 for (i = 0; i < kinfo->num_tqps; i++) {
280 queue = handle->kinfo.tqp[i];
281 tqp = container_of(queue, struct hclge_tqp, q);
282 /* command : HCLGE_OPC_QUERY_IGU_STAT */
283 hclge_cmd_setup_basic_desc(&desc[0],
284 HCLGE_OPC_QUERY_RX_STATUS,
285 true);
286
a90bb9a5 287 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 288 ret = hclge_cmd_send(&hdev->hw, desc, 1);
289 if (ret) {
290 dev_err(&hdev->pdev->dev,
291 "Query tqp stat fail, status = %d,queue = %d\n",
292 ret, i);
293 return ret;
294 }
295 tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
cf72fa63 296 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 297 }
298
299 for (i = 0; i < kinfo->num_tqps; i++) {
300 queue = handle->kinfo.tqp[i];
301 tqp = container_of(queue, struct hclge_tqp, q);
302 /* command : HCLGE_OPC_QUERY_IGU_STAT */
303 hclge_cmd_setup_basic_desc(&desc[0],
304 HCLGE_OPC_QUERY_TX_STATUS,
305 true);
306
a90bb9a5 307 desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff));
46a3df9f
S		 308 ret = hclge_cmd_send(&hdev->hw, desc, 1);
309 if (ret) {
310 dev_err(&hdev->pdev->dev,
311 "Query tqp stat fail, status = %d,queue = %d\n",
312 ret, i);
313 return ret;
314 }
315 tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
cf72fa63 316 le32_to_cpu(desc[0].data[1]);
46a3df9f
S		 317 }
318
319 return 0;
320}
321
322static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
323{
324 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
325 struct hclge_tqp *tqp;
326 u64 *buff = data;
327 int i;
328
329 for (i = 0; i < kinfo->num_tqps; i++) {
330 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 331 *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd;
46a3df9f
S		 332 }
333
334 for (i = 0; i < kinfo->num_tqps; i++) {
335 tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
a90bb9a5 336 *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd;
46a3df9f
S		 337 }
338
339 return buff;
340}
341
342static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
343{
344 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
345
346 return kinfo->num_tqps * (2);
347}
348
349static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
350{
351 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
352 u8 *buff = data;
353 int i = 0;
354
355 for (i = 0; i < kinfo->num_tqps; i++) {
356 struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
357 struct hclge_tqp, q);
0c218123 358 snprintf(buff, ETH_GSTRING_LEN, "txq%d_pktnum_rcd",
46a3df9f
S		 359 tqp->index);
360 buff = buff + ETH_GSTRING_LEN;
361 }
362
363 for (i = 0; i < kinfo->num_tqps; i++) {
364 struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
365 struct hclge_tqp, q);
0c218123 366 snprintf(buff, ETH_GSTRING_LEN, "rxq%d_pktnum_rcd",
46a3df9f
S		 367 tqp->index);
368 buff = buff + ETH_GSTRING_LEN;
369 }
370
371 return buff;
372}
373
374static u64 *hclge_comm_get_stats(void *comm_stats,
375 const struct hclge_comm_stats_str strs[],
376 int size, u64 *data)
377{
378 u64 *buf = data;
379 u32 i;
380
381 for (i = 0; i < size; i++)
382 buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
383
384 return buf + size;
385}
386
387static u8 *hclge_comm_get_strings(u32 stringset,
388 const struct hclge_comm_stats_str strs[],
389 int size, u8 *data)
390{
391 char *buff = (char *)data;
392 u32 i;
393
394 if (stringset != ETH_SS_STATS)
395 return buff;
396
397 for (i = 0; i < size; i++) {
398 snprintf(buff, ETH_GSTRING_LEN,
399 strs[i].desc);
400 buff = buff + ETH_GSTRING_LEN;
401 }
402
403 return (u8 *)buff;
404}
405
406static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
407 struct net_device_stats *net_stats)
408{
409 net_stats->tx_dropped = 0;
200a88c6 410 net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 411 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
a6c51c26 412 net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 413
414 net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
415 net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
416
a6c51c26 417 net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num;
46a3df9f
S		 418 net_stats->rx_length_errors =
419 hw_stats->mac_stats.mac_rx_undersize_pkt_num;
420 net_stats->rx_length_errors +=
200a88c6 421 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f 422 net_stats->rx_over_errors =
200a88c6 423 hw_stats->mac_stats.mac_rx_oversize_pkt_num;
46a3df9f
S		 424}
425
426static void hclge_update_stats_for_all(struct hclge_dev *hdev)
427{
428 struct hnae3_handle *handle;
429 int status;
430
431 handle = &hdev->vport[0].nic;
432 if (handle->client) {
433 status = hclge_tqps_update_stats(handle);
434 if (status) {
435 dev_err(&hdev->pdev->dev,
436 "Update TQPS stats fail, status = %d.\n",
437 status);
438 }
439 }
440
441 status = hclge_mac_update_stats(hdev);
442 if (status)
443 dev_err(&hdev->pdev->dev,
444 "Update MAC stats fail, status = %d.\n", status);
445
46a3df9f
S		 446 hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
447}
448
449static void hclge_update_stats(struct hnae3_handle *handle,
450 struct net_device_stats *net_stats)
451{
452 struct hclge_vport *vport = hclge_get_vport(handle);
453 struct hclge_dev *hdev = vport->back;
454 struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
455 int status;
456
c5f65480
JS		 457 if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state))
458 return;
459
46a3df9f
S		 460 status = hclge_mac_update_stats(hdev);
461 if (status)
462 dev_err(&hdev->pdev->dev,
463 "Update MAC stats fail, status = %d.\n",
464 status);
465
46a3df9f
S		 466 status = hclge_tqps_update_stats(handle);
467 if (status)
468 dev_err(&hdev->pdev->dev,
469 "Update TQPS stats fail, status = %d.\n",
470 status);
471
472 hclge_update_netstat(hw_stats, net_stats);
c5f65480
JS		 473
474 clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state);
46a3df9f
S		 475}
476
477static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
478{
4dc13b96
FL		 479#define HCLGE_LOOPBACK_TEST_FLAGS (HNAE3_SUPPORT_APP_LOOPBACK |\
480 HNAE3_SUPPORT_PHY_LOOPBACK |\
481 HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK |\
482 HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK)
46a3df9f
S		 483
484 struct hclge_vport *vport = hclge_get_vport(handle);
485 struct hclge_dev *hdev = vport->back;
486 int count = 0;
487
488 /* Loopback test support rules:
489 * mac: only GE mode support
490 * serdes: all mac mode will support include GE/XGE/LGE/CGE
491 * phy: only support when phy device exist on board
492 */
493 if (stringset == ETH_SS_TEST) {
494 /* clear loopback bit flags at first */
495 handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
3ff6cde8 496 if (hdev->pdev->revision >= 0x21 ||
4dc13b96 497 hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
46a3df9f
S		 498 hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
499 hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
500 count += 1;
eb66d503 501 handle->flags |= HNAE3_SUPPORT_APP_LOOPBACK;
46a3df9f 502 }
5fd50ac3 503
4dc13b96
FL		 504 count += 2;
505 handle->flags |= HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK;
506 handle->flags |= HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK;
46a3df9f
S		 507 } else if (stringset == ETH_SS_STATS) {
508 count = ARRAY_SIZE(g_mac_stats_string) +
46a3df9f
S		 509 hclge_tqps_get_sset_count(handle, stringset);
510 }
511
512 return count;
513}
514
515static void hclge_get_strings(struct hnae3_handle *handle,
516 u32 stringset,
517 u8 *data)
518{
519 u8 *p = (char *)data;
520 int size;
521
522 if (stringset == ETH_SS_STATS) {
523 size = ARRAY_SIZE(g_mac_stats_string);
524 p = hclge_comm_get_strings(stringset,
525 g_mac_stats_string,
526 size,
527 p);
46a3df9f
S		 528 p = hclge_tqps_get_strings(handle, p);
529 } else if (stringset == ETH_SS_TEST) {
eb66d503 530 if (handle->flags & HNAE3_SUPPORT_APP_LOOPBACK) {
46a3df9f 531 memcpy(p,
eb66d503 532 hns3_nic_test_strs[HNAE3_LOOP_APP],
46a3df9f
S		 533 ETH_GSTRING_LEN);
534 p += ETH_GSTRING_LEN;
535 }
4dc13b96 536 if (handle->flags & HNAE3_SUPPORT_SERDES_SERIAL_LOOPBACK) {
46a3df9f 537 memcpy(p,
4dc13b96
FL		 538 hns3_nic_test_strs[HNAE3_LOOP_SERIAL_SERDES],
539 ETH_GSTRING_LEN);
540 p += ETH_GSTRING_LEN;
541 }
542 if (handle->flags & HNAE3_SUPPORT_SERDES_PARALLEL_LOOPBACK) {
543 memcpy(p,
544 hns3_nic_test_strs[HNAE3_LOOP_PARALLEL_SERDES],
46a3df9f
S		 545 ETH_GSTRING_LEN);
546 p += ETH_GSTRING_LEN;
547 }
548 if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
549 memcpy(p,
a7b687b3 550 hns3_nic_test_strs[HNAE3_LOOP_PHY],
46a3df9f
S		 551 ETH_GSTRING_LEN);
552 p += ETH_GSTRING_LEN;
553 }
554 }
555}
556
557static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
558{
559 struct hclge_vport *vport = hclge_get_vport(handle);
560 struct hclge_dev *hdev = vport->back;
561 u64 *p;
562
563 p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
564 g_mac_stats_string,
565 ARRAY_SIZE(g_mac_stats_string),
566 data);
46a3df9f
S		 567 p = hclge_tqps_get_stats(handle, p);
568}
569
570static int hclge_parse_func_status(struct hclge_dev *hdev,
d44f9b63 571 struct hclge_func_status_cmd *status)
46a3df9f
S		 572{
573 if (!(status->pf_state & HCLGE_PF_STATE_DONE))
574 return -EINVAL;
575
576 /* Set the pf to main pf */
577 if (status->pf_state & HCLGE_PF_STATE_MAIN)
578 hdev->flag |= HCLGE_FLAG_MAIN;
579 else
580 hdev->flag &= ~HCLGE_FLAG_MAIN;
581
46a3df9f
S		 582 return 0;
583}
584
585static int hclge_query_function_status(struct hclge_dev *hdev)
586{
d44f9b63 587 struct hclge_func_status_cmd *req;
46a3df9f
S		 588 struct hclge_desc desc;
589 int timeout = 0;
590 int ret;
591
592 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
d44f9b63 593 req = (struct hclge_func_status_cmd *)desc.data;
46a3df9f
S		 594
595 do {
596 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
597 if (ret) {
598 dev_err(&hdev->pdev->dev,
599 "query function status failed %d.\n",
600 ret);
601
602 return ret;
603 }
604
605 /* Check pf reset is done */
606 if (req->pf_state)
607 break;
608 usleep_range(1000, 2000);
609 } while (timeout++ < 5);
610
611 ret = hclge_parse_func_status(hdev, req);
612
613 return ret;
614}
615
616static int hclge_query_pf_resource(struct hclge_dev *hdev)
617{
d44f9b63 618 struct hclge_pf_res_cmd *req;
46a3df9f
S		 619 struct hclge_desc desc;
620 int ret;
621
622 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
623 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
624 if (ret) {
625 dev_err(&hdev->pdev->dev,
626 "query pf resource failed %d.\n", ret);
627 return ret;
628 }
629
d44f9b63 630 req = (struct hclge_pf_res_cmd *)desc.data;
46a3df9f
S		 631 hdev->num_tqps = __le16_to_cpu(req->tqp_num);
632 hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
633
e92a0843 634 if (hnae3_dev_roce_supported(hdev)) {
375dd5e4
JS		 635 hdev->roce_base_msix_offset =
636 hnae3_get_field(__le16_to_cpu(req->msixcap_localid_ba_rocee),
637 HCLGE_MSIX_OFT_ROCEE_M, HCLGE_MSIX_OFT_ROCEE_S);
887c3820 638 hdev->num_roce_msi =
e4e87715
PL		 639 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
640 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 641
642 /* PF should have NIC vectors and Roce vectors,
643 * NIC vectors are queued before Roce vectors.
644 */
375dd5e4
JS		 645 hdev->num_msi = hdev->num_roce_msi +
646 hdev->roce_base_msix_offset;
46a3df9f
S		 647 } else {
648 hdev->num_msi =
e4e87715
PL		 649 hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number),
650 HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
46a3df9f
S		 651 }
652
653 return 0;
654}
655
656static int hclge_parse_speed(int speed_cmd, int *speed)
657{
658 switch (speed_cmd) {
659 case 6:
660 *speed = HCLGE_MAC_SPEED_10M;
661 break;
662 case 7:
663 *speed = HCLGE_MAC_SPEED_100M;
664 break;
665 case 0:
666 *speed = HCLGE_MAC_SPEED_1G;
667 break;
668 case 1:
669 *speed = HCLGE_MAC_SPEED_10G;
670 break;
671 case 2:
672 *speed = HCLGE_MAC_SPEED_25G;
673 break;
674 case 3:
675 *speed = HCLGE_MAC_SPEED_40G;
676 break;
677 case 4:
678 *speed = HCLGE_MAC_SPEED_50G;
679 break;
680 case 5:
681 *speed = HCLGE_MAC_SPEED_100G;
682 break;
683 default:
684 return -EINVAL;
685 }
686
687 return 0;
688}
689
0979aa0b
FL		 690static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev,
691 u8 speed_ability)
692{
693 unsigned long *supported = hdev->hw.mac.supported;
694
695 if (speed_ability & HCLGE_SUPPORT_1G_BIT)
696 set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
697 supported);
698
699 if (speed_ability & HCLGE_SUPPORT_10G_BIT)
700 set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
701 supported);
702
703 if (speed_ability & HCLGE_SUPPORT_25G_BIT)
704 set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT,
705 supported);
706
707 if (speed_ability & HCLGE_SUPPORT_50G_BIT)
708 set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT,
709 supported);
710
711 if (speed_ability & HCLGE_SUPPORT_100G_BIT)
712 set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT,
713 supported);
714
715 set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported);
716 set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported);
717}
718
719static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability)
720{
721 u8 media_type = hdev->hw.mac.media_type;
722
723 if (media_type != HNAE3_MEDIA_TYPE_FIBER)
724 return;
725
726 hclge_parse_fiber_link_mode(hdev, speed_ability);
727}
728
46a3df9f
S		 729static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
730{
d44f9b63 731 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 732 u64 mac_addr_tmp_high;
733 u64 mac_addr_tmp;
734 int i;
735
d44f9b63 736 req = (struct hclge_cfg_param_cmd *)desc[0].data;
46a3df9f
S		 737
738 /* get the configuration */
e4e87715
PL		 739 cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
740 HCLGE_CFG_VMDQ_M,
741 HCLGE_CFG_VMDQ_S);
742 cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
743 HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
744 cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]),
745 HCLGE_CFG_TQP_DESC_N_M,
746 HCLGE_CFG_TQP_DESC_N_S);
747
748 cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]),
749 HCLGE_CFG_PHY_ADDR_M,
750 HCLGE_CFG_PHY_ADDR_S);
751 cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]),
752 HCLGE_CFG_MEDIA_TP_M,
753 HCLGE_CFG_MEDIA_TP_S);
754 cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]),
755 HCLGE_CFG_RX_BUF_LEN_M,
756 HCLGE_CFG_RX_BUF_LEN_S);
46a3df9f
S		 757 /* get mac_address */
758 mac_addr_tmp = __le32_to_cpu(req->param[2]);
e4e87715
PL		 759 mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]),
760 HCLGE_CFG_MAC_ADDR_H_M,
761 HCLGE_CFG_MAC_ADDR_H_S);
46a3df9f
S		 762
763 mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
764
e4e87715
PL		 765 cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]),
766 HCLGE_CFG_DEFAULT_SPEED_M,
767 HCLGE_CFG_DEFAULT_SPEED_S);
768 cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]),
769 HCLGE_CFG_RSS_SIZE_M,
770 HCLGE_CFG_RSS_SIZE_S);
0e7a40cd 771
46a3df9f
S		 772 for (i = 0; i < ETH_ALEN; i++)
773 cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
774
d44f9b63 775 req = (struct hclge_cfg_param_cmd *)desc[1].data;
46a3df9f 776 cfg->numa_node_map = __le32_to_cpu(req->param[0]);
0979aa0b 777
e4e87715
PL		 778 cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]),
779 HCLGE_CFG_SPEED_ABILITY_M,
780 HCLGE_CFG_SPEED_ABILITY_S);
39932473
JS		 781 cfg->umv_space = hnae3_get_field(__le32_to_cpu(req->param[1]),
782 HCLGE_CFG_UMV_TBL_SPACE_M,
783 HCLGE_CFG_UMV_TBL_SPACE_S);
784 if (!cfg->umv_space)
785 cfg->umv_space = HCLGE_DEFAULT_UMV_SPACE_PER_PF;
46a3df9f
S		 786}
787
788/* hclge_get_cfg: query the static parameter from flash
789 * @hdev: pointer to struct hclge_dev
790 * @hcfg: the config structure to be getted
791 */
792static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
793{
794 struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
d44f9b63 795 struct hclge_cfg_param_cmd *req;
46a3df9f
S		 796 int i, ret;
797
798 for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
a90bb9a5
YL		 799 u32 offset = 0;
800
d44f9b63 801 req = (struct hclge_cfg_param_cmd *)desc[i].data;
46a3df9f
S		 802 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
803 true);
e4e87715
PL		 804 hnae3_set_field(offset, HCLGE_CFG_OFFSET_M,
805 HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
46a3df9f 806 /* Len should be united by 4 bytes when send to hardware */
e4e87715
PL		 807 hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S,
808 HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
a90bb9a5 809 req->offset = cpu_to_le32(offset);
46a3df9f
S		 810 }
811
812 ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
813 if (ret) {
3f639907 814 dev_err(&hdev->pdev->dev, "get config failed %d.\n", ret);
46a3df9f
S		 815 return ret;
816 }
817
818 hclge_parse_cfg(hcfg, desc);
3f639907 819
46a3df9f
S		 820 return 0;
821}
822
823static int hclge_get_cap(struct hclge_dev *hdev)
824{
825 int ret;
826
827 ret = hclge_query_function_status(hdev);
828 if (ret) {
829 dev_err(&hdev->pdev->dev,
830 "query function status error %d.\n", ret);
831 return ret;
832 }
833
834 /* get pf resource */
835 ret = hclge_query_pf_resource(hdev);
3f639907
JS		 836 if (ret)
837 dev_err(&hdev->pdev->dev, "query pf resource error %d.\n", ret);
46a3df9f 838
3f639907 839 return ret;
46a3df9f
S		 840}
841
842static int hclge_configure(struct hclge_dev *hdev)
843{
844 struct hclge_cfg cfg;
845 int ret, i;
846
847 ret = hclge_get_cfg(hdev, &cfg);
848 if (ret) {
849 dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
850 return ret;
851 }
852
853 hdev->num_vmdq_vport = cfg.vmdq_vport_num;
854 hdev->base_tqp_pid = 0;
0e7a40cd 855 hdev->rss_size_max = cfg.rss_size_max;
46a3df9f 856 hdev->rx_buf_len = cfg.rx_buf_len;
fbbb1536 857 ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
46a3df9f 858 hdev->hw.mac.media_type = cfg.media_type;
2a4776e1 859 hdev->hw.mac.phy_addr = cfg.phy_addr;
46a3df9f
S		 860 hdev->num_desc = cfg.tqp_desc_num;
861 hdev->tm_info.num_pg = 1;
cacde272 862 hdev->tc_max = cfg.tc_num;
46a3df9f 863 hdev->tm_info.hw_pfc_map = 0;
39932473 864 hdev->wanted_umv_size = cfg.umv_space;
46a3df9f
S		 865
866 ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
867 if (ret) {
868 dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
869 return ret;
870 }
871
0979aa0b
FL		 872 hclge_parse_link_mode(hdev, cfg.speed_ability);
873
cacde272
YL		 874 if ((hdev->tc_max > HNAE3_MAX_TC) ||
875 (hdev->tc_max < 1)) {
46a3df9f 876 dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
cacde272
YL		 877 hdev->tc_max);
878 hdev->tc_max = 1;
46a3df9f
S		 879 }
880
cacde272
YL		 881 /* Dev does not support DCB */
882 if (!hnae3_dev_dcb_supported(hdev)) {
883 hdev->tc_max = 1;
884 hdev->pfc_max = 0;
885 } else {
886 hdev->pfc_max = hdev->tc_max;
887 }
888
889 hdev->tm_info.num_tc = hdev->tc_max;
890
46a3df9f 891 /* Currently not support uncontiuous tc */
cacde272 892 for (i = 0; i < hdev->tm_info.num_tc; i++)
e4e87715 893 hnae3_set_bit(hdev->hw_tc_map, i, 1);
46a3df9f 894
71b83869 895 hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
46a3df9f
S		 896
897 return ret;
898}
899
900static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
901 int tso_mss_max)
902{
d44f9b63 903 struct hclge_cfg_tso_status_cmd *req;
46a3df9f 904 struct hclge_desc desc;
a90bb9a5 905 u16 tso_mss;
46a3df9f
S		 906
907 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
908
d44f9b63 909 req = (struct hclge_cfg_tso_status_cmd *)desc.data;
a90bb9a5
YL		 910
911 tso_mss = 0;
e4e87715
PL		 912 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
913 HCLGE_TSO_MSS_MIN_S, tso_mss_min);
a90bb9a5
YL		 914 req->tso_mss_min = cpu_to_le16(tso_mss);
915
916 tso_mss = 0;
e4e87715
PL		 917 hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M,
918 HCLGE_TSO_MSS_MIN_S, tso_mss_max);
a90bb9a5 919 req->tso_mss_max = cpu_to_le16(tso_mss);
46a3df9f
S		 920
921 return hclge_cmd_send(&hdev->hw, &desc, 1);
922}
923
924static int hclge_alloc_tqps(struct hclge_dev *hdev)
925{
926 struct hclge_tqp *tqp;
927 int i;
928
929 hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
930 sizeof(struct hclge_tqp), GFP_KERNEL);
931 if (!hdev->htqp)
932 return -ENOMEM;
933
934 tqp = hdev->htqp;
935
936 for (i = 0; i < hdev->num_tqps; i++) {
937 tqp->dev = &hdev->pdev->dev;
938 tqp->index = i;
939
940 tqp->q.ae_algo = &ae_algo;
941 tqp->q.buf_size = hdev->rx_buf_len;
942 tqp->q.desc_num = hdev->num_desc;
943 tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
944 i * HCLGE_TQP_REG_SIZE;
945
946 tqp++;
947 }
948
949 return 0;
950}
951
952static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
953 u16 tqp_pid, u16 tqp_vid, bool is_pf)
954{
d44f9b63 955 struct hclge_tqp_map_cmd *req;
46a3df9f
S		 956 struct hclge_desc desc;
957 int ret;
958
959 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
960
d44f9b63 961 req = (struct hclge_tqp_map_cmd *)desc.data;
46a3df9f 962 req->tqp_id = cpu_to_le16(tqp_pid);
a90bb9a5 963 req->tqp_vf = func_id;
46a3df9f
S		 964 req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
965 1 << HCLGE_TQP_MAP_EN_B;
966 req->tqp_vid = cpu_to_le16(tqp_vid);
967
968 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907
JS		 969 if (ret)
970 dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", ret);
46a3df9f 971
3f639907 972 return ret;
46a3df9f
S		 973}
974
128b900d 975static int hclge_assign_tqp(struct hclge_vport *vport)
46a3df9f 976{
128b900d 977 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
46a3df9f 978 struct hclge_dev *hdev = vport->back;
7df7dad6 979 int i, alloced;
46a3df9f
S		 980
981 for (i = 0, alloced = 0; i < hdev->num_tqps &&
128b900d 982 alloced < kinfo->num_tqps; i++) {
46a3df9f
S		 983 if (!hdev->htqp[i].alloced) {
984 hdev->htqp[i].q.handle = &vport->nic;
985 hdev->htqp[i].q.tqp_index = alloced;
128b900d
YL		 986 hdev->htqp[i].q.desc_num = kinfo->num_desc;
987 kinfo->tqp[alloced] = &hdev->htqp[i].q;
46a3df9f 988 hdev->htqp[i].alloced = true;
46a3df9f
S		 989 alloced++;
990 }
991 }
128b900d 992 vport->alloc_tqps = kinfo->num_tqps;
46a3df9f
S		 993
994 return 0;
995}
996
128b900d
YL		 997static int hclge_knic_setup(struct hclge_vport *vport,
998 u16 num_tqps, u16 num_desc)
46a3df9f
S		 999{
1000 struct hnae3_handle *nic = &vport->nic;
1001 struct hnae3_knic_private_info *kinfo = &nic->kinfo;
1002 struct hclge_dev *hdev = vport->back;
1003 int i, ret;
1004
128b900d 1005 kinfo->num_desc = num_desc;
46a3df9f
S		 1006 kinfo->rx_buf_len = hdev->rx_buf_len;
1007 kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
1008 kinfo->rss_size
1009 = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
1010 kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
1011
1012 for (i = 0; i < HNAE3_MAX_TC; i++) {
1013 if (hdev->hw_tc_map & BIT(i)) {
1014 kinfo->tc_info[i].enable = true;
1015 kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
1016 kinfo->tc_info[i].tqp_count = kinfo->rss_size;
1017 kinfo->tc_info[i].tc = i;
1018 } else {
1019 /* Set to default queue if TC is disable */
1020 kinfo->tc_info[i].enable = false;
1021 kinfo->tc_info[i].tqp_offset = 0;
1022 kinfo->tc_info[i].tqp_count = 1;
1023 kinfo->tc_info[i].tc = 0;
1024 }
1025 }
1026
1027 kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
1028 sizeof(struct hnae3_queue *), GFP_KERNEL);
1029 if (!kinfo->tqp)
1030 return -ENOMEM;
1031
128b900d 1032 ret = hclge_assign_tqp(vport);
3f639907 1033 if (ret)
46a3df9f 1034 dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
46a3df9f 1035
3f639907 1036 return ret;
46a3df9f
S		 1037}
1038
7df7dad6
L		 1039static int hclge_map_tqp_to_vport(struct hclge_dev *hdev,
1040 struct hclge_vport *vport)
1041{
1042 struct hnae3_handle *nic = &vport->nic;
1043 struct hnae3_knic_private_info *kinfo;
1044 u16 i;
1045
1046 kinfo = &nic->kinfo;
1047 for (i = 0; i < kinfo->num_tqps; i++) {
1048 struct hclge_tqp *q =
1049 container_of(kinfo->tqp[i], struct hclge_tqp, q);
1050 bool is_pf;
1051 int ret;
1052
1053 is_pf = !(vport->vport_id);
1054 ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index,
1055 i, is_pf);
1056 if (ret)
1057 return ret;
1058 }
1059
1060 return 0;
1061}
1062
1063static int hclge_map_tqp(struct hclge_dev *hdev)
1064{
1065 struct hclge_vport *vport = hdev->vport;
1066 u16 i, num_vport;
1067
1068 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1069 for (i = 0; i < num_vport; i++) {
1070 int ret;
1071
1072 ret = hclge_map_tqp_to_vport(hdev, vport);
1073 if (ret)
1074 return ret;
1075
1076 vport++;
1077 }
1078
1079 return 0;
1080}
1081
46a3df9f
S		 1082static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
1083{
1084 /* this would be initialized later */
1085}
1086
1087static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
1088{
1089 struct hnae3_handle *nic = &vport->nic;
1090 struct hclge_dev *hdev = vport->back;
1091 int ret;
1092
1093 nic->pdev = hdev->pdev;
1094 nic->ae_algo = &ae_algo;
1095 nic->numa_node_mask = hdev->numa_node_mask;
1096
1097 if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
128b900d 1098 ret = hclge_knic_setup(vport, num_tqps, hdev->num_desc);
46a3df9f
S		 1099 if (ret) {
1100 dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
1101 ret);
1102 return ret;
1103 }
1104 } else {
1105 hclge_unic_setup(vport, num_tqps);
1106 }
1107
1108 return 0;
1109}
1110
1111static int hclge_alloc_vport(struct hclge_dev *hdev)
1112{
1113 struct pci_dev *pdev = hdev->pdev;
1114 struct hclge_vport *vport;
1115 u32 tqp_main_vport;
1116 u32 tqp_per_vport;
1117 int num_vport, i;
1118 int ret;
1119
1120 /* We need to alloc a vport for main NIC of PF */
1121 num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
1122
38e62046
HT		 1123 if (hdev->num_tqps < num_vport) {
1124 dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)",
1125 hdev->num_tqps, num_vport);
1126 return -EINVAL;
1127 }
46a3df9f
S		 1128
1129 /* Alloc the same number of TQPs for every vport */
1130 tqp_per_vport = hdev->num_tqps / num_vport;
1131 tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
1132
1133 vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
1134 GFP_KERNEL);
1135 if (!vport)
1136 return -ENOMEM;
1137
1138 hdev->vport = vport;
1139 hdev->num_alloc_vport = num_vport;
1140
2312e050
FL		 1141 if (IS_ENABLED(CONFIG_PCI_IOV))
1142 hdev->num_alloc_vfs = hdev->num_req_vfs;
46a3df9f
S		 1143
1144 for (i = 0; i < num_vport; i++) {
1145 vport->back = hdev;
1146 vport->vport_id = i;
1147
1148 if (i == 0)
1149 ret = hclge_vport_setup(vport, tqp_main_vport);
1150 else
1151 ret = hclge_vport_setup(vport, tqp_per_vport);
1152 if (ret) {
1153 dev_err(&pdev->dev,
1154 "vport setup failed for vport %d, %d\n",
1155 i, ret);
1156 return ret;
1157 }
1158
1159 vport++;
1160 }
1161
1162 return 0;
1163}
1164
acf61ecd
YL		 1165static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev,
1166 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1167{
1168/* TX buffer size is unit by 128 byte */
1169#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
1170#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
d44f9b63 1171 struct hclge_tx_buff_alloc_cmd *req;
46a3df9f
S		 1172 struct hclge_desc desc;
1173 int ret;
1174 u8 i;
1175
d44f9b63 1176 req = (struct hclge_tx_buff_alloc_cmd *)desc.data;
46a3df9f
S		 1177
1178 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
9ffe79a9 1179 for (i = 0; i < HCLGE_TC_NUM; i++) {
acf61ecd 1180 u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9 1181
46a3df9f
S		 1182 req->tx_pkt_buff[i] =
1183 cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
1184 HCLGE_BUF_SIZE_UPDATE_EN_MSK);
9ffe79a9 1185 }
46a3df9f
S		 1186
1187 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1188 if (ret)
46a3df9f
S		 1189 dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
1190 ret);
46a3df9f 1191
3f639907 1192 return ret;
46a3df9f
S		 1193}
1194
acf61ecd
YL		 1195static int hclge_tx_buffer_alloc(struct hclge_dev *hdev,
1196 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1197{
acf61ecd 1198 int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc);
46a3df9f 1199
3f639907
JS		 1200 if (ret)
1201 dev_err(&hdev->pdev->dev, "tx buffer alloc failed %d\n", ret);
46a3df9f 1202
3f639907 1203 return ret;
46a3df9f
S		 1204}
1205
1206static int hclge_get_tc_num(struct hclge_dev *hdev)
1207{
1208 int i, cnt = 0;
1209
1210 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1211 if (hdev->hw_tc_map & BIT(i))
1212 cnt++;
1213 return cnt;
1214}
1215
1216static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
1217{
1218 int i, cnt = 0;
1219
1220 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
1221 if (hdev->hw_tc_map & BIT(i) &&
1222 hdev->tm_info.hw_pfc_map & BIT(i))
1223 cnt++;
1224 return cnt;
1225}
1226
1227/* Get the number of pfc enabled TCs, which have private buffer */
acf61ecd
YL		 1228static int hclge_get_pfc_priv_num(struct hclge_dev *hdev,
1229 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1230{
1231 struct hclge_priv_buf *priv;
1232 int i, cnt = 0;
1233
1234 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1235 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1236 if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
1237 priv->enable)
1238 cnt++;
1239 }
1240
1241 return cnt;
1242}
1243
1244/* Get the number of pfc disabled TCs, which have private buffer */
acf61ecd
YL		 1245static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev,
1246 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1247{
1248 struct hclge_priv_buf *priv;
1249 int i, cnt = 0;
1250
1251 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1252 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1253 if (hdev->hw_tc_map & BIT(i) &&
1254 !(hdev->tm_info.hw_pfc_map & BIT(i)) &&
1255 priv->enable)
1256 cnt++;
1257 }
1258
1259 return cnt;
1260}
1261
acf61ecd 1262static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1263{
1264 struct hclge_priv_buf *priv;
1265 u32 rx_priv = 0;
1266 int i;
1267
1268 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1269 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1270 if (priv->enable)
1271 rx_priv += priv->buf_size;
1272 }
1273 return rx_priv;
1274}
1275
acf61ecd 1276static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1277{
1278 u32 i, total_tx_size = 0;
1279
1280 for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
acf61ecd 1281 total_tx_size += buf_alloc->priv_buf[i].tx_buf_size;
9ffe79a9
YL		 1282
1283 return total_tx_size;
1284}
1285
acf61ecd
YL		 1286static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev,
1287 struct hclge_pkt_buf_alloc *buf_alloc,
1288 u32 rx_all)
46a3df9f
S		 1289{
1290 u32 shared_buf_min, shared_buf_tc, shared_std;
1291 int tc_num, pfc_enable_num;
1292 u32 shared_buf;
1293 u32 rx_priv;
1294 int i;
1295
1296 tc_num = hclge_get_tc_num(hdev);
1297 pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
1298
d221df4e
YL		 1299 if (hnae3_dev_dcb_supported(hdev))
1300 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
1301 else
1302 shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
1303
46a3df9f
S		 1304 shared_buf_tc = pfc_enable_num * hdev->mps +
1305 (tc_num - pfc_enable_num) * hdev->mps / 2 +
1306 hdev->mps;
1307 shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
1308
acf61ecd 1309 rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc);
46a3df9f
S		 1310 if (rx_all <= rx_priv + shared_std)
1311 return false;
1312
1313 shared_buf = rx_all - rx_priv;
acf61ecd
YL		 1314 buf_alloc->s_buf.buf_size = shared_buf;
1315 buf_alloc->s_buf.self.high = shared_buf;
1316 buf_alloc->s_buf.self.low = 2 * hdev->mps;
46a3df9f
S		 1317
1318 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
1319 if ((hdev->hw_tc_map & BIT(i)) &&
1320 (hdev->tm_info.hw_pfc_map & BIT(i))) {
acf61ecd
YL		 1321 buf_alloc->s_buf.tc_thrd[i].low = hdev->mps;
1322 buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps;
46a3df9f 1323 } else {
acf61ecd
YL		 1324 buf_alloc->s_buf.tc_thrd[i].low = 0;
1325 buf_alloc->s_buf.tc_thrd[i].high = hdev->mps;
46a3df9f
S		 1326 }
1327 }
1328
1329 return true;
1330}
1331
acf61ecd
YL		 1332static int hclge_tx_buffer_calc(struct hclge_dev *hdev,
1333 struct hclge_pkt_buf_alloc *buf_alloc)
9ffe79a9
YL		 1334{
1335 u32 i, total_size;
1336
1337 total_size = hdev->pkt_buf_size;
1338
1339 /* alloc tx buffer for all enabled tc */
1340 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1341 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
9ffe79a9
YL		 1342
1343 if (total_size < HCLGE_DEFAULT_TX_BUF)
1344 return -ENOMEM;
1345
1346 if (hdev->hw_tc_map & BIT(i))
1347 priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF;
1348 else
1349 priv->tx_buf_size = 0;
1350
1351 total_size -= priv->tx_buf_size;
1352 }
1353
1354 return 0;
1355}
1356
46a3df9f
S		 1357/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
1358 * @hdev: pointer to struct hclge_dev
acf61ecd 1359 * @buf_alloc: pointer to buffer calculation data
46a3df9f
S		 1360 * @return: 0: calculate sucessful, negative: fail
1361 */
1db9b1bf
YL		 1362static int hclge_rx_buffer_calc(struct hclge_dev *hdev,
1363 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1364{
996ff918
YL		 1365#define HCLGE_BUF_SIZE_UNIT 128
1366 u32 rx_all = hdev->pkt_buf_size, aligned_mps;
46a3df9f
S		 1367 int no_pfc_priv_num, pfc_priv_num;
1368 struct hclge_priv_buf *priv;
1369 int i;
1370
996ff918 1371 aligned_mps = round_up(hdev->mps, HCLGE_BUF_SIZE_UNIT);
acf61ecd 1372 rx_all -= hclge_get_tx_buff_alloced(buf_alloc);
9ffe79a9 1373
d602a525
YL		 1374 /* When DCB is not supported, rx private
1375 * buffer is not allocated.
1376 */
1377 if (!hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1378 if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
d602a525
YL		 1379 return -ENOMEM;
1380
1381 return 0;
1382 }
1383
46a3df9f
S		 1384 /* step 1, try to alloc private buffer for all enabled tc */
1385 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1386 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1387 if (hdev->hw_tc_map & BIT(i)) {
1388 priv->enable = 1;
1389 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
996ff918
YL		 1390 priv->wl.low = aligned_mps;
1391 priv->wl.high = priv->wl.low + aligned_mps;
46a3df9f
S		 1392 priv->buf_size = priv->wl.high +
1393 HCLGE_DEFAULT_DV;
1394 } else {
1395 priv->wl.low = 0;
996ff918 1396 priv->wl.high = 2 * aligned_mps;
46a3df9f
S		 1397 priv->buf_size = priv->wl.high;
1398 }
bb1fe9ea
YL		 1399 } else {
1400 priv->enable = 0;
1401 priv->wl.low = 0;
1402 priv->wl.high = 0;
1403 priv->buf_size = 0;
46a3df9f
S		 1404 }
1405 }
1406
acf61ecd 1407 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1408 return 0;
1409
1410 /* step 2, try to decrease the buffer size of
1411 * no pfc TC's private buffer
1412 */
1413 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1414 priv = &buf_alloc->priv_buf[i];
46a3df9f 1415
bb1fe9ea
YL		 1416 priv->enable = 0;
1417 priv->wl.low = 0;
1418 priv->wl.high = 0;
1419 priv->buf_size = 0;
1420
1421 if (!(hdev->hw_tc_map & BIT(i)))
1422 continue;
1423
1424 priv->enable = 1;
46a3df9f
S		 1425
1426 if (hdev->tm_info.hw_pfc_map & BIT(i)) {
1427 priv->wl.low = 128;
996ff918 1428 priv->wl.high = priv->wl.low + aligned_mps;
46a3df9f
S		 1429 priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
1430 } else {
1431 priv->wl.low = 0;
996ff918 1432 priv->wl.high = aligned_mps;
46a3df9f
S		 1433 priv->buf_size = priv->wl.high;
1434 }
1435 }
1436
acf61ecd 1437 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1438 return 0;
1439
1440 /* step 3, try to reduce the number of pfc disabled TCs,
1441 * which have private buffer
1442 */
1443 /* get the total no pfc enable TC number, which have private buffer */
acf61ecd 1444 no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1445
1446 /* let the last to be cleared first */
1447 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1448 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1449
1450 if (hdev->hw_tc_map & BIT(i) &&
1451 !(hdev->tm_info.hw_pfc_map & BIT(i))) {
1452 /* Clear the no pfc TC private buffer */
1453 priv->wl.low = 0;
1454 priv->wl.high = 0;
1455 priv->buf_size = 0;
1456 priv->enable = 0;
1457 no_pfc_priv_num--;
1458 }
1459
acf61ecd 1460 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1461 no_pfc_priv_num == 0)
1462 break;
1463 }
1464
acf61ecd 1465 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1466 return 0;
1467
1468 /* step 4, try to reduce the number of pfc enabled TCs
1469 * which have private buffer.
1470 */
acf61ecd 1471 pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc);
46a3df9f
S		 1472
1473 /* let the last to be cleared first */
1474 for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
acf61ecd 1475 priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1476
1477 if (hdev->hw_tc_map & BIT(i) &&
1478 hdev->tm_info.hw_pfc_map & BIT(i)) {
1479 /* Reduce the number of pfc TC with private buffer */
1480 priv->wl.low = 0;
1481 priv->enable = 0;
1482 priv->wl.high = 0;
1483 priv->buf_size = 0;
1484 pfc_priv_num--;
1485 }
1486
acf61ecd 1487 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) ||
46a3df9f
S		 1488 pfc_priv_num == 0)
1489 break;
1490 }
acf61ecd 1491 if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all))
46a3df9f
S		 1492 return 0;
1493
1494 return -ENOMEM;
1495}
1496
acf61ecd
YL		 1497static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev,
1498 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1499{
d44f9b63 1500 struct hclge_rx_priv_buff_cmd *req;
46a3df9f
S		 1501 struct hclge_desc desc;
1502 int ret;
1503 int i;
1504
1505 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
d44f9b63 1506 req = (struct hclge_rx_priv_buff_cmd *)desc.data;
46a3df9f
S		 1507
1508 /* Alloc private buffer TCs */
1509 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
acf61ecd 1510 struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i];
46a3df9f
S		 1511
1512 req->buf_num[i] =
1513 cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
1514 req->buf_num[i] |=
5bca3b94 1515 cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B);
46a3df9f
S		 1516 }
1517
b8c8bf47 1518 req->shared_buf =
acf61ecd 1519 cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
b8c8bf47
YL		 1520 (1 << HCLGE_TC0_PRI_BUF_EN_B));
1521
46a3df9f 1522 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1523 if (ret)
46a3df9f
S		 1524 dev_err(&hdev->pdev->dev,
1525 "rx private buffer alloc cmd failed %d\n", ret);
46a3df9f 1526
3f639907 1527 return ret;
46a3df9f
S		 1528}
1529
acf61ecd
YL		 1530static int hclge_rx_priv_wl_config(struct hclge_dev *hdev,
1531 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f
S		 1532{
1533 struct hclge_rx_priv_wl_buf *req;
1534 struct hclge_priv_buf *priv;
1535 struct hclge_desc desc[2];
1536 int i, j;
1537 int ret;
1538
1539 for (i = 0; i < 2; i++) {
1540 hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
1541 false);
1542 req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
1543
1544 /* The first descriptor set the NEXT bit to 1 */
1545 if (i == 0)
1546 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1547 else
1548 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1549
1550 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
acf61ecd
YL		 1551 u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j;
1552
1553 priv = &buf_alloc->priv_buf[idx];
46a3df9f
S		 1554 req->tc_wl[j].high =
1555 cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
1556 req->tc_wl[j].high |=
3738287c 1557 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1558 req->tc_wl[j].low =
1559 cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
1560 req->tc_wl[j].low |=
3738287c 1561 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1562 }
1563 }
1564
1565 /* Send 2 descriptor at one time */
1566 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3f639907 1567 if (ret)
46a3df9f
S		 1568 dev_err(&hdev->pdev->dev,
1569 "rx private waterline config cmd failed %d\n",
1570 ret);
3f639907 1571 return ret;
46a3df9f
S		 1572}
1573
acf61ecd
YL		 1574static int hclge_common_thrd_config(struct hclge_dev *hdev,
1575 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1576{
acf61ecd 1577 struct hclge_shared_buf *s_buf = &buf_alloc->s_buf;
46a3df9f
S		 1578 struct hclge_rx_com_thrd *req;
1579 struct hclge_desc desc[2];
1580 struct hclge_tc_thrd *tc;
1581 int i, j;
1582 int ret;
1583
1584 for (i = 0; i < 2; i++) {
1585 hclge_cmd_setup_basic_desc(&desc[i],
1586 HCLGE_OPC_RX_COM_THRD_ALLOC, false);
1587 req = (struct hclge_rx_com_thrd *)&desc[i].data;
1588
1589 /* The first descriptor set the NEXT bit to 1 */
1590 if (i == 0)
1591 desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1592 else
1593 desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
1594
1595 for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
1596 tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
1597
1598 req->com_thrd[j].high =
1599 cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
1600 req->com_thrd[j].high |=
3738287c 1601 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1602 req->com_thrd[j].low =
1603 cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
1604 req->com_thrd[j].low |=
3738287c 1605 cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1606 }
1607 }
1608
1609 /* Send 2 descriptors at one time */
1610 ret = hclge_cmd_send(&hdev->hw, desc, 2);
3f639907 1611 if (ret)
46a3df9f
S		 1612 dev_err(&hdev->pdev->dev,
1613 "common threshold config cmd failed %d\n", ret);
3f639907 1614 return ret;
46a3df9f
S		 1615}
1616
acf61ecd
YL		 1617static int hclge_common_wl_config(struct hclge_dev *hdev,
1618 struct hclge_pkt_buf_alloc *buf_alloc)
46a3df9f 1619{
acf61ecd 1620 struct hclge_shared_buf *buf = &buf_alloc->s_buf;
46a3df9f
S		 1621 struct hclge_rx_com_wl *req;
1622 struct hclge_desc desc;
1623 int ret;
1624
1625 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
1626
1627 req = (struct hclge_rx_com_wl *)desc.data;
1628 req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
3738287c 1629 req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1630
1631 req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
3738287c 1632 req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B));
46a3df9f
S		 1633
1634 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1635 if (ret)
46a3df9f
S		 1636 dev_err(&hdev->pdev->dev,
1637 "common waterline config cmd failed %d\n", ret);
46a3df9f 1638
3f639907 1639 return ret;
46a3df9f
S		 1640}
1641
1642int hclge_buffer_alloc(struct hclge_dev *hdev)
1643{
acf61ecd 1644 struct hclge_pkt_buf_alloc *pkt_buf;
46a3df9f
S		 1645 int ret;
1646
acf61ecd
YL		 1647 pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL);
1648 if (!pkt_buf)
46a3df9f
S		 1649 return -ENOMEM;
1650
acf61ecd 1651 ret = hclge_tx_buffer_calc(hdev, pkt_buf);
9ffe79a9
YL		 1652 if (ret) {
1653 dev_err(&hdev->pdev->dev,
1654 "could not calc tx buffer size for all TCs %d\n", ret);
acf61ecd 1655 goto out;
9ffe79a9
YL		 1656 }
1657
acf61ecd 1658 ret = hclge_tx_buffer_alloc(hdev, pkt_buf);
46a3df9f
S		 1659 if (ret) {
1660 dev_err(&hdev->pdev->dev,
1661 "could not alloc tx buffers %d\n", ret);
acf61ecd 1662 goto out;
46a3df9f
S		 1663 }
1664
acf61ecd 1665 ret = hclge_rx_buffer_calc(hdev, pkt_buf);
46a3df9f
S		 1666 if (ret) {
1667 dev_err(&hdev->pdev->dev,
1668 "could not calc rx priv buffer size for all TCs %d\n",
1669 ret);
acf61ecd 1670 goto out;
46a3df9f
S		 1671 }
1672
acf61ecd 1673 ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf);
46a3df9f
S		 1674 if (ret) {
1675 dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
1676 ret);
acf61ecd 1677 goto out;
46a3df9f
S		 1678 }
1679
2daf4a65 1680 if (hnae3_dev_dcb_supported(hdev)) {
acf61ecd 1681 ret = hclge_rx_priv_wl_config(hdev, pkt_buf);
2daf4a65
YL		 1682 if (ret) {
1683 dev_err(&hdev->pdev->dev,
1684 "could not configure rx private waterline %d\n",
1685 ret);
acf61ecd 1686 goto out;
2daf4a65 1687 }
46a3df9f 1688
acf61ecd 1689 ret = hclge_common_thrd_config(hdev, pkt_buf);
2daf4a65
YL		 1690 if (ret) {
1691 dev_err(&hdev->pdev->dev,
1692 "could not configure common threshold %d\n",
1693 ret);
acf61ecd 1694 goto out;
2daf4a65 1695 }
46a3df9f
S		 1696 }
1697
acf61ecd
YL		 1698 ret = hclge_common_wl_config(hdev, pkt_buf);
1699 if (ret)
46a3df9f
S		 1700 dev_err(&hdev->pdev->dev,
1701 "could not configure common waterline %d\n", ret);
46a3df9f 1702
acf61ecd
YL		 1703out:
1704 kfree(pkt_buf);
1705 return ret;
46a3df9f
S		 1706}
1707
1708static int hclge_init_roce_base_info(struct hclge_vport *vport)
1709{
1710 struct hnae3_handle *roce = &vport->roce;
1711 struct hnae3_handle *nic = &vport->nic;
1712
887c3820 1713 roce->rinfo.num_vectors = vport->back->num_roce_msi;
46a3df9f
S		 1714
1715 if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
1716 vport->back->num_msi_left == 0)
1717 return -EINVAL;
1718
1719 roce->rinfo.base_vector = vport->back->roce_base_vector;
1720
1721 roce->rinfo.netdev = nic->kinfo.netdev;
1722 roce->rinfo.roce_io_base = vport->back->hw.io_base;
1723
1724 roce->pdev = nic->pdev;
1725 roce->ae_algo = nic->ae_algo;
1726 roce->numa_node_mask = nic->numa_node_mask;
1727
1728 return 0;
1729}
1730
887c3820 1731static int hclge_init_msi(struct hclge_dev *hdev)
46a3df9f
S		 1732{
1733 struct pci_dev *pdev = hdev->pdev;
887c3820
SM		 1734 int vectors;
1735 int i;
46a3df9f 1736
887c3820
SM		 1737 vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi,
1738 PCI_IRQ_MSI | PCI_IRQ_MSIX);
1739 if (vectors < 0) {
1740 dev_err(&pdev->dev,
1741 "failed(%d) to allocate MSI/MSI-X vectors\n",
1742 vectors);
1743 return vectors;
46a3df9f 1744 }
887c3820
SM		 1745 if (vectors < hdev->num_msi)
1746 dev_warn(&hdev->pdev->dev,
1747 "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n",
1748 hdev->num_msi, vectors);
46a3df9f 1749
887c3820
SM		 1750 hdev->num_msi = vectors;
1751 hdev->num_msi_left = vectors;
1752 hdev->base_msi_vector = pdev->irq;
46a3df9f 1753 hdev->roce_base_vector = hdev->base_msi_vector +
375dd5e4 1754 hdev->roce_base_msix_offset;
46a3df9f 1755
46a3df9f
S		 1756 hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
1757 sizeof(u16), GFP_KERNEL);
887c3820
SM		 1758 if (!hdev->vector_status) {
1759 pci_free_irq_vectors(pdev);
46a3df9f 1760 return -ENOMEM;
887c3820 1761 }
46a3df9f
S		 1762
1763 for (i = 0; i < hdev->num_msi; i++)
1764 hdev->vector_status[i] = HCLGE_INVALID_VPORT;
1765
887c3820
SM		 1766 hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi,
1767 sizeof(int), GFP_KERNEL);
1768 if (!hdev->vector_irq) {
1769 pci_free_irq_vectors(pdev);
1770 return -ENOMEM;
46a3df9f 1771 }
46a3df9f
S		 1772
1773 return 0;
1774}
1775
2d03eacc 1776static u8 hclge_check_speed_dup(u8 duplex, int speed)
46a3df9f 1777{
46a3df9f 1778
2d03eacc
YL		 1779 if (!(speed == HCLGE_MAC_SPEED_10M || speed == HCLGE_MAC_SPEED_100M))
1780 duplex = HCLGE_MAC_FULL;
46a3df9f 1781
2d03eacc 1782 return duplex;
46a3df9f
S		 1783}
1784
2d03eacc
YL		 1785static int hclge_cfg_mac_speed_dup_hw(struct hclge_dev *hdev, int speed,
1786 u8 duplex)
46a3df9f 1787{
d44f9b63 1788 struct hclge_config_mac_speed_dup_cmd *req;
46a3df9f
S		 1789 struct hclge_desc desc;
1790 int ret;
1791
d44f9b63 1792 req = (struct hclge_config_mac_speed_dup_cmd *)desc.data;
46a3df9f
S		 1793
1794 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
1795
e4e87715 1796 hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
46a3df9f
S		 1797
1798 switch (speed) {
1799 case HCLGE_MAC_SPEED_10M:
e4e87715
PL		 1800 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1801 HCLGE_CFG_SPEED_S, 6);
46a3df9f
S		 1802 break;
1803 case HCLGE_MAC_SPEED_100M:
e4e87715
PL		 1804 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1805 HCLGE_CFG_SPEED_S, 7);
46a3df9f
S		 1806 break;
1807 case HCLGE_MAC_SPEED_1G:
e4e87715
PL		 1808 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1809 HCLGE_CFG_SPEED_S, 0);
46a3df9f
S		 1810 break;
1811 case HCLGE_MAC_SPEED_10G:
e4e87715
PL		 1812 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1813 HCLGE_CFG_SPEED_S, 1);
46a3df9f
S		 1814 break;
1815 case HCLGE_MAC_SPEED_25G:
e4e87715
PL		 1816 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1817 HCLGE_CFG_SPEED_S, 2);
46a3df9f
S		 1818 break;
1819 case HCLGE_MAC_SPEED_40G:
e4e87715
PL		 1820 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1821 HCLGE_CFG_SPEED_S, 3);
46a3df9f
S		 1822 break;
1823 case HCLGE_MAC_SPEED_50G:
e4e87715
PL		 1824 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1825 HCLGE_CFG_SPEED_S, 4);
46a3df9f
S		 1826 break;
1827 case HCLGE_MAC_SPEED_100G:
e4e87715
PL		 1828 hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
1829 HCLGE_CFG_SPEED_S, 5);
46a3df9f
S		 1830 break;
1831 default:
d7629e74 1832 dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
46a3df9f
S		 1833 return -EINVAL;
1834 }
1835
e4e87715
PL		 1836 hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1837 1);
46a3df9f
S		 1838
1839 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1840 if (ret) {
1841 dev_err(&hdev->pdev->dev,
1842 "mac speed/duplex config cmd failed %d.\n", ret);
1843 return ret;
1844 }
1845
2d03eacc
YL		 1846 return 0;
1847}
1848
1849int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
1850{
1851 int ret;
1852
1853 duplex = hclge_check_speed_dup(duplex, speed);
1854 if (hdev->hw.mac.speed == speed && hdev->hw.mac.duplex == duplex)
1855 return 0;
1856
1857 ret = hclge_cfg_mac_speed_dup_hw(hdev, speed, duplex);
1858 if (ret)
1859 return ret;
1860
1861 hdev->hw.mac.speed = speed;
1862 hdev->hw.mac.duplex = duplex;
46a3df9f
S		 1863
1864 return 0;
1865}
1866
1867static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
1868 u8 duplex)
1869{
1870 struct hclge_vport *vport = hclge_get_vport(handle);
1871 struct hclge_dev *hdev = vport->back;
1872
1873 return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
1874}
1875
1876static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
1877 u8 *duplex)
1878{
d44f9b63 1879 struct hclge_query_an_speed_dup_cmd *req;
46a3df9f
S		 1880 struct hclge_desc desc;
1881 int speed_tmp;
1882 int ret;
1883
d44f9b63 1884 req = (struct hclge_query_an_speed_dup_cmd *)desc.data;
46a3df9f
S		 1885
1886 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
1887 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
1888 if (ret) {
1889 dev_err(&hdev->pdev->dev,
1890 "mac speed/autoneg/duplex query cmd failed %d\n",
1891 ret);
1892 return ret;
1893 }
1894
e4e87715
PL		 1895 *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
1896 speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
1897 HCLGE_QUERY_SPEED_S);
46a3df9f
S		 1898
1899 ret = hclge_parse_speed(speed_tmp, speed);
3f639907 1900 if (ret)
46a3df9f
S		 1901 dev_err(&hdev->pdev->dev,
1902 "could not parse speed(=%d), %d\n", speed_tmp, ret);
46a3df9f 1903
3f639907 1904 return ret;
46a3df9f
S		 1905}
1906
46a3df9f
S		 1907static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
1908{
d44f9b63 1909 struct hclge_config_auto_neg_cmd *req;
46a3df9f 1910 struct hclge_desc desc;
a90bb9a5 1911 u32 flag = 0;
46a3df9f
S		 1912 int ret;
1913
1914 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
1915
d44f9b63 1916 req = (struct hclge_config_auto_neg_cmd *)desc.data;
e4e87715 1917 hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
a90bb9a5 1918 req->cfg_an_cmd_flag = cpu_to_le32(flag);
46a3df9f
S		 1919
1920 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 1921 if (ret)
46a3df9f
S		 1922 dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
1923 ret);
46a3df9f 1924
3f639907 1925 return ret;
46a3df9f
S		 1926}
1927
1928static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
1929{
1930 struct hclge_vport *vport = hclge_get_vport(handle);
1931 struct hclge_dev *hdev = vport->back;
1932
1933 return hclge_set_autoneg_en(hdev, enable);
1934}
1935
1936static int hclge_get_autoneg(struct hnae3_handle *handle)
1937{
1938 struct hclge_vport *vport = hclge_get_vport(handle);
1939 struct hclge_dev *hdev = vport->back;
27b5bf49
FL		 1940 struct phy_device *phydev = hdev->hw.mac.phydev;
1941
1942 if (phydev)
1943 return phydev->autoneg;
46a3df9f
S		 1944
1945 return hdev->hw.mac.autoneg;
1946}
1947
1948static int hclge_mac_init(struct hclge_dev *hdev)
1949{
f9fd82a9
FL		 1950 struct hnae3_handle *handle = &hdev->vport[0].nic;
1951 struct net_device *netdev = handle->kinfo.netdev;
46a3df9f 1952 struct hclge_mac *mac = &hdev->hw.mac;
f9fd82a9 1953 int mtu;
46a3df9f
S		 1954 int ret;
1955
2d03eacc
YL		 1956 hdev->hw.mac.duplex = HCLGE_MAC_FULL;
1957 ret = hclge_cfg_mac_speed_dup_hw(hdev, hdev->hw.mac.speed,
1958 hdev->hw.mac.duplex);
46a3df9f
S		 1959 if (ret) {
1960 dev_err(&hdev->pdev->dev,
1961 "Config mac speed dup fail ret=%d\n", ret);
1962 return ret;
1963 }
1964
1965 mac->link = 0;
1966
f9fd82a9
FL		 1967 if (netdev)
1968 mtu = netdev->mtu;
1969 else
1970 mtu = ETH_DATA_LEN;
1971
1972 ret = hclge_set_mtu(handle, mtu);
3f639907 1973 if (ret)
f9fd82a9
FL		 1974 dev_err(&hdev->pdev->dev,
1975 "set mtu failed ret=%d\n", ret);
f9fd82a9 1976
3f639907 1977 return ret;
46a3df9f
S		 1978}
1979
c1a81619
SM		 1980static void hclge_mbx_task_schedule(struct hclge_dev *hdev)
1981{
1982 if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state))
1983 schedule_work(&hdev->mbx_service_task);
1984}
1985
cb1b9f77
SM		 1986static void hclge_reset_task_schedule(struct hclge_dev *hdev)
1987{
1988 if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state))
1989 schedule_work(&hdev->rst_service_task);
1990}
1991
46a3df9f
S		 1992static void hclge_task_schedule(struct hclge_dev *hdev)
1993{
1994 if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
1995 !test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
1996 !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
1997 (void)schedule_work(&hdev->service_task);
1998}
1999
2000static int hclge_get_mac_link_status(struct hclge_dev *hdev)
2001{
d44f9b63 2002 struct hclge_link_status_cmd *req;
46a3df9f
S		 2003 struct hclge_desc desc;
2004 int link_status;
2005 int ret;
2006
2007 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
2008 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2009 if (ret) {
2010 dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
2011 ret);
2012 return ret;
2013 }
2014
d44f9b63 2015 req = (struct hclge_link_status_cmd *)desc.data;
c79301d8 2016 link_status = req->status & HCLGE_LINK_STATUS_UP_M;
46a3df9f
S		 2017
2018 return !!link_status;
2019}
2020
2021static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
2022{
2023 int mac_state;
2024 int link_stat;
2025
582d37bb
PL		 2026 if (test_bit(HCLGE_STATE_DOWN, &hdev->state))
2027 return 0;
2028
46a3df9f
S		 2029 mac_state = hclge_get_mac_link_status(hdev);
2030
2031 if (hdev->hw.mac.phydev) {
fd813314 2032 if (hdev->hw.mac.phydev->state == PHY_RUNNING)
46a3df9f
S		 2033 link_stat = mac_state &
2034 hdev->hw.mac.phydev->link;
2035 else
2036 link_stat = 0;
2037
2038 } else {
2039 link_stat = mac_state;
2040 }
2041
2042 return !!link_stat;
2043}
2044
2045static void hclge_update_link_status(struct hclge_dev *hdev)
2046{
2047 struct hnae3_client *client = hdev->nic_client;
2048 struct hnae3_handle *handle;
2049 int state;
2050 int i;
2051
2052 if (!client)
2053 return;
2054 state = hclge_get_mac_phy_link(hdev);
2055 if (state != hdev->hw.mac.link) {
2056 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2057 handle = &hdev->vport[i].nic;
2058 client->ops->link_status_change(handle, state);
2059 }
2060 hdev->hw.mac.link = state;
2061 }
2062}
2063
2064static int hclge_update_speed_duplex(struct hclge_dev *hdev)
2065{
2066 struct hclge_mac mac = hdev->hw.mac;
2067 u8 duplex;
2068 int speed;
2069 int ret;
2070
2071 /* get the speed and duplex as autoneg'result from mac cmd when phy
2072 * doesn't exit.
2073 */
c040366b 2074 if (mac.phydev || !mac.autoneg)
46a3df9f
S		 2075 return 0;
2076
2077 ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
2078 if (ret) {
2079 dev_err(&hdev->pdev->dev,
2080 "mac autoneg/speed/duplex query failed %d\n", ret);
2081 return ret;
2082 }
2083
2d03eacc
YL		 2084 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
2085 if (ret) {
2086 dev_err(&hdev->pdev->dev,
2087 "mac speed/duplex config failed %d\n", ret);
2088 return ret;
46a3df9f
S		 2089 }
2090
2091 return 0;
2092}
2093
2094static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
2095{
2096 struct hclge_vport *vport = hclge_get_vport(handle);
2097 struct hclge_dev *hdev = vport->back;
2098
2099 return hclge_update_speed_duplex(hdev);
2100}
2101
2102static int hclge_get_status(struct hnae3_handle *handle)
2103{
2104 struct hclge_vport *vport = hclge_get_vport(handle);
2105 struct hclge_dev *hdev = vport->back;
2106
2107 hclge_update_link_status(hdev);
2108
2109 return hdev->hw.mac.link;
2110}
2111
d039ef68 2112static void hclge_service_timer(struct timer_list *t)
46a3df9f 2113{
d039ef68 2114 struct hclge_dev *hdev = from_timer(hdev, t, service_timer);
46a3df9f 2115
d039ef68 2116 mod_timer(&hdev->service_timer, jiffies + HZ);
c5f65480 2117 hdev->hw_stats.stats_timer++;
46a3df9f
S		 2118 hclge_task_schedule(hdev);
2119}
2120
2121static void hclge_service_complete(struct hclge_dev *hdev)
2122{
2123 WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
2124
2125 /* Flush memory before next watchdog */
2126 smp_mb__before_atomic();
2127 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
2128}
2129
ca1d7669
SM		 2130static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval)
2131{
2132 u32 rst_src_reg;
c1a81619 2133 u32 cmdq_src_reg;
ca1d7669
SM		 2134
2135 /* fetch the events from their corresponding regs */
9ca8d1a7 2136 rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS);
c1a81619
SM		 2137 cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG);
2138
2139 /* Assumption: If by any chance reset and mailbox events are reported
2140 * together then we will only process reset event in this go and will
2141 * defer the processing of the mailbox events. Since, we would have not
2142 * cleared RX CMDQ event this time we would receive again another
2143 * interrupt from H/W just for the mailbox.
2144 */
ca1d7669
SM		 2145
2146 /* check for vector0 reset event sources */
6dd22bbc
HT		 2147 if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) {
2148 dev_info(&hdev->pdev->dev, "IMP reset interrupt\n");
2149 set_bit(HNAE3_IMP_RESET, &hdev->reset_pending);
2150 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2151 *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2152 return HCLGE_VECTOR0_EVENT_RST;
2153 }
2154
ca1d7669 2155 if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) {
65e41e7e 2156 dev_info(&hdev->pdev->dev, "global reset interrupt\n");
8d40854f 2157 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
ca1d7669
SM		 2158 set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending);
2159 *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2160 return HCLGE_VECTOR0_EVENT_RST;
2161 }
2162
2163 if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) {
65e41e7e 2164 dev_info(&hdev->pdev->dev, "core reset interrupt\n");
8d40854f 2165 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
ca1d7669
SM		 2166 set_bit(HNAE3_CORE_RESET, &hdev->reset_pending);
2167 *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2168 return HCLGE_VECTOR0_EVENT_RST;
2169 }
2170
c1a81619
SM		 2171 /* check for vector0 mailbox(=CMDQ RX) event source */
2172 if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
2173 cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B);
2174 *clearval = cmdq_src_reg;
2175 return HCLGE_VECTOR0_EVENT_MBX;
2176 }
ca1d7669
SM		 2177
2178 return HCLGE_VECTOR0_EVENT_OTHER;
2179}
2180
2181static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,
2182 u32 regclr)
2183{
c1a81619
SM		 2184 switch (event_type) {
2185 case HCLGE_VECTOR0_EVENT_RST:
ca1d7669 2186 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);
c1a81619
SM		 2187 break;
2188 case HCLGE_VECTOR0_EVENT_MBX:
2189 hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr);
2190 break;
fa7a4bd5
JS		 2191 default:
2192 break;
c1a81619 2193 }
ca1d7669
SM		 2194}
2195
8e52a602
XW		 2196static void hclge_clear_all_event_cause(struct hclge_dev *hdev)
2197{
2198 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST,
2199 BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) |
2200 BIT(HCLGE_VECTOR0_CORERESET_INT_B) |
2201 BIT(HCLGE_VECTOR0_IMPRESET_INT_B));
2202 hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0);
2203}
2204
466b0c00
L		 2205static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable)
2206{
2207 writel(enable ? 1 : 0, vector->addr);
2208}
2209
2210static irqreturn_t hclge_misc_irq_handle(int irq, void *data)
2211{
2212 struct hclge_dev *hdev = data;
ca1d7669
SM		 2213 u32 event_cause;
2214 u32 clearval;
466b0c00
L		 2215
2216 hclge_enable_vector(&hdev->misc_vector, false);
ca1d7669
SM		 2217 event_cause = hclge_check_event_cause(hdev, &clearval);
2218
c1a81619 2219 /* vector 0 interrupt is shared with reset and mailbox source events.*/
ca1d7669
SM		 2220 switch (event_cause) {
2221 case HCLGE_VECTOR0_EVENT_RST:
cb1b9f77 2222 hclge_reset_task_schedule(hdev);
ca1d7669 2223 break;
c1a81619
SM		 2224 case HCLGE_VECTOR0_EVENT_MBX:
2225 /* If we are here then,
2226 * 1. Either we are not handling any mbx task and we are not
2227 * scheduled as well
2228 * OR
2229 * 2. We could be handling a mbx task but nothing more is
2230 * scheduled.
2231 * In both cases, we should schedule mbx task as there are more
2232 * mbx messages reported by this interrupt.
2233 */
2234 hclge_mbx_task_schedule(hdev);
f0ad97ac 2235 break;
ca1d7669 2236 default:
f0ad97ac
YL		 2237 dev_warn(&hdev->pdev->dev,
2238 "received unknown or unhandled event of vector0\n");
ca1d7669
SM		 2239 break;
2240 }
2241
cd8c5c26 2242 /* clear the source of interrupt if it is not cause by reset */
0d441140 2243 if (event_cause == HCLGE_VECTOR0_EVENT_MBX) {
cd8c5c26
YL		 2244 hclge_clear_event_cause(hdev, event_cause, clearval);
2245 hclge_enable_vector(&hdev->misc_vector, true);
2246 }
466b0c00
L		 2247
2248 return IRQ_HANDLED;
2249}
2250
2251static void hclge_free_vector(struct hclge_dev *hdev, int vector_id)
2252{
36cbbdf6
PL		 2253 if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) {
2254 dev_warn(&hdev->pdev->dev,
2255 "vector(vector_id %d) has been freed.\n", vector_id);
2256 return;
2257 }
2258
466b0c00
L		 2259 hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT;
2260 hdev->num_msi_left += 1;
2261 hdev->num_msi_used -= 1;
2262}
2263
2264static void hclge_get_misc_vector(struct hclge_dev *hdev)
2265{
2266 struct hclge_misc_vector *vector = &hdev->misc_vector;
2267
2268 vector->vector_irq = pci_irq_vector(hdev->pdev, 0);
2269
2270 vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE;
2271 hdev->vector_status[0] = 0;
2272
2273 hdev->num_msi_left -= 1;
2274 hdev->num_msi_used += 1;
2275}
2276
2277static int hclge_misc_irq_init(struct hclge_dev *hdev)
2278{
2279 int ret;
2280
2281 hclge_get_misc_vector(hdev);
2282
ca1d7669
SM		 2283 /* this would be explicitly freed in the end */
2284 ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle,
2285 0, "hclge_misc", hdev);
466b0c00
L		 2286 if (ret) {
2287 hclge_free_vector(hdev, 0);
2288 dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n",
2289 hdev->misc_vector.vector_irq);
2290 }
2291
2292 return ret;
2293}
2294
ca1d7669
SM		 2295static void hclge_misc_irq_uninit(struct hclge_dev *hdev)
2296{
2297 free_irq(hdev->misc_vector.vector_irq, hdev);
2298 hclge_free_vector(hdev, 0);
2299}
2300
4ed340ab
L		 2301static int hclge_notify_client(struct hclge_dev *hdev,
2302 enum hnae3_reset_notify_type type)
2303{
2304 struct hnae3_client *client = hdev->nic_client;
2305 u16 i;
2306
2307 if (!client->ops->reset_notify)
2308 return -EOPNOTSUPP;
2309
2310 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2311 struct hnae3_handle *handle = &hdev->vport[i].nic;
2312 int ret;
2313
2314 ret = client->ops->reset_notify(handle, type);
65e41e7e
HT		 2315 if (ret) {
2316 dev_err(&hdev->pdev->dev,
2317 "notify nic client failed %d(%d)\n", type, ret);
4ed340ab 2318 return ret;
65e41e7e 2319 }
4ed340ab
L		 2320 }
2321
2322 return 0;
2323}
2324
f403a84f
HT		 2325static int hclge_notify_roce_client(struct hclge_dev *hdev,
2326 enum hnae3_reset_notify_type type)
2327{
2328 struct hnae3_client *client = hdev->roce_client;
2329 int ret = 0;
2330 u16 i;
2331
2332 if (!client)
2333 return 0;
2334
2335 if (!client->ops->reset_notify)
2336 return -EOPNOTSUPP;
2337
2338 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
2339 struct hnae3_handle *handle = &hdev->vport[i].roce;
2340
2341 ret = client->ops->reset_notify(handle, type);
2342 if (ret) {
2343 dev_err(&hdev->pdev->dev,
2344 "notify roce client failed %d(%d)",
2345 type, ret);
2346 return ret;
2347 }
2348 }
2349
2350 return ret;
2351}
2352
4ed340ab
L		 2353static int hclge_reset_wait(struct hclge_dev *hdev)
2354{
2355#define HCLGE_RESET_WATI_MS 100
6dd22bbc 2356#define HCLGE_RESET_WAIT_CNT 200
4ed340ab
L		 2357 u32 val, reg, reg_bit;
2358 u32 cnt = 0;
2359
2360 switch (hdev->reset_type) {
6dd22bbc
HT		 2361 case HNAE3_IMP_RESET:
2362 reg = HCLGE_GLOBAL_RESET_REG;
2363 reg_bit = HCLGE_IMP_RESET_BIT;
2364 break;
4ed340ab
L		 2365 case HNAE3_GLOBAL_RESET:
2366 reg = HCLGE_GLOBAL_RESET_REG;
2367 reg_bit = HCLGE_GLOBAL_RESET_BIT;
2368 break;
2369 case HNAE3_CORE_RESET:
2370 reg = HCLGE_GLOBAL_RESET_REG;
2371 reg_bit = HCLGE_CORE_RESET_BIT;
2372 break;
2373 case HNAE3_FUNC_RESET:
2374 reg = HCLGE_FUN_RST_ING;
2375 reg_bit = HCLGE_FUN_RST_ING_B;
2376 break;
6b9a97ee
HT		 2377 case HNAE3_FLR_RESET:
2378 break;
4ed340ab
L		 2379 default:
2380 dev_err(&hdev->pdev->dev,
2381 "Wait for unsupported reset type: %d\n",
2382 hdev->reset_type);
2383 return -EINVAL;
2384 }
2385
6b9a97ee
HT		 2386 if (hdev->reset_type == HNAE3_FLR_RESET) {
2387 while (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state) &&
2388 cnt++ < HCLGE_RESET_WAIT_CNT)
2389 msleep(HCLGE_RESET_WATI_MS);
2390
2391 if (!test_bit(HNAE3_FLR_DONE, &hdev->flr_state)) {
2392 dev_err(&hdev->pdev->dev,
2393 "flr wait timeout: %d\n", cnt);
2394 return -EBUSY;
2395 }
2396
2397 return 0;
2398 }
2399
4ed340ab 2400 val = hclge_read_dev(&hdev->hw, reg);
e4e87715 2401 while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) {
4ed340ab
L		 2402 msleep(HCLGE_RESET_WATI_MS);
2403 val = hclge_read_dev(&hdev->hw, reg);
2404 cnt++;
2405 }
2406
4ed340ab
L		 2407 if (cnt >= HCLGE_RESET_WAIT_CNT) {
2408 dev_warn(&hdev->pdev->dev,
2409 "Wait for reset timeout: %d\n", hdev->reset_type);
2410 return -EBUSY;
2411 }
2412
2413 return 0;
2414}
2415
aa5c4f17
HT		 2416static int hclge_set_vf_rst(struct hclge_dev *hdev, int func_id, bool reset)
2417{
2418 struct hclge_vf_rst_cmd *req;
2419 struct hclge_desc desc;
2420
2421 req = (struct hclge_vf_rst_cmd *)desc.data;
2422 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GBL_RST_STATUS, false);
2423 req->dest_vfid = func_id;
2424
2425 if (reset)
2426 req->vf_rst = 0x1;
2427
2428 return hclge_cmd_send(&hdev->hw, &desc, 1);
2429}
2430
2431int hclge_set_all_vf_rst(struct hclge_dev *hdev, bool reset)
2432{
2433 int i;
2434
2435 for (i = hdev->num_vmdq_vport + 1; i < hdev->num_alloc_vport; i++) {
2436 struct hclge_vport *vport = &hdev->vport[i];
2437 int ret;
2438
2439 /* Send cmd to set/clear VF's FUNC_RST_ING */
2440 ret = hclge_set_vf_rst(hdev, vport->vport_id, reset);
2441 if (ret) {
2442 dev_err(&hdev->pdev->dev,
2443 "set vf(%d) rst failded %d!\n",
2444 vport->vport_id, ret);
2445 return ret;
2446 }
2447
2448 if (!reset)
2449 continue;
2450
2451 /* Inform VF to process the reset.
2452 * hclge_inform_reset_assert_to_vf may fail if VF
2453 * driver is not loaded.
2454 */
2455 ret = hclge_inform_reset_assert_to_vf(vport);
2456 if (ret)
2457 dev_warn(&hdev->pdev->dev,
2458 "inform reset to vf(%d) failded %d!\n",
2459 vport->vport_id, ret);
2460 }
2461
2462 return 0;
2463}
2464
2bfbd35d 2465int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
4ed340ab
L		 2466{
2467 struct hclge_desc desc;
2468 struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data;
2469 int ret;
2470
2471 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false);
e4e87715 2472 hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1);
4ed340ab
L		 2473 req->fun_reset_vfid = func_id;
2474
2475 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
2476 if (ret)
2477 dev_err(&hdev->pdev->dev,
2478 "send function reset cmd fail, status =%d\n", ret);
2479
2480 return ret;
2481}
2482
f2f432f2 2483static void hclge_do_reset(struct hclge_dev *hdev)
4ed340ab
L		 2484{
2485 struct pci_dev *pdev = hdev->pdev;
2486 u32 val;
2487
f2f432f2 2488 switch (hdev->reset_type) {
4ed340ab
L		 2489 case HNAE3_GLOBAL_RESET:
2490 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e4e87715 2491 hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1);
4ed340ab
L		 2492 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2493 dev_info(&pdev->dev, "Global Reset requested\n");
2494 break;
2495 case HNAE3_CORE_RESET:
2496 val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG);
e4e87715 2497 hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1);
4ed340ab
L		 2498 hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val);
2499 dev_info(&pdev->dev, "Core Reset requested\n");
2500 break;
2501 case HNAE3_FUNC_RESET:
2502 dev_info(&pdev->dev, "PF Reset requested\n");
cb1b9f77
SM		 2503 /* schedule again to check later */
2504 set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending);
2505 hclge_reset_task_schedule(hdev);
4ed340ab 2506 break;
6b9a97ee
HT		 2507 case HNAE3_FLR_RESET:
2508 dev_info(&pdev->dev, "FLR requested\n");
2509 /* schedule again to check later */
2510 set_bit(HNAE3_FLR_RESET, &hdev->reset_pending);
2511 hclge_reset_task_schedule(hdev);
2512 break;
4ed340ab
L		 2513 default:
2514 dev_warn(&pdev->dev,
f2f432f2 2515 "Unsupported reset type: %d\n", hdev->reset_type);
4ed340ab
L		 2516 break;
2517 }
2518}
2519
f2f432f2
SM		 2520static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev,
2521 unsigned long *addr)
2522{
2523 enum hnae3_reset_type rst_level = HNAE3_NONE_RESET;
2524
2525 /* return the highest priority reset level amongst all */
7cea834d
HT		 2526 if (test_bit(HNAE3_IMP_RESET, addr)) {
2527 rst_level = HNAE3_IMP_RESET;
2528 clear_bit(HNAE3_IMP_RESET, addr);
2529 clear_bit(HNAE3_GLOBAL_RESET, addr);
2530 clear_bit(HNAE3_CORE_RESET, addr);
2531 clear_bit(HNAE3_FUNC_RESET, addr);
2532 } else if (test_bit(HNAE3_GLOBAL_RESET, addr)) {
f2f432f2 2533 rst_level = HNAE3_GLOBAL_RESET;
7cea834d
HT		 2534 clear_bit(HNAE3_GLOBAL_RESET, addr);
2535 clear_bit(HNAE3_CORE_RESET, addr);
2536 clear_bit(HNAE3_FUNC_RESET, addr);
2537 } else if (test_bit(HNAE3_CORE_RESET, addr)) {
f2f432f2 2538 rst_level = HNAE3_CORE_RESET;
7cea834d
HT		 2539 clear_bit(HNAE3_CORE_RESET, addr);
2540 clear_bit(HNAE3_FUNC_RESET, addr);
2541 } else if (test_bit(HNAE3_FUNC_RESET, addr)) {
f2f432f2 2542 rst_level = HNAE3_FUNC_RESET;
7cea834d 2543 clear_bit(HNAE3_FUNC_RESET, addr);
6b9a97ee
HT		 2544 } else if (test_bit(HNAE3_FLR_RESET, addr)) {
2545 rst_level = HNAE3_FLR_RESET;
2546 clear_bit(HNAE3_FLR_RESET, addr);
7cea834d 2547 }
f2f432f2
SM		 2548
2549 return rst_level;
2550}
2551
cd8c5c26
YL		 2552static void hclge_clear_reset_cause(struct hclge_dev *hdev)
2553{
2554 u32 clearval = 0;
2555
2556 switch (hdev->reset_type) {
2557 case HNAE3_IMP_RESET:
2558 clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B);
2559 break;
2560 case HNAE3_GLOBAL_RESET:
2561 clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B);
2562 break;
2563 case HNAE3_CORE_RESET:
2564 clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B);
2565 break;
2566 default:
cd8c5c26
YL		 2567 break;
2568 }
2569
2570 if (!clearval)
2571 return;
2572
2573 hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval);
2574 hclge_enable_vector(&hdev->misc_vector, true);
2575}
2576
aa5c4f17
HT		 2577static int hclge_reset_prepare_down(struct hclge_dev *hdev)
2578{
2579 int ret = 0;
2580
2581 switch (hdev->reset_type) {
2582 case HNAE3_FUNC_RESET:
6b9a97ee
HT		 2583 /* fall through */
2584 case HNAE3_FLR_RESET:
aa5c4f17
HT		 2585 ret = hclge_set_all_vf_rst(hdev, true);
2586 break;
2587 default:
2588 break;
2589 }
2590
2591 return ret;
2592}
2593
35d93a30
HT		 2594static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
2595{
6dd22bbc 2596 u32 reg_val;
35d93a30
HT		 2597 int ret = 0;
2598
2599 switch (hdev->reset_type) {
2600 case HNAE3_FUNC_RESET:
aa5c4f17
HT		 2601 /* There is no mechanism for PF to know if VF has stopped IO
2602 * for now, just wait 100 ms for VF to stop IO
2603 */
2604 msleep(100);
35d93a30
HT		 2605 ret = hclge_func_reset_cmd(hdev, 0);
2606 if (ret) {
2607 dev_err(&hdev->pdev->dev,
141b95d5 2608 "asserting function reset fail %d!\n", ret);
35d93a30
HT		 2609 return ret;
2610 }
2611
2612 /* After performaning pf reset, it is not necessary to do the
2613 * mailbox handling or send any command to firmware, because
2614 * any mailbox handling or command to firmware is only valid
2615 * after hclge_cmd_init is called.
2616 */
2617 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2618 break;
6b9a97ee
HT		 2619 case HNAE3_FLR_RESET:
2620 /* There is no mechanism for PF to know if VF has stopped IO
2621 * for now, just wait 100 ms for VF to stop IO
2622 */
2623 msleep(100);
2624 set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
2625 set_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
2626 break;
6dd22bbc
HT		 2627 case HNAE3_IMP_RESET:
2628 reg_val = hclge_read_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG);
2629 hclge_write_dev(&hdev->hw, HCLGE_PF_OTHER_INT_REG,
2630 BIT(HCLGE_VECTOR0_IMP_RESET_INT_B) | reg_val);
2631 break;
35d93a30
HT		 2632 default:
2633 break;
2634 }
2635
2636 dev_info(&hdev->pdev->dev, "prepare wait ok\n");
2637
2638 return ret;
2639}
2640
65e41e7e
HT		 2641static bool hclge_reset_err_handle(struct hclge_dev *hdev, bool is_timeout)
2642{
2643#define MAX_RESET_FAIL_CNT 5
2644#define RESET_UPGRADE_DELAY_SEC 10
2645
2646 if (hdev->reset_pending) {
2647 dev_info(&hdev->pdev->dev, "Reset pending %lu\n",
2648 hdev->reset_pending);
2649 return true;
2650 } else if ((hdev->reset_type != HNAE3_IMP_RESET) &&
2651 (hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) &
2652 BIT(HCLGE_IMP_RESET_BIT))) {
2653 dev_info(&hdev->pdev->dev,
2654 "reset failed because IMP Reset is pending\n");
2655 hclge_clear_reset_cause(hdev);
2656 return false;
2657 } else if (hdev->reset_fail_cnt < MAX_RESET_FAIL_CNT) {
2658 hdev->reset_fail_cnt++;
2659 if (is_timeout) {
2660 set_bit(hdev->reset_type, &hdev->reset_pending);
2661 dev_info(&hdev->pdev->dev,
2662 "re-schedule to wait for hw reset done\n");
2663 return true;
2664 }
2665
2666 dev_info(&hdev->pdev->dev, "Upgrade reset level\n");
2667 hclge_clear_reset_cause(hdev);
2668 mod_timer(&hdev->reset_timer,
2669 jiffies + RESET_UPGRADE_DELAY_SEC * HZ);
2670
2671 return false;
2672 }
2673
2674 hclge_clear_reset_cause(hdev);
2675 dev_err(&hdev->pdev->dev, "Reset fail!\n");
2676 return false;
2677}
2678
aa5c4f17
HT		 2679static int hclge_reset_prepare_up(struct hclge_dev *hdev)
2680{
2681 int ret = 0;
2682
2683 switch (hdev->reset_type) {
2684 case HNAE3_FUNC_RESET:
6b9a97ee
HT		 2685 /* fall through */
2686 case HNAE3_FLR_RESET:
aa5c4f17
HT		 2687 ret = hclge_set_all_vf_rst(hdev, false);
2688 break;
2689 default:
2690 break;
2691 }
2692
2693 return ret;
2694}
2695
f2f432f2
SM		 2696static void hclge_reset(struct hclge_dev *hdev)
2697{
6871af29 2698 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
65e41e7e
HT		 2699 bool is_timeout = false;
2700 int ret;
9de0b86f 2701
6871af29
JS		 2702 /* Initialize ae_dev reset status as well, in case enet layer wants to
2703 * know if device is undergoing reset
2704 */
2705 ae_dev->reset_type = hdev->reset_type;
4d60291b 2706 hdev->reset_count++;
0742ed7c 2707 hdev->last_reset_time = jiffies;
f2f432f2 2708 /* perform reset of the stack & ae device for a client */
65e41e7e
HT		 2709 ret = hclge_notify_roce_client(hdev, HNAE3_DOWN_CLIENT);
2710 if (ret)
2711 goto err_reset;
2712
aa5c4f17
HT		 2713 ret = hclge_reset_prepare_down(hdev);
2714 if (ret)
2715 goto err_reset;
2716
6d4fab39 2717 rtnl_lock();
65e41e7e
HT		 2718 ret = hclge_notify_client(hdev, HNAE3_DOWN_CLIENT);
2719 if (ret)
2720 goto err_reset_lock;
f2f432f2 2721
65e41e7e 2722 rtnl_unlock();
35d93a30 2723
65e41e7e
HT		 2724 ret = hclge_reset_prepare_wait(hdev);
2725 if (ret)
2726 goto err_reset;
cd8c5c26 2727
65e41e7e
HT		 2728 if (hclge_reset_wait(hdev)) {
2729 is_timeout = true;
2730 goto err_reset;
f2f432f2
SM		 2731 }
2732
65e41e7e
HT		 2733 ret = hclge_notify_roce_client(hdev, HNAE3_UNINIT_CLIENT);
2734 if (ret)
2735 goto err_reset;
2736
2737 rtnl_lock();
2738 ret = hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT);
2739 if (ret)
2740 goto err_reset_lock;
2741
2742 ret = hclge_reset_ae_dev(hdev->ae_dev);
2743 if (ret)
2744 goto err_reset_lock;
2745
2746 ret = hclge_notify_client(hdev, HNAE3_INIT_CLIENT);
2747 if (ret)
2748 goto err_reset_lock;
2749
2750 hclge_clear_reset_cause(hdev);
2751
aa5c4f17
HT		 2752 ret = hclge_reset_prepare_up(hdev);
2753 if (ret)
2754 goto err_reset_lock;
2755
65e41e7e
HT		 2756 ret = hclge_notify_client(hdev, HNAE3_UP_CLIENT);
2757 if (ret)
2758 goto err_reset_lock;
2759
6d4fab39 2760 rtnl_unlock();
f403a84f 2761
65e41e7e
HT		 2762 ret = hclge_notify_roce_client(hdev, HNAE3_INIT_CLIENT);
2763 if (ret)
2764 goto err_reset;
2765
2766 ret = hclge_notify_roce_client(hdev, HNAE3_UP_CLIENT);
2767 if (ret)
2768 goto err_reset;
2769
2770 return;
2771
2772err_reset_lock:
2773 rtnl_unlock();
2774err_reset:
2775 if (hclge_reset_err_handle(hdev, is_timeout))
2776 hclge_reset_task_schedule(hdev);
f2f432f2
SM		 2777}
2778
6ae4e733
SJ		 2779static void hclge_reset_event(struct pci_dev *pdev, struct hnae3_handle *handle)
2780{
2781 struct hnae3_ae_dev *ae_dev = pci_get_drvdata(pdev);
2782 struct hclge_dev *hdev = ae_dev->priv;
2783
2784 /* We might end up getting called broadly because of 2 below cases:
2785 * 1. Recoverable error was conveyed through APEI and only way to bring
2786 * normalcy is to reset.
2787 * 2. A new reset request from the stack due to timeout
2788 *
2789 * For the first case,error event might not have ae handle available.
2790 * check if this is a new reset request and we are not here just because
6d4c3981
SM		 2791 * last reset attempt did not succeed and watchdog hit us again. We will
2792 * know this if last reset request did not occur very recently (watchdog
2793 * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz)
2794 * In case of new request we reset the "reset level" to PF reset.
9de0b86f
HT		 2795 * And if it is a repeat reset request of the most recent one then we
2796 * want to make sure we throttle the reset request. Therefore, we will
2797 * not allow it again before 3*HZ times.
6d4c3981 2798 */
6ae4e733
SJ		 2799 if (!handle)
2800 handle = &hdev->vport[0].nic;
2801
0742ed7c 2802 if (time_before(jiffies, (hdev->last_reset_time + 3 * HZ)))
9de0b86f 2803 return;
720bd583 2804 else if (hdev->default_reset_request)
0742ed7c 2805 hdev->reset_level =
720bd583
HT		 2806 hclge_get_reset_level(hdev,
2807 &hdev->default_reset_request);
0742ed7c
HT		 2808 else if (time_after(jiffies, (hdev->last_reset_time + 4 * 5 * HZ)))
2809 hdev->reset_level = HNAE3_FUNC_RESET;
4ed340ab 2810
6d4c3981 2811 dev_info(&hdev->pdev->dev, "received reset event , reset type is %d",
0742ed7c 2812 hdev->reset_level);
6d4c3981
SM		 2813
2814 /* request reset & schedule reset task */
0742ed7c 2815 set_bit(hdev->reset_level, &hdev->reset_request);
6d4c3981
SM		 2816 hclge_reset_task_schedule(hdev);
2817
0742ed7c
HT		 2818 if (hdev->reset_level < HNAE3_GLOBAL_RESET)
2819 hdev->reset_level++;
4ed340ab
L		 2820}
2821
720bd583
HT		 2822static void hclge_set_def_reset_request(struct hnae3_ae_dev *ae_dev,
2823 enum hnae3_reset_type rst_type)
2824{
2825 struct hclge_dev *hdev = ae_dev->priv;
2826
2827 set_bit(rst_type, &hdev->default_reset_request);
2828}
2829
65e41e7e
HT		 2830static void hclge_reset_timer(struct timer_list *t)
2831{
2832 struct hclge_dev *hdev = from_timer(hdev, t, reset_timer);
2833
2834 dev_info(&hdev->pdev->dev,
2835 "triggering global reset in reset timer\n");
2836 set_bit(HNAE3_GLOBAL_RESET, &hdev->default_reset_request);
2837 hclge_reset_event(hdev->pdev, NULL);
2838}
2839
4ed340ab
L		 2840static void hclge_reset_subtask(struct hclge_dev *hdev)
2841{
f2f432f2
SM		 2842 /* check if there is any ongoing reset in the hardware. This status can
2843 * be checked from reset_pending. If there is then, we need to wait for
2844 * hardware to complete reset.
2845 * a. If we are able to figure out in reasonable time that hardware
2846 * has fully resetted then, we can proceed with driver, client
2847 * reset.
2848 * b. else, we can come back later to check this status so re-sched
2849 * now.
2850 */
0742ed7c 2851 hdev->last_reset_time = jiffies;
f2f432f2
SM		 2852 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending);
2853 if (hdev->reset_type != HNAE3_NONE_RESET)
2854 hclge_reset(hdev);
4ed340ab 2855
f2f432f2
SM		 2856 /* check if we got any *new* reset requests to be honored */
2857 hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request);
2858 if (hdev->reset_type != HNAE3_NONE_RESET)
2859 hclge_do_reset(hdev);
4ed340ab 2860
4ed340ab
L		 2861 hdev->reset_type = HNAE3_NONE_RESET;
2862}
2863
cb1b9f77 2864static void hclge_reset_service_task(struct work_struct *work)
466b0c00 2865{
cb1b9f77
SM		 2866 struct hclge_dev *hdev =
2867 container_of(work, struct hclge_dev, rst_service_task);
2868
2869 if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
2870 return;
2871
2872 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
2873
4ed340ab 2874 hclge_reset_subtask(hdev);
cb1b9f77
SM		 2875
2876 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
466b0c00
L		 2877}
2878
c1a81619
SM		 2879static void hclge_mailbox_service_task(struct work_struct *work)
2880{
2881 struct hclge_dev *hdev =
2882 container_of(work, struct hclge_dev, mbx_service_task);
2883
2884 if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state))
2885 return;
2886
2887 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
2888
2889 hclge_mbx_handler(hdev);
2890
2891 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
2892}
2893
46a3df9f
S		 2894static void hclge_service_task(struct work_struct *work)
2895{
2896 struct hclge_dev *hdev =
2897 container_of(work, struct hclge_dev, service_task);
2898
c5f65480
JS		 2899 if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) {
2900 hclge_update_stats_for_all(hdev);
2901 hdev->hw_stats.stats_timer = 0;
2902 }
2903
46a3df9f
S		 2904 hclge_update_speed_duplex(hdev);
2905 hclge_update_link_status(hdev);
46a3df9f
S		 2906 hclge_service_complete(hdev);
2907}
2908
46a3df9f
S		 2909struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
2910{
2911 /* VF handle has no client */
2912 if (!handle->client)
2913 return container_of(handle, struct hclge_vport, nic);
2914 else if (handle->client->type == HNAE3_CLIENT_ROCE)
2915 return container_of(handle, struct hclge_vport, roce);
2916 else
2917 return container_of(handle, struct hclge_vport, nic);
2918}
2919
2920static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
2921 struct hnae3_vector_info *vector_info)
2922{
2923 struct hclge_vport *vport = hclge_get_vport(handle);
2924 struct hnae3_vector_info *vector = vector_info;
2925 struct hclge_dev *hdev = vport->back;
2926 int alloc = 0;
2927 int i, j;
2928
2929 vector_num = min(hdev->num_msi_left, vector_num);
2930
2931 for (j = 0; j < vector_num; j++) {
2932 for (i = 1; i < hdev->num_msi; i++) {
2933 if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
2934 vector->vector = pci_irq_vector(hdev->pdev, i);
2935 vector->io_addr = hdev->hw.io_base +
2936 HCLGE_VECTOR_REG_BASE +
2937 (i - 1) * HCLGE_VECTOR_REG_OFFSET +
2938 vport->vport_id *
2939 HCLGE_VECTOR_VF_OFFSET;
2940 hdev->vector_status[i] = vport->vport_id;
887c3820 2941 hdev->vector_irq[i] = vector->vector;
46a3df9f
S		 2942
2943 vector++;
2944 alloc++;
2945
2946 break;
2947 }
2948 }
2949 }
2950 hdev->num_msi_left -= alloc;
2951 hdev->num_msi_used += alloc;
2952
2953 return alloc;
2954}
2955
2956static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
2957{
2958 int i;
2959
887c3820
SM		 2960 for (i = 0; i < hdev->num_msi; i++)
2961 if (vector == hdev->vector_irq[i])
2962 return i;
2963
46a3df9f
S		 2964 return -EINVAL;
2965}
2966
0d3e6631
YL		 2967static int hclge_put_vector(struct hnae3_handle *handle, int vector)
2968{
2969 struct hclge_vport *vport = hclge_get_vport(handle);
2970 struct hclge_dev *hdev = vport->back;
2971 int vector_id;
2972
2973 vector_id = hclge_get_vector_index(hdev, vector);
2974 if (vector_id < 0) {
2975 dev_err(&hdev->pdev->dev,
2976 "Get vector index fail. vector_id =%d\n", vector_id);
2977 return vector_id;
2978 }
2979
2980 hclge_free_vector(hdev, vector_id);
2981
2982 return 0;
2983}
2984
46a3df9f
S		 2985static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
2986{
2987 return HCLGE_RSS_KEY_SIZE;
2988}
2989
2990static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
2991{
2992 return HCLGE_RSS_IND_TBL_SIZE;
2993}
2994
46a3df9f
S		 2995static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
2996 const u8 hfunc, const u8 *key)
2997{
d44f9b63 2998 struct hclge_rss_config_cmd *req;
46a3df9f
S		 2999 struct hclge_desc desc;
3000 int key_offset;
3001 int key_size;
3002 int ret;
3003
d44f9b63 3004 req = (struct hclge_rss_config_cmd *)desc.data;
46a3df9f
S		 3005
3006 for (key_offset = 0; key_offset < 3; key_offset++) {
3007 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
3008 false);
3009
3010 req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
3011 req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
3012
3013 if (key_offset == 2)
3014 key_size =
3015 HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
3016 else
3017 key_size = HCLGE_RSS_HASH_KEY_NUM;
3018
3019 memcpy(req->hash_key,
3020 key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
3021
3022 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3023 if (ret) {
3024 dev_err(&hdev->pdev->dev,
3025 "Configure RSS config fail, status = %d\n",
3026 ret);
3027 return ret;
3028 }
3029 }
3030 return 0;
3031}
3032
89523cfa 3033static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir)
46a3df9f 3034{
d44f9b63 3035 struct hclge_rss_indirection_table_cmd *req;
46a3df9f
S		 3036 struct hclge_desc desc;
3037 int i, j;
3038 int ret;
3039
d44f9b63 3040 req = (struct hclge_rss_indirection_table_cmd *)desc.data;
46a3df9f
S		 3041
3042 for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
3043 hclge_cmd_setup_basic_desc
3044 (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
3045
a90bb9a5
YL		 3046 req->start_table_index =
3047 cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE);
3048 req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK);
46a3df9f
S		 3049
3050 for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
3051 req->rss_result[j] =
3052 indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
3053
3054 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3055 if (ret) {
3056 dev_err(&hdev->pdev->dev,
3057 "Configure rss indir table fail,status = %d\n",
3058 ret);
3059 return ret;
3060 }
3061 }
3062 return 0;
3063}
3064
3065static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
3066 u16 *tc_size, u16 *tc_offset)
3067{
d44f9b63 3068 struct hclge_rss_tc_mode_cmd *req;
46a3df9f
S		 3069 struct hclge_desc desc;
3070 int ret;
3071 int i;
3072
3073 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
d44f9b63 3074 req = (struct hclge_rss_tc_mode_cmd *)desc.data;
46a3df9f
S		 3075
3076 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
a90bb9a5
YL		 3077 u16 mode = 0;
3078
e4e87715
PL		 3079 hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1));
3080 hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M,
3081 HCLGE_RSS_TC_SIZE_S, tc_size[i]);
3082 hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M,
3083 HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
a90bb9a5
YL		 3084
3085 req->rss_tc_mode[i] = cpu_to_le16(mode);
46a3df9f
S		 3086 }
3087
3088 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3089 if (ret)
46a3df9f
S		 3090 dev_err(&hdev->pdev->dev,
3091 "Configure rss tc mode fail, status = %d\n", ret);
46a3df9f 3092
3f639907 3093 return ret;
46a3df9f
S		 3094}
3095
232fc64b
PL		 3096static void hclge_get_rss_type(struct hclge_vport *vport)
3097{
3098 if (vport->rss_tuple_sets.ipv4_tcp_en ||
3099 vport->rss_tuple_sets.ipv4_udp_en ||
3100 vport->rss_tuple_sets.ipv4_sctp_en ||
3101 vport->rss_tuple_sets.ipv6_tcp_en ||
3102 vport->rss_tuple_sets.ipv6_udp_en ||
3103 vport->rss_tuple_sets.ipv6_sctp_en)
3104 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L4;
3105 else if (vport->rss_tuple_sets.ipv4_fragment_en ||
3106 vport->rss_tuple_sets.ipv6_fragment_en)
3107 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_L3;
3108 else
3109 vport->nic.kinfo.rss_type = PKT_HASH_TYPE_NONE;
3110}
3111
46a3df9f
S		 3112static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
3113{
d44f9b63 3114 struct hclge_rss_input_tuple_cmd *req;
46a3df9f
S		 3115 struct hclge_desc desc;
3116 int ret;
3117
3118 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
3119
d44f9b63 3120 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429
YL		 3121
3122 /* Get the tuple cfg from pf */
3123 req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en;
3124 req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en;
3125 req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en;
3126 req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en;
3127 req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en;
3128 req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en;
3129 req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en;
3130 req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en;
232fc64b 3131 hclge_get_rss_type(&hdev->vport[0]);
46a3df9f 3132 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3133 if (ret)
46a3df9f
S		 3134 dev_err(&hdev->pdev->dev,
3135 "Configure rss input fail, status = %d\n", ret);
3f639907 3136 return ret;
46a3df9f
S		 3137}
3138
3139static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
3140 u8 *key, u8 *hfunc)
3141{
3142 struct hclge_vport *vport = hclge_get_vport(handle);
46a3df9f
S		 3143 int i;
3144
3145 /* Get hash algorithm */
775501a1
JS		 3146 if (hfunc) {
3147 switch (vport->rss_algo) {
3148 case HCLGE_RSS_HASH_ALGO_TOEPLITZ:
3149 *hfunc = ETH_RSS_HASH_TOP;
3150 break;
3151 case HCLGE_RSS_HASH_ALGO_SIMPLE:
3152 *hfunc = ETH_RSS_HASH_XOR;
3153 break;
3154 default:
3155 *hfunc = ETH_RSS_HASH_UNKNOWN;
3156 break;
3157 }
3158 }
46a3df9f
S		 3159
3160 /* Get the RSS Key required by the user */
3161 if (key)
3162 memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
3163
3164 /* Get indirect table */
3165 if (indir)
3166 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3167 indir[i] = vport->rss_indirection_tbl[i];
3168
3169 return 0;
3170}
3171
3172static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
3173 const u8 *key, const u8 hfunc)
3174{
3175 struct hclge_vport *vport = hclge_get_vport(handle);
3176 struct hclge_dev *hdev = vport->back;
3177 u8 hash_algo;
3178 int ret, i;
3179
3180 /* Set the RSS Hash Key if specififed by the user */
3181 if (key) {
775501a1
JS		 3182 switch (hfunc) {
3183 case ETH_RSS_HASH_TOP:
46a3df9f 3184 hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
775501a1
JS		 3185 break;
3186 case ETH_RSS_HASH_XOR:
3187 hash_algo = HCLGE_RSS_HASH_ALGO_SIMPLE;
3188 break;
3189 case ETH_RSS_HASH_NO_CHANGE:
3190 hash_algo = vport->rss_algo;
3191 break;
3192 default:
46a3df9f 3193 return -EINVAL;
775501a1
JS		 3194 }
3195
46a3df9f
S		 3196 ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
3197 if (ret)
3198 return ret;
89523cfa
YL		 3199
3200 /* Update the shadow RSS key with user specified qids */
3201 memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
3202 vport->rss_algo = hash_algo;
46a3df9f
S		 3203 }
3204
3205 /* Update the shadow RSS table with user specified qids */
3206 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3207 vport->rss_indirection_tbl[i] = indir[i];
3208
3209 /* Update the hardware */
89523cfa 3210 return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl);
46a3df9f
S		 3211}
3212
f7db940a
L		 3213static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc)
3214{
3215 u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0;
3216
3217 if (nfc->data & RXH_L4_B_2_3)
3218 hash_sets |= HCLGE_D_PORT_BIT;
3219 else
3220 hash_sets &= ~HCLGE_D_PORT_BIT;
3221
3222 if (nfc->data & RXH_IP_SRC)
3223 hash_sets |= HCLGE_S_IP_BIT;
3224 else
3225 hash_sets &= ~HCLGE_S_IP_BIT;
3226
3227 if (nfc->data & RXH_IP_DST)
3228 hash_sets |= HCLGE_D_IP_BIT;
3229 else
3230 hash_sets &= ~HCLGE_D_IP_BIT;
3231
3232 if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW)
3233 hash_sets |= HCLGE_V_TAG_BIT;
3234
3235 return hash_sets;
3236}
3237
3238static int hclge_set_rss_tuple(struct hnae3_handle *handle,
3239 struct ethtool_rxnfc *nfc)
3240{
3241 struct hclge_vport *vport = hclge_get_vport(handle);
3242 struct hclge_dev *hdev = vport->back;
3243 struct hclge_rss_input_tuple_cmd *req;
3244 struct hclge_desc desc;
3245 u8 tuple_sets;
3246 int ret;
3247
3248 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST |
3249 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3250 return -EINVAL;
3251
3252 req = (struct hclge_rss_input_tuple_cmd *)desc.data;
6f2af429 3253 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
f7db940a 3254
6f2af429
YL		 3255 req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en;
3256 req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en;
3257 req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en;
3258 req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en;
3259 req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en;
3260 req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en;
3261 req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en;
3262 req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en;
f7db940a
L		 3263
3264 tuple_sets = hclge_get_rss_hash_bits(nfc);
3265 switch (nfc->flow_type) {
3266 case TCP_V4_FLOW:
3267 req->ipv4_tcp_en = tuple_sets;
3268 break;
3269 case TCP_V6_FLOW:
3270 req->ipv6_tcp_en = tuple_sets;
3271 break;
3272 case UDP_V4_FLOW:
3273 req->ipv4_udp_en = tuple_sets;
3274 break;
3275 case UDP_V6_FLOW:
3276 req->ipv6_udp_en = tuple_sets;
3277 break;
3278 case SCTP_V4_FLOW:
3279 req->ipv4_sctp_en = tuple_sets;
3280 break;
3281 case SCTP_V6_FLOW:
3282 if ((nfc->data & RXH_L4_B_0_1) ||
3283 (nfc->data & RXH_L4_B_2_3))
3284 return -EINVAL;
3285
3286 req->ipv6_sctp_en = tuple_sets;
3287 break;
3288 case IPV4_FLOW:
3289 req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3290 break;
3291 case IPV6_FLOW:
3292 req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
3293 break;
3294 default:
3295 return -EINVAL;
3296 }
3297
3298 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6f2af429 3299 if (ret) {
f7db940a
L		 3300 dev_err(&hdev->pdev->dev,
3301 "Set rss tuple fail, status = %d\n", ret);
6f2af429
YL		 3302 return ret;
3303 }
f7db940a 3304
6f2af429
YL		 3305 vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en;
3306 vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en;
3307 vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en;
3308 vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en;
3309 vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en;
3310 vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en;
3311 vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en;
3312 vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en;
232fc64b 3313 hclge_get_rss_type(vport);
6f2af429 3314 return 0;
f7db940a
L		 3315}
3316
07d29954
L		 3317static int hclge_get_rss_tuple(struct hnae3_handle *handle,
3318 struct ethtool_rxnfc *nfc)
3319{
3320 struct hclge_vport *vport = hclge_get_vport(handle);
07d29954 3321 u8 tuple_sets;
07d29954
L		 3322
3323 nfc->data = 0;
3324
07d29954
L		 3325 switch (nfc->flow_type) {
3326 case TCP_V4_FLOW:
6f2af429 3327 tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en;
07d29954
L		 3328 break;
3329 case UDP_V4_FLOW:
6f2af429 3330 tuple_sets = vport->rss_tuple_sets.ipv4_udp_en;
07d29954
L		 3331 break;
3332 case TCP_V6_FLOW:
6f2af429 3333 tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en;
07d29954
L		 3334 break;
3335 case UDP_V6_FLOW:
6f2af429 3336 tuple_sets = vport->rss_tuple_sets.ipv6_udp_en;
07d29954
L		 3337 break;
3338 case SCTP_V4_FLOW:
6f2af429 3339 tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en;
07d29954
L		 3340 break;
3341 case SCTP_V6_FLOW:
6f2af429 3342 tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en;
07d29954
L		 3343 break;
3344 case IPV4_FLOW:
3345 case IPV6_FLOW:
3346 tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT;
3347 break;
3348 default:
3349 return -EINVAL;
3350 }
3351
3352 if (!tuple_sets)
3353 return 0;
3354
3355 if (tuple_sets & HCLGE_D_PORT_BIT)
3356 nfc->data |= RXH_L4_B_2_3;
3357 if (tuple_sets & HCLGE_S_PORT_BIT)
3358 nfc->data |= RXH_L4_B_0_1;
3359 if (tuple_sets & HCLGE_D_IP_BIT)
3360 nfc->data |= RXH_IP_DST;
3361 if (tuple_sets & HCLGE_S_IP_BIT)
3362 nfc->data |= RXH_IP_SRC;
3363
3364 return 0;
3365}
3366
46a3df9f
S		 3367static int hclge_get_tc_size(struct hnae3_handle *handle)
3368{
3369 struct hclge_vport *vport = hclge_get_vport(handle);
3370 struct hclge_dev *hdev = vport->back;
3371
3372 return hdev->rss_size_max;
3373}
3374
77f255c1 3375int hclge_rss_init_hw(struct hclge_dev *hdev)
46a3df9f 3376{
46a3df9f 3377 struct hclge_vport *vport = hdev->vport;
268f5dfa
YL		 3378 u8 *rss_indir = vport[0].rss_indirection_tbl;
3379 u16 rss_size = vport[0].alloc_rss_size;
3380 u8 *key = vport[0].rss_hash_key;
3381 u8 hfunc = vport[0].rss_algo;
46a3df9f 3382 u16 tc_offset[HCLGE_MAX_TC_NUM];
46a3df9f
S		 3383 u16 tc_valid[HCLGE_MAX_TC_NUM];
3384 u16 tc_size[HCLGE_MAX_TC_NUM];
268f5dfa
YL		 3385 u16 roundup_size;
3386 int i, ret;
68ece54e 3387
46a3df9f
S		 3388 ret = hclge_set_rss_indir_table(hdev, rss_indir);
3389 if (ret)
268f5dfa 3390 return ret;
46a3df9f 3391
46a3df9f
S		 3392 ret = hclge_set_rss_algo_key(hdev, hfunc, key);
3393 if (ret)
268f5dfa 3394 return ret;
46a3df9f
S		 3395
3396 ret = hclge_set_rss_input_tuple(hdev);
3397 if (ret)
268f5dfa 3398 return ret;
46a3df9f 3399
68ece54e
YL		 3400 /* Each TC have the same queue size, and tc_size set to hardware is
3401 * the log2 of roundup power of two of rss_size, the acutal queue
3402 * size is limited by indirection table.
3403 */
3404 if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
3405 dev_err(&hdev->pdev->dev,
3406 "Configure rss tc size failed, invalid TC_SIZE = %d\n",
3407 rss_size);
268f5dfa 3408 return -EINVAL;
68ece54e
YL		 3409 }
3410
3411 roundup_size = roundup_pow_of_two(rss_size);
3412 roundup_size = ilog2(roundup_size);
3413
46a3df9f 3414 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
68ece54e 3415 tc_valid[i] = 0;
46a3df9f 3416
68ece54e
YL		 3417 if (!(hdev->hw_tc_map & BIT(i)))
3418 continue;
3419
3420 tc_valid[i] = 1;
3421 tc_size[i] = roundup_size;
3422 tc_offset[i] = rss_size * i;
46a3df9f 3423 }
68ece54e 3424
268f5dfa
YL		 3425 return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
3426}
46a3df9f 3427
268f5dfa
YL		 3428void hclge_rss_indir_init_cfg(struct hclge_dev *hdev)
3429{
3430 struct hclge_vport *vport = hdev->vport;
3431 int i, j;
46a3df9f 3432
268f5dfa
YL		 3433 for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
3434 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
3435 vport[j].rss_indirection_tbl[i] =
3436 i % vport[j].alloc_rss_size;
3437 }
3438}
3439
3440static void hclge_rss_init_cfg(struct hclge_dev *hdev)
3441{
3442 struct hclge_vport *vport = hdev->vport;
3443 int i;
3444
268f5dfa
YL		 3445 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
3446 vport[i].rss_tuple_sets.ipv4_tcp_en =
3447 HCLGE_RSS_INPUT_TUPLE_OTHER;
3448 vport[i].rss_tuple_sets.ipv4_udp_en =
3449 HCLGE_RSS_INPUT_TUPLE_OTHER;
3450 vport[i].rss_tuple_sets.ipv4_sctp_en =
3451 HCLGE_RSS_INPUT_TUPLE_SCTP;
3452 vport[i].rss_tuple_sets.ipv4_fragment_en =
3453 HCLGE_RSS_INPUT_TUPLE_OTHER;
3454 vport[i].rss_tuple_sets.ipv6_tcp_en =
3455 HCLGE_RSS_INPUT_TUPLE_OTHER;
3456 vport[i].rss_tuple_sets.ipv6_udp_en =
3457 HCLGE_RSS_INPUT_TUPLE_OTHER;
3458 vport[i].rss_tuple_sets.ipv6_sctp_en =
3459 HCLGE_RSS_INPUT_TUPLE_SCTP;
3460 vport[i].rss_tuple_sets.ipv6_fragment_en =
3461 HCLGE_RSS_INPUT_TUPLE_OTHER;
3462
3463 vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
ea739c90
FL		 3464
3465 netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE);
268f5dfa
YL		 3466 }
3467
3468 hclge_rss_indir_init_cfg(hdev);
46a3df9f
S		 3469}
3470
84e095d6
SM		 3471int hclge_bind_ring_with_vector(struct hclge_vport *vport,
3472 int vector_id, bool en,
3473 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3474{
3475 struct hclge_dev *hdev = vport->back;
46a3df9f
S		 3476 struct hnae3_ring_chain_node *node;
3477 struct hclge_desc desc;
84e095d6
SM		 3478 struct hclge_ctrl_vector_chain_cmd *req
3479 = (struct hclge_ctrl_vector_chain_cmd *)desc.data;
3480 enum hclge_cmd_status status;
3481 enum hclge_opcode_type op;
3482 u16 tqp_type_and_id;
46a3df9f
S		 3483 int i;
3484
84e095d6
SM		 3485 op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR;
3486 hclge_cmd_setup_basic_desc(&desc, op, false);
46a3df9f
S		 3487 req->int_vector_id = vector_id;
3488
3489 i = 0;
3490 for (node = ring_chain; node; node = node->next) {
84e095d6 3491 tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]);
e4e87715
PL		 3492 hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M,
3493 HCLGE_INT_TYPE_S,
3494 hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B));
3495 hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M,
3496 HCLGE_TQP_ID_S, node->tqp_index);
3497 hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M,
3498 HCLGE_INT_GL_IDX_S,
3499 hnae3_get_field(node->int_gl_idx,
3500 HNAE3_RING_GL_IDX_M,
3501 HNAE3_RING_GL_IDX_S));
84e095d6 3502 req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id);
46a3df9f
S		 3503 if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) {
3504 req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD;
84e095d6 3505 req->vfid = vport->vport_id;
46a3df9f 3506
84e095d6
SM		 3507 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3508 if (status) {
46a3df9f
S		 3509 dev_err(&hdev->pdev->dev,
3510 "Map TQP fail, status is %d.\n",
84e095d6
SM		 3511 status);
3512 return -EIO;
46a3df9f
S		 3513 }
3514 i = 0;
3515
3516 hclge_cmd_setup_basic_desc(&desc,
84e095d6 3517 op,
46a3df9f
S		 3518 false);
3519 req->int_vector_id = vector_id;
3520 }
3521 }
3522
3523 if (i > 0) {
3524 req->int_cause_num = i;
84e095d6
SM		 3525 req->vfid = vport->vport_id;
3526 status = hclge_cmd_send(&hdev->hw, &desc, 1);
3527 if (status) {
46a3df9f 3528 dev_err(&hdev->pdev->dev,
84e095d6
SM		 3529 "Map TQP fail, status is %d.\n", status);
3530 return -EIO;
46a3df9f
S		 3531 }
3532 }
3533
3534 return 0;
3535}
3536
84e095d6
SM		 3537static int hclge_map_ring_to_vector(struct hnae3_handle *handle,
3538 int vector,
3539 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3540{
3541 struct hclge_vport *vport = hclge_get_vport(handle);
3542 struct hclge_dev *hdev = vport->back;
3543 int vector_id;
3544
3545 vector_id = hclge_get_vector_index(hdev, vector);
3546 if (vector_id < 0) {
3547 dev_err(&hdev->pdev->dev,
84e095d6 3548 "Get vector index fail. vector_id =%d\n", vector_id);
46a3df9f
S		 3549 return vector_id;
3550 }
3551
84e095d6 3552 return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain);
46a3df9f
S		 3553}
3554
84e095d6
SM		 3555static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle,
3556 int vector,
3557 struct hnae3_ring_chain_node *ring_chain)
46a3df9f
S		 3558{
3559 struct hclge_vport *vport = hclge_get_vport(handle);
3560 struct hclge_dev *hdev = vport->back;
84e095d6 3561 int vector_id, ret;
46a3df9f 3562
b50ae26c
PL		 3563 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
3564 return 0;
3565
46a3df9f
S		 3566 vector_id = hclge_get_vector_index(hdev, vector);
3567 if (vector_id < 0) {
3568 dev_err(&handle->pdev->dev,
3569 "Get vector index fail. ret =%d\n", vector_id);
3570 return vector_id;
3571 }
3572
84e095d6 3573 ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain);
0d3e6631 3574 if (ret)
84e095d6
SM		 3575 dev_err(&handle->pdev->dev,
3576 "Unmap ring from vector fail. vectorid=%d, ret =%d\n",
3577 vector_id,
3578 ret);
46a3df9f 3579
0d3e6631 3580 return ret;
46a3df9f
S		 3581}
3582
3583int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
3584 struct hclge_promisc_param *param)
3585{
d44f9b63 3586 struct hclge_promisc_cfg_cmd *req;
46a3df9f
S		 3587 struct hclge_desc desc;
3588 int ret;
3589
3590 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false);
3591
d44f9b63 3592 req = (struct hclge_promisc_cfg_cmd *)desc.data;
46a3df9f 3593 req->vf_id = param->vf_id;
96c0e861
PL		 3594
3595 /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on
3596 * pdev revision(0x20), new revision support them. The
3597 * value of this two fields will not return error when driver
3598 * send command to fireware in revision(0x20).
3599 */
3600 req->flag = (param->enable << HCLGE_PROMISC_EN_B) |
3601 HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B;
46a3df9f
S		 3602
3603 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 3604 if (ret)
46a3df9f
S		 3605 dev_err(&hdev->pdev->dev,
3606 "Set promisc mode fail, status is %d.\n", ret);
3f639907
JS		 3607
3608 return ret;
46a3df9f
S		 3609}
3610
3611void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc,
3612 bool en_mc, bool en_bc, int vport_id)
3613{
3614 if (!param)
3615 return;
3616
3617 memset(param, 0, sizeof(struct hclge_promisc_param));
3618 if (en_uc)
3619 param->enable = HCLGE_PROMISC_EN_UC;
3620 if (en_mc)
3621 param->enable |= HCLGE_PROMISC_EN_MC;
3622 if (en_bc)
3623 param->enable |= HCLGE_PROMISC_EN_BC;
3624 param->vf_id = vport_id;
3625}
3626
7fa6be4f
HT		 3627static int hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc,
3628 bool en_mc_pmc)
46a3df9f
S		 3629{
3630 struct hclge_vport *vport = hclge_get_vport(handle);
3631 struct hclge_dev *hdev = vport->back;
3632 struct hclge_promisc_param param;
3633
3b75c3df
PL		 3634 hclge_promisc_param_init(&param, en_uc_pmc, en_mc_pmc, true,
3635 vport->vport_id);
7fa6be4f 3636 return hclge_cmd_set_promisc_mode(hdev, &param);
46a3df9f
S		 3637}
3638
d695964d
JS		 3639static int hclge_get_fd_mode(struct hclge_dev *hdev, u8 *fd_mode)
3640{
3641 struct hclge_get_fd_mode_cmd *req;
3642 struct hclge_desc desc;
3643 int ret;
3644
3645 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_MODE_CTRL, true);
3646
3647 req = (struct hclge_get_fd_mode_cmd *)desc.data;
3648
3649 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3650 if (ret) {
3651 dev_err(&hdev->pdev->dev, "get fd mode fail, ret=%d\n", ret);
3652 return ret;
3653 }
3654
3655 *fd_mode = req->mode;
3656
3657 return ret;
3658}
3659
3660static int hclge_get_fd_allocation(struct hclge_dev *hdev,
3661 u32 *stage1_entry_num,
3662 u32 *stage2_entry_num,
3663 u16 *stage1_counter_num,
3664 u16 *stage2_counter_num)
3665{
3666 struct hclge_get_fd_allocation_cmd *req;
3667 struct hclge_desc desc;
3668 int ret;
3669
3670 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_GET_ALLOCATION, true);
3671
3672 req = (struct hclge_get_fd_allocation_cmd *)desc.data;
3673
3674 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3675 if (ret) {
3676 dev_err(&hdev->pdev->dev, "query fd allocation fail, ret=%d\n",
3677 ret);
3678 return ret;
3679 }
3680
3681 *stage1_entry_num = le32_to_cpu(req->stage1_entry_num);
3682 *stage2_entry_num = le32_to_cpu(req->stage2_entry_num);
3683 *stage1_counter_num = le16_to_cpu(req->stage1_counter_num);
3684 *stage2_counter_num = le16_to_cpu(req->stage2_counter_num);
3685
3686 return ret;
3687}
3688
3689static int hclge_set_fd_key_config(struct hclge_dev *hdev, int stage_num)
3690{
3691 struct hclge_set_fd_key_config_cmd *req;
3692 struct hclge_fd_key_cfg *stage;
3693 struct hclge_desc desc;
3694 int ret;
3695
3696 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_KEY_CONFIG, false);
3697
3698 req = (struct hclge_set_fd_key_config_cmd *)desc.data;
3699 stage = &hdev->fd_cfg.key_cfg[stage_num];
3700 req->stage = stage_num;
3701 req->key_select = stage->key_sel;
3702 req->inner_sipv6_word_en = stage->inner_sipv6_word_en;
3703 req->inner_dipv6_word_en = stage->inner_dipv6_word_en;
3704 req->outer_sipv6_word_en = stage->outer_sipv6_word_en;
3705 req->outer_dipv6_word_en = stage->outer_dipv6_word_en;
3706 req->tuple_mask = cpu_to_le32(~stage->tuple_active);
3707 req->meta_data_mask = cpu_to_le32(~stage->meta_data_active);
3708
3709 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3710 if (ret)
3711 dev_err(&hdev->pdev->dev, "set fd key fail, ret=%d\n", ret);
3712
3713 return ret;
3714}
3715
3716static int hclge_init_fd_config(struct hclge_dev *hdev)
3717{
3718#define LOW_2_WORDS 0x03
3719 struct hclge_fd_key_cfg *key_cfg;
3720 int ret;
3721
3722 if (!hnae3_dev_fd_supported(hdev))
3723 return 0;
3724
3725 ret = hclge_get_fd_mode(hdev, &hdev->fd_cfg.fd_mode);
3726 if (ret)
3727 return ret;
3728
3729 switch (hdev->fd_cfg.fd_mode) {
3730 case HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1:
3731 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH;
3732 break;
3733 case HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1:
3734 hdev->fd_cfg.max_key_length = MAX_KEY_LENGTH / 2;
3735 break;
3736 default:
3737 dev_err(&hdev->pdev->dev,
3738 "Unsupported flow director mode %d\n",
3739 hdev->fd_cfg.fd_mode);
3740 return -EOPNOTSUPP;
3741 }
3742
3743 hdev->fd_cfg.fd_en = true;
3744 hdev->fd_cfg.proto_support =
3745 TCP_V4_FLOW | UDP_V4_FLOW | SCTP_V4_FLOW | TCP_V6_FLOW |
3746 UDP_V6_FLOW | SCTP_V6_FLOW | IPV4_USER_FLOW | IPV6_USER_FLOW;
3747 key_cfg = &hdev->fd_cfg.key_cfg[HCLGE_FD_STAGE_1];
3748 key_cfg->key_sel = HCLGE_FD_KEY_BASE_ON_TUPLE,
3749 key_cfg->inner_sipv6_word_en = LOW_2_WORDS;
3750 key_cfg->inner_dipv6_word_en = LOW_2_WORDS;
3751 key_cfg->outer_sipv6_word_en = 0;
3752 key_cfg->outer_dipv6_word_en = 0;
3753
3754 key_cfg->tuple_active = BIT(INNER_VLAN_TAG_FST) | BIT(INNER_ETH_TYPE) |
3755 BIT(INNER_IP_PROTO) | BIT(INNER_IP_TOS) |
3756 BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
3757 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
3758
3759 /* If use max 400bit key, we can support tuples for ether type */
3760 if (hdev->fd_cfg.max_key_length == MAX_KEY_LENGTH) {
3761 hdev->fd_cfg.proto_support |= ETHER_FLOW;
3762 key_cfg->tuple_active |=
3763 BIT(INNER_DST_MAC) | BIT(INNER_SRC_MAC);
3764 }
3765
3766 /* roce_type is used to filter roce frames
3767 * dst_vport is used to specify the rule
3768 */
3769 key_cfg->meta_data_active = BIT(ROCE_TYPE) | BIT(DST_VPORT);
3770
3771 ret = hclge_get_fd_allocation(hdev,
3772 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1],
3773 &hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_2],
3774 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_1],
3775 &hdev->fd_cfg.cnt_num[HCLGE_FD_STAGE_2]);
3776 if (ret)
3777 return ret;
3778
3779 return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
3780}
3781
11732868
JS		 3782static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
3783 int loc, u8 *key, bool is_add)
3784{
3785 struct hclge_fd_tcam_config_1_cmd *req1;
3786 struct hclge_fd_tcam_config_2_cmd *req2;
3787 struct hclge_fd_tcam_config_3_cmd *req3;
3788 struct hclge_desc desc[3];
3789 int ret;
3790
3791 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
3792 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3793 hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
3794 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
3795 hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
3796
3797 req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
3798 req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
3799 req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
3800
3801 req1->stage = stage;
3802 req1->xy_sel = sel_x ? 1 : 0;
3803 hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
3804 req1->index = cpu_to_le32(loc);
3805 req1->entry_vld = sel_x ? is_add : 0;
3806
3807 if (key) {
3808 memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
3809 memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
3810 sizeof(req2->tcam_data));
3811 memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
3812 sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
3813 }
3814
3815 ret = hclge_cmd_send(&hdev->hw, desc, 3);
3816 if (ret)
3817 dev_err(&hdev->pdev->dev,
3818 "config tcam key fail, ret=%d\n",
3819 ret);
3820
3821 return ret;
3822}
3823
3824static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
3825 struct hclge_fd_ad_data *action)
3826{
3827 struct hclge_fd_ad_config_cmd *req;
3828 struct hclge_desc desc;
3829 u64 ad_data = 0;
3830 int ret;
3831
3832 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
3833
3834 req = (struct hclge_fd_ad_config_cmd *)desc.data;
3835 req->index = cpu_to_le32(loc);
3836 req->stage = stage;
3837
3838 hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
3839 action->write_rule_id_to_bd);
3840 hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
3841 action->rule_id);
3842 ad_data <<= 32;
3843 hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
3844 hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
3845 action->forward_to_direct_queue);
3846 hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
3847 action->queue_id);
3848 hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
3849 hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
3850 HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
3851 hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
3852 hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
3853 action->counter_id);
3854
3855 req->ad_data = cpu_to_le64(ad_data);
3856 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3857 if (ret)
3858 dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
3859
3860 return ret;
3861}
3862
3863static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
3864 struct hclge_fd_rule *rule)
3865{
3866 u16 tmp_x_s, tmp_y_s;
3867 u32 tmp_x_l, tmp_y_l;
3868 int i;
3869
3870 if (rule->unused_tuple & tuple_bit)
3871 return true;
3872
3873 switch (tuple_bit) {
3874 case 0:
3875 return false;
3876 case BIT(INNER_DST_MAC):
3877 for (i = 0; i < 6; i++) {
3878 calc_x(key_x[5 - i], rule->tuples.dst_mac[i],
3879 rule->tuples_mask.dst_mac[i]);
3880 calc_y(key_y[5 - i], rule->tuples.dst_mac[i],
3881 rule->tuples_mask.dst_mac[i]);
3882 }
3883
3884 return true;
3885 case BIT(INNER_SRC_MAC):
3886 for (i = 0; i < 6; i++) {
3887 calc_x(key_x[5 - i], rule->tuples.src_mac[i],
3888 rule->tuples.src_mac[i]);
3889 calc_y(key_y[5 - i], rule->tuples.src_mac[i],
3890 rule->tuples.src_mac[i]);
3891 }
3892
3893 return true;
3894 case BIT(INNER_VLAN_TAG_FST):
3895 calc_x(tmp_x_s, rule->tuples.vlan_tag1,
3896 rule->tuples_mask.vlan_tag1);
3897 calc_y(tmp_y_s, rule->tuples.vlan_tag1,
3898 rule->tuples_mask.vlan_tag1);
3899 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3900 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3901
3902 return true;
3903 case BIT(INNER_ETH_TYPE):
3904 calc_x(tmp_x_s, rule->tuples.ether_proto,
3905 rule->tuples_mask.ether_proto);
3906 calc_y(tmp_y_s, rule->tuples.ether_proto,
3907 rule->tuples_mask.ether_proto);
3908 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3909 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3910
3911 return true;
3912 case BIT(INNER_IP_TOS):
3913 calc_x(*key_x, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
3914 calc_y(*key_y, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
3915
3916 return true;
3917 case BIT(INNER_IP_PROTO):
3918 calc_x(*key_x, rule->tuples.ip_proto,
3919 rule->tuples_mask.ip_proto);
3920 calc_y(*key_y, rule->tuples.ip_proto,
3921 rule->tuples_mask.ip_proto);
3922
3923 return true;
3924 case BIT(INNER_SRC_IP):
3925 calc_x(tmp_x_l, rule->tuples.src_ip[3],
3926 rule->tuples_mask.src_ip[3]);
3927 calc_y(tmp_y_l, rule->tuples.src_ip[3],
3928 rule->tuples_mask.src_ip[3]);
3929 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
3930 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
3931
3932 return true;
3933 case BIT(INNER_DST_IP):
3934 calc_x(tmp_x_l, rule->tuples.dst_ip[3],
3935 rule->tuples_mask.dst_ip[3]);
3936 calc_y(tmp_y_l, rule->tuples.dst_ip[3],
3937 rule->tuples_mask.dst_ip[3]);
3938 *(__le32 *)key_x = cpu_to_le32(tmp_x_l);
3939 *(__le32 *)key_y = cpu_to_le32(tmp_y_l);
3940
3941 return true;
3942 case BIT(INNER_SRC_PORT):
3943 calc_x(tmp_x_s, rule->tuples.src_port,
3944 rule->tuples_mask.src_port);
3945 calc_y(tmp_y_s, rule->tuples.src_port,
3946 rule->tuples_mask.src_port);
3947 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3948 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3949
3950 return true;
3951 case BIT(INNER_DST_PORT):
3952 calc_x(tmp_x_s, rule->tuples.dst_port,
3953 rule->tuples_mask.dst_port);
3954 calc_y(tmp_y_s, rule->tuples.dst_port,
3955 rule->tuples_mask.dst_port);
3956 *(__le16 *)key_x = cpu_to_le16(tmp_x_s);
3957 *(__le16 *)key_y = cpu_to_le16(tmp_y_s);
3958
3959 return true;
3960 default:
3961 return false;
3962 }
3963}
3964
3965static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
3966 u8 vf_id, u8 network_port_id)
3967{
3968 u32 port_number = 0;
3969
3970 if (port_type == HOST_PORT) {
3971 hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
3972 pf_id);
3973 hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
3974 vf_id);
3975 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
3976 } else {
3977 hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
3978 HCLGE_NETWORK_PORT_ID_S, network_port_id);
3979 hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
3980 }
3981
3982 return port_number;
3983}
3984
3985static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
3986 __le32 *key_x, __le32 *key_y,
3987 struct hclge_fd_rule *rule)
3988{
3989 u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
3990 u8 cur_pos = 0, tuple_size, shift_bits;
3991 int i;
3992
3993 for (i = 0; i < MAX_META_DATA; i++) {
3994 tuple_size = meta_data_key_info[i].key_length;
3995 tuple_bit = key_cfg->meta_data_active & BIT(i);
3996
3997 switch (tuple_bit) {
3998 case BIT(ROCE_TYPE):
3999 hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
4000 cur_pos += tuple_size;
4001 break;
4002 case BIT(DST_VPORT):
4003 port_number = hclge_get_port_number(HOST_PORT, 0,
4004 rule->vf_id, 0);
4005 hnae3_set_field(meta_data,
4006 GENMASK(cur_pos + tuple_size, cur_pos),
4007 cur_pos, port_number);
4008 cur_pos += tuple_size;
4009 break;
4010 default:
4011 break;
4012 }
4013 }
4014
4015 calc_x(tmp_x, meta_data, 0xFFFFFFFF);
4016 calc_y(tmp_y, meta_data, 0xFFFFFFFF);
4017 shift_bits = sizeof(meta_data) * 8 - cur_pos;
4018
4019 *key_x = cpu_to_le32(tmp_x << shift_bits);
4020 *key_y = cpu_to_le32(tmp_y << shift_bits);
4021}
4022
4023/* A complete key is combined with meta data key and tuple key.
4024 * Meta data key is stored at the MSB region, and tuple key is stored at
4025 * the LSB region, unused bits will be filled 0.
4026 */
4027static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
4028 struct hclge_fd_rule *rule)
4029{
4030 struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
4031 u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
4032 u8 *cur_key_x, *cur_key_y;
4033 int i, ret, tuple_size;
4034 u8 meta_data_region;
4035
4036 memset(key_x, 0, sizeof(key_x));
4037 memset(key_y, 0, sizeof(key_y));
4038 cur_key_x = key_x;
4039 cur_key_y = key_y;
4040
4041 for (i = 0 ; i < MAX_TUPLE; i++) {
4042 bool tuple_valid;
4043 u32 check_tuple;
4044
4045 tuple_size = tuple_key_info[i].key_length / 8;
4046 check_tuple = key_cfg->tuple_active & BIT(i);
4047
4048 tuple_valid = hclge_fd_convert_tuple(check_tuple, cur_key_x,
4049 cur_key_y, rule);
4050 if (tuple_valid) {
4051 cur_key_x += tuple_size;
4052 cur_key_y += tuple_size;
4053 }
4054 }
4055
4056 meta_data_region = hdev->fd_cfg.max_key_length / 8 -
4057 MAX_META_DATA_LENGTH / 8;
4058
4059 hclge_fd_convert_meta_data(key_cfg,
4060 (__le32 *)(key_x + meta_data_region),
4061 (__le32 *)(key_y + meta_data_region),
4062 rule);
4063
4064 ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
4065 true);
4066 if (ret) {
4067 dev_err(&hdev->pdev->dev,
4068 "fd key_y config fail, loc=%d, ret=%d\n",
4069 rule->queue_id, ret);
4070 return ret;
4071 }
4072
4073 ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
4074 true);
4075 if (ret)
4076 dev_err(&hdev->pdev->dev,
4077 "fd key_x config fail, loc=%d, ret=%d\n",
4078 rule->queue_id, ret);
4079 return ret;
4080}
4081
4082static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
4083 struct hclge_fd_rule *rule)
4084{
4085 struct hclge_fd_ad_data ad_data;
4086
4087 ad_data.ad_id = rule->location;
4088
4089 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
4090 ad_data.drop_packet = true;
4091 ad_data.forward_to_direct_queue = false;
4092 ad_data.queue_id = 0;
4093 } else {
4094 ad_data.drop_packet = false;
4095 ad_data.forward_to_direct_queue = true;
4096 ad_data.queue_id = rule->queue_id;
4097 }
4098
4099 ad_data.use_counter = false;
4100 ad_data.counter_id = 0;
4101
4102 ad_data.use_next_stage = false;
4103 ad_data.next_input_key = 0;
4104
4105 ad_data.write_rule_id_to_bd = true;
4106 ad_data.rule_id = rule->location;
4107
4108 return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
4109}
4110
dd74f815
JS		 4111static int hclge_fd_check_spec(struct hclge_dev *hdev,
4112 struct ethtool_rx_flow_spec *fs, u32 *unused)
4113{
4114 struct ethtool_tcpip4_spec *tcp_ip4_spec;
4115 struct ethtool_usrip4_spec *usr_ip4_spec;
4116 struct ethtool_tcpip6_spec *tcp_ip6_spec;
4117 struct ethtool_usrip6_spec *usr_ip6_spec;
4118 struct ethhdr *ether_spec;
4119
4120 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4121 return -EINVAL;
4122
4123 if (!(fs->flow_type & hdev->fd_cfg.proto_support))
4124 return -EOPNOTSUPP;
4125
4126 if ((fs->flow_type & FLOW_EXT) &&
4127 (fs->h_ext.data[0] != 0 || fs->h_ext.data[1] != 0)) {
4128 dev_err(&hdev->pdev->dev, "user-def bytes are not supported\n");
4129 return -EOPNOTSUPP;
4130 }
4131
4132 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4133 case SCTP_V4_FLOW:
4134 case TCP_V4_FLOW:
4135 case UDP_V4_FLOW:
4136 tcp_ip4_spec = &fs->h_u.tcp_ip4_spec;
4137 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC);
4138
4139 if (!tcp_ip4_spec->ip4src)
4140 *unused |= BIT(INNER_SRC_IP);
4141
4142 if (!tcp_ip4_spec->ip4dst)
4143 *unused |= BIT(INNER_DST_IP);
4144
4145 if (!tcp_ip4_spec->psrc)
4146 *unused |= BIT(INNER_SRC_PORT);
4147
4148 if (!tcp_ip4_spec->pdst)
4149 *unused |= BIT(INNER_DST_PORT);
4150
4151 if (!tcp_ip4_spec->tos)
4152 *unused |= BIT(INNER_IP_TOS);
4153
4154 break;
4155 case IP_USER_FLOW:
4156 usr_ip4_spec = &fs->h_u.usr_ip4_spec;
4157 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4158 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT);
4159
4160 if (!usr_ip4_spec->ip4src)
4161 *unused |= BIT(INNER_SRC_IP);
4162
4163 if (!usr_ip4_spec->ip4dst)
4164 *unused |= BIT(INNER_DST_IP);
4165
4166 if (!usr_ip4_spec->tos)
4167 *unused |= BIT(INNER_IP_TOS);
4168
4169 if (!usr_ip4_spec->proto)
4170 *unused |= BIT(INNER_IP_PROTO);
4171
4172 if (usr_ip4_spec->l4_4_bytes)
4173 return -EOPNOTSUPP;
4174
4175 if (usr_ip4_spec->ip_ver != ETH_RX_NFC_IP4)
4176 return -EOPNOTSUPP;
4177
4178 break;
4179 case SCTP_V6_FLOW:
4180 case TCP_V6_FLOW:
4181 case UDP_V6_FLOW:
4182 tcp_ip6_spec = &fs->h_u.tcp_ip6_spec;
4183 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4184 BIT(INNER_IP_TOS);
4185
4186 if (!tcp_ip6_spec->ip6src[0] && !tcp_ip6_spec->ip6src[1] &&
4187 !tcp_ip6_spec->ip6src[2] && !tcp_ip6_spec->ip6src[3])
4188 *unused |= BIT(INNER_SRC_IP);
4189
4190 if (!tcp_ip6_spec->ip6dst[0] && !tcp_ip6_spec->ip6dst[1] &&
4191 !tcp_ip6_spec->ip6dst[2] && !tcp_ip6_spec->ip6dst[3])
4192 *unused |= BIT(INNER_DST_IP);
4193
4194 if (!tcp_ip6_spec->psrc)
4195 *unused |= BIT(INNER_SRC_PORT);
4196
4197 if (!tcp_ip6_spec->pdst)
4198 *unused |= BIT(INNER_DST_PORT);
4199
4200 if (tcp_ip6_spec->tclass)
4201 return -EOPNOTSUPP;
4202
4203 break;
4204 case IPV6_USER_FLOW:
4205 usr_ip6_spec = &fs->h_u.usr_ip6_spec;
4206 *unused |= BIT(INNER_SRC_MAC) | BIT(INNER_DST_MAC) |
4207 BIT(INNER_IP_TOS) | BIT(INNER_SRC_PORT) |
4208 BIT(INNER_DST_PORT);
4209
4210 if (!usr_ip6_spec->ip6src[0] && !usr_ip6_spec->ip6src[1] &&
4211 !usr_ip6_spec->ip6src[2] && !usr_ip6_spec->ip6src[3])
4212 *unused |= BIT(INNER_SRC_IP);
4213
4214 if (!usr_ip6_spec->ip6dst[0] && !usr_ip6_spec->ip6dst[1] &&
4215 !usr_ip6_spec->ip6dst[2] && !usr_ip6_spec->ip6dst[3])
4216 *unused |= BIT(INNER_DST_IP);
4217
4218 if (!usr_ip6_spec->l4_proto)
4219 *unused |= BIT(INNER_IP_PROTO);
4220
4221 if (usr_ip6_spec->tclass)
4222 return -EOPNOTSUPP;
4223
4224 if (usr_ip6_spec->l4_4_bytes)
4225 return -EOPNOTSUPP;
4226
4227 break;
4228 case ETHER_FLOW:
4229 ether_spec = &fs->h_u.ether_spec;
4230 *unused |= BIT(INNER_SRC_IP) | BIT(INNER_DST_IP) |
4231 BIT(INNER_SRC_PORT) | BIT(INNER_DST_PORT) |
4232 BIT(INNER_IP_TOS) | BIT(INNER_IP_PROTO);
4233
4234 if (is_zero_ether_addr(ether_spec->h_source))
4235 *unused |= BIT(INNER_SRC_MAC);
4236
4237 if (is_zero_ether_addr(ether_spec->h_dest))
4238 *unused |= BIT(INNER_DST_MAC);
4239
4240 if (!ether_spec->h_proto)
4241 *unused |= BIT(INNER_ETH_TYPE);
4242
4243 break;
4244 default:
4245 return -EOPNOTSUPP;
4246 }
4247
4248 if ((fs->flow_type & FLOW_EXT)) {
4249 if (fs->h_ext.vlan_etype)
4250 return -EOPNOTSUPP;
4251 if (!fs->h_ext.vlan_tci)
4252 *unused |= BIT(INNER_VLAN_TAG_FST);
4253
4254 if (fs->m_ext.vlan_tci) {
4255 if (be16_to_cpu(fs->h_ext.vlan_tci) >= VLAN_N_VID)
4256 return -EINVAL;
4257 }
4258 } else {
4259 *unused |= BIT(INNER_VLAN_TAG_FST);
4260 }
4261
4262 if (fs->flow_type & FLOW_MAC_EXT) {
4263 if (!(hdev->fd_cfg.proto_support & ETHER_FLOW))
4264 return -EOPNOTSUPP;
4265
4266 if (is_zero_ether_addr(fs->h_ext.h_dest))
4267 *unused |= BIT(INNER_DST_MAC);
4268 else
4269 *unused &= ~(BIT(INNER_DST_MAC));
4270 }
4271
4272 return 0;
4273}
4274
4275static bool hclge_fd_rule_exist(struct hclge_dev *hdev, u16 location)
4276{
4277 struct hclge_fd_rule *rule = NULL;
4278 struct hlist_node *node2;
4279
4280 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4281 if (rule->location >= location)
4282 break;
4283 }
4284
4285 return rule && rule->location == location;
4286}
4287
4288static int hclge_fd_update_rule_list(struct hclge_dev *hdev,
4289 struct hclge_fd_rule *new_rule,
4290 u16 location,
4291 bool is_add)
4292{
4293 struct hclge_fd_rule *rule = NULL, *parent = NULL;
4294 struct hlist_node *node2;
4295
4296 if (is_add && !new_rule)
4297 return -EINVAL;
4298
4299 hlist_for_each_entry_safe(rule, node2,
4300 &hdev->fd_rule_list, rule_node) {
4301 if (rule->location >= location)
4302 break;
4303 parent = rule;
4304 }
4305
4306 if (rule && rule->location == location) {
4307 hlist_del(&rule->rule_node);
4308 kfree(rule);
4309 hdev->hclge_fd_rule_num--;
4310
4311 if (!is_add)
4312 return 0;
4313
4314 } else if (!is_add) {
4315 dev_err(&hdev->pdev->dev,
4316 "delete fail, rule %d is inexistent\n",
4317 location);
4318 return -EINVAL;
4319 }
4320
4321 INIT_HLIST_NODE(&new_rule->rule_node);
4322
4323 if (parent)
4324 hlist_add_behind(&new_rule->rule_node, &parent->rule_node);
4325 else
4326 hlist_add_head(&new_rule->rule_node, &hdev->fd_rule_list);
4327
4328 hdev->hclge_fd_rule_num++;
4329
4330 return 0;
4331}
4332
4333static int hclge_fd_get_tuple(struct hclge_dev *hdev,
4334 struct ethtool_rx_flow_spec *fs,
4335 struct hclge_fd_rule *rule)
4336{
4337 u32 flow_type = fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT);
4338
4339 switch (flow_type) {
4340 case SCTP_V4_FLOW:
4341 case TCP_V4_FLOW:
4342 case UDP_V4_FLOW:
4343 rule->tuples.src_ip[3] =
4344 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4src);
4345 rule->tuples_mask.src_ip[3] =
4346 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4src);
4347
4348 rule->tuples.dst_ip[3] =
4349 be32_to_cpu(fs->h_u.tcp_ip4_spec.ip4dst);
4350 rule->tuples_mask.dst_ip[3] =
4351 be32_to_cpu(fs->m_u.tcp_ip4_spec.ip4dst);
4352
4353 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc);
4354 rule->tuples_mask.src_port =
4355 be16_to_cpu(fs->m_u.tcp_ip4_spec.psrc);
4356
4357 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst);
4358 rule->tuples_mask.dst_port =
4359 be16_to_cpu(fs->m_u.tcp_ip4_spec.pdst);
4360
4361 rule->tuples.ip_tos = fs->h_u.tcp_ip4_spec.tos;
4362 rule->tuples_mask.ip_tos = fs->m_u.tcp_ip4_spec.tos;
4363
4364 rule->tuples.ether_proto = ETH_P_IP;
4365 rule->tuples_mask.ether_proto = 0xFFFF;
4366
4367 break;
4368 case IP_USER_FLOW:
4369 rule->tuples.src_ip[3] =
4370 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4src);
4371 rule->tuples_mask.src_ip[3] =
4372 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4src);
4373
4374 rule->tuples.dst_ip[3] =
4375 be32_to_cpu(fs->h_u.usr_ip4_spec.ip4dst);
4376 rule->tuples_mask.dst_ip[3] =
4377 be32_to_cpu(fs->m_u.usr_ip4_spec.ip4dst);
4378
4379 rule->tuples.ip_tos = fs->h_u.usr_ip4_spec.tos;
4380 rule->tuples_mask.ip_tos = fs->m_u.usr_ip4_spec.tos;
4381
4382 rule->tuples.ip_proto = fs->h_u.usr_ip4_spec.proto;
4383 rule->tuples_mask.ip_proto = fs->m_u.usr_ip4_spec.proto;
4384
4385 rule->tuples.ether_proto = ETH_P_IP;
4386 rule->tuples_mask.ether_proto = 0xFFFF;
4387
4388 break;
4389 case SCTP_V6_FLOW:
4390 case TCP_V6_FLOW:
4391 case UDP_V6_FLOW:
4392 be32_to_cpu_array(rule->tuples.src_ip,
4393 fs->h_u.tcp_ip6_spec.ip6src, 4);
4394 be32_to_cpu_array(rule->tuples_mask.src_ip,
4395 fs->m_u.tcp_ip6_spec.ip6src, 4);
4396
4397 be32_to_cpu_array(rule->tuples.dst_ip,
4398 fs->h_u.tcp_ip6_spec.ip6dst, 4);
4399 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4400 fs->m_u.tcp_ip6_spec.ip6dst, 4);
4401
4402 rule->tuples.src_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.psrc);
4403 rule->tuples_mask.src_port =
4404 be16_to_cpu(fs->m_u.tcp_ip6_spec.psrc);
4405
4406 rule->tuples.dst_port = be16_to_cpu(fs->h_u.tcp_ip6_spec.pdst);
4407 rule->tuples_mask.dst_port =
4408 be16_to_cpu(fs->m_u.tcp_ip6_spec.pdst);
4409
4410 rule->tuples.ether_proto = ETH_P_IPV6;
4411 rule->tuples_mask.ether_proto = 0xFFFF;
4412
4413 break;
4414 case IPV6_USER_FLOW:
4415 be32_to_cpu_array(rule->tuples.src_ip,
4416 fs->h_u.usr_ip6_spec.ip6src, 4);
4417 be32_to_cpu_array(rule->tuples_mask.src_ip,
4418 fs->m_u.usr_ip6_spec.ip6src, 4);
4419
4420 be32_to_cpu_array(rule->tuples.dst_ip,
4421 fs->h_u.usr_ip6_spec.ip6dst, 4);
4422 be32_to_cpu_array(rule->tuples_mask.dst_ip,
4423 fs->m_u.usr_ip6_spec.ip6dst, 4);
4424
4425 rule->tuples.ip_proto = fs->h_u.usr_ip6_spec.l4_proto;
4426 rule->tuples_mask.ip_proto = fs->m_u.usr_ip6_spec.l4_proto;
4427
4428 rule->tuples.ether_proto = ETH_P_IPV6;
4429 rule->tuples_mask.ether_proto = 0xFFFF;
4430
4431 break;
4432 case ETHER_FLOW:
4433 ether_addr_copy(rule->tuples.src_mac,
4434 fs->h_u.ether_spec.h_source);
4435 ether_addr_copy(rule->tuples_mask.src_mac,
4436 fs->m_u.ether_spec.h_source);
4437
4438 ether_addr_copy(rule->tuples.dst_mac,
4439 fs->h_u.ether_spec.h_dest);
4440 ether_addr_copy(rule->tuples_mask.dst_mac,
4441 fs->m_u.ether_spec.h_dest);
4442
4443 rule->tuples.ether_proto =
4444 be16_to_cpu(fs->h_u.ether_spec.h_proto);
4445 rule->tuples_mask.ether_proto =
4446 be16_to_cpu(fs->m_u.ether_spec.h_proto);
4447
4448 break;
4449 default:
4450 return -EOPNOTSUPP;
4451 }
4452
4453 switch (flow_type) {
4454 case SCTP_V4_FLOW:
4455 case SCTP_V6_FLOW:
4456 rule->tuples.ip_proto = IPPROTO_SCTP;
4457 rule->tuples_mask.ip_proto = 0xFF;
4458 break;
4459 case TCP_V4_FLOW:
4460 case TCP_V6_FLOW:
4461 rule->tuples.ip_proto = IPPROTO_TCP;
4462 rule->tuples_mask.ip_proto = 0xFF;
4463 break;
4464 case UDP_V4_FLOW:
4465 case UDP_V6_FLOW:
4466 rule->tuples.ip_proto = IPPROTO_UDP;
4467 rule->tuples_mask.ip_proto = 0xFF;
4468 break;
4469 default:
4470 break;
4471 }
4472
4473 if ((fs->flow_type & FLOW_EXT)) {
4474 rule->tuples.vlan_tag1 = be16_to_cpu(fs->h_ext.vlan_tci);
4475 rule->tuples_mask.vlan_tag1 = be16_to_cpu(fs->m_ext.vlan_tci);
4476 }
4477
4478 if (fs->flow_type & FLOW_MAC_EXT) {
4479 ether_addr_copy(rule->tuples.dst_mac, fs->h_ext.h_dest);
4480 ether_addr_copy(rule->tuples_mask.dst_mac, fs->m_ext.h_dest);
4481 }
4482
4483 return 0;
4484}
4485
4486static int hclge_add_fd_entry(struct hnae3_handle *handle,
4487 struct ethtool_rxnfc *cmd)
4488{
4489 struct hclge_vport *vport = hclge_get_vport(handle);
4490 struct hclge_dev *hdev = vport->back;
4491 u16 dst_vport_id = 0, q_index = 0;
4492 struct ethtool_rx_flow_spec *fs;
4493 struct hclge_fd_rule *rule;
4494 u32 unused = 0;
4495 u8 action;
4496 int ret;
4497
4498 if (!hnae3_dev_fd_supported(hdev))
4499 return -EOPNOTSUPP;
4500
4501 if (!hdev->fd_cfg.fd_en) {
4502 dev_warn(&hdev->pdev->dev,
4503 "Please enable flow director first\n");
4504 return -EOPNOTSUPP;
4505 }
4506
4507 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4508
4509 ret = hclge_fd_check_spec(hdev, fs, &unused);
4510 if (ret) {
4511 dev_err(&hdev->pdev->dev, "Check fd spec failed\n");
4512 return ret;
4513 }
4514
4515 if (fs->ring_cookie == RX_CLS_FLOW_DISC) {
4516 action = HCLGE_FD_ACTION_DROP_PACKET;
4517 } else {
4518 u32 ring = ethtool_get_flow_spec_ring(fs->ring_cookie);
4519 u8 vf = ethtool_get_flow_spec_ring_vf(fs->ring_cookie);
4520 u16 tqps;
4521
4522 dst_vport_id = vf ? hdev->vport[vf].vport_id : vport->vport_id;
4523 tqps = vf ? hdev->vport[vf].alloc_tqps : vport->alloc_tqps;
4524
4525 if (ring >= tqps) {
4526 dev_err(&hdev->pdev->dev,
4527 "Error: queue id (%d) > max tqp num (%d)\n",
4528 ring, tqps - 1);
4529 return -EINVAL;
4530 }
4531
4532 if (vf > hdev->num_req_vfs) {
4533 dev_err(&hdev->pdev->dev,
4534 "Error: vf id (%d) > max vf num (%d)\n",
4535 vf, hdev->num_req_vfs);
4536 return -EINVAL;
4537 }
4538
4539 action = HCLGE_FD_ACTION_ACCEPT_PACKET;
4540 q_index = ring;
4541 }
4542
4543 rule = kzalloc(sizeof(*rule), GFP_KERNEL);
4544 if (!rule)
4545 return -ENOMEM;
4546
4547 ret = hclge_fd_get_tuple(hdev, fs, rule);
4548 if (ret)
4549 goto free_rule;
4550
4551 rule->flow_type = fs->flow_type;
4552
4553 rule->location = fs->location;
4554 rule->unused_tuple = unused;
4555 rule->vf_id = dst_vport_id;
4556 rule->queue_id = q_index;
4557 rule->action = action;
4558
4559 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4560 if (ret)
4561 goto free_rule;
4562
4563 ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4564 if (ret)
4565 goto free_rule;
4566
4567 ret = hclge_fd_update_rule_list(hdev, rule, fs->location, true);
4568 if (ret)
4569 goto free_rule;
4570
4571 return ret;
4572
4573free_rule:
4574 kfree(rule);
4575 return ret;
4576}
4577
4578static int hclge_del_fd_entry(struct hnae3_handle *handle,
4579 struct ethtool_rxnfc *cmd)
4580{
4581 struct hclge_vport *vport = hclge_get_vport(handle);
4582 struct hclge_dev *hdev = vport->back;
4583 struct ethtool_rx_flow_spec *fs;
4584 int ret;
4585
4586 if (!hnae3_dev_fd_supported(hdev))
4587 return -EOPNOTSUPP;
4588
4589 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4590
4591 if (fs->location >= hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1])
4592 return -EINVAL;
4593
4594 if (!hclge_fd_rule_exist(hdev, fs->location)) {
4595 dev_err(&hdev->pdev->dev,
4596 "Delete fail, rule %d is inexistent\n",
4597 fs->location);
4598 return -ENOENT;
4599 }
4600
4601 ret = hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4602 fs->location, NULL, false);
4603 if (ret)
4604 return ret;
4605
4606 return hclge_fd_update_rule_list(hdev, NULL, fs->location,
4607 false);
4608}
4609
6871af29
JS		 4610static void hclge_del_all_fd_entries(struct hnae3_handle *handle,
4611 bool clear_list)
4612{
4613 struct hclge_vport *vport = hclge_get_vport(handle);
4614 struct hclge_dev *hdev = vport->back;
4615 struct hclge_fd_rule *rule;
4616 struct hlist_node *node;
4617
4618 if (!hnae3_dev_fd_supported(hdev))
4619 return;
4620
4621 if (clear_list) {
4622 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4623 rule_node) {
4624 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4625 rule->location, NULL, false);
4626 hlist_del(&rule->rule_node);
4627 kfree(rule);
4628 hdev->hclge_fd_rule_num--;
4629 }
4630 } else {
4631 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list,
4632 rule_node)
4633 hclge_fd_tcam_config(hdev, HCLGE_FD_STAGE_1, true,
4634 rule->location, NULL, false);
4635 }
4636}
4637
4638static int hclge_restore_fd_entries(struct hnae3_handle *handle)
4639{
4640 struct hclge_vport *vport = hclge_get_vport(handle);
4641 struct hclge_dev *hdev = vport->back;
4642 struct hclge_fd_rule *rule;
4643 struct hlist_node *node;
4644 int ret;
4645
65e41e7e
HT		 4646 /* Return ok here, because reset error handling will check this
4647 * return value. If error is returned here, the reset process will
4648 * fail.
4649 */
6871af29 4650 if (!hnae3_dev_fd_supported(hdev))
65e41e7e 4651 return 0;
6871af29
JS		 4652
4653 hlist_for_each_entry_safe(rule, node, &hdev->fd_rule_list, rule_node) {
4654 ret = hclge_config_action(hdev, HCLGE_FD_STAGE_1, rule);
4655 if (!ret)
4656 ret = hclge_config_key(hdev, HCLGE_FD_STAGE_1, rule);
4657
4658 if (ret) {
4659 dev_warn(&hdev->pdev->dev,
4660 "Restore rule %d failed, remove it\n",
4661 rule->location);
4662 hlist_del(&rule->rule_node);
4663 kfree(rule);
4664 hdev->hclge_fd_rule_num--;
4665 }
4666 }
4667 return 0;
4668}
4669
05c2314f
JS		 4670static int hclge_get_fd_rule_cnt(struct hnae3_handle *handle,
4671 struct ethtool_rxnfc *cmd)
4672{
4673 struct hclge_vport *vport = hclge_get_vport(handle);
4674 struct hclge_dev *hdev = vport->back;
4675
4676 if (!hnae3_dev_fd_supported(hdev))
4677 return -EOPNOTSUPP;
4678
4679 cmd->rule_cnt = hdev->hclge_fd_rule_num;
4680 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4681
4682 return 0;
4683}
4684
4685static int hclge_get_fd_rule_info(struct hnae3_handle *handle,
4686 struct ethtool_rxnfc *cmd)
4687{
4688 struct hclge_vport *vport = hclge_get_vport(handle);
4689 struct hclge_fd_rule *rule = NULL;
4690 struct hclge_dev *hdev = vport->back;
4691 struct ethtool_rx_flow_spec *fs;
4692 struct hlist_node *node2;
4693
4694 if (!hnae3_dev_fd_supported(hdev))
4695 return -EOPNOTSUPP;
4696
4697 fs = (struct ethtool_rx_flow_spec *)&cmd->fs;
4698
4699 hlist_for_each_entry_safe(rule, node2, &hdev->fd_rule_list, rule_node) {
4700 if (rule->location >= fs->location)
4701 break;
4702 }
4703
4704 if (!rule || fs->location != rule->location)
4705 return -ENOENT;
4706
4707 fs->flow_type = rule->flow_type;
4708 switch (fs->flow_type & ~(FLOW_EXT | FLOW_MAC_EXT)) {
4709 case SCTP_V4_FLOW:
4710 case TCP_V4_FLOW:
4711 case UDP_V4_FLOW:
4712 fs->h_u.tcp_ip4_spec.ip4src =
4713 cpu_to_be32(rule->tuples.src_ip[3]);
4714 fs->m_u.tcp_ip4_spec.ip4src =
4715 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4716 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4717
4718 fs->h_u.tcp_ip4_spec.ip4dst =
4719 cpu_to_be32(rule->tuples.dst_ip[3]);
4720 fs->m_u.tcp_ip4_spec.ip4dst =
4721 rule->unused_tuple & BIT(INNER_DST_IP) ?
4722 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4723
4724 fs->h_u.tcp_ip4_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4725 fs->m_u.tcp_ip4_spec.psrc =
4726 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4727 0 : cpu_to_be16(rule->tuples_mask.src_port);
4728
4729 fs->h_u.tcp_ip4_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4730 fs->m_u.tcp_ip4_spec.pdst =
4731 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4732 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4733
4734 fs->h_u.tcp_ip4_spec.tos = rule->tuples.ip_tos;
4735 fs->m_u.tcp_ip4_spec.tos =
4736 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4737 0 : rule->tuples_mask.ip_tos;
4738
4739 break;
4740 case IP_USER_FLOW:
4741 fs->h_u.usr_ip4_spec.ip4src =
4742 cpu_to_be32(rule->tuples.src_ip[3]);
4743 fs->m_u.tcp_ip4_spec.ip4src =
4744 rule->unused_tuple & BIT(INNER_SRC_IP) ?
4745 0 : cpu_to_be32(rule->tuples_mask.src_ip[3]);
4746
4747 fs->h_u.usr_ip4_spec.ip4dst =
4748 cpu_to_be32(rule->tuples.dst_ip[3]);
4749 fs->m_u.usr_ip4_spec.ip4dst =
4750 rule->unused_tuple & BIT(INNER_DST_IP) ?
4751 0 : cpu_to_be32(rule->tuples_mask.dst_ip[3]);
4752
4753 fs->h_u.usr_ip4_spec.tos = rule->tuples.ip_tos;
4754 fs->m_u.usr_ip4_spec.tos =
4755 rule->unused_tuple & BIT(INNER_IP_TOS) ?
4756 0 : rule->tuples_mask.ip_tos;
4757
4758 fs->h_u.usr_ip4_spec.proto = rule->tuples.ip_proto;
4759 fs->m_u.usr_ip4_spec.proto =
4760 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4761 0 : rule->tuples_mask.ip_proto;
4762
4763 fs->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4;
4764
4765 break;
4766 case SCTP_V6_FLOW:
4767 case TCP_V6_FLOW:
4768 case UDP_V6_FLOW:
4769 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6src,
4770 rule->tuples.src_ip, 4);
4771 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4772 memset(fs->m_u.tcp_ip6_spec.ip6src, 0, sizeof(int) * 4);
4773 else
4774 cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6src,
4775 rule->tuples_mask.src_ip, 4);
4776
4777 cpu_to_be32_array(fs->h_u.tcp_ip6_spec.ip6dst,
4778 rule->tuples.dst_ip, 4);
4779 if (rule->unused_tuple & BIT(INNER_DST_IP))
4780 memset(fs->m_u.tcp_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4781 else
4782 cpu_to_be32_array(fs->m_u.tcp_ip6_spec.ip6dst,
4783 rule->tuples_mask.dst_ip, 4);
4784
4785 fs->h_u.tcp_ip6_spec.psrc = cpu_to_be16(rule->tuples.src_port);
4786 fs->m_u.tcp_ip6_spec.psrc =
4787 rule->unused_tuple & BIT(INNER_SRC_PORT) ?
4788 0 : cpu_to_be16(rule->tuples_mask.src_port);
4789
4790 fs->h_u.tcp_ip6_spec.pdst = cpu_to_be16(rule->tuples.dst_port);
4791 fs->m_u.tcp_ip6_spec.pdst =
4792 rule->unused_tuple & BIT(INNER_DST_PORT) ?
4793 0 : cpu_to_be16(rule->tuples_mask.dst_port);
4794
4795 break;
4796 case IPV6_USER_FLOW:
4797 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6src,
4798 rule->tuples.src_ip, 4);
4799 if (rule->unused_tuple & BIT(INNER_SRC_IP))
4800 memset(fs->m_u.usr_ip6_spec.ip6src, 0, sizeof(int) * 4);
4801 else
4802 cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6src,
4803 rule->tuples_mask.src_ip, 4);
4804
4805 cpu_to_be32_array(fs->h_u.usr_ip6_spec.ip6dst,
4806 rule->tuples.dst_ip, 4);
4807 if (rule->unused_tuple & BIT(INNER_DST_IP))
4808 memset(fs->m_u.usr_ip6_spec.ip6dst, 0, sizeof(int) * 4);
4809 else
4810 cpu_to_be32_array(fs->m_u.usr_ip6_spec.ip6dst,
4811 rule->tuples_mask.dst_ip, 4);
4812
4813 fs->h_u.usr_ip6_spec.l4_proto = rule->tuples.ip_proto;
4814 fs->m_u.usr_ip6_spec.l4_proto =
4815 rule->unused_tuple & BIT(INNER_IP_PROTO) ?
4816 0 : rule->tuples_mask.ip_proto;
4817
4818 break;
4819 case ETHER_FLOW:
4820 ether_addr_copy(fs->h_u.ether_spec.h_source,
4821 rule->tuples.src_mac);
4822 if (rule->unused_tuple & BIT(INNER_SRC_MAC))
4823 eth_zero_addr(fs->m_u.ether_spec.h_source);
4824 else
4825 ether_addr_copy(fs->m_u.ether_spec.h_source,
4826 rule->tuples_mask.src_mac);
4827
4828 ether_addr_copy(fs->h_u.ether_spec.h_dest,
4829 rule->tuples.dst_mac);
4830 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4831 eth_zero_addr(fs->m_u.ether_spec.h_dest);
4832 else
4833 ether_addr_copy(fs->m_u.ether_spec.h_dest,
4834 rule->tuples_mask.dst_mac);
4835
4836 fs->h_u.ether_spec.h_proto =
4837 cpu_to_be16(rule->tuples.ether_proto);
4838 fs->m_u.ether_spec.h_proto =
4839 rule->unused_tuple & BIT(INNER_ETH_TYPE) ?
4840 0 : cpu_to_be16(rule->tuples_mask.ether_proto);
4841
4842 break;
4843 default:
4844 return -EOPNOTSUPP;
4845 }
4846
4847 if (fs->flow_type & FLOW_EXT) {
4848 fs->h_ext.vlan_tci = cpu_to_be16(rule->tuples.vlan_tag1);
4849 fs->m_ext.vlan_tci =
4850 rule->unused_tuple & BIT(INNER_VLAN_TAG_FST) ?
4851 cpu_to_be16(VLAN_VID_MASK) :
4852 cpu_to_be16(rule->tuples_mask.vlan_tag1);
4853 }
4854
4855 if (fs->flow_type & FLOW_MAC_EXT) {
4856 ether_addr_copy(fs->h_ext.h_dest, rule->tuples.dst_mac);
4857 if (rule->unused_tuple & BIT(INNER_DST_MAC))
4858 eth_zero_addr(fs->m_u.ether_spec.h_dest);
4859 else
4860 ether_addr_copy(fs->m_u.ether_spec.h_dest,
4861 rule->tuples_mask.dst_mac);
4862 }
4863
4864 if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
4865 fs->ring_cookie = RX_CLS_FLOW_DISC;
4866 } else {
4867 u64 vf_id;
4868
4869 fs->ring_cookie = rule->queue_id;
4870 vf_id = rule->vf_id;
4871 vf_id <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
4872 fs->ring_cookie |= vf_id;
4873 }
4874
4875 return 0;
4876}
4877
4878static int hclge_get_all_rules(struct hnae3_handle *handle,
4879 struct ethtool_rxnfc *cmd, u32 *rule_locs)
4880{
4881 struct hclge_vport *vport = hclge_get_vport(handle);
4882 struct hclge_dev *hdev = vport->back;
4883 struct hclge_fd_rule *rule;
4884 struct hlist_node *node2;
4885 int cnt = 0;
4886
4887 if (!hnae3_dev_fd_supported(hdev))
4888 return -EOPNOTSUPP;
4889
4890 cmd->data = hdev->fd_cfg.rule_num[HCLGE_FD_STAGE_1];
4891
4892 hlist_for_each_entry_safe(rule, node2,
4893 &hdev->fd_rule_list, rule_node) {
4894 if (cnt == cmd->rule_cnt)
4895 return -EMSGSIZE;
4896
4897 rule_locs[cnt] = rule->location;
4898 cnt++;
4899 }
4900
4901 cmd->rule_cnt = cnt;
4902
4903 return 0;
4904}
4905
4d60291b
HT		 4906static bool hclge_get_hw_reset_stat(struct hnae3_handle *handle)
4907{
4908 struct hclge_vport *vport = hclge_get_vport(handle);
4909 struct hclge_dev *hdev = vport->back;
4910
4911 return hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) ||
4912 hclge_read_dev(&hdev->hw, HCLGE_FUN_RST_ING);
4913}
4914
4915static bool hclge_ae_dev_resetting(struct hnae3_handle *handle)
4916{
4917 struct hclge_vport *vport = hclge_get_vport(handle);
4918 struct hclge_dev *hdev = vport->back;
4919
4920 return test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
4921}
4922
4923static unsigned long hclge_ae_dev_reset_cnt(struct hnae3_handle *handle)
4924{
4925 struct hclge_vport *vport = hclge_get_vport(handle);
4926 struct hclge_dev *hdev = vport->back;
4927
4928 return hdev->reset_count;
4929}
4930
c17852a8
JS		 4931static void hclge_enable_fd(struct hnae3_handle *handle, bool enable)
4932{
4933 struct hclge_vport *vport = hclge_get_vport(handle);
4934 struct hclge_dev *hdev = vport->back;
4935
4936 hdev->fd_cfg.fd_en = enable;
4937 if (!enable)
4938 hclge_del_all_fd_entries(handle, false);
4939 else
4940 hclge_restore_fd_entries(handle);
4941}
4942
46a3df9f
S		 4943static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
4944{
4945 struct hclge_desc desc;
d44f9b63
YL		 4946 struct hclge_config_mac_mode_cmd *req =
4947 (struct hclge_config_mac_mode_cmd *)desc.data;
a90bb9a5 4948 u32 loop_en = 0;
46a3df9f
S		 4949 int ret;
4950
4951 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false);
e4e87715
PL		 4952 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable);
4953 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable);
4954 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable);
4955 hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable);
4956 hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0);
4957 hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0);
4958 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0);
4959 hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0);
4960 hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable);
4961 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable);
4962 hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable);
4963 hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable);
4964 hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable);
4965 hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable);
a90bb9a5 4966 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
46a3df9f
S		 4967
4968 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4969 if (ret)
4970 dev_err(&hdev->pdev->dev,
4971 "mac enable fail, ret =%d.\n", ret);
4972}
4973
eb66d503 4974static int hclge_set_app_loopback(struct hclge_dev *hdev, bool en)
c39c4d98 4975{
c39c4d98 4976 struct hclge_config_mac_mode_cmd *req;
c39c4d98
YL		 4977 struct hclge_desc desc;
4978 u32 loop_en;
4979 int ret;
4980
e4d68dae
YL		 4981 req = (struct hclge_config_mac_mode_cmd *)&desc.data[0];
4982 /* 1 Read out the MAC mode config at first */
4983 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true);
4984 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
4985 if (ret) {
4986 dev_err(&hdev->pdev->dev,
4987 "mac loopback get fail, ret =%d.\n", ret);
4988 return ret;
4989 }
c39c4d98 4990
e4d68dae
YL		 4991 /* 2 Then setup the loopback flag */
4992 loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en);
e4e87715 4993 hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0);
0f29fc23
YL		 4994 hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, en ? 1 : 0);
4995 hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, en ? 1 : 0);
e4d68dae
YL		 4996
4997 req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en);
c39c4d98 4998
e4d68dae
YL		 4999 /* 3 Config mac work mode with loopback flag
5000 * and its original configure parameters
5001 */
5002 hclge_cmd_reuse_desc(&desc, false);
5003 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5004 if (ret)
5005 dev_err(&hdev->pdev->dev,
5006 "mac loopback set fail, ret =%d.\n", ret);
5007 return ret;
5008}
c39c4d98 5009
4dc13b96
FL		 5010static int hclge_set_serdes_loopback(struct hclge_dev *hdev, bool en,
5011 enum hnae3_loop loop_mode)
5fd50ac3
PL		 5012{
5013#define HCLGE_SERDES_RETRY_MS 10
5014#define HCLGE_SERDES_RETRY_NUM 100
5015 struct hclge_serdes_lb_cmd *req;
5016 struct hclge_desc desc;
5017 int ret, i = 0;
4dc13b96 5018 u8 loop_mode_b;
5fd50ac3 5019
d0d72bac 5020 req = (struct hclge_serdes_lb_cmd *)desc.data;
5fd50ac3
PL		 5021 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK, false);
5022
4dc13b96
FL		 5023 switch (loop_mode) {
5024 case HNAE3_LOOP_SERIAL_SERDES:
5025 loop_mode_b = HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B;
5026 break;
5027 case HNAE3_LOOP_PARALLEL_SERDES:
5028 loop_mode_b = HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B;
5029 break;
5030 default:
5031 dev_err(&hdev->pdev->dev,
5032 "unsupported serdes loopback mode %d\n", loop_mode);
5033 return -ENOTSUPP;
5034 }
5035
5fd50ac3 5036 if (en) {
4dc13b96
FL		 5037 req->enable = loop_mode_b;
5038 req->mask = loop_mode_b;
5fd50ac3 5039 } else {
4dc13b96 5040 req->mask = loop_mode_b;
5fd50ac3
PL		 5041 }
5042
5043 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5044 if (ret) {
5045 dev_err(&hdev->pdev->dev,
5046 "serdes loopback set fail, ret = %d\n", ret);
5047 return ret;
5048 }
5049
5050 do {
5051 msleep(HCLGE_SERDES_RETRY_MS);
5052 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SERDES_LOOPBACK,
5053 true);
5054 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5055 if (ret) {
5056 dev_err(&hdev->pdev->dev,
5057 "serdes loopback get, ret = %d\n", ret);
5058 return ret;
5059 }
5060 } while (++i < HCLGE_SERDES_RETRY_NUM &&
5061 !(req->result & HCLGE_CMD_SERDES_DONE_B));
5062
5063 if (!(req->result & HCLGE_CMD_SERDES_DONE_B)) {
5064 dev_err(&hdev->pdev->dev, "serdes loopback set timeout\n");
5065 return -EBUSY;
5066 } else if (!(req->result & HCLGE_CMD_SERDES_SUCCESS_B)) {
5067 dev_err(&hdev->pdev->dev, "serdes loopback set failed in fw\n");
5068 return -EIO;
5069 }
5070
0f29fc23 5071 hclge_cfg_mac_mode(hdev, en);
5fd50ac3
PL		 5072 return 0;
5073}
5074
0f29fc23
YL		 5075static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id,
5076 int stream_id, bool enable)
5077{
5078 struct hclge_desc desc;
5079 struct hclge_cfg_com_tqp_queue_cmd *req =
5080 (struct hclge_cfg_com_tqp_queue_cmd *)desc.data;
5081 int ret;
5082
5083 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false);
5084 req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK);
5085 req->stream_id = cpu_to_le16(stream_id);
5086 req->enable |= enable << HCLGE_TQP_ENABLE_B;
5087
5088 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5089 if (ret)
5090 dev_err(&hdev->pdev->dev,
5091 "Tqp enable fail, status =%d.\n", ret);
5092 return ret;
5093}
5094
e4d68dae
YL		 5095static int hclge_set_loopback(struct hnae3_handle *handle,
5096 enum hnae3_loop loop_mode, bool en)
5097{
5098 struct hclge_vport *vport = hclge_get_vport(handle);
5099 struct hclge_dev *hdev = vport->back;
0f29fc23 5100 int i, ret;
e4d68dae
YL		 5101
5102 switch (loop_mode) {
eb66d503
FL		 5103 case HNAE3_LOOP_APP:
5104 ret = hclge_set_app_loopback(hdev, en);
c39c4d98 5105 break;
4dc13b96
FL		 5106 case HNAE3_LOOP_SERIAL_SERDES:
5107 case HNAE3_LOOP_PARALLEL_SERDES:
5108 ret = hclge_set_serdes_loopback(hdev, en, loop_mode);
5fd50ac3 5109 break;
c39c4d98
YL		 5110 default:
5111 ret = -ENOTSUPP;
5112 dev_err(&hdev->pdev->dev,
5113 "loop_mode %d is not supported\n", loop_mode);
5114 break;
5115 }
5116
0f29fc23
YL		 5117 for (i = 0; i < vport->alloc_tqps; i++) {
5118 ret = hclge_tqp_enable(hdev, i, 0, en);
5119 if (ret)
5120 return ret;
5121 }
46a3df9f 5122
0f29fc23 5123 return 0;
46a3df9f
S		 5124}
5125
5126static void hclge_reset_tqp_stats(struct hnae3_handle *handle)
5127{
5128 struct hclge_vport *vport = hclge_get_vport(handle);
5129 struct hnae3_queue *queue;
5130 struct hclge_tqp *tqp;
5131 int i;
5132
5133 for (i = 0; i < vport->alloc_tqps; i++) {
5134 queue = handle->kinfo.tqp[i];
5135 tqp = container_of(queue, struct hclge_tqp, q);
5136 memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats));
5137 }
5138}
5139
5140static int hclge_ae_start(struct hnae3_handle *handle)
5141{
5142 struct hclge_vport *vport = hclge_get_vport(handle);
5143 struct hclge_dev *hdev = vport->back;
46a3df9f 5144
46a3df9f
S		 5145 /* mac enable */
5146 hclge_cfg_mac_mode(hdev, true);
5147 clear_bit(HCLGE_STATE_DOWN, &hdev->state);
d039ef68 5148 mod_timer(&hdev->service_timer, jiffies + HZ);
be8d8cdb 5149 hdev->hw.mac.link = 0;
46a3df9f 5150
b50ae26c
PL		 5151 /* reset tqp stats */
5152 hclge_reset_tqp_stats(handle);
5153
b01b7cf1 5154 hclge_mac_start_phy(hdev);
46a3df9f 5155
46a3df9f
S		 5156 return 0;
5157}
5158
5159static void hclge_ae_stop(struct hnae3_handle *handle)
5160{
5161 struct hclge_vport *vport = hclge_get_vport(handle);
5162 struct hclge_dev *hdev = vport->back;
46a3df9f 5163
2f7e4896
FL		 5164 set_bit(HCLGE_STATE_DOWN, &hdev->state);
5165
b50ae26c
PL		 5166 del_timer_sync(&hdev->service_timer);
5167 cancel_work_sync(&hdev->service_task);
f5be7967 5168 clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
b50ae26c 5169
35d93a30
HT		 5170 /* If it is not PF reset, the firmware will disable the MAC,
5171 * so it only need to stop phy here.
5172 */
5173 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state) &&
5174 hdev->reset_type != HNAE3_FUNC_RESET) {
9617f668 5175 hclge_mac_stop_phy(hdev);
b50ae26c 5176 return;
9617f668 5177 }
b50ae26c 5178
46a3df9f
S		 5179 /* Mac disable */
5180 hclge_cfg_mac_mode(hdev, false);
5181
5182 hclge_mac_stop_phy(hdev);
5183
5184 /* reset tqp stats */
5185 hclge_reset_tqp_stats(handle);
f30dfddc
FL		 5186 del_timer_sync(&hdev->service_timer);
5187 cancel_work_sync(&hdev->service_task);
5188 hclge_update_link_status(hdev);
46a3df9f
S		 5189}
5190
5191static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport,
5192 u16 cmdq_resp, u8 resp_code,
5193 enum hclge_mac_vlan_tbl_opcode op)
5194{
5195 struct hclge_dev *hdev = vport->back;
5196 int return_status = -EIO;
5197
5198 if (cmdq_resp) {
5199 dev_err(&hdev->pdev->dev,
5200 "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n",
5201 cmdq_resp);
5202 return -EIO;
5203 }
5204
5205 if (op == HCLGE_MAC_VLAN_ADD) {
5206 if ((!resp_code) || (resp_code == 1)) {
5207 return_status = 0;
5208 } else if (resp_code == 2) {
eefd00a5 5209 return_status = -ENOSPC;
46a3df9f
S		 5210 dev_err(&hdev->pdev->dev,
5211 "add mac addr failed for uc_overflow.\n");
5212 } else if (resp_code == 3) {
eefd00a5 5213 return_status = -ENOSPC;
46a3df9f
S		 5214 dev_err(&hdev->pdev->dev,
5215 "add mac addr failed for mc_overflow.\n");
5216 } else {
5217 dev_err(&hdev->pdev->dev,
5218 "add mac addr failed for undefined, code=%d.\n",
5219 resp_code);
5220 }
5221 } else if (op == HCLGE_MAC_VLAN_REMOVE) {
5222 if (!resp_code) {
5223 return_status = 0;
5224 } else if (resp_code == 1) {
eefd00a5 5225 return_status = -ENOENT;
46a3df9f
S		 5226 dev_dbg(&hdev->pdev->dev,
5227 "remove mac addr failed for miss.\n");
5228 } else {
5229 dev_err(&hdev->pdev->dev,
5230 "remove mac addr failed for undefined, code=%d.\n",
5231 resp_code);
5232 }
5233 } else if (op == HCLGE_MAC_VLAN_LKUP) {
5234 if (!resp_code) {
5235 return_status = 0;
5236 } else if (resp_code == 1) {
eefd00a5 5237 return_status = -ENOENT;
46a3df9f
S		 5238 dev_dbg(&hdev->pdev->dev,
5239 "lookup mac addr failed for miss.\n");
5240 } else {
5241 dev_err(&hdev->pdev->dev,
5242 "lookup mac addr failed for undefined, code=%d.\n",
5243 resp_code);
5244 }
5245 } else {
eefd00a5 5246 return_status = -EINVAL;
46a3df9f
S		 5247 dev_err(&hdev->pdev->dev,
5248 "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n",
5249 op);
5250 }
5251
5252 return return_status;
5253}
5254
5255static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr)
5256{
5257 int word_num;
5258 int bit_num;
5259
5260 if (vfid > 255 || vfid < 0)
5261 return -EIO;
5262
5263 if (vfid >= 0 && vfid <= 191) {
5264 word_num = vfid / 32;
5265 bit_num = vfid % 32;
5266 if (clr)
a90bb9a5 5267 desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 5268 else
a90bb9a5 5269 desc[1].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 5270 } else {
5271 word_num = (vfid - 192) / 32;
5272 bit_num = vfid % 32;
5273 if (clr)
a90bb9a5 5274 desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num));
46a3df9f 5275 else
a90bb9a5 5276 desc[2].data[word_num] |= cpu_to_le32(1 << bit_num);
46a3df9f
S		 5277 }
5278
5279 return 0;
5280}
5281
5282static bool hclge_is_all_function_id_zero(struct hclge_desc *desc)
5283{
5284#define HCLGE_DESC_NUMBER 3
5285#define HCLGE_FUNC_NUMBER_PER_DESC 6
5286 int i, j;
5287
6c39d527 5288 for (i = 1; i < HCLGE_DESC_NUMBER; i++)
46a3df9f
S		 5289 for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++)
5290 if (desc[i].data[j])
5291 return false;
5292
5293 return true;
5294}
5295
d44f9b63 5296static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req,
46a3df9f
S		 5297 const u8 *addr)
5298{
5299 const unsigned char *mac_addr = addr;
5300 u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) |
5301 (mac_addr[0]) | (mac_addr[1] << 8);
5302 u32 low_val = mac_addr[4] | (mac_addr[5] << 8);
5303
5304 new_req->mac_addr_hi32 = cpu_to_le32(high_val);
5305 new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff);
5306}
5307
46a3df9f 5308static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 5309 struct hclge_mac_vlan_tbl_entry_cmd *req)
46a3df9f
S		 5310{
5311 struct hclge_dev *hdev = vport->back;
5312 struct hclge_desc desc;
5313 u8 resp_code;
a90bb9a5 5314 u16 retval;
46a3df9f
S		 5315 int ret;
5316
5317 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false);
5318
d44f9b63 5319 memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 5320
5321 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5322 if (ret) {
5323 dev_err(&hdev->pdev->dev,
5324 "del mac addr failed for cmd_send, ret =%d.\n",
5325 ret);
5326 return ret;
5327 }
a90bb9a5
YL		 5328 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5329 retval = le16_to_cpu(desc.retval);
46a3df9f 5330
a90bb9a5 5331 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 5332 HCLGE_MAC_VLAN_REMOVE);
5333}
5334
5335static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 5336 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 5337 struct hclge_desc *desc,
5338 bool is_mc)
5339{
5340 struct hclge_dev *hdev = vport->back;
5341 u8 resp_code;
a90bb9a5 5342 u16 retval;
46a3df9f
S		 5343 int ret;
5344
5345 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true);
5346 if (is_mc) {
5347 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5348 memcpy(desc[0].data,
5349 req,
d44f9b63 5350 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 5351 hclge_cmd_setup_basic_desc(&desc[1],
5352 HCLGE_OPC_MAC_VLAN_ADD,
5353 true);
5354 desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5355 hclge_cmd_setup_basic_desc(&desc[2],
5356 HCLGE_OPC_MAC_VLAN_ADD,
5357 true);
5358 ret = hclge_cmd_send(&hdev->hw, desc, 3);
5359 } else {
5360 memcpy(desc[0].data,
5361 req,
d44f9b63 5362 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f
S		 5363 ret = hclge_cmd_send(&hdev->hw, desc, 1);
5364 }
5365 if (ret) {
5366 dev_err(&hdev->pdev->dev,
5367 "lookup mac addr failed for cmd_send, ret =%d.\n",
5368 ret);
5369 return ret;
5370 }
a90bb9a5
YL		 5371 resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff;
5372 retval = le16_to_cpu(desc[0].retval);
46a3df9f 5373
a90bb9a5 5374 return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code,
46a3df9f
S		 5375 HCLGE_MAC_VLAN_LKUP);
5376}
5377
5378static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport,
d44f9b63 5379 struct hclge_mac_vlan_tbl_entry_cmd *req,
46a3df9f
S		 5380 struct hclge_desc *mc_desc)
5381{
5382 struct hclge_dev *hdev = vport->back;
5383 int cfg_status;
5384 u8 resp_code;
a90bb9a5 5385 u16 retval;
46a3df9f
S		 5386 int ret;
5387
5388 if (!mc_desc) {
5389 struct hclge_desc desc;
5390
5391 hclge_cmd_setup_basic_desc(&desc,
5392 HCLGE_OPC_MAC_VLAN_ADD,
5393 false);
d44f9b63
YL		 5394 memcpy(desc.data, req,
5395 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 5396 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
a90bb9a5
YL		 5397 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5398 retval = le16_to_cpu(desc.retval);
5399
5400 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 5401 resp_code,
5402 HCLGE_MAC_VLAN_ADD);
5403 } else {
c3b6f755 5404 hclge_cmd_reuse_desc(&mc_desc[0], false);
46a3df9f 5405 mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 5406 hclge_cmd_reuse_desc(&mc_desc[1], false);
46a3df9f 5407 mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
c3b6f755 5408 hclge_cmd_reuse_desc(&mc_desc[2], false);
46a3df9f
S		 5409 mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT);
5410 memcpy(mc_desc[0].data, req,
d44f9b63 5411 sizeof(struct hclge_mac_vlan_tbl_entry_cmd));
46a3df9f 5412 ret = hclge_cmd_send(&hdev->hw, mc_desc, 3);
a90bb9a5
YL		 5413 resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff;
5414 retval = le16_to_cpu(mc_desc[0].retval);
5415
5416 cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval,
46a3df9f
S		 5417 resp_code,
5418 HCLGE_MAC_VLAN_ADD);
5419 }
5420
5421 if (ret) {
5422 dev_err(&hdev->pdev->dev,
5423 "add mac addr failed for cmd_send, ret =%d.\n",
5424 ret);
5425 return ret;
5426 }
5427
5428 return cfg_status;
5429}
5430
39932473
JS		 5431static int hclge_init_umv_space(struct hclge_dev *hdev)
5432{
5433 u16 allocated_size = 0;
5434 int ret;
5435
5436 ret = hclge_set_umv_space(hdev, hdev->wanted_umv_size, &allocated_size,
5437 true);
5438 if (ret)
5439 return ret;
5440
5441 if (allocated_size < hdev->wanted_umv_size)
5442 dev_warn(&hdev->pdev->dev,
5443 "Alloc umv space failed, want %d, get %d\n",
5444 hdev->wanted_umv_size, allocated_size);
5445
5446 mutex_init(&hdev->umv_mutex);
5447 hdev->max_umv_size = allocated_size;
5448 hdev->priv_umv_size = hdev->max_umv_size / (hdev->num_req_vfs + 2);
5449 hdev->share_umv_size = hdev->priv_umv_size +
5450 hdev->max_umv_size % (hdev->num_req_vfs + 2);
5451
5452 return 0;
5453}
5454
5455static int hclge_uninit_umv_space(struct hclge_dev *hdev)
5456{
5457 int ret;
5458
5459 if (hdev->max_umv_size > 0) {
5460 ret = hclge_set_umv_space(hdev, hdev->max_umv_size, NULL,
5461 false);
5462 if (ret)
5463 return ret;
5464 hdev->max_umv_size = 0;
5465 }
5466 mutex_destroy(&hdev->umv_mutex);
5467
5468 return 0;
5469}
5470
5471static int hclge_set_umv_space(struct hclge_dev *hdev, u16 space_size,
5472 u16 *allocated_size, bool is_alloc)
5473{
5474 struct hclge_umv_spc_alc_cmd *req;
5475 struct hclge_desc desc;
5476 int ret;
5477
5478 req = (struct hclge_umv_spc_alc_cmd *)desc.data;
5479 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_ALLOCATE, false);
5480 hnae3_set_bit(req->allocate, HCLGE_UMV_SPC_ALC_B, !is_alloc);
5481 req->space_size = cpu_to_le32(space_size);
5482
5483 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5484 if (ret) {
5485 dev_err(&hdev->pdev->dev,
5486 "%s umv space failed for cmd_send, ret =%d\n",
5487 is_alloc ? "allocate" : "free", ret);
5488 return ret;
5489 }
5490
5491 if (is_alloc && allocated_size)
5492 *allocated_size = le32_to_cpu(desc.data[1]);
5493
5494 return 0;
5495}
5496
5497static void hclge_reset_umv_space(struct hclge_dev *hdev)
5498{
5499 struct hclge_vport *vport;
5500 int i;
5501
5502 for (i = 0; i < hdev->num_alloc_vport; i++) {
5503 vport = &hdev->vport[i];
5504 vport->used_umv_num = 0;
5505 }
5506
5507 mutex_lock(&hdev->umv_mutex);
5508 hdev->share_umv_size = hdev->priv_umv_size +
5509 hdev->max_umv_size % (hdev->num_req_vfs + 2);
5510 mutex_unlock(&hdev->umv_mutex);
5511}
5512
5513static bool hclge_is_umv_space_full(struct hclge_vport *vport)
5514{
5515 struct hclge_dev *hdev = vport->back;
5516 bool is_full;
5517
5518 mutex_lock(&hdev->umv_mutex);
5519 is_full = (vport->used_umv_num >= hdev->priv_umv_size &&
5520 hdev->share_umv_size == 0);
5521 mutex_unlock(&hdev->umv_mutex);
5522
5523 return is_full;
5524}
5525
5526static void hclge_update_umv_space(struct hclge_vport *vport, bool is_free)
5527{
5528 struct hclge_dev *hdev = vport->back;
5529
5530 mutex_lock(&hdev->umv_mutex);
5531 if (is_free) {
5532 if (vport->used_umv_num > hdev->priv_umv_size)
5533 hdev->share_umv_size++;
5534 vport->used_umv_num--;
5535 } else {
5536 if (vport->used_umv_num >= hdev->priv_umv_size)
5537 hdev->share_umv_size--;
5538 vport->used_umv_num++;
5539 }
5540 mutex_unlock(&hdev->umv_mutex);
5541}
5542
46a3df9f
S		 5543static int hclge_add_uc_addr(struct hnae3_handle *handle,
5544 const unsigned char *addr)
5545{
5546 struct hclge_vport *vport = hclge_get_vport(handle);
5547
5548 return hclge_add_uc_addr_common(vport, addr);
5549}
5550
5551int hclge_add_uc_addr_common(struct hclge_vport *vport,
5552 const unsigned char *addr)
5553{
5554 struct hclge_dev *hdev = vport->back;
d44f9b63 5555 struct hclge_mac_vlan_tbl_entry_cmd req;
d07b6bb4 5556 struct hclge_desc desc;
a90bb9a5 5557 u16 egress_port = 0;
aa7a795e 5558 int ret;
46a3df9f
S		 5559
5560 /* mac addr check */
5561 if (is_zero_ether_addr(addr) ||
5562 is_broadcast_ether_addr(addr) ||
5563 is_multicast_ether_addr(addr)) {
5564 dev_err(&hdev->pdev->dev,
5565 "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n",
5566 addr,
5567 is_zero_ether_addr(addr),
5568 is_broadcast_ether_addr(addr),
5569 is_multicast_ether_addr(addr));
5570 return -EINVAL;
5571 }
5572
5573 memset(&req, 0, sizeof(req));
e4e87715 5574 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
a90bb9a5 5575
e4e87715
PL		 5576 hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M,
5577 HCLGE_MAC_EPORT_VFID_S, vport->vport_id);
a90bb9a5
YL		 5578
5579 req.egress_port = cpu_to_le16(egress_port);
46a3df9f
S		 5580
5581 hclge_prepare_mac_addr(&req, addr);
5582
d07b6bb4
JS		 5583 /* Lookup the mac address in the mac_vlan table, and add
5584 * it if the entry is inexistent. Repeated unicast entry
5585 * is not allowed in the mac vlan table.
5586 */
5587 ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false);
39932473
JS		 5588 if (ret == -ENOENT) {
5589 if (!hclge_is_umv_space_full(vport)) {
5590 ret = hclge_add_mac_vlan_tbl(vport, &req, NULL);
5591 if (!ret)
5592 hclge_update_umv_space(vport, false);
5593 return ret;
5594 }
5595
5596 dev_err(&hdev->pdev->dev, "UC MAC table full(%u)\n",
5597 hdev->priv_umv_size);
5598
5599 return -ENOSPC;
5600 }
d07b6bb4
JS		 5601
5602 /* check if we just hit the duplicate */
5603 if (!ret)
5604 ret = -EINVAL;
5605
5606 dev_err(&hdev->pdev->dev,
5607 "PF failed to add unicast entry(%pM) in the MAC table\n",
5608 addr);
46a3df9f 5609
aa7a795e 5610 return ret;
46a3df9f
S		 5611}
5612
5613static int hclge_rm_uc_addr(struct hnae3_handle *handle,
5614 const unsigned char *addr)
5615{
5616 struct hclge_vport *vport = hclge_get_vport(handle);
5617
5618 return hclge_rm_uc_addr_common(vport, addr);
5619}
5620
5621int hclge_rm_uc_addr_common(struct hclge_vport *vport,
5622 const unsigned char *addr)
5623{
5624 struct hclge_dev *hdev = vport->back;
d44f9b63 5625 struct hclge_mac_vlan_tbl_entry_cmd req;
aa7a795e 5626 int ret;
46a3df9f
S		 5627
5628 /* mac addr check */
5629 if (is_zero_ether_addr(addr) ||
5630 is_broadcast_ether_addr(addr) ||
5631 is_multicast_ether_addr(addr)) {
5632 dev_dbg(&hdev->pdev->dev,
5633 "Remove mac err! invalid mac:%pM.\n",
5634 addr);
5635 return -EINVAL;
5636 }
5637
5638 memset(&req, 0, sizeof(req));
e4e87715
PL		 5639 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5640 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
46a3df9f 5641 hclge_prepare_mac_addr(&req, addr);
aa7a795e 5642 ret = hclge_remove_mac_vlan_tbl(vport, &req);
39932473
JS		 5643 if (!ret)
5644 hclge_update_umv_space(vport, true);
46a3df9f 5645
aa7a795e 5646 return ret;
46a3df9f
S		 5647}
5648
5649static int hclge_add_mc_addr(struct hnae3_handle *handle,
5650 const unsigned char *addr)
5651{
5652 struct hclge_vport *vport = hclge_get_vport(handle);
5653
a10829c4 5654 return hclge_add_mc_addr_common(vport, addr);
46a3df9f
S		 5655}
5656
5657int hclge_add_mc_addr_common(struct hclge_vport *vport,
5658 const unsigned char *addr)
5659{
5660 struct hclge_dev *hdev = vport->back;
d44f9b63 5661 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f 5662 struct hclge_desc desc[3];
46a3df9f
S		 5663 int status;
5664
5665 /* mac addr check */
5666 if (!is_multicast_ether_addr(addr)) {
5667 dev_err(&hdev->pdev->dev,
5668 "Add mc mac err! invalid mac:%pM.\n",
5669 addr);
5670 return -EINVAL;
5671 }
5672 memset(&req, 0, sizeof(req));
e4e87715
PL		 5673 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5674 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5675 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
fd5f9da3 5676 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 5677 hclge_prepare_mac_addr(&req, addr);
5678 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5679 if (!status) {
5680 /* This mac addr exist, update VFID for it */
5681 hclge_update_desc_vfid(desc, vport->vport_id, false);
5682 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5683 } else {
5684 /* This mac addr do not exist, add new entry for it */
5685 memset(desc[0].data, 0, sizeof(desc[0].data));
5686 memset(desc[1].data, 0, sizeof(desc[0].data));
5687 memset(desc[2].data, 0, sizeof(desc[0].data));
5688 hclge_update_desc_vfid(desc, vport->vport_id, false);
5689 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5690 }
5691
1f6db589
JS		 5692 if (status == -ENOSPC)
5693 dev_err(&hdev->pdev->dev, "mc mac vlan table is full\n");
46a3df9f
S		 5694
5695 return status;
5696}
5697
5698static int hclge_rm_mc_addr(struct hnae3_handle *handle,
5699 const unsigned char *addr)
5700{
5701 struct hclge_vport *vport = hclge_get_vport(handle);
5702
5703 return hclge_rm_mc_addr_common(vport, addr);
5704}
5705
5706int hclge_rm_mc_addr_common(struct hclge_vport *vport,
5707 const unsigned char *addr)
5708{
5709 struct hclge_dev *hdev = vport->back;
d44f9b63 5710 struct hclge_mac_vlan_tbl_entry_cmd req;
46a3df9f
S		 5711 enum hclge_cmd_status status;
5712 struct hclge_desc desc[3];
46a3df9f
S		 5713
5714 /* mac addr check */
5715 if (!is_multicast_ether_addr(addr)) {
5716 dev_dbg(&hdev->pdev->dev,
5717 "Remove mc mac err! invalid mac:%pM.\n",
5718 addr);
5719 return -EINVAL;
5720 }
5721
5722 memset(&req, 0, sizeof(req));
e4e87715
PL		 5723 hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
5724 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0);
5725 hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1);
fd5f9da3 5726 hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 1);
46a3df9f
S		 5727 hclge_prepare_mac_addr(&req, addr);
5728 status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true);
5729 if (!status) {
5730 /* This mac addr exist, remove this handle's VFID for it */
5731 hclge_update_desc_vfid(desc, vport->vport_id, true);
5732
5733 if (hclge_is_all_function_id_zero(desc))
5734 /* All the vfid is zero, so need to delete this entry */
5735 status = hclge_remove_mac_vlan_tbl(vport, &req);
5736 else
5737 /* Not all the vfid is zero, update the vfid */
5738 status = hclge_add_mac_vlan_tbl(vport, &req, desc);
5739
5740 } else {
40cca1c5
XW		 5741 /* Maybe this mac address is in mta table, but it cannot be
5742 * deleted here because an entry of mta represents an address
5743 * range rather than a specific address. the delete action to
5744 * all entries will take effect in update_mta_status called by
5745 * hns3_nic_set_rx_mode.
5746 */
5747 status = 0;
46a3df9f
S		 5748 }
5749
46a3df9f
S		 5750 return status;
5751}
5752
f5aac71c
FL		 5753static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev,
5754 u16 cmdq_resp, u8 resp_code)
5755{
5756#define HCLGE_ETHERTYPE_SUCCESS_ADD 0
5757#define HCLGE_ETHERTYPE_ALREADY_ADD 1
5758#define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2
5759#define HCLGE_ETHERTYPE_KEY_CONFLICT 3
5760
5761 int return_status;
5762
5763 if (cmdq_resp) {
5764 dev_err(&hdev->pdev->dev,
5765 "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n",
5766 cmdq_resp);
5767 return -EIO;
5768 }
5769
5770 switch (resp_code) {
5771 case HCLGE_ETHERTYPE_SUCCESS_ADD:
5772 case HCLGE_ETHERTYPE_ALREADY_ADD:
5773 return_status = 0;
5774 break;
5775 case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW:
5776 dev_err(&hdev->pdev->dev,
5777 "add mac ethertype failed for manager table overflow.\n");
5778 return_status = -EIO;
5779 break;
5780 case HCLGE_ETHERTYPE_KEY_CONFLICT:
5781 dev_err(&hdev->pdev->dev,
5782 "add mac ethertype failed for key conflict.\n");
5783 return_status = -EIO;
5784 break;
5785 default:
5786 dev_err(&hdev->pdev->dev,
5787 "add mac ethertype failed for undefined, code=%d.\n",
5788 resp_code);
5789 return_status = -EIO;
5790 }
5791
5792 return return_status;
5793}
5794
5795static int hclge_add_mgr_tbl(struct hclge_dev *hdev,
5796 const struct hclge_mac_mgr_tbl_entry_cmd *req)
5797{
5798 struct hclge_desc desc;
5799 u8 resp_code;
5800 u16 retval;
5801 int ret;
5802
5803 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false);
5804 memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd));
5805
5806 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
5807 if (ret) {
5808 dev_err(&hdev->pdev->dev,
5809 "add mac ethertype failed for cmd_send, ret =%d.\n",
5810 ret);
5811 return ret;
5812 }
5813
5814 resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff;
5815 retval = le16_to_cpu(desc.retval);
5816
5817 return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code);
5818}
5819
5820static int init_mgr_tbl(struct hclge_dev *hdev)
5821{
5822 int ret;
5823 int i;
5824
5825 for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) {
5826 ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]);
5827 if (ret) {
5828 dev_err(&hdev->pdev->dev,
5829 "add mac ethertype failed, ret =%d.\n",
5830 ret);
5831 return ret;
5832 }
5833 }
5834
5835 return 0;
5836}
5837
46a3df9f
S		 5838static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p)
5839{
5840 struct hclge_vport *vport = hclge_get_vport(handle);
5841 struct hclge_dev *hdev = vport->back;
5842
5843 ether_addr_copy(p, hdev->hw.mac.mac_addr);
5844}
5845
59098055
FL		 5846static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p,
5847 bool is_first)
46a3df9f
S		 5848{
5849 const unsigned char *new_addr = (const unsigned char *)p;
5850 struct hclge_vport *vport = hclge_get_vport(handle);
5851 struct hclge_dev *hdev = vport->back;
18838d0c 5852 int ret;
46a3df9f
S		 5853
5854 /* mac addr check */
5855 if (is_zero_ether_addr(new_addr) ||
5856 is_broadcast_ether_addr(new_addr) ||
5857 is_multicast_ether_addr(new_addr)) {
5858 dev_err(&hdev->pdev->dev,
5859 "Change uc mac err! invalid mac:%p.\n",
5860 new_addr);
5861 return -EINVAL;
5862 }
5863
59098055 5864 if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 5865 dev_warn(&hdev->pdev->dev,
59098055 5866 "remove old uc mac address fail.\n");
46a3df9f 5867
18838d0c
FL		 5868 ret = hclge_add_uc_addr(handle, new_addr);
5869 if (ret) {
5870 dev_err(&hdev->pdev->dev,
5871 "add uc mac address fail, ret =%d.\n",
5872 ret);
5873
59098055
FL		 5874 if (!is_first &&
5875 hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr))
18838d0c 5876 dev_err(&hdev->pdev->dev,
59098055 5877 "restore uc mac address fail.\n");
18838d0c
FL		 5878
5879 return -EIO;
46a3df9f
S		 5880 }
5881
e98d7183 5882 ret = hclge_pause_addr_cfg(hdev, new_addr);
18838d0c
FL		 5883 if (ret) {
5884 dev_err(&hdev->pdev->dev,
5885 "configure mac pause address fail, ret =%d.\n",
5886 ret);
5887 return -EIO;
5888 }
5889
5890 ether_addr_copy(hdev->hw.mac.mac_addr, new_addr);
5891
5892 return 0;
46a3df9f
S		 5893}
5894
26483246
XW		 5895static int hclge_do_ioctl(struct hnae3_handle *handle, struct ifreq *ifr,
5896 int cmd)
5897{
5898 struct hclge_vport *vport = hclge_get_vport(handle);
5899 struct hclge_dev *hdev = vport->back;
5900
5901 if (!hdev->hw.mac.phydev)
5902 return -EOPNOTSUPP;
5903
5904 return phy_mii_ioctl(hdev->hw.mac.phydev, ifr, cmd);
5905}
5906
46a3df9f 5907static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type,
64d114f0 5908 u8 fe_type, bool filter_en)
46a3df9f 5909{
d44f9b63 5910 struct hclge_vlan_filter_ctrl_cmd *req;
46a3df9f
S		 5911 struct hclge_desc desc;
5912 int ret;
5913
5914 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false);
5915
d44f9b63 5916 req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data;
46a3df9f 5917 req->vlan_type = vlan_type;
64d114f0 5918 req->vlan_fe = filter_en ? fe_type : 0;
46a3df9f
S		 5919
5920 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 5921 if (ret)
46a3df9f
S		 5922 dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n",
5923 ret);
46a3df9f 5924
3f639907 5925 return ret;
46a3df9f
S		 5926}
5927
391b5e93
JS		 5928#define HCLGE_FILTER_TYPE_VF 0
5929#define HCLGE_FILTER_TYPE_PORT 1
64d114f0
ZL		 5930#define HCLGE_FILTER_FE_EGRESS_V1_B BIT(0)
5931#define HCLGE_FILTER_FE_NIC_INGRESS_B BIT(0)
5932#define HCLGE_FILTER_FE_NIC_EGRESS_B BIT(1)
5933#define HCLGE_FILTER_FE_ROCE_INGRESS_B BIT(2)
5934#define HCLGE_FILTER_FE_ROCE_EGRESS_B BIT(3)
5935#define HCLGE_FILTER_FE_EGRESS (HCLGE_FILTER_FE_NIC_EGRESS_B \
5936 | HCLGE_FILTER_FE_ROCE_EGRESS_B)
5937#define HCLGE_FILTER_FE_INGRESS (HCLGE_FILTER_FE_NIC_INGRESS_B \
5938 | HCLGE_FILTER_FE_ROCE_INGRESS_B)
391b5e93
JS		 5939
5940static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable)
5941{
5942 struct hclge_vport *vport = hclge_get_vport(handle);
5943 struct hclge_dev *hdev = vport->back;
5944
64d114f0
ZL		 5945 if (hdev->pdev->revision >= 0x21) {
5946 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5947 HCLGE_FILTER_FE_EGRESS, enable);
5948 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
5949 HCLGE_FILTER_FE_INGRESS, enable);
5950 } else {
5951 hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
5952 HCLGE_FILTER_FE_EGRESS_V1_B, enable);
5953 }
c60edc17
JS		 5954 if (enable)
5955 handle->netdev_flags |= HNAE3_VLAN_FLTR;
5956 else
5957 handle->netdev_flags &= ~HNAE3_VLAN_FLTR;
391b5e93
JS		 5958}
5959
dc8131d8
YL		 5960static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid,
5961 bool is_kill, u16 vlan, u8 qos,
5962 __be16 proto)
46a3df9f
S		 5963{
5964#define HCLGE_MAX_VF_BYTES 16
d44f9b63
YL		 5965 struct hclge_vlan_filter_vf_cfg_cmd *req0;
5966 struct hclge_vlan_filter_vf_cfg_cmd *req1;
46a3df9f
S		 5967 struct hclge_desc desc[2];
5968 u8 vf_byte_val;
5969 u8 vf_byte_off;
5970 int ret;
5971
5972 hclge_cmd_setup_basic_desc(&desc[0],
5973 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
5974 hclge_cmd_setup_basic_desc(&desc[1],
5975 HCLGE_OPC_VLAN_FILTER_VF_CFG, false);
5976
5977 desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
5978
5979 vf_byte_off = vfid / 8;
5980 vf_byte_val = 1 << (vfid % 8);
5981
d44f9b63
YL		 5982 req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data;
5983 req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data;
46a3df9f 5984
a90bb9a5 5985 req0->vlan_id = cpu_to_le16(vlan);
46a3df9f
S		 5986 req0->vlan_cfg = is_kill;
5987
5988 if (vf_byte_off < HCLGE_MAX_VF_BYTES)
5989 req0->vf_bitmap[vf_byte_off] = vf_byte_val;
5990 else
5991 req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val;
5992
5993 ret = hclge_cmd_send(&hdev->hw, desc, 2);
5994 if (ret) {
5995 dev_err(&hdev->pdev->dev,
5996 "Send vf vlan command fail, ret =%d.\n",
5997 ret);
5998 return ret;
5999 }
6000
6001 if (!is_kill) {
6c251711 6002#define HCLGE_VF_VLAN_NO_ENTRY 2
46a3df9f
S		 6003 if (!req0->resp_code || req0->resp_code == 1)
6004 return 0;
6005
6c251711
YL		 6006 if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) {
6007 dev_warn(&hdev->pdev->dev,
6008 "vf vlan table is full, vf vlan filter is disabled\n");
6009 return 0;
6010 }
6011
46a3df9f
S		 6012 dev_err(&hdev->pdev->dev,
6013 "Add vf vlan filter fail, ret =%d.\n",
6014 req0->resp_code);
6015 } else {
41dafea2 6016#define HCLGE_VF_VLAN_DEL_NO_FOUND 1
46a3df9f
S		 6017 if (!req0->resp_code)
6018 return 0;
6019
41dafea2
YL		 6020 if (req0->resp_code == HCLGE_VF_VLAN_DEL_NO_FOUND) {
6021 dev_warn(&hdev->pdev->dev,
6022 "vlan %d filter is not in vf vlan table\n",
6023 vlan);
6024 return 0;
6025 }
6026
46a3df9f
S		 6027 dev_err(&hdev->pdev->dev,
6028 "Kill vf vlan filter fail, ret =%d.\n",
6029 req0->resp_code);
6030 }
6031
6032 return -EIO;
6033}
6034
dc8131d8
YL		 6035static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto,
6036 u16 vlan_id, bool is_kill)
46a3df9f 6037{
d44f9b63 6038 struct hclge_vlan_filter_pf_cfg_cmd *req;
46a3df9f
S		 6039 struct hclge_desc desc;
6040 u8 vlan_offset_byte_val;
6041 u8 vlan_offset_byte;
6042 u8 vlan_offset_160;
6043 int ret;
6044
6045 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false);
6046
6047 vlan_offset_160 = vlan_id / 160;
6048 vlan_offset_byte = (vlan_id % 160) / 8;
6049 vlan_offset_byte_val = 1 << (vlan_id % 8);
6050
d44f9b63 6051 req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data;
46a3df9f
S		 6052 req->vlan_offset = vlan_offset_160;
6053 req->vlan_cfg = is_kill;
6054 req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val;
6055
6056 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
dc8131d8
YL		 6057 if (ret)
6058 dev_err(&hdev->pdev->dev,
6059 "port vlan command, send fail, ret =%d.\n", ret);
6060 return ret;
6061}
6062
6063static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto,
6064 u16 vport_id, u16 vlan_id, u8 qos,
6065 bool is_kill)
6066{
6067 u16 vport_idx, vport_num = 0;
6068 int ret;
6069
daaa8521
YL		 6070 if (is_kill && !vlan_id)
6071 return 0;
6072
dc8131d8
YL		 6073 ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id,
6074 0, proto);
46a3df9f
S		 6075 if (ret) {
6076 dev_err(&hdev->pdev->dev,
dc8131d8
YL		 6077 "Set %d vport vlan filter config fail, ret =%d.\n",
6078 vport_id, ret);
46a3df9f
S		 6079 return ret;
6080 }
6081
dc8131d8
YL		 6082 /* vlan 0 may be added twice when 8021q module is enabled */
6083 if (!is_kill && !vlan_id &&
6084 test_bit(vport_id, hdev->vlan_table[vlan_id]))
6085 return 0;
6086
6087 if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) {
46a3df9f 6088 dev_err(&hdev->pdev->dev,
dc8131d8
YL		 6089 "Add port vlan failed, vport %d is already in vlan %d\n",
6090 vport_id, vlan_id);
6091 return -EINVAL;
46a3df9f
S		 6092 }
6093
dc8131d8
YL		 6094 if (is_kill &&
6095 !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) {
6096 dev_err(&hdev->pdev->dev,
6097 "Delete port vlan failed, vport %d is not in vlan %d\n",
6098 vport_id, vlan_id);
6099 return -EINVAL;
6100 }
6101
54e97d11 6102 for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], HCLGE_VPORT_NUM)
dc8131d8
YL		 6103 vport_num++;
6104
6105 if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1))
6106 ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id,
6107 is_kill);
6108
6109 return ret;
6110}
6111
6112int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
6113 u16 vlan_id, bool is_kill)
6114{
6115 struct hclge_vport *vport = hclge_get_vport(handle);
6116 struct hclge_dev *hdev = vport->back;
6117
6118 return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id,
6119 0, is_kill);
46a3df9f
S		 6120}
6121
6122static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid,
6123 u16 vlan, u8 qos, __be16 proto)
6124{
6125 struct hclge_vport *vport = hclge_get_vport(handle);
6126 struct hclge_dev *hdev = vport->back;
6127
6128 if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7))
6129 return -EINVAL;
6130 if (proto != htons(ETH_P_8021Q))
6131 return -EPROTONOSUPPORT;
6132
dc8131d8 6133 return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false);
46a3df9f
S		 6134}
6135
5f6ea83f
PL		 6136static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport)
6137{
6138 struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg;
6139 struct hclge_vport_vtag_tx_cfg_cmd *req;
6140 struct hclge_dev *hdev = vport->back;
6141 struct hclge_desc desc;
6142 int status;
6143
6144 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false);
6145
6146 req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data;
6147 req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1);
6148 req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2);
e4e87715
PL		 6149 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B,
6150 vcfg->accept_tag1 ? 1 : 0);
6151 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B,
6152 vcfg->accept_untag1 ? 1 : 0);
6153 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B,
6154 vcfg->accept_tag2 ? 1 : 0);
6155 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B,
6156 vcfg->accept_untag2 ? 1 : 0);
6157 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B,
6158 vcfg->insert_tag1_en ? 1 : 0);
6159 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B,
6160 vcfg->insert_tag2_en ? 1 : 0);
6161 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0);
5f6ea83f
PL		 6162
6163 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
6164 req->vf_bitmap[req->vf_offset] =
6165 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
6166
6167 status = hclge_cmd_send(&hdev->hw, &desc, 1);
6168 if (status)
6169 dev_err(&hdev->pdev->dev,
6170 "Send port txvlan cfg command fail, ret =%d\n",
6171 status);
6172
6173 return status;
6174}
6175
6176static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport)
6177{
6178 struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg;
6179 struct hclge_vport_vtag_rx_cfg_cmd *req;
6180 struct hclge_dev *hdev = vport->back;
6181 struct hclge_desc desc;
6182 int status;
6183
6184 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false);
6185
6186 req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data;
e4e87715
PL		 6187 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B,
6188 vcfg->strip_tag1_en ? 1 : 0);
6189 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B,
6190 vcfg->strip_tag2_en ? 1 : 0);
6191 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B,
6192 vcfg->vlan1_vlan_prionly ? 1 : 0);
6193 hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B,
6194 vcfg->vlan2_vlan_prionly ? 1 : 0);
5f6ea83f
PL		 6195
6196 req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD;
6197 req->vf_bitmap[req->vf_offset] =
6198 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE);
6199
6200 status = hclge_cmd_send(&hdev->hw, &desc, 1);
6201 if (status)
6202 dev_err(&hdev->pdev->dev,
6203 "Send port rxvlan cfg command fail, ret =%d\n",
6204 status);
6205
6206 return status;
6207}
6208
6209static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev)
6210{
6211 struct hclge_rx_vlan_type_cfg_cmd *rx_req;
6212 struct hclge_tx_vlan_type_cfg_cmd *tx_req;
6213 struct hclge_desc desc;
6214 int status;
6215
6216 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false);
6217 rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data;
6218 rx_req->ot_fst_vlan_type =
6219 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type);
6220 rx_req->ot_sec_vlan_type =
6221 cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type);
6222 rx_req->in_fst_vlan_type =
6223 cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type);
6224 rx_req->in_sec_vlan_type =
6225 cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type);
6226
6227 status = hclge_cmd_send(&hdev->hw, &desc, 1);
6228 if (status) {
6229 dev_err(&hdev->pdev->dev,
6230 "Send rxvlan protocol type command fail, ret =%d\n",
6231 status);
6232 return status;
6233 }
6234
6235 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false);
6236
d0d72bac 6237 tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)desc.data;
5f6ea83f
PL		 6238 tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type);
6239 tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type);
6240
6241 status = hclge_cmd_send(&hdev->hw, &desc, 1);
6242 if (status)
6243 dev_err(&hdev->pdev->dev,
6244 "Send txvlan protocol type command fail, ret =%d\n",
6245 status);
6246
6247 return status;
6248}
6249
46a3df9f
S		 6250static int hclge_init_vlan_config(struct hclge_dev *hdev)
6251{
5f6ea83f
PL		 6252#define HCLGE_DEF_VLAN_TYPE 0x8100
6253
c60edc17 6254 struct hnae3_handle *handle = &hdev->vport[0].nic;
5f6ea83f 6255 struct hclge_vport *vport;
46a3df9f 6256 int ret;
5f6ea83f
PL		 6257 int i;
6258
64d114f0
ZL		 6259 if (hdev->pdev->revision >= 0x21) {
6260 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6261 HCLGE_FILTER_FE_EGRESS, true);
6262 if (ret)
6263 return ret;
46a3df9f 6264
64d114f0
ZL		 6265 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT,
6266 HCLGE_FILTER_FE_INGRESS, true);
6267 if (ret)
6268 return ret;
6269 } else {
6270 ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF,
6271 HCLGE_FILTER_FE_EGRESS_V1_B,
6272 true);
6273 if (ret)
6274 return ret;
6275 }
46a3df9f 6276
c60edc17
JS		 6277 handle->netdev_flags |= HNAE3_VLAN_FLTR;
6278
5f6ea83f
PL		 6279 hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
6280 hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
6281 hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE;
6282 hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE;
6283 hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE;
6284 hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE;
6285
6286 ret = hclge_set_vlan_protocol_type(hdev);
5e43aef8
L		 6287 if (ret)
6288 return ret;
46a3df9f 6289
5f6ea83f
PL		 6290 for (i = 0; i < hdev->num_alloc_vport; i++) {
6291 vport = &hdev->vport[i];
dcb35cce
PL		 6292 vport->txvlan_cfg.accept_tag1 = true;
6293 vport->txvlan_cfg.accept_untag1 = true;
6294
6295 /* accept_tag2 and accept_untag2 are not supported on
6296 * pdev revision(0x20), new revision support them. The
6297 * value of this two fields will not return error when driver
6298 * send command to fireware in revision(0x20).
6299 * This two fields can not configured by user.
6300 */
6301 vport->txvlan_cfg.accept_tag2 = true;
6302 vport->txvlan_cfg.accept_untag2 = true;
6303
5f6ea83f
PL		 6304 vport->txvlan_cfg.insert_tag1_en = false;
6305 vport->txvlan_cfg.insert_tag2_en = false;
6306 vport->txvlan_cfg.default_tag1 = 0;
6307 vport->txvlan_cfg.default_tag2 = 0;
6308
6309 ret = hclge_set_vlan_tx_offload_cfg(vport);
6310 if (ret)
6311 return ret;
6312
6313 vport->rxvlan_cfg.strip_tag1_en = false;
6314 vport->rxvlan_cfg.strip_tag2_en = true;
6315 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6316 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6317
6318 ret = hclge_set_vlan_rx_offload_cfg(vport);
6319 if (ret)
6320 return ret;
6321 }
6322
dc8131d8 6323 return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false);
46a3df9f
S		 6324}
6325
b2641e2a 6326int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable)
052ece6d
PL		 6327{
6328 struct hclge_vport *vport = hclge_get_vport(handle);
6329
6330 vport->rxvlan_cfg.strip_tag1_en = false;
6331 vport->rxvlan_cfg.strip_tag2_en = enable;
6332 vport->rxvlan_cfg.vlan1_vlan_prionly = false;
6333 vport->rxvlan_cfg.vlan2_vlan_prionly = false;
6334
6335 return hclge_set_vlan_rx_offload_cfg(vport);
6336}
6337
dd72140c 6338static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu)
46a3df9f 6339{
d44f9b63 6340 struct hclge_config_max_frm_size_cmd *req;
46a3df9f 6341 struct hclge_desc desc;
2866ccb2 6342 int max_frm_size;
46a3df9f
S		 6343 int ret;
6344
2866ccb2
FL		 6345 max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
6346
6347 if (max_frm_size < HCLGE_MAC_MIN_FRAME ||
6348 max_frm_size > HCLGE_MAC_MAX_FRAME)
46a3df9f
S		 6349 return -EINVAL;
6350
2866ccb2
FL		 6351 max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME);
6352
46a3df9f
S		 6353 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false);
6354
d44f9b63 6355 req = (struct hclge_config_max_frm_size_cmd *)desc.data;
2866ccb2 6356 req->max_frm_size = cpu_to_le16(max_frm_size);
8fc7346c 6357 req->min_frm_size = HCLGE_MAC_MIN_FRAME;
46a3df9f
S		 6358
6359 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
3f639907 6360 if (ret)
46a3df9f 6361 dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret);
3f639907
JS		 6362 else
6363 hdev->mps = max_frm_size;
2866ccb2 6364
3f639907 6365 return ret;
46a3df9f
S		 6366}
6367
dd72140c
FL		 6368static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu)
6369{
6370 struct hclge_vport *vport = hclge_get_vport(handle);
6371 struct hclge_dev *hdev = vport->back;
6372 int ret;
6373
6374 ret = hclge_set_mac_mtu(hdev, new_mtu);
6375 if (ret) {
6376 dev_err(&hdev->pdev->dev,
6377 "Change mtu fail, ret =%d\n", ret);
6378 return ret;
6379 }
6380
6381 ret = hclge_buffer_alloc(hdev);
6382 if (ret)
6383 dev_err(&hdev->pdev->dev,
6384 "Allocate buffer fail, ret =%d\n", ret);
6385
6386 return ret;
6387}
6388
46a3df9f
S		 6389static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id,
6390 bool enable)
6391{
d44f9b63 6392 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 6393 struct hclge_desc desc;
6394 int ret;
6395
6396 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false);
6397
d44f9b63 6398 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f 6399 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
e4e87715 6400 hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable);
46a3df9f
S		 6401
6402 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6403 if (ret) {
6404 dev_err(&hdev->pdev->dev,
6405 "Send tqp reset cmd error, status =%d\n", ret);
6406 return ret;
6407 }
6408
6409 return 0;
6410}
6411
6412static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id)
6413{
d44f9b63 6414 struct hclge_reset_tqp_queue_cmd *req;
46a3df9f
S		 6415 struct hclge_desc desc;
6416 int ret;
6417
6418 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true);
6419
d44f9b63 6420 req = (struct hclge_reset_tqp_queue_cmd *)desc.data;
46a3df9f
S		 6421 req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK);
6422
6423 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
6424 if (ret) {
6425 dev_err(&hdev->pdev->dev,
6426 "Get reset status error, status =%d\n", ret);
6427 return ret;
6428 }
6429
e4e87715 6430 return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B);
46a3df9f
S		 6431}
6432
814e0274
PL		 6433static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle,
6434 u16 queue_id)
6435{
6436 struct hnae3_queue *queue;
6437 struct hclge_tqp *tqp;
6438
6439 queue = handle->kinfo.tqp[queue_id];
6440 tqp = container_of(queue, struct hclge_tqp, q);
6441
6442 return tqp->index;
6443}
6444
7fa6be4f 6445int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id)
46a3df9f
S		 6446{
6447 struct hclge_vport *vport = hclge_get_vport(handle);
6448 struct hclge_dev *hdev = vport->back;
6449 int reset_try_times = 0;
6450 int reset_status;
814e0274 6451 u16 queue_gid;
7fa6be4f 6452 int ret = 0;
46a3df9f 6453
814e0274
PL		 6454 queue_gid = hclge_covert_handle_qid_global(handle, queue_id);
6455
46a3df9f
S		 6456 ret = hclge_tqp_enable(hdev, queue_id, 0, false);
6457 if (ret) {
7fa6be4f
HT		 6458 dev_err(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret);
6459 return ret;
46a3df9f
S		 6460 }
6461
814e0274 6462 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
46a3df9f 6463 if (ret) {
7fa6be4f
HT		 6464 dev_err(&hdev->pdev->dev,
6465 "Send reset tqp cmd fail, ret = %d\n", ret);
6466 return ret;
46a3df9f
S		 6467 }
6468
6469 reset_try_times = 0;
6470 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6471 /* Wait for tqp hw reset */
6472 msleep(20);
814e0274 6473 reset_status = hclge_get_reset_status(hdev, queue_gid);
46a3df9f
S		 6474 if (reset_status)
6475 break;
6476 }
6477
6478 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
7fa6be4f
HT		 6479 dev_err(&hdev->pdev->dev, "Reset TQP fail\n");
6480 return ret;
46a3df9f
S		 6481 }
6482
814e0274 6483 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
7fa6be4f
HT		 6484 if (ret)
6485 dev_err(&hdev->pdev->dev,
6486 "Deassert the soft reset fail, ret = %d\n", ret);
6487
6488 return ret;
46a3df9f
S		 6489}
6490
1a426f8b
PL		 6491void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id)
6492{
6493 struct hclge_dev *hdev = vport->back;
6494 int reset_try_times = 0;
6495 int reset_status;
6496 u16 queue_gid;
6497 int ret;
6498
6499 queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id);
6500
6501 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true);
6502 if (ret) {
6503 dev_warn(&hdev->pdev->dev,
6504 "Send reset tqp cmd fail, ret = %d\n", ret);
6505 return;
6506 }
6507
6508 reset_try_times = 0;
6509 while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) {
6510 /* Wait for tqp hw reset */
6511 msleep(20);
6512 reset_status = hclge_get_reset_status(hdev, queue_gid);
6513 if (reset_status)
6514 break;
6515 }
6516
6517 if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) {
6518 dev_warn(&hdev->pdev->dev, "Reset TQP fail\n");
6519 return;
6520 }
6521
6522 ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false);
6523 if (ret)
6524 dev_warn(&hdev->pdev->dev,
6525 "Deassert the soft reset fail, ret = %d\n", ret);
6526}
6527
46a3df9f
S		 6528static u32 hclge_get_fw_version(struct hnae3_handle *handle)
6529{
6530 struct hclge_vport *vport = hclge_get_vport(handle);
6531 struct hclge_dev *hdev = vport->back;
6532
6533 return hdev->fw_version;
6534}
6535
61387774
PL		 6536static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6537{
6538 struct phy_device *phydev = hdev->hw.mac.phydev;
6539
6540 if (!phydev)
6541 return;
6542
70814e81 6543 phy_set_asym_pause(phydev, rx_en, tx_en);
61387774
PL		 6544}
6545
6546static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en)
6547{
61387774
PL		 6548 int ret;
6549
6550 if (rx_en && tx_en)
40173a2e 6551 hdev->fc_mode_last_time = HCLGE_FC_FULL;
61387774 6552 else if (rx_en && !tx_en)
40173a2e 6553 hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
61387774 6554 else if (!rx_en && tx_en)
40173a2e 6555 hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
61387774 6556 else
40173a2e 6557 hdev->fc_mode_last_time = HCLGE_FC_NONE;
61387774 6558
40173a2e 6559 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
61387774 6560 return 0;
61387774
PL		 6561
6562 ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
6563 if (ret) {
6564 dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n",
6565 ret);
6566 return ret;
6567 }
6568
40173a2e 6569 hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
61387774
PL		 6570
6571 return 0;
6572}
6573
1770a7a3
PL		 6574int hclge_cfg_flowctrl(struct hclge_dev *hdev)
6575{
6576 struct phy_device *phydev = hdev->hw.mac.phydev;
6577 u16 remote_advertising = 0;
6578 u16 local_advertising = 0;
6579 u32 rx_pause, tx_pause;
6580 u8 flowctl;
6581
6582 if (!phydev->link || !phydev->autoneg)
6583 return 0;
6584
5f991f7b 6585 local_advertising = ethtool_adv_to_lcl_adv_t(phydev->advertising);
1770a7a3
PL		 6586
6587 if (phydev->pause)
6588 remote_advertising = LPA_PAUSE_CAP;
6589
6590 if (phydev->asym_pause)
6591 remote_advertising |= LPA_PAUSE_ASYM;
6592
6593 flowctl = mii_resolve_flowctrl_fdx(local_advertising,
6594 remote_advertising);
6595 tx_pause = flowctl & FLOW_CTRL_TX;
6596 rx_pause = flowctl & FLOW_CTRL_RX;
6597
6598 if (phydev->duplex == HCLGE_MAC_HALF) {
6599 tx_pause = 0;
6600 rx_pause = 0;
6601 }
6602
6603 return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause);
6604}
6605
46a3df9f
S		 6606static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg,
6607 u32 *rx_en, u32 *tx_en)
6608{
6609 struct hclge_vport *vport = hclge_get_vport(handle);
6610 struct hclge_dev *hdev = vport->back;
6611
6612 *auto_neg = hclge_get_autoneg(handle);
6613
6614 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6615 *rx_en = 0;
6616 *tx_en = 0;
6617 return;
6618 }
6619
6620 if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) {
6621 *rx_en = 1;
6622 *tx_en = 0;
6623 } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) {
6624 *tx_en = 1;
6625 *rx_en = 0;
6626 } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) {
6627 *rx_en = 1;
6628 *tx_en = 1;
6629 } else {
6630 *rx_en = 0;
6631 *tx_en = 0;
6632 }
6633}
6634
61387774
PL		 6635static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
6636 u32 rx_en, u32 tx_en)
6637{
6638 struct hclge_vport *vport = hclge_get_vport(handle);
6639 struct hclge_dev *hdev = vport->back;
6640 struct phy_device *phydev = hdev->hw.mac.phydev;
6641 u32 fc_autoneg;
6642
61387774
PL		 6643 fc_autoneg = hclge_get_autoneg(handle);
6644 if (auto_neg != fc_autoneg) {
6645 dev_info(&hdev->pdev->dev,
6646 "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n");
6647 return -EOPNOTSUPP;
6648 }
6649
6650 if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) {
6651 dev_info(&hdev->pdev->dev,
6652 "Priority flow control enabled. Cannot set link flow control.\n");
6653 return -EOPNOTSUPP;
6654 }
6655
6656 hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
6657
6658 if (!fc_autoneg)
6659 return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
6660
0c963e8c
FL		 6661 /* Only support flow control negotiation for netdev with
6662 * phy attached for now.
6663 */
6664 if (!phydev)
6665 return -EOPNOTSUPP;
6666
61387774
PL		 6667 return phy_start_aneg(phydev);
6668}
6669
46a3df9f
S		 6670static void hclge_get_ksettings_an_result(struct hnae3_handle *handle,
6671 u8 *auto_neg, u32 *speed, u8 *duplex)
6672{
6673 struct hclge_vport *vport = hclge_get_vport(handle);
6674 struct hclge_dev *hdev = vport->back;
6675
6676 if (speed)
6677 *speed = hdev->hw.mac.speed;
6678 if (duplex)
6679 *duplex = hdev->hw.mac.duplex;
6680 if (auto_neg)
6681 *auto_neg = hdev->hw.mac.autoneg;
6682}
6683
6684static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type)
6685{
6686 struct hclge_vport *vport = hclge_get_vport(handle);
6687 struct hclge_dev *hdev = vport->back;
6688
6689 if (media_type)
6690 *media_type = hdev->hw.mac.media_type;
6691}
6692
6693static void hclge_get_mdix_mode(struct hnae3_handle *handle,
6694 u8 *tp_mdix_ctrl, u8 *tp_mdix)
6695{
6696 struct hclge_vport *vport = hclge_get_vport(handle);
6697 struct hclge_dev *hdev = vport->back;
6698 struct phy_device *phydev = hdev->hw.mac.phydev;
6699 int mdix_ctrl, mdix, retval, is_resolved;
6700
6701 if (!phydev) {
6702 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6703 *tp_mdix = ETH_TP_MDI_INVALID;
6704 return;
6705 }
6706
6707 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX);
6708
6709 retval = phy_read(phydev, HCLGE_PHY_CSC_REG);
e4e87715
PL		 6710 mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M,
6711 HCLGE_PHY_MDIX_CTRL_S);
46a3df9f
S		 6712
6713 retval = phy_read(phydev, HCLGE_PHY_CSS_REG);
e4e87715
PL		 6714 mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B);
6715 is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B);
46a3df9f
S		 6716
6717 phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER);
6718
6719 switch (mdix_ctrl) {
6720 case 0x0:
6721 *tp_mdix_ctrl = ETH_TP_MDI;
6722 break;
6723 case 0x1:
6724 *tp_mdix_ctrl = ETH_TP_MDI_X;
6725 break;
6726 case 0x3:
6727 *tp_mdix_ctrl = ETH_TP_MDI_AUTO;
6728 break;
6729 default:
6730 *tp_mdix_ctrl = ETH_TP_MDI_INVALID;
6731 break;
6732 }
6733
6734 if (!is_resolved)
6735 *tp_mdix = ETH_TP_MDI_INVALID;
6736 else if (mdix)
6737 *tp_mdix = ETH_TP_MDI_X;
6738 else
6739 *tp_mdix = ETH_TP_MDI;
6740}
6741
b01b7cf1
FL		 6742static int hclge_init_instance_hw(struct hclge_dev *hdev)
6743{
6744 return hclge_mac_connect_phy(hdev);
6745}
6746
6747static void hclge_uninit_instance_hw(struct hclge_dev *hdev)
6748{
6749 hclge_mac_disconnect_phy(hdev);
6750}
6751
46a3df9f
S		 6752static int hclge_init_client_instance(struct hnae3_client *client,
6753 struct hnae3_ae_dev *ae_dev)
6754{
6755 struct hclge_dev *hdev = ae_dev->priv;
6756 struct hclge_vport *vport;
6757 int i, ret;
6758
6759 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
6760 vport = &hdev->vport[i];
6761
6762 switch (client->type) {
6763 case HNAE3_CLIENT_KNIC:
6764
6765 hdev->nic_client = client;
6766 vport->nic.client = client;
6767 ret = client->ops->init_instance(&vport->nic);
6768 if (ret)
49dd8054 6769 goto clear_nic;
46a3df9f 6770
b01b7cf1
FL		 6771 ret = hclge_init_instance_hw(hdev);
6772 if (ret) {
6773 client->ops->uninit_instance(&vport->nic,
6774 0);
49dd8054 6775 goto clear_nic;
b01b7cf1
FL		 6776 }
6777
d9f28fc2
JS		 6778 hnae3_set_client_init_flag(client, ae_dev, 1);
6779
46a3df9f 6780 if (hdev->roce_client &&
e92a0843 6781 hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 6782 struct hnae3_client *rc = hdev->roce_client;
6783
6784 ret = hclge_init_roce_base_info(vport);
6785 if (ret)
49dd8054 6786 goto clear_roce;
46a3df9f
S		 6787
6788 ret = rc->ops->init_instance(&vport->roce);
6789 if (ret)
49dd8054 6790 goto clear_roce;
d9f28fc2
JS		 6791
6792 hnae3_set_client_init_flag(hdev->roce_client,
6793 ae_dev, 1);
46a3df9f
S		 6794 }
6795
6796 break;
6797 case HNAE3_CLIENT_UNIC:
6798 hdev->nic_client = client;
6799 vport->nic.client = client;
6800
6801 ret = client->ops->init_instance(&vport->nic);
6802 if (ret)
49dd8054 6803 goto clear_nic;
46a3df9f 6804
d9f28fc2
JS		 6805 hnae3_set_client_init_flag(client, ae_dev, 1);
6806
46a3df9f
S		 6807 break;
6808 case HNAE3_CLIENT_ROCE:
e92a0843 6809 if (hnae3_dev_roce_supported(hdev)) {
46a3df9f
S		 6810 hdev->roce_client = client;
6811 vport->roce.client = client;
6812 }
6813
3a46f34d 6814 if (hdev->roce_client && hdev->nic_client) {
46a3df9f
S		 6815 ret = hclge_init_roce_base_info(vport);
6816 if (ret)
49dd8054 6817 goto clear_roce;
46a3df9f
S		 6818
6819 ret = client->ops->init_instance(&vport->roce);
6820 if (ret)
49dd8054 6821 goto clear_roce;
d9f28fc2
JS		 6822
6823 hnae3_set_client_init_flag(client, ae_dev, 1);
46a3df9f 6824 }
fa7a4bd5
JS		 6825
6826 break;
6827 default:
6828 return -EINVAL;
46a3df9f
S		 6829 }
6830 }
6831
6832 return 0;
49dd8054
JS		 6833
6834clear_nic:
6835 hdev->nic_client = NULL;
6836 vport->nic.client = NULL;
6837 return ret;
6838clear_roce:
6839 hdev->roce_client = NULL;
6840 vport->roce.client = NULL;
6841 return ret;
46a3df9f
S		 6842}
6843
6844static void hclge_uninit_client_instance(struct hnae3_client *client,
6845 struct hnae3_ae_dev *ae_dev)
6846{
6847 struct hclge_dev *hdev = ae_dev->priv;
6848 struct hclge_vport *vport;
6849 int i;
6850
6851 for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
6852 vport = &hdev->vport[i];
a17dcf3f 6853 if (hdev->roce_client) {
46a3df9f
S		 6854 hdev->roce_client->ops->uninit_instance(&vport->roce,
6855 0);
a17dcf3f
L		 6856 hdev->roce_client = NULL;
6857 vport->roce.client = NULL;
6858 }
46a3df9f
S		 6859 if (client->type == HNAE3_CLIENT_ROCE)
6860 return;
49dd8054 6861 if (hdev->nic_client && client->ops->uninit_instance) {
b01b7cf1 6862 hclge_uninit_instance_hw(hdev);
46a3df9f 6863 client->ops->uninit_instance(&vport->nic, 0);
a17dcf3f
L		 6864 hdev->nic_client = NULL;
6865 vport->nic.client = NULL;
6866 }
46a3df9f
S		 6867 }
6868}
6869
6870static int hclge_pci_init(struct hclge_dev *hdev)
6871{
6872 struct pci_dev *pdev = hdev->pdev;
6873 struct hclge_hw *hw;
6874 int ret;
6875
6876 ret = pci_enable_device(pdev);
6877 if (ret) {
6878 dev_err(&pdev->dev, "failed to enable PCI device\n");
3e249d3b 6879 return ret;
46a3df9f
S		 6880 }
6881
6882 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
6883 if (ret) {
6884 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
6885 if (ret) {
6886 dev_err(&pdev->dev,
6887 "can't set consistent PCI DMA");
6888 goto err_disable_device;
6889 }
6890 dev_warn(&pdev->dev, "set DMA mask to 32 bits\n");
6891 }
6892
6893 ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME);
6894 if (ret) {
6895 dev_err(&pdev->dev, "PCI request regions failed %d\n", ret);
6896 goto err_disable_device;
6897 }
6898
6899 pci_set_master(pdev);
6900 hw = &hdev->hw;
46a3df9f
S		 6901 hw->io_base = pcim_iomap(pdev, 2, 0);
6902 if (!hw->io_base) {
6903 dev_err(&pdev->dev, "Can't map configuration register space\n");
6904 ret = -ENOMEM;
6905 goto err_clr_master;
6906 }
6907
709eb41a
L		 6908 hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev);
6909
46a3df9f
S		 6910 return 0;
6911err_clr_master:
6912 pci_clear_master(pdev);
6913 pci_release_regions(pdev);
6914err_disable_device:
6915 pci_disable_device(pdev);
46a3df9f
S		 6916
6917 return ret;
6918}
6919
6920static void hclge_pci_uninit(struct hclge_dev *hdev)
6921{
6922 struct pci_dev *pdev = hdev->pdev;
6923
6a814413 6924 pcim_iounmap(pdev, hdev->hw.io_base);
887c3820 6925 pci_free_irq_vectors(pdev);
46a3df9f
S		 6926 pci_clear_master(pdev);
6927 pci_release_mem_regions(pdev);
6928 pci_disable_device(pdev);
6929}
6930
48569cda
PL		 6931static void hclge_state_init(struct hclge_dev *hdev)
6932{
6933 set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state);
6934 set_bit(HCLGE_STATE_DOWN, &hdev->state);
6935 clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state);
6936 clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state);
6937 clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state);
6938 clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state);
6939}
6940
6941static void hclge_state_uninit(struct hclge_dev *hdev)
6942{
6943 set_bit(HCLGE_STATE_DOWN, &hdev->state);
6944
6945 if (hdev->service_timer.function)
6946 del_timer_sync(&hdev->service_timer);
65e41e7e
HT		 6947 if (hdev->reset_timer.function)
6948 del_timer_sync(&hdev->reset_timer);
48569cda
PL		 6949 if (hdev->service_task.func)
6950 cancel_work_sync(&hdev->service_task);
6951 if (hdev->rst_service_task.func)
6952 cancel_work_sync(&hdev->rst_service_task);
6953 if (hdev->mbx_service_task.func)
6954 cancel_work_sync(&hdev->mbx_service_task);
6955}
6956
6b9a97ee
HT		 6957static void hclge_flr_prepare(struct hnae3_ae_dev *ae_dev)
6958{
6959#define HCLGE_FLR_WAIT_MS 100
6960#define HCLGE_FLR_WAIT_CNT 50
6961 struct hclge_dev *hdev = ae_dev->priv;
6962 int cnt = 0;
6963
6964 clear_bit(HNAE3_FLR_DOWN, &hdev->flr_state);
6965 clear_bit(HNAE3_FLR_DONE, &hdev->flr_state);
6966 set_bit(HNAE3_FLR_RESET, &hdev->default_reset_request);
6967 hclge_reset_event(hdev->pdev, NULL);
6968
6969 while (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state) &&
6970 cnt++ < HCLGE_FLR_WAIT_CNT)
6971 msleep(HCLGE_FLR_WAIT_MS);
6972
6973 if (!test_bit(HNAE3_FLR_DOWN, &hdev->flr_state))
6974 dev_err(&hdev->pdev->dev,
6975 "flr wait down timeout: %d\n", cnt);
6976}
6977
6978static void hclge_flr_done(struct hnae3_ae_dev *ae_dev)
6979{
6980 struct hclge_dev *hdev = ae_dev->priv;
6981
6982 set_bit(HNAE3_FLR_DONE, &hdev->flr_state);
6983}
6984
46a3df9f
S		 6985static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev)
6986{
6987 struct pci_dev *pdev = ae_dev->pdev;
46a3df9f
S		 6988 struct hclge_dev *hdev;
6989 int ret;
6990
6991 hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL);
6992 if (!hdev) {
6993 ret = -ENOMEM;
ffd5656e 6994 goto out;
46a3df9f
S		 6995 }
6996
46a3df9f
S		 6997 hdev->pdev = pdev;
6998 hdev->ae_dev = ae_dev;
4ed340ab 6999 hdev->reset_type = HNAE3_NONE_RESET;
0742ed7c 7000 hdev->reset_level = HNAE3_FUNC_RESET;
46a3df9f
S		 7001 ae_dev->priv = hdev;
7002
46a3df9f
S		 7003 ret = hclge_pci_init(hdev);
7004 if (ret) {
7005 dev_err(&pdev->dev, "PCI init failed\n");
ffd5656e 7006 goto out;
46a3df9f
S		 7007 }
7008
3efb960f
L		 7009 /* Firmware command queue initialize */
7010 ret = hclge_cmd_queue_init(hdev);
7011 if (ret) {
7012 dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret);
ffd5656e 7013 goto err_pci_uninit;
3efb960f
L		 7014 }
7015
7016 /* Firmware command initialize */
46a3df9f
S		 7017 ret = hclge_cmd_init(hdev);
7018 if (ret)
ffd5656e 7019 goto err_cmd_uninit;
46a3df9f
S		 7020
7021 ret = hclge_get_cap(hdev);
7022 if (ret) {
e00e2197
CIK		 7023 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
7024 ret);
ffd5656e 7025 goto err_cmd_uninit;
46a3df9f
S		 7026 }
7027
7028 ret = hclge_configure(hdev);
7029 if (ret) {
7030 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
ffd5656e 7031 goto err_cmd_uninit;
46a3df9f
S		 7032 }
7033
887c3820 7034 ret = hclge_init_msi(hdev);
46a3df9f 7035 if (ret) {
887c3820 7036 dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret);
ffd5656e 7037 goto err_cmd_uninit;
46a3df9f
S		 7038 }
7039
466b0c00
L		 7040 ret = hclge_misc_irq_init(hdev);
7041 if (ret) {
7042 dev_err(&pdev->dev,
7043 "Misc IRQ(vector0) init error, ret = %d.\n",
7044 ret);
ffd5656e 7045 goto err_msi_uninit;
466b0c00
L		 7046 }
7047
46a3df9f
S		 7048 ret = hclge_alloc_tqps(hdev);
7049 if (ret) {
7050 dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret);
ffd5656e 7051 goto err_msi_irq_uninit;
46a3df9f
S		 7052 }
7053
7054 ret = hclge_alloc_vport(hdev);
7055 if (ret) {
7056 dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret);
ffd5656e 7057 goto err_msi_irq_uninit;
46a3df9f
S		 7058 }
7059
7df7dad6
L		 7060 ret = hclge_map_tqp(hdev);
7061 if (ret) {
7062 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
2312e050 7063 goto err_msi_irq_uninit;
7df7dad6
L		 7064 }
7065
c5ef83cb
HT		 7066 if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) {
7067 ret = hclge_mac_mdio_config(hdev);
7068 if (ret) {
7069 dev_err(&hdev->pdev->dev,
7070 "mdio config fail ret=%d\n", ret);
2312e050 7071 goto err_msi_irq_uninit;
c5ef83cb 7072 }
cf9cca2d 7073 }
7074
39932473
JS		 7075 ret = hclge_init_umv_space(hdev);
7076 if (ret) {
7077 dev_err(&pdev->dev, "umv space init error, ret=%d.\n", ret);
7078 goto err_msi_irq_uninit;
7079 }
7080
46a3df9f
S		 7081 ret = hclge_mac_init(hdev);
7082 if (ret) {
7083 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
ffd5656e 7084 goto err_mdiobus_unreg;
46a3df9f 7085 }
46a3df9f
S		 7086
7087 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
7088 if (ret) {
7089 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
ffd5656e 7090 goto err_mdiobus_unreg;
46a3df9f
S		 7091 }
7092
46a3df9f
S		 7093 ret = hclge_init_vlan_config(hdev);
7094 if (ret) {
7095 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
ffd5656e 7096 goto err_mdiobus_unreg;
46a3df9f
S		 7097 }
7098
7099 ret = hclge_tm_schd_init(hdev);
7100 if (ret) {
7101 dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret);
ffd5656e 7102 goto err_mdiobus_unreg;
68ece54e
YL		 7103 }
7104
268f5dfa 7105 hclge_rss_init_cfg(hdev);
68ece54e
YL		 7106 ret = hclge_rss_init_hw(hdev);
7107 if (ret) {
7108 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
ffd5656e 7109 goto err_mdiobus_unreg;
46a3df9f
S		 7110 }
7111
f5aac71c
FL		 7112 ret = init_mgr_tbl(hdev);
7113 if (ret) {
7114 dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret);
ffd5656e 7115 goto err_mdiobus_unreg;
f5aac71c
FL		 7116 }
7117
d695964d
JS		 7118 ret = hclge_init_fd_config(hdev);
7119 if (ret) {
7120 dev_err(&pdev->dev,
7121 "fd table init fail, ret=%d\n", ret);
7122 goto err_mdiobus_unreg;
7123 }
7124
99714195
SJ		 7125 ret = hclge_hw_error_set_state(hdev, true);
7126 if (ret) {
7127 dev_err(&pdev->dev,
7128 "hw error interrupts enable failed, ret =%d\n", ret);
7129 goto err_mdiobus_unreg;
7130 }
7131
cacde272
YL		 7132 hclge_dcb_ops_set(hdev);
7133
d039ef68 7134 timer_setup(&hdev->service_timer, hclge_service_timer, 0);
65e41e7e 7135 timer_setup(&hdev->reset_timer, hclge_reset_timer, 0);
46a3df9f 7136 INIT_WORK(&hdev->service_task, hclge_service_task);
cb1b9f77 7137 INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task);
c1a81619 7138 INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task);
46a3df9f 7139
8e52a602
XW		 7140 hclge_clear_all_event_cause(hdev);
7141
466b0c00
L		 7142 /* Enable MISC vector(vector0) */
7143 hclge_enable_vector(&hdev->misc_vector, true);
7144
48569cda 7145 hclge_state_init(hdev);
0742ed7c 7146 hdev->last_reset_time = jiffies;
46a3df9f
S		 7147
7148 pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME);
7149 return 0;
7150
ffd5656e
HT		 7151err_mdiobus_unreg:
7152 if (hdev->hw.mac.phydev)
7153 mdiobus_unregister(hdev->hw.mac.mdio_bus);
ffd5656e
HT		 7154err_msi_irq_uninit:
7155 hclge_misc_irq_uninit(hdev);
7156err_msi_uninit:
7157 pci_free_irq_vectors(pdev);
7158err_cmd_uninit:
7159 hclge_destroy_cmd_queue(&hdev->hw);
7160err_pci_uninit:
6a814413 7161 pcim_iounmap(pdev, hdev->hw.io_base);
ffd5656e 7162 pci_clear_master(pdev);
46a3df9f 7163 pci_release_regions(pdev);
ffd5656e 7164 pci_disable_device(pdev);
ffd5656e 7165out:
46a3df9f
S		 7166 return ret;
7167}
7168
c6dc5213 7169static void hclge_stats_clear(struct hclge_dev *hdev)
7170{
7171 memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats));
7172}
7173
4ed340ab
L		 7174static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
7175{
7176 struct hclge_dev *hdev = ae_dev->priv;
7177 struct pci_dev *pdev = ae_dev->pdev;
7178 int ret;
7179
7180 set_bit(HCLGE_STATE_DOWN, &hdev->state);
7181
c6dc5213 7182 hclge_stats_clear(hdev);
dc8131d8 7183 memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table));
c6dc5213 7184
4ed340ab
L		 7185 ret = hclge_cmd_init(hdev);
7186 if (ret) {
7187 dev_err(&pdev->dev, "Cmd queue init failed\n");
7188 return ret;
7189 }
7190
7191 ret = hclge_get_cap(hdev);
7192 if (ret) {
7193 dev_err(&pdev->dev, "get hw capability error, ret = %d.\n",
7194 ret);
7195 return ret;
7196 }
7197
7198 ret = hclge_configure(hdev);
7199 if (ret) {
7200 dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret);
7201 return ret;
7202 }
7203
7204 ret = hclge_map_tqp(hdev);
7205 if (ret) {
7206 dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret);
7207 return ret;
7208 }
7209
39932473
JS		 7210 hclge_reset_umv_space(hdev);
7211
4ed340ab
L		 7212 ret = hclge_mac_init(hdev);
7213 if (ret) {
7214 dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret);
7215 return ret;
7216 }
7217
4ed340ab
L		 7218 ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX);
7219 if (ret) {
7220 dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret);
7221 return ret;
7222 }
7223
7224 ret = hclge_init_vlan_config(hdev);
7225 if (ret) {
7226 dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret);
7227 return ret;
7228 }
7229
f31c1ba6 7230 ret = hclge_tm_init_hw(hdev);
4ed340ab 7231 if (ret) {
f31c1ba6 7232 dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret);
4ed340ab
L		 7233 return ret;
7234 }
7235
7236 ret = hclge_rss_init_hw(hdev);
7237 if (ret) {
7238 dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret);
7239 return ret;
7240 }
7241
d695964d
JS		 7242 ret = hclge_init_fd_config(hdev);
7243 if (ret) {
7244 dev_err(&pdev->dev,
7245 "fd table init fail, ret=%d\n", ret);
7246 return ret;
7247 }
7248
01865a50
SJ		 7249 /* Re-enable the TM hw error interrupts because
7250 * they get disabled on core/global reset.
7251 */
7252 if (hclge_enable_tm_hw_error(hdev, true))
7253 dev_err(&pdev->dev, "failed to enable TM hw error interrupts\n");
7254
4ed340ab
L		 7255 dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
7256 HCLGE_DRIVER_NAME);
7257
7258 return 0;
7259}
7260
46a3df9f
S		 7261static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev)
7262{
7263 struct hclge_dev *hdev = ae_dev->priv;
7264 struct hclge_mac *mac = &hdev->hw.mac;
7265
48569cda 7266 hclge_state_uninit(hdev);
46a3df9f
S		 7267
7268 if (mac->phydev)
7269 mdiobus_unregister(mac->mdio_bus);
7270
39932473
JS		 7271 hclge_uninit_umv_space(hdev);
7272
466b0c00
L		 7273 /* Disable MISC vector(vector0) */
7274 hclge_enable_vector(&hdev->misc_vector, false);
8e52a602
XW		 7275 synchronize_irq(hdev->misc_vector.vector_irq);
7276
99714195 7277 hclge_hw_error_set_state(hdev, false);
46a3df9f 7278 hclge_destroy_cmd_queue(&hdev->hw);
ca1d7669 7279 hclge_misc_irq_uninit(hdev);
46a3df9f
S		 7280 hclge_pci_uninit(hdev);
7281 ae_dev->priv = NULL;
7282}
7283
482d2e9c
PL		 7284static u32 hclge_get_max_channels(struct hnae3_handle *handle)
7285{
7286 struct hnae3_knic_private_info *kinfo = &handle->kinfo;
7287 struct hclge_vport *vport = hclge_get_vport(handle);
7288 struct hclge_dev *hdev = vport->back;
7289
7290 return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps);
7291}
7292
7293static void hclge_get_channels(struct hnae3_handle *handle,
7294 struct ethtool_channels *ch)
7295{
7296 struct hclge_vport *vport = hclge_get_vport(handle);
7297
7298 ch->max_combined = hclge_get_max_channels(handle);
7299 ch->other_count = 1;
7300 ch->max_other = 1;
7301 ch->combined_count = vport->alloc_tqps;
7302}
7303
09f2af64 7304static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle,
0d43bf45 7305 u16 *alloc_tqps, u16 *max_rss_size)
09f2af64
PL		 7306{
7307 struct hclge_vport *vport = hclge_get_vport(handle);
7308 struct hclge_dev *hdev = vport->back;
09f2af64 7309
0d43bf45 7310 *alloc_tqps = vport->alloc_tqps;
09f2af64
PL		 7311 *max_rss_size = hdev->rss_size_max;
7312}
7313
7314static void hclge_release_tqp(struct hclge_vport *vport)
7315{
7316 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
7317 struct hclge_dev *hdev = vport->back;
7318 int i;
7319
7320 for (i = 0; i < kinfo->num_tqps; i++) {
7321 struct hclge_tqp *tqp =
7322 container_of(kinfo->tqp[i], struct hclge_tqp, q);
7323
7324 tqp->q.handle = NULL;
7325 tqp->q.tqp_index = 0;
7326 tqp->alloced = false;
7327 }
7328
7329 devm_kfree(&hdev->pdev->dev, kinfo->tqp);
7330 kinfo->tqp = NULL;
7331}
7332
7333static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num)
7334{
7335 struct hclge_vport *vport = hclge_get_vport(handle);
7336 struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo;
7337 struct hclge_dev *hdev = vport->back;
7338 int cur_rss_size = kinfo->rss_size;
7339 int cur_tqps = kinfo->num_tqps;
7340 u16 tc_offset[HCLGE_MAX_TC_NUM];
7341 u16 tc_valid[HCLGE_MAX_TC_NUM];
7342 u16 tc_size[HCLGE_MAX_TC_NUM];
7343 u16 roundup_size;
7344 u32 *rss_indir;
7345 int ret, i;
7346
fdace1bc 7347 /* Free old tqps, and reallocate with new tqp number when nic setup */
09f2af64
PL		 7348 hclge_release_tqp(vport);
7349
128b900d 7350 ret = hclge_knic_setup(vport, new_tqps_num, kinfo->num_desc);
09f2af64
PL		 7351 if (ret) {
7352 dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret);
7353 return ret;
7354 }
7355
7356 ret = hclge_map_tqp_to_vport(hdev, vport);
7357 if (ret) {
7358 dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret);
7359 return ret;
7360 }
7361
7362 ret = hclge_tm_schd_init(hdev);
7363 if (ret) {
7364 dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret);
7365 return ret;
7366 }
7367
7368 roundup_size = roundup_pow_of_two(kinfo->rss_size);
7369 roundup_size = ilog2(roundup_size);
7370 /* Set the RSS TC mode according to the new RSS size */
7371 for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
7372 tc_valid[i] = 0;
7373
7374 if (!(hdev->hw_tc_map & BIT(i)))
7375 continue;
7376
7377 tc_valid[i] = 1;
7378 tc_size[i] = roundup_size;
7379 tc_offset[i] = kinfo->rss_size * i;
7380 }
7381 ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
7382 if (ret)
7383 return ret;
7384
7385 /* Reinitializes the rss indirect table according to the new RSS size */
7386 rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
7387 if (!rss_indir)
7388 return -ENOMEM;
7389
7390 for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
7391 rss_indir[i] = i % kinfo->rss_size;
7392
7393 ret = hclge_set_rss(handle, rss_indir, NULL, 0);
7394 if (ret)
7395 dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n",
7396 ret);
7397
7398 kfree(rss_indir);
7399
7400 if (!ret)
7401 dev_info(&hdev->pdev->dev,
7402 "Channels changed, rss_size from %d to %d, tqps from %d to %d",
7403 cur_rss_size, kinfo->rss_size,
7404 cur_tqps, kinfo->rss_size * kinfo->num_tc);
7405
7406 return ret;
7407}
7408
77b34110
FL		 7409static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit,
7410 u32 *regs_num_64_bit)
7411{
7412 struct hclge_desc desc;
7413 u32 total_num;
7414 int ret;
7415
7416 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true);
7417 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7418 if (ret) {
7419 dev_err(&hdev->pdev->dev,
7420 "Query register number cmd failed, ret = %d.\n", ret);
7421 return ret;
7422 }
7423
7424 *regs_num_32_bit = le32_to_cpu(desc.data[0]);
7425 *regs_num_64_bit = le32_to_cpu(desc.data[1]);
7426
7427 total_num = *regs_num_32_bit + *regs_num_64_bit;
7428 if (!total_num)
7429 return -EINVAL;
7430
7431 return 0;
7432}
7433
7434static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7435 void *data)
7436{
7437#define HCLGE_32_BIT_REG_RTN_DATANUM 8
7438
7439 struct hclge_desc *desc;
7440 u32 *reg_val = data;
7441 __le32 *desc_data;
7442 int cmd_num;
7443 int i, k, n;
7444 int ret;
7445
7446 if (regs_num == 0)
7447 return 0;
7448
7449 cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM);
7450 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7451 if (!desc)
7452 return -ENOMEM;
7453
7454 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true);
7455 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7456 if (ret) {
7457 dev_err(&hdev->pdev->dev,
7458 "Query 32 bit register cmd failed, ret = %d.\n", ret);
7459 kfree(desc);
7460 return ret;
7461 }
7462
7463 for (i = 0; i < cmd_num; i++) {
7464 if (i == 0) {
7465 desc_data = (__le32 *)(&desc[i].data[0]);
7466 n = HCLGE_32_BIT_REG_RTN_DATANUM - 2;
7467 } else {
7468 desc_data = (__le32 *)(&desc[i]);
7469 n = HCLGE_32_BIT_REG_RTN_DATANUM;
7470 }
7471 for (k = 0; k < n; k++) {
7472 *reg_val++ = le32_to_cpu(*desc_data++);
7473
7474 regs_num--;
7475 if (!regs_num)
7476 break;
7477 }
7478 }
7479
7480 kfree(desc);
7481 return 0;
7482}
7483
7484static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num,
7485 void *data)
7486{
7487#define HCLGE_64_BIT_REG_RTN_DATANUM 4
7488
7489 struct hclge_desc *desc;
7490 u64 *reg_val = data;
7491 __le64 *desc_data;
7492 int cmd_num;
7493 int i, k, n;
7494 int ret;
7495
7496 if (regs_num == 0)
7497 return 0;
7498
7499 cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM);
7500 desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL);
7501 if (!desc)
7502 return -ENOMEM;
7503
7504 hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true);
7505 ret = hclge_cmd_send(&hdev->hw, desc, cmd_num);
7506 if (ret) {
7507 dev_err(&hdev->pdev->dev,
7508 "Query 64 bit register cmd failed, ret = %d.\n", ret);
7509 kfree(desc);
7510 return ret;
7511 }
7512
7513 for (i = 0; i < cmd_num; i++) {
7514 if (i == 0) {
7515 desc_data = (__le64 *)(&desc[i].data[0]);
7516 n = HCLGE_64_BIT_REG_RTN_DATANUM - 1;
7517 } else {
7518 desc_data = (__le64 *)(&desc[i]);
7519 n = HCLGE_64_BIT_REG_RTN_DATANUM;
7520 }
7521 for (k = 0; k < n; k++) {
7522 *reg_val++ = le64_to_cpu(*desc_data++);
7523
7524 regs_num--;
7525 if (!regs_num)
7526 break;
7527 }
7528 }
7529
7530 kfree(desc);
7531 return 0;
7532}
7533
7534static int hclge_get_regs_len(struct hnae3_handle *handle)
7535{
7536 struct hclge_vport *vport = hclge_get_vport(handle);
7537 struct hclge_dev *hdev = vport->back;
7538 u32 regs_num_32_bit, regs_num_64_bit;
7539 int ret;
7540
7541 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7542 if (ret) {
7543 dev_err(&hdev->pdev->dev,
7544 "Get register number failed, ret = %d.\n", ret);
7545 return -EOPNOTSUPP;
7546 }
7547
7548 return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64);
7549}
7550
7551static void hclge_get_regs(struct hnae3_handle *handle, u32 *version,
7552 void *data)
7553{
7554 struct hclge_vport *vport = hclge_get_vport(handle);
7555 struct hclge_dev *hdev = vport->back;
7556 u32 regs_num_32_bit, regs_num_64_bit;
7557 int ret;
7558
7559 *version = hdev->fw_version;
7560
7561 ret = hclge_get_regs_num(hdev, &regs_num_32_bit, &regs_num_64_bit);
7562 if (ret) {
7563 dev_err(&hdev->pdev->dev,
7564 "Get register number failed, ret = %d.\n", ret);
7565 return;
7566 }
7567
7568 ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data);
7569 if (ret) {
7570 dev_err(&hdev->pdev->dev,
7571 "Get 32 bit register failed, ret = %d.\n", ret);
7572 return;
7573 }
7574
7575 data = (u32 *)data + regs_num_32_bit;
7576 ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit,
7577 data);
7578 if (ret)
7579 dev_err(&hdev->pdev->dev,
7580 "Get 64 bit register failed, ret = %d.\n", ret);
7581}
7582
f6f75abc 7583static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status)
07f8e940
JS		 7584{
7585 struct hclge_set_led_state_cmd *req;
7586 struct hclge_desc desc;
7587 int ret;
7588
7589 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false);
7590
7591 req = (struct hclge_set_led_state_cmd *)desc.data;
e4e87715
PL		 7592 hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M,
7593 HCLGE_LED_LOCATE_STATE_S, locate_led_status);
07f8e940
JS		 7594
7595 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
7596 if (ret)
7597 dev_err(&hdev->pdev->dev,
7598 "Send set led state cmd error, ret =%d\n", ret);
7599
7600 return ret;
7601}
7602
7603enum hclge_led_status {
7604 HCLGE_LED_OFF,
7605 HCLGE_LED_ON,
7606 HCLGE_LED_NO_CHANGE = 0xFF,
7607};
7608
7609static int hclge_set_led_id(struct hnae3_handle *handle,
7610 enum ethtool_phys_id_state status)
7611{
07f8e940
JS		 7612 struct hclge_vport *vport = hclge_get_vport(handle);
7613 struct hclge_dev *hdev = vport->back;
07f8e940
JS		 7614
7615 switch (status) {
7616 case ETHTOOL_ID_ACTIVE:
f6f75abc 7617 return hclge_set_led_status(hdev, HCLGE_LED_ON);
07f8e940 7618 case ETHTOOL_ID_INACTIVE:
f6f75abc 7619 return hclge_set_led_status(hdev, HCLGE_LED_OFF);
07f8e940 7620 default:
f6f75abc 7621 return -EINVAL;
07f8e940 7622 }
07f8e940
JS		 7623}
7624
0979aa0b
FL		 7625static void hclge_get_link_mode(struct hnae3_handle *handle,
7626 unsigned long *supported,
7627 unsigned long *advertising)
7628{
7629 unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS);
7630 struct hclge_vport *vport = hclge_get_vport(handle);
7631 struct hclge_dev *hdev = vport->back;
7632 unsigned int idx = 0;
7633
7634 for (; idx < size; idx++) {
7635 supported[idx] = hdev->hw.mac.supported[idx];
7636 advertising[idx] = hdev->hw.mac.advertising[idx];
7637 }
7638}
7639
46a3df9f
S		 7640static const struct hnae3_ae_ops hclge_ops = {
7641 .init_ae_dev = hclge_init_ae_dev,
7642 .uninit_ae_dev = hclge_uninit_ae_dev,
6b9a97ee
HT		 7643 .flr_prepare = hclge_flr_prepare,
7644 .flr_done = hclge_flr_done,
46a3df9f
S		 7645 .init_client_instance = hclge_init_client_instance,
7646 .uninit_client_instance = hclge_uninit_client_instance,
84e095d6
SM		 7647 .map_ring_to_vector = hclge_map_ring_to_vector,
7648 .unmap_ring_from_vector = hclge_unmap_ring_frm_vector,
46a3df9f 7649 .get_vector = hclge_get_vector,
0d3e6631 7650 .put_vector = hclge_put_vector,
46a3df9f 7651 .set_promisc_mode = hclge_set_promisc_mode,
c39c4d98 7652 .set_loopback = hclge_set_loopback,
46a3df9f
S		 7653 .start = hclge_ae_start,
7654 .stop = hclge_ae_stop,
7655 .get_status = hclge_get_status,
7656 .get_ksettings_an_result = hclge_get_ksettings_an_result,
7657 .update_speed_duplex_h = hclge_update_speed_duplex_h,
7658 .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h,
7659 .get_media_type = hclge_get_media_type,
7660 .get_rss_key_size = hclge_get_rss_key_size,
7661 .get_rss_indir_size = hclge_get_rss_indir_size,
7662 .get_rss = hclge_get_rss,
7663 .set_rss = hclge_set_rss,
f7db940a 7664 .set_rss_tuple = hclge_set_rss_tuple,
07d29954 7665 .get_rss_tuple = hclge_get_rss_tuple,
46a3df9f
S		 7666 .get_tc_size = hclge_get_tc_size,
7667 .get_mac_addr = hclge_get_mac_addr,
7668 .set_mac_addr = hclge_set_mac_addr,
26483246 7669 .do_ioctl = hclge_do_ioctl,
46a3df9f
S		 7670 .add_uc_addr = hclge_add_uc_addr,
7671 .rm_uc_addr = hclge_rm_uc_addr,
7672 .add_mc_addr = hclge_add_mc_addr,
7673 .rm_mc_addr = hclge_rm_mc_addr,
7674 .set_autoneg = hclge_set_autoneg,
7675 .get_autoneg = hclge_get_autoneg,
7676 .get_pauseparam = hclge_get_pauseparam,
61387774 7677 .set_pauseparam = hclge_set_pauseparam,
46a3df9f
S		 7678 .set_mtu = hclge_set_mtu,
7679 .reset_queue = hclge_reset_tqp,
7680 .get_stats = hclge_get_stats,
7681 .update_stats = hclge_update_stats,
7682 .get_strings = hclge_get_strings,
7683 .get_sset_count = hclge_get_sset_count,
7684 .get_fw_version = hclge_get_fw_version,
7685 .get_mdix_mode = hclge_get_mdix_mode,
391b5e93 7686 .enable_vlan_filter = hclge_enable_vlan_filter,
dc8131d8 7687 .set_vlan_filter = hclge_set_vlan_filter,
46a3df9f 7688 .set_vf_vlan_filter = hclge_set_vf_vlan_filter,
052ece6d 7689 .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag,
4ed340ab 7690 .reset_event = hclge_reset_event,
720bd583 7691 .set_default_reset_request = hclge_set_def_reset_request,
09f2af64
PL		 7692 .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info,
7693 .set_channels = hclge_set_channels,
482d2e9c 7694 .get_channels = hclge_get_channels,
77b34110
FL		 7695 .get_regs_len = hclge_get_regs_len,
7696 .get_regs = hclge_get_regs,
07f8e940 7697 .set_led_id = hclge_set_led_id,
0979aa0b 7698 .get_link_mode = hclge_get_link_mode,
dd74f815
JS		 7699 .add_fd_entry = hclge_add_fd_entry,
7700 .del_fd_entry = hclge_del_fd_entry,
6871af29 7701 .del_all_fd_entries = hclge_del_all_fd_entries,
05c2314f
JS		 7702 .get_fd_rule_cnt = hclge_get_fd_rule_cnt,
7703 .get_fd_rule_info = hclge_get_fd_rule_info,
7704 .get_fd_all_rules = hclge_get_all_rules,
6871af29 7705 .restore_fd_rules = hclge_restore_fd_entries,
c17852a8 7706 .enable_fd = hclge_enable_fd,
5a9f0eac 7707 .process_hw_error = hclge_process_ras_hw_error,
4d60291b
HT		 7708 .get_hw_reset_stat = hclge_get_hw_reset_stat,
7709 .ae_dev_resetting = hclge_ae_dev_resetting,
7710 .ae_dev_reset_cnt = hclge_ae_dev_reset_cnt,
46a3df9f
S		 7711};
7712
7713static struct hnae3_ae_algo ae_algo = {
7714 .ops = &hclge_ops,
46a3df9f
S		 7715 .pdev_id_table = ae_algo_pci_tbl,
7716};
7717
7718static int hclge_init(void)
7719{
7720 pr_info("%s is initializing\n", HCLGE_NAME);
7721
854cf33a
FL		 7722 hnae3_register_ae_algo(&ae_algo);
7723
7724 return 0;
46a3df9f
S		 7725}
7726
7727static void hclge_exit(void)
7728{
7729 hnae3_unregister_ae_algo(&ae_algo);
7730}
7731module_init(hclge_init);
7732module_exit(hclge_exit);
7733
7734MODULE_LICENSE("GPL");
7735MODULE_AUTHOR("Huawei Tech. Co., Ltd.");
7736MODULE_DESCRIPTION("HCLGE Driver");
7737MODULE_VERSION(HCLGE_MOD_VERSION);
Linux 6.x block layer and io_uring tree(s)