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46a3df9f S |
1 | /* |
2 | * Copyright (c) 2016-2017 Hisilicon Limited. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | */ | |
9 | ||
10 | #include <linux/acpi.h> | |
11 | #include <linux/device.h> | |
12 | #include <linux/etherdevice.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/kernel.h> | |
16 | #include <linux/module.h> | |
17 | #include <linux/netdevice.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/platform_device.h> | |
2866ccb2 | 20 | #include <linux/if_vlan.h> |
f2f432f2 | 21 | #include <net/rtnetlink.h> |
46a3df9f | 22 | #include "hclge_cmd.h" |
cacde272 | 23 | #include "hclge_dcb.h" |
46a3df9f | 24 | #include "hclge_main.h" |
dde1a86e | 25 | #include "hclge_mbx.h" |
46a3df9f S |
26 | #include "hclge_mdio.h" |
27 | #include "hclge_tm.h" | |
28 | #include "hnae3.h" | |
29 | ||
30 | #define HCLGE_NAME "hclge" | |
31 | #define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) | |
32 | #define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f)) | |
33 | #define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f)) | |
34 | #define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f)) | |
35 | ||
46a3df9f S |
36 | static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, |
37 | enum hclge_mta_dmac_sel_type mta_mac_sel, | |
38 | bool enable); | |
f9fd82a9 | 39 | static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu); |
46a3df9f | 40 | static int hclge_init_vlan_config(struct hclge_dev *hdev); |
4ed340ab | 41 | static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev); |
46a3df9f S |
42 | |
43 | static struct hnae3_ae_algo ae_algo; | |
44 | ||
45 | static const struct pci_device_id ae_algo_pci_tbl[] = { | |
46 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0}, | |
47 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0}, | |
48 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0}, | |
49 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0}, | |
50 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0}, | |
51 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0}, | |
52 | {PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0}, | |
e92a0843 | 53 | /* required last entry */ |
46a3df9f S |
54 | {0, } |
55 | }; | |
56 | ||
2f550a46 YL |
57 | MODULE_DEVICE_TABLE(pci, ae_algo_pci_tbl); |
58 | ||
46a3df9f S |
59 | static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = { |
60 | "Mac Loopback test", | |
61 | "Serdes Loopback test", | |
62 | "Phy Loopback test" | |
63 | }; | |
64 | ||
65 | static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = { | |
66 | {"igu_rx_oversize_pkt", | |
67 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)}, | |
68 | {"igu_rx_undersize_pkt", | |
69 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)}, | |
70 | {"igu_rx_out_all_pkt", | |
71 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)}, | |
72 | {"igu_rx_uni_pkt", | |
73 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)}, | |
74 | {"igu_rx_multi_pkt", | |
75 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)}, | |
76 | {"igu_rx_broad_pkt", | |
77 | HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)}, | |
78 | {"egu_tx_out_all_pkt", | |
79 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)}, | |
80 | {"egu_tx_uni_pkt", | |
81 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)}, | |
82 | {"egu_tx_multi_pkt", | |
83 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)}, | |
84 | {"egu_tx_broad_pkt", | |
85 | HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)}, | |
86 | {"ssu_ppp_mac_key_num", | |
87 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)}, | |
88 | {"ssu_ppp_host_key_num", | |
89 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)}, | |
90 | {"ppp_ssu_mac_rlt_num", | |
91 | HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)}, | |
92 | {"ppp_ssu_host_rlt_num", | |
93 | HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)}, | |
94 | {"ssu_tx_in_num", | |
95 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)}, | |
96 | {"ssu_tx_out_num", | |
97 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)}, | |
98 | {"ssu_rx_in_num", | |
99 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)}, | |
100 | {"ssu_rx_out_num", | |
101 | HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)} | |
102 | }; | |
103 | ||
104 | static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = { | |
105 | {"igu_rx_err_pkt", | |
106 | HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)}, | |
107 | {"igu_rx_no_eof_pkt", | |
108 | HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)}, | |
109 | {"igu_rx_no_sof_pkt", | |
110 | HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)}, | |
111 | {"egu_tx_1588_pkt", | |
112 | HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)}, | |
113 | {"ssu_full_drop_num", | |
114 | HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)}, | |
115 | {"ssu_part_drop_num", | |
116 | HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)}, | |
117 | {"ppp_key_drop_num", | |
118 | HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)}, | |
119 | {"ppp_rlt_drop_num", | |
120 | HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)}, | |
121 | {"ssu_key_drop_num", | |
122 | HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)}, | |
123 | {"pkt_curr_buf_cnt", | |
124 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)}, | |
125 | {"qcn_fb_rcv_cnt", | |
126 | HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)}, | |
127 | {"qcn_fb_drop_cnt", | |
128 | HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)}, | |
129 | {"qcn_fb_invaild_cnt", | |
130 | HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)}, | |
131 | {"rx_packet_tc0_in_cnt", | |
132 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)}, | |
133 | {"rx_packet_tc1_in_cnt", | |
134 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)}, | |
135 | {"rx_packet_tc2_in_cnt", | |
136 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)}, | |
137 | {"rx_packet_tc3_in_cnt", | |
138 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)}, | |
139 | {"rx_packet_tc4_in_cnt", | |
140 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)}, | |
141 | {"rx_packet_tc5_in_cnt", | |
142 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)}, | |
143 | {"rx_packet_tc6_in_cnt", | |
144 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)}, | |
145 | {"rx_packet_tc7_in_cnt", | |
146 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)}, | |
147 | {"rx_packet_tc0_out_cnt", | |
148 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)}, | |
149 | {"rx_packet_tc1_out_cnt", | |
150 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)}, | |
151 | {"rx_packet_tc2_out_cnt", | |
152 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)}, | |
153 | {"rx_packet_tc3_out_cnt", | |
154 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)}, | |
155 | {"rx_packet_tc4_out_cnt", | |
156 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)}, | |
157 | {"rx_packet_tc5_out_cnt", | |
158 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)}, | |
159 | {"rx_packet_tc6_out_cnt", | |
160 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)}, | |
161 | {"rx_packet_tc7_out_cnt", | |
162 | HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)}, | |
163 | {"tx_packet_tc0_in_cnt", | |
164 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)}, | |
165 | {"tx_packet_tc1_in_cnt", | |
166 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)}, | |
167 | {"tx_packet_tc2_in_cnt", | |
168 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)}, | |
169 | {"tx_packet_tc3_in_cnt", | |
170 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)}, | |
171 | {"tx_packet_tc4_in_cnt", | |
172 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)}, | |
173 | {"tx_packet_tc5_in_cnt", | |
174 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)}, | |
175 | {"tx_packet_tc6_in_cnt", | |
176 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)}, | |
177 | {"tx_packet_tc7_in_cnt", | |
178 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)}, | |
179 | {"tx_packet_tc0_out_cnt", | |
180 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)}, | |
181 | {"tx_packet_tc1_out_cnt", | |
182 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)}, | |
183 | {"tx_packet_tc2_out_cnt", | |
184 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)}, | |
185 | {"tx_packet_tc3_out_cnt", | |
186 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)}, | |
187 | {"tx_packet_tc4_out_cnt", | |
188 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)}, | |
189 | {"tx_packet_tc5_out_cnt", | |
190 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)}, | |
191 | {"tx_packet_tc6_out_cnt", | |
192 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)}, | |
193 | {"tx_packet_tc7_out_cnt", | |
194 | HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)}, | |
195 | {"pkt_curr_buf_tc0_cnt", | |
196 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)}, | |
197 | {"pkt_curr_buf_tc1_cnt", | |
198 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)}, | |
199 | {"pkt_curr_buf_tc2_cnt", | |
200 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)}, | |
201 | {"pkt_curr_buf_tc3_cnt", | |
202 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)}, | |
203 | {"pkt_curr_buf_tc4_cnt", | |
204 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)}, | |
205 | {"pkt_curr_buf_tc5_cnt", | |
206 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)}, | |
207 | {"pkt_curr_buf_tc6_cnt", | |
208 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)}, | |
209 | {"pkt_curr_buf_tc7_cnt", | |
210 | HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)}, | |
211 | {"mb_uncopy_num", | |
212 | HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)}, | |
213 | {"lo_pri_unicast_rlt_drop_num", | |
214 | HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)}, | |
215 | {"hi_pri_multicast_rlt_drop_num", | |
216 | HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)}, | |
217 | {"lo_pri_multicast_rlt_drop_num", | |
218 | HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)}, | |
219 | {"rx_oq_drop_pkt_cnt", | |
220 | HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)}, | |
221 | {"tx_oq_drop_pkt_cnt", | |
222 | HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)}, | |
223 | {"nic_l2_err_drop_pkt_cnt", | |
224 | HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)}, | |
225 | {"roc_l2_err_drop_pkt_cnt", | |
226 | HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)} | |
227 | }; | |
228 | ||
229 | static const struct hclge_comm_stats_str g_mac_stats_string[] = { | |
230 | {"mac_tx_mac_pause_num", | |
231 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)}, | |
232 | {"mac_rx_mac_pause_num", | |
233 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)}, | |
234 | {"mac_tx_pfc_pri0_pkt_num", | |
235 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)}, | |
236 | {"mac_tx_pfc_pri1_pkt_num", | |
237 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)}, | |
238 | {"mac_tx_pfc_pri2_pkt_num", | |
239 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)}, | |
240 | {"mac_tx_pfc_pri3_pkt_num", | |
241 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)}, | |
242 | {"mac_tx_pfc_pri4_pkt_num", | |
243 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)}, | |
244 | {"mac_tx_pfc_pri5_pkt_num", | |
245 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)}, | |
246 | {"mac_tx_pfc_pri6_pkt_num", | |
247 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)}, | |
248 | {"mac_tx_pfc_pri7_pkt_num", | |
249 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)}, | |
250 | {"mac_rx_pfc_pri0_pkt_num", | |
251 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)}, | |
252 | {"mac_rx_pfc_pri1_pkt_num", | |
253 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)}, | |
254 | {"mac_rx_pfc_pri2_pkt_num", | |
255 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)}, | |
256 | {"mac_rx_pfc_pri3_pkt_num", | |
257 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)}, | |
258 | {"mac_rx_pfc_pri4_pkt_num", | |
259 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)}, | |
260 | {"mac_rx_pfc_pri5_pkt_num", | |
261 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)}, | |
262 | {"mac_rx_pfc_pri6_pkt_num", | |
263 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)}, | |
264 | {"mac_rx_pfc_pri7_pkt_num", | |
265 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)}, | |
266 | {"mac_tx_total_pkt_num", | |
267 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)}, | |
268 | {"mac_tx_total_oct_num", | |
269 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)}, | |
270 | {"mac_tx_good_pkt_num", | |
271 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)}, | |
272 | {"mac_tx_bad_pkt_num", | |
273 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)}, | |
274 | {"mac_tx_good_oct_num", | |
275 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)}, | |
276 | {"mac_tx_bad_oct_num", | |
277 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)}, | |
278 | {"mac_tx_uni_pkt_num", | |
279 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)}, | |
280 | {"mac_tx_multi_pkt_num", | |
281 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)}, | |
282 | {"mac_tx_broad_pkt_num", | |
283 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)}, | |
284 | {"mac_tx_undersize_pkt_num", | |
285 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)}, | |
200a88c6 JS |
286 | {"mac_tx_oversize_pkt_num", |
287 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_oversize_pkt_num)}, | |
46a3df9f S |
288 | {"mac_tx_64_oct_pkt_num", |
289 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)}, | |
290 | {"mac_tx_65_127_oct_pkt_num", | |
291 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)}, | |
292 | {"mac_tx_128_255_oct_pkt_num", | |
293 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)}, | |
294 | {"mac_tx_256_511_oct_pkt_num", | |
295 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)}, | |
296 | {"mac_tx_512_1023_oct_pkt_num", | |
297 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)}, | |
298 | {"mac_tx_1024_1518_oct_pkt_num", | |
299 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)}, | |
91f384f6 JS |
300 | {"mac_tx_1519_2047_oct_pkt_num", |
301 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_2047_oct_pkt_num)}, | |
302 | {"mac_tx_2048_4095_oct_pkt_num", | |
303 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_2048_4095_oct_pkt_num)}, | |
304 | {"mac_tx_4096_8191_oct_pkt_num", | |
305 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_4096_8191_oct_pkt_num)}, | |
91f384f6 JS |
306 | {"mac_tx_8192_9216_oct_pkt_num", |
307 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_8192_9216_oct_pkt_num)}, | |
308 | {"mac_tx_9217_12287_oct_pkt_num", | |
309 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_9217_12287_oct_pkt_num)}, | |
310 | {"mac_tx_12288_16383_oct_pkt_num", | |
311 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_12288_16383_oct_pkt_num)}, | |
312 | {"mac_tx_1519_max_good_pkt_num", | |
313 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_good_oct_pkt_num)}, | |
314 | {"mac_tx_1519_max_bad_pkt_num", | |
315 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_bad_oct_pkt_num)}, | |
46a3df9f S |
316 | {"mac_rx_total_pkt_num", |
317 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)}, | |
318 | {"mac_rx_total_oct_num", | |
319 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)}, | |
320 | {"mac_rx_good_pkt_num", | |
321 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)}, | |
322 | {"mac_rx_bad_pkt_num", | |
323 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)}, | |
324 | {"mac_rx_good_oct_num", | |
325 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)}, | |
326 | {"mac_rx_bad_oct_num", | |
327 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)}, | |
328 | {"mac_rx_uni_pkt_num", | |
329 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)}, | |
330 | {"mac_rx_multi_pkt_num", | |
331 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)}, | |
332 | {"mac_rx_broad_pkt_num", | |
333 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)}, | |
334 | {"mac_rx_undersize_pkt_num", | |
335 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)}, | |
200a88c6 JS |
336 | {"mac_rx_oversize_pkt_num", |
337 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_oversize_pkt_num)}, | |
46a3df9f S |
338 | {"mac_rx_64_oct_pkt_num", |
339 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)}, | |
340 | {"mac_rx_65_127_oct_pkt_num", | |
341 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)}, | |
342 | {"mac_rx_128_255_oct_pkt_num", | |
343 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)}, | |
344 | {"mac_rx_256_511_oct_pkt_num", | |
345 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)}, | |
346 | {"mac_rx_512_1023_oct_pkt_num", | |
347 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)}, | |
348 | {"mac_rx_1024_1518_oct_pkt_num", | |
349 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)}, | |
91f384f6 JS |
350 | {"mac_rx_1519_2047_oct_pkt_num", |
351 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_2047_oct_pkt_num)}, | |
352 | {"mac_rx_2048_4095_oct_pkt_num", | |
353 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_2048_4095_oct_pkt_num)}, | |
354 | {"mac_rx_4096_8191_oct_pkt_num", | |
355 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_4096_8191_oct_pkt_num)}, | |
91f384f6 JS |
356 | {"mac_rx_8192_9216_oct_pkt_num", |
357 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_8192_9216_oct_pkt_num)}, | |
358 | {"mac_rx_9217_12287_oct_pkt_num", | |
359 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_9217_12287_oct_pkt_num)}, | |
360 | {"mac_rx_12288_16383_oct_pkt_num", | |
361 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_12288_16383_oct_pkt_num)}, | |
362 | {"mac_rx_1519_max_good_pkt_num", | |
363 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_good_oct_pkt_num)}, | |
364 | {"mac_rx_1519_max_bad_pkt_num", | |
365 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_bad_oct_pkt_num)}, | |
46a3df9f | 366 | |
a6c51c26 JS |
367 | {"mac_tx_fragment_pkt_num", |
368 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_fragment_pkt_num)}, | |
369 | {"mac_tx_undermin_pkt_num", | |
370 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undermin_pkt_num)}, | |
371 | {"mac_tx_jabber_pkt_num", | |
372 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_jabber_pkt_num)}, | |
373 | {"mac_tx_err_all_pkt_num", | |
374 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_err_all_pkt_num)}, | |
375 | {"mac_tx_from_app_good_pkt_num", | |
376 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_good_pkt_num)}, | |
377 | {"mac_tx_from_app_bad_pkt_num", | |
378 | HCLGE_MAC_STATS_FIELD_OFF(mac_tx_from_app_bad_pkt_num)}, | |
379 | {"mac_rx_fragment_pkt_num", | |
380 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fragment_pkt_num)}, | |
381 | {"mac_rx_undermin_pkt_num", | |
382 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undermin_pkt_num)}, | |
383 | {"mac_rx_jabber_pkt_num", | |
384 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_jabber_pkt_num)}, | |
385 | {"mac_rx_fcs_err_pkt_num", | |
386 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_fcs_err_pkt_num)}, | |
387 | {"mac_rx_send_app_good_pkt_num", | |
388 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_good_pkt_num)}, | |
389 | {"mac_rx_send_app_bad_pkt_num", | |
390 | HCLGE_MAC_STATS_FIELD_OFF(mac_rx_send_app_bad_pkt_num)} | |
46a3df9f S |
391 | }; |
392 | ||
f5aac71c FL |
393 | static const struct hclge_mac_mgr_tbl_entry_cmd hclge_mgr_table[] = { |
394 | { | |
395 | .flags = HCLGE_MAC_MGR_MASK_VLAN_B, | |
396 | .ethter_type = cpu_to_le16(HCLGE_MAC_ETHERTYPE_LLDP), | |
397 | .mac_addr_hi32 = cpu_to_le32(htonl(0x0180C200)), | |
398 | .mac_addr_lo16 = cpu_to_le16(htons(0x000E)), | |
399 | .i_port_bitmap = 0x1, | |
400 | }, | |
401 | }; | |
402 | ||
46a3df9f S |
403 | static int hclge_64_bit_update_stats(struct hclge_dev *hdev) |
404 | { | |
405 | #define HCLGE_64_BIT_CMD_NUM 5 | |
406 | #define HCLGE_64_BIT_RTN_DATANUM 4 | |
407 | u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats); | |
408 | struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM]; | |
a90bb9a5 | 409 | __le64 *desc_data; |
46a3df9f S |
410 | int i, k, n; |
411 | int ret; | |
412 | ||
413 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true); | |
414 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM); | |
415 | if (ret) { | |
416 | dev_err(&hdev->pdev->dev, | |
417 | "Get 64 bit pkt stats fail, status = %d.\n", ret); | |
418 | return ret; | |
419 | } | |
420 | ||
421 | for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) { | |
422 | if (unlikely(i == 0)) { | |
a90bb9a5 | 423 | desc_data = (__le64 *)(&desc[i].data[0]); |
46a3df9f S |
424 | n = HCLGE_64_BIT_RTN_DATANUM - 1; |
425 | } else { | |
a90bb9a5 | 426 | desc_data = (__le64 *)(&desc[i]); |
46a3df9f S |
427 | n = HCLGE_64_BIT_RTN_DATANUM; |
428 | } | |
429 | for (k = 0; k < n; k++) { | |
a90bb9a5 | 430 | *data++ += le64_to_cpu(*desc_data); |
46a3df9f S |
431 | desc_data++; |
432 | } | |
433 | } | |
434 | ||
435 | return 0; | |
436 | } | |
437 | ||
438 | static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats) | |
439 | { | |
440 | stats->pkt_curr_buf_cnt = 0; | |
441 | stats->pkt_curr_buf_tc0_cnt = 0; | |
442 | stats->pkt_curr_buf_tc1_cnt = 0; | |
443 | stats->pkt_curr_buf_tc2_cnt = 0; | |
444 | stats->pkt_curr_buf_tc3_cnt = 0; | |
445 | stats->pkt_curr_buf_tc4_cnt = 0; | |
446 | stats->pkt_curr_buf_tc5_cnt = 0; | |
447 | stats->pkt_curr_buf_tc6_cnt = 0; | |
448 | stats->pkt_curr_buf_tc7_cnt = 0; | |
449 | } | |
450 | ||
451 | static int hclge_32_bit_update_stats(struct hclge_dev *hdev) | |
452 | { | |
453 | #define HCLGE_32_BIT_CMD_NUM 8 | |
454 | #define HCLGE_32_BIT_RTN_DATANUM 8 | |
455 | ||
456 | struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM]; | |
457 | struct hclge_32_bit_stats *all_32_bit_stats; | |
a90bb9a5 | 458 | __le32 *desc_data; |
46a3df9f S |
459 | int i, k, n; |
460 | u64 *data; | |
461 | int ret; | |
462 | ||
463 | all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats; | |
464 | data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt); | |
465 | ||
466 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true); | |
467 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM); | |
468 | if (ret) { | |
469 | dev_err(&hdev->pdev->dev, | |
470 | "Get 32 bit pkt stats fail, status = %d.\n", ret); | |
471 | ||
472 | return ret; | |
473 | } | |
474 | ||
475 | hclge_reset_partial_32bit_counter(all_32_bit_stats); | |
476 | for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) { | |
477 | if (unlikely(i == 0)) { | |
a90bb9a5 YL |
478 | __le16 *desc_data_16bit; |
479 | ||
46a3df9f | 480 | all_32_bit_stats->igu_rx_err_pkt += |
a90bb9a5 YL |
481 | le32_to_cpu(desc[i].data[0]); |
482 | ||
483 | desc_data_16bit = (__le16 *)&desc[i].data[1]; | |
46a3df9f | 484 | all_32_bit_stats->igu_rx_no_eof_pkt += |
a90bb9a5 YL |
485 | le16_to_cpu(*desc_data_16bit); |
486 | ||
487 | desc_data_16bit++; | |
46a3df9f | 488 | all_32_bit_stats->igu_rx_no_sof_pkt += |
a90bb9a5 | 489 | le16_to_cpu(*desc_data_16bit); |
46a3df9f | 490 | |
a90bb9a5 | 491 | desc_data = &desc[i].data[2]; |
46a3df9f S |
492 | n = HCLGE_32_BIT_RTN_DATANUM - 4; |
493 | } else { | |
a90bb9a5 | 494 | desc_data = (__le32 *)&desc[i]; |
46a3df9f S |
495 | n = HCLGE_32_BIT_RTN_DATANUM; |
496 | } | |
497 | for (k = 0; k < n; k++) { | |
a90bb9a5 | 498 | *data++ += le32_to_cpu(*desc_data); |
46a3df9f S |
499 | desc_data++; |
500 | } | |
501 | } | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | static int hclge_mac_update_stats(struct hclge_dev *hdev) | |
507 | { | |
91f384f6 | 508 | #define HCLGE_MAC_CMD_NUM 21 |
46a3df9f S |
509 | #define HCLGE_RTN_DATA_NUM 4 |
510 | ||
511 | u64 *data = (u64 *)(&hdev->hw_stats.mac_stats); | |
512 | struct hclge_desc desc[HCLGE_MAC_CMD_NUM]; | |
a90bb9a5 | 513 | __le64 *desc_data; |
46a3df9f S |
514 | int i, k, n; |
515 | int ret; | |
516 | ||
517 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true); | |
518 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM); | |
519 | if (ret) { | |
520 | dev_err(&hdev->pdev->dev, | |
521 | "Get MAC pkt stats fail, status = %d.\n", ret); | |
522 | ||
523 | return ret; | |
524 | } | |
525 | ||
526 | for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) { | |
527 | if (unlikely(i == 0)) { | |
a90bb9a5 | 528 | desc_data = (__le64 *)(&desc[i].data[0]); |
46a3df9f S |
529 | n = HCLGE_RTN_DATA_NUM - 2; |
530 | } else { | |
a90bb9a5 | 531 | desc_data = (__le64 *)(&desc[i]); |
46a3df9f S |
532 | n = HCLGE_RTN_DATA_NUM; |
533 | } | |
534 | for (k = 0; k < n; k++) { | |
a90bb9a5 | 535 | *data++ += le64_to_cpu(*desc_data); |
46a3df9f S |
536 | desc_data++; |
537 | } | |
538 | } | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | static int hclge_tqps_update_stats(struct hnae3_handle *handle) | |
544 | { | |
545 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
546 | struct hclge_vport *vport = hclge_get_vport(handle); | |
547 | struct hclge_dev *hdev = vport->back; | |
548 | struct hnae3_queue *queue; | |
549 | struct hclge_desc desc[1]; | |
550 | struct hclge_tqp *tqp; | |
551 | int ret, i; | |
552 | ||
553 | for (i = 0; i < kinfo->num_tqps; i++) { | |
554 | queue = handle->kinfo.tqp[i]; | |
555 | tqp = container_of(queue, struct hclge_tqp, q); | |
556 | /* command : HCLGE_OPC_QUERY_IGU_STAT */ | |
557 | hclge_cmd_setup_basic_desc(&desc[0], | |
558 | HCLGE_OPC_QUERY_RX_STATUS, | |
559 | true); | |
560 | ||
a90bb9a5 | 561 | desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); |
46a3df9f S |
562 | ret = hclge_cmd_send(&hdev->hw, desc, 1); |
563 | if (ret) { | |
564 | dev_err(&hdev->pdev->dev, | |
565 | "Query tqp stat fail, status = %d,queue = %d\n", | |
566 | ret, i); | |
567 | return ret; | |
568 | } | |
569 | tqp->tqp_stats.rcb_rx_ring_pktnum_rcd += | |
cf72fa63 | 570 | le32_to_cpu(desc[0].data[1]); |
46a3df9f S |
571 | } |
572 | ||
573 | for (i = 0; i < kinfo->num_tqps; i++) { | |
574 | queue = handle->kinfo.tqp[i]; | |
575 | tqp = container_of(queue, struct hclge_tqp, q); | |
576 | /* command : HCLGE_OPC_QUERY_IGU_STAT */ | |
577 | hclge_cmd_setup_basic_desc(&desc[0], | |
578 | HCLGE_OPC_QUERY_TX_STATUS, | |
579 | true); | |
580 | ||
a90bb9a5 | 581 | desc[0].data[0] = cpu_to_le32((tqp->index & 0x1ff)); |
46a3df9f S |
582 | ret = hclge_cmd_send(&hdev->hw, desc, 1); |
583 | if (ret) { | |
584 | dev_err(&hdev->pdev->dev, | |
585 | "Query tqp stat fail, status = %d,queue = %d\n", | |
586 | ret, i); | |
587 | return ret; | |
588 | } | |
589 | tqp->tqp_stats.rcb_tx_ring_pktnum_rcd += | |
cf72fa63 | 590 | le32_to_cpu(desc[0].data[1]); |
46a3df9f S |
591 | } |
592 | ||
593 | return 0; | |
594 | } | |
595 | ||
596 | static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data) | |
597 | { | |
598 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
599 | struct hclge_tqp *tqp; | |
600 | u64 *buff = data; | |
601 | int i; | |
602 | ||
603 | for (i = 0; i < kinfo->num_tqps; i++) { | |
604 | tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); | |
a90bb9a5 | 605 | *buff++ = tqp->tqp_stats.rcb_tx_ring_pktnum_rcd; |
46a3df9f S |
606 | } |
607 | ||
608 | for (i = 0; i < kinfo->num_tqps; i++) { | |
609 | tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q); | |
a90bb9a5 | 610 | *buff++ = tqp->tqp_stats.rcb_rx_ring_pktnum_rcd; |
46a3df9f S |
611 | } |
612 | ||
613 | return buff; | |
614 | } | |
615 | ||
616 | static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset) | |
617 | { | |
618 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
619 | ||
620 | return kinfo->num_tqps * (2); | |
621 | } | |
622 | ||
623 | static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data) | |
624 | { | |
625 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
626 | u8 *buff = data; | |
627 | int i = 0; | |
628 | ||
629 | for (i = 0; i < kinfo->num_tqps; i++) { | |
630 | struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i], | |
631 | struct hclge_tqp, q); | |
a6c51c26 | 632 | snprintf(buff, ETH_GSTRING_LEN, "txq#%d_pktnum_rcd", |
46a3df9f S |
633 | tqp->index); |
634 | buff = buff + ETH_GSTRING_LEN; | |
635 | } | |
636 | ||
637 | for (i = 0; i < kinfo->num_tqps; i++) { | |
638 | struct hclge_tqp *tqp = container_of(kinfo->tqp[i], | |
639 | struct hclge_tqp, q); | |
a6c51c26 | 640 | snprintf(buff, ETH_GSTRING_LEN, "rxq#%d_pktnum_rcd", |
46a3df9f S |
641 | tqp->index); |
642 | buff = buff + ETH_GSTRING_LEN; | |
643 | } | |
644 | ||
645 | return buff; | |
646 | } | |
647 | ||
648 | static u64 *hclge_comm_get_stats(void *comm_stats, | |
649 | const struct hclge_comm_stats_str strs[], | |
650 | int size, u64 *data) | |
651 | { | |
652 | u64 *buf = data; | |
653 | u32 i; | |
654 | ||
655 | for (i = 0; i < size; i++) | |
656 | buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset); | |
657 | ||
658 | return buf + size; | |
659 | } | |
660 | ||
661 | static u8 *hclge_comm_get_strings(u32 stringset, | |
662 | const struct hclge_comm_stats_str strs[], | |
663 | int size, u8 *data) | |
664 | { | |
665 | char *buff = (char *)data; | |
666 | u32 i; | |
667 | ||
668 | if (stringset != ETH_SS_STATS) | |
669 | return buff; | |
670 | ||
671 | for (i = 0; i < size; i++) { | |
672 | snprintf(buff, ETH_GSTRING_LEN, | |
673 | strs[i].desc); | |
674 | buff = buff + ETH_GSTRING_LEN; | |
675 | } | |
676 | ||
677 | return (u8 *)buff; | |
678 | } | |
679 | ||
680 | static void hclge_update_netstat(struct hclge_hw_stats *hw_stats, | |
681 | struct net_device_stats *net_stats) | |
682 | { | |
683 | net_stats->tx_dropped = 0; | |
684 | net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num; | |
685 | net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num; | |
686 | net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num; | |
687 | ||
200a88c6 | 688 | net_stats->rx_errors = hw_stats->mac_stats.mac_rx_oversize_pkt_num; |
46a3df9f | 689 | net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num; |
46a3df9f S |
690 | net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt; |
691 | net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt; | |
a6c51c26 | 692 | net_stats->rx_errors += hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; |
46a3df9f S |
693 | |
694 | net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num; | |
695 | net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num; | |
696 | ||
a6c51c26 | 697 | net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rx_fcs_err_pkt_num; |
46a3df9f S |
698 | net_stats->rx_length_errors = |
699 | hw_stats->mac_stats.mac_rx_undersize_pkt_num; | |
700 | net_stats->rx_length_errors += | |
200a88c6 | 701 | hw_stats->mac_stats.mac_rx_oversize_pkt_num; |
46a3df9f | 702 | net_stats->rx_over_errors = |
200a88c6 | 703 | hw_stats->mac_stats.mac_rx_oversize_pkt_num; |
46a3df9f S |
704 | } |
705 | ||
706 | static void hclge_update_stats_for_all(struct hclge_dev *hdev) | |
707 | { | |
708 | struct hnae3_handle *handle; | |
709 | int status; | |
710 | ||
711 | handle = &hdev->vport[0].nic; | |
712 | if (handle->client) { | |
713 | status = hclge_tqps_update_stats(handle); | |
714 | if (status) { | |
715 | dev_err(&hdev->pdev->dev, | |
716 | "Update TQPS stats fail, status = %d.\n", | |
717 | status); | |
718 | } | |
719 | } | |
720 | ||
721 | status = hclge_mac_update_stats(hdev); | |
722 | if (status) | |
723 | dev_err(&hdev->pdev->dev, | |
724 | "Update MAC stats fail, status = %d.\n", status); | |
725 | ||
726 | status = hclge_32_bit_update_stats(hdev); | |
727 | if (status) | |
728 | dev_err(&hdev->pdev->dev, | |
729 | "Update 32 bit stats fail, status = %d.\n", | |
730 | status); | |
731 | ||
732 | hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats); | |
733 | } | |
734 | ||
735 | static void hclge_update_stats(struct hnae3_handle *handle, | |
736 | struct net_device_stats *net_stats) | |
737 | { | |
738 | struct hclge_vport *vport = hclge_get_vport(handle); | |
739 | struct hclge_dev *hdev = vport->back; | |
740 | struct hclge_hw_stats *hw_stats = &hdev->hw_stats; | |
741 | int status; | |
742 | ||
c5f65480 JS |
743 | if (test_and_set_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state)) |
744 | return; | |
745 | ||
46a3df9f S |
746 | status = hclge_mac_update_stats(hdev); |
747 | if (status) | |
748 | dev_err(&hdev->pdev->dev, | |
749 | "Update MAC stats fail, status = %d.\n", | |
750 | status); | |
751 | ||
752 | status = hclge_32_bit_update_stats(hdev); | |
753 | if (status) | |
754 | dev_err(&hdev->pdev->dev, | |
755 | "Update 32 bit stats fail, status = %d.\n", | |
756 | status); | |
757 | ||
758 | status = hclge_64_bit_update_stats(hdev); | |
759 | if (status) | |
760 | dev_err(&hdev->pdev->dev, | |
761 | "Update 64 bit stats fail, status = %d.\n", | |
762 | status); | |
763 | ||
764 | status = hclge_tqps_update_stats(handle); | |
765 | if (status) | |
766 | dev_err(&hdev->pdev->dev, | |
767 | "Update TQPS stats fail, status = %d.\n", | |
768 | status); | |
769 | ||
770 | hclge_update_netstat(hw_stats, net_stats); | |
c5f65480 JS |
771 | |
772 | clear_bit(HCLGE_STATE_STATISTICS_UPDATING, &hdev->state); | |
46a3df9f S |
773 | } |
774 | ||
775 | static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset) | |
776 | { | |
777 | #define HCLGE_LOOPBACK_TEST_FLAGS 0x7 | |
778 | ||
779 | struct hclge_vport *vport = hclge_get_vport(handle); | |
780 | struct hclge_dev *hdev = vport->back; | |
781 | int count = 0; | |
782 | ||
783 | /* Loopback test support rules: | |
784 | * mac: only GE mode support | |
785 | * serdes: all mac mode will support include GE/XGE/LGE/CGE | |
786 | * phy: only support when phy device exist on board | |
787 | */ | |
788 | if (stringset == ETH_SS_TEST) { | |
789 | /* clear loopback bit flags at first */ | |
790 | handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS)); | |
791 | if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M || | |
792 | hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M || | |
793 | hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) { | |
794 | count += 1; | |
795 | handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK; | |
796 | } else { | |
797 | count = -EOPNOTSUPP; | |
798 | } | |
799 | } else if (stringset == ETH_SS_STATS) { | |
800 | count = ARRAY_SIZE(g_mac_stats_string) + | |
801 | ARRAY_SIZE(g_all_32bit_stats_string) + | |
802 | ARRAY_SIZE(g_all_64bit_stats_string) + | |
803 | hclge_tqps_get_sset_count(handle, stringset); | |
804 | } | |
805 | ||
806 | return count; | |
807 | } | |
808 | ||
809 | static void hclge_get_strings(struct hnae3_handle *handle, | |
810 | u32 stringset, | |
811 | u8 *data) | |
812 | { | |
813 | u8 *p = (char *)data; | |
814 | int size; | |
815 | ||
816 | if (stringset == ETH_SS_STATS) { | |
817 | size = ARRAY_SIZE(g_mac_stats_string); | |
818 | p = hclge_comm_get_strings(stringset, | |
819 | g_mac_stats_string, | |
820 | size, | |
821 | p); | |
822 | size = ARRAY_SIZE(g_all_32bit_stats_string); | |
823 | p = hclge_comm_get_strings(stringset, | |
824 | g_all_32bit_stats_string, | |
825 | size, | |
826 | p); | |
827 | size = ARRAY_SIZE(g_all_64bit_stats_string); | |
828 | p = hclge_comm_get_strings(stringset, | |
829 | g_all_64bit_stats_string, | |
830 | size, | |
831 | p); | |
832 | p = hclge_tqps_get_strings(handle, p); | |
833 | } else if (stringset == ETH_SS_TEST) { | |
834 | if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) { | |
835 | memcpy(p, | |
836 | hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC], | |
837 | ETH_GSTRING_LEN); | |
838 | p += ETH_GSTRING_LEN; | |
839 | } | |
840 | if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) { | |
841 | memcpy(p, | |
842 | hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES], | |
843 | ETH_GSTRING_LEN); | |
844 | p += ETH_GSTRING_LEN; | |
845 | } | |
846 | if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) { | |
847 | memcpy(p, | |
848 | hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY], | |
849 | ETH_GSTRING_LEN); | |
850 | p += ETH_GSTRING_LEN; | |
851 | } | |
852 | } | |
853 | } | |
854 | ||
855 | static void hclge_get_stats(struct hnae3_handle *handle, u64 *data) | |
856 | { | |
857 | struct hclge_vport *vport = hclge_get_vport(handle); | |
858 | struct hclge_dev *hdev = vport->back; | |
859 | u64 *p; | |
860 | ||
861 | p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats, | |
862 | g_mac_stats_string, | |
863 | ARRAY_SIZE(g_mac_stats_string), | |
864 | data); | |
865 | p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats, | |
866 | g_all_32bit_stats_string, | |
867 | ARRAY_SIZE(g_all_32bit_stats_string), | |
868 | p); | |
869 | p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats, | |
870 | g_all_64bit_stats_string, | |
871 | ARRAY_SIZE(g_all_64bit_stats_string), | |
872 | p); | |
873 | p = hclge_tqps_get_stats(handle, p); | |
874 | } | |
875 | ||
876 | static int hclge_parse_func_status(struct hclge_dev *hdev, | |
d44f9b63 | 877 | struct hclge_func_status_cmd *status) |
46a3df9f S |
878 | { |
879 | if (!(status->pf_state & HCLGE_PF_STATE_DONE)) | |
880 | return -EINVAL; | |
881 | ||
882 | /* Set the pf to main pf */ | |
883 | if (status->pf_state & HCLGE_PF_STATE_MAIN) | |
884 | hdev->flag |= HCLGE_FLAG_MAIN; | |
885 | else | |
886 | hdev->flag &= ~HCLGE_FLAG_MAIN; | |
887 | ||
46a3df9f S |
888 | return 0; |
889 | } | |
890 | ||
891 | static int hclge_query_function_status(struct hclge_dev *hdev) | |
892 | { | |
d44f9b63 | 893 | struct hclge_func_status_cmd *req; |
46a3df9f S |
894 | struct hclge_desc desc; |
895 | int timeout = 0; | |
896 | int ret; | |
897 | ||
898 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true); | |
d44f9b63 | 899 | req = (struct hclge_func_status_cmd *)desc.data; |
46a3df9f S |
900 | |
901 | do { | |
902 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
903 | if (ret) { | |
904 | dev_err(&hdev->pdev->dev, | |
905 | "query function status failed %d.\n", | |
906 | ret); | |
907 | ||
908 | return ret; | |
909 | } | |
910 | ||
911 | /* Check pf reset is done */ | |
912 | if (req->pf_state) | |
913 | break; | |
914 | usleep_range(1000, 2000); | |
915 | } while (timeout++ < 5); | |
916 | ||
917 | ret = hclge_parse_func_status(hdev, req); | |
918 | ||
919 | return ret; | |
920 | } | |
921 | ||
922 | static int hclge_query_pf_resource(struct hclge_dev *hdev) | |
923 | { | |
d44f9b63 | 924 | struct hclge_pf_res_cmd *req; |
46a3df9f S |
925 | struct hclge_desc desc; |
926 | int ret; | |
927 | ||
928 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true); | |
929 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
930 | if (ret) { | |
931 | dev_err(&hdev->pdev->dev, | |
932 | "query pf resource failed %d.\n", ret); | |
933 | return ret; | |
934 | } | |
935 | ||
d44f9b63 | 936 | req = (struct hclge_pf_res_cmd *)desc.data; |
46a3df9f S |
937 | hdev->num_tqps = __le16_to_cpu(req->tqp_num); |
938 | hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S; | |
939 | ||
e92a0843 | 940 | if (hnae3_dev_roce_supported(hdev)) { |
887c3820 | 941 | hdev->num_roce_msi = |
e4e87715 PL |
942 | hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), |
943 | HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); | |
46a3df9f S |
944 | |
945 | /* PF should have NIC vectors and Roce vectors, | |
946 | * NIC vectors are queued before Roce vectors. | |
947 | */ | |
887c3820 | 948 | hdev->num_msi = hdev->num_roce_msi + HCLGE_ROCE_VECTOR_OFFSET; |
46a3df9f S |
949 | } else { |
950 | hdev->num_msi = | |
e4e87715 PL |
951 | hnae3_get_field(__le16_to_cpu(req->pf_intr_vector_number), |
952 | HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S); | |
46a3df9f S |
953 | } |
954 | ||
955 | return 0; | |
956 | } | |
957 | ||
958 | static int hclge_parse_speed(int speed_cmd, int *speed) | |
959 | { | |
960 | switch (speed_cmd) { | |
961 | case 6: | |
962 | *speed = HCLGE_MAC_SPEED_10M; | |
963 | break; | |
964 | case 7: | |
965 | *speed = HCLGE_MAC_SPEED_100M; | |
966 | break; | |
967 | case 0: | |
968 | *speed = HCLGE_MAC_SPEED_1G; | |
969 | break; | |
970 | case 1: | |
971 | *speed = HCLGE_MAC_SPEED_10G; | |
972 | break; | |
973 | case 2: | |
974 | *speed = HCLGE_MAC_SPEED_25G; | |
975 | break; | |
976 | case 3: | |
977 | *speed = HCLGE_MAC_SPEED_40G; | |
978 | break; | |
979 | case 4: | |
980 | *speed = HCLGE_MAC_SPEED_50G; | |
981 | break; | |
982 | case 5: | |
983 | *speed = HCLGE_MAC_SPEED_100G; | |
984 | break; | |
985 | default: | |
986 | return -EINVAL; | |
987 | } | |
988 | ||
989 | return 0; | |
990 | } | |
991 | ||
0979aa0b FL |
992 | static void hclge_parse_fiber_link_mode(struct hclge_dev *hdev, |
993 | u8 speed_ability) | |
994 | { | |
995 | unsigned long *supported = hdev->hw.mac.supported; | |
996 | ||
997 | if (speed_ability & HCLGE_SUPPORT_1G_BIT) | |
998 | set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, | |
999 | supported); | |
1000 | ||
1001 | if (speed_ability & HCLGE_SUPPORT_10G_BIT) | |
1002 | set_bit(ETHTOOL_LINK_MODE_10000baseSR_Full_BIT, | |
1003 | supported); | |
1004 | ||
1005 | if (speed_ability & HCLGE_SUPPORT_25G_BIT) | |
1006 | set_bit(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT, | |
1007 | supported); | |
1008 | ||
1009 | if (speed_ability & HCLGE_SUPPORT_50G_BIT) | |
1010 | set_bit(ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT, | |
1011 | supported); | |
1012 | ||
1013 | if (speed_ability & HCLGE_SUPPORT_100G_BIT) | |
1014 | set_bit(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT, | |
1015 | supported); | |
1016 | ||
1017 | set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, supported); | |
1018 | set_bit(ETHTOOL_LINK_MODE_Pause_BIT, supported); | |
1019 | } | |
1020 | ||
1021 | static void hclge_parse_link_mode(struct hclge_dev *hdev, u8 speed_ability) | |
1022 | { | |
1023 | u8 media_type = hdev->hw.mac.media_type; | |
1024 | ||
1025 | if (media_type != HNAE3_MEDIA_TYPE_FIBER) | |
1026 | return; | |
1027 | ||
1028 | hclge_parse_fiber_link_mode(hdev, speed_ability); | |
1029 | } | |
1030 | ||
46a3df9f S |
1031 | static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc) |
1032 | { | |
d44f9b63 | 1033 | struct hclge_cfg_param_cmd *req; |
46a3df9f S |
1034 | u64 mac_addr_tmp_high; |
1035 | u64 mac_addr_tmp; | |
1036 | int i; | |
1037 | ||
d44f9b63 | 1038 | req = (struct hclge_cfg_param_cmd *)desc[0].data; |
46a3df9f S |
1039 | |
1040 | /* get the configuration */ | |
e4e87715 PL |
1041 | cfg->vmdq_vport_num = hnae3_get_field(__le32_to_cpu(req->param[0]), |
1042 | HCLGE_CFG_VMDQ_M, | |
1043 | HCLGE_CFG_VMDQ_S); | |
1044 | cfg->tc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), | |
1045 | HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S); | |
1046 | cfg->tqp_desc_num = hnae3_get_field(__le32_to_cpu(req->param[0]), | |
1047 | HCLGE_CFG_TQP_DESC_N_M, | |
1048 | HCLGE_CFG_TQP_DESC_N_S); | |
1049 | ||
1050 | cfg->phy_addr = hnae3_get_field(__le32_to_cpu(req->param[1]), | |
1051 | HCLGE_CFG_PHY_ADDR_M, | |
1052 | HCLGE_CFG_PHY_ADDR_S); | |
1053 | cfg->media_type = hnae3_get_field(__le32_to_cpu(req->param[1]), | |
1054 | HCLGE_CFG_MEDIA_TP_M, | |
1055 | HCLGE_CFG_MEDIA_TP_S); | |
1056 | cfg->rx_buf_len = hnae3_get_field(__le32_to_cpu(req->param[1]), | |
1057 | HCLGE_CFG_RX_BUF_LEN_M, | |
1058 | HCLGE_CFG_RX_BUF_LEN_S); | |
46a3df9f S |
1059 | /* get mac_address */ |
1060 | mac_addr_tmp = __le32_to_cpu(req->param[2]); | |
e4e87715 PL |
1061 | mac_addr_tmp_high = hnae3_get_field(__le32_to_cpu(req->param[3]), |
1062 | HCLGE_CFG_MAC_ADDR_H_M, | |
1063 | HCLGE_CFG_MAC_ADDR_H_S); | |
46a3df9f S |
1064 | |
1065 | mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1; | |
1066 | ||
e4e87715 PL |
1067 | cfg->default_speed = hnae3_get_field(__le32_to_cpu(req->param[3]), |
1068 | HCLGE_CFG_DEFAULT_SPEED_M, | |
1069 | HCLGE_CFG_DEFAULT_SPEED_S); | |
1070 | cfg->rss_size_max = hnae3_get_field(__le32_to_cpu(req->param[3]), | |
1071 | HCLGE_CFG_RSS_SIZE_M, | |
1072 | HCLGE_CFG_RSS_SIZE_S); | |
0e7a40cd | 1073 | |
46a3df9f S |
1074 | for (i = 0; i < ETH_ALEN; i++) |
1075 | cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff; | |
1076 | ||
d44f9b63 | 1077 | req = (struct hclge_cfg_param_cmd *)desc[1].data; |
46a3df9f | 1078 | cfg->numa_node_map = __le32_to_cpu(req->param[0]); |
0979aa0b | 1079 | |
e4e87715 PL |
1080 | cfg->speed_ability = hnae3_get_field(__le32_to_cpu(req->param[1]), |
1081 | HCLGE_CFG_SPEED_ABILITY_M, | |
1082 | HCLGE_CFG_SPEED_ABILITY_S); | |
46a3df9f S |
1083 | } |
1084 | ||
1085 | /* hclge_get_cfg: query the static parameter from flash | |
1086 | * @hdev: pointer to struct hclge_dev | |
1087 | * @hcfg: the config structure to be getted | |
1088 | */ | |
1089 | static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg) | |
1090 | { | |
1091 | struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM]; | |
d44f9b63 | 1092 | struct hclge_cfg_param_cmd *req; |
46a3df9f S |
1093 | int i, ret; |
1094 | ||
1095 | for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) { | |
a90bb9a5 YL |
1096 | u32 offset = 0; |
1097 | ||
d44f9b63 | 1098 | req = (struct hclge_cfg_param_cmd *)desc[i].data; |
46a3df9f S |
1099 | hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM, |
1100 | true); | |
e4e87715 PL |
1101 | hnae3_set_field(offset, HCLGE_CFG_OFFSET_M, |
1102 | HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES); | |
46a3df9f | 1103 | /* Len should be united by 4 bytes when send to hardware */ |
e4e87715 PL |
1104 | hnae3_set_field(offset, HCLGE_CFG_RD_LEN_M, HCLGE_CFG_RD_LEN_S, |
1105 | HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT); | |
a90bb9a5 | 1106 | req->offset = cpu_to_le32(offset); |
46a3df9f S |
1107 | } |
1108 | ||
1109 | ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM); | |
1110 | if (ret) { | |
1111 | dev_err(&hdev->pdev->dev, | |
1112 | "get config failed %d.\n", ret); | |
1113 | return ret; | |
1114 | } | |
1115 | ||
1116 | hclge_parse_cfg(hcfg, desc); | |
1117 | return 0; | |
1118 | } | |
1119 | ||
1120 | static int hclge_get_cap(struct hclge_dev *hdev) | |
1121 | { | |
1122 | int ret; | |
1123 | ||
1124 | ret = hclge_query_function_status(hdev); | |
1125 | if (ret) { | |
1126 | dev_err(&hdev->pdev->dev, | |
1127 | "query function status error %d.\n", ret); | |
1128 | return ret; | |
1129 | } | |
1130 | ||
1131 | /* get pf resource */ | |
1132 | ret = hclge_query_pf_resource(hdev); | |
1133 | if (ret) { | |
1134 | dev_err(&hdev->pdev->dev, | |
1135 | "query pf resource error %d.\n", ret); | |
1136 | return ret; | |
1137 | } | |
1138 | ||
1139 | return 0; | |
1140 | } | |
1141 | ||
1142 | static int hclge_configure(struct hclge_dev *hdev) | |
1143 | { | |
1144 | struct hclge_cfg cfg; | |
1145 | int ret, i; | |
1146 | ||
1147 | ret = hclge_get_cfg(hdev, &cfg); | |
1148 | if (ret) { | |
1149 | dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret); | |
1150 | return ret; | |
1151 | } | |
1152 | ||
1153 | hdev->num_vmdq_vport = cfg.vmdq_vport_num; | |
1154 | hdev->base_tqp_pid = 0; | |
0e7a40cd | 1155 | hdev->rss_size_max = cfg.rss_size_max; |
46a3df9f | 1156 | hdev->rx_buf_len = cfg.rx_buf_len; |
fbbb1536 | 1157 | ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr); |
46a3df9f | 1158 | hdev->hw.mac.media_type = cfg.media_type; |
2a4776e1 | 1159 | hdev->hw.mac.phy_addr = cfg.phy_addr; |
46a3df9f S |
1160 | hdev->num_desc = cfg.tqp_desc_num; |
1161 | hdev->tm_info.num_pg = 1; | |
cacde272 | 1162 | hdev->tc_max = cfg.tc_num; |
46a3df9f S |
1163 | hdev->tm_info.hw_pfc_map = 0; |
1164 | ||
1165 | ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed); | |
1166 | if (ret) { | |
1167 | dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret); | |
1168 | return ret; | |
1169 | } | |
1170 | ||
0979aa0b FL |
1171 | hclge_parse_link_mode(hdev, cfg.speed_ability); |
1172 | ||
cacde272 YL |
1173 | if ((hdev->tc_max > HNAE3_MAX_TC) || |
1174 | (hdev->tc_max < 1)) { | |
46a3df9f | 1175 | dev_warn(&hdev->pdev->dev, "TC num = %d.\n", |
cacde272 YL |
1176 | hdev->tc_max); |
1177 | hdev->tc_max = 1; | |
46a3df9f S |
1178 | } |
1179 | ||
cacde272 YL |
1180 | /* Dev does not support DCB */ |
1181 | if (!hnae3_dev_dcb_supported(hdev)) { | |
1182 | hdev->tc_max = 1; | |
1183 | hdev->pfc_max = 0; | |
1184 | } else { | |
1185 | hdev->pfc_max = hdev->tc_max; | |
1186 | } | |
1187 | ||
1188 | hdev->tm_info.num_tc = hdev->tc_max; | |
1189 | ||
46a3df9f | 1190 | /* Currently not support uncontiuous tc */ |
cacde272 | 1191 | for (i = 0; i < hdev->tm_info.num_tc; i++) |
e4e87715 | 1192 | hnae3_set_bit(hdev->hw_tc_map, i, 1); |
46a3df9f | 1193 | |
71b83869 | 1194 | hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE; |
46a3df9f S |
1195 | |
1196 | return ret; | |
1197 | } | |
1198 | ||
1199 | static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min, | |
1200 | int tso_mss_max) | |
1201 | { | |
d44f9b63 | 1202 | struct hclge_cfg_tso_status_cmd *req; |
46a3df9f | 1203 | struct hclge_desc desc; |
a90bb9a5 | 1204 | u16 tso_mss; |
46a3df9f S |
1205 | |
1206 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false); | |
1207 | ||
d44f9b63 | 1208 | req = (struct hclge_cfg_tso_status_cmd *)desc.data; |
a90bb9a5 YL |
1209 | |
1210 | tso_mss = 0; | |
e4e87715 PL |
1211 | hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, |
1212 | HCLGE_TSO_MSS_MIN_S, tso_mss_min); | |
a90bb9a5 YL |
1213 | req->tso_mss_min = cpu_to_le16(tso_mss); |
1214 | ||
1215 | tso_mss = 0; | |
e4e87715 PL |
1216 | hnae3_set_field(tso_mss, HCLGE_TSO_MSS_MIN_M, |
1217 | HCLGE_TSO_MSS_MIN_S, tso_mss_max); | |
a90bb9a5 | 1218 | req->tso_mss_max = cpu_to_le16(tso_mss); |
46a3df9f S |
1219 | |
1220 | return hclge_cmd_send(&hdev->hw, &desc, 1); | |
1221 | } | |
1222 | ||
1223 | static int hclge_alloc_tqps(struct hclge_dev *hdev) | |
1224 | { | |
1225 | struct hclge_tqp *tqp; | |
1226 | int i; | |
1227 | ||
1228 | hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps, | |
1229 | sizeof(struct hclge_tqp), GFP_KERNEL); | |
1230 | if (!hdev->htqp) | |
1231 | return -ENOMEM; | |
1232 | ||
1233 | tqp = hdev->htqp; | |
1234 | ||
1235 | for (i = 0; i < hdev->num_tqps; i++) { | |
1236 | tqp->dev = &hdev->pdev->dev; | |
1237 | tqp->index = i; | |
1238 | ||
1239 | tqp->q.ae_algo = &ae_algo; | |
1240 | tqp->q.buf_size = hdev->rx_buf_len; | |
1241 | tqp->q.desc_num = hdev->num_desc; | |
1242 | tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET + | |
1243 | i * HCLGE_TQP_REG_SIZE; | |
1244 | ||
1245 | tqp++; | |
1246 | } | |
1247 | ||
1248 | return 0; | |
1249 | } | |
1250 | ||
1251 | static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id, | |
1252 | u16 tqp_pid, u16 tqp_vid, bool is_pf) | |
1253 | { | |
d44f9b63 | 1254 | struct hclge_tqp_map_cmd *req; |
46a3df9f S |
1255 | struct hclge_desc desc; |
1256 | int ret; | |
1257 | ||
1258 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false); | |
1259 | ||
d44f9b63 | 1260 | req = (struct hclge_tqp_map_cmd *)desc.data; |
46a3df9f | 1261 | req->tqp_id = cpu_to_le16(tqp_pid); |
a90bb9a5 | 1262 | req->tqp_vf = func_id; |
46a3df9f S |
1263 | req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B | |
1264 | 1 << HCLGE_TQP_MAP_EN_B; | |
1265 | req->tqp_vid = cpu_to_le16(tqp_vid); | |
1266 | ||
1267 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
1268 | if (ret) { | |
1269 | dev_err(&hdev->pdev->dev, "TQP map failed %d.\n", | |
1270 | ret); | |
1271 | return ret; | |
1272 | } | |
1273 | ||
1274 | return 0; | |
1275 | } | |
1276 | ||
1277 | static int hclge_assign_tqp(struct hclge_vport *vport, | |
1278 | struct hnae3_queue **tqp, u16 num_tqps) | |
1279 | { | |
1280 | struct hclge_dev *hdev = vport->back; | |
7df7dad6 | 1281 | int i, alloced; |
46a3df9f S |
1282 | |
1283 | for (i = 0, alloced = 0; i < hdev->num_tqps && | |
1284 | alloced < num_tqps; i++) { | |
1285 | if (!hdev->htqp[i].alloced) { | |
1286 | hdev->htqp[i].q.handle = &vport->nic; | |
1287 | hdev->htqp[i].q.tqp_index = alloced; | |
1288 | tqp[alloced] = &hdev->htqp[i].q; | |
1289 | hdev->htqp[i].alloced = true; | |
46a3df9f S |
1290 | alloced++; |
1291 | } | |
1292 | } | |
1293 | vport->alloc_tqps = num_tqps; | |
1294 | ||
1295 | return 0; | |
1296 | } | |
1297 | ||
1298 | static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps) | |
1299 | { | |
1300 | struct hnae3_handle *nic = &vport->nic; | |
1301 | struct hnae3_knic_private_info *kinfo = &nic->kinfo; | |
1302 | struct hclge_dev *hdev = vport->back; | |
1303 | int i, ret; | |
1304 | ||
1305 | kinfo->num_desc = hdev->num_desc; | |
1306 | kinfo->rx_buf_len = hdev->rx_buf_len; | |
1307 | kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc); | |
1308 | kinfo->rss_size | |
1309 | = min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc); | |
1310 | kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc; | |
1311 | ||
1312 | for (i = 0; i < HNAE3_MAX_TC; i++) { | |
1313 | if (hdev->hw_tc_map & BIT(i)) { | |
1314 | kinfo->tc_info[i].enable = true; | |
1315 | kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size; | |
1316 | kinfo->tc_info[i].tqp_count = kinfo->rss_size; | |
1317 | kinfo->tc_info[i].tc = i; | |
1318 | } else { | |
1319 | /* Set to default queue if TC is disable */ | |
1320 | kinfo->tc_info[i].enable = false; | |
1321 | kinfo->tc_info[i].tqp_offset = 0; | |
1322 | kinfo->tc_info[i].tqp_count = 1; | |
1323 | kinfo->tc_info[i].tc = 0; | |
1324 | } | |
1325 | } | |
1326 | ||
1327 | kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps, | |
1328 | sizeof(struct hnae3_queue *), GFP_KERNEL); | |
1329 | if (!kinfo->tqp) | |
1330 | return -ENOMEM; | |
1331 | ||
1332 | ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps); | |
1333 | if (ret) { | |
1334 | dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret); | |
1335 | return -EINVAL; | |
1336 | } | |
1337 | ||
1338 | return 0; | |
1339 | } | |
1340 | ||
7df7dad6 L |
1341 | static int hclge_map_tqp_to_vport(struct hclge_dev *hdev, |
1342 | struct hclge_vport *vport) | |
1343 | { | |
1344 | struct hnae3_handle *nic = &vport->nic; | |
1345 | struct hnae3_knic_private_info *kinfo; | |
1346 | u16 i; | |
1347 | ||
1348 | kinfo = &nic->kinfo; | |
1349 | for (i = 0; i < kinfo->num_tqps; i++) { | |
1350 | struct hclge_tqp *q = | |
1351 | container_of(kinfo->tqp[i], struct hclge_tqp, q); | |
1352 | bool is_pf; | |
1353 | int ret; | |
1354 | ||
1355 | is_pf = !(vport->vport_id); | |
1356 | ret = hclge_map_tqps_to_func(hdev, vport->vport_id, q->index, | |
1357 | i, is_pf); | |
1358 | if (ret) | |
1359 | return ret; | |
1360 | } | |
1361 | ||
1362 | return 0; | |
1363 | } | |
1364 | ||
1365 | static int hclge_map_tqp(struct hclge_dev *hdev) | |
1366 | { | |
1367 | struct hclge_vport *vport = hdev->vport; | |
1368 | u16 i, num_vport; | |
1369 | ||
1370 | num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; | |
1371 | for (i = 0; i < num_vport; i++) { | |
1372 | int ret; | |
1373 | ||
1374 | ret = hclge_map_tqp_to_vport(hdev, vport); | |
1375 | if (ret) | |
1376 | return ret; | |
1377 | ||
1378 | vport++; | |
1379 | } | |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
46a3df9f S |
1384 | static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps) |
1385 | { | |
1386 | /* this would be initialized later */ | |
1387 | } | |
1388 | ||
1389 | static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps) | |
1390 | { | |
1391 | struct hnae3_handle *nic = &vport->nic; | |
1392 | struct hclge_dev *hdev = vport->back; | |
1393 | int ret; | |
1394 | ||
1395 | nic->pdev = hdev->pdev; | |
1396 | nic->ae_algo = &ae_algo; | |
1397 | nic->numa_node_mask = hdev->numa_node_mask; | |
1398 | ||
1399 | if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) { | |
1400 | ret = hclge_knic_setup(vport, num_tqps); | |
1401 | if (ret) { | |
1402 | dev_err(&hdev->pdev->dev, "knic setup failed %d\n", | |
1403 | ret); | |
1404 | return ret; | |
1405 | } | |
1406 | } else { | |
1407 | hclge_unic_setup(vport, num_tqps); | |
1408 | } | |
1409 | ||
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | static int hclge_alloc_vport(struct hclge_dev *hdev) | |
1414 | { | |
1415 | struct pci_dev *pdev = hdev->pdev; | |
1416 | struct hclge_vport *vport; | |
1417 | u32 tqp_main_vport; | |
1418 | u32 tqp_per_vport; | |
1419 | int num_vport, i; | |
1420 | int ret; | |
1421 | ||
1422 | /* We need to alloc a vport for main NIC of PF */ | |
1423 | num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1; | |
1424 | ||
38e62046 HT |
1425 | if (hdev->num_tqps < num_vport) { |
1426 | dev_err(&hdev->pdev->dev, "tqps(%d) is less than vports(%d)", | |
1427 | hdev->num_tqps, num_vport); | |
1428 | return -EINVAL; | |
1429 | } | |
46a3df9f S |
1430 | |
1431 | /* Alloc the same number of TQPs for every vport */ | |
1432 | tqp_per_vport = hdev->num_tqps / num_vport; | |
1433 | tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport; | |
1434 | ||
1435 | vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport), | |
1436 | GFP_KERNEL); | |
1437 | if (!vport) | |
1438 | return -ENOMEM; | |
1439 | ||
1440 | hdev->vport = vport; | |
1441 | hdev->num_alloc_vport = num_vport; | |
1442 | ||
2312e050 FL |
1443 | if (IS_ENABLED(CONFIG_PCI_IOV)) |
1444 | hdev->num_alloc_vfs = hdev->num_req_vfs; | |
46a3df9f S |
1445 | |
1446 | for (i = 0; i < num_vport; i++) { | |
1447 | vport->back = hdev; | |
1448 | vport->vport_id = i; | |
1449 | ||
1450 | if (i == 0) | |
1451 | ret = hclge_vport_setup(vport, tqp_main_vport); | |
1452 | else | |
1453 | ret = hclge_vport_setup(vport, tqp_per_vport); | |
1454 | if (ret) { | |
1455 | dev_err(&pdev->dev, | |
1456 | "vport setup failed for vport %d, %d\n", | |
1457 | i, ret); | |
1458 | return ret; | |
1459 | } | |
1460 | ||
1461 | vport++; | |
1462 | } | |
1463 | ||
1464 | return 0; | |
1465 | } | |
1466 | ||
acf61ecd YL |
1467 | static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, |
1468 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f S |
1469 | { |
1470 | /* TX buffer size is unit by 128 byte */ | |
1471 | #define HCLGE_BUF_SIZE_UNIT_SHIFT 7 | |
1472 | #define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15) | |
d44f9b63 | 1473 | struct hclge_tx_buff_alloc_cmd *req; |
46a3df9f S |
1474 | struct hclge_desc desc; |
1475 | int ret; | |
1476 | u8 i; | |
1477 | ||
d44f9b63 | 1478 | req = (struct hclge_tx_buff_alloc_cmd *)desc.data; |
46a3df9f S |
1479 | |
1480 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0); | |
9ffe79a9 | 1481 | for (i = 0; i < HCLGE_TC_NUM; i++) { |
acf61ecd | 1482 | u32 buf_size = buf_alloc->priv_buf[i].tx_buf_size; |
9ffe79a9 | 1483 | |
46a3df9f S |
1484 | req->tx_pkt_buff[i] = |
1485 | cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) | | |
1486 | HCLGE_BUF_SIZE_UPDATE_EN_MSK); | |
9ffe79a9 | 1487 | } |
46a3df9f S |
1488 | |
1489 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
1490 | if (ret) { | |
1491 | dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n", | |
1492 | ret); | |
1493 | return ret; | |
1494 | } | |
1495 | ||
1496 | return 0; | |
1497 | } | |
1498 | ||
acf61ecd YL |
1499 | static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, |
1500 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1501 | { |
acf61ecd | 1502 | int ret = hclge_cmd_alloc_tx_buff(hdev, buf_alloc); |
46a3df9f S |
1503 | |
1504 | if (ret) { | |
1505 | dev_err(&hdev->pdev->dev, | |
1506 | "tx buffer alloc failed %d\n", ret); | |
1507 | return ret; | |
1508 | } | |
1509 | ||
1510 | return 0; | |
1511 | } | |
1512 | ||
1513 | static int hclge_get_tc_num(struct hclge_dev *hdev) | |
1514 | { | |
1515 | int i, cnt = 0; | |
1516 | ||
1517 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) | |
1518 | if (hdev->hw_tc_map & BIT(i)) | |
1519 | cnt++; | |
1520 | return cnt; | |
1521 | } | |
1522 | ||
1523 | static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev) | |
1524 | { | |
1525 | int i, cnt = 0; | |
1526 | ||
1527 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) | |
1528 | if (hdev->hw_tc_map & BIT(i) && | |
1529 | hdev->tm_info.hw_pfc_map & BIT(i)) | |
1530 | cnt++; | |
1531 | return cnt; | |
1532 | } | |
1533 | ||
1534 | /* Get the number of pfc enabled TCs, which have private buffer */ | |
acf61ecd YL |
1535 | static int hclge_get_pfc_priv_num(struct hclge_dev *hdev, |
1536 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f S |
1537 | { |
1538 | struct hclge_priv_buf *priv; | |
1539 | int i, cnt = 0; | |
1540 | ||
1541 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1542 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1543 | if ((hdev->tm_info.hw_pfc_map & BIT(i)) && |
1544 | priv->enable) | |
1545 | cnt++; | |
1546 | } | |
1547 | ||
1548 | return cnt; | |
1549 | } | |
1550 | ||
1551 | /* Get the number of pfc disabled TCs, which have private buffer */ | |
acf61ecd YL |
1552 | static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev, |
1553 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f S |
1554 | { |
1555 | struct hclge_priv_buf *priv; | |
1556 | int i, cnt = 0; | |
1557 | ||
1558 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1559 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1560 | if (hdev->hw_tc_map & BIT(i) && |
1561 | !(hdev->tm_info.hw_pfc_map & BIT(i)) && | |
1562 | priv->enable) | |
1563 | cnt++; | |
1564 | } | |
1565 | ||
1566 | return cnt; | |
1567 | } | |
1568 | ||
acf61ecd | 1569 | static u32 hclge_get_rx_priv_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) |
46a3df9f S |
1570 | { |
1571 | struct hclge_priv_buf *priv; | |
1572 | u32 rx_priv = 0; | |
1573 | int i; | |
1574 | ||
1575 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1576 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1577 | if (priv->enable) |
1578 | rx_priv += priv->buf_size; | |
1579 | } | |
1580 | return rx_priv; | |
1581 | } | |
1582 | ||
acf61ecd | 1583 | static u32 hclge_get_tx_buff_alloced(struct hclge_pkt_buf_alloc *buf_alloc) |
9ffe79a9 YL |
1584 | { |
1585 | u32 i, total_tx_size = 0; | |
1586 | ||
1587 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) | |
acf61ecd | 1588 | total_tx_size += buf_alloc->priv_buf[i].tx_buf_size; |
9ffe79a9 YL |
1589 | |
1590 | return total_tx_size; | |
1591 | } | |
1592 | ||
acf61ecd YL |
1593 | static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, |
1594 | struct hclge_pkt_buf_alloc *buf_alloc, | |
1595 | u32 rx_all) | |
46a3df9f S |
1596 | { |
1597 | u32 shared_buf_min, shared_buf_tc, shared_std; | |
1598 | int tc_num, pfc_enable_num; | |
1599 | u32 shared_buf; | |
1600 | u32 rx_priv; | |
1601 | int i; | |
1602 | ||
1603 | tc_num = hclge_get_tc_num(hdev); | |
1604 | pfc_enable_num = hclge_get_pfc_enalbe_num(hdev); | |
1605 | ||
d221df4e YL |
1606 | if (hnae3_dev_dcb_supported(hdev)) |
1607 | shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV; | |
1608 | else | |
1609 | shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV; | |
1610 | ||
46a3df9f S |
1611 | shared_buf_tc = pfc_enable_num * hdev->mps + |
1612 | (tc_num - pfc_enable_num) * hdev->mps / 2 + | |
1613 | hdev->mps; | |
1614 | shared_std = max_t(u32, shared_buf_min, shared_buf_tc); | |
1615 | ||
acf61ecd | 1616 | rx_priv = hclge_get_rx_priv_buff_alloced(buf_alloc); |
46a3df9f S |
1617 | if (rx_all <= rx_priv + shared_std) |
1618 | return false; | |
1619 | ||
1620 | shared_buf = rx_all - rx_priv; | |
acf61ecd YL |
1621 | buf_alloc->s_buf.buf_size = shared_buf; |
1622 | buf_alloc->s_buf.self.high = shared_buf; | |
1623 | buf_alloc->s_buf.self.low = 2 * hdev->mps; | |
46a3df9f S |
1624 | |
1625 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
1626 | if ((hdev->hw_tc_map & BIT(i)) && | |
1627 | (hdev->tm_info.hw_pfc_map & BIT(i))) { | |
acf61ecd YL |
1628 | buf_alloc->s_buf.tc_thrd[i].low = hdev->mps; |
1629 | buf_alloc->s_buf.tc_thrd[i].high = 2 * hdev->mps; | |
46a3df9f | 1630 | } else { |
acf61ecd YL |
1631 | buf_alloc->s_buf.tc_thrd[i].low = 0; |
1632 | buf_alloc->s_buf.tc_thrd[i].high = hdev->mps; | |
46a3df9f S |
1633 | } |
1634 | } | |
1635 | ||
1636 | return true; | |
1637 | } | |
1638 | ||
acf61ecd YL |
1639 | static int hclge_tx_buffer_calc(struct hclge_dev *hdev, |
1640 | struct hclge_pkt_buf_alloc *buf_alloc) | |
9ffe79a9 YL |
1641 | { |
1642 | u32 i, total_size; | |
1643 | ||
1644 | total_size = hdev->pkt_buf_size; | |
1645 | ||
1646 | /* alloc tx buffer for all enabled tc */ | |
1647 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1648 | struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; |
9ffe79a9 YL |
1649 | |
1650 | if (total_size < HCLGE_DEFAULT_TX_BUF) | |
1651 | return -ENOMEM; | |
1652 | ||
1653 | if (hdev->hw_tc_map & BIT(i)) | |
1654 | priv->tx_buf_size = HCLGE_DEFAULT_TX_BUF; | |
1655 | else | |
1656 | priv->tx_buf_size = 0; | |
1657 | ||
1658 | total_size -= priv->tx_buf_size; | |
1659 | } | |
1660 | ||
1661 | return 0; | |
1662 | } | |
1663 | ||
46a3df9f S |
1664 | /* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs |
1665 | * @hdev: pointer to struct hclge_dev | |
acf61ecd | 1666 | * @buf_alloc: pointer to buffer calculation data |
46a3df9f S |
1667 | * @return: 0: calculate sucessful, negative: fail |
1668 | */ | |
1db9b1bf YL |
1669 | static int hclge_rx_buffer_calc(struct hclge_dev *hdev, |
1670 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1671 | { |
9ffe79a9 | 1672 | u32 rx_all = hdev->pkt_buf_size; |
46a3df9f S |
1673 | int no_pfc_priv_num, pfc_priv_num; |
1674 | struct hclge_priv_buf *priv; | |
1675 | int i; | |
1676 | ||
acf61ecd | 1677 | rx_all -= hclge_get_tx_buff_alloced(buf_alloc); |
9ffe79a9 | 1678 | |
d602a525 YL |
1679 | /* When DCB is not supported, rx private |
1680 | * buffer is not allocated. | |
1681 | */ | |
1682 | if (!hnae3_dev_dcb_supported(hdev)) { | |
acf61ecd | 1683 | if (!hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
d602a525 YL |
1684 | return -ENOMEM; |
1685 | ||
1686 | return 0; | |
1687 | } | |
1688 | ||
46a3df9f S |
1689 | /* step 1, try to alloc private buffer for all enabled tc */ |
1690 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1691 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1692 | if (hdev->hw_tc_map & BIT(i)) { |
1693 | priv->enable = 1; | |
1694 | if (hdev->tm_info.hw_pfc_map & BIT(i)) { | |
1695 | priv->wl.low = hdev->mps; | |
1696 | priv->wl.high = priv->wl.low + hdev->mps; | |
1697 | priv->buf_size = priv->wl.high + | |
1698 | HCLGE_DEFAULT_DV; | |
1699 | } else { | |
1700 | priv->wl.low = 0; | |
1701 | priv->wl.high = 2 * hdev->mps; | |
1702 | priv->buf_size = priv->wl.high; | |
1703 | } | |
bb1fe9ea YL |
1704 | } else { |
1705 | priv->enable = 0; | |
1706 | priv->wl.low = 0; | |
1707 | priv->wl.high = 0; | |
1708 | priv->buf_size = 0; | |
46a3df9f S |
1709 | } |
1710 | } | |
1711 | ||
acf61ecd | 1712 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
46a3df9f S |
1713 | return 0; |
1714 | ||
1715 | /* step 2, try to decrease the buffer size of | |
1716 | * no pfc TC's private buffer | |
1717 | */ | |
1718 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1719 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f | 1720 | |
bb1fe9ea YL |
1721 | priv->enable = 0; |
1722 | priv->wl.low = 0; | |
1723 | priv->wl.high = 0; | |
1724 | priv->buf_size = 0; | |
1725 | ||
1726 | if (!(hdev->hw_tc_map & BIT(i))) | |
1727 | continue; | |
1728 | ||
1729 | priv->enable = 1; | |
46a3df9f S |
1730 | |
1731 | if (hdev->tm_info.hw_pfc_map & BIT(i)) { | |
1732 | priv->wl.low = 128; | |
1733 | priv->wl.high = priv->wl.low + hdev->mps; | |
1734 | priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV; | |
1735 | } else { | |
1736 | priv->wl.low = 0; | |
1737 | priv->wl.high = hdev->mps; | |
1738 | priv->buf_size = priv->wl.high; | |
1739 | } | |
1740 | } | |
1741 | ||
acf61ecd | 1742 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
46a3df9f S |
1743 | return 0; |
1744 | ||
1745 | /* step 3, try to reduce the number of pfc disabled TCs, | |
1746 | * which have private buffer | |
1747 | */ | |
1748 | /* get the total no pfc enable TC number, which have private buffer */ | |
acf61ecd | 1749 | no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev, buf_alloc); |
46a3df9f S |
1750 | |
1751 | /* let the last to be cleared first */ | |
1752 | for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { | |
acf61ecd | 1753 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1754 | |
1755 | if (hdev->hw_tc_map & BIT(i) && | |
1756 | !(hdev->tm_info.hw_pfc_map & BIT(i))) { | |
1757 | /* Clear the no pfc TC private buffer */ | |
1758 | priv->wl.low = 0; | |
1759 | priv->wl.high = 0; | |
1760 | priv->buf_size = 0; | |
1761 | priv->enable = 0; | |
1762 | no_pfc_priv_num--; | |
1763 | } | |
1764 | ||
acf61ecd | 1765 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || |
46a3df9f S |
1766 | no_pfc_priv_num == 0) |
1767 | break; | |
1768 | } | |
1769 | ||
acf61ecd | 1770 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
46a3df9f S |
1771 | return 0; |
1772 | ||
1773 | /* step 4, try to reduce the number of pfc enabled TCs | |
1774 | * which have private buffer. | |
1775 | */ | |
acf61ecd | 1776 | pfc_priv_num = hclge_get_pfc_priv_num(hdev, buf_alloc); |
46a3df9f S |
1777 | |
1778 | /* let the last to be cleared first */ | |
1779 | for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) { | |
acf61ecd | 1780 | priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1781 | |
1782 | if (hdev->hw_tc_map & BIT(i) && | |
1783 | hdev->tm_info.hw_pfc_map & BIT(i)) { | |
1784 | /* Reduce the number of pfc TC with private buffer */ | |
1785 | priv->wl.low = 0; | |
1786 | priv->enable = 0; | |
1787 | priv->wl.high = 0; | |
1788 | priv->buf_size = 0; | |
1789 | pfc_priv_num--; | |
1790 | } | |
1791 | ||
acf61ecd | 1792 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all) || |
46a3df9f S |
1793 | pfc_priv_num == 0) |
1794 | break; | |
1795 | } | |
acf61ecd | 1796 | if (hclge_is_rx_buf_ok(hdev, buf_alloc, rx_all)) |
46a3df9f S |
1797 | return 0; |
1798 | ||
1799 | return -ENOMEM; | |
1800 | } | |
1801 | ||
acf61ecd YL |
1802 | static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev, |
1803 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1804 | { |
d44f9b63 | 1805 | struct hclge_rx_priv_buff_cmd *req; |
46a3df9f S |
1806 | struct hclge_desc desc; |
1807 | int ret; | |
1808 | int i; | |
1809 | ||
1810 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false); | |
d44f9b63 | 1811 | req = (struct hclge_rx_priv_buff_cmd *)desc.data; |
46a3df9f S |
1812 | |
1813 | /* Alloc private buffer TCs */ | |
1814 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
acf61ecd | 1815 | struct hclge_priv_buf *priv = &buf_alloc->priv_buf[i]; |
46a3df9f S |
1816 | |
1817 | req->buf_num[i] = | |
1818 | cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S); | |
1819 | req->buf_num[i] |= | |
5bca3b94 | 1820 | cpu_to_le16(1 << HCLGE_TC0_PRI_BUF_EN_B); |
46a3df9f S |
1821 | } |
1822 | ||
b8c8bf47 | 1823 | req->shared_buf = |
acf61ecd | 1824 | cpu_to_le16((buf_alloc->s_buf.buf_size >> HCLGE_BUF_UNIT_S) | |
b8c8bf47 YL |
1825 | (1 << HCLGE_TC0_PRI_BUF_EN_B)); |
1826 | ||
46a3df9f S |
1827 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
1828 | if (ret) { | |
1829 | dev_err(&hdev->pdev->dev, | |
1830 | "rx private buffer alloc cmd failed %d\n", ret); | |
1831 | return ret; | |
1832 | } | |
1833 | ||
1834 | return 0; | |
1835 | } | |
1836 | ||
acf61ecd YL |
1837 | static int hclge_rx_priv_wl_config(struct hclge_dev *hdev, |
1838 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f S |
1839 | { |
1840 | struct hclge_rx_priv_wl_buf *req; | |
1841 | struct hclge_priv_buf *priv; | |
1842 | struct hclge_desc desc[2]; | |
1843 | int i, j; | |
1844 | int ret; | |
1845 | ||
1846 | for (i = 0; i < 2; i++) { | |
1847 | hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC, | |
1848 | false); | |
1849 | req = (struct hclge_rx_priv_wl_buf *)desc[i].data; | |
1850 | ||
1851 | /* The first descriptor set the NEXT bit to 1 */ | |
1852 | if (i == 0) | |
1853 | desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
1854 | else | |
1855 | desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
1856 | ||
1857 | for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { | |
acf61ecd YL |
1858 | u32 idx = i * HCLGE_TC_NUM_ONE_DESC + j; |
1859 | ||
1860 | priv = &buf_alloc->priv_buf[idx]; | |
46a3df9f S |
1861 | req->tc_wl[j].high = |
1862 | cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S); | |
1863 | req->tc_wl[j].high |= | |
3738287c | 1864 | cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
46a3df9f S |
1865 | req->tc_wl[j].low = |
1866 | cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S); | |
1867 | req->tc_wl[j].low |= | |
3738287c | 1868 | cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
46a3df9f S |
1869 | } |
1870 | } | |
1871 | ||
1872 | /* Send 2 descriptor at one time */ | |
1873 | ret = hclge_cmd_send(&hdev->hw, desc, 2); | |
1874 | if (ret) { | |
1875 | dev_err(&hdev->pdev->dev, | |
1876 | "rx private waterline config cmd failed %d\n", | |
1877 | ret); | |
1878 | return ret; | |
1879 | } | |
1880 | return 0; | |
1881 | } | |
1882 | ||
acf61ecd YL |
1883 | static int hclge_common_thrd_config(struct hclge_dev *hdev, |
1884 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1885 | { |
acf61ecd | 1886 | struct hclge_shared_buf *s_buf = &buf_alloc->s_buf; |
46a3df9f S |
1887 | struct hclge_rx_com_thrd *req; |
1888 | struct hclge_desc desc[2]; | |
1889 | struct hclge_tc_thrd *tc; | |
1890 | int i, j; | |
1891 | int ret; | |
1892 | ||
1893 | for (i = 0; i < 2; i++) { | |
1894 | hclge_cmd_setup_basic_desc(&desc[i], | |
1895 | HCLGE_OPC_RX_COM_THRD_ALLOC, false); | |
1896 | req = (struct hclge_rx_com_thrd *)&desc[i].data; | |
1897 | ||
1898 | /* The first descriptor set the NEXT bit to 1 */ | |
1899 | if (i == 0) | |
1900 | desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
1901 | else | |
1902 | desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
1903 | ||
1904 | for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) { | |
1905 | tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j]; | |
1906 | ||
1907 | req->com_thrd[j].high = | |
1908 | cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S); | |
1909 | req->com_thrd[j].high |= | |
3738287c | 1910 | cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
46a3df9f S |
1911 | req->com_thrd[j].low = |
1912 | cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S); | |
1913 | req->com_thrd[j].low |= | |
3738287c | 1914 | cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
46a3df9f S |
1915 | } |
1916 | } | |
1917 | ||
1918 | /* Send 2 descriptors at one time */ | |
1919 | ret = hclge_cmd_send(&hdev->hw, desc, 2); | |
1920 | if (ret) { | |
1921 | dev_err(&hdev->pdev->dev, | |
1922 | "common threshold config cmd failed %d\n", ret); | |
1923 | return ret; | |
1924 | } | |
1925 | return 0; | |
1926 | } | |
1927 | ||
acf61ecd YL |
1928 | static int hclge_common_wl_config(struct hclge_dev *hdev, |
1929 | struct hclge_pkt_buf_alloc *buf_alloc) | |
46a3df9f | 1930 | { |
acf61ecd | 1931 | struct hclge_shared_buf *buf = &buf_alloc->s_buf; |
46a3df9f S |
1932 | struct hclge_rx_com_wl *req; |
1933 | struct hclge_desc desc; | |
1934 | int ret; | |
1935 | ||
1936 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false); | |
1937 | ||
1938 | req = (struct hclge_rx_com_wl *)desc.data; | |
1939 | req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S); | |
3738287c | 1940 | req->com_wl.high |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
46a3df9f S |
1941 | |
1942 | req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S); | |
3738287c | 1943 | req->com_wl.low |= cpu_to_le16(BIT(HCLGE_RX_PRIV_EN_B)); |
46a3df9f S |
1944 | |
1945 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
1946 | if (ret) { | |
1947 | dev_err(&hdev->pdev->dev, | |
1948 | "common waterline config cmd failed %d\n", ret); | |
1949 | return ret; | |
1950 | } | |
1951 | ||
1952 | return 0; | |
1953 | } | |
1954 | ||
1955 | int hclge_buffer_alloc(struct hclge_dev *hdev) | |
1956 | { | |
acf61ecd | 1957 | struct hclge_pkt_buf_alloc *pkt_buf; |
46a3df9f S |
1958 | int ret; |
1959 | ||
acf61ecd YL |
1960 | pkt_buf = kzalloc(sizeof(*pkt_buf), GFP_KERNEL); |
1961 | if (!pkt_buf) | |
46a3df9f S |
1962 | return -ENOMEM; |
1963 | ||
acf61ecd | 1964 | ret = hclge_tx_buffer_calc(hdev, pkt_buf); |
9ffe79a9 YL |
1965 | if (ret) { |
1966 | dev_err(&hdev->pdev->dev, | |
1967 | "could not calc tx buffer size for all TCs %d\n", ret); | |
acf61ecd | 1968 | goto out; |
9ffe79a9 YL |
1969 | } |
1970 | ||
acf61ecd | 1971 | ret = hclge_tx_buffer_alloc(hdev, pkt_buf); |
46a3df9f S |
1972 | if (ret) { |
1973 | dev_err(&hdev->pdev->dev, | |
1974 | "could not alloc tx buffers %d\n", ret); | |
acf61ecd | 1975 | goto out; |
46a3df9f S |
1976 | } |
1977 | ||
acf61ecd | 1978 | ret = hclge_rx_buffer_calc(hdev, pkt_buf); |
46a3df9f S |
1979 | if (ret) { |
1980 | dev_err(&hdev->pdev->dev, | |
1981 | "could not calc rx priv buffer size for all TCs %d\n", | |
1982 | ret); | |
acf61ecd | 1983 | goto out; |
46a3df9f S |
1984 | } |
1985 | ||
acf61ecd | 1986 | ret = hclge_rx_priv_buf_alloc(hdev, pkt_buf); |
46a3df9f S |
1987 | if (ret) { |
1988 | dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n", | |
1989 | ret); | |
acf61ecd | 1990 | goto out; |
46a3df9f S |
1991 | } |
1992 | ||
2daf4a65 | 1993 | if (hnae3_dev_dcb_supported(hdev)) { |
acf61ecd | 1994 | ret = hclge_rx_priv_wl_config(hdev, pkt_buf); |
2daf4a65 YL |
1995 | if (ret) { |
1996 | dev_err(&hdev->pdev->dev, | |
1997 | "could not configure rx private waterline %d\n", | |
1998 | ret); | |
acf61ecd | 1999 | goto out; |
2daf4a65 | 2000 | } |
46a3df9f | 2001 | |
acf61ecd | 2002 | ret = hclge_common_thrd_config(hdev, pkt_buf); |
2daf4a65 YL |
2003 | if (ret) { |
2004 | dev_err(&hdev->pdev->dev, | |
2005 | "could not configure common threshold %d\n", | |
2006 | ret); | |
acf61ecd | 2007 | goto out; |
2daf4a65 | 2008 | } |
46a3df9f S |
2009 | } |
2010 | ||
acf61ecd YL |
2011 | ret = hclge_common_wl_config(hdev, pkt_buf); |
2012 | if (ret) | |
46a3df9f S |
2013 | dev_err(&hdev->pdev->dev, |
2014 | "could not configure common waterline %d\n", ret); | |
46a3df9f | 2015 | |
acf61ecd YL |
2016 | out: |
2017 | kfree(pkt_buf); | |
2018 | return ret; | |
46a3df9f S |
2019 | } |
2020 | ||
2021 | static int hclge_init_roce_base_info(struct hclge_vport *vport) | |
2022 | { | |
2023 | struct hnae3_handle *roce = &vport->roce; | |
2024 | struct hnae3_handle *nic = &vport->nic; | |
2025 | ||
887c3820 | 2026 | roce->rinfo.num_vectors = vport->back->num_roce_msi; |
46a3df9f S |
2027 | |
2028 | if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors || | |
2029 | vport->back->num_msi_left == 0) | |
2030 | return -EINVAL; | |
2031 | ||
2032 | roce->rinfo.base_vector = vport->back->roce_base_vector; | |
2033 | ||
2034 | roce->rinfo.netdev = nic->kinfo.netdev; | |
2035 | roce->rinfo.roce_io_base = vport->back->hw.io_base; | |
2036 | ||
2037 | roce->pdev = nic->pdev; | |
2038 | roce->ae_algo = nic->ae_algo; | |
2039 | roce->numa_node_mask = nic->numa_node_mask; | |
2040 | ||
2041 | return 0; | |
2042 | } | |
2043 | ||
887c3820 | 2044 | static int hclge_init_msi(struct hclge_dev *hdev) |
46a3df9f S |
2045 | { |
2046 | struct pci_dev *pdev = hdev->pdev; | |
887c3820 SM |
2047 | int vectors; |
2048 | int i; | |
46a3df9f | 2049 | |
887c3820 SM |
2050 | vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, |
2051 | PCI_IRQ_MSI | PCI_IRQ_MSIX); | |
2052 | if (vectors < 0) { | |
2053 | dev_err(&pdev->dev, | |
2054 | "failed(%d) to allocate MSI/MSI-X vectors\n", | |
2055 | vectors); | |
2056 | return vectors; | |
46a3df9f | 2057 | } |
887c3820 SM |
2058 | if (vectors < hdev->num_msi) |
2059 | dev_warn(&hdev->pdev->dev, | |
2060 | "requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", | |
2061 | hdev->num_msi, vectors); | |
46a3df9f | 2062 | |
887c3820 SM |
2063 | hdev->num_msi = vectors; |
2064 | hdev->num_msi_left = vectors; | |
2065 | hdev->base_msi_vector = pdev->irq; | |
46a3df9f S |
2066 | hdev->roce_base_vector = hdev->base_msi_vector + |
2067 | HCLGE_ROCE_VECTOR_OFFSET; | |
2068 | ||
46a3df9f S |
2069 | hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi, |
2070 | sizeof(u16), GFP_KERNEL); | |
887c3820 SM |
2071 | if (!hdev->vector_status) { |
2072 | pci_free_irq_vectors(pdev); | |
46a3df9f | 2073 | return -ENOMEM; |
887c3820 | 2074 | } |
46a3df9f S |
2075 | |
2076 | for (i = 0; i < hdev->num_msi; i++) | |
2077 | hdev->vector_status[i] = HCLGE_INVALID_VPORT; | |
2078 | ||
887c3820 SM |
2079 | hdev->vector_irq = devm_kcalloc(&pdev->dev, hdev->num_msi, |
2080 | sizeof(int), GFP_KERNEL); | |
2081 | if (!hdev->vector_irq) { | |
2082 | pci_free_irq_vectors(pdev); | |
2083 | return -ENOMEM; | |
46a3df9f | 2084 | } |
46a3df9f S |
2085 | |
2086 | return 0; | |
2087 | } | |
2088 | ||
2089 | static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed) | |
2090 | { | |
2091 | struct hclge_mac *mac = &hdev->hw.mac; | |
2092 | ||
2093 | if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M)) | |
2094 | mac->duplex = (u8)duplex; | |
2095 | else | |
2096 | mac->duplex = HCLGE_MAC_FULL; | |
2097 | ||
2098 | mac->speed = speed; | |
2099 | } | |
2100 | ||
2101 | int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex) | |
2102 | { | |
d44f9b63 | 2103 | struct hclge_config_mac_speed_dup_cmd *req; |
46a3df9f S |
2104 | struct hclge_desc desc; |
2105 | int ret; | |
2106 | ||
d44f9b63 | 2107 | req = (struct hclge_config_mac_speed_dup_cmd *)desc.data; |
46a3df9f S |
2108 | |
2109 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false); | |
2110 | ||
e4e87715 | 2111 | hnae3_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex); |
46a3df9f S |
2112 | |
2113 | switch (speed) { | |
2114 | case HCLGE_MAC_SPEED_10M: | |
e4e87715 PL |
2115 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2116 | HCLGE_CFG_SPEED_S, 6); | |
46a3df9f S |
2117 | break; |
2118 | case HCLGE_MAC_SPEED_100M: | |
e4e87715 PL |
2119 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2120 | HCLGE_CFG_SPEED_S, 7); | |
46a3df9f S |
2121 | break; |
2122 | case HCLGE_MAC_SPEED_1G: | |
e4e87715 PL |
2123 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2124 | HCLGE_CFG_SPEED_S, 0); | |
46a3df9f S |
2125 | break; |
2126 | case HCLGE_MAC_SPEED_10G: | |
e4e87715 PL |
2127 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2128 | HCLGE_CFG_SPEED_S, 1); | |
46a3df9f S |
2129 | break; |
2130 | case HCLGE_MAC_SPEED_25G: | |
e4e87715 PL |
2131 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2132 | HCLGE_CFG_SPEED_S, 2); | |
46a3df9f S |
2133 | break; |
2134 | case HCLGE_MAC_SPEED_40G: | |
e4e87715 PL |
2135 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2136 | HCLGE_CFG_SPEED_S, 3); | |
46a3df9f S |
2137 | break; |
2138 | case HCLGE_MAC_SPEED_50G: | |
e4e87715 PL |
2139 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2140 | HCLGE_CFG_SPEED_S, 4); | |
46a3df9f S |
2141 | break; |
2142 | case HCLGE_MAC_SPEED_100G: | |
e4e87715 PL |
2143 | hnae3_set_field(req->speed_dup, HCLGE_CFG_SPEED_M, |
2144 | HCLGE_CFG_SPEED_S, 5); | |
46a3df9f S |
2145 | break; |
2146 | default: | |
d7629e74 | 2147 | dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed); |
46a3df9f S |
2148 | return -EINVAL; |
2149 | } | |
2150 | ||
e4e87715 PL |
2151 | hnae3_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B, |
2152 | 1); | |
46a3df9f S |
2153 | |
2154 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2155 | if (ret) { | |
2156 | dev_err(&hdev->pdev->dev, | |
2157 | "mac speed/duplex config cmd failed %d.\n", ret); | |
2158 | return ret; | |
2159 | } | |
2160 | ||
2161 | hclge_check_speed_dup(hdev, duplex, speed); | |
2162 | ||
2163 | return 0; | |
2164 | } | |
2165 | ||
2166 | static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed, | |
2167 | u8 duplex) | |
2168 | { | |
2169 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2170 | struct hclge_dev *hdev = vport->back; | |
2171 | ||
2172 | return hclge_cfg_mac_speed_dup(hdev, speed, duplex); | |
2173 | } | |
2174 | ||
2175 | static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed, | |
2176 | u8 *duplex) | |
2177 | { | |
d44f9b63 | 2178 | struct hclge_query_an_speed_dup_cmd *req; |
46a3df9f S |
2179 | struct hclge_desc desc; |
2180 | int speed_tmp; | |
2181 | int ret; | |
2182 | ||
d44f9b63 | 2183 | req = (struct hclge_query_an_speed_dup_cmd *)desc.data; |
46a3df9f S |
2184 | |
2185 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true); | |
2186 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2187 | if (ret) { | |
2188 | dev_err(&hdev->pdev->dev, | |
2189 | "mac speed/autoneg/duplex query cmd failed %d\n", | |
2190 | ret); | |
2191 | return ret; | |
2192 | } | |
2193 | ||
e4e87715 PL |
2194 | *duplex = hnae3_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B); |
2195 | speed_tmp = hnae3_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M, | |
2196 | HCLGE_QUERY_SPEED_S); | |
46a3df9f S |
2197 | |
2198 | ret = hclge_parse_speed(speed_tmp, speed); | |
2199 | if (ret) { | |
2200 | dev_err(&hdev->pdev->dev, | |
2201 | "could not parse speed(=%d), %d\n", speed_tmp, ret); | |
2202 | return -EIO; | |
2203 | } | |
2204 | ||
2205 | return 0; | |
2206 | } | |
2207 | ||
46a3df9f S |
2208 | static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable) |
2209 | { | |
d44f9b63 | 2210 | struct hclge_config_auto_neg_cmd *req; |
46a3df9f | 2211 | struct hclge_desc desc; |
a90bb9a5 | 2212 | u32 flag = 0; |
46a3df9f S |
2213 | int ret; |
2214 | ||
2215 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false); | |
2216 | ||
d44f9b63 | 2217 | req = (struct hclge_config_auto_neg_cmd *)desc.data; |
e4e87715 | 2218 | hnae3_set_bit(flag, HCLGE_MAC_CFG_AN_EN_B, !!enable); |
a90bb9a5 | 2219 | req->cfg_an_cmd_flag = cpu_to_le32(flag); |
46a3df9f S |
2220 | |
2221 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2222 | if (ret) { | |
2223 | dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n", | |
2224 | ret); | |
2225 | return ret; | |
2226 | } | |
2227 | ||
2228 | return 0; | |
2229 | } | |
2230 | ||
2231 | static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable) | |
2232 | { | |
2233 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2234 | struct hclge_dev *hdev = vport->back; | |
2235 | ||
2236 | return hclge_set_autoneg_en(hdev, enable); | |
2237 | } | |
2238 | ||
2239 | static int hclge_get_autoneg(struct hnae3_handle *handle) | |
2240 | { | |
2241 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2242 | struct hclge_dev *hdev = vport->back; | |
27b5bf49 FL |
2243 | struct phy_device *phydev = hdev->hw.mac.phydev; |
2244 | ||
2245 | if (phydev) | |
2246 | return phydev->autoneg; | |
46a3df9f S |
2247 | |
2248 | return hdev->hw.mac.autoneg; | |
2249 | } | |
2250 | ||
7564094c PL |
2251 | static int hclge_set_default_mac_vlan_mask(struct hclge_dev *hdev, |
2252 | bool mask_vlan, | |
2253 | u8 *mac_mask) | |
2254 | { | |
2255 | struct hclge_mac_vlan_mask_entry_cmd *req; | |
2256 | struct hclge_desc desc; | |
2257 | int status; | |
2258 | ||
2259 | req = (struct hclge_mac_vlan_mask_entry_cmd *)desc.data; | |
2260 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_MASK_SET, false); | |
2261 | ||
e4e87715 PL |
2262 | hnae3_set_bit(req->vlan_mask, HCLGE_VLAN_MASK_EN_B, |
2263 | mask_vlan ? 1 : 0); | |
7564094c PL |
2264 | ether_addr_copy(req->mac_mask, mac_mask); |
2265 | ||
2266 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2267 | if (status) | |
2268 | dev_err(&hdev->pdev->dev, | |
2269 | "Config mac_vlan_mask failed for cmd_send, ret =%d\n", | |
2270 | status); | |
2271 | ||
2272 | return status; | |
2273 | } | |
2274 | ||
46a3df9f S |
2275 | static int hclge_mac_init(struct hclge_dev *hdev) |
2276 | { | |
f9fd82a9 FL |
2277 | struct hnae3_handle *handle = &hdev->vport[0].nic; |
2278 | struct net_device *netdev = handle->kinfo.netdev; | |
46a3df9f | 2279 | struct hclge_mac *mac = &hdev->hw.mac; |
7564094c | 2280 | u8 mac_mask[ETH_ALEN] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; |
40cca1c5 | 2281 | struct hclge_vport *vport; |
f9fd82a9 | 2282 | int mtu; |
46a3df9f | 2283 | int ret; |
40cca1c5 | 2284 | int i; |
46a3df9f S |
2285 | |
2286 | ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL); | |
2287 | if (ret) { | |
2288 | dev_err(&hdev->pdev->dev, | |
2289 | "Config mac speed dup fail ret=%d\n", ret); | |
2290 | return ret; | |
2291 | } | |
2292 | ||
2293 | mac->link = 0; | |
2294 | ||
46a3df9f | 2295 | /* Initialize the MTA table work mode */ |
46a3df9f S |
2296 | hdev->enable_mta = true; |
2297 | hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36; | |
2298 | ||
2299 | ret = hclge_set_mta_filter_mode(hdev, | |
2300 | hdev->mta_mac_sel_type, | |
2301 | hdev->enable_mta); | |
2302 | if (ret) { | |
2303 | dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n", | |
2304 | ret); | |
2305 | return ret; | |
2306 | } | |
2307 | ||
40cca1c5 XW |
2308 | for (i = 0; i < hdev->num_alloc_vport; i++) { |
2309 | vport = &hdev->vport[i]; | |
2310 | vport->accept_mta_mc = false; | |
2311 | ||
2312 | memset(vport->mta_shadow, 0, sizeof(vport->mta_shadow)); | |
2313 | ret = hclge_cfg_func_mta_filter(hdev, vport->vport_id, false); | |
2314 | if (ret) { | |
2315 | dev_err(&hdev->pdev->dev, | |
2316 | "set mta filter mode fail ret=%d\n", ret); | |
2317 | return ret; | |
2318 | } | |
7564094c PL |
2319 | } |
2320 | ||
2321 | ret = hclge_set_default_mac_vlan_mask(hdev, true, mac_mask); | |
f9fd82a9 | 2322 | if (ret) { |
7564094c PL |
2323 | dev_err(&hdev->pdev->dev, |
2324 | "set default mac_vlan_mask fail ret=%d\n", ret); | |
f9fd82a9 FL |
2325 | return ret; |
2326 | } | |
7564094c | 2327 | |
f9fd82a9 FL |
2328 | if (netdev) |
2329 | mtu = netdev->mtu; | |
2330 | else | |
2331 | mtu = ETH_DATA_LEN; | |
2332 | ||
2333 | ret = hclge_set_mtu(handle, mtu); | |
2334 | if (ret) { | |
2335 | dev_err(&hdev->pdev->dev, | |
2336 | "set mtu failed ret=%d\n", ret); | |
2337 | return ret; | |
2338 | } | |
2339 | ||
2340 | return 0; | |
46a3df9f S |
2341 | } |
2342 | ||
c1a81619 SM |
2343 | static void hclge_mbx_task_schedule(struct hclge_dev *hdev) |
2344 | { | |
2345 | if (!test_and_set_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state)) | |
2346 | schedule_work(&hdev->mbx_service_task); | |
2347 | } | |
2348 | ||
cb1b9f77 SM |
2349 | static void hclge_reset_task_schedule(struct hclge_dev *hdev) |
2350 | { | |
2351 | if (!test_and_set_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state)) | |
2352 | schedule_work(&hdev->rst_service_task); | |
2353 | } | |
2354 | ||
46a3df9f S |
2355 | static void hclge_task_schedule(struct hclge_dev *hdev) |
2356 | { | |
2357 | if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) && | |
2358 | !test_bit(HCLGE_STATE_REMOVING, &hdev->state) && | |
2359 | !test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)) | |
2360 | (void)schedule_work(&hdev->service_task); | |
2361 | } | |
2362 | ||
2363 | static int hclge_get_mac_link_status(struct hclge_dev *hdev) | |
2364 | { | |
d44f9b63 | 2365 | struct hclge_link_status_cmd *req; |
46a3df9f S |
2366 | struct hclge_desc desc; |
2367 | int link_status; | |
2368 | int ret; | |
2369 | ||
2370 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true); | |
2371 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2372 | if (ret) { | |
2373 | dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n", | |
2374 | ret); | |
2375 | return ret; | |
2376 | } | |
2377 | ||
d44f9b63 | 2378 | req = (struct hclge_link_status_cmd *)desc.data; |
46a3df9f S |
2379 | link_status = req->status & HCLGE_LINK_STATUS; |
2380 | ||
2381 | return !!link_status; | |
2382 | } | |
2383 | ||
2384 | static int hclge_get_mac_phy_link(struct hclge_dev *hdev) | |
2385 | { | |
2386 | int mac_state; | |
2387 | int link_stat; | |
2388 | ||
2389 | mac_state = hclge_get_mac_link_status(hdev); | |
2390 | ||
2391 | if (hdev->hw.mac.phydev) { | |
2392 | if (!genphy_read_status(hdev->hw.mac.phydev)) | |
2393 | link_stat = mac_state & | |
2394 | hdev->hw.mac.phydev->link; | |
2395 | else | |
2396 | link_stat = 0; | |
2397 | ||
2398 | } else { | |
2399 | link_stat = mac_state; | |
2400 | } | |
2401 | ||
2402 | return !!link_stat; | |
2403 | } | |
2404 | ||
2405 | static void hclge_update_link_status(struct hclge_dev *hdev) | |
2406 | { | |
2407 | struct hnae3_client *client = hdev->nic_client; | |
2408 | struct hnae3_handle *handle; | |
2409 | int state; | |
2410 | int i; | |
2411 | ||
2412 | if (!client) | |
2413 | return; | |
2414 | state = hclge_get_mac_phy_link(hdev); | |
2415 | if (state != hdev->hw.mac.link) { | |
2416 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { | |
2417 | handle = &hdev->vport[i].nic; | |
2418 | client->ops->link_status_change(handle, state); | |
2419 | } | |
2420 | hdev->hw.mac.link = state; | |
2421 | } | |
2422 | } | |
2423 | ||
2424 | static int hclge_update_speed_duplex(struct hclge_dev *hdev) | |
2425 | { | |
2426 | struct hclge_mac mac = hdev->hw.mac; | |
2427 | u8 duplex; | |
2428 | int speed; | |
2429 | int ret; | |
2430 | ||
2431 | /* get the speed and duplex as autoneg'result from mac cmd when phy | |
2432 | * doesn't exit. | |
2433 | */ | |
c040366b | 2434 | if (mac.phydev || !mac.autoneg) |
46a3df9f S |
2435 | return 0; |
2436 | ||
2437 | ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex); | |
2438 | if (ret) { | |
2439 | dev_err(&hdev->pdev->dev, | |
2440 | "mac autoneg/speed/duplex query failed %d\n", ret); | |
2441 | return ret; | |
2442 | } | |
2443 | ||
2444 | if ((mac.speed != speed) || (mac.duplex != duplex)) { | |
2445 | ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex); | |
2446 | if (ret) { | |
2447 | dev_err(&hdev->pdev->dev, | |
2448 | "mac speed/duplex config failed %d\n", ret); | |
2449 | return ret; | |
2450 | } | |
2451 | } | |
2452 | ||
2453 | return 0; | |
2454 | } | |
2455 | ||
2456 | static int hclge_update_speed_duplex_h(struct hnae3_handle *handle) | |
2457 | { | |
2458 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2459 | struct hclge_dev *hdev = vport->back; | |
2460 | ||
2461 | return hclge_update_speed_duplex(hdev); | |
2462 | } | |
2463 | ||
2464 | static int hclge_get_status(struct hnae3_handle *handle) | |
2465 | { | |
2466 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2467 | struct hclge_dev *hdev = vport->back; | |
2468 | ||
2469 | hclge_update_link_status(hdev); | |
2470 | ||
2471 | return hdev->hw.mac.link; | |
2472 | } | |
2473 | ||
d039ef68 | 2474 | static void hclge_service_timer(struct timer_list *t) |
46a3df9f | 2475 | { |
d039ef68 | 2476 | struct hclge_dev *hdev = from_timer(hdev, t, service_timer); |
46a3df9f | 2477 | |
d039ef68 | 2478 | mod_timer(&hdev->service_timer, jiffies + HZ); |
c5f65480 | 2479 | hdev->hw_stats.stats_timer++; |
46a3df9f S |
2480 | hclge_task_schedule(hdev); |
2481 | } | |
2482 | ||
2483 | static void hclge_service_complete(struct hclge_dev *hdev) | |
2484 | { | |
2485 | WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state)); | |
2486 | ||
2487 | /* Flush memory before next watchdog */ | |
2488 | smp_mb__before_atomic(); | |
2489 | clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); | |
2490 | } | |
2491 | ||
ca1d7669 SM |
2492 | static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) |
2493 | { | |
2494 | u32 rst_src_reg; | |
c1a81619 | 2495 | u32 cmdq_src_reg; |
ca1d7669 SM |
2496 | |
2497 | /* fetch the events from their corresponding regs */ | |
2498 | rst_src_reg = hclge_read_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG); | |
c1a81619 SM |
2499 | cmdq_src_reg = hclge_read_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG); |
2500 | ||
2501 | /* Assumption: If by any chance reset and mailbox events are reported | |
2502 | * together then we will only process reset event in this go and will | |
2503 | * defer the processing of the mailbox events. Since, we would have not | |
2504 | * cleared RX CMDQ event this time we would receive again another | |
2505 | * interrupt from H/W just for the mailbox. | |
2506 | */ | |
ca1d7669 SM |
2507 | |
2508 | /* check for vector0 reset event sources */ | |
2509 | if (BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) & rst_src_reg) { | |
8d40854f | 2510 | set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state); |
ca1d7669 SM |
2511 | set_bit(HNAE3_GLOBAL_RESET, &hdev->reset_pending); |
2512 | *clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); | |
2513 | return HCLGE_VECTOR0_EVENT_RST; | |
2514 | } | |
2515 | ||
2516 | if (BIT(HCLGE_VECTOR0_CORERESET_INT_B) & rst_src_reg) { | |
8d40854f | 2517 | set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state); |
ca1d7669 SM |
2518 | set_bit(HNAE3_CORE_RESET, &hdev->reset_pending); |
2519 | *clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); | |
2520 | return HCLGE_VECTOR0_EVENT_RST; | |
2521 | } | |
2522 | ||
2523 | if (BIT(HCLGE_VECTOR0_IMPRESET_INT_B) & rst_src_reg) { | |
2524 | set_bit(HNAE3_IMP_RESET, &hdev->reset_pending); | |
2525 | *clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); | |
2526 | return HCLGE_VECTOR0_EVENT_RST; | |
2527 | } | |
2528 | ||
c1a81619 SM |
2529 | /* check for vector0 mailbox(=CMDQ RX) event source */ |
2530 | if (BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) { | |
2531 | cmdq_src_reg &= ~BIT(HCLGE_VECTOR0_RX_CMDQ_INT_B); | |
2532 | *clearval = cmdq_src_reg; | |
2533 | return HCLGE_VECTOR0_EVENT_MBX; | |
2534 | } | |
ca1d7669 SM |
2535 | |
2536 | return HCLGE_VECTOR0_EVENT_OTHER; | |
2537 | } | |
2538 | ||
2539 | static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type, | |
2540 | u32 regclr) | |
2541 | { | |
c1a81619 SM |
2542 | switch (event_type) { |
2543 | case HCLGE_VECTOR0_EVENT_RST: | |
ca1d7669 | 2544 | hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr); |
c1a81619 SM |
2545 | break; |
2546 | case HCLGE_VECTOR0_EVENT_MBX: | |
2547 | hclge_write_dev(&hdev->hw, HCLGE_VECTOR0_CMDQ_SRC_REG, regclr); | |
2548 | break; | |
2549 | } | |
ca1d7669 SM |
2550 | } |
2551 | ||
8e52a602 XW |
2552 | static void hclge_clear_all_event_cause(struct hclge_dev *hdev) |
2553 | { | |
2554 | hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_RST, | |
2555 | BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B) | | |
2556 | BIT(HCLGE_VECTOR0_CORERESET_INT_B) | | |
2557 | BIT(HCLGE_VECTOR0_IMPRESET_INT_B)); | |
2558 | hclge_clear_event_cause(hdev, HCLGE_VECTOR0_EVENT_MBX, 0); | |
2559 | } | |
2560 | ||
466b0c00 L |
2561 | static void hclge_enable_vector(struct hclge_misc_vector *vector, bool enable) |
2562 | { | |
2563 | writel(enable ? 1 : 0, vector->addr); | |
2564 | } | |
2565 | ||
2566 | static irqreturn_t hclge_misc_irq_handle(int irq, void *data) | |
2567 | { | |
2568 | struct hclge_dev *hdev = data; | |
ca1d7669 SM |
2569 | u32 event_cause; |
2570 | u32 clearval; | |
466b0c00 L |
2571 | |
2572 | hclge_enable_vector(&hdev->misc_vector, false); | |
ca1d7669 SM |
2573 | event_cause = hclge_check_event_cause(hdev, &clearval); |
2574 | ||
c1a81619 | 2575 | /* vector 0 interrupt is shared with reset and mailbox source events.*/ |
ca1d7669 SM |
2576 | switch (event_cause) { |
2577 | case HCLGE_VECTOR0_EVENT_RST: | |
cb1b9f77 | 2578 | hclge_reset_task_schedule(hdev); |
ca1d7669 | 2579 | break; |
c1a81619 SM |
2580 | case HCLGE_VECTOR0_EVENT_MBX: |
2581 | /* If we are here then, | |
2582 | * 1. Either we are not handling any mbx task and we are not | |
2583 | * scheduled as well | |
2584 | * OR | |
2585 | * 2. We could be handling a mbx task but nothing more is | |
2586 | * scheduled. | |
2587 | * In both cases, we should schedule mbx task as there are more | |
2588 | * mbx messages reported by this interrupt. | |
2589 | */ | |
2590 | hclge_mbx_task_schedule(hdev); | |
f0ad97ac | 2591 | break; |
ca1d7669 | 2592 | default: |
f0ad97ac YL |
2593 | dev_warn(&hdev->pdev->dev, |
2594 | "received unknown or unhandled event of vector0\n"); | |
ca1d7669 SM |
2595 | break; |
2596 | } | |
2597 | ||
cd8c5c26 YL |
2598 | /* clear the source of interrupt if it is not cause by reset */ |
2599 | if (event_cause != HCLGE_VECTOR0_EVENT_RST) { | |
2600 | hclge_clear_event_cause(hdev, event_cause, clearval); | |
2601 | hclge_enable_vector(&hdev->misc_vector, true); | |
2602 | } | |
466b0c00 L |
2603 | |
2604 | return IRQ_HANDLED; | |
2605 | } | |
2606 | ||
2607 | static void hclge_free_vector(struct hclge_dev *hdev, int vector_id) | |
2608 | { | |
36cbbdf6 PL |
2609 | if (hdev->vector_status[vector_id] == HCLGE_INVALID_VPORT) { |
2610 | dev_warn(&hdev->pdev->dev, | |
2611 | "vector(vector_id %d) has been freed.\n", vector_id); | |
2612 | return; | |
2613 | } | |
2614 | ||
466b0c00 L |
2615 | hdev->vector_status[vector_id] = HCLGE_INVALID_VPORT; |
2616 | hdev->num_msi_left += 1; | |
2617 | hdev->num_msi_used -= 1; | |
2618 | } | |
2619 | ||
2620 | static void hclge_get_misc_vector(struct hclge_dev *hdev) | |
2621 | { | |
2622 | struct hclge_misc_vector *vector = &hdev->misc_vector; | |
2623 | ||
2624 | vector->vector_irq = pci_irq_vector(hdev->pdev, 0); | |
2625 | ||
2626 | vector->addr = hdev->hw.io_base + HCLGE_MISC_VECTOR_REG_BASE; | |
2627 | hdev->vector_status[0] = 0; | |
2628 | ||
2629 | hdev->num_msi_left -= 1; | |
2630 | hdev->num_msi_used += 1; | |
2631 | } | |
2632 | ||
2633 | static int hclge_misc_irq_init(struct hclge_dev *hdev) | |
2634 | { | |
2635 | int ret; | |
2636 | ||
2637 | hclge_get_misc_vector(hdev); | |
2638 | ||
ca1d7669 SM |
2639 | /* this would be explicitly freed in the end */ |
2640 | ret = request_irq(hdev->misc_vector.vector_irq, hclge_misc_irq_handle, | |
2641 | 0, "hclge_misc", hdev); | |
466b0c00 L |
2642 | if (ret) { |
2643 | hclge_free_vector(hdev, 0); | |
2644 | dev_err(&hdev->pdev->dev, "request misc irq(%d) fail\n", | |
2645 | hdev->misc_vector.vector_irq); | |
2646 | } | |
2647 | ||
2648 | return ret; | |
2649 | } | |
2650 | ||
ca1d7669 SM |
2651 | static void hclge_misc_irq_uninit(struct hclge_dev *hdev) |
2652 | { | |
2653 | free_irq(hdev->misc_vector.vector_irq, hdev); | |
2654 | hclge_free_vector(hdev, 0); | |
2655 | } | |
2656 | ||
4ed340ab L |
2657 | static int hclge_notify_client(struct hclge_dev *hdev, |
2658 | enum hnae3_reset_notify_type type) | |
2659 | { | |
2660 | struct hnae3_client *client = hdev->nic_client; | |
2661 | u16 i; | |
2662 | ||
2663 | if (!client->ops->reset_notify) | |
2664 | return -EOPNOTSUPP; | |
2665 | ||
2666 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { | |
2667 | struct hnae3_handle *handle = &hdev->vport[i].nic; | |
2668 | int ret; | |
2669 | ||
2670 | ret = client->ops->reset_notify(handle, type); | |
2671 | if (ret) | |
2672 | return ret; | |
2673 | } | |
2674 | ||
2675 | return 0; | |
2676 | } | |
2677 | ||
2678 | static int hclge_reset_wait(struct hclge_dev *hdev) | |
2679 | { | |
2680 | #define HCLGE_RESET_WATI_MS 100 | |
2681 | #define HCLGE_RESET_WAIT_CNT 5 | |
2682 | u32 val, reg, reg_bit; | |
2683 | u32 cnt = 0; | |
2684 | ||
2685 | switch (hdev->reset_type) { | |
2686 | case HNAE3_GLOBAL_RESET: | |
2687 | reg = HCLGE_GLOBAL_RESET_REG; | |
2688 | reg_bit = HCLGE_GLOBAL_RESET_BIT; | |
2689 | break; | |
2690 | case HNAE3_CORE_RESET: | |
2691 | reg = HCLGE_GLOBAL_RESET_REG; | |
2692 | reg_bit = HCLGE_CORE_RESET_BIT; | |
2693 | break; | |
2694 | case HNAE3_FUNC_RESET: | |
2695 | reg = HCLGE_FUN_RST_ING; | |
2696 | reg_bit = HCLGE_FUN_RST_ING_B; | |
2697 | break; | |
2698 | default: | |
2699 | dev_err(&hdev->pdev->dev, | |
2700 | "Wait for unsupported reset type: %d\n", | |
2701 | hdev->reset_type); | |
2702 | return -EINVAL; | |
2703 | } | |
2704 | ||
2705 | val = hclge_read_dev(&hdev->hw, reg); | |
e4e87715 | 2706 | while (hnae3_get_bit(val, reg_bit) && cnt < HCLGE_RESET_WAIT_CNT) { |
4ed340ab L |
2707 | msleep(HCLGE_RESET_WATI_MS); |
2708 | val = hclge_read_dev(&hdev->hw, reg); | |
2709 | cnt++; | |
2710 | } | |
2711 | ||
4ed340ab L |
2712 | if (cnt >= HCLGE_RESET_WAIT_CNT) { |
2713 | dev_warn(&hdev->pdev->dev, | |
2714 | "Wait for reset timeout: %d\n", hdev->reset_type); | |
2715 | return -EBUSY; | |
2716 | } | |
2717 | ||
2718 | return 0; | |
2719 | } | |
2720 | ||
2bfbd35d | 2721 | int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id) |
4ed340ab L |
2722 | { |
2723 | struct hclge_desc desc; | |
2724 | struct hclge_reset_cmd *req = (struct hclge_reset_cmd *)desc.data; | |
2725 | int ret; | |
2726 | ||
2727 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_RST_TRIGGER, false); | |
e4e87715 | 2728 | hnae3_set_bit(req->mac_func_reset, HCLGE_CFG_RESET_FUNC_B, 1); |
4ed340ab L |
2729 | req->fun_reset_vfid = func_id; |
2730 | ||
2731 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
2732 | if (ret) | |
2733 | dev_err(&hdev->pdev->dev, | |
2734 | "send function reset cmd fail, status =%d\n", ret); | |
2735 | ||
2736 | return ret; | |
2737 | } | |
2738 | ||
f2f432f2 | 2739 | static void hclge_do_reset(struct hclge_dev *hdev) |
4ed340ab L |
2740 | { |
2741 | struct pci_dev *pdev = hdev->pdev; | |
2742 | u32 val; | |
2743 | ||
f2f432f2 | 2744 | switch (hdev->reset_type) { |
4ed340ab L |
2745 | case HNAE3_GLOBAL_RESET: |
2746 | val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); | |
e4e87715 | 2747 | hnae3_set_bit(val, HCLGE_GLOBAL_RESET_BIT, 1); |
4ed340ab L |
2748 | hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); |
2749 | dev_info(&pdev->dev, "Global Reset requested\n"); | |
2750 | break; | |
2751 | case HNAE3_CORE_RESET: | |
2752 | val = hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG); | |
e4e87715 | 2753 | hnae3_set_bit(val, HCLGE_CORE_RESET_BIT, 1); |
4ed340ab L |
2754 | hclge_write_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG, val); |
2755 | dev_info(&pdev->dev, "Core Reset requested\n"); | |
2756 | break; | |
2757 | case HNAE3_FUNC_RESET: | |
2758 | dev_info(&pdev->dev, "PF Reset requested\n"); | |
2759 | hclge_func_reset_cmd(hdev, 0); | |
cb1b9f77 SM |
2760 | /* schedule again to check later */ |
2761 | set_bit(HNAE3_FUNC_RESET, &hdev->reset_pending); | |
2762 | hclge_reset_task_schedule(hdev); | |
4ed340ab L |
2763 | break; |
2764 | default: | |
2765 | dev_warn(&pdev->dev, | |
f2f432f2 | 2766 | "Unsupported reset type: %d\n", hdev->reset_type); |
4ed340ab L |
2767 | break; |
2768 | } | |
2769 | } | |
2770 | ||
f2f432f2 SM |
2771 | static enum hnae3_reset_type hclge_get_reset_level(struct hclge_dev *hdev, |
2772 | unsigned long *addr) | |
2773 | { | |
2774 | enum hnae3_reset_type rst_level = HNAE3_NONE_RESET; | |
2775 | ||
2776 | /* return the highest priority reset level amongst all */ | |
2777 | if (test_bit(HNAE3_GLOBAL_RESET, addr)) | |
2778 | rst_level = HNAE3_GLOBAL_RESET; | |
2779 | else if (test_bit(HNAE3_CORE_RESET, addr)) | |
2780 | rst_level = HNAE3_CORE_RESET; | |
2781 | else if (test_bit(HNAE3_IMP_RESET, addr)) | |
2782 | rst_level = HNAE3_IMP_RESET; | |
2783 | else if (test_bit(HNAE3_FUNC_RESET, addr)) | |
2784 | rst_level = HNAE3_FUNC_RESET; | |
2785 | ||
2786 | /* now, clear all other resets */ | |
2787 | clear_bit(HNAE3_GLOBAL_RESET, addr); | |
2788 | clear_bit(HNAE3_CORE_RESET, addr); | |
2789 | clear_bit(HNAE3_IMP_RESET, addr); | |
2790 | clear_bit(HNAE3_FUNC_RESET, addr); | |
2791 | ||
2792 | return rst_level; | |
2793 | } | |
2794 | ||
cd8c5c26 YL |
2795 | static void hclge_clear_reset_cause(struct hclge_dev *hdev) |
2796 | { | |
2797 | u32 clearval = 0; | |
2798 | ||
2799 | switch (hdev->reset_type) { | |
2800 | case HNAE3_IMP_RESET: | |
2801 | clearval = BIT(HCLGE_VECTOR0_IMPRESET_INT_B); | |
2802 | break; | |
2803 | case HNAE3_GLOBAL_RESET: | |
2804 | clearval = BIT(HCLGE_VECTOR0_GLOBALRESET_INT_B); | |
2805 | break; | |
2806 | case HNAE3_CORE_RESET: | |
2807 | clearval = BIT(HCLGE_VECTOR0_CORERESET_INT_B); | |
2808 | break; | |
2809 | default: | |
cd8c5c26 YL |
2810 | break; |
2811 | } | |
2812 | ||
2813 | if (!clearval) | |
2814 | return; | |
2815 | ||
2816 | hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, clearval); | |
2817 | hclge_enable_vector(&hdev->misc_vector, true); | |
2818 | } | |
2819 | ||
f2f432f2 SM |
2820 | static void hclge_reset(struct hclge_dev *hdev) |
2821 | { | |
2822 | /* perform reset of the stack & ae device for a client */ | |
6d4fab39 | 2823 | rtnl_lock(); |
f2f432f2 SM |
2824 | hclge_notify_client(hdev, HNAE3_DOWN_CLIENT); |
2825 | ||
2826 | if (!hclge_reset_wait(hdev)) { | |
f2f432f2 SM |
2827 | hclge_notify_client(hdev, HNAE3_UNINIT_CLIENT); |
2828 | hclge_reset_ae_dev(hdev->ae_dev); | |
2829 | hclge_notify_client(hdev, HNAE3_INIT_CLIENT); | |
cd8c5c26 YL |
2830 | |
2831 | hclge_clear_reset_cause(hdev); | |
f2f432f2 SM |
2832 | } else { |
2833 | /* schedule again to check pending resets later */ | |
2834 | set_bit(hdev->reset_type, &hdev->reset_pending); | |
2835 | hclge_reset_task_schedule(hdev); | |
2836 | } | |
2837 | ||
2838 | hclge_notify_client(hdev, HNAE3_UP_CLIENT); | |
6d4fab39 | 2839 | rtnl_unlock(); |
f2f432f2 SM |
2840 | } |
2841 | ||
6d4c3981 | 2842 | static void hclge_reset_event(struct hnae3_handle *handle) |
4ed340ab L |
2843 | { |
2844 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2845 | struct hclge_dev *hdev = vport->back; | |
2846 | ||
6d4c3981 SM |
2847 | /* check if this is a new reset request and we are not here just because |
2848 | * last reset attempt did not succeed and watchdog hit us again. We will | |
2849 | * know this if last reset request did not occur very recently (watchdog | |
2850 | * timer = 5*HZ, let us check after sufficiently large time, say 4*5*Hz) | |
2851 | * In case of new request we reset the "reset level" to PF reset. | |
2852 | */ | |
2853 | if (time_after(jiffies, (handle->last_reset_time + 4 * 5 * HZ))) | |
2854 | handle->reset_level = HNAE3_FUNC_RESET; | |
4ed340ab | 2855 | |
6d4c3981 SM |
2856 | dev_info(&hdev->pdev->dev, "received reset event , reset type is %d", |
2857 | handle->reset_level); | |
2858 | ||
2859 | /* request reset & schedule reset task */ | |
2860 | set_bit(handle->reset_level, &hdev->reset_request); | |
2861 | hclge_reset_task_schedule(hdev); | |
2862 | ||
2863 | if (handle->reset_level < HNAE3_GLOBAL_RESET) | |
2864 | handle->reset_level++; | |
2865 | ||
2866 | handle->last_reset_time = jiffies; | |
4ed340ab L |
2867 | } |
2868 | ||
2869 | static void hclge_reset_subtask(struct hclge_dev *hdev) | |
2870 | { | |
f2f432f2 SM |
2871 | /* check if there is any ongoing reset in the hardware. This status can |
2872 | * be checked from reset_pending. If there is then, we need to wait for | |
2873 | * hardware to complete reset. | |
2874 | * a. If we are able to figure out in reasonable time that hardware | |
2875 | * has fully resetted then, we can proceed with driver, client | |
2876 | * reset. | |
2877 | * b. else, we can come back later to check this status so re-sched | |
2878 | * now. | |
2879 | */ | |
2880 | hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_pending); | |
2881 | if (hdev->reset_type != HNAE3_NONE_RESET) | |
2882 | hclge_reset(hdev); | |
4ed340ab | 2883 | |
f2f432f2 SM |
2884 | /* check if we got any *new* reset requests to be honored */ |
2885 | hdev->reset_type = hclge_get_reset_level(hdev, &hdev->reset_request); | |
2886 | if (hdev->reset_type != HNAE3_NONE_RESET) | |
2887 | hclge_do_reset(hdev); | |
4ed340ab | 2888 | |
4ed340ab L |
2889 | hdev->reset_type = HNAE3_NONE_RESET; |
2890 | } | |
2891 | ||
cb1b9f77 | 2892 | static void hclge_reset_service_task(struct work_struct *work) |
466b0c00 | 2893 | { |
cb1b9f77 SM |
2894 | struct hclge_dev *hdev = |
2895 | container_of(work, struct hclge_dev, rst_service_task); | |
2896 | ||
2897 | if (test_and_set_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) | |
2898 | return; | |
2899 | ||
2900 | clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); | |
2901 | ||
4ed340ab | 2902 | hclge_reset_subtask(hdev); |
cb1b9f77 SM |
2903 | |
2904 | clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); | |
466b0c00 L |
2905 | } |
2906 | ||
c1a81619 SM |
2907 | static void hclge_mailbox_service_task(struct work_struct *work) |
2908 | { | |
2909 | struct hclge_dev *hdev = | |
2910 | container_of(work, struct hclge_dev, mbx_service_task); | |
2911 | ||
2912 | if (test_and_set_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state)) | |
2913 | return; | |
2914 | ||
2915 | clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); | |
2916 | ||
2917 | hclge_mbx_handler(hdev); | |
2918 | ||
2919 | clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); | |
2920 | } | |
2921 | ||
46a3df9f S |
2922 | static void hclge_service_task(struct work_struct *work) |
2923 | { | |
2924 | struct hclge_dev *hdev = | |
2925 | container_of(work, struct hclge_dev, service_task); | |
2926 | ||
c5f65480 JS |
2927 | if (hdev->hw_stats.stats_timer >= HCLGE_STATS_TIMER_INTERVAL) { |
2928 | hclge_update_stats_for_all(hdev); | |
2929 | hdev->hw_stats.stats_timer = 0; | |
2930 | } | |
2931 | ||
46a3df9f S |
2932 | hclge_update_speed_duplex(hdev); |
2933 | hclge_update_link_status(hdev); | |
46a3df9f S |
2934 | hclge_service_complete(hdev); |
2935 | } | |
2936 | ||
46a3df9f S |
2937 | struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle) |
2938 | { | |
2939 | /* VF handle has no client */ | |
2940 | if (!handle->client) | |
2941 | return container_of(handle, struct hclge_vport, nic); | |
2942 | else if (handle->client->type == HNAE3_CLIENT_ROCE) | |
2943 | return container_of(handle, struct hclge_vport, roce); | |
2944 | else | |
2945 | return container_of(handle, struct hclge_vport, nic); | |
2946 | } | |
2947 | ||
2948 | static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num, | |
2949 | struct hnae3_vector_info *vector_info) | |
2950 | { | |
2951 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2952 | struct hnae3_vector_info *vector = vector_info; | |
2953 | struct hclge_dev *hdev = vport->back; | |
2954 | int alloc = 0; | |
2955 | int i, j; | |
2956 | ||
2957 | vector_num = min(hdev->num_msi_left, vector_num); | |
2958 | ||
2959 | for (j = 0; j < vector_num; j++) { | |
2960 | for (i = 1; i < hdev->num_msi; i++) { | |
2961 | if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) { | |
2962 | vector->vector = pci_irq_vector(hdev->pdev, i); | |
2963 | vector->io_addr = hdev->hw.io_base + | |
2964 | HCLGE_VECTOR_REG_BASE + | |
2965 | (i - 1) * HCLGE_VECTOR_REG_OFFSET + | |
2966 | vport->vport_id * | |
2967 | HCLGE_VECTOR_VF_OFFSET; | |
2968 | hdev->vector_status[i] = vport->vport_id; | |
887c3820 | 2969 | hdev->vector_irq[i] = vector->vector; |
46a3df9f S |
2970 | |
2971 | vector++; | |
2972 | alloc++; | |
2973 | ||
2974 | break; | |
2975 | } | |
2976 | } | |
2977 | } | |
2978 | hdev->num_msi_left -= alloc; | |
2979 | hdev->num_msi_used += alloc; | |
2980 | ||
2981 | return alloc; | |
2982 | } | |
2983 | ||
2984 | static int hclge_get_vector_index(struct hclge_dev *hdev, int vector) | |
2985 | { | |
2986 | int i; | |
2987 | ||
887c3820 SM |
2988 | for (i = 0; i < hdev->num_msi; i++) |
2989 | if (vector == hdev->vector_irq[i]) | |
2990 | return i; | |
2991 | ||
46a3df9f S |
2992 | return -EINVAL; |
2993 | } | |
2994 | ||
0d3e6631 YL |
2995 | static int hclge_put_vector(struct hnae3_handle *handle, int vector) |
2996 | { | |
2997 | struct hclge_vport *vport = hclge_get_vport(handle); | |
2998 | struct hclge_dev *hdev = vport->back; | |
2999 | int vector_id; | |
3000 | ||
3001 | vector_id = hclge_get_vector_index(hdev, vector); | |
3002 | if (vector_id < 0) { | |
3003 | dev_err(&hdev->pdev->dev, | |
3004 | "Get vector index fail. vector_id =%d\n", vector_id); | |
3005 | return vector_id; | |
3006 | } | |
3007 | ||
3008 | hclge_free_vector(hdev, vector_id); | |
3009 | ||
3010 | return 0; | |
3011 | } | |
3012 | ||
46a3df9f S |
3013 | static u32 hclge_get_rss_key_size(struct hnae3_handle *handle) |
3014 | { | |
3015 | return HCLGE_RSS_KEY_SIZE; | |
3016 | } | |
3017 | ||
3018 | static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle) | |
3019 | { | |
3020 | return HCLGE_RSS_IND_TBL_SIZE; | |
3021 | } | |
3022 | ||
46a3df9f S |
3023 | static int hclge_set_rss_algo_key(struct hclge_dev *hdev, |
3024 | const u8 hfunc, const u8 *key) | |
3025 | { | |
d44f9b63 | 3026 | struct hclge_rss_config_cmd *req; |
46a3df9f S |
3027 | struct hclge_desc desc; |
3028 | int key_offset; | |
3029 | int key_size; | |
3030 | int ret; | |
3031 | ||
d44f9b63 | 3032 | req = (struct hclge_rss_config_cmd *)desc.data; |
46a3df9f S |
3033 | |
3034 | for (key_offset = 0; key_offset < 3; key_offset++) { | |
3035 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, | |
3036 | false); | |
3037 | ||
3038 | req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK); | |
3039 | req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B); | |
3040 | ||
3041 | if (key_offset == 2) | |
3042 | key_size = | |
3043 | HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2; | |
3044 | else | |
3045 | key_size = HCLGE_RSS_HASH_KEY_NUM; | |
3046 | ||
3047 | memcpy(req->hash_key, | |
3048 | key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size); | |
3049 | ||
3050 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3051 | if (ret) { | |
3052 | dev_err(&hdev->pdev->dev, | |
3053 | "Configure RSS config fail, status = %d\n", | |
3054 | ret); | |
3055 | return ret; | |
3056 | } | |
3057 | } | |
3058 | return 0; | |
3059 | } | |
3060 | ||
89523cfa | 3061 | static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u8 *indir) |
46a3df9f | 3062 | { |
d44f9b63 | 3063 | struct hclge_rss_indirection_table_cmd *req; |
46a3df9f S |
3064 | struct hclge_desc desc; |
3065 | int i, j; | |
3066 | int ret; | |
3067 | ||
d44f9b63 | 3068 | req = (struct hclge_rss_indirection_table_cmd *)desc.data; |
46a3df9f S |
3069 | |
3070 | for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) { | |
3071 | hclge_cmd_setup_basic_desc | |
3072 | (&desc, HCLGE_OPC_RSS_INDIR_TABLE, false); | |
3073 | ||
a90bb9a5 YL |
3074 | req->start_table_index = |
3075 | cpu_to_le16(i * HCLGE_RSS_CFG_TBL_SIZE); | |
3076 | req->rss_set_bitmap = cpu_to_le16(HCLGE_RSS_SET_BITMAP_MSK); | |
46a3df9f S |
3077 | |
3078 | for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++) | |
3079 | req->rss_result[j] = | |
3080 | indir[i * HCLGE_RSS_CFG_TBL_SIZE + j]; | |
3081 | ||
3082 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3083 | if (ret) { | |
3084 | dev_err(&hdev->pdev->dev, | |
3085 | "Configure rss indir table fail,status = %d\n", | |
3086 | ret); | |
3087 | return ret; | |
3088 | } | |
3089 | } | |
3090 | return 0; | |
3091 | } | |
3092 | ||
3093 | static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid, | |
3094 | u16 *tc_size, u16 *tc_offset) | |
3095 | { | |
d44f9b63 | 3096 | struct hclge_rss_tc_mode_cmd *req; |
46a3df9f S |
3097 | struct hclge_desc desc; |
3098 | int ret; | |
3099 | int i; | |
3100 | ||
3101 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false); | |
d44f9b63 | 3102 | req = (struct hclge_rss_tc_mode_cmd *)desc.data; |
46a3df9f S |
3103 | |
3104 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
a90bb9a5 YL |
3105 | u16 mode = 0; |
3106 | ||
e4e87715 PL |
3107 | hnae3_set_bit(mode, HCLGE_RSS_TC_VALID_B, (tc_valid[i] & 0x1)); |
3108 | hnae3_set_field(mode, HCLGE_RSS_TC_SIZE_M, | |
3109 | HCLGE_RSS_TC_SIZE_S, tc_size[i]); | |
3110 | hnae3_set_field(mode, HCLGE_RSS_TC_OFFSET_M, | |
3111 | HCLGE_RSS_TC_OFFSET_S, tc_offset[i]); | |
a90bb9a5 YL |
3112 | |
3113 | req->rss_tc_mode[i] = cpu_to_le16(mode); | |
46a3df9f S |
3114 | } |
3115 | ||
3116 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3117 | if (ret) { | |
3118 | dev_err(&hdev->pdev->dev, | |
3119 | "Configure rss tc mode fail, status = %d\n", ret); | |
3120 | return ret; | |
3121 | } | |
3122 | ||
3123 | return 0; | |
3124 | } | |
3125 | ||
3126 | static int hclge_set_rss_input_tuple(struct hclge_dev *hdev) | |
3127 | { | |
d44f9b63 | 3128 | struct hclge_rss_input_tuple_cmd *req; |
46a3df9f S |
3129 | struct hclge_desc desc; |
3130 | int ret; | |
3131 | ||
3132 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); | |
3133 | ||
d44f9b63 | 3134 | req = (struct hclge_rss_input_tuple_cmd *)desc.data; |
6f2af429 YL |
3135 | |
3136 | /* Get the tuple cfg from pf */ | |
3137 | req->ipv4_tcp_en = hdev->vport[0].rss_tuple_sets.ipv4_tcp_en; | |
3138 | req->ipv4_udp_en = hdev->vport[0].rss_tuple_sets.ipv4_udp_en; | |
3139 | req->ipv4_sctp_en = hdev->vport[0].rss_tuple_sets.ipv4_sctp_en; | |
3140 | req->ipv4_fragment_en = hdev->vport[0].rss_tuple_sets.ipv4_fragment_en; | |
3141 | req->ipv6_tcp_en = hdev->vport[0].rss_tuple_sets.ipv6_tcp_en; | |
3142 | req->ipv6_udp_en = hdev->vport[0].rss_tuple_sets.ipv6_udp_en; | |
3143 | req->ipv6_sctp_en = hdev->vport[0].rss_tuple_sets.ipv6_sctp_en; | |
3144 | req->ipv6_fragment_en = hdev->vport[0].rss_tuple_sets.ipv6_fragment_en; | |
46a3df9f S |
3145 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
3146 | if (ret) { | |
3147 | dev_err(&hdev->pdev->dev, | |
3148 | "Configure rss input fail, status = %d\n", ret); | |
3149 | return ret; | |
3150 | } | |
3151 | ||
3152 | return 0; | |
3153 | } | |
3154 | ||
3155 | static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir, | |
3156 | u8 *key, u8 *hfunc) | |
3157 | { | |
3158 | struct hclge_vport *vport = hclge_get_vport(handle); | |
46a3df9f S |
3159 | int i; |
3160 | ||
3161 | /* Get hash algorithm */ | |
3162 | if (hfunc) | |
89523cfa | 3163 | *hfunc = vport->rss_algo; |
46a3df9f S |
3164 | |
3165 | /* Get the RSS Key required by the user */ | |
3166 | if (key) | |
3167 | memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE); | |
3168 | ||
3169 | /* Get indirect table */ | |
3170 | if (indir) | |
3171 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) | |
3172 | indir[i] = vport->rss_indirection_tbl[i]; | |
3173 | ||
3174 | return 0; | |
3175 | } | |
3176 | ||
3177 | static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir, | |
3178 | const u8 *key, const u8 hfunc) | |
3179 | { | |
3180 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3181 | struct hclge_dev *hdev = vport->back; | |
3182 | u8 hash_algo; | |
3183 | int ret, i; | |
3184 | ||
3185 | /* Set the RSS Hash Key if specififed by the user */ | |
3186 | if (key) { | |
46a3df9f S |
3187 | |
3188 | if (hfunc == ETH_RSS_HASH_TOP || | |
3189 | hfunc == ETH_RSS_HASH_NO_CHANGE) | |
3190 | hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; | |
3191 | else | |
3192 | return -EINVAL; | |
3193 | ret = hclge_set_rss_algo_key(hdev, hash_algo, key); | |
3194 | if (ret) | |
3195 | return ret; | |
89523cfa YL |
3196 | |
3197 | /* Update the shadow RSS key with user specified qids */ | |
3198 | memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE); | |
3199 | vport->rss_algo = hash_algo; | |
46a3df9f S |
3200 | } |
3201 | ||
3202 | /* Update the shadow RSS table with user specified qids */ | |
3203 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) | |
3204 | vport->rss_indirection_tbl[i] = indir[i]; | |
3205 | ||
3206 | /* Update the hardware */ | |
89523cfa | 3207 | return hclge_set_rss_indir_table(hdev, vport->rss_indirection_tbl); |
46a3df9f S |
3208 | } |
3209 | ||
f7db940a L |
3210 | static u8 hclge_get_rss_hash_bits(struct ethtool_rxnfc *nfc) |
3211 | { | |
3212 | u8 hash_sets = nfc->data & RXH_L4_B_0_1 ? HCLGE_S_PORT_BIT : 0; | |
3213 | ||
3214 | if (nfc->data & RXH_L4_B_2_3) | |
3215 | hash_sets |= HCLGE_D_PORT_BIT; | |
3216 | else | |
3217 | hash_sets &= ~HCLGE_D_PORT_BIT; | |
3218 | ||
3219 | if (nfc->data & RXH_IP_SRC) | |
3220 | hash_sets |= HCLGE_S_IP_BIT; | |
3221 | else | |
3222 | hash_sets &= ~HCLGE_S_IP_BIT; | |
3223 | ||
3224 | if (nfc->data & RXH_IP_DST) | |
3225 | hash_sets |= HCLGE_D_IP_BIT; | |
3226 | else | |
3227 | hash_sets &= ~HCLGE_D_IP_BIT; | |
3228 | ||
3229 | if (nfc->flow_type == SCTP_V4_FLOW || nfc->flow_type == SCTP_V6_FLOW) | |
3230 | hash_sets |= HCLGE_V_TAG_BIT; | |
3231 | ||
3232 | return hash_sets; | |
3233 | } | |
3234 | ||
3235 | static int hclge_set_rss_tuple(struct hnae3_handle *handle, | |
3236 | struct ethtool_rxnfc *nfc) | |
3237 | { | |
3238 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3239 | struct hclge_dev *hdev = vport->back; | |
3240 | struct hclge_rss_input_tuple_cmd *req; | |
3241 | struct hclge_desc desc; | |
3242 | u8 tuple_sets; | |
3243 | int ret; | |
3244 | ||
3245 | if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | | |
3246 | RXH_L4_B_0_1 | RXH_L4_B_2_3)) | |
3247 | return -EINVAL; | |
3248 | ||
3249 | req = (struct hclge_rss_input_tuple_cmd *)desc.data; | |
6f2af429 | 3250 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false); |
f7db940a | 3251 | |
6f2af429 YL |
3252 | req->ipv4_tcp_en = vport->rss_tuple_sets.ipv4_tcp_en; |
3253 | req->ipv4_udp_en = vport->rss_tuple_sets.ipv4_udp_en; | |
3254 | req->ipv4_sctp_en = vport->rss_tuple_sets.ipv4_sctp_en; | |
3255 | req->ipv4_fragment_en = vport->rss_tuple_sets.ipv4_fragment_en; | |
3256 | req->ipv6_tcp_en = vport->rss_tuple_sets.ipv6_tcp_en; | |
3257 | req->ipv6_udp_en = vport->rss_tuple_sets.ipv6_udp_en; | |
3258 | req->ipv6_sctp_en = vport->rss_tuple_sets.ipv6_sctp_en; | |
3259 | req->ipv6_fragment_en = vport->rss_tuple_sets.ipv6_fragment_en; | |
f7db940a L |
3260 | |
3261 | tuple_sets = hclge_get_rss_hash_bits(nfc); | |
3262 | switch (nfc->flow_type) { | |
3263 | case TCP_V4_FLOW: | |
3264 | req->ipv4_tcp_en = tuple_sets; | |
3265 | break; | |
3266 | case TCP_V6_FLOW: | |
3267 | req->ipv6_tcp_en = tuple_sets; | |
3268 | break; | |
3269 | case UDP_V4_FLOW: | |
3270 | req->ipv4_udp_en = tuple_sets; | |
3271 | break; | |
3272 | case UDP_V6_FLOW: | |
3273 | req->ipv6_udp_en = tuple_sets; | |
3274 | break; | |
3275 | case SCTP_V4_FLOW: | |
3276 | req->ipv4_sctp_en = tuple_sets; | |
3277 | break; | |
3278 | case SCTP_V6_FLOW: | |
3279 | if ((nfc->data & RXH_L4_B_0_1) || | |
3280 | (nfc->data & RXH_L4_B_2_3)) | |
3281 | return -EINVAL; | |
3282 | ||
3283 | req->ipv6_sctp_en = tuple_sets; | |
3284 | break; | |
3285 | case IPV4_FLOW: | |
3286 | req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3287 | break; | |
3288 | case IPV6_FLOW: | |
3289 | req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3290 | break; | |
3291 | default: | |
3292 | return -EINVAL; | |
3293 | } | |
3294 | ||
3295 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
6f2af429 | 3296 | if (ret) { |
f7db940a L |
3297 | dev_err(&hdev->pdev->dev, |
3298 | "Set rss tuple fail, status = %d\n", ret); | |
6f2af429 YL |
3299 | return ret; |
3300 | } | |
f7db940a | 3301 | |
6f2af429 YL |
3302 | vport->rss_tuple_sets.ipv4_tcp_en = req->ipv4_tcp_en; |
3303 | vport->rss_tuple_sets.ipv4_udp_en = req->ipv4_udp_en; | |
3304 | vport->rss_tuple_sets.ipv4_sctp_en = req->ipv4_sctp_en; | |
3305 | vport->rss_tuple_sets.ipv4_fragment_en = req->ipv4_fragment_en; | |
3306 | vport->rss_tuple_sets.ipv6_tcp_en = req->ipv6_tcp_en; | |
3307 | vport->rss_tuple_sets.ipv6_udp_en = req->ipv6_udp_en; | |
3308 | vport->rss_tuple_sets.ipv6_sctp_en = req->ipv6_sctp_en; | |
3309 | vport->rss_tuple_sets.ipv6_fragment_en = req->ipv6_fragment_en; | |
3310 | return 0; | |
f7db940a L |
3311 | } |
3312 | ||
07d29954 L |
3313 | static int hclge_get_rss_tuple(struct hnae3_handle *handle, |
3314 | struct ethtool_rxnfc *nfc) | |
3315 | { | |
3316 | struct hclge_vport *vport = hclge_get_vport(handle); | |
07d29954 | 3317 | u8 tuple_sets; |
07d29954 L |
3318 | |
3319 | nfc->data = 0; | |
3320 | ||
07d29954 L |
3321 | switch (nfc->flow_type) { |
3322 | case TCP_V4_FLOW: | |
6f2af429 | 3323 | tuple_sets = vport->rss_tuple_sets.ipv4_tcp_en; |
07d29954 L |
3324 | break; |
3325 | case UDP_V4_FLOW: | |
6f2af429 | 3326 | tuple_sets = vport->rss_tuple_sets.ipv4_udp_en; |
07d29954 L |
3327 | break; |
3328 | case TCP_V6_FLOW: | |
6f2af429 | 3329 | tuple_sets = vport->rss_tuple_sets.ipv6_tcp_en; |
07d29954 L |
3330 | break; |
3331 | case UDP_V6_FLOW: | |
6f2af429 | 3332 | tuple_sets = vport->rss_tuple_sets.ipv6_udp_en; |
07d29954 L |
3333 | break; |
3334 | case SCTP_V4_FLOW: | |
6f2af429 | 3335 | tuple_sets = vport->rss_tuple_sets.ipv4_sctp_en; |
07d29954 L |
3336 | break; |
3337 | case SCTP_V6_FLOW: | |
6f2af429 | 3338 | tuple_sets = vport->rss_tuple_sets.ipv6_sctp_en; |
07d29954 L |
3339 | break; |
3340 | case IPV4_FLOW: | |
3341 | case IPV6_FLOW: | |
3342 | tuple_sets = HCLGE_S_IP_BIT | HCLGE_D_IP_BIT; | |
3343 | break; | |
3344 | default: | |
3345 | return -EINVAL; | |
3346 | } | |
3347 | ||
3348 | if (!tuple_sets) | |
3349 | return 0; | |
3350 | ||
3351 | if (tuple_sets & HCLGE_D_PORT_BIT) | |
3352 | nfc->data |= RXH_L4_B_2_3; | |
3353 | if (tuple_sets & HCLGE_S_PORT_BIT) | |
3354 | nfc->data |= RXH_L4_B_0_1; | |
3355 | if (tuple_sets & HCLGE_D_IP_BIT) | |
3356 | nfc->data |= RXH_IP_DST; | |
3357 | if (tuple_sets & HCLGE_S_IP_BIT) | |
3358 | nfc->data |= RXH_IP_SRC; | |
3359 | ||
3360 | return 0; | |
3361 | } | |
3362 | ||
46a3df9f S |
3363 | static int hclge_get_tc_size(struct hnae3_handle *handle) |
3364 | { | |
3365 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3366 | struct hclge_dev *hdev = vport->back; | |
3367 | ||
3368 | return hdev->rss_size_max; | |
3369 | } | |
3370 | ||
77f255c1 | 3371 | int hclge_rss_init_hw(struct hclge_dev *hdev) |
46a3df9f | 3372 | { |
46a3df9f | 3373 | struct hclge_vport *vport = hdev->vport; |
268f5dfa YL |
3374 | u8 *rss_indir = vport[0].rss_indirection_tbl; |
3375 | u16 rss_size = vport[0].alloc_rss_size; | |
3376 | u8 *key = vport[0].rss_hash_key; | |
3377 | u8 hfunc = vport[0].rss_algo; | |
46a3df9f | 3378 | u16 tc_offset[HCLGE_MAX_TC_NUM]; |
46a3df9f S |
3379 | u16 tc_valid[HCLGE_MAX_TC_NUM]; |
3380 | u16 tc_size[HCLGE_MAX_TC_NUM]; | |
268f5dfa YL |
3381 | u16 roundup_size; |
3382 | int i, ret; | |
68ece54e | 3383 | |
46a3df9f S |
3384 | ret = hclge_set_rss_indir_table(hdev, rss_indir); |
3385 | if (ret) | |
268f5dfa | 3386 | return ret; |
46a3df9f | 3387 | |
46a3df9f S |
3388 | ret = hclge_set_rss_algo_key(hdev, hfunc, key); |
3389 | if (ret) | |
268f5dfa | 3390 | return ret; |
46a3df9f S |
3391 | |
3392 | ret = hclge_set_rss_input_tuple(hdev); | |
3393 | if (ret) | |
268f5dfa | 3394 | return ret; |
46a3df9f | 3395 | |
68ece54e YL |
3396 | /* Each TC have the same queue size, and tc_size set to hardware is |
3397 | * the log2 of roundup power of two of rss_size, the acutal queue | |
3398 | * size is limited by indirection table. | |
3399 | */ | |
3400 | if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) { | |
3401 | dev_err(&hdev->pdev->dev, | |
3402 | "Configure rss tc size failed, invalid TC_SIZE = %d\n", | |
3403 | rss_size); | |
268f5dfa | 3404 | return -EINVAL; |
68ece54e YL |
3405 | } |
3406 | ||
3407 | roundup_size = roundup_pow_of_two(rss_size); | |
3408 | roundup_size = ilog2(roundup_size); | |
3409 | ||
46a3df9f | 3410 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { |
68ece54e | 3411 | tc_valid[i] = 0; |
46a3df9f | 3412 | |
68ece54e YL |
3413 | if (!(hdev->hw_tc_map & BIT(i))) |
3414 | continue; | |
3415 | ||
3416 | tc_valid[i] = 1; | |
3417 | tc_size[i] = roundup_size; | |
3418 | tc_offset[i] = rss_size * i; | |
46a3df9f | 3419 | } |
68ece54e | 3420 | |
268f5dfa YL |
3421 | return hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); |
3422 | } | |
46a3df9f | 3423 | |
268f5dfa YL |
3424 | void hclge_rss_indir_init_cfg(struct hclge_dev *hdev) |
3425 | { | |
3426 | struct hclge_vport *vport = hdev->vport; | |
3427 | int i, j; | |
46a3df9f | 3428 | |
268f5dfa YL |
3429 | for (j = 0; j < hdev->num_vmdq_vport + 1; j++) { |
3430 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) | |
3431 | vport[j].rss_indirection_tbl[i] = | |
3432 | i % vport[j].alloc_rss_size; | |
3433 | } | |
3434 | } | |
3435 | ||
3436 | static void hclge_rss_init_cfg(struct hclge_dev *hdev) | |
3437 | { | |
3438 | struct hclge_vport *vport = hdev->vport; | |
3439 | int i; | |
3440 | ||
268f5dfa YL |
3441 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { |
3442 | vport[i].rss_tuple_sets.ipv4_tcp_en = | |
3443 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3444 | vport[i].rss_tuple_sets.ipv4_udp_en = | |
3445 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3446 | vport[i].rss_tuple_sets.ipv4_sctp_en = | |
3447 | HCLGE_RSS_INPUT_TUPLE_SCTP; | |
3448 | vport[i].rss_tuple_sets.ipv4_fragment_en = | |
3449 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3450 | vport[i].rss_tuple_sets.ipv6_tcp_en = | |
3451 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3452 | vport[i].rss_tuple_sets.ipv6_udp_en = | |
3453 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3454 | vport[i].rss_tuple_sets.ipv6_sctp_en = | |
3455 | HCLGE_RSS_INPUT_TUPLE_SCTP; | |
3456 | vport[i].rss_tuple_sets.ipv6_fragment_en = | |
3457 | HCLGE_RSS_INPUT_TUPLE_OTHER; | |
3458 | ||
3459 | vport[i].rss_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ; | |
ea739c90 FL |
3460 | |
3461 | netdev_rss_key_fill(vport[i].rss_hash_key, HCLGE_RSS_KEY_SIZE); | |
268f5dfa YL |
3462 | } |
3463 | ||
3464 | hclge_rss_indir_init_cfg(hdev); | |
46a3df9f S |
3465 | } |
3466 | ||
84e095d6 SM |
3467 | int hclge_bind_ring_with_vector(struct hclge_vport *vport, |
3468 | int vector_id, bool en, | |
3469 | struct hnae3_ring_chain_node *ring_chain) | |
46a3df9f S |
3470 | { |
3471 | struct hclge_dev *hdev = vport->back; | |
46a3df9f S |
3472 | struct hnae3_ring_chain_node *node; |
3473 | struct hclge_desc desc; | |
84e095d6 SM |
3474 | struct hclge_ctrl_vector_chain_cmd *req |
3475 | = (struct hclge_ctrl_vector_chain_cmd *)desc.data; | |
3476 | enum hclge_cmd_status status; | |
3477 | enum hclge_opcode_type op; | |
3478 | u16 tqp_type_and_id; | |
46a3df9f S |
3479 | int i; |
3480 | ||
84e095d6 SM |
3481 | op = en ? HCLGE_OPC_ADD_RING_TO_VECTOR : HCLGE_OPC_DEL_RING_TO_VECTOR; |
3482 | hclge_cmd_setup_basic_desc(&desc, op, false); | |
46a3df9f S |
3483 | req->int_vector_id = vector_id; |
3484 | ||
3485 | i = 0; | |
3486 | for (node = ring_chain; node; node = node->next) { | |
84e095d6 | 3487 | tqp_type_and_id = le16_to_cpu(req->tqp_type_and_id[i]); |
e4e87715 PL |
3488 | hnae3_set_field(tqp_type_and_id, HCLGE_INT_TYPE_M, |
3489 | HCLGE_INT_TYPE_S, | |
3490 | hnae3_get_bit(node->flag, HNAE3_RING_TYPE_B)); | |
3491 | hnae3_set_field(tqp_type_and_id, HCLGE_TQP_ID_M, | |
3492 | HCLGE_TQP_ID_S, node->tqp_index); | |
3493 | hnae3_set_field(tqp_type_and_id, HCLGE_INT_GL_IDX_M, | |
3494 | HCLGE_INT_GL_IDX_S, | |
3495 | hnae3_get_field(node->int_gl_idx, | |
3496 | HNAE3_RING_GL_IDX_M, | |
3497 | HNAE3_RING_GL_IDX_S)); | |
84e095d6 | 3498 | req->tqp_type_and_id[i] = cpu_to_le16(tqp_type_and_id); |
46a3df9f S |
3499 | if (++i >= HCLGE_VECTOR_ELEMENTS_PER_CMD) { |
3500 | req->int_cause_num = HCLGE_VECTOR_ELEMENTS_PER_CMD; | |
84e095d6 | 3501 | req->vfid = vport->vport_id; |
46a3df9f | 3502 | |
84e095d6 SM |
3503 | status = hclge_cmd_send(&hdev->hw, &desc, 1); |
3504 | if (status) { | |
46a3df9f S |
3505 | dev_err(&hdev->pdev->dev, |
3506 | "Map TQP fail, status is %d.\n", | |
84e095d6 SM |
3507 | status); |
3508 | return -EIO; | |
46a3df9f S |
3509 | } |
3510 | i = 0; | |
3511 | ||
3512 | hclge_cmd_setup_basic_desc(&desc, | |
84e095d6 | 3513 | op, |
46a3df9f S |
3514 | false); |
3515 | req->int_vector_id = vector_id; | |
3516 | } | |
3517 | } | |
3518 | ||
3519 | if (i > 0) { | |
3520 | req->int_cause_num = i; | |
84e095d6 SM |
3521 | req->vfid = vport->vport_id; |
3522 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3523 | if (status) { | |
46a3df9f | 3524 | dev_err(&hdev->pdev->dev, |
84e095d6 SM |
3525 | "Map TQP fail, status is %d.\n", status); |
3526 | return -EIO; | |
46a3df9f S |
3527 | } |
3528 | } | |
3529 | ||
3530 | return 0; | |
3531 | } | |
3532 | ||
84e095d6 SM |
3533 | static int hclge_map_ring_to_vector(struct hnae3_handle *handle, |
3534 | int vector, | |
3535 | struct hnae3_ring_chain_node *ring_chain) | |
46a3df9f S |
3536 | { |
3537 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3538 | struct hclge_dev *hdev = vport->back; | |
3539 | int vector_id; | |
3540 | ||
3541 | vector_id = hclge_get_vector_index(hdev, vector); | |
3542 | if (vector_id < 0) { | |
3543 | dev_err(&hdev->pdev->dev, | |
84e095d6 | 3544 | "Get vector index fail. vector_id =%d\n", vector_id); |
46a3df9f S |
3545 | return vector_id; |
3546 | } | |
3547 | ||
84e095d6 | 3548 | return hclge_bind_ring_with_vector(vport, vector_id, true, ring_chain); |
46a3df9f S |
3549 | } |
3550 | ||
84e095d6 SM |
3551 | static int hclge_unmap_ring_frm_vector(struct hnae3_handle *handle, |
3552 | int vector, | |
3553 | struct hnae3_ring_chain_node *ring_chain) | |
46a3df9f S |
3554 | { |
3555 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3556 | struct hclge_dev *hdev = vport->back; | |
84e095d6 | 3557 | int vector_id, ret; |
46a3df9f | 3558 | |
b50ae26c PL |
3559 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) |
3560 | return 0; | |
3561 | ||
46a3df9f S |
3562 | vector_id = hclge_get_vector_index(hdev, vector); |
3563 | if (vector_id < 0) { | |
3564 | dev_err(&handle->pdev->dev, | |
3565 | "Get vector index fail. ret =%d\n", vector_id); | |
3566 | return vector_id; | |
3567 | } | |
3568 | ||
84e095d6 | 3569 | ret = hclge_bind_ring_with_vector(vport, vector_id, false, ring_chain); |
0d3e6631 | 3570 | if (ret) |
84e095d6 SM |
3571 | dev_err(&handle->pdev->dev, |
3572 | "Unmap ring from vector fail. vectorid=%d, ret =%d\n", | |
3573 | vector_id, | |
3574 | ret); | |
46a3df9f | 3575 | |
0d3e6631 | 3576 | return ret; |
46a3df9f S |
3577 | } |
3578 | ||
3579 | int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev, | |
3580 | struct hclge_promisc_param *param) | |
3581 | { | |
d44f9b63 | 3582 | struct hclge_promisc_cfg_cmd *req; |
46a3df9f S |
3583 | struct hclge_desc desc; |
3584 | int ret; | |
3585 | ||
3586 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_PROMISC_MODE, false); | |
3587 | ||
d44f9b63 | 3588 | req = (struct hclge_promisc_cfg_cmd *)desc.data; |
46a3df9f | 3589 | req->vf_id = param->vf_id; |
96c0e861 PL |
3590 | |
3591 | /* HCLGE_PROMISC_TX_EN_B and HCLGE_PROMISC_RX_EN_B are not supported on | |
3592 | * pdev revision(0x20), new revision support them. The | |
3593 | * value of this two fields will not return error when driver | |
3594 | * send command to fireware in revision(0x20). | |
3595 | */ | |
3596 | req->flag = (param->enable << HCLGE_PROMISC_EN_B) | | |
3597 | HCLGE_PROMISC_TX_EN_B | HCLGE_PROMISC_RX_EN_B; | |
46a3df9f S |
3598 | |
3599 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3600 | if (ret) { | |
3601 | dev_err(&hdev->pdev->dev, | |
3602 | "Set promisc mode fail, status is %d.\n", ret); | |
3603 | return ret; | |
3604 | } | |
3605 | return 0; | |
3606 | } | |
3607 | ||
3608 | void hclge_promisc_param_init(struct hclge_promisc_param *param, bool en_uc, | |
3609 | bool en_mc, bool en_bc, int vport_id) | |
3610 | { | |
3611 | if (!param) | |
3612 | return; | |
3613 | ||
3614 | memset(param, 0, sizeof(struct hclge_promisc_param)); | |
3615 | if (en_uc) | |
3616 | param->enable = HCLGE_PROMISC_EN_UC; | |
3617 | if (en_mc) | |
3618 | param->enable |= HCLGE_PROMISC_EN_MC; | |
3619 | if (en_bc) | |
3620 | param->enable |= HCLGE_PROMISC_EN_BC; | |
3621 | param->vf_id = vport_id; | |
3622 | } | |
3623 | ||
3b75c3df PL |
3624 | static void hclge_set_promisc_mode(struct hnae3_handle *handle, bool en_uc_pmc, |
3625 | bool en_mc_pmc) | |
46a3df9f S |
3626 | { |
3627 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3628 | struct hclge_dev *hdev = vport->back; | |
3629 | struct hclge_promisc_param param; | |
3630 | ||
3b75c3df PL |
3631 | hclge_promisc_param_init(¶m, en_uc_pmc, en_mc_pmc, true, |
3632 | vport->vport_id); | |
46a3df9f S |
3633 | hclge_cmd_set_promisc_mode(hdev, ¶m); |
3634 | } | |
3635 | ||
3636 | static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable) | |
3637 | { | |
3638 | struct hclge_desc desc; | |
d44f9b63 YL |
3639 | struct hclge_config_mac_mode_cmd *req = |
3640 | (struct hclge_config_mac_mode_cmd *)desc.data; | |
a90bb9a5 | 3641 | u32 loop_en = 0; |
46a3df9f S |
3642 | int ret; |
3643 | ||
3644 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, false); | |
e4e87715 PL |
3645 | hnae3_set_bit(loop_en, HCLGE_MAC_TX_EN_B, enable); |
3646 | hnae3_set_bit(loop_en, HCLGE_MAC_RX_EN_B, enable); | |
3647 | hnae3_set_bit(loop_en, HCLGE_MAC_PAD_TX_B, enable); | |
3648 | hnae3_set_bit(loop_en, HCLGE_MAC_PAD_RX_B, enable); | |
3649 | hnae3_set_bit(loop_en, HCLGE_MAC_1588_TX_B, 0); | |
3650 | hnae3_set_bit(loop_en, HCLGE_MAC_1588_RX_B, 0); | |
3651 | hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, 0); | |
3652 | hnae3_set_bit(loop_en, HCLGE_MAC_LINE_LP_B, 0); | |
3653 | hnae3_set_bit(loop_en, HCLGE_MAC_FCS_TX_B, enable); | |
3654 | hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_B, enable); | |
3655 | hnae3_set_bit(loop_en, HCLGE_MAC_RX_FCS_STRIP_B, enable); | |
3656 | hnae3_set_bit(loop_en, HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B, enable); | |
3657 | hnae3_set_bit(loop_en, HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B, enable); | |
3658 | hnae3_set_bit(loop_en, HCLGE_MAC_TX_UNDER_MIN_ERR_B, enable); | |
a90bb9a5 | 3659 | req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); |
46a3df9f S |
3660 | |
3661 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3662 | if (ret) | |
3663 | dev_err(&hdev->pdev->dev, | |
3664 | "mac enable fail, ret =%d.\n", ret); | |
3665 | } | |
3666 | ||
e4d68dae | 3667 | static int hclge_set_mac_loopback(struct hclge_dev *hdev, bool en) |
c39c4d98 | 3668 | { |
c39c4d98 | 3669 | struct hclge_config_mac_mode_cmd *req; |
c39c4d98 YL |
3670 | struct hclge_desc desc; |
3671 | u32 loop_en; | |
3672 | int ret; | |
3673 | ||
e4d68dae YL |
3674 | req = (struct hclge_config_mac_mode_cmd *)&desc.data[0]; |
3675 | /* 1 Read out the MAC mode config at first */ | |
3676 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAC_MODE, true); | |
3677 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3678 | if (ret) { | |
3679 | dev_err(&hdev->pdev->dev, | |
3680 | "mac loopback get fail, ret =%d.\n", ret); | |
3681 | return ret; | |
3682 | } | |
c39c4d98 | 3683 | |
e4d68dae YL |
3684 | /* 2 Then setup the loopback flag */ |
3685 | loop_en = le32_to_cpu(req->txrx_pad_fcs_loop_en); | |
e4e87715 | 3686 | hnae3_set_bit(loop_en, HCLGE_MAC_APP_LP_B, en ? 1 : 0); |
e4d68dae YL |
3687 | |
3688 | req->txrx_pad_fcs_loop_en = cpu_to_le32(loop_en); | |
c39c4d98 | 3689 | |
e4d68dae YL |
3690 | /* 3 Config mac work mode with loopback flag |
3691 | * and its original configure parameters | |
3692 | */ | |
3693 | hclge_cmd_reuse_desc(&desc, false); | |
3694 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3695 | if (ret) | |
3696 | dev_err(&hdev->pdev->dev, | |
3697 | "mac loopback set fail, ret =%d.\n", ret); | |
3698 | return ret; | |
3699 | } | |
c39c4d98 | 3700 | |
e4d68dae YL |
3701 | static int hclge_set_loopback(struct hnae3_handle *handle, |
3702 | enum hnae3_loop loop_mode, bool en) | |
3703 | { | |
3704 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3705 | struct hclge_dev *hdev = vport->back; | |
3706 | int ret; | |
3707 | ||
3708 | switch (loop_mode) { | |
3709 | case HNAE3_MAC_INTER_LOOP_MAC: | |
3710 | ret = hclge_set_mac_loopback(hdev, en); | |
c39c4d98 YL |
3711 | break; |
3712 | default: | |
3713 | ret = -ENOTSUPP; | |
3714 | dev_err(&hdev->pdev->dev, | |
3715 | "loop_mode %d is not supported\n", loop_mode); | |
3716 | break; | |
3717 | } | |
3718 | ||
3719 | return ret; | |
3720 | } | |
3721 | ||
46a3df9f S |
3722 | static int hclge_tqp_enable(struct hclge_dev *hdev, int tqp_id, |
3723 | int stream_id, bool enable) | |
3724 | { | |
3725 | struct hclge_desc desc; | |
d44f9b63 YL |
3726 | struct hclge_cfg_com_tqp_queue_cmd *req = |
3727 | (struct hclge_cfg_com_tqp_queue_cmd *)desc.data; | |
46a3df9f S |
3728 | int ret; |
3729 | ||
3730 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CFG_COM_TQP_QUEUE, false); | |
3731 | req->tqp_id = cpu_to_le16(tqp_id & HCLGE_RING_ID_MASK); | |
3732 | req->stream_id = cpu_to_le16(stream_id); | |
3733 | req->enable |= enable << HCLGE_TQP_ENABLE_B; | |
3734 | ||
3735 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3736 | if (ret) | |
3737 | dev_err(&hdev->pdev->dev, | |
3738 | "Tqp enable fail, status =%d.\n", ret); | |
3739 | return ret; | |
3740 | } | |
3741 | ||
3742 | static void hclge_reset_tqp_stats(struct hnae3_handle *handle) | |
3743 | { | |
3744 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3745 | struct hnae3_queue *queue; | |
3746 | struct hclge_tqp *tqp; | |
3747 | int i; | |
3748 | ||
3749 | for (i = 0; i < vport->alloc_tqps; i++) { | |
3750 | queue = handle->kinfo.tqp[i]; | |
3751 | tqp = container_of(queue, struct hclge_tqp, q); | |
3752 | memset(&tqp->tqp_stats, 0, sizeof(tqp->tqp_stats)); | |
3753 | } | |
3754 | } | |
3755 | ||
3756 | static int hclge_ae_start(struct hnae3_handle *handle) | |
3757 | { | |
3758 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3759 | struct hclge_dev *hdev = vport->back; | |
814e0274 | 3760 | int i, ret; |
46a3df9f | 3761 | |
814e0274 PL |
3762 | for (i = 0; i < vport->alloc_tqps; i++) |
3763 | hclge_tqp_enable(hdev, i, 0, true); | |
46a3df9f | 3764 | |
46a3df9f S |
3765 | /* mac enable */ |
3766 | hclge_cfg_mac_mode(hdev, true); | |
3767 | clear_bit(HCLGE_STATE_DOWN, &hdev->state); | |
d039ef68 | 3768 | mod_timer(&hdev->service_timer, jiffies + HZ); |
be8d8cdb | 3769 | hdev->hw.mac.link = 0; |
46a3df9f | 3770 | |
b50ae26c PL |
3771 | /* reset tqp stats */ |
3772 | hclge_reset_tqp_stats(handle); | |
3773 | ||
46a3df9f S |
3774 | ret = hclge_mac_start_phy(hdev); |
3775 | if (ret) | |
3776 | return ret; | |
3777 | ||
46a3df9f S |
3778 | return 0; |
3779 | } | |
3780 | ||
3781 | static void hclge_ae_stop(struct hnae3_handle *handle) | |
3782 | { | |
3783 | struct hclge_vport *vport = hclge_get_vport(handle); | |
3784 | struct hclge_dev *hdev = vport->back; | |
814e0274 | 3785 | int i; |
46a3df9f | 3786 | |
b50ae26c PL |
3787 | del_timer_sync(&hdev->service_timer); |
3788 | cancel_work_sync(&hdev->service_task); | |
f5be7967 | 3789 | clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state); |
b50ae26c | 3790 | |
9617f668 YL |
3791 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) { |
3792 | hclge_mac_stop_phy(hdev); | |
b50ae26c | 3793 | return; |
9617f668 | 3794 | } |
b50ae26c | 3795 | |
814e0274 PL |
3796 | for (i = 0; i < vport->alloc_tqps; i++) |
3797 | hclge_tqp_enable(hdev, i, 0, false); | |
46a3df9f | 3798 | |
46a3df9f S |
3799 | /* Mac disable */ |
3800 | hclge_cfg_mac_mode(hdev, false); | |
3801 | ||
3802 | hclge_mac_stop_phy(hdev); | |
3803 | ||
3804 | /* reset tqp stats */ | |
3805 | hclge_reset_tqp_stats(handle); | |
f30dfddc FL |
3806 | del_timer_sync(&hdev->service_timer); |
3807 | cancel_work_sync(&hdev->service_task); | |
3808 | hclge_update_link_status(hdev); | |
46a3df9f S |
3809 | } |
3810 | ||
3811 | static int hclge_get_mac_vlan_cmd_status(struct hclge_vport *vport, | |
3812 | u16 cmdq_resp, u8 resp_code, | |
3813 | enum hclge_mac_vlan_tbl_opcode op) | |
3814 | { | |
3815 | struct hclge_dev *hdev = vport->back; | |
3816 | int return_status = -EIO; | |
3817 | ||
3818 | if (cmdq_resp) { | |
3819 | dev_err(&hdev->pdev->dev, | |
3820 | "cmdq execute failed for get_mac_vlan_cmd_status,status=%d.\n", | |
3821 | cmdq_resp); | |
3822 | return -EIO; | |
3823 | } | |
3824 | ||
3825 | if (op == HCLGE_MAC_VLAN_ADD) { | |
3826 | if ((!resp_code) || (resp_code == 1)) { | |
3827 | return_status = 0; | |
3828 | } else if (resp_code == 2) { | |
eefd00a5 | 3829 | return_status = -ENOSPC; |
46a3df9f S |
3830 | dev_err(&hdev->pdev->dev, |
3831 | "add mac addr failed for uc_overflow.\n"); | |
3832 | } else if (resp_code == 3) { | |
eefd00a5 | 3833 | return_status = -ENOSPC; |
46a3df9f S |
3834 | dev_err(&hdev->pdev->dev, |
3835 | "add mac addr failed for mc_overflow.\n"); | |
3836 | } else { | |
3837 | dev_err(&hdev->pdev->dev, | |
3838 | "add mac addr failed for undefined, code=%d.\n", | |
3839 | resp_code); | |
3840 | } | |
3841 | } else if (op == HCLGE_MAC_VLAN_REMOVE) { | |
3842 | if (!resp_code) { | |
3843 | return_status = 0; | |
3844 | } else if (resp_code == 1) { | |
eefd00a5 | 3845 | return_status = -ENOENT; |
46a3df9f S |
3846 | dev_dbg(&hdev->pdev->dev, |
3847 | "remove mac addr failed for miss.\n"); | |
3848 | } else { | |
3849 | dev_err(&hdev->pdev->dev, | |
3850 | "remove mac addr failed for undefined, code=%d.\n", | |
3851 | resp_code); | |
3852 | } | |
3853 | } else if (op == HCLGE_MAC_VLAN_LKUP) { | |
3854 | if (!resp_code) { | |
3855 | return_status = 0; | |
3856 | } else if (resp_code == 1) { | |
eefd00a5 | 3857 | return_status = -ENOENT; |
46a3df9f S |
3858 | dev_dbg(&hdev->pdev->dev, |
3859 | "lookup mac addr failed for miss.\n"); | |
3860 | } else { | |
3861 | dev_err(&hdev->pdev->dev, | |
3862 | "lookup mac addr failed for undefined, code=%d.\n", | |
3863 | resp_code); | |
3864 | } | |
3865 | } else { | |
eefd00a5 | 3866 | return_status = -EINVAL; |
46a3df9f S |
3867 | dev_err(&hdev->pdev->dev, |
3868 | "unknown opcode for get_mac_vlan_cmd_status,opcode=%d.\n", | |
3869 | op); | |
3870 | } | |
3871 | ||
3872 | return return_status; | |
3873 | } | |
3874 | ||
3875 | static int hclge_update_desc_vfid(struct hclge_desc *desc, int vfid, bool clr) | |
3876 | { | |
3877 | int word_num; | |
3878 | int bit_num; | |
3879 | ||
3880 | if (vfid > 255 || vfid < 0) | |
3881 | return -EIO; | |
3882 | ||
3883 | if (vfid >= 0 && vfid <= 191) { | |
3884 | word_num = vfid / 32; | |
3885 | bit_num = vfid % 32; | |
3886 | if (clr) | |
a90bb9a5 | 3887 | desc[1].data[word_num] &= cpu_to_le32(~(1 << bit_num)); |
46a3df9f | 3888 | else |
a90bb9a5 | 3889 | desc[1].data[word_num] |= cpu_to_le32(1 << bit_num); |
46a3df9f S |
3890 | } else { |
3891 | word_num = (vfid - 192) / 32; | |
3892 | bit_num = vfid % 32; | |
3893 | if (clr) | |
a90bb9a5 | 3894 | desc[2].data[word_num] &= cpu_to_le32(~(1 << bit_num)); |
46a3df9f | 3895 | else |
a90bb9a5 | 3896 | desc[2].data[word_num] |= cpu_to_le32(1 << bit_num); |
46a3df9f S |
3897 | } |
3898 | ||
3899 | return 0; | |
3900 | } | |
3901 | ||
3902 | static bool hclge_is_all_function_id_zero(struct hclge_desc *desc) | |
3903 | { | |
3904 | #define HCLGE_DESC_NUMBER 3 | |
3905 | #define HCLGE_FUNC_NUMBER_PER_DESC 6 | |
3906 | int i, j; | |
3907 | ||
3908 | for (i = 0; i < HCLGE_DESC_NUMBER; i++) | |
3909 | for (j = 0; j < HCLGE_FUNC_NUMBER_PER_DESC; j++) | |
3910 | if (desc[i].data[j]) | |
3911 | return false; | |
3912 | ||
3913 | return true; | |
3914 | } | |
3915 | ||
d44f9b63 | 3916 | static void hclge_prepare_mac_addr(struct hclge_mac_vlan_tbl_entry_cmd *new_req, |
46a3df9f S |
3917 | const u8 *addr) |
3918 | { | |
3919 | const unsigned char *mac_addr = addr; | |
3920 | u32 high_val = mac_addr[2] << 16 | (mac_addr[3] << 24) | | |
3921 | (mac_addr[0]) | (mac_addr[1] << 8); | |
3922 | u32 low_val = mac_addr[4] | (mac_addr[5] << 8); | |
3923 | ||
3924 | new_req->mac_addr_hi32 = cpu_to_le32(high_val); | |
3925 | new_req->mac_addr_lo16 = cpu_to_le16(low_val & 0xffff); | |
3926 | } | |
3927 | ||
1db9b1bf YL |
3928 | static u16 hclge_get_mac_addr_to_mta_index(struct hclge_vport *vport, |
3929 | const u8 *addr) | |
46a3df9f S |
3930 | { |
3931 | u16 high_val = addr[1] | (addr[0] << 8); | |
3932 | struct hclge_dev *hdev = vport->back; | |
3933 | u32 rsh = 4 - hdev->mta_mac_sel_type; | |
3934 | u16 ret_val = (high_val >> rsh) & 0xfff; | |
3935 | ||
3936 | return ret_val; | |
3937 | } | |
3938 | ||
3939 | static int hclge_set_mta_filter_mode(struct hclge_dev *hdev, | |
3940 | enum hclge_mta_dmac_sel_type mta_mac_sel, | |
3941 | bool enable) | |
3942 | { | |
d44f9b63 | 3943 | struct hclge_mta_filter_mode_cmd *req; |
46a3df9f S |
3944 | struct hclge_desc desc; |
3945 | int ret; | |
3946 | ||
d44f9b63 | 3947 | req = (struct hclge_mta_filter_mode_cmd *)desc.data; |
46a3df9f S |
3948 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_MODE_CFG, false); |
3949 | ||
e4e87715 PL |
3950 | hnae3_set_bit(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_EN_B, |
3951 | enable); | |
3952 | hnae3_set_field(req->dmac_sel_en, HCLGE_CFG_MTA_MAC_SEL_M, | |
3953 | HCLGE_CFG_MTA_MAC_SEL_S, mta_mac_sel); | |
46a3df9f S |
3954 | |
3955 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3956 | if (ret) { | |
3957 | dev_err(&hdev->pdev->dev, | |
3958 | "Config mat filter mode failed for cmd_send, ret =%d.\n", | |
3959 | ret); | |
3960 | return ret; | |
3961 | } | |
3962 | ||
3963 | return 0; | |
3964 | } | |
3965 | ||
3966 | int hclge_cfg_func_mta_filter(struct hclge_dev *hdev, | |
3967 | u8 func_id, | |
3968 | bool enable) | |
3969 | { | |
d44f9b63 | 3970 | struct hclge_cfg_func_mta_filter_cmd *req; |
46a3df9f S |
3971 | struct hclge_desc desc; |
3972 | int ret; | |
3973 | ||
d44f9b63 | 3974 | req = (struct hclge_cfg_func_mta_filter_cmd *)desc.data; |
46a3df9f S |
3975 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_MAC_FUNC_CFG, false); |
3976 | ||
e4e87715 PL |
3977 | hnae3_set_bit(req->accept, HCLGE_CFG_FUNC_MTA_ACCEPT_B, |
3978 | enable); | |
46a3df9f S |
3979 | req->function_id = func_id; |
3980 | ||
3981 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
3982 | if (ret) { | |
3983 | dev_err(&hdev->pdev->dev, | |
3984 | "Config func_id enable failed for cmd_send, ret =%d.\n", | |
3985 | ret); | |
3986 | return ret; | |
3987 | } | |
3988 | ||
3989 | return 0; | |
3990 | } | |
3991 | ||
3992 | static int hclge_set_mta_table_item(struct hclge_vport *vport, | |
3993 | u16 idx, | |
3994 | bool enable) | |
3995 | { | |
3996 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 3997 | struct hclge_cfg_func_mta_item_cmd *req; |
46a3df9f | 3998 | struct hclge_desc desc; |
a90bb9a5 | 3999 | u16 item_idx = 0; |
46a3df9f S |
4000 | int ret; |
4001 | ||
d44f9b63 | 4002 | req = (struct hclge_cfg_func_mta_item_cmd *)desc.data; |
46a3df9f | 4003 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MTA_TBL_ITEM_CFG, false); |
e4e87715 | 4004 | hnae3_set_bit(req->accept, HCLGE_CFG_MTA_ITEM_ACCEPT_B, enable); |
46a3df9f | 4005 | |
e4e87715 PL |
4006 | hnae3_set_field(item_idx, HCLGE_CFG_MTA_ITEM_IDX_M, |
4007 | HCLGE_CFG_MTA_ITEM_IDX_S, idx); | |
a90bb9a5 | 4008 | req->item_idx = cpu_to_le16(item_idx); |
46a3df9f S |
4009 | |
4010 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4011 | if (ret) { | |
4012 | dev_err(&hdev->pdev->dev, | |
4013 | "Config mta table item failed for cmd_send, ret =%d.\n", | |
4014 | ret); | |
4015 | return ret; | |
4016 | } | |
4017 | ||
40cca1c5 XW |
4018 | if (enable) |
4019 | set_bit(idx, vport->mta_shadow); | |
4020 | else | |
4021 | clear_bit(idx, vport->mta_shadow); | |
4022 | ||
46a3df9f S |
4023 | return 0; |
4024 | } | |
4025 | ||
40cca1c5 XW |
4026 | static int hclge_update_mta_status(struct hnae3_handle *handle) |
4027 | { | |
4028 | unsigned long mta_status[BITS_TO_LONGS(HCLGE_MTA_TBL_SIZE)]; | |
4029 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4030 | struct net_device *netdev = handle->kinfo.netdev; | |
4031 | struct netdev_hw_addr *ha; | |
4032 | u16 tbl_idx; | |
4033 | ||
4034 | memset(mta_status, 0, sizeof(mta_status)); | |
4035 | ||
4036 | /* update mta_status from mc addr list */ | |
4037 | netdev_for_each_mc_addr(ha, netdev) { | |
4038 | tbl_idx = hclge_get_mac_addr_to_mta_index(vport, ha->addr); | |
4039 | set_bit(tbl_idx, mta_status); | |
4040 | } | |
4041 | ||
4042 | return hclge_update_mta_status_common(vport, mta_status, | |
4043 | 0, HCLGE_MTA_TBL_SIZE, true); | |
4044 | } | |
4045 | ||
4046 | int hclge_update_mta_status_common(struct hclge_vport *vport, | |
4047 | unsigned long *status, | |
4048 | u16 idx, | |
4049 | u16 count, | |
4050 | bool update_filter) | |
4051 | { | |
4052 | struct hclge_dev *hdev = vport->back; | |
4053 | u16 update_max = idx + count; | |
4054 | u16 check_max; | |
4055 | int ret = 0; | |
4056 | bool used; | |
4057 | u16 i; | |
4058 | ||
4059 | /* setup mta check range */ | |
4060 | if (update_filter) { | |
4061 | i = 0; | |
4062 | check_max = HCLGE_MTA_TBL_SIZE; | |
4063 | } else { | |
4064 | i = idx; | |
4065 | check_max = update_max; | |
4066 | } | |
4067 | ||
4068 | used = false; | |
4069 | /* check and update all mta item */ | |
4070 | for (; i < check_max; i++) { | |
4071 | /* ignore unused item */ | |
4072 | if (!test_bit(i, vport->mta_shadow)) | |
4073 | continue; | |
4074 | ||
4075 | /* if i in update range then update it */ | |
4076 | if (i >= idx && i < update_max) | |
4077 | if (!test_bit(i - idx, status)) | |
4078 | hclge_set_mta_table_item(vport, i, false); | |
4079 | ||
4080 | if (!used && test_bit(i, vport->mta_shadow)) | |
4081 | used = true; | |
4082 | } | |
4083 | ||
4084 | /* no longer use mta, disable it */ | |
4085 | if (vport->accept_mta_mc && update_filter && !used) { | |
4086 | ret = hclge_cfg_func_mta_filter(hdev, | |
4087 | vport->vport_id, | |
4088 | false); | |
4089 | if (ret) | |
4090 | dev_err(&hdev->pdev->dev, | |
4091 | "disable func mta filter fail ret=%d\n", | |
4092 | ret); | |
4093 | else | |
4094 | vport->accept_mta_mc = false; | |
4095 | } | |
4096 | ||
4097 | return ret; | |
4098 | } | |
4099 | ||
46a3df9f | 4100 | static int hclge_remove_mac_vlan_tbl(struct hclge_vport *vport, |
d44f9b63 | 4101 | struct hclge_mac_vlan_tbl_entry_cmd *req) |
46a3df9f S |
4102 | { |
4103 | struct hclge_dev *hdev = vport->back; | |
4104 | struct hclge_desc desc; | |
4105 | u8 resp_code; | |
a90bb9a5 | 4106 | u16 retval; |
46a3df9f S |
4107 | int ret; |
4108 | ||
4109 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_REMOVE, false); | |
4110 | ||
d44f9b63 | 4111 | memcpy(desc.data, req, sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
46a3df9f S |
4112 | |
4113 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4114 | if (ret) { | |
4115 | dev_err(&hdev->pdev->dev, | |
4116 | "del mac addr failed for cmd_send, ret =%d.\n", | |
4117 | ret); | |
4118 | return ret; | |
4119 | } | |
a90bb9a5 YL |
4120 | resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; |
4121 | retval = le16_to_cpu(desc.retval); | |
46a3df9f | 4122 | |
a90bb9a5 | 4123 | return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, |
46a3df9f S |
4124 | HCLGE_MAC_VLAN_REMOVE); |
4125 | } | |
4126 | ||
4127 | static int hclge_lookup_mac_vlan_tbl(struct hclge_vport *vport, | |
d44f9b63 | 4128 | struct hclge_mac_vlan_tbl_entry_cmd *req, |
46a3df9f S |
4129 | struct hclge_desc *desc, |
4130 | bool is_mc) | |
4131 | { | |
4132 | struct hclge_dev *hdev = vport->back; | |
4133 | u8 resp_code; | |
a90bb9a5 | 4134 | u16 retval; |
46a3df9f S |
4135 | int ret; |
4136 | ||
4137 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_MAC_VLAN_ADD, true); | |
4138 | if (is_mc) { | |
4139 | desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
4140 | memcpy(desc[0].data, | |
4141 | req, | |
d44f9b63 | 4142 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
46a3df9f S |
4143 | hclge_cmd_setup_basic_desc(&desc[1], |
4144 | HCLGE_OPC_MAC_VLAN_ADD, | |
4145 | true); | |
4146 | desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
4147 | hclge_cmd_setup_basic_desc(&desc[2], | |
4148 | HCLGE_OPC_MAC_VLAN_ADD, | |
4149 | true); | |
4150 | ret = hclge_cmd_send(&hdev->hw, desc, 3); | |
4151 | } else { | |
4152 | memcpy(desc[0].data, | |
4153 | req, | |
d44f9b63 | 4154 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
46a3df9f S |
4155 | ret = hclge_cmd_send(&hdev->hw, desc, 1); |
4156 | } | |
4157 | if (ret) { | |
4158 | dev_err(&hdev->pdev->dev, | |
4159 | "lookup mac addr failed for cmd_send, ret =%d.\n", | |
4160 | ret); | |
4161 | return ret; | |
4162 | } | |
a90bb9a5 YL |
4163 | resp_code = (le32_to_cpu(desc[0].data[0]) >> 8) & 0xff; |
4164 | retval = le16_to_cpu(desc[0].retval); | |
46a3df9f | 4165 | |
a90bb9a5 | 4166 | return hclge_get_mac_vlan_cmd_status(vport, retval, resp_code, |
46a3df9f S |
4167 | HCLGE_MAC_VLAN_LKUP); |
4168 | } | |
4169 | ||
4170 | static int hclge_add_mac_vlan_tbl(struct hclge_vport *vport, | |
d44f9b63 | 4171 | struct hclge_mac_vlan_tbl_entry_cmd *req, |
46a3df9f S |
4172 | struct hclge_desc *mc_desc) |
4173 | { | |
4174 | struct hclge_dev *hdev = vport->back; | |
4175 | int cfg_status; | |
4176 | u8 resp_code; | |
a90bb9a5 | 4177 | u16 retval; |
46a3df9f S |
4178 | int ret; |
4179 | ||
4180 | if (!mc_desc) { | |
4181 | struct hclge_desc desc; | |
4182 | ||
4183 | hclge_cmd_setup_basic_desc(&desc, | |
4184 | HCLGE_OPC_MAC_VLAN_ADD, | |
4185 | false); | |
d44f9b63 YL |
4186 | memcpy(desc.data, req, |
4187 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); | |
46a3df9f | 4188 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); |
a90bb9a5 YL |
4189 | resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; |
4190 | retval = le16_to_cpu(desc.retval); | |
4191 | ||
4192 | cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, | |
46a3df9f S |
4193 | resp_code, |
4194 | HCLGE_MAC_VLAN_ADD); | |
4195 | } else { | |
c3b6f755 | 4196 | hclge_cmd_reuse_desc(&mc_desc[0], false); |
46a3df9f | 4197 | mc_desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
c3b6f755 | 4198 | hclge_cmd_reuse_desc(&mc_desc[1], false); |
46a3df9f | 4199 | mc_desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); |
c3b6f755 | 4200 | hclge_cmd_reuse_desc(&mc_desc[2], false); |
46a3df9f S |
4201 | mc_desc[2].flag &= cpu_to_le16(~HCLGE_CMD_FLAG_NEXT); |
4202 | memcpy(mc_desc[0].data, req, | |
d44f9b63 | 4203 | sizeof(struct hclge_mac_vlan_tbl_entry_cmd)); |
46a3df9f | 4204 | ret = hclge_cmd_send(&hdev->hw, mc_desc, 3); |
a90bb9a5 YL |
4205 | resp_code = (le32_to_cpu(mc_desc[0].data[0]) >> 8) & 0xff; |
4206 | retval = le16_to_cpu(mc_desc[0].retval); | |
4207 | ||
4208 | cfg_status = hclge_get_mac_vlan_cmd_status(vport, retval, | |
46a3df9f S |
4209 | resp_code, |
4210 | HCLGE_MAC_VLAN_ADD); | |
4211 | } | |
4212 | ||
4213 | if (ret) { | |
4214 | dev_err(&hdev->pdev->dev, | |
4215 | "add mac addr failed for cmd_send, ret =%d.\n", | |
4216 | ret); | |
4217 | return ret; | |
4218 | } | |
4219 | ||
4220 | return cfg_status; | |
4221 | } | |
4222 | ||
4223 | static int hclge_add_uc_addr(struct hnae3_handle *handle, | |
4224 | const unsigned char *addr) | |
4225 | { | |
4226 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4227 | ||
4228 | return hclge_add_uc_addr_common(vport, addr); | |
4229 | } | |
4230 | ||
4231 | int hclge_add_uc_addr_common(struct hclge_vport *vport, | |
4232 | const unsigned char *addr) | |
4233 | { | |
4234 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4235 | struct hclge_mac_vlan_tbl_entry_cmd req; |
d07b6bb4 | 4236 | struct hclge_desc desc; |
a90bb9a5 | 4237 | u16 egress_port = 0; |
aa7a795e | 4238 | int ret; |
46a3df9f S |
4239 | |
4240 | /* mac addr check */ | |
4241 | if (is_zero_ether_addr(addr) || | |
4242 | is_broadcast_ether_addr(addr) || | |
4243 | is_multicast_ether_addr(addr)) { | |
4244 | dev_err(&hdev->pdev->dev, | |
4245 | "Set_uc mac err! invalid mac:%pM. is_zero:%d,is_br=%d,is_mul=%d\n", | |
4246 | addr, | |
4247 | is_zero_ether_addr(addr), | |
4248 | is_broadcast_ether_addr(addr), | |
4249 | is_multicast_ether_addr(addr)); | |
4250 | return -EINVAL; | |
4251 | } | |
4252 | ||
4253 | memset(&req, 0, sizeof(req)); | |
e4e87715 | 4254 | hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); |
a90bb9a5 | 4255 | |
e4e87715 PL |
4256 | hnae3_set_field(egress_port, HCLGE_MAC_EPORT_VFID_M, |
4257 | HCLGE_MAC_EPORT_VFID_S, vport->vport_id); | |
a90bb9a5 YL |
4258 | |
4259 | req.egress_port = cpu_to_le16(egress_port); | |
46a3df9f S |
4260 | |
4261 | hclge_prepare_mac_addr(&req, addr); | |
4262 | ||
d07b6bb4 JS |
4263 | /* Lookup the mac address in the mac_vlan table, and add |
4264 | * it if the entry is inexistent. Repeated unicast entry | |
4265 | * is not allowed in the mac vlan table. | |
4266 | */ | |
4267 | ret = hclge_lookup_mac_vlan_tbl(vport, &req, &desc, false); | |
4268 | if (ret == -ENOENT) | |
4269 | return hclge_add_mac_vlan_tbl(vport, &req, NULL); | |
4270 | ||
4271 | /* check if we just hit the duplicate */ | |
4272 | if (!ret) | |
4273 | ret = -EINVAL; | |
4274 | ||
4275 | dev_err(&hdev->pdev->dev, | |
4276 | "PF failed to add unicast entry(%pM) in the MAC table\n", | |
4277 | addr); | |
46a3df9f | 4278 | |
aa7a795e | 4279 | return ret; |
46a3df9f S |
4280 | } |
4281 | ||
4282 | static int hclge_rm_uc_addr(struct hnae3_handle *handle, | |
4283 | const unsigned char *addr) | |
4284 | { | |
4285 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4286 | ||
4287 | return hclge_rm_uc_addr_common(vport, addr); | |
4288 | } | |
4289 | ||
4290 | int hclge_rm_uc_addr_common(struct hclge_vport *vport, | |
4291 | const unsigned char *addr) | |
4292 | { | |
4293 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4294 | struct hclge_mac_vlan_tbl_entry_cmd req; |
aa7a795e | 4295 | int ret; |
46a3df9f S |
4296 | |
4297 | /* mac addr check */ | |
4298 | if (is_zero_ether_addr(addr) || | |
4299 | is_broadcast_ether_addr(addr) || | |
4300 | is_multicast_ether_addr(addr)) { | |
4301 | dev_dbg(&hdev->pdev->dev, | |
4302 | "Remove mac err! invalid mac:%pM.\n", | |
4303 | addr); | |
4304 | return -EINVAL; | |
4305 | } | |
4306 | ||
4307 | memset(&req, 0, sizeof(req)); | |
e4e87715 PL |
4308 | hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); |
4309 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
46a3df9f | 4310 | hclge_prepare_mac_addr(&req, addr); |
aa7a795e | 4311 | ret = hclge_remove_mac_vlan_tbl(vport, &req); |
46a3df9f | 4312 | |
aa7a795e | 4313 | return ret; |
46a3df9f S |
4314 | } |
4315 | ||
4316 | static int hclge_add_mc_addr(struct hnae3_handle *handle, | |
4317 | const unsigned char *addr) | |
4318 | { | |
4319 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4320 | ||
4321 | return hclge_add_mc_addr_common(vport, addr); | |
4322 | } | |
4323 | ||
4324 | int hclge_add_mc_addr_common(struct hclge_vport *vport, | |
4325 | const unsigned char *addr) | |
4326 | { | |
4327 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4328 | struct hclge_mac_vlan_tbl_entry_cmd req; |
46a3df9f S |
4329 | struct hclge_desc desc[3]; |
4330 | u16 tbl_idx; | |
4331 | int status; | |
4332 | ||
4333 | /* mac addr check */ | |
4334 | if (!is_multicast_ether_addr(addr)) { | |
4335 | dev_err(&hdev->pdev->dev, | |
4336 | "Add mc mac err! invalid mac:%pM.\n", | |
4337 | addr); | |
4338 | return -EINVAL; | |
4339 | } | |
4340 | memset(&req, 0, sizeof(req)); | |
e4e87715 PL |
4341 | hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); |
4342 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
4343 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); | |
4344 | hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
46a3df9f S |
4345 | hclge_prepare_mac_addr(&req, addr); |
4346 | status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); | |
4347 | if (!status) { | |
4348 | /* This mac addr exist, update VFID for it */ | |
4349 | hclge_update_desc_vfid(desc, vport->vport_id, false); | |
4350 | status = hclge_add_mac_vlan_tbl(vport, &req, desc); | |
4351 | } else { | |
4352 | /* This mac addr do not exist, add new entry for it */ | |
4353 | memset(desc[0].data, 0, sizeof(desc[0].data)); | |
4354 | memset(desc[1].data, 0, sizeof(desc[0].data)); | |
4355 | memset(desc[2].data, 0, sizeof(desc[0].data)); | |
4356 | hclge_update_desc_vfid(desc, vport->vport_id, false); | |
4357 | status = hclge_add_mac_vlan_tbl(vport, &req, desc); | |
4358 | } | |
4359 | ||
40cca1c5 XW |
4360 | /* If mc mac vlan table is full, use MTA table */ |
4361 | if (status == -ENOSPC) { | |
4362 | if (!vport->accept_mta_mc) { | |
4363 | status = hclge_cfg_func_mta_filter(hdev, | |
4364 | vport->vport_id, | |
4365 | true); | |
4366 | if (status) { | |
4367 | dev_err(&hdev->pdev->dev, | |
4368 | "set mta filter mode fail ret=%d\n", | |
4369 | status); | |
4370 | return status; | |
4371 | } | |
4372 | vport->accept_mta_mc = true; | |
4373 | } | |
4374 | ||
4375 | /* Set MTA table for this MAC address */ | |
4376 | tbl_idx = hclge_get_mac_addr_to_mta_index(vport, addr); | |
4377 | status = hclge_set_mta_table_item(vport, tbl_idx, true); | |
4378 | } | |
46a3df9f S |
4379 | |
4380 | return status; | |
4381 | } | |
4382 | ||
4383 | static int hclge_rm_mc_addr(struct hnae3_handle *handle, | |
4384 | const unsigned char *addr) | |
4385 | { | |
4386 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4387 | ||
4388 | return hclge_rm_mc_addr_common(vport, addr); | |
4389 | } | |
4390 | ||
4391 | int hclge_rm_mc_addr_common(struct hclge_vport *vport, | |
4392 | const unsigned char *addr) | |
4393 | { | |
4394 | struct hclge_dev *hdev = vport->back; | |
d44f9b63 | 4395 | struct hclge_mac_vlan_tbl_entry_cmd req; |
46a3df9f S |
4396 | enum hclge_cmd_status status; |
4397 | struct hclge_desc desc[3]; | |
46a3df9f S |
4398 | |
4399 | /* mac addr check */ | |
4400 | if (!is_multicast_ether_addr(addr)) { | |
4401 | dev_dbg(&hdev->pdev->dev, | |
4402 | "Remove mc mac err! invalid mac:%pM.\n", | |
4403 | addr); | |
4404 | return -EINVAL; | |
4405 | } | |
4406 | ||
4407 | memset(&req, 0, sizeof(req)); | |
e4e87715 PL |
4408 | hnae3_set_bit(req.flags, HCLGE_MAC_VLAN_BIT0_EN_B, 1); |
4409 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
4410 | hnae3_set_bit(req.entry_type, HCLGE_MAC_VLAN_BIT1_EN_B, 1); | |
4411 | hnae3_set_bit(req.mc_mac_en, HCLGE_MAC_VLAN_BIT0_EN_B, 0); | |
46a3df9f S |
4412 | hclge_prepare_mac_addr(&req, addr); |
4413 | status = hclge_lookup_mac_vlan_tbl(vport, &req, desc, true); | |
4414 | if (!status) { | |
4415 | /* This mac addr exist, remove this handle's VFID for it */ | |
4416 | hclge_update_desc_vfid(desc, vport->vport_id, true); | |
4417 | ||
4418 | if (hclge_is_all_function_id_zero(desc)) | |
4419 | /* All the vfid is zero, so need to delete this entry */ | |
4420 | status = hclge_remove_mac_vlan_tbl(vport, &req); | |
4421 | else | |
4422 | /* Not all the vfid is zero, update the vfid */ | |
4423 | status = hclge_add_mac_vlan_tbl(vport, &req, desc); | |
4424 | ||
4425 | } else { | |
40cca1c5 XW |
4426 | /* Maybe this mac address is in mta table, but it cannot be |
4427 | * deleted here because an entry of mta represents an address | |
4428 | * range rather than a specific address. the delete action to | |
4429 | * all entries will take effect in update_mta_status called by | |
4430 | * hns3_nic_set_rx_mode. | |
4431 | */ | |
4432 | status = 0; | |
46a3df9f S |
4433 | } |
4434 | ||
46a3df9f S |
4435 | return status; |
4436 | } | |
4437 | ||
f5aac71c FL |
4438 | static int hclge_get_mac_ethertype_cmd_status(struct hclge_dev *hdev, |
4439 | u16 cmdq_resp, u8 resp_code) | |
4440 | { | |
4441 | #define HCLGE_ETHERTYPE_SUCCESS_ADD 0 | |
4442 | #define HCLGE_ETHERTYPE_ALREADY_ADD 1 | |
4443 | #define HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW 2 | |
4444 | #define HCLGE_ETHERTYPE_KEY_CONFLICT 3 | |
4445 | ||
4446 | int return_status; | |
4447 | ||
4448 | if (cmdq_resp) { | |
4449 | dev_err(&hdev->pdev->dev, | |
4450 | "cmdq execute failed for get_mac_ethertype_cmd_status, status=%d.\n", | |
4451 | cmdq_resp); | |
4452 | return -EIO; | |
4453 | } | |
4454 | ||
4455 | switch (resp_code) { | |
4456 | case HCLGE_ETHERTYPE_SUCCESS_ADD: | |
4457 | case HCLGE_ETHERTYPE_ALREADY_ADD: | |
4458 | return_status = 0; | |
4459 | break; | |
4460 | case HCLGE_ETHERTYPE_MGR_TBL_OVERFLOW: | |
4461 | dev_err(&hdev->pdev->dev, | |
4462 | "add mac ethertype failed for manager table overflow.\n"); | |
4463 | return_status = -EIO; | |
4464 | break; | |
4465 | case HCLGE_ETHERTYPE_KEY_CONFLICT: | |
4466 | dev_err(&hdev->pdev->dev, | |
4467 | "add mac ethertype failed for key conflict.\n"); | |
4468 | return_status = -EIO; | |
4469 | break; | |
4470 | default: | |
4471 | dev_err(&hdev->pdev->dev, | |
4472 | "add mac ethertype failed for undefined, code=%d.\n", | |
4473 | resp_code); | |
4474 | return_status = -EIO; | |
4475 | } | |
4476 | ||
4477 | return return_status; | |
4478 | } | |
4479 | ||
4480 | static int hclge_add_mgr_tbl(struct hclge_dev *hdev, | |
4481 | const struct hclge_mac_mgr_tbl_entry_cmd *req) | |
4482 | { | |
4483 | struct hclge_desc desc; | |
4484 | u8 resp_code; | |
4485 | u16 retval; | |
4486 | int ret; | |
4487 | ||
4488 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_ETHTYPE_ADD, false); | |
4489 | memcpy(desc.data, req, sizeof(struct hclge_mac_mgr_tbl_entry_cmd)); | |
4490 | ||
4491 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4492 | if (ret) { | |
4493 | dev_err(&hdev->pdev->dev, | |
4494 | "add mac ethertype failed for cmd_send, ret =%d.\n", | |
4495 | ret); | |
4496 | return ret; | |
4497 | } | |
4498 | ||
4499 | resp_code = (le32_to_cpu(desc.data[0]) >> 8) & 0xff; | |
4500 | retval = le16_to_cpu(desc.retval); | |
4501 | ||
4502 | return hclge_get_mac_ethertype_cmd_status(hdev, retval, resp_code); | |
4503 | } | |
4504 | ||
4505 | static int init_mgr_tbl(struct hclge_dev *hdev) | |
4506 | { | |
4507 | int ret; | |
4508 | int i; | |
4509 | ||
4510 | for (i = 0; i < ARRAY_SIZE(hclge_mgr_table); i++) { | |
4511 | ret = hclge_add_mgr_tbl(hdev, &hclge_mgr_table[i]); | |
4512 | if (ret) { | |
4513 | dev_err(&hdev->pdev->dev, | |
4514 | "add mac ethertype failed, ret =%d.\n", | |
4515 | ret); | |
4516 | return ret; | |
4517 | } | |
4518 | } | |
4519 | ||
4520 | return 0; | |
4521 | } | |
4522 | ||
46a3df9f S |
4523 | static void hclge_get_mac_addr(struct hnae3_handle *handle, u8 *p) |
4524 | { | |
4525 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4526 | struct hclge_dev *hdev = vport->back; | |
4527 | ||
4528 | ether_addr_copy(p, hdev->hw.mac.mac_addr); | |
4529 | } | |
4530 | ||
59098055 FL |
4531 | static int hclge_set_mac_addr(struct hnae3_handle *handle, void *p, |
4532 | bool is_first) | |
46a3df9f S |
4533 | { |
4534 | const unsigned char *new_addr = (const unsigned char *)p; | |
4535 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4536 | struct hclge_dev *hdev = vport->back; | |
18838d0c | 4537 | int ret; |
46a3df9f S |
4538 | |
4539 | /* mac addr check */ | |
4540 | if (is_zero_ether_addr(new_addr) || | |
4541 | is_broadcast_ether_addr(new_addr) || | |
4542 | is_multicast_ether_addr(new_addr)) { | |
4543 | dev_err(&hdev->pdev->dev, | |
4544 | "Change uc mac err! invalid mac:%p.\n", | |
4545 | new_addr); | |
4546 | return -EINVAL; | |
4547 | } | |
4548 | ||
59098055 | 4549 | if (!is_first && hclge_rm_uc_addr(handle, hdev->hw.mac.mac_addr)) |
18838d0c | 4550 | dev_warn(&hdev->pdev->dev, |
59098055 | 4551 | "remove old uc mac address fail.\n"); |
46a3df9f | 4552 | |
18838d0c FL |
4553 | ret = hclge_add_uc_addr(handle, new_addr); |
4554 | if (ret) { | |
4555 | dev_err(&hdev->pdev->dev, | |
4556 | "add uc mac address fail, ret =%d.\n", | |
4557 | ret); | |
4558 | ||
59098055 FL |
4559 | if (!is_first && |
4560 | hclge_add_uc_addr(handle, hdev->hw.mac.mac_addr)) | |
18838d0c | 4561 | dev_err(&hdev->pdev->dev, |
59098055 | 4562 | "restore uc mac address fail.\n"); |
18838d0c FL |
4563 | |
4564 | return -EIO; | |
46a3df9f S |
4565 | } |
4566 | ||
e98d7183 | 4567 | ret = hclge_pause_addr_cfg(hdev, new_addr); |
18838d0c FL |
4568 | if (ret) { |
4569 | dev_err(&hdev->pdev->dev, | |
4570 | "configure mac pause address fail, ret =%d.\n", | |
4571 | ret); | |
4572 | return -EIO; | |
4573 | } | |
4574 | ||
4575 | ether_addr_copy(hdev->hw.mac.mac_addr, new_addr); | |
4576 | ||
4577 | return 0; | |
46a3df9f S |
4578 | } |
4579 | ||
4580 | static int hclge_set_vlan_filter_ctrl(struct hclge_dev *hdev, u8 vlan_type, | |
4581 | bool filter_en) | |
4582 | { | |
d44f9b63 | 4583 | struct hclge_vlan_filter_ctrl_cmd *req; |
46a3df9f S |
4584 | struct hclge_desc desc; |
4585 | int ret; | |
4586 | ||
4587 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_CTRL, false); | |
4588 | ||
d44f9b63 | 4589 | req = (struct hclge_vlan_filter_ctrl_cmd *)desc.data; |
46a3df9f S |
4590 | req->vlan_type = vlan_type; |
4591 | req->vlan_fe = filter_en; | |
4592 | ||
4593 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4594 | if (ret) { | |
4595 | dev_err(&hdev->pdev->dev, "set vlan filter fail, ret =%d.\n", | |
4596 | ret); | |
4597 | return ret; | |
4598 | } | |
4599 | ||
4600 | return 0; | |
4601 | } | |
4602 | ||
391b5e93 JS |
4603 | #define HCLGE_FILTER_TYPE_VF 0 |
4604 | #define HCLGE_FILTER_TYPE_PORT 1 | |
4605 | ||
4606 | static void hclge_enable_vlan_filter(struct hnae3_handle *handle, bool enable) | |
4607 | { | |
4608 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4609 | struct hclge_dev *hdev = vport->back; | |
4610 | ||
4611 | hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, enable); | |
4612 | } | |
4613 | ||
dc8131d8 YL |
4614 | static int hclge_set_vf_vlan_common(struct hclge_dev *hdev, int vfid, |
4615 | bool is_kill, u16 vlan, u8 qos, | |
4616 | __be16 proto) | |
46a3df9f S |
4617 | { |
4618 | #define HCLGE_MAX_VF_BYTES 16 | |
d44f9b63 YL |
4619 | struct hclge_vlan_filter_vf_cfg_cmd *req0; |
4620 | struct hclge_vlan_filter_vf_cfg_cmd *req1; | |
46a3df9f S |
4621 | struct hclge_desc desc[2]; |
4622 | u8 vf_byte_val; | |
4623 | u8 vf_byte_off; | |
4624 | int ret; | |
4625 | ||
4626 | hclge_cmd_setup_basic_desc(&desc[0], | |
4627 | HCLGE_OPC_VLAN_FILTER_VF_CFG, false); | |
4628 | hclge_cmd_setup_basic_desc(&desc[1], | |
4629 | HCLGE_OPC_VLAN_FILTER_VF_CFG, false); | |
4630 | ||
4631 | desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT); | |
4632 | ||
4633 | vf_byte_off = vfid / 8; | |
4634 | vf_byte_val = 1 << (vfid % 8); | |
4635 | ||
d44f9b63 YL |
4636 | req0 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[0].data; |
4637 | req1 = (struct hclge_vlan_filter_vf_cfg_cmd *)desc[1].data; | |
46a3df9f | 4638 | |
a90bb9a5 | 4639 | req0->vlan_id = cpu_to_le16(vlan); |
46a3df9f S |
4640 | req0->vlan_cfg = is_kill; |
4641 | ||
4642 | if (vf_byte_off < HCLGE_MAX_VF_BYTES) | |
4643 | req0->vf_bitmap[vf_byte_off] = vf_byte_val; | |
4644 | else | |
4645 | req1->vf_bitmap[vf_byte_off - HCLGE_MAX_VF_BYTES] = vf_byte_val; | |
4646 | ||
4647 | ret = hclge_cmd_send(&hdev->hw, desc, 2); | |
4648 | if (ret) { | |
4649 | dev_err(&hdev->pdev->dev, | |
4650 | "Send vf vlan command fail, ret =%d.\n", | |
4651 | ret); | |
4652 | return ret; | |
4653 | } | |
4654 | ||
4655 | if (!is_kill) { | |
6c251711 | 4656 | #define HCLGE_VF_VLAN_NO_ENTRY 2 |
46a3df9f S |
4657 | if (!req0->resp_code || req0->resp_code == 1) |
4658 | return 0; | |
4659 | ||
6c251711 YL |
4660 | if (req0->resp_code == HCLGE_VF_VLAN_NO_ENTRY) { |
4661 | dev_warn(&hdev->pdev->dev, | |
4662 | "vf vlan table is full, vf vlan filter is disabled\n"); | |
4663 | return 0; | |
4664 | } | |
4665 | ||
46a3df9f S |
4666 | dev_err(&hdev->pdev->dev, |
4667 | "Add vf vlan filter fail, ret =%d.\n", | |
4668 | req0->resp_code); | |
4669 | } else { | |
4670 | if (!req0->resp_code) | |
4671 | return 0; | |
4672 | ||
4673 | dev_err(&hdev->pdev->dev, | |
4674 | "Kill vf vlan filter fail, ret =%d.\n", | |
4675 | req0->resp_code); | |
4676 | } | |
4677 | ||
4678 | return -EIO; | |
4679 | } | |
4680 | ||
dc8131d8 YL |
4681 | static int hclge_set_port_vlan_filter(struct hclge_dev *hdev, __be16 proto, |
4682 | u16 vlan_id, bool is_kill) | |
46a3df9f | 4683 | { |
d44f9b63 | 4684 | struct hclge_vlan_filter_pf_cfg_cmd *req; |
46a3df9f S |
4685 | struct hclge_desc desc; |
4686 | u8 vlan_offset_byte_val; | |
4687 | u8 vlan_offset_byte; | |
4688 | u8 vlan_offset_160; | |
4689 | int ret; | |
4690 | ||
4691 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_FILTER_PF_CFG, false); | |
4692 | ||
4693 | vlan_offset_160 = vlan_id / 160; | |
4694 | vlan_offset_byte = (vlan_id % 160) / 8; | |
4695 | vlan_offset_byte_val = 1 << (vlan_id % 8); | |
4696 | ||
d44f9b63 | 4697 | req = (struct hclge_vlan_filter_pf_cfg_cmd *)desc.data; |
46a3df9f S |
4698 | req->vlan_offset = vlan_offset_160; |
4699 | req->vlan_cfg = is_kill; | |
4700 | req->vlan_offset_bitmap[vlan_offset_byte] = vlan_offset_byte_val; | |
4701 | ||
4702 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
dc8131d8 YL |
4703 | if (ret) |
4704 | dev_err(&hdev->pdev->dev, | |
4705 | "port vlan command, send fail, ret =%d.\n", ret); | |
4706 | return ret; | |
4707 | } | |
4708 | ||
4709 | static int hclge_set_vlan_filter_hw(struct hclge_dev *hdev, __be16 proto, | |
4710 | u16 vport_id, u16 vlan_id, u8 qos, | |
4711 | bool is_kill) | |
4712 | { | |
4713 | u16 vport_idx, vport_num = 0; | |
4714 | int ret; | |
4715 | ||
4716 | ret = hclge_set_vf_vlan_common(hdev, vport_id, is_kill, vlan_id, | |
4717 | 0, proto); | |
46a3df9f S |
4718 | if (ret) { |
4719 | dev_err(&hdev->pdev->dev, | |
dc8131d8 YL |
4720 | "Set %d vport vlan filter config fail, ret =%d.\n", |
4721 | vport_id, ret); | |
46a3df9f S |
4722 | return ret; |
4723 | } | |
4724 | ||
dc8131d8 YL |
4725 | /* vlan 0 may be added twice when 8021q module is enabled */ |
4726 | if (!is_kill && !vlan_id && | |
4727 | test_bit(vport_id, hdev->vlan_table[vlan_id])) | |
4728 | return 0; | |
4729 | ||
4730 | if (!is_kill && test_and_set_bit(vport_id, hdev->vlan_table[vlan_id])) { | |
46a3df9f | 4731 | dev_err(&hdev->pdev->dev, |
dc8131d8 YL |
4732 | "Add port vlan failed, vport %d is already in vlan %d\n", |
4733 | vport_id, vlan_id); | |
4734 | return -EINVAL; | |
46a3df9f S |
4735 | } |
4736 | ||
dc8131d8 YL |
4737 | if (is_kill && |
4738 | !test_and_clear_bit(vport_id, hdev->vlan_table[vlan_id])) { | |
4739 | dev_err(&hdev->pdev->dev, | |
4740 | "Delete port vlan failed, vport %d is not in vlan %d\n", | |
4741 | vport_id, vlan_id); | |
4742 | return -EINVAL; | |
4743 | } | |
4744 | ||
4745 | for_each_set_bit(vport_idx, hdev->vlan_table[vlan_id], VLAN_N_VID) | |
4746 | vport_num++; | |
4747 | ||
4748 | if ((is_kill && vport_num == 0) || (!is_kill && vport_num == 1)) | |
4749 | ret = hclge_set_port_vlan_filter(hdev, proto, vlan_id, | |
4750 | is_kill); | |
4751 | ||
4752 | return ret; | |
4753 | } | |
4754 | ||
4755 | int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto, | |
4756 | u16 vlan_id, bool is_kill) | |
4757 | { | |
4758 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4759 | struct hclge_dev *hdev = vport->back; | |
4760 | ||
4761 | return hclge_set_vlan_filter_hw(hdev, proto, vport->vport_id, vlan_id, | |
4762 | 0, is_kill); | |
46a3df9f S |
4763 | } |
4764 | ||
4765 | static int hclge_set_vf_vlan_filter(struct hnae3_handle *handle, int vfid, | |
4766 | u16 vlan, u8 qos, __be16 proto) | |
4767 | { | |
4768 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4769 | struct hclge_dev *hdev = vport->back; | |
4770 | ||
4771 | if ((vfid >= hdev->num_alloc_vfs) || (vlan > 4095) || (qos > 7)) | |
4772 | return -EINVAL; | |
4773 | if (proto != htons(ETH_P_8021Q)) | |
4774 | return -EPROTONOSUPPORT; | |
4775 | ||
dc8131d8 | 4776 | return hclge_set_vlan_filter_hw(hdev, proto, vfid, vlan, qos, false); |
46a3df9f S |
4777 | } |
4778 | ||
5f6ea83f PL |
4779 | static int hclge_set_vlan_tx_offload_cfg(struct hclge_vport *vport) |
4780 | { | |
4781 | struct hclge_tx_vtag_cfg *vcfg = &vport->txvlan_cfg; | |
4782 | struct hclge_vport_vtag_tx_cfg_cmd *req; | |
4783 | struct hclge_dev *hdev = vport->back; | |
4784 | struct hclge_desc desc; | |
4785 | int status; | |
4786 | ||
4787 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_TX_CFG, false); | |
4788 | ||
4789 | req = (struct hclge_vport_vtag_tx_cfg_cmd *)desc.data; | |
4790 | req->def_vlan_tag1 = cpu_to_le16(vcfg->default_tag1); | |
4791 | req->def_vlan_tag2 = cpu_to_le16(vcfg->default_tag2); | |
e4e87715 PL |
4792 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG1_B, |
4793 | vcfg->accept_tag1 ? 1 : 0); | |
4794 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG1_B, | |
4795 | vcfg->accept_untag1 ? 1 : 0); | |
4796 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_TAG2_B, | |
4797 | vcfg->accept_tag2 ? 1 : 0); | |
4798 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_ACCEPT_UNTAG2_B, | |
4799 | vcfg->accept_untag2 ? 1 : 0); | |
4800 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG1_EN_B, | |
4801 | vcfg->insert_tag1_en ? 1 : 0); | |
4802 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_PORT_INS_TAG2_EN_B, | |
4803 | vcfg->insert_tag2_en ? 1 : 0); | |
4804 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_CFG_NIC_ROCE_SEL_B, 0); | |
5f6ea83f PL |
4805 | |
4806 | req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; | |
4807 | req->vf_bitmap[req->vf_offset] = | |
4808 | 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); | |
4809 | ||
4810 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4811 | if (status) | |
4812 | dev_err(&hdev->pdev->dev, | |
4813 | "Send port txvlan cfg command fail, ret =%d\n", | |
4814 | status); | |
4815 | ||
4816 | return status; | |
4817 | } | |
4818 | ||
4819 | static int hclge_set_vlan_rx_offload_cfg(struct hclge_vport *vport) | |
4820 | { | |
4821 | struct hclge_rx_vtag_cfg *vcfg = &vport->rxvlan_cfg; | |
4822 | struct hclge_vport_vtag_rx_cfg_cmd *req; | |
4823 | struct hclge_dev *hdev = vport->back; | |
4824 | struct hclge_desc desc; | |
4825 | int status; | |
4826 | ||
4827 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_VLAN_PORT_RX_CFG, false); | |
4828 | ||
4829 | req = (struct hclge_vport_vtag_rx_cfg_cmd *)desc.data; | |
e4e87715 PL |
4830 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG1_EN_B, |
4831 | vcfg->strip_tag1_en ? 1 : 0); | |
4832 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_REM_TAG2_EN_B, | |
4833 | vcfg->strip_tag2_en ? 1 : 0); | |
4834 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG1_EN_B, | |
4835 | vcfg->vlan1_vlan_prionly ? 1 : 0); | |
4836 | hnae3_set_bit(req->vport_vlan_cfg, HCLGE_SHOW_TAG2_EN_B, | |
4837 | vcfg->vlan2_vlan_prionly ? 1 : 0); | |
5f6ea83f PL |
4838 | |
4839 | req->vf_offset = vport->vport_id / HCLGE_VF_NUM_PER_CMD; | |
4840 | req->vf_bitmap[req->vf_offset] = | |
4841 | 1 << (vport->vport_id % HCLGE_VF_NUM_PER_BYTE); | |
4842 | ||
4843 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4844 | if (status) | |
4845 | dev_err(&hdev->pdev->dev, | |
4846 | "Send port rxvlan cfg command fail, ret =%d\n", | |
4847 | status); | |
4848 | ||
4849 | return status; | |
4850 | } | |
4851 | ||
4852 | static int hclge_set_vlan_protocol_type(struct hclge_dev *hdev) | |
4853 | { | |
4854 | struct hclge_rx_vlan_type_cfg_cmd *rx_req; | |
4855 | struct hclge_tx_vlan_type_cfg_cmd *tx_req; | |
4856 | struct hclge_desc desc; | |
4857 | int status; | |
4858 | ||
4859 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_TYPE_ID, false); | |
4860 | rx_req = (struct hclge_rx_vlan_type_cfg_cmd *)desc.data; | |
4861 | rx_req->ot_fst_vlan_type = | |
4862 | cpu_to_le16(hdev->vlan_type_cfg.rx_ot_fst_vlan_type); | |
4863 | rx_req->ot_sec_vlan_type = | |
4864 | cpu_to_le16(hdev->vlan_type_cfg.rx_ot_sec_vlan_type); | |
4865 | rx_req->in_fst_vlan_type = | |
4866 | cpu_to_le16(hdev->vlan_type_cfg.rx_in_fst_vlan_type); | |
4867 | rx_req->in_sec_vlan_type = | |
4868 | cpu_to_le16(hdev->vlan_type_cfg.rx_in_sec_vlan_type); | |
4869 | ||
4870 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4871 | if (status) { | |
4872 | dev_err(&hdev->pdev->dev, | |
4873 | "Send rxvlan protocol type command fail, ret =%d\n", | |
4874 | status); | |
4875 | return status; | |
4876 | } | |
4877 | ||
4878 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MAC_VLAN_INSERT, false); | |
4879 | ||
4880 | tx_req = (struct hclge_tx_vlan_type_cfg_cmd *)&desc.data; | |
4881 | tx_req->ot_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_ot_vlan_type); | |
4882 | tx_req->in_vlan_type = cpu_to_le16(hdev->vlan_type_cfg.tx_in_vlan_type); | |
4883 | ||
4884 | status = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4885 | if (status) | |
4886 | dev_err(&hdev->pdev->dev, | |
4887 | "Send txvlan protocol type command fail, ret =%d\n", | |
4888 | status); | |
4889 | ||
4890 | return status; | |
4891 | } | |
4892 | ||
46a3df9f S |
4893 | static int hclge_init_vlan_config(struct hclge_dev *hdev) |
4894 | { | |
5f6ea83f PL |
4895 | #define HCLGE_DEF_VLAN_TYPE 0x8100 |
4896 | ||
5e43aef8 | 4897 | struct hnae3_handle *handle; |
5f6ea83f | 4898 | struct hclge_vport *vport; |
46a3df9f | 4899 | int ret; |
5f6ea83f PL |
4900 | int i; |
4901 | ||
4902 | ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_VF, true); | |
4903 | if (ret) | |
4904 | return ret; | |
46a3df9f | 4905 | |
5f6ea83f | 4906 | ret = hclge_set_vlan_filter_ctrl(hdev, HCLGE_FILTER_TYPE_PORT, true); |
46a3df9f S |
4907 | if (ret) |
4908 | return ret; | |
4909 | ||
5f6ea83f PL |
4910 | hdev->vlan_type_cfg.rx_in_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; |
4911 | hdev->vlan_type_cfg.rx_in_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4912 | hdev->vlan_type_cfg.rx_ot_fst_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4913 | hdev->vlan_type_cfg.rx_ot_sec_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4914 | hdev->vlan_type_cfg.tx_ot_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4915 | hdev->vlan_type_cfg.tx_in_vlan_type = HCLGE_DEF_VLAN_TYPE; | |
4916 | ||
4917 | ret = hclge_set_vlan_protocol_type(hdev); | |
5e43aef8 L |
4918 | if (ret) |
4919 | return ret; | |
46a3df9f | 4920 | |
5f6ea83f PL |
4921 | for (i = 0; i < hdev->num_alloc_vport; i++) { |
4922 | vport = &hdev->vport[i]; | |
dcb35cce PL |
4923 | vport->txvlan_cfg.accept_tag1 = true; |
4924 | vport->txvlan_cfg.accept_untag1 = true; | |
4925 | ||
4926 | /* accept_tag2 and accept_untag2 are not supported on | |
4927 | * pdev revision(0x20), new revision support them. The | |
4928 | * value of this two fields will not return error when driver | |
4929 | * send command to fireware in revision(0x20). | |
4930 | * This two fields can not configured by user. | |
4931 | */ | |
4932 | vport->txvlan_cfg.accept_tag2 = true; | |
4933 | vport->txvlan_cfg.accept_untag2 = true; | |
4934 | ||
5f6ea83f PL |
4935 | vport->txvlan_cfg.insert_tag1_en = false; |
4936 | vport->txvlan_cfg.insert_tag2_en = false; | |
4937 | vport->txvlan_cfg.default_tag1 = 0; | |
4938 | vport->txvlan_cfg.default_tag2 = 0; | |
4939 | ||
4940 | ret = hclge_set_vlan_tx_offload_cfg(vport); | |
4941 | if (ret) | |
4942 | return ret; | |
4943 | ||
4944 | vport->rxvlan_cfg.strip_tag1_en = false; | |
4945 | vport->rxvlan_cfg.strip_tag2_en = true; | |
4946 | vport->rxvlan_cfg.vlan1_vlan_prionly = false; | |
4947 | vport->rxvlan_cfg.vlan2_vlan_prionly = false; | |
4948 | ||
4949 | ret = hclge_set_vlan_rx_offload_cfg(vport); | |
4950 | if (ret) | |
4951 | return ret; | |
4952 | } | |
4953 | ||
5e43aef8 | 4954 | handle = &hdev->vport[0].nic; |
dc8131d8 | 4955 | return hclge_set_vlan_filter(handle, htons(ETH_P_8021Q), 0, false); |
46a3df9f S |
4956 | } |
4957 | ||
b2641e2a | 4958 | int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable) |
052ece6d PL |
4959 | { |
4960 | struct hclge_vport *vport = hclge_get_vport(handle); | |
4961 | ||
4962 | vport->rxvlan_cfg.strip_tag1_en = false; | |
4963 | vport->rxvlan_cfg.strip_tag2_en = enable; | |
4964 | vport->rxvlan_cfg.vlan1_vlan_prionly = false; | |
4965 | vport->rxvlan_cfg.vlan2_vlan_prionly = false; | |
4966 | ||
4967 | return hclge_set_vlan_rx_offload_cfg(vport); | |
4968 | } | |
4969 | ||
dd72140c | 4970 | static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mtu) |
46a3df9f | 4971 | { |
d44f9b63 | 4972 | struct hclge_config_max_frm_size_cmd *req; |
46a3df9f | 4973 | struct hclge_desc desc; |
2866ccb2 | 4974 | int max_frm_size; |
46a3df9f S |
4975 | int ret; |
4976 | ||
2866ccb2 FL |
4977 | max_frm_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; |
4978 | ||
4979 | if (max_frm_size < HCLGE_MAC_MIN_FRAME || | |
4980 | max_frm_size > HCLGE_MAC_MAX_FRAME) | |
46a3df9f S |
4981 | return -EINVAL; |
4982 | ||
2866ccb2 FL |
4983 | max_frm_size = max(max_frm_size, HCLGE_MAC_DEFAULT_FRAME); |
4984 | ||
46a3df9f S |
4985 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_MAX_FRM_SIZE, false); |
4986 | ||
d44f9b63 | 4987 | req = (struct hclge_config_max_frm_size_cmd *)desc.data; |
2866ccb2 | 4988 | req->max_frm_size = cpu_to_le16(max_frm_size); |
8fc7346c | 4989 | req->min_frm_size = HCLGE_MAC_MIN_FRAME; |
46a3df9f S |
4990 | |
4991 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
4992 | if (ret) { | |
4993 | dev_err(&hdev->pdev->dev, "set mtu fail, ret =%d.\n", ret); | |
4994 | return ret; | |
4995 | } | |
4996 | ||
2866ccb2 FL |
4997 | hdev->mps = max_frm_size; |
4998 | ||
46a3df9f S |
4999 | return 0; |
5000 | } | |
5001 | ||
dd72140c FL |
5002 | static int hclge_set_mtu(struct hnae3_handle *handle, int new_mtu) |
5003 | { | |
5004 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5005 | struct hclge_dev *hdev = vport->back; | |
5006 | int ret; | |
5007 | ||
5008 | ret = hclge_set_mac_mtu(hdev, new_mtu); | |
5009 | if (ret) { | |
5010 | dev_err(&hdev->pdev->dev, | |
5011 | "Change mtu fail, ret =%d\n", ret); | |
5012 | return ret; | |
5013 | } | |
5014 | ||
5015 | ret = hclge_buffer_alloc(hdev); | |
5016 | if (ret) | |
5017 | dev_err(&hdev->pdev->dev, | |
5018 | "Allocate buffer fail, ret =%d\n", ret); | |
5019 | ||
5020 | return ret; | |
5021 | } | |
5022 | ||
46a3df9f S |
5023 | static int hclge_send_reset_tqp_cmd(struct hclge_dev *hdev, u16 queue_id, |
5024 | bool enable) | |
5025 | { | |
d44f9b63 | 5026 | struct hclge_reset_tqp_queue_cmd *req; |
46a3df9f S |
5027 | struct hclge_desc desc; |
5028 | int ret; | |
5029 | ||
5030 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, false); | |
5031 | ||
d44f9b63 | 5032 | req = (struct hclge_reset_tqp_queue_cmd *)desc.data; |
46a3df9f | 5033 | req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); |
e4e87715 | 5034 | hnae3_set_bit(req->reset_req, HCLGE_TQP_RESET_B, enable); |
46a3df9f S |
5035 | |
5036 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
5037 | if (ret) { | |
5038 | dev_err(&hdev->pdev->dev, | |
5039 | "Send tqp reset cmd error, status =%d\n", ret); | |
5040 | return ret; | |
5041 | } | |
5042 | ||
5043 | return 0; | |
5044 | } | |
5045 | ||
5046 | static int hclge_get_reset_status(struct hclge_dev *hdev, u16 queue_id) | |
5047 | { | |
d44f9b63 | 5048 | struct hclge_reset_tqp_queue_cmd *req; |
46a3df9f S |
5049 | struct hclge_desc desc; |
5050 | int ret; | |
5051 | ||
5052 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RESET_TQP_QUEUE, true); | |
5053 | ||
d44f9b63 | 5054 | req = (struct hclge_reset_tqp_queue_cmd *)desc.data; |
46a3df9f S |
5055 | req->tqp_id = cpu_to_le16(queue_id & HCLGE_RING_ID_MASK); |
5056 | ||
5057 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
5058 | if (ret) { | |
5059 | dev_err(&hdev->pdev->dev, | |
5060 | "Get reset status error, status =%d\n", ret); | |
5061 | return ret; | |
5062 | } | |
5063 | ||
e4e87715 | 5064 | return hnae3_get_bit(req->ready_to_reset, HCLGE_TQP_RESET_B); |
46a3df9f S |
5065 | } |
5066 | ||
814e0274 PL |
5067 | static u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, |
5068 | u16 queue_id) | |
5069 | { | |
5070 | struct hnae3_queue *queue; | |
5071 | struct hclge_tqp *tqp; | |
5072 | ||
5073 | queue = handle->kinfo.tqp[queue_id]; | |
5074 | tqp = container_of(queue, struct hclge_tqp, q); | |
5075 | ||
5076 | return tqp->index; | |
5077 | } | |
5078 | ||
84e095d6 | 5079 | void hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id) |
46a3df9f S |
5080 | { |
5081 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5082 | struct hclge_dev *hdev = vport->back; | |
5083 | int reset_try_times = 0; | |
5084 | int reset_status; | |
814e0274 | 5085 | u16 queue_gid; |
46a3df9f S |
5086 | int ret; |
5087 | ||
b50ae26c PL |
5088 | if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state)) |
5089 | return; | |
5090 | ||
814e0274 PL |
5091 | queue_gid = hclge_covert_handle_qid_global(handle, queue_id); |
5092 | ||
46a3df9f S |
5093 | ret = hclge_tqp_enable(hdev, queue_id, 0, false); |
5094 | if (ret) { | |
5095 | dev_warn(&hdev->pdev->dev, "Disable tqp fail, ret = %d\n", ret); | |
5096 | return; | |
5097 | } | |
5098 | ||
814e0274 | 5099 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); |
46a3df9f S |
5100 | if (ret) { |
5101 | dev_warn(&hdev->pdev->dev, | |
5102 | "Send reset tqp cmd fail, ret = %d\n", ret); | |
5103 | return; | |
5104 | } | |
5105 | ||
5106 | reset_try_times = 0; | |
5107 | while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { | |
5108 | /* Wait for tqp hw reset */ | |
5109 | msleep(20); | |
814e0274 | 5110 | reset_status = hclge_get_reset_status(hdev, queue_gid); |
46a3df9f S |
5111 | if (reset_status) |
5112 | break; | |
5113 | } | |
5114 | ||
5115 | if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { | |
5116 | dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); | |
5117 | return; | |
5118 | } | |
5119 | ||
814e0274 | 5120 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); |
46a3df9f S |
5121 | if (ret) { |
5122 | dev_warn(&hdev->pdev->dev, | |
5123 | "Deassert the soft reset fail, ret = %d\n", ret); | |
5124 | return; | |
5125 | } | |
5126 | } | |
5127 | ||
1a426f8b PL |
5128 | void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id) |
5129 | { | |
5130 | struct hclge_dev *hdev = vport->back; | |
5131 | int reset_try_times = 0; | |
5132 | int reset_status; | |
5133 | u16 queue_gid; | |
5134 | int ret; | |
5135 | ||
5136 | queue_gid = hclge_covert_handle_qid_global(&vport->nic, queue_id); | |
5137 | ||
5138 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, true); | |
5139 | if (ret) { | |
5140 | dev_warn(&hdev->pdev->dev, | |
5141 | "Send reset tqp cmd fail, ret = %d\n", ret); | |
5142 | return; | |
5143 | } | |
5144 | ||
5145 | reset_try_times = 0; | |
5146 | while (reset_try_times++ < HCLGE_TQP_RESET_TRY_TIMES) { | |
5147 | /* Wait for tqp hw reset */ | |
5148 | msleep(20); | |
5149 | reset_status = hclge_get_reset_status(hdev, queue_gid); | |
5150 | if (reset_status) | |
5151 | break; | |
5152 | } | |
5153 | ||
5154 | if (reset_try_times >= HCLGE_TQP_RESET_TRY_TIMES) { | |
5155 | dev_warn(&hdev->pdev->dev, "Reset TQP fail\n"); | |
5156 | return; | |
5157 | } | |
5158 | ||
5159 | ret = hclge_send_reset_tqp_cmd(hdev, queue_gid, false); | |
5160 | if (ret) | |
5161 | dev_warn(&hdev->pdev->dev, | |
5162 | "Deassert the soft reset fail, ret = %d\n", ret); | |
5163 | } | |
5164 | ||
46a3df9f S |
5165 | static u32 hclge_get_fw_version(struct hnae3_handle *handle) |
5166 | { | |
5167 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5168 | struct hclge_dev *hdev = vport->back; | |
5169 | ||
5170 | return hdev->fw_version; | |
5171 | } | |
5172 | ||
f34ffffd PL |
5173 | static void hclge_get_flowctrl_adv(struct hnae3_handle *handle, |
5174 | u32 *flowctrl_adv) | |
5175 | { | |
5176 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5177 | struct hclge_dev *hdev = vport->back; | |
5178 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5179 | ||
5180 | if (!phydev) | |
5181 | return; | |
5182 | ||
5183 | *flowctrl_adv |= (phydev->advertising & ADVERTISED_Pause) | | |
5184 | (phydev->advertising & ADVERTISED_Asym_Pause); | |
5185 | } | |
5186 | ||
61387774 PL |
5187 | static void hclge_set_flowctrl_adv(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) |
5188 | { | |
5189 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5190 | ||
5191 | if (!phydev) | |
5192 | return; | |
5193 | ||
5194 | phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause); | |
5195 | ||
5196 | if (rx_en) | |
5197 | phydev->advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause; | |
5198 | ||
5199 | if (tx_en) | |
5200 | phydev->advertising ^= ADVERTISED_Asym_Pause; | |
5201 | } | |
5202 | ||
5203 | static int hclge_cfg_pauseparam(struct hclge_dev *hdev, u32 rx_en, u32 tx_en) | |
5204 | { | |
61387774 PL |
5205 | int ret; |
5206 | ||
5207 | if (rx_en && tx_en) | |
40173a2e | 5208 | hdev->fc_mode_last_time = HCLGE_FC_FULL; |
61387774 | 5209 | else if (rx_en && !tx_en) |
40173a2e | 5210 | hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE; |
61387774 | 5211 | else if (!rx_en && tx_en) |
40173a2e | 5212 | hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE; |
61387774 | 5213 | else |
40173a2e | 5214 | hdev->fc_mode_last_time = HCLGE_FC_NONE; |
61387774 | 5215 | |
40173a2e | 5216 | if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) |
61387774 | 5217 | return 0; |
61387774 PL |
5218 | |
5219 | ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en); | |
5220 | if (ret) { | |
5221 | dev_err(&hdev->pdev->dev, "configure pauseparam error, ret = %d.\n", | |
5222 | ret); | |
5223 | return ret; | |
5224 | } | |
5225 | ||
40173a2e | 5226 | hdev->tm_info.fc_mode = hdev->fc_mode_last_time; |
61387774 PL |
5227 | |
5228 | return 0; | |
5229 | } | |
5230 | ||
1770a7a3 PL |
5231 | int hclge_cfg_flowctrl(struct hclge_dev *hdev) |
5232 | { | |
5233 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5234 | u16 remote_advertising = 0; | |
5235 | u16 local_advertising = 0; | |
5236 | u32 rx_pause, tx_pause; | |
5237 | u8 flowctl; | |
5238 | ||
5239 | if (!phydev->link || !phydev->autoneg) | |
5240 | return 0; | |
5241 | ||
5242 | if (phydev->advertising & ADVERTISED_Pause) | |
5243 | local_advertising = ADVERTISE_PAUSE_CAP; | |
5244 | ||
5245 | if (phydev->advertising & ADVERTISED_Asym_Pause) | |
5246 | local_advertising |= ADVERTISE_PAUSE_ASYM; | |
5247 | ||
5248 | if (phydev->pause) | |
5249 | remote_advertising = LPA_PAUSE_CAP; | |
5250 | ||
5251 | if (phydev->asym_pause) | |
5252 | remote_advertising |= LPA_PAUSE_ASYM; | |
5253 | ||
5254 | flowctl = mii_resolve_flowctrl_fdx(local_advertising, | |
5255 | remote_advertising); | |
5256 | tx_pause = flowctl & FLOW_CTRL_TX; | |
5257 | rx_pause = flowctl & FLOW_CTRL_RX; | |
5258 | ||
5259 | if (phydev->duplex == HCLGE_MAC_HALF) { | |
5260 | tx_pause = 0; | |
5261 | rx_pause = 0; | |
5262 | } | |
5263 | ||
5264 | return hclge_cfg_pauseparam(hdev, rx_pause, tx_pause); | |
5265 | } | |
5266 | ||
46a3df9f S |
5267 | static void hclge_get_pauseparam(struct hnae3_handle *handle, u32 *auto_neg, |
5268 | u32 *rx_en, u32 *tx_en) | |
5269 | { | |
5270 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5271 | struct hclge_dev *hdev = vport->back; | |
5272 | ||
5273 | *auto_neg = hclge_get_autoneg(handle); | |
5274 | ||
5275 | if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { | |
5276 | *rx_en = 0; | |
5277 | *tx_en = 0; | |
5278 | return; | |
5279 | } | |
5280 | ||
5281 | if (hdev->tm_info.fc_mode == HCLGE_FC_RX_PAUSE) { | |
5282 | *rx_en = 1; | |
5283 | *tx_en = 0; | |
5284 | } else if (hdev->tm_info.fc_mode == HCLGE_FC_TX_PAUSE) { | |
5285 | *tx_en = 1; | |
5286 | *rx_en = 0; | |
5287 | } else if (hdev->tm_info.fc_mode == HCLGE_FC_FULL) { | |
5288 | *rx_en = 1; | |
5289 | *tx_en = 1; | |
5290 | } else { | |
5291 | *rx_en = 0; | |
5292 | *tx_en = 0; | |
5293 | } | |
5294 | } | |
5295 | ||
61387774 PL |
5296 | static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg, |
5297 | u32 rx_en, u32 tx_en) | |
5298 | { | |
5299 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5300 | struct hclge_dev *hdev = vport->back; | |
5301 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5302 | u32 fc_autoneg; | |
5303 | ||
61387774 PL |
5304 | fc_autoneg = hclge_get_autoneg(handle); |
5305 | if (auto_neg != fc_autoneg) { | |
5306 | dev_info(&hdev->pdev->dev, | |
5307 | "To change autoneg please use: ethtool -s <dev> autoneg <on|off>\n"); | |
5308 | return -EOPNOTSUPP; | |
5309 | } | |
5310 | ||
5311 | if (hdev->tm_info.fc_mode == HCLGE_FC_PFC) { | |
5312 | dev_info(&hdev->pdev->dev, | |
5313 | "Priority flow control enabled. Cannot set link flow control.\n"); | |
5314 | return -EOPNOTSUPP; | |
5315 | } | |
5316 | ||
5317 | hclge_set_flowctrl_adv(hdev, rx_en, tx_en); | |
5318 | ||
5319 | if (!fc_autoneg) | |
5320 | return hclge_cfg_pauseparam(hdev, rx_en, tx_en); | |
5321 | ||
0c963e8c FL |
5322 | /* Only support flow control negotiation for netdev with |
5323 | * phy attached for now. | |
5324 | */ | |
5325 | if (!phydev) | |
5326 | return -EOPNOTSUPP; | |
5327 | ||
61387774 PL |
5328 | return phy_start_aneg(phydev); |
5329 | } | |
5330 | ||
46a3df9f S |
5331 | static void hclge_get_ksettings_an_result(struct hnae3_handle *handle, |
5332 | u8 *auto_neg, u32 *speed, u8 *duplex) | |
5333 | { | |
5334 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5335 | struct hclge_dev *hdev = vport->back; | |
5336 | ||
5337 | if (speed) | |
5338 | *speed = hdev->hw.mac.speed; | |
5339 | if (duplex) | |
5340 | *duplex = hdev->hw.mac.duplex; | |
5341 | if (auto_neg) | |
5342 | *auto_neg = hdev->hw.mac.autoneg; | |
5343 | } | |
5344 | ||
5345 | static void hclge_get_media_type(struct hnae3_handle *handle, u8 *media_type) | |
5346 | { | |
5347 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5348 | struct hclge_dev *hdev = vport->back; | |
5349 | ||
5350 | if (media_type) | |
5351 | *media_type = hdev->hw.mac.media_type; | |
5352 | } | |
5353 | ||
5354 | static void hclge_get_mdix_mode(struct hnae3_handle *handle, | |
5355 | u8 *tp_mdix_ctrl, u8 *tp_mdix) | |
5356 | { | |
5357 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5358 | struct hclge_dev *hdev = vport->back; | |
5359 | struct phy_device *phydev = hdev->hw.mac.phydev; | |
5360 | int mdix_ctrl, mdix, retval, is_resolved; | |
5361 | ||
5362 | if (!phydev) { | |
5363 | *tp_mdix_ctrl = ETH_TP_MDI_INVALID; | |
5364 | *tp_mdix = ETH_TP_MDI_INVALID; | |
5365 | return; | |
5366 | } | |
5367 | ||
5368 | phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_MDIX); | |
5369 | ||
5370 | retval = phy_read(phydev, HCLGE_PHY_CSC_REG); | |
e4e87715 PL |
5371 | mdix_ctrl = hnae3_get_field(retval, HCLGE_PHY_MDIX_CTRL_M, |
5372 | HCLGE_PHY_MDIX_CTRL_S); | |
46a3df9f S |
5373 | |
5374 | retval = phy_read(phydev, HCLGE_PHY_CSS_REG); | |
e4e87715 PL |
5375 | mdix = hnae3_get_bit(retval, HCLGE_PHY_MDIX_STATUS_B); |
5376 | is_resolved = hnae3_get_bit(retval, HCLGE_PHY_SPEED_DUP_RESOLVE_B); | |
46a3df9f S |
5377 | |
5378 | phy_write(phydev, HCLGE_PHY_PAGE_REG, HCLGE_PHY_PAGE_COPPER); | |
5379 | ||
5380 | switch (mdix_ctrl) { | |
5381 | case 0x0: | |
5382 | *tp_mdix_ctrl = ETH_TP_MDI; | |
5383 | break; | |
5384 | case 0x1: | |
5385 | *tp_mdix_ctrl = ETH_TP_MDI_X; | |
5386 | break; | |
5387 | case 0x3: | |
5388 | *tp_mdix_ctrl = ETH_TP_MDI_AUTO; | |
5389 | break; | |
5390 | default: | |
5391 | *tp_mdix_ctrl = ETH_TP_MDI_INVALID; | |
5392 | break; | |
5393 | } | |
5394 | ||
5395 | if (!is_resolved) | |
5396 | *tp_mdix = ETH_TP_MDI_INVALID; | |
5397 | else if (mdix) | |
5398 | *tp_mdix = ETH_TP_MDI_X; | |
5399 | else | |
5400 | *tp_mdix = ETH_TP_MDI; | |
5401 | } | |
5402 | ||
5403 | static int hclge_init_client_instance(struct hnae3_client *client, | |
5404 | struct hnae3_ae_dev *ae_dev) | |
5405 | { | |
5406 | struct hclge_dev *hdev = ae_dev->priv; | |
5407 | struct hclge_vport *vport; | |
5408 | int i, ret; | |
5409 | ||
5410 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { | |
5411 | vport = &hdev->vport[i]; | |
5412 | ||
5413 | switch (client->type) { | |
5414 | case HNAE3_CLIENT_KNIC: | |
5415 | ||
5416 | hdev->nic_client = client; | |
5417 | vport->nic.client = client; | |
5418 | ret = client->ops->init_instance(&vport->nic); | |
5419 | if (ret) | |
99a6993a | 5420 | return ret; |
46a3df9f S |
5421 | |
5422 | if (hdev->roce_client && | |
e92a0843 | 5423 | hnae3_dev_roce_supported(hdev)) { |
46a3df9f S |
5424 | struct hnae3_client *rc = hdev->roce_client; |
5425 | ||
5426 | ret = hclge_init_roce_base_info(vport); | |
5427 | if (ret) | |
99a6993a | 5428 | return ret; |
46a3df9f S |
5429 | |
5430 | ret = rc->ops->init_instance(&vport->roce); | |
5431 | if (ret) | |
99a6993a | 5432 | return ret; |
46a3df9f S |
5433 | } |
5434 | ||
5435 | break; | |
5436 | case HNAE3_CLIENT_UNIC: | |
5437 | hdev->nic_client = client; | |
5438 | vport->nic.client = client; | |
5439 | ||
5440 | ret = client->ops->init_instance(&vport->nic); | |
5441 | if (ret) | |
99a6993a | 5442 | return ret; |
46a3df9f S |
5443 | |
5444 | break; | |
5445 | case HNAE3_CLIENT_ROCE: | |
e92a0843 | 5446 | if (hnae3_dev_roce_supported(hdev)) { |
46a3df9f S |
5447 | hdev->roce_client = client; |
5448 | vport->roce.client = client; | |
5449 | } | |
5450 | ||
3a46f34d | 5451 | if (hdev->roce_client && hdev->nic_client) { |
46a3df9f S |
5452 | ret = hclge_init_roce_base_info(vport); |
5453 | if (ret) | |
99a6993a | 5454 | return ret; |
46a3df9f S |
5455 | |
5456 | ret = client->ops->init_instance(&vport->roce); | |
5457 | if (ret) | |
99a6993a | 5458 | return ret; |
46a3df9f S |
5459 | } |
5460 | } | |
5461 | } | |
5462 | ||
5463 | return 0; | |
46a3df9f S |
5464 | } |
5465 | ||
5466 | static void hclge_uninit_client_instance(struct hnae3_client *client, | |
5467 | struct hnae3_ae_dev *ae_dev) | |
5468 | { | |
5469 | struct hclge_dev *hdev = ae_dev->priv; | |
5470 | struct hclge_vport *vport; | |
5471 | int i; | |
5472 | ||
5473 | for (i = 0; i < hdev->num_vmdq_vport + 1; i++) { | |
5474 | vport = &hdev->vport[i]; | |
a17dcf3f | 5475 | if (hdev->roce_client) { |
46a3df9f S |
5476 | hdev->roce_client->ops->uninit_instance(&vport->roce, |
5477 | 0); | |
a17dcf3f L |
5478 | hdev->roce_client = NULL; |
5479 | vport->roce.client = NULL; | |
5480 | } | |
46a3df9f S |
5481 | if (client->type == HNAE3_CLIENT_ROCE) |
5482 | return; | |
a17dcf3f | 5483 | if (client->ops->uninit_instance) { |
46a3df9f | 5484 | client->ops->uninit_instance(&vport->nic, 0); |
a17dcf3f L |
5485 | hdev->nic_client = NULL; |
5486 | vport->nic.client = NULL; | |
5487 | } | |
46a3df9f S |
5488 | } |
5489 | } | |
5490 | ||
5491 | static int hclge_pci_init(struct hclge_dev *hdev) | |
5492 | { | |
5493 | struct pci_dev *pdev = hdev->pdev; | |
5494 | struct hclge_hw *hw; | |
5495 | int ret; | |
5496 | ||
5497 | ret = pci_enable_device(pdev); | |
5498 | if (ret) { | |
5499 | dev_err(&pdev->dev, "failed to enable PCI device\n"); | |
3e249d3b | 5500 | return ret; |
46a3df9f S |
5501 | } |
5502 | ||
5503 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); | |
5504 | if (ret) { | |
5505 | ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); | |
5506 | if (ret) { | |
5507 | dev_err(&pdev->dev, | |
5508 | "can't set consistent PCI DMA"); | |
5509 | goto err_disable_device; | |
5510 | } | |
5511 | dev_warn(&pdev->dev, "set DMA mask to 32 bits\n"); | |
5512 | } | |
5513 | ||
5514 | ret = pci_request_regions(pdev, HCLGE_DRIVER_NAME); | |
5515 | if (ret) { | |
5516 | dev_err(&pdev->dev, "PCI request regions failed %d\n", ret); | |
5517 | goto err_disable_device; | |
5518 | } | |
5519 | ||
5520 | pci_set_master(pdev); | |
5521 | hw = &hdev->hw; | |
46a3df9f S |
5522 | hw->io_base = pcim_iomap(pdev, 2, 0); |
5523 | if (!hw->io_base) { | |
5524 | dev_err(&pdev->dev, "Can't map configuration register space\n"); | |
5525 | ret = -ENOMEM; | |
5526 | goto err_clr_master; | |
5527 | } | |
5528 | ||
709eb41a L |
5529 | hdev->num_req_vfs = pci_sriov_get_totalvfs(pdev); |
5530 | ||
46a3df9f S |
5531 | return 0; |
5532 | err_clr_master: | |
5533 | pci_clear_master(pdev); | |
5534 | pci_release_regions(pdev); | |
5535 | err_disable_device: | |
5536 | pci_disable_device(pdev); | |
46a3df9f S |
5537 | |
5538 | return ret; | |
5539 | } | |
5540 | ||
5541 | static void hclge_pci_uninit(struct hclge_dev *hdev) | |
5542 | { | |
5543 | struct pci_dev *pdev = hdev->pdev; | |
5544 | ||
6a814413 | 5545 | pcim_iounmap(pdev, hdev->hw.io_base); |
887c3820 | 5546 | pci_free_irq_vectors(pdev); |
46a3df9f S |
5547 | pci_clear_master(pdev); |
5548 | pci_release_mem_regions(pdev); | |
5549 | pci_disable_device(pdev); | |
5550 | } | |
5551 | ||
48569cda PL |
5552 | static void hclge_state_init(struct hclge_dev *hdev) |
5553 | { | |
5554 | set_bit(HCLGE_STATE_SERVICE_INITED, &hdev->state); | |
5555 | set_bit(HCLGE_STATE_DOWN, &hdev->state); | |
5556 | clear_bit(HCLGE_STATE_RST_SERVICE_SCHED, &hdev->state); | |
5557 | clear_bit(HCLGE_STATE_RST_HANDLING, &hdev->state); | |
5558 | clear_bit(HCLGE_STATE_MBX_SERVICE_SCHED, &hdev->state); | |
5559 | clear_bit(HCLGE_STATE_MBX_HANDLING, &hdev->state); | |
5560 | } | |
5561 | ||
5562 | static void hclge_state_uninit(struct hclge_dev *hdev) | |
5563 | { | |
5564 | set_bit(HCLGE_STATE_DOWN, &hdev->state); | |
5565 | ||
5566 | if (hdev->service_timer.function) | |
5567 | del_timer_sync(&hdev->service_timer); | |
5568 | if (hdev->service_task.func) | |
5569 | cancel_work_sync(&hdev->service_task); | |
5570 | if (hdev->rst_service_task.func) | |
5571 | cancel_work_sync(&hdev->rst_service_task); | |
5572 | if (hdev->mbx_service_task.func) | |
5573 | cancel_work_sync(&hdev->mbx_service_task); | |
5574 | } | |
5575 | ||
46a3df9f S |
5576 | static int hclge_init_ae_dev(struct hnae3_ae_dev *ae_dev) |
5577 | { | |
5578 | struct pci_dev *pdev = ae_dev->pdev; | |
46a3df9f S |
5579 | struct hclge_dev *hdev; |
5580 | int ret; | |
5581 | ||
5582 | hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); | |
5583 | if (!hdev) { | |
5584 | ret = -ENOMEM; | |
ffd5656e | 5585 | goto out; |
46a3df9f S |
5586 | } |
5587 | ||
46a3df9f S |
5588 | hdev->pdev = pdev; |
5589 | hdev->ae_dev = ae_dev; | |
4ed340ab | 5590 | hdev->reset_type = HNAE3_NONE_RESET; |
cb1b9f77 | 5591 | hdev->reset_request = 0; |
ca1d7669 | 5592 | hdev->reset_pending = 0; |
46a3df9f S |
5593 | ae_dev->priv = hdev; |
5594 | ||
46a3df9f S |
5595 | ret = hclge_pci_init(hdev); |
5596 | if (ret) { | |
5597 | dev_err(&pdev->dev, "PCI init failed\n"); | |
ffd5656e | 5598 | goto out; |
46a3df9f S |
5599 | } |
5600 | ||
3efb960f L |
5601 | /* Firmware command queue initialize */ |
5602 | ret = hclge_cmd_queue_init(hdev); | |
5603 | if (ret) { | |
5604 | dev_err(&pdev->dev, "Cmd queue init failed, ret = %d.\n", ret); | |
ffd5656e | 5605 | goto err_pci_uninit; |
3efb960f L |
5606 | } |
5607 | ||
5608 | /* Firmware command initialize */ | |
46a3df9f S |
5609 | ret = hclge_cmd_init(hdev); |
5610 | if (ret) | |
ffd5656e | 5611 | goto err_cmd_uninit; |
46a3df9f S |
5612 | |
5613 | ret = hclge_get_cap(hdev); | |
5614 | if (ret) { | |
e00e2197 CIK |
5615 | dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", |
5616 | ret); | |
ffd5656e | 5617 | goto err_cmd_uninit; |
46a3df9f S |
5618 | } |
5619 | ||
5620 | ret = hclge_configure(hdev); | |
5621 | if (ret) { | |
5622 | dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); | |
ffd5656e | 5623 | goto err_cmd_uninit; |
46a3df9f S |
5624 | } |
5625 | ||
887c3820 | 5626 | ret = hclge_init_msi(hdev); |
46a3df9f | 5627 | if (ret) { |
887c3820 | 5628 | dev_err(&pdev->dev, "Init MSI/MSI-X error, ret = %d.\n", ret); |
ffd5656e | 5629 | goto err_cmd_uninit; |
46a3df9f S |
5630 | } |
5631 | ||
466b0c00 L |
5632 | ret = hclge_misc_irq_init(hdev); |
5633 | if (ret) { | |
5634 | dev_err(&pdev->dev, | |
5635 | "Misc IRQ(vector0) init error, ret = %d.\n", | |
5636 | ret); | |
ffd5656e | 5637 | goto err_msi_uninit; |
466b0c00 L |
5638 | } |
5639 | ||
46a3df9f S |
5640 | ret = hclge_alloc_tqps(hdev); |
5641 | if (ret) { | |
5642 | dev_err(&pdev->dev, "Allocate TQPs error, ret = %d.\n", ret); | |
ffd5656e | 5643 | goto err_msi_irq_uninit; |
46a3df9f S |
5644 | } |
5645 | ||
5646 | ret = hclge_alloc_vport(hdev); | |
5647 | if (ret) { | |
5648 | dev_err(&pdev->dev, "Allocate vport error, ret = %d.\n", ret); | |
ffd5656e | 5649 | goto err_msi_irq_uninit; |
46a3df9f S |
5650 | } |
5651 | ||
7df7dad6 L |
5652 | ret = hclge_map_tqp(hdev); |
5653 | if (ret) { | |
5654 | dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); | |
2312e050 | 5655 | goto err_msi_irq_uninit; |
7df7dad6 L |
5656 | } |
5657 | ||
c5ef83cb HT |
5658 | if (hdev->hw.mac.media_type == HNAE3_MEDIA_TYPE_COPPER) { |
5659 | ret = hclge_mac_mdio_config(hdev); | |
5660 | if (ret) { | |
5661 | dev_err(&hdev->pdev->dev, | |
5662 | "mdio config fail ret=%d\n", ret); | |
2312e050 | 5663 | goto err_msi_irq_uninit; |
c5ef83cb | 5664 | } |
cf9cca2d | 5665 | } |
5666 | ||
46a3df9f S |
5667 | ret = hclge_mac_init(hdev); |
5668 | if (ret) { | |
5669 | dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); | |
ffd5656e | 5670 | goto err_mdiobus_unreg; |
46a3df9f | 5671 | } |
46a3df9f S |
5672 | |
5673 | ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); | |
5674 | if (ret) { | |
5675 | dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); | |
ffd5656e | 5676 | goto err_mdiobus_unreg; |
46a3df9f S |
5677 | } |
5678 | ||
46a3df9f S |
5679 | ret = hclge_init_vlan_config(hdev); |
5680 | if (ret) { | |
5681 | dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); | |
ffd5656e | 5682 | goto err_mdiobus_unreg; |
46a3df9f S |
5683 | } |
5684 | ||
5685 | ret = hclge_tm_schd_init(hdev); | |
5686 | if (ret) { | |
5687 | dev_err(&pdev->dev, "tm schd init fail, ret =%d\n", ret); | |
ffd5656e | 5688 | goto err_mdiobus_unreg; |
68ece54e YL |
5689 | } |
5690 | ||
268f5dfa | 5691 | hclge_rss_init_cfg(hdev); |
68ece54e YL |
5692 | ret = hclge_rss_init_hw(hdev); |
5693 | if (ret) { | |
5694 | dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); | |
ffd5656e | 5695 | goto err_mdiobus_unreg; |
46a3df9f S |
5696 | } |
5697 | ||
f5aac71c FL |
5698 | ret = init_mgr_tbl(hdev); |
5699 | if (ret) { | |
5700 | dev_err(&pdev->dev, "manager table init fail, ret =%d\n", ret); | |
ffd5656e | 5701 | goto err_mdiobus_unreg; |
f5aac71c FL |
5702 | } |
5703 | ||
cacde272 YL |
5704 | hclge_dcb_ops_set(hdev); |
5705 | ||
d039ef68 | 5706 | timer_setup(&hdev->service_timer, hclge_service_timer, 0); |
46a3df9f | 5707 | INIT_WORK(&hdev->service_task, hclge_service_task); |
cb1b9f77 | 5708 | INIT_WORK(&hdev->rst_service_task, hclge_reset_service_task); |
c1a81619 | 5709 | INIT_WORK(&hdev->mbx_service_task, hclge_mailbox_service_task); |
46a3df9f | 5710 | |
8e52a602 XW |
5711 | hclge_clear_all_event_cause(hdev); |
5712 | ||
466b0c00 L |
5713 | /* Enable MISC vector(vector0) */ |
5714 | hclge_enable_vector(&hdev->misc_vector, true); | |
5715 | ||
48569cda | 5716 | hclge_state_init(hdev); |
46a3df9f S |
5717 | |
5718 | pr_info("%s driver initialization finished.\n", HCLGE_DRIVER_NAME); | |
5719 | return 0; | |
5720 | ||
ffd5656e HT |
5721 | err_mdiobus_unreg: |
5722 | if (hdev->hw.mac.phydev) | |
5723 | mdiobus_unregister(hdev->hw.mac.mdio_bus); | |
ffd5656e HT |
5724 | err_msi_irq_uninit: |
5725 | hclge_misc_irq_uninit(hdev); | |
5726 | err_msi_uninit: | |
5727 | pci_free_irq_vectors(pdev); | |
5728 | err_cmd_uninit: | |
5729 | hclge_destroy_cmd_queue(&hdev->hw); | |
5730 | err_pci_uninit: | |
6a814413 | 5731 | pcim_iounmap(pdev, hdev->hw.io_base); |
ffd5656e | 5732 | pci_clear_master(pdev); |
46a3df9f | 5733 | pci_release_regions(pdev); |
ffd5656e | 5734 | pci_disable_device(pdev); |
ffd5656e | 5735 | out: |
46a3df9f S |
5736 | return ret; |
5737 | } | |
5738 | ||
c6dc5213 | 5739 | static void hclge_stats_clear(struct hclge_dev *hdev) |
5740 | { | |
5741 | memset(&hdev->hw_stats, 0, sizeof(hdev->hw_stats)); | |
5742 | } | |
5743 | ||
4ed340ab L |
5744 | static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev) |
5745 | { | |
5746 | struct hclge_dev *hdev = ae_dev->priv; | |
5747 | struct pci_dev *pdev = ae_dev->pdev; | |
5748 | int ret; | |
5749 | ||
5750 | set_bit(HCLGE_STATE_DOWN, &hdev->state); | |
5751 | ||
c6dc5213 | 5752 | hclge_stats_clear(hdev); |
dc8131d8 | 5753 | memset(hdev->vlan_table, 0, sizeof(hdev->vlan_table)); |
c6dc5213 | 5754 | |
4ed340ab L |
5755 | ret = hclge_cmd_init(hdev); |
5756 | if (ret) { | |
5757 | dev_err(&pdev->dev, "Cmd queue init failed\n"); | |
5758 | return ret; | |
5759 | } | |
5760 | ||
5761 | ret = hclge_get_cap(hdev); | |
5762 | if (ret) { | |
5763 | dev_err(&pdev->dev, "get hw capability error, ret = %d.\n", | |
5764 | ret); | |
5765 | return ret; | |
5766 | } | |
5767 | ||
5768 | ret = hclge_configure(hdev); | |
5769 | if (ret) { | |
5770 | dev_err(&pdev->dev, "Configure dev error, ret = %d.\n", ret); | |
5771 | return ret; | |
5772 | } | |
5773 | ||
5774 | ret = hclge_map_tqp(hdev); | |
5775 | if (ret) { | |
5776 | dev_err(&pdev->dev, "Map tqp error, ret = %d.\n", ret); | |
5777 | return ret; | |
5778 | } | |
5779 | ||
5780 | ret = hclge_mac_init(hdev); | |
5781 | if (ret) { | |
5782 | dev_err(&pdev->dev, "Mac init error, ret = %d\n", ret); | |
5783 | return ret; | |
5784 | } | |
5785 | ||
4ed340ab L |
5786 | ret = hclge_config_tso(hdev, HCLGE_TSO_MSS_MIN, HCLGE_TSO_MSS_MAX); |
5787 | if (ret) { | |
5788 | dev_err(&pdev->dev, "Enable tso fail, ret =%d\n", ret); | |
5789 | return ret; | |
5790 | } | |
5791 | ||
5792 | ret = hclge_init_vlan_config(hdev); | |
5793 | if (ret) { | |
5794 | dev_err(&pdev->dev, "VLAN init fail, ret =%d\n", ret); | |
5795 | return ret; | |
5796 | } | |
5797 | ||
f31c1ba6 | 5798 | ret = hclge_tm_init_hw(hdev); |
4ed340ab | 5799 | if (ret) { |
f31c1ba6 | 5800 | dev_err(&pdev->dev, "tm init hw fail, ret =%d\n", ret); |
4ed340ab L |
5801 | return ret; |
5802 | } | |
5803 | ||
5804 | ret = hclge_rss_init_hw(hdev); | |
5805 | if (ret) { | |
5806 | dev_err(&pdev->dev, "Rss init fail, ret =%d\n", ret); | |
5807 | return ret; | |
5808 | } | |
5809 | ||
4ed340ab L |
5810 | dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n", |
5811 | HCLGE_DRIVER_NAME); | |
5812 | ||
5813 | return 0; | |
5814 | } | |
5815 | ||
46a3df9f S |
5816 | static void hclge_uninit_ae_dev(struct hnae3_ae_dev *ae_dev) |
5817 | { | |
5818 | struct hclge_dev *hdev = ae_dev->priv; | |
5819 | struct hclge_mac *mac = &hdev->hw.mac; | |
5820 | ||
48569cda | 5821 | hclge_state_uninit(hdev); |
46a3df9f S |
5822 | |
5823 | if (mac->phydev) | |
5824 | mdiobus_unregister(mac->mdio_bus); | |
5825 | ||
466b0c00 L |
5826 | /* Disable MISC vector(vector0) */ |
5827 | hclge_enable_vector(&hdev->misc_vector, false); | |
8e52a602 XW |
5828 | synchronize_irq(hdev->misc_vector.vector_irq); |
5829 | ||
46a3df9f | 5830 | hclge_destroy_cmd_queue(&hdev->hw); |
ca1d7669 | 5831 | hclge_misc_irq_uninit(hdev); |
46a3df9f S |
5832 | hclge_pci_uninit(hdev); |
5833 | ae_dev->priv = NULL; | |
5834 | } | |
5835 | ||
482d2e9c PL |
5836 | static u32 hclge_get_max_channels(struct hnae3_handle *handle) |
5837 | { | |
5838 | struct hnae3_knic_private_info *kinfo = &handle->kinfo; | |
5839 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5840 | struct hclge_dev *hdev = vport->back; | |
5841 | ||
5842 | return min_t(u32, hdev->rss_size_max * kinfo->num_tc, hdev->num_tqps); | |
5843 | } | |
5844 | ||
5845 | static void hclge_get_channels(struct hnae3_handle *handle, | |
5846 | struct ethtool_channels *ch) | |
5847 | { | |
5848 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5849 | ||
5850 | ch->max_combined = hclge_get_max_channels(handle); | |
5851 | ch->other_count = 1; | |
5852 | ch->max_other = 1; | |
5853 | ch->combined_count = vport->alloc_tqps; | |
5854 | } | |
5855 | ||
09f2af64 PL |
5856 | static void hclge_get_tqps_and_rss_info(struct hnae3_handle *handle, |
5857 | u16 *free_tqps, u16 *max_rss_size) | |
5858 | { | |
5859 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5860 | struct hclge_dev *hdev = vport->back; | |
5861 | u16 temp_tqps = 0; | |
5862 | int i; | |
5863 | ||
5864 | for (i = 0; i < hdev->num_tqps; i++) { | |
5865 | if (!hdev->htqp[i].alloced) | |
5866 | temp_tqps++; | |
5867 | } | |
5868 | *free_tqps = temp_tqps; | |
5869 | *max_rss_size = hdev->rss_size_max; | |
5870 | } | |
5871 | ||
5872 | static void hclge_release_tqp(struct hclge_vport *vport) | |
5873 | { | |
5874 | struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; | |
5875 | struct hclge_dev *hdev = vport->back; | |
5876 | int i; | |
5877 | ||
5878 | for (i = 0; i < kinfo->num_tqps; i++) { | |
5879 | struct hclge_tqp *tqp = | |
5880 | container_of(kinfo->tqp[i], struct hclge_tqp, q); | |
5881 | ||
5882 | tqp->q.handle = NULL; | |
5883 | tqp->q.tqp_index = 0; | |
5884 | tqp->alloced = false; | |
5885 | } | |
5886 | ||
5887 | devm_kfree(&hdev->pdev->dev, kinfo->tqp); | |
5888 | kinfo->tqp = NULL; | |
5889 | } | |
5890 | ||
5891 | static int hclge_set_channels(struct hnae3_handle *handle, u32 new_tqps_num) | |
5892 | { | |
5893 | struct hclge_vport *vport = hclge_get_vport(handle); | |
5894 | struct hnae3_knic_private_info *kinfo = &vport->nic.kinfo; | |
5895 | struct hclge_dev *hdev = vport->back; | |
5896 | int cur_rss_size = kinfo->rss_size; | |
5897 | int cur_tqps = kinfo->num_tqps; | |
5898 | u16 tc_offset[HCLGE_MAX_TC_NUM]; | |
5899 | u16 tc_valid[HCLGE_MAX_TC_NUM]; | |
5900 | u16 tc_size[HCLGE_MAX_TC_NUM]; | |
5901 | u16 roundup_size; | |
5902 | u32 *rss_indir; | |
5903 | int ret, i; | |
5904 | ||
5905 | hclge_release_tqp(vport); | |
5906 | ||
5907 | ret = hclge_knic_setup(vport, new_tqps_num); | |
5908 | if (ret) { | |
5909 | dev_err(&hdev->pdev->dev, "setup nic fail, ret =%d\n", ret); | |
5910 | return ret; | |
5911 | } | |
5912 | ||
5913 | ret = hclge_map_tqp_to_vport(hdev, vport); | |
5914 | if (ret) { | |
5915 | dev_err(&hdev->pdev->dev, "map vport tqp fail, ret =%d\n", ret); | |
5916 | return ret; | |
5917 | } | |
5918 | ||
5919 | ret = hclge_tm_schd_init(hdev); | |
5920 | if (ret) { | |
5921 | dev_err(&hdev->pdev->dev, "tm schd init fail, ret =%d\n", ret); | |
5922 | return ret; | |
5923 | } | |
5924 | ||
5925 | roundup_size = roundup_pow_of_two(kinfo->rss_size); | |
5926 | roundup_size = ilog2(roundup_size); | |
5927 | /* Set the RSS TC mode according to the new RSS size */ | |
5928 | for (i = 0; i < HCLGE_MAX_TC_NUM; i++) { | |
5929 | tc_valid[i] = 0; | |
5930 | ||
5931 | if (!(hdev->hw_tc_map & BIT(i))) | |
5932 | continue; | |
5933 | ||
5934 | tc_valid[i] = 1; | |
5935 | tc_size[i] = roundup_size; | |
5936 | tc_offset[i] = kinfo->rss_size * i; | |
5937 | } | |
5938 | ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset); | |
5939 | if (ret) | |
5940 | return ret; | |
5941 | ||
5942 | /* Reinitializes the rss indirect table according to the new RSS size */ | |
5943 | rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL); | |
5944 | if (!rss_indir) | |
5945 | return -ENOMEM; | |
5946 | ||
5947 | for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) | |
5948 | rss_indir[i] = i % kinfo->rss_size; | |
5949 | ||
5950 | ret = hclge_set_rss(handle, rss_indir, NULL, 0); | |
5951 | if (ret) | |
5952 | dev_err(&hdev->pdev->dev, "set rss indir table fail, ret=%d\n", | |
5953 | ret); | |
5954 | ||
5955 | kfree(rss_indir); | |
5956 | ||
5957 | if (!ret) | |
5958 | dev_info(&hdev->pdev->dev, | |
5959 | "Channels changed, rss_size from %d to %d, tqps from %d to %d", | |
5960 | cur_rss_size, kinfo->rss_size, | |
5961 | cur_tqps, kinfo->rss_size * kinfo->num_tc); | |
5962 | ||
5963 | return ret; | |
5964 | } | |
5965 | ||
77b34110 FL |
5966 | static int hclge_get_regs_num(struct hclge_dev *hdev, u32 *regs_num_32_bit, |
5967 | u32 *regs_num_64_bit) | |
5968 | { | |
5969 | struct hclge_desc desc; | |
5970 | u32 total_num; | |
5971 | int ret; | |
5972 | ||
5973 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_REG_NUM, true); | |
5974 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
5975 | if (ret) { | |
5976 | dev_err(&hdev->pdev->dev, | |
5977 | "Query register number cmd failed, ret = %d.\n", ret); | |
5978 | return ret; | |
5979 | } | |
5980 | ||
5981 | *regs_num_32_bit = le32_to_cpu(desc.data[0]); | |
5982 | *regs_num_64_bit = le32_to_cpu(desc.data[1]); | |
5983 | ||
5984 | total_num = *regs_num_32_bit + *regs_num_64_bit; | |
5985 | if (!total_num) | |
5986 | return -EINVAL; | |
5987 | ||
5988 | return 0; | |
5989 | } | |
5990 | ||
5991 | static int hclge_get_32_bit_regs(struct hclge_dev *hdev, u32 regs_num, | |
5992 | void *data) | |
5993 | { | |
5994 | #define HCLGE_32_BIT_REG_RTN_DATANUM 8 | |
5995 | ||
5996 | struct hclge_desc *desc; | |
5997 | u32 *reg_val = data; | |
5998 | __le32 *desc_data; | |
5999 | int cmd_num; | |
6000 | int i, k, n; | |
6001 | int ret; | |
6002 | ||
6003 | if (regs_num == 0) | |
6004 | return 0; | |
6005 | ||
6006 | cmd_num = DIV_ROUND_UP(regs_num + 2, HCLGE_32_BIT_REG_RTN_DATANUM); | |
6007 | desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); | |
6008 | if (!desc) | |
6009 | return -ENOMEM; | |
6010 | ||
6011 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_32_BIT_REG, true); | |
6012 | ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); | |
6013 | if (ret) { | |
6014 | dev_err(&hdev->pdev->dev, | |
6015 | "Query 32 bit register cmd failed, ret = %d.\n", ret); | |
6016 | kfree(desc); | |
6017 | return ret; | |
6018 | } | |
6019 | ||
6020 | for (i = 0; i < cmd_num; i++) { | |
6021 | if (i == 0) { | |
6022 | desc_data = (__le32 *)(&desc[i].data[0]); | |
6023 | n = HCLGE_32_BIT_REG_RTN_DATANUM - 2; | |
6024 | } else { | |
6025 | desc_data = (__le32 *)(&desc[i]); | |
6026 | n = HCLGE_32_BIT_REG_RTN_DATANUM; | |
6027 | } | |
6028 | for (k = 0; k < n; k++) { | |
6029 | *reg_val++ = le32_to_cpu(*desc_data++); | |
6030 | ||
6031 | regs_num--; | |
6032 | if (!regs_num) | |
6033 | break; | |
6034 | } | |
6035 | } | |
6036 | ||
6037 | kfree(desc); | |
6038 | return 0; | |
6039 | } | |
6040 | ||
6041 | static int hclge_get_64_bit_regs(struct hclge_dev *hdev, u32 regs_num, | |
6042 | void *data) | |
6043 | { | |
6044 | #define HCLGE_64_BIT_REG_RTN_DATANUM 4 | |
6045 | ||
6046 | struct hclge_desc *desc; | |
6047 | u64 *reg_val = data; | |
6048 | __le64 *desc_data; | |
6049 | int cmd_num; | |
6050 | int i, k, n; | |
6051 | int ret; | |
6052 | ||
6053 | if (regs_num == 0) | |
6054 | return 0; | |
6055 | ||
6056 | cmd_num = DIV_ROUND_UP(regs_num + 1, HCLGE_64_BIT_REG_RTN_DATANUM); | |
6057 | desc = kcalloc(cmd_num, sizeof(struct hclge_desc), GFP_KERNEL); | |
6058 | if (!desc) | |
6059 | return -ENOMEM; | |
6060 | ||
6061 | hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_QUERY_64_BIT_REG, true); | |
6062 | ret = hclge_cmd_send(&hdev->hw, desc, cmd_num); | |
6063 | if (ret) { | |
6064 | dev_err(&hdev->pdev->dev, | |
6065 | "Query 64 bit register cmd failed, ret = %d.\n", ret); | |
6066 | kfree(desc); | |
6067 | return ret; | |
6068 | } | |
6069 | ||
6070 | for (i = 0; i < cmd_num; i++) { | |
6071 | if (i == 0) { | |
6072 | desc_data = (__le64 *)(&desc[i].data[0]); | |
6073 | n = HCLGE_64_BIT_REG_RTN_DATANUM - 1; | |
6074 | } else { | |
6075 | desc_data = (__le64 *)(&desc[i]); | |
6076 | n = HCLGE_64_BIT_REG_RTN_DATANUM; | |
6077 | } | |
6078 | for (k = 0; k < n; k++) { | |
6079 | *reg_val++ = le64_to_cpu(*desc_data++); | |
6080 | ||
6081 | regs_num--; | |
6082 | if (!regs_num) | |
6083 | break; | |
6084 | } | |
6085 | } | |
6086 | ||
6087 | kfree(desc); | |
6088 | return 0; | |
6089 | } | |
6090 | ||
6091 | static int hclge_get_regs_len(struct hnae3_handle *handle) | |
6092 | { | |
6093 | struct hclge_vport *vport = hclge_get_vport(handle); | |
6094 | struct hclge_dev *hdev = vport->back; | |
6095 | u32 regs_num_32_bit, regs_num_64_bit; | |
6096 | int ret; | |
6097 | ||
6098 | ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); | |
6099 | if (ret) { | |
6100 | dev_err(&hdev->pdev->dev, | |
6101 | "Get register number failed, ret = %d.\n", ret); | |
6102 | return -EOPNOTSUPP; | |
6103 | } | |
6104 | ||
6105 | return regs_num_32_bit * sizeof(u32) + regs_num_64_bit * sizeof(u64); | |
6106 | } | |
6107 | ||
6108 | static void hclge_get_regs(struct hnae3_handle *handle, u32 *version, | |
6109 | void *data) | |
6110 | { | |
6111 | struct hclge_vport *vport = hclge_get_vport(handle); | |
6112 | struct hclge_dev *hdev = vport->back; | |
6113 | u32 regs_num_32_bit, regs_num_64_bit; | |
6114 | int ret; | |
6115 | ||
6116 | *version = hdev->fw_version; | |
6117 | ||
6118 | ret = hclge_get_regs_num(hdev, ®s_num_32_bit, ®s_num_64_bit); | |
6119 | if (ret) { | |
6120 | dev_err(&hdev->pdev->dev, | |
6121 | "Get register number failed, ret = %d.\n", ret); | |
6122 | return; | |
6123 | } | |
6124 | ||
6125 | ret = hclge_get_32_bit_regs(hdev, regs_num_32_bit, data); | |
6126 | if (ret) { | |
6127 | dev_err(&hdev->pdev->dev, | |
6128 | "Get 32 bit register failed, ret = %d.\n", ret); | |
6129 | return; | |
6130 | } | |
6131 | ||
6132 | data = (u32 *)data + regs_num_32_bit; | |
6133 | ret = hclge_get_64_bit_regs(hdev, regs_num_64_bit, | |
6134 | data); | |
6135 | if (ret) | |
6136 | dev_err(&hdev->pdev->dev, | |
6137 | "Get 64 bit register failed, ret = %d.\n", ret); | |
6138 | } | |
6139 | ||
f6f75abc | 6140 | static int hclge_set_led_status(struct hclge_dev *hdev, u8 locate_led_status) |
07f8e940 JS |
6141 | { |
6142 | struct hclge_set_led_state_cmd *req; | |
6143 | struct hclge_desc desc; | |
6144 | int ret; | |
6145 | ||
6146 | hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_LED_STATUS_CFG, false); | |
6147 | ||
6148 | req = (struct hclge_set_led_state_cmd *)desc.data; | |
e4e87715 PL |
6149 | hnae3_set_field(req->locate_led_config, HCLGE_LED_LOCATE_STATE_M, |
6150 | HCLGE_LED_LOCATE_STATE_S, locate_led_status); | |
07f8e940 JS |
6151 | |
6152 | ret = hclge_cmd_send(&hdev->hw, &desc, 1); | |
6153 | if (ret) | |
6154 | dev_err(&hdev->pdev->dev, | |
6155 | "Send set led state cmd error, ret =%d\n", ret); | |
6156 | ||
6157 | return ret; | |
6158 | } | |
6159 | ||
6160 | enum hclge_led_status { | |
6161 | HCLGE_LED_OFF, | |
6162 | HCLGE_LED_ON, | |
6163 | HCLGE_LED_NO_CHANGE = 0xFF, | |
6164 | }; | |
6165 | ||
6166 | static int hclge_set_led_id(struct hnae3_handle *handle, | |
6167 | enum ethtool_phys_id_state status) | |
6168 | { | |
07f8e940 JS |
6169 | struct hclge_vport *vport = hclge_get_vport(handle); |
6170 | struct hclge_dev *hdev = vport->back; | |
07f8e940 JS |
6171 | |
6172 | switch (status) { | |
6173 | case ETHTOOL_ID_ACTIVE: | |
f6f75abc | 6174 | return hclge_set_led_status(hdev, HCLGE_LED_ON); |
07f8e940 | 6175 | case ETHTOOL_ID_INACTIVE: |
f6f75abc | 6176 | return hclge_set_led_status(hdev, HCLGE_LED_OFF); |
07f8e940 | 6177 | default: |
f6f75abc | 6178 | return -EINVAL; |
07f8e940 | 6179 | } |
07f8e940 JS |
6180 | } |
6181 | ||
0979aa0b FL |
6182 | static void hclge_get_link_mode(struct hnae3_handle *handle, |
6183 | unsigned long *supported, | |
6184 | unsigned long *advertising) | |
6185 | { | |
6186 | unsigned int size = BITS_TO_LONGS(__ETHTOOL_LINK_MODE_MASK_NBITS); | |
6187 | struct hclge_vport *vport = hclge_get_vport(handle); | |
6188 | struct hclge_dev *hdev = vport->back; | |
6189 | unsigned int idx = 0; | |
6190 | ||
6191 | for (; idx < size; idx++) { | |
6192 | supported[idx] = hdev->hw.mac.supported[idx]; | |
6193 | advertising[idx] = hdev->hw.mac.advertising[idx]; | |
6194 | } | |
6195 | } | |
6196 | ||
6197 | static void hclge_get_port_type(struct hnae3_handle *handle, | |
6198 | u8 *port_type) | |
6199 | { | |
6200 | struct hclge_vport *vport = hclge_get_vport(handle); | |
6201 | struct hclge_dev *hdev = vport->back; | |
6202 | u8 media_type = hdev->hw.mac.media_type; | |
6203 | ||
6204 | switch (media_type) { | |
6205 | case HNAE3_MEDIA_TYPE_FIBER: | |
6206 | *port_type = PORT_FIBRE; | |
6207 | break; | |
6208 | case HNAE3_MEDIA_TYPE_COPPER: | |
6209 | *port_type = PORT_TP; | |
6210 | break; | |
6211 | case HNAE3_MEDIA_TYPE_UNKNOWN: | |
6212 | default: | |
6213 | *port_type = PORT_OTHER; | |
6214 | break; | |
6215 | } | |
6216 | } | |
6217 | ||
46a3df9f S |
6218 | static const struct hnae3_ae_ops hclge_ops = { |
6219 | .init_ae_dev = hclge_init_ae_dev, | |
6220 | .uninit_ae_dev = hclge_uninit_ae_dev, | |
6221 | .init_client_instance = hclge_init_client_instance, | |
6222 | .uninit_client_instance = hclge_uninit_client_instance, | |
84e095d6 SM |
6223 | .map_ring_to_vector = hclge_map_ring_to_vector, |
6224 | .unmap_ring_from_vector = hclge_unmap_ring_frm_vector, | |
46a3df9f | 6225 | .get_vector = hclge_get_vector, |
0d3e6631 | 6226 | .put_vector = hclge_put_vector, |
46a3df9f | 6227 | .set_promisc_mode = hclge_set_promisc_mode, |
c39c4d98 | 6228 | .set_loopback = hclge_set_loopback, |
46a3df9f S |
6229 | .start = hclge_ae_start, |
6230 | .stop = hclge_ae_stop, | |
6231 | .get_status = hclge_get_status, | |
6232 | .get_ksettings_an_result = hclge_get_ksettings_an_result, | |
6233 | .update_speed_duplex_h = hclge_update_speed_duplex_h, | |
6234 | .cfg_mac_speed_dup_h = hclge_cfg_mac_speed_dup_h, | |
6235 | .get_media_type = hclge_get_media_type, | |
6236 | .get_rss_key_size = hclge_get_rss_key_size, | |
6237 | .get_rss_indir_size = hclge_get_rss_indir_size, | |
6238 | .get_rss = hclge_get_rss, | |
6239 | .set_rss = hclge_set_rss, | |
f7db940a | 6240 | .set_rss_tuple = hclge_set_rss_tuple, |
07d29954 | 6241 | .get_rss_tuple = hclge_get_rss_tuple, |
46a3df9f S |
6242 | .get_tc_size = hclge_get_tc_size, |
6243 | .get_mac_addr = hclge_get_mac_addr, | |
6244 | .set_mac_addr = hclge_set_mac_addr, | |
6245 | .add_uc_addr = hclge_add_uc_addr, | |
6246 | .rm_uc_addr = hclge_rm_uc_addr, | |
6247 | .add_mc_addr = hclge_add_mc_addr, | |
6248 | .rm_mc_addr = hclge_rm_mc_addr, | |
40cca1c5 | 6249 | .update_mta_status = hclge_update_mta_status, |
46a3df9f S |
6250 | .set_autoneg = hclge_set_autoneg, |
6251 | .get_autoneg = hclge_get_autoneg, | |
6252 | .get_pauseparam = hclge_get_pauseparam, | |
61387774 | 6253 | .set_pauseparam = hclge_set_pauseparam, |
46a3df9f S |
6254 | .set_mtu = hclge_set_mtu, |
6255 | .reset_queue = hclge_reset_tqp, | |
6256 | .get_stats = hclge_get_stats, | |
6257 | .update_stats = hclge_update_stats, | |
6258 | .get_strings = hclge_get_strings, | |
6259 | .get_sset_count = hclge_get_sset_count, | |
6260 | .get_fw_version = hclge_get_fw_version, | |
6261 | .get_mdix_mode = hclge_get_mdix_mode, | |
391b5e93 | 6262 | .enable_vlan_filter = hclge_enable_vlan_filter, |
dc8131d8 | 6263 | .set_vlan_filter = hclge_set_vlan_filter, |
46a3df9f | 6264 | .set_vf_vlan_filter = hclge_set_vf_vlan_filter, |
052ece6d | 6265 | .enable_hw_strip_rxvtag = hclge_en_hw_strip_rxvtag, |
4ed340ab | 6266 | .reset_event = hclge_reset_event, |
09f2af64 PL |
6267 | .get_tqps_and_rss_info = hclge_get_tqps_and_rss_info, |
6268 | .set_channels = hclge_set_channels, | |
482d2e9c | 6269 | .get_channels = hclge_get_channels, |
f34ffffd | 6270 | .get_flowctrl_adv = hclge_get_flowctrl_adv, |
77b34110 FL |
6271 | .get_regs_len = hclge_get_regs_len, |
6272 | .get_regs = hclge_get_regs, | |
07f8e940 | 6273 | .set_led_id = hclge_set_led_id, |
0979aa0b FL |
6274 | .get_link_mode = hclge_get_link_mode, |
6275 | .get_port_type = hclge_get_port_type, | |
46a3df9f S |
6276 | }; |
6277 | ||
6278 | static struct hnae3_ae_algo ae_algo = { | |
6279 | .ops = &hclge_ops, | |
46a3df9f S |
6280 | .pdev_id_table = ae_algo_pci_tbl, |
6281 | }; | |
6282 | ||
6283 | static int hclge_init(void) | |
6284 | { | |
6285 | pr_info("%s is initializing\n", HCLGE_NAME); | |
6286 | ||
854cf33a FL |
6287 | hnae3_register_ae_algo(&ae_algo); |
6288 | ||
6289 | return 0; | |
46a3df9f S |
6290 | } |
6291 | ||
6292 | static void hclge_exit(void) | |
6293 | { | |
6294 | hnae3_unregister_ae_algo(&ae_algo); | |
6295 | } | |
6296 | module_init(hclge_init); | |
6297 | module_exit(hclge_exit); | |
6298 | ||
6299 | MODULE_LICENSE("GPL"); | |
6300 | MODULE_AUTHOR("Huawei Tech. Co., Ltd."); | |
6301 | MODULE_DESCRIPTION("HCLGE Driver"); | |
6302 | MODULE_VERSION(HCLGE_MOD_VERSION); |